HMR0.cpp@ 75649

Last change on this file since 75649 was 74789, checked in by vboxsync, 6 years ago
vm.h,VMM,REM: s/VMCPU_FF_IS_PENDING/VMCPU_FF_IS_ANY_SET/g to emphasize the plurality of the flags argument and encourage using VMCPU_FF_IS_SET. bugref:9180
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 75.1 KB

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1	/* $Id: HMR0.cpp 74789 2018-10-12 10:34:32Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/hm_vmx.h>
29	#include <VBox/vmm/hm_svm.h>
30	#include <VBox/vmm/gim.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35	#include <iprt/asm-amd64-x86.h>
36	#include <iprt/cpuset.h>
37	#include <iprt/mem.h>
38	#include <iprt/memobj.h>
39	#include <iprt/once.h>
40	#include <iprt/param.h>
41	#include <iprt/power.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44	#include <iprt/x86.h>
45	#include "HMVMXR0.h"
46	#include "HMSVMR0.h"
47
48
49	/*********************************************************************************************************************************
50	* Internal Functions *
51	*********************************************************************************************************************************/
52	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* This is used to manage the status code of a RTMpOnAll in HM.
65	*/
66	typedef struct HMR0FIRSTRC
67	{
68	/** The status code. */
69	int32_t volatile rc;
70	/** The ID of the CPU reporting the first failure. */
71	RTCPUID volatile idCpu;
72	} HMR0FIRSTRC;
73	/** Pointer to a first return code structure. */
74	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
75
76
77	/*********************************************************************************************************************************
78	* Global Variables *
79	*********************************************************************************************************************************/
80	/**
81	* Global data.
82	*/
83	static struct
84	{
85	/** Per CPU globals. */
86	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
87
88	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
89	* @{ */
90	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu));
91	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
92	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));
93	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost, void *pvArg));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
100	/** @} */
101
102	/** Maximum ASID allowed. */
103	uint32_t uMaxAsid;
104
105	/** VT-x data. */
106	struct
107	{
108	/** Set to by us to indicate VMX is supported by the CPU. */
109	bool fSupported;
110	/** Whether we're using SUPR0EnableVTx or not. */
111	bool fUsingSUPR0EnableVTx;
112	/** Whether we're using the preemption timer or not. */
113	bool fUsePreemptTimer;
114	/** The shift mask employed by the VMX-Preemption timer. */
115	uint8_t cPreemptTimerShift;
116
117	/** Host CR4 value (set by ring-0 VMX init) */
118	uint64_t u64HostCr4;
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121	/** Host SMM monitor control (used for logging/diagnostics) */
122	uint64_t u64HostSmmMonitorCtl;
123
124	/** VMX MSR values. */
125	VMXMSRS Msrs;
126
127	/** Last instruction error. */
128	uint32_t ulLastInstrError;
129
130	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
131	* module termination. */
132	bool fCalledSUPR0EnableVTx;
133	} vmx;
134
135	/** AMD-V information. */
136	struct
137	{
138	/* HWCR MSR (for diagnostics) */
139	uint64_t u64MsrHwcr;
140
141	/** SVM revision. */
142	uint32_t u32Rev;
143
144	/** SVM feature bits from cpuid 0x8000000a */
145	uint32_t u32Features;
146
147	/** Set by us to indicate SVM is supported by the CPU. */
148	bool fSupported;
149	} svm;
150
151	/** Last recorded error code during HM ring-0 init. */
152	int32_t rcInit;
153
154	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
155	* enabled and disabled each time it's used to execute guest code. */
156	bool fGlobalInit;
157	/** Indicates whether the host is suspending or not. We'll refuse a few
158	* actions when the host is being suspended to speed up the suspending and
159	* avoid trouble. */
160	bool volatile fSuspended;
161
162	/** Whether we've already initialized all CPUs.
163	* @remarks We could check the EnableAllCpusOnce state, but this is
164	* simpler and hopefully easier to understand. */
165	bool fEnabled;
166	/** Serialize initialization in HMR0EnableAllCpus. */
167	RTONCE EnableAllCpusOnce;
168	} g_HmR0;
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	# ifndef DEBUG_bird
212	/**
213	* Get the CPU ID on which the failure status code was reported.
214	*
215	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
216	* @param pFirstRc The first return code structure.
217	*/
218	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->idCpu;
221	}
222	# endif
223	#endif /* VBOX_STRICT */
224
225
226	/** @name Dummy callback handlers.
227	* @{ */
228
229	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
230	{
231	RT_NOREF2(pVCpu, pHostCpu);
232	return VINF_SUCCESS;
233	}
234
235	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
236	{
237	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
238	}
239
240	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
241	bool fEnabledBySystem, void *pvArg)
242	{
243	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pvArg);
244	return VINF_SUCCESS;
245	}
246
247	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
248	{
249	RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
254	{
255	RT_NOREF1(pVM);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
260	{
261	RT_NOREF1(pVM);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
266	{
267	RT_NOREF1(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu)
272	{
273	RT_NOREF(pVCpu);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)
278	{
279	RT_NOREF1(pVCpu);
280	return VINF_SUCCESS;
281	}
282
283	/** @} */
284
285
286	/**
287	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
288	* Down at the Rate Specified" erratum.
289	*
290	* Errata names and related steppings:
291	* - BA86 - D0.
292	* - AAX65 - C2.
293	* - AAU65 - C2, K0.
294	* - AAO95 - B1.
295	* - AAT59 - C2.
296	* - AAK139 - D0.
297	* - AAM126 - C0, C1, D0.
298	* - AAN92 - B1.
299	* - AAJ124 - C0, D0.
300	* - AAP86 - B1.
301	*
302	* Steppings: B1, C0, C1, C2, D0, K0.
303	*
304	* @returns true if subject to it, false if not.
305	*/
306	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
307	{
308	uint32_t u = ASMCpuId_EAX(1);
309	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
310	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
311	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
312	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
313	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
315	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
316	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
317	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
318	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
321	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
322	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
323	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
324	)
325	return true;
326	return false;
327	}
328
329
330	/**
331	* Intel specific initialization code.
332	*
333	* @returns VBox status code (will only fail if out of memory).
334	* @param uFeatEcx Standard cpuid:1 feature ECX leaf.
335	* @param uFeatEdx Standard cpuid:1 feature EDX leaf.
336	*/
337	static int hmR0InitIntel(uint32_t uFeatEcx, uint32_t uFeatEdx)
338	{
339	/*
340	* Check that all the required VT-x features are present.
341	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
342	*/
343	if ( (uFeatEcx & X86_CPUID_FEATURE_ECX_VMX)
344	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_MSR)
345	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_FXSR))
346	{
347	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
348	g_HmR0.vmx.Msrs.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
349
350	/*
351	* First try use native kernel API for controlling VT-x.
352	* (This is only supported by some Mac OS X kernels atm.)
353	*/
354	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
355	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
356	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
357	{
358	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
359	if (RT_SUCCESS(rc))
360	{
361	g_HmR0.vmx.fSupported = true;
362	rc = SUPR0EnableVTx(false /* fEnable */);
363	AssertLogRelRC(rc);
364	}
365	}
366	else
367	{
368	HMR0FIRSTRC FirstRc;
369	hmR0FirstRcInit(&FirstRc);
370	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
371	if (RT_SUCCESS(g_HmR0.rcInit))
372	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
373	}
374	if (RT_SUCCESS(g_HmR0.rcInit))
375	{
376	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
377	g_HmR0.vmx.Msrs.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
378
379	/*
380	* Read all relevant registers and MSRs.
381	*/
382	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
383	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
384	g_HmR0.vmx.Msrs.u64Basic = ASMRdMsr(MSR_IA32_VMX_BASIC);
385	/* KVM workaround: Intel SDM section 34.15.5 describes that MSR_IA32_SMM_MONITOR_CTL
386	* depends on bit 49 of MSR_IA32_VMX_BASIC while table 35-2 says that this MSR is
387	* available if either VMX or SMX is supported. */
388	if (RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_DUAL_MON))
389	g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
390	g_HmR0.vmx.Msrs.PinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
391	g_HmR0.vmx.Msrs.ProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
392	g_HmR0.vmx.Msrs.ExitCtls.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
393	g_HmR0.vmx.Msrs.EntryCtls.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
394	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
395	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
396	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
397	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
398	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
399	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
400	if (RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
401	{
402	g_HmR0.vmx.Msrs.TruePinCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS);
403	g_HmR0.vmx.Msrs.TrueProcCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
404	g_HmR0.vmx.Msrs.TrueEntryCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_ENTRY_CTLS);
405	g_HmR0.vmx.Msrs.TrueExitCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_EXIT_CTLS);
406	}
407
408	/* VPID 16 bits ASID. */
409	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
410
411	if (g_HmR0.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
412	{
413	g_HmR0.vmx.Msrs.ProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
414	if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & (VMX_PROC_CTLS2_EPT \| VMX_PROC_CTLS2_VPID))
415	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
416
417	if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMFUNC)
418	g_HmR0.vmx.Msrs.u64VmFunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
419	}
420
421	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
422	{
423	/*
424	* Enter root mode
425	*/
426	RTR0MEMOBJ hScatchMemObj;
427	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
428	if (RT_FAILURE(rc))
429	{
430	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
431	return rc;
432	}
433
434	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
435	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
436	ASMMemZeroPage(pvScatchPage);
437
438	/* Set revision dword at the beginning of the structure. */
439	(uint32_t )pvScatchPage = RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
440
441	/* Make sure we don't get rescheduled to another cpu during this probe. */
442	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
443
444	/*
445	* Check CR4.VMXE.
446	*/
447	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
448	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
449	{
450	/* In theory this bit could be cleared behind our back. Which would cause #UD
451	faults when we try to execute the VMX instructions... */
452	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
453	}
454
455	/*
456	* The only way of checking if we're in VMX root mode or not is to try and enter it.
457	* There is no instruction or control bit that tells us if we're in VMX root mode.
458	* Therefore, try and enter VMX root mode here.
459	*/
460	rc = VMXEnable(HCPhysScratchPage);
461	if (RT_SUCCESS(rc))
462	{
463	g_HmR0.vmx.fSupported = true;
464	VMXDisable();
465	}
466	else
467	{
468	/*
469	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
470	* it will crash the host when we enter raw mode, because:
471	*
472	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
473	* this bit), and
474	* (b) turning off paging causes a #GP (unavoidable when switching
475	* from long to 32 bits mode or 32 bits to PAE).
476	*
477	* They should fix their code, but until they do we simply refuse to run.
478	*/
479	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
480	Assert(g_HmR0.vmx.fSupported == false);
481	}
482
483	/*
484	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
485	* set before (some software could incorrectly think it is in VMX mode).
486	*/
487	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
488	ASMSetFlags(fEFlags);
489
490	RTR0MemObjFree(hScatchMemObj, false);
491	}
492
493	if (g_HmR0.vmx.fSupported)
494	{
495	rc = VMXR0GlobalInit();
496	if (RT_FAILURE(rc))
497	g_HmR0.rcInit = rc;
498
499	/*
500	* Install the VT-x methods.
501	*/
502	g_HmR0.pfnEnterSession = VMXR0Enter;
503	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
504	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
505	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
506	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
507	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
508	g_HmR0.pfnInitVM = VMXR0InitVM;
509	g_HmR0.pfnTermVM = VMXR0TermVM;
510	g_HmR0.pfnSetupVM = VMXR0SetupVM;
511
512	/*
513	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
514	* Timer Does Not Count Down at the Rate Specified" erratum.
515	*/
516	if (g_HmR0.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
517	{
518	g_HmR0.vmx.fUsePreemptTimer = true;
519	g_HmR0.vmx.cPreemptTimerShift = RT_BF_GET(g_HmR0.vmx.Msrs.u64Misc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
520	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
521	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
522	}
523	}
524	}
525	#ifdef LOG_ENABLED
526	else
527	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
528	#endif
529	}
530	else
531	g_HmR0.rcInit = VERR_VMX_NO_VMX;
532	return VINF_SUCCESS;
533	}
534
535
536	/**
537	* AMD-specific initialization code.
538	*
539	* @returns VBox status code.
540	* @param uFeatEdx Standard cpuid:1 feature EDX leaf.
541	* @param uExtFeatEcx Extended cpuid:0x80000001 feature ECX leaf.
542	* @param uMaxExtLeaf Extended cpuid:0x80000000 feature maximum valid leaf.
543	*/
544	static int hmR0InitAmd(uint32_t uFeatEdx, uint32_t uExtFeatEcx, uint32_t uMaxExtLeaf)
545	{
546	/*
547	* Read all SVM MSRs if SVM is available.
548	* We also require all SVM-enabled CPUs to support rdmsr/wrmsr and fxsave/fxrstor.
549	*/
550	int rc;
551	if ( (uExtFeatEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
552	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_MSR)
553	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_FXSR)
554	&& ASMIsValidExtRange(uMaxExtLeaf)
555	&& uMaxExtLeaf >= 0x8000000a)
556	{
557	/* Call the global AMD-V initialization routine. */
558	rc = SVMR0GlobalInit();
559	if (RT_FAILURE(rc))
560	{
561	g_HmR0.rcInit = rc;
562	return rc;
563	}
564
565	/*
566	* Install the AMD-V methods.
567	*/
568	g_HmR0.pfnEnterSession = SVMR0Enter;
569	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
570	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
571	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
572	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
573	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
574	g_HmR0.pfnInitVM = SVMR0InitVM;
575	g_HmR0.pfnTermVM = SVMR0TermVM;
576	g_HmR0.pfnSetupVM = SVMR0SetupVM;
577
578	/* Query AMD features. */
579	uint32_t u32Dummy;
580	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
581
582	/*
583	* We need to check if AMD-V has been properly initialized on all CPUs.
584	* Some BIOSes might do a poor job.
585	*/
586	HMR0FIRSTRC FirstRc;
587	hmR0FirstRcInit(&FirstRc);
588	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
589	AssertRC(rc);
590	if (RT_SUCCESS(rc))
591	rc = hmR0FirstRcGetStatus(&FirstRc);
592	#ifndef DEBUG_bird
593	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
594	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
595	#endif
596	if (RT_SUCCESS(rc))
597	{
598	/* Read the HWCR MSR for diagnostics. */
599	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
600	g_HmR0.svm.fSupported = true;
601	}
602	else
603	{
604	g_HmR0.rcInit = rc;
605	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
606	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
607	}
608	}
609	else
610	{
611	/* Don't fail if AMD-V is not supported. See @bugref{6785}. */
612	rc = VINF_SUCCESS;
613	g_HmR0.rcInit = VERR_SVM_NO_SVM;
614	}
615	return rc;
616	}
617
618
619	/**
620	* Does global Ring-0 HM initialization (at module init).
621	*
622	* @returns VBox status code.
623	*/
624	VMMR0_INT_DECL(int) HMR0Init(void)
625	{
626	/*
627	* Initialize the globals.
628	*/
629	g_HmR0.fEnabled = false;
630	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
631	g_HmR0.EnableAllCpusOnce = s_OnceInit;
632	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
633	{
634	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
635	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
636	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
637	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
638	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
639	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
640	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
641	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
642	#endif
643	}
644
645	/* Fill in all callbacks with placeholders. */
646	g_HmR0.pfnEnterSession = hmR0DummyEnter;
647	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
648	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
649	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
650	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
651	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
652	g_HmR0.pfnInitVM = hmR0DummyInitVM;
653	g_HmR0.pfnTermVM = hmR0DummyTermVM;
654	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
655
656	/* Default is global VT-x/AMD-V init. */
657	g_HmR0.fGlobalInit = true;
658
659	/*
660	* Make sure aCpuInfo is big enough for all the CPUs on this system.
661	*/
662	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
663	{
664	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
665	return VERR_TOO_MANY_CPUS;
666	}
667
668	/*
669	* Check for VT-x and AMD-V capabilities.
670	*/
671	int rc;
672	if (ASMHasCpuId())
673	{
674	/* Standard features. */
675	uint32_t uMaxLeaf, uVendorEbx, uVendorEcx, uVendorEdx;
676	ASMCpuId(0, &uMaxLeaf, &uVendorEbx, &uVendorEcx, &uVendorEdx);
677	if (ASMIsValidStdRange(uMaxLeaf))
678	{
679	uint32_t uFeatEcx, uFeatEdx, uDummy;
680	ASMCpuId(1, &uDummy, &uDummy, &uFeatEcx, &uFeatEdx);
681
682	/* Go to CPU specific initialization code. */
683	if ( ASMIsIntelCpuEx(uVendorEbx, uVendorEcx, uVendorEdx)
684	\|\| ASMIsViaCentaurCpuEx(uVendorEbx, uVendorEcx, uVendorEdx))
685	{
686	rc = hmR0InitIntel(uFeatEcx, uFeatEdx);
687	if (RT_FAILURE(rc))
688	return rc;
689	}
690	else if (ASMIsAmdCpuEx(uVendorEbx, uVendorEcx, uVendorEdx))
691	{
692	/* Query extended features for SVM capability. */
693	uint32_t uExtFeatEcx;
694	uint32_t const uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
695	if (ASMIsValidExtRange(uMaxExtLeaf))
696	ASMCpuId(0x80000001, &uDummy, &uDummy, &uExtFeatEcx, &uDummy);
697	else
698	uExtFeatEcx = 0;
699
700	rc = hmR0InitAmd(uFeatEdx, uExtFeatEcx, uMaxExtLeaf);
701	if (RT_FAILURE(rc))
702	return rc;
703	}
704	else
705	g_HmR0.rcInit = VERR_HM_UNKNOWN_CPU;
706	}
707	else
708	g_HmR0.rcInit = VERR_HM_UNKNOWN_CPU;
709	}
710	else
711	g_HmR0.rcInit = VERR_HM_NO_CPUID;
712
713	/*
714	* Register notification callbacks that we can use to disable/enable CPUs
715	* when brought offline/online or suspending/resuming.
716	*/
717	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
718	{
719	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
720	AssertRC(rc);
721
722	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
723	AssertRC(rc);
724	}
725
726	/* We return success here because module init shall not fail if HM
727	fails to initialize. */
728	return VINF_SUCCESS;
729	}
730
731
732	/**
733	* Does global Ring-0 HM termination (at module termination).
734	*
735	* @returns VBox status code.
736	*/
737	VMMR0_INT_DECL(int) HMR0Term(void)
738	{
739	int rc;
740	if ( g_HmR0.vmx.fSupported
741	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
742	{
743	/*
744	* Simple if the host OS manages VT-x.
745	*/
746	Assert(g_HmR0.fGlobalInit);
747
748	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
749	{
750	rc = SUPR0EnableVTx(false /* fEnable */);
751	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
752	}
753	else
754	rc = VINF_SUCCESS;
755
756	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
757	{
758	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
759	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
760	}
761	}
762	else
763	{
764	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
765
766	/* Doesn't really matter if this fails. */
767	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
768	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
769
770	/*
771	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
772	*/
773	if (g_HmR0.fGlobalInit)
774	{
775	HMR0FIRSTRC FirstRc;
776	hmR0FirstRcInit(&FirstRc);
777	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
778	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
779	if (RT_SUCCESS(rc))
780	rc = hmR0FirstRcGetStatus(&FirstRc);
781	}
782
783	/*
784	* Free the per-cpu pages used for VT-x and AMD-V.
785	*/
786	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
787	{
788	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
789	{
790	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
791	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
792	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
793	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
794	}
795	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
796	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
797	{
798	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
799	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
800	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
801	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
802	}
803	#endif
804	}
805	}
806
807	/** @todo This needs cleaning up. There's no matching
808	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
809	* should move into their respective modules. */
810	/* Finally, call global VT-x/AMD-V termination. */
811	if (g_HmR0.vmx.fSupported)
812	VMXR0GlobalTerm();
813	else if (g_HmR0.svm.fSupported)
814	SVMR0GlobalTerm();
815
816	return rc;
817	}
818
819
820	/**
821	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
822	* on a CPU.
823	*
824	* @param idCpu The identifier for the CPU the function is called on.
825	* @param pvUser1 Pointer to the first RC structure.
826	* @param pvUser2 Ignored.
827	*/
828	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
829	{
830	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
831	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
832	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
833	NOREF(idCpu); NOREF(pvUser2);
834
835	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
836	hmR0FirstRcSetStatus(pFirstRc, rc);
837	}
838
839
840	/**
841	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
842	* on a CPU.
843	*
844	* @param idCpu The identifier for the CPU the function is called on.
845	* @param pvUser1 Pointer to the first RC structure.
846	* @param pvUser2 Ignored.
847	*/
848	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
849	{
850	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
851	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
852	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
853	NOREF(idCpu); NOREF(pvUser2);
854
855	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
856	hmR0FirstRcSetStatus(pFirstRc, rc);
857	}
858
859
860	/**
861	* Enable VT-x or AMD-V on the current CPU
862	*
863	* @returns VBox status code.
864	* @param pVM The cross context VM structure. Can be NULL.
865	* @param idCpu The identifier for the CPU the function is called on.
866	*
867	* @remarks Maybe called with interrupts disabled!
868	*/
869	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
870	{
871	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
872
873	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
874	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
875	Assert(!pHostCpu->fConfigured);
876	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
877
878	pHostCpu->idCpu = idCpu;
879	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
880
881	int rc;
882	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
883	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
884	else
885	{
886	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
887	if (g_HmR0.vmx.fSupported)
888	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
889	else
890	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, NULL /* pvArg */);
891	}
892	if (RT_SUCCESS(rc))
893	pHostCpu->fConfigured = true;
894
895	return rc;
896	}
897
898
899	/**
900	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
901	*
902	* @param idCpu The identifier for the CPU the function is called on.
903	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
904	* @param pvUser2 The 2nd user argument.
905	*/
906	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
907	{
908	PVM pVM = (PVM)pvUser1; /* can be NULL! */
909	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
910	AssertReturnVoid(g_HmR0.fGlobalInit);
911	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
912	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
913	}
914
915
916	/**
917	* RTOnce callback employed by HMR0EnableAllCpus.
918	*
919	* @returns VBox status code.
920	* @param pvUser Pointer to the VM.
921	*/
922	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
923	{
924	PVM pVM = (PVM)pvUser;
925
926	/*
927	* Indicate that we've initialized.
928	*
929	* Note! There is a potential race between this function and the suspend
930	* notification. Kind of unlikely though, so ignored for now.
931	*/
932	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
933	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
934
935	/*
936	* The global init variable is set by the first VM.
937	*/
938	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
939
940	#ifdef VBOX_STRICT
941	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
942	{
943	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
944	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
945	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
946	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
947	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
948	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
949	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
950	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
951	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
952	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
953	# endif
954	}
955	#endif
956
957	int rc;
958	if ( g_HmR0.vmx.fSupported
959	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
960	{
961	/*
962	* Global VT-x initialization API (only darwin for now).
963	*/
964	rc = SUPR0EnableVTx(true /* fEnable */);
965	if (RT_SUCCESS(rc))
966	{
967	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
968	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
969	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
970	}
971	else
972	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
973	}
974	else
975	{
976	/*
977	* We're doing the job ourselves.
978	*/
979	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
980	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
981	{
982	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
983	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
984	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
985	#endif
986	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
987	{
988	/** @todo NUMA */
989	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
990	AssertLogRelRCReturn(rc, rc);
991
992	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
993	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
994	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
995
996	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
997	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
998	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
999
1000	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1001	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
1002	false /* executable R0 mapping */);
1003	AssertLogRelRCReturn(rc, rc);
1004
1005	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
1006	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
1007	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
1008
1009	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
1010	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
1011	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
1012	#endif
1013	}
1014	}
1015
1016	rc = VINF_SUCCESS;
1017	}
1018
1019	if ( RT_SUCCESS(rc)
1020	&& g_HmR0.fGlobalInit)
1021	{
1022	/* First time, so initialize each cpu/core. */
1023	HMR0FIRSTRC FirstRc;
1024	hmR0FirstRcInit(&FirstRc);
1025	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1026	if (RT_SUCCESS(rc))
1027	rc = hmR0FirstRcGetStatus(&FirstRc);
1028	}
1029
1030	return rc;
1031	}
1032
1033
1034	/**
1035	* Sets up HM on all cpus.
1036	*
1037	* @returns VBox status code.
1038	* @param pVM The cross context VM structure.
1039	*/
1040	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1041	{
1042	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1043	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1044	return VERR_HM_SUSPEND_PENDING;
1045
1046	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1047	}
1048
1049
1050	/**
1051	* Disable VT-x or AMD-V on the current CPU.
1052	*
1053	* @returns VBox status code.
1054	* @param idCpu The identifier for the CPU this function is called on.
1055	*
1056	* @remarks Must be called with preemption disabled.
1057	*/
1058	static int hmR0DisableCpu(RTCPUID idCpu)
1059	{
1060	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1061
1062	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1063	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1064	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1065	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1066	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
1067	AssertRelease(idCpu == RTMpCpuId());
1068
1069	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
1070	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1071	AssertPtr(pHostCpu->pvMemObj);
1072	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1073
1074	int rc;
1075	if (pHostCpu->fConfigured)
1076	{
1077	rc = g_HmR0.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1078	AssertRCReturn(rc, rc);
1079
1080	pHostCpu->fConfigured = false;
1081	pHostCpu->idCpu = NIL_RTCPUID;
1082	}
1083	else
1084	rc = VINF_SUCCESS; /* nothing to do */
1085	return rc;
1086	}
1087
1088
1089	/**
1090	* Worker function passed to RTMpOnAll() that is to be called on the target
1091	* CPUs.
1092	*
1093	* @param idCpu The identifier for the CPU the function is called on.
1094	* @param pvUser1 The 1st user argument.
1095	* @param pvUser2 Opaque pointer to the FirstRc.
1096	*/
1097	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1098	{
1099	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1100	AssertReturnVoid(g_HmR0.fGlobalInit);
1101	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1102	}
1103
1104
1105	/**
1106	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1107	* CPU.
1108	*
1109	* @param idCpu The identifier for the CPU the function is called on.
1110	* @param pvUser1 Null, not used.
1111	* @param pvUser2 Null, not used.
1112	*/
1113	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1114	{
1115	NOREF(pvUser1);
1116	NOREF(pvUser2);
1117	hmR0DisableCpu(idCpu);
1118	}
1119
1120
1121	/**
1122	* Callback function invoked when a cpu goes online or offline.
1123	*
1124	* @param enmEvent The Mp event.
1125	* @param idCpu The identifier for the CPU the function is called on.
1126	* @param pvData Opaque data (PVM pointer).
1127	*/
1128	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1129	{
1130	NOREF(pvData);
1131	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1132
1133	/*
1134	* We only care about uninitializing a CPU that is going offline. When a
1135	* CPU comes online, the initialization is done lazily in HMR0Enter().
1136	*/
1137	switch (enmEvent)
1138	{
1139	case RTMPEVENT_OFFLINE:
1140	{
1141	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1142	RTThreadPreemptDisable(&PreemptState);
1143	if (idCpu == RTMpCpuId())
1144	{
1145	int rc = hmR0DisableCpu(idCpu);
1146	AssertRC(rc);
1147	RTThreadPreemptRestore(&PreemptState);
1148	}
1149	else
1150	{
1151	RTThreadPreemptRestore(&PreemptState);
1152	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1153	}
1154	break;
1155	}
1156
1157	default:
1158	break;
1159	}
1160	}
1161
1162
1163	/**
1164	* Called whenever a system power state change occurs.
1165	*
1166	* @param enmEvent The Power event.
1167	* @param pvUser User argument.
1168	*/
1169	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1170	{
1171	NOREF(pvUser);
1172	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1173
1174	#ifdef LOG_ENABLED
1175	if (enmEvent == RTPOWEREVENT_SUSPEND)
1176	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1177	else
1178	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1179	#endif
1180
1181	if (enmEvent == RTPOWEREVENT_SUSPEND)
1182	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1183
1184	if (g_HmR0.fEnabled)
1185	{
1186	int rc;
1187	HMR0FIRSTRC FirstRc;
1188	hmR0FirstRcInit(&FirstRc);
1189
1190	if (enmEvent == RTPOWEREVENT_SUSPEND)
1191	{
1192	if (g_HmR0.fGlobalInit)
1193	{
1194	/* Turn off VT-x or AMD-V on all CPUs. */
1195	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1196	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1197	}
1198	/* else nothing to do here for the local init case */
1199	}
1200	else
1201	{
1202	/* Reinit the CPUs from scratch as the suspend state might have
1203	messed with the MSRs. (lousy BIOSes as usual) */
1204	if (g_HmR0.vmx.fSupported)
1205	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1206	else
1207	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1208	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1209	if (RT_SUCCESS(rc))
1210	rc = hmR0FirstRcGetStatus(&FirstRc);
1211	#ifdef LOG_ENABLED
1212	if (RT_FAILURE(rc))
1213	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1214	#endif
1215	if (g_HmR0.fGlobalInit)
1216	{
1217	/* Turn VT-x or AMD-V back on on all CPUs. */
1218	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1219	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1220	}
1221	/* else nothing to do here for the local init case */
1222	}
1223	}
1224
1225	if (enmEvent == RTPOWEREVENT_RESUME)
1226	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1227	}
1228
1229
1230	/**
1231	* Does ring-0 per-VM HM initialization.
1232	*
1233	* This will copy HM global into the VM structure and call the CPU specific
1234	* init routine which will allocate resources for each virtual CPU and such.
1235	*
1236	* @returns VBox status code.
1237	* @param pVM The cross context VM structure.
1238	*
1239	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1240	* vmR3InitRing3().
1241	*/
1242	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1243	{
1244	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1245
1246	#ifdef LOG_ENABLED
1247	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1248	#endif
1249
1250	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1251	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1252	return VERR_HM_SUSPEND_PENDING;
1253
1254	/*
1255	* Copy globals to the VM structure.
1256	*/
1257	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1258	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1259	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1260	if (pVM->hm.s.vmx.fSupported)
1261	{
1262	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1263	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1264	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1265	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1266	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.vmx.u64HostSmmMonitorCtl;
1267	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1268	}
1269	else if (pVM->hm.s.svm.fSupported)
1270	{
1271	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1272	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1273	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1274	}
1275	pVM->hm.s.rcInit = g_HmR0.rcInit;
1276	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1277
1278	/*
1279	* Set default maximum inner loops in ring-0 before returning to ring-3.
1280	* Can be overriden using CFGM.
1281	*/
1282	if (!pVM->hm.s.cMaxResumeLoops)
1283	{
1284	pVM->hm.s.cMaxResumeLoops = 1024;
1285	if (RTThreadPreemptIsPendingTrusty())
1286	pVM->hm.s.cMaxResumeLoops = 8192;
1287	}
1288
1289	/*
1290	* Initialize some per-VCPU fields.
1291	*/
1292	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1293	{
1294	PVMCPU pVCpu = &pVM->aCpus[i];
1295	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1296	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1297	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1298
1299	/* We'll aways increment this the first time (host uses ASID 0). */
1300	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1301	}
1302
1303	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1304
1305	/*
1306	* Call the hardware specific initialization method.
1307	*/
1308	return g_HmR0.pfnInitVM(pVM);
1309	}
1310
1311
1312	/**
1313	* Does ring-0 per VM HM termination.
1314	*
1315	* @returns VBox status code.
1316	* @param pVM The cross context VM structure.
1317	*/
1318	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1319	{
1320	Log(("HMR0TermVM: %p\n", pVM));
1321	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1322
1323	/*
1324	* Call the hardware specific method.
1325	*
1326	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1327	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1328	*/
1329	return g_HmR0.pfnTermVM(pVM);
1330	}
1331
1332
1333	/**
1334	* Sets up a VT-x or AMD-V session.
1335	*
1336	* This is mostly about setting up the hardware VM state.
1337	*
1338	* @returns VBox status code.
1339	* @param pVM The cross context VM structure.
1340	*/
1341	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1342	{
1343	Log(("HMR0SetupVM: %p\n", pVM));
1344	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1345
1346	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1347	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1348
1349	/* On first entry we'll sync everything. */
1350	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1351	{
1352	PVMCPU pVCpu = &pVM->aCpus[i];
1353	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1354	}
1355
1356	/*
1357	* Call the hardware specific setup VM method. This requires the CPU to be
1358	* enabled for AMD-V/VT-x and preemption to be prevented.
1359	*/
1360	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1361	RTThreadPreemptDisable(&PreemptState);
1362	RTCPUID const idCpu = RTMpCpuId();
1363
1364	/* Enable VT-x or AMD-V if local init is required. */
1365	int rc;
1366	if (!g_HmR0.fGlobalInit)
1367	{
1368	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1369	rc = hmR0EnableCpu(pVM, idCpu);
1370	if (RT_FAILURE(rc))
1371	{
1372	RTThreadPreemptRestore(&PreemptState);
1373	return rc;
1374	}
1375	}
1376
1377	/* Setup VT-x or AMD-V. */
1378	rc = g_HmR0.pfnSetupVM(pVM);
1379
1380	/* Disable VT-x or AMD-V if local init was done before. */
1381	if (!g_HmR0.fGlobalInit)
1382	{
1383	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1384	int rc2 = hmR0DisableCpu(idCpu);
1385	AssertRC(rc2);
1386	}
1387
1388	RTThreadPreemptRestore(&PreemptState);
1389	return rc;
1390	}
1391
1392
1393	/**
1394	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1395	* required for entering HM context.
1396	*
1397	* @returns VBox status code.
1398	* @param pVCpu The cross context virtual CPU structure.
1399	*
1400	* @remarks No-long-jump zone!!!
1401	*/
1402	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)
1403	{
1404	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1405
1406	int rc = VINF_SUCCESS;
1407	RTCPUID const idCpu = RTMpCpuId();
1408	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1409	AssertPtr(pHostCpu);
1410
1411	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1412	if (!pHostCpu->fConfigured)
1413	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1414
1415	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1416	if (g_HmR0.vmx.fSupported)
1417	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1418	else
1419	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1420
1421	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1422	pVCpu->hm.s.idEnteredCpu = idCpu;
1423	return rc;
1424	}
1425
1426
1427	/**
1428	* Enters the VT-x or AMD-V session.
1429	*
1430	* @returns VBox status code.
1431	* @param pVCpu The cross context virtual CPU structure.
1432	*
1433	* @remarks This is called with preemption disabled.
1434	*/
1435	VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)
1436	{
1437	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1438	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1439	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1440
1441	/* Load the bare minimum state required for entering HM. */
1442	int rc = hmR0EnterCpu(pVCpu);
1443	AssertRCReturn(rc, rc);
1444
1445	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1446	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1447	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1448	#endif
1449
1450	RTCPUID const idCpu = RTMpCpuId();
1451	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1452	Assert(pHostCpu);
1453	if (g_HmR0.vmx.fSupported)
1454	{
1455	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1456	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1457	}
1458	else
1459	{
1460	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1461	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1462	}
1463
1464	rc = g_HmR0.pfnEnterSession(pVCpu, pHostCpu);
1465	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1466
1467	/* Exports the host-state as we may be resuming code after a longjmp and quite
1468	possibly now be scheduled on a different CPU. */
1469	rc = g_HmR0.pfnExportHostState(pVCpu);
1470	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1471
1472	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1473	if (fStartedSet)
1474	PGMRZDynMapReleaseAutoSet(pVCpu);
1475	#endif
1476
1477	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1478	if (RT_FAILURE(rc))
1479	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1480	return rc;
1481	}
1482
1483
1484	/**
1485	* Deinitializes the bare minimum state used for HM context and if necessary
1486	* disable HM on the CPU.
1487	*
1488	* @returns VBox status code.
1489	* @param pVCpu The cross context virtual CPU structure.
1490	*
1491	* @remarks No-long-jump zone!!!
1492	*/
1493	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1494	{
1495	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1496	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1497
1498	RTCPUID const idCpu = RTMpCpuId();
1499	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1500
1501	if ( !g_HmR0.fGlobalInit
1502	&& pHostCpu->fConfigured)
1503	{
1504	int rc = hmR0DisableCpu(idCpu);
1505	AssertRCReturn(rc, rc);
1506	Assert(!pHostCpu->fConfigured);
1507	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1508
1509	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1510	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1511	}
1512
1513	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1514	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1515
1516	return VINF_SUCCESS;
1517	}
1518
1519
1520	/**
1521	* Thread-context hook for HM.
1522	*
1523	* @param enmEvent The thread-context event.
1524	* @param pvUser Opaque pointer to the VMCPU.
1525	*/
1526	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1527	{
1528	PVMCPU pVCpu = (PVMCPU)pvUser;
1529	Assert(pVCpu);
1530	Assert(g_HmR0.pfnThreadCtxCallback);
1531
1532	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1533	}
1534
1535
1536	/**
1537	* Runs guest code in a hardware accelerated VM.
1538	*
1539	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1540	* called from setjmp assembly.)
1541	* @param pVM The cross context VM structure.
1542	* @param pVCpu The cross context virtual CPU structure.
1543	*
1544	* @remarks Can be called with preemption enabled if thread-context hooks are
1545	* used!!!
1546	*/
1547	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1548	{
1549	RT_NOREF(pVM);
1550
1551	#ifdef VBOX_STRICT
1552	/* With thread-context hooks we would be running this code with preemption enabled. */
1553	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1554	{
1555	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1556	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1557	Assert(pHostCpu->fConfigured);
1558	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1559	}
1560	#endif
1561
1562	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1563	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1564	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1565	PGMRZDynMapStartAutoSet(pVCpu);
1566	#endif
1567
1568	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1569
1570	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1571	PGMRZDynMapReleaseAutoSet(pVCpu);
1572	#endif
1573	return VBOXSTRICTRC_VAL(rcStrict);
1574	}
1575
1576
1577	/**
1578	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1579	* the host CPU and that guest access to it must be intercepted.
1580	*
1581	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1582	*/
1583	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1584	{
1585	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1586	}
1587
1588
1589	/**
1590	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1591	*
1592	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1593	*/
1594	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1595	{
1596	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1597	}
1598
1599
1600	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1601
1602	/**
1603	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1604	*
1605	* @returns VBox status code.
1606	* @param pVM The cross context VM structure.
1607	* @param pVCpu The cross context virtual CPU structure.
1608	* @param pCtx Pointer to the guest CPU context.
1609	*/
1610	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1611	{
1612	RT_NOREF(pCtx);
1613	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1614	if (pVM->hm.s.vmx.fSupported)
1615	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1616	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1617	}
1618
1619
1620	/**
1621	* Save guest debug state (64 bits guest mode & 32 bits host only)
1622	*
1623	* @returns VBox status code.
1624	* @param pVM The cross context VM structure.
1625	* @param pVCpu The cross context virtual CPU structure.
1626	* @param pCtx Pointer to the guest CPU context.
1627	*/
1628	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1629	{
1630	RT_NOREF(pCtx);
1631	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1632	if (pVM->hm.s.vmx.fSupported)
1633	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1634	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1635	}
1636
1637
1638	/**
1639	* Test the 32->64 bits switcher.
1640	*
1641	* @returns VBox status code.
1642	* @param pVM The cross context VM structure.
1643	*/
1644	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1645	{
1646	PVMCPU pVCpu = &pVM->aCpus[0];
1647	uint32_t aParam[5] = { 0, 1, 2, 3, 4 };
1648	int rc;
1649
1650	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1651	if (pVM->hm.s.vmx.fSupported)
1652	rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1653	else
1654	rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1655	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1656
1657	return rc;
1658	}
1659
1660	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1661
1662	/**
1663	* Returns suspend status of the host.
1664	*
1665	* @returns Suspend pending or not.
1666	*/
1667	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1668	{
1669	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1670	}
1671
1672
1673	/**
1674	* Invalidates a guest page from the host TLB.
1675	*
1676	* @param pVCpu The cross context virtual CPU structure.
1677	* @param GCVirt Page to invalidate.
1678	*/
1679	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1680	{
1681	PVM pVM = pVCpu->CTX_SUFF(pVM);
1682	if (pVM->hm.s.vmx.fSupported)
1683	return VMXR0InvalidatePage(pVCpu, GCVirt);
1684	return SVMR0InvalidatePage(pVCpu, GCVirt);
1685	}
1686
1687
1688	/**
1689	* Returns the cpu structure for the current cpu.
1690	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1691	*
1692	* @returns The cpu structure pointer.
1693	*/
1694	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void)
1695	{
1696	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1697	RTCPUID const idCpu = RTMpCpuId();
1698	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1699	return &g_HmR0.aCpuInfo[idCpu];
1700	}
1701
1702
1703	/**
1704	* Interface for importing state on demand (used by IEM).
1705	*
1706	* @returns VBox status code.
1707	* @param pVCpu The cross context CPU structure.
1708	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1709	*/
1710	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
1711	{
1712	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1713	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1714	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1715	}
1716
1717
1718	#ifdef VBOX_WITH_RAW_MODE
1719	/**
1720	* Raw-mode switcher hook - disable VT-x if it's active and the current
1721	* switcher turns off paging.
1722	*
1723	* @returns VBox status code.
1724	* @param pVM The cross context VM structure.
1725	* @param enmSwitcher The switcher we're about to use.
1726	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1727	*/
1728	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1729	{
1730	NOREF(pVM);
1731
1732	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1733
1734	*pfVTxDisabled = false;
1735
1736	/* No such issues with AMD-V */
1737	if (!g_HmR0.vmx.fSupported)
1738	return VINF_SUCCESS;
1739
1740	/* Check if the switching we're up to is safe. */
1741	switch (enmSwitcher)
1742	{
1743	case VMMSWITCHER_32_TO_32:
1744	case VMMSWITCHER_PAE_TO_PAE:
1745	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1746
1747	case VMMSWITCHER_32_TO_PAE:
1748	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1749	case VMMSWITCHER_AMD64_TO_32:
1750	case VMMSWITCHER_AMD64_TO_PAE:
1751	break; /* unsafe switchers */
1752
1753	default:
1754	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1755	}
1756
1757	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1758	regardless of whether we're currently using VT-x or not. */
1759	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1760	{
1761	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1762	return VINF_SUCCESS;
1763	}
1764
1765	/** @todo Check if this code is presumptive wrt other VT-x users on the
1766	* system... */
1767
1768	/* Nothing to do if we haven't enabled VT-x. */
1769	if (!g_HmR0.fEnabled)
1770	return VINF_SUCCESS;
1771
1772	/* Local init implies the CPU is currently not in VMX root mode. */
1773	if (!g_HmR0.fGlobalInit)
1774	return VINF_SUCCESS;
1775
1776	/* Ok, disable VT-x. */
1777	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1778	AssertReturn( pHostCpu
1779	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1780	&& pHostCpu->pvMemObj
1781	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS,
1782	VERR_HM_IPE_2);
1783
1784	*pfVTxDisabled = true;
1785	return VMXR0DisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1786	}
1787
1788
1789	/**
1790	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1791	* switcher turned off paging.
1792	*
1793	* @param pVM The cross context VM structure.
1794	* @param fVTxDisabled Whether VT-x was disabled or not.
1795	*/
1796	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1797	{
1798	Assert(!ASMIntAreEnabled());
1799
1800	if (!fVTxDisabled)
1801	return; /* nothing to do */
1802
1803	Assert(g_HmR0.vmx.fSupported);
1804	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1805	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1806	else
1807	{
1808	Assert(g_HmR0.fEnabled);
1809	Assert(g_HmR0.fGlobalInit);
1810
1811	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1812	AssertReturnVoid( pHostCpu
1813	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1814	&& pHostCpu->pvMemObj
1815	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1816
1817	VMXR0EnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
1818	}
1819	}
1820	#endif /* VBOX_WITH_RAW_MODE */
1821
1822
1823	#ifdef VBOX_STRICT
1824	/**
1825	* Dumps a descriptor.
1826	*
1827	* @param pDesc Descriptor to dump.
1828	* @param Sel Selector number.
1829	* @param pszMsg Message to prepend the log entry with.
1830	*/
1831	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1832	{
1833	/*
1834	* Make variable description string.
1835	*/
1836	static struct
1837	{
1838	unsigned cch;
1839	const char *psz;
1840	} const s_aTypes[32] =
1841	{
1842	# define STRENTRY(str) { sizeof(str) - 1, str }
1843
1844	/* system */
1845	# if HC_ARCH_BITS == 64
1846	STRENTRY("Reserved0 "), /* 0x00 */
1847	STRENTRY("Reserved1 "), /* 0x01 */
1848	STRENTRY("LDT "), /* 0x02 */
1849	STRENTRY("Reserved3 "), /* 0x03 */
1850	STRENTRY("Reserved4 "), /* 0x04 */
1851	STRENTRY("Reserved5 "), /* 0x05 */
1852	STRENTRY("Reserved6 "), /* 0x06 */
1853	STRENTRY("Reserved7 "), /* 0x07 */
1854	STRENTRY("Reserved8 "), /* 0x08 */
1855	STRENTRY("TSS64Avail "), /* 0x09 */
1856	STRENTRY("ReservedA "), /* 0x0a */
1857	STRENTRY("TSS64Busy "), /* 0x0b */
1858	STRENTRY("Call64 "), /* 0x0c */
1859	STRENTRY("ReservedD "), /* 0x0d */
1860	STRENTRY("Int64 "), /* 0x0e */
1861	STRENTRY("Trap64 "), /* 0x0f */
1862	# else
1863	STRENTRY("Reserved0 "), /* 0x00 */
1864	STRENTRY("TSS16Avail "), /* 0x01 */
1865	STRENTRY("LDT "), /* 0x02 */
1866	STRENTRY("TSS16Busy "), /* 0x03 */
1867	STRENTRY("Call16 "), /* 0x04 */
1868	STRENTRY("Task "), /* 0x05 */
1869	STRENTRY("Int16 "), /* 0x06 */
1870	STRENTRY("Trap16 "), /* 0x07 */
1871	STRENTRY("Reserved8 "), /* 0x08 */
1872	STRENTRY("TSS32Avail "), /* 0x09 */
1873	STRENTRY("ReservedA "), /* 0x0a */
1874	STRENTRY("TSS32Busy "), /* 0x0b */
1875	STRENTRY("Call32 "), /* 0x0c */
1876	STRENTRY("ReservedD "), /* 0x0d */
1877	STRENTRY("Int32 "), /* 0x0e */
1878	STRENTRY("Trap32 "), /* 0x0f */
1879	# endif
1880	/* non system */
1881	STRENTRY("DataRO "), /* 0x10 */
1882	STRENTRY("DataRO Accessed "), /* 0x11 */
1883	STRENTRY("DataRW "), /* 0x12 */
1884	STRENTRY("DataRW Accessed "), /* 0x13 */
1885	STRENTRY("DataDownRO "), /* 0x14 */
1886	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1887	STRENTRY("DataDownRW "), /* 0x16 */
1888	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1889	STRENTRY("CodeEO "), /* 0x18 */
1890	STRENTRY("CodeEO Accessed "), /* 0x19 */
1891	STRENTRY("CodeER "), /* 0x1a */
1892	STRENTRY("CodeER Accessed "), /* 0x1b */
1893	STRENTRY("CodeConfEO "), /* 0x1c */
1894	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1895	STRENTRY("CodeConfER "), /* 0x1e */
1896	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1897	# undef SYSENTRY
1898	};
1899	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1900	char szMsg[128];
1901	char *psz = &szMsg[0];
1902	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1903	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1904	psz += s_aTypes[i].cch;
1905
1906	if (pDesc->Gen.u1Present)
1907	ADD_STR(psz, "Present ");
1908	else
1909	ADD_STR(psz, "Not-Present ");
1910	# if HC_ARCH_BITS == 64
1911	if (pDesc->Gen.u1Long)
1912	ADD_STR(psz, "64-bit ");
1913	else
1914	ADD_STR(psz, "Comp ");
1915	# else
1916	if (pDesc->Gen.u1Granularity)
1917	ADD_STR(psz, "Page ");
1918	if (pDesc->Gen.u1DefBig)
1919	ADD_STR(psz, "32-bit ");
1920	else
1921	ADD_STR(psz, "16-bit ");
1922	# endif
1923	# undef ADD_STR
1924	*psz = '\0';
1925
1926	/*
1927	* Limit and Base and format the output.
1928	*/
1929	#ifdef LOG_ENABLED
1930	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1931
1932	# if HC_ARCH_BITS == 64
1933	uint64_t u32Base = X86DESC64_BASE(pDesc);
1934	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1935	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1936	# else
1937	uint32_t u32Base = X86DESC_BASE(pDesc);
1938	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1939	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1940	# endif
1941	#else
1942	NOREF(Sel); NOREF(pszMsg);
1943	#endif
1944	}
1945
1946
1947	/**
1948	* Formats a full register dump.
1949	*
1950	* @param pVCpu The cross context virtual CPU structure.
1951	*/
1952	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu)
1953	{
1954	/*
1955	* Format the flags.
1956	*/
1957	static struct
1958	{
1959	const char pszSet; const char pszClear; uint32_t fFlag;
1960	} const s_aFlags[] =
1961	{
1962	{ "vip", NULL, X86_EFL_VIP },
1963	{ "vif", NULL, X86_EFL_VIF },
1964	{ "ac", NULL, X86_EFL_AC },
1965	{ "vm", NULL, X86_EFL_VM },
1966	{ "rf", NULL, X86_EFL_RF },
1967	{ "nt", NULL, X86_EFL_NT },
1968	{ "ov", "nv", X86_EFL_OF },
1969	{ "dn", "up", X86_EFL_DF },
1970	{ "ei", "di", X86_EFL_IF },
1971	{ "tf", NULL, X86_EFL_TF },
1972	{ "nt", "pl", X86_EFL_SF },
1973	{ "nz", "zr", X86_EFL_ZF },
1974	{ "ac", "na", X86_EFL_AF },
1975	{ "po", "pe", X86_EFL_PF },
1976	{ "cy", "nc", X86_EFL_CF },
1977	};
1978	char szEFlags[80];
1979	char *psz = szEFlags;
1980	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1981	uint32_t uEFlags = pCtx->eflags.u32;
1982	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1983	{
1984	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1985	if (pszAdd)
1986	{
1987	strcpy(psz, pszAdd);
1988	psz += strlen(pszAdd);
1989	*psz++ = ' ';
1990	}
1991	}
1992	psz[-1] = '\0';
1993
1994	/*
1995	* Format the registers.
1996	*/
1997	if (CPUMIsGuestIn64BitCode(pVCpu))
1998	{
1999	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
2000	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
2001	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2002	"r14=%016RX64 r15=%016RX64\n"
2003	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
2004	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2005	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2006	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2007	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2008	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2009	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2010	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2011	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2012	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2013	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2014	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2015	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2016	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2017	,
2018	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2019	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2020	pCtx->r14, pCtx->r15,
2021	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2022	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2023	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2024	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2025	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2026	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2027	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2028	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2029	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2030	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2031	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2032	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2033	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2034	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2035	}
2036	else
2037	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2038	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2039	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2040	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2041	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2042	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2043	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2044	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2045	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2046	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2047	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2048	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2049	,
2050	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2051	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2052	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2053	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2054	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2055	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2056	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2057	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2058	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2059	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2060	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2061	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2062
2063	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2064	Log(("FPU:\n"
2065	"FCW=%04x FSW=%04x FTW=%02x\n"
2066	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2067	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2068	,
2069	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
2070	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
2071	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
2072	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
2073
2074	Log(("MSR:\n"
2075	"EFER =%016RX64\n"
2076	"PAT =%016RX64\n"
2077	"STAR =%016RX64\n"
2078	"CSTAR =%016RX64\n"
2079	"LSTAR =%016RX64\n"
2080	"SFMASK =%016RX64\n"
2081	"KERNELGSBASE =%016RX64\n",
2082	pCtx->msrEFER,
2083	pCtx->msrPAT,
2084	pCtx->msrSTAR,
2085	pCtx->msrCSTAR,
2086	pCtx->msrLSTAR,
2087	pCtx->msrSFMASK,
2088	pCtx->msrKERNELGSBASE));
2089
2090	NOREF(pFpuCtx);
2091	}
2092	#endif /* VBOX_STRICT */
2093

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 75649

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