HMR0.cpp@ 76232

Last change on this file since 76232 was 76232, checked in by vboxsync, 6 years ago
VMM/HMR0: Read the VMX MSRs into a separate function.
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File size: 72.5 KB

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1	/* $Id: HMR0.cpp 76232 2018-12-14 12:54:14Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/hm_vmx.h>
29	#include <VBox/vmm/hm_svm.h>
30	#include <VBox/vmm/gim.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35	#include <iprt/asm-amd64-x86.h>
36	#include <iprt/cpuset.h>
37	#include <iprt/mem.h>
38	#include <iprt/memobj.h>
39	#include <iprt/once.h>
40	#include <iprt/param.h>
41	#include <iprt/power.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44	#include <iprt/x86.h>
45	#include "HMVMXR0.h"
46	#include "HMSVMR0.h"
47
48
49	/*********************************************************************************************************************************
50	* Internal Functions *
51	*********************************************************************************************************************************/
52	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* This is used to manage the status code of a RTMpOnAll in HM.
65	*/
66	typedef struct HMR0FIRSTRC
67	{
68	/** The status code. */
69	int32_t volatile rc;
70	/** The ID of the CPU reporting the first failure. */
71	RTCPUID volatile idCpu;
72	} HMR0FIRSTRC;
73	/** Pointer to a first return code structure. */
74	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
75
76
77	/*********************************************************************************************************************************
78	* Global Variables *
79	*********************************************************************************************************************************/
80	/**
81	* Global data.
82	*/
83	static struct
84	{
85	/** Per CPU globals. */
86	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
87
88	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
89	* @{ */
90	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu));
91	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
92	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));
93	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost, void *pvArg));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
100	/** @} */
101
102	/** Maximum ASID allowed. */
103	uint32_t uMaxAsid;
104
105	/** VT-x data. */
106	struct
107	{
108	/** Set to by us to indicate VMX is supported by the CPU. */
109	bool fSupported;
110	/** Whether we're using SUPR0EnableVTx or not. */
111	bool fUsingSUPR0EnableVTx;
112	/** Whether we're using the preemption timer or not. */
113	bool fUsePreemptTimer;
114	/** The shift mask employed by the VMX-Preemption timer. */
115	uint8_t cPreemptTimerShift;
116
117	/** Host CR4 value (set by ring-0 VMX init) */
118	uint64_t u64HostCr4;
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121	/** Host SMM monitor control (used for logging/diagnostics) */
122	uint64_t u64HostSmmMonitorCtl;
123
124	/** VMX MSR values. */
125	VMXMSRS Msrs;
126
127	/** Last instruction error. */
128	uint32_t ulLastInstrError;
129
130	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
131	* module termination. */
132	bool fCalledSUPR0EnableVTx;
133	} vmx;
134
135	/** AMD-V information. */
136	struct
137	{
138	/* HWCR MSR (for diagnostics) */
139	uint64_t u64MsrHwcr;
140
141	/** SVM revision. */
142	uint32_t u32Rev;
143
144	/** SVM feature bits from cpuid 0x8000000a */
145	uint32_t u32Features;
146
147	/** Set by us to indicate SVM is supported by the CPU. */
148	bool fSupported;
149	} svm;
150
151	/** Last recorded error code during HM ring-0 init. */
152	int32_t rcInit;
153
154	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
155	* enabled and disabled each time it's used to execute guest code. */
156	bool fGlobalInit;
157	/** Indicates whether the host is suspending or not. We'll refuse a few
158	* actions when the host is being suspended to speed up the suspending and
159	* avoid trouble. */
160	bool volatile fSuspended;
161
162	/** Whether we've already initialized all CPUs.
163	* @remarks We could check the EnableAllCpusOnce state, but this is
164	* simpler and hopefully easier to understand. */
165	bool fEnabled;
166	/** Serialize initialization in HMR0EnableAllCpus. */
167	RTONCE EnableAllCpusOnce;
168	} g_HmR0;
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	# ifndef DEBUG_bird
212	/**
213	* Get the CPU ID on which the failure status code was reported.
214	*
215	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
216	* @param pFirstRc The first return code structure.
217	*/
218	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->idCpu;
221	}
222	# endif
223	#endif /* VBOX_STRICT */
224
225
226	/** @name Dummy callback handlers.
227	* @{ */
228
229	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
230	{
231	RT_NOREF2(pVCpu, pHostCpu);
232	return VINF_SUCCESS;
233	}
234
235	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
236	{
237	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
238	}
239
240	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
241	bool fEnabledBySystem, void *pvArg)
242	{
243	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pvArg);
244	return VINF_SUCCESS;
245	}
246
247	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
248	{
249	RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
254	{
255	RT_NOREF1(pVM);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
260	{
261	RT_NOREF1(pVM);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
266	{
267	RT_NOREF1(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu)
272	{
273	RT_NOREF(pVCpu);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)
278	{
279	RT_NOREF1(pVCpu);
280	return VINF_SUCCESS;
281	}
282
283	/** @} */
284
285
286	/**
287	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
288	* Down at the Rate Specified" erratum.
289	*
290	* Errata names and related steppings:
291	* - BA86 - D0.
292	* - AAX65 - C2.
293	* - AAU65 - C2, K0.
294	* - AAO95 - B1.
295	* - AAT59 - C2.
296	* - AAK139 - D0.
297	* - AAM126 - C0, C1, D0.
298	* - AAN92 - B1.
299	* - AAJ124 - C0, D0.
300	* - AAP86 - B1.
301	*
302	* Steppings: B1, C0, C1, C2, D0, K0.
303	*
304	* @returns true if subject to it, false if not.
305	*/
306	static bool hmR0InitIntelIsSubjectToVmxPreemptTimerErratum(void)
307	{
308	uint32_t u = ASMCpuId_EAX(1);
309	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
310	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
311	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
312	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
313	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
315	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
316	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
317	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
318	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
321	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
322	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
323	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
324	)
325	return true;
326	return false;
327	}
328
329
330	/**
331	* Reads all the VMX feature MSRs.
332	*
333	* @param pVmxMsrs Where to read the VMX MSRs into.
334	* @remarks The caller is expected to have verified if this is an Intel CPU and that
335	* VMX is present (i.e. SUPR0GetVTSupport() must have returned
336	* SUPVTCAPS_VT_X).
337	*/
338	static void hmR0InitIntelReadVmxMsrs(PVMXMSRS pVmxMsrs)
339	{
340	Assert(pVmxMsrs);
341	RT_ZERO(*pVmxMsrs);
342
343	/*
344	* Note! We assume here that all MSRs are consistent across host CPUs
345	* and don't bother with preventing CPU migration.
346	*/
347
348	pVmxMsrs->u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
349	pVmxMsrs->u64Basic = ASMRdMsr(MSR_IA32_VMX_BASIC);
350	pVmxMsrs->PinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
351	pVmxMsrs->ProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
352	pVmxMsrs->ExitCtls.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
353	pVmxMsrs->EntryCtls.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
354	pVmxMsrs->u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
355	pVmxMsrs->u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
356	pVmxMsrs->u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
357	pVmxMsrs->u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
358	pVmxMsrs->u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
359	pVmxMsrs->u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
360
361	if (RT_BF_GET(pVmxMsrs->u64Basic, VMX_BF_BASIC_TRUE_CTLS))
362	{
363	pVmxMsrs->TruePinCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS);
364	pVmxMsrs->TrueProcCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
365	pVmxMsrs->TrueEntryCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_ENTRY_CTLS);
366	pVmxMsrs->TrueExitCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_EXIT_CTLS);
367	}
368
369	if (pVmxMsrs->ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
370	{
371	pVmxMsrs->ProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
372	if (pVmxMsrs->ProcCtls2.n.allowed1 & (VMX_PROC_CTLS2_EPT \| VMX_PROC_CTLS2_VPID))
373	pVmxMsrs->u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
374
375	if (pVmxMsrs->ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMFUNC)
376	pVmxMsrs->u64VmFunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
377	}
378	}
379
380
381	/**
382	* Intel specific initialization code.
383	*
384	* @returns VBox status code (will only fail if out of memory).
385	*/
386	static int hmR0InitIntel(void)
387	{
388	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
389	g_HmR0.vmx.Msrs.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
390
391	/*
392	* First try use native kernel API for controlling VT-x.
393	* (This is only supported by some Mac OS X kernels atm.)
394	*/
395	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
396	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
397	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
398	{
399	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
400	if (RT_SUCCESS(rc))
401	{
402	g_HmR0.vmx.fSupported = true;
403	rc = SUPR0EnableVTx(false /* fEnable */);
404	AssertLogRelRC(rc);
405	}
406	}
407	else
408	{
409	HMR0FIRSTRC FirstRc;
410	hmR0FirstRcInit(&FirstRc);
411	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
412	if (RT_SUCCESS(g_HmR0.rcInit))
413	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
414	}
415
416	if (RT_SUCCESS(g_HmR0.rcInit))
417	{
418	/* Read CR4 and EFER for logging/diagnostic purposes. */
419	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
420	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
421
422	/* Read all the VMX MSRs for determining which VMX features we can use later. */
423	hmR0InitIntelReadVmxMsrs(&g_HmR0.vmx.Msrs);
424
425	/*
426	* KVM workaround: Intel SDM section 34.15.5 describes that MSR_IA32_SMM_MONITOR_CTL
427	* depends on bit 49 of MSR_IA32_VMX_BASIC while table 35-2 says that this MSR is
428	* available if either VMX or SMX is supported.
429	*/
430	if (RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_DUAL_MON))
431	g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
432
433	/* Initialize VPID - 16 bits ASID. */
434	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
435
436	/*
437	* If the host OS has not enabled VT-x for us, try enter VMX root mode
438	* to really verify if VT-x is usable.
439	*/
440	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
441	{
442	/* Allocate a temporary VMXON region. */
443	RTR0MEMOBJ hScatchMemObj;
444	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
445	if (RT_FAILURE(rc))
446	{
447	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
448	return rc;
449	}
450	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
451	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
452	ASMMemZeroPage(pvScatchPage);
453
454	/* Set revision dword at the beginning of the VMXON structure. */
455	(uint32_t )pvScatchPage = RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
456
457	/* Make sure we don't get rescheduled to another CPU during this probe. */
458	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
459
460	/* Check CR4.VMXE. */
461	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
462	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
463	{
464	/* In theory this bit could be cleared behind our back. Which would cause #UD
465	faults when we try to execute the VMX instructions... */
466	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
467	}
468
469	/*
470	* The only way of checking if we're in VMX root mode or not is to try and enter it.
471	* There is no instruction or control bit that tells us if we're in VMX root mode.
472	* Therefore, try and enter VMX root mode here.
473	*/
474	rc = VMXEnable(HCPhysScratchPage);
475	if (RT_SUCCESS(rc))
476	{
477	g_HmR0.vmx.fSupported = true;
478	VMXDisable();
479	}
480	else
481	{
482	/*
483	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
484	* it will crash the host when we enter raw mode, because:
485	*
486	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
487	* this bit), and
488	* (b) turning off paging causes a #GP (unavoidable when switching
489	* from long to 32 bits mode or 32 bits to PAE).
490	*
491	* They should fix their code, but until they do we simply refuse to run.
492	*/
493	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
494	Assert(g_HmR0.vmx.fSupported == false);
495	}
496
497	/*
498	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
499	* set before (some software could incorrectly think it is in VMX mode).
500	*/
501	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
502	ASMSetFlags(fEFlags);
503
504	RTR0MemObjFree(hScatchMemObj, false);
505	}
506
507	if (g_HmR0.vmx.fSupported)
508	{
509	rc = VMXR0GlobalInit();
510	if (RT_FAILURE(rc))
511	g_HmR0.rcInit = rc;
512
513	/*
514	* Install the VT-x methods.
515	*/
516	g_HmR0.pfnEnterSession = VMXR0Enter;
517	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
518	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
519	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
520	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
521	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
522	g_HmR0.pfnInitVM = VMXR0InitVM;
523	g_HmR0.pfnTermVM = VMXR0TermVM;
524	g_HmR0.pfnSetupVM = VMXR0SetupVM;
525
526	/*
527	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
528	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
529	*/
530	if (g_HmR0.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
531	{
532	g_HmR0.vmx.fUsePreemptTimer = true;
533	g_HmR0.vmx.cPreemptTimerShift = RT_BF_GET(g_HmR0.vmx.Msrs.u64Misc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
534	if (hmR0InitIntelIsSubjectToVmxPreemptTimerErratum())
535	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
536	}
537	}
538	}
539	#ifdef LOG_ENABLED
540	else
541	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
542	#endif
543	return VINF_SUCCESS;
544	}
545
546
547	/**
548	* AMD-specific initialization code.
549	*
550	* @returns VBox status code (will only fail if out of memory).
551	*/
552	static int hmR0InitAmd(void)
553	{
554	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
555	int rc = SVMR0GlobalInit();
556	if (RT_FAILURE(rc))
557	{
558	g_HmR0.rcInit = rc;
559	return rc;
560	}
561
562	/*
563	* Install the AMD-V methods.
564	*/
565	g_HmR0.pfnEnterSession = SVMR0Enter;
566	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
567	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
568	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
569	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
570	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
571	g_HmR0.pfnInitVM = SVMR0InitVM;
572	g_HmR0.pfnTermVM = SVMR0TermVM;
573	g_HmR0.pfnSetupVM = SVMR0SetupVM;
574
575	/* Query AMD features. */
576	uint32_t u32Dummy;
577	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
578
579	/*
580	* We need to check if AMD-V has been properly initialized on all CPUs.
581	* Some BIOSes might do a poor job.
582	*/
583	HMR0FIRSTRC FirstRc;
584	hmR0FirstRcInit(&FirstRc);
585	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
586	AssertRC(rc);
587	if (RT_SUCCESS(rc))
588	rc = hmR0FirstRcGetStatus(&FirstRc);
589	#ifndef DEBUG_bird
590	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
591	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
592	#endif
593	if (RT_SUCCESS(rc))
594	{
595	/* Read the HWCR MSR for diagnostics. */
596	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
597	g_HmR0.svm.fSupported = true;
598	}
599	else
600	{
601	g_HmR0.rcInit = rc;
602	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
603	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
604	}
605	return rc;
606	}
607
608
609	/**
610	* Does global Ring-0 HM initialization (at module init).
611	*
612	* @returns VBox status code.
613	*/
614	VMMR0_INT_DECL(int) HMR0Init(void)
615	{
616	/*
617	* Initialize the globals.
618	*/
619	g_HmR0.fEnabled = false;
620	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
621	g_HmR0.EnableAllCpusOnce = s_OnceInit;
622	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
623	{
624	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
625	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
626	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
627	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
628	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
629	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
630	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
631	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
632	#endif
633	}
634
635	/* Fill in all callbacks with placeholders. */
636	g_HmR0.pfnEnterSession = hmR0DummyEnter;
637	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
638	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
639	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
640	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
641	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
642	g_HmR0.pfnInitVM = hmR0DummyInitVM;
643	g_HmR0.pfnTermVM = hmR0DummyTermVM;
644	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
645
646	/* Default is global VT-x/AMD-V init. */
647	g_HmR0.fGlobalInit = true;
648
649	/*
650	* Make sure aCpuInfo is big enough for all the CPUs on this system.
651	*/
652	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
653	{
654	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
655	return VERR_TOO_MANY_CPUS;
656	}
657
658	/*
659	* Check for VT-x or AMD-V support.
660	* Return failure only in out-of-memory situations.
661	*/
662	uint32_t fCaps = 0;
663	int rc = SUPR0GetVTSupport(&fCaps);
664	if (RT_SUCCESS(rc))
665	{
666	if (fCaps & SUPVTCAPS_VT_X)
667	{
668	rc = hmR0InitIntel();
669	if (RT_FAILURE(rc))
670	return rc;
671	}
672	else
673	{
674	Assert(fCaps & SUPVTCAPS_AMD_V);
675	rc = hmR0InitAmd();
676	if (RT_FAILURE(rc))
677	return rc;
678	}
679	}
680	else
681	g_HmR0.rcInit = VERR_UNSUPPORTED_CPU;
682
683	/*
684	* Register notification callbacks that we can use to disable/enable CPUs
685	* when brought offline/online or suspending/resuming.
686	*/
687	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
688	{
689	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
690	AssertRC(rc);
691
692	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
693	AssertRC(rc);
694	}
695
696	/* We return success here because module init shall not fail if HM fails to initialize. */
697	return VINF_SUCCESS;
698	}
699
700
701	/**
702	* Does global Ring-0 HM termination (at module termination).
703	*
704	* @returns VBox status code.
705	*/
706	VMMR0_INT_DECL(int) HMR0Term(void)
707	{
708	int rc;
709	if ( g_HmR0.vmx.fSupported
710	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
711	{
712	/*
713	* Simple if the host OS manages VT-x.
714	*/
715	Assert(g_HmR0.fGlobalInit);
716
717	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
718	{
719	rc = SUPR0EnableVTx(false /* fEnable */);
720	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
721	}
722	else
723	rc = VINF_SUCCESS;
724
725	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
726	{
727	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
728	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
729	}
730	}
731	else
732	{
733	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
734
735	/* Doesn't really matter if this fails. */
736	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
737	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
738
739	/*
740	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
741	*/
742	if (g_HmR0.fGlobalInit)
743	{
744	HMR0FIRSTRC FirstRc;
745	hmR0FirstRcInit(&FirstRc);
746	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
747	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
748	if (RT_SUCCESS(rc))
749	rc = hmR0FirstRcGetStatus(&FirstRc);
750	}
751
752	/*
753	* Free the per-cpu pages used for VT-x and AMD-V.
754	*/
755	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
756	{
757	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
758	{
759	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
760	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
761	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
762	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
763	}
764	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
765	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
766	{
767	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
768	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
769	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
770	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
771	}
772	#endif
773	}
774	}
775
776	/** @todo This needs cleaning up. There's no matching
777	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
778	* should move into their respective modules. */
779	/* Finally, call global VT-x/AMD-V termination. */
780	if (g_HmR0.vmx.fSupported)
781	VMXR0GlobalTerm();
782	else if (g_HmR0.svm.fSupported)
783	SVMR0GlobalTerm();
784
785	return rc;
786	}
787
788
789	/**
790	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
791	* on a CPU.
792	*
793	* @param idCpu The identifier for the CPU the function is called on.
794	* @param pvUser1 Pointer to the first RC structure.
795	* @param pvUser2 Ignored.
796	*/
797	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
798	{
799	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
800	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
801	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
802	NOREF(idCpu); NOREF(pvUser2);
803
804	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
805	hmR0FirstRcSetStatus(pFirstRc, rc);
806	}
807
808
809	/**
810	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
811	* on a CPU.
812	*
813	* @param idCpu The identifier for the CPU the function is called on.
814	* @param pvUser1 Pointer to the first RC structure.
815	* @param pvUser2 Ignored.
816	*/
817	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
818	{
819	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
820	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
821	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
822	NOREF(idCpu); NOREF(pvUser2);
823
824	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
825	hmR0FirstRcSetStatus(pFirstRc, rc);
826	}
827
828
829	/**
830	* Enable VT-x or AMD-V on the current CPU
831	*
832	* @returns VBox status code.
833	* @param pVM The cross context VM structure. Can be NULL.
834	* @param idCpu The identifier for the CPU the function is called on.
835	*
836	* @remarks Maybe called with interrupts disabled!
837	*/
838	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
839	{
840	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
841
842	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
843	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
844	Assert(!pHostCpu->fConfigured);
845	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
846
847	pHostCpu->idCpu = idCpu;
848	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
849
850	int rc;
851	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
852	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
853	else
854	{
855	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
856	if (g_HmR0.vmx.fSupported)
857	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
858	else
859	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, NULL /* pvArg */);
860	}
861	if (RT_SUCCESS(rc))
862	pHostCpu->fConfigured = true;
863
864	return rc;
865	}
866
867
868	/**
869	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
870	*
871	* @param idCpu The identifier for the CPU the function is called on.
872	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
873	* @param pvUser2 The 2nd user argument.
874	*/
875	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
876	{
877	PVM pVM = (PVM)pvUser1; /* can be NULL! */
878	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
879	AssertReturnVoid(g_HmR0.fGlobalInit);
880	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
881	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
882	}
883
884
885	/**
886	* RTOnce callback employed by HMR0EnableAllCpus.
887	*
888	* @returns VBox status code.
889	* @param pvUser Pointer to the VM.
890	*/
891	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
892	{
893	PVM pVM = (PVM)pvUser;
894
895	/*
896	* Indicate that we've initialized.
897	*
898	* Note! There is a potential race between this function and the suspend
899	* notification. Kind of unlikely though, so ignored for now.
900	*/
901	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
902	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
903
904	/*
905	* The global init variable is set by the first VM.
906	*/
907	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
908
909	#ifdef VBOX_STRICT
910	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
911	{
912	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
913	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
914	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
915	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
916	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
917	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
918	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
919	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
920	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
921	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
922	# endif
923	}
924	#endif
925
926	int rc;
927	if ( g_HmR0.vmx.fSupported
928	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
929	{
930	/*
931	* Global VT-x initialization API (only darwin for now).
932	*/
933	rc = SUPR0EnableVTx(true /* fEnable */);
934	if (RT_SUCCESS(rc))
935	{
936	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
937	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
938	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
939	}
940	else
941	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
942	}
943	else
944	{
945	/*
946	* We're doing the job ourselves.
947	*/
948	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
949	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
950	{
951	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
952	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
953	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
954	#endif
955	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
956	{
957	/** @todo NUMA */
958	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
959	AssertLogRelRCReturn(rc, rc);
960
961	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
962	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
963	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
964
965	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
966	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
967	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
968
969	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
970	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
971	false /* executable R0 mapping */);
972	AssertLogRelRCReturn(rc, rc);
973
974	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
975	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
976	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
977
978	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
979	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
980	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
981	#endif
982	}
983	}
984
985	rc = VINF_SUCCESS;
986	}
987
988	if ( RT_SUCCESS(rc)
989	&& g_HmR0.fGlobalInit)
990	{
991	/* First time, so initialize each cpu/core. */
992	HMR0FIRSTRC FirstRc;
993	hmR0FirstRcInit(&FirstRc);
994	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
995	if (RT_SUCCESS(rc))
996	rc = hmR0FirstRcGetStatus(&FirstRc);
997	}
998
999	return rc;
1000	}
1001
1002
1003	/**
1004	* Sets up HM on all cpus.
1005	*
1006	* @returns VBox status code.
1007	* @param pVM The cross context VM structure.
1008	*/
1009	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1010	{
1011	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1012	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1013	return VERR_HM_SUSPEND_PENDING;
1014
1015	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1016	}
1017
1018
1019	/**
1020	* Disable VT-x or AMD-V on the current CPU.
1021	*
1022	* @returns VBox status code.
1023	* @param idCpu The identifier for the CPU this function is called on.
1024	*
1025	* @remarks Must be called with preemption disabled.
1026	*/
1027	static int hmR0DisableCpu(RTCPUID idCpu)
1028	{
1029	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1030
1031	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1032	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1033	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1034	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1035	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
1036	AssertRelease(idCpu == RTMpCpuId());
1037
1038	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
1039	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1040	AssertPtr(pHostCpu->pvMemObj);
1041	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1042
1043	int rc;
1044	if (pHostCpu->fConfigured)
1045	{
1046	rc = g_HmR0.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1047	AssertRCReturn(rc, rc);
1048
1049	pHostCpu->fConfigured = false;
1050	pHostCpu->idCpu = NIL_RTCPUID;
1051	}
1052	else
1053	rc = VINF_SUCCESS; /* nothing to do */
1054	return rc;
1055	}
1056
1057
1058	/**
1059	* Worker function passed to RTMpOnAll() that is to be called on the target
1060	* CPUs.
1061	*
1062	* @param idCpu The identifier for the CPU the function is called on.
1063	* @param pvUser1 The 1st user argument.
1064	* @param pvUser2 Opaque pointer to the FirstRc.
1065	*/
1066	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1067	{
1068	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1069	AssertReturnVoid(g_HmR0.fGlobalInit);
1070	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1071	}
1072
1073
1074	/**
1075	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1076	* CPU.
1077	*
1078	* @param idCpu The identifier for the CPU the function is called on.
1079	* @param pvUser1 Null, not used.
1080	* @param pvUser2 Null, not used.
1081	*/
1082	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1083	{
1084	NOREF(pvUser1);
1085	NOREF(pvUser2);
1086	hmR0DisableCpu(idCpu);
1087	}
1088
1089
1090	/**
1091	* Callback function invoked when a cpu goes online or offline.
1092	*
1093	* @param enmEvent The Mp event.
1094	* @param idCpu The identifier for the CPU the function is called on.
1095	* @param pvData Opaque data (PVM pointer).
1096	*/
1097	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1098	{
1099	NOREF(pvData);
1100	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1101
1102	/*
1103	* We only care about uninitializing a CPU that is going offline. When a
1104	* CPU comes online, the initialization is done lazily in HMR0Enter().
1105	*/
1106	switch (enmEvent)
1107	{
1108	case RTMPEVENT_OFFLINE:
1109	{
1110	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1111	RTThreadPreemptDisable(&PreemptState);
1112	if (idCpu == RTMpCpuId())
1113	{
1114	int rc = hmR0DisableCpu(idCpu);
1115	AssertRC(rc);
1116	RTThreadPreemptRestore(&PreemptState);
1117	}
1118	else
1119	{
1120	RTThreadPreemptRestore(&PreemptState);
1121	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1122	}
1123	break;
1124	}
1125
1126	default:
1127	break;
1128	}
1129	}
1130
1131
1132	/**
1133	* Called whenever a system power state change occurs.
1134	*
1135	* @param enmEvent The Power event.
1136	* @param pvUser User argument.
1137	*/
1138	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1139	{
1140	NOREF(pvUser);
1141	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1142
1143	#ifdef LOG_ENABLED
1144	if (enmEvent == RTPOWEREVENT_SUSPEND)
1145	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1146	else
1147	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1148	#endif
1149
1150	if (enmEvent == RTPOWEREVENT_SUSPEND)
1151	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1152
1153	if (g_HmR0.fEnabled)
1154	{
1155	int rc;
1156	HMR0FIRSTRC FirstRc;
1157	hmR0FirstRcInit(&FirstRc);
1158
1159	if (enmEvent == RTPOWEREVENT_SUSPEND)
1160	{
1161	if (g_HmR0.fGlobalInit)
1162	{
1163	/* Turn off VT-x or AMD-V on all CPUs. */
1164	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1165	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1166	}
1167	/* else nothing to do here for the local init case */
1168	}
1169	else
1170	{
1171	/* Reinit the CPUs from scratch as the suspend state might have
1172	messed with the MSRs. (lousy BIOSes as usual) */
1173	if (g_HmR0.vmx.fSupported)
1174	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1175	else
1176	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1177	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1178	if (RT_SUCCESS(rc))
1179	rc = hmR0FirstRcGetStatus(&FirstRc);
1180	#ifdef LOG_ENABLED
1181	if (RT_FAILURE(rc))
1182	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1183	#endif
1184	if (g_HmR0.fGlobalInit)
1185	{
1186	/* Turn VT-x or AMD-V back on on all CPUs. */
1187	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1188	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1189	}
1190	/* else nothing to do here for the local init case */
1191	}
1192	}
1193
1194	if (enmEvent == RTPOWEREVENT_RESUME)
1195	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1196	}
1197
1198
1199	/**
1200	* Does ring-0 per-VM HM initialization.
1201	*
1202	* This will copy HM global into the VM structure and call the CPU specific
1203	* init routine which will allocate resources for each virtual CPU and such.
1204	*
1205	* @returns VBox status code.
1206	* @param pVM The cross context VM structure.
1207	*
1208	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1209	* vmR3InitRing3().
1210	*/
1211	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1212	{
1213	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1214
1215	#ifdef LOG_ENABLED
1216	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1217	#endif
1218
1219	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1220	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1221	return VERR_HM_SUSPEND_PENDING;
1222
1223	/*
1224	* Copy globals to the VM structure.
1225	*/
1226	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1227	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1228	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1229	if (pVM->hm.s.vmx.fSupported)
1230	{
1231	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1232	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1233	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1234	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1235	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.vmx.u64HostSmmMonitorCtl;
1236	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1237	}
1238	else if (pVM->hm.s.svm.fSupported)
1239	{
1240	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1241	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1242	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1243	}
1244	pVM->hm.s.rcInit = g_HmR0.rcInit;
1245	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1246
1247	/*
1248	* Set default maximum inner loops in ring-0 before returning to ring-3.
1249	* Can be overriden using CFGM.
1250	*/
1251	if (!pVM->hm.s.cMaxResumeLoops)
1252	{
1253	pVM->hm.s.cMaxResumeLoops = 1024;
1254	if (RTThreadPreemptIsPendingTrusty())
1255	pVM->hm.s.cMaxResumeLoops = 8192;
1256	}
1257
1258	/*
1259	* Initialize some per-VCPU fields.
1260	*/
1261	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1262	{
1263	PVMCPU pVCpu = &pVM->aCpus[i];
1264	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1265	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1266	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1267
1268	/* We'll aways increment this the first time (host uses ASID 0). */
1269	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1270	}
1271
1272	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1273
1274	/*
1275	* Call the hardware specific initialization method.
1276	*/
1277	return g_HmR0.pfnInitVM(pVM);
1278	}
1279
1280
1281	/**
1282	* Does ring-0 per VM HM termination.
1283	*
1284	* @returns VBox status code.
1285	* @param pVM The cross context VM structure.
1286	*/
1287	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1288	{
1289	Log(("HMR0TermVM: %p\n", pVM));
1290	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1291
1292	/*
1293	* Call the hardware specific method.
1294	*
1295	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1296	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1297	*/
1298	return g_HmR0.pfnTermVM(pVM);
1299	}
1300
1301
1302	/**
1303	* Sets up a VT-x or AMD-V session.
1304	*
1305	* This is mostly about setting up the hardware VM state.
1306	*
1307	* @returns VBox status code.
1308	* @param pVM The cross context VM structure.
1309	*/
1310	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1311	{
1312	Log(("HMR0SetupVM: %p\n", pVM));
1313	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1314
1315	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1316	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1317
1318	/* On first entry we'll sync everything. */
1319	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1320	{
1321	PVMCPU pVCpu = &pVM->aCpus[i];
1322	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1323	}
1324
1325	/*
1326	* Call the hardware specific setup VM method. This requires the CPU to be
1327	* enabled for AMD-V/VT-x and preemption to be prevented.
1328	*/
1329	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1330	RTThreadPreemptDisable(&PreemptState);
1331	RTCPUID const idCpu = RTMpCpuId();
1332
1333	/* Enable VT-x or AMD-V if local init is required. */
1334	int rc;
1335	if (!g_HmR0.fGlobalInit)
1336	{
1337	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1338	rc = hmR0EnableCpu(pVM, idCpu);
1339	if (RT_FAILURE(rc))
1340	{
1341	RTThreadPreemptRestore(&PreemptState);
1342	return rc;
1343	}
1344	}
1345
1346	/* Setup VT-x or AMD-V. */
1347	rc = g_HmR0.pfnSetupVM(pVM);
1348
1349	/* Disable VT-x or AMD-V if local init was done before. */
1350	if (!g_HmR0.fGlobalInit)
1351	{
1352	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1353	int rc2 = hmR0DisableCpu(idCpu);
1354	AssertRC(rc2);
1355	}
1356
1357	RTThreadPreemptRestore(&PreemptState);
1358	return rc;
1359	}
1360
1361
1362	/**
1363	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1364	* required for entering HM context.
1365	*
1366	* @returns VBox status code.
1367	* @param pVCpu The cross context virtual CPU structure.
1368	*
1369	* @remarks No-long-jump zone!!!
1370	*/
1371	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)
1372	{
1373	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1374
1375	int rc = VINF_SUCCESS;
1376	RTCPUID const idCpu = RTMpCpuId();
1377	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1378	AssertPtr(pHostCpu);
1379
1380	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1381	if (!pHostCpu->fConfigured)
1382	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1383
1384	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1385	if (g_HmR0.vmx.fSupported)
1386	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1387	else
1388	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1389
1390	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1391	pVCpu->hm.s.idEnteredCpu = idCpu;
1392	return rc;
1393	}
1394
1395
1396	/**
1397	* Enters the VT-x or AMD-V session.
1398	*
1399	* @returns VBox status code.
1400	* @param pVCpu The cross context virtual CPU structure.
1401	*
1402	* @remarks This is called with preemption disabled.
1403	*/
1404	VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)
1405	{
1406	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1407	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1408	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1409
1410	/* Load the bare minimum state required for entering HM. */
1411	int rc = hmR0EnterCpu(pVCpu);
1412	AssertRCReturn(rc, rc);
1413
1414	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1415	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1416	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1417	#endif
1418
1419	RTCPUID const idCpu = RTMpCpuId();
1420	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1421	Assert(pHostCpu);
1422	if (g_HmR0.vmx.fSupported)
1423	{
1424	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1425	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1426	}
1427	else
1428	{
1429	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1430	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1431	}
1432
1433	rc = g_HmR0.pfnEnterSession(pVCpu, pHostCpu);
1434	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1435
1436	/* Exports the host-state as we may be resuming code after a longjmp and quite
1437	possibly now be scheduled on a different CPU. */
1438	rc = g_HmR0.pfnExportHostState(pVCpu);
1439	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1440
1441	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1442	if (fStartedSet)
1443	PGMRZDynMapReleaseAutoSet(pVCpu);
1444	#endif
1445
1446	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1447	if (RT_FAILURE(rc))
1448	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1449	return rc;
1450	}
1451
1452
1453	/**
1454	* Deinitializes the bare minimum state used for HM context and if necessary
1455	* disable HM on the CPU.
1456	*
1457	* @returns VBox status code.
1458	* @param pVCpu The cross context virtual CPU structure.
1459	*
1460	* @remarks No-long-jump zone!!!
1461	*/
1462	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1463	{
1464	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1465	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1466
1467	RTCPUID const idCpu = RTMpCpuId();
1468	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1469
1470	if ( !g_HmR0.fGlobalInit
1471	&& pHostCpu->fConfigured)
1472	{
1473	int rc = hmR0DisableCpu(idCpu);
1474	AssertRCReturn(rc, rc);
1475	Assert(!pHostCpu->fConfigured);
1476	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1477
1478	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1479	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1480	}
1481
1482	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1483	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1484
1485	return VINF_SUCCESS;
1486	}
1487
1488
1489	/**
1490	* Thread-context hook for HM.
1491	*
1492	* @param enmEvent The thread-context event.
1493	* @param pvUser Opaque pointer to the VMCPU.
1494	*/
1495	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1496	{
1497	PVMCPU pVCpu = (PVMCPU)pvUser;
1498	Assert(pVCpu);
1499	Assert(g_HmR0.pfnThreadCtxCallback);
1500
1501	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1502	}
1503
1504
1505	/**
1506	* Runs guest code in a hardware accelerated VM.
1507	*
1508	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1509	* called from setjmp assembly.)
1510	* @param pVM The cross context VM structure.
1511	* @param pVCpu The cross context virtual CPU structure.
1512	*
1513	* @remarks Can be called with preemption enabled if thread-context hooks are
1514	* used!!!
1515	*/
1516	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1517	{
1518	RT_NOREF(pVM);
1519
1520	#ifdef VBOX_STRICT
1521	/* With thread-context hooks we would be running this code with preemption enabled. */
1522	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1523	{
1524	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1525	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1526	Assert(pHostCpu->fConfigured);
1527	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1528	}
1529	#endif
1530
1531	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1532	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1533	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1534	PGMRZDynMapStartAutoSet(pVCpu);
1535	#endif
1536
1537	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1538
1539	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1540	PGMRZDynMapReleaseAutoSet(pVCpu);
1541	#endif
1542	return VBOXSTRICTRC_VAL(rcStrict);
1543	}
1544
1545
1546	/**
1547	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1548	* the host CPU and that guest access to it must be intercepted.
1549	*
1550	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1551	*/
1552	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1553	{
1554	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1555	}
1556
1557
1558	/**
1559	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1560	*
1561	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1562	*/
1563	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1564	{
1565	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1566	}
1567
1568
1569	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1570
1571	/**
1572	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1573	*
1574	* @returns VBox status code.
1575	* @param pVM The cross context VM structure.
1576	* @param pVCpu The cross context virtual CPU structure.
1577	* @param pCtx Pointer to the guest CPU context.
1578	*/
1579	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1580	{
1581	RT_NOREF(pCtx);
1582	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1583	if (pVM->hm.s.vmx.fSupported)
1584	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1585	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1586	}
1587
1588
1589	/**
1590	* Save guest debug state (64 bits guest mode & 32 bits host only)
1591	*
1592	* @returns VBox status code.
1593	* @param pVM The cross context VM structure.
1594	* @param pVCpu The cross context virtual CPU structure.
1595	* @param pCtx Pointer to the guest CPU context.
1596	*/
1597	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1598	{
1599	RT_NOREF(pCtx);
1600	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1601	if (pVM->hm.s.vmx.fSupported)
1602	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1603	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1604	}
1605
1606
1607	/**
1608	* Test the 32->64 bits switcher.
1609	*
1610	* @returns VBox status code.
1611	* @param pVM The cross context VM structure.
1612	*/
1613	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1614	{
1615	PVMCPU pVCpu = &pVM->aCpus[0];
1616	uint32_t aParam[5] = { 0, 1, 2, 3, 4 };
1617	int rc;
1618
1619	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1620	if (pVM->hm.s.vmx.fSupported)
1621	rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1622	else
1623	rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1624	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1625
1626	return rc;
1627	}
1628
1629	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1630
1631	/**
1632	* Returns suspend status of the host.
1633	*
1634	* @returns Suspend pending or not.
1635	*/
1636	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1637	{
1638	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1639	}
1640
1641
1642	/**
1643	* Invalidates a guest page from the host TLB.
1644	*
1645	* @param pVCpu The cross context virtual CPU structure.
1646	* @param GCVirt Page to invalidate.
1647	*/
1648	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1649	{
1650	PVM pVM = pVCpu->CTX_SUFF(pVM);
1651	if (pVM->hm.s.vmx.fSupported)
1652	return VMXR0InvalidatePage(pVCpu, GCVirt);
1653	return SVMR0InvalidatePage(pVCpu, GCVirt);
1654	}
1655
1656
1657	/**
1658	* Returns the cpu structure for the current cpu.
1659	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1660	*
1661	* @returns The cpu structure pointer.
1662	*/
1663	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void)
1664	{
1665	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1666	RTCPUID const idCpu = RTMpCpuId();
1667	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1668	return &g_HmR0.aCpuInfo[idCpu];
1669	}
1670
1671
1672	/**
1673	* Interface for importing state on demand (used by IEM).
1674	*
1675	* @returns VBox status code.
1676	* @param pVCpu The cross context CPU structure.
1677	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1678	*/
1679	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
1680	{
1681	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1682	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1683	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1684	}
1685
1686
1687	#ifdef VBOX_WITH_RAW_MODE
1688	/**
1689	* Raw-mode switcher hook - disable VT-x if it's active and the current
1690	* switcher turns off paging.
1691	*
1692	* @returns VBox status code.
1693	* @param pVM The cross context VM structure.
1694	* @param enmSwitcher The switcher we're about to use.
1695	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1696	*/
1697	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1698	{
1699	NOREF(pVM);
1700
1701	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1702
1703	*pfVTxDisabled = false;
1704
1705	/* No such issues with AMD-V */
1706	if (!g_HmR0.vmx.fSupported)
1707	return VINF_SUCCESS;
1708
1709	/* Check if the switching we're up to is safe. */
1710	switch (enmSwitcher)
1711	{
1712	case VMMSWITCHER_32_TO_32:
1713	case VMMSWITCHER_PAE_TO_PAE:
1714	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1715
1716	case VMMSWITCHER_32_TO_PAE:
1717	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1718	case VMMSWITCHER_AMD64_TO_32:
1719	case VMMSWITCHER_AMD64_TO_PAE:
1720	break; /* unsafe switchers */
1721
1722	default:
1723	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1724	}
1725
1726	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1727	regardless of whether we're currently using VT-x or not. */
1728	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1729	{
1730	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1731	return VINF_SUCCESS;
1732	}
1733
1734	/** @todo Check if this code is presumptive wrt other VT-x users on the
1735	* system... */
1736
1737	/* Nothing to do if we haven't enabled VT-x. */
1738	if (!g_HmR0.fEnabled)
1739	return VINF_SUCCESS;
1740
1741	/* Local init implies the CPU is currently not in VMX root mode. */
1742	if (!g_HmR0.fGlobalInit)
1743	return VINF_SUCCESS;
1744
1745	/* Ok, disable VT-x. */
1746	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1747	AssertReturn( pHostCpu
1748	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1749	&& pHostCpu->pvMemObj
1750	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS,
1751	VERR_HM_IPE_2);
1752
1753	*pfVTxDisabled = true;
1754	return VMXR0DisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1755	}
1756
1757
1758	/**
1759	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1760	* switcher turned off paging.
1761	*
1762	* @param pVM The cross context VM structure.
1763	* @param fVTxDisabled Whether VT-x was disabled or not.
1764	*/
1765	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1766	{
1767	Assert(!ASMIntAreEnabled());
1768
1769	if (!fVTxDisabled)
1770	return; /* nothing to do */
1771
1772	Assert(g_HmR0.vmx.fSupported);
1773	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1774	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1775	else
1776	{
1777	Assert(g_HmR0.fEnabled);
1778	Assert(g_HmR0.fGlobalInit);
1779
1780	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1781	AssertReturnVoid( pHostCpu
1782	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1783	&& pHostCpu->pvMemObj
1784	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1785
1786	VMXR0EnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
1787	}
1788	}
1789	#endif /* VBOX_WITH_RAW_MODE */
1790
1791
1792	#ifdef VBOX_STRICT
1793	/**
1794	* Dumps a descriptor.
1795	*
1796	* @param pDesc Descriptor to dump.
1797	* @param Sel Selector number.
1798	* @param pszMsg Message to prepend the log entry with.
1799	*/
1800	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1801	{
1802	/*
1803	* Make variable description string.
1804	*/
1805	static struct
1806	{
1807	unsigned cch;
1808	const char *psz;
1809	} const s_aTypes[32] =
1810	{
1811	# define STRENTRY(str) { sizeof(str) - 1, str }
1812
1813	/* system */
1814	# if HC_ARCH_BITS == 64
1815	STRENTRY("Reserved0 "), /* 0x00 */
1816	STRENTRY("Reserved1 "), /* 0x01 */
1817	STRENTRY("LDT "), /* 0x02 */
1818	STRENTRY("Reserved3 "), /* 0x03 */
1819	STRENTRY("Reserved4 "), /* 0x04 */
1820	STRENTRY("Reserved5 "), /* 0x05 */
1821	STRENTRY("Reserved6 "), /* 0x06 */
1822	STRENTRY("Reserved7 "), /* 0x07 */
1823	STRENTRY("Reserved8 "), /* 0x08 */
1824	STRENTRY("TSS64Avail "), /* 0x09 */
1825	STRENTRY("ReservedA "), /* 0x0a */
1826	STRENTRY("TSS64Busy "), /* 0x0b */
1827	STRENTRY("Call64 "), /* 0x0c */
1828	STRENTRY("ReservedD "), /* 0x0d */
1829	STRENTRY("Int64 "), /* 0x0e */
1830	STRENTRY("Trap64 "), /* 0x0f */
1831	# else
1832	STRENTRY("Reserved0 "), /* 0x00 */
1833	STRENTRY("TSS16Avail "), /* 0x01 */
1834	STRENTRY("LDT "), /* 0x02 */
1835	STRENTRY("TSS16Busy "), /* 0x03 */
1836	STRENTRY("Call16 "), /* 0x04 */
1837	STRENTRY("Task "), /* 0x05 */
1838	STRENTRY("Int16 "), /* 0x06 */
1839	STRENTRY("Trap16 "), /* 0x07 */
1840	STRENTRY("Reserved8 "), /* 0x08 */
1841	STRENTRY("TSS32Avail "), /* 0x09 */
1842	STRENTRY("ReservedA "), /* 0x0a */
1843	STRENTRY("TSS32Busy "), /* 0x0b */
1844	STRENTRY("Call32 "), /* 0x0c */
1845	STRENTRY("ReservedD "), /* 0x0d */
1846	STRENTRY("Int32 "), /* 0x0e */
1847	STRENTRY("Trap32 "), /* 0x0f */
1848	# endif
1849	/* non system */
1850	STRENTRY("DataRO "), /* 0x10 */
1851	STRENTRY("DataRO Accessed "), /* 0x11 */
1852	STRENTRY("DataRW "), /* 0x12 */
1853	STRENTRY("DataRW Accessed "), /* 0x13 */
1854	STRENTRY("DataDownRO "), /* 0x14 */
1855	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1856	STRENTRY("DataDownRW "), /* 0x16 */
1857	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1858	STRENTRY("CodeEO "), /* 0x18 */
1859	STRENTRY("CodeEO Accessed "), /* 0x19 */
1860	STRENTRY("CodeER "), /* 0x1a */
1861	STRENTRY("CodeER Accessed "), /* 0x1b */
1862	STRENTRY("CodeConfEO "), /* 0x1c */
1863	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1864	STRENTRY("CodeConfER "), /* 0x1e */
1865	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1866	# undef SYSENTRY
1867	};
1868	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1869	char szMsg[128];
1870	char *psz = &szMsg[0];
1871	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1872	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1873	psz += s_aTypes[i].cch;
1874
1875	if (pDesc->Gen.u1Present)
1876	ADD_STR(psz, "Present ");
1877	else
1878	ADD_STR(psz, "Not-Present ");
1879	# if HC_ARCH_BITS == 64
1880	if (pDesc->Gen.u1Long)
1881	ADD_STR(psz, "64-bit ");
1882	else
1883	ADD_STR(psz, "Comp ");
1884	# else
1885	if (pDesc->Gen.u1Granularity)
1886	ADD_STR(psz, "Page ");
1887	if (pDesc->Gen.u1DefBig)
1888	ADD_STR(psz, "32-bit ");
1889	else
1890	ADD_STR(psz, "16-bit ");
1891	# endif
1892	# undef ADD_STR
1893	*psz = '\0';
1894
1895	/*
1896	* Limit and Base and format the output.
1897	*/
1898	#ifdef LOG_ENABLED
1899	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1900
1901	# if HC_ARCH_BITS == 64
1902	uint64_t u32Base = X86DESC64_BASE(pDesc);
1903	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1904	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1905	# else
1906	uint32_t u32Base = X86DESC_BASE(pDesc);
1907	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1908	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1909	# endif
1910	#else
1911	NOREF(Sel); NOREF(pszMsg);
1912	#endif
1913	}
1914
1915
1916	/**
1917	* Formats a full register dump.
1918	*
1919	* @param pVCpu The cross context virtual CPU structure.
1920	*/
1921	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu)
1922	{
1923	/*
1924	* Format the flags.
1925	*/
1926	static struct
1927	{
1928	const char pszSet; const char pszClear; uint32_t fFlag;
1929	} const s_aFlags[] =
1930	{
1931	{ "vip", NULL, X86_EFL_VIP },
1932	{ "vif", NULL, X86_EFL_VIF },
1933	{ "ac", NULL, X86_EFL_AC },
1934	{ "vm", NULL, X86_EFL_VM },
1935	{ "rf", NULL, X86_EFL_RF },
1936	{ "nt", NULL, X86_EFL_NT },
1937	{ "ov", "nv", X86_EFL_OF },
1938	{ "dn", "up", X86_EFL_DF },
1939	{ "ei", "di", X86_EFL_IF },
1940	{ "tf", NULL, X86_EFL_TF },
1941	{ "nt", "pl", X86_EFL_SF },
1942	{ "nz", "zr", X86_EFL_ZF },
1943	{ "ac", "na", X86_EFL_AF },
1944	{ "po", "pe", X86_EFL_PF },
1945	{ "cy", "nc", X86_EFL_CF },
1946	};
1947	char szEFlags[80];
1948	char *psz = szEFlags;
1949	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1950	uint32_t uEFlags = pCtx->eflags.u32;
1951	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1952	{
1953	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1954	if (pszAdd)
1955	{
1956	strcpy(psz, pszAdd);
1957	psz += strlen(pszAdd);
1958	*psz++ = ' ';
1959	}
1960	}
1961	psz[-1] = '\0';
1962
1963	/*
1964	* Format the registers.
1965	*/
1966	if (CPUMIsGuestIn64BitCode(pVCpu))
1967	{
1968	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1969	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1970	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1971	"r14=%016RX64 r15=%016RX64\n"
1972	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1973	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1974	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1975	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1976	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1977	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1978	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1979	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1980	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1981	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1982	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1983	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1984	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1985	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1986	,
1987	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1988	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1989	pCtx->r14, pCtx->r15,
1990	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1991	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1992	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1993	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1994	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1995	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1996	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1997	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1998	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1999	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2000	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2001	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2002	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2003	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2004	}
2005	else
2006	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2007	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2008	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2009	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2010	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2011	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2012	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2013	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2014	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2015	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2016	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2017	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2018	,
2019	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2020	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2021	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2022	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2023	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2024	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2025	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2026	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2027	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2028	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2029	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2030	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2031
2032	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2033	Log(("FPU:\n"
2034	"FCW=%04x FSW=%04x FTW=%02x\n"
2035	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2036	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2037	,
2038	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
2039	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
2040	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
2041	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
2042
2043	Log(("MSR:\n"
2044	"EFER =%016RX64\n"
2045	"PAT =%016RX64\n"
2046	"STAR =%016RX64\n"
2047	"CSTAR =%016RX64\n"
2048	"LSTAR =%016RX64\n"
2049	"SFMASK =%016RX64\n"
2050	"KERNELGSBASE =%016RX64\n",
2051	pCtx->msrEFER,
2052	pCtx->msrPAT,
2053	pCtx->msrSTAR,
2054	pCtx->msrCSTAR,
2055	pCtx->msrLSTAR,
2056	pCtx->msrSFMASK,
2057	pCtx->msrKERNELGSBASE));
2058
2059	NOREF(pFpuCtx);
2060	}
2061	#endif /* VBOX_STRICT */
2062

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 76232

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