HMR0.cpp@ 78220

Last change on this file since 78220 was 78220, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Hardware-assisted nested VT-x infrastructure changes and VM-entry implementation.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 71.2 KB

Line
1	/* $Id: HMR0.cpp 78220 2019-04-20 04:08:44Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/hmvmxinline.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMPHYSCPU aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPU pVCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
99	/** @} */
100
101	/** Hardware-virtualization data. */
102	struct
103	{
104	union
105	{
106	/** VT-x data. */
107	struct
108	{
109	/** Host CR4 value (set by ring-0 VMX init) */
110	uint64_t u64HostCr4;
111	/** Host EFER value (set by ring-0 VMX init) */
112	uint64_t u64HostMsrEfer;
113	/** Host SMM monitor control (used for logging/diagnostics) */
114	uint64_t u64HostSmmMonitorCtl;
115	/** Last instruction error. */
116	uint32_t ulLastInstrError;
117	/** The shift mask employed by the VMX-Preemption timer. */
118	uint8_t cPreemptTimerShift;
119	/** Padding. */
120	uint8_t abPadding[3];
121	/** Whether we're using the preemption timer or not. */
122	bool fUsePreemptTimer;
123	/** Whether we're using SUPR0EnableVTx or not. */
124	bool fUsingSUPR0EnableVTx;
125	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
126	* module termination. */
127	bool fCalledSUPR0EnableVTx;
128	/** Set to by us to indicate VMX is supported by the CPU. */
129	bool fSupported;
130	} vmx;
131
132	/** AMD-V data. */
133	struct
134	{
135	/** SVM revision. */
136	uint32_t u32Rev;
137	/** SVM feature bits from cpuid 0x8000000a */
138	uint32_t u32Features;
139	/** Padding. */
140	bool afPadding[3];
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	} u;
145	/** Maximum allowed ASID/VPID (inclusive). */
146	uint32_t uMaxAsid;
147	/** MSRs. */
148	SUPHWVIRTMSRS Msrs;
149	} hwvirt;
150
151	/** Last recorded error code during HM ring-0 init. */
152	int32_t rcInit;
153
154	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
155	* enabled and disabled each time it's used to execute guest code. */
156	bool fGlobalInit;
157	/** Indicates whether the host is suspending or not. We'll refuse a few
158	* actions when the host is being suspended to speed up the suspending and
159	* avoid trouble. */
160	bool volatile fSuspended;
161
162	/** Whether we've already initialized all CPUs.
163	* @remarks We could check the EnableAllCpusOnce state, but this is
164	* simpler and hopefully easier to understand. */
165	bool fEnabled;
166	/** Serialize initialization in HMR0EnableAllCpus. */
167	RTONCE EnableAllCpusOnce;
168	} g_HmR0;
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	# ifndef DEBUG_bird
212	/**
213	* Get the CPU ID on which the failure status code was reported.
214	*
215	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
216	* @param pFirstRc The first return code structure.
217	*/
218	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->idCpu;
221	}
222	# endif
223	#endif /* VBOX_STRICT */
224
225
226	/** @name Dummy callback handlers.
227	* @{ */
228
229	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu)
230	{
231	RT_NOREF1(pVCpu);
232	return VINF_SUCCESS;
233	}
234
235	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
236	{
237	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
238	}
239
240	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
241	bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
242	{
243	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
244	return VINF_SUCCESS;
245	}
246
247	static DECLCALLBACK(int) hmR0DummyDisableCpu(void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
248	{
249	RT_NOREF2(pvCpuPage, HCPhysCpuPage);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
254	{
255	RT_NOREF1(pVM);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
260	{
261	RT_NOREF1(pVM);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
266	{
267	RT_NOREF1(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu)
272	{
273	RT_NOREF(pVCpu);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)
278	{
279	RT_NOREF1(pVCpu);
280	return VINF_SUCCESS;
281	}
282
283	/** @} */
284
285
286	/**
287	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
288	* Down at the Rate Specified" erratum.
289	*
290	* Errata names and related steppings:
291	* - BA86 - D0.
292	* - AAX65 - C2.
293	* - AAU65 - C2, K0.
294	* - AAO95 - B1.
295	* - AAT59 - C2.
296	* - AAK139 - D0.
297	* - AAM126 - C0, C1, D0.
298	* - AAN92 - B1.
299	* - AAJ124 - C0, D0.
300	* - AAP86 - B1.
301	*
302	* Steppings: B1, C0, C1, C2, D0, K0.
303	*
304	* @returns true if subject to it, false if not.
305	*/
306	static bool hmR0InitIntelIsSubjectToVmxPreemptTimerErratum(void)
307	{
308	uint32_t u = ASMCpuId_EAX(1);
309	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
310	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
311	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
312	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
313	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
315	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
316	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
317	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
318	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
321	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
322	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
323	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
324	)
325	return true;
326	return false;
327	}
328
329
330	/**
331	* Intel specific initialization code.
332	*
333	* @returns VBox status code (will only fail if out of memory).
334	*/
335	static int hmR0InitIntel(void)
336	{
337	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
338	g_HmR0.hwvirt.Msrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
339
340	/*
341	* First try use native kernel API for controlling VT-x.
342	* (This is only supported by some Mac OS X kernels atm.)
343	*/
344	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
345	g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
346	if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
347	{
348	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
349	if (RT_SUCCESS(rc))
350	{
351	g_HmR0.hwvirt.u.vmx.fSupported = true;
352	rc = SUPR0EnableVTx(false /* fEnable */);
353	AssertLogRelRC(rc);
354	}
355	}
356	else
357	{
358	HMR0FIRSTRC FirstRc;
359	hmR0FirstRcInit(&FirstRc);
360	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
361	if (RT_SUCCESS(g_HmR0.rcInit))
362	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
363	}
364
365	if (RT_SUCCESS(g_HmR0.rcInit))
366	{
367	/* Read CR4 and EFER for logging/diagnostic purposes. */
368	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
369	g_HmR0.hwvirt.u.vmx.u64HostMsrEfer = ASMRdMsr(MSR_K6_EFER);
370
371	/* Get VMX MSRs for determining VMX features we can ultimately use. */
372	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_VT_X, false /* fForce */);
373
374	/*
375	* Nested KVM workaround: Intel SDM section 34.15.5 describes that
376	* MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
377	* table 35-2 says that this MSR is available if either VMX or SMX is supported.
378	*/
379	uint64_t const uVmxBasicMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Basic;
380	if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
381	g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
382
383	/* Initialize VPID - 16 bits ASID. */
384	g_HmR0.hwvirt.uMaxAsid = 0x10000; /* exclusive */
385
386	/*
387	* If the host OS has not enabled VT-x for us, try enter VMX root mode
388	* to really verify if VT-x is usable.
389	*/
390	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
391	{
392	/* Allocate a temporary VMXON region. */
393	RTR0MEMOBJ hScatchMemObj;
394	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
395	if (RT_FAILURE(rc))
396	{
397	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
398	return rc;
399	}
400	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
401	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
402	ASMMemZeroPage(pvScatchPage);
403
404	/* Set revision dword at the beginning of the VMXON structure. */
405	(uint32_t )pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
406
407	/* Make sure we don't get rescheduled to another CPU during this probe. */
408	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
409
410	/* Check CR4.VMXE. */
411	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
412	if (!(g_HmR0.hwvirt.u.vmx.u64HostCr4 & X86_CR4_VMXE))
413	{
414	/* In theory this bit could be cleared behind our back. Which would cause #UD
415	faults when we try to execute the VMX instructions... */
416	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4 \| X86_CR4_VMXE);
417	}
418
419	/*
420	* The only way of checking if we're in VMX root mode or not is to try and enter it.
421	* There is no instruction or control bit that tells us if we're in VMX root mode.
422	* Therefore, try and enter VMX root mode here.
423	*/
424	rc = VMXEnable(HCPhysScratchPage);
425	if (RT_SUCCESS(rc))
426	{
427	g_HmR0.hwvirt.u.vmx.fSupported = true;
428	VMXDisable();
429	}
430	else
431	{
432	/*
433	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
434	* it will crash the host when we enter raw mode, because:
435	*
436	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
437	* this bit), and
438	* (b) turning off paging causes a #GP (unavoidable when switching
439	* from long to 32 bits mode or 32 bits to PAE).
440	*
441	* They should fix their code, but until they do we simply refuse to run.
442	*/
443	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
444	Assert(g_HmR0.hwvirt.u.vmx.fSupported == false);
445	}
446
447	/*
448	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
449	* set before (some software could incorrectly think it is in VMX mode).
450	*/
451	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4);
452	ASMSetFlags(fEFlags);
453
454	RTR0MemObjFree(hScatchMemObj, false);
455	}
456
457	if (g_HmR0.hwvirt.u.vmx.fSupported)
458	{
459	rc = VMXR0GlobalInit();
460	if (RT_FAILURE(rc))
461	g_HmR0.rcInit = rc;
462
463	/*
464	* Install the VT-x methods.
465	*/
466	g_HmR0.pfnEnterSession = VMXR0Enter;
467	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
468	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
469	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
470	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
471	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
472	g_HmR0.pfnInitVM = VMXR0InitVM;
473	g_HmR0.pfnTermVM = VMXR0TermVM;
474	g_HmR0.pfnSetupVM = VMXR0SetupVM;
475
476	/*
477	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
478	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
479	*/
480	uint32_t const fPinCtls = RT_HI_U32(g_HmR0.hwvirt.Msrs.u.vmx.u64PinCtls);
481	if (fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
482	{
483	uint64_t const uVmxMiscMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Misc;
484	g_HmR0.hwvirt.u.vmx.fUsePreemptTimer = true;
485	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = RT_BF_GET(uVmxMiscMsr, VMX_BF_MISC_PREEMPT_TIMER_TSC);
486	if (hmR0InitIntelIsSubjectToVmxPreemptTimerErratum())
487	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
488	}
489	}
490	}
491	#ifdef LOG_ENABLED
492	else
493	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
494	#endif
495	return VINF_SUCCESS;
496	}
497
498
499	/**
500	* AMD-specific initialization code.
501	*
502	* @returns VBox status code (will only fail if out of memory).
503	*/
504	static int hmR0InitAmd(void)
505	{
506	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
507	int rc = SVMR0GlobalInit();
508	if (RT_FAILURE(rc))
509	{
510	g_HmR0.rcInit = rc;
511	return rc;
512	}
513
514	/*
515	* Install the AMD-V methods.
516	*/
517	g_HmR0.pfnEnterSession = SVMR0Enter;
518	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
519	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
520	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
521	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
522	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
523	g_HmR0.pfnInitVM = SVMR0InitVM;
524	g_HmR0.pfnTermVM = SVMR0TermVM;
525	g_HmR0.pfnSetupVM = SVMR0SetupVM;
526
527	/* Query AMD features. */
528	uint32_t u32Dummy;
529	ASMCpuId(0x8000000a, &g_HmR0.hwvirt.u.svm.u32Rev, &g_HmR0.hwvirt.uMaxAsid, &u32Dummy, &g_HmR0.hwvirt.u.svm.u32Features);
530
531	/*
532	* We need to check if AMD-V has been properly initialized on all CPUs.
533	* Some BIOSes might do a poor job.
534	*/
535	HMR0FIRSTRC FirstRc;
536	hmR0FirstRcInit(&FirstRc);
537	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
538	AssertRC(rc);
539	if (RT_SUCCESS(rc))
540	rc = hmR0FirstRcGetStatus(&FirstRc);
541	#ifndef DEBUG_bird
542	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
543	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
544	#endif
545	if (RT_SUCCESS(rc))
546	{
547	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_AMD_V, false /* fForce */);
548	g_HmR0.hwvirt.u.svm.fSupported = true;
549	}
550	else
551	{
552	g_HmR0.rcInit = rc;
553	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
554	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
555	}
556	return rc;
557	}
558
559
560	/**
561	* Does global Ring-0 HM initialization (at module init).
562	*
563	* @returns VBox status code.
564	*/
565	VMMR0_INT_DECL(int) HMR0Init(void)
566	{
567	/*
568	* Initialize the globals.
569	*/
570	g_HmR0.fEnabled = false;
571	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
572	g_HmR0.EnableAllCpusOnce = s_OnceInit;
573	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
574	{
575	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
576	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
577	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
578	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
579	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
580	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
581	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
582	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
583	#endif
584	}
585
586	/* Fill in all callbacks with placeholders. */
587	g_HmR0.pfnEnterSession = hmR0DummyEnter;
588	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
589	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
590	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
591	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
592	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
593	g_HmR0.pfnInitVM = hmR0DummyInitVM;
594	g_HmR0.pfnTermVM = hmR0DummyTermVM;
595	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
596
597	/* Default is global VT-x/AMD-V init. */
598	g_HmR0.fGlobalInit = true;
599
600	/*
601	* Make sure aCpuInfo is big enough for all the CPUs on this system.
602	*/
603	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
604	{
605	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
606	return VERR_TOO_MANY_CPUS;
607	}
608
609	/*
610	* Check for VT-x or AMD-V support.
611	* Return failure only in out-of-memory situations.
612	*/
613	uint32_t fCaps = 0;
614	int rc = SUPR0GetVTSupport(&fCaps);
615	if (RT_SUCCESS(rc))
616	{
617	if (fCaps & SUPVTCAPS_VT_X)
618	{
619	rc = hmR0InitIntel();
620	if (RT_FAILURE(rc))
621	return rc;
622	}
623	else
624	{
625	Assert(fCaps & SUPVTCAPS_AMD_V);
626	rc = hmR0InitAmd();
627	if (RT_FAILURE(rc))
628	return rc;
629	}
630	}
631	else
632	g_HmR0.rcInit = VERR_UNSUPPORTED_CPU;
633
634	/*
635	* Register notification callbacks that we can use to disable/enable CPUs
636	* when brought offline/online or suspending/resuming.
637	*/
638	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
639	{
640	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
641	AssertRC(rc);
642
643	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
644	AssertRC(rc);
645	}
646
647	/* We return success here because module init shall not fail if HM fails to initialize. */
648	return VINF_SUCCESS;
649	}
650
651
652	/**
653	* Does global Ring-0 HM termination (at module termination).
654	*
655	* @returns VBox status code.
656	*/
657	VMMR0_INT_DECL(int) HMR0Term(void)
658	{
659	int rc;
660	if ( g_HmR0.hwvirt.u.vmx.fSupported
661	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
662	{
663	/*
664	* Simple if the host OS manages VT-x.
665	*/
666	Assert(g_HmR0.fGlobalInit);
667
668	if (g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx)
669	{
670	rc = SUPR0EnableVTx(false /* fEnable */);
671	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = false;
672	}
673	else
674	rc = VINF_SUCCESS;
675
676	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
677	{
678	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
679	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
680	}
681	}
682	else
683	{
684	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
685
686	/* Doesn't really matter if this fails. */
687	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
688	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
689
690	/*
691	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
692	*/
693	if (g_HmR0.fGlobalInit)
694	{
695	HMR0FIRSTRC FirstRc;
696	hmR0FirstRcInit(&FirstRc);
697	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
698	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
699	if (RT_SUCCESS(rc))
700	rc = hmR0FirstRcGetStatus(&FirstRc);
701	}
702
703	/*
704	* Free the per-cpu pages used for VT-x and AMD-V.
705	*/
706	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
707	{
708	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
709	{
710	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
711	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
712	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
713	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
714	}
715	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
716	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
717	{
718	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
719	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
720	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
721	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
722	}
723	#endif
724	}
725	}
726
727	/** @todo This needs cleaning up. There's no matching
728	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
729	* should move into their respective modules. */
730	/* Finally, call global VT-x/AMD-V termination. */
731	if (g_HmR0.hwvirt.u.vmx.fSupported)
732	VMXR0GlobalTerm();
733	else if (g_HmR0.hwvirt.u.svm.fSupported)
734	SVMR0GlobalTerm();
735
736	return rc;
737	}
738
739
740	/**
741	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
742	* on a CPU.
743	*
744	* @param idCpu The identifier for the CPU the function is called on.
745	* @param pvUser1 Pointer to the first RC structure.
746	* @param pvUser2 Ignored.
747	*/
748	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
749	{
750	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
751	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
752	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
753	NOREF(idCpu); NOREF(pvUser2);
754
755	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
756	hmR0FirstRcSetStatus(pFirstRc, rc);
757	}
758
759
760	/**
761	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
762	* on a CPU.
763	*
764	* @param idCpu The identifier for the CPU the function is called on.
765	* @param pvUser1 Pointer to the first RC structure.
766	* @param pvUser2 Ignored.
767	*/
768	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
769	{
770	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
771	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
772	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
773	NOREF(idCpu); NOREF(pvUser2);
774
775	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
776	hmR0FirstRcSetStatus(pFirstRc, rc);
777	}
778
779
780	/**
781	* Enable VT-x or AMD-V on the current CPU
782	*
783	* @returns VBox status code.
784	* @param pVM The cross context VM structure. Can be NULL.
785	* @param idCpu The identifier for the CPU the function is called on.
786	*
787	* @remarks Maybe called with interrupts disabled!
788	*/
789	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
790	{
791	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
792
793	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
794	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
795	Assert(!pHostCpu->fConfigured);
796	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
797
798	pHostCpu->idCpu = idCpu;
799	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
800
801	int rc;
802	if ( g_HmR0.hwvirt.u.vmx.fSupported
803	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
804	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.hwvirt.Msrs);
805	else
806	{
807	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
808	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.hwvirt.Msrs);
809	}
810	if (RT_SUCCESS(rc))
811	pHostCpu->fConfigured = true;
812	return rc;
813	}
814
815
816	/**
817	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
818	*
819	* @param idCpu The identifier for the CPU the function is called on.
820	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
821	* @param pvUser2 The 2nd user argument.
822	*/
823	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
824	{
825	PVM pVM = (PVM)pvUser1; /* can be NULL! */
826	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
827	AssertReturnVoid(g_HmR0.fGlobalInit);
828	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
829	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
830	}
831
832
833	/**
834	* RTOnce callback employed by HMR0EnableAllCpus.
835	*
836	* @returns VBox status code.
837	* @param pvUser Pointer to the VM.
838	*/
839	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
840	{
841	PVM pVM = (PVM)pvUser;
842
843	/*
844	* Indicate that we've initialized.
845	*
846	* Note! There is a potential race between this function and the suspend
847	* notification. Kind of unlikely though, so ignored for now.
848	*/
849	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
850	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
851
852	/*
853	* The global init variable is set by the first VM.
854	*/
855	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
856
857	#ifdef VBOX_STRICT
858	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
859	{
860	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
861	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
862	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
863	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
864	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
865	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
866	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
867	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
868	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
869	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
870	# endif
871	}
872	#endif
873
874	int rc;
875	if ( g_HmR0.hwvirt.u.vmx.fSupported
876	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
877	{
878	/*
879	* Global VT-x initialization API (only darwin for now).
880	*/
881	rc = SUPR0EnableVTx(true /* fEnable */);
882	if (RT_SUCCESS(rc))
883	{
884	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = true;
885	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
886	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
887	}
888	else
889	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
890	}
891	else
892	{
893	/*
894	* We're doing the job ourselves.
895	*/
896	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
897	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
898	{
899	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
900	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
901	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
902	#endif
903	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
904	{
905	/** @todo NUMA */
906	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
907	AssertLogRelRCReturn(rc, rc);
908
909	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
910	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
911	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
912
913	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
914	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
915	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
916
917	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
918	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
919	false /* executable R0 mapping */);
920	AssertLogRelRCReturn(rc, rc);
921
922	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
923	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
924	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
925
926	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
927	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
928	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
929	#endif
930	}
931	}
932
933	rc = VINF_SUCCESS;
934	}
935
936	if ( RT_SUCCESS(rc)
937	&& g_HmR0.fGlobalInit)
938	{
939	/* First time, so initialize each cpu/core. */
940	HMR0FIRSTRC FirstRc;
941	hmR0FirstRcInit(&FirstRc);
942	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
943	if (RT_SUCCESS(rc))
944	rc = hmR0FirstRcGetStatus(&FirstRc);
945	}
946
947	return rc;
948	}
949
950
951	/**
952	* Sets up HM on all cpus.
953	*
954	* @returns VBox status code.
955	* @param pVM The cross context VM structure.
956	*/
957	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
958	{
959	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
960	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
961	return VERR_HM_SUSPEND_PENDING;
962
963	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
964	}
965
966
967	/**
968	* Disable VT-x or AMD-V on the current CPU.
969	*
970	* @returns VBox status code.
971	* @param idCpu The identifier for the CPU this function is called on.
972	*
973	* @remarks Must be called with preemption disabled.
974	*/
975	static int hmR0DisableCpu(RTCPUID idCpu)
976	{
977	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
978
979	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
980	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
981	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
982	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
983	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
984	AssertRelease(idCpu == RTMpCpuId());
985
986	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
987	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
988	AssertPtr(pHostCpu->pvMemObj);
989	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
990
991	int rc;
992	if (pHostCpu->fConfigured)
993	{
994	rc = g_HmR0.pfnDisableCpu(pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
995	AssertRCReturn(rc, rc);
996
997	pHostCpu->fConfigured = false;
998	pHostCpu->idCpu = NIL_RTCPUID;
999	}
1000	else
1001	rc = VINF_SUCCESS; /* nothing to do */
1002	return rc;
1003	}
1004
1005
1006	/**
1007	* Worker function passed to RTMpOnAll() that is to be called on the target
1008	* CPUs.
1009	*
1010	* @param idCpu The identifier for the CPU the function is called on.
1011	* @param pvUser1 The 1st user argument.
1012	* @param pvUser2 Opaque pointer to the FirstRc.
1013	*/
1014	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1015	{
1016	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1017	AssertReturnVoid(g_HmR0.fGlobalInit);
1018	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1019	}
1020
1021
1022	/**
1023	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1024	* CPU.
1025	*
1026	* @param idCpu The identifier for the CPU the function is called on.
1027	* @param pvUser1 Null, not used.
1028	* @param pvUser2 Null, not used.
1029	*/
1030	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1031	{
1032	NOREF(pvUser1);
1033	NOREF(pvUser2);
1034	hmR0DisableCpu(idCpu);
1035	}
1036
1037
1038	/**
1039	* Callback function invoked when a cpu goes online or offline.
1040	*
1041	* @param enmEvent The Mp event.
1042	* @param idCpu The identifier for the CPU the function is called on.
1043	* @param pvData Opaque data (PVM pointer).
1044	*/
1045	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1046	{
1047	NOREF(pvData);
1048	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1049
1050	/*
1051	* We only care about uninitializing a CPU that is going offline. When a
1052	* CPU comes online, the initialization is done lazily in HMR0Enter().
1053	*/
1054	switch (enmEvent)
1055	{
1056	case RTMPEVENT_OFFLINE:
1057	{
1058	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1059	RTThreadPreemptDisable(&PreemptState);
1060	if (idCpu == RTMpCpuId())
1061	{
1062	int rc = hmR0DisableCpu(idCpu);
1063	AssertRC(rc);
1064	RTThreadPreemptRestore(&PreemptState);
1065	}
1066	else
1067	{
1068	RTThreadPreemptRestore(&PreemptState);
1069	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1070	}
1071	break;
1072	}
1073
1074	default:
1075	break;
1076	}
1077	}
1078
1079
1080	/**
1081	* Called whenever a system power state change occurs.
1082	*
1083	* @param enmEvent The Power event.
1084	* @param pvUser User argument.
1085	*/
1086	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1087	{
1088	NOREF(pvUser);
1089	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1090
1091	#ifdef LOG_ENABLED
1092	if (enmEvent == RTPOWEREVENT_SUSPEND)
1093	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1094	else
1095	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1096	#endif
1097
1098	if (enmEvent == RTPOWEREVENT_SUSPEND)
1099	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1100
1101	if (g_HmR0.fEnabled)
1102	{
1103	int rc;
1104	HMR0FIRSTRC FirstRc;
1105	hmR0FirstRcInit(&FirstRc);
1106
1107	if (enmEvent == RTPOWEREVENT_SUSPEND)
1108	{
1109	if (g_HmR0.fGlobalInit)
1110	{
1111	/* Turn off VT-x or AMD-V on all CPUs. */
1112	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1113	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1114	}
1115	/* else nothing to do here for the local init case */
1116	}
1117	else
1118	{
1119	/* Reinit the CPUs from scratch as the suspend state might have
1120	messed with the MSRs. (lousy BIOSes as usual) */
1121	if (g_HmR0.hwvirt.u.vmx.fSupported)
1122	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1123	else
1124	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1125	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1126	if (RT_SUCCESS(rc))
1127	rc = hmR0FirstRcGetStatus(&FirstRc);
1128	#ifdef LOG_ENABLED
1129	if (RT_FAILURE(rc))
1130	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1131	#endif
1132	if (g_HmR0.fGlobalInit)
1133	{
1134	/* Turn VT-x or AMD-V back on on all CPUs. */
1135	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1136	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1137	}
1138	/* else nothing to do here for the local init case */
1139	}
1140	}
1141
1142	if (enmEvent == RTPOWEREVENT_RESUME)
1143	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1144	}
1145
1146
1147	/**
1148	* Does ring-0 per-VM HM initialization.
1149	*
1150	* This will call the CPU specific init. routine which may initialize and allocate
1151	* resources for virtual CPUs.
1152	*
1153	* @returns VBox status code.
1154	* @param pVM The cross context VM structure.
1155	*
1156	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1157	* vmR3InitRing3().
1158	*/
1159	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1160	{
1161	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1162
1163	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1164	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1165	return VERR_HM_SUSPEND_PENDING;
1166
1167	/*
1168	* Copy globals to the VM structure.
1169	*/
1170	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1171	if (pVM->hm.s.vmx.fSupported)
1172	{
1173	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.hwvirt.u.vmx.fUsePreemptTimer; /* Can be overridden by CFGM see HMR3Init(). */
1174	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.hwvirt.u.vmx.cPreemptTimerShift;
1175	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.hwvirt.u.vmx.u64HostCr4;
1176	pVM->hm.s.vmx.u64HostMsrEfer = g_HmR0.hwvirt.u.vmx.u64HostMsrEfer;
1177	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl;
1178	HMGetVmxMsrsFromHwvirtMsrs(&g_HmR0.hwvirt.Msrs, &pVM->hm.s.vmx.Msrs);
1179	}
1180	else if (pVM->hm.s.svm.fSupported)
1181	{
1182	pVM->hm.s.svm.u32Rev = g_HmR0.hwvirt.u.svm.u32Rev;
1183	pVM->hm.s.svm.u32Features = g_HmR0.hwvirt.u.svm.u32Features;
1184	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.hwvirt.Msrs.u.svm.u64MsrHwcr;
1185	}
1186	pVM->hm.s.rcInit = g_HmR0.rcInit;
1187	pVM->hm.s.uMaxAsid = g_HmR0.hwvirt.uMaxAsid;
1188
1189	/*
1190	* Set default maximum inner loops in ring-0 before returning to ring-3.
1191	* Can be overriden using CFGM.
1192	*/
1193	if (!pVM->hm.s.cMaxResumeLoops)
1194	{
1195	pVM->hm.s.cMaxResumeLoops = 1024;
1196	if (RTThreadPreemptIsPendingTrusty())
1197	pVM->hm.s.cMaxResumeLoops = 8192;
1198	}
1199
1200	/*
1201	* Initialize some per-VCPU fields.
1202	*/
1203	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1204	{
1205	PVMCPU pVCpu = &pVM->aCpus[i];
1206	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1207	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1208
1209	/* We'll aways increment this the first time (host uses ASID 0). */
1210	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1211	}
1212
1213	/*
1214	* Get host kernel features that HM might need to know in order
1215	* to co-operate and function properly with the host OS (e.g. SMAP).
1216	*
1217	* Technically, we could do this as part of the pre-init VM procedure
1218	* but it shouldn't be done later than this point so we do it here.
1219	*/
1220	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1221
1222	/*
1223	* Call the hardware specific initialization method.
1224	*/
1225	return g_HmR0.pfnInitVM(pVM);
1226	}
1227
1228
1229	/**
1230	* Does ring-0 per VM HM termination.
1231	*
1232	* @returns VBox status code.
1233	* @param pVM The cross context VM structure.
1234	*/
1235	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1236	{
1237	Log(("HMR0TermVM: %p\n", pVM));
1238	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1239
1240	/*
1241	* Call the hardware specific method.
1242	*
1243	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1244	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1245	*/
1246	return g_HmR0.pfnTermVM(pVM);
1247	}
1248
1249
1250	/**
1251	* Sets up a VT-x or AMD-V session.
1252	*
1253	* This is mostly about setting up the hardware VM state.
1254	*
1255	* @returns VBox status code.
1256	* @param pVM The cross context VM structure.
1257	*/
1258	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1259	{
1260	Log(("HMR0SetupVM: %p\n", pVM));
1261	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1262
1263	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1264	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1265
1266	/* On first entry we'll sync everything. */
1267	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1268	{
1269	PVMCPU pVCpu = &pVM->aCpus[i];
1270	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1271	}
1272
1273	/*
1274	* Call the hardware specific setup VM method. This requires the CPU to be
1275	* enabled for AMD-V/VT-x and preemption to be prevented.
1276	*/
1277	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1278	RTThreadPreemptDisable(&PreemptState);
1279	RTCPUID const idCpu = RTMpCpuId();
1280
1281	/* Enable VT-x or AMD-V if local init is required. */
1282	int rc;
1283	if (!g_HmR0.fGlobalInit)
1284	{
1285	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1286	rc = hmR0EnableCpu(pVM, idCpu);
1287	if (RT_FAILURE(rc))
1288	{
1289	RTThreadPreemptRestore(&PreemptState);
1290	return rc;
1291	}
1292	}
1293
1294	/* Setup VT-x or AMD-V. */
1295	rc = g_HmR0.pfnSetupVM(pVM);
1296
1297	/* Disable VT-x or AMD-V if local init was done before. */
1298	if (!g_HmR0.fGlobalInit)
1299	{
1300	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1301	int rc2 = hmR0DisableCpu(idCpu);
1302	AssertRC(rc2);
1303	}
1304
1305	RTThreadPreemptRestore(&PreemptState);
1306	return rc;
1307	}
1308
1309
1310	/**
1311	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1312	* required for entering HM context.
1313	*
1314	* @returns VBox status code.
1315	* @param pVCpu The cross context virtual CPU structure.
1316	*
1317	* @remarks No-long-jump zone!!!
1318	*/
1319	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)
1320	{
1321	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1322
1323	int rc = VINF_SUCCESS;
1324	RTCPUID const idCpu = RTMpCpuId();
1325	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1326	AssertPtr(pHostCpu);
1327
1328	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1329	if (!pHostCpu->fConfigured)
1330	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1331
1332	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1333	if (g_HmR0.hwvirt.u.vmx.fSupported)
1334	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1335	else
1336	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1337
1338	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1339	pVCpu->hm.s.idEnteredCpu = idCpu;
1340	return rc;
1341	}
1342
1343
1344	/**
1345	* Enters the VT-x or AMD-V session.
1346	*
1347	* @returns VBox status code.
1348	* @param pVCpu The cross context virtual CPU structure.
1349	*
1350	* @remarks This is called with preemption disabled.
1351	*/
1352	VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)
1353	{
1354	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1355	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1356	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1357
1358	/* Load the bare minimum state required for entering HM. */
1359	int rc = hmR0EnterCpu(pVCpu);
1360	if (RT_SUCCESS(rc))
1361	{
1362	if (g_HmR0.hwvirt.u.vmx.fSupported)
1363	{
1364	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1365	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1366	}
1367	else
1368	{
1369	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1370	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1371	}
1372
1373	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1374	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1375	bool const fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1376	#endif
1377
1378	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1379	rc = g_HmR0.pfnEnterSession(pVCpu);
1380	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1381
1382	/* Exports the host-state as we may be resuming code after a longjmp and quite
1383	possibly now be scheduled on a different CPU. */
1384	rc = g_HmR0.pfnExportHostState(pVCpu);
1385	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1386
1387	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1388	if (fStartedSet)
1389	PGMRZDynMapReleaseAutoSet(pVCpu);
1390	#endif
1391	}
1392	return rc;
1393	}
1394
1395
1396	/**
1397	* Deinitializes the bare minimum state used for HM context and if necessary
1398	* disable HM on the CPU.
1399	*
1400	* @returns VBox status code.
1401	* @param pVCpu The cross context virtual CPU structure.
1402	*
1403	* @remarks No-long-jump zone!!!
1404	*/
1405	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1406	{
1407	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1408	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1409
1410	RTCPUID const idCpu = RTMpCpuId();
1411	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1412
1413	if ( !g_HmR0.fGlobalInit
1414	&& pHostCpu->fConfigured)
1415	{
1416	int rc = hmR0DisableCpu(idCpu);
1417	AssertRCReturn(rc, rc);
1418	Assert(!pHostCpu->fConfigured);
1419	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1420
1421	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1422	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1423	}
1424
1425	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1426	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1427
1428	return VINF_SUCCESS;
1429	}
1430
1431
1432	/**
1433	* Thread-context hook for HM.
1434	*
1435	* @param enmEvent The thread-context event.
1436	* @param pvUser Opaque pointer to the VMCPU.
1437	*/
1438	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1439	{
1440	PVMCPU pVCpu = (PVMCPU)pvUser;
1441	Assert(pVCpu);
1442	Assert(g_HmR0.pfnThreadCtxCallback);
1443
1444	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1445	}
1446
1447
1448	/**
1449	* Runs guest code in a hardware accelerated VM.
1450	*
1451	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1452	* called from setjmp assembly.)
1453	* @param pVM The cross context VM structure.
1454	* @param pVCpu The cross context virtual CPU structure.
1455	*
1456	* @remarks Can be called with preemption enabled if thread-context hooks are
1457	* used!!!
1458	*/
1459	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1460	{
1461	RT_NOREF(pVM);
1462
1463	#ifdef VBOX_STRICT
1464	/* With thread-context hooks we would be running this code with preemption enabled. */
1465	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1466	{
1467	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1468	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1469	Assert(pHostCpu->fConfigured);
1470	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1471	}
1472	#endif
1473
1474	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1475	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1476	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1477	PGMRZDynMapStartAutoSet(pVCpu);
1478	#endif
1479
1480	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1481
1482	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1483	PGMRZDynMapReleaseAutoSet(pVCpu);
1484	#endif
1485	return VBOXSTRICTRC_VAL(rcStrict);
1486	}
1487
1488
1489	/**
1490	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1491	* the host CPU and that guest access to it must be intercepted.
1492	*
1493	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1494	*/
1495	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1496	{
1497	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1498	}
1499
1500
1501	/**
1502	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1503	*
1504	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1505	*/
1506	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1507	{
1508	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1509	}
1510
1511
1512	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1513
1514	/**
1515	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1516	*
1517	* @returns VBox status code.
1518	* @param pVM The cross context VM structure.
1519	* @param pVCpu The cross context virtual CPU structure.
1520	* @param pCtx Pointer to the guest CPU context.
1521	*/
1522	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1523	{
1524	RT_NOREF(pCtx);
1525	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1526	if (pVM->hm.s.vmx.fSupported)
1527	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1528	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1529	}
1530
1531
1532	/**
1533	* Save guest debug state (64 bits guest mode & 32 bits host only)
1534	*
1535	* @returns VBox status code.
1536	* @param pVM The cross context VM structure.
1537	* @param pVCpu The cross context virtual CPU structure.
1538	* @param pCtx Pointer to the guest CPU context.
1539	*/
1540	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1541	{
1542	RT_NOREF(pCtx);
1543	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1544	if (pVM->hm.s.vmx.fSupported)
1545	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1546	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1547	}
1548
1549
1550	/**
1551	* Test the 32->64 bits switcher.
1552	*
1553	* @returns VBox status code.
1554	* @param pVM The cross context VM structure.
1555	*/
1556	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1557	{
1558	PVMCPU pVCpu = &pVM->aCpus[0];
1559	uint32_t aParam[5] = { 0, 1, 2, 3, 4 };
1560	int rc;
1561
1562	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1563	if (pVM->hm.s.vmx.fSupported)
1564	rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1565	else
1566	rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1567	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1568
1569	return rc;
1570	}
1571
1572	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1573
1574	/**
1575	* Returns suspend status of the host.
1576	*
1577	* @returns Suspend pending or not.
1578	*/
1579	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1580	{
1581	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1582	}
1583
1584
1585	/**
1586	* Invalidates a guest page from the host TLB.
1587	*
1588	* @param pVCpu The cross context virtual CPU structure.
1589	* @param GCVirt Page to invalidate.
1590	*/
1591	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1592	{
1593	PVM pVM = pVCpu->CTX_SUFF(pVM);
1594	if (pVM->hm.s.vmx.fSupported)
1595	return VMXR0InvalidatePage(pVCpu, GCVirt);
1596	return SVMR0InvalidatePage(pVCpu, GCVirt);
1597	}
1598
1599
1600	/**
1601	* Returns the cpu structure for the current cpu.
1602	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1603	*
1604	* @returns The cpu structure pointer.
1605	*/
1606	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1607	{
1608	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1609	RTCPUID const idCpu = RTMpCpuId();
1610	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1611	return &g_HmR0.aCpuInfo[idCpu];
1612	}
1613
1614
1615	/**
1616	* Interface for importing state on demand (used by IEM).
1617	*
1618	* @returns VBox status code.
1619	* @param pVCpu The cross context CPU structure.
1620	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1621	*/
1622	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
1623	{
1624	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1625	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1626	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1627	}
1628
1629
1630	#ifdef VBOX_WITH_RAW_MODE
1631	/**
1632	* Raw-mode switcher hook - disable VT-x if it's active and the current
1633	* switcher turns off paging.
1634	*
1635	* @returns VBox status code.
1636	* @param pVM The cross context VM structure.
1637	* @param enmSwitcher The switcher we're about to use.
1638	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1639	*/
1640	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1641	{
1642	NOREF(pVM);
1643
1644	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1645
1646	*pfVTxDisabled = false;
1647
1648	/* No such issues with AMD-V */
1649	if (!g_HmR0.hwvirt.u.vmx.fSupported)
1650	return VINF_SUCCESS;
1651
1652	/* Check if the switching we're up to is safe. */
1653	switch (enmSwitcher)
1654	{
1655	case VMMSWITCHER_32_TO_32:
1656	case VMMSWITCHER_PAE_TO_PAE:
1657	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1658
1659	case VMMSWITCHER_32_TO_PAE:
1660	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1661	case VMMSWITCHER_AMD64_TO_32:
1662	case VMMSWITCHER_AMD64_TO_PAE:
1663	break; /* unsafe switchers */
1664
1665	default:
1666	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1667	}
1668
1669	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1670	regardless of whether we're currently using VT-x or not. */
1671	if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
1672	{
1673	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1674	return VINF_SUCCESS;
1675	}
1676
1677	/** @todo Check if this code is presumptive wrt other VT-x users on the
1678	* system... */
1679
1680	/* Nothing to do if we haven't enabled VT-x. */
1681	if (!g_HmR0.fEnabled)
1682	return VINF_SUCCESS;
1683
1684	/* Local init implies the CPU is currently not in VMX root mode. */
1685	if (!g_HmR0.fGlobalInit)
1686	return VINF_SUCCESS;
1687
1688	/* Ok, disable VT-x. */
1689	PCHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
1690	AssertReturn( pHostCpu
1691	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1692	&& pHostCpu->pvMemObj
1693	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS,
1694	VERR_HM_IPE_2);
1695
1696	*pfVTxDisabled = true;
1697	return VMXR0DisableCpu(pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1698	}
1699
1700
1701	/**
1702	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1703	* switcher turned off paging.
1704	*
1705	* @param pVM The cross context VM structure.
1706	* @param fVTxDisabled Whether VT-x was disabled or not.
1707	*/
1708	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1709	{
1710	Assert(!ASMIntAreEnabled());
1711
1712	if (!fVTxDisabled)
1713	return; /* nothing to do */
1714
1715	Assert(g_HmR0.hwvirt.u.vmx.fSupported);
1716	if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
1717	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1718	else
1719	{
1720	Assert(g_HmR0.fEnabled);
1721	Assert(g_HmR0.fGlobalInit);
1722
1723	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
1724	AssertReturnVoid( pHostCpu
1725	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1726	&& pHostCpu->pvMemObj
1727	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1728
1729	VMXR0EnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.hwvirt.Msrs);
1730	}
1731	}
1732	#endif /* VBOX_WITH_RAW_MODE */
1733
1734
1735	#ifdef VBOX_STRICT
1736	/**
1737	* Dumps a descriptor.
1738	*
1739	* @param pDesc Descriptor to dump.
1740	* @param Sel Selector number.
1741	* @param pszMsg Message to prepend the log entry with.
1742	*/
1743	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1744	{
1745	/*
1746	* Make variable description string.
1747	*/
1748	static struct
1749	{
1750	unsigned cch;
1751	const char *psz;
1752	} const s_aTypes[32] =
1753	{
1754	# define STRENTRY(str) { sizeof(str) - 1, str }
1755
1756	/* system */
1757	# if HC_ARCH_BITS == 64
1758	STRENTRY("Reserved0 "), /* 0x00 */
1759	STRENTRY("Reserved1 "), /* 0x01 */
1760	STRENTRY("LDT "), /* 0x02 */
1761	STRENTRY("Reserved3 "), /* 0x03 */
1762	STRENTRY("Reserved4 "), /* 0x04 */
1763	STRENTRY("Reserved5 "), /* 0x05 */
1764	STRENTRY("Reserved6 "), /* 0x06 */
1765	STRENTRY("Reserved7 "), /* 0x07 */
1766	STRENTRY("Reserved8 "), /* 0x08 */
1767	STRENTRY("TSS64Avail "), /* 0x09 */
1768	STRENTRY("ReservedA "), /* 0x0a */
1769	STRENTRY("TSS64Busy "), /* 0x0b */
1770	STRENTRY("Call64 "), /* 0x0c */
1771	STRENTRY("ReservedD "), /* 0x0d */
1772	STRENTRY("Int64 "), /* 0x0e */
1773	STRENTRY("Trap64 "), /* 0x0f */
1774	# else
1775	STRENTRY("Reserved0 "), /* 0x00 */
1776	STRENTRY("TSS16Avail "), /* 0x01 */
1777	STRENTRY("LDT "), /* 0x02 */
1778	STRENTRY("TSS16Busy "), /* 0x03 */
1779	STRENTRY("Call16 "), /* 0x04 */
1780	STRENTRY("Task "), /* 0x05 */
1781	STRENTRY("Int16 "), /* 0x06 */
1782	STRENTRY("Trap16 "), /* 0x07 */
1783	STRENTRY("Reserved8 "), /* 0x08 */
1784	STRENTRY("TSS32Avail "), /* 0x09 */
1785	STRENTRY("ReservedA "), /* 0x0a */
1786	STRENTRY("TSS32Busy "), /* 0x0b */
1787	STRENTRY("Call32 "), /* 0x0c */
1788	STRENTRY("ReservedD "), /* 0x0d */
1789	STRENTRY("Int32 "), /* 0x0e */
1790	STRENTRY("Trap32 "), /* 0x0f */
1791	# endif
1792	/* non system */
1793	STRENTRY("DataRO "), /* 0x10 */
1794	STRENTRY("DataRO Accessed "), /* 0x11 */
1795	STRENTRY("DataRW "), /* 0x12 */
1796	STRENTRY("DataRW Accessed "), /* 0x13 */
1797	STRENTRY("DataDownRO "), /* 0x14 */
1798	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1799	STRENTRY("DataDownRW "), /* 0x16 */
1800	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1801	STRENTRY("CodeEO "), /* 0x18 */
1802	STRENTRY("CodeEO Accessed "), /* 0x19 */
1803	STRENTRY("CodeER "), /* 0x1a */
1804	STRENTRY("CodeER Accessed "), /* 0x1b */
1805	STRENTRY("CodeConfEO "), /* 0x1c */
1806	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1807	STRENTRY("CodeConfER "), /* 0x1e */
1808	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1809	# undef SYSENTRY
1810	};
1811	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1812	char szMsg[128];
1813	char *psz = &szMsg[0];
1814	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1815	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1816	psz += s_aTypes[i].cch;
1817
1818	if (pDesc->Gen.u1Present)
1819	ADD_STR(psz, "Present ");
1820	else
1821	ADD_STR(psz, "Not-Present ");
1822	# if HC_ARCH_BITS == 64
1823	if (pDesc->Gen.u1Long)
1824	ADD_STR(psz, "64-bit ");
1825	else
1826	ADD_STR(psz, "Comp ");
1827	# else
1828	if (pDesc->Gen.u1Granularity)
1829	ADD_STR(psz, "Page ");
1830	if (pDesc->Gen.u1DefBig)
1831	ADD_STR(psz, "32-bit ");
1832	else
1833	ADD_STR(psz, "16-bit ");
1834	# endif
1835	# undef ADD_STR
1836	*psz = '\0';
1837
1838	/*
1839	* Limit and Base and format the output.
1840	*/
1841	#ifdef LOG_ENABLED
1842	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1843
1844	# if HC_ARCH_BITS == 64
1845	uint64_t u32Base = X86DESC64_BASE(pDesc);
1846	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1847	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1848	# else
1849	uint32_t u32Base = X86DESC_BASE(pDesc);
1850	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1851	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1852	# endif
1853	#else
1854	NOREF(Sel); NOREF(pszMsg);
1855	#endif
1856	}
1857
1858
1859	/**
1860	* Formats a full register dump.
1861	*
1862	* @param pVCpu The cross context virtual CPU structure.
1863	*/
1864	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu)
1865	{
1866	/*
1867	* Format the flags.
1868	*/
1869	static struct
1870	{
1871	const char pszSet; const char pszClear; uint32_t fFlag;
1872	} const s_aFlags[] =
1873	{
1874	{ "vip", NULL, X86_EFL_VIP },
1875	{ "vif", NULL, X86_EFL_VIF },
1876	{ "ac", NULL, X86_EFL_AC },
1877	{ "vm", NULL, X86_EFL_VM },
1878	{ "rf", NULL, X86_EFL_RF },
1879	{ "nt", NULL, X86_EFL_NT },
1880	{ "ov", "nv", X86_EFL_OF },
1881	{ "dn", "up", X86_EFL_DF },
1882	{ "ei", "di", X86_EFL_IF },
1883	{ "tf", NULL, X86_EFL_TF },
1884	{ "nt", "pl", X86_EFL_SF },
1885	{ "nz", "zr", X86_EFL_ZF },
1886	{ "ac", "na", X86_EFL_AF },
1887	{ "po", "pe", X86_EFL_PF },
1888	{ "cy", "nc", X86_EFL_CF },
1889	};
1890	char szEFlags[80];
1891	char *psz = szEFlags;
1892	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1893	uint32_t uEFlags = pCtx->eflags.u32;
1894	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1895	{
1896	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1897	if (pszAdd)
1898	{
1899	strcpy(psz, pszAdd);
1900	psz += strlen(pszAdd);
1901	*psz++ = ' ';
1902	}
1903	}
1904	psz[-1] = '\0';
1905
1906	/*
1907	* Format the registers.
1908	*/
1909	if (CPUMIsGuestIn64BitCode(pVCpu))
1910	{
1911	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1912	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1913	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1914	"r14=%016RX64 r15=%016RX64\n"
1915	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1916	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1917	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1918	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1919	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1920	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1921	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1922	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1923	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1924	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1925	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1926	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1927	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1928	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1929	,
1930	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1931	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1932	pCtx->r14, pCtx->r15,
1933	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1934	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1935	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1936	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1937	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1938	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1939	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1940	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1941	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1942	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1943	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1944	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1945	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1946	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1947	}
1948	else
1949	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1950	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1951	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1952	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1953	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1954	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1955	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1956	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1957	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1958	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1959	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1960	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1961	,
1962	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1963	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1964	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1965	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1966	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1967	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1968	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1969	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1970	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1971	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1972	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1973	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1974
1975	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1976	Log(("FPU:\n"
1977	"FCW=%04x FSW=%04x FTW=%02x\n"
1978	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1979	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1980	,
1981	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1982	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1983	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1984	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1985
1986	Log(("MSR:\n"
1987	"EFER =%016RX64\n"
1988	"PAT =%016RX64\n"
1989	"STAR =%016RX64\n"
1990	"CSTAR =%016RX64\n"
1991	"LSTAR =%016RX64\n"
1992	"SFMASK =%016RX64\n"
1993	"KERNELGSBASE =%016RX64\n",
1994	pCtx->msrEFER,
1995	pCtx->msrPAT,
1996	pCtx->msrSTAR,
1997	pCtx->msrCSTAR,
1998	pCtx->msrLSTAR,
1999	pCtx->msrSFMASK,
2000	pCtx->msrKERNELGSBASE));
2001
2002	NOREF(pFpuCtx);
2003	}
2004	#endif /* VBOX_STRICT */
2005

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 78220

Download in other formats: