HMR0.cpp@ 80047

Last change on this file since 80047 was 80047, checked in by vboxsync, 5 years ago
Main: Kicking out raw-mode - GVMMR0, HMR0. bugref:9517
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1	/* $Id: HMR0.cpp 80047 2019-07-29 19:12:29Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/hmvmxinline.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMPHYSCPU aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPU pVCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
99	/** @} */
100
101	/** Hardware-virtualization data. */
102	struct
103	{
104	union
105	{
106	/** VT-x data. */
107	struct
108	{
109	/** Host CR4 value (set by ring-0 VMX init) */
110	uint64_t u64HostCr4;
111	/** Host EFER value (set by ring-0 VMX init) */
112	uint64_t u64HostMsrEfer;
113	/** Host SMM monitor control (used for logging/diagnostics) */
114	uint64_t u64HostSmmMonitorCtl;
115	/** Last instruction error. */
116	uint32_t ulLastInstrError;
117	/** The shift mask employed by the VMX-Preemption timer. */
118	uint8_t cPreemptTimerShift;
119	/** Padding. */
120	uint8_t abPadding[3];
121	/** Whether we're using the preemption timer or not. */
122	bool fUsePreemptTimer;
123	/** Whether we're using SUPR0EnableVTx or not. */
124	bool fUsingSUPR0EnableVTx;
125	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
126	* module termination. */
127	bool fCalledSUPR0EnableVTx;
128	/** Set to by us to indicate VMX is supported by the CPU. */
129	bool fSupported;
130	} vmx;
131
132	/** AMD-V data. */
133	struct
134	{
135	/** SVM revision. */
136	uint32_t u32Rev;
137	/** SVM feature bits from cpuid 0x8000000a */
138	uint32_t u32Features;
139	/** Padding. */
140	bool afPadding[3];
141	/** Set by us to indicate SVM is supported by the CPU. */
142	bool fSupported;
143	} svm;
144	} u;
145	/** Maximum allowed ASID/VPID (inclusive). */
146	uint32_t uMaxAsid;
147	/** MSRs. */
148	SUPHWVIRTMSRS Msrs;
149	} hwvirt;
150
151	/** Last recorded error code during HM ring-0 init. */
152	int32_t rcInit;
153
154	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
155	* enabled and disabled each time it's used to execute guest code. */
156	bool fGlobalInit;
157	/** Indicates whether the host is suspending or not. We'll refuse a few
158	* actions when the host is being suspended to speed up the suspending and
159	* avoid trouble. */
160	bool volatile fSuspended;
161
162	/** Whether we've already initialized all CPUs.
163	* @remarks We could check the EnableAllCpusOnce state, but this is
164	* simpler and hopefully easier to understand. */
165	bool fEnabled;
166	/** Serialize initialization in HMR0EnableAllCpus. */
167	RTONCE EnableAllCpusOnce;
168	} g_HmR0;
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	# ifndef DEBUG_bird
212	/**
213	* Get the CPU ID on which the failure status code was reported.
214	*
215	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
216	* @param pFirstRc The first return code structure.
217	*/
218	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->idCpu;
221	}
222	# endif
223	#endif /* VBOX_STRICT */
224
225
226	/** @name Dummy callback handlers.
227	* @{ */
228
229	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu)
230	{
231	RT_NOREF1(pVCpu);
232	return VINF_SUCCESS;
233	}
234
235	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
236	{
237	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
238	}
239
240	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
241	bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
242	{
243	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
244	return VINF_SUCCESS;
245	}
246
247	static DECLCALLBACK(int) hmR0DummyDisableCpu(void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
248	{
249	RT_NOREF2(pvCpuPage, HCPhysCpuPage);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
254	{
255	RT_NOREF1(pVM);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
260	{
261	RT_NOREF1(pVM);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
266	{
267	RT_NOREF1(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu)
272	{
273	RT_NOREF(pVCpu);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)
278	{
279	RT_NOREF1(pVCpu);
280	return VINF_SUCCESS;
281	}
282
283	/** @} */
284
285
286	/**
287	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
288	* Down at the Rate Specified" erratum.
289	*
290	* Errata names and related steppings:
291	* - BA86 - D0.
292	* - AAX65 - C2.
293	* - AAU65 - C2, K0.
294	* - AAO95 - B1.
295	* - AAT59 - C2.
296	* - AAK139 - D0.
297	* - AAM126 - C0, C1, D0.
298	* - AAN92 - B1.
299	* - AAJ124 - C0, D0.
300	* - AAP86 - B1.
301	*
302	* Steppings: B1, C0, C1, C2, D0, K0.
303	*
304	* @returns true if subject to it, false if not.
305	*/
306	static bool hmR0InitIntelIsSubjectToVmxPreemptTimerErratum(void)
307	{
308	uint32_t u = ASMCpuId_EAX(1);
309	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
310	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
311	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
312	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
313	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
314	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
315	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
316	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
317	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
318	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
319	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
321	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
322	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
323	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
324	)
325	return true;
326	return false;
327	}
328
329
330	/**
331	* Intel specific initialization code.
332	*
333	* @returns VBox status code (will only fail if out of memory).
334	*/
335	static int hmR0InitIntel(void)
336	{
337	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
338	g_HmR0.hwvirt.Msrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
339
340	/*
341	* First try use native kernel API for controlling VT-x.
342	* (This is only supported by some Mac OS X kernels atm.)
343	*/
344	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
345	g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
346	if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
347	{
348	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
349	if (RT_SUCCESS(rc))
350	{
351	g_HmR0.hwvirt.u.vmx.fSupported = true;
352	rc = SUPR0EnableVTx(false /* fEnable */);
353	AssertLogRelRC(rc);
354	}
355	}
356	else
357	{
358	HMR0FIRSTRC FirstRc;
359	hmR0FirstRcInit(&FirstRc);
360	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
361	if (RT_SUCCESS(g_HmR0.rcInit))
362	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
363	}
364
365	if (RT_SUCCESS(g_HmR0.rcInit))
366	{
367	/* Read CR4 and EFER for logging/diagnostic purposes. */
368	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
369	g_HmR0.hwvirt.u.vmx.u64HostMsrEfer = ASMRdMsr(MSR_K6_EFER);
370
371	/* Get VMX MSRs for determining VMX features we can ultimately use. */
372	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_VT_X, false /* fForce */);
373
374	/*
375	* Nested KVM workaround: Intel SDM section 34.15.5 describes that
376	* MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
377	* table 35-2 says that this MSR is available if either VMX or SMX is supported.
378	*/
379	uint64_t const uVmxBasicMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Basic;
380	if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
381	g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
382
383	/* Initialize VPID - 16 bits ASID. */
384	g_HmR0.hwvirt.uMaxAsid = 0x10000; /* exclusive */
385
386	/*
387	* If the host OS has not enabled VT-x for us, try enter VMX root mode
388	* to really verify if VT-x is usable.
389	*/
390	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
391	{
392	/* Allocate a temporary VMXON region. */
393	RTR0MEMOBJ hScatchMemObj;
394	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
395	if (RT_FAILURE(rc))
396	{
397	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
398	return rc;
399	}
400	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
401	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
402	ASMMemZeroPage(pvScatchPage);
403
404	/* Set revision dword at the beginning of the VMXON structure. */
405	(uint32_t )pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
406
407	/* Make sure we don't get rescheduled to another CPU during this probe. */
408	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
409
410	/* Check CR4.VMXE. */
411	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
412	if (!(g_HmR0.hwvirt.u.vmx.u64HostCr4 & X86_CR4_VMXE))
413	{
414	/* In theory this bit could be cleared behind our back. Which would cause #UD
415	faults when we try to execute the VMX instructions... */
416	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4 \| X86_CR4_VMXE);
417	}
418
419	/*
420	* The only way of checking if we're in VMX root mode or not is to try and enter it.
421	* There is no instruction or control bit that tells us if we're in VMX root mode.
422	* Therefore, try and enter VMX root mode here.
423	*/
424	rc = VMXEnable(HCPhysScratchPage);
425	if (RT_SUCCESS(rc))
426	{
427	g_HmR0.hwvirt.u.vmx.fSupported = true;
428	VMXDisable();
429	}
430	else
431	{
432	/*
433	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
434	* it will crash the host when we enter raw mode, because:
435	*
436	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
437	* this bit), and
438	* (b) turning off paging causes a #GP (unavoidable when switching
439	* from long to 32 bits mode or 32 bits to PAE).
440	*
441	* They should fix their code, but until they do we simply refuse to run.
442	*/
443	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
444	Assert(g_HmR0.hwvirt.u.vmx.fSupported == false);
445	}
446
447	/*
448	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
449	* set before (some software could incorrectly think it is in VMX mode).
450	*/
451	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4);
452	ASMSetFlags(fEFlags);
453
454	RTR0MemObjFree(hScatchMemObj, false);
455	}
456
457	if (g_HmR0.hwvirt.u.vmx.fSupported)
458	{
459	rc = VMXR0GlobalInit();
460	if (RT_FAILURE(rc))
461	g_HmR0.rcInit = rc;
462
463	/*
464	* Install the VT-x methods.
465	*/
466	g_HmR0.pfnEnterSession = VMXR0Enter;
467	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
468	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
469	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
470	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
471	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
472	g_HmR0.pfnInitVM = VMXR0InitVM;
473	g_HmR0.pfnTermVM = VMXR0TermVM;
474	g_HmR0.pfnSetupVM = VMXR0SetupVM;
475
476	/*
477	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
478	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
479	*/
480	VMXCTLSMSR PinCtls;
481	PinCtls.u = g_HmR0.hwvirt.Msrs.u.vmx.u64PinCtls;
482	if (PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
483	{
484	uint64_t const uVmxMiscMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Misc;
485	g_HmR0.hwvirt.u.vmx.fUsePreemptTimer = true;
486	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = RT_BF_GET(uVmxMiscMsr, VMX_BF_MISC_PREEMPT_TIMER_TSC);
487	if (hmR0InitIntelIsSubjectToVmxPreemptTimerErratum())
488	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
489	}
490	}
491	}
492	#ifdef LOG_ENABLED
493	else
494	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
495	#endif
496	return VINF_SUCCESS;
497	}
498
499
500	/**
501	* AMD-specific initialization code.
502	*
503	* @returns VBox status code (will only fail if out of memory).
504	*/
505	static int hmR0InitAmd(void)
506	{
507	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
508	int rc = SVMR0GlobalInit();
509	if (RT_FAILURE(rc))
510	{
511	g_HmR0.rcInit = rc;
512	return rc;
513	}
514
515	/*
516	* Install the AMD-V methods.
517	*/
518	g_HmR0.pfnEnterSession = SVMR0Enter;
519	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
520	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
521	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
522	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
523	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
524	g_HmR0.pfnInitVM = SVMR0InitVM;
525	g_HmR0.pfnTermVM = SVMR0TermVM;
526	g_HmR0.pfnSetupVM = SVMR0SetupVM;
527
528	/* Query AMD features. */
529	uint32_t u32Dummy;
530	ASMCpuId(0x8000000a, &g_HmR0.hwvirt.u.svm.u32Rev, &g_HmR0.hwvirt.uMaxAsid, &u32Dummy, &g_HmR0.hwvirt.u.svm.u32Features);
531
532	/*
533	* We need to check if AMD-V has been properly initialized on all CPUs.
534	* Some BIOSes might do a poor job.
535	*/
536	HMR0FIRSTRC FirstRc;
537	hmR0FirstRcInit(&FirstRc);
538	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
539	AssertRC(rc);
540	if (RT_SUCCESS(rc))
541	rc = hmR0FirstRcGetStatus(&FirstRc);
542	#ifndef DEBUG_bird
543	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
544	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
545	#endif
546	if (RT_SUCCESS(rc))
547	{
548	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_AMD_V, false /* fForce */);
549	g_HmR0.hwvirt.u.svm.fSupported = true;
550	}
551	else
552	{
553	g_HmR0.rcInit = rc;
554	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
555	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
556	}
557	return rc;
558	}
559
560
561	/**
562	* Does global Ring-0 HM initialization (at module init).
563	*
564	* @returns VBox status code.
565	*/
566	VMMR0_INT_DECL(int) HMR0Init(void)
567	{
568	/*
569	* Initialize the globals.
570	*/
571	g_HmR0.fEnabled = false;
572	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
573	g_HmR0.EnableAllCpusOnce = s_OnceInit;
574	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
575	{
576	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
577	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
578	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
579	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
580	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
581	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
582	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
583	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
584	#endif
585	}
586
587	/* Fill in all callbacks with placeholders. */
588	g_HmR0.pfnEnterSession = hmR0DummyEnter;
589	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
590	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
591	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
592	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
593	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
594	g_HmR0.pfnInitVM = hmR0DummyInitVM;
595	g_HmR0.pfnTermVM = hmR0DummyTermVM;
596	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
597
598	/* Default is global VT-x/AMD-V init. */
599	g_HmR0.fGlobalInit = true;
600
601	/*
602	* Make sure aCpuInfo is big enough for all the CPUs on this system.
603	*/
604	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
605	{
606	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
607	return VERR_TOO_MANY_CPUS;
608	}
609
610	/*
611	* Check for VT-x or AMD-V support.
612	* Return failure only in out-of-memory situations.
613	*/
614	uint32_t fCaps = 0;
615	int rc = SUPR0GetVTSupport(&fCaps);
616	if (RT_SUCCESS(rc))
617	{
618	if (fCaps & SUPVTCAPS_VT_X)
619	{
620	rc = hmR0InitIntel();
621	if (RT_FAILURE(rc))
622	return rc;
623	}
624	else
625	{
626	Assert(fCaps & SUPVTCAPS_AMD_V);
627	rc = hmR0InitAmd();
628	if (RT_FAILURE(rc))
629	return rc;
630	}
631	}
632	else
633	g_HmR0.rcInit = VERR_UNSUPPORTED_CPU;
634
635	/*
636	* Register notification callbacks that we can use to disable/enable CPUs
637	* when brought offline/online or suspending/resuming.
638	*/
639	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
640	{
641	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
642	AssertRC(rc);
643
644	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
645	AssertRC(rc);
646	}
647
648	/* We return success here because module init shall not fail if HM fails to initialize. */
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Does global Ring-0 HM termination (at module termination).
655	*
656	* @returns VBox status code.
657	*/
658	VMMR0_INT_DECL(int) HMR0Term(void)
659	{
660	int rc;
661	if ( g_HmR0.hwvirt.u.vmx.fSupported
662	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
663	{
664	/*
665	* Simple if the host OS manages VT-x.
666	*/
667	Assert(g_HmR0.fGlobalInit);
668
669	if (g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx)
670	{
671	rc = SUPR0EnableVTx(false /* fEnable */);
672	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = false;
673	}
674	else
675	rc = VINF_SUCCESS;
676
677	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
678	{
679	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
680	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
681	}
682	}
683	else
684	{
685	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
686
687	/* Doesn't really matter if this fails. */
688	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
689	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
690
691	/*
692	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
693	*/
694	if (g_HmR0.fGlobalInit)
695	{
696	HMR0FIRSTRC FirstRc;
697	hmR0FirstRcInit(&FirstRc);
698	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
699	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
700	if (RT_SUCCESS(rc))
701	rc = hmR0FirstRcGetStatus(&FirstRc);
702	}
703
704	/*
705	* Free the per-cpu pages used for VT-x and AMD-V.
706	*/
707	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
708	{
709	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
710	{
711	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
712	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
713	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
714	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
715	}
716	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
717	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
718	{
719	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
720	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
721	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
722	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
723	}
724	#endif
725	}
726	}
727
728	/** @todo This needs cleaning up. There's no matching
729	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
730	* should move into their respective modules. */
731	/* Finally, call global VT-x/AMD-V termination. */
732	if (g_HmR0.hwvirt.u.vmx.fSupported)
733	VMXR0GlobalTerm();
734	else if (g_HmR0.hwvirt.u.svm.fSupported)
735	SVMR0GlobalTerm();
736
737	return rc;
738	}
739
740
741	/**
742	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
743	* on a CPU.
744	*
745	* @param idCpu The identifier for the CPU the function is called on.
746	* @param pvUser1 Pointer to the first RC structure.
747	* @param pvUser2 Ignored.
748	*/
749	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
750	{
751	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
752	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
753	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
754	NOREF(idCpu); NOREF(pvUser2);
755
756	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
757	hmR0FirstRcSetStatus(pFirstRc, rc);
758	}
759
760
761	/**
762	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
763	* on a CPU.
764	*
765	* @param idCpu The identifier for the CPU the function is called on.
766	* @param pvUser1 Pointer to the first RC structure.
767	* @param pvUser2 Ignored.
768	*/
769	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
770	{
771	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
772	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
773	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
774	NOREF(idCpu); NOREF(pvUser2);
775
776	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
777	hmR0FirstRcSetStatus(pFirstRc, rc);
778	}
779
780
781	/**
782	* Enable VT-x or AMD-V on the current CPU
783	*
784	* @returns VBox status code.
785	* @param pVM The cross context VM structure. Can be NULL.
786	* @param idCpu The identifier for the CPU the function is called on.
787	*
788	* @remarks Maybe called with interrupts disabled!
789	*/
790	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
791	{
792	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
793
794	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
795	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
796	Assert(!pHostCpu->fConfigured);
797	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
798
799	pHostCpu->idCpu = idCpu;
800	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
801
802	int rc;
803	if ( g_HmR0.hwvirt.u.vmx.fSupported
804	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
805	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.hwvirt.Msrs);
806	else
807	{
808	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
809	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.hwvirt.Msrs);
810	}
811	if (RT_SUCCESS(rc))
812	pHostCpu->fConfigured = true;
813	return rc;
814	}
815
816
817	/**
818	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
819	*
820	* @param idCpu The identifier for the CPU the function is called on.
821	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
822	* @param pvUser2 The 2nd user argument.
823	*/
824	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
825	{
826	PVM pVM = (PVM)pvUser1; /* can be NULL! */
827	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
828	AssertReturnVoid(g_HmR0.fGlobalInit);
829	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
830	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
831	}
832
833
834	/**
835	* RTOnce callback employed by HMR0EnableAllCpus.
836	*
837	* @returns VBox status code.
838	* @param pvUser Pointer to the VM.
839	*/
840	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
841	{
842	PVM pVM = (PVM)pvUser;
843
844	/*
845	* Indicate that we've initialized.
846	*
847	* Note! There is a potential race between this function and the suspend
848	* notification. Kind of unlikely though, so ignored for now.
849	*/
850	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
851	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
852
853	/*
854	* The global init variable is set by the first VM.
855	*/
856	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
857
858	#ifdef VBOX_STRICT
859	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
860	{
861	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
862	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
863	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
864	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
865	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
866	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
867	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
868	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
869	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
870	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
871	# endif
872	}
873	#endif
874
875	int rc;
876	if ( g_HmR0.hwvirt.u.vmx.fSupported
877	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
878	{
879	/*
880	* Global VT-x initialization API (only darwin for now).
881	*/
882	rc = SUPR0EnableVTx(true /* fEnable */);
883	if (RT_SUCCESS(rc))
884	{
885	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = true;
886	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
887	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
888	}
889	else
890	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
891	}
892	else
893	{
894	/*
895	* We're doing the job ourselves.
896	*/
897	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
898	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
899	{
900	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
901	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
902	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
903	#endif
904	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
905	{
906	/** @todo NUMA */
907	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
908	AssertLogRelRCReturn(rc, rc);
909
910	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
911	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
912	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
913
914	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
915	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
916	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
917
918	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
919	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
920	false /* executable R0 mapping */);
921	AssertLogRelRCReturn(rc, rc);
922
923	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
924	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
925	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
926
927	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
928	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
929	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
930	#endif
931	}
932	}
933
934	rc = VINF_SUCCESS;
935	}
936
937	if ( RT_SUCCESS(rc)
938	&& g_HmR0.fGlobalInit)
939	{
940	/* First time, so initialize each cpu/core. */
941	HMR0FIRSTRC FirstRc;
942	hmR0FirstRcInit(&FirstRc);
943	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
944	if (RT_SUCCESS(rc))
945	rc = hmR0FirstRcGetStatus(&FirstRc);
946	}
947
948	return rc;
949	}
950
951
952	/**
953	* Sets up HM on all cpus.
954	*
955	* @returns VBox status code.
956	* @param pVM The cross context VM structure.
957	*/
958	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
959	{
960	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
961	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
962	return VERR_HM_SUSPEND_PENDING;
963
964	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
965	}
966
967
968	/**
969	* Disable VT-x or AMD-V on the current CPU.
970	*
971	* @returns VBox status code.
972	* @param idCpu The identifier for the CPU this function is called on.
973	*
974	* @remarks Must be called with preemption disabled.
975	*/
976	static int hmR0DisableCpu(RTCPUID idCpu)
977	{
978	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
979
980	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
981	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
982	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
983	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
984	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
985	AssertRelease(idCpu == RTMpCpuId());
986
987	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
988	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
989	AssertPtr(pHostCpu->pvMemObj);
990	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
991
992	int rc;
993	if (pHostCpu->fConfigured)
994	{
995	rc = g_HmR0.pfnDisableCpu(pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
996	AssertRCReturn(rc, rc);
997
998	pHostCpu->fConfigured = false;
999	pHostCpu->idCpu = NIL_RTCPUID;
1000	}
1001	else
1002	rc = VINF_SUCCESS; /* nothing to do */
1003	return rc;
1004	}
1005
1006
1007	/**
1008	* Worker function passed to RTMpOnAll() that is to be called on the target
1009	* CPUs.
1010	*
1011	* @param idCpu The identifier for the CPU the function is called on.
1012	* @param pvUser1 The 1st user argument.
1013	* @param pvUser2 Opaque pointer to the FirstRc.
1014	*/
1015	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1016	{
1017	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1018	AssertReturnVoid(g_HmR0.fGlobalInit);
1019	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1020	}
1021
1022
1023	/**
1024	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1025	* CPU.
1026	*
1027	* @param idCpu The identifier for the CPU the function is called on.
1028	* @param pvUser1 Null, not used.
1029	* @param pvUser2 Null, not used.
1030	*/
1031	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1032	{
1033	NOREF(pvUser1);
1034	NOREF(pvUser2);
1035	hmR0DisableCpu(idCpu);
1036	}
1037
1038
1039	/**
1040	* Callback function invoked when a cpu goes online or offline.
1041	*
1042	* @param enmEvent The Mp event.
1043	* @param idCpu The identifier for the CPU the function is called on.
1044	* @param pvData Opaque data (PVM pointer).
1045	*/
1046	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1047	{
1048	NOREF(pvData);
1049	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1050
1051	/*
1052	* We only care about uninitializing a CPU that is going offline. When a
1053	* CPU comes online, the initialization is done lazily in HMR0Enter().
1054	*/
1055	switch (enmEvent)
1056	{
1057	case RTMPEVENT_OFFLINE:
1058	{
1059	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1060	RTThreadPreemptDisable(&PreemptState);
1061	if (idCpu == RTMpCpuId())
1062	{
1063	int rc = hmR0DisableCpu(idCpu);
1064	AssertRC(rc);
1065	RTThreadPreemptRestore(&PreemptState);
1066	}
1067	else
1068	{
1069	RTThreadPreemptRestore(&PreemptState);
1070	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1071	}
1072	break;
1073	}
1074
1075	default:
1076	break;
1077	}
1078	}
1079
1080
1081	/**
1082	* Called whenever a system power state change occurs.
1083	*
1084	* @param enmEvent The Power event.
1085	* @param pvUser User argument.
1086	*/
1087	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1088	{
1089	NOREF(pvUser);
1090	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1091
1092	#ifdef LOG_ENABLED
1093	if (enmEvent == RTPOWEREVENT_SUSPEND)
1094	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1095	else
1096	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1097	#endif
1098
1099	if (enmEvent == RTPOWEREVENT_SUSPEND)
1100	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1101
1102	if (g_HmR0.fEnabled)
1103	{
1104	int rc;
1105	HMR0FIRSTRC FirstRc;
1106	hmR0FirstRcInit(&FirstRc);
1107
1108	if (enmEvent == RTPOWEREVENT_SUSPEND)
1109	{
1110	if (g_HmR0.fGlobalInit)
1111	{
1112	/* Turn off VT-x or AMD-V on all CPUs. */
1113	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1114	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1115	}
1116	/* else nothing to do here for the local init case */
1117	}
1118	else
1119	{
1120	/* Reinit the CPUs from scratch as the suspend state might have
1121	messed with the MSRs. (lousy BIOSes as usual) */
1122	if (g_HmR0.hwvirt.u.vmx.fSupported)
1123	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1124	else
1125	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1126	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1127	if (RT_SUCCESS(rc))
1128	rc = hmR0FirstRcGetStatus(&FirstRc);
1129	#ifdef LOG_ENABLED
1130	if (RT_FAILURE(rc))
1131	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1132	#endif
1133	if (g_HmR0.fGlobalInit)
1134	{
1135	/* Turn VT-x or AMD-V back on on all CPUs. */
1136	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1137	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1138	}
1139	/* else nothing to do here for the local init case */
1140	}
1141	}
1142
1143	if (enmEvent == RTPOWEREVENT_RESUME)
1144	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1145	}
1146
1147
1148	/**
1149	* Does ring-0 per-VM HM initialization.
1150	*
1151	* This will call the CPU specific init. routine which may initialize and allocate
1152	* resources for virtual CPUs.
1153	*
1154	* @returns VBox status code.
1155	* @param pVM The cross context VM structure.
1156	*
1157	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1158	* vmR3InitRing3().
1159	*/
1160	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1161	{
1162	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1163
1164	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1165	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1166	return VERR_HM_SUSPEND_PENDING;
1167
1168	/*
1169	* Copy globals to the VM structure.
1170	*/
1171	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1172	if (pVM->hm.s.vmx.fSupported)
1173	{
1174	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.hwvirt.u.vmx.fUsePreemptTimer; /* Can be overridden by CFGM in HMR3Init(). */
1175	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.hwvirt.u.vmx.cPreemptTimerShift;
1176	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.hwvirt.u.vmx.u64HostCr4;
1177	pVM->hm.s.vmx.u64HostMsrEfer = g_HmR0.hwvirt.u.vmx.u64HostMsrEfer;
1178	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl;
1179	HMGetVmxMsrsFromHwvirtMsrs(&g_HmR0.hwvirt.Msrs, &pVM->hm.s.vmx.Msrs);
1180	/* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
1181
1182	/* Enable VPID if supported and configured. */
1183	if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1184	pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
1185
1186	/* Use VMCS shadowing if supported. */
1187	Assert(!pVM->hm.s.vmx.fUseVmcsShadowing);
1188	if ( pVM->cpum.ro.GuestFeatures.fVmx
1189	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING))
1190	pVM->hm.s.vmx.fUseVmcsShadowing = true;
1191
1192	/* Use the VMCS controls for swapping the EFER MSR if supported. */
1193	Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
1194	#if HC_ARCH_BITS == 64
1195	if ( (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
1196	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1197	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
1198	pVM->hm.s.vmx.fSupportsVmcsEfer = true;
1199	#endif
1200
1201	#if 0
1202	/* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
1203	if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1204	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1205	pVM->hm.s.fVirtApicRegs = true;
1206
1207	/* Enable posted-interrupt processing if supported. */
1208	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1209	* here. */
1210	if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1211	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1212	pVM->hm.s.fPostedIntrs = true;
1213	#endif
1214	}
1215	else if (pVM->hm.s.svm.fSupported)
1216	{
1217	pVM->hm.s.svm.u32Rev = g_HmR0.hwvirt.u.svm.u32Rev;
1218	pVM->hm.s.svm.u32Features = g_HmR0.hwvirt.u.svm.u32Features;
1219	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.hwvirt.Msrs.u.svm.u64MsrHwcr;
1220	/* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
1221	}
1222	pVM->hm.s.rcInit = g_HmR0.rcInit;
1223	pVM->hm.s.uMaxAsid = g_HmR0.hwvirt.uMaxAsid;
1224
1225	/*
1226	* Set default maximum inner loops in ring-0 before returning to ring-3.
1227	* Can be overriden using CFGM.
1228	*/
1229	if (!pVM->hm.s.cMaxResumeLoops)
1230	{
1231	pVM->hm.s.cMaxResumeLoops = 1024;
1232	if (RTThreadPreemptIsPendingTrusty())
1233	pVM->hm.s.cMaxResumeLoops = 8192;
1234	}
1235
1236	/*
1237	* Initialize some per-VCPU fields.
1238	*/
1239	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1240	{
1241	PVMCPU pVCpu = &pVM->aCpus[i];
1242	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1243	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1244
1245	/* We'll aways increment this the first time (host uses ASID 0). */
1246	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1247	}
1248
1249	/*
1250	* Get host kernel features that HM might need to know in order
1251	* to co-operate and function properly with the host OS (e.g. SMAP).
1252	*
1253	* Technically, we could do this as part of the pre-init VM procedure
1254	* but it shouldn't be done later than this point so we do it here.
1255	*/
1256	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1257
1258	/*
1259	* Call the hardware specific initialization method.
1260	*/
1261	return g_HmR0.pfnInitVM(pVM);
1262	}
1263
1264
1265	/**
1266	* Does ring-0 per VM HM termination.
1267	*
1268	* @returns VBox status code.
1269	* @param pVM The cross context VM structure.
1270	*/
1271	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1272	{
1273	Log(("HMR0TermVM: %p\n", pVM));
1274	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1275
1276	/*
1277	* Call the hardware specific method.
1278	*
1279	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1280	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1281	*/
1282	return g_HmR0.pfnTermVM(pVM);
1283	}
1284
1285
1286	/**
1287	* Sets up a VT-x or AMD-V session.
1288	*
1289	* This is mostly about setting up the hardware VM state.
1290	*
1291	* @returns VBox status code.
1292	* @param pVM The cross context VM structure.
1293	*/
1294	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1295	{
1296	Log(("HMR0SetupVM: %p\n", pVM));
1297	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1298
1299	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1300	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1301
1302	/* On first entry we'll sync everything. */
1303	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1304	{
1305	PVMCPU pVCpu = &pVM->aCpus[i];
1306	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1307	}
1308
1309	/*
1310	* Call the hardware specific setup VM method. This requires the CPU to be
1311	* enabled for AMD-V/VT-x and preemption to be prevented.
1312	*/
1313	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1314	RTThreadPreemptDisable(&PreemptState);
1315	RTCPUID const idCpu = RTMpCpuId();
1316
1317	/* Enable VT-x or AMD-V if local init is required. */
1318	int rc;
1319	if (!g_HmR0.fGlobalInit)
1320	{
1321	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1322	rc = hmR0EnableCpu(pVM, idCpu);
1323	if (RT_FAILURE(rc))
1324	{
1325	RTThreadPreemptRestore(&PreemptState);
1326	return rc;
1327	}
1328	}
1329
1330	/* Setup VT-x or AMD-V. */
1331	rc = g_HmR0.pfnSetupVM(pVM);
1332
1333	/* Disable VT-x or AMD-V if local init was done before. */
1334	if (!g_HmR0.fGlobalInit)
1335	{
1336	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1337	int rc2 = hmR0DisableCpu(idCpu);
1338	AssertRC(rc2);
1339	}
1340
1341	RTThreadPreemptRestore(&PreemptState);
1342	return rc;
1343	}
1344
1345
1346	/**
1347	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1348	* required for entering HM context.
1349	*
1350	* @returns VBox status code.
1351	* @param pVCpu The cross context virtual CPU structure.
1352	*
1353	* @remarks No-long-jump zone!!!
1354	*/
1355	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)
1356	{
1357	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1358
1359	int rc = VINF_SUCCESS;
1360	RTCPUID const idCpu = RTMpCpuId();
1361	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1362	AssertPtr(pHostCpu);
1363
1364	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1365	if (!pHostCpu->fConfigured)
1366	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1367
1368	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1369	if (g_HmR0.hwvirt.u.vmx.fSupported)
1370	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1371	else
1372	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1373
1374	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1375	pVCpu->hm.s.idEnteredCpu = idCpu;
1376	return rc;
1377	}
1378
1379
1380	/**
1381	* Enters the VT-x or AMD-V session.
1382	*
1383	* @returns VBox status code.
1384	* @param pVCpu The cross context virtual CPU structure.
1385	*
1386	* @remarks This is called with preemption disabled.
1387	*/
1388	VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)
1389	{
1390	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1391	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1392	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1393
1394	/* Load the bare minimum state required for entering HM. */
1395	int rc = hmR0EnterCpu(pVCpu);
1396	if (RT_SUCCESS(rc))
1397	{
1398	if (g_HmR0.hwvirt.u.vmx.fSupported)
1399	{
1400	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1401	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1402	}
1403	else
1404	{
1405	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1406	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1407	}
1408
1409	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1410	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1411	bool const fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1412	#endif
1413
1414	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1415	rc = g_HmR0.pfnEnterSession(pVCpu);
1416	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1417
1418	/* Exports the host-state as we may be resuming code after a longjmp and quite
1419	possibly now be scheduled on a different CPU. */
1420	rc = g_HmR0.pfnExportHostState(pVCpu);
1421	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1422
1423	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1424	if (fStartedSet)
1425	PGMRZDynMapReleaseAutoSet(pVCpu);
1426	#endif
1427	}
1428	return rc;
1429	}
1430
1431
1432	/**
1433	* Deinitializes the bare minimum state used for HM context and if necessary
1434	* disable HM on the CPU.
1435	*
1436	* @returns VBox status code.
1437	* @param pVCpu The cross context virtual CPU structure.
1438	*
1439	* @remarks No-long-jump zone!!!
1440	*/
1441	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1442	{
1443	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1444	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1445
1446	RTCPUID const idCpu = RTMpCpuId();
1447	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1448
1449	if ( !g_HmR0.fGlobalInit
1450	&& pHostCpu->fConfigured)
1451	{
1452	int rc = hmR0DisableCpu(idCpu);
1453	AssertRCReturn(rc, rc);
1454	Assert(!pHostCpu->fConfigured);
1455	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1456
1457	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1458	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1459	}
1460
1461	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1462	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1463
1464	return VINF_SUCCESS;
1465	}
1466
1467
1468	/**
1469	* Thread-context hook for HM.
1470	*
1471	* @param enmEvent The thread-context event.
1472	* @param pvUser Opaque pointer to the VMCPU.
1473	*/
1474	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1475	{
1476	PVMCPU pVCpu = (PVMCPU)pvUser;
1477	Assert(pVCpu);
1478	Assert(g_HmR0.pfnThreadCtxCallback);
1479
1480	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1481	}
1482
1483
1484	/**
1485	* Runs guest code in a hardware accelerated VM.
1486	*
1487	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1488	* called from setjmp assembly.)
1489	* @param pVM The cross context VM structure.
1490	* @param pVCpu The cross context virtual CPU structure.
1491	*
1492	* @remarks Can be called with preemption enabled if thread-context hooks are
1493	* used!!!
1494	*/
1495	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1496	{
1497	RT_NOREF(pVM);
1498
1499	#ifdef VBOX_STRICT
1500	/* With thread-context hooks we would be running this code with preemption enabled. */
1501	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1502	{
1503	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1504	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1505	Assert(pHostCpu->fConfigured);
1506	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1507	}
1508	#endif
1509
1510	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1511	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1512	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1513	PGMRZDynMapStartAutoSet(pVCpu);
1514	#endif
1515
1516	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1517
1518	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1519	PGMRZDynMapReleaseAutoSet(pVCpu);
1520	#endif
1521	return VBOXSTRICTRC_VAL(rcStrict);
1522	}
1523
1524
1525	/**
1526	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1527	* the host CPU and that guest access to it must be intercepted.
1528	*
1529	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1530	*/
1531	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1532	{
1533	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1534	}
1535
1536
1537	/**
1538	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1539	*
1540	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1541	*/
1542	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1543	{
1544	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1545	}
1546
1547
1548	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1549
1550	/**
1551	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1552	*
1553	* @returns VBox status code.
1554	* @param pVM The cross context VM structure.
1555	* @param pVCpu The cross context virtual CPU structure.
1556	* @param pCtx Pointer to the guest CPU context.
1557	*/
1558	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1559	{
1560	RT_NOREF(pCtx);
1561	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1562	if (pVM->hm.s.vmx.fSupported)
1563	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1564	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1565	}
1566
1567
1568	/**
1569	* Save guest debug state (64 bits guest mode & 32 bits host only)
1570	*
1571	* @returns VBox status code.
1572	* @param pVM The cross context VM structure.
1573	* @param pVCpu The cross context virtual CPU structure.
1574	* @param pCtx Pointer to the guest CPU context.
1575	*/
1576	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1577	{
1578	RT_NOREF(pCtx);
1579	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1580	if (pVM->hm.s.vmx.fSupported)
1581	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1582	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1583	}
1584
1585
1586	/**
1587	* Test the 32->64 bits switcher.
1588	*
1589	* @returns VBox status code.
1590	* @param pVM The cross context VM structure.
1591	*/
1592	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1593	{
1594	PVMCPU pVCpu = &pVM->aCpus[0];
1595	uint32_t aParam[5] = { 0, 1, 2, 3, 4 };
1596	int rc;
1597
1598	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1599	if (pVM->hm.s.vmx.fSupported)
1600	rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1601	else
1602	rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1603	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1604
1605	return rc;
1606	}
1607
1608	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1609
1610	/**
1611	* Returns suspend status of the host.
1612	*
1613	* @returns Suspend pending or not.
1614	*/
1615	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1616	{
1617	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1618	}
1619
1620
1621	/**
1622	* Invalidates a guest page from the host TLB.
1623	*
1624	* @param pVCpu The cross context virtual CPU structure.
1625	* @param GCVirt Page to invalidate.
1626	*/
1627	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1628	{
1629	PVM pVM = pVCpu->CTX_SUFF(pVM);
1630	if (pVM->hm.s.vmx.fSupported)
1631	return VMXR0InvalidatePage(pVCpu, GCVirt);
1632	return SVMR0InvalidatePage(pVCpu, GCVirt);
1633	}
1634
1635
1636	/**
1637	* Returns the cpu structure for the current cpu.
1638	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1639	*
1640	* @returns The cpu structure pointer.
1641	*/
1642	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1643	{
1644	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1645	RTCPUID const idCpu = RTMpCpuId();
1646	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1647	return &g_HmR0.aCpuInfo[idCpu];
1648	}
1649
1650
1651	/**
1652	* Interface for importing state on demand (used by IEM).
1653	*
1654	* @returns VBox status code.
1655	* @param pVCpu The cross context CPU structure.
1656	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1657	*/
1658	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
1659	{
1660	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1661	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1662	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1663	}
1664
1665	#ifdef VBOX_STRICT
1666
1667	/**
1668	* Dumps a descriptor.
1669	*
1670	* @param pDesc Descriptor to dump.
1671	* @param Sel Selector number.
1672	* @param pszMsg Message to prepend the log entry with.
1673	*/
1674	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1675	{
1676	/*
1677	* Make variable description string.
1678	*/
1679	static struct
1680	{
1681	unsigned cch;
1682	const char *psz;
1683	} const s_aTypes[32] =
1684	{
1685	# define STRENTRY(str) { sizeof(str) - 1, str }
1686
1687	/* system */
1688	# if HC_ARCH_BITS == 64
1689	STRENTRY("Reserved0 "), /* 0x00 */
1690	STRENTRY("Reserved1 "), /* 0x01 */
1691	STRENTRY("LDT "), /* 0x02 */
1692	STRENTRY("Reserved3 "), /* 0x03 */
1693	STRENTRY("Reserved4 "), /* 0x04 */
1694	STRENTRY("Reserved5 "), /* 0x05 */
1695	STRENTRY("Reserved6 "), /* 0x06 */
1696	STRENTRY("Reserved7 "), /* 0x07 */
1697	STRENTRY("Reserved8 "), /* 0x08 */
1698	STRENTRY("TSS64Avail "), /* 0x09 */
1699	STRENTRY("ReservedA "), /* 0x0a */
1700	STRENTRY("TSS64Busy "), /* 0x0b */
1701	STRENTRY("Call64 "), /* 0x0c */
1702	STRENTRY("ReservedD "), /* 0x0d */
1703	STRENTRY("Int64 "), /* 0x0e */
1704	STRENTRY("Trap64 "), /* 0x0f */
1705	# else
1706	STRENTRY("Reserved0 "), /* 0x00 */
1707	STRENTRY("TSS16Avail "), /* 0x01 */
1708	STRENTRY("LDT "), /* 0x02 */
1709	STRENTRY("TSS16Busy "), /* 0x03 */
1710	STRENTRY("Call16 "), /* 0x04 */
1711	STRENTRY("Task "), /* 0x05 */
1712	STRENTRY("Int16 "), /* 0x06 */
1713	STRENTRY("Trap16 "), /* 0x07 */
1714	STRENTRY("Reserved8 "), /* 0x08 */
1715	STRENTRY("TSS32Avail "), /* 0x09 */
1716	STRENTRY("ReservedA "), /* 0x0a */
1717	STRENTRY("TSS32Busy "), /* 0x0b */
1718	STRENTRY("Call32 "), /* 0x0c */
1719	STRENTRY("ReservedD "), /* 0x0d */
1720	STRENTRY("Int32 "), /* 0x0e */
1721	STRENTRY("Trap32 "), /* 0x0f */
1722	# endif
1723	/* non system */
1724	STRENTRY("DataRO "), /* 0x10 */
1725	STRENTRY("DataRO Accessed "), /* 0x11 */
1726	STRENTRY("DataRW "), /* 0x12 */
1727	STRENTRY("DataRW Accessed "), /* 0x13 */
1728	STRENTRY("DataDownRO "), /* 0x14 */
1729	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1730	STRENTRY("DataDownRW "), /* 0x16 */
1731	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1732	STRENTRY("CodeEO "), /* 0x18 */
1733	STRENTRY("CodeEO Accessed "), /* 0x19 */
1734	STRENTRY("CodeER "), /* 0x1a */
1735	STRENTRY("CodeER Accessed "), /* 0x1b */
1736	STRENTRY("CodeConfEO "), /* 0x1c */
1737	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1738	STRENTRY("CodeConfER "), /* 0x1e */
1739	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1740	# undef SYSENTRY
1741	};
1742	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1743	char szMsg[128];
1744	char *psz = &szMsg[0];
1745	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1746	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1747	psz += s_aTypes[i].cch;
1748
1749	if (pDesc->Gen.u1Present)
1750	ADD_STR(psz, "Present ");
1751	else
1752	ADD_STR(psz, "Not-Present ");
1753	# if HC_ARCH_BITS == 64
1754	if (pDesc->Gen.u1Long)
1755	ADD_STR(psz, "64-bit ");
1756	else
1757	ADD_STR(psz, "Comp ");
1758	# else
1759	if (pDesc->Gen.u1Granularity)
1760	ADD_STR(psz, "Page ");
1761	if (pDesc->Gen.u1DefBig)
1762	ADD_STR(psz, "32-bit ");
1763	else
1764	ADD_STR(psz, "16-bit ");
1765	# endif
1766	# undef ADD_STR
1767	*psz = '\0';
1768
1769	/*
1770	* Limit and Base and format the output.
1771	*/
1772	#ifdef LOG_ENABLED
1773	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1774
1775	# if HC_ARCH_BITS == 64
1776	uint64_t u32Base = X86DESC64_BASE(pDesc);
1777	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1778	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1779	# else
1780	uint32_t u32Base = X86DESC_BASE(pDesc);
1781	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1782	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1783	# endif
1784	#else
1785	NOREF(Sel); NOREF(pszMsg);
1786	#endif
1787	}
1788
1789
1790	/**
1791	* Formats a full register dump.
1792	*
1793	* @param pVCpu The cross context virtual CPU structure.
1794	*/
1795	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu)
1796	{
1797	/*
1798	* Format the flags.
1799	*/
1800	static struct
1801	{
1802	const char pszSet; const char pszClear; uint32_t fFlag;
1803	} const s_aFlags[] =
1804	{
1805	{ "vip", NULL, X86_EFL_VIP },
1806	{ "vif", NULL, X86_EFL_VIF },
1807	{ "ac", NULL, X86_EFL_AC },
1808	{ "vm", NULL, X86_EFL_VM },
1809	{ "rf", NULL, X86_EFL_RF },
1810	{ "nt", NULL, X86_EFL_NT },
1811	{ "ov", "nv", X86_EFL_OF },
1812	{ "dn", "up", X86_EFL_DF },
1813	{ "ei", "di", X86_EFL_IF },
1814	{ "tf", NULL, X86_EFL_TF },
1815	{ "nt", "pl", X86_EFL_SF },
1816	{ "nz", "zr", X86_EFL_ZF },
1817	{ "ac", "na", X86_EFL_AF },
1818	{ "po", "pe", X86_EFL_PF },
1819	{ "cy", "nc", X86_EFL_CF },
1820	};
1821	char szEFlags[80];
1822	char *psz = szEFlags;
1823	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1824	uint32_t uEFlags = pCtx->eflags.u32;
1825	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1826	{
1827	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1828	if (pszAdd)
1829	{
1830	strcpy(psz, pszAdd);
1831	psz += strlen(pszAdd);
1832	*psz++ = ' ';
1833	}
1834	}
1835	psz[-1] = '\0';
1836
1837	/*
1838	* Format the registers.
1839	*/
1840	if (CPUMIsGuestIn64BitCode(pVCpu))
1841	{
1842	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1843	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1844	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1845	"r14=%016RX64 r15=%016RX64\n"
1846	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1847	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1848	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1849	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1850	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1851	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1852	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1853	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1854	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1855	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1856	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1857	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1858	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1859	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1860	,
1861	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1862	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1863	pCtx->r14, pCtx->r15,
1864	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1865	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1866	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1867	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1868	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1869	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1870	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1871	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1872	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1873	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1874	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1875	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1876	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1877	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1878	}
1879	else
1880	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1881	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1882	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1883	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1884	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1885	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1886	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1887	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1888	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1889	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1890	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1891	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1892	,
1893	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1894	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1895	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1896	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1897	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1898	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1899	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1900	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1901	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1902	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1903	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1904	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1905
1906	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1907	Log(("FPU:\n"
1908	"FCW=%04x FSW=%04x FTW=%02x\n"
1909	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1910	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1911	,
1912	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1913	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1914	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1915	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1916
1917	Log(("MSR:\n"
1918	"EFER =%016RX64\n"
1919	"PAT =%016RX64\n"
1920	"STAR =%016RX64\n"
1921	"CSTAR =%016RX64\n"
1922	"LSTAR =%016RX64\n"
1923	"SFMASK =%016RX64\n"
1924	"KERNELGSBASE =%016RX64\n",
1925	pCtx->msrEFER,
1926	pCtx->msrPAT,
1927	pCtx->msrSTAR,
1928	pCtx->msrCSTAR,
1929	pCtx->msrLSTAR,
1930	pCtx->msrSFMASK,
1931	pCtx->msrKERNELGSBASE));
1932
1933	NOREF(pFpuCtx);
1934	}
1935
1936	#endif /* VBOX_STRICT */
1937

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 80047

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