HMR0.cpp@ 87519

Last change on this file since 87519 was 87519, checked in by vboxsync, 4 years ago
VMM/HM: Make a R0 copy of HM::cMaxResumeLoopsCfg and do proper validation. bugref:9217
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1	/* $Id: HMR0.cpp 87519 2021-02-01 21:17:51Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vmcc.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/hmvmxinline.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMPHYSCPU aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnCallRing3Callback, (PVMCPUCC pVCpu, VMMCALLRING3 enmOperation));
92	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu));
93	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM));
100	/** @} */
101
102	/** Hardware-virtualization data. */
103	struct
104	{
105	union
106	{
107	/** VT-x data. */
108	struct
109	{
110	/** Host CR4 value (set by ring-0 VMX init) */
111	uint64_t u64HostCr4;
112	/** Host EFER value (set by ring-0 VMX init) */
113	uint64_t u64HostMsrEfer;
114	/** Host SMM monitor control (used for logging/diagnostics) */
115	uint64_t u64HostSmmMonitorCtl;
116	/** Last instruction error. */
117	uint32_t ulLastInstrError;
118	/** The shift mask employed by the VMX-Preemption timer. */
119	uint8_t cPreemptTimerShift;
120	/** Padding. */
121	uint8_t abPadding[3];
122	/** Whether we're using the preemption timer or not. */
123	bool fUsePreemptTimer;
124	/** Whether we're using SUPR0EnableVTx or not. */
125	bool fUsingSUPR0EnableVTx;
126	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
127	* module termination. */
128	bool fCalledSUPR0EnableVTx;
129	/** Set to by us to indicate VMX is supported by the CPU. */
130	bool fSupported;
131	} vmx;
132
133	/** AMD-V data. */
134	struct
135	{
136	/** SVM revision. */
137	uint32_t u32Rev;
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140	/** Padding. */
141	bool afPadding[3];
142	/** Set by us to indicate SVM is supported by the CPU. */
143	bool fSupported;
144	} svm;
145	} u;
146	/** Maximum allowed ASID/VPID (inclusive). */
147	uint32_t uMaxAsid;
148	/** MSRs. */
149	SUPHWVIRTMSRS Msrs;
150	} hwvirt;
151
152	/** Last recorded error code during HM ring-0 init. */
153	int32_t rcInit;
154
155	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
156	* enabled and disabled each time it's used to execute guest code. */
157	bool fGlobalInit;
158	/** Indicates whether the host is suspending or not. We'll refuse a few
159	* actions when the host is being suspended to speed up the suspending and
160	* avoid trouble. */
161	bool volatile fSuspended;
162
163	/** Whether we've already initialized all CPUs.
164	* @remarks We could check the EnableAllCpusOnce state, but this is
165	* simpler and hopefully easier to understand. */
166	bool fEnabled;
167	/** Serialize initialization in HMR0EnableAllCpus. */
168	RTONCE EnableAllCpusOnce;
169	} g_HmR0;
170
171
172	/**
173	* Initializes a first return code structure.
174	*
175	* @param pFirstRc The structure to init.
176	*/
177	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
178	{
179	pFirstRc->rc = VINF_SUCCESS;
180	pFirstRc->idCpu = NIL_RTCPUID;
181	}
182
183
184	/**
185	* Try set the status code (success ignored).
186	*
187	* @param pFirstRc The first return code structure.
188	* @param rc The status code.
189	*/
190	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
191	{
192	if ( RT_FAILURE(rc)
193	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
194	pFirstRc->idCpu = RTMpCpuId();
195	}
196
197
198	/**
199	* Get the status code of a first return code structure.
200	*
201	* @returns The status code; VINF_SUCCESS or error status, no informational or
202	* warning errors.
203	* @param pFirstRc The first return code structure.
204	*/
205	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
206	{
207	return pFirstRc->rc;
208	}
209
210
211	#ifdef VBOX_STRICT
212	# ifndef DEBUG_bird
213	/**
214	* Get the CPU ID on which the failure status code was reported.
215	*
216	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
217	* @param pFirstRc The first return code structure.
218	*/
219	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
220	{
221	return pFirstRc->idCpu;
222	}
223	# endif
224	#endif /* VBOX_STRICT */
225
226
227	/** @name Dummy callback handlers.
228	* @{ */
229
230	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu)
231	{
232	RT_NOREF1(pVCpu);
233	return VINF_SUCCESS;
234	}
235
236	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
237	{
238	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
239	}
240
241	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
242	bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
243	{
244	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
245	return VINF_SUCCESS;
246	}
247
248	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
249	{
250	RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM)
255	{
256	RT_NOREF1(pVM);
257	return VINF_SUCCESS;
258	}
259
260	static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM)
261	{
262	RT_NOREF1(pVM);
263	return VINF_SUCCESS;
264	}
265
266	static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM)
267	{
268	RT_NOREF1(pVM);
269	return VINF_SUCCESS;
270	}
271
272	static DECLCALLBACK(int) hmR0DummyCallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
273	{
274	RT_NOREF2(pVCpu, enmOperation);
275	return VINF_SUCCESS;
276	}
277
278	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu)
279	{
280	RT_NOREF(pVCpu);
281	return VINF_SUCCESS;
282	}
283
284	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu)
285	{
286	RT_NOREF1(pVCpu);
287	return VINF_SUCCESS;
288	}
289
290	/** @} */
291
292
293	/**
294	* Intel specific initialization code.
295	*
296	* @returns VBox status code (will only fail if out of memory).
297	*/
298	static int hmR0InitIntel(void)
299	{
300	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
301	g_HmR0.hwvirt.Msrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
302
303	/*
304	* First try use native kernel API for controlling VT-x.
305	* (This is only supported by some Mac OS X kernels atm.)
306	*/
307	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
308	g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
309	if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
310	{
311	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
312	if (RT_SUCCESS(rc))
313	{
314	g_HmR0.hwvirt.u.vmx.fSupported = true;
315	rc = SUPR0EnableVTx(false /* fEnable */);
316	AssertLogRelRC(rc);
317	}
318	}
319	else
320	{
321	HMR0FIRSTRC FirstRc;
322	hmR0FirstRcInit(&FirstRc);
323	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
324	if (RT_SUCCESS(g_HmR0.rcInit))
325	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
326	}
327
328	if (RT_SUCCESS(g_HmR0.rcInit))
329	{
330	/* Read CR4 and EFER for logging/diagnostic purposes. */
331	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
332	g_HmR0.hwvirt.u.vmx.u64HostMsrEfer = ASMRdMsr(MSR_K6_EFER);
333
334	/* Get VMX MSRs for determining VMX features we can ultimately use. */
335	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_VT_X, false /* fForce */);
336
337	/*
338	* Nested KVM workaround: Intel SDM section 34.15.5 describes that
339	* MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
340	* table 35-2 says that this MSR is available if either VMX or SMX is supported.
341	*/
342	uint64_t const uVmxBasicMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Basic;
343	if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
344	g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
345
346	/* Initialize VPID - 16 bits ASID. */
347	g_HmR0.hwvirt.uMaxAsid = 0x10000; /* exclusive */
348
349	/*
350	* If the host OS has not enabled VT-x for us, try enter VMX root mode
351	* to really verify if VT-x is usable.
352	*/
353	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
354	{
355	/* Allocate a temporary VMXON region. */
356	RTR0MEMOBJ hScatchMemObj;
357	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
358	if (RT_FAILURE(rc))
359	{
360	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
361	return rc;
362	}
363	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
364	RTHCPHYS const HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
365	ASMMemZeroPage(pvScatchPage);
366
367	/* Set revision dword at the beginning of the VMXON structure. */
368	(uint32_t )pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
369
370	/* Make sure we don't get rescheduled to another CPU during this probe. */
371	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
372
373	/* Enable CR4.VMXE if it isn't already set. */
374	RTCCUINTREG const uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
375
376	/*
377	* The only way of checking if we're in VMX root mode or not is to try and enter it.
378	* There is no instruction or control bit that tells us if we're in VMX root mode.
379	* Therefore, try and enter VMX root mode here.
380	*/
381	rc = VMXEnable(HCPhysScratchPage);
382	if (RT_SUCCESS(rc))
383	{
384	g_HmR0.hwvirt.u.vmx.fSupported = true;
385	VMXDisable();
386	}
387	else
388	{
389	/*
390	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
391	* it will crash the host when we enter raw mode, because:
392	*
393	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
394	* this bit), and
395	* (b) turning off paging causes a #GP (unavoidable when switching
396	* from long to 32 bits mode or 32 bits to PAE).
397	*
398	* They should fix their code, but until they do we simply refuse to run.
399	*/
400	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
401	Assert(g_HmR0.hwvirt.u.vmx.fSupported == false);
402	}
403
404	/* Restore CR4.VMXE if it wasn't set prior to us setting it above. */
405	if (!(uOldCr4 & X86_CR4_VMXE))
406	SUPR0ChangeCR4(0 /* fOrMask */, ~(uint64_t)X86_CR4_VMXE);
407
408	/* Restore interrupts. */
409	ASMSetFlags(fEFlags);
410
411	RTR0MemObjFree(hScatchMemObj, false);
412	}
413
414	if (g_HmR0.hwvirt.u.vmx.fSupported)
415	{
416	rc = VMXR0GlobalInit();
417	if (RT_FAILURE(rc))
418	g_HmR0.rcInit = rc;
419
420	/*
421	* Install the VT-x methods.
422	*/
423	g_HmR0.pfnEnterSession = VMXR0Enter;
424	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
425	g_HmR0.pfnCallRing3Callback = VMXR0CallRing3Callback;
426	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
427	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
428	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
429	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
430	g_HmR0.pfnInitVM = VMXR0InitVM;
431	g_HmR0.pfnTermVM = VMXR0TermVM;
432	g_HmR0.pfnSetupVM = VMXR0SetupVM;
433
434	/*
435	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
436	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
437	*/
438	VMXCTLSMSR PinCtls;
439	PinCtls.u = g_HmR0.hwvirt.Msrs.u.vmx.u64PinCtls;
440	if (PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
441	{
442	uint64_t const uVmxMiscMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Misc;
443	g_HmR0.hwvirt.u.vmx.fUsePreemptTimer = true;
444	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = RT_BF_GET(uVmxMiscMsr, VMX_BF_MISC_PREEMPT_TIMER_TSC);
445	if (HMIsSubjectToVmxPreemptTimerErratum())
446	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
447	}
448	}
449	}
450	#ifdef LOG_ENABLED
451	else
452	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
453	#endif
454	return VINF_SUCCESS;
455	}
456
457
458	/**
459	* AMD-specific initialization code.
460	*
461	* @returns VBox status code (will only fail if out of memory).
462	*/
463	static int hmR0InitAmd(void)
464	{
465	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
466	int rc = SVMR0GlobalInit();
467	if (RT_FAILURE(rc))
468	{
469	g_HmR0.rcInit = rc;
470	return rc;
471	}
472
473	/*
474	* Install the AMD-V methods.
475	*/
476	g_HmR0.pfnEnterSession = SVMR0Enter;
477	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
478	g_HmR0.pfnCallRing3Callback = SVMR0CallRing3Callback;
479	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
480	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
481	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
482	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
483	g_HmR0.pfnInitVM = SVMR0InitVM;
484	g_HmR0.pfnTermVM = SVMR0TermVM;
485	g_HmR0.pfnSetupVM = SVMR0SetupVM;
486
487	/* Query AMD features. */
488	uint32_t u32Dummy;
489	ASMCpuId(0x8000000a, &g_HmR0.hwvirt.u.svm.u32Rev, &g_HmR0.hwvirt.uMaxAsid, &u32Dummy, &g_HmR0.hwvirt.u.svm.u32Features);
490
491	/*
492	* We need to check if AMD-V has been properly initialized on all CPUs.
493	* Some BIOSes might do a poor job.
494	*/
495	HMR0FIRSTRC FirstRc;
496	hmR0FirstRcInit(&FirstRc);
497	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
498	AssertRC(rc);
499	if (RT_SUCCESS(rc))
500	rc = hmR0FirstRcGetStatus(&FirstRc);
501	#ifndef DEBUG_bird
502	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
503	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
504	#endif
505	if (RT_SUCCESS(rc))
506	{
507	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_AMD_V, false /* fForce */);
508	g_HmR0.hwvirt.u.svm.fSupported = true;
509	}
510	else
511	{
512	g_HmR0.rcInit = rc;
513	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
514	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
515	}
516	return rc;
517	}
518
519
520	/**
521	* Does global Ring-0 HM initialization (at module init).
522	*
523	* @returns VBox status code.
524	*/
525	VMMR0_INT_DECL(int) HMR0Init(void)
526	{
527	/*
528	* Initialize the globals.
529	*/
530	g_HmR0.fEnabled = false;
531	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
532	g_HmR0.EnableAllCpusOnce = s_OnceInit;
533	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
534	{
535	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
536	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
537	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
538	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
539	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
540	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
541	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
542	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
543	#endif
544	}
545
546	/* Fill in all callbacks with placeholders. */
547	g_HmR0.pfnEnterSession = hmR0DummyEnter;
548	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
549	g_HmR0.pfnCallRing3Callback = hmR0DummyCallRing3Callback;
550	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
551	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
552	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
553	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
554	g_HmR0.pfnInitVM = hmR0DummyInitVM;
555	g_HmR0.pfnTermVM = hmR0DummyTermVM;
556	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
557
558	/* Default is global VT-x/AMD-V init. */
559	g_HmR0.fGlobalInit = true;
560
561	/*
562	* Make sure aCpuInfo is big enough for all the CPUs on this system.
563	*/
564	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
565	{
566	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
567	return VERR_TOO_MANY_CPUS;
568	}
569
570	/*
571	* Check for VT-x or AMD-V support.
572	* Return failure only in out-of-memory situations.
573	*/
574	uint32_t fCaps = 0;
575	int rc = SUPR0GetVTSupport(&fCaps);
576	if (RT_SUCCESS(rc))
577	{
578	if (fCaps & SUPVTCAPS_VT_X)
579	{
580	rc = hmR0InitIntel();
581	if (RT_FAILURE(rc))
582	return rc;
583	}
584	else
585	{
586	Assert(fCaps & SUPVTCAPS_AMD_V);
587	rc = hmR0InitAmd();
588	if (RT_FAILURE(rc))
589	return rc;
590	}
591	}
592	else
593	g_HmR0.rcInit = VERR_UNSUPPORTED_CPU;
594
595	/*
596	* Register notification callbacks that we can use to disable/enable CPUs
597	* when brought offline/online or suspending/resuming.
598	*/
599	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
600	{
601	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
602	AssertRC(rc);
603
604	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
605	AssertRC(rc);
606	}
607
608	/* We return success here because module init shall not fail if HM fails to initialize. */
609	return VINF_SUCCESS;
610	}
611
612
613	/**
614	* Does global Ring-0 HM termination (at module termination).
615	*
616	* @returns VBox status code.
617	*/
618	VMMR0_INT_DECL(int) HMR0Term(void)
619	{
620	int rc;
621	if ( g_HmR0.hwvirt.u.vmx.fSupported
622	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
623	{
624	/*
625	* Simple if the host OS manages VT-x.
626	*/
627	Assert(g_HmR0.fGlobalInit);
628
629	if (g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx)
630	{
631	rc = SUPR0EnableVTx(false /* fEnable */);
632	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = false;
633	}
634	else
635	rc = VINF_SUCCESS;
636
637	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
638	{
639	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
640	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
641	}
642	}
643	else
644	{
645	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
646
647	/* Doesn't really matter if this fails. */
648	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
649	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
650
651	/*
652	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
653	*/
654	if (g_HmR0.fGlobalInit)
655	{
656	HMR0FIRSTRC FirstRc;
657	hmR0FirstRcInit(&FirstRc);
658	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
659	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
660	if (RT_SUCCESS(rc))
661	rc = hmR0FirstRcGetStatus(&FirstRc);
662	}
663
664	/*
665	* Free the per-cpu pages used for VT-x and AMD-V.
666	*/
667	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
668	{
669	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
670	{
671	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
672	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
673	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
674	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
675	}
676	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
677	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
678	{
679	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
680	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
681	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
682	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
683	}
684	#endif
685	}
686	}
687
688	/** @todo This needs cleaning up. There's no matching
689	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
690	* should move into their respective modules. */
691	/* Finally, call global VT-x/AMD-V termination. */
692	if (g_HmR0.hwvirt.u.vmx.fSupported)
693	VMXR0GlobalTerm();
694	else if (g_HmR0.hwvirt.u.svm.fSupported)
695	SVMR0GlobalTerm();
696
697	return rc;
698	}
699
700
701	/**
702	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
703	* on a CPU.
704	*
705	* @param idCpu The identifier for the CPU the function is called on.
706	* @param pvUser1 Pointer to the first RC structure.
707	* @param pvUser2 Ignored.
708	*/
709	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
710	{
711	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
712	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
713	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
714	NOREF(idCpu); NOREF(pvUser2);
715
716	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
717	hmR0FirstRcSetStatus(pFirstRc, rc);
718	}
719
720
721	/**
722	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
723	* on a CPU.
724	*
725	* @param idCpu The identifier for the CPU the function is called on.
726	* @param pvUser1 Pointer to the first RC structure.
727	* @param pvUser2 Ignored.
728	*/
729	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
730	{
731	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
732	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
733	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
734	NOREF(idCpu); NOREF(pvUser2);
735
736	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
737	hmR0FirstRcSetStatus(pFirstRc, rc);
738	}
739
740
741	/**
742	* Enable VT-x or AMD-V on the current CPU
743	*
744	* @returns VBox status code.
745	* @param pVM The cross context VM structure. Can be NULL.
746	* @param idCpu The identifier for the CPU the function is called on.
747	*
748	* @remarks Maybe called with interrupts disabled!
749	*/
750	static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
751	{
752	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
753
754	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
755	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
756	Assert(!pHostCpu->fConfigured);
757	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
758
759	pHostCpu->idCpu = idCpu;
760	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
761
762	int rc;
763	if ( g_HmR0.hwvirt.u.vmx.fSupported
764	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
765	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.hwvirt.Msrs);
766	else
767	{
768	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
769	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.hwvirt.Msrs);
770	}
771	if (RT_SUCCESS(rc))
772	pHostCpu->fConfigured = true;
773	return rc;
774	}
775
776
777	/**
778	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
779	*
780	* @param idCpu The identifier for the CPU the function is called on.
781	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
782	* @param pvUser2 The 2nd user argument.
783	*/
784	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
785	{
786	PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */
787	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
788	AssertReturnVoid(g_HmR0.fGlobalInit);
789	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
790	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
791	}
792
793
794	/**
795	* RTOnce callback employed by HMR0EnableAllCpus.
796	*
797	* @returns VBox status code.
798	* @param pvUser Pointer to the VM.
799	*/
800	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
801	{
802	PVMCC pVM = (PVMCC)pvUser;
803
804	/*
805	* Indicate that we've initialized.
806	*
807	* Note! There is a potential race between this function and the suspend
808	* notification. Kind of unlikely though, so ignored for now.
809	*/
810	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
811	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
812
813	/*
814	* The global init variable is set by the first VM.
815	*/
816	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
817
818	#ifdef VBOX_STRICT
819	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
820	{
821	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
822	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
823	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
824	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
825	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
826	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
827	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
828	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
829	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
830	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
831	# endif
832	}
833	#endif
834
835	int rc;
836	if ( g_HmR0.hwvirt.u.vmx.fSupported
837	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
838	{
839	/*
840	* Global VT-x initialization API (only darwin for now).
841	*/
842	rc = SUPR0EnableVTx(true /* fEnable */);
843	if (RT_SUCCESS(rc))
844	{
845	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = true;
846	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
847	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
848	}
849	else
850	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
851	}
852	else
853	{
854	/*
855	* We're doing the job ourselves.
856	*/
857	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
858	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
859	{
860	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
861	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
862	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
863	#endif
864	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
865	{
866	/** @todo NUMA */
867	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
868	AssertLogRelRCReturn(rc, rc);
869
870	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
871	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
872	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
873
874	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
875	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
876	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
877
878	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
879	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
880	false /* executable R0 mapping */);
881	AssertLogRelRCReturn(rc, rc);
882
883	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
884	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
885	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
886
887	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
888	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
889	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
890	#endif
891	}
892	}
893
894	rc = VINF_SUCCESS;
895	}
896
897	if ( RT_SUCCESS(rc)
898	&& g_HmR0.fGlobalInit)
899	{
900	/* First time, so initialize each cpu/core. */
901	HMR0FIRSTRC FirstRc;
902	hmR0FirstRcInit(&FirstRc);
903	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
904	if (RT_SUCCESS(rc))
905	rc = hmR0FirstRcGetStatus(&FirstRc);
906	}
907
908	return rc;
909	}
910
911
912	/**
913	* Sets up HM on all cpus.
914	*
915	* @returns VBox status code.
916	* @param pVM The cross context VM structure.
917	*/
918	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM)
919	{
920	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
921	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
922	return VERR_HM_SUSPEND_PENDING;
923
924	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
925	}
926
927
928	/**
929	* Disable VT-x or AMD-V on the current CPU.
930	*
931	* @returns VBox status code.
932	* @param idCpu The identifier for the CPU this function is called on.
933	*
934	* @remarks Must be called with preemption disabled.
935	*/
936	static int hmR0DisableCpu(RTCPUID idCpu)
937	{
938	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
939
940	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
941	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
942	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
943	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
944	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
945	AssertRelease(idCpu == RTMpCpuId());
946
947	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
948	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
949	AssertPtr(pHostCpu->pvMemObj);
950	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
951
952	int rc;
953	if (pHostCpu->fConfigured)
954	{
955	rc = g_HmR0.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
956	AssertRCReturn(rc, rc);
957
958	pHostCpu->fConfigured = false;
959	pHostCpu->idCpu = NIL_RTCPUID;
960	}
961	else
962	rc = VINF_SUCCESS; /* nothing to do */
963	return rc;
964	}
965
966
967	/**
968	* Worker function passed to RTMpOnAll() that is to be called on the target
969	* CPUs.
970	*
971	* @param idCpu The identifier for the CPU the function is called on.
972	* @param pvUser1 The 1st user argument.
973	* @param pvUser2 Opaque pointer to the FirstRc.
974	*/
975	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
976	{
977	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
978	AssertReturnVoid(g_HmR0.fGlobalInit);
979	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
980	}
981
982
983	/**
984	* Worker function passed to RTMpOnSpecific() that is to be called on the target
985	* CPU.
986	*
987	* @param idCpu The identifier for the CPU the function is called on.
988	* @param pvUser1 Null, not used.
989	* @param pvUser2 Null, not used.
990	*/
991	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
992	{
993	NOREF(pvUser1);
994	NOREF(pvUser2);
995	hmR0DisableCpu(idCpu);
996	}
997
998
999	/**
1000	* Callback function invoked when a cpu goes online or offline.
1001	*
1002	* @param enmEvent The Mp event.
1003	* @param idCpu The identifier for the CPU the function is called on.
1004	* @param pvData Opaque data (PVMCC pointer).
1005	*/
1006	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1007	{
1008	NOREF(pvData);
1009	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1010
1011	/*
1012	* We only care about uninitializing a CPU that is going offline. When a
1013	* CPU comes online, the initialization is done lazily in HMR0Enter().
1014	*/
1015	switch (enmEvent)
1016	{
1017	case RTMPEVENT_OFFLINE:
1018	{
1019	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1020	RTThreadPreemptDisable(&PreemptState);
1021	if (idCpu == RTMpCpuId())
1022	{
1023	int rc = hmR0DisableCpu(idCpu);
1024	AssertRC(rc);
1025	RTThreadPreemptRestore(&PreemptState);
1026	}
1027	else
1028	{
1029	RTThreadPreemptRestore(&PreemptState);
1030	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1031	}
1032	break;
1033	}
1034
1035	default:
1036	break;
1037	}
1038	}
1039
1040
1041	/**
1042	* Called whenever a system power state change occurs.
1043	*
1044	* @param enmEvent The Power event.
1045	* @param pvUser User argument.
1046	*/
1047	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1048	{
1049	NOREF(pvUser);
1050	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1051
1052	#ifdef LOG_ENABLED
1053	if (enmEvent == RTPOWEREVENT_SUSPEND)
1054	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1055	else
1056	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1057	#endif
1058
1059	if (enmEvent == RTPOWEREVENT_SUSPEND)
1060	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1061
1062	if (g_HmR0.fEnabled)
1063	{
1064	int rc;
1065	HMR0FIRSTRC FirstRc;
1066	hmR0FirstRcInit(&FirstRc);
1067
1068	if (enmEvent == RTPOWEREVENT_SUSPEND)
1069	{
1070	if (g_HmR0.fGlobalInit)
1071	{
1072	/* Turn off VT-x or AMD-V on all CPUs. */
1073	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1074	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1075	}
1076	/* else nothing to do here for the local init case */
1077	}
1078	else
1079	{
1080	/* Reinit the CPUs from scratch as the suspend state might have
1081	messed with the MSRs. (lousy BIOSes as usual) */
1082	if (g_HmR0.hwvirt.u.vmx.fSupported)
1083	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1084	else
1085	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1086	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1087	if (RT_SUCCESS(rc))
1088	rc = hmR0FirstRcGetStatus(&FirstRc);
1089	#ifdef LOG_ENABLED
1090	if (RT_FAILURE(rc))
1091	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1092	#endif
1093	if (g_HmR0.fGlobalInit)
1094	{
1095	/* Turn VT-x or AMD-V back on on all CPUs. */
1096	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1097	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1098	}
1099	/* else nothing to do here for the local init case */
1100	}
1101	}
1102
1103	if (enmEvent == RTPOWEREVENT_RESUME)
1104	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1105	}
1106
1107
1108	/**
1109	* Does ring-0 per-VM HM initialization.
1110	*
1111	* This will call the CPU specific init. routine which may initialize and allocate
1112	* resources for virtual CPUs.
1113	*
1114	* @returns VBox status code.
1115	* @param pVM The cross context VM structure.
1116	*
1117	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1118	* vmR3InitRing3().
1119	*/
1120	VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM)
1121	{
1122	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1123
1124	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1125	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1126	return VERR_HM_SUSPEND_PENDING;
1127
1128	/*
1129	* Copy globals to the VM structure.
1130	*/
1131	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1132	if (pVM->hm.s.vmx.fSupported)
1133	{
1134	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.hwvirt.u.vmx.fUsePreemptTimer; /* Can be overridden by CFGM in HMR3Init(). */
1135	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.hwvirt.u.vmx.cPreemptTimerShift;
1136	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.hwvirt.u.vmx.u64HostCr4;
1137	pVM->hm.s.vmx.u64HostMsrEfer = g_HmR0.hwvirt.u.vmx.u64HostMsrEfer;
1138	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl;
1139	HMGetVmxMsrsFromHwvirtMsrs(&g_HmR0.hwvirt.Msrs, &pVM->hm.s.vmx.Msrs);
1140	/* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
1141
1142	/* Enable VPID if supported and configured. */
1143	if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1144	pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
1145
1146	/* Use VMCS shadowing if supported. */
1147	Assert(!pVM->hm.s.vmx.fUseVmcsShadowing);
1148	if ( pVM->cpum.ro.GuestFeatures.fVmx
1149	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING))
1150	pVM->hm.s.vmx.fUseVmcsShadowing = true;
1151
1152	/* Use the VMCS controls for swapping the EFER MSR if supported. */
1153	Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
1154	if ( (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
1155	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1156	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
1157	pVM->hm.s.vmx.fSupportsVmcsEfer = true;
1158
1159	#if 0
1160	/* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
1161	if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1162	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1163	pVM->hm.s.fVirtApicRegs = true;
1164
1165	/* Enable posted-interrupt processing if supported. */
1166	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1167	* here. */
1168	if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1169	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1170	pVM->hm.s.fPostedIntrs = true;
1171	#endif
1172	}
1173	else if (pVM->hm.s.svm.fSupported)
1174	{
1175	pVM->hm.s.svm.u32Rev = g_HmR0.hwvirt.u.svm.u32Rev;
1176	pVM->hm.s.svm.fFeaturesForRing3 = pVM->hmr0.s.svm.fFeatures = g_HmR0.hwvirt.u.svm.u32Features;
1177	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.hwvirt.Msrs.u.svm.u64MsrHwcr;
1178	/* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
1179	}
1180	pVM->hm.s.rcInit = g_HmR0.rcInit;
1181	pVM->hm.s.uMaxAsid = g_HmR0.hwvirt.uMaxAsid;
1182
1183	/*
1184	* Set default maximum inner loops in ring-0 before returning to ring-3.
1185	* Can be overriden using CFGM.
1186	*/
1187	uint32_t cMaxResumeLoops = pVM->hm.s.cMaxResumeLoopsCfg;
1188	if (!cMaxResumeLoops)
1189	{
1190	cMaxResumeLoops = 1024;
1191	if (RTThreadPreemptIsPendingTrusty())
1192	cMaxResumeLoops = 8192;
1193	}
1194	else if (cMaxResumeLoops > 16384)
1195	cMaxResumeLoops = 16384;
1196	else if (cMaxResumeLoops < 32)
1197	cMaxResumeLoops = 32;
1198	pVM->hm.s.cMaxResumeLoopsCfg = pVM->hmr0.s.cMaxResumeLoops = cMaxResumeLoops;
1199
1200	/*
1201	* Initialize some per-VCPU fields.
1202	*/
1203	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1204	{
1205	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1206	pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1207	pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1208
1209	/* We'll aways increment this the first time (host uses ASID 0). */
1210	AssertReturn(!pVCpu->hmr0.s.uCurrentAsid, VERR_HM_IPE_3);
1211	}
1212
1213	/*
1214	* Get host kernel features that HM might need to know in order
1215	* to co-operate and function properly with the host OS (e.g. SMAP).
1216	*
1217	* Technically, we could do this as part of the pre-init VM procedure
1218	* but it shouldn't be done later than this point so we do it here.
1219	*/
1220	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1221
1222	/*
1223	* Call the hardware specific initialization method.
1224	*/
1225	return g_HmR0.pfnInitVM(pVM);
1226	}
1227
1228
1229	/**
1230	* Does ring-0 per VM HM termination.
1231	*
1232	* @returns VBox status code.
1233	* @param pVM The cross context VM structure.
1234	*/
1235	VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM)
1236	{
1237	Log(("HMR0TermVM: %p\n", pVM));
1238	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1239
1240	/*
1241	* Call the hardware specific method.
1242	*
1243	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1244	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1245	*/
1246	return g_HmR0.pfnTermVM(pVM);
1247	}
1248
1249
1250	/**
1251	* Sets up a VT-x or AMD-V session.
1252	*
1253	* This is mostly about setting up the hardware VM state.
1254	*
1255	* @returns VBox status code.
1256	* @param pVM The cross context VM structure.
1257	*/
1258	VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM)
1259	{
1260	Log(("HMR0SetupVM: %p\n", pVM));
1261	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1262
1263	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1264	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1265
1266	/* On first entry we'll sync everything. */
1267	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1268
1269	/*
1270	* Call the hardware specific setup VM method. This requires the CPU to be
1271	* enabled for AMD-V/VT-x and preemption to be prevented.
1272	*/
1273	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1274	RTThreadPreemptDisable(&PreemptState);
1275	RTCPUID const idCpu = RTMpCpuId();
1276
1277	/* Enable VT-x or AMD-V if local init is required. */
1278	int rc;
1279	if (!g_HmR0.fGlobalInit)
1280	{
1281	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1282	rc = hmR0EnableCpu(pVM, idCpu);
1283	if (RT_FAILURE(rc))
1284	{
1285	RTThreadPreemptRestore(&PreemptState);
1286	return rc;
1287	}
1288	}
1289
1290	/* Setup VT-x or AMD-V. */
1291	rc = g_HmR0.pfnSetupVM(pVM);
1292
1293	/* Disable VT-x or AMD-V if local init was done before. */
1294	if (!g_HmR0.fGlobalInit)
1295	{
1296	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1297	int rc2 = hmR0DisableCpu(idCpu);
1298	AssertRC(rc2);
1299	}
1300
1301	RTThreadPreemptRestore(&PreemptState);
1302	return rc;
1303	}
1304
1305
1306	/**
1307	* Notification callback before performing a longjump to ring-3.
1308	*
1309	* @returns VBox status code.
1310	* @param pVCpu The cross context virtual CPU structure.
1311	* @param enmOperation The operation causing the ring-3 longjump.
1312	* @param pvUser User argument, currently unused, NULL.
1313	*/
1314	static DECLCALLBACK(int) hmR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1315	{
1316	RT_NOREF(pvUser);
1317	Assert(pVCpu);
1318	Assert(g_HmR0.pfnCallRing3Callback);
1319	return g_HmR0.pfnCallRing3Callback(pVCpu, enmOperation);
1320	}
1321
1322
1323	/**
1324	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1325	* required for entering HM context.
1326	*
1327	* @returns VBox status code.
1328	* @param pVCpu The cross context virtual CPU structure.
1329	*
1330	* @remarks No-long-jump zone!!!
1331	*/
1332	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu)
1333	{
1334	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1335
1336	int rc = VINF_SUCCESS;
1337	RTCPUID const idCpu = RTMpCpuId();
1338	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1339	AssertPtr(pHostCpu);
1340
1341	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1342	if (!pHostCpu->fConfigured)
1343	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1344
1345	/* Register a callback to fire prior to performing a longjmp to ring-3 so HM can disable VT-x/AMD-V if needed. */
1346	VMMRZCallRing3SetNotification(pVCpu, hmR0CallRing3Callback, NULL /* pvUser */);
1347
1348	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1349	if (g_HmR0.hwvirt.u.vmx.fSupported)
1350	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1351	else
1352	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1353
1354	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1355	pVCpu->hmr0.s.idEnteredCpu = idCpu;
1356	return rc;
1357	}
1358
1359
1360	/**
1361	* Enters the VT-x or AMD-V session.
1362	*
1363	* @returns VBox status code.
1364	* @param pVCpu The cross context virtual CPU structure.
1365	*
1366	* @remarks This is called with preemption disabled.
1367	*/
1368	VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu)
1369	{
1370	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1371	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1372	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1373
1374	/* Load the bare minimum state required for entering HM. */
1375	int rc = hmR0EnterCpu(pVCpu);
1376	if (RT_SUCCESS(rc))
1377	{
1378	if (g_HmR0.hwvirt.u.vmx.fSupported)
1379	{
1380	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1381	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1382	}
1383	else
1384	{
1385	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1386	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1387	}
1388
1389	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1390	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1391	bool const fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1392	#endif
1393
1394	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1395	rc = g_HmR0.pfnEnterSession(pVCpu);
1396	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1397
1398	/* Exports the host-state as we may be resuming code after a longjmp and quite
1399	possibly now be scheduled on a different CPU. */
1400	rc = g_HmR0.pfnExportHostState(pVCpu);
1401	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1402
1403	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1404	if (fStartedSet)
1405	PGMRZDynMapReleaseAutoSet(pVCpu);
1406	#endif
1407	}
1408	return rc;
1409	}
1410
1411
1412	/**
1413	* Deinitializes the bare minimum state used for HM context and if necessary
1414	* disable HM on the CPU.
1415	*
1416	* @returns VBox status code.
1417	* @param pVCpu The cross context virtual CPU structure.
1418	*
1419	* @remarks No-long-jump zone!!!
1420	*/
1421	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu)
1422	{
1423	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1424	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1425
1426	RTCPUID const idCpu = RTMpCpuId();
1427	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1428
1429	if ( !g_HmR0.fGlobalInit
1430	&& pHostCpu->fConfigured)
1431	{
1432	int rc = hmR0DisableCpu(idCpu);
1433	AssertRCReturn(rc, rc);
1434	Assert(!pHostCpu->fConfigured);
1435	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1436
1437	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1438	pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1439	}
1440
1441	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1442	pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1443
1444	/* De-register the longjmp-to-ring 3 callback now that we have reliquished hardware resources. */
1445	VMMRZCallRing3RemoveNotification(pVCpu);
1446	return VINF_SUCCESS;
1447	}
1448
1449
1450	/**
1451	* Thread-context hook for HM.
1452	*
1453	* @param enmEvent The thread-context event.
1454	* @param pvUser Opaque pointer to the VMCPU.
1455	*/
1456	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1457	{
1458	PVMCPUCC pVCpu = (PVMCPUCC)pvUser;
1459	Assert(pVCpu);
1460	Assert(g_HmR0.pfnThreadCtxCallback);
1461
1462	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1463	}
1464
1465
1466	/**
1467	* Runs guest code in a hardware accelerated VM.
1468	*
1469	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1470	* called from setjmp assembly.)
1471	* @param pVM The cross context VM structure.
1472	* @param pVCpu The cross context virtual CPU structure.
1473	*
1474	* @remarks Can be called with preemption enabled if thread-context hooks are
1475	* used!!!
1476	*/
1477	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu)
1478	{
1479	RT_NOREF(pVM);
1480
1481	#ifdef VBOX_STRICT
1482	/* With thread-context hooks we would be running this code with preemption enabled. */
1483	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1484	{
1485	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1486	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1487	Assert(pHostCpu->fConfigured);
1488	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1489	}
1490	#endif
1491
1492	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1493	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1494	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1495	PGMRZDynMapStartAutoSet(pVCpu);
1496	#endif
1497
1498	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1499
1500	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1501	PGMRZDynMapReleaseAutoSet(pVCpu);
1502	#endif
1503	return VBOXSTRICTRC_VAL(rcStrict);
1504	}
1505
1506
1507	/**
1508	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1509	* the host CPU and that guest access to it must be intercepted.
1510	*
1511	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1512	*/
1513	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu)
1514	{
1515	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1516	}
1517
1518
1519	/**
1520	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1521	*
1522	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1523	*/
1524	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu)
1525	{
1526	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1527	}
1528
1529
1530	/**
1531	* Returns suspend status of the host.
1532	*
1533	* @returns Suspend pending or not.
1534	*/
1535	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1536	{
1537	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1538	}
1539
1540
1541	/**
1542	* Invalidates a guest page from the host TLB.
1543	*
1544	* @param pVCpu The cross context virtual CPU structure.
1545	* @param GCVirt Page to invalidate.
1546	*/
1547	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1548	{
1549	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1550	if (pVM->hm.s.vmx.fSupported)
1551	return VMXR0InvalidatePage(pVCpu, GCVirt);
1552	return SVMR0InvalidatePage(pVCpu, GCVirt);
1553	}
1554
1555
1556	/**
1557	* Returns the cpu structure for the current cpu.
1558	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1559	*
1560	* @returns The cpu structure pointer.
1561	*/
1562	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1563	{
1564	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1565	RTCPUID const idCpu = RTMpCpuId();
1566	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1567	return &g_HmR0.aCpuInfo[idCpu];
1568	}
1569
1570
1571	/**
1572	* Interface for importing state on demand (used by IEM).
1573	*
1574	* @returns VBox status code.
1575	* @param pVCpu The cross context CPU structure.
1576	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1577	*/
1578	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1579	{
1580	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1581	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1582	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1583	}
1584
1585	#ifdef VBOX_STRICT
1586
1587	/**
1588	* Dumps a descriptor.
1589	*
1590	* @param pDesc Descriptor to dump.
1591	* @param Sel The selector.
1592	* @param pszSel The name of the selector.
1593	*/
1594	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel)
1595	{
1596	/*
1597	* Make variable description string.
1598	*/
1599	static struct
1600	{
1601	unsigned cch;
1602	const char *psz;
1603	} const s_aTypes[32] =
1604	{
1605	# define STRENTRY(str) { sizeof(str) - 1, str }
1606
1607	/* system */
1608	# if HC_ARCH_BITS == 64
1609	STRENTRY("Reserved0 "), /* 0x00 */
1610	STRENTRY("Reserved1 "), /* 0x01 */
1611	STRENTRY("LDT "), /* 0x02 */
1612	STRENTRY("Reserved3 "), /* 0x03 */
1613	STRENTRY("Reserved4 "), /* 0x04 */
1614	STRENTRY("Reserved5 "), /* 0x05 */
1615	STRENTRY("Reserved6 "), /* 0x06 */
1616	STRENTRY("Reserved7 "), /* 0x07 */
1617	STRENTRY("Reserved8 "), /* 0x08 */
1618	STRENTRY("TSS64Avail "), /* 0x09 */
1619	STRENTRY("ReservedA "), /* 0x0a */
1620	STRENTRY("TSS64Busy "), /* 0x0b */
1621	STRENTRY("Call64 "), /* 0x0c */
1622	STRENTRY("ReservedD "), /* 0x0d */
1623	STRENTRY("Int64 "), /* 0x0e */
1624	STRENTRY("Trap64 "), /* 0x0f */
1625	# else
1626	STRENTRY("Reserved0 "), /* 0x00 */
1627	STRENTRY("TSS16Avail "), /* 0x01 */
1628	STRENTRY("LDT "), /* 0x02 */
1629	STRENTRY("TSS16Busy "), /* 0x03 */
1630	STRENTRY("Call16 "), /* 0x04 */
1631	STRENTRY("Task "), /* 0x05 */
1632	STRENTRY("Int16 "), /* 0x06 */
1633	STRENTRY("Trap16 "), /* 0x07 */
1634	STRENTRY("Reserved8 "), /* 0x08 */
1635	STRENTRY("TSS32Avail "), /* 0x09 */
1636	STRENTRY("ReservedA "), /* 0x0a */
1637	STRENTRY("TSS32Busy "), /* 0x0b */
1638	STRENTRY("Call32 "), /* 0x0c */
1639	STRENTRY("ReservedD "), /* 0x0d */
1640	STRENTRY("Int32 "), /* 0x0e */
1641	STRENTRY("Trap32 "), /* 0x0f */
1642	# endif
1643	/* non system */
1644	STRENTRY("DataRO "), /* 0x10 */
1645	STRENTRY("DataRO Accessed "), /* 0x11 */
1646	STRENTRY("DataRW "), /* 0x12 */
1647	STRENTRY("DataRW Accessed "), /* 0x13 */
1648	STRENTRY("DataDownRO "), /* 0x14 */
1649	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1650	STRENTRY("DataDownRW "), /* 0x16 */
1651	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1652	STRENTRY("CodeEO "), /* 0x18 */
1653	STRENTRY("CodeEO Accessed "), /* 0x19 */
1654	STRENTRY("CodeER "), /* 0x1a */
1655	STRENTRY("CodeER Accessed "), /* 0x1b */
1656	STRENTRY("CodeConfEO "), /* 0x1c */
1657	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1658	STRENTRY("CodeConfER "), /* 0x1e */
1659	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1660	# undef SYSENTRY
1661	};
1662	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1663	char szMsg[128];
1664	char *psz = &szMsg[0];
1665	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1666	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1667	psz += s_aTypes[i].cch;
1668
1669	if (pDesc->Gen.u1Present)
1670	ADD_STR(psz, "Present ");
1671	else
1672	ADD_STR(psz, "Not-Present ");
1673	# if HC_ARCH_BITS == 64
1674	if (pDesc->Gen.u1Long)
1675	ADD_STR(psz, "64-bit ");
1676	else
1677	ADD_STR(psz, "Comp ");
1678	# else
1679	if (pDesc->Gen.u1Granularity)
1680	ADD_STR(psz, "Page ");
1681	if (pDesc->Gen.u1DefBig)
1682	ADD_STR(psz, "32-bit ");
1683	else
1684	ADD_STR(psz, "16-bit ");
1685	# endif
1686	# undef ADD_STR
1687	*psz = '\0';
1688
1689	/*
1690	* Limit and Base and format the output.
1691	*/
1692	#ifdef LOG_ENABLED
1693	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1694
1695	# if HC_ARCH_BITS == 64
1696	uint64_t const u64Base = X86DESC64_BASE(pDesc);
1697	Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel,
1698	Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1699	# else
1700	uint32_t const u32Base = X86DESC_BASE(pDesc);
1701	Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel,
1702	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1703	# endif
1704	#else
1705	NOREF(Sel); NOREF(pszSel);
1706	#endif
1707	}
1708
1709
1710	/**
1711	* Formats a full register dump.
1712	*
1713	* @param pVCpu The cross context virtual CPU structure.
1714	* @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX).
1715	*/
1716	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags)
1717	{
1718	/*
1719	* Format the flags.
1720	*/
1721	static struct
1722	{
1723	const char *pszSet;
1724	const char *pszClear;
1725	uint32_t fFlag;
1726	} const s_aFlags[] =
1727	{
1728	{ "vip", NULL, X86_EFL_VIP },
1729	{ "vif", NULL, X86_EFL_VIF },
1730	{ "ac", NULL, X86_EFL_AC },
1731	{ "vm", NULL, X86_EFL_VM },
1732	{ "rf", NULL, X86_EFL_RF },
1733	{ "nt", NULL, X86_EFL_NT },
1734	{ "ov", "nv", X86_EFL_OF },
1735	{ "dn", "up", X86_EFL_DF },
1736	{ "ei", "di", X86_EFL_IF },
1737	{ "tf", NULL, X86_EFL_TF },
1738	{ "nt", "pl", X86_EFL_SF },
1739	{ "nz", "zr", X86_EFL_ZF },
1740	{ "ac", "na", X86_EFL_AF },
1741	{ "po", "pe", X86_EFL_PF },
1742	{ "cy", "nc", X86_EFL_CF },
1743	};
1744	char szEFlags[80];
1745	char *psz = szEFlags;
1746	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1747	uint32_t uEFlags = pCtx->eflags.u32;
1748	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1749	{
1750	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1751	if (pszAdd)
1752	{
1753	strcpy(psz, pszAdd);
1754	psz += strlen(pszAdd);
1755	*psz++ = ' ';
1756	}
1757	}
1758	psz[-1] = '\0';
1759
1760	if (fFlags & HM_DUMP_REG_FLAGS_GPRS)
1761	{
1762	/*
1763	* Format the registers.
1764	*/
1765	if (CPUMIsGuestIn64BitCode(pVCpu))
1766	{
1767	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1768	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1769	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1770	"r14=%016RX64 r15=%016RX64\n"
1771	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1772	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1773	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1774	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1775	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1776	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1777	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1778	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1779	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1780	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1781	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1782	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1783	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1784	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1785	,
1786	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1787	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1788	pCtx->r14, pCtx->r15,
1789	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1790	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1791	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1792	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1793	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1794	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1795	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1796	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1797	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1798	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1799	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1800	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1801	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1802	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1803	}
1804	else
1805	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1806	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1807	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1808	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1809	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1810	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1811	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1812	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1813	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1814	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1815	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1816	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1817	,
1818	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1819	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1820	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1821	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1822	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1823	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1824	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1825	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1826	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1827	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1828	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1829	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1830	}
1831
1832	if (fFlags & HM_DUMP_REG_FLAGS_FPU)
1833	{
1834	PCX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1835	Log(("FPU:\n"
1836	"FCW=%04x FSW=%04x FTW=%02x\n"
1837	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1838	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1839	,
1840	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1841	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1842	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1843	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1844	NOREF(pFpuCtx);
1845	}
1846
1847	if (fFlags & HM_DUMP_REG_FLAGS_MSRS)
1848	{
1849	Log(("MSR:\n"
1850	"EFER =%016RX64\n"
1851	"PAT =%016RX64\n"
1852	"STAR =%016RX64\n"
1853	"CSTAR =%016RX64\n"
1854	"LSTAR =%016RX64\n"
1855	"SFMASK =%016RX64\n"
1856	"KERNELGSBASE =%016RX64\n",
1857	pCtx->msrEFER,
1858	pCtx->msrPAT,
1859	pCtx->msrSTAR,
1860	pCtx->msrCSTAR,
1861	pCtx->msrLSTAR,
1862	pCtx->msrSFMASK,
1863	pCtx->msrKERNELGSBASE));
1864	}
1865	}
1866
1867	#endif /* VBOX_STRICT */
1868

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 87519

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