HMR0.cpp@ 87543

Last change on this file since 87543 was 87543, checked in by vboxsync, 4 years ago
VMM/HMVMX: Use g_HmMsrs instead of pVM->hm.s.vmx.Msrs in ring-0, part 2. bugref:9217
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1	/* $Id: HMR0.cpp 87543 2021-02-02 17:00:24Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vmcc.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/hmvmxinline.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
54	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
55
56
57	/*********************************************************************************************************************************
58	* Structures and Typedefs *
59	*********************************************************************************************************************************/
60	/**
61	* This is used to manage the status code of a RTMpOnAll in HM.
62	*/
63	typedef struct HMR0FIRSTRC
64	{
65	/** The status code. */
66	int32_t volatile rc;
67	/** The ID of the CPU reporting the first failure. */
68	RTCPUID volatile idCpu;
69	} HMR0FIRSTRC;
70	/** Pointer to a first return code structure. */
71	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
72
73	/**
74	* Ring-0 method table for AMD-V and VT-x specific operations.
75	*/
76	typedef struct HMR0VTABLE
77	{
78	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu));
79	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit));
80	DECLR0CALLBACKMEMBER(int, pfnCallRing3Callback, (PVMCPUCC pVCpu, VMMCALLRING3 enmOperation));
81	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu));
82	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu));
83	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
84	bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
85	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
86	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM));
87	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM));
88	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM));
89	} HMR0VTABLE;
90
91
92	/*********************************************************************************************************************************
93	* Global Variables *
94	*********************************************************************************************************************************/
95	/** The active ring-0 HM operations (copied from one of the table at init). */
96	static HMR0VTABLE g_HmR0Ops;
97	/** Indicates whether the host is suspending or not. We'll refuse a few
98	* actions when the host is being suspended to speed up the suspending and
99	* avoid trouble. */
100	static bool volatile g_fHmSuspended;
101	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
102	* enabled and disabled each time it's used to execute guest code. */
103	static bool g_fHmGlobalInit;
104	/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
105	uint32_t g_fHmHostKernelFeatures;
106	/** Maximum allowed ASID/VPID (inclusive).
107	* @todo r=bird: This is exclusive for VT-x according to source code comment.
108	* Couldn't immediately find any docs on AMD-V, but suspect it is
109	* exclusive there as well given how hmR0SvmFlushTaggedTlb() use it. */
110	uint32_t g_uHmMaxAsid;
111
112
113	/** Set if VT-x (VMX) is supported by the CPU. */
114	bool g_fHmVmxSupported = false;
115	/** Whether we're using the preemption timer or not. */
116	bool g_fHmVmxUsePreemptTimer;
117	/** The shift mask employed by the VMX-Preemption timer. */
118	uint8_t g_cHmVmxPreemptTimerShift;
119	/** Whether we're using SUPR0EnableVTx or not. */
120	static bool g_fHmVmxUsingSUPR0EnableVTx = false;
121	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
122	* module termination. */
123	static bool g_fHmVmxCalledSUPR0EnableVTx = false;
124	/** Host CR4 value (set by ring-0 VMX init) */
125	uint64_t g_uHmVmxHostCr4;
126	/** Host EFER value (set by ring-0 VMX init) */
127	uint64_t g_uHmVmxHostMsrEfer;
128	/** Host SMM monitor control (used for logging/diagnostics) */
129	uint64_t g_uHmVmxHostSmmMonitorCtl;
130
131
132	/** Set if AMD-V is supported by the CPU. */
133	bool g_fHmSvmSupported = false;
134	/** SVM revision. */
135	uint32_t g_uHmSvmRev;
136	/** SVM feature bits from cpuid 0x8000000a */
137	uint32_t g_fHmSvmFeatures;
138
139
140	/** MSRs. */
141	SUPHWVIRTMSRS g_HmMsrs;
142
143	/** Last recorded error code during HM ring-0 init. */
144	static int32_t g_rcHmInit = VINF_SUCCESS;
145
146	/** Per CPU globals. */
147	static HMPHYSCPU g_aHmCpuInfo[RTCPUSET_MAX_CPUS];
148
149	/** Whether we've already initialized all CPUs.
150	* @remarks We could check the EnableAllCpusOnce state, but this is
151	* simpler and hopefully easier to understand. */
152	static bool g_fHmEnabled = false;
153	/** Serialize initialization in HMR0EnableAllCpus. */
154	static RTONCE g_HmEnableAllCpusOnce = RTONCE_INITIALIZER;
155
156
157	/** HM ring-0 operations for VT-x. */
158	static HMR0VTABLE const g_HmR0OpsVmx =
159	{
160	/* .pfnEnterSession = */ VMXR0Enter,
161	/* .pfnThreadCtxCallback = */ VMXR0ThreadCtxCallback,
162	/* .pfnCallRing3Callback = */ VMXR0CallRing3Callback,
163	/* .pfnExportHostState = */ VMXR0ExportHostState,
164	/* .pfnRunGuestCode = */ VMXR0RunGuestCode,
165	/* .pfnEnableCpu = */ VMXR0EnableCpu,
166	/* .pfnDisableCpu = */ VMXR0DisableCpu,
167	/* .pfnInitVM = */ VMXR0InitVM,
168	/* .pfnTermVM = */ VMXR0TermVM,
169	/* .pfnSetupVM = */ VMXR0SetupVM,
170	};
171
172	/** HM ring-0 operations for AMD-V. */
173	static HMR0VTABLE const g_HmR0OpsSvm =
174	{
175	/* .pfnEnterSession = */ SVMR0Enter,
176	/* .pfnThreadCtxCallback = */ SVMR0ThreadCtxCallback,
177	/* .pfnCallRing3Callback = */ SVMR0CallRing3Callback,
178	/* .pfnExportHostState = */ SVMR0ExportHostState,
179	/* .pfnRunGuestCode = */ SVMR0RunGuestCode,
180	/* .pfnEnableCpu = */ SVMR0EnableCpu,
181	/* .pfnDisableCpu = */ SVMR0DisableCpu,
182	/* .pfnInitVM = */ SVMR0InitVM,
183	/* .pfnTermVM = */ SVMR0TermVM,
184	/* .pfnSetupVM = */ SVMR0SetupVM,
185	};
186
187
188	/** @name Dummy callback handlers for when neither VT-x nor AMD-V is supported.
189	* @{ */
190
191	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu)
192	{
193	RT_NOREF(pVCpu);
194	return VINF_SUCCESS;
195	}
196
197	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
198	{
199	RT_NOREF(enmEvent, pVCpu, fGlobalInit);
200	}
201
202	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
203	bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
204	{
205	RT_NOREF(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
206	return VINF_SUCCESS;
207	}
208
209	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
210	{
211	RT_NOREF(pHostCpu, pvCpuPage, HCPhysCpuPage);
212	return VINF_SUCCESS;
213	}
214
215	static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM)
216	{
217	RT_NOREF(pVM);
218	return VINF_SUCCESS;
219	}
220
221	static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM)
222	{
223	RT_NOREF(pVM);
224	return VINF_SUCCESS;
225	}
226
227	static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM)
228	{
229	RT_NOREF(pVM);
230	return VINF_SUCCESS;
231	}
232
233	static DECLCALLBACK(int) hmR0DummyCallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
234	{
235	RT_NOREF(pVCpu, enmOperation);
236	return VINF_SUCCESS;
237	}
238
239	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu)
240	{
241	RT_NOREF(pVCpu);
242	return VERR_NOT_SUPPORTED;
243	}
244
245	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu)
246	{
247	RT_NOREF(pVCpu);
248	return VINF_SUCCESS;
249	}
250
251	/** Dummy ops. */
252	static HMR0VTABLE const g_HmR0OpsDummy =
253	{
254	/* .pfnEnterSession = */ hmR0DummyEnter,
255	/* .pfnThreadCtxCallback = */ hmR0DummyThreadCtxCallback,
256	/* .pfnCallRing3Callback = */ hmR0DummyCallRing3Callback,
257	/* .pfnExportHostState = */ hmR0DummyExportHostState,
258	/* .pfnRunGuestCode = */ hmR0DummyRunGuestCode,
259	/* .pfnEnableCpu = */ hmR0DummyEnableCpu,
260	/* .pfnDisableCpu = */ hmR0DummyDisableCpu,
261	/* .pfnInitVM = */ hmR0DummyInitVM,
262	/* .pfnTermVM = */ hmR0DummyTermVM,
263	/* .pfnSetupVM = */ hmR0DummySetupVM,
264	};
265
266	/** @} */
267
268
269	/**
270	* Initializes a first return code structure.
271	*
272	* @param pFirstRc The structure to init.
273	*/
274	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
275	{
276	pFirstRc->rc = VINF_SUCCESS;
277	pFirstRc->idCpu = NIL_RTCPUID;
278	}
279
280
281	/**
282	* Try set the status code (success ignored).
283	*
284	* @param pFirstRc The first return code structure.
285	* @param rc The status code.
286	*/
287	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
288	{
289	if ( RT_FAILURE(rc)
290	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
291	pFirstRc->idCpu = RTMpCpuId();
292	}
293
294
295	/**
296	* Get the status code of a first return code structure.
297	*
298	* @returns The status code; VINF_SUCCESS or error status, no informational or
299	* warning errors.
300	* @param pFirstRc The first return code structure.
301	*/
302	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
303	{
304	return pFirstRc->rc;
305	}
306
307
308	#ifdef VBOX_STRICT
309	# ifndef DEBUG_bird
310	/**
311	* Get the CPU ID on which the failure status code was reported.
312	*
313	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
314	* @param pFirstRc The first return code structure.
315	*/
316	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
317	{
318	return pFirstRc->idCpu;
319	}
320	# endif
321	#endif /* VBOX_STRICT */
322
323
324
325	/**
326	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
327	* on a CPU.
328	*
329	* @param idCpu The identifier for the CPU the function is called on.
330	* @param pvUser1 Pointer to the first RC structure.
331	* @param pvUser2 Ignored.
332	*/
333	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
334	{
335	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
336	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
337	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
338	NOREF(idCpu); NOREF(pvUser2);
339
340	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
341	hmR0FirstRcSetStatus(pFirstRc, rc);
342	}
343
344
345	/**
346	* Intel specific initialization code.
347	*
348	* @returns VBox status code (will only fail if out of memory).
349	*/
350	static int hmR0InitIntel(void)
351	{
352	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
353	g_HmMsrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
354
355	/*
356	* First try use native kernel API for controlling VT-x.
357	* (This is only supported by some Mac OS X kernels atm.)
358	*/
359	int rc;
360	g_rcHmInit = rc = SUPR0EnableVTx(true /* fEnable */);
361	g_fHmVmxUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
362	if (g_fHmVmxUsingSUPR0EnableVTx)
363	{
364	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
365	if (RT_SUCCESS(rc))
366	{
367	g_fHmVmxSupported = true;
368	rc = SUPR0EnableVTx(false /* fEnable */);
369	AssertLogRelRC(rc);
370	rc = VINF_SUCCESS;
371	}
372	}
373	else
374	{
375	HMR0FIRSTRC FirstRc;
376	hmR0FirstRcInit(&FirstRc);
377	g_rcHmInit = rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
378	if (RT_SUCCESS(rc))
379	g_rcHmInit = rc = hmR0FirstRcGetStatus(&FirstRc);
380	}
381
382	if (RT_SUCCESS(rc))
383	{
384	/* Read CR4 and EFER for logging/diagnostic purposes. */
385	g_uHmVmxHostCr4 = ASMGetCR4();
386	g_uHmVmxHostMsrEfer = ASMRdMsr(MSR_K6_EFER);
387
388	/* Get VMX MSRs for determining VMX features we can ultimately use. */
389	SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_VT_X, false /* fForce */);
390
391	/*
392	* Nested KVM workaround: Intel SDM section 34.15.5 describes that
393	* MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
394	* table 35-2 says that this MSR is available if either VMX or SMX is supported.
395	*/
396	uint64_t const uVmxBasicMsr = g_HmMsrs.u.vmx.u64Basic;
397	if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
398	g_uHmVmxHostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
399
400	/* Initialize VPID - 16 bits ASID. */
401	g_uHmMaxAsid = 0x10000; /* exclusive */
402
403	/*
404	* If the host OS has not enabled VT-x for us, try enter VMX root mode
405	* to really verify if VT-x is usable.
406	*/
407	if (!g_fHmVmxUsingSUPR0EnableVTx)
408	{
409	/* Allocate a temporary VMXON region. */
410	RTR0MEMOBJ hScatchMemObj;
411	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
412	if (RT_FAILURE(rc))
413	{
414	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
415	return rc;
416	}
417	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
418	RTHCPHYS const HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
419	ASMMemZeroPage(pvScatchPage);
420
421	/* Set revision dword at the beginning of the VMXON structure. */
422	(uint32_t )pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
423
424	/* Make sure we don't get rescheduled to another CPU during this probe. */
425	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
426
427	/* Enable CR4.VMXE if it isn't already set. */
428	RTCCUINTREG const uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
429
430	/*
431	* The only way of checking if we're in VMX root mode or not is to try and enter it.
432	* There is no instruction or control bit that tells us if we're in VMX root mode.
433	* Therefore, try and enter VMX root mode here.
434	*/
435	rc = VMXEnable(HCPhysScratchPage);
436	if (RT_SUCCESS(rc))
437	{
438	g_fHmVmxSupported = true;
439	VMXDisable();
440	}
441	else
442	{
443	/*
444	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
445	* it will crash the host when we enter raw mode, because:
446	*
447	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
448	* this bit), and
449	* (b) turning off paging causes a #GP (unavoidable when switching
450	* from long to 32 bits mode or 32 bits to PAE).
451	*
452	* They should fix their code, but until they do we simply refuse to run.
453	*/
454	g_rcHmInit = VERR_VMX_IN_VMX_ROOT_MODE;
455	Assert(g_fHmVmxSupported == false);
456	}
457
458	/* Restore CR4.VMXE if it wasn't set prior to us setting it above. */
459	if (!(uOldCr4 & X86_CR4_VMXE))
460	SUPR0ChangeCR4(0 /* fOrMask */, ~(uint64_t)X86_CR4_VMXE);
461
462	/* Restore interrupts. */
463	ASMSetFlags(fEFlags);
464
465	RTR0MemObjFree(hScatchMemObj, false);
466	}
467
468	if (g_fHmVmxSupported)
469	{
470	rc = VMXR0GlobalInit();
471	if (RT_SUCCESS(rc))
472	{
473	/*
474	* Install the VT-x methods.
475	*/
476	g_HmR0Ops = g_HmR0OpsVmx;
477
478	/*
479	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
480	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
481	*/
482	if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
483	{
484	g_fHmVmxUsePreemptTimer = true;
485	g_cHmVmxPreemptTimerShift = RT_BF_GET(g_HmMsrs.u.vmx.u64Misc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
486	if (HMIsSubjectToVmxPreemptTimerErratum())
487	g_cHmVmxPreemptTimerShift = 0; /* This is about right most of the time here. */
488	}
489	}
490	else
491	{
492	g_rcHmInit = rc;
493	g_fHmVmxSupported = false;
494	}
495	}
496	}
497	#ifdef LOG_ENABLED
498	else
499	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_rcHmInit);
500	#endif
501	return VINF_SUCCESS;
502	}
503
504
505	/**
506	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
507	* on a CPU.
508	*
509	* @param idCpu The identifier for the CPU the function is called on.
510	* @param pvUser1 Pointer to the first RC structure.
511	* @param pvUser2 Ignored.
512	*/
513	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
514	{
515	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
516	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
517	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
518	NOREF(idCpu); NOREF(pvUser2);
519
520	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
521	hmR0FirstRcSetStatus(pFirstRc, rc);
522	}
523
524
525	/**
526	* AMD-specific initialization code.
527	*
528	* @returns VBox status code (will only fail if out of memory).
529	*/
530	static int hmR0InitAmd(void)
531	{
532	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
533	int rc = SVMR0GlobalInit();
534	if (RT_SUCCESS(rc))
535	{
536	/*
537	* Install the AMD-V methods.
538	*/
539	g_HmR0Ops = g_HmR0OpsSvm;
540
541	/* Query AMD features. */
542	uint32_t u32Dummy;
543	ASMCpuId(0x8000000a, &g_uHmSvmRev, &g_uHmMaxAsid, &u32Dummy, &g_fHmSvmFeatures);
544
545	/*
546	* We need to check if AMD-V has been properly initialized on all CPUs.
547	* Some BIOSes might do a poor job.
548	*/
549	HMR0FIRSTRC FirstRc;
550	hmR0FirstRcInit(&FirstRc);
551	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
552	AssertRC(rc);
553	if (RT_SUCCESS(rc))
554	rc = hmR0FirstRcGetStatus(&FirstRc);
555	#ifndef DEBUG_bird
556	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
557	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
558	#endif
559	if (RT_SUCCESS(rc))
560	{
561	SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_AMD_V, false /* fForce */);
562	g_fHmSvmSupported = true;
563	}
564	else
565	{
566	g_rcHmInit = rc;
567	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
568	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
569	}
570	}
571	else
572	g_rcHmInit = rc;
573	return rc;
574	}
575
576
577	/**
578	* Does global Ring-0 HM initialization (at module init).
579	*
580	* @returns VBox status code.
581	*/
582	VMMR0_INT_DECL(int) HMR0Init(void)
583	{
584	/*
585	* Initialize the globals.
586	*/
587	g_fHmEnabled = false;
588	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
589	{
590	g_aHmCpuInfo[i].idCpu = NIL_RTCPUID;
591	g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
592	g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
593	g_aHmCpuInfo[i].pvMemObj = NULL;
594	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
595	g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
596	g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
597	g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
598	#endif
599	}
600
601	/* Fill in all callbacks with placeholders. */
602	g_HmR0Ops = g_HmR0OpsDummy;
603
604	/* Default is global VT-x/AMD-V init. */
605	g_fHmGlobalInit = true;
606
607	g_fHmVmxSupported = false;
608	g_fHmSvmSupported = false;
609	g_uHmMaxAsid = 0;
610
611	/*
612	* Get host kernel features that HM might need to know in order
613	* to co-operate and function properly with the host OS (e.g. SMAP).
614	*/
615	g_fHmHostKernelFeatures = SUPR0GetKernelFeatures();
616
617	/*
618	* Make sure aCpuInfo is big enough for all the CPUs on this system.
619	*/
620	if (RTMpGetArraySize() > RT_ELEMENTS(g_aHmCpuInfo))
621	{
622	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aHmCpuInfo)));
623	return VERR_TOO_MANY_CPUS;
624	}
625
626	/*
627	* Check for VT-x or AMD-V support.
628	* Return failure only in out-of-memory situations.
629	*/
630	uint32_t fCaps = 0;
631	int rc = SUPR0GetVTSupport(&fCaps);
632	if (RT_SUCCESS(rc))
633	{
634	if (fCaps & SUPVTCAPS_VT_X)
635	rc = hmR0InitIntel();
636	else
637	{
638	Assert(fCaps & SUPVTCAPS_AMD_V);
639	rc = hmR0InitAmd();
640	}
641	if (RT_SUCCESS(rc))
642	{
643	/*
644	* Register notification callbacks that we can use to disable/enable CPUs
645	* when brought offline/online or suspending/resuming.
646	*/
647	if (!g_fHmVmxUsingSUPR0EnableVTx)
648	{
649	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
650	if (RT_SUCCESS(rc))
651	{
652	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
653	if (RT_FAILURE(rc))
654	RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
655	}
656	if (RT_FAILURE(rc))
657	{
658	/* There shouldn't be any per-cpu allocations at this point,
659	so just have to call SVMR0GlobalTerm and VMXR0GlobalTerm. */
660	if (fCaps & SUPVTCAPS_VT_X)
661	VMXR0GlobalTerm();
662	else
663	SVMR0GlobalTerm();
664	g_HmR0Ops = g_HmR0OpsDummy;
665	g_rcHmInit = rc;
666	g_fHmSvmSupported = false;
667	g_fHmVmxSupported = false;
668	}
669	}
670	}
671	}
672	else
673	{
674	g_rcHmInit = rc;
675	rc = VINF_SUCCESS; /* We return success here because module init shall not fail if HM fails to initialize. */
676	}
677	return rc;
678	}
679
680
681	/**
682	* Does global Ring-0 HM termination (at module termination).
683	*
684	* @returns VBox status code (ignored).
685	*/
686	VMMR0_INT_DECL(int) HMR0Term(void)
687	{
688	int rc;
689	if ( g_fHmVmxSupported
690	&& g_fHmVmxUsingSUPR0EnableVTx)
691	{
692	/*
693	* Simple if the host OS manages VT-x.
694	*/
695	Assert(g_fHmGlobalInit);
696
697	if (g_fHmVmxCalledSUPR0EnableVTx)
698	{
699	rc = SUPR0EnableVTx(false /* fEnable */);
700	g_fHmVmxCalledSUPR0EnableVTx = false;
701	}
702	else
703	rc = VINF_SUCCESS;
704
705	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aHmCpuInfo); iCpu++)
706	{
707	g_aHmCpuInfo[iCpu].fConfigured = false;
708	Assert(g_aHmCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
709	}
710	}
711	else
712	{
713	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
714
715	/* Doesn't really matter if this fails. */
716	RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
717	RTPowerNotificationDeregister(hmR0PowerCallback, NULL);
718	rc = VINF_SUCCESS;
719
720	/*
721	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
722	*/
723	if (g_fHmGlobalInit)
724	{
725	HMR0FIRSTRC FirstRc;
726	hmR0FirstRcInit(&FirstRc);
727	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
728	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
729	if (RT_SUCCESS(rc))
730	rc = hmR0FirstRcGetStatus(&FirstRc);
731	}
732
733	/*
734	* Free the per-cpu pages used for VT-x and AMD-V.
735	*/
736	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
737	{
738	if (g_aHmCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
739	{
740	RTR0MemObjFree(g_aHmCpuInfo[i].hMemObj, false);
741	g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
742	g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
743	g_aHmCpuInfo[i].pvMemObj = NULL;
744	}
745	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
746	if (g_aHmCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
747	{
748	RTR0MemObjFree(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, false);
749	g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
750	g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
751	g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
752	}
753	#endif
754	}
755	}
756
757	/** @todo This needs cleaning up. There's no matching
758	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
759	* should move into their respective modules. */
760	/* Finally, call global VT-x/AMD-V termination. */
761	if (g_fHmVmxSupported)
762	VMXR0GlobalTerm();
763	else if (g_fHmSvmSupported)
764	SVMR0GlobalTerm();
765
766	return rc;
767	}
768
769
770	/**
771	* Enable VT-x or AMD-V on the current CPU
772	*
773	* @returns VBox status code.
774	* @param pVM The cross context VM structure. Can be NULL.
775	* @param idCpu The identifier for the CPU the function is called on.
776	*
777	* @remarks Maybe called with interrupts disabled!
778	*/
779	static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
780	{
781	PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
782
783	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
784	Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
785	Assert(!pHostCpu->fConfigured);
786	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
787
788	pHostCpu->idCpu = idCpu;
789	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
790
791	int rc;
792	if ( g_fHmVmxSupported
793	&& g_fHmVmxUsingSUPR0EnableVTx)
794	rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmMsrs);
795	else
796	{
797	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
798	rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmMsrs);
799	}
800	if (RT_SUCCESS(rc))
801	pHostCpu->fConfigured = true;
802	return rc;
803	}
804
805
806	/**
807	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
808	*
809	* @param idCpu The identifier for the CPU the function is called on.
810	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
811	* @param pvUser2 The 2nd user argument.
812	*/
813	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
814	{
815	PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */
816	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
817	AssertReturnVoid(g_fHmGlobalInit);
818	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
819	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
820	}
821
822
823	/**
824	* RTOnce callback employed by HMR0EnableAllCpus.
825	*
826	* @returns VBox status code.
827	* @param pvUser Pointer to the VM.
828	*/
829	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
830	{
831	PVMCC pVM = (PVMCC)pvUser;
832
833	/*
834	* Indicate that we've initialized.
835	*
836	* Note! There is a potential race between this function and the suspend
837	* notification. Kind of unlikely though, so ignored for now.
838	*/
839	AssertReturn(!g_fHmEnabled, VERR_HM_ALREADY_ENABLED_IPE);
840	ASMAtomicWriteBool(&g_fHmEnabled, true);
841
842	/*
843	* The global init variable is set by the first VM.
844	*/
845	g_fHmGlobalInit = pVM->hm.s.fGlobalInit;
846
847	#ifdef VBOX_STRICT
848	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
849	{
850	Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
851	Assert(g_aHmCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
852	Assert(g_aHmCpuInfo[i].pvMemObj == NULL);
853	Assert(!g_aHmCpuInfo[i].fConfigured);
854	Assert(!g_aHmCpuInfo[i].cTlbFlushes);
855	Assert(!g_aHmCpuInfo[i].uCurrentAsid);
856	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
857	Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
858	Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
859	Assert(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
860	# endif
861	}
862	#endif
863
864	int rc;
865	if ( g_fHmVmxSupported
866	&& g_fHmVmxUsingSUPR0EnableVTx)
867	{
868	/*
869	* Global VT-x initialization API (only darwin for now).
870	*/
871	rc = SUPR0EnableVTx(true /* fEnable */);
872	if (RT_SUCCESS(rc))
873	{
874	g_fHmVmxCalledSUPR0EnableVTx = true;
875	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
876	g_fHmGlobalInit = pVM->hm.s.fGlobalInit = true;
877	}
878	else
879	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
880	}
881	else
882	{
883	/*
884	* We're doing the job ourselves.
885	*/
886	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
887	for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
888	{
889	Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
890	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
891	Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
892	#endif
893	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
894	{
895	/** @todo NUMA */
896	rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
897	AssertLogRelRCReturn(rc, rc);
898
899	g_aHmCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].hMemObj, 0);
900	Assert(g_aHmCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
901	Assert(!(g_aHmCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
902
903	g_aHmCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_aHmCpuInfo[i].hMemObj);
904	AssertPtr(g_aHmCpuInfo[i].pvMemObj);
905	ASMMemZeroPage(g_aHmCpuInfo[i].pvMemObj);
906
907	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
908	rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
909	false /* executable R0 mapping */);
910	AssertLogRelRCReturn(rc, rc);
911
912	g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, 0);
913	Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
914	Assert(!(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
915
916	g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm);
917	AssertPtr(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm);
918	ASMMemFill32(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
919	#endif
920	}
921	}
922
923	rc = VINF_SUCCESS;
924	}
925
926	if ( RT_SUCCESS(rc)
927	&& g_fHmGlobalInit)
928	{
929	/* First time, so initialize each cpu/core. */
930	HMR0FIRSTRC FirstRc;
931	hmR0FirstRcInit(&FirstRc);
932	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
933	if (RT_SUCCESS(rc))
934	rc = hmR0FirstRcGetStatus(&FirstRc);
935	}
936
937	return rc;
938	}
939
940
941	/**
942	* Sets up HM on all cpus.
943	*
944	* @returns VBox status code.
945	* @param pVM The cross context VM structure.
946	*/
947	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM)
948	{
949	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
950	if (ASMAtomicReadBool(&g_fHmSuspended))
951	return VERR_HM_SUSPEND_PENDING;
952
953	return RTOnce(&g_HmEnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
954	}
955
956
957	/**
958	* Disable VT-x or AMD-V on the current CPU.
959	*
960	* @returns VBox status code.
961	* @param idCpu The identifier for the CPU this function is called on.
962	*
963	* @remarks Must be called with preemption disabled.
964	*/
965	static int hmR0DisableCpu(RTCPUID idCpu)
966	{
967	PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
968
969	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
970	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
971	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
972	Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
973	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
974	AssertRelease(idCpu == RTMpCpuId());
975
976	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
977	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
978	AssertPtr(pHostCpu->pvMemObj);
979	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
980
981	int rc;
982	if (pHostCpu->fConfigured)
983	{
984	rc = g_HmR0Ops.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
985	AssertRCReturn(rc, rc);
986
987	pHostCpu->fConfigured = false;
988	pHostCpu->idCpu = NIL_RTCPUID;
989	}
990	else
991	rc = VINF_SUCCESS; /* nothing to do */
992	return rc;
993	}
994
995
996	/**
997	* Worker function passed to RTMpOnAll() that is to be called on the target
998	* CPUs.
999	*
1000	* @param idCpu The identifier for the CPU the function is called on.
1001	* @param pvUser1 The 1st user argument.
1002	* @param pvUser2 Opaque pointer to the FirstRc.
1003	*/
1004	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1005	{
1006	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1007	AssertReturnVoid(g_fHmGlobalInit);
1008	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1009	}
1010
1011
1012	/**
1013	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1014	* CPU.
1015	*
1016	* @param idCpu The identifier for the CPU the function is called on.
1017	* @param pvUser1 Null, not used.
1018	* @param pvUser2 Null, not used.
1019	*/
1020	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1021	{
1022	NOREF(pvUser1);
1023	NOREF(pvUser2);
1024	hmR0DisableCpu(idCpu);
1025	}
1026
1027
1028	/**
1029	* Callback function invoked when a cpu goes online or offline.
1030	*
1031	* @param enmEvent The Mp event.
1032	* @param idCpu The identifier for the CPU the function is called on.
1033	* @param pvData Opaque data (PVMCC pointer).
1034	*/
1035	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1036	{
1037	NOREF(pvData);
1038	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1039
1040	/*
1041	* We only care about uninitializing a CPU that is going offline. When a
1042	* CPU comes online, the initialization is done lazily in HMR0Enter().
1043	*/
1044	switch (enmEvent)
1045	{
1046	case RTMPEVENT_OFFLINE:
1047	{
1048	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1049	RTThreadPreemptDisable(&PreemptState);
1050	if (idCpu == RTMpCpuId())
1051	{
1052	int rc = hmR0DisableCpu(idCpu);
1053	AssertRC(rc);
1054	RTThreadPreemptRestore(&PreemptState);
1055	}
1056	else
1057	{
1058	RTThreadPreemptRestore(&PreemptState);
1059	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1060	}
1061	break;
1062	}
1063
1064	default:
1065	break;
1066	}
1067	}
1068
1069
1070	/**
1071	* Called whenever a system power state change occurs.
1072	*
1073	* @param enmEvent The Power event.
1074	* @param pvUser User argument.
1075	*/
1076	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1077	{
1078	NOREF(pvUser);
1079	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1080
1081	#ifdef LOG_ENABLED
1082	if (enmEvent == RTPOWEREVENT_SUSPEND)
1083	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1084	else
1085	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1086	#endif
1087
1088	if (enmEvent == RTPOWEREVENT_SUSPEND)
1089	ASMAtomicWriteBool(&g_fHmSuspended, true);
1090
1091	if (g_fHmEnabled)
1092	{
1093	int rc;
1094	HMR0FIRSTRC FirstRc;
1095	hmR0FirstRcInit(&FirstRc);
1096
1097	if (enmEvent == RTPOWEREVENT_SUSPEND)
1098	{
1099	if (g_fHmGlobalInit)
1100	{
1101	/* Turn off VT-x or AMD-V on all CPUs. */
1102	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1103	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1104	}
1105	/* else nothing to do here for the local init case */
1106	}
1107	else
1108	{
1109	/* Reinit the CPUs from scratch as the suspend state might have
1110	messed with the MSRs. (lousy BIOSes as usual) */
1111	if (g_fHmVmxSupported)
1112	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1113	else
1114	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1115	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1116	if (RT_SUCCESS(rc))
1117	rc = hmR0FirstRcGetStatus(&FirstRc);
1118	#ifdef LOG_ENABLED
1119	if (RT_FAILURE(rc))
1120	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1121	#endif
1122	if (g_fHmGlobalInit)
1123	{
1124	/* Turn VT-x or AMD-V back on on all CPUs. */
1125	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1126	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1127	}
1128	/* else nothing to do here for the local init case */
1129	}
1130	}
1131
1132	if (enmEvent == RTPOWEREVENT_RESUME)
1133	ASMAtomicWriteBool(&g_fHmSuspended, false);
1134	}
1135
1136
1137	/**
1138	* Does ring-0 per-VM HM initialization.
1139	*
1140	* This will call the CPU specific init. routine which may initialize and allocate
1141	* resources for virtual CPUs.
1142	*
1143	* @returns VBox status code.
1144	* @param pVM The cross context VM structure.
1145	*
1146	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1147	* vmR3InitRing3().
1148	*/
1149	VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM)
1150	{
1151	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1152
1153	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1154	if (ASMAtomicReadBool(&g_fHmSuspended))
1155	return VERR_HM_SUSPEND_PENDING;
1156
1157	/*
1158	* Copy globals to the VM structure.
1159	*/
1160	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1161	if (pVM->hm.s.vmx.fSupported)
1162	{
1163	pVM->hm.s.vmx.fUsePreemptTimer &= g_fHmVmxUsePreemptTimer; /* Can be overridden by CFGM in HMR3Init(). */
1164	pVM->hm.s.vmx.cPreemptTimerShift = g_cHmVmxPreemptTimerShift;
1165	pVM->hm.s.vmx.u64HostCr4 = g_uHmVmxHostCr4;
1166	pVM->hm.s.vmx.u64HostMsrEfer = g_uHmVmxHostMsrEfer;
1167	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_uHmVmxHostSmmMonitorCtl;
1168	HMGetVmxMsrsFromHwvirtMsrs(&g_HmMsrs, &pVM->hm.s.vmx.MsrsForRing3);
1169	/* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
1170
1171	/* Enable VPID if supported and configured. */
1172	if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1173	pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
1174
1175	/* Use VMCS shadowing if supported. */
1176	Assert(!pVM->hm.s.vmx.fUseVmcsShadowing);
1177	if ( pVM->cpum.ro.GuestFeatures.fVmx
1178	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING))
1179	pVM->hm.s.vmx.fUseVmcsShadowing = true;
1180
1181	/* Use the VMCS controls for swapping the EFER MSR if supported. */
1182	Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
1183	if ( (g_HmMsrs.u.vmx.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
1184	&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1185	&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
1186	pVM->hm.s.vmx.fSupportsVmcsEfer = true;
1187
1188	#if 0
1189	/* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
1190	if ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1191	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1192	pVM->hm.s.fVirtApicRegs = true;
1193
1194	/* Enable posted-interrupt processing if supported. */
1195	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1196	* here. */
1197	if ( (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1198	&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1199	pVM->hm.s.fPostedIntrs = true;
1200	#endif
1201	}
1202	else if (pVM->hm.s.svm.fSupported)
1203	{
1204	pVM->hm.s.svm.u32Rev = g_uHmSvmRev;
1205	pVM->hm.s.svm.fFeaturesForRing3 = g_fHmSvmFeatures;
1206	pVM->hm.s.svm.u64MsrHwcr = g_HmMsrs.u.svm.u64MsrHwcr;
1207	/* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
1208	}
1209	pVM->hm.s.rcInit = g_rcHmInit;
1210	pVM->hm.s.uMaxAsidForLog = g_uHmMaxAsid;
1211
1212	/*
1213	* Set default maximum inner loops in ring-0 before returning to ring-3.
1214	* Can be overriden using CFGM.
1215	*/
1216	uint32_t cMaxResumeLoops = pVM->hm.s.cMaxResumeLoopsCfg;
1217	if (!cMaxResumeLoops)
1218	{
1219	cMaxResumeLoops = 1024;
1220	if (RTThreadPreemptIsPendingTrusty())
1221	cMaxResumeLoops = 8192;
1222	}
1223	else if (cMaxResumeLoops > 16384)
1224	cMaxResumeLoops = 16384;
1225	else if (cMaxResumeLoops < 32)
1226	cMaxResumeLoops = 32;
1227	pVM->hm.s.cMaxResumeLoopsCfg = pVM->hmr0.s.cMaxResumeLoops = cMaxResumeLoops;
1228
1229	/*
1230	* Initialize some per-VCPU fields.
1231	*/
1232	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1233	{
1234	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1235	pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1236	pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1237
1238	/* We'll aways increment this the first time (host uses ASID 0). */
1239	AssertReturn(!pVCpu->hmr0.s.uCurrentAsid, VERR_HM_IPE_3);
1240	}
1241
1242	/*
1243	* Configure defences against spectre and other CPU bugs.
1244	*/
1245	uint32_t fWorldSwitcher = 0;
1246	uint32_t cLastStdLeaf = ASMCpuId_EAX(0);
1247	if (cLastStdLeaf >= 0x00000007 && ASMIsValidStdRange(cLastStdLeaf))
1248	{
1249	uint32_t uEdx = 0;
1250	ASMCpuIdExSlow(0x00000007, 0, 0, 0, NULL, NULL, NULL, &uEdx);
1251
1252	if ((pVM->hm.s.fIbpbOnVmExit \|\| pVM->hm.s.fIbpbOnVmEntry) && (uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB))
1253	{
1254	if (pVM->hm.s.fIbpbOnVmExit)
1255	fWorldSwitcher \|= HM_WSF_IBPB_EXIT;
1256	if (pVM->hm.s.fIbpbOnVmEntry)
1257	fWorldSwitcher \|= HM_WSF_IBPB_ENTRY;
1258	}
1259	if (pVM->hm.s.fL1dFlushOnVmEntry && (uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1260	fWorldSwitcher \|= HM_WSF_L1D_ENTRY;
1261	if (pVM->hm.s.fMdsClearOnVmEntry && (uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR))
1262	fWorldSwitcher \|= HM_WSF_MDS_ENTRY;
1263	}
1264	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1265	{
1266	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1267	pVCpu->hmr0.s.fWorldSwitcher = fWorldSwitcher;
1268	}
1269	pVM->hm.s.fWorldSwitcherForLog = fWorldSwitcher;
1270
1271
1272	/*
1273	* Call the hardware specific initialization method.
1274	*/
1275	return g_HmR0Ops.pfnInitVM(pVM);
1276	}
1277
1278
1279	/**
1280	* Does ring-0 per VM HM termination.
1281	*
1282	* @returns VBox status code.
1283	* @param pVM The cross context VM structure.
1284	*/
1285	VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM)
1286	{
1287	Log(("HMR0TermVM: %p\n", pVM));
1288	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1289
1290	/*
1291	* Call the hardware specific method.
1292	*
1293	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1294	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1295	*/
1296	return g_HmR0Ops.pfnTermVM(pVM);
1297	}
1298
1299
1300	/**
1301	* Sets up a VT-x or AMD-V session.
1302	*
1303	* This is mostly about setting up the hardware VM state.
1304	*
1305	* @returns VBox status code.
1306	* @param pVM The cross context VM structure.
1307	*/
1308	VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM)
1309	{
1310	Log(("HMR0SetupVM: %p\n", pVM));
1311	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1312
1313	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1314	AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1315
1316	/* On first entry we'll sync everything. */
1317	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1318
1319	/*
1320	* Call the hardware specific setup VM method. This requires the CPU to be
1321	* enabled for AMD-V/VT-x and preemption to be prevented.
1322	*/
1323	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1324	RTThreadPreemptDisable(&PreemptState);
1325	RTCPUID const idCpu = RTMpCpuId();
1326
1327	/* Enable VT-x or AMD-V if local init is required. */
1328	int rc;
1329	if (!g_fHmGlobalInit)
1330	{
1331	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1332	rc = hmR0EnableCpu(pVM, idCpu);
1333	if (RT_FAILURE(rc))
1334	{
1335	RTThreadPreemptRestore(&PreemptState);
1336	return rc;
1337	}
1338	}
1339
1340	/* Setup VT-x or AMD-V. */
1341	rc = g_HmR0Ops.pfnSetupVM(pVM);
1342
1343	/* Disable VT-x or AMD-V if local init was done before. */
1344	if (!g_fHmGlobalInit)
1345	{
1346	Assert(!g_fHmVmxSupported \|\| !g_fHmVmxUsingSUPR0EnableVTx);
1347	int rc2 = hmR0DisableCpu(idCpu);
1348	AssertRC(rc2);
1349	}
1350
1351	RTThreadPreemptRestore(&PreemptState);
1352	return rc;
1353	}
1354
1355
1356	/**
1357	* Notification callback before performing a longjump to ring-3.
1358	*
1359	* @returns VBox status code.
1360	* @param pVCpu The cross context virtual CPU structure.
1361	* @param enmOperation The operation causing the ring-3 longjump.
1362	* @param pvUser User argument, currently unused, NULL.
1363	*/
1364	static DECLCALLBACK(int) hmR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1365	{
1366	RT_NOREF(pvUser);
1367	Assert(pVCpu);
1368	Assert(g_HmR0Ops.pfnCallRing3Callback);
1369	return g_HmR0Ops.pfnCallRing3Callback(pVCpu, enmOperation);
1370	}
1371
1372
1373	/**
1374	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1375	* required for entering HM context.
1376	*
1377	* @returns VBox status code.
1378	* @param pVCpu The cross context virtual CPU structure.
1379	*
1380	* @remarks No-long-jump zone!!!
1381	*/
1382	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu)
1383	{
1384	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1385
1386	int rc = VINF_SUCCESS;
1387	RTCPUID const idCpu = RTMpCpuId();
1388	PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1389	AssertPtr(pHostCpu);
1390
1391	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1392	if (!pHostCpu->fConfigured)
1393	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1394
1395	/* Register a callback to fire prior to performing a longjmp to ring-3 so HM can disable VT-x/AMD-V if needed. */
1396	VMMRZCallRing3SetNotification(pVCpu, hmR0CallRing3Callback, NULL /* pvUser */);
1397
1398	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1399	if (g_fHmVmxSupported)
1400	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1401	else
1402	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1403
1404	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1405	pVCpu->hmr0.s.idEnteredCpu = idCpu;
1406	return rc;
1407	}
1408
1409
1410	/**
1411	* Enters the VT-x or AMD-V session.
1412	*
1413	* @returns VBox status code.
1414	* @param pVCpu The cross context virtual CPU structure.
1415	*
1416	* @remarks This is called with preemption disabled.
1417	*/
1418	VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu)
1419	{
1420	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1421	AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1422	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1423
1424	/* Load the bare minimum state required for entering HM. */
1425	int rc = hmR0EnterCpu(pVCpu);
1426	if (RT_SUCCESS(rc))
1427	{
1428	if (g_fHmVmxSupported)
1429	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1430	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1431	else
1432	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1433	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1434
1435	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1436	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1437	bool const fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1438	#endif
1439
1440	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1441	rc = g_HmR0Ops.pfnEnterSession(pVCpu);
1442	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1443
1444	/* Exports the host-state as we may be resuming code after a longjmp and quite
1445	possibly now be scheduled on a different CPU. */
1446	rc = g_HmR0Ops.pfnExportHostState(pVCpu);
1447	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1448
1449	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1450	if (fStartedSet)
1451	PGMRZDynMapReleaseAutoSet(pVCpu);
1452	#endif
1453	}
1454	return rc;
1455	}
1456
1457
1458	/**
1459	* Deinitializes the bare minimum state used for HM context and if necessary
1460	* disable HM on the CPU.
1461	*
1462	* @returns VBox status code.
1463	* @param pVCpu The cross context virtual CPU structure.
1464	*
1465	* @remarks No-long-jump zone!!!
1466	*/
1467	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu)
1468	{
1469	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1470	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1471
1472	RTCPUID const idCpu = RTMpCpuId();
1473	PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1474
1475	if ( !g_fHmGlobalInit
1476	&& pHostCpu->fConfigured)
1477	{
1478	int rc = hmR0DisableCpu(idCpu);
1479	AssertRCReturn(rc, rc);
1480	Assert(!pHostCpu->fConfigured);
1481	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1482
1483	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1484	pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1485	}
1486
1487	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1488	pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1489
1490	/* De-register the longjmp-to-ring 3 callback now that we have reliquished hardware resources. */
1491	VMMRZCallRing3RemoveNotification(pVCpu);
1492	return VINF_SUCCESS;
1493	}
1494
1495
1496	/**
1497	* Thread-context hook for HM.
1498	*
1499	* @param enmEvent The thread-context event.
1500	* @param pvUser Opaque pointer to the VMCPU.
1501	*/
1502	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1503	{
1504	PVMCPUCC pVCpu = (PVMCPUCC)pvUser;
1505	Assert(pVCpu);
1506	Assert(g_HmR0Ops.pfnThreadCtxCallback);
1507
1508	g_HmR0Ops.pfnThreadCtxCallback(enmEvent, pVCpu, g_fHmGlobalInit);
1509	}
1510
1511
1512	/**
1513	* Runs guest code in a hardware accelerated VM.
1514	*
1515	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1516	* called from setjmp assembly.)
1517	* @param pVM The cross context VM structure.
1518	* @param pVCpu The cross context virtual CPU structure.
1519	*
1520	* @remarks Can be called with preemption enabled if thread-context hooks are
1521	* used!!!
1522	*/
1523	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu)
1524	{
1525	RT_NOREF(pVM);
1526
1527	#ifdef VBOX_STRICT
1528	/* With thread-context hooks we would be running this code with preemption enabled. */
1529	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1530	{
1531	PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[RTMpCpuId()];
1532	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1533	Assert(pHostCpu->fConfigured);
1534	AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1535	}
1536	#endif
1537
1538	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1539	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1540	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1541	PGMRZDynMapStartAutoSet(pVCpu);
1542	#endif
1543
1544	VBOXSTRICTRC rcStrict = g_HmR0Ops.pfnRunGuestCode(pVCpu);
1545
1546	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1547	PGMRZDynMapReleaseAutoSet(pVCpu);
1548	#endif
1549	return VBOXSTRICTRC_VAL(rcStrict);
1550	}
1551
1552
1553	/**
1554	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1555	* the host CPU and that guest access to it must be intercepted.
1556	*
1557	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1558	*/
1559	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu)
1560	{
1561	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1562	}
1563
1564
1565	/**
1566	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1567	*
1568	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1569	*/
1570	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu)
1571	{
1572	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1573	}
1574
1575
1576	/**
1577	* Returns suspend status of the host.
1578	*
1579	* @returns Suspend pending or not.
1580	*/
1581	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1582	{
1583	return ASMAtomicReadBool(&g_fHmSuspended);
1584	}
1585
1586
1587	/**
1588	* Invalidates a guest page from the host TLB.
1589	*
1590	* @param pVCpu The cross context virtual CPU structure.
1591	* @param GCVirt Page to invalidate.
1592	*/
1593	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1594	{
1595	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1596	if (pVM->hm.s.vmx.fSupported)
1597	return VMXR0InvalidatePage(pVCpu, GCVirt);
1598	return SVMR0InvalidatePage(pVCpu, GCVirt);
1599	}
1600
1601
1602	/**
1603	* Returns the cpu structure for the current cpu.
1604	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1605	*
1606	* @returns The cpu structure pointer.
1607	*/
1608	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1609	{
1610	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1611	RTCPUID const idCpu = RTMpCpuId();
1612	Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
1613	return &g_aHmCpuInfo[idCpu];
1614	}
1615
1616
1617	/**
1618	* Interface for importing state on demand (used by IEM).
1619	*
1620	* @returns VBox status code.
1621	* @param pVCpu The cross context CPU structure.
1622	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1623	*/
1624	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1625	{
1626	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1627	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1628	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1629	}
1630
1631	#ifdef VBOX_STRICT
1632
1633	/**
1634	* Dumps a descriptor.
1635	*
1636	* @param pDesc Descriptor to dump.
1637	* @param Sel The selector.
1638	* @param pszSel The name of the selector.
1639	*/
1640	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel)
1641	{
1642	/*
1643	* Make variable description string.
1644	*/
1645	static struct
1646	{
1647	unsigned cch;
1648	const char *psz;
1649	} const s_aTypes[32] =
1650	{
1651	# define STRENTRY(str) { sizeof(str) - 1, str }
1652
1653	/* system */
1654	# if HC_ARCH_BITS == 64
1655	STRENTRY("Reserved0 "), /* 0x00 */
1656	STRENTRY("Reserved1 "), /* 0x01 */
1657	STRENTRY("LDT "), /* 0x02 */
1658	STRENTRY("Reserved3 "), /* 0x03 */
1659	STRENTRY("Reserved4 "), /* 0x04 */
1660	STRENTRY("Reserved5 "), /* 0x05 */
1661	STRENTRY("Reserved6 "), /* 0x06 */
1662	STRENTRY("Reserved7 "), /* 0x07 */
1663	STRENTRY("Reserved8 "), /* 0x08 */
1664	STRENTRY("TSS64Avail "), /* 0x09 */
1665	STRENTRY("ReservedA "), /* 0x0a */
1666	STRENTRY("TSS64Busy "), /* 0x0b */
1667	STRENTRY("Call64 "), /* 0x0c */
1668	STRENTRY("ReservedD "), /* 0x0d */
1669	STRENTRY("Int64 "), /* 0x0e */
1670	STRENTRY("Trap64 "), /* 0x0f */
1671	# else
1672	STRENTRY("Reserved0 "), /* 0x00 */
1673	STRENTRY("TSS16Avail "), /* 0x01 */
1674	STRENTRY("LDT "), /* 0x02 */
1675	STRENTRY("TSS16Busy "), /* 0x03 */
1676	STRENTRY("Call16 "), /* 0x04 */
1677	STRENTRY("Task "), /* 0x05 */
1678	STRENTRY("Int16 "), /* 0x06 */
1679	STRENTRY("Trap16 "), /* 0x07 */
1680	STRENTRY("Reserved8 "), /* 0x08 */
1681	STRENTRY("TSS32Avail "), /* 0x09 */
1682	STRENTRY("ReservedA "), /* 0x0a */
1683	STRENTRY("TSS32Busy "), /* 0x0b */
1684	STRENTRY("Call32 "), /* 0x0c */
1685	STRENTRY("ReservedD "), /* 0x0d */
1686	STRENTRY("Int32 "), /* 0x0e */
1687	STRENTRY("Trap32 "), /* 0x0f */
1688	# endif
1689	/* non system */
1690	STRENTRY("DataRO "), /* 0x10 */
1691	STRENTRY("DataRO Accessed "), /* 0x11 */
1692	STRENTRY("DataRW "), /* 0x12 */
1693	STRENTRY("DataRW Accessed "), /* 0x13 */
1694	STRENTRY("DataDownRO "), /* 0x14 */
1695	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1696	STRENTRY("DataDownRW "), /* 0x16 */
1697	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1698	STRENTRY("CodeEO "), /* 0x18 */
1699	STRENTRY("CodeEO Accessed "), /* 0x19 */
1700	STRENTRY("CodeER "), /* 0x1a */
1701	STRENTRY("CodeER Accessed "), /* 0x1b */
1702	STRENTRY("CodeConfEO "), /* 0x1c */
1703	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1704	STRENTRY("CodeConfER "), /* 0x1e */
1705	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1706	# undef SYSENTRY
1707	};
1708	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1709	char szMsg[128];
1710	char *psz = &szMsg[0];
1711	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1712	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1713	psz += s_aTypes[i].cch;
1714
1715	if (pDesc->Gen.u1Present)
1716	ADD_STR(psz, "Present ");
1717	else
1718	ADD_STR(psz, "Not-Present ");
1719	# if HC_ARCH_BITS == 64
1720	if (pDesc->Gen.u1Long)
1721	ADD_STR(psz, "64-bit ");
1722	else
1723	ADD_STR(psz, "Comp ");
1724	# else
1725	if (pDesc->Gen.u1Granularity)
1726	ADD_STR(psz, "Page ");
1727	if (pDesc->Gen.u1DefBig)
1728	ADD_STR(psz, "32-bit ");
1729	else
1730	ADD_STR(psz, "16-bit ");
1731	# endif
1732	# undef ADD_STR
1733	*psz = '\0';
1734
1735	/*
1736	* Limit and Base and format the output.
1737	*/
1738	#ifdef LOG_ENABLED
1739	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1740
1741	# if HC_ARCH_BITS == 64
1742	uint64_t const u64Base = X86DESC64_BASE(pDesc);
1743	Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel,
1744	Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1745	# else
1746	uint32_t const u32Base = X86DESC_BASE(pDesc);
1747	Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel,
1748	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1749	# endif
1750	#else
1751	NOREF(Sel); NOREF(pszSel);
1752	#endif
1753	}
1754
1755
1756	/**
1757	* Formats a full register dump.
1758	*
1759	* @param pVCpu The cross context virtual CPU structure.
1760	* @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX).
1761	*/
1762	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags)
1763	{
1764	/*
1765	* Format the flags.
1766	*/
1767	static struct
1768	{
1769	const char *pszSet;
1770	const char *pszClear;
1771	uint32_t fFlag;
1772	} const s_aFlags[] =
1773	{
1774	{ "vip", NULL, X86_EFL_VIP },
1775	{ "vif", NULL, X86_EFL_VIF },
1776	{ "ac", NULL, X86_EFL_AC },
1777	{ "vm", NULL, X86_EFL_VM },
1778	{ "rf", NULL, X86_EFL_RF },
1779	{ "nt", NULL, X86_EFL_NT },
1780	{ "ov", "nv", X86_EFL_OF },
1781	{ "dn", "up", X86_EFL_DF },
1782	{ "ei", "di", X86_EFL_IF },
1783	{ "tf", NULL, X86_EFL_TF },
1784	{ "nt", "pl", X86_EFL_SF },
1785	{ "nz", "zr", X86_EFL_ZF },
1786	{ "ac", "na", X86_EFL_AF },
1787	{ "po", "pe", X86_EFL_PF },
1788	{ "cy", "nc", X86_EFL_CF },
1789	};
1790	char szEFlags[80];
1791	char *psz = szEFlags;
1792	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1793	uint32_t uEFlags = pCtx->eflags.u32;
1794	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1795	{
1796	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1797	if (pszAdd)
1798	{
1799	strcpy(psz, pszAdd);
1800	psz += strlen(pszAdd);
1801	*psz++ = ' ';
1802	}
1803	}
1804	psz[-1] = '\0';
1805
1806	if (fFlags & HM_DUMP_REG_FLAGS_GPRS)
1807	{
1808	/*
1809	* Format the registers.
1810	*/
1811	if (CPUMIsGuestIn64BitCode(pVCpu))
1812	{
1813	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1814	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1815	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1816	"r14=%016RX64 r15=%016RX64\n"
1817	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1818	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1819	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1820	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1821	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1822	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1823	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1824	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1825	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1826	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1827	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1828	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1829	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1830	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1831	,
1832	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1833	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1834	pCtx->r14, pCtx->r15,
1835	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1836	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1837	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1838	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1839	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1840	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1841	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1842	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1843	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1844	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1845	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1846	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1847	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1848	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1849	}
1850	else
1851	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1852	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1853	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1854	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1855	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1856	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1857	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1858	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1859	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1860	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1861	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1862	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1863	,
1864	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1865	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1866	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1867	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1868	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1869	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1870	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1871	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1872	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1873	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1874	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1875	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1876	}
1877
1878	if (fFlags & HM_DUMP_REG_FLAGS_FPU)
1879	{
1880	PCX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1881	Log(("FPU:\n"
1882	"FCW=%04x FSW=%04x FTW=%02x\n"
1883	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1884	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1885	,
1886	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1887	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1888	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1889	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1890	NOREF(pFpuCtx);
1891	}
1892
1893	if (fFlags & HM_DUMP_REG_FLAGS_MSRS)
1894	{
1895	Log(("MSR:\n"
1896	"EFER =%016RX64\n"
1897	"PAT =%016RX64\n"
1898	"STAR =%016RX64\n"
1899	"CSTAR =%016RX64\n"
1900	"LSTAR =%016RX64\n"
1901	"SFMASK =%016RX64\n"
1902	"KERNELGSBASE =%016RX64\n",
1903	pCtx->msrEFER,
1904	pCtx->msrPAT,
1905	pCtx->msrSTAR,
1906	pCtx->msrCSTAR,
1907	pCtx->msrLSTAR,
1908	pCtx->msrSFMASK,
1909	pCtx->msrKERNELGSBASE));
1910	}
1911	}
1912
1913	#endif /* VBOX_STRICT */
1914

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 87543

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