| 1 | ; $Id: HMR0Mixed.mac 48326 2013-09-05 20:41:59Z vboxsync $
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| 2 | ;; @file
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| 3 | ; HM - Ring-0 Host 32/64, Guest 32/64 world-switch routines
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| 4 | ;
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| 5 | ; Darwin uses this to build two versions in the hybrid case.
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| 6 | ; Included by HMR0A.asm with RT_ARCH_AMD64 defined or undefined.
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| 7 | ;
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| 8 |
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| 9 | ;
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| 10 | ; Copyright (C) 2006-2013 Oracle Corporation
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| 11 | ;
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| 12 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 13 | ; available from http://www.virtualbox.org. This file is free software;
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| 14 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 15 | ; General Public License (GPL) as published by the Free Software
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| 16 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 17 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 18 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 19 | ;
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| 20 |
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| 21 | %ifdef RT_ARCH_AMD64
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| 22 | ;;
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| 23 | ; Keep these macro definitions in this file as it gets included and compiled
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| 24 | ; with RT_ARCH_AMD64 once and RT_ARCH_X86 once.
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| 25 | %define VMX_SKIP_GDTR
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| 26 | %ifndef RT_OS_DARWIN
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| 27 | ; Darwin (Mavericks) uses IDTR limit to store the CPUID so we need to restore it always. See @bugref{6875}.
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| 28 | %define VMX_SKIP_IDTR
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| 29 | %endif
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| 30 | %define VMX_SKIP_TR
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| 31 | %endif
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| 32 |
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| 33 | ;; @def RESTORESTATEVM32
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| 34 | ; Macro restoring essential host state and updating guest state
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| 35 | ; for common host, 32-bit guest for VT-x.
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| 36 | ;
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| 37 | ; @param 1 Jump label suffix 1.
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| 38 | ; @param 2 Jump label suffix 2.
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| 39 | ; @param 3 Jump label suffix 3.
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| 40 | %macro RESTORESTATEVM32 3
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| 41 | ; Restore base and limit of the IDTR & GDTR.
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| 42 | %ifndef VMX_SKIP_IDTR
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| 43 | lidt [xSP]
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| 44 | add xSP, xCB * 2
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| 45 | %endif
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| 46 | %ifndef VMX_SKIP_GDTR
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| 47 | lgdt [xSP]
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| 48 | add xSP, xCB * 2
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| 49 | %endif
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| 50 |
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| 51 | push xDI
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| 52 | %ifndef VMX_SKIP_TR
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| 53 | mov xDI, [xSP + xCB * 3] ; pCtx (*3 to skip the saved xDI, TR, LDTR).
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| 54 | %else
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| 55 | mov xDI, [xSP + xCB * 2] ; pCtx (*2 to skip the saved xDI, LDTR).
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| 56 | %endif
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| 57 |
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| 58 | mov [ss:xDI + CPUMCTX.eax], eax
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| 59 | mov [ss:xDI + CPUMCTX.ebx], ebx
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| 60 | mov [ss:xDI + CPUMCTX.ecx], ecx
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| 61 | mov [ss:xDI + CPUMCTX.edx], edx
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| 62 | mov [ss:xDI + CPUMCTX.esi], esi
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| 63 | mov [ss:xDI + CPUMCTX.ebp], ebp
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| 64 | mov xAX, cr2
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| 65 | mov [ss:xDI + CPUMCTX.cr2], xAX
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| 66 |
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| 67 | %ifdef RT_ARCH_AMD64
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| 68 | pop xAX ; The guest edi we pushed above.
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| 69 | mov dword [ss:xDI + CPUMCTX.edi], eax
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| 70 | %else
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| 71 | pop dword [ss:xDI + CPUMCTX.edi] ; The guest edi we pushed above.
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| 72 | %endif
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| 73 |
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| 74 | %ifndef VMX_SKIP_TR
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| 75 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
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| 76 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
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| 77 | ; @todo get rid of sgdt
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| 78 | pop xBX ; Saved TR
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| 79 | sub xSP, xCB * 2
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| 80 | sgdt [xSP]
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| 81 | mov xAX, xBX
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| 82 | and eax, X86_SEL_MASK_OFF_RPL ; Mask away TI and RPL bits leaving only the descriptor offset.
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| 83 | add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
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| 84 | and dword [ss:xAX + 4], ~RT_BIT(9) ; Clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit).
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| 85 | ltr bx
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| 86 | add xSP, xCB * 2
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| 87 | %endif
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| 88 |
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| 89 | pop xAX ; Saved LDTR
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| 90 | %ifdef RT_ARCH_AMD64
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| 91 | cmp eax, 0
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| 92 | je .skipldtwrite32%1
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| 93 | %endif
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| 94 | lldt ax
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| 95 |
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| 96 | .skipldtwrite32%1:
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| 97 | add xSP, xCB ; pCtx
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| 98 |
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| 99 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 100 | pop xDX ; Saved pCache
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| 101 |
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| 102 | ; Note! If we get here as a result of invalid VMCS pointer, all the following
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| 103 | ; vmread's will fail (only eflags.cf=1 will be set) but that shouldn't cause any
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| 104 | ; trouble only just less efficient.
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| 105 | mov ecx, [ss:xDX + VMCSCACHE.Read.cValidEntries]
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| 106 | cmp ecx, 0 ; Can't happen
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| 107 | je .no_cached_read32%2
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| 108 | jmp .cached_read32%3
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| 109 |
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| 110 | ALIGN(16)
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| 111 | .cached_read32%3:
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| 112 | dec xCX
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| 113 | mov eax, [ss:xDX + VMCSCACHE.Read.aField + xCX * 4]
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| 114 | vmread [ss:xDX + VMCSCACHE.Read.aFieldVal + xCX * 8], xAX
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| 115 | cmp xCX, 0
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| 116 | jnz .cached_read32%3
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| 117 | .no_cached_read32%2:
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| 118 | %endif
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| 119 |
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| 120 | ; Restore segment registers.
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| 121 | MYPOPSEGS xAX, ax
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| 122 |
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| 123 | ; Restore general purpose registers.
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| 124 | MYPOPAD
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| 125 | %endmacro
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| 126 |
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| 127 |
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| 128 | ;/**
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| 129 | ; * Prepares for and executes VMLAUNCH/VMRESUME (32 bits guest mode)
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| 130 | ; *
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| 131 | ; * @returns VBox status code
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| 132 | ; * @param fResume x86:[ebp+8], msc:rcx,gcc:rdi vmlauch/vmresume
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| 133 | ; * @param pCtx x86:[ebp+c], msc:rdx,gcc:rsi Guest context
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| 134 | ; * @param pCache x86:[esp+10],msc:r8, gcc:rdx VMCS cache
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| 135 | ; */
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| 136 | ALIGNCODE(16)
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| 137 | BEGINPROC MY_NAME(VMXR0StartVM32)
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| 138 | push xBP
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| 139 | mov xBP, xSP
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| 140 |
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| 141 | pushf
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| 142 | cli
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| 143 |
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| 144 | ; Save all general purpose host registers.
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| 145 | MYPUSHAD
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| 146 |
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| 147 | ; First we have to save some final CPU context registers.
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| 148 | mov eax, VMX_VMCS_HOST_RIP
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| 149 | %ifdef RT_ARCH_AMD64
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| 150 | lea r10, [.vmlaunch_done wrt rip]
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| 151 | vmwrite rax, r10
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| 152 | %else
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| 153 | mov ecx, .vmlaunch_done
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| 154 | vmwrite eax, ecx
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| 155 | %endif
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| 156 | ; Note: assumes success!
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| 157 |
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| 158 | ; Save the Guest CPU context pointer.
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| 159 | %ifdef RT_ARCH_AMD64
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| 160 | %ifdef ASM_CALL64_GCC
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| 161 | ; fResume already in rdi
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| 162 | ; pCtx already in rsi
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| 163 | mov rbx, rdx ; pCache
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| 164 | %else
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| 165 | mov rdi, rcx ; fResume
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| 166 | mov rsi, rdx ; pCtx
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| 167 | mov rbx, r8 ; pCache
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| 168 | %endif
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| 169 | %else
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| 170 | mov edi, [ebp + 8] ; fResume
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| 171 | mov esi, [ebp + 12] ; pCtx
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| 172 | mov ebx, [ebp + 16] ; pCache
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| 173 | %endif
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| 174 |
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| 175 | ; Save segment registers.
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| 176 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case).
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| 177 | MYPUSHSEGS xAX, ax
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| 178 |
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| 179 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 180 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
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| 181 | cmp ecx, 0
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| 182 | je .no_cached_writes
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| 183 | mov edx, ecx
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| 184 | mov ecx, 0
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| 185 | jmp .cached_write
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| 186 |
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| 187 | ALIGN(16)
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| 188 | .cached_write:
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| 189 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX * 4]
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| 190 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX * 8]
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| 191 | inc xCX
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| 192 | cmp xCX, xDX
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| 193 | jl .cached_write
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| 194 |
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| 195 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
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| 196 | .no_cached_writes:
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| 197 |
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| 198 | ; Save the pCache pointer.
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| 199 | push xBX
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| 200 | %endif
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| 201 |
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| 202 | ; Save the pCtx pointer.
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| 203 | push xSI
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| 204 |
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| 205 | ; Save LDTR.
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| 206 | xor eax, eax
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| 207 | sldt ax
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| 208 | push xAX
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| 209 |
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| 210 | %ifndef VMX_SKIP_TR
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| 211 | ; The TR limit is reset to 0x67; restore it manually.
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| 212 | str eax
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| 213 | push xAX
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| 214 | %endif
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| 215 |
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| 216 | %ifndef VMX_SKIP_GDTR
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| 217 | ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
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| 218 | sub xSP, xCB * 2
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| 219 | sgdt [xSP]
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| 220 | %endif
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| 221 | %ifndef VMX_SKIP_IDTR
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| 222 | sub xSP, xCB * 2
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| 223 | sidt [xSP]
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| 224 | %endif
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| 225 |
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| 226 | ; Load CR2 if necessary (may be expensive as writing CR2 is a synchronizing instruction).
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| 227 | mov xBX, [xSI + CPUMCTX.cr2]
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| 228 | mov xDX, cr2
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| 229 | cmp xBX, xDX
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| 230 | je .skipcr2write32
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| 231 | mov cr2, xBX
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| 232 |
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| 233 | .skipcr2write32:
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| 234 | mov eax, VMX_VMCS_HOST_RSP
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| 235 | vmwrite xAX, xSP
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| 236 | ; Note: assumes success!
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| 237 | ; Don't mess with ESP anymore!!!
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| 238 |
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| 239 | ; Load Guest's general purpose registers.
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| 240 | mov eax, [xSI + CPUMCTX.eax]
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| 241 | mov ebx, [xSI + CPUMCTX.ebx]
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| 242 | mov ecx, [xSI + CPUMCTX.ecx]
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| 243 | mov edx, [xSI + CPUMCTX.edx]
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| 244 | mov ebp, [xSI + CPUMCTX.ebp]
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| 245 |
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| 246 | ; Resume or start?
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| 247 | cmp xDI, 0 ; fResume
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| 248 | je .vmlaunch_launch
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| 249 |
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| 250 | ; Restore edi & esi.
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| 251 | mov edi, [xSI + CPUMCTX.edi]
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| 252 | mov esi, [xSI + CPUMCTX.esi]
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| 253 |
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| 254 | vmresume
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| 255 | jmp .vmlaunch_done; ; Here if vmresume detected a failure.
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| 256 |
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| 257 | .vmlaunch_launch:
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| 258 | ; Restore edi & esi.
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| 259 | mov edi, [xSI + CPUMCTX.edi]
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| 260 | mov esi, [xSI + CPUMCTX.esi]
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| 261 |
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| 262 | vmlaunch
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| 263 | jmp .vmlaunch_done; ; Here if vmlaunch detected a failure.
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| 264 |
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| 265 | ALIGNCODE(16) ;; @todo YASM BUG - this alignment is wrong on darwin, it's 1 byte off.
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| 266 | .vmlaunch_done:
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| 267 | jc near .vmxstart_invalid_vmcs_ptr
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| 268 | jz near .vmxstart_start_failed
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| 269 |
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| 270 | RESTORESTATEVM32 A, B, C
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| 271 | mov eax, VINF_SUCCESS
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| 272 |
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| 273 | .vmstart_end:
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| 274 | popf
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| 275 | pop xBP
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| 276 | ret
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| 277 |
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| 278 | .vmxstart_invalid_vmcs_ptr:
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| 279 | RESTORESTATEVM32 D, E, F
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| 280 | mov eax, VERR_VMX_INVALID_VMCS_PTR_TO_START_VM
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| 281 | jmp .vmstart_end
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| 282 |
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| 283 | .vmxstart_start_failed:
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| 284 | RESTORESTATEVM32 G, H, I
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| 285 | mov eax, VERR_VMX_UNABLE_TO_START_VM
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| 286 | jmp .vmstart_end
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| 287 |
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| 288 | ENDPROC MY_NAME(VMXR0StartVM32)
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| 289 |
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| 290 |
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| 291 | %ifdef RT_ARCH_AMD64
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| 292 | ;; @def RESTORESTATEVM64
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| 293 | ; Macro restoring essential host state and updating guest state
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| 294 | ; for 64-bit host, 64-bit guest for VT-x.
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| 295 | ;
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| 296 | ; @param 1 Jump label suffix 1.
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| 297 | ; @param 2 Jump label suffix 2.
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| 298 | ; @param 3 Jump label suffix 3.
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| 299 | %macro RESTORESTATEVM64 3
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| 300 | ; Restore base and limit of the IDTR & GDTR
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| 301 | %ifndef VMX_SKIP_IDTR
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| 302 | lidt [xSP]
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| 303 | add xSP, xCB * 2
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| 304 | %endif
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| 305 | %ifndef VMX_SKIP_GDTR
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| 306 | lgdt [xSP]
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| 307 | add xSP, xCB * 2
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| 308 | %endif
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| 309 |
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| 310 | push xDI
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| 311 | %ifndef VMX_SKIP_TR
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| 312 | mov xDI, [xSP + xCB * 3] ; pCtx (*3 to skip the saved xDI, TR, LDTR)
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| 313 | %else
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| 314 | mov xDI, [xSP + xCB * 2] ; pCtx (*2 to skip the saved xDI, LDTR)
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| 315 | %endif
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| 316 |
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| 317 | mov qword [xDI + CPUMCTX.eax], rax
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| 318 | mov qword [xDI + CPUMCTX.ebx], rbx
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| 319 | mov qword [xDI + CPUMCTX.ecx], rcx
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| 320 | mov qword [xDI + CPUMCTX.edx], rdx
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| 321 | mov qword [xDI + CPUMCTX.esi], rsi
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| 322 | mov qword [xDI + CPUMCTX.ebp], rbp
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| 323 | mov qword [xDI + CPUMCTX.r8], r8
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| 324 | mov qword [xDI + CPUMCTX.r9], r9
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| 325 | mov qword [xDI + CPUMCTX.r10], r10
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| 326 | mov qword [xDI + CPUMCTX.r11], r11
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| 327 | mov qword [xDI + CPUMCTX.r12], r12
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| 328 | mov qword [xDI + CPUMCTX.r13], r13
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| 329 | mov qword [xDI + CPUMCTX.r14], r14
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| 330 | mov qword [xDI + CPUMCTX.r15], r15
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| 331 | mov rax, cr2
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| 332 | mov qword [xDI + CPUMCTX.cr2], rax
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| 333 |
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| 334 | pop xAX ; The guest edi we pushed above
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| 335 | mov qword [xDI + CPUMCTX.edi], rax
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| 336 |
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| 337 | %ifndef VMX_SKIP_TR
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| 338 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
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| 339 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p).
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| 340 | ; @todo get rid of sgdt
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| 341 | pop xBX ; Saved TR
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| 342 | sub xSP, xCB * 2
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| 343 | sgdt [xSP]
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| 344 | mov xAX, xBX
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| 345 | and eax, X86_SEL_MASK_OFF_RPL ; Mask away TI and RPL bits leaving only the descriptor offset.
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| 346 | add xAX, [xSP + 2] ; eax <- GDTR.address + descriptor offset.
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| 347 | and dword [xAX + 4], ~RT_BIT(9) ; Clear the busy flag in TSS desc (bits 0-7=base, bit 9=busy bit).
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| 348 | ltr bx
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| 349 | add xSP, xCB * 2
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| 350 | %endif
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| 351 |
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| 352 | pop xAX ; Saved LDTR
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| 353 | cmp eax, 0
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| 354 | je .skipldtwrite64%1
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| 355 | lldt ax
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| 356 |
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| 357 | .skipldtwrite64%1:
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| 358 | pop xSI ; pCtx (needed in rsi by the macros below)
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| 359 |
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| 360 | %ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
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| 361 | ; Save the guest MSRs and load the host MSRs.
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| 362 | LOADHOSTMSREX MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
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| 363 | LOADHOSTMSREX MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
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| 364 | LOADHOSTMSREX MSR_K6_STAR, CPUMCTX.msrSTAR
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| 365 | LOADHOSTMSREX MSR_K8_LSTAR, CPUMCTX.msrLSTAR
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| 366 | %endif
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| 367 |
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| 368 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 369 | pop xDX ; Saved pCache
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| 370 |
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| 371 | ; Note! If we get here as a result of invalid VMCS pointer, all the following
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| 372 | ; vmread's will fail (only eflags.cf=1 will be set) but that shouldn't cause any
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| 373 | ; trouble only just less efficient.
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| 374 | mov ecx, [xDX + VMCSCACHE.Read.cValidEntries]
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| 375 | cmp ecx, 0 ; Can't happen
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| 376 | je .no_cached_read64%2
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| 377 | jmp .cached_read64%3
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| 378 |
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| 379 | ALIGN(16)
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| 380 | .cached_read64%3:
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| 381 | dec xCX
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| 382 | mov eax, [xDX + VMCSCACHE.Read.aField + xCX * 4]
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| 383 | vmread [xDX + VMCSCACHE.Read.aFieldVal + xCX * 8], xAX
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| 384 | cmp xCX, 0
|
|---|
| 385 | jnz .cached_read64%3
|
|---|
| 386 | .no_cached_read64%2:
|
|---|
| 387 | %endif
|
|---|
| 388 |
|
|---|
| 389 | ; Restore segment registers.
|
|---|
| 390 | MYPOPSEGS xAX, ax
|
|---|
| 391 |
|
|---|
| 392 | ; Restore general purpose registers.
|
|---|
| 393 | MYPOPAD
|
|---|
| 394 | %endmacro
|
|---|
| 395 |
|
|---|
| 396 |
|
|---|
| 397 | ;/**
|
|---|
| 398 | ; * Prepares for and executes VMLAUNCH/VMRESUME (64 bits guest mode)
|
|---|
| 399 | ; *
|
|---|
| 400 | ; * @returns VBox status code
|
|---|
| 401 | ; * @param fResume msc:rcx, gcc:rdi vmlauch/vmresume
|
|---|
| 402 | ; * @param pCtx msc:rdx, gcc:rsi Guest context
|
|---|
| 403 | ; * @param pCache msc:r8, gcc:rdx VMCS cache
|
|---|
| 404 | ; */
|
|---|
| 405 | ALIGNCODE(16)
|
|---|
| 406 | BEGINPROC MY_NAME(VMXR0StartVM64)
|
|---|
| 407 | push xBP
|
|---|
| 408 | mov xBP, xSP
|
|---|
| 409 |
|
|---|
| 410 | pushf
|
|---|
| 411 | cli
|
|---|
| 412 |
|
|---|
| 413 | ; Save all general purpose host registers.
|
|---|
| 414 | MYPUSHAD
|
|---|
| 415 |
|
|---|
| 416 | ; First we have to save some final CPU context registers.
|
|---|
| 417 | lea r10, [.vmlaunch64_done wrt rip]
|
|---|
| 418 | mov rax, VMX_VMCS_HOST_RIP ; Return address (too difficult to continue after VMLAUNCH?).
|
|---|
| 419 | vmwrite rax, r10
|
|---|
| 420 | ; Note: assumes success!
|
|---|
| 421 |
|
|---|
| 422 | ; Save the Guest CPU context pointer.
|
|---|
| 423 | %ifdef ASM_CALL64_GCC
|
|---|
| 424 | ; fResume already in rdi
|
|---|
| 425 | ; pCtx already in rsi
|
|---|
| 426 | mov rbx, rdx ; pCache
|
|---|
| 427 | %else
|
|---|
| 428 | mov rdi, rcx ; fResume
|
|---|
| 429 | mov rsi, rdx ; pCtx
|
|---|
| 430 | mov rbx, r8 ; pCache
|
|---|
| 431 | %endif
|
|---|
| 432 |
|
|---|
| 433 | ; Save segment registers.
|
|---|
| 434 | ; Note: MYPUSHSEGS trashes rdx & rcx, so we moved it here (msvc amd64 case).
|
|---|
| 435 | MYPUSHSEGS xAX, ax
|
|---|
| 436 |
|
|---|
| 437 | %ifdef VMX_USE_CACHED_VMCS_ACCESSES
|
|---|
| 438 | mov ecx, [xBX + VMCSCACHE.Write.cValidEntries]
|
|---|
| 439 | cmp ecx, 0
|
|---|
| 440 | je .no_cached_writes
|
|---|
| 441 | mov edx, ecx
|
|---|
| 442 | mov ecx, 0
|
|---|
| 443 | jmp .cached_write
|
|---|
| 444 |
|
|---|
| 445 | ALIGN(16)
|
|---|
| 446 | .cached_write:
|
|---|
| 447 | mov eax, [xBX + VMCSCACHE.Write.aField + xCX * 4]
|
|---|
| 448 | vmwrite xAX, [xBX + VMCSCACHE.Write.aFieldVal + xCX * 8]
|
|---|
| 449 | inc xCX
|
|---|
| 450 | cmp xCX, xDX
|
|---|
| 451 | jl .cached_write
|
|---|
| 452 |
|
|---|
| 453 | mov dword [xBX + VMCSCACHE.Write.cValidEntries], 0
|
|---|
| 454 | .no_cached_writes:
|
|---|
| 455 |
|
|---|
| 456 | ; Save the pCache pointer.
|
|---|
| 457 | push xBX
|
|---|
| 458 | %endif
|
|---|
| 459 |
|
|---|
| 460 | %ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
|
|---|
| 461 | ; Save the host MSRs and load the guest MSRs.
|
|---|
| 462 | LOADGUESTMSR MSR_K8_LSTAR, CPUMCTX.msrLSTAR
|
|---|
| 463 | LOADGUESTMSR MSR_K6_STAR, CPUMCTX.msrSTAR
|
|---|
| 464 | LOADGUESTMSR MSR_K8_SF_MASK, CPUMCTX.msrSFMASK
|
|---|
| 465 | LOADGUESTMSR MSR_K8_KERNEL_GS_BASE, CPUMCTX.msrKERNELGSBASE
|
|---|
| 466 | %endif
|
|---|
| 467 |
|
|---|
| 468 | ; Save the pCtx pointer.
|
|---|
| 469 | push xSI
|
|---|
| 470 |
|
|---|
| 471 | ; Save LDTR.
|
|---|
| 472 | xor eax, eax
|
|---|
| 473 | sldt ax
|
|---|
| 474 | push xAX
|
|---|
| 475 |
|
|---|
| 476 | %ifndef VMX_SKIP_TR
|
|---|
| 477 | ; The TR limit is reset to 0x67; restore it manually.
|
|---|
| 478 | str eax
|
|---|
| 479 | push xAX
|
|---|
| 480 | %endif
|
|---|
| 481 |
|
|---|
| 482 | ; VT-x only saves the base of the GDTR & IDTR and resets the limit to 0xffff; we must restore the limit correctly!
|
|---|
| 483 | %ifndef VMX_SKIP_GDTR
|
|---|
| 484 | sub xSP, xCB * 2
|
|---|
| 485 | sgdt [xSP]
|
|---|
| 486 | %endif
|
|---|
| 487 | %ifndef VMX_SKIP_IDTR
|
|---|
| 488 | sub xSP, xCB * 2
|
|---|
| 489 | sidt [xSP]
|
|---|
| 490 | %endif
|
|---|
| 491 |
|
|---|
| 492 | ; Load CR2 if necessary (may be expensive as writing CR2 is a synchronizing instruction).
|
|---|
| 493 | mov rbx, qword [xSI + CPUMCTX.cr2]
|
|---|
| 494 | mov rdx, cr2
|
|---|
| 495 | cmp rbx, rdx
|
|---|
| 496 | je .skipcr2write
|
|---|
| 497 | mov cr2, rbx
|
|---|
| 498 |
|
|---|
| 499 | .skipcr2write:
|
|---|
| 500 | mov eax, VMX_VMCS_HOST_RSP
|
|---|
| 501 | vmwrite xAX, xSP
|
|---|
| 502 | ; Note: assumes success!
|
|---|
| 503 | ; Don't mess with ESP anymore!!!
|
|---|
| 504 |
|
|---|
| 505 | ; Restore Guest's general purpose registers.
|
|---|
| 506 | mov rax, qword [xSI + CPUMCTX.eax]
|
|---|
| 507 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 508 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 509 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 510 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 511 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 512 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 513 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 514 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 515 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 516 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 517 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 518 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 519 |
|
|---|
| 520 | ; Resume or start?
|
|---|
| 521 | cmp xDI, 0 ; fResume
|
|---|
| 522 | je .vmlaunch64_launch
|
|---|
| 523 |
|
|---|
| 524 | ; Restore edi & esi.
|
|---|
| 525 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 526 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 527 |
|
|---|
| 528 | vmresume
|
|---|
| 529 | jmp .vmlaunch64_done; ; Here if vmresume detected a failure.
|
|---|
| 530 |
|
|---|
| 531 | .vmlaunch64_launch:
|
|---|
| 532 | ; Restore rdi & rsi.
|
|---|
| 533 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 534 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 535 |
|
|---|
| 536 | vmlaunch
|
|---|
| 537 | jmp .vmlaunch64_done; ; Here if vmlaunch detected a failure.
|
|---|
| 538 |
|
|---|
| 539 | ALIGNCODE(16)
|
|---|
| 540 | .vmlaunch64_done:
|
|---|
| 541 | jc near .vmxstart64_invalid_vmcs_ptr
|
|---|
| 542 | jz near .vmxstart64_start_failed
|
|---|
| 543 |
|
|---|
| 544 | RESTORESTATEVM64 a, b, c
|
|---|
| 545 | mov eax, VINF_SUCCESS
|
|---|
| 546 |
|
|---|
| 547 | .vmstart64_end:
|
|---|
| 548 | popf
|
|---|
| 549 | pop xBP
|
|---|
| 550 | ret
|
|---|
| 551 |
|
|---|
| 552 | .vmxstart64_invalid_vmcs_ptr:
|
|---|
| 553 | RESTORESTATEVM64 d, e, f
|
|---|
| 554 | mov eax, VERR_VMX_INVALID_VMCS_PTR_TO_START_VM
|
|---|
| 555 | jmp .vmstart64_end
|
|---|
| 556 |
|
|---|
| 557 | .vmxstart64_start_failed:
|
|---|
| 558 | RESTORESTATEVM64 g, h, i
|
|---|
| 559 | mov eax, VERR_VMX_UNABLE_TO_START_VM
|
|---|
| 560 | jmp .vmstart64_end
|
|---|
| 561 | ENDPROC MY_NAME(VMXR0StartVM64)
|
|---|
| 562 | %endif ; RT_ARCH_AMD64
|
|---|
| 563 |
|
|---|
| 564 |
|
|---|
| 565 | ;/**
|
|---|
| 566 | ; * Prepares for and executes VMRUN (32 bits guests)
|
|---|
| 567 | ; *
|
|---|
| 568 | ; * @returns VBox status code
|
|---|
| 569 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 570 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 571 | ; * @param pCtx Guest context
|
|---|
| 572 | ; */
|
|---|
| 573 | ALIGNCODE(16)
|
|---|
| 574 | BEGINPROC MY_NAME(SVMR0VMRun)
|
|---|
| 575 | %ifdef RT_ARCH_AMD64 ; fake a cdecl stack frame
|
|---|
| 576 | %ifdef ASM_CALL64_GCC
|
|---|
| 577 | push rdx
|
|---|
| 578 | push rsi
|
|---|
| 579 | push rdi
|
|---|
| 580 | %else
|
|---|
| 581 | push r8
|
|---|
| 582 | push rdx
|
|---|
| 583 | push rcx
|
|---|
| 584 | %endif
|
|---|
| 585 | push 0
|
|---|
| 586 | %endif
|
|---|
| 587 | push xBP
|
|---|
| 588 | mov xBP, xSP
|
|---|
| 589 | pushf
|
|---|
| 590 |
|
|---|
| 591 | ; Save all general purpose host registers.
|
|---|
| 592 | MYPUSHAD
|
|---|
| 593 |
|
|---|
| 594 | ; Save the Guest CPU context pointer.
|
|---|
| 595 | mov xSI, [xBP + xCB * 2 + RTHCPHYS_CB * 2] ; pCtx
|
|---|
| 596 | push xSI ; push for saving the state at the end
|
|---|
| 597 |
|
|---|
| 598 | ; Save host fs, gs, sysenter msr etc.
|
|---|
| 599 | mov xAX, [xBP + xCB * 2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 600 | push xAX ; save for the vmload after vmrun
|
|---|
| 601 | vmsave
|
|---|
| 602 |
|
|---|
| 603 | ; Setup eax for VMLOAD.
|
|---|
| 604 | mov xAX, [xBP + xCB * 2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 605 |
|
|---|
| 606 | ; Restore Guest's general purpose registers.
|
|---|
| 607 | ; eax is loaded from the VMCB by VMRUN.
|
|---|
| 608 | mov ebx, [xSI + CPUMCTX.ebx]
|
|---|
| 609 | mov ecx, [xSI + CPUMCTX.ecx]
|
|---|
| 610 | mov edx, [xSI + CPUMCTX.edx]
|
|---|
| 611 | mov edi, [xSI + CPUMCTX.edi]
|
|---|
| 612 | mov ebp, [xSI + CPUMCTX.ebp]
|
|---|
| 613 | mov esi, [xSI + CPUMCTX.esi]
|
|---|
| 614 |
|
|---|
| 615 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch.
|
|---|
| 616 | clgi
|
|---|
| 617 | sti
|
|---|
| 618 |
|
|---|
| 619 | ; Load guest fs, gs, sysenter msr etc.
|
|---|
| 620 | vmload
|
|---|
| 621 | ; Run the VM.
|
|---|
| 622 | vmrun
|
|---|
| 623 |
|
|---|
| 624 | ; eax is in the VMCB already; we can use it here.
|
|---|
| 625 |
|
|---|
| 626 | ; Save guest fs, gs, sysenter msr etc.
|
|---|
| 627 | vmsave
|
|---|
| 628 |
|
|---|
| 629 | ; Load host fs, gs, sysenter msr etc.
|
|---|
| 630 | pop xAX ; Pushed above
|
|---|
| 631 | vmload
|
|---|
| 632 |
|
|---|
| 633 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
|---|
| 634 | cli
|
|---|
| 635 | stgi
|
|---|
| 636 |
|
|---|
| 637 | pop xAX ; pCtx
|
|---|
| 638 |
|
|---|
| 639 | mov [ss:xAX + CPUMCTX.ebx], ebx
|
|---|
| 640 | mov [ss:xAX + CPUMCTX.ecx], ecx
|
|---|
| 641 | mov [ss:xAX + CPUMCTX.edx], edx
|
|---|
| 642 | mov [ss:xAX + CPUMCTX.esi], esi
|
|---|
| 643 | mov [ss:xAX + CPUMCTX.edi], edi
|
|---|
| 644 | mov [ss:xAX + CPUMCTX.ebp], ebp
|
|---|
| 645 |
|
|---|
| 646 | ; Restore general purpose registers.
|
|---|
| 647 | MYPOPAD
|
|---|
| 648 |
|
|---|
| 649 | mov eax, VINF_SUCCESS
|
|---|
| 650 |
|
|---|
| 651 | popf
|
|---|
| 652 | pop xBP
|
|---|
| 653 | %ifdef RT_ARCH_AMD64
|
|---|
| 654 | add xSP, 4*xCB
|
|---|
| 655 | %endif
|
|---|
| 656 | ret
|
|---|
| 657 | ENDPROC MY_NAME(SVMR0VMRun)
|
|---|
| 658 |
|
|---|
| 659 | %ifdef RT_ARCH_AMD64
|
|---|
| 660 | ;/**
|
|---|
| 661 | ; * Prepares for and executes VMRUN (64 bits guests)
|
|---|
| 662 | ; *
|
|---|
| 663 | ; * @returns VBox status code
|
|---|
| 664 | ; * @param HCPhysVMCB Physical address of host VMCB
|
|---|
| 665 | ; * @param HCPhysVMCB Physical address of guest VMCB
|
|---|
| 666 | ; * @param pCtx Guest context
|
|---|
| 667 | ; */
|
|---|
| 668 | ALIGNCODE(16)
|
|---|
| 669 | BEGINPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 670 | ; Fake a cdecl stack frame
|
|---|
| 671 | %ifdef ASM_CALL64_GCC
|
|---|
| 672 | push rdx
|
|---|
| 673 | push rsi
|
|---|
| 674 | push rdi
|
|---|
| 675 | %else
|
|---|
| 676 | push r8
|
|---|
| 677 | push rdx
|
|---|
| 678 | push rcx
|
|---|
| 679 | %endif
|
|---|
| 680 | push 0
|
|---|
| 681 | push rbp
|
|---|
| 682 | mov rbp, rsp
|
|---|
| 683 | pushf
|
|---|
| 684 |
|
|---|
| 685 | ; Manual save and restore:
|
|---|
| 686 | ; - General purpose registers except RIP, RSP, RAX
|
|---|
| 687 | ;
|
|---|
| 688 | ; Trashed:
|
|---|
| 689 | ; - CR2 (we don't care)
|
|---|
| 690 | ; - LDTR (reset to 0)
|
|---|
| 691 | ; - DRx (presumably not changed at all)
|
|---|
| 692 | ; - DR7 (reset to 0x400)
|
|---|
| 693 | ;
|
|---|
| 694 |
|
|---|
| 695 | ; Save all general purpose host registers.
|
|---|
| 696 | MYPUSHAD
|
|---|
| 697 |
|
|---|
| 698 | ; Save the Guest CPU context pointer.
|
|---|
| 699 | mov rsi, [rbp + xCB * 2 + RTHCPHYS_CB * 2] ; pCtx
|
|---|
| 700 | push rsi ; push for saving the state at the end
|
|---|
| 701 |
|
|---|
| 702 | ; Save host fs, gs, sysenter msr etc.
|
|---|
| 703 | mov rax, [rbp + xCB * 2] ; pVMCBHostPhys (64 bits physical address; x86: take low dword only)
|
|---|
| 704 | push rax ; Save for the vmload after vmrun
|
|---|
| 705 | vmsave
|
|---|
| 706 |
|
|---|
| 707 | ; Setup eax for VMLOAD.
|
|---|
| 708 | mov rax, [rbp + xCB * 2 + RTHCPHYS_CB] ; pVMCBPhys (64 bits physical address; take low dword only)
|
|---|
| 709 |
|
|---|
| 710 | ; Restore Guest's general purpose registers.
|
|---|
| 711 | ; rax is loaded from the VMCB by VMRUN.
|
|---|
| 712 | mov rbx, qword [xSI + CPUMCTX.ebx]
|
|---|
| 713 | mov rcx, qword [xSI + CPUMCTX.ecx]
|
|---|
| 714 | mov rdx, qword [xSI + CPUMCTX.edx]
|
|---|
| 715 | mov rdi, qword [xSI + CPUMCTX.edi]
|
|---|
| 716 | mov rbp, qword [xSI + CPUMCTX.ebp]
|
|---|
| 717 | mov r8, qword [xSI + CPUMCTX.r8]
|
|---|
| 718 | mov r9, qword [xSI + CPUMCTX.r9]
|
|---|
| 719 | mov r10, qword [xSI + CPUMCTX.r10]
|
|---|
| 720 | mov r11, qword [xSI + CPUMCTX.r11]
|
|---|
| 721 | mov r12, qword [xSI + CPUMCTX.r12]
|
|---|
| 722 | mov r13, qword [xSI + CPUMCTX.r13]
|
|---|
| 723 | mov r14, qword [xSI + CPUMCTX.r14]
|
|---|
| 724 | mov r15, qword [xSI + CPUMCTX.r15]
|
|---|
| 725 | mov rsi, qword [xSI + CPUMCTX.esi]
|
|---|
| 726 |
|
|---|
| 727 | ; Clear the global interrupt flag & execute sti to make sure external interrupts cause a world switch.
|
|---|
| 728 | clgi
|
|---|
| 729 | sti
|
|---|
| 730 |
|
|---|
| 731 | ; Load guest fs, gs, sysenter msr etc.
|
|---|
| 732 | vmload
|
|---|
| 733 | ; Run the VM.
|
|---|
| 734 | vmrun
|
|---|
| 735 |
|
|---|
| 736 | ; rax is in the VMCB already; we can use it here.
|
|---|
| 737 |
|
|---|
| 738 | ; Save guest fs, gs, sysenter msr etc.
|
|---|
| 739 | vmsave
|
|---|
| 740 |
|
|---|
| 741 | ; Load host fs, gs, sysenter msr etc.
|
|---|
| 742 | pop rax ; pushed above
|
|---|
| 743 | vmload
|
|---|
| 744 |
|
|---|
| 745 | ; Set the global interrupt flag again, but execute cli to make sure IF=0.
|
|---|
| 746 | cli
|
|---|
| 747 | stgi
|
|---|
| 748 |
|
|---|
| 749 | pop rax ; pCtx
|
|---|
| 750 |
|
|---|
| 751 | mov qword [rax + CPUMCTX.ebx], rbx
|
|---|
| 752 | mov qword [rax + CPUMCTX.ecx], rcx
|
|---|
| 753 | mov qword [rax + CPUMCTX.edx], rdx
|
|---|
| 754 | mov qword [rax + CPUMCTX.esi], rsi
|
|---|
| 755 | mov qword [rax + CPUMCTX.edi], rdi
|
|---|
| 756 | mov qword [rax + CPUMCTX.ebp], rbp
|
|---|
| 757 | mov qword [rax + CPUMCTX.r8], r8
|
|---|
| 758 | mov qword [rax + CPUMCTX.r9], r9
|
|---|
| 759 | mov qword [rax + CPUMCTX.r10], r10
|
|---|
| 760 | mov qword [rax + CPUMCTX.r11], r11
|
|---|
| 761 | mov qword [rax + CPUMCTX.r12], r12
|
|---|
| 762 | mov qword [rax + CPUMCTX.r13], r13
|
|---|
| 763 | mov qword [rax + CPUMCTX.r14], r14
|
|---|
| 764 | mov qword [rax + CPUMCTX.r15], r15
|
|---|
| 765 |
|
|---|
| 766 | ; Restore general purpose registers.
|
|---|
| 767 | MYPOPAD
|
|---|
| 768 |
|
|---|
| 769 | mov eax, VINF_SUCCESS
|
|---|
| 770 |
|
|---|
| 771 | popf
|
|---|
| 772 | pop rbp
|
|---|
| 773 | add rsp, 4 * xCB
|
|---|
| 774 | ret
|
|---|
| 775 | ENDPROC MY_NAME(SVMR0VMRun64)
|
|---|
| 776 | %endif ; RT_ARCH_AMD64
|
|---|
| 777 |
|
|---|
