HMSVMR0.cpp@ 71076

Last change on this file since 71076 was 71004, checked in by vboxsync, 7 years ago
VMM/HMSVMR0: Nested Hw.virt: Fix intercepting VMMCALL while executing the nested-guest (required for Hyper-V, KVM paravirt. nested VMs)
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1	/* $Id: HMSVMR0.cpp 71004 2018-02-14 07:58:57Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#define HMSVM_USE_IEM_EVENT_REFLECTION
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_SYNC_FULL_NESTED_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60	#else
61	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
62	#endif
63
64	/** If we decide to use a function table approach this can be useful to
65	* switch to a "static DECLCALLBACK(int)". */
66	#define HMSVM_EXIT_DECL static int
67
68	/** Macro for checking and returning from the using function for
69	* \#VMEXIT intercepts that maybe caused during delivering of another
70	* event in the guest. */
71	#ifdef VBOX_WITH_NESTED_HWVIRT
72	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
73	do \
74	{ \
75	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
76	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
77	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
78	else if ( rc == VINF_EM_RESET \
79	&& HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
80	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_SHUTDOWN, 0, 0)); \
81	else \
82	return rc; \
83	} while (0)
84	#else
85	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
86	do \
87	{ \
88	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
89	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
90	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
91	else \
92	return rc; \
93	} while (0)
94	#endif
95
96	/**
97	* Updates interrupt shadow for the current RIP.
98	*/
99	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
100	do { \
101	/* Update interrupt shadow. */ \
102	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
103	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
104	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
105	} while (0)
106
107	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
108	* instruction that exited. */
109	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
110	do { \
111	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
112	(a_rc) = VINF_EM_DBG_STEPPED; \
113	} while (0)
114
115	/** Assert that preemption is disabled or covered by thread-context hooks. */
116	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
117	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
118
119	/** Assert that we haven't migrated CPUs when thread-context hooks are not
120	* used. */
121	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
122	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
123	("Illegal migration! Entered on CPU %u Current %u\n", \
124	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
125
126	/** Assert that we're not executing a nested-guest. */
127	#ifdef VBOX_WITH_NESTED_HWVIRT
128	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
129	#else
130	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
131	#endif
132
133	/** Assert that we're executing a nested-guest. */
134	#ifdef VBOX_WITH_NESTED_HWVIRT
135	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
136	#else
137	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
138	#endif
139
140	/** Validate segment descriptor granularity bit. */
141	#ifdef VBOX_STRICT
142	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
143	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
144	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
145	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
146	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
147	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
148	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
149	#else
150	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) do { } while (0)
151	#endif
152
153	/**
154	* Exception bitmap mask for all contributory exceptions.
155	*
156	* Page fault is deliberately excluded here as it's conditional as to whether
157	* it's contributory or benign. Page faults are handled separately.
158	*/
159	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
160	\| RT_BIT(X86_XCPT_DE))
161
162	/**
163	* Mandatory/unconditional guest control intercepts.
164	*
165	* SMIs can and do happen in normal operation. We need not intercept them
166	* while executing the guest or nested-guest.
167	*/
168	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
169	\| SVM_CTRL_INTERCEPT_NMI \
170	\| SVM_CTRL_INTERCEPT_INIT \
171	\| SVM_CTRL_INTERCEPT_RDPMC \
172	\| SVM_CTRL_INTERCEPT_CPUID \
173	\| SVM_CTRL_INTERCEPT_RSM \
174	\| SVM_CTRL_INTERCEPT_HLT \
175	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
176	\| SVM_CTRL_INTERCEPT_MSR_PROT \
177	\| SVM_CTRL_INTERCEPT_INVLPGA \
178	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
179	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
180	\| SVM_CTRL_INTERCEPT_VMRUN \
181	\| SVM_CTRL_INTERCEPT_SKINIT \
182	\| SVM_CTRL_INTERCEPT_WBINVD \
183	\| SVM_CTRL_INTERCEPT_MONITOR \
184	\| SVM_CTRL_INTERCEPT_MWAIT \
185	\| SVM_CTRL_INTERCEPT_XSETBV)
186
187	/** @name VMCB Clean Bits.
188	*
189	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
190	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
191	* memory.
192	*
193	* @{ */
194	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
195	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
196	/** I/O permission bitmap, MSR permission bitmap. */
197	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
198	/** ASID. */
199	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
200	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
201	V_INTR_VECTOR. */
202	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
203	/** Nested Paging: Nested CR3 (nCR3), PAT. */
204	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
205	/** Control registers (CR0, CR3, CR4, EFER). */
206	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
207	/** Debug registers (DR6, DR7). */
208	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
209	/** GDT, IDT limit and base. */
210	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
211	/** Segment register: CS, SS, DS, ES limit and base. */
212	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
213	/** CR2.*/
214	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
215	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
216	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
217	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
218	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
219	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
220	/** Mask of all valid VMCB Clean bits. */
221	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
222	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
223	\| HMSVM_VMCB_CLEAN_ASID \
224	\| HMSVM_VMCB_CLEAN_TPR \
225	\| HMSVM_VMCB_CLEAN_NP \
226	\| HMSVM_VMCB_CLEAN_CRX_EFER \
227	\| HMSVM_VMCB_CLEAN_DRX \
228	\| HMSVM_VMCB_CLEAN_DT \
229	\| HMSVM_VMCB_CLEAN_SEG \
230	\| HMSVM_VMCB_CLEAN_CR2 \
231	\| HMSVM_VMCB_CLEAN_LBR \
232	\| HMSVM_VMCB_CLEAN_AVIC)
233	/** @} */
234
235	/** @name SVM transient.
236	*
237	* A state structure for holding miscellaneous information across AMD-V
238	* VMRUN/\#VMEXIT operation, restored after the transition.
239	*
240	* @{ */
241	typedef struct SVMTRANSIENT
242	{
243	/** The host's rflags/eflags. */
244	RTCCUINTREG fEFlags;
245	#if HC_ARCH_BITS == 32
246	uint32_t u32Alignment0;
247	#endif
248
249	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
250	uint64_t u64ExitCode;
251	/** The guest's TPR value used for TPR shadowing. */
252	uint8_t u8GuestTpr;
253	/** Alignment. */
254	uint8_t abAlignment0[7];
255
256	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
257	bool fWasGuestFPUStateActive;
258	/** Whether the guest debug state was active at the time of \#VMEXIT. */
259	bool fWasGuestDebugStateActive;
260	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
261	bool fWasHyperDebugStateActive;
262	/** Whether the TSC offset mode needs to be updated. */
263	bool fUpdateTscOffsetting;
264	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
265	bool fRestoreTscAuxMsr;
266	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
267	* contributary exception or a page-fault. */
268	bool fVectoringDoublePF;
269	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
270	* external interrupt or NMI. */
271	bool fVectoringPF;
272	} SVMTRANSIENT, *PSVMTRANSIENT;
273	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
274	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
275	/** @} */
276
277	/**
278	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
279	*/
280	typedef enum SVMMSREXITREAD
281	{
282	/** Reading this MSR causes a \#VMEXIT. */
283	SVMMSREXIT_INTERCEPT_READ = 0xb,
284	/** Reading this MSR does not cause a \#VMEXIT. */
285	SVMMSREXIT_PASSTHRU_READ
286	} SVMMSREXITREAD;
287
288	/**
289	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
290	*/
291	typedef enum SVMMSREXITWRITE
292	{
293	/** Writing to this MSR causes a \#VMEXIT. */
294	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
295	/** Writing to this MSR does not cause a \#VMEXIT. */
296	SVMMSREXIT_PASSTHRU_WRITE
297	} SVMMSREXITWRITE;
298
299	/**
300	* SVM \#VMEXIT handler.
301	*
302	* @returns VBox status code.
303	* @param pVCpu The cross context virtual CPU structure.
304	* @param pMixedCtx Pointer to the guest-CPU context.
305	* @param pSvmTransient Pointer to the SVM-transient structure.
306	*/
307	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
308
309
310	/*********************************************************************************************************************************
311	* Internal Functions *
312	*********************************************************************************************************************************/
313	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
314	SVMMSREXITWRITE enmWrite);
315	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
316	static void hmR0SvmLeave(PVMCPU pVCpu);
317
318	/** @name \#VMEXIT handlers.
319	* @{
320	*/
321	static FNSVMEXITHANDLER hmR0SvmExitIntr;
322	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
323	static FNSVMEXITHANDLER hmR0SvmExitInvd;
324	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
325	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
326	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
327	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
328	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
329	static FNSVMEXITHANDLER hmR0SvmExitHlt;
330	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
331	static FNSVMEXITHANDLER hmR0SvmExitMwait;
332	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
333	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
334	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
335	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
336	static FNSVMEXITHANDLER hmR0SvmExitMsr;
337	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
338	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
339	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
340	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
341	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
342	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
343	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
344	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
345	static FNSVMEXITHANDLER hmR0SvmExitPause;
346	static FNSVMEXITHANDLER hmR0SvmExitIret;
347	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
348	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
349	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
350	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
351	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
352	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
353	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
354	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
355	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
356	#endif
357	#ifdef VBOX_WITH_NESTED_HWVIRT
358	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
359	static FNSVMEXITHANDLER hmR0SvmExitClgi;
360	static FNSVMEXITHANDLER hmR0SvmExitStgi;
361	static FNSVMEXITHANDLER hmR0SvmExitVmload;
362	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
363	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
364	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
365	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
366	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
367	#endif
368	/** @} */
369
370	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
371	#ifdef VBOX_WITH_NESTED_HWVIRT
372	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
373	#endif
374
375
376	/*********************************************************************************************************************************
377	* Global Variables *
378	*********************************************************************************************************************************/
379	/** Ring-0 memory object for the IO bitmap. */
380	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
381	/** Physical address of the IO bitmap. */
382	RTHCPHYS g_HCPhysIOBitmap = 0;
383	/** Pointer to the IO bitmap. */
384	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
385
386	#ifdef VBOX_WITH_NESTED_HWVIRT
387	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
388	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
389	/** Physical address of the nested-guest MSRPM bitmap. */
390	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
391	/** Pointer to the nested-guest MSRPM bitmap. */
392	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
393	#endif
394
395
396	#ifdef VBOX_STRICT
397	# define HMSVM_LOG_CS RT_BIT_32(0)
398	# define HMSVM_LOG_SS RT_BIT_32(1)
399	# define HMSVM_LOG_FS RT_BIT_32(2)
400	# define HMSVM_LOG_GS RT_BIT_32(3)
401	# define HMSVM_LOG_LBR RT_BIT_32(4)
402	# define HMSVM_LOG_ALL ( HMSVM_LOG_CS \
403	\| HMSVM_LOG_SS \
404	\| HMSVM_LOG_FS \
405	\| HMSVM_LOG_GS \
406	\| HMSVM_LOG_LBR)
407
408	/**
409	* Dumps CPU state and additional info. to the logger for diagnostics.
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param pVmcb Pointer to the VM control block.
413	* @param pCtx Pointer to the guest-CPU context.
414	* @param pszPrefix Log prefix.
415	* @param fFlags Log flags, see HMSVM_LOG_XXX.
416	* @param uVerbose The verbosity level, currently unused.
417	*/
418	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, PCPUMCTX pCtx, const char *pszPrefix, uint32_t fFlags,
419	uint8_t uVerbose)
420	{
421	RT_NOREF2(pVCpu, uVerbose);
422
423	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip,
424	pCtx->rflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
425	Log4(("%s: rsp=%#RX64 rbp=%#RX64 rdi=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp, pCtx->rdi));
426	if (fFlags & HMSVM_LOG_CS)
427	{
428	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
429	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
430	}
431	if (fFlags & HMSVM_LOG_SS)
432	{
433	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
434	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
435	}
436	if (fFlags & HMSVM_LOG_FS)
437	{
438	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
439	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
440	}
441	if (fFlags & HMSVM_LOG_GS)
442	{
443	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
444	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
445	}
446
447	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
448	if (fFlags & HMSVM_LOG_LBR)
449	{
450	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
451	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
452	}
453	NOREF(pVmcbGuest);
454	}
455	#endif
456
457
458	/**
459	* Sets up and activates AMD-V on the current CPU.
460	*
461	* @returns VBox status code.
462	* @param pCpu Pointer to the CPU info struct.
463	* @param pVM The cross context VM structure. Can be
464	* NULL after a resume!
465	* @param pvCpuPage Pointer to the global CPU page.
466	* @param HCPhysCpuPage Physical address of the global CPU page.
467	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
468	* @param pvArg Unused on AMD-V.
469	*/
470	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
471	void *pvArg)
472	{
473	Assert(!fEnabledByHost);
474	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
475	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
476	Assert(pvCpuPage); NOREF(pvCpuPage);
477	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
478
479	NOREF(pvArg);
480	NOREF(fEnabledByHost);
481
482	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
483	RTCCUINTREG fEFlags = ASMIntDisableFlags();
484
485	/*
486	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
487	*/
488	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
489	if (u64HostEfer & MSR_K6_EFER_SVME)
490	{
491	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
492	if ( pVM
493	&& pVM->hm.s.svm.fIgnoreInUseError)
494	{
495	pCpu->fIgnoreAMDVInUseError = true;
496	}
497
498	if (!pCpu->fIgnoreAMDVInUseError)
499	{
500	ASMSetFlags(fEFlags);
501	return VERR_SVM_IN_USE;
502	}
503	}
504
505	/* Turn on AMD-V in the EFER MSR. */
506	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
507
508	/* Write the physical page address where the CPU will store the host state while executing the VM. */
509	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
510
511	/* Restore interrupts. */
512	ASMSetFlags(fEFlags);
513
514	/*
515	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
516	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
517	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
518	* guest code.
519	*/
520	pCpu->fFlushAsidBeforeUse = true;
521
522	/*
523	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
524	*/
525	++pCpu->cTlbFlushes;
526
527	return VINF_SUCCESS;
528	}
529
530
531	/**
532	* Deactivates AMD-V on the current CPU.
533	*
534	* @returns VBox status code.
535	* @param pCpu Pointer to the CPU info struct.
536	* @param pvCpuPage Pointer to the global CPU page.
537	* @param HCPhysCpuPage Physical address of the global CPU page.
538	*/
539	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
540	{
541	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
542	AssertReturn( HCPhysCpuPage
543	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
544	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
545	NOREF(pCpu);
546
547	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG fEFlags = ASMIntDisableFlags();
549
550	/* Turn off AMD-V in the EFER MSR. */
551	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
552	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
553
554	/* Invalidate host state physical address. */
555	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
556
557	/* Restore interrupts. */
558	ASMSetFlags(fEFlags);
559
560	return VINF_SUCCESS;
561	}
562
563
564	/**
565	* Does global AMD-V initialization (called during module initialization).
566	*
567	* @returns VBox status code.
568	*/
569	VMMR0DECL(int) SVMR0GlobalInit(void)
570	{
571	/*
572	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
573	* once globally here instead of per-VM.
574	*/
575	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
576	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
577	if (RT_FAILURE(rc))
578	return rc;
579
580	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
581	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
582
583	/* Set all bits to intercept all IO accesses. */
584	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
585
586	#ifdef VBOX_WITH_NESTED_HWVIRT
587	/*
588	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
589	*/
590	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
591	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
592	if (RT_FAILURE(rc))
593	return rc;
594
595	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
596	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
597
598	/* Set all bits to intercept all MSR accesses. */
599	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
600	#endif
601
602	return VINF_SUCCESS;
603	}
604
605
606	/**
607	* Does global AMD-V termination (called during module termination).
608	*/
609	VMMR0DECL(void) SVMR0GlobalTerm(void)
610	{
611	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
612	{
613	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
614	g_pvIOBitmap = NULL;
615	g_HCPhysIOBitmap = 0;
616	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
617	}
618
619	#ifdef VBOX_WITH_NESTED_HWVIRT
620	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
621	{
622	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
623	g_pvNstGstMsrBitmap = NULL;
624	g_HCPhysNstGstMsrBitmap = 0;
625	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
626	}
627	#endif
628	}
629
630
631	/**
632	* Frees any allocated per-VCPU structures for a VM.
633	*
634	* @param pVM The cross context VM structure.
635	*/
636	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
637	{
638	for (uint32_t i = 0; i < pVM->cCpus; i++)
639	{
640	PVMCPU pVCpu = &pVM->aCpus[i];
641	AssertPtr(pVCpu);
642
643	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
644	{
645	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
646	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
647	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
648	}
649
650	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
651	{
652	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
653	pVCpu->hm.s.svm.pVmcb = NULL;
654	pVCpu->hm.s.svm.HCPhysVmcb = 0;
655	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
656	}
657
658	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
661	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
662	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
663	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666	}
667
668
669	/**
670	* Does per-VM AMD-V initialization.
671	*
672	* @returns VBox status code.
673	* @param pVM The cross context VM structure.
674	*/
675	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
676	{
677	int rc = VERR_INTERNAL_ERROR_5;
678
679	/*
680	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
681	*/
682	uint32_t u32Family;
683	uint32_t u32Model;
684	uint32_t u32Stepping;
685	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
686	{
687	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
688	pVM->hm.s.svm.fAlwaysFlushTLB = true;
689	}
690
691	/*
692	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
693	*/
694	for (VMCPUID i = 0; i < pVM->cCpus; i++)
695	{
696	PVMCPU pVCpu = &pVM->aCpus[i];
697	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
698	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
699	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
700	}
701
702	for (VMCPUID i = 0; i < pVM->cCpus; i++)
703	{
704	PVMCPU pVCpu = &pVM->aCpus[i];
705
706	/*
707	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
708	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
709	*/
710	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
711	if (RT_FAILURE(rc))
712	goto failure_cleanup;
713
714	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
715	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
716	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
717	ASMMemZeroPage(pvVmcbHost);
718
719	/*
720	* Allocate one page for the guest-state VMCB.
721	*/
722	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
723	if (RT_FAILURE(rc))
724	goto failure_cleanup;
725
726	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
727	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
728	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
729	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
730
731	/*
732	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
733	* SVM to not require one.
734	*/
735	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
736	false /* fExecutable */);
737	if (RT_FAILURE(rc))
738	goto failure_cleanup;
739
740	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
741	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
742	/* Set all bits to intercept all MSR accesses (changed later on). */
743	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
744	}
745
746	return VINF_SUCCESS;
747
748	failure_cleanup:
749	hmR0SvmFreeStructs(pVM);
750	return rc;
751	}
752
753
754	/**
755	* Does per-VM AMD-V termination.
756	*
757	* @returns VBox status code.
758	* @param pVM The cross context VM structure.
759	*/
760	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
761	{
762	hmR0SvmFreeStructs(pVM);
763	return VINF_SUCCESS;
764	}
765
766
767	/**
768	* Returns whether the VMCB Clean Bits feature is supported.
769	*
770	* @return @c true if supported, @c false otherwise.
771	* @param pVCpu The cross context virtual CPU structure.
772	* @param pCtx Pointer to the guest-CPU context.
773	*/
774	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu, PCPUMCTX pCtx)
775	{
776	PVM pVM = pVCpu->CTX_SUFF(pVM);
777	#ifdef VBOX_WITH_NESTED_HWVIRT
778	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
779	{
780	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
781	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
782	}
783	#else
784	RT_NOREF(pCtx);
785	#endif
786	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
787	}
788
789
790	/**
791	* Returns whether the decode assists feature is supported.
792	*
793	* @return @c true if supported, @c false otherwise.
794	* @param pVCpu The cross context virtual CPU structure.
795	* @param pCtx Pointer to the guest-CPU context.
796	*/
797	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu, PCPUMCTX pCtx)
798	{
799	PVM pVM = pVCpu->CTX_SUFF(pVM);
800	#ifdef VBOX_WITH_NESTED_HWVIRT
801	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
802	{
803	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
804	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
805	}
806	#else
807	RT_NOREF(pCtx);
808	#endif
809	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
810	}
811
812
813	/**
814	* Returns whether the NRIP_SAVE feature is supported.
815	*
816	* @return @c true if supported, @c false otherwise.
817	* @param pVCpu The cross context virtual CPU structure.
818	* @param pCtx Pointer to the guest-CPU context.
819	*/
820	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu, PCPUMCTX pCtx)
821	{
822	PVM pVM = pVCpu->CTX_SUFF(pVM);
823	#ifdef VBOX_WITH_NESTED_HWVIRT
824	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
825	{
826	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
827	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
828	}
829	#else
830	RT_NOREF(pCtx);
831	#endif
832	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
833	}
834
835
836	/**
837	* Sets the permission bits for the specified MSR in the MSRPM.
838	*
839	* @param pVmcb Pointer to the VM control block.
840	* @param pbMsrBitmap Pointer to the MSR bitmap.
841	* @param uMsr The MSR for which the access permissions are being set.
842	* @param enmRead MSR read permissions.
843	* @param enmWrite MSR write permissions.
844	*/
845	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
846	SVMMSREXITWRITE enmWrite)
847	{
848	uint16_t offMsrpm;
849	uint32_t uMsrpmBit;
850	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
851	AssertRC(rc);
852
853	Assert(uMsrpmBit < 0x3fff);
854	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
855
856	pbMsrBitmap += offMsrpm;
857	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
858	ASMBitSet(pbMsrBitmap, uMsrpmBit);
859	else
860	ASMBitClear(pbMsrBitmap, uMsrpmBit);
861
862	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
863	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
864	else
865	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
866
867	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
868	}
869
870
871	/**
872	* Sets up AMD-V for the specified VM.
873	* This function is only called once per-VM during initalization.
874	*
875	* @returns VBox status code.
876	* @param pVM The cross context VM structure.
877	*/
878	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
879	{
880	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
881	AssertReturn(pVM, VERR_INVALID_PARAMETER);
882	Assert(pVM->hm.s.svm.fSupported);
883
884	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
885	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
886	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
887
888	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
889	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
890
891	#ifdef VBOX_WITH_NESTED_HWVIRT
892	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
893	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
894
895	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
896	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
897	#endif
898
899	for (VMCPUID i = 0; i < pVM->cCpus; i++)
900	{
901	PVMCPU pVCpu = &pVM->aCpus[i];
902	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
903
904	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
905
906	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
907	Assert(!pVCpu->hm.s.idxExitHistoryFree);
908	HMCPU_EXIT_HISTORY_RESET(pVCpu);
909
910	/* Always trap #AC for reasons of security. */
911	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
912
913	/* Always trap #DB for reasons of security. */
914	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
915
916	/* Trap exceptions unconditionally (debug purposes). */
917	#ifdef HMSVM_ALWAYS_TRAP_PF
918	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
919	#endif
920	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
921	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
922	pVmcb->ctrl.u32InterceptXcpt \|= 0
923	\| RT_BIT(X86_XCPT_BP)
924	\| RT_BIT(X86_XCPT_DE)
925	\| RT_BIT(X86_XCPT_NM)
926	\| RT_BIT(X86_XCPT_UD)
927	\| RT_BIT(X86_XCPT_NP)
928	\| RT_BIT(X86_XCPT_SS)
929	\| RT_BIT(X86_XCPT_GP)
930	\| RT_BIT(X86_XCPT_PF)
931	\| RT_BIT(X86_XCPT_MF)
932	;
933	#endif
934
935	/* Set up unconditional intercepts and conditions. */
936	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
937	\| SVM_CTRL_INTERCEPT_VMMCALL;
938
939	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
940	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
941
942	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
943	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
944
945	/* Intercept all DRx reads and writes by default. Changed later on. */
946	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
947	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
948
949	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
950	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
951
952	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
953	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
954	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
955
956	/* Set IO and MSR bitmap permission bitmap physical addresses. */
957	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
958	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
959
960	/* LBR virtualization. */
961	if (fUseLbrVirt)
962	{
963	pVmcb->ctrl.LbrVirt.n.u1LbrVirt = fUseLbrVirt;
964	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
965	}
966	else
967	Assert(pVmcb->ctrl.LbrVirt.n.u1LbrVirt == 0);
968
969	#ifdef VBOX_WITH_NESTED_HWVIRT
970	/* Virtualized VMSAVE/VMLOAD. */
971	pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
972	if (!fUseVirtVmsaveVmload)
973	{
974	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
975	\| SVM_CTRL_INTERCEPT_VMLOAD;
976	}
977
978	/* Virtual GIF. */
979	pVmcb->ctrl.IntCtrl.n.u1VGifEnable = fUseVGif;
980	if (!fUseVGif)
981	{
982	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
983	\| SVM_CTRL_INTERCEPT_STGI;
984	}
985	#endif
986
987	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
988	Assert(pVmcb->ctrl.u32VmcbCleanBits == 0);
989
990	/* The host ASID MBZ, for the guest start with 1. */
991	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
992
993	/*
994	* Setup the PAT MSR (applicable for Nested Paging only).
995	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
996	* so choose type 6 for all PAT slots.
997	*/
998	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
999
1000	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1001	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1002
1003	/* Without Nested Paging, we need additionally intercepts. */
1004	if (!pVM->hm.s.fNestedPaging)
1005	{
1006	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1007	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1008	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1009
1010	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1011	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1012	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1013
1014	/* Page faults must be intercepted to implement shadow paging. */
1015	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1016	}
1017
1018	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1019	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1020	#endif
1021
1022	/* Apply the exceptions intercepts needed by the GIM provider. */
1023	if (pVCpu->hm.s.fGIMTrapXcptUD)
1024	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1025
1026	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1027	if (fUsePauseFilter)
1028	{
1029	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1030	if (fPauseFilterThreshold)
1031	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1032	}
1033
1034	/*
1035	* The following MSRs are saved/restored automatically during the world-switch.
1036	* Don't intercept guest read/write accesses to these MSRs.
1037	*/
1038	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1039	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1040	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1041	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1042	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1043	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1044	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1045	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1046	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1047	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1048	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1049	}
1050
1051	return VINF_SUCCESS;
1052	}
1053
1054
1055	/**
1056	* Gets a pointer to the currently active guest or nested-guest VMCB.
1057	*
1058	* @returns Pointer to the current context VMCB.
1059	* @param pVCpu The cross context virtual CPU structure.
1060	* @param pCtx Pointer to the guest-CPU context.
1061	*/
1062	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
1063	{
1064	#ifdef VBOX_WITH_NESTED_HWVIRT
1065	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1066	return pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1067	#else
1068	RT_NOREF(pCtx);
1069	#endif
1070	return pVCpu->hm.s.svm.pVmcb;
1071	}
1072
1073
1074	/**
1075	* Invalidates a guest page by guest virtual address.
1076	*
1077	* @returns VBox status code.
1078	* @param pVM The cross context VM structure.
1079	* @param pVCpu The cross context virtual CPU structure.
1080	* @param GCVirt Guest virtual address of the page to invalidate.
1081	*/
1082	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1083	{
1084	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1085	Assert(pVM->hm.s.svm.fSupported);
1086
1087	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1088
1089	/* Skip it if a TLB flush is already pending. */
1090	if (!fFlushPending)
1091	{
1092	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
1093
1094	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1095	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
1096	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1097
1098	#if HC_ARCH_BITS == 32
1099	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1100	if (CPUMIsGuestInLongMode(pVCpu))
1101	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1102	else
1103	#endif
1104	{
1105	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1106	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1107	}
1108	}
1109	return VINF_SUCCESS;
1110	}
1111
1112
1113	/**
1114	* Flushes the appropriate tagged-TLB entries.
1115	*
1116	* @param pVCpu The cross context virtual CPU structure.
1117	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
1118	* @param pVmcb Pointer to the VM control block.
1119	*/
1120	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
1121	{
1122	#ifndef VBOX_WITH_NESTED_HWVIRT
1123	RT_NOREF(pCtx);
1124	#endif
1125
1126	PVM pVM = pVCpu->CTX_SUFF(pVM);
1127	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
1128
1129	/*
1130	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1131	* This can happen both for start & resume due to long jumps back to ring-3.
1132	*
1133	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no correlation
1134	* between it and the physical CPU.
1135	*
1136	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1137	* so we cannot reuse the ASIDs without flushing.
1138	*/
1139	bool fNewAsid = false;
1140	Assert(pCpu->idCpu != NIL_RTCPUID);
1141	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1142	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes
1143	#ifdef VBOX_WITH_NESTED_HWVIRT
1144	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1145	#endif
1146	)
1147	{
1148	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1149	pVCpu->hm.s.fForceTLBFlush = true;
1150	fNewAsid = true;
1151	}
1152
1153	/* Set TLB flush state as checked until we return from the world switch. */
1154	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1155
1156	/* Check for explicit TLB flushes. */
1157	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1158	{
1159	pVCpu->hm.s.fForceTLBFlush = true;
1160	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1161	}
1162
1163	/*
1164	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1165	* This Host CPU requirement takes precedence.
1166	*/
1167	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1168	{
1169	pCpu->uCurrentAsid = 1;
1170	pVCpu->hm.s.uCurrentAsid = 1;
1171	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1172	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1173
1174	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1175	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1176
1177	/* Keep track of last CPU ID even when flushing all the time. */
1178	if (fNewAsid)
1179	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1180	}
1181	else
1182	{
1183	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1184	if (pVCpu->hm.s.fForceTLBFlush)
1185	{
1186	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1187	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1188
1189	if (fNewAsid)
1190	{
1191	++pCpu->uCurrentAsid;
1192
1193	bool fHitASIDLimit = false;
1194	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1195	{
1196	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1197	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1198	fHitASIDLimit = true;
1199	}
1200
1201	if ( fHitASIDLimit
1202	\|\| pCpu->fFlushAsidBeforeUse)
1203	{
1204	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1205	pCpu->fFlushAsidBeforeUse = false;
1206	}
1207
1208	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1209	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1210	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1211	}
1212	else
1213	{
1214	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1215	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1216	else
1217	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1218	}
1219
1220	pVCpu->hm.s.fForceTLBFlush = false;
1221	}
1222	}
1223
1224	/* Update VMCB with the ASID. */
1225	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1226	{
1227	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1228	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1229	}
1230
1231	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
1232	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1233	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1234	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1235	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1236	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1237	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1238	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1239
1240	#ifdef VBOX_WITH_STATISTICS
1241	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1242	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1243	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1244	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1245	{
1246	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1247	}
1248	else
1249	{
1250	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1251	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1252	}
1253	#endif
1254	}
1255
1256
1257	/** @name 64-bit guest on 32-bit host OS helper functions.
1258	*
1259	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1260	* mode (code segment, paging). These wrappers/helpers perform the necessary
1261	* bits for the 32->64 switcher.
1262	*
1263	* @{ */
1264	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1265	/**
1266	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1267	*
1268	* @returns VBox status code.
1269	* @param HCPhysVmcbHost Physical address of host VMCB.
1270	* @param HCPhysVmcb Physical address of the VMCB.
1271	* @param pCtx Pointer to the guest-CPU context.
1272	* @param pVM The cross context VM structure.
1273	* @param pVCpu The cross context virtual CPU structure.
1274	*/
1275	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1276	{
1277	uint32_t aParam[8];
1278	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1279	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1280	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1281	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1282	aParam[4] = VM_RC_ADDR(pVM, pVM);
1283	aParam[5] = 0;
1284	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1285	aParam[7] = 0;
1286
1287	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1288	}
1289
1290
1291	/**
1292	* Executes the specified VMRUN handler in 64-bit mode.
1293	*
1294	* @returns VBox status code.
1295	* @param pVM The cross context VM structure.
1296	* @param pVCpu The cross context virtual CPU structure.
1297	* @param pCtx Pointer to the guest-CPU context.
1298	* @param enmOp The operation to perform.
1299	* @param cParams Number of parameters.
1300	* @param paParam Array of 32-bit parameters.
1301	*/
1302	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1303	uint32_t cParams, uint32_t *paParam)
1304	{
1305	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1306	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1307
1308	NOREF(pCtx);
1309
1310	/* Disable interrupts. */
1311	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1312
1313	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1314	RTCPUID idHostCpu = RTMpCpuId();
1315	CPUMR0SetLApic(pVCpu, idHostCpu);
1316	#endif
1317
1318	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1319	CPUMSetHyperEIP(pVCpu, enmOp);
1320	for (int i = (int)cParams - 1; i >= 0; i--)
1321	CPUMPushHyper(pVCpu, paParam[i]);
1322
1323	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1324	/* Call the switcher. */
1325	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1326	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1327
1328	/* Restore interrupts. */
1329	ASMSetFlags(uOldEFlags);
1330	return rc;
1331	}
1332
1333	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1334	/** @} */
1335
1336
1337	/**
1338	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1339	* the corresponding VMCB Clean bit.
1340	*
1341	* @param pVmcb Pointer to the VM control block.
1342	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1343	*/
1344	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1345	{
1346	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1347	{
1348	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1349	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1350	}
1351	}
1352
1353
1354	/**
1355	* Removes an exception from the intercept-exception bitmap in the VMCB and
1356	* updates the corresponding VMCB Clean bit.
1357	*
1358	* @param pVCpu The cross context virtual CPU structure.
1359	* @param pCtx Pointer to the guest-CPU context.
1360	* @param pVmcb Pointer to the VM control block.
1361	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1362	*
1363	* @remarks This takes into account if we're executing a nested-guest and only
1364	* removes the exception intercept if both the guest -and- nested-guest
1365	* are not intercepting it.
1366	*/
1367	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint32_t u32Xcpt)
1368	{
1369	Assert(u32Xcpt != X86_XCPT_DB);
1370	Assert(u32Xcpt != X86_XCPT_AC);
1371	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1372	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1373	{
1374	bool fRemoveXcpt = true;
1375	#ifdef VBOX_WITH_NESTED_HWVIRT
1376	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1377	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1378	{
1379	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
1380	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
1381	fRemoveXcpt = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(u32Xcpt));
1382	}
1383	#else
1384	RT_NOREF2(pVCpu, pCtx);
1385	#endif
1386	if (fRemoveXcpt)
1387	{
1388	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1389	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1390	}
1391	}
1392	#else
1393	RT_NOREF3(pVCpu, pCtx, pVmcb);
1394	#endif
1395	}
1396
1397
1398	/**
1399	* Loads the guest (or nested-guest) CR0 control register into the guest-state
1400	* area in the VMCB.
1401	*
1402	* Although the guest CR0 is a separate field in the VMCB we have to consider
1403	* the FPU state itself which is shared between the host and the guest.
1404	*
1405	* @returns VBox status code.
1406	* @param pVCpu The cross context virtual CPU structure.
1407	* @param pVmcb Pointer to the VM control block.
1408	* @param pCtx Pointer to the guest-CPU context.
1409	*
1410	* @remarks No-long-jump zone!!!
1411	*/
1412	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1413	{
1414	uint64_t u64GuestCR0 = pCtx->cr0;
1415
1416	/* Always enable caching. */
1417	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1418
1419	/*
1420	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1421	*/
1422	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1423	{
1424	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1425	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1426	}
1427
1428	/*
1429	* Guest FPU bits.
1430	*/
1431	bool fInterceptNM = false;
1432	bool fInterceptMF = false;
1433	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1434	if (CPUMIsGuestFPUStateActive(pVCpu))
1435	{
1436	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1437	if (!(pCtx->cr0 & X86_CR0_NE))
1438	{
1439	Log4(("hmR0SvmLoadSharedCR0: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1440	fInterceptMF = true;
1441	}
1442	}
1443	else
1444	{
1445	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1446	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1447	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1448	}
1449
1450	/*
1451	* Update the exception intercept bitmap.
1452	*/
1453	if (fInterceptNM)
1454	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1455	else
1456	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_NM);
1457
1458	if (fInterceptMF)
1459	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1460	else
1461	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_MF);
1462
1463	pVmcb->guest.u64CR0 = u64GuestCR0;
1464	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1465	}
1466
1467
1468	/**
1469	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1470	*
1471	* @returns VBox status code.
1472	* @param pVCpu The cross context virtual CPU structure.
1473	* @param pVmcb Pointer to the VM control block.
1474	* @param pCtx Pointer to the guest-CPU context.
1475	*
1476	* @remarks No-long-jump zone!!!
1477	*/
1478	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1479	{
1480	PVM pVM = pVCpu->CTX_SUFF(pVM);
1481
1482	/*
1483	* Guest CR2.
1484	*/
1485	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1486	{
1487	pVmcb->guest.u64CR2 = pCtx->cr2;
1488	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1489	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1490	}
1491
1492	/*
1493	* Guest CR3.
1494	*/
1495	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1496	{
1497	if (pVM->hm.s.fNestedPaging)
1498	{
1499	PGMMODE enmShwPagingMode;
1500	#if HC_ARCH_BITS == 32
1501	if (CPUMIsGuestInLongModeEx(pCtx))
1502	enmShwPagingMode = PGMMODE_AMD64_NX;
1503	else
1504	#endif
1505	enmShwPagingMode = PGMGetHostMode(pVM);
1506
1507	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1508	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1509	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1510	pVmcb->guest.u64CR3 = pCtx->cr3;
1511	}
1512	else
1513	{
1514	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1515	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1516	}
1517
1518	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1519	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1520	}
1521
1522	/*
1523	* Guest CR4.
1524	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1525	*/
1526	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1527	{
1528	uint64_t u64GuestCR4 = pCtx->cr4;
1529	Assert(RT_HI_U32(u64GuestCR4) == 0);
1530	if (!pVM->hm.s.fNestedPaging)
1531	{
1532	switch (pVCpu->hm.s.enmShadowMode)
1533	{
1534	case PGMMODE_REAL:
1535	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1536	AssertFailed();
1537	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1538
1539	case PGMMODE_32_BIT: /* 32-bit paging. */
1540	u64GuestCR4 &= ~X86_CR4_PAE;
1541	break;
1542
1543	case PGMMODE_PAE: /* PAE paging. */
1544	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1545	/** Must use PAE paging as we could use physical memory > 4 GB */
1546	u64GuestCR4 \|= X86_CR4_PAE;
1547	break;
1548
1549	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1550	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1551	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1552	break;
1553	#else
1554	AssertFailed();
1555	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1556	#endif
1557
1558	default: /* shut up gcc */
1559	AssertFailed();
1560	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1561	}
1562	}
1563
1564	pVmcb->guest.u64CR4 = u64GuestCR4;
1565	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1566
1567	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1568	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1569
1570	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1571	}
1572
1573	return VINF_SUCCESS;
1574	}
1575
1576
1577	/**
1578	* Loads the guest (or nested-guest) segment registers into the VMCB.
1579	*
1580	* @returns VBox status code.
1581	* @param pVCpu The cross context virtual CPU structure.
1582	* @param pVmcb Pointer to the VM control block.
1583	* @param pCtx Pointer to the guest-CPU context.
1584	*
1585	* @remarks No-long-jump zone!!!
1586	*/
1587	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1588	{
1589	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1590	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1591	{
1592	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1593	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1594	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1595	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1596	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1597	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1598
1599	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1600	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1601	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1602	}
1603
1604	/* Guest TR. */
1605	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1606	{
1607	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1608	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1609	}
1610
1611	/* Guest LDTR. */
1612	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1613	{
1614	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1615	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1616	}
1617
1618	/* Guest GDTR. */
1619	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1620	{
1621	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1622	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1623	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1624	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1625	}
1626
1627	/* Guest IDTR. */
1628	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1629	{
1630	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1631	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1632	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1633	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1634	}
1635	}
1636
1637
1638	/**
1639	* Loads the guest (or nested-guest) MSRs into the VMCB.
1640	*
1641	* @param pVCpu The cross context virtual CPU structure.
1642	* @param pVmcb Pointer to the VM control block.
1643	* @param pCtx Pointer to the guest-CPU context.
1644	*
1645	* @remarks No-long-jump zone!!!
1646	*/
1647	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1648	{
1649	/* Guest Sysenter MSRs. */
1650	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1651	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1652	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1653
1654	/*
1655	* Guest EFER MSR.
1656	* AMD-V requires guest EFER.SVME to be set. Weird.
1657	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1658	*/
1659	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1660	{
1661	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1662	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1663	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1664	}
1665
1666	/* 64-bit MSRs. */
1667	if (CPUMIsGuestInLongModeEx(pCtx))
1668	{
1669	/* Load these always as the guest may modify FS/GS base using MSRs in 64-bit mode which we don't intercept. */
1670	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1671	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1672	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1673	}
1674	else
1675	{
1676	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1677	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1678	{
1679	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1680	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1681	}
1682	}
1683
1684	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1685	* be writable in 32-bit mode. Clarify with AMD spec. */
1686	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1687	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1688	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1689	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1690	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1691	}
1692
1693
1694	/**
1695	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1696	* necessary intercepts accordingly.
1697	*
1698	* @param pVCpu The cross context virtual CPU structure.
1699	* @param pVmcb Pointer to the VM control block.
1700	* @param pCtx Pointer to the guest-CPU context.
1701	*
1702	* @remarks No-long-jump zone!!!
1703	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1704	*/
1705	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1706	{
1707	bool fInterceptMovDRx = false;
1708
1709	/*
1710	* Anyone single stepping on the host side? If so, we'll have to use the
1711	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1712	* the VMM level like the VT-x implementations does.
1713	*/
1714	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1715	if (fStepping)
1716	{
1717	pVCpu->hm.s.fClearTrapFlag = true;
1718	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1719	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1720	}
1721
1722	if ( fStepping
1723	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1724	{
1725	/*
1726	* Use the combined guest and host DRx values found in the hypervisor
1727	* register set because the debugger has breakpoints active or someone
1728	* is single stepping on the host side.
1729	*
1730	* Note! DBGF expects a clean DR6 state before executing guest code.
1731	*/
1732	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1733	if ( CPUMIsGuestInLongModeEx(pCtx)
1734	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1735	{
1736	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1737	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1738	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1739	}
1740	else
1741	#endif
1742	if (!CPUMIsHyperDebugStateActive(pVCpu))
1743	{
1744	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1745	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1746	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1747	}
1748
1749	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1750	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1751	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1752	{
1753	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1754	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1755	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1756	pVCpu->hm.s.fUsingHyperDR7 = true;
1757	}
1758
1759	/** @todo If we cared, we could optimize to allow the guest to read registers
1760	* with the same values. */
1761	fInterceptMovDRx = true;
1762	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1763	}
1764	else
1765	{
1766	/*
1767	* Update DR6, DR7 with the guest values if necessary.
1768	*/
1769	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1770	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1771	{
1772	pVmcb->guest.u64DR7 = pCtx->dr[7];
1773	pVmcb->guest.u64DR6 = pCtx->dr[6];
1774	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1775	pVCpu->hm.s.fUsingHyperDR7 = false;
1776	}
1777
1778	/*
1779	* If the guest has enabled debug registers, we need to load them prior to
1780	* executing guest code so they'll trigger at the right time.
1781	*/
1782	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1783	{
1784	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1785	if ( CPUMIsGuestInLongModeEx(pCtx)
1786	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1787	{
1788	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1789	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1790	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1791	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1792	}
1793	else
1794	#endif
1795	if (!CPUMIsGuestDebugStateActive(pVCpu))
1796	{
1797	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1798	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1799	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1800	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1801	}
1802	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1803	}
1804	/*
1805	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1806	* intercept #DB as DR6 is updated in the VMCB.
1807	*
1808	* Note! If we cared and dared, we could skip intercepting \#DB here.
1809	* However, \#DB shouldn't be performance critical, so we'll play safe
1810	* and keep the code similar to the VT-x code and always intercept it.
1811	*/
1812	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1813	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1814	&& !CPUMIsGuestDebugStateActive(pVCpu))
1815	#else
1816	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1817	#endif
1818	{
1819	fInterceptMovDRx = true;
1820	}
1821	}
1822
1823	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1824	if (fInterceptMovDRx)
1825	{
1826	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1827	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1828	{
1829	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1830	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1831	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1832	}
1833	}
1834	else
1835	{
1836	if ( pVmcb->ctrl.u16InterceptRdDRx
1837	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1838	{
1839	pVmcb->ctrl.u16InterceptRdDRx = 0;
1840	pVmcb->ctrl.u16InterceptWrDRx = 0;
1841	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1842	}
1843	}
1844	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1845	}
1846
1847
1848	#ifdef VBOX_WITH_NESTED_HWVIRT
1849	/**
1850	* Loads the nested-guest APIC state (currently just the TPR).
1851	*
1852	* @param pVCpu The cross context virtual CPU structure.
1853	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1854	*/
1855	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1856	{
1857	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1858	{
1859	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1860	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1861	pVCpu->hm.s.svm.fSyncVTpr = false;
1862	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1863
1864	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1865	}
1866	}
1867	#endif
1868
1869	/**
1870	* Loads the guest APIC state (currently just the TPR).
1871	*
1872	* @returns VBox status code.
1873	* @param pVCpu The cross context virtual CPU structure.
1874	* @param pVmcb Pointer to the VM control block.
1875	* @param pCtx Pointer to the guest-CPU context.
1876	*/
1877	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1878	{
1879	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1880	return VINF_SUCCESS;
1881
1882	int rc = VINF_SUCCESS;
1883	PVM pVM = pVCpu->CTX_SUFF(pVM);
1884	if ( PDMHasApic(pVM)
1885	&& APICIsEnabled(pVCpu))
1886	{
1887	bool fPendingIntr;
1888	uint8_t u8Tpr;
1889	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1890	AssertRCReturn(rc, rc);
1891
1892	/* Assume that we need to trap all TPR accesses and thus need not check on
1893	every #VMEXIT if we should update the TPR. */
1894	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1895	pVCpu->hm.s.svm.fSyncVTpr = false;
1896
1897	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1898	if (pVM->hm.s.fTPRPatchingActive)
1899	{
1900	pCtx->msrLSTAR = u8Tpr;
1901	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1902
1903	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1904	if (fPendingIntr)
1905	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1906	else
1907	{
1908	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1909	pVCpu->hm.s.svm.fSyncVTpr = true;
1910	}
1911	}
1912	else
1913	{
1914	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1915	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1916
1917	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1918	if (fPendingIntr)
1919	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1920	else
1921	{
1922	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1923	pVCpu->hm.s.svm.fSyncVTpr = true;
1924	}
1925
1926	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1927	}
1928	}
1929
1930	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1931	return rc;
1932	}
1933
1934
1935	/**
1936	* Loads the exception interrupts required for guest (or nested-guest) execution in
1937	* the VMCB.
1938	*
1939	* @param pVCpu The cross context virtual CPU structure.
1940	* @param pVmcb Pointer to the VM control block.
1941	* @param pCtx Pointer to the guest-CPU context.
1942	*/
1943	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1944	{
1945	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1946	{
1947	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1948	if (pVCpu->hm.s.fGIMTrapXcptUD)
1949	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1950	else
1951	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_UD);
1952
1953	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1954	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1955	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1956	else
1957	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_BP);
1958
1959	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1960	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1961	}
1962	}
1963
1964
1965	#ifdef VBOX_WITH_NESTED_HWVIRT
1966	/**
1967	* Loads the intercepts required for nested-guest execution in the VMCB.
1968	*
1969	* This merges the guest and nested-guest intercepts in a way that if the outer
1970	* guest intercepts an exception we need to intercept it in the nested-guest as
1971	* well and handle it accordingly.
1972	*
1973	* @param pVCpu The cross context virtual CPU structure.
1974	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1975	* @param pCtx Pointer to the guest-CPU context.
1976	*/
1977	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1978	{
1979	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1980	{
1981	/* First, load the guest exception intercepts into the guest VMCB. */
1982	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1983	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1984
1985	/* Next, merge the intercepts into the nested-guest VMCB. */
1986	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1987	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1988
1989	/* Always intercept CR0, CR4 reads and writes as we alter them. */
1990	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(0) \| RT_BIT(4);
1991	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(0) \| RT_BIT(4);
1992
1993	/* Always intercept CR3 reads and writes without nested-paging as we load shadow page tables. */
1994	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1995	{
1996	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1997	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1998	}
1999
2000	/** @todo Figure out debugging with nested-guests, till then just intercept
2001	* all DR[0-15] accesses. */
2002	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
2003	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
2004
2005	/*
2006	* Adjust intercepts while executing the nested-guest that differ from the
2007	* outer guest intercepts.
2008	*
2009	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2010	* that belong to the nested-guest to the outer guest.
2011	*
2012	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2013	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2014	*/
2015	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2016	pVmcbNstGst->ctrl.u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ( ~SVM_CTRL_INTERCEPT_VINTR
2017	\| ~SVM_CTRL_INTERCEPT_VMMCALL))
2018	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2019
2020	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2021	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2022
2023	/*
2024	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2025	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2026	*/
2027	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2028	{
2029	pVmcbNstGst->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2030	\| SVM_CTRL_INTERCEPT_VMLOAD;
2031	}
2032
2033	/*
2034	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2035	* CLGI/STGI instructions executed by the nested-guest.
2036	*/
2037	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2038	{
2039	pVmcbNstGst->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2040	\| SVM_CTRL_INTERCEPT_STGI;
2041	}
2042
2043	/* Finally, update the VMCB clean bits. */
2044	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2045
2046	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
2047	}
2048	}
2049	#endif
2050
2051
2052	/**
2053	* Sets up the appropriate function to run guest code.
2054	*
2055	* @returns VBox status code.
2056	* @param pVCpu The cross context virtual CPU structure.
2057	*
2058	* @remarks No-long-jump zone!!!
2059	*/
2060	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
2061	{
2062	if (CPUMIsGuestInLongMode(pVCpu))
2063	{
2064	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2065	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2066	#endif
2067	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2068	#if HC_ARCH_BITS == 32
2069	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2070	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2071	#else
2072	/* 64-bit host or hybrid host. */
2073	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2074	#endif
2075	}
2076	else
2077	{
2078	/* Guest is not in long mode, use the 32-bit handler. */
2079	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2080	}
2081	return VINF_SUCCESS;
2082	}
2083
2084
2085	/**
2086	* Enters the AMD-V session.
2087	*
2088	* @returns VBox status code.
2089	* @param pVM The cross context VM structure.
2090	* @param pVCpu The cross context virtual CPU structure.
2091	* @param pCpu Pointer to the CPU info struct.
2092	*/
2093	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2094	{
2095	AssertPtr(pVM);
2096	AssertPtr(pVCpu);
2097	Assert(pVM->hm.s.svm.fSupported);
2098	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2099	NOREF(pVM); NOREF(pCpu);
2100
2101	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2102	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2103
2104	pVCpu->hm.s.fLeaveDone = false;
2105	return VINF_SUCCESS;
2106	}
2107
2108
2109	/**
2110	* Thread-context callback for AMD-V.
2111	*
2112	* @param enmEvent The thread-context event.
2113	* @param pVCpu The cross context virtual CPU structure.
2114	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2115	* @thread EMT(pVCpu)
2116	*/
2117	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2118	{
2119	NOREF(fGlobalInit);
2120
2121	switch (enmEvent)
2122	{
2123	case RTTHREADCTXEVENT_OUT:
2124	{
2125	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2126	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2127	VMCPU_ASSERT_EMT(pVCpu);
2128
2129	/* No longjmps (log-flush, locks) in this fragile context. */
2130	VMMRZCallRing3Disable(pVCpu);
2131
2132	if (!pVCpu->hm.s.fLeaveDone)
2133	{
2134	hmR0SvmLeave(pVCpu);
2135	pVCpu->hm.s.fLeaveDone = true;
2136	}
2137
2138	/* Leave HM context, takes care of local init (term). */
2139	int rc = HMR0LeaveCpu(pVCpu);
2140	AssertRC(rc); NOREF(rc);
2141
2142	/* Restore longjmp state. */
2143	VMMRZCallRing3Enable(pVCpu);
2144	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2145	break;
2146	}
2147
2148	case RTTHREADCTXEVENT_IN:
2149	{
2150	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2151	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2152	VMCPU_ASSERT_EMT(pVCpu);
2153
2154	/* No longjmps (log-flush, locks) in this fragile context. */
2155	VMMRZCallRing3Disable(pVCpu);
2156
2157	/*
2158	* Initialize the bare minimum state required for HM. This takes care of
2159	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2160	*/
2161	int rc = HMR0EnterCpu(pVCpu);
2162	AssertRC(rc); NOREF(rc);
2163	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2164
2165	pVCpu->hm.s.fLeaveDone = false;
2166
2167	/* Restore longjmp state. */
2168	VMMRZCallRing3Enable(pVCpu);
2169	break;
2170	}
2171
2172	default:
2173	break;
2174	}
2175	}
2176
2177
2178	/**
2179	* Saves the host state.
2180	*
2181	* @returns VBox status code.
2182	* @param pVM The cross context VM structure.
2183	* @param pVCpu The cross context virtual CPU structure.
2184	*
2185	* @remarks No-long-jump zone!!!
2186	*/
2187	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
2188	{
2189	NOREF(pVM);
2190	NOREF(pVCpu);
2191	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2192	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
2193	return VINF_SUCCESS;
2194	}
2195
2196
2197	/**
2198	* Loads the guest state into the VMCB.
2199	*
2200	* The CPU state will be loaded from these fields on every successful VM-entry.
2201	* Also sets up the appropriate VMRUN function to execute guest code based on
2202	* the guest CPU mode.
2203	*
2204	* @returns VBox status code.
2205	* @param pVM The cross context VM structure.
2206	* @param pVCpu The cross context virtual CPU structure.
2207	* @param pCtx Pointer to the guest-CPU context.
2208	*
2209	* @remarks No-long-jump zone!!!
2210	*/
2211	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2212	{
2213	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2214
2215	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2216	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2217
2218	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2219
2220	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
2221	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2222
2223	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
2224	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
2225
2226	pVmcb->guest.u64RIP = pCtx->rip;
2227	pVmcb->guest.u64RSP = pCtx->rsp;
2228	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2229	pVmcb->guest.u64RAX = pCtx->rax;
2230
2231	#ifdef VBOX_WITH_NESTED_HWVIRT
2232	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1)
2233	{
2234	Assert(pVM->hm.s.svm.fVGif);
2235	pVmcb->ctrl.IntCtrl.n.u1VGif = pCtx->hwvirt.fGif;
2236	}
2237	#endif
2238
2239	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
2240	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2241
2242	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
2243
2244	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2245	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2246
2247	/* Clear any unused and reserved bits. */
2248	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2249	\| HM_CHANGED_GUEST_RSP
2250	\| HM_CHANGED_GUEST_RFLAGS
2251	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2252	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2253	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2254	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2255	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2256	\| HM_CHANGED_SVM_RESERVED2
2257	\| HM_CHANGED_SVM_RESERVED3
2258	\| HM_CHANGED_SVM_RESERVED4);
2259
2260	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2261	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2262	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2263	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2264
2265	#ifdef VBOX_STRICT
2266	hmR0SvmLogState(pVCpu, pVmcb, pCtx, "hmR0SvmLoadGuestState", 0 /* fFlags /, 0 / uVerbose */);
2267	#endif
2268	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2269	return rc;
2270	}
2271
2272
2273	#ifdef VBOX_WITH_NESTED_HWVIRT
2274	/**
2275	* Caches the nested-guest VMCB fields before we modify them for execution using
2276	* hardware-assisted SVM.
2277	*
2278	* @returns true if the VMCB was previously already cached, false otherwise.
2279	* @param pCtx Pointer to the guest-CPU context.
2280	*
2281	* @sa HMSvmNstGstVmExitNotify.
2282	*/
2283	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2284	{
2285	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2286	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2287	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2288	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2289
2290	/*
2291	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2292	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2293	*
2294	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2295	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2296	*/
2297	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2298	if (!fWasCached)
2299	{
2300	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2301	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2302	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2303	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2304	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2305	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2306	pNstGstVmcbCache->u64CR0 = pVmcbNstGstState->u64CR0;
2307	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2308	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2309	pNstGstVmcbCache->u64EFER = pVmcbNstGstState->u64EFER;
2310	pNstGstVmcbCache->u64DBGCTL = pVmcbNstGstState->u64DBGCTL;
2311	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2312	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2313	pNstGstVmcbCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2314	pNstGstVmcbCache->u32VmcbCleanBits = pVmcbNstGstCtrl->u32VmcbCleanBits;
2315	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2316	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2317	pNstGstVmcbCache->u1NestedPaging = pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging;
2318	pNstGstVmcbCache->u1LbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2319	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2320	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2321	}
2322
2323	return fWasCached;
2324	}
2325
2326
2327	/**
2328	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2329	*
2330	* @param pVCpu The cross context virtual CPU structure.
2331	* @param pCtx Pointer to the guest-CPU context.
2332	*/
2333	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2334	{
2335	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2336	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2337
2338	/*
2339	* First cache the nested-guest VMCB fields we may potentially modify.
2340	*/
2341	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2342	if (!fVmcbCached)
2343	{
2344	/*
2345	* The IOPM of the nested-guest can be ignored because the the guest always
2346	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2347	* into the nested-guest one and swap it back on the #VMEXIT.
2348	*/
2349	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2350
2351	/*
2352	* Load the host-physical address into the MSRPM rather than the nested-guest
2353	* physical address (currently we trap all MSRs in the nested-guest).
2354	*/
2355	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2356
2357	/*
2358	* Use the same nested-paging as the "outer" guest. We can't dynamically
2359	* switch off nested-paging suddenly while executing a VM (see assertion at the
2360	* end of Trap0eHandler in PGMAllBth.h).
2361	*/
2362	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2363
2364	/* For now copy the LBR info. from outer guest VMCB. */
2365	/** @todo fix this later. */
2366	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2367	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2368	pVmcbNstGst->guest.u64DBGCTL = pVmcb->guest.u64DBGCTL;
2369	}
2370	else
2371	{
2372	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2373	Assert(pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap);
2374	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2375	}
2376	}
2377
2378
2379	/**
2380	* Loads the nested-guest state into the VMCB.
2381	*
2382	* @returns VBox status code.
2383	* @param pVCpu The cross context virtual CPU structure.
2384	* @param pCtx Pointer to the guest-CPU context.
2385	*
2386	* @remarks No-long-jump zone!!!
2387	*/
2388	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2389	{
2390	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2391
2392	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2393	Assert(pVmcbNstGst);
2394
2395	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2396
2397	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
2398	AssertRCReturn(rc, rc);
2399
2400	/*
2401	* We need to load the entire state (including FS, GS etc.) as we could be continuing
2402	* to execute the nested-guest at any point (not just immediately after VMRUN) and thus
2403	* the VMCB can possibly be out-of-sync with the actual nested-guest state if it was
2404	* executed in IEM.
2405	*/
2406	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2407	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2408	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2409
2410	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2411	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2412	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2413	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2414
2415	#ifdef VBOX_WITH_NESTED_HWVIRT
2416	Assert(pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable == 0); /* Nested VGIF not supported yet. */
2417	#endif
2418
2419	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst, pCtx);
2420
2421	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2422	AssertRCReturn(rc, rc);
2423
2424	/* Clear any unused and reserved bits. */
2425	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2426	\| HM_CHANGED_GUEST_RSP
2427	\| HM_CHANGED_GUEST_RFLAGS
2428	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2429	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2430	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2431	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2432	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2433	\| HM_CHANGED_SVM_RESERVED2
2434	\| HM_CHANGED_SVM_RESERVED3
2435	\| HM_CHANGED_SVM_RESERVED4);
2436
2437	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2438	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2439	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2440	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2441
2442	#ifdef VBOX_STRICT
2443	hmR0SvmLogState(pVCpu, pVmcbNstGst, pCtx, "hmR0SvmLoadGuestStateNested", HMSVM_LOG_ALL, 0 /* uVerbose */);
2444	#endif
2445	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2446	return rc;
2447	}
2448	#endif
2449
2450
2451	/**
2452	* Loads the state shared between the host and guest or nested-guest into the
2453	* VMCB.
2454	*
2455	* @param pVCpu The cross context virtual CPU structure.
2456	* @param pVmcb Pointer to the VM control block.
2457	* @param pCtx Pointer to the guest-CPU context.
2458	*
2459	* @remarks No-long-jump zone!!!
2460	*/
2461	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2462	{
2463	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2464	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2465
2466	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2467	{
2468	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2469	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2470	}
2471
2472	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2473	{
2474	/** @todo Figure out stepping with nested-guest. */
2475	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2476	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2477	else
2478	{
2479	pVmcb->guest.u64DR6 = pCtx->dr[6];
2480	pVmcb->guest.u64DR7 = pCtx->dr[7];
2481	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2482	}
2483
2484	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2485	}
2486
2487	/* Unused on AMD-V. */
2488	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2489
2490	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2491	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2492	}
2493
2494
2495	/**
2496	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2497	* context.
2498	*
2499	* Currently there is no residual state left in the CPU that is not updated in the
2500	* VMCB.
2501	*
2502	* @returns VBox status code.
2503	* @param pVCpu The cross context virtual CPU structure.
2504	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2505	* out-of-sync. Make sure to update the required fields
2506	* before using them.
2507	* @param pVmcb Pointer to the VM control block.
2508	*/
2509	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2510	{
2511	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2512
2513	pMixedCtx->rip = pVmcb->guest.u64RIP;
2514	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2515	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2516	pMixedCtx->rax = pVmcb->guest.u64RAX;
2517
2518	#ifdef VBOX_WITH_NESTED_HWVIRT
2519	/*
2520	* Guest Virtual GIF (Global Interrupt Flag).
2521	*/
2522	if ( pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1
2523	&& !CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2524	{
2525	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fVGif);
2526	pMixedCtx->hwvirt.fGif = pVmcb->ctrl.IntCtrl.n.u1VGif;
2527	}
2528	#endif
2529
2530	/*
2531	* Guest interrupt shadow.
2532	*/
2533	if (pVmcb->ctrl.IntShadow.n.u1IntShadow)
2534	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2535	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2536	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2537
2538	/*
2539	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2540	*/
2541	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2542
2543	/*
2544	* Guest MSRs.
2545	*/
2546	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2547	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2548	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2549	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2550	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2551	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2552	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2553	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2554
2555	/*
2556	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2557	*/
2558	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2559	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2560	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2561	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2562	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2563	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2564
2565	/*
2566	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2567	* register (yet).
2568	*/
2569	/** @todo SELM might need to be fixed as it too should not care about the
2570	* granularity bit. See @bugref{6785}. */
2571	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2572	&& pMixedCtx->cs.Attr.n.u1Present
2573	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2574	{
2575	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2576	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2577	}
2578
2579	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2580	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2581	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2582	HMSVM_ASSERT_SEG_GRANULARITY(es);
2583	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2584	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2585
2586	/*
2587	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2588	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2589	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2590	* See AMD spec. 15.5.1 "Basic operation".
2591	*/
2592	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2593	uint8_t const uCpl = pVmcb->guest.u8CPL;
2594	if (pMixedCtx->ss.Attr.n.u2Dpl != uCpl)
2595	{
2596	Log4(("hmR0SvmSaveGuestState: CPL differs. SS.DPL=%u, CPL=%u, overwriting SS.DPL!\n", pMixedCtx->ss.Attr.n.u2Dpl, uCpl));
2597	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2598	}
2599
2600	/*
2601	* Guest TR.
2602	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2603	* between Intel and AMD. See @bugref{6208#c39}.
2604	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2605	*/
2606	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2607	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2608	{
2609	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2610	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2611	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2612	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2613	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2614	}
2615
2616	/*
2617	* Guest Descriptor-Table registers (GDTR, IDTR, LDTR).
2618	*/
2619	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2620	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2621	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2622
2623	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2624	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2625
2626	/*
2627	* Guest Debug registers.
2628	*/
2629	if (!pVCpu->hm.s.fUsingHyperDR7)
2630	{
2631	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2632	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2633	}
2634	else
2635	{
2636	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2637	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2638	}
2639
2640	/*
2641	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2642	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2643	*/
2644	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2645	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2646	{
2647	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2648	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2649	}
2650
2651	#ifdef VBOX_STRICT
2652	if (CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2653	hmR0SvmLogState(pVCpu, pVmcb, pMixedCtx, "hmR0SvmSaveGuestStateNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR, 0 /* uVerbose */);
2654	#endif
2655	}
2656
2657
2658	/**
2659	* Does the necessary state syncing before returning to ring-3 for any reason
2660	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2661	*
2662	* @param pVCpu The cross context virtual CPU structure.
2663	*
2664	* @remarks No-long-jmp zone!!!
2665	*/
2666	static void hmR0SvmLeave(PVMCPU pVCpu)
2667	{
2668	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2669	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2670	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2671
2672	/*
2673	* !!! IMPORTANT !!!
2674	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2675	*/
2676
2677	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2678	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2679	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); /** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2680
2681	/*
2682	* Restore host debug registers if necessary and resync on next R0 reentry.
2683	*/
2684	#ifdef VBOX_STRICT
2685	if (CPUMIsHyperDebugStateActive(pVCpu))
2686	{
2687	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2688	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2689	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2690	}
2691	#endif
2692	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2693	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);/** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2694
2695	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2696	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2697
2698	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2699	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2700	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2701	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2702	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2703
2704	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2705	}
2706
2707
2708	/**
2709	* Leaves the AMD-V session.
2710	*
2711	* @returns VBox status code.
2712	* @param pVCpu The cross context virtual CPU structure.
2713	*/
2714	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2715	{
2716	HM_DISABLE_PREEMPT();
2717	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2718	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2719
2720	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2721	and done this from the SVMR0ThreadCtxCallback(). */
2722	if (!pVCpu->hm.s.fLeaveDone)
2723	{
2724	hmR0SvmLeave(pVCpu);
2725	pVCpu->hm.s.fLeaveDone = true;
2726	}
2727
2728	/*
2729	* !!! IMPORTANT !!!
2730	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2731	*/
2732
2733	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2734	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2735	VMMR0ThreadCtxHookDisable(pVCpu);
2736
2737	/* Leave HM context. This takes care of local init (term). */
2738	int rc = HMR0LeaveCpu(pVCpu);
2739
2740	HM_RESTORE_PREEMPT();
2741	return rc;
2742	}
2743
2744
2745	/**
2746	* Does the necessary state syncing before doing a longjmp to ring-3.
2747	*
2748	* @returns VBox status code.
2749	* @param pVCpu The cross context virtual CPU structure.
2750	*
2751	* @remarks No-long-jmp zone!!!
2752	*/
2753	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2754	{
2755	return hmR0SvmLeaveSession(pVCpu);
2756	}
2757
2758
2759	/**
2760	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2761	* any remaining host state) before we longjump to ring-3 and possibly get
2762	* preempted.
2763	*
2764	* @param pVCpu The cross context virtual CPU structure.
2765	* @param enmOperation The operation causing the ring-3 longjump.
2766	* @param pvUser The user argument (pointer to the possibly
2767	* out-of-date guest-CPU context).
2768	*/
2769	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2770	{
2771	RT_NOREF_PV(pvUser);
2772
2773	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2774	{
2775	/*
2776	* !!! IMPORTANT !!!
2777	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2778	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2779	*/
2780	VMMRZCallRing3RemoveNotification(pVCpu);
2781	VMMRZCallRing3Disable(pVCpu);
2782	HM_DISABLE_PREEMPT();
2783
2784	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2785	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2786
2787	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2788	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2789
2790	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2791	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2792	VMMR0ThreadCtxHookDisable(pVCpu);
2793
2794	/* Leave HM context. This takes care of local init (term). */
2795	HMR0LeaveCpu(pVCpu);
2796
2797	HM_RESTORE_PREEMPT();
2798	return VINF_SUCCESS;
2799	}
2800
2801	Assert(pVCpu);
2802	Assert(pvUser);
2803	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2804	HMSVM_ASSERT_PREEMPT_SAFE();
2805
2806	VMMRZCallRing3Disable(pVCpu);
2807	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2808
2809	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2810	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2811	AssertRCReturn(rc, rc);
2812
2813	VMMRZCallRing3Enable(pVCpu);
2814	return VINF_SUCCESS;
2815	}
2816
2817
2818	/**
2819	* Take necessary actions before going back to ring-3.
2820	*
2821	* An action requires us to go back to ring-3. This function does the necessary
2822	* steps before we can safely return to ring-3. This is not the same as longjmps
2823	* to ring-3, this is voluntary.
2824	*
2825	* @returns VBox status code.
2826	* @param pVM The cross context VM structure.
2827	* @param pVCpu The cross context virtual CPU structure.
2828	* @param pCtx Pointer to the guest-CPU context.
2829	* @param rcExit The reason for exiting to ring-3. Can be
2830	* VINF_VMM_UNKNOWN_RING3_CALL.
2831	*/
2832	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2833	{
2834	Assert(pVM);
2835	Assert(pVCpu);
2836	Assert(pCtx);
2837	HMSVM_ASSERT_PREEMPT_SAFE();
2838
2839	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2840	VMMRZCallRing3Disable(pVCpu);
2841	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
2842	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
2843
2844	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2845	if (pVCpu->hm.s.Event.fPending)
2846	{
2847	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2848	Assert(!pVCpu->hm.s.Event.fPending);
2849	}
2850
2851	/* Sync. the necessary state for going back to ring-3. */
2852	hmR0SvmLeaveSession(pVCpu);
2853	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2854
2855	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2856	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2857	\| CPUM_CHANGED_LDTR
2858	\| CPUM_CHANGED_GDTR
2859	\| CPUM_CHANGED_IDTR
2860	\| CPUM_CHANGED_TR
2861	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2862	if ( pVM->hm.s.fNestedPaging
2863	&& CPUMIsGuestPagingEnabledEx(pCtx))
2864	{
2865	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2866	}
2867
2868	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2869	if (rcExit != VINF_EM_RAW_INTERRUPT)
2870	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2871
2872	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2873
2874	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2875	VMMRZCallRing3RemoveNotification(pVCpu);
2876	VMMRZCallRing3Enable(pVCpu);
2877
2878	/*
2879	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2880	* and if we're injecting an event we should have a TRPM trap pending.
2881	*/
2882	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2883	pVCpu->hm.s.u32HMError = rcExit,
2884	VERR_SVM_IPE_5);
2885	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2886	pVCpu->hm.s.u32HMError = rcExit,
2887	VERR_SVM_IPE_4);
2888
2889	return rcExit;
2890	}
2891
2892
2893	#ifdef VBOX_WITH_NESTED_HWVIRT
2894	/**
2895	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2896	* intercepts for the nested-guest.
2897	*
2898	* @param pVM The cross context VM structure.
2899	* @param pVCpu The cross context virtual CPU structure.
2900	* @param pCtx Pointer to the nested guest-CPU context.
2901	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2902	*
2903	* @remarks No-long-jump zone!!!
2904	*/
2905	static void hmR0SvmUpdateTscOffsettingNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcbNstGst)
2906	{
2907	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2908
2909	bool fParavirtTsc;
2910	uint64_t uTscOffset;
2911	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
2912
2913	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2914	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2915	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); RT_NOREF(pCtx);
2916
2917	/*
2918	* Only avoid intercepting if we determined the host TSC (++) is stable enough
2919	* to not intercept -and- the nested-hypervisor itself does not want to intercept it.
2920	*/
2921	if ( fCanUseRealTsc
2922	&& !(pVmcbNstGstCache->u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
2923	{
2924	pVmcbNstGstCtrl->u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2925	pVmcbNstGstCtrl->u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2926	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2927	}
2928	else
2929	{
2930	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2931	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2932	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2933	}
2934
2935	/* Apply the nested-guest VMCB's TSC offset over the guest one. */
2936	uTscOffset = HMSvmNstGstApplyTscOffset(pVCpu, uTscOffset);
2937
2938	/* Update the nested-guest VMCB with the combined TSC offset (of guest and nested-guest). */
2939	pVmcbNstGstCtrl->u64TSCOffset = uTscOffset;
2940
2941	/* Finally update the VMCB clean bits since we touched the intercepts as well as the TSC offset. */
2942	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2943
2944	if (fParavirtTsc)
2945	{
2946	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2947	information before every VM-entry, hence disable it for performance sake. */
2948	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2949	}
2950	}
2951	#endif
2952
2953
2954	/**
2955	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2956	* intercepts.
2957	*
2958	* @param pVM The cross context VM structure.
2959	* @param pVCpu The cross context virtual CPU structure.
2960	* @param pVmcb Pointer to the VM control block.
2961	*
2962	* @remarks No-long-jump zone!!!
2963	*/
2964	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2965	{
2966	bool fParavirtTsc;
2967	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2968	if (fCanUseRealTsc)
2969	{
2970	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2971	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2972	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2973	}
2974	else
2975	{
2976	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2977	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2978	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2979	}
2980	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2981
2982	/** @todo later optimize this to be done elsewhere and not before every
2983	* VM-entry. */
2984	if (fParavirtTsc)
2985	{
2986	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2987	information before every VM-entry, hence disable it for performance sake. */
2988	#if 0
2989	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2990	AssertRC(rc);
2991	#endif
2992	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2993	}
2994	}
2995
2996
2997	/**
2998	* Sets an event as a pending event to be injected into the guest.
2999	*
3000	* @param pVCpu The cross context virtual CPU structure.
3001	* @param pEvent Pointer to the SVM event.
3002	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3003	* page-fault.
3004	*
3005	* @remarks Statistics counter assumes this is a guest event being reflected to
3006	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3007	*/
3008	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3009	{
3010	Assert(!pVCpu->hm.s.Event.fPending);
3011	Assert(pEvent->n.u1Valid);
3012
3013	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3014	pVCpu->hm.s.Event.fPending = true;
3015	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3016
3017	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3018	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3019	}
3020
3021
3022	/**
3023	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3024	*
3025	* @param pVCpu The cross context virtual CPU structure.
3026	*/
3027	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3028	{
3029	SVMEVENT Event;
3030	Event.u = 0;
3031	Event.n.u1Valid = 1;
3032	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3033	Event.n.u8Vector = X86_XCPT_UD;
3034	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3035	}
3036
3037
3038	/**
3039	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3040	*
3041	* @param pVCpu The cross context virtual CPU structure.
3042	*/
3043	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3044	{
3045	SVMEVENT Event;
3046	Event.u = 0;
3047	Event.n.u1Valid = 1;
3048	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3049	Event.n.u8Vector = X86_XCPT_DB;
3050	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3051	}
3052
3053
3054	/**
3055	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3056	*
3057	* @param pVCpu The cross context virtual CPU structure.
3058	* @param pCtx Pointer to the guest-CPU context.
3059	* @param u32ErrCode The error-code for the page-fault.
3060	* @param uFaultAddress The page fault address (CR2).
3061	*
3062	* @remarks This updates the guest CR2 with @a uFaultAddress!
3063	*/
3064	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3065	{
3066	SVMEVENT Event;
3067	Event.u = 0;
3068	Event.n.u1Valid = 1;
3069	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3070	Event.n.u8Vector = X86_XCPT_PF;
3071	Event.n.u1ErrorCodeValid = 1;
3072	Event.n.u32ErrorCode = u32ErrCode;
3073
3074	/* Update CR2 of the guest. */
3075	if (pCtx->cr2 != uFaultAddress)
3076	{
3077	pCtx->cr2 = uFaultAddress;
3078	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3079	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3080	}
3081
3082	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3083	}
3084
3085
3086	/**
3087	* Sets a device-not-available (\#NM) exception as pending-for-injection into
3088	* the VM.
3089	*
3090	* @param pVCpu The cross context virtual CPU structure.
3091	*/
3092	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3093	{
3094	SVMEVENT Event;
3095	Event.u = 0;
3096	Event.n.u1Valid = 1;
3097	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3098	Event.n.u8Vector = X86_XCPT_NM;
3099	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3100	}
3101
3102
3103	/**
3104	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3105	*
3106	* @param pVCpu The cross context virtual CPU structure.
3107	*/
3108	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3109	{
3110	SVMEVENT Event;
3111	Event.u = 0;
3112	Event.n.u1Valid = 1;
3113	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3114	Event.n.u8Vector = X86_XCPT_MF;
3115	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3116	}
3117
3118
3119	/**
3120	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3121	*
3122	* @param pVCpu The cross context virtual CPU structure.
3123	*/
3124	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3125	{
3126	SVMEVENT Event;
3127	Event.u = 0;
3128	Event.n.u1Valid = 1;
3129	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3130	Event.n.u8Vector = X86_XCPT_DF;
3131	Event.n.u1ErrorCodeValid = 1;
3132	Event.n.u32ErrorCode = 0;
3133	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3134	}
3135
3136
3137	/**
3138	* Injects an event into the guest upon VMRUN by updating the relevant field
3139	* in the VMCB.
3140	*
3141	* @param pVCpu The cross context virtual CPU structure.
3142	* @param pVmcb Pointer to the guest VM control block.
3143	* @param pCtx Pointer to the guest-CPU context.
3144	* @param pEvent Pointer to the event.
3145	*
3146	* @remarks No-long-jump zone!!!
3147	* @remarks Requires CR0!
3148	*/
3149	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
3150	{
3151	NOREF(pVCpu); NOREF(pCtx);
3152
3153	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3154	pVmcb->ctrl.EventInject.u = pEvent->u;
3155	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3156
3157	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3158	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3159	}
3160
3161
3162
3163	/**
3164	* Converts any TRPM trap into a pending HM event. This is typically used when
3165	* entering from ring-3 (not longjmp returns).
3166	*
3167	* @param pVCpu The cross context virtual CPU structure.
3168	*/
3169	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3170	{
3171	Assert(TRPMHasTrap(pVCpu));
3172	Assert(!pVCpu->hm.s.Event.fPending);
3173
3174	uint8_t uVector;
3175	TRPMEVENT enmTrpmEvent;
3176	RTGCUINT uErrCode;
3177	RTGCUINTPTR GCPtrFaultAddress;
3178	uint8_t cbInstr;
3179
3180	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3181	AssertRC(rc);
3182
3183	SVMEVENT Event;
3184	Event.u = 0;
3185	Event.n.u1Valid = 1;
3186	Event.n.u8Vector = uVector;
3187
3188	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3189	if (enmTrpmEvent == TRPM_TRAP)
3190	{
3191	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3192	switch (uVector)
3193	{
3194	case X86_XCPT_NMI:
3195	{
3196	Event.n.u3Type = SVM_EVENT_NMI;
3197	break;
3198	}
3199
3200	case X86_XCPT_PF:
3201	case X86_XCPT_DF:
3202	case X86_XCPT_TS:
3203	case X86_XCPT_NP:
3204	case X86_XCPT_SS:
3205	case X86_XCPT_GP:
3206	case X86_XCPT_AC:
3207	{
3208	Event.n.u1ErrorCodeValid = 1;
3209	Event.n.u32ErrorCode = uErrCode;
3210	break;
3211	}
3212	}
3213	}
3214	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3215	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3216	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3217	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3218	else
3219	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3220
3221	rc = TRPMResetTrap(pVCpu);
3222	AssertRC(rc);
3223
3224	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3225	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3226
3227	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3228	}
3229
3230
3231	/**
3232	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3233	* AMD-V to execute any instruction.
3234	*
3235	* @param pVCpu The cross context virtual CPU structure.
3236	*/
3237	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3238	{
3239	Assert(pVCpu->hm.s.Event.fPending);
3240	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3241
3242	SVMEVENT Event;
3243	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3244
3245	uint8_t uVector = Event.n.u8Vector;
3246	uint8_t uVectorType = Event.n.u3Type;
3247	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3248
3249	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3250
3251	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3252	AssertRC(rc);
3253
3254	if (Event.n.u1ErrorCodeValid)
3255	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3256
3257	if ( uVectorType == SVM_EVENT_EXCEPTION
3258	&& uVector == X86_XCPT_PF)
3259	{
3260	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3261	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3262	}
3263	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3264	{
3265	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3266	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3267	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3268	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3269	}
3270	pVCpu->hm.s.Event.fPending = false;
3271	}
3272
3273
3274	/**
3275	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3276	* now.
3277	*
3278	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3279	* @param pVCpu The cross context virtual CPU structure.
3280	* @param pCtx Pointer to the guest-CPU context.
3281	*
3282	* @remarks No-long-jump zone!!!
3283	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3284	*/
3285	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
3286	{
3287	/*
3288	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
3289	* inhibit interrupts or clear any existing interrupt-inhibition.
3290	*/
3291	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3292	{
3293	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
3294	{
3295	/*
3296	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3297	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
3298	*/
3299	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3300	return false;
3301	}
3302	return true;
3303	}
3304	return false;
3305	}
3306
3307
3308	/**
3309	* Sets the virtual interrupt intercept control in the VMCB.
3310	*
3311	* @param pVmcb Pointer to the VM control block.
3312	*/
3313	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
3314	{
3315	/*
3316	* When AVIC isn't supported, indicate that a virtual interrupt is pending and to
3317	* cause a #VMEXIT when the guest is ready to accept interrupts. At #VMEXIT, we
3318	* then get the interrupt from the APIC (updating ISR at the right time) and
3319	* inject the interrupt.
3320	*
3321	* With AVIC is supported, we could make use of the asynchronously delivery without
3322	* #VMEXIT and we would be passing the AVIC page to SVM.
3323	*/
3324	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3325	{
3326	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 0);
3327	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3328	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
3329	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3330	Log4(("Set VINTR intercept\n"));
3331	}
3332	}
3333
3334
3335	/**
3336	* Clears the virtual interrupt intercept control in the VMCB as
3337	* we are figured the guest is unable process any interrupts
3338	* at this point of time.
3339	*
3340	* @param pVmcb Pointer to the VM control block.
3341	*/
3342	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
3343	{
3344	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3345	{
3346	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 1);
3347	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
3348	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3349	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3350	Log4(("Cleared VINTR intercept\n"));
3351	}
3352	}
3353
3354
3355	/**
3356	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3357	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3358	* virtual NMIs.
3359	*
3360	* @param pVmcb Pointer to the VM control block.
3361	*/
3362	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3363	{
3364	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3365	{
3366	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3367	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3368
3369	Log4(("Setting IRET intercept\n"));
3370	}
3371	}
3372
3373
3374	/**
3375	* Clears the IRET intercept control in the VMCB.
3376	*
3377	* @param pVmcb Pointer to the VM control block.
3378	*/
3379	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3380	{
3381	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3382	{
3383	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3384	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3385
3386	Log4(("Clearing IRET intercept\n"));
3387	}
3388	}
3389
3390	#ifdef VBOX_WITH_NESTED_HWVIRT
3391
3392
3393	/**
3394	* Evaluates the event to be delivered to the nested-guest and sets it as the
3395	* pending event.
3396	*
3397	* @returns VBox strict status code.
3398	* @param pVCpu The cross context virtual CPU structure.
3399	* @param pCtx Pointer to the guest-CPU context.
3400	*/
3401	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3402	{
3403	Log4Func(("\n"));
3404
3405	Assert(!pVCpu->hm.s.Event.fPending);
3406
3407	bool const fGif = pCtx->hwvirt.fGif;
3408	if (fGif)
3409	{
3410	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3411
3412	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3413
3414	/*
3415	* Check if the nested-guest can receive NMIs.
3416	* NMIs are higher priority than regular interrupts.
3417	*/
3418	/** @todo SMI. SMIs take priority over NMIs. */
3419	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3420	{
3421	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3422	if (fBlockNmi)
3423	hmR0SvmSetIretIntercept(pVmcbNstGst);
3424	else if (fIntShadow)
3425	{
3426	/** @todo Figure this out, how we shall manage virt. intercept if the
3427	* nested-guest already has one set and/or if we really need it? */
3428	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3429	}
3430	else
3431	{
3432	Log4(("Pending NMI\n"));
3433
3434	SVMEVENT Event;
3435	Event.u = 0;
3436	Event.n.u1Valid = 1;
3437	Event.n.u8Vector = X86_XCPT_NMI;
3438	Event.n.u3Type = SVM_EVENT_NMI;
3439
3440	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3441	hmR0SvmSetIretIntercept(pVmcbNstGst);
3442	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3443	return VINF_SUCCESS;
3444	}
3445	}
3446
3447	/*
3448	* Check if the nested-guest can receive external interrupts (generated by
3449	* the guest's PIC/APIC).
3450	*
3451	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3452	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3453	*
3454	* External interrupts that are generated for the outer guest may be intercepted
3455	* depending on how the nested-guest VMCB was programmed by guest software.
3456	*
3457	* Physical interrupts always take priority over virtual interrupts,
3458	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3459	*/
3460	if (!fIntShadow)
3461	{
3462	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3463	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3464	&& !pVCpu->hm.s.fSingleInstruction
3465	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3466	{
3467	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR)
3468	{
3469	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3470	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3471	}
3472
3473	uint8_t u8Interrupt;
3474	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3475	if (RT_SUCCESS(rc))
3476	{
3477	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3478
3479	SVMEVENT Event;
3480	Event.u = 0;
3481	Event.n.u1Valid = 1;
3482	Event.n.u8Vector = u8Interrupt;
3483	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3484
3485	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3486	}
3487	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3488	{
3489	/*
3490	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3491	* updated eventually when the TPR is written by the guest.
3492	*/
3493	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3494	}
3495	else
3496	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3497	}
3498
3499	/*
3500	* Check if the nested-guest is intercepting virtual (using V_IRQ and related fields)
3501	* interrupt injection. The virtual interrupt injection itself, if any, will be done
3502	* by the physical CPU.
3503	*/
3504	/** @todo later explore this for performance reasons. Right now the hardware
3505	* takes care of virtual interrupt injection for nested-guest. */
3506	#if 0
3507	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3508	&& (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3509	&& CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx))
3510	{
3511	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3512	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3513	}
3514	#endif
3515	}
3516	}
3517
3518	return VINF_SUCCESS;
3519	}
3520	#endif
3521
3522
3523	/**
3524	* Evaluates the event to be delivered to the guest and sets it as the pending
3525	* event.
3526	*
3527	* @param pVCpu The cross context virtual CPU structure.
3528	* @param pCtx Pointer to the guest-CPU context.
3529	*
3530	* @remarks Don't use this function when we are actively executing a
3531	* nested-guest, use hmR0SvmEvaluatePendingEventNested instead.
3532	*/
3533	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3534	{
3535	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3536	Assert(!pVCpu->hm.s.Event.fPending);
3537
3538	#ifdef VBOX_WITH_NESTED_HWVIRT
3539	bool const fGif = pCtx->hwvirt.fGif;
3540	#else
3541	bool const fGif = true;
3542	#endif
3543	Log4Func(("fGif=%RTbool\n", fGif));
3544
3545	/*
3546	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3547	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3548	*/
3549	if (fGif)
3550	{
3551	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3552	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3553	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3554	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3555
3556	Log4Func(("fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fBlockInt, fIntShadow,
3557	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3558
3559	/** @todo SMI. SMIs take priority over NMIs. */
3560	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3561	{
3562	if (fBlockNmi)
3563	hmR0SvmSetIretIntercept(pVmcb);
3564	else if (fIntShadow)
3565	hmR0SvmSetVirtIntrIntercept(pVmcb);
3566	else
3567	{
3568	Log4(("Pending NMI\n"));
3569
3570	SVMEVENT Event;
3571	Event.u = 0;
3572	Event.n.u1Valid = 1;
3573	Event.n.u8Vector = X86_XCPT_NMI;
3574	Event.n.u3Type = SVM_EVENT_NMI;
3575
3576	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3577	hmR0SvmSetIretIntercept(pVmcb);
3578	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3579	return;
3580	}
3581	}
3582	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3583	&& !pVCpu->hm.s.fSingleInstruction)
3584	{
3585	/*
3586	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3587	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3588	*/
3589	if ( !fBlockInt
3590	&& !fIntShadow)
3591	{
3592	uint8_t u8Interrupt;
3593	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3594	if (RT_SUCCESS(rc))
3595	{
3596	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3597
3598	SVMEVENT Event;
3599	Event.u = 0;
3600	Event.n.u1Valid = 1;
3601	Event.n.u8Vector = u8Interrupt;
3602	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3603
3604	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3605	}
3606	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3607	{
3608	/*
3609	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3610	* updated eventually when the TPR is written by the guest.
3611	*/
3612	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3613	}
3614	else
3615	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3616	}
3617	else
3618	hmR0SvmSetVirtIntrIntercept(pVmcb);
3619	}
3620	}
3621	}
3622
3623
3624	/**
3625	* Injects any pending events into the guest or nested-guest.
3626	*
3627	* @param pVCpu The cross context virtual CPU structure.
3628	* @param pCtx Pointer to the guest-CPU context.
3629	* @param pVmcb Pointer to the VM control block.
3630	*/
3631	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3632	{
3633	Assert(!TRPMHasTrap(pVCpu));
3634	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3635
3636	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3637	#ifdef VBOX_STRICT
3638	bool const fGif = pCtx->hwvirt.fGif;
3639	bool fAllowInt = fGif;
3640	if (fGif)
3641	{
3642	/*
3643	* For nested-guests we have no way to determine if we're injecting a physical or virtual
3644	* interrupt at this point. Hence the partial verification below.
3645	*/
3646	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3647	fAllowInt = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx) \|\| CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx);
3648	else
3649	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3650	}
3651	#endif
3652
3653	if (pVCpu->hm.s.Event.fPending)
3654	{
3655	SVMEVENT Event;
3656	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3657	Assert(Event.n.u1Valid);
3658
3659	/*
3660	* Validate event injection pre-conditions.
3661	*/
3662	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3663	{
3664	Assert(fAllowInt);
3665	Assert(!fIntShadow);
3666	}
3667	else if (Event.n.u3Type == SVM_EVENT_NMI)
3668	{
3669	Assert(fGif);
3670	Assert(!fIntShadow);
3671	}
3672
3673	/*
3674	* Inject it (update VMCB for injection by the hardware).
3675	*/
3676	Log4(("Injecting pending HM event\n"));
3677	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3678	pVCpu->hm.s.Event.fPending = false;
3679
3680	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3681	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3682	else
3683	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3684	}
3685	else
3686	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3687
3688	/*
3689	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3690	*
3691	* For nested-guests: We need to update it too for the scenario where IEM executes
3692	* the nested-guest but execution later continues here with an interrupt shadow active.
3693	*/
3694	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3695	}
3696
3697
3698	/**
3699	* Reports world-switch error and dumps some useful debug info.
3700	*
3701	* @param pVM The cross context VM structure.
3702	* @param pVCpu The cross context virtual CPU structure.
3703	* @param rcVMRun The return code from VMRUN (or
3704	* VERR_SVM_INVALID_GUEST_STATE for invalid
3705	* guest-state).
3706	* @param pCtx Pointer to the guest-CPU context.
3707	*/
3708	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3709	{
3710	NOREF(pCtx);
3711	HMSVM_ASSERT_PREEMPT_SAFE();
3712	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3713	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3714
3715	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3716	{
3717	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3718	#ifdef VBOX_STRICT
3719	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3720	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3721	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3722	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3723	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3724	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3725	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3726	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3727	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3728	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3729
3730	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3731	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3732	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3733
3734	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3735	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3736	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3737	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved0));
3738	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3739	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3740	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3741	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3742	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3743	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved1));
3744	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3745	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3746
3747	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3748	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3749	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3750	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3751	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3752	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3753	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3754	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3755	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3756	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3757	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3758	Log4(("ctrl.NestedPaging.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPaging.n.u1NestedPaging));
3759	Log4(("ctrl.NestedPaging.u1Sev %#x\n", pVmcb->ctrl.NestedPaging.n.u1Sev));
3760	Log4(("ctrl.NestedPaging.u1SevEs %#x\n", pVmcb->ctrl.NestedPaging.n.u1SevEs));
3761	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3762	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3763	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3764	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3765	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3766	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3767
3768	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3769
3770	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3771	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3772
3773	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3774	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3775	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3776	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3777	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3778	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3779	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3780	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3781	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3782	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3783	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3784	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3785	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3786	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3787	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3788	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3789	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3790	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3791	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3792	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3793
3794	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3795	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3796
3797	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3798	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3799	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3800	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3801
3802	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3803	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3804
3805	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3806	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3807	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3808	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3809
3810	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3811	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3812	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3813	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3814	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3815	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3816	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3817
3818	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3819	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3820	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3821	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3822
3823	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3824	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3825	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3826
3827	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3828	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3829	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3830	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3831	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3832	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3833	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3834	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3835	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3836	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3837	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3838	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3839	#endif /* VBOX_STRICT */
3840	}
3841	else
3842	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3843
3844	NOREF(pVmcb);
3845	}
3846
3847
3848	/**
3849	* Check per-VM and per-VCPU force flag actions that require us to go back to
3850	* ring-3 for one reason or another.
3851	*
3852	* @returns VBox status code (information status code included).
3853	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3854	* ring-3.
3855	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3856	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3857	* interrupts)
3858	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3859	* all EMTs to be in ring-3.
3860	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3861	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3862	* to the EM loop.
3863	*
3864	* @param pVM The cross context VM structure.
3865	* @param pVCpu The cross context virtual CPU structure.
3866	* @param pCtx Pointer to the guest-CPU context.
3867	*/
3868	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3869	{
3870	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3871
3872	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3873	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3874	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3875
3876	/* Update pending interrupts into the APIC's IRR. */
3877	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3878	APICUpdatePendingInterrupts(pVCpu);
3879
3880	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3881	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3882	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3883	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3884	{
3885	/* Pending PGM C3 sync. */
3886	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3887	{
3888	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3889	if (rc != VINF_SUCCESS)
3890	{
3891	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3892	return rc;
3893	}
3894	}
3895
3896	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3897	/* -XXX- what was that about single stepping? */
3898	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3899	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3900	{
3901	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3902	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3903	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3904	return rc;
3905	}
3906
3907	/* Pending VM request packets, such as hardware interrupts. */
3908	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3909	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3910	{
3911	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3912	return VINF_EM_PENDING_REQUEST;
3913	}
3914
3915	/* Pending PGM pool flushes. */
3916	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3917	{
3918	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3919	return VINF_PGM_POOL_FLUSH_PENDING;
3920	}
3921
3922	/* Pending DMA requests. */
3923	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3924	{
3925	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3926	return VINF_EM_RAW_TO_R3;
3927	}
3928	}
3929
3930	return VINF_SUCCESS;
3931	}
3932
3933
3934	#ifdef VBOX_WITH_NESTED_HWVIRT
3935	/**
3936	* Does the preparations before executing nested-guest code in AMD-V.
3937	*
3938	* @returns VBox status code (informational status codes included).
3939	* @retval VINF_SUCCESS if we can proceed with running the guest.
3940	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3941	*
3942	* @param pVM The cross context VM structure.
3943	* @param pVCpu The cross context virtual CPU structure.
3944	* @param pCtx Pointer to the guest-CPU context.
3945	* @param pSvmTransient Pointer to the SVM transient structure.
3946	*
3947	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3948	* @sa hmR0SvmPreRunGuest.
3949	*/
3950	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3951	{
3952	HMSVM_ASSERT_PREEMPT_SAFE();
3953
3954	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3955	{
3956	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3957	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3958	return VINF_EM_RESCHEDULE_REM;
3959	#endif
3960	}
3961	else
3962	return VINF_SVM_VMEXIT;
3963
3964	/* Check force flag actions that might require us to go back to ring-3. */
3965	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3966	if (rc != VINF_SUCCESS)
3967	return rc;
3968
3969	if (TRPMHasTrap(pVCpu))
3970	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3971	else if (!pVCpu->hm.s.Event.fPending)
3972	{
3973	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3974	if (rcStrict != VINF_SUCCESS)
3975	return VBOXSTRICTRC_VAL(rcStrict);
3976	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3977	return VINF_SVM_VMEXIT;
3978	}
3979
3980	/*
3981	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3982	* Just do it in software, see @bugref{8411}.
3983	* NB: If we could continue a task switch exit we wouldn't need to do this.
3984	*/
3985	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3986	&& pVCpu->hm.s.Event.fPending
3987	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
3988	{
3989	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3990	}
3991
3992	#ifdef HMSVM_SYNC_FULL_NESTED_GUEST_STATE
3993	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3994	#endif
3995
3996	/*
3997	* Load the nested-guest state.
3998	*/
3999	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
4000	AssertRCReturn(rc, rc);
4001	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */
4002
4003	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */
4004	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
4005
4006	/*
4007	* No longjmps to ring-3 from this point on!!!
4008	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4009	* This also disables flushing of the R0-logger instance (if any).
4010	*/
4011	VMMRZCallRing3Disable(pVCpu);
4012
4013	/*
4014	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4015	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4016	*
4017	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4018	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4019	*
4020	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4021	* executing guest code.
4022	*/
4023	pSvmTransient->fEFlags = ASMIntDisableFlags();
4024	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4025	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4026	{
4027	ASMSetFlags(pSvmTransient->fEFlags);
4028	VMMRZCallRing3Enable(pVCpu);
4029	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4030	return VINF_EM_RAW_TO_R3;
4031	}
4032	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4033	{
4034	ASMSetFlags(pSvmTransient->fEFlags);
4035	VMMRZCallRing3Enable(pVCpu);
4036	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4037	return VINF_EM_RAW_INTERRUPT;
4038	}
4039
4040	/*
4041	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4042	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4043	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4044	*
4045	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4046	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4047	*/
4048	if (pVCpu->hm.s.Event.fPending)
4049	{
4050	SVMEVENT Event;
4051	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4052	if ( Event.n.u1Valid
4053	&& Event.n.u3Type == SVM_EVENT_NMI
4054	&& Event.n.u8Vector == X86_XCPT_NMI
4055	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4056	{
4057	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4058	}
4059	}
4060
4061	return VINF_SUCCESS;
4062	}
4063	#endif
4064
4065
4066	/**
4067	* Does the preparations before executing guest code in AMD-V.
4068	*
4069	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4070	* recompiler. We must be cautious what we do here regarding committing
4071	* guest-state information into the VMCB assuming we assuredly execute the guest
4072	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4073	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4074	* that the recompiler can (and should) use them when it resumes guest
4075	* execution. Otherwise such operations must be done when we can no longer
4076	* exit to ring-3.
4077	*
4078	* @returns VBox status code (informational status codes included).
4079	* @retval VINF_SUCCESS if we can proceed with running the guest.
4080	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4081	*
4082	* @param pVM The cross context VM structure.
4083	* @param pVCpu The cross context virtual CPU structure.
4084	* @param pCtx Pointer to the guest-CPU context.
4085	* @param pSvmTransient Pointer to the SVM transient structure.
4086	*/
4087	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4088	{
4089	HMSVM_ASSERT_PREEMPT_SAFE();
4090	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4091
4092	/* Check force flag actions that might require us to go back to ring-3. */
4093	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
4094	if (rc != VINF_SUCCESS)
4095	return rc;
4096
4097	if (TRPMHasTrap(pVCpu))
4098	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4099	else if (!pVCpu->hm.s.Event.fPending)
4100	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
4101
4102	/*
4103	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4104	* Just do it in software, see @bugref{8411}.
4105	* NB: If we could continue a task switch exit we wouldn't need to do this.
4106	*/
4107	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4108	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4109	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4110
4111	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4112	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4113	#endif
4114
4115	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
4116	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
4117	AssertRCReturn(rc, rc);
4118	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
4119
4120	/*
4121	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
4122	* so we can update it on the way back if the guest changed the TPR.
4123	*/
4124	if (pVCpu->hm.s.svm.fSyncVTpr)
4125	{
4126	if (pVM->hm.s.fTPRPatchingActive)
4127	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
4128	else
4129	{
4130	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4131	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4132	}
4133	}
4134
4135	/*
4136	* No longjmps to ring-3 from this point on!!!
4137	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4138	* This also disables flushing of the R0-logger instance (if any).
4139	*/
4140	VMMRZCallRing3Disable(pVCpu);
4141
4142	/*
4143	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4144	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4145	*
4146	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4147	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4148	*
4149	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4150	* executing guest code.
4151	*/
4152	pSvmTransient->fEFlags = ASMIntDisableFlags();
4153	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4154	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4155	{
4156	ASMSetFlags(pSvmTransient->fEFlags);
4157	VMMRZCallRing3Enable(pVCpu);
4158	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4159	return VINF_EM_RAW_TO_R3;
4160	}
4161	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4162	{
4163	ASMSetFlags(pSvmTransient->fEFlags);
4164	VMMRZCallRing3Enable(pVCpu);
4165	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4166	return VINF_EM_RAW_INTERRUPT;
4167	}
4168
4169	/*
4170	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4171	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4172	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4173	*
4174	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4175	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4176	*/
4177	if (pVCpu->hm.s.Event.fPending)
4178	{
4179	SVMEVENT Event;
4180	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4181	if ( Event.n.u1Valid
4182	&& Event.n.u3Type == SVM_EVENT_NMI
4183	&& Event.n.u8Vector == X86_XCPT_NMI
4184	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4185	{
4186	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4187	}
4188	}
4189
4190	return VINF_SUCCESS;
4191	}
4192
4193
4194	#ifdef VBOX_WITH_NESTED_HWVIRT
4195	/**
4196	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
4197	* means there is no backing out to ring-3 or anywhere else at this point.
4198	*
4199	* @param pVM The cross context VM structure.
4200	* @param pVCpu The cross context virtual CPU structure.
4201	* @param pCtx Pointer to the guest-CPU context.
4202	* @param pSvmTransient Pointer to the SVM transient structure.
4203	*
4204	* @remarks Called with preemption disabled.
4205	* @remarks No-long-jump zone!!!
4206	*/
4207	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4208	{
4209	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4210	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4211	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4212	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4213
4214	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4215	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4216
4217	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4218	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
4219
4220	if ( pVCpu->hm.s.fPreloadGuestFpu
4221	&& !CPUMIsGuestFPUStateActive(pVCpu))
4222	{
4223	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4224	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4225	}
4226
4227	/* Load the state shared between host and nested-guest (FPU, debug). */
4228	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4229	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
4230
4231	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4232	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4233
4234	/* Setup TSC offsetting. */
4235	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4236	if ( pSvmTransient->fUpdateTscOffsetting
4237	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4238	{
4239	hmR0SvmUpdateTscOffsettingNested(pVM, pVCpu, pCtx, pVmcbNstGst);
4240	pSvmTransient->fUpdateTscOffsetting = false;
4241	}
4242
4243	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4244	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4245	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4246
4247	/* Store status of the shared guest-host state at the time of VMRUN. */
4248	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4249	if (CPUMIsGuestInLongModeEx(pCtx))
4250	{
4251	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4252	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4253	}
4254	else
4255	#endif
4256	{
4257	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4258	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4259	}
4260	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4261
4262	/* The TLB flushing would've already been setup by the nested-hypervisor. */
4263	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4264	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
4265	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4266
4267	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4268
4269	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4270	to start executing. */
4271
4272	/*
4273	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4274	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4275	*
4276	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4277	*/
4278	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4279	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4280	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4281	{
4282	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4283	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4284	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4285	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4286	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4287	pSvmTransient->fRestoreTscAuxMsr = true;
4288	}
4289	else
4290	{
4291	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4292	pSvmTransient->fRestoreTscAuxMsr = false;
4293	}
4294
4295	/*
4296	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
4297	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
4298	*/
4299	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4300	if (!fSupportsVmcbCleanBits)
4301	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4302	}
4303	#endif
4304
4305
4306	/**
4307	* Prepares to run guest code in AMD-V and we've committed to doing so. This
4308	* means there is no backing out to ring-3 or anywhere else at this
4309	* point.
4310	*
4311	* @param pVM The cross context VM structure.
4312	* @param pVCpu The cross context virtual CPU structure.
4313	* @param pCtx Pointer to the guest-CPU context.
4314	* @param pSvmTransient Pointer to the SVM transient structure.
4315	*
4316	* @remarks Called with preemption disabled.
4317	* @remarks No-long-jump zone!!!
4318	*/
4319	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4320	{
4321	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4322	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4323	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4324	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4325
4326	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4327	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4328
4329	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4330	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
4331
4332	if ( pVCpu->hm.s.fPreloadGuestFpu
4333	&& !CPUMIsGuestFPUStateActive(pVCpu))
4334	{
4335	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4336	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4337	}
4338
4339	/* Load the state shared between host and guest (FPU, debug). */
4340	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4341	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
4342
4343	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4344	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4345
4346	/* Setup TSC offsetting. */
4347	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4348	if ( pSvmTransient->fUpdateTscOffsetting
4349	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4350	{
4351	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
4352	pSvmTransient->fUpdateTscOffsetting = false;
4353	}
4354
4355	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4356	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4357	pVmcb->ctrl.u32VmcbCleanBits = 0;
4358
4359	/* Store status of the shared guest-host state at the time of VMRUN. */
4360	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4361	if (CPUMIsGuestInLongModeEx(pCtx))
4362	{
4363	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4364	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4365	}
4366	else
4367	#endif
4368	{
4369	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4370	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4371	}
4372	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4373
4374	/* Flush the appropriate tagged-TLB entries. */
4375	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4376	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
4377	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4378
4379	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4380
4381	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4382	to start executing. */
4383
4384	/*
4385	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4386	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4387	*
4388	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4389	*/
4390	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4391	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4392	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4393	{
4394	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4395	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4396	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4397	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4398	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4399	pSvmTransient->fRestoreTscAuxMsr = true;
4400	}
4401	else
4402	{
4403	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4404	pSvmTransient->fRestoreTscAuxMsr = false;
4405	}
4406
4407	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4408	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4409	if (!fSupportsVmcbCleanBits)
4410	pVmcb->ctrl.u32VmcbCleanBits = 0;
4411	}
4412
4413
4414	/**
4415	* Wrapper for running the guest code in AMD-V.
4416	*
4417	* @returns VBox strict status code.
4418	* @param pVM The cross context VM structure.
4419	* @param pVCpu The cross context virtual CPU structure.
4420	* @param pCtx Pointer to the guest-CPU context.
4421	*
4422	* @remarks No-long-jump zone!!!
4423	*/
4424	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4425	{
4426	/*
4427	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4428	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4429	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4430	*/
4431	#ifdef VBOX_WITH_KERNEL_USING_XMM
4432	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4433	pVCpu->hm.s.svm.pfnVMRun);
4434	#else
4435	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4436	#endif
4437	}
4438
4439
4440	#ifdef VBOX_WITH_NESTED_HWVIRT
4441	/**
4442	* Wrapper for running the nested-guest code in AMD-V.
4443	*
4444	* @returns VBox strict status code.
4445	* @param pVM The cross context VM structure.
4446	* @param pVCpu The cross context virtual CPU structure.
4447	* @param pCtx Pointer to the guest-CPU context.
4448	*
4449	* @remarks No-long-jump zone!!!
4450	*/
4451	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4452	{
4453	/*
4454	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4455	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4456	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4457	*/
4458	#ifdef VBOX_WITH_KERNEL_USING_XMM
4459	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4460	pVCpu->hm.s.svm.pfnVMRun);
4461	#else
4462	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4463	#endif
4464	}
4465
4466
4467	/**
4468	* Performs some essential restoration of state after running nested-guest code in
4469	* AMD-V.
4470	*
4471	* @param pVM The cross context VM structure.
4472	* @param pVCpu The cross context virtual CPU structure.
4473	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4474	* out-of-sync. Make sure to update the required fields
4475	* before using them.
4476	* @param pSvmTransient Pointer to the SVM transient structure.
4477	* @param rcVMRun Return code of VMRUN.
4478	*
4479	* @remarks Called with interrupts disabled.
4480	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4481	* unconditionally when it is safe to do so.
4482	*/
4483	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4484	{
4485	RT_NOREF(pVM);
4486	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4487
4488	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4489	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4490
4491	/* TSC read must be done early for maximum accuracy. */
4492	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4493	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4494	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4495	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4496	{
4497	/*
4498	* Undo what we did in hmR0SvmUpdateTscOffsettingNested() but don't restore the
4499	* nested-guest VMCB TSC offset here. It shall eventually be restored on #VMEXIT
4500	* later by HMSvmNstGstVmExitNotify().
4501	*/
4502	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset - pVmcbNstGstCache->u64TSCOffset);
4503	}
4504
4505	if (pSvmTransient->fRestoreTscAuxMsr)
4506	{
4507	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4508	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4509	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4510	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4511	}
4512
4513	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4514	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4515	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4516
4517	Assert(!(ASMGetFlags() & X86_EFL_IF));
4518	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4519	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4520
4521	/* Mark the VMCB-state cache as unmodified by VMM. */
4522	pVmcbNstGstCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4523
4524	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4525	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4526	{
4527	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4528	return;
4529	}
4530
4531	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4532	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4533	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4534	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4535
4536	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4537	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4538	guest-CPU context. */
4539	}
4540	#endif
4541
4542	/**
4543	* Performs some essential restoration of state after running guest code in
4544	* AMD-V.
4545	*
4546	* @param pVM The cross context VM structure.
4547	* @param pVCpu The cross context virtual CPU structure.
4548	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4549	* out-of-sync. Make sure to update the required fields
4550	* before using them.
4551	* @param pSvmTransient Pointer to the SVM transient structure.
4552	* @param rcVMRun Return code of VMRUN.
4553	*
4554	* @remarks Called with interrupts disabled.
4555	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4556	* unconditionally when it is safe to do so.
4557	*/
4558	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4559	{
4560	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4561
4562	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4563	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4564
4565	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4566	pVmcb->ctrl.u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4567
4568	/* TSC read must be done early for maximum accuracy. */
4569	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4570	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4571
4572	if (pSvmTransient->fRestoreTscAuxMsr)
4573	{
4574	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4575	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4576	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4577	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4578	}
4579
4580	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4581	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4582	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4583
4584	Assert(!(ASMGetFlags() & X86_EFL_IF));
4585	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4586	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4587
4588	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4589	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4590	{
4591	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4592	return;
4593	}
4594
4595	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4596	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4597	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4598	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4599
4600	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4601
4602	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4603	{
4604	if (pVCpu->hm.s.svm.fSyncVTpr)
4605	{
4606	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4607	if ( pVM->hm.s.fTPRPatchingActive
4608	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4609	{
4610	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4611	AssertRC(rc);
4612	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4613	}
4614	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4615	{
4616	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4617	AssertRC(rc);
4618	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4619	}
4620	}
4621	}
4622	}
4623
4624
4625	/**
4626	* Runs the guest code using AMD-V.
4627	*
4628	* @returns VBox status code.
4629	* @param pVM The cross context VM structure.
4630	* @param pVCpu The cross context virtual CPU structure.
4631	* @param pCtx Pointer to the guest-CPU context.
4632	* @param pcLoops Pointer to the number of executed loops.
4633	*/
4634	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4635	{
4636	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4637	Assert(pcLoops);
4638	Assert(*pcLoops <= cMaxResumeLoops);
4639
4640	SVMTRANSIENT SvmTransient;
4641	SvmTransient.fUpdateTscOffsetting = true;
4642
4643	int rc = VERR_INTERNAL_ERROR_5;
4644	for (;;)
4645	{
4646	Assert(!HMR0SuspendPending());
4647	HMSVM_ASSERT_CPU_SAFE();
4648
4649	/* Preparatory work for running guest code, this may force us to return
4650	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4651	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4652	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4653	if (rc != VINF_SUCCESS)
4654	break;
4655
4656	/*
4657	* No longjmps to ring-3 from this point on!!!
4658	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4659	* This also disables flushing of the R0-logger instance (if any).
4660	*/
4661	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4662	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4663
4664	/* Restore any residual host-state and save any bits shared between host
4665	and guest into the guest-CPU state. Re-enables interrupts! */
4666	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4667
4668	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4669	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4670	{
4671	if (rc == VINF_SUCCESS)
4672	rc = VERR_SVM_INVALID_GUEST_STATE;
4673	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4674	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4675	break;
4676	}
4677
4678	/* Handle the #VMEXIT. */
4679	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4680	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4681	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4682	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4683	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4684	if (rc != VINF_SUCCESS)
4685	break;
4686	if (++(*pcLoops) >= cMaxResumeLoops)
4687	{
4688	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4689	rc = VINF_EM_RAW_INTERRUPT;
4690	break;
4691	}
4692	}
4693
4694	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4695	return rc;
4696	}
4697
4698
4699	/**
4700	* Runs the guest code using AMD-V in single step mode.
4701	*
4702	* @returns VBox status code.
4703	* @param pVM The cross context VM structure.
4704	* @param pVCpu The cross context virtual CPU structure.
4705	* @param pCtx Pointer to the guest-CPU context.
4706	* @param pcLoops Pointer to the number of executed loops.
4707	*/
4708	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4709	{
4710	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4711	Assert(pcLoops);
4712	Assert(*pcLoops <= cMaxResumeLoops);
4713
4714	SVMTRANSIENT SvmTransient;
4715	SvmTransient.fUpdateTscOffsetting = true;
4716
4717	uint16_t uCsStart = pCtx->cs.Sel;
4718	uint64_t uRipStart = pCtx->rip;
4719
4720	int rc = VERR_INTERNAL_ERROR_5;
4721	for (;;)
4722	{
4723	Assert(!HMR0SuspendPending());
4724	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4725	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4726	(unsigned)RTMpCpuId(), *pcLoops));
4727
4728	/* Preparatory work for running guest code, this may force us to return
4729	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4730	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4731	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4732	if (rc != VINF_SUCCESS)
4733	break;
4734
4735	/*
4736	* No longjmps to ring-3 from this point on!!!
4737	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4738	* This also disables flushing of the R0-logger instance (if any).
4739	*/
4740	VMMRZCallRing3Disable(pVCpu);
4741	VMMRZCallRing3RemoveNotification(pVCpu);
4742	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4743
4744	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4745
4746	/*
4747	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4748	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4749	*/
4750	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4751	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4752	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4753	{
4754	if (rc == VINF_SUCCESS)
4755	rc = VERR_SVM_INVALID_GUEST_STATE;
4756	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4757	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4758	return rc;
4759	}
4760
4761	/* Handle the #VMEXIT. */
4762	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4763	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4764	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4765	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4766	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4767	if (rc != VINF_SUCCESS)
4768	break;
4769	if (++(*pcLoops) >= cMaxResumeLoops)
4770	{
4771	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4772	rc = VINF_EM_RAW_INTERRUPT;
4773	break;
4774	}
4775
4776	/*
4777	* Did the RIP change, if so, consider it a single step.
4778	* Otherwise, make sure one of the TFs gets set.
4779	*/
4780	if ( pCtx->rip != uRipStart
4781	\|\| pCtx->cs.Sel != uCsStart)
4782	{
4783	rc = VINF_EM_DBG_STEPPED;
4784	break;
4785	}
4786	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4787	}
4788
4789	/*
4790	* Clear the X86_EFL_TF if necessary.
4791	*/
4792	if (pVCpu->hm.s.fClearTrapFlag)
4793	{
4794	pVCpu->hm.s.fClearTrapFlag = false;
4795	pCtx->eflags.Bits.u1TF = 0;
4796	}
4797
4798	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4799	return rc;
4800	}
4801
4802	#ifdef VBOX_WITH_NESTED_HWVIRT
4803	/**
4804	* Runs the nested-guest code using AMD-V.
4805	*
4806	* @returns VBox status code.
4807	* @param pVM The cross context VM structure.
4808	* @param pVCpu The cross context virtual CPU structure.
4809	* @param pCtx Pointer to the guest-CPU context.
4810	* @param pcLoops Pointer to the number of executed loops. If we're switching
4811	* from the guest-code execution loop to this nested-guest
4812	* execution loop pass the remainder value, else pass 0.
4813	*/
4814	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4815	{
4816	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4817	Assert(pcLoops);
4818	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4819
4820	SVMTRANSIENT SvmTransient;
4821	SvmTransient.fUpdateTscOffsetting = true;
4822
4823	int rc = VERR_INTERNAL_ERROR_4;
4824	for (;;)
4825	{
4826	Assert(!HMR0SuspendPending());
4827	HMSVM_ASSERT_CPU_SAFE();
4828
4829	/* Preparatory work for running nested-guest code, this may force us to return
4830	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4831	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4832	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4833	if ( rc != VINF_SUCCESS
4834	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4835	{
4836	break;
4837	}
4838
4839	/*
4840	* No longjmps to ring-3 from this point on!!!
4841	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4842	* This also disables flushing of the R0-logger instance (if any).
4843	*/
4844	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4845
4846	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4847
4848	/* Restore any residual host-state and save any bits shared between host
4849	and guest into the guest-CPU state. Re-enables interrupts! */
4850	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4851
4852	if (RT_LIKELY( rc == VINF_SUCCESS
4853	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4854	{ /* extremely likely */ }
4855	else
4856	{
4857	/* VMRUN failed, shouldn't really happen, Guru. */
4858	if (rc != VINF_SUCCESS)
4859	break;
4860
4861	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4862	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4863	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4864	break;
4865	}
4866
4867	/* Handle the #VMEXIT. */
4868	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4869	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4870	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4871	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4872	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4873	if (rc != VINF_SUCCESS)
4874	break;
4875	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4876	{
4877	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4878	rc = VINF_EM_RAW_INTERRUPT;
4879	break;
4880	}
4881
4882	/** @todo handle single-stepping */
4883	}
4884
4885	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4886	return rc;
4887	}
4888	#endif
4889
4890
4891	/**
4892	* Runs the guest code using AMD-V.
4893	*
4894	* @returns Strict VBox status code.
4895	* @param pVM The cross context VM structure.
4896	* @param pVCpu The cross context virtual CPU structure.
4897	* @param pCtx Pointer to the guest-CPU context.
4898	*/
4899	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4900	{
4901	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4902	HMSVM_ASSERT_PREEMPT_SAFE();
4903	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4904
4905	uint32_t cLoops = 0;
4906	int rc;
4907	#ifdef VBOX_WITH_NESTED_HWVIRT
4908	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4909	#endif
4910	{
4911	if (!pVCpu->hm.s.fSingleInstruction)
4912	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4913	else
4914	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4915	}
4916	#ifdef VBOX_WITH_NESTED_HWVIRT
4917	else
4918	{
4919	rc = VINF_SVM_VMRUN;
4920	}
4921
4922	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4923	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4924	if (rc == VINF_SVM_VMRUN)
4925	{
4926	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4927	if (rc == VINF_SVM_VMEXIT)
4928	rc = VINF_SUCCESS;
4929	}
4930	#endif
4931
4932	/* Fixup error codes. */
4933	if (rc == VERR_EM_INTERPRETER)
4934	rc = VINF_EM_RAW_EMULATE_INSTR;
4935	else if (rc == VINF_EM_RESET)
4936	rc = VINF_EM_TRIPLE_FAULT;
4937
4938	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4939	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4940	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4941	return rc;
4942	}
4943
4944
4945	#ifdef VBOX_WITH_NESTED_HWVIRT
4946	/**
4947	* Determines whether an IOIO intercept is active for the nested-guest or not.
4948	*
4949	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4950	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4951	*/
4952	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4953	{
4954	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4955	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4956	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4957	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4958	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4959	const bool fRep = pIoExitInfo->n.u1REP;
4960	const bool fStrIo = pIoExitInfo->n.u1STR;
4961
4962	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4963	NULL /* pIoExitInfo */);
4964	}
4965
4966
4967	/**
4968	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4969	* SVM_EXIT_INVALID).
4970	*
4971	* @returns VBox status code (informational status codes included).
4972	* @param pVCpu The cross context virtual CPU structure.
4973	* @param pCtx Pointer to the guest-CPU context.
4974	* @param pSvmTransient Pointer to the SVM transient structure.
4975	*/
4976	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4977	{
4978	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4979	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4980	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4981
4982	#define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4983	VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
4984
4985	/*
4986	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4987	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
4988	*/
4989	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4990	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4991	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4992	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4993	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4994
4995	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4996	switch (uExitCode)
4997	{
4998	case SVM_EXIT_CPUID:
4999	{
5000	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
5001	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5002	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5003	}
5004
5005	case SVM_EXIT_RDTSC:
5006	{
5007	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
5008	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5009	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5010	}
5011
5012	case SVM_EXIT_RDTSCP:
5013	{
5014	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
5015	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5016	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5017	}
5018
5019
5020	case SVM_EXIT_MONITOR:
5021	{
5022	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
5023	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5024	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5025	}
5026
5027	case SVM_EXIT_MWAIT:
5028	{
5029	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
5030	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5031	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5032	}
5033
5034	case SVM_EXIT_HLT:
5035	{
5036	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
5037	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5038	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5039	}
5040
5041	case SVM_EXIT_MSR:
5042	{
5043	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
5044	{
5045	uint32_t const idMsr = pCtx->ecx;
5046	uint16_t offMsrpm;
5047	uint32_t uMsrpmBit;
5048	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5049	if (RT_SUCCESS(rc))
5050	{
5051	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5052	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
5053	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
5054
5055	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5056	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5057	{
5058	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5059	}
5060	}
5061	else
5062	{
5063	/*
5064	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5065	* See AMD-V spec. "15.11 MSR Intercepts".
5066	*/
5067	Assert(rc == VERR_OUT_OF_RANGE);
5068	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5069	}
5070	}
5071	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5072	}
5073
5074	case SVM_EXIT_IOIO:
5075	{
5076	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
5077	{
5078	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
5079	SVMIOIOEXITINFO IoExitInfo;
5080	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5081	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
5082	if (fIntercept)
5083	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5084	}
5085	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5086	}
5087
5088	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5089	{
5090	PVM pVM = pVCpu->CTX_SUFF(pVM);
5091	if (pVM->hm.s.fNestedPaging)
5092	{
5093	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5094	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5095
5096	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5097	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5098	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5099
5100	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
5101	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5102	return VINF_SUCCESS;
5103	}
5104	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
5105	}
5106
5107	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5108	{
5109	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_NM))
5110	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5111	hmR0SvmSetPendingXcptNM(pVCpu);
5112	return VINF_SUCCESS;
5113	}
5114
5115	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5116	{
5117	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
5118	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5119	hmR0SvmSetPendingXcptUD(pVCpu);
5120	return VINF_SUCCESS;
5121	}
5122
5123	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5124	{
5125	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
5126	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5127	hmR0SvmSetPendingXcptMF(pVCpu);
5128	return VINF_SUCCESS;
5129	}
5130
5131	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5132	{
5133	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5134	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5135	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
5136	}
5137
5138	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5139	{
5140	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5141	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5142	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5143	}
5144
5145	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5146	{
5147	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5148	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5149	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
5150	}
5151
5152	case SVM_EXIT_READ_CR0:
5153	case SVM_EXIT_READ_CR3:
5154	case SVM_EXIT_READ_CR4:
5155	{
5156	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5157	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5158	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5159	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5160	}
5161
5162	case SVM_EXIT_WRITE_CR0:
5163	case SVM_EXIT_WRITE_CR3:
5164	case SVM_EXIT_WRITE_CR4:
5165	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
5166	{
5167	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5168	Log4(("hmR0SvmHandleExitNested: Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5169
5170	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5171	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5172	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5173	}
5174
5175	case SVM_EXIT_PAUSE:
5176	{
5177	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5178	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5179	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5180	}
5181
5182	case SVM_EXIT_VINTR:
5183	{
5184	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5185	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5186	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5187	}
5188
5189	case SVM_EXIT_INTR:
5190	case SVM_EXIT_NMI:
5191	case SVM_EXIT_SMI:
5192	{
5193	/*
5194	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5195	*
5196	* Although we don't intercept SMIs, the nested-guest might. Therefore, we
5197	* might get an SMI #VMEXIT here so simply ignore rather than causing a
5198	* corresponding nested-guest #VMEXIT.
5199	*/
5200	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5201	}
5202
5203	case SVM_EXIT_FERR_FREEZE:
5204	{
5205	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5206	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5207	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5208	}
5209
5210	case SVM_EXIT_INVLPG:
5211	{
5212	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5213	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5214	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5215	}
5216
5217	case SVM_EXIT_WBINVD:
5218	{
5219	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5220	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5221	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5222	}
5223
5224	case SVM_EXIT_INVD:
5225	{
5226	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5227	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5228	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5229	}
5230
5231	case SVM_EXIT_RDPMC:
5232	{
5233	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5234	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5235	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5236	}
5237
5238	default:
5239	{
5240	switch (uExitCode)
5241	{
5242	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5243	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5244	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5245	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5246	{
5247	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5248	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5249	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5250	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5251	}
5252
5253	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5254	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5255	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5256	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5257	{
5258	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5259	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5260	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5261	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5262	}
5263
5264	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
5265	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
5266	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
5267	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
5268	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
5269	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
5270	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
5271	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
5272	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
5273	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
5274	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
5275	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5276	{
5277	uint8_t const uVector = uExitCode - SVM_EXIT_EXCEPTION_0;
5278	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5279	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5280	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5281	}
5282
5283	case SVM_EXIT_XSETBV:
5284	{
5285	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5286	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5287	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5288	}
5289
5290	case SVM_EXIT_TASK_SWITCH:
5291	{
5292	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5293	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5294	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5295	}
5296
5297	case SVM_EXIT_IRET:
5298	{
5299	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5300	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5301	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5302	}
5303
5304	case SVM_EXIT_SHUTDOWN:
5305	{
5306	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5307	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5308	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5309	}
5310
5311	case SVM_EXIT_VMMCALL:
5312	{
5313	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5314	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5315	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5316	}
5317
5318	case SVM_EXIT_CLGI:
5319	{
5320	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5321	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5322	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5323	}
5324
5325	case SVM_EXIT_STGI:
5326	{
5327	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5328	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5329	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5330	}
5331
5332	case SVM_EXIT_VMLOAD:
5333	{
5334	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5335	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5336	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5337	}
5338
5339	case SVM_EXIT_VMSAVE:
5340	{
5341	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5342	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5343	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5344	}
5345
5346	case SVM_EXIT_INVLPGA:
5347	{
5348	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5349	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5350	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5351	}
5352
5353	case SVM_EXIT_VMRUN:
5354	{
5355	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5356	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5357	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5358	}
5359
5360	case SVM_EXIT_RSM:
5361	{
5362	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5363	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5364	hmR0SvmSetPendingXcptUD(pVCpu);
5365	return VINF_SUCCESS;
5366	}
5367
5368	case SVM_EXIT_SKINIT:
5369	{
5370	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5371	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5372	hmR0SvmSetPendingXcptUD(pVCpu);
5373	return VINF_SUCCESS;
5374	}
5375
5376	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5377	case SVM_EXIT_NPF: /* We don't yet support nested-paging for nested-guests, so this should never happen. */
5378	{
5379	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5380	}
5381
5382	default:
5383	{
5384	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5385	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5386	return VERR_SVM_UNKNOWN_EXIT;
5387	}
5388	}
5389	}
5390	}
5391	/* not reached */
5392
5393	#undef HM_SVM_VMEXIT_NESTED
5394	}
5395	#endif
5396
5397
5398	/**
5399	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5400	*
5401	* @returns VBox status code (informational status codes included).
5402	* @param pVCpu The cross context virtual CPU structure.
5403	* @param pCtx Pointer to the guest-CPU context.
5404	* @param pSvmTransient Pointer to the SVM transient structure.
5405	*/
5406	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5407	{
5408	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5409	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5410
5411	/*
5412	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5413	* normal workloads (for some definition of "normal").
5414	*/
5415	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5416	switch (uExitCode)
5417	{
5418	case SVM_EXIT_NPF:
5419	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5420
5421	case SVM_EXIT_IOIO:
5422	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5423
5424	case SVM_EXIT_RDTSC:
5425	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5426
5427	case SVM_EXIT_RDTSCP:
5428	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5429
5430	case SVM_EXIT_CPUID:
5431	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5432
5433	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5434	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5435
5436	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5437	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5438
5439	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5440	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5441
5442	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5443	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5444
5445	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5446	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5447
5448	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5449	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5450
5451	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5452	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5453
5454	case SVM_EXIT_MONITOR:
5455	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5456
5457	case SVM_EXIT_MWAIT:
5458	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5459
5460	case SVM_EXIT_HLT:
5461	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5462
5463	case SVM_EXIT_READ_CR0:
5464	case SVM_EXIT_READ_CR3:
5465	case SVM_EXIT_READ_CR4:
5466	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5467
5468	case SVM_EXIT_WRITE_CR0:
5469	case SVM_EXIT_WRITE_CR3:
5470	case SVM_EXIT_WRITE_CR4:
5471	case SVM_EXIT_WRITE_CR8:
5472	{
5473	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5474	Log4(("hmR0SvmHandleExitNested: Write CR%u\n", uCr)); NOREF(uCr);
5475	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5476	}
5477
5478	case SVM_EXIT_PAUSE:
5479	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5480
5481	case SVM_EXIT_VMMCALL:
5482	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5483
5484	case SVM_EXIT_VINTR:
5485	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5486
5487	case SVM_EXIT_INTR:
5488	case SVM_EXIT_FERR_FREEZE:
5489	case SVM_EXIT_NMI:
5490	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5491
5492	case SVM_EXIT_MSR:
5493	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5494
5495	case SVM_EXIT_INVLPG:
5496	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5497
5498	case SVM_EXIT_WBINVD:
5499	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5500
5501	case SVM_EXIT_INVD:
5502	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5503
5504	case SVM_EXIT_RDPMC:
5505	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5506
5507	default:
5508	{
5509	switch (pSvmTransient->u64ExitCode)
5510	{
5511	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5512	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5513	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5514	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5515	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5516
5517	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5518	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5519	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5520	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5521	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5522
5523	case SVM_EXIT_XSETBV:
5524	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5525
5526	case SVM_EXIT_TASK_SWITCH:
5527	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5528
5529	case SVM_EXIT_IRET:
5530	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5531
5532	case SVM_EXIT_SHUTDOWN:
5533	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5534
5535	case SVM_EXIT_SMI:
5536	case SVM_EXIT_INIT:
5537	{
5538	/*
5539	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5540	* If it ever does, we want to know about it so log the exit code and bail.
5541	*/
5542	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5543	}
5544
5545	#ifdef VBOX_WITH_NESTED_HWVIRT
5546	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5547	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5548	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5549	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5550	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5551	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5552	#else
5553	case SVM_EXIT_CLGI:
5554	case SVM_EXIT_STGI:
5555	case SVM_EXIT_VMLOAD:
5556	case SVM_EXIT_VMSAVE:
5557	case SVM_EXIT_INVLPGA:
5558	case SVM_EXIT_VMRUN:
5559	#endif
5560	case SVM_EXIT_RSM:
5561	case SVM_EXIT_SKINIT:
5562	{
5563	hmR0SvmSetPendingXcptUD(pVCpu);
5564	return VINF_SUCCESS;
5565	}
5566
5567	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5568	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5569	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5570	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5571	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5572	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5573	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5574	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5575	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5576	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5577	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5578	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5579	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5580	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5581	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5582	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5583	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5584	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5585	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5586	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5587	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5588	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5589	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5590	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5591	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5592	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5593	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5594
5595	default:
5596	{
5597	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5598	pVCpu->hm.s.u32HMError = uExitCode;
5599	return VERR_SVM_UNKNOWN_EXIT;
5600	}
5601	}
5602	}
5603	}
5604	/* not reached */
5605	}
5606
5607
5608	#ifdef DEBUG
5609	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5610	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5611	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5612
5613	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5614	do \
5615	{ \
5616	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5617	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5618	} while (0)
5619
5620	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5621	do { \
5622	AssertPtr(pVCpu); \
5623	AssertPtr(pCtx); \
5624	AssertPtr(pSvmTransient); \
5625	Assert(ASMIntAreEnabled()); \
5626	HMSVM_ASSERT_PREEMPT_SAFE(); \
5627	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5628	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5629	HMSVM_ASSERT_PREEMPT_SAFE(); \
5630	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5631	HMSVM_ASSERT_PREEMPT_CPUID(); \
5632	} while (0)
5633	#else /* Release builds */
5634	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5635	#endif
5636
5637
5638	/**
5639	* Worker for hmR0SvmInterpretInvlpg().
5640	*
5641	* @return VBox status code.
5642	* @param pVCpu The cross context virtual CPU structure.
5643	* @param pCpu Pointer to the disassembler state.
5644	* @param pCtx The guest CPU context.
5645	*/
5646	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5647	{
5648	DISQPVPARAMVAL Param1;
5649	RTGCPTR GCPtrPage;
5650
5651	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5652	if (RT_FAILURE(rc))
5653	return VERR_EM_INTERPRETER;
5654
5655	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5656	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5657	{
5658	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5659	return VERR_EM_INTERPRETER;
5660
5661	GCPtrPage = Param1.val.val64;
5662	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5663	rc = VBOXSTRICTRC_VAL(rc2);
5664	}
5665	else
5666	{
5667	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5668	rc = VERR_EM_INTERPRETER;
5669	}
5670
5671	return rc;
5672	}
5673
5674
5675	/**
5676	* Interprets INVLPG.
5677	*
5678	* @returns VBox status code.
5679	* @retval VINF_* Scheduling instructions.
5680	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5681	* @retval VERR_* Fatal errors.
5682	*
5683	* @param pVM The cross context VM structure.
5684	* @param pVCpu The cross context virtual CPU structure.
5685	* @param pCtx The guest CPU context.
5686	*
5687	* @remarks Updates the RIP if the instruction was executed successfully.
5688	*/
5689	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5690	{
5691	/* Only allow 32 & 64 bit code. */
5692	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5693	{
5694	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5695	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5696	if ( RT_SUCCESS(rc)
5697	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5698	{
5699	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5700	if (RT_SUCCESS(rc))
5701	pCtx->rip += pDis->cbInstr;
5702	return rc;
5703	}
5704	else
5705	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5706	}
5707	return VERR_EM_INTERPRETER;
5708	}
5709
5710
5711	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5712	/**
5713	* Gets the IEM exception flags for the specified SVM event.
5714	*
5715	* @returns The IEM exception flags.
5716	* @param pEvent Pointer to the SVM event.
5717	*
5718	* @remarks This function currently only constructs flags required for
5719	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5720	* and CR2 aspects of an exception are not included).
5721	*/
5722	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5723	{
5724	uint8_t const uEventType = pEvent->n.u3Type;
5725	uint32_t fIemXcptFlags;
5726	switch (uEventType)
5727	{
5728	case SVM_EVENT_EXCEPTION:
5729	/*
5730	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5731	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5732	*/
5733	if (pEvent->n.u8Vector == X86_XCPT_BP)
5734	{
5735	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5736	break;
5737	}
5738	if (pEvent->n.u8Vector == X86_XCPT_OF)
5739	{
5740	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5741	break;
5742	}
5743	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5744	RT_FALL_THRU();
5745	case SVM_EVENT_NMI:
5746	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5747	break;
5748
5749	case SVM_EVENT_EXTERNAL_IRQ:
5750	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5751	break;
5752
5753	case SVM_EVENT_SOFTWARE_INT:
5754	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5755	break;
5756
5757	default:
5758	fIemXcptFlags = 0;
5759	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5760	break;
5761	}
5762	return fIemXcptFlags;
5763	}
5764
5765	#else
5766	/**
5767	* Determines if an exception is a contributory exception.
5768	*
5769	* Contributory exceptions are ones which can cause double-faults unless the
5770	* original exception was a benign exception. Page-fault is intentionally not
5771	* included here as it's a conditional contributory exception.
5772	*
5773	* @returns @c true if the exception is contributory, @c false otherwise.
5774	* @param uVector The exception vector.
5775	*/
5776	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5777	{
5778	switch (uVector)
5779	{
5780	case X86_XCPT_GP:
5781	case X86_XCPT_SS:
5782	case X86_XCPT_NP:
5783	case X86_XCPT_TS:
5784	case X86_XCPT_DE:
5785	return true;
5786	default:
5787	break;
5788	}
5789	return false;
5790	}
5791	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5792
5793
5794	/**
5795	* Handle a condition that occurred while delivering an event through the guest
5796	* IDT.
5797	*
5798	* @returns VBox status code (informational error codes included).
5799	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5800	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5801	* continue execution of the guest which will delivery the \#DF.
5802	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5803	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5804	*
5805	* @param pVCpu The cross context virtual CPU structure.
5806	* @param pCtx Pointer to the guest-CPU context.
5807	* @param pSvmTransient Pointer to the SVM transient structure.
5808	*
5809	* @remarks No-long-jump zone!!!
5810	*/
5811	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5812	{
5813	int rc = VINF_SUCCESS;
5814	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5815
5816	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5817	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5818	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5819
5820	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5821	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5822	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5823	{
5824	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5825	IEMXCPTRAISE enmRaise;
5826	IEMXCPTRAISEINFO fRaiseInfo;
5827	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5828	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5829	if (fExitIsHwXcpt)
5830	{
5831	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5832	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5833	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5834	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5835	}
5836	else
5837	{
5838	/*
5839	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5840	* end up here.
5841	*
5842	* If the event was:
5843	* - a software interrupt, we can re-execute the instruction which will regenerate
5844	* the event.
5845	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5846	* - a hardware exception or external interrupt, we re-inject it.
5847	*/
5848	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5849	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5850	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5851	else
5852	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5853	}
5854
5855	switch (enmRaise)
5856	{
5857	case IEMXCPTRAISE_CURRENT_XCPT:
5858	case IEMXCPTRAISE_PREV_EVENT:
5859	{
5860	/* For software interrupts, we shall re-execute the instruction. */
5861	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5862	{
5863	RTGCUINTPTR GCPtrFaultAddress = 0;
5864
5865	/* If we are re-injecting an NMI, clear NMI blocking. */
5866	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5867	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5868
5869	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5870	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5871	pSvmTransient->fVectoringPF = true;
5872	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5873	&& uIdtVector == X86_XCPT_PF)
5874	{
5875	/*
5876	* If the previous exception was a #PF, we need to recover the CR2 value.
5877	* This can't happen with shadow paging.
5878	*/
5879	GCPtrFaultAddress = pCtx->cr2;
5880	}
5881
5882	/*
5883	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5884	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5885	*/
5886	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5887	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5888	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5889
5890	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5891	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5892	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5893	}
5894	break;
5895	}
5896
5897	case IEMXCPTRAISE_REEXEC_INSTR:
5898	{
5899	Assert(rc == VINF_SUCCESS);
5900	break;
5901	}
5902
5903	case IEMXCPTRAISE_DOUBLE_FAULT:
5904	{
5905	/*
5906	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5907	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5908	*/
5909	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5910	{
5911	pSvmTransient->fVectoringDoublePF = true;
5912	Assert(rc == VINF_SUCCESS);
5913	}
5914	else
5915	{
5916	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5917	hmR0SvmSetPendingXcptDF(pVCpu);
5918	rc = VINF_HM_DOUBLE_FAULT;
5919	}
5920	break;
5921	}
5922
5923	case IEMXCPTRAISE_TRIPLE_FAULT:
5924	{
5925	rc = VINF_EM_RESET;
5926	break;
5927	}
5928
5929	case IEMXCPTRAISE_CPU_HANG:
5930	{
5931	rc = VERR_EM_GUEST_CPU_HANG;
5932	break;
5933	}
5934
5935	default:
5936	{
5937	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5938	rc = VERR_SVM_IPE_2;
5939	break;
5940	}
5941	}
5942	#else
5943	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5944
5945	typedef enum
5946	{
5947	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5948	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5949	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5950	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5951	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5952	} SVMREFLECTXCPT;
5953
5954	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5955	bool fReflectingNmi = false;
5956	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5957	{
5958	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5959	{
5960	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5961
5962	#ifdef VBOX_STRICT
5963	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5964	&& uExitVector == X86_XCPT_PF)
5965	{
5966	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5967	}
5968	#endif
5969
5970	if ( uIdtVector == X86_XCPT_BP
5971	\|\| uIdtVector == X86_XCPT_OF)
5972	{
5973	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5974	}
5975	else if ( uExitVector == X86_XCPT_PF
5976	&& uIdtVector == X86_XCPT_PF)
5977	{
5978	pSvmTransient->fVectoringDoublePF = true;
5979	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
5980	}
5981	else if ( uExitVector == X86_XCPT_AC
5982	&& uIdtVector == X86_XCPT_AC)
5983	{
5984	enmReflect = SVMREFLECTXCPT_HANG;
5985	Log4(("IDT: Nested #AC - Bad guest\n"));
5986	}
5987	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
5988	&& hmR0SvmIsContributoryXcpt(uExitVector)
5989	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
5990	\|\| uIdtVector == X86_XCPT_PF))
5991	{
5992	enmReflect = SVMREFLECTXCPT_DF;
5993	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
5994	uIdtVector, uExitVector));
5995	}
5996	else if (uIdtVector == X86_XCPT_DF)
5997	{
5998	enmReflect = SVMREFLECTXCPT_TF;
5999	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
6000	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
6001	}
6002	else
6003	enmReflect = SVMREFLECTXCPT_XCPT;
6004	}
6005	else
6006	{
6007	/*
6008	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
6009	* exception to the guest after handling the #VMEXIT.
6010	*/
6011	enmReflect = SVMREFLECTXCPT_XCPT;
6012	}
6013	}
6014	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
6015	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
6016	{
6017	enmReflect = SVMREFLECTXCPT_XCPT;
6018	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
6019
6020	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
6021	{
6022	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
6023	if (uExitVector == X86_XCPT_PF)
6024	{
6025	pSvmTransient->fVectoringPF = true;
6026	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
6027	}
6028	}
6029	}
6030	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
6031
6032	switch (enmReflect)
6033	{
6034	case SVMREFLECTXCPT_XCPT:
6035	{
6036	/* If we are re-injecting the NMI, clear NMI blocking. */
6037	if (fReflectingNmi)
6038	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6039
6040	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
6041	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6042	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
6043
6044	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
6045	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
6046	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
6047	break;
6048	}
6049
6050	case SVMREFLECTXCPT_DF:
6051	{
6052	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6053	hmR0SvmSetPendingXcptDF(pVCpu);
6054	rc = VINF_HM_DOUBLE_FAULT;
6055	break;
6056	}
6057
6058	case SVMREFLECTXCPT_TF:
6059	{
6060	rc = VINF_EM_RESET;
6061	break;
6062	}
6063
6064	case SVMREFLECTXCPT_HANG:
6065	{
6066	rc = VERR_EM_GUEST_CPU_HANG;
6067	break;
6068	}
6069
6070	default:
6071	Assert(rc == VINF_SUCCESS);
6072	break;
6073	}
6074	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
6075	}
6076	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6077	NOREF(pCtx);
6078	return rc;
6079	}
6080
6081
6082	/**
6083	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
6084	* supported, otherwise advances the RIP by the number of bytes specified in
6085	* @a cb.
6086	*
6087	* @param pVCpu The cross context virtual CPU structure.
6088	* @param pCtx Pointer to the guest-CPU context.
6089	* @param cb RIP increment value in bytes.
6090	*
6091	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
6092	* when NRIP_SAVE is supported by the CPU, otherwise use
6093	* hmR0SvmAdvanceRipDumb!
6094	*/
6095	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6096	{
6097	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6098	if (fSupportsNextRipSave)
6099	{
6100	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6101	Assert(pVmcb->ctrl.u64NextRIP);
6102	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
6103	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6104	}
6105	else
6106	pCtx->rip += cb;
6107
6108	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6109	}
6110
6111
6112	#ifdef VBOX_WITH_NESTED_HWVIRT
6113	/**
6114	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
6115	* feature. Otherwise, returns the value in @a cbLikely.
6116	*
6117	* @param pVCpu The cross context virtual CPU structure.
6118	* @param pCtx Pointer to the guest-CPU context.
6119	* @param cbLikely The likely instruction length.
6120	*/
6121	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
6122	{
6123	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
6124	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6125	if (fSupportsNextRipSave)
6126	{
6127	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6128	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6129	Assert(cbInstr == cbLikely);
6130	return cbInstr;
6131	}
6132	return cbLikely;
6133	}
6134	#endif
6135
6136
6137	/**
6138	* Advances the guest RIP by the number of bytes specified in @a cb. This does
6139	* not make use of any hardware features to determine the instruction length.
6140	*
6141	* @param pVCpu The cross context virtual CPU structure.
6142	* @param pCtx Pointer to the guest-CPU context.
6143	* @param cb RIP increment value in bytes.
6144	*/
6145	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6146	{
6147	pCtx->rip += cb;
6148	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6149	}
6150	#undef HMSVM_UPDATE_INTR_SHADOW
6151
6152
6153	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6154	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6155	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6156
6157	/** @name \#VMEXIT handlers.
6158	* @{
6159	*/
6160
6161	/**
6162	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6163	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6164	*/
6165	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6166	{
6167	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6168
6169	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6170	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6171	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6172	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6173
6174	/*
6175	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
6176	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
6177	* interrupt it is until the host actually take the interrupt.
6178	*
6179	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
6180	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6181	*/
6182	return VINF_EM_RAW_INTERRUPT;
6183	}
6184
6185
6186	/**
6187	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6188	*/
6189	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6190	{
6191	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6192
6193	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6194	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
6195	int rc = VINF_SUCCESS;
6196	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6197	return rc;
6198	}
6199
6200
6201	/**
6202	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6203	*/
6204	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6205	{
6206	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6207
6208	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6209	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
6210	int rc = VINF_SUCCESS;
6211	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6212	return rc;
6213	}
6214
6215
6216	/**
6217	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6218	*/
6219	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6220	{
6221	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6222	PVM pVM = pVCpu->CTX_SUFF(pVM);
6223	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6224	if (RT_LIKELY(rc == VINF_SUCCESS))
6225	{
6226	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6227	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6228	}
6229	else
6230	{
6231	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6232	rc = VERR_EM_INTERPRETER;
6233	}
6234	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
6235	return rc;
6236	}
6237
6238
6239	/**
6240	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6241	*/
6242	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6243	{
6244	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6245	PVM pVM = pVCpu->CTX_SUFF(pVM);
6246	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6247	if (RT_LIKELY(rc == VINF_SUCCESS))
6248	{
6249	pSvmTransient->fUpdateTscOffsetting = true;
6250	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6251	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6252	}
6253	else
6254	{
6255	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
6256	rc = VERR_EM_INTERPRETER;
6257	}
6258	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
6259	return rc;
6260	}
6261
6262
6263	/**
6264	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6265	*/
6266	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6267	{
6268	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6269	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
6270	if (RT_LIKELY(rc == VINF_SUCCESS))
6271	{
6272	pSvmTransient->fUpdateTscOffsetting = true;
6273	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6274	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6275	}
6276	else
6277	{
6278	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
6279	rc = VERR_EM_INTERPRETER;
6280	}
6281	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
6282	return rc;
6283	}
6284
6285
6286	/**
6287	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6288	*/
6289	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6290	{
6291	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6292	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6293	if (RT_LIKELY(rc == VINF_SUCCESS))
6294	{
6295	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6296	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6297	}
6298	else
6299	{
6300	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6301	rc = VERR_EM_INTERPRETER;
6302	}
6303	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6304	return rc;
6305	}
6306
6307
6308	/**
6309	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6310	*/
6311	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6312	{
6313	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6314	PVM pVM = pVCpu->CTX_SUFF(pVM);
6315	Assert(!pVM->hm.s.fNestedPaging);
6316	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6317
6318	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6319	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6320	if ( fSupportsDecodeAssists
6321	&& fSupportsNextRipSave)
6322	{
6323	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6324	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6325	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6326	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6327	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6328	return VBOXSTRICTRC_VAL(rcStrict);
6329	}
6330
6331	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6332	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6333	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6334	return rc;
6335	}
6336
6337
6338	/**
6339	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6340	*/
6341	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6342	{
6343	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6344
6345	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6346	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6347	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6348	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6349	if (rc != VINF_SUCCESS)
6350	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6351	return rc;
6352	}
6353
6354
6355	/**
6356	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6357	*/
6358	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6359	{
6360	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6361	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6362	if (RT_LIKELY(rc == VINF_SUCCESS))
6363	{
6364	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6365	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6366	}
6367	else
6368	{
6369	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6370	rc = VERR_EM_INTERPRETER;
6371	}
6372	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6373	return rc;
6374	}
6375
6376
6377	/**
6378	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6379	*/
6380	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6381	{
6382	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6383	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6384	int rc = VBOXSTRICTRC_VAL(rc2);
6385	if ( rc == VINF_EM_HALT
6386	\|\| rc == VINF_SUCCESS)
6387	{
6388	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6389
6390	if ( rc == VINF_EM_HALT
6391	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6392	{
6393	rc = VINF_SUCCESS;
6394	}
6395	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6396	}
6397	else
6398	{
6399	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6400	rc = VERR_EM_INTERPRETER;
6401	}
6402	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6403	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6404	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6405	return rc;
6406	}
6407
6408
6409	/**
6410	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6411	* \#VMEXIT.
6412	*/
6413	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6414	{
6415	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6416	return VINF_EM_RESET;
6417	}
6418
6419
6420	/**
6421	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6422	*/
6423	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6424	{
6425	RT_NOREF(pCtx);
6426	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64\n", pSvmTransient->u64ExitCode));
6427	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6428	return VERR_SVM_UNEXPECTED_EXIT;
6429	}
6430
6431
6432	/**
6433	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6434	*/
6435	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6436	{
6437	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6438
6439	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6440	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6441
6442	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6443	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6444	if ( fSupportsDecodeAssists
6445	&& fSupportsNextRipSave)
6446	{
6447	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6448	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6449	if (fMovCRx)
6450	{
6451	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6452	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6453	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6454	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6455	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6456	return VBOXSTRICTRC_VAL(rcStrict);
6457	}
6458	/* else: SMSW instruction, fall back below to IEM for this. */
6459	}
6460
6461	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6462	int rc = VBOXSTRICTRC_VAL(rc2);
6463	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6464	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6465	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6466	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6467	return rc;
6468	}
6469
6470
6471	/**
6472	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6473	*/
6474	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6475	{
6476	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6477
6478	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6479	Assert(iCrReg <= 15);
6480
6481	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6482	bool fDecodedInstr = false;
6483	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6484	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6485	if ( fSupportsDecodeAssists
6486	&& fSupportsNextRipSave)
6487	{
6488	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6489	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6490	if (fMovCRx)
6491	{
6492	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6493	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6494	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6495	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6496	fDecodedInstr = true;
6497	}
6498	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6499	}
6500
6501	if (!fDecodedInstr)
6502	{
6503	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6504	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6505	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6506	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6507	rcStrict = VERR_EM_INTERPRETER;
6508	}
6509
6510	if (rcStrict == VINF_SUCCESS)
6511	{
6512	switch (iCrReg)
6513	{
6514	case 0: /* CR0. */
6515	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6516	break;
6517
6518	case 3: /* CR3. */
6519	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6520	break;
6521
6522	case 4: /* CR4. */
6523	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6524	break;
6525
6526	case 8: /* CR8 (TPR). */
6527	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6528	break;
6529
6530	default:
6531	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6532	pSvmTransient->u64ExitCode, iCrReg));
6533	break;
6534	}
6535	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6536	}
6537	else
6538	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6539	return VBOXSTRICTRC_TODO(rcStrict);
6540	}
6541
6542
6543	/**
6544	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6545	* \#VMEXIT.
6546	*/
6547	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6548	{
6549	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6550	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6551	PVM pVM = pVCpu->CTX_SUFF(pVM);
6552
6553	int rc;
6554	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6555	{
6556	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6557	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6558
6559	/* Handle TPR patching; intercepted LSTAR write. */
6560	if ( pVM->hm.s.fTPRPatchingActive
6561	&& pCtx->ecx == MSR_K8_LSTAR)
6562	{
6563	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6564	{
6565	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6566	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6567	AssertRC(rc2);
6568	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6569	}
6570	rc = VINF_SUCCESS;
6571	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6572	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6573	return rc;
6574	}
6575
6576	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6577	if (fSupportsNextRipSave)
6578	{
6579	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6580	if (RT_LIKELY(rc == VINF_SUCCESS))
6581	{
6582	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6583	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6584	}
6585	else
6586	AssertMsg( rc == VERR_EM_INTERPRETER
6587	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6588	}
6589	else
6590	{
6591	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6592	if (RT_LIKELY(rc == VINF_SUCCESS))
6593	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6594	else
6595	AssertMsg( rc == VERR_EM_INTERPRETER
6596	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6597	}
6598
6599	if (rc == VINF_SUCCESS)
6600	{
6601	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6602	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6603	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6604	{
6605	/*
6606	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6607	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6608	* EMInterpretWrmsr() changes it.
6609	*/
6610	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6611	}
6612	else
6613	{
6614	switch (pCtx->ecx)
6615	{
6616	case MSR_K6_EFER: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR); break;
6617	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6618	case MSR_K8_FS_BASE:
6619	case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
6620	case MSR_IA32_SYSENTER_CS: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6621	case MSR_IA32_SYSENTER_EIP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6622	case MSR_IA32_SYSENTER_ESP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6623	}
6624	}
6625	}
6626	}
6627	else
6628	{
6629	/* MSR Read access. */
6630	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6631	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6632	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6633
6634	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6635	if (fSupportsNextRipSave)
6636	{
6637	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6638	if (RT_LIKELY(rc == VINF_SUCCESS))
6639	{
6640	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6641	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6642	}
6643	else
6644	AssertMsg( rc == VERR_EM_INTERPRETER
6645	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6646	}
6647	else
6648	{
6649	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6650	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6651	{
6652	AssertMsg( rc == VERR_EM_INTERPRETER
6653	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6654	}
6655	/* RIP updated by EMInterpretInstruction(). */
6656	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6657	}
6658	}
6659
6660	/* RIP has been updated by EMInterpret[Rd\|Wr]msr() or EMInterpretInstruction(). */
6661	return rc;
6662	}
6663
6664
6665	/**
6666	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6667	*/
6668	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6669	{
6670	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6671	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6672
6673	/** @todo Stepping with nested-guest. */
6674	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6675	{
6676	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6677	if (pSvmTransient->fWasGuestDebugStateActive)
6678	{
6679	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6680	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6681	return VERR_SVM_UNEXPECTED_EXIT;
6682	}
6683
6684	/*
6685	* Lazy DR0-3 loading.
6686	*/
6687	if (!pSvmTransient->fWasHyperDebugStateActive)
6688	{
6689	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6690	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6691
6692	/* Don't intercept DRx read and writes. */
6693	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6694	pVmcb->ctrl.u16InterceptRdDRx = 0;
6695	pVmcb->ctrl.u16InterceptWrDRx = 0;
6696	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6697
6698	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6699	VMMRZCallRing3Disable(pVCpu);
6700	HM_DISABLE_PREEMPT();
6701
6702	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6703	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6704	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6705
6706	HM_RESTORE_PREEMPT();
6707	VMMRZCallRing3Enable(pVCpu);
6708
6709	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6710	return VINF_SUCCESS;
6711	}
6712	}
6713
6714	/*
6715	* Interpret the read/writing of DRx.
6716	*/
6717	/** @todo Decode assist. */
6718	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6719	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6720	if (RT_LIKELY(rc == VINF_SUCCESS))
6721	{
6722	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6723	/** @todo CPUM should set this flag! */
6724	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6725	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6726	}
6727	else
6728	Assert(rc == VERR_EM_INTERPRETER);
6729	return VBOXSTRICTRC_TODO(rc);
6730	}
6731
6732
6733	/**
6734	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6735	*/
6736	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6737	{
6738	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6739	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6740	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6741	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6742	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6743	return rc;
6744	}
6745
6746
6747	/**
6748	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6749	*/
6750	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6751	{
6752	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6753
6754	/** @todo decode assists... */
6755	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6756	if (rcStrict == VINF_IEM_RAISED_XCPT)
6757	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6758
6759	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6760	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6761	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6762
6763	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6764	return VBOXSTRICTRC_TODO(rcStrict);
6765	}
6766
6767
6768	/**
6769	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6770	*/
6771	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6772	{
6773	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6774
6775	/* I/O operation lookup arrays. */
6776	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6777	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6778	the result (in AL/AX/EAX). */
6779	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6780
6781	PVM pVM = pVCpu->CTX_SUFF(pVM);
6782	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6783
6784	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6785	SVMIOIOEXITINFO IoExitInfo;
6786	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6787	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6788	uint32_t cbValue = s_aIOSize[uIOWidth];
6789	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6790
6791	if (RT_UNLIKELY(!cbValue))
6792	{
6793	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6794	return VERR_EM_INTERPRETER;
6795	}
6796
6797	VBOXSTRICTRC rcStrict;
6798	bool fUpdateRipAlready = false;
6799	if (IoExitInfo.n.u1STR)
6800	{
6801	#ifdef VBOX_WITH_2ND_IEM_STEP
6802	/* INS/OUTS - I/O String instruction. */
6803	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6804	* in EXITINFO1? Investigate once this thing is up and running. */
6805	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6806	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6807	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6808	static IEMMODE const s_aenmAddrMode[8] =
6809	{
6810	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6811	};
6812	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6813	if (enmAddrMode != (IEMMODE)-1)
6814	{
6815	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6816	if (cbInstr <= 15 && cbInstr >= 1)
6817	{
6818	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6819	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6820	{
6821	/* Don't know exactly how to detect whether u3SEG is valid, currently
6822	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6823	2384 Opterons when only checking NRIP. */
6824	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6825	if ( fSupportsNextRipSave
6826	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6827	{
6828	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6829	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6830	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6831	IoExitInfo.n.u3SEG, true /fIoChecked/);
6832	}
6833	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6834	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6835	X86_SREG_DS, true /fIoChecked/);
6836	else
6837	rcStrict = IEMExecOne(pVCpu);
6838	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6839	}
6840	else
6841	{
6842	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6843	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6844	true /fIoChecked/);
6845	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6846	}
6847	}
6848	else
6849	{
6850	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6851	rcStrict = IEMExecOne(pVCpu);
6852	}
6853	}
6854	else
6855	{
6856	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6857	rcStrict = IEMExecOne(pVCpu);
6858	}
6859	fUpdateRipAlready = true;
6860
6861	#else
6862	/* INS/OUTS - I/O String instruction. */
6863	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6864
6865	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6866	* in EXITINFO1? Investigate once this thing is up and running. */
6867
6868	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6869	if (rcStrict == VINF_SUCCESS)
6870	{
6871	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6872	{
6873	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6874	(DISCPUMODE)pDis->uAddrMode, cbValue);
6875	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6876	}
6877	else
6878	{
6879	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6880	(DISCPUMODE)pDis->uAddrMode, cbValue);
6881	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6882	}
6883	}
6884	else
6885	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6886	#endif
6887	}
6888	else
6889	{
6890	/* IN/OUT - I/O instruction. */
6891	Assert(!IoExitInfo.n.u1REP);
6892
6893	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6894	{
6895	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6896	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6897	}
6898	else
6899	{
6900	uint32_t u32Val = 0;
6901	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6902	if (IOM_SUCCESS(rcStrict))
6903	{
6904	/* Save result of I/O IN instr. in AL/AX/EAX. */
6905	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6906	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6907	}
6908	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6909	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6910
6911	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6912	}
6913	}
6914
6915	if (IOM_SUCCESS(rcStrict))
6916	{
6917	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6918	if (!fUpdateRipAlready)
6919	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6920
6921	/*
6922	* If any I/O breakpoints are armed, we need to check if one triggered
6923	* and take appropriate action.
6924	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6925	*/
6926	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6927	* execution engines about whether hyper BPs and such are pending. */
6928	uint32_t const uDr7 = pCtx->dr[7];
6929	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6930	&& X86_DR7_ANY_RW_IO(uDr7)
6931	&& (pCtx->cr4 & X86_CR4_DE))
6932	\|\| DBGFBpIsHwIoArmed(pVM)))
6933	{
6934	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6935	VMMRZCallRing3Disable(pVCpu);
6936	HM_DISABLE_PREEMPT();
6937
6938	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6939	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6940
6941	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6942	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6943	{
6944	/* Raise #DB. */
6945	pVmcb->guest.u64DR6 = pCtx->dr[6];
6946	pVmcb->guest.u64DR7 = pCtx->dr[7];
6947	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6948	hmR0SvmSetPendingXcptDB(pVCpu);
6949	}
6950	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6951	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6952	else if ( rcStrict2 != VINF_SUCCESS
6953	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6954	rcStrict = rcStrict2;
6955	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6956
6957	HM_RESTORE_PREEMPT();
6958	VMMRZCallRing3Enable(pVCpu);
6959	}
6960
6961	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6962	}
6963
6964	#ifdef VBOX_STRICT
6965	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6966	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6967	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6968	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6969	else
6970	{
6971	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6972	* statuses, that the VMM device and some others may return. See
6973	* IOM_SUCCESS() for guidance. */
6974	AssertMsg( RT_FAILURE(rcStrict)
6975	\|\| rcStrict == VINF_SUCCESS
6976	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6977	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6978	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6979	\|\| rcStrict == VINF_EM_RAW_TO_R3
6980	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6981	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6982	}
6983	#endif
6984	return VBOXSTRICTRC_TODO(rcStrict);
6985	}
6986
6987
6988	/**
6989	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6990	*/
6991	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6992	{
6993	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6994	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
6995
6996	PVM pVM = pVCpu->CTX_SUFF(pVM);
6997	Assert(pVM->hm.s.fNestedPaging);
6998
6999	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7000
7001	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7002	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7003	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7004	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7005
7006	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
7007
7008	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7009	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
7010	if ( pVM->hm.s.fTprPatchingAllowed
7011	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7012	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7013	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7014	&& !CPUMIsGuestInLongModeEx(pCtx)
7015	&& !CPUMGetGuestCPL(pVCpu)
7016	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7017	{
7018	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7019	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7020
7021	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7022	{
7023	/* Only attempt to patch the instruction once. */
7024	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7025	if (!pPatch)
7026	return VINF_EM_HM_PATCH_TPR_INSTR;
7027	}
7028	}
7029	#endif
7030
7031	/*
7032	* Determine the nested paging mode.
7033	*/
7034	PGMMODE enmNestedPagingMode;
7035	#if HC_ARCH_BITS == 32
7036	if (CPUMIsGuestInLongModeEx(pCtx))
7037	enmNestedPagingMode = PGMMODE_AMD64_NX;
7038	else
7039	#endif
7040	enmNestedPagingMode = PGMGetHostMode(pVM);
7041
7042	/*
7043	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7044	*/
7045	int rc;
7046	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7047	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7048	{
7049	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
7050	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
7051	if (pVCpu->hm.s.Event.fPending)
7052	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7053
7054	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7055	u32ErrCode);
7056	rc = VBOXSTRICTRC_VAL(rc2);
7057
7058	/*
7059	* If we succeed, resume guest execution.
7060	* If we fail in interpreting the instruction because we couldn't get the guest physical address
7061	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
7062	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
7063	* weird case. See @bugref{6043}.
7064	*/
7065	if ( rc == VINF_SUCCESS
7066	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7067	\|\| rc == VERR_PAGE_NOT_PRESENT)
7068	{
7069	/* Successfully handled MMIO operation. */
7070	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
7071	rc = VINF_SUCCESS;
7072	}
7073	return rc;
7074	}
7075
7076	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7077	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7078	TRPMResetTrap(pVCpu);
7079
7080	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7081
7082	/*
7083	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7084	*/
7085	if ( rc == VINF_SUCCESS
7086	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7087	\|\| rc == VERR_PAGE_NOT_PRESENT)
7088	{
7089	/* We've successfully synced our shadow page tables. */
7090	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7091	rc = VINF_SUCCESS;
7092	}
7093
7094	return rc;
7095	}
7096
7097
7098	/**
7099	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7100	* \#VMEXIT.
7101	*/
7102	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7103	{
7104	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7105	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7106
7107	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7108	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7109	hmR0SvmClearVirtIntrIntercept(pVmcb);
7110
7111	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7112	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7113	return VINF_SUCCESS;
7114	}
7115
7116
7117	/**
7118	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7119	* \#VMEXIT.
7120	*/
7121	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7122	{
7123	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7124
7125	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7126
7127	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7128	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7129	#endif
7130
7131	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7132	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7133	{
7134	/*
7135	* AMD-V provides us with the exception which caused the TS; we collect
7136	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
7137	*/
7138	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
7139	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7140	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7141	}
7142
7143	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7144	* emulation. */
7145	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7146	return VERR_EM_INTERPRETER;
7147	}
7148
7149
7150	/**
7151	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7152	*/
7153	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7154	{
7155	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7156	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
7157
7158	bool fRipUpdated;
7159	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
7160	if (RT_SUCCESS(rcStrict))
7161	{
7162	/* Only update the RIP if we're continuing guest execution and not
7163	in the case of say VINF_GIM_R3_HYPERCALL. */
7164	if ( rcStrict == VINF_SUCCESS
7165	&& !fRipUpdated)
7166	{
7167	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
7168	}
7169
7170	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
7171	we would need to reload the guest changed bits here before VM-entry. */
7172	return VBOXSTRICTRC_VAL(rcStrict);
7173	}
7174
7175	hmR0SvmSetPendingXcptUD(pVCpu);
7176	return VINF_SUCCESS;
7177	}
7178
7179
7180	/**
7181	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7182	*/
7183	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7184	{
7185	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7186	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
7187	return VINF_EM_RAW_INTERRUPT;
7188	}
7189
7190
7191	/**
7192	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7193	*/
7194	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7195	{
7196	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7197
7198	/* Clear NMI blocking. */
7199	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7200
7201	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7202	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7203	hmR0SvmClearIretIntercept(pVmcb);
7204
7205	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7206	return VINF_SUCCESS;
7207	}
7208
7209
7210	/**
7211	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
7212	* Conditional \#VMEXIT.
7213	*/
7214	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7215	{
7216	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7217	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7218
7219	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7220
7221	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7222	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7223	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7224	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7225	PVM pVM = pVCpu->CTX_SUFF(pVM);
7226
7227	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7228	if (pVM->hm.s.fNestedPaging)
7229	{
7230	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7231	if (!pSvmTransient->fVectoringDoublePF)
7232	{
7233	/* A genuine guest #PF, reflect it to the guest. */
7234	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7235	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7236	uFaultAddress, u32ErrCode));
7237	}
7238	else
7239	{
7240	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7241	hmR0SvmSetPendingXcptDF(pVCpu);
7242	Log4(("Pending #DF due to vectoring #PF. NP\n"));
7243	}
7244	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7245	return VINF_SUCCESS;
7246	}
7247	#endif
7248
7249	Assert(!pVM->hm.s.fNestedPaging);
7250
7251	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7252	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
7253	if ( pVM->hm.s.fTprPatchingAllowed
7254	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7255	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
7256	&& !CPUMIsGuestInLongModeEx(pCtx)
7257	&& !CPUMGetGuestCPL(pVCpu)
7258	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7259	{
7260	RTGCPHYS GCPhysApicBase;
7261	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7262	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7263
7264	/* Check if the page at the fault-address is the APIC base. */
7265	RTGCPHYS GCPhysPage;
7266	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7267	if ( rc2 == VINF_SUCCESS
7268	&& GCPhysPage == GCPhysApicBase)
7269	{
7270	/* Only attempt to patch the instruction once. */
7271	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7272	if (!pPatch)
7273	return VINF_EM_HM_PATCH_TPR_INSTR;
7274	}
7275	}
7276	#endif
7277
7278	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7279	pCtx->rip, u32ErrCode, pCtx->cr3));
7280
7281	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7282	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7283	if (pSvmTransient->fVectoringPF)
7284	{
7285	Assert(pVCpu->hm.s.Event.fPending);
7286	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7287	}
7288
7289	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7290	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7291
7292	Log4(("#PF rc=%Rrc\n", rc));
7293
7294	if (rc == VINF_SUCCESS)
7295	{
7296	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7297	TRPMResetTrap(pVCpu);
7298	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7299	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7300	return rc;
7301	}
7302	else if (rc == VINF_EM_RAW_GUEST_TRAP)
7303	{
7304	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7305
7306	if (!pSvmTransient->fVectoringDoublePF)
7307	{
7308	/* It's a guest page fault and needs to be reflected to the guest. */
7309	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7310	TRPMResetTrap(pVCpu);
7311	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7312	}
7313	else
7314	{
7315	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7316	TRPMResetTrap(pVCpu);
7317	hmR0SvmSetPendingXcptDF(pVCpu);
7318	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7319	}
7320
7321	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7322	return VINF_SUCCESS;
7323	}
7324
7325	TRPMResetTrap(pVCpu);
7326	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7327	return rc;
7328	}
7329
7330
7331	/**
7332	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
7333	* Conditional \#VMEXIT.
7334	*/
7335	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7336	{
7337	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7338
7339	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7340	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7341	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7342
7343	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7344	VMMRZCallRing3Disable(pVCpu);
7345	HM_DISABLE_PREEMPT();
7346
7347	int rc;
7348	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7349	if (pSvmTransient->fWasGuestFPUStateActive)
7350	{
7351	rc = VINF_EM_RAW_GUEST_TRAP;
7352	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7353	}
7354	else
7355	{
7356	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7357	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7358	#endif
7359	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7360	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7361	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7362	}
7363
7364	HM_RESTORE_PREEMPT();
7365	VMMRZCallRing3Enable(pVCpu);
7366
7367	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7368	{
7369	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7370	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7371	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7372	pVCpu->hm.s.fPreloadGuestFpu = true;
7373	}
7374	else
7375	{
7376	/* Forward #NM to the guest. */
7377	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7378	hmR0SvmSetPendingXcptNM(pVCpu);
7379	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7380	}
7381	return VINF_SUCCESS;
7382	}
7383
7384
7385	/**
7386	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7387	* Conditional \#VMEXIT.
7388	*/
7389	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7390	{
7391	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7392
7393	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7394	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7395	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7396
7397	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7398	if (pVCpu->hm.s.fGIMTrapXcptUD)
7399	{
7400	uint8_t cbInstr = 0;
7401	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7402	if (rcStrict == VINF_SUCCESS)
7403	{
7404	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7405	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7406	rc = VINF_SUCCESS;
7407	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7408	}
7409	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7410	rc = VINF_SUCCESS;
7411	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7412	rc = VINF_GIM_R3_HYPERCALL;
7413	else
7414	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7415	}
7416
7417	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7418	if (RT_FAILURE(rc))
7419	{
7420	hmR0SvmSetPendingXcptUD(pVCpu);
7421	rc = VINF_SUCCESS;
7422	}
7423
7424	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7425	return rc;
7426	}
7427
7428
7429	/**
7430	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7431	* Conditional \#VMEXIT.
7432	*/
7433	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7434	{
7435	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7436
7437	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7438	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7439	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7440
7441	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7442
7443	if (!(pCtx->cr0 & X86_CR0_NE))
7444	{
7445	PVM pVM = pVCpu->CTX_SUFF(pVM);
7446	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7447	unsigned cbOp;
7448	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7449	if (RT_SUCCESS(rc))
7450	{
7451	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7452	/** @todo FERR intercept when in nested-guest mode? */
7453	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7454	if (RT_SUCCESS(rc))
7455	pCtx->rip += cbOp;
7456	}
7457	else
7458	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7459	return rc;
7460	}
7461
7462	hmR0SvmSetPendingXcptMF(pVCpu);
7463	return VINF_SUCCESS;
7464	}
7465
7466
7467	/**
7468	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7469	* \#VMEXIT.
7470	*/
7471	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7472	{
7473	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7474
7475	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7476	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7477	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7478	{
7479	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7480	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7481	}
7482
7483	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7484
7485	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7486	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7487	PVM pVM = pVCpu->CTX_SUFF(pVM);
7488	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7489	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7490	if (rc == VINF_EM_RAW_GUEST_TRAP)
7491	{
7492	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7493	if (CPUMIsHyperDebugStateActive(pVCpu))
7494	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7495
7496	/* Reflect the exception back to the guest. */
7497	hmR0SvmSetPendingXcptDB(pVCpu);
7498	rc = VINF_SUCCESS;
7499	}
7500
7501	/*
7502	* Update DR6.
7503	*/
7504	if (CPUMIsHyperDebugStateActive(pVCpu))
7505	{
7506	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7507	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7508	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7509	}
7510	else
7511	{
7512	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7513	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7514	}
7515
7516	return rc;
7517	}
7518
7519
7520	/**
7521	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7522	* Conditional \#VMEXIT.
7523	*/
7524	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7525	{
7526	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7527
7528	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7529	* shutdown VMEXIT. */
7530	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7531
7532	SVMEVENT Event;
7533	Event.u = 0;
7534	Event.n.u1Valid = 1;
7535	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7536	Event.n.u8Vector = X86_XCPT_AC;
7537	Event.n.u1ErrorCodeValid = 1;
7538	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7539	return VINF_SUCCESS;
7540	}
7541
7542
7543	/**
7544	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7545	* Conditional \#VMEXIT.
7546	*/
7547	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7548	{
7549	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7550
7551	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7552
7553	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7554	if (rc == VINF_EM_RAW_GUEST_TRAP)
7555	{
7556	SVMEVENT Event;
7557	Event.u = 0;
7558	Event.n.u1Valid = 1;
7559	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7560	Event.n.u8Vector = X86_XCPT_BP;
7561	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7562	}
7563
7564	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7565	return rc;
7566	}
7567
7568
7569	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
7570	/**
7571	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7572	*/
7573	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7574	{
7575	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7576
7577	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7578
7579	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7580	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_EXCEPTION_0;
7581	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7582	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7583	Assert(uVector <= X86_XCPT_LAST);
7584	Log4(("hmR0SvmExitXcptGeneric: uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7585
7586	SVMEVENT Event;
7587	Event.u = 0;
7588	Event.n.u1Valid = 1;
7589	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7590	Event.n.u8Vector = uVector;
7591	switch (uVector)
7592	{
7593	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7594	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7595	case X86_XCPT_DF:
7596	case X86_XCPT_TS:
7597	case X86_XCPT_NP:
7598	case X86_XCPT_SS:
7599	case X86_XCPT_GP:
7600	case X86_XCPT_AC:
7601	{
7602	Event.n.u1ErrorCodeValid = 1;
7603	Event.n.u32ErrorCode = uErrCode;
7604	break;
7605	}
7606	}
7607
7608	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7609	return VINF_SUCCESS;
7610	}
7611	#endif
7612
7613	#ifdef VBOX_WITH_NESTED_HWVIRT
7614	/**
7615	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7616	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7617	*/
7618	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7619	{
7620	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7621
7622	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7623
7624	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7625	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7626	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7627	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7628
7629	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7630	pCtx->rip, u32ErrCode, pCtx->cr3));
7631
7632	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7633	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7634	if (pSvmTransient->fVectoringPF)
7635	{
7636	Assert(pVCpu->hm.s.Event.fPending);
7637	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7638	}
7639
7640	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7641
7642	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7643	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7644
7645	Log4(("#PFNested: rc=%Rrc\n", rc));
7646
7647	if (rc == VINF_SUCCESS)
7648	{
7649	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7650	TRPMResetTrap(pVCpu);
7651	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7652	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7653	return rc;
7654	}
7655
7656	if (rc == VINF_EM_RAW_GUEST_TRAP)
7657	{
7658	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7659
7660	if (!pSvmTransient->fVectoringDoublePF)
7661	{
7662	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7663	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7664	TRPMResetTrap(pVCpu);
7665	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7666	}
7667	else
7668	{
7669	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7670	TRPMResetTrap(pVCpu);
7671	hmR0SvmSetPendingXcptDF(pVCpu);
7672	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7673	}
7674
7675	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7676	return VINF_SUCCESS;
7677	}
7678
7679	TRPMResetTrap(pVCpu);
7680	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7681	return rc;
7682	}
7683
7684
7685	/**
7686	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7687	*/
7688	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7689	{
7690	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7691
7692	#ifdef VBOX_STRICT
7693	PCSVMVMCB pVmcbTmp = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7694	Assert(pVmcbTmp);
7695	Assert(!pVmcbTmp->ctrl.IntCtrl.n.u1VGifEnable);
7696	RT_NOREF(pVmcbTmp);
7697	#endif
7698
7699	/** @todo Stat. */
7700	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7701	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7702	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7703	return VBOXSTRICTRC_VAL(rcStrict);
7704	}
7705
7706
7707	/**
7708	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7709	*/
7710	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7711	{
7712	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7713
7714	#ifdef VBOX_STRICT
7715	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7716	Assert(pVmcb);
7717	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7718	RT_NOREF(pVmcb);
7719	#endif
7720
7721	/** @todo Stat. */
7722	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7723	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7724	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7725	return VBOXSTRICTRC_VAL(rcStrict);
7726	}
7727
7728
7729	/**
7730	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7731	*/
7732	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7733	{
7734	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7735
7736	#ifdef VBOX_STRICT
7737	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7738	Assert(pVmcb);
7739	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7740	RT_NOREF(pVmcb);
7741	#endif
7742
7743	/** @todo Stat. */
7744	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7745	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7746	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7747	if (rcStrict == VINF_SUCCESS)
7748	{
7749	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7750	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7751	\| HM_CHANGED_GUEST_TR
7752	\| HM_CHANGED_GUEST_LDTR);
7753	}
7754	return VBOXSTRICTRC_VAL(rcStrict);
7755	}
7756
7757
7758	/**
7759	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7760	*/
7761	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7762	{
7763	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7764
7765	#ifdef VBOX_STRICT
7766	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7767	Assert(pVmcb);
7768	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7769	RT_NOREF(pVmcb);
7770	#endif
7771
7772	/** @todo Stat. */
7773	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7774	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7775	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7776	return VBOXSTRICTRC_VAL(rcStrict);
7777	}
7778
7779
7780	/**
7781	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7782	*/
7783	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7784	{
7785	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7786	/** @todo Stat. */
7787	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7788	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7789	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7790	return VBOXSTRICTRC_VAL(rcStrict);
7791	}
7792
7793
7794	/**
7795	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7796	*/
7797	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7798	{
7799	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7800	/** @todo Stat. */
7801	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7802	#if 0
7803	VBOXSTRICTRC rcStrict;
7804	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7805	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7806	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7807	if (rcStrict == VINF_SUCCESS)
7808	{
7809	rcStrict = VINF_SVM_VMRUN;
7810	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7811	}
7812	return VBOXSTRICTRC_VAL(rcStrict);
7813	#endif
7814	return VERR_EM_INTERPRETER;
7815	}
7816
7817
7818	/**
7819	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7820	* Unconditional \#VMEXIT.
7821	*/
7822	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7823	{
7824	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7825
7826	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7827	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7828	* shutdown VMEXIT. */
7829	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7830	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7831	{
7832	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7833	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7834	}
7835
7836	hmR0SvmSetPendingXcptDB(pVCpu);
7837	return VINF_SUCCESS;
7838	}
7839
7840
7841	/**
7842	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7843	* Conditional \#VMEXIT.
7844	*/
7845	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7846	{
7847	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7848
7849	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7850	* shutdown VMEXIT. */
7851	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7852
7853	SVMEVENT Event;
7854	Event.u = 0;
7855	Event.n.u1Valid = 1;
7856	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7857	Event.n.u8Vector = X86_XCPT_BP;
7858	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7859	return VINF_SUCCESS;
7860	}
7861
7862	#endif /* VBOX_WITH_NESTED_HWVIRT */
7863
7864
7865	/** @} */
7866

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 71076

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