HMSVMR0.cpp@ 71875

Last change on this file since 71875 was 71859, checked in by vboxsync, 7 years ago
VMM: SVM NestedPagingCtrl naming consistency with rest of the VMCB fields.
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1	/* $Id: HMSVMR0.cpp 71859 2018-04-13 10:56:05Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#define HMSVM_USE_IEM_EVENT_REFLECTION
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_SYNC_FULL_NESTED_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	if ((u64ExitCode) == SVM_EXIT_NPF) \
65	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
66	else \
67	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
68	} while (0)
69	# endif
70	#else
71	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
72	# ifdef VBOX_WITH_NESTED_HWVIRT
73	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
74	# endif
75	#endif /* !VBOX_WITH_STATISTICS */
76
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static int
81
82	/** Macro for checking and returning from the using function for
83	* \#VMEXIT intercepts that maybe caused during delivering of another
84	* event in the guest. */
85	#ifdef VBOX_WITH_NESTED_HWVIRT
86	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
87	do \
88	{ \
89	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
90	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
91	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
92	else if ( rc == VINF_EM_RESET \
93	&& HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
94	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_SHUTDOWN, 0, 0)); \
95	else \
96	return rc; \
97	} while (0)
98	#else
99	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
100	do \
101	{ \
102	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
103	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
104	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
105	else \
106	return rc; \
107	} while (0)
108	#endif
109
110	/**
111	* Updates interrupt shadow for the current RIP.
112	*/
113	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
114	do { \
115	/* Update interrupt shadow. */ \
116	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
117	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
118	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
119	} while (0)
120
121	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
122	* instruction that exited. */
123	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
124	do { \
125	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
126	(a_rc) = VINF_EM_DBG_STEPPED; \
127	} while (0)
128
129	/** Assert that preemption is disabled or covered by thread-context hooks. */
130	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
131	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
132
133	/** Assert that we haven't migrated CPUs when thread-context hooks are not
134	* used. */
135	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
136	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
137	("Illegal migration! Entered on CPU %u Current %u\n", \
138	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
139
140	/** Assert that we're not executing a nested-guest. */
141	#ifdef VBOX_WITH_NESTED_HWVIRT
142	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
143	#else
144	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
145	#endif
146
147	/** Assert that we're executing a nested-guest. */
148	#ifdef VBOX_WITH_NESTED_HWVIRT
149	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
150	#else
151	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
152	#endif
153
154	/** Validate segment descriptor granularity bit. */
155	#ifdef VBOX_STRICT
156	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
157	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
158	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
159	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
160	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
161	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
162	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
163	#else
164	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) do { } while (0)
165	#endif
166
167	/**
168	* Exception bitmap mask for all contributory exceptions.
169	*
170	* Page fault is deliberately excluded here as it's conditional as to whether
171	* it's contributory or benign. Page faults are handled separately.
172	*/
173	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
174	\| RT_BIT(X86_XCPT_DE))
175
176	/**
177	* Mandatory/unconditional guest control intercepts.
178	*
179	* SMIs can and do happen in normal operation. We need not intercept them
180	* while executing the guest or nested-guest.
181	*/
182	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
183	\| SVM_CTRL_INTERCEPT_NMI \
184	\| SVM_CTRL_INTERCEPT_INIT \
185	\| SVM_CTRL_INTERCEPT_RDPMC \
186	\| SVM_CTRL_INTERCEPT_CPUID \
187	\| SVM_CTRL_INTERCEPT_RSM \
188	\| SVM_CTRL_INTERCEPT_HLT \
189	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
190	\| SVM_CTRL_INTERCEPT_MSR_PROT \
191	\| SVM_CTRL_INTERCEPT_INVLPGA \
192	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
193	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
194	\| SVM_CTRL_INTERCEPT_VMRUN \
195	\| SVM_CTRL_INTERCEPT_SKINIT \
196	\| SVM_CTRL_INTERCEPT_WBINVD \
197	\| SVM_CTRL_INTERCEPT_MONITOR \
198	\| SVM_CTRL_INTERCEPT_MWAIT \
199	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
200	\| SVM_CTRL_INTERCEPT_XSETBV)
201
202	/** @name VMCB Clean Bits.
203	*
204	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
205	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
206	* memory.
207	*
208	* @{ */
209	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
210	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
211	/** I/O permission bitmap, MSR permission bitmap. */
212	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
213	/** ASID. */
214	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
215	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
216	V_INTR_VECTOR. */
217	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
218	/** Nested Paging: Nested CR3 (nCR3), PAT. */
219	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
220	/** Control registers (CR0, CR3, CR4, EFER). */
221	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
222	/** Debug registers (DR6, DR7). */
223	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
224	/** GDT, IDT limit and base. */
225	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
226	/** Segment register: CS, SS, DS, ES limit and base. */
227	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
228	/** CR2.*/
229	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
230	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
231	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
232	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
233	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
234	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
235	/** Mask of all valid VMCB Clean bits. */
236	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
237	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
238	\| HMSVM_VMCB_CLEAN_ASID \
239	\| HMSVM_VMCB_CLEAN_TPR \
240	\| HMSVM_VMCB_CLEAN_NP \
241	\| HMSVM_VMCB_CLEAN_CRX_EFER \
242	\| HMSVM_VMCB_CLEAN_DRX \
243	\| HMSVM_VMCB_CLEAN_DT \
244	\| HMSVM_VMCB_CLEAN_SEG \
245	\| HMSVM_VMCB_CLEAN_CR2 \
246	\| HMSVM_VMCB_CLEAN_LBR \
247	\| HMSVM_VMCB_CLEAN_AVIC)
248	/** @} */
249
250	/** @name SVM transient.
251	*
252	* A state structure for holding miscellaneous information across AMD-V
253	* VMRUN/\#VMEXIT operation, restored after the transition.
254	*
255	* @{ */
256	typedef struct SVMTRANSIENT
257	{
258	/** The host's rflags/eflags. */
259	RTCCUINTREG fEFlags;
260	#if HC_ARCH_BITS == 32
261	uint32_t u32Alignment0;
262	#endif
263
264	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
265	uint64_t u64ExitCode;
266	/** The guest's TPR value used for TPR shadowing. */
267	uint8_t u8GuestTpr;
268	/** Alignment. */
269	uint8_t abAlignment0[7];
270
271	/** Whether the guest debug state was active at the time of \#VMEXIT. */
272	bool fWasGuestDebugStateActive;
273	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
274	bool fWasHyperDebugStateActive;
275	/** Whether the TSC offset mode needs to be updated. */
276	bool fUpdateTscOffsetting;
277	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
278	bool fRestoreTscAuxMsr;
279	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
280	* contributary exception or a page-fault. */
281	bool fVectoringDoublePF;
282	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
283	* external interrupt or NMI. */
284	bool fVectoringPF;
285	} SVMTRANSIENT, *PSVMTRANSIENT;
286	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
287	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestDebugStateActive, sizeof(uint64_t));
288	/** @} */
289
290	/**
291	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
292	*/
293	typedef enum SVMMSREXITREAD
294	{
295	/** Reading this MSR causes a \#VMEXIT. */
296	SVMMSREXIT_INTERCEPT_READ = 0xb,
297	/** Reading this MSR does not cause a \#VMEXIT. */
298	SVMMSREXIT_PASSTHRU_READ
299	} SVMMSREXITREAD;
300
301	/**
302	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
303	*/
304	typedef enum SVMMSREXITWRITE
305	{
306	/** Writing to this MSR causes a \#VMEXIT. */
307	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
308	/** Writing to this MSR does not cause a \#VMEXIT. */
309	SVMMSREXIT_PASSTHRU_WRITE
310	} SVMMSREXITWRITE;
311
312	/**
313	* SVM \#VMEXIT handler.
314	*
315	* @returns VBox status code.
316	* @param pVCpu The cross context virtual CPU structure.
317	* @param pMixedCtx Pointer to the guest-CPU context.
318	* @param pSvmTransient Pointer to the SVM-transient structure.
319	*/
320	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
321
322
323	/*********************************************************************************************************************************
324	* Internal Functions *
325	*********************************************************************************************************************************/
326	static void hmR0SvmSetMsrPermission(PCPUMCTX pCtx, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
327	SVMMSREXITWRITE enmWrite);
328	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
329	static void hmR0SvmLeave(PVMCPU pVCpu);
330
331	/** @name \#VMEXIT handlers.
332	* @{
333	*/
334	static FNSVMEXITHANDLER hmR0SvmExitIntr;
335	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
336	static FNSVMEXITHANDLER hmR0SvmExitInvd;
337	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
338	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
339	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
340	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
341	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
342	static FNSVMEXITHANDLER hmR0SvmExitHlt;
343	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
344	static FNSVMEXITHANDLER hmR0SvmExitMwait;
345	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
346	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
347	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
348	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
349	static FNSVMEXITHANDLER hmR0SvmExitMsr;
350	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
351	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
352	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
353	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
354	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
355	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
356	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
357	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
358	static FNSVMEXITHANDLER hmR0SvmExitPause;
359	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
360	static FNSVMEXITHANDLER hmR0SvmExitIret;
361	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
362	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
363	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
364	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
365	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
366	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
367	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
368	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
369	#endif
370	#ifdef VBOX_WITH_NESTED_HWVIRT
371	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
372	static FNSVMEXITHANDLER hmR0SvmExitClgi;
373	static FNSVMEXITHANDLER hmR0SvmExitStgi;
374	static FNSVMEXITHANDLER hmR0SvmExitVmload;
375	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
376	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
377	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
378	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
379	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
380	#endif
381	/** @} */
382
383	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
384	#ifdef VBOX_WITH_NESTED_HWVIRT
385	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
386	#endif
387
388
389	/*********************************************************************************************************************************
390	* Global Variables *
391	*********************************************************************************************************************************/
392	/** Ring-0 memory object for the IO bitmap. */
393	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
394	/** Physical address of the IO bitmap. */
395	static RTHCPHYS g_HCPhysIOBitmap;
396	/** Pointer to the IO bitmap. */
397	static R0PTRTYPE(void *) g_pvIOBitmap;
398
399	#ifdef VBOX_STRICT
400	# define HMSVM_LOG_CS RT_BIT_32(0)
401	# define HMSVM_LOG_SS RT_BIT_32(1)
402	# define HMSVM_LOG_FS RT_BIT_32(2)
403	# define HMSVM_LOG_GS RT_BIT_32(3)
404	# define HMSVM_LOG_LBR RT_BIT_32(4)
405	# define HMSVM_LOG_ALL ( HMSVM_LOG_CS \
406	\| HMSVM_LOG_SS \
407	\| HMSVM_LOG_FS \
408	\| HMSVM_LOG_GS \
409	\| HMSVM_LOG_LBR)
410
411	/**
412	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
413	*
414	* @param pVCpu The cross context virtual CPU structure.
415	* @param pVmcb Pointer to the VM control block.
416	* @param pCtx Pointer to the guest-CPU context.
417	* @param pszPrefix Log prefix.
418	* @param fFlags Log flags, see HMSVM_LOG_XXX.
419	* @param uVerbose The verbosity level, currently unused.
420	*/
421	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, PCPUMCTX pCtx, const char *pszPrefix, uint32_t fFlags,
422	uint8_t uVerbose)
423	{
424	RT_NOREF2(pVCpu, uVerbose);
425
426	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip,
427	pCtx->rflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
428	Log4(("%s: rsp=%#RX64 rbp=%#RX64 rdi=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp, pCtx->rdi));
429	if (fFlags & HMSVM_LOG_CS)
430	{
431	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
432	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
433	}
434	if (fFlags & HMSVM_LOG_SS)
435	{
436	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
437	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
438	}
439	if (fFlags & HMSVM_LOG_FS)
440	{
441	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
442	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
443	}
444	if (fFlags & HMSVM_LOG_GS)
445	{
446	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
447	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
448	}
449
450	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
451	if (fFlags & HMSVM_LOG_LBR)
452	{
453	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
454	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
455	}
456	NOREF(pVmcbGuest);
457	}
458	#endif /* VBOX_STRICT */
459
460
461	/**
462	* Sets up and activates AMD-V on the current CPU.
463	*
464	* @returns VBox status code.
465	* @param pCpu Pointer to the CPU info struct.
466	* @param pVM The cross context VM structure. Can be
467	* NULL after a resume!
468	* @param pvCpuPage Pointer to the global CPU page.
469	* @param HCPhysCpuPage Physical address of the global CPU page.
470	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
471	* @param pvArg Unused on AMD-V.
472	*/
473	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
474	void *pvArg)
475	{
476	Assert(!fEnabledByHost);
477	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
478	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
479	Assert(pvCpuPage); NOREF(pvCpuPage);
480	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
481
482	NOREF(pvArg);
483	NOREF(fEnabledByHost);
484
485	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
486	RTCCUINTREG fEFlags = ASMIntDisableFlags();
487
488	/*
489	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
490	*/
491	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
492	if (u64HostEfer & MSR_K6_EFER_SVME)
493	{
494	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
495	if ( pVM
496	&& pVM->hm.s.svm.fIgnoreInUseError)
497	{
498	pCpu->fIgnoreAMDVInUseError = true;
499	}
500
501	if (!pCpu->fIgnoreAMDVInUseError)
502	{
503	ASMSetFlags(fEFlags);
504	return VERR_SVM_IN_USE;
505	}
506	}
507
508	/* Turn on AMD-V in the EFER MSR. */
509	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
510
511	/* Write the physical page address where the CPU will store the host state while executing the VM. */
512	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
513
514	/* Restore interrupts. */
515	ASMSetFlags(fEFlags);
516
517	/*
518	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
519	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
520	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
521	* guest code.
522	*/
523	pCpu->fFlushAsidBeforeUse = true;
524
525	/*
526	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
527	*/
528	++pCpu->cTlbFlushes;
529
530	return VINF_SUCCESS;
531	}
532
533
534	/**
535	* Deactivates AMD-V on the current CPU.
536	*
537	* @returns VBox status code.
538	* @param pCpu Pointer to the CPU info struct.
539	* @param pvCpuPage Pointer to the global CPU page.
540	* @param HCPhysCpuPage Physical address of the global CPU page.
541	*/
542	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
543	{
544	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
545	AssertReturn( HCPhysCpuPage
546	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
547	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
548	NOREF(pCpu);
549
550	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
551	RTCCUINTREG fEFlags = ASMIntDisableFlags();
552
553	/* Turn off AMD-V in the EFER MSR. */
554	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
555	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
556
557	/* Invalidate host state physical address. */
558	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
559
560	/* Restore interrupts. */
561	ASMSetFlags(fEFlags);
562
563	return VINF_SUCCESS;
564	}
565
566
567	/**
568	* Does global AMD-V initialization (called during module initialization).
569	*
570	* @returns VBox status code.
571	*/
572	VMMR0DECL(int) SVMR0GlobalInit(void)
573	{
574	/*
575	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
576	* intercept all IO accesses, it's done once globally here instead of per-VM.
577	*/
578	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
579	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
580	if (RT_FAILURE(rc))
581	return rc;
582
583	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
584	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
585
586	/* Set all bits to intercept all IO accesses. */
587	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
588
589	return VINF_SUCCESS;
590	}
591
592
593	/**
594	* Does global AMD-V termination (called during module termination).
595	*/
596	VMMR0DECL(void) SVMR0GlobalTerm(void)
597	{
598	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
599	{
600	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
601	g_pvIOBitmap = NULL;
602	g_HCPhysIOBitmap = 0;
603	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
604	}
605	}
606
607
608	/**
609	* Frees any allocated per-VCPU structures for a VM.
610	*
611	* @param pVM The cross context VM structure.
612	*/
613	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
614	{
615	for (uint32_t i = 0; i < pVM->cCpus; i++)
616	{
617	PVMCPU pVCpu = &pVM->aCpus[i];
618	AssertPtr(pVCpu);
619
620	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
621	{
622	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
623	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
624	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
625	}
626
627	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
628	{
629	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
630	pVCpu->hm.s.svm.pVmcb = NULL;
631	pVCpu->hm.s.svm.HCPhysVmcb = 0;
632	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
633	}
634
635	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
636	{
637	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
638	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
639	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
640	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
641	}
642	}
643	}
644
645
646	/**
647	* Does per-VM AMD-V initialization.
648	*
649	* @returns VBox status code.
650	* @param pVM The cross context VM structure.
651	*/
652	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
653	{
654	int rc = VERR_INTERNAL_ERROR_5;
655
656	/*
657	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
658	*/
659	uint32_t u32Family;
660	uint32_t u32Model;
661	uint32_t u32Stepping;
662	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
663	{
664	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
665	pVM->hm.s.svm.fAlwaysFlushTLB = true;
666	}
667
668	/*
669	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
670	*/
671	for (VMCPUID i = 0; i < pVM->cCpus; i++)
672	{
673	PVMCPU pVCpu = &pVM->aCpus[i];
674	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
675	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
676	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
677	}
678
679	for (VMCPUID i = 0; i < pVM->cCpus; i++)
680	{
681	PVMCPU pVCpu = &pVM->aCpus[i];
682
683	/*
684	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
685	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
686	*/
687	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
688	if (RT_FAILURE(rc))
689	goto failure_cleanup;
690
691	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
692	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
693	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
694	ASMMemZeroPage(pvVmcbHost);
695
696	/*
697	* Allocate one page for the guest-state VMCB.
698	*/
699	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
700	if (RT_FAILURE(rc))
701	goto failure_cleanup;
702
703	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
704	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
705	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
706	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
707
708	/*
709	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
710	* SVM to not require one.
711	*/
712	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
713	false /* fExecutable */);
714	if (RT_FAILURE(rc))
715	goto failure_cleanup;
716
717	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
718	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
719	/* Set all bits to intercept all MSR accesses (changed later on). */
720	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
721	}
722
723	return VINF_SUCCESS;
724
725	failure_cleanup:
726	hmR0SvmFreeStructs(pVM);
727	return rc;
728	}
729
730
731	/**
732	* Does per-VM AMD-V termination.
733	*
734	* @returns VBox status code.
735	* @param pVM The cross context VM structure.
736	*/
737	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
738	{
739	hmR0SvmFreeStructs(pVM);
740	return VINF_SUCCESS;
741	}
742
743
744	/**
745	* Returns whether the VMCB Clean Bits feature is supported.
746	*
747	* @return @c true if supported, @c false otherwise.
748	* @param pVCpu The cross context virtual CPU structure.
749	* @param pCtx Pointer to the guest-CPU context.
750	*/
751	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu, PCPUMCTX pCtx)
752	{
753	PVM pVM = pVCpu->CTX_SUFF(pVM);
754	#ifdef VBOX_WITH_NESTED_HWVIRT
755	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
756	{
757	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
758	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
759	}
760	#else
761	RT_NOREF(pCtx);
762	#endif
763	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
764	}
765
766
767	/**
768	* Returns whether the decode assists feature is supported.
769	*
770	* @return @c true if supported, @c false otherwise.
771	* @param pVCpu The cross context virtual CPU structure.
772	* @param pCtx Pointer to the guest-CPU context.
773	*/
774	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu, PCPUMCTX pCtx)
775	{
776	PVM pVM = pVCpu->CTX_SUFF(pVM);
777	#ifdef VBOX_WITH_NESTED_HWVIRT
778	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
779	{
780	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
781	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
782	}
783	#else
784	RT_NOREF(pCtx);
785	#endif
786	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
787	}
788
789
790	/**
791	* Returns whether the NRIP_SAVE feature is supported.
792	*
793	* @return @c true if supported, @c false otherwise.
794	* @param pVCpu The cross context virtual CPU structure.
795	* @param pCtx Pointer to the guest-CPU context.
796	*/
797	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu, PCPUMCTX pCtx)
798	{
799	PVM pVM = pVCpu->CTX_SUFF(pVM);
800	#ifdef VBOX_WITH_NESTED_HWVIRT
801	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
802	{
803	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
804	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
805	}
806	#else
807	RT_NOREF(pCtx);
808	#endif
809	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
810	}
811
812
813	/**
814	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
815	*
816	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
817	* @param pbMsrBitmap Pointer to the MSR bitmap.
818	* @param idMsr The MSR for which the permissions are being set.
819	* @param enmRead MSR read permissions.
820	* @param enmWrite MSR write permissions.
821	*
822	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
823	* caller needs to take care of this.
824	*/
825	static void hmR0SvmSetMsrPermission(PCPUMCTX pCtx, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
826	SVMMSREXITWRITE enmWrite)
827	{
828	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
829	uint16_t offMsrpm;
830	uint8_t uMsrpmBit;
831	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
832	AssertRC(rc);
833
834	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
835	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
836
837	pbMsrBitmap += offMsrpm;
838	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
839	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
840	else
841	{
842	if (!fInNestedGuestMode)
843	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
844	#ifdef VBOX_WITH_NESTED_HWVIRT
845	else
846	{
847	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
848	uint8_t const pbNstGstMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
849	pbNstGstMsrBitmap += offMsrpm;
850	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
851	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
852	else
853	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
854	}
855	#endif
856	}
857
858	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
859	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
860	else
861	{
862	if (!fInNestedGuestMode)
863	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
864	#ifdef VBOX_WITH_NESTED_HWVIRT
865	else
866	{
867	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
868	uint8_t const pbNstGstMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
869	pbNstGstMsrBitmap += offMsrpm;
870	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
871	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
872	else
873	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
874	}
875	#endif
876	}
877	}
878
879
880	/**
881	* Sets up AMD-V for the specified VM.
882	* This function is only called once per-VM during initalization.
883	*
884	* @returns VBox status code.
885	* @param pVM The cross context VM structure.
886	*/
887	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
888	{
889	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
890	AssertReturn(pVM, VERR_INVALID_PARAMETER);
891	Assert(pVM->hm.s.svm.fSupported);
892
893	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
894	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
895	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
896
897	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
898	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
899
900	#ifdef VBOX_WITH_NESTED_HWVIRT
901	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
902	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
903
904	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
905	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
906	#endif
907
908	for (VMCPUID i = 0; i < pVM->cCpus; i++)
909	{
910	PVMCPU pVCpu = &pVM->aCpus[i];
911	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
912
913	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
914
915	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
916	Assert(!pVCpu->hm.s.idxExitHistoryFree);
917	HMCPU_EXIT_HISTORY_RESET(pVCpu);
918
919	/* Always trap #AC for reasons of security. */
920	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
921
922	/* Always trap #DB for reasons of security. */
923	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
924
925	/* Trap exceptions unconditionally (debug purposes). */
926	#ifdef HMSVM_ALWAYS_TRAP_PF
927	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
928	#endif
929	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
930	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
931	pVmcb->ctrl.u32InterceptXcpt \|= 0
932	\| RT_BIT(X86_XCPT_BP)
933	\| RT_BIT(X86_XCPT_DE)
934	\| RT_BIT(X86_XCPT_NM)
935	\| RT_BIT(X86_XCPT_UD)
936	\| RT_BIT(X86_XCPT_NP)
937	\| RT_BIT(X86_XCPT_SS)
938	\| RT_BIT(X86_XCPT_GP)
939	\| RT_BIT(X86_XCPT_PF)
940	\| RT_BIT(X86_XCPT_MF)
941	;
942	#endif
943
944	/* Set up unconditional intercepts and conditions. */
945	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
946	\| SVM_CTRL_INTERCEPT_VMMCALL;
947
948	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
949	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(4);
950
951	/* Intercept all DRx reads and writes by default. Changed later on. */
952	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
953	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
954
955	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
956	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
957
958	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
959	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
960	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
961
962	/* Set IO and MSR bitmap permission bitmap physical addresses. */
963	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
964	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
965
966	/* LBR virtualization. */
967	if (fUseLbrVirt)
968	{
969	pVmcb->ctrl.LbrVirt.n.u1LbrVirt = fUseLbrVirt;
970	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
971	}
972	else
973	Assert(pVmcb->ctrl.LbrVirt.n.u1LbrVirt == 0);
974
975	#ifdef VBOX_WITH_NESTED_HWVIRT
976	/* Virtualized VMSAVE/VMLOAD. */
977	pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
978	if (!fUseVirtVmsaveVmload)
979	{
980	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
981	\| SVM_CTRL_INTERCEPT_VMLOAD;
982	}
983
984	/* Virtual GIF. */
985	pVmcb->ctrl.IntCtrl.n.u1VGifEnable = fUseVGif;
986	if (!fUseVGif)
987	{
988	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
989	\| SVM_CTRL_INTERCEPT_STGI;
990	}
991	#endif
992
993	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
994	Assert(pVmcb->ctrl.u32VmcbCleanBits == 0);
995
996	/* The host ASID MBZ, for the guest start with 1. */
997	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
998
999	/*
1000	* Setup the PAT MSR (applicable for Nested Paging only).
1001	*
1002	* While guests can modify and see the modified values throug the shadow values,
1003	* we shall not honor any guest modifications of this MSR to ensure caching is always
1004	* enabled similar to how we always run with CR0.CD and NW bits cleared.
1005	*/
1006	pVmcb->guest.u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
1007
1008	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1009	pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1010
1011	/* Without Nested Paging, we need additionally intercepts. */
1012	if (!pVM->hm.s.fNestedPaging)
1013	{
1014	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1015	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1016	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1017
1018	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1019	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1020	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1021
1022	/* Page faults must be intercepted to implement shadow paging. */
1023	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1024	}
1025
1026	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1027	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1028	#endif
1029
1030	/* Apply the exceptions intercepts needed by the GIM provider. */
1031	if (pVCpu->hm.s.fGIMTrapXcptUD)
1032	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1033
1034	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1035	if (fUsePauseFilter)
1036	{
1037	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1038	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1039	if (fPauseFilterThreshold)
1040	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1041	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1042	}
1043
1044	/*
1045	* The following MSRs are saved/restored automatically during the world-switch.
1046	* Don't intercept guest read/write accesses to these MSRs.
1047	*/
1048	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1049	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1050	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1051	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1052	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1053	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1054	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1055	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1056	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1057	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1058	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1059	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1060	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
1061	}
1062
1063	return VINF_SUCCESS;
1064	}
1065
1066
1067	/**
1068	* Gets a pointer to the currently active guest or nested-guest VMCB.
1069	*
1070	* @returns Pointer to the current context VMCB.
1071	* @param pVCpu The cross context virtual CPU structure.
1072	* @param pCtx Pointer to the guest-CPU context.
1073	*/
1074	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
1075	{
1076	#ifdef VBOX_WITH_NESTED_HWVIRT
1077	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1078	return pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1079	#else
1080	RT_NOREF(pCtx);
1081	#endif
1082	return pVCpu->hm.s.svm.pVmcb;
1083	}
1084
1085
1086	/**
1087	* Gets a pointer to the nested-guest VMCB cache.
1088	*
1089	* @returns Pointer to the nested-guest VMCB cache.
1090	* @param pVCpu The cross context virtual CPU structure.
1091	* @param pCtx Pointer to the guest-CPU context.
1092	*/
1093	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPU pVCpu, PCPUMCTX pCtx)
1094	{
1095	#ifdef VBOX_WITH_NESTED_HWVIRT
1096	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); RT_NOREF(pCtx);
1097	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1098	#else
1099	RT_NOREF2(pVCpu, pCtx);
1100	return NULL;
1101	#endif
1102	}
1103
1104
1105	/**
1106	* Invalidates a guest page by guest virtual address.
1107	*
1108	* @returns VBox status code.
1109	* @param pVM The cross context VM structure.
1110	* @param pVCpu The cross context virtual CPU structure.
1111	* @param GCVirt Guest virtual address of the page to invalidate.
1112	*/
1113	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1114	{
1115	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1116	Assert(pVM->hm.s.svm.fSupported);
1117
1118	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1119
1120	/* Skip it if a TLB flush is already pending. */
1121	if (!fFlushPending)
1122	{
1123	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
1124
1125	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1126	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
1127	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1128
1129	#if HC_ARCH_BITS == 32
1130	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1131	if (CPUMIsGuestInLongMode(pVCpu))
1132	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1133	else
1134	#endif
1135	{
1136	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1137	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1138	}
1139	}
1140	return VINF_SUCCESS;
1141	}
1142
1143
1144	/**
1145	* Flushes the appropriate tagged-TLB entries.
1146	*
1147	* @param pVCpu The cross context virtual CPU structure.
1148	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
1149	* @param pVmcb Pointer to the VM control block.
1150	* @param pHostCpu Pointer to the HM host-CPU info.
1151	*/
1152	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, PHMGLOBALCPUINFO pHostCpu)
1153	{
1154	#ifndef VBOX_WITH_NESTED_HWVIRT
1155	RT_NOREF(pCtx);
1156	#endif
1157	PVM pVM = pVCpu->CTX_SUFF(pVM);
1158
1159	/*
1160	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1161	* This can happen both for start & resume due to long jumps back to ring-3.
1162	*
1163	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no correlation
1164	* between it and the physical CPU.
1165	*
1166	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1167	* so we cannot reuse the ASIDs without flushing.
1168	*/
1169	bool fNewAsid = false;
1170	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1171	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1172	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1173	#ifdef VBOX_WITH_NESTED_HWVIRT
1174	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1175	#endif
1176	)
1177	{
1178	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1179	pVCpu->hm.s.fForceTLBFlush = true;
1180	fNewAsid = true;
1181	}
1182
1183	/* Set TLB flush state as checked until we return from the world switch. */
1184	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1185
1186	/* Check for explicit TLB flushes. */
1187	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1188	{
1189	pVCpu->hm.s.fForceTLBFlush = true;
1190	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1191	}
1192
1193	/*
1194	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1195	* This Host CPU requirement takes precedence.
1196	*/
1197	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1198	{
1199	pHostCpu->uCurrentAsid = 1;
1200	pVCpu->hm.s.uCurrentAsid = 1;
1201	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1202	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1203	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1204
1205	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1206	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1207	}
1208	else
1209	{
1210	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1211	if (pVCpu->hm.s.fForceTLBFlush)
1212	{
1213	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1214	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1215
1216	if (fNewAsid)
1217	{
1218	++pHostCpu->uCurrentAsid;
1219
1220	bool fHitASIDLimit = false;
1221	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1222	{
1223	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1224	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1225	fHitASIDLimit = true;
1226	}
1227
1228	if ( fHitASIDLimit
1229	\|\| pHostCpu->fFlushAsidBeforeUse)
1230	{
1231	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1232	pHostCpu->fFlushAsidBeforeUse = false;
1233	}
1234
1235	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1236	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1237	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1238	}
1239	else
1240	{
1241	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1242	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1243	else
1244	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1245	}
1246
1247	pVCpu->hm.s.fForceTLBFlush = false;
1248	}
1249	}
1250
1251	/* Update VMCB with the ASID. */
1252	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1253	{
1254	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1255	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1256	}
1257
1258	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1259	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1260	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1261	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1262	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1263	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1264	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1265	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1266
1267	#ifdef VBOX_WITH_STATISTICS
1268	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1269	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1270	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1271	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1272	{
1273	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1274	}
1275	else
1276	{
1277	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1278	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1279	}
1280	#endif
1281	}
1282
1283
1284	/** @name 64-bit guest on 32-bit host OS helper functions.
1285	*
1286	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1287	* mode (code segment, paging). These wrappers/helpers perform the necessary
1288	* bits for the 32->64 switcher.
1289	*
1290	* @{ */
1291	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1292	/**
1293	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1294	*
1295	* @returns VBox status code.
1296	* @param HCPhysVmcbHost Physical address of host VMCB.
1297	* @param HCPhysVmcb Physical address of the VMCB.
1298	* @param pCtx Pointer to the guest-CPU context.
1299	* @param pVM The cross context VM structure.
1300	* @param pVCpu The cross context virtual CPU structure.
1301	*/
1302	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1303	{
1304	uint32_t aParam[8];
1305	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1306	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1307	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1308	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1309	aParam[4] = VM_RC_ADDR(pVM, pVM);
1310	aParam[5] = 0;
1311	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1312	aParam[7] = 0;
1313
1314	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1315	}
1316
1317
1318	/**
1319	* Executes the specified VMRUN handler in 64-bit mode.
1320	*
1321	* @returns VBox status code.
1322	* @param pVM The cross context VM structure.
1323	* @param pVCpu The cross context virtual CPU structure.
1324	* @param pCtx Pointer to the guest-CPU context.
1325	* @param enmOp The operation to perform.
1326	* @param cParams Number of parameters.
1327	* @param paParam Array of 32-bit parameters.
1328	*/
1329	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1330	uint32_t cParams, uint32_t *paParam)
1331	{
1332	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1333	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1334
1335	NOREF(pCtx);
1336
1337	/* Disable interrupts. */
1338	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1339
1340	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1341	RTCPUID idHostCpu = RTMpCpuId();
1342	CPUMR0SetLApic(pVCpu, idHostCpu);
1343	#endif
1344
1345	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1346	CPUMSetHyperEIP(pVCpu, enmOp);
1347	for (int i = (int)cParams - 1; i >= 0; i--)
1348	CPUMPushHyper(pVCpu, paParam[i]);
1349
1350	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1351	/* Call the switcher. */
1352	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1353	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1354
1355	/* Restore interrupts. */
1356	ASMSetFlags(uOldEFlags);
1357	return rc;
1358	}
1359
1360	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1361	/** @} */
1362
1363
1364	/**
1365	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1366	* the corresponding VMCB Clean bit.
1367	*
1368	* @param pVmcb Pointer to the VM control block.
1369	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1370	*/
1371	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1372	{
1373	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1374	{
1375	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1376	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1377	}
1378	}
1379
1380
1381	/**
1382	* Removes an exception from the intercept-exception bitmap in the VMCB and
1383	* updates the corresponding VMCB Clean bit.
1384	*
1385	* @param pVCpu The cross context virtual CPU structure.
1386	* @param pCtx Pointer to the guest-CPU context.
1387	* @param pVmcb Pointer to the VM control block.
1388	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1389	*
1390	* @remarks This takes into account if we're executing a nested-guest and only
1391	* removes the exception intercept if both the guest -and- nested-guest
1392	* are not intercepting it.
1393	*/
1394	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint32_t u32Xcpt)
1395	{
1396	Assert(u32Xcpt != X86_XCPT_DB);
1397	Assert(u32Xcpt != X86_XCPT_AC);
1398	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1399	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1400	{
1401	bool fRemoveXcpt = true;
1402	#ifdef VBOX_WITH_NESTED_HWVIRT
1403	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1404	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1405	{
1406	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
1407	fRemoveXcpt = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(u32Xcpt));
1408	}
1409	#else
1410	RT_NOREF2(pVCpu, pCtx);
1411	#endif
1412	if (fRemoveXcpt)
1413	{
1414	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1415	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1416	}
1417	}
1418	#else
1419	RT_NOREF3(pVCpu, pCtx, pVmcb);
1420	#endif
1421	}
1422
1423
1424	/**
1425	* Loads the guest (or nested-guest) CR0 control register into the guest-state
1426	* area in the VMCB.
1427	*
1428	* Although the guest CR0 is a separate field in the VMCB we have to consider
1429	* the FPU state itself which is shared between the host and the guest.
1430	*
1431	* @returns VBox status code.
1432	* @param pVCpu The cross context virtual CPU structure.
1433	* @param pVmcb Pointer to the VM control block.
1434	* @param pCtx Pointer to the guest-CPU context.
1435	*
1436	* @remarks No-long-jump zone!!!
1437	*/
1438	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1439	{
1440	/* The guest FPU is now always pre-loaded before executing guest code, see @bugref{7243#c101}. */
1441	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1442
1443	uint64_t const uGuestCr0 = pCtx->cr0;
1444	uint64_t uShadowCr0 = uGuestCr0;
1445
1446	/* Always enable caching. */
1447	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1448
1449	/* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()). */
1450	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1451	{
1452	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1453	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1454	}
1455
1456	/*
1457	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that lets us
1458	* isolate the host from it, IEM/REM still needs work to emulate it properly. see @bugref{7243#c103}.
1459	*/
1460	if (!(uGuestCr0 & X86_CR0_NE))
1461	{
1462	uShadowCr0 \|= X86_CR0_NE;
1463	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1464	}
1465	else
1466	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_MF);
1467
1468	/*
1469	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1470	*
1471	* CR0 writes still needs interception as PGM requires tracking paging mode changes, see @bugref{6944}.
1472	* We also don't ever want to honor weird things like cache disable from the guest. However, we can
1473	* avoid intercepting changes to the TS & MP bits by clearing the CR0 write intercept below and keeping
1474	* SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1475	*/
1476	if (uShadowCr0 == uGuestCr0)
1477	{
1478	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1479	{
1480	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1481	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1482	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1483	}
1484	else
1485	{
1486	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1487	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
1488	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1489	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1490	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1491	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1492	}
1493	}
1494	else
1495	{
1496	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1497	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1498	}
1499	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1500
1501	Assert(RT_HI_U32(uShadowCr0) == 0);
1502	if (pVmcb->guest.u64CR0 != uShadowCr0)
1503	{
1504	pVmcb->guest.u64CR0 = uShadowCr0;
1505	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1506	}
1507	}
1508
1509
1510	/**
1511	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1512	*
1513	* @returns VBox status code.
1514	* @param pVCpu The cross context virtual CPU structure.
1515	* @param pVmcb Pointer to the VM control block.
1516	* @param pCtx Pointer to the guest-CPU context.
1517	*
1518	* @remarks No-long-jump zone!!!
1519	*/
1520	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1521	{
1522	PVM pVM = pVCpu->CTX_SUFF(pVM);
1523
1524	/*
1525	* Guest CR2.
1526	*/
1527	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1528	{
1529	pVmcb->guest.u64CR2 = pCtx->cr2;
1530	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1531	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1532	}
1533
1534	/*
1535	* Guest CR3.
1536	*/
1537	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1538	{
1539	if (pVM->hm.s.fNestedPaging)
1540	{
1541	PGMMODE enmShwPagingMode;
1542	#if HC_ARCH_BITS == 32
1543	if (CPUMIsGuestInLongModeEx(pCtx))
1544	enmShwPagingMode = PGMMODE_AMD64_NX;
1545	else
1546	#endif
1547	enmShwPagingMode = PGMGetHostMode(pVM);
1548
1549	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1550	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1551	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1552	pVmcb->guest.u64CR3 = pCtx->cr3;
1553	}
1554	else
1555	{
1556	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1557	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1558	}
1559
1560	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1561	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1562	}
1563
1564	/*
1565	* Guest CR4.
1566	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1567	*/
1568	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1569	{
1570	uint64_t uShadowCr4 = pCtx->cr4;
1571	if (!pVM->hm.s.fNestedPaging)
1572	{
1573	switch (pVCpu->hm.s.enmShadowMode)
1574	{
1575	case PGMMODE_REAL:
1576	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1577	AssertFailed();
1578	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1579
1580	case PGMMODE_32_BIT: /* 32-bit paging. */
1581	uShadowCr4 &= ~X86_CR4_PAE;
1582	break;
1583
1584	case PGMMODE_PAE: /* PAE paging. */
1585	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1586	/** Must use PAE paging as we could use physical memory > 4 GB */
1587	uShadowCr4 \|= X86_CR4_PAE;
1588	break;
1589
1590	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1591	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1592	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1593	break;
1594	#else
1595	AssertFailed();
1596	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1597	#endif
1598
1599	default: /* shut up gcc */
1600	AssertFailed();
1601	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1602	}
1603	}
1604
1605	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1606	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1607
1608	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1609	if (uShadowCr4 == pCtx->cr4)
1610	{
1611	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1612	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1613	else
1614	{
1615	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1616	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
1617	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1618	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1619	}
1620	}
1621	else
1622	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1623
1624	/* CR4 writes are always intercepted (both guest, nested-guest) from tracking PGM mode changes. */
1625	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1626
1627	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1628	Assert(RT_HI_U32(uShadowCr4) == 0);
1629	pVmcb->guest.u64CR4 = uShadowCr4;
1630	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1631
1632	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1633	}
1634
1635	return VINF_SUCCESS;
1636	}
1637
1638
1639	/**
1640	* Loads the guest (or nested-guest) segment registers into the VMCB.
1641	*
1642	* @returns VBox status code.
1643	* @param pVCpu The cross context virtual CPU structure.
1644	* @param pVmcb Pointer to the VM control block.
1645	* @param pCtx Pointer to the guest-CPU context.
1646	*
1647	* @remarks No-long-jump zone!!!
1648	*/
1649	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1650	{
1651	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1652	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1653	{
1654	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1655	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1656	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1657	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1658	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1659	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1660
1661	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1662	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1663	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1664	}
1665
1666	/* Guest TR. */
1667	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1668	{
1669	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1670	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1671	}
1672
1673	/* Guest LDTR. */
1674	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1675	{
1676	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1677	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1678	}
1679
1680	/* Guest GDTR. */
1681	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1682	{
1683	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1684	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1685	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1686	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1687	}
1688
1689	/* Guest IDTR. */
1690	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1691	{
1692	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1693	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1694	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1695	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1696	}
1697	}
1698
1699
1700	/**
1701	* Loads the guest (or nested-guest) MSRs into the VMCB.
1702	*
1703	* @param pVCpu The cross context virtual CPU structure.
1704	* @param pVmcb Pointer to the VM control block.
1705	* @param pCtx Pointer to the guest-CPU context.
1706	*
1707	* @remarks No-long-jump zone!!!
1708	*/
1709	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1710	{
1711	/* Guest Sysenter MSRs. */
1712	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1713	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1714	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1715
1716	/*
1717	* Guest EFER MSR.
1718	* AMD-V requires guest EFER.SVME to be set. Weird.
1719	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1720	*/
1721	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1722	{
1723	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1724	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1725	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1726	}
1727
1728	/* 64-bit MSRs. */
1729	if (CPUMIsGuestInLongModeEx(pCtx))
1730	{
1731	/* Load these always as the guest may modify FS/GS base using MSRs in 64-bit mode which we don't intercept. */
1732	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1733	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1734	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1735	}
1736	else
1737	{
1738	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1739	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1740	{
1741	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1742	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1743	}
1744	}
1745
1746	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1747	* be writable in 32-bit mode. Clarify with AMD spec. */
1748	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1749	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1750	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1751	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1752	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1753
1754	/* We don't honor guest modifications to its PAT MSR (similar to ignoring CR0.CD, NW bits). */
1755	}
1756
1757
1758	/**
1759	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1760	* necessary intercepts accordingly.
1761	*
1762	* @param pVCpu The cross context virtual CPU structure.
1763	* @param pVmcb Pointer to the VM control block.
1764	* @param pCtx Pointer to the guest-CPU context.
1765	*
1766	* @remarks No-long-jump zone!!!
1767	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1768	*/
1769	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1770	{
1771	bool fInterceptMovDRx = false;
1772
1773	/*
1774	* Anyone single stepping on the host side? If so, we'll have to use the
1775	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1776	* the VMM level like the VT-x implementations does.
1777	*/
1778	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1779	if (fStepping)
1780	{
1781	pVCpu->hm.s.fClearTrapFlag = true;
1782	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1783	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1784	}
1785
1786	if ( fStepping
1787	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1788	{
1789	/*
1790	* Use the combined guest and host DRx values found in the hypervisor
1791	* register set because the debugger has breakpoints active or someone
1792	* is single stepping on the host side.
1793	*
1794	* Note! DBGF expects a clean DR6 state before executing guest code.
1795	*/
1796	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1797	if ( CPUMIsGuestInLongModeEx(pCtx)
1798	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1799	{
1800	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1801	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1802	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1803	}
1804	else
1805	#endif
1806	if (!CPUMIsHyperDebugStateActive(pVCpu))
1807	{
1808	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1809	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1810	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1811	}
1812
1813	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1814	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1815	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1816	{
1817	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1818	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1819	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1820	pVCpu->hm.s.fUsingHyperDR7 = true;
1821	}
1822
1823	/** @todo If we cared, we could optimize to allow the guest to read registers
1824	* with the same values. */
1825	fInterceptMovDRx = true;
1826	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1827	}
1828	else
1829	{
1830	/*
1831	* Update DR6, DR7 with the guest values if necessary.
1832	*/
1833	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1834	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1835	{
1836	pVmcb->guest.u64DR7 = pCtx->dr[7];
1837	pVmcb->guest.u64DR6 = pCtx->dr[6];
1838	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1839	pVCpu->hm.s.fUsingHyperDR7 = false;
1840	}
1841
1842	/*
1843	* If the guest has enabled debug registers, we need to load them prior to
1844	* executing guest code so they'll trigger at the right time.
1845	*/
1846	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1847	{
1848	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1849	if ( CPUMIsGuestInLongModeEx(pCtx)
1850	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1851	{
1852	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1853	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1854	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1855	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1856	}
1857	else
1858	#endif
1859	if (!CPUMIsGuestDebugStateActive(pVCpu))
1860	{
1861	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1862	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1863	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1864	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1865	}
1866	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1867	}
1868	/*
1869	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1870	* intercept #DB as DR6 is updated in the VMCB.
1871	*
1872	* Note! If we cared and dared, we could skip intercepting \#DB here.
1873	* However, \#DB shouldn't be performance critical, so we'll play safe
1874	* and keep the code similar to the VT-x code and always intercept it.
1875	*/
1876	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1877	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1878	&& !CPUMIsGuestDebugStateActive(pVCpu))
1879	#else
1880	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1881	#endif
1882	{
1883	fInterceptMovDRx = true;
1884	}
1885	}
1886
1887	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1888	if (fInterceptMovDRx)
1889	{
1890	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1891	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1892	{
1893	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1894	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1895	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1896	}
1897	}
1898	else
1899	{
1900	if ( pVmcb->ctrl.u16InterceptRdDRx
1901	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1902	{
1903	pVmcb->ctrl.u16InterceptRdDRx = 0;
1904	pVmcb->ctrl.u16InterceptWrDRx = 0;
1905	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1906	}
1907	}
1908	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1909	}
1910
1911
1912	#ifdef VBOX_WITH_NESTED_HWVIRT
1913	/**
1914	* Loads the nested-guest APIC state (currently just the TPR).
1915	*
1916	* @param pVCpu The cross context virtual CPU structure.
1917	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1918	*/
1919	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1920	{
1921	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1922	{
1923	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1924	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1925	pVCpu->hm.s.svm.fSyncVTpr = false;
1926	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1927
1928	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1929	}
1930	}
1931	#endif
1932
1933	/**
1934	* Loads the guest APIC state (currently just the TPR).
1935	*
1936	* @returns VBox status code.
1937	* @param pVCpu The cross context virtual CPU structure.
1938	* @param pVmcb Pointer to the VM control block.
1939	* @param pCtx Pointer to the guest-CPU context.
1940	*/
1941	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1942	{
1943	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1944	return VINF_SUCCESS;
1945
1946	int rc = VINF_SUCCESS;
1947	PVM pVM = pVCpu->CTX_SUFF(pVM);
1948	if ( PDMHasApic(pVM)
1949	&& APICIsEnabled(pVCpu))
1950	{
1951	bool fPendingIntr;
1952	uint8_t u8Tpr;
1953	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1954	AssertRCReturn(rc, rc);
1955
1956	/* Assume that we need to trap all TPR accesses and thus need not check on
1957	every #VMEXIT if we should update the TPR. */
1958	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1959	pVCpu->hm.s.svm.fSyncVTpr = false;
1960
1961	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1962	if (pVM->hm.s.fTPRPatchingActive)
1963	{
1964	pCtx->msrLSTAR = u8Tpr;
1965	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1966
1967	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1968	if (fPendingIntr)
1969	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1970	else
1971	{
1972	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1973	pVCpu->hm.s.svm.fSyncVTpr = true;
1974	}
1975	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
1976	}
1977	else
1978	{
1979	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1980	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1981
1982	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1983	if (fPendingIntr)
1984	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1985	else
1986	{
1987	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1988	pVCpu->hm.s.svm.fSyncVTpr = true;
1989	}
1990
1991	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1992	}
1993	}
1994
1995	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1996	return rc;
1997	}
1998
1999
2000	/**
2001	* Loads the exception interrupts required for guest (or nested-guest) execution in
2002	* the VMCB.
2003	*
2004	* @param pVCpu The cross context virtual CPU structure.
2005	* @param pVmcb Pointer to the VM control block.
2006	* @param pCtx Pointer to the guest-CPU context.
2007	*/
2008	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2009	{
2010	/* If we modify intercepts from here, please check & adjust hmR0SvmLoadGuestXcptInterceptsNested()
2011	if required. */
2012	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
2013	{
2014	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2015	if (pVCpu->hm.s.fGIMTrapXcptUD)
2016	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
2017	else
2018	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_UD);
2019
2020	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2021	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2022	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
2023	else
2024	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_BP);
2025
2026	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
2027	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
2028	}
2029	}
2030
2031
2032	#ifdef VBOX_WITH_NESTED_HWVIRT
2033	/**
2034	* Loads the intercepts required for nested-guest execution in the VMCB.
2035	*
2036	* This merges the guest and nested-guest intercepts in a way that if the outer
2037	* guest intercepts an exception we need to intercept it in the nested-guest as
2038	* well and handle it accordingly.
2039	*
2040	* @param pVCpu The cross context virtual CPU structure.
2041	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2042	* @param pCtx Pointer to the guest-CPU context.
2043	*/
2044	static void hmR0SvmLoadGuestInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
2045	{
2046	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
2047	{
2048	PVM pVM = pVCpu->CTX_SUFF(pVM);
2049	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2050	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2051
2052	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2053	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2054	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2055
2056	/* Always intercept CR4 writes for tracking PGM mode changes. */
2057	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2058
2059	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2060	if (!pVM->hm.s.fNestedPaging)
2061	{
2062	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2063	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2064	}
2065
2066	/** @todo Figure out debugging with nested-guests, till then just intercept
2067	* all DR[0-15] accesses. */
2068	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2069	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2070
2071	/*
2072	* Merge the guest's exception intercepts into the nested-guest VMCB.
2073	*
2074	* - \#UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2075	* while executing the nested-guest.
2076	*
2077	* - \#BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2078	* be tweaked later depending on how we wish to implement breakpoints.
2079	*
2080	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2081	* for VM debugger breakpoints, see hmR0SvmLoadGuestXcptIntercepts.
2082	*/
2083	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2084	pVmcbNstGstCtrl->u32InterceptXcpt \|= (pVmcb->ctrl.u32InterceptXcpt & ~( RT_BIT(X86_XCPT_UD)
2085	\| RT_BIT(X86_XCPT_BP)));
2086	#else
2087	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2088	#endif
2089
2090	/*
2091	* Adjust intercepts while executing the nested-guest that differ from the
2092	* outer guest intercepts.
2093	*
2094	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2095	* that belong to the nested-guest to the outer guest.
2096	*
2097	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2098	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2099	*/
2100	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2101	\| SVM_CTRL_INTERCEPT_VMMCALL))
2102	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2103
2104	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2105	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2106
2107	/*
2108	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2109	* since SVM doesn't have a preemption timer.
2110	*
2111	* We do this here rather than in hmR0SvmVmRunSetupVmcb() as we may have been executing the
2112	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters.
2113	*/
2114	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
2115	{
2116	pVmcbNstGstCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, pVmcb->ctrl.u16PauseFilterCount);
2117	pVmcbNstGstCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold,
2118	pVmcb->ctrl.u16PauseFilterThreshold);
2119	}
2120	else
2121	{
2122	pVmcbNstGstCtrl->u16PauseFilterCount = pVmcb->ctrl.u16PauseFilterCount;
2123	pVmcbNstGstCtrl->u16PauseFilterThreshold = pVmcb->ctrl.u16PauseFilterThreshold;
2124	}
2125
2126	/** @todo This doesn't make sense. Re-think and remove. */
2127	#if 1
2128	/*
2129	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2130	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2131	*/
2132	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2133	{
2134	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2135	\| SVM_CTRL_INTERCEPT_VMLOAD;
2136	}
2137
2138	/*
2139	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2140	* CLGI/STGI instructions executed by the nested-guest.
2141	*/
2142	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2143	{
2144	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2145	\| SVM_CTRL_INTERCEPT_STGI;
2146	}
2147	#endif
2148
2149	/* Finally, update the VMCB clean bits. */
2150	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2151	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
2152	}
2153	}
2154	#endif
2155
2156
2157	/**
2158	* Sets up the appropriate function to run guest code.
2159	*
2160	* @returns VBox status code.
2161	* @param pVCpu The cross context virtual CPU structure.
2162	*
2163	* @remarks No-long-jump zone!!!
2164	*/
2165	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
2166	{
2167	if (CPUMIsGuestInLongMode(pVCpu))
2168	{
2169	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2170	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2171	#endif
2172	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2173	#if HC_ARCH_BITS == 32
2174	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2175	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2176	#else
2177	/* 64-bit host or hybrid host. */
2178	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2179	#endif
2180	}
2181	else
2182	{
2183	/* Guest is not in long mode, use the 32-bit handler. */
2184	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2185	}
2186	return VINF_SUCCESS;
2187	}
2188
2189
2190	/**
2191	* Enters the AMD-V session.
2192	*
2193	* @returns VBox status code.
2194	* @param pVM The cross context VM structure.
2195	* @param pVCpu The cross context virtual CPU structure.
2196	* @param pCpu Pointer to the CPU info struct.
2197	*/
2198	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2199	{
2200	AssertPtr(pVM);
2201	AssertPtr(pVCpu);
2202	Assert(pVM->hm.s.svm.fSupported);
2203	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2204	NOREF(pVM); NOREF(pCpu);
2205
2206	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2207	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2208
2209	pVCpu->hm.s.fLeaveDone = false;
2210	return VINF_SUCCESS;
2211	}
2212
2213
2214	/**
2215	* Thread-context callback for AMD-V.
2216	*
2217	* @param enmEvent The thread-context event.
2218	* @param pVCpu The cross context virtual CPU structure.
2219	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2220	* @thread EMT(pVCpu)
2221	*/
2222	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2223	{
2224	NOREF(fGlobalInit);
2225
2226	switch (enmEvent)
2227	{
2228	case RTTHREADCTXEVENT_OUT:
2229	{
2230	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2231	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2232	VMCPU_ASSERT_EMT(pVCpu);
2233
2234	/* No longjmps (log-flush, locks) in this fragile context. */
2235	VMMRZCallRing3Disable(pVCpu);
2236
2237	if (!pVCpu->hm.s.fLeaveDone)
2238	{
2239	hmR0SvmLeave(pVCpu);
2240	pVCpu->hm.s.fLeaveDone = true;
2241	}
2242
2243	/* Leave HM context, takes care of local init (term). */
2244	int rc = HMR0LeaveCpu(pVCpu);
2245	AssertRC(rc); NOREF(rc);
2246
2247	/* Restore longjmp state. */
2248	VMMRZCallRing3Enable(pVCpu);
2249	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2250	break;
2251	}
2252
2253	case RTTHREADCTXEVENT_IN:
2254	{
2255	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2256	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2257	VMCPU_ASSERT_EMT(pVCpu);
2258
2259	/* No longjmps (log-flush, locks) in this fragile context. */
2260	VMMRZCallRing3Disable(pVCpu);
2261
2262	/*
2263	* Initialize the bare minimum state required for HM. This takes care of
2264	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2265	*/
2266	int rc = HMR0EnterCpu(pVCpu);
2267	AssertRC(rc); NOREF(rc);
2268	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2269
2270	pVCpu->hm.s.fLeaveDone = false;
2271
2272	/* Restore longjmp state. */
2273	VMMRZCallRing3Enable(pVCpu);
2274	break;
2275	}
2276
2277	default:
2278	break;
2279	}
2280	}
2281
2282
2283	/**
2284	* Saves the host state.
2285	*
2286	* @returns VBox status code.
2287	* @param pVM The cross context VM structure.
2288	* @param pVCpu The cross context virtual CPU structure.
2289	*
2290	* @remarks No-long-jump zone!!!
2291	*/
2292	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
2293	{
2294	NOREF(pVM);
2295	NOREF(pVCpu);
2296	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2297	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
2298	return VINF_SUCCESS;
2299	}
2300
2301
2302	/**
2303	* Loads the guest state into the VMCB.
2304	*
2305	* The CPU state will be loaded from these fields on every successful VM-entry.
2306	* Also sets up the appropriate VMRUN function to execute guest code based on
2307	* the guest CPU mode.
2308	*
2309	* @returns VBox status code.
2310	* @param pVM The cross context VM structure.
2311	* @param pVCpu The cross context virtual CPU structure.
2312	* @param pCtx Pointer to the guest-CPU context.
2313	*
2314	* @remarks No-long-jump zone!!!
2315	*/
2316	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2317	{
2318	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2319
2320	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2321	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2322
2323	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2324
2325	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
2326	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2327
2328	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
2329	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
2330
2331	pVmcb->guest.u64RIP = pCtx->rip;
2332	pVmcb->guest.u64RSP = pCtx->rsp;
2333	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2334	pVmcb->guest.u64RAX = pCtx->rax;
2335
2336	#ifdef VBOX_WITH_NESTED_HWVIRT
2337	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1)
2338	{
2339	Assert(pVM->hm.s.svm.fVGif);
2340	pVmcb->ctrl.IntCtrl.n.u1VGif = pCtx->hwvirt.fGif;
2341	}
2342	#endif
2343
2344	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
2345	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2346
2347	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
2348
2349	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2350	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2351
2352	/* Clear any unused and reserved bits. */
2353	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2354	\| HM_CHANGED_GUEST_RSP
2355	\| HM_CHANGED_GUEST_RFLAGS
2356	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2357	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2358	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2359	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2360	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2361	\| HM_CHANGED_SVM_RESERVED2
2362	\| HM_CHANGED_SVM_RESERVED3
2363	\| HM_CHANGED_SVM_RESERVED4);
2364
2365	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2366	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2367	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2368	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2369
2370	#ifdef VBOX_STRICT
2371	hmR0SvmLogState(pVCpu, pVmcb, pCtx, "hmR0SvmLoadGuestState", 0 /* fFlags /, 0 / uVerbose */);
2372	#endif
2373	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2374	return rc;
2375	}
2376
2377
2378	#ifdef VBOX_WITH_NESTED_HWVIRT
2379	/**
2380	* Merges the guest and nested-guest MSR permission bitmap.
2381	*
2382	* If the guest is intercepting an MSR we need to intercept it regardless of
2383	* whether the nested-guest is intercepting it or not.
2384	*
2385	* @param pHostCpu Pointer to the physical CPU HM info. struct.
2386	* @param pVCpu The cross context virtual CPU structure.
2387	* @param pCtx Pointer to the nested-guest-CPU context.
2388	*/
2389	static void hmR0SvmMergeMsrpm(PHMGLOBALCPUINFO pHostCpu, PVMCPU pVCpu, PCPUMCTX pCtx)
2390	{
2391	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2392	uint64_t const pu64NstGstMsrpm = (uint64_t const )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2393	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2394
2395	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2396	uint32_t const offRsvdQwords = 0x1800 >> 3;
2397	for (uint32_t i = 0; i < offRsvdQwords; i++)
2398	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2399	}
2400
2401
2402	/**
2403	* Caches the nested-guest VMCB fields before we modify them for execution using
2404	* hardware-assisted SVM.
2405	*
2406	* @returns true if the VMCB was previously already cached, false otherwise.
2407	* @param pCtx Pointer to the guest-CPU context.
2408	*
2409	* @sa HMSvmNstGstVmExitNotify.
2410	*/
2411	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2412	{
2413	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2414	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2415	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2416	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2417
2418	/*
2419	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2420	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2421	*
2422	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2423	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2424	*/
2425	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2426	if (!fWasCached)
2427	{
2428	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2429	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2430	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2431	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2432	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2433	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2434	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2435	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2436	pVmcbNstGstCache->u64CR0 = pVmcbNstGstState->u64CR0;
2437	pVmcbNstGstCache->u64CR3 = pVmcbNstGstState->u64CR3;
2438	pVmcbNstGstCache->u64CR4 = pVmcbNstGstState->u64CR4;
2439	pVmcbNstGstCache->u64EFER = pVmcbNstGstState->u64EFER;
2440	pVmcbNstGstCache->u64PAT = pVmcbNstGstState->u64PAT;
2441	pVmcbNstGstCache->u64DBGCTL = pVmcbNstGstState->u64DBGCTL;
2442	pVmcbNstGstCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2443	pVmcbNstGstCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2444	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2445	pVmcbNstGstCache->u32VmcbCleanBits = pVmcbNstGstCtrl->u32VmcbCleanBits;
2446	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2447	pVmcbNstGstCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2448	pVmcbNstGstCache->u1NestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2449	pVmcbNstGstCache->u1LbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2450	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2451	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2452	}
2453
2454	return fWasCached;
2455	}
2456
2457
2458	/**
2459	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2460	*
2461	* @param pVCpu The cross context virtual CPU structure.
2462	* @param pCtx Pointer to the guest-CPU context.
2463	*/
2464	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2465	{
2466	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2467	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2468
2469	/*
2470	* First cache the nested-guest VMCB fields we may potentially modify.
2471	*/
2472	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2473	if (!fVmcbCached)
2474	{
2475	/*
2476	* The IOPM of the nested-guest can be ignored because the the guest always
2477	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2478	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2479	*/
2480	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2481
2482	/*
2483	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2484	* nested-paging suddenly while executing a VM (see assertion at the end of
2485	* Trap0eHandler() in PGMAllBth.h).
2486	*/
2487	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2488
2489	/* Override nested-guest PAT MSR, see @bugref{7243#c109}. */
2490	PSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2491	pVmcbNstGstState->u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
2492
2493	#ifdef DEBUG_ramshankar
2494	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2495	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2496	pVmcbNstGstState->u64DBGCTL = pVmcb->guest.u64DBGCTL;
2497	#endif
2498	}
2499	else
2500	{
2501	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2502	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2503	}
2504	}
2505
2506
2507	/**
2508	* Loads the nested-guest state into the VMCB.
2509	*
2510	* @returns VBox status code.
2511	* @param pVCpu The cross context virtual CPU structure.
2512	* @param pCtx Pointer to the guest-CPU context.
2513	*
2514	* @remarks No-long-jump zone!!!
2515	*/
2516	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2517	{
2518	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2519
2520	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2521	Assert(pVmcbNstGst);
2522
2523	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2524
2525	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
2526	AssertRCReturn(rc, rc);
2527
2528	/*
2529	* We need to load the entire state (including FS, GS etc.) as we could be continuing
2530	* to execute the nested-guest at any point (not just immediately after VMRUN) and thus
2531	* the VMCB can possibly be out-of-sync with the actual nested-guest state if it was
2532	* executed in IEM.
2533	*/
2534	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2535	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2536	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2537
2538	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2539	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2540	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2541	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2542
2543	#ifdef VBOX_WITH_NESTED_HWVIRT
2544	Assert(pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable == 0); /* Nested VGIF not supported yet. */
2545	#endif
2546
2547	hmR0SvmLoadGuestInterceptsNested(pVCpu, pVmcbNstGst, pCtx);
2548
2549	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2550	AssertRCReturn(rc, rc);
2551
2552	/* Clear any unused and reserved bits. */
2553	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2554	\| HM_CHANGED_GUEST_RSP
2555	\| HM_CHANGED_GUEST_RFLAGS
2556	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2557	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2558	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2559	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2560	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2561	\| HM_CHANGED_SVM_RESERVED2
2562	\| HM_CHANGED_SVM_RESERVED3
2563	\| HM_CHANGED_SVM_RESERVED4);
2564
2565	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2566	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2567	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2568	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2569
2570	#ifdef VBOX_STRICT
2571	hmR0SvmLogState(pVCpu, pVmcbNstGst, pCtx, "hmR0SvmLoadGuestStateNested", HMSVM_LOG_ALL, 0 /* uVerbose */);
2572	#endif
2573	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2574	return rc;
2575	}
2576	#endif /* VBOX_WITH_NESTED_HWVIRT */
2577
2578
2579	/**
2580	* Loads the state shared between the host and guest or nested-guest into the
2581	* VMCB.
2582	*
2583	* @param pVCpu The cross context virtual CPU structure.
2584	* @param pVmcb Pointer to the VM control block.
2585	* @param pCtx Pointer to the guest-CPU context.
2586	*
2587	* @remarks No-long-jump zone!!!
2588	*/
2589	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2590	{
2591	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2592	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2593
2594	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2595	{
2596	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2597	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2598	}
2599
2600	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2601	{
2602	/** @todo Figure out stepping with nested-guest. */
2603	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2604	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2605	else
2606	{
2607	pVmcb->guest.u64DR6 = pCtx->dr[6];
2608	pVmcb->guest.u64DR7 = pCtx->dr[7];
2609	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2610	}
2611
2612	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2613	}
2614
2615	/* Unused on AMD-V. */
2616	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2617
2618	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2619	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2620	}
2621
2622
2623	/**
2624	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2625	* context.
2626	*
2627	* Currently there is no residual state left in the CPU that is not updated in the
2628	* VMCB.
2629	*
2630	* @returns VBox status code.
2631	* @param pVCpu The cross context virtual CPU structure.
2632	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2633	* out-of-sync. Make sure to update the required fields
2634	* before using them.
2635	* @param pVmcb Pointer to the VM control block.
2636	*/
2637	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2638	{
2639	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2640
2641	pMixedCtx->rip = pVmcb->guest.u64RIP;
2642	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2643	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2644	pMixedCtx->rax = pVmcb->guest.u64RAX;
2645
2646	#ifdef VBOX_WITH_NESTED_HWVIRT
2647	/*
2648	* Guest Virtual GIF (Global Interrupt Flag).
2649	*/
2650	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1)
2651	{
2652	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fVGif);
2653	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx));
2654	pMixedCtx->hwvirt.fGif = pVmcb->ctrl.IntCtrl.n.u1VGif;
2655	}
2656	#endif
2657
2658	/*
2659	* Guest interrupt shadow.
2660	*/
2661	if (pVmcb->ctrl.IntShadow.n.u1IntShadow)
2662	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2663	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2664	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2665
2666	/*
2667	* Guest Control registers: CR0, CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2668	*/
2669	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2670
2671	/* If we're not intercepting changes to CR0 TS & MP bits, sync those bits here. */
2672	if (!(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(0)))
2673	{
2674	pMixedCtx->cr0 = (pMixedCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2675	\| (pVmcb->guest.u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2676	}
2677
2678	/*
2679	* Guest MSRs.
2680	*/
2681	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2682	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2683	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2684	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2685	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2686	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2687	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2688	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2689
2690	/*
2691	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2692	*/
2693	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2694	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2695	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2696	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2697	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2698	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2699
2700	/*
2701	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2702	* register (yet).
2703	*/
2704	/** @todo SELM might need to be fixed as it too should not care about the
2705	* granularity bit. See @bugref{6785}. */
2706	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2707	&& pMixedCtx->cs.Attr.n.u1Present
2708	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2709	{
2710	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2711	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2712	}
2713
2714	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2715	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2716	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2717	HMSVM_ASSERT_SEG_GRANULARITY(es);
2718	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2719	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2720
2721	/*
2722	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2723	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2724	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2725	* See AMD spec. 15.5.1 "Basic operation".
2726	*/
2727	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2728	uint8_t const uCpl = pVmcb->guest.u8CPL;
2729	if (pMixedCtx->ss.Attr.n.u2Dpl != uCpl)
2730	{
2731	Log4(("hmR0SvmSaveGuestState: CPL differs. SS.DPL=%u, CPL=%u, overwriting SS.DPL!\n", pMixedCtx->ss.Attr.n.u2Dpl, uCpl));
2732	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2733	}
2734
2735	/*
2736	* Guest TR.
2737	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2738	* between Intel and AMD. See @bugref{6208#c39}.
2739	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2740	*/
2741	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2742	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2743	{
2744	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2745	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2746	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2747	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2748	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2749	}
2750
2751	/*
2752	* Guest Descriptor-Table registers (GDTR, IDTR, LDTR).
2753	*/
2754	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2755	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2756	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2757
2758	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2759	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2760
2761	/*
2762	* Guest Debug registers.
2763	*/
2764	if (!pVCpu->hm.s.fUsingHyperDR7)
2765	{
2766	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2767	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2768	}
2769	else
2770	{
2771	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2772	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2773	}
2774
2775	/*
2776	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2777	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2778	*/
2779	if ( pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging
2780	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2781	{
2782	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2783	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2784	}
2785
2786	#ifdef VBOX_STRICT
2787	if (CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2788	hmR0SvmLogState(pVCpu, pVmcb, pMixedCtx, "hmR0SvmSaveGuestStateNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR, 0 /* uVerbose */);
2789	#endif
2790	}
2791
2792
2793	/**
2794	* Does the necessary state syncing before returning to ring-3 for any reason
2795	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2796	*
2797	* @param pVCpu The cross context virtual CPU structure.
2798	*
2799	* @remarks No-long-jmp zone!!!
2800	*/
2801	static void hmR0SvmLeave(PVMCPU pVCpu)
2802	{
2803	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2804	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2805	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2806
2807	/*
2808	* !!! IMPORTANT !!!
2809	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2810	*/
2811
2812	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2813	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2814	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); /** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2815
2816	/*
2817	* Restore host debug registers if necessary and resync on next R0 reentry.
2818	*/
2819	#ifdef VBOX_STRICT
2820	if (CPUMIsHyperDebugStateActive(pVCpu))
2821	{
2822	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2823	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2824	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2825	}
2826	#endif
2827	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2828	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);/** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2829
2830	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2831	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2832
2833	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2834	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2835	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2836	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2837	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2838
2839	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2840	}
2841
2842
2843	/**
2844	* Leaves the AMD-V session.
2845	*
2846	* @returns VBox status code.
2847	* @param pVCpu The cross context virtual CPU structure.
2848	*/
2849	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2850	{
2851	HM_DISABLE_PREEMPT();
2852	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2853	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2854
2855	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2856	and done this from the SVMR0ThreadCtxCallback(). */
2857	if (!pVCpu->hm.s.fLeaveDone)
2858	{
2859	hmR0SvmLeave(pVCpu);
2860	pVCpu->hm.s.fLeaveDone = true;
2861	}
2862
2863	/*
2864	* !!! IMPORTANT !!!
2865	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2866	*/
2867
2868	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2869	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2870	VMMR0ThreadCtxHookDisable(pVCpu);
2871
2872	/* Leave HM context. This takes care of local init (term). */
2873	int rc = HMR0LeaveCpu(pVCpu);
2874
2875	HM_RESTORE_PREEMPT();
2876	return rc;
2877	}
2878
2879
2880	/**
2881	* Does the necessary state syncing before doing a longjmp to ring-3.
2882	*
2883	* @returns VBox status code.
2884	* @param pVCpu The cross context virtual CPU structure.
2885	*
2886	* @remarks No-long-jmp zone!!!
2887	*/
2888	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2889	{
2890	return hmR0SvmLeaveSession(pVCpu);
2891	}
2892
2893
2894	/**
2895	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2896	* any remaining host state) before we longjump to ring-3 and possibly get
2897	* preempted.
2898	*
2899	* @param pVCpu The cross context virtual CPU structure.
2900	* @param enmOperation The operation causing the ring-3 longjump.
2901	* @param pvUser The user argument (pointer to the possibly
2902	* out-of-date guest-CPU context).
2903	*/
2904	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2905	{
2906	RT_NOREF_PV(pvUser);
2907
2908	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2909	{
2910	/*
2911	* !!! IMPORTANT !!!
2912	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2913	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2914	*/
2915	VMMRZCallRing3RemoveNotification(pVCpu);
2916	VMMRZCallRing3Disable(pVCpu);
2917	HM_DISABLE_PREEMPT();
2918
2919	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2920	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2921
2922	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2923	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2924
2925	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2926	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2927	VMMR0ThreadCtxHookDisable(pVCpu);
2928
2929	/* Leave HM context. This takes care of local init (term). */
2930	HMR0LeaveCpu(pVCpu);
2931
2932	HM_RESTORE_PREEMPT();
2933	return VINF_SUCCESS;
2934	}
2935
2936	Assert(pVCpu);
2937	Assert(pvUser);
2938	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2939	HMSVM_ASSERT_PREEMPT_SAFE();
2940
2941	VMMRZCallRing3Disable(pVCpu);
2942	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2943
2944	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2945	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2946	AssertRCReturn(rc, rc);
2947
2948	VMMRZCallRing3Enable(pVCpu);
2949	return VINF_SUCCESS;
2950	}
2951
2952
2953	/**
2954	* Take necessary actions before going back to ring-3.
2955	*
2956	* An action requires us to go back to ring-3. This function does the necessary
2957	* steps before we can safely return to ring-3. This is not the same as longjmps
2958	* to ring-3, this is voluntary.
2959	*
2960	* @returns VBox status code.
2961	* @param pVM The cross context VM structure.
2962	* @param pVCpu The cross context virtual CPU structure.
2963	* @param pCtx Pointer to the guest-CPU context.
2964	* @param rcExit The reason for exiting to ring-3. Can be
2965	* VINF_VMM_UNKNOWN_RING3_CALL.
2966	*/
2967	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2968	{
2969	Assert(pVM);
2970	Assert(pVCpu);
2971	Assert(pCtx);
2972	HMSVM_ASSERT_PREEMPT_SAFE();
2973
2974	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2975	VMMRZCallRing3Disable(pVCpu);
2976	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
2977	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
2978
2979	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2980	if (pVCpu->hm.s.Event.fPending)
2981	{
2982	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2983	Assert(!pVCpu->hm.s.Event.fPending);
2984	}
2985
2986	/* Sync. the necessary state for going back to ring-3. */
2987	hmR0SvmLeaveSession(pVCpu);
2988	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2989
2990	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2991	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2992	\| CPUM_CHANGED_LDTR
2993	\| CPUM_CHANGED_GDTR
2994	\| CPUM_CHANGED_IDTR
2995	\| CPUM_CHANGED_TR
2996	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2997	if ( pVM->hm.s.fNestedPaging
2998	&& CPUMIsGuestPagingEnabledEx(pCtx))
2999	{
3000	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3001	}
3002
3003	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
3004	if (rcExit != VINF_EM_RAW_INTERRUPT)
3005	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3006
3007	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3008
3009	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
3010	VMMRZCallRing3RemoveNotification(pVCpu);
3011	VMMRZCallRing3Enable(pVCpu);
3012
3013	/*
3014	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3015	* and if we're injecting an event we should have a TRPM trap pending.
3016	*/
3017	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3018	pVCpu->hm.s.u32HMError = rcExit,
3019	VERR_SVM_IPE_5);
3020	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3021	pVCpu->hm.s.u32HMError = rcExit,
3022	VERR_SVM_IPE_4);
3023
3024	return rcExit;
3025	}
3026
3027
3028	#ifdef VBOX_WITH_NESTED_HWVIRT
3029	/**
3030	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3031	* intercepts for the nested-guest.
3032	*
3033	* @param pVM The cross context VM structure.
3034	* @param pVCpu The cross context virtual CPU structure.
3035	* @param pCtx Pointer to the nested guest-CPU context.
3036	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
3037	*
3038	* @remarks No-long-jump zone!!!
3039	*/
3040	static void hmR0SvmUpdateTscOffsettingNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcbNstGst)
3041	{
3042	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
3043
3044	bool fParavirtTsc;
3045	uint64_t uTscOffset;
3046	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
3047
3048	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
3049	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
3050
3051	/*
3052	* Only avoid intercepting if we determined the host TSC (++) is stable enough
3053	* to not intercept -and- the nested-hypervisor itself does not want to intercept it.
3054	*/
3055	if ( fCanUseRealTsc
3056	&& !(pVmcbNstGstCache->u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
3057	{
3058	pVmcbNstGstCtrl->u64InterceptCtrl &= ~(SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3059	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
3060
3061	/* Apply the nested-guest VMCB's TSC offset over the guest one. */
3062	uTscOffset = HMSvmNstGstApplyTscOffset(pVCpu, uTscOffset);
3063
3064	/* Update the nested-guest VMCB with the combined TSC offset (of guest and nested-guest). */
3065	pVmcbNstGstCtrl->u64TSCOffset = uTscOffset;
3066	}
3067	else
3068	{
3069	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP;
3070	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
3071	}
3072
3073	/* Finally update the VMCB clean bits since we touched the intercepts as well as the TSC offset. */
3074	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3075
3076	if (fParavirtTsc)
3077	{
3078	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3079	information before every VM-entry, hence disable it for performance sake. */
3080	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3081	}
3082	}
3083	#endif
3084
3085
3086	/**
3087	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3088	* intercepts.
3089	*
3090	* @param pVM The cross context VM structure.
3091	* @param pVCpu The cross context virtual CPU structure.
3092	* @param pVmcb Pointer to the VM control block.
3093	*
3094	* @remarks No-long-jump zone!!!
3095	*/
3096	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
3097	{
3098	bool fParavirtTsc;
3099	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
3100	if (fCanUseRealTsc)
3101	{
3102	pVmcb->ctrl.u64InterceptCtrl &= ~(SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3103	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
3104	}
3105	else
3106	{
3107	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP;
3108	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
3109	}
3110	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3111
3112	/** @todo later optimize this to be done elsewhere and not before every
3113	* VM-entry. */
3114	if (fParavirtTsc)
3115	{
3116	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3117	information before every VM-entry, hence disable it for performance sake. */
3118	#if 0
3119	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
3120	AssertRC(rc);
3121	#endif
3122	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3123	}
3124	}
3125
3126
3127	/**
3128	* Sets an event as a pending event to be injected into the guest.
3129	*
3130	* @param pVCpu The cross context virtual CPU structure.
3131	* @param pEvent Pointer to the SVM event.
3132	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3133	* page-fault.
3134	*
3135	* @remarks Statistics counter assumes this is a guest event being reflected to
3136	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3137	*/
3138	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3139	{
3140	Assert(!pVCpu->hm.s.Event.fPending);
3141	Assert(pEvent->n.u1Valid);
3142
3143	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3144	pVCpu->hm.s.Event.fPending = true;
3145	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3146
3147	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3148	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3149	}
3150
3151
3152	/**
3153	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3154	*
3155	* @param pVCpu The cross context virtual CPU structure.
3156	*/
3157	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3158	{
3159	SVMEVENT Event;
3160	Event.u = 0;
3161	Event.n.u1Valid = 1;
3162	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3163	Event.n.u8Vector = X86_XCPT_UD;
3164	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3165	}
3166
3167
3168	/**
3169	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3170	*
3171	* @param pVCpu The cross context virtual CPU structure.
3172	*/
3173	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3174	{
3175	SVMEVENT Event;
3176	Event.u = 0;
3177	Event.n.u1Valid = 1;
3178	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3179	Event.n.u8Vector = X86_XCPT_DB;
3180	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3181	}
3182
3183
3184	/**
3185	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3186	*
3187	* @param pVCpu The cross context virtual CPU structure.
3188	* @param pCtx Pointer to the guest-CPU context.
3189	* @param u32ErrCode The error-code for the page-fault.
3190	* @param uFaultAddress The page fault address (CR2).
3191	*
3192	* @remarks This updates the guest CR2 with @a uFaultAddress!
3193	*/
3194	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3195	{
3196	SVMEVENT Event;
3197	Event.u = 0;
3198	Event.n.u1Valid = 1;
3199	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3200	Event.n.u8Vector = X86_XCPT_PF;
3201	Event.n.u1ErrorCodeValid = 1;
3202	Event.n.u32ErrorCode = u32ErrCode;
3203
3204	/* Update CR2 of the guest. */
3205	if (pCtx->cr2 != uFaultAddress)
3206	{
3207	pCtx->cr2 = uFaultAddress;
3208	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3209	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3210	}
3211
3212	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3213	}
3214
3215
3216	/**
3217	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3218	*
3219	* @param pVCpu The cross context virtual CPU structure.
3220	*/
3221	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3222	{
3223	SVMEVENT Event;
3224	Event.u = 0;
3225	Event.n.u1Valid = 1;
3226	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3227	Event.n.u8Vector = X86_XCPT_MF;
3228	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3229	}
3230
3231
3232	/**
3233	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3234	*
3235	* @param pVCpu The cross context virtual CPU structure.
3236	*/
3237	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3238	{
3239	SVMEVENT Event;
3240	Event.u = 0;
3241	Event.n.u1Valid = 1;
3242	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3243	Event.n.u8Vector = X86_XCPT_DF;
3244	Event.n.u1ErrorCodeValid = 1;
3245	Event.n.u32ErrorCode = 0;
3246	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3247	}
3248
3249
3250	/**
3251	* Injects an event into the guest upon VMRUN by updating the relevant field
3252	* in the VMCB.
3253	*
3254	* @param pVCpu The cross context virtual CPU structure.
3255	* @param pVmcb Pointer to the guest VM control block.
3256	* @param pCtx Pointer to the guest-CPU context.
3257	* @param pEvent Pointer to the event.
3258	*
3259	* @remarks No-long-jump zone!!!
3260	* @remarks Requires CR0!
3261	*/
3262	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
3263	{
3264	NOREF(pVCpu); NOREF(pCtx);
3265
3266	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3267	pVmcb->ctrl.EventInject.u = pEvent->u;
3268	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3269
3270	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3271	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3272	}
3273
3274
3275
3276	/**
3277	* Converts any TRPM trap into a pending HM event. This is typically used when
3278	* entering from ring-3 (not longjmp returns).
3279	*
3280	* @param pVCpu The cross context virtual CPU structure.
3281	*/
3282	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3283	{
3284	Assert(TRPMHasTrap(pVCpu));
3285	Assert(!pVCpu->hm.s.Event.fPending);
3286
3287	uint8_t uVector;
3288	TRPMEVENT enmTrpmEvent;
3289	RTGCUINT uErrCode;
3290	RTGCUINTPTR GCPtrFaultAddress;
3291	uint8_t cbInstr;
3292
3293	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3294	AssertRC(rc);
3295
3296	SVMEVENT Event;
3297	Event.u = 0;
3298	Event.n.u1Valid = 1;
3299	Event.n.u8Vector = uVector;
3300
3301	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3302	if (enmTrpmEvent == TRPM_TRAP)
3303	{
3304	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3305	switch (uVector)
3306	{
3307	case X86_XCPT_NMI:
3308	{
3309	Event.n.u3Type = SVM_EVENT_NMI;
3310	break;
3311	}
3312
3313	case X86_XCPT_PF:
3314	case X86_XCPT_DF:
3315	case X86_XCPT_TS:
3316	case X86_XCPT_NP:
3317	case X86_XCPT_SS:
3318	case X86_XCPT_GP:
3319	case X86_XCPT_AC:
3320	{
3321	Event.n.u1ErrorCodeValid = 1;
3322	Event.n.u32ErrorCode = uErrCode;
3323	break;
3324	}
3325	}
3326	}
3327	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3328	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3329	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3330	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3331	else
3332	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3333
3334	rc = TRPMResetTrap(pVCpu);
3335	AssertRC(rc);
3336
3337	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3338	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3339
3340	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3341	}
3342
3343
3344	/**
3345	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3346	* AMD-V to execute any instruction.
3347	*
3348	* @param pVCpu The cross context virtual CPU structure.
3349	*/
3350	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3351	{
3352	Assert(pVCpu->hm.s.Event.fPending);
3353	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3354
3355	SVMEVENT Event;
3356	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3357
3358	uint8_t uVector = Event.n.u8Vector;
3359	uint8_t uVectorType = Event.n.u3Type;
3360	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3361
3362	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3363
3364	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3365	AssertRC(rc);
3366
3367	if (Event.n.u1ErrorCodeValid)
3368	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3369
3370	if ( uVectorType == SVM_EVENT_EXCEPTION
3371	&& uVector == X86_XCPT_PF)
3372	{
3373	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3374	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3375	}
3376	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3377	{
3378	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3379	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3380	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3381	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3382	}
3383	pVCpu->hm.s.Event.fPending = false;
3384	}
3385
3386
3387	/**
3388	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3389	* now.
3390	*
3391	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3392	* @param pVCpu The cross context virtual CPU structure.
3393	* @param pCtx Pointer to the guest-CPU context.
3394	*
3395	* @remarks No-long-jump zone!!!
3396	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3397	*/
3398	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
3399	{
3400	/*
3401	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
3402	* inhibit interrupts or clear any existing interrupt-inhibition.
3403	*/
3404	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3405	{
3406	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
3407	{
3408	/*
3409	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3410	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
3411	*/
3412	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3413	return false;
3414	}
3415	return true;
3416	}
3417	return false;
3418	}
3419
3420
3421	/**
3422	* Sets the virtual interrupt intercept control in the VMCB.
3423	*
3424	* @param pVmcb Pointer to the VM control block.
3425	*/
3426	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
3427	{
3428	/*
3429	* When AVIC isn't supported, indicate that a virtual interrupt is pending and to
3430	* cause a #VMEXIT when the guest is ready to accept interrupts. At #VMEXIT, we
3431	* then get the interrupt from the APIC (updating ISR at the right time) and
3432	* inject the interrupt.
3433	*
3434	* With AVIC is supported, we could make use of the asynchronously delivery without
3435	* #VMEXIT and we would be passing the AVIC page to SVM.
3436	*/
3437	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3438	{
3439	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 0);
3440	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3441	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
3442	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3443	Log4(("Set VINTR intercept\n"));
3444	}
3445	}
3446
3447
3448	/**
3449	* Clears the virtual interrupt intercept control in the VMCB as
3450	* we are figured the guest is unable process any interrupts
3451	* at this point of time.
3452	*
3453	* @param pVmcb Pointer to the VM control block.
3454	*/
3455	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
3456	{
3457	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3458	{
3459	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 1);
3460	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
3461	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3462	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3463	Log4(("Cleared VINTR intercept\n"));
3464	}
3465	}
3466
3467
3468	/**
3469	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3470	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3471	* virtual NMIs.
3472	*
3473	* @param pVmcb Pointer to the VM control block.
3474	*/
3475	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3476	{
3477	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3478	{
3479	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3480	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3481
3482	Log4(("Setting IRET intercept\n"));
3483	}
3484	}
3485
3486
3487	/**
3488	* Clears the IRET intercept control in the VMCB.
3489	*
3490	* @param pVmcb Pointer to the VM control block.
3491	*/
3492	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3493	{
3494	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3495	{
3496	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3497	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3498
3499	Log4(("Clearing IRET intercept\n"));
3500	}
3501	}
3502
3503	#ifdef VBOX_WITH_NESTED_HWVIRT
3504
3505
3506	/**
3507	* Evaluates the event to be delivered to the nested-guest and sets it as the
3508	* pending event.
3509	*
3510	* @returns VBox strict status code.
3511	* @param pVCpu The cross context virtual CPU structure.
3512	* @param pCtx Pointer to the guest-CPU context.
3513	*/
3514	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3515	{
3516	Log4Func(("\n"));
3517
3518	Assert(!pVCpu->hm.s.Event.fPending);
3519
3520	bool const fGif = pCtx->hwvirt.fGif;
3521	if (fGif)
3522	{
3523	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3524
3525	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3526
3527	/*
3528	* Check if the nested-guest can receive NMIs.
3529	* NMIs are higher priority than regular interrupts.
3530	*/
3531	/** @todo SMI. SMIs take priority over NMIs. */
3532	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3533	{
3534	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3535	if (fBlockNmi)
3536	hmR0SvmSetIretIntercept(pVmcbNstGst);
3537	else if (fIntShadow)
3538	{
3539	/** @todo Figure this out, how we shall manage virt. intercept if the
3540	* nested-guest already has one set and/or if we really need it? */
3541	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3542	}
3543	else
3544	{
3545	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3546	{
3547	Log4(("Intercepting NMI -> #VMEXIT\n"));
3548	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3549	}
3550
3551	Log4(("Pending NMI\n"));
3552	SVMEVENT Event;
3553	Event.u = 0;
3554	Event.n.u1Valid = 1;
3555	Event.n.u8Vector = X86_XCPT_NMI;
3556	Event.n.u3Type = SVM_EVENT_NMI;
3557	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3558	hmR0SvmSetIretIntercept(pVmcbNstGst);
3559	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3560	return VINF_SUCCESS;
3561	}
3562	}
3563
3564	/*
3565	* Check if the nested-guest can receive external interrupts (generated by
3566	* the guest's PIC/APIC).
3567	*
3568	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3569	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3570	*
3571	* External interrupts that are generated for the outer guest may be intercepted
3572	* depending on how the nested-guest VMCB was programmed by guest software.
3573	*
3574	* Physical interrupts always take priority over virtual interrupts,
3575	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3576	*/
3577	if (!fIntShadow)
3578	{
3579	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3580	&& !pVCpu->hm.s.fSingleInstruction
3581	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3582	{
3583	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3584	{
3585	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3586	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3587	}
3588
3589	uint8_t u8Interrupt;
3590	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3591	if (RT_SUCCESS(rc))
3592	{
3593	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3594	SVMEVENT Event;
3595	Event.u = 0;
3596	Event.n.u1Valid = 1;
3597	Event.n.u8Vector = u8Interrupt;
3598	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3599	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3600	}
3601	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3602	{
3603	/*
3604	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3605	* updated eventually when the TPR is written by the guest.
3606	*/
3607	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3608	}
3609	else
3610	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3611	}
3612
3613	/*
3614	* Check if the nested-guest is intercepting virtual (using V_IRQ and related fields)
3615	* interrupt injection. The virtual interrupt injection itself, if any, will be done
3616	* by the physical CPU.
3617	*/
3618	/** @todo later explore this for performance reasons. Right now the hardware
3619	* takes care of virtual interrupt injection for nested-guest. */
3620	#if 0
3621	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3622	&& CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR)
3623	&& CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx))
3624	{
3625	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3626	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3627	}
3628	#endif
3629	}
3630	}
3631
3632	return VINF_SUCCESS;
3633	}
3634	#endif
3635
3636
3637	/**
3638	* Evaluates the event to be delivered to the guest and sets it as the pending
3639	* event.
3640	*
3641	* @param pVCpu The cross context virtual CPU structure.
3642	* @param pCtx Pointer to the guest-CPU context.
3643	*
3644	* @remarks Don't use this function when we are actively executing a
3645	* nested-guest, use hmR0SvmEvaluatePendingEventNested instead.
3646	*/
3647	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3648	{
3649	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3650	Assert(!pVCpu->hm.s.Event.fPending);
3651
3652	#ifdef VBOX_WITH_NESTED_HWVIRT
3653	bool const fGif = pCtx->hwvirt.fGif;
3654	#else
3655	bool const fGif = true;
3656	#endif
3657	Log4Func(("fGif=%RTbool\n", fGif));
3658
3659	/*
3660	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3661	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3662	*/
3663	if (fGif)
3664	{
3665	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3666	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3667	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3668	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3669
3670	Log4Func(("fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fBlockInt, fIntShadow,
3671	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3672
3673	/** @todo SMI. SMIs take priority over NMIs. */
3674	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3675	{
3676	if (fBlockNmi)
3677	hmR0SvmSetIretIntercept(pVmcb);
3678	else if (fIntShadow)
3679	hmR0SvmSetVirtIntrIntercept(pVmcb);
3680	else
3681	{
3682	Log4(("Pending NMI\n"));
3683
3684	SVMEVENT Event;
3685	Event.u = 0;
3686	Event.n.u1Valid = 1;
3687	Event.n.u8Vector = X86_XCPT_NMI;
3688	Event.n.u3Type = SVM_EVENT_NMI;
3689
3690	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3691	hmR0SvmSetIretIntercept(pVmcb);
3692	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3693	return;
3694	}
3695	}
3696	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3697	&& !pVCpu->hm.s.fSingleInstruction)
3698	{
3699	/*
3700	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3701	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3702	*/
3703	if ( !fBlockInt
3704	&& !fIntShadow)
3705	{
3706	uint8_t u8Interrupt;
3707	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3708	if (RT_SUCCESS(rc))
3709	{
3710	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3711
3712	SVMEVENT Event;
3713	Event.u = 0;
3714	Event.n.u1Valid = 1;
3715	Event.n.u8Vector = u8Interrupt;
3716	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3717
3718	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3719	}
3720	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3721	{
3722	/*
3723	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3724	* updated eventually when the TPR is written by the guest.
3725	*/
3726	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3727	}
3728	else
3729	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3730	}
3731	else
3732	hmR0SvmSetVirtIntrIntercept(pVmcb);
3733	}
3734	}
3735	}
3736
3737
3738	/**
3739	* Injects any pending events into the guest or nested-guest.
3740	*
3741	* @param pVCpu The cross context virtual CPU structure.
3742	* @param pCtx Pointer to the guest-CPU context.
3743	* @param pVmcb Pointer to the VM control block.
3744	*/
3745	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3746	{
3747	Assert(!TRPMHasTrap(pVCpu));
3748	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3749
3750	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3751	#ifdef VBOX_STRICT
3752	bool const fGif = pCtx->hwvirt.fGif;
3753	bool fAllowInt = fGif;
3754	if (fGif)
3755	{
3756	/*
3757	* For nested-guests we have no way to determine if we're injecting a physical or virtual
3758	* interrupt at this point. Hence the partial verification below.
3759	*/
3760	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3761	fAllowInt = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx) \|\| CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx);
3762	else
3763	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3764	}
3765	#endif
3766
3767	if (pVCpu->hm.s.Event.fPending)
3768	{
3769	SVMEVENT Event;
3770	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3771	Assert(Event.n.u1Valid);
3772
3773	/*
3774	* Validate event injection pre-conditions.
3775	*/
3776	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3777	{
3778	Assert(fAllowInt);
3779	Assert(!fIntShadow);
3780	}
3781	else if (Event.n.u3Type == SVM_EVENT_NMI)
3782	{
3783	Assert(fGif);
3784	Assert(!fIntShadow);
3785	}
3786
3787	/*
3788	* Inject it (update VMCB for injection by the hardware).
3789	*/
3790	Log4(("Injecting pending HM event\n"));
3791	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3792	pVCpu->hm.s.Event.fPending = false;
3793
3794	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3795	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3796	else
3797	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3798	}
3799	else
3800	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3801
3802	/*
3803	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3804	*
3805	* For nested-guests: We need to update it too for the scenario where IEM executes
3806	* the nested-guest but execution later continues here with an interrupt shadow active.
3807	*/
3808	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3809	}
3810
3811
3812	/**
3813	* Reports world-switch error and dumps some useful debug info.
3814	*
3815	* @param pVM The cross context VM structure.
3816	* @param pVCpu The cross context virtual CPU structure.
3817	* @param rcVMRun The return code from VMRUN (or
3818	* VERR_SVM_INVALID_GUEST_STATE for invalid
3819	* guest-state).
3820	* @param pCtx Pointer to the guest-CPU context.
3821	*/
3822	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3823	{
3824	NOREF(pCtx);
3825	HMSVM_ASSERT_PREEMPT_SAFE();
3826	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3827	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3828
3829	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3830	{
3831	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3832	#ifdef VBOX_STRICT
3833	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3834	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3835	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3836	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3837	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3838	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3839	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3840	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3841	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3842	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3843
3844	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3845	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3846	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3847
3848	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3849	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3850	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3851	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved0));
3852	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3853	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3854	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3855	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3856	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3857	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved1));
3858	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3859	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3860
3861	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3862	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3863	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3864	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3865	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3866	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3867	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3868	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3869	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3870	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3871	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3872	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3873	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3874	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3875	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3876	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3877	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3878	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3879	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3880	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3881
3882	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3883
3884	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3885	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3886
3887	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3888	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3889	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3890	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3891	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3892	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3893	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3894	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3895	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3896	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3897	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3898	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3899	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3900	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3901	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3902	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3903	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3904	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3905	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3906	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3907
3908	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3909	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3910
3911	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3912	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3913	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3914	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3915
3916	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3917	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3918
3919	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3920	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3921	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3922	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3923
3924	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3925	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3926	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3927	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3928	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3929	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3930	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3931
3932	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3933	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3934	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3935	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3936
3937	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3938	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3939	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3940
3941	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3942	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3943	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3944	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3945	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3946	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3947	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
3948	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3949	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3950	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3951	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3952	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3953	#endif /* VBOX_STRICT */
3954	}
3955	else
3956	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3957
3958	NOREF(pVmcb);
3959	}
3960
3961
3962	/**
3963	* Check per-VM and per-VCPU force flag actions that require us to go back to
3964	* ring-3 for one reason or another.
3965	*
3966	* @returns VBox status code (information status code included).
3967	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3968	* ring-3.
3969	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3970	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3971	* interrupts)
3972	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3973	* all EMTs to be in ring-3.
3974	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3975	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3976	* to the EM loop.
3977	*
3978	* @param pVM The cross context VM structure.
3979	* @param pVCpu The cross context virtual CPU structure.
3980	* @param pCtx Pointer to the guest-CPU context.
3981	*/
3982	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3983	{
3984	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3985
3986	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3987	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3988	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3989
3990	/* Update pending interrupts into the APIC's IRR. */
3991	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3992	APICUpdatePendingInterrupts(pVCpu);
3993
3994	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3995	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3996	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3997	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3998	{
3999	/* Pending PGM C3 sync. */
4000	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4001	{
4002	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4003	if (rc != VINF_SUCCESS)
4004	{
4005	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4006	return rc;
4007	}
4008	}
4009
4010	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4011	/* -XXX- what was that about single stepping? */
4012	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
4013	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4014	{
4015	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4016	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
4017	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4018	return rc;
4019	}
4020
4021	/* Pending VM request packets, such as hardware interrupts. */
4022	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
4023	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
4024	{
4025	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
4026	return VINF_EM_PENDING_REQUEST;
4027	}
4028
4029	/* Pending PGM pool flushes. */
4030	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4031	{
4032	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
4033	return VINF_PGM_POOL_FLUSH_PENDING;
4034	}
4035
4036	/* Pending DMA requests. */
4037	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
4038	{
4039	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
4040	return VINF_EM_RAW_TO_R3;
4041	}
4042	}
4043
4044	return VINF_SUCCESS;
4045	}
4046
4047
4048	#ifdef VBOX_WITH_NESTED_HWVIRT
4049	/**
4050	* Does the preparations before executing nested-guest code in AMD-V.
4051	*
4052	* @returns VBox status code (informational status codes included).
4053	* @retval VINF_SUCCESS if we can proceed with running the guest.
4054	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4055	*
4056	* @param pVM The cross context VM structure.
4057	* @param pVCpu The cross context virtual CPU structure.
4058	* @param pCtx Pointer to the guest-CPU context.
4059	* @param pSvmTransient Pointer to the SVM transient structure.
4060	*
4061	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
4062	* @sa hmR0SvmPreRunGuest.
4063	*/
4064	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4065	{
4066	HMSVM_ASSERT_PREEMPT_SAFE();
4067
4068	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4069	{
4070	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4071	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4072	return VINF_EM_RESCHEDULE_REM;
4073	#endif
4074	}
4075	else
4076	return VINF_SVM_VMEXIT;
4077
4078	/* Check force flag actions that might require us to go back to ring-3. */
4079	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
4080	if (rc != VINF_SUCCESS)
4081	return rc;
4082
4083	if (TRPMHasTrap(pVCpu))
4084	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4085	else if (!pVCpu->hm.s.Event.fPending)
4086	{
4087	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
4088	if (rcStrict != VINF_SUCCESS)
4089	return VBOXSTRICTRC_VAL(rcStrict);
4090	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4091	return VINF_SVM_VMEXIT;
4092	}
4093
4094	/*
4095	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4096	* Just do it in software, see @bugref{8411}.
4097	* NB: If we could continue a task switch exit we wouldn't need to do this.
4098	*/
4099	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4100	&& pVCpu->hm.s.Event.fPending
4101	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4102	{
4103	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4104	}
4105
4106	#ifdef HMSVM_SYNC_FULL_NESTED_GUEST_STATE
4107	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4108	#endif
4109
4110	/*
4111	* Load the nested-guest state.
4112	*/
4113	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
4114	AssertRCReturn(rc, rc);
4115	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */
4116
4117	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */
4118	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
4119
4120	/*
4121	* No longjmps to ring-3 from this point on!!!
4122	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4123	* This also disables flushing of the R0-logger instance (if any).
4124	*/
4125	VMMRZCallRing3Disable(pVCpu);
4126
4127	/*
4128	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4129	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4130	*
4131	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4132	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4133	*
4134	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4135	* executing guest code.
4136	*/
4137	pSvmTransient->fEFlags = ASMIntDisableFlags();
4138	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4139	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4140	{
4141	ASMSetFlags(pSvmTransient->fEFlags);
4142	VMMRZCallRing3Enable(pVCpu);
4143	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4144	return VINF_EM_RAW_TO_R3;
4145	}
4146	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4147	{
4148	ASMSetFlags(pSvmTransient->fEFlags);
4149	VMMRZCallRing3Enable(pVCpu);
4150	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4151	return VINF_EM_RAW_INTERRUPT;
4152	}
4153
4154	/*
4155	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4156	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4157	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4158	*
4159	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4160	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4161	*/
4162	if (pVCpu->hm.s.Event.fPending)
4163	{
4164	SVMEVENT Event;
4165	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4166	if ( Event.n.u1Valid
4167	&& Event.n.u3Type == SVM_EVENT_NMI
4168	&& Event.n.u8Vector == X86_XCPT_NMI
4169	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4170	{
4171	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4172	}
4173	}
4174
4175	return VINF_SUCCESS;
4176	}
4177	#endif
4178
4179
4180	/**
4181	* Does the preparations before executing guest code in AMD-V.
4182	*
4183	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4184	* recompiler. We must be cautious what we do here regarding committing
4185	* guest-state information into the VMCB assuming we assuredly execute the guest
4186	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4187	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4188	* that the recompiler can (and should) use them when it resumes guest
4189	* execution. Otherwise such operations must be done when we can no longer
4190	* exit to ring-3.
4191	*
4192	* @returns VBox status code (informational status codes included).
4193	* @retval VINF_SUCCESS if we can proceed with running the guest.
4194	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4195	*
4196	* @param pVM The cross context VM structure.
4197	* @param pVCpu The cross context virtual CPU structure.
4198	* @param pCtx Pointer to the guest-CPU context.
4199	* @param pSvmTransient Pointer to the SVM transient structure.
4200	*/
4201	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4202	{
4203	HMSVM_ASSERT_PREEMPT_SAFE();
4204	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4205
4206	/* Check force flag actions that might require us to go back to ring-3. */
4207	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
4208	if (rc != VINF_SUCCESS)
4209	return rc;
4210
4211	if (TRPMHasTrap(pVCpu))
4212	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4213	else if (!pVCpu->hm.s.Event.fPending)
4214	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
4215
4216	/*
4217	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4218	* Just do it in software, see @bugref{8411}.
4219	* NB: If we could continue a task switch exit we wouldn't need to do this.
4220	*/
4221	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4222	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4223	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4224
4225	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4226	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4227	#endif
4228
4229	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
4230	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
4231	AssertRCReturn(rc, rc);
4232	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
4233
4234	/*
4235	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
4236	* so we can update it on the way back if the guest changed the TPR.
4237	*/
4238	if (pVCpu->hm.s.svm.fSyncVTpr)
4239	{
4240	if (pVM->hm.s.fTPRPatchingActive)
4241	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
4242	else
4243	{
4244	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4245	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4246	}
4247	}
4248
4249	/*
4250	* No longjmps to ring-3 from this point on!!!
4251	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4252	* This also disables flushing of the R0-logger instance (if any).
4253	*/
4254	VMMRZCallRing3Disable(pVCpu);
4255
4256	/*
4257	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4258	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4259	*
4260	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4261	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4262	*
4263	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4264	* executing guest code.
4265	*/
4266	pSvmTransient->fEFlags = ASMIntDisableFlags();
4267	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4268	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4269	{
4270	ASMSetFlags(pSvmTransient->fEFlags);
4271	VMMRZCallRing3Enable(pVCpu);
4272	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4273	return VINF_EM_RAW_TO_R3;
4274	}
4275	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4276	{
4277	ASMSetFlags(pSvmTransient->fEFlags);
4278	VMMRZCallRing3Enable(pVCpu);
4279	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4280	return VINF_EM_RAW_INTERRUPT;
4281	}
4282
4283	/*
4284	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4285	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4286	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4287	*
4288	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4289	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4290	*/
4291	if (pVCpu->hm.s.Event.fPending)
4292	{
4293	SVMEVENT Event;
4294	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4295	if ( Event.n.u1Valid
4296	&& Event.n.u3Type == SVM_EVENT_NMI
4297	&& Event.n.u8Vector == X86_XCPT_NMI
4298	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4299	{
4300	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4301	}
4302	}
4303
4304	return VINF_SUCCESS;
4305	}
4306
4307
4308	/**
4309	* Prepares to run guest or nested-guest code in AMD-V and we've committed to
4310	* doing so.
4311	*
4312	* This means there is no backing out to ring-3 or anywhere else at this point.
4313	*
4314	* @param pVM The cross context VM structure.
4315	* @param pVCpu The cross context virtual CPU structure.
4316	* @param pCtx Pointer to the guest-CPU context.
4317	* @param pSvmTransient Pointer to the SVM transient structure.
4318	*
4319	* @remarks Called with preemption disabled.
4320	* @remarks No-long-jump zone!!!
4321	*/
4322	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4323	{
4324	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4325	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4326	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4327
4328	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4329	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4330
4331	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
4332	PSVMVMCB pVmcb = !fInNestedGuestMode ? pVCpu->hm.s.svm.pVmcb : pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4333
4334	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
4335
4336	if (!CPUMIsGuestFPUStateActive(pVCpu))
4337	{
4338	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4339	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4340	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4341	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4342	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4343	}
4344
4345	/* Load the state shared between host and guest (FPU, debug). */
4346	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4347	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
4348
4349	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4350	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4351
4352	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
4353	RTCPUID const idHostCpu = pHostCpu->idCpu;
4354	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4355
4356	/* Setup TSC offsetting. */
4357	if ( pSvmTransient->fUpdateTscOffsetting
4358	\|\| fMigratedHostCpu)
4359	{
4360	if (!fInNestedGuestMode)
4361	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
4362	else
4363	hmR0SvmUpdateTscOffsettingNested(pVM, pVCpu, pCtx, pVmcb);
4364	pSvmTransient->fUpdateTscOffsetting = false;
4365	}
4366
4367	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4368	if (fMigratedHostCpu)
4369	pVmcb->ctrl.u32VmcbCleanBits = 0;
4370
4371	/* Store status of the shared guest-host state at the time of VMRUN. */
4372	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4373	if (CPUMIsGuestInLongModeEx(pCtx))
4374	{
4375	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4376	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4377	}
4378	else
4379	#endif
4380	{
4381	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4382	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4383	}
4384
4385	uint8_t *pbMsrBitmap;
4386	if (!fInNestedGuestMode)
4387	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4388	else
4389	{
4390	hmR0SvmMergeMsrpm(pHostCpu, pVCpu, pCtx);
4391
4392	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4393	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4394	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4395	}
4396
4397	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4398	/* Flush the appropriate tagged-TLB entries. */
4399	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb, pHostCpu);
4400	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4401
4402	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4403
4404	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4405	to start executing. */
4406
4407	/*
4408	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4409	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4410	*
4411	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4412	*/
4413	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4414	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4415	{
4416	uint64_t const uGuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4417	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4418	if (uGuestTscAux != pVCpu->hm.s.u64HostTscAux)
4419	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4420	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4421	pSvmTransient->fRestoreTscAuxMsr = true;
4422	}
4423	else
4424	{
4425	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4426	pSvmTransient->fRestoreTscAuxMsr = false;
4427	}
4428	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4429
4430	/*
4431	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the
4432	* nested virtualization case, mark all state-bits as dirty indicating to the
4433	* CPU to re-load from VMCB.
4434	*/
4435	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4436	if (!fSupportsVmcbCleanBits)
4437	pVmcb->ctrl.u32VmcbCleanBits = 0;
4438	}
4439
4440
4441	/**
4442	* Wrapper for running the guest code in AMD-V.
4443	*
4444	* @returns VBox strict status code.
4445	* @param pVM The cross context VM structure.
4446	* @param pVCpu The cross context virtual CPU structure.
4447	* @param pCtx Pointer to the guest-CPU context.
4448	*
4449	* @remarks No-long-jump zone!!!
4450	*/
4451	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4452	{
4453	/*
4454	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4455	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4456	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4457	*/
4458	#ifdef VBOX_WITH_KERNEL_USING_XMM
4459	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4460	pVCpu->hm.s.svm.pfnVMRun);
4461	#else
4462	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4463	#endif
4464	}
4465
4466
4467	#ifdef VBOX_WITH_NESTED_HWVIRT
4468	/**
4469	* Wrapper for running the nested-guest code in AMD-V.
4470	*
4471	* @returns VBox strict status code.
4472	* @param pVM The cross context VM structure.
4473	* @param pVCpu The cross context virtual CPU structure.
4474	* @param pCtx Pointer to the guest-CPU context.
4475	*
4476	* @remarks No-long-jump zone!!!
4477	*/
4478	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4479	{
4480	/*
4481	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4482	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4483	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4484	*/
4485	#ifdef VBOX_WITH_KERNEL_USING_XMM
4486	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4487	pVCpu->hm.s.svm.pfnVMRun);
4488	#else
4489	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4490	#endif
4491	}
4492
4493
4494	/**
4495	* Performs some essential restoration of state after running nested-guest code in
4496	* AMD-V.
4497	*
4498	* @param pVM The cross context VM structure.
4499	* @param pVCpu The cross context virtual CPU structure.
4500	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4501	* out-of-sync. Make sure to update the required fields
4502	* before using them.
4503	* @param pSvmTransient Pointer to the SVM transient structure.
4504	* @param rcVMRun Return code of VMRUN.
4505	*
4506	* @remarks Called with interrupts disabled.
4507	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4508	* unconditionally when it is safe to do so.
4509	*/
4510	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4511	{
4512	RT_NOREF(pVM);
4513	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4514
4515	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4516	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4517
4518	/* TSC read must be done early for maximum accuracy. */
4519	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4520	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4521	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pMixedCtx);
4522	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4523	{
4524	/*
4525	* Undo what we did in hmR0SvmUpdateTscOffsettingNested() but don't restore the
4526	* nested-guest VMCB TSC offset here. It shall eventually be restored on #VMEXIT
4527	* later by HMSvmNstGstVmExitNotify().
4528	*/
4529	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset - pVmcbNstGstCache->u64TSCOffset);
4530	}
4531
4532	if (pSvmTransient->fRestoreTscAuxMsr)
4533	{
4534	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4535	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4536	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4537	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4538	}
4539
4540	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4541	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4542	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4543
4544	Assert(!(ASMGetFlags() & X86_EFL_IF));
4545	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4546	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4547
4548	/* Mark the VMCB-state cache as unmodified by VMM. */
4549	pVmcbNstGstCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4550
4551	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4552	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4553	{
4554	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4555	return;
4556	}
4557
4558	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4559	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4560	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4561	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4562
4563	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4564	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4565	guest-CPU context. */
4566	}
4567	#endif
4568
4569	/**
4570	* Performs some essential restoration of state after running guest code in
4571	* AMD-V.
4572	*
4573	* @param pVM The cross context VM structure.
4574	* @param pVCpu The cross context virtual CPU structure.
4575	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4576	* out-of-sync. Make sure to update the required fields
4577	* before using them.
4578	* @param pSvmTransient Pointer to the SVM transient structure.
4579	* @param rcVMRun Return code of VMRUN.
4580	*
4581	* @remarks Called with interrupts disabled.
4582	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4583	* unconditionally when it is safe to do so.
4584	*/
4585	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4586	{
4587	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4588
4589	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4590	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4591
4592	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4593	pVmcb->ctrl.u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4594
4595	/* TSC read must be done early for maximum accuracy. */
4596	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4597	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4598
4599	if (pSvmTransient->fRestoreTscAuxMsr)
4600	{
4601	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4602	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4603	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4604	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4605	}
4606
4607	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4608	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4609	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4610
4611	Assert(!(ASMGetFlags() & X86_EFL_IF));
4612	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4613	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4614
4615	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4616	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4617	{
4618	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4619	return;
4620	}
4621
4622	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4623	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4624	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4625	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4626
4627	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4628
4629	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4630	{
4631	if (pVCpu->hm.s.svm.fSyncVTpr)
4632	{
4633	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4634	if ( pVM->hm.s.fTPRPatchingActive
4635	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4636	{
4637	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4638	AssertRC(rc);
4639	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4640	}
4641	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4642	{
4643	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4644	AssertRC(rc);
4645	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4646	}
4647	}
4648	}
4649	}
4650
4651
4652	/**
4653	* Runs the guest code using AMD-V.
4654	*
4655	* @returns VBox status code.
4656	* @param pVM The cross context VM structure.
4657	* @param pVCpu The cross context virtual CPU structure.
4658	* @param pCtx Pointer to the guest-CPU context.
4659	* @param pcLoops Pointer to the number of executed loops.
4660	*/
4661	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4662	{
4663	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4664	Assert(pcLoops);
4665	Assert(*pcLoops <= cMaxResumeLoops);
4666
4667	SVMTRANSIENT SvmTransient;
4668	SvmTransient.fUpdateTscOffsetting = true;
4669
4670	int rc = VERR_INTERNAL_ERROR_5;
4671	for (;;)
4672	{
4673	Assert(!HMR0SuspendPending());
4674	HMSVM_ASSERT_CPU_SAFE();
4675
4676	/* Preparatory work for running guest code, this may force us to return
4677	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4678	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4679	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4680	if (rc != VINF_SUCCESS)
4681	break;
4682
4683	/*
4684	* No longjmps to ring-3 from this point on!!!
4685	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4686	* This also disables flushing of the R0-logger instance (if any).
4687	*/
4688	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4689	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4690
4691	/* Restore any residual host-state and save any bits shared between host
4692	and guest into the guest-CPU state. Re-enables interrupts! */
4693	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4694
4695	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4696	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4697	{
4698	if (rc == VINF_SUCCESS)
4699	rc = VERR_SVM_INVALID_GUEST_STATE;
4700	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4701	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4702	break;
4703	}
4704
4705	/* Handle the #VMEXIT. */
4706	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4707	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4708	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4709	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4710	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4711	if (rc != VINF_SUCCESS)
4712	break;
4713	if (++(*pcLoops) >= cMaxResumeLoops)
4714	{
4715	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4716	rc = VINF_EM_RAW_INTERRUPT;
4717	break;
4718	}
4719	}
4720
4721	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4722	return rc;
4723	}
4724
4725
4726	/**
4727	* Runs the guest code using AMD-V in single step mode.
4728	*
4729	* @returns VBox status code.
4730	* @param pVM The cross context VM structure.
4731	* @param pVCpu The cross context virtual CPU structure.
4732	* @param pCtx Pointer to the guest-CPU context.
4733	* @param pcLoops Pointer to the number of executed loops.
4734	*/
4735	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4736	{
4737	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4738	Assert(pcLoops);
4739	Assert(*pcLoops <= cMaxResumeLoops);
4740
4741	SVMTRANSIENT SvmTransient;
4742	SvmTransient.fUpdateTscOffsetting = true;
4743
4744	uint16_t uCsStart = pCtx->cs.Sel;
4745	uint64_t uRipStart = pCtx->rip;
4746
4747	int rc = VERR_INTERNAL_ERROR_5;
4748	for (;;)
4749	{
4750	Assert(!HMR0SuspendPending());
4751	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4752	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4753	(unsigned)RTMpCpuId(), *pcLoops));
4754
4755	/* Preparatory work for running guest code, this may force us to return
4756	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4757	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4758	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4759	if (rc != VINF_SUCCESS)
4760	break;
4761
4762	/*
4763	* No longjmps to ring-3 from this point on!!!
4764	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4765	* This also disables flushing of the R0-logger instance (if any).
4766	*/
4767	VMMRZCallRing3Disable(pVCpu);
4768	VMMRZCallRing3RemoveNotification(pVCpu);
4769	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4770
4771	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4772
4773	/*
4774	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4775	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4776	*/
4777	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4778	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4779	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4780	{
4781	if (rc == VINF_SUCCESS)
4782	rc = VERR_SVM_INVALID_GUEST_STATE;
4783	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4784	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4785	return rc;
4786	}
4787
4788	/* Handle the #VMEXIT. */
4789	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4790	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4791	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4792	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4793	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4794	if (rc != VINF_SUCCESS)
4795	break;
4796	if (++(*pcLoops) >= cMaxResumeLoops)
4797	{
4798	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4799	rc = VINF_EM_RAW_INTERRUPT;
4800	break;
4801	}
4802
4803	/*
4804	* Did the RIP change, if so, consider it a single step.
4805	* Otherwise, make sure one of the TFs gets set.
4806	*/
4807	if ( pCtx->rip != uRipStart
4808	\|\| pCtx->cs.Sel != uCsStart)
4809	{
4810	rc = VINF_EM_DBG_STEPPED;
4811	break;
4812	}
4813	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4814	}
4815
4816	/*
4817	* Clear the X86_EFL_TF if necessary.
4818	*/
4819	if (pVCpu->hm.s.fClearTrapFlag)
4820	{
4821	pVCpu->hm.s.fClearTrapFlag = false;
4822	pCtx->eflags.Bits.u1TF = 0;
4823	}
4824
4825	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4826	return rc;
4827	}
4828
4829	#ifdef VBOX_WITH_NESTED_HWVIRT
4830	/**
4831	* Runs the nested-guest code using AMD-V.
4832	*
4833	* @returns VBox status code.
4834	* @param pVM The cross context VM structure.
4835	* @param pVCpu The cross context virtual CPU structure.
4836	* @param pCtx Pointer to the guest-CPU context.
4837	* @param pcLoops Pointer to the number of executed loops. If we're switching
4838	* from the guest-code execution loop to this nested-guest
4839	* execution loop pass the remainder value, else pass 0.
4840	*/
4841	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4842	{
4843	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4844	Assert(pcLoops);
4845	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4846
4847	SVMTRANSIENT SvmTransient;
4848	SvmTransient.fUpdateTscOffsetting = true;
4849
4850	int rc = VERR_INTERNAL_ERROR_4;
4851	for (;;)
4852	{
4853	Assert(!HMR0SuspendPending());
4854	HMSVM_ASSERT_CPU_SAFE();
4855
4856	/* Preparatory work for running nested-guest code, this may force us to return
4857	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4858	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4859	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4860	if ( rc != VINF_SUCCESS
4861	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4862	{
4863	break;
4864	}
4865
4866	/*
4867	* No longjmps to ring-3 from this point on!!!
4868	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4869	* This also disables flushing of the R0-logger instance (if any).
4870	*/
4871	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4872
4873	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4874
4875	/* Restore any residual host-state and save any bits shared between host
4876	and guest into the guest-CPU state. Re-enables interrupts! */
4877	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4878
4879	if (RT_LIKELY( rc == VINF_SUCCESS
4880	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4881	{ /* extremely likely */ }
4882	else
4883	{
4884	/* VMRUN failed, shouldn't really happen, Guru. */
4885	if (rc != VINF_SUCCESS)
4886	break;
4887
4888	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4889	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4890	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4891	break;
4892	}
4893
4894	/* Handle the #VMEXIT. */
4895	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4896	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4897	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4898	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4899	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4900	if (rc != VINF_SUCCESS)
4901	break;
4902	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4903	{
4904	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4905	rc = VINF_EM_RAW_INTERRUPT;
4906	break;
4907	}
4908
4909	/** @todo handle single-stepping */
4910	}
4911
4912	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4913	return rc;
4914	}
4915	#endif
4916
4917
4918	/**
4919	* Runs the guest code using AMD-V.
4920	*
4921	* @returns Strict VBox status code.
4922	* @param pVM The cross context VM structure.
4923	* @param pVCpu The cross context virtual CPU structure.
4924	* @param pCtx Pointer to the guest-CPU context.
4925	*/
4926	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4927	{
4928	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4929	HMSVM_ASSERT_PREEMPT_SAFE();
4930	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4931
4932	uint32_t cLoops = 0;
4933	int rc;
4934	#ifdef VBOX_WITH_NESTED_HWVIRT
4935	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4936	#endif
4937	{
4938	if (!pVCpu->hm.s.fSingleInstruction)
4939	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4940	else
4941	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4942	}
4943	#ifdef VBOX_WITH_NESTED_HWVIRT
4944	else
4945	{
4946	rc = VINF_SVM_VMRUN;
4947	}
4948
4949	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4950	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4951	if (rc == VINF_SVM_VMRUN)
4952	{
4953	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4954	if (rc == VINF_SVM_VMEXIT)
4955	rc = VINF_SUCCESS;
4956	}
4957	#endif
4958
4959	/* Fixup error codes. */
4960	if (rc == VERR_EM_INTERPRETER)
4961	rc = VINF_EM_RAW_EMULATE_INSTR;
4962	else if (rc == VINF_EM_RESET)
4963	rc = VINF_EM_TRIPLE_FAULT;
4964
4965	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4966	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4967	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4968	return rc;
4969	}
4970
4971
4972	#ifdef VBOX_WITH_NESTED_HWVIRT
4973	/**
4974	* Determines whether an IOIO intercept is active for the nested-guest or not.
4975	*
4976	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4977	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4978	*/
4979	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4980	{
4981	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4982	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4983	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4984	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4985	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4986	const bool fRep = pIoExitInfo->n.u1REP;
4987	const bool fStrIo = pIoExitInfo->n.u1STR;
4988
4989	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4990	NULL /* pIoExitInfo */);
4991	}
4992
4993
4994	/**
4995	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4996	* SVM_EXIT_INVALID).
4997	*
4998	* @returns VBox status code (informational status codes included).
4999	* @param pVCpu The cross context virtual CPU structure.
5000	* @param pCtx Pointer to the guest-CPU context.
5001	* @param pSvmTransient Pointer to the SVM transient structure.
5002	*/
5003	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5004	{
5005	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
5006	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5007	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5008
5009	#define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5010	VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
5011
5012	/*
5013	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
5014	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
5015	*/
5016	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
5017	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5018	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5019	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5020	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5021
5022	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5023	switch (uExitCode)
5024	{
5025	case SVM_EXIT_CPUID:
5026	{
5027	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
5028	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5029	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5030	}
5031
5032	case SVM_EXIT_RDTSC:
5033	{
5034	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
5035	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5036	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5037	}
5038
5039	case SVM_EXIT_RDTSCP:
5040	{
5041	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
5042	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5043	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5044	}
5045
5046	case SVM_EXIT_MONITOR:
5047	{
5048	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
5049	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5050	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5051	}
5052
5053	case SVM_EXIT_MWAIT:
5054	{
5055	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
5056	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5057	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5058	}
5059
5060	case SVM_EXIT_HLT:
5061	{
5062	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
5063	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5064	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5065	}
5066
5067	case SVM_EXIT_MSR:
5068	{
5069	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
5070	{
5071	uint32_t const idMsr = pCtx->ecx;
5072	uint16_t offMsrpm;
5073	uint8_t uMsrpmBit;
5074	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5075	if (RT_SUCCESS(rc))
5076	{
5077	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
5078	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
5079
5080	uint8_t const pbMsrBitmap = (uint8_t const )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5081	pbMsrBitmap += offMsrpm;
5082	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
5083	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
5084
5085	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5086	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5087	{
5088	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5089	}
5090	}
5091	else
5092	{
5093	/*
5094	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5095	* See AMD-V spec. "15.11 MSR Intercepts".
5096	*/
5097	Assert(rc == VERR_OUT_OF_RANGE);
5098	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5099	}
5100	}
5101	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5102	}
5103
5104	case SVM_EXIT_IOIO:
5105	{
5106	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
5107	{
5108	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
5109	SVMIOIOEXITINFO IoExitInfo;
5110	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5111	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
5112	if (fIntercept)
5113	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5114	}
5115	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5116	}
5117
5118	case SVM_EXIT_XCPT_PF:
5119	{
5120	PVM pVM = pVCpu->CTX_SUFF(pVM);
5121	if (pVM->hm.s.fNestedPaging)
5122	{
5123	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5124	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5125
5126	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5127	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5128	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5129
5130	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
5131	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5132	return VINF_SUCCESS;
5133	}
5134	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
5135	}
5136
5137	case SVM_EXIT_XCPT_UD:
5138	{
5139	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
5140	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5141	hmR0SvmSetPendingXcptUD(pVCpu);
5142	return VINF_SUCCESS;
5143	}
5144
5145	case SVM_EXIT_XCPT_MF:
5146	{
5147	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
5148	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5149	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5150	}
5151
5152	case SVM_EXIT_XCPT_DB:
5153	{
5154	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5155	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5156	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
5157	}
5158
5159	case SVM_EXIT_XCPT_AC:
5160	{
5161	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5162	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5163	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5164	}
5165
5166	case SVM_EXIT_XCPT_BP:
5167	{
5168	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5169	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5170	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
5171	}
5172
5173	case SVM_EXIT_READ_CR0:
5174	case SVM_EXIT_READ_CR3:
5175	case SVM_EXIT_READ_CR4:
5176	{
5177	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5178	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5179	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5180	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5181	}
5182
5183	case SVM_EXIT_CR0_SEL_WRITE:
5184	{
5185	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5186	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5187	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5188	}
5189
5190	case SVM_EXIT_WRITE_CR0:
5191	case SVM_EXIT_WRITE_CR3:
5192	case SVM_EXIT_WRITE_CR4:
5193	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set? */
5194	{
5195	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5196	Log4(("hmR0SvmHandleExitNested: Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5197
5198	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5199	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5200	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5201	}
5202
5203	case SVM_EXIT_PAUSE:
5204	{
5205	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5206	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5207	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5208	}
5209
5210	case SVM_EXIT_VINTR:
5211	{
5212	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5213	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5214	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5215	}
5216
5217	case SVM_EXIT_INTR:
5218	case SVM_EXIT_NMI:
5219	case SVM_EXIT_XCPT_NMI: /* Shouldn't ever happen, SVM_EXIT_NMI is used instead. */
5220	case SVM_EXIT_SMI:
5221	{
5222	/*
5223	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5224	*
5225	* Although we don't intercept SMIs, the nested-guest might. Therefore, we
5226	* might get an SMI #VMEXIT here so simply ignore rather than causing a
5227	* corresponding nested-guest #VMEXIT.
5228	*/
5229	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5230	}
5231
5232	case SVM_EXIT_FERR_FREEZE:
5233	{
5234	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5235	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5236	return hmR0SvmExitFerrFreeze(pVCpu, pCtx, pSvmTransient);
5237	}
5238
5239	case SVM_EXIT_INVLPG:
5240	{
5241	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5242	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5243	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5244	}
5245
5246	case SVM_EXIT_WBINVD:
5247	{
5248	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5249	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5250	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5251	}
5252
5253	case SVM_EXIT_INVD:
5254	{
5255	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5256	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5257	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5258	}
5259
5260	case SVM_EXIT_RDPMC:
5261	{
5262	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5263	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5264	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5265	}
5266
5267	default:
5268	{
5269	switch (uExitCode)
5270	{
5271	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5272	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5273	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5274	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5275	{
5276	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5277	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5278	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5279	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5280	}
5281
5282	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5283	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5284	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5285	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5286	{
5287	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5288	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5289	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5290	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5291	}
5292
5293	case SVM_EXIT_XCPT_0: /* #DE */
5294	/* SVM_EXIT_XCPT_1: / / #DB - Handled above. */
5295	/* SVM_EXIT_XCPT_2: / / #NMI - Handled above. */
5296	/* SVM_EXIT_XCPT_3: / / #BP - Handled above. */
5297	case SVM_EXIT_XCPT_4: /* #OF */
5298	case SVM_EXIT_XCPT_5: /* #BR */
5299	/* SVM_EXIT_XCPT_6: / / #UD - Handled above. */
5300	case SVM_EXIT_XCPT_7: /* #NM */
5301	case SVM_EXIT_XCPT_8: /* #DF */
5302	case SVM_EXIT_XCPT_9: /* #CO_SEG_OVERRUN */
5303	case SVM_EXIT_XCPT_10: /* #TS */
5304	case SVM_EXIT_XCPT_11: /* #NP */
5305	case SVM_EXIT_XCPT_12: /* #SS */
5306	case SVM_EXIT_XCPT_13: /* #GP */
5307	/* SVM_EXIT_XCPT_14: / / #PF - Handled above. */
5308	case SVM_EXIT_XCPT_15: /* Reserved. */
5309	/* SVM_EXIT_XCPT_16: / / #MF - Handled above. */
5310	/* SVM_EXIT_XCPT_17: / / #AC - Handled above. */
5311	case SVM_EXIT_XCPT_18: /* #MC */
5312	case SVM_EXIT_XCPT_19: /* #XF */
5313	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5314	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5315	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5316	{
5317	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5318	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5319	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5320	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5321	}
5322
5323	case SVM_EXIT_XSETBV:
5324	{
5325	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5326	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5327	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5328	}
5329
5330	case SVM_EXIT_TASK_SWITCH:
5331	{
5332	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5333	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5334	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5335	}
5336
5337	case SVM_EXIT_IRET:
5338	{
5339	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5340	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5341	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5342	}
5343
5344	case SVM_EXIT_SHUTDOWN:
5345	{
5346	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5347	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5348	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5349	}
5350
5351	case SVM_EXIT_VMMCALL:
5352	{
5353	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5354	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5355	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5356	}
5357
5358	case SVM_EXIT_CLGI:
5359	{
5360	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5361	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5362	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5363	}
5364
5365	case SVM_EXIT_STGI:
5366	{
5367	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5368	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5369	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5370	}
5371
5372	case SVM_EXIT_VMLOAD:
5373	{
5374	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5375	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5376	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5377	}
5378
5379	case SVM_EXIT_VMSAVE:
5380	{
5381	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5382	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5383	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5384	}
5385
5386	case SVM_EXIT_INVLPGA:
5387	{
5388	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5389	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5390	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5391	}
5392
5393	case SVM_EXIT_VMRUN:
5394	{
5395	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5396	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5397	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5398	}
5399
5400	case SVM_EXIT_RSM:
5401	{
5402	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5403	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5404	hmR0SvmSetPendingXcptUD(pVCpu);
5405	return VINF_SUCCESS;
5406	}
5407
5408	case SVM_EXIT_SKINIT:
5409	{
5410	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5411	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5412	hmR0SvmSetPendingXcptUD(pVCpu);
5413	return VINF_SUCCESS;
5414	}
5415
5416	/** @todo Needed when restoring saved-state when saved state support wasn't yet
5417	* added. Perhaps it won't be required later. */
5418	#if 0
5419	case SVM_EXIT_NPF:
5420	{
5421	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5422	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5423	return HM_SVM_VMEXIT_NESTED(pVCpu, SVM_EXIT_XCPT_14, RT_LO_U32(uExitInfo1), uExitInfo2);
5424	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, RT_LO_U32(uExitInfo1), uExitInfo2);
5425	return VINF_SUCCESS;
5426	}
5427	#else
5428	case SVM_EXIT_NPF:
5429	#endif
5430	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5431	{
5432	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5433	}
5434
5435	default:
5436	{
5437	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5438	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5439	return VERR_SVM_UNKNOWN_EXIT;
5440	}
5441	}
5442	}
5443	}
5444	/* not reached */
5445
5446	#undef HM_SVM_VMEXIT_NESTED
5447	}
5448	#endif
5449
5450
5451	/**
5452	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5453	*
5454	* @returns VBox status code (informational status codes included).
5455	* @param pVCpu The cross context virtual CPU structure.
5456	* @param pCtx Pointer to the guest-CPU context.
5457	* @param pSvmTransient Pointer to the SVM transient structure.
5458	*/
5459	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5460	{
5461	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5462	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5463
5464	/*
5465	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5466	* normal workloads (for some definition of "normal").
5467	*/
5468	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5469	switch (uExitCode)
5470	{
5471	case SVM_EXIT_NPF:
5472	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5473
5474	case SVM_EXIT_IOIO:
5475	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5476
5477	case SVM_EXIT_RDTSC:
5478	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5479
5480	case SVM_EXIT_RDTSCP:
5481	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5482
5483	case SVM_EXIT_CPUID:
5484	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5485
5486	case SVM_EXIT_XCPT_14: /* X86_XCPT_PF */
5487	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5488
5489	case SVM_EXIT_XCPT_6: /* X86_XCPT_UD */
5490	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5491
5492	case SVM_EXIT_XCPT_16: /* X86_XCPT_MF */
5493	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5494
5495	case SVM_EXIT_XCPT_1: /* X86_XCPT_DB */
5496	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5497
5498	case SVM_EXIT_XCPT_17: /* X86_XCPT_AC */
5499	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5500
5501	case SVM_EXIT_XCPT_3: /* X86_XCPT_BP */
5502	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5503
5504	case SVM_EXIT_MONITOR:
5505	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5506
5507	case SVM_EXIT_MWAIT:
5508	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5509
5510	case SVM_EXIT_HLT:
5511	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5512
5513	case SVM_EXIT_READ_CR0:
5514	case SVM_EXIT_READ_CR3:
5515	case SVM_EXIT_READ_CR4:
5516	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5517
5518	case SVM_EXIT_CR0_SEL_WRITE:
5519	case SVM_EXIT_WRITE_CR0:
5520	case SVM_EXIT_WRITE_CR3:
5521	case SVM_EXIT_WRITE_CR4:
5522	case SVM_EXIT_WRITE_CR8:
5523	{
5524	uint8_t const uCr = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : uExitCode - SVM_EXIT_WRITE_CR0;
5525	Log4(("hmR0SvmHandleExit: Write CR%u\n", uCr)); NOREF(uCr);
5526	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5527	}
5528
5529	case SVM_EXIT_PAUSE:
5530	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5531
5532	case SVM_EXIT_VMMCALL:
5533	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5534
5535	case SVM_EXIT_VINTR:
5536	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5537
5538	case SVM_EXIT_FERR_FREEZE:
5539	return hmR0SvmExitFerrFreeze(pVCpu, pCtx, pSvmTransient);
5540
5541	case SVM_EXIT_INTR:
5542	case SVM_EXIT_NMI:
5543	case SVM_EXIT_XCPT_NMI: /* Shouldn't ever happen, SVM_EXIT_NMI is used instead. */
5544	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5545
5546	case SVM_EXIT_MSR:
5547	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5548
5549	case SVM_EXIT_INVLPG:
5550	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5551
5552	case SVM_EXIT_WBINVD:
5553	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5554
5555	case SVM_EXIT_INVD:
5556	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5557
5558	case SVM_EXIT_RDPMC:
5559	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5560
5561	default:
5562	{
5563	switch (pSvmTransient->u64ExitCode)
5564	{
5565	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5566	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5567	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5568	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5569	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5570
5571	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5572	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5573	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5574	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5575	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5576
5577	case SVM_EXIT_XSETBV:
5578	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5579
5580	case SVM_EXIT_TASK_SWITCH:
5581	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5582
5583	case SVM_EXIT_IRET:
5584	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5585
5586	case SVM_EXIT_SHUTDOWN:
5587	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5588
5589	case SVM_EXIT_SMI:
5590	case SVM_EXIT_INIT:
5591	{
5592	/*
5593	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5594	* If it ever does, we want to know about it so log the exit code and bail.
5595	*/
5596	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5597	}
5598
5599	#ifdef VBOX_WITH_NESTED_HWVIRT
5600	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5601	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5602	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5603	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5604	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5605	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5606	#else
5607	case SVM_EXIT_CLGI:
5608	case SVM_EXIT_STGI:
5609	case SVM_EXIT_VMLOAD:
5610	case SVM_EXIT_VMSAVE:
5611	case SVM_EXIT_INVLPGA:
5612	case SVM_EXIT_VMRUN:
5613	#endif
5614	case SVM_EXIT_RSM:
5615	case SVM_EXIT_SKINIT:
5616	{
5617	hmR0SvmSetPendingXcptUD(pVCpu);
5618	return VINF_SUCCESS;
5619	}
5620
5621	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5622	case SVM_EXIT_XCPT_0: /* #DE */
5623	/* SVM_EXIT_XCPT_1: / / #DB - Handled above. */
5624	/* SVM_EXIT_XCPT_2: / / #NMI - Handled above. */
5625	/* SVM_EXIT_XCPT_3: / / #BP - Handled above. */
5626	case SVM_EXIT_XCPT_4: /* #OF */
5627	case SVM_EXIT_XCPT_5: /* #BR */
5628	/* SVM_EXIT_XCPT_6: / / #UD - Handled above. */
5629	case SVM_EXIT_XCPT_7: /* #NM */
5630	case SVM_EXIT_XCPT_8: /* #DF */
5631	case SVM_EXIT_XCPT_9: /* #CO_SEG_OVERRUN */
5632	case SVM_EXIT_XCPT_10: /* #TS */
5633	case SVM_EXIT_XCPT_11: /* #NP */
5634	case SVM_EXIT_XCPT_12: /* #SS */
5635	case SVM_EXIT_XCPT_13: /* #GP */
5636	/* SVM_EXIT_XCPT_14: / / #PF - Handled above. */
5637	case SVM_EXIT_XCPT_15: /* Reserved. */
5638	/* SVM_EXIT_XCPT_16: / / #MF - Handled above. */
5639	/* SVM_EXIT_XCPT_17: / / #AC - Handled above. */
5640	case SVM_EXIT_XCPT_18: /* #MC */
5641	case SVM_EXIT_XCPT_19: /* #XF */
5642	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5643	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5644	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5645	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5646	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5647
5648	default:
5649	{
5650	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5651	pVCpu->hm.s.u32HMError = uExitCode;
5652	return VERR_SVM_UNKNOWN_EXIT;
5653	}
5654	}
5655	}
5656	}
5657	/* not reached */
5658	}
5659
5660
5661	#ifdef DEBUG
5662	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5663	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5664	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5665
5666	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5667	do \
5668	{ \
5669	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5670	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5671	} while (0)
5672
5673	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5674	do { \
5675	AssertPtr(pVCpu); \
5676	AssertPtr(pCtx); \
5677	AssertPtr(pSvmTransient); \
5678	Assert(ASMIntAreEnabled()); \
5679	HMSVM_ASSERT_PREEMPT_SAFE(); \
5680	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5681	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5682	HMSVM_ASSERT_PREEMPT_SAFE(); \
5683	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5684	HMSVM_ASSERT_PREEMPT_CPUID(); \
5685	} while (0)
5686	#else /* Release builds */
5687	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5688	#endif
5689
5690
5691	/**
5692	* Worker for hmR0SvmInterpretInvlpg().
5693	*
5694	* @return VBox status code.
5695	* @param pVCpu The cross context virtual CPU structure.
5696	* @param pCpu Pointer to the disassembler state.
5697	* @param pCtx The guest CPU context.
5698	*/
5699	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5700	{
5701	DISQPVPARAMVAL Param1;
5702	RTGCPTR GCPtrPage;
5703
5704	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5705	if (RT_FAILURE(rc))
5706	return VERR_EM_INTERPRETER;
5707
5708	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5709	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5710	{
5711	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5712	return VERR_EM_INTERPRETER;
5713
5714	GCPtrPage = Param1.val.val64;
5715	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5716	rc = VBOXSTRICTRC_VAL(rc2);
5717	}
5718	else
5719	{
5720	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5721	rc = VERR_EM_INTERPRETER;
5722	}
5723
5724	return rc;
5725	}
5726
5727
5728	/**
5729	* Interprets INVLPG.
5730	*
5731	* @returns VBox status code.
5732	* @retval VINF_* Scheduling instructions.
5733	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5734	* @retval VERR_* Fatal errors.
5735	*
5736	* @param pVM The cross context VM structure.
5737	* @param pVCpu The cross context virtual CPU structure.
5738	* @param pCtx The guest CPU context.
5739	*
5740	* @remarks Updates the RIP if the instruction was executed successfully.
5741	*/
5742	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5743	{
5744	/* Only allow 32 & 64 bit code. */
5745	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5746	{
5747	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5748	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5749	if ( RT_SUCCESS(rc)
5750	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5751	{
5752	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5753	if (RT_SUCCESS(rc))
5754	pCtx->rip += pDis->cbInstr;
5755	return rc;
5756	}
5757	else
5758	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5759	}
5760	return VERR_EM_INTERPRETER;
5761	}
5762
5763
5764	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5765	/**
5766	* Gets the IEM exception flags for the specified SVM event.
5767	*
5768	* @returns The IEM exception flags.
5769	* @param pEvent Pointer to the SVM event.
5770	*
5771	* @remarks This function currently only constructs flags required for
5772	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5773	* and CR2 aspects of an exception are not included).
5774	*/
5775	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5776	{
5777	uint8_t const uEventType = pEvent->n.u3Type;
5778	uint32_t fIemXcptFlags;
5779	switch (uEventType)
5780	{
5781	case SVM_EVENT_EXCEPTION:
5782	/*
5783	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5784	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5785	*/
5786	if (pEvent->n.u8Vector == X86_XCPT_BP)
5787	{
5788	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5789	break;
5790	}
5791	if (pEvent->n.u8Vector == X86_XCPT_OF)
5792	{
5793	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5794	break;
5795	}
5796	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5797	RT_FALL_THRU();
5798	case SVM_EVENT_NMI:
5799	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5800	break;
5801
5802	case SVM_EVENT_EXTERNAL_IRQ:
5803	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5804	break;
5805
5806	case SVM_EVENT_SOFTWARE_INT:
5807	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5808	break;
5809
5810	default:
5811	fIemXcptFlags = 0;
5812	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5813	break;
5814	}
5815	return fIemXcptFlags;
5816	}
5817
5818	#else
5819	/**
5820	* Determines if an exception is a contributory exception.
5821	*
5822	* Contributory exceptions are ones which can cause double-faults unless the
5823	* original exception was a benign exception. Page-fault is intentionally not
5824	* included here as it's a conditional contributory exception.
5825	*
5826	* @returns @c true if the exception is contributory, @c false otherwise.
5827	* @param uVector The exception vector.
5828	*/
5829	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5830	{
5831	switch (uVector)
5832	{
5833	case X86_XCPT_GP:
5834	case X86_XCPT_SS:
5835	case X86_XCPT_NP:
5836	case X86_XCPT_TS:
5837	case X86_XCPT_DE:
5838	return true;
5839	default:
5840	break;
5841	}
5842	return false;
5843	}
5844	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5845
5846
5847	/**
5848	* Handle a condition that occurred while delivering an event through the guest
5849	* IDT.
5850	*
5851	* @returns VBox status code (informational error codes included).
5852	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5853	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5854	* continue execution of the guest which will delivery the \#DF.
5855	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5856	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5857	*
5858	* @param pVCpu The cross context virtual CPU structure.
5859	* @param pCtx Pointer to the guest-CPU context.
5860	* @param pSvmTransient Pointer to the SVM transient structure.
5861	*
5862	* @remarks No-long-jump zone!!!
5863	*/
5864	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5865	{
5866	int rc = VINF_SUCCESS;
5867	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5868
5869	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5870	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5871	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5872
5873	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5874	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5875	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5876	{
5877	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5878	IEMXCPTRAISE enmRaise;
5879	IEMXCPTRAISEINFO fRaiseInfo;
5880	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5881	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5882	if (fExitIsHwXcpt)
5883	{
5884	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5885	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5886	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5887	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5888	}
5889	else
5890	{
5891	/*
5892	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5893	* end up here.
5894	*
5895	* If the event was:
5896	* - a software interrupt, we can re-execute the instruction which will regenerate
5897	* the event.
5898	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5899	* - a hardware exception or external interrupt, we re-inject it.
5900	*/
5901	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5902	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5903	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5904	else
5905	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5906	}
5907
5908	switch (enmRaise)
5909	{
5910	case IEMXCPTRAISE_CURRENT_XCPT:
5911	case IEMXCPTRAISE_PREV_EVENT:
5912	{
5913	/* For software interrupts, we shall re-execute the instruction. */
5914	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5915	{
5916	RTGCUINTPTR GCPtrFaultAddress = 0;
5917
5918	/* If we are re-injecting an NMI, clear NMI blocking. */
5919	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5920	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5921
5922	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5923	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5924	pSvmTransient->fVectoringPF = true;
5925	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5926	&& uIdtVector == X86_XCPT_PF)
5927	{
5928	/*
5929	* If the previous exception was a #PF, we need to recover the CR2 value.
5930	* This can't happen with shadow paging.
5931	*/
5932	GCPtrFaultAddress = pCtx->cr2;
5933	}
5934
5935	/*
5936	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5937	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5938	*/
5939	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5940	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5941	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5942
5943	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5944	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5945	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5946	}
5947	break;
5948	}
5949
5950	case IEMXCPTRAISE_REEXEC_INSTR:
5951	{
5952	Assert(rc == VINF_SUCCESS);
5953	break;
5954	}
5955
5956	case IEMXCPTRAISE_DOUBLE_FAULT:
5957	{
5958	/*
5959	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5960	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5961	*/
5962	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5963	{
5964	pSvmTransient->fVectoringDoublePF = true;
5965	Assert(rc == VINF_SUCCESS);
5966	}
5967	else
5968	{
5969	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5970	hmR0SvmSetPendingXcptDF(pVCpu);
5971	rc = VINF_HM_DOUBLE_FAULT;
5972	}
5973	break;
5974	}
5975
5976	case IEMXCPTRAISE_TRIPLE_FAULT:
5977	{
5978	rc = VINF_EM_RESET;
5979	break;
5980	}
5981
5982	case IEMXCPTRAISE_CPU_HANG:
5983	{
5984	rc = VERR_EM_GUEST_CPU_HANG;
5985	break;
5986	}
5987
5988	default:
5989	{
5990	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5991	rc = VERR_SVM_IPE_2;
5992	break;
5993	}
5994	}
5995	#else
5996	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5997
5998	typedef enum
5999	{
6000	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
6001	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
6002	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
6003	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
6004	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
6005	} SVMREFLECTXCPT;
6006
6007	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
6008	bool fReflectingNmi = false;
6009	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
6010	{
6011	if (pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31)
6012	{
6013	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0);
6014
6015	#ifdef VBOX_STRICT
6016	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
6017	&& uExitVector == X86_XCPT_PF)
6018	{
6019	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
6020	}
6021	#endif
6022
6023	if ( uIdtVector == X86_XCPT_BP
6024	\|\| uIdtVector == X86_XCPT_OF)
6025	{
6026	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
6027	}
6028	else if ( uExitVector == X86_XCPT_PF
6029	&& uIdtVector == X86_XCPT_PF)
6030	{
6031	pSvmTransient->fVectoringDoublePF = true;
6032	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
6033	}
6034	else if ( uExitVector == X86_XCPT_AC
6035	&& uIdtVector == X86_XCPT_AC)
6036	{
6037	enmReflect = SVMREFLECTXCPT_HANG;
6038	Log4(("IDT: Nested #AC - Bad guest\n"));
6039	}
6040	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
6041	&& hmR0SvmIsContributoryXcpt(uExitVector)
6042	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
6043	\|\| uIdtVector == X86_XCPT_PF))
6044	{
6045	enmReflect = SVMREFLECTXCPT_DF;
6046	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
6047	uIdtVector, uExitVector));
6048	}
6049	else if (uIdtVector == X86_XCPT_DF)
6050	{
6051	enmReflect = SVMREFLECTXCPT_TF;
6052	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
6053	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
6054	}
6055	else
6056	enmReflect = SVMREFLECTXCPT_XCPT;
6057	}
6058	else
6059	{
6060	/*
6061	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
6062	* exception to the guest after handling the #VMEXIT.
6063	*/
6064	enmReflect = SVMREFLECTXCPT_XCPT;
6065	}
6066	}
6067	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
6068	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
6069	{
6070	enmReflect = SVMREFLECTXCPT_XCPT;
6071	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
6072
6073	if (pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31)
6074	{
6075	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0);
6076	if (uExitVector == X86_XCPT_PF)
6077	{
6078	pSvmTransient->fVectoringPF = true;
6079	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
6080	}
6081	}
6082	}
6083	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
6084
6085	switch (enmReflect)
6086	{
6087	case SVMREFLECTXCPT_XCPT:
6088	{
6089	/* If we are re-injecting the NMI, clear NMI blocking. */
6090	if (fReflectingNmi)
6091	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6092
6093	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
6094	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6095	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
6096
6097	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
6098	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
6099	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
6100	break;
6101	}
6102
6103	case SVMREFLECTXCPT_DF:
6104	{
6105	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6106	hmR0SvmSetPendingXcptDF(pVCpu);
6107	rc = VINF_HM_DOUBLE_FAULT;
6108	break;
6109	}
6110
6111	case SVMREFLECTXCPT_TF:
6112	{
6113	rc = VINF_EM_RESET;
6114	break;
6115	}
6116
6117	case SVMREFLECTXCPT_HANG:
6118	{
6119	rc = VERR_EM_GUEST_CPU_HANG;
6120	break;
6121	}
6122
6123	default:
6124	Assert(rc == VINF_SUCCESS);
6125	break;
6126	}
6127	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
6128	}
6129	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6130	NOREF(pCtx);
6131	return rc;
6132	}
6133
6134
6135	/**
6136	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
6137	* supported, otherwise advances the RIP by the number of bytes specified in
6138	* @a cb.
6139	*
6140	* @param pVCpu The cross context virtual CPU structure.
6141	* @param pCtx Pointer to the guest-CPU context.
6142	* @param cb RIP increment value in bytes.
6143	*
6144	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
6145	* when NRIP_SAVE is supported by the CPU, otherwise use
6146	* hmR0SvmAdvanceRipDumb!
6147	*/
6148	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6149	{
6150	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6151	if (fSupportsNextRipSave)
6152	{
6153	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6154	Assert(pVmcb->ctrl.u64NextRIP);
6155	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
6156	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6157	}
6158	else
6159	pCtx->rip += cb;
6160
6161	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6162	}
6163
6164
6165	#ifdef VBOX_WITH_NESTED_HWVIRT
6166	/**
6167	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
6168	* feature. Otherwise, returns the value in @a cbLikely.
6169	*
6170	* @param pVCpu The cross context virtual CPU structure.
6171	* @param pCtx Pointer to the guest-CPU context.
6172	* @param cbLikely The likely instruction length.
6173	*/
6174	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
6175	{
6176	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
6177	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6178	if (fSupportsNextRipSave)
6179	{
6180	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6181	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6182	Assert(cbInstr == cbLikely);
6183	return cbInstr;
6184	}
6185	return cbLikely;
6186	}
6187	#endif
6188
6189
6190	/**
6191	* Advances the guest RIP by the number of bytes specified in @a cb. This does
6192	* not make use of any hardware features to determine the instruction length.
6193	*
6194	* @param pVCpu The cross context virtual CPU structure.
6195	* @param pCtx Pointer to the guest-CPU context.
6196	* @param cb RIP increment value in bytes.
6197	*/
6198	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6199	{
6200	pCtx->rip += cb;
6201	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6202	}
6203	#undef HMSVM_UPDATE_INTR_SHADOW
6204
6205
6206	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6207	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6208	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6209
6210	/** @name \#VMEXIT handlers.
6211	* @{
6212	*/
6213
6214	/**
6215	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6216	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6217	*/
6218	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6219	{
6220	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6221
6222	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6223	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6224	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6225	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6226
6227	/*
6228	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
6229	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
6230	* interrupt it is until the host actually take the interrupt.
6231	*
6232	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
6233	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6234	*/
6235	return VINF_EM_RAW_INTERRUPT;
6236	}
6237
6238
6239	/**
6240	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6241	*/
6242	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6243	{
6244	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6245
6246	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6247	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
6248	int rc = VINF_SUCCESS;
6249	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6250	return rc;
6251	}
6252
6253
6254	/**
6255	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6256	*/
6257	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6258	{
6259	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6260
6261	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6262	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
6263	int rc = VINF_SUCCESS;
6264	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6265	return rc;
6266	}
6267
6268
6269	/**
6270	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6271	*/
6272	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6273	{
6274	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6275	PVM pVM = pVCpu->CTX_SUFF(pVM);
6276	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6277	if (RT_LIKELY(rc == VINF_SUCCESS))
6278	{
6279	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6280	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6281	}
6282	else
6283	{
6284	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6285	rc = VERR_EM_INTERPRETER;
6286	}
6287	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
6288	return rc;
6289	}
6290
6291
6292	/**
6293	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6294	*/
6295	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6296	{
6297	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6298	PVM pVM = pVCpu->CTX_SUFF(pVM);
6299	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6300	if (RT_LIKELY(rc == VINF_SUCCESS))
6301	{
6302	pSvmTransient->fUpdateTscOffsetting = true;
6303	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6304	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6305	}
6306	else
6307	{
6308	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
6309	rc = VERR_EM_INTERPRETER;
6310	}
6311	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
6312	return rc;
6313	}
6314
6315
6316	/**
6317	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6318	*/
6319	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6320	{
6321	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6322	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
6323	if (RT_LIKELY(rc == VINF_SUCCESS))
6324	{
6325	pSvmTransient->fUpdateTscOffsetting = true;
6326	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6327	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6328	}
6329	else
6330	{
6331	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
6332	rc = VERR_EM_INTERPRETER;
6333	}
6334	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
6335	return rc;
6336	}
6337
6338
6339	/**
6340	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6341	*/
6342	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6343	{
6344	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6345	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6346	if (RT_LIKELY(rc == VINF_SUCCESS))
6347	{
6348	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6349	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6350	}
6351	else
6352	{
6353	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6354	rc = VERR_EM_INTERPRETER;
6355	}
6356	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6357	return rc;
6358	}
6359
6360
6361	/**
6362	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6363	*/
6364	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6365	{
6366	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6367	PVM pVM = pVCpu->CTX_SUFF(pVM);
6368	Assert(!pVM->hm.s.fNestedPaging);
6369	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6370
6371	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6372	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6373	if ( fSupportsDecodeAssists
6374	&& fSupportsNextRipSave)
6375	{
6376	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6377	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6378	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6379	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6380	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6381	return VBOXSTRICTRC_VAL(rcStrict);
6382	}
6383
6384	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6385	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6386	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6387	return rc;
6388	}
6389
6390
6391	/**
6392	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6393	*/
6394	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6395	{
6396	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6397
6398	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6399	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6400	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6401	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6402	if (rc != VINF_SUCCESS)
6403	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6404	return rc;
6405	}
6406
6407
6408	/**
6409	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6410	*/
6411	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6412	{
6413	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6414	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6415	if (RT_LIKELY(rc == VINF_SUCCESS))
6416	{
6417	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6418	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6419	}
6420	else
6421	{
6422	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6423	rc = VERR_EM_INTERPRETER;
6424	}
6425	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6426	return rc;
6427	}
6428
6429
6430	/**
6431	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6432	*/
6433	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6434	{
6435	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6436	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6437	int rc = VBOXSTRICTRC_VAL(rc2);
6438	if ( rc == VINF_EM_HALT
6439	\|\| rc == VINF_SUCCESS)
6440	{
6441	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6442
6443	if ( rc == VINF_EM_HALT
6444	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6445	{
6446	rc = VINF_SUCCESS;
6447	}
6448	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6449	}
6450	else
6451	{
6452	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6453	rc = VERR_EM_INTERPRETER;
6454	}
6455	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6456	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6457	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6458	return rc;
6459	}
6460
6461
6462	/**
6463	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6464	* \#VMEXIT.
6465	*/
6466	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6467	{
6468	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6469	return VINF_EM_RESET;
6470	}
6471
6472
6473	/**
6474	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6475	*/
6476	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6477	{
6478	RT_NOREF(pCtx);
6479	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6480	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6481	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6482	RT_NOREF(pVmcb);
6483	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6484	return VERR_SVM_UNEXPECTED_EXIT;
6485	}
6486
6487
6488	/**
6489	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6490	*/
6491	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6492	{
6493	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6494
6495	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6496	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6497
6498	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6499	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6500	if ( fSupportsDecodeAssists
6501	&& fSupportsNextRipSave)
6502	{
6503	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6504	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6505	if (fMovCRx)
6506	{
6507	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6508	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6509	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6510	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6511	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6512	return VBOXSTRICTRC_VAL(rcStrict);
6513	}
6514	/* else: SMSW instruction, fall back below to IEM for this. */
6515	}
6516
6517	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6518	int rc = VBOXSTRICTRC_VAL(rc2);
6519	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6520	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6521	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6522	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6523	return rc;
6524	}
6525
6526
6527	/**
6528	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6529	*/
6530	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6531	{
6532	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6533
6534	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6535	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6536	Assert(iCrReg <= 15);
6537
6538	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6539	bool fDecodedInstr = false;
6540	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6541	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6542	if ( fSupportsDecodeAssists
6543	&& fSupportsNextRipSave)
6544	{
6545	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6546	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6547	if (fMovCRx)
6548	{
6549	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6550	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6551	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6552	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6553	fDecodedInstr = true;
6554	}
6555	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6556	}
6557
6558	if (!fDecodedInstr)
6559	{
6560	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6561	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6562	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6563	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6564	rcStrict = VERR_EM_INTERPRETER;
6565	}
6566
6567	if (rcStrict == VINF_SUCCESS)
6568	{
6569	switch (iCrReg)
6570	{
6571	case 0: /* CR0. */
6572	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6573	break;
6574
6575	case 3: /* CR3. */
6576	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6577	break;
6578
6579	case 4: /* CR4. */
6580	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6581	break;
6582
6583	case 8: /* CR8 (TPR). */
6584	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6585	break;
6586
6587	default:
6588	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6589	pSvmTransient->u64ExitCode, iCrReg));
6590	break;
6591	}
6592	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6593	}
6594	else
6595	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6596	return VBOXSTRICTRC_TODO(rcStrict);
6597	}
6598
6599
6600	/**
6601	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6602	* \#VMEXIT.
6603	*/
6604	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6605	{
6606	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6607	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6608	PVM pVM = pVCpu->CTX_SUFF(pVM);
6609
6610	int rc;
6611	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6612	{
6613	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6614	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6615
6616	/* Handle TPR patching; intercepted LSTAR write. */
6617	if ( pVM->hm.s.fTPRPatchingActive
6618	&& pCtx->ecx == MSR_K8_LSTAR)
6619	{
6620	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6621	{
6622	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6623	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6624	AssertRC(rc2);
6625	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6626	}
6627	rc = VINF_SUCCESS;
6628	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6629	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6630	return rc;
6631	}
6632
6633	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6634	if (fSupportsNextRipSave)
6635	{
6636	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6637	if (RT_LIKELY(rc == VINF_SUCCESS))
6638	{
6639	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6640	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6641	}
6642	else
6643	AssertMsg( rc == VERR_EM_INTERPRETER
6644	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6645	}
6646	else
6647	{
6648	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6649	if (RT_LIKELY(rc == VINF_SUCCESS))
6650	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6651	else
6652	AssertMsg( rc == VERR_EM_INTERPRETER
6653	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6654	}
6655
6656	if (rc == VINF_SUCCESS)
6657	{
6658	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6659	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6660	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6661	{
6662	/*
6663	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6664	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6665	* EMInterpretWrmsr() changes it.
6666	*/
6667	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6668	}
6669	else
6670	{
6671	switch (pCtx->ecx)
6672	{
6673	case MSR_K6_EFER: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR); break;
6674	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6675	case MSR_K8_FS_BASE:
6676	case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
6677	case MSR_IA32_SYSENTER_CS: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6678	case MSR_IA32_SYSENTER_EIP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6679	case MSR_IA32_SYSENTER_ESP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6680	}
6681	}
6682	}
6683	}
6684	else
6685	{
6686	/* MSR Read access. */
6687	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6688	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6689	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6690
6691	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6692	if (fSupportsNextRipSave)
6693	{
6694	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6695	if (RT_LIKELY(rc == VINF_SUCCESS))
6696	{
6697	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6698	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6699	}
6700	else
6701	AssertMsg( rc == VERR_EM_INTERPRETER
6702	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6703	}
6704	else
6705	{
6706	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6707	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6708	{
6709	AssertMsg( rc == VERR_EM_INTERPRETER
6710	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6711	}
6712	/* RIP updated by EMInterpretInstruction(). */
6713	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6714	}
6715	}
6716
6717	/* RIP has been updated by EMInterpret[Rd\|Wr]msr() or EMInterpretInstruction(). */
6718	return rc;
6719	}
6720
6721
6722	/**
6723	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6724	*/
6725	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6726	{
6727	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6728	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6729
6730	/** @todo Stepping with nested-guest. */
6731	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6732	{
6733	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6734	if (pSvmTransient->fWasGuestDebugStateActive)
6735	{
6736	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6737	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6738	return VERR_SVM_UNEXPECTED_EXIT;
6739	}
6740
6741	/*
6742	* Lazy DR0-3 loading.
6743	*/
6744	if (!pSvmTransient->fWasHyperDebugStateActive)
6745	{
6746	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6747	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6748
6749	/* Don't intercept DRx read and writes. */
6750	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6751	pVmcb->ctrl.u16InterceptRdDRx = 0;
6752	pVmcb->ctrl.u16InterceptWrDRx = 0;
6753	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6754
6755	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6756	VMMRZCallRing3Disable(pVCpu);
6757	HM_DISABLE_PREEMPT();
6758
6759	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6760	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6761	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6762
6763	HM_RESTORE_PREEMPT();
6764	VMMRZCallRing3Enable(pVCpu);
6765
6766	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6767	return VINF_SUCCESS;
6768	}
6769	}
6770
6771	/*
6772	* Interpret the read/writing of DRx.
6773	*/
6774	/** @todo Decode assist. */
6775	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6776	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6777	if (RT_LIKELY(rc == VINF_SUCCESS))
6778	{
6779	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6780	/** @todo CPUM should set this flag! */
6781	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6782	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6783	}
6784	else
6785	Assert(rc == VERR_EM_INTERPRETER);
6786	return VBOXSTRICTRC_TODO(rc);
6787	}
6788
6789
6790	/**
6791	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6792	*/
6793	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6794	{
6795	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6796	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6797	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6798	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6799	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6800	return rc;
6801	}
6802
6803
6804	/**
6805	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6806	*/
6807	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6808	{
6809	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6810
6811	/** @todo decode assists... */
6812	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6813	if (rcStrict == VINF_IEM_RAISED_XCPT)
6814	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6815
6816	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6817	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6818	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6819
6820	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6821	return VBOXSTRICTRC_TODO(rcStrict);
6822	}
6823
6824
6825	/**
6826	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6827	*/
6828	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6829	{
6830	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6831
6832	/* I/O operation lookup arrays. */
6833	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6834	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6835	the result (in AL/AX/EAX). */
6836	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6837
6838	PVM pVM = pVCpu->CTX_SUFF(pVM);
6839	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6840
6841	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6842	SVMIOIOEXITINFO IoExitInfo;
6843	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6844	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6845	uint32_t cbValue = s_aIOSize[uIOWidth];
6846	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6847
6848	if (RT_UNLIKELY(!cbValue))
6849	{
6850	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6851	return VERR_EM_INTERPRETER;
6852	}
6853
6854	VBOXSTRICTRC rcStrict;
6855	bool fUpdateRipAlready = false;
6856	if (IoExitInfo.n.u1STR)
6857	{
6858	#ifdef VBOX_WITH_2ND_IEM_STEP
6859	/* INS/OUTS - I/O String instruction. */
6860	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6861	* in EXITINFO1? Investigate once this thing is up and running. */
6862	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6863	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6864	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6865	static IEMMODE const s_aenmAddrMode[8] =
6866	{
6867	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6868	};
6869	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6870	if (enmAddrMode != (IEMMODE)-1)
6871	{
6872	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6873	if (cbInstr <= 15 && cbInstr >= 1)
6874	{
6875	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6876	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6877	{
6878	/* Don't know exactly how to detect whether u3SEG is valid, currently
6879	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6880	2384 Opterons when only checking NRIP. */
6881	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6882	if ( fSupportsNextRipSave
6883	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6884	{
6885	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6886	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6887	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6888	IoExitInfo.n.u3SEG, true /fIoChecked/);
6889	}
6890	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6891	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6892	X86_SREG_DS, true /fIoChecked/);
6893	else
6894	rcStrict = IEMExecOne(pVCpu);
6895	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6896	}
6897	else
6898	{
6899	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6900	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6901	true /fIoChecked/);
6902	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6903	}
6904	}
6905	else
6906	{
6907	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6908	rcStrict = IEMExecOne(pVCpu);
6909	}
6910	}
6911	else
6912	{
6913	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6914	rcStrict = IEMExecOne(pVCpu);
6915	}
6916	fUpdateRipAlready = true;
6917
6918	#else
6919	/* INS/OUTS - I/O String instruction. */
6920	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6921
6922	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6923	* in EXITINFO1? Investigate once this thing is up and running. */
6924
6925	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6926	if (rcStrict == VINF_SUCCESS)
6927	{
6928	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6929	{
6930	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6931	(DISCPUMODE)pDis->uAddrMode, cbValue);
6932	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6933	}
6934	else
6935	{
6936	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6937	(DISCPUMODE)pDis->uAddrMode, cbValue);
6938	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6939	}
6940	}
6941	else
6942	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6943	#endif
6944	}
6945	else
6946	{
6947	/* IN/OUT - I/O instruction. */
6948	Assert(!IoExitInfo.n.u1REP);
6949
6950	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6951	{
6952	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6953	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6954	}
6955	else
6956	{
6957	uint32_t u32Val = 0;
6958	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6959	if (IOM_SUCCESS(rcStrict))
6960	{
6961	/* Save result of I/O IN instr. in AL/AX/EAX. */
6962	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6963	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6964	}
6965	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6966	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6967
6968	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6969	}
6970	}
6971
6972	if (IOM_SUCCESS(rcStrict))
6973	{
6974	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6975	if (!fUpdateRipAlready)
6976	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6977
6978	/*
6979	* If any I/O breakpoints are armed, we need to check if one triggered
6980	* and take appropriate action.
6981	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6982	*/
6983	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6984	* execution engines about whether hyper BPs and such are pending. */
6985	uint32_t const uDr7 = pCtx->dr[7];
6986	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6987	&& X86_DR7_ANY_RW_IO(uDr7)
6988	&& (pCtx->cr4 & X86_CR4_DE))
6989	\|\| DBGFBpIsHwIoArmed(pVM)))
6990	{
6991	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6992	VMMRZCallRing3Disable(pVCpu);
6993	HM_DISABLE_PREEMPT();
6994
6995	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6996	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6997
6998	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6999	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
7000	{
7001	/* Raise #DB. */
7002	pVmcb->guest.u64DR6 = pCtx->dr[6];
7003	pVmcb->guest.u64DR7 = pCtx->dr[7];
7004	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7005	hmR0SvmSetPendingXcptDB(pVCpu);
7006	}
7007	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
7008	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
7009	else if ( rcStrict2 != VINF_SUCCESS
7010	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
7011	rcStrict = rcStrict2;
7012	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
7013
7014	HM_RESTORE_PREEMPT();
7015	VMMRZCallRing3Enable(pVCpu);
7016	}
7017
7018	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7019	}
7020
7021	#ifdef VBOX_STRICT
7022	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
7023	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
7024	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
7025	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
7026	else
7027	{
7028	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
7029	* statuses, that the VMM device and some others may return. See
7030	* IOM_SUCCESS() for guidance. */
7031	AssertMsg( RT_FAILURE(rcStrict)
7032	\|\| rcStrict == VINF_SUCCESS
7033	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
7034	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
7035	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
7036	\|\| rcStrict == VINF_EM_RAW_TO_R3
7037	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
7038	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7039	}
7040	#endif
7041	return VBOXSTRICTRC_TODO(rcStrict);
7042	}
7043
7044
7045	/**
7046	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
7047	*/
7048	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7049	{
7050	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7051	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7052
7053	PVM pVM = pVCpu->CTX_SUFF(pVM);
7054	Assert(pVM->hm.s.fNestedPaging);
7055
7056	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7057
7058	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7059	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7060	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /** @todo Make it more explicit that high bits can be non-zero. */
7061	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7062
7063	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
7064
7065	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7066	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
7067	if ( pVM->hm.s.fTprPatchingAllowed
7068	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7069	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7070	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7071	&& !CPUMIsGuestInLongModeEx(pCtx)
7072	&& !CPUMGetGuestCPL(pVCpu)
7073	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7074	{
7075	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7076	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7077
7078	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7079	{
7080	/* Only attempt to patch the instruction once. */
7081	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7082	if (!pPatch)
7083	return VINF_EM_HM_PATCH_TPR_INSTR;
7084	}
7085	}
7086	#endif
7087
7088	/*
7089	* Determine the nested paging mode.
7090	*/
7091	PGMMODE enmNestedPagingMode;
7092	#if HC_ARCH_BITS == 32
7093	if (CPUMIsGuestInLongModeEx(pCtx))
7094	enmNestedPagingMode = PGMMODE_AMD64_NX;
7095	else
7096	#endif
7097	enmNestedPagingMode = PGMGetHostMode(pVM);
7098
7099	/*
7100	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7101	*/
7102	int rc;
7103	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7104	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7105	{
7106	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
7107	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
7108	if (pVCpu->hm.s.Event.fPending)
7109	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7110
7111	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7112	u32ErrCode);
7113	rc = VBOXSTRICTRC_VAL(rc2);
7114
7115	/*
7116	* If we succeed, resume guest execution.
7117	* If we fail in interpreting the instruction because we couldn't get the guest physical address
7118	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
7119	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
7120	* weird case. See @bugref{6043}.
7121	*/
7122	if ( rc == VINF_SUCCESS
7123	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7124	\|\| rc == VERR_PAGE_NOT_PRESENT)
7125	{
7126	/* Successfully handled MMIO operation. */
7127	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
7128	rc = VINF_SUCCESS;
7129	}
7130	return rc;
7131	}
7132
7133	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7134	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7135	TRPMResetTrap(pVCpu);
7136
7137	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7138
7139	/*
7140	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7141	*/
7142	if ( rc == VINF_SUCCESS
7143	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7144	\|\| rc == VERR_PAGE_NOT_PRESENT)
7145	{
7146	/* We've successfully synced our shadow page tables. */
7147	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7148	rc = VINF_SUCCESS;
7149	}
7150
7151	return rc;
7152	}
7153
7154
7155	/**
7156	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7157	* \#VMEXIT.
7158	*/
7159	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7160	{
7161	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7162	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7163
7164	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7165	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7166	hmR0SvmClearVirtIntrIntercept(pVmcb);
7167
7168	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7169	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7170	return VINF_SUCCESS;
7171	}
7172
7173
7174	/**
7175	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7176	* \#VMEXIT.
7177	*/
7178	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7179	{
7180	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7181
7182	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7183
7184	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7185	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7186	#endif
7187
7188	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7189	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7190	{
7191	/*
7192	* AMD-V provides us with the exception which caused the TS; we collect
7193	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
7194	*/
7195	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
7196	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7197	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7198	}
7199
7200	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7201	* emulation. */
7202	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7203	return VERR_EM_INTERPRETER;
7204	}
7205
7206
7207	/**
7208	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7209	*/
7210	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7211	{
7212	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7213	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
7214
7215	bool fRipUpdated;
7216	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
7217	if (RT_SUCCESS(rcStrict))
7218	{
7219	/* Only update the RIP if we're continuing guest execution and not
7220	in the case of say VINF_GIM_R3_HYPERCALL. */
7221	if ( rcStrict == VINF_SUCCESS
7222	&& !fRipUpdated)
7223	{
7224	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
7225	}
7226
7227	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
7228	we would need to reload the guest changed bits here before VM-entry. */
7229	return VBOXSTRICTRC_VAL(rcStrict);
7230	}
7231
7232	hmR0SvmSetPendingXcptUD(pVCpu);
7233	return VINF_SUCCESS;
7234	}
7235
7236
7237	/**
7238	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7239	*/
7240	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7241	{
7242	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7243	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
7244	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
7245	/** @todo The guest has likely hit a contended spinlock. We might want to
7246	* poke a schedule different guest VCPU. */
7247	return VINF_EM_RAW_INTERRUPT;
7248	}
7249
7250
7251	/**
7252	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7253	* \#VMEXIT.
7254	*/
7255	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7256	{
7257	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7258	Assert(!(pCtx->cr0 & X86_CR0_NE));
7259
7260	Log4(("hmR0SvmExitFerrFreeze: Raising IRQ 13 in response to #FERR\n"));
7261	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7262	}
7263
7264
7265	/**
7266	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7267	*/
7268	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7269	{
7270	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7271
7272	/* Clear NMI blocking. */
7273	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7274
7275	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7276	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7277	hmR0SvmClearIretIntercept(pVmcb);
7278
7279	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7280	return VINF_SUCCESS;
7281	}
7282
7283
7284	/**
7285	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7286	* Conditional \#VMEXIT.
7287	*/
7288	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7289	{
7290	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7291	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7292
7293	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7294
7295	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7296	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7297	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7298	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7299	PVM pVM = pVCpu->CTX_SUFF(pVM);
7300
7301	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7302	if (pVM->hm.s.fNestedPaging)
7303	{
7304	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7305	if (!pSvmTransient->fVectoringDoublePF)
7306	{
7307	/* A genuine guest #PF, reflect it to the guest. */
7308	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7309	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7310	uFaultAddress, u32ErrCode));
7311	}
7312	else
7313	{
7314	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7315	hmR0SvmSetPendingXcptDF(pVCpu);
7316	Log4(("Pending #DF due to vectoring #PF. NP\n"));
7317	}
7318	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7319	return VINF_SUCCESS;
7320	}
7321	#endif
7322
7323	Assert(!pVM->hm.s.fNestedPaging);
7324
7325	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7326	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
7327	if ( pVM->hm.s.fTprPatchingAllowed
7328	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7329	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
7330	&& !CPUMIsGuestInLongModeEx(pCtx)
7331	&& !CPUMGetGuestCPL(pVCpu)
7332	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7333	{
7334	RTGCPHYS GCPhysApicBase;
7335	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7336	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7337
7338	/* Check if the page at the fault-address is the APIC base. */
7339	RTGCPHYS GCPhysPage;
7340	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7341	if ( rc2 == VINF_SUCCESS
7342	&& GCPhysPage == GCPhysApicBase)
7343	{
7344	/* Only attempt to patch the instruction once. */
7345	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7346	if (!pPatch)
7347	return VINF_EM_HM_PATCH_TPR_INSTR;
7348	}
7349	}
7350	#endif
7351
7352	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7353	pCtx->rip, u32ErrCode, pCtx->cr3));
7354
7355	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7356	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7357	if (pSvmTransient->fVectoringPF)
7358	{
7359	Assert(pVCpu->hm.s.Event.fPending);
7360	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7361	}
7362
7363	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7364	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7365
7366	Log4(("#PF rc=%Rrc\n", rc));
7367
7368	if (rc == VINF_SUCCESS)
7369	{
7370	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7371	TRPMResetTrap(pVCpu);
7372	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7373	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7374	return rc;
7375	}
7376	else if (rc == VINF_EM_RAW_GUEST_TRAP)
7377	{
7378	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7379
7380	if (!pSvmTransient->fVectoringDoublePF)
7381	{
7382	/* It's a guest page fault and needs to be reflected to the guest. */
7383	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7384	TRPMResetTrap(pVCpu);
7385	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7386	}
7387	else
7388	{
7389	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7390	TRPMResetTrap(pVCpu);
7391	hmR0SvmSetPendingXcptDF(pVCpu);
7392	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7393	}
7394
7395	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7396	return VINF_SUCCESS;
7397	}
7398
7399	TRPMResetTrap(pVCpu);
7400	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7401	return rc;
7402	}
7403
7404
7405	/**
7406	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7407	* Conditional \#VMEXIT.
7408	*/
7409	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7410	{
7411	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7412	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7413
7414	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7415	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7416	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7417
7418	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7419	if (pVCpu->hm.s.fGIMTrapXcptUD)
7420	{
7421	uint8_t cbInstr = 0;
7422	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7423	if (rcStrict == VINF_SUCCESS)
7424	{
7425	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7426	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7427	rc = VINF_SUCCESS;
7428	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7429	}
7430	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7431	rc = VINF_SUCCESS;
7432	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7433	rc = VINF_GIM_R3_HYPERCALL;
7434	else
7435	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7436	}
7437
7438	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7439	if (RT_FAILURE(rc))
7440	{
7441	hmR0SvmSetPendingXcptUD(pVCpu);
7442	rc = VINF_SUCCESS;
7443	}
7444
7445	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7446	return rc;
7447	}
7448
7449
7450	/**
7451	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7452	* Conditional \#VMEXIT.
7453	*/
7454	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7455	{
7456	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7457
7458	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7459	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7460	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7461
7462	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7463
7464	if (!(pCtx->cr0 & X86_CR0_NE))
7465	{
7466	PVM pVM = pVCpu->CTX_SUFF(pVM);
7467	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7468	unsigned cbOp;
7469	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7470	if (RT_SUCCESS(rc))
7471	{
7472	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7473	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7474	if (RT_SUCCESS(rc))
7475	pCtx->rip += cbOp;
7476	}
7477	else
7478	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7479	return rc;
7480	}
7481
7482	hmR0SvmSetPendingXcptMF(pVCpu);
7483	return VINF_SUCCESS;
7484	}
7485
7486
7487	/**
7488	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7489	* \#VMEXIT.
7490	*/
7491	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7492	{
7493	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7494
7495	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7496	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7497	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7498	{
7499	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7500	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7501	}
7502
7503	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7504
7505	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7506	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7507	PVM pVM = pVCpu->CTX_SUFF(pVM);
7508	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7509	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7510	if (rc == VINF_EM_RAW_GUEST_TRAP)
7511	{
7512	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7513	if (CPUMIsHyperDebugStateActive(pVCpu))
7514	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7515
7516	/* Reflect the exception back to the guest. */
7517	hmR0SvmSetPendingXcptDB(pVCpu);
7518	rc = VINF_SUCCESS;
7519	}
7520
7521	/*
7522	* Update DR6.
7523	*/
7524	if (CPUMIsHyperDebugStateActive(pVCpu))
7525	{
7526	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7527	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7528	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7529	}
7530	else
7531	{
7532	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7533	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7534	}
7535
7536	return rc;
7537	}
7538
7539
7540	/**
7541	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7542	* Conditional \#VMEXIT.
7543	*/
7544	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7545	{
7546	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7547
7548	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7549	* shutdown VMEXIT. */
7550	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7551
7552	SVMEVENT Event;
7553	Event.u = 0;
7554	Event.n.u1Valid = 1;
7555	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7556	Event.n.u8Vector = X86_XCPT_AC;
7557	Event.n.u1ErrorCodeValid = 1;
7558	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7559	return VINF_SUCCESS;
7560	}
7561
7562
7563	/**
7564	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7565	* Conditional \#VMEXIT.
7566	*/
7567	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7568	{
7569	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7570
7571	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7572
7573	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7574	if (rc == VINF_EM_RAW_GUEST_TRAP)
7575	{
7576	SVMEVENT Event;
7577	Event.u = 0;
7578	Event.n.u1Valid = 1;
7579	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7580	Event.n.u8Vector = X86_XCPT_BP;
7581	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7582	}
7583
7584	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7585	return rc;
7586	}
7587
7588
7589	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
7590	/**
7591	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7592	*/
7593	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7594	{
7595	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7596
7597	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7598
7599	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7600	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7601	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7602	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7603	Assert(uVector <= X86_XCPT_LAST);
7604	Log4(("hmR0SvmExitXcptGeneric: uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7605
7606	SVMEVENT Event;
7607	Event.u = 0;
7608	Event.n.u1Valid = 1;
7609	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7610	Event.n.u8Vector = uVector;
7611	switch (uVector)
7612	{
7613	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7614	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7615	case X86_XCPT_DF:
7616	case X86_XCPT_TS:
7617	case X86_XCPT_NP:
7618	case X86_XCPT_SS:
7619	case X86_XCPT_GP:
7620	case X86_XCPT_AC:
7621	{
7622	Event.n.u1ErrorCodeValid = 1;
7623	Event.n.u32ErrorCode = uErrCode;
7624	break;
7625	}
7626	}
7627
7628	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7629	return VINF_SUCCESS;
7630	}
7631	#endif
7632
7633	#ifdef VBOX_WITH_NESTED_HWVIRT
7634	/**
7635	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7636	* (SVM_EXIT_XCPT_14). Conditional \#VMEXIT.
7637	*/
7638	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7639	{
7640	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7641
7642	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7643
7644	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7645	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7646	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7647	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7648
7649	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7650	pCtx->rip, u32ErrCode, pCtx->cr3));
7651
7652	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7653	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7654	if (pSvmTransient->fVectoringPF)
7655	{
7656	Assert(pVCpu->hm.s.Event.fPending);
7657	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7658	}
7659
7660	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7661
7662	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7663	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7664
7665	Log4(("#PFNested: rc=%Rrc\n", rc));
7666
7667	if (rc == VINF_SUCCESS)
7668	{
7669	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7670	TRPMResetTrap(pVCpu);
7671	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7672	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7673	return rc;
7674	}
7675
7676	if (rc == VINF_EM_RAW_GUEST_TRAP)
7677	{
7678	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7679
7680	if (!pSvmTransient->fVectoringDoublePF)
7681	{
7682	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7683	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7684	TRPMResetTrap(pVCpu);
7685	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7686	}
7687	else
7688	{
7689	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7690	TRPMResetTrap(pVCpu);
7691	hmR0SvmSetPendingXcptDF(pVCpu);
7692	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7693	}
7694
7695	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7696	return VINF_SUCCESS;
7697	}
7698
7699	TRPMResetTrap(pVCpu);
7700	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7701	return rc;
7702	}
7703
7704
7705	/**
7706	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7707	*/
7708	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7709	{
7710	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7711
7712	#ifdef VBOX_STRICT
7713	PCSVMVMCB pVmcbTmp = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7714	Assert(pVmcbTmp);
7715	Assert(!pVmcbTmp->ctrl.IntCtrl.n.u1VGifEnable);
7716	RT_NOREF(pVmcbTmp);
7717	#endif
7718
7719	/** @todo Stat. */
7720	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7721	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7722	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7723	return VBOXSTRICTRC_VAL(rcStrict);
7724	}
7725
7726
7727	/**
7728	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7729	*/
7730	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7731	{
7732	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7733
7734	#ifdef VBOX_STRICT
7735	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7736	Assert(pVmcb);
7737	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7738	RT_NOREF(pVmcb);
7739	#endif
7740
7741	/** @todo Stat. */
7742	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7743	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7744	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7745	return VBOXSTRICTRC_VAL(rcStrict);
7746	}
7747
7748
7749	/**
7750	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7751	*/
7752	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7753	{
7754	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7755
7756	#ifdef VBOX_STRICT
7757	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7758	Assert(pVmcb);
7759	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7760	RT_NOREF(pVmcb);
7761	#endif
7762
7763	/** @todo Stat. */
7764	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7765	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7766	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7767	if (rcStrict == VINF_SUCCESS)
7768	{
7769	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7770	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7771	\| HM_CHANGED_GUEST_TR
7772	\| HM_CHANGED_GUEST_LDTR);
7773	}
7774	return VBOXSTRICTRC_VAL(rcStrict);
7775	}
7776
7777
7778	/**
7779	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7780	*/
7781	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7782	{
7783	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7784
7785	#ifdef VBOX_STRICT
7786	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7787	Assert(pVmcb);
7788	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7789	RT_NOREF(pVmcb);
7790	#endif
7791
7792	/** @todo Stat. */
7793	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7794	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7795	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7796	return VBOXSTRICTRC_VAL(rcStrict);
7797	}
7798
7799
7800	/**
7801	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7802	*/
7803	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7804	{
7805	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7806	/** @todo Stat. */
7807	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7808	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7809	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7810	return VBOXSTRICTRC_VAL(rcStrict);
7811	}
7812
7813
7814	/**
7815	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7816	*/
7817	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7818	{
7819	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7820	/** @todo Stat. */
7821	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7822	#if 0
7823	VBOXSTRICTRC rcStrict;
7824	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7825	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7826	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7827	if (rcStrict == VINF_SUCCESS)
7828	{
7829	rcStrict = VINF_SVM_VMRUN;
7830	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7831	}
7832	return VBOXSTRICTRC_VAL(rcStrict);
7833	#endif
7834	return VERR_EM_INTERPRETER;
7835	}
7836
7837
7838	/**
7839	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7840	* Unconditional \#VMEXIT.
7841	*/
7842	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7843	{
7844	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7845
7846	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7847	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7848	* shutdown VMEXIT. */
7849	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7850	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7851	{
7852	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7853	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7854	}
7855
7856	hmR0SvmSetPendingXcptDB(pVCpu);
7857	return VINF_SUCCESS;
7858	}
7859
7860
7861	/**
7862	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7863	* Conditional \#VMEXIT.
7864	*/
7865	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7866	{
7867	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7868
7869	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7870	* shutdown VMEXIT. */
7871	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7872
7873	SVMEVENT Event;
7874	Event.u = 0;
7875	Event.n.u1Valid = 1;
7876	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7877	Event.n.u8Vector = X86_XCPT_BP;
7878	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7879	return VINF_SUCCESS;
7880	}
7881
7882	#endif /* VBOX_WITH_NESTED_HWVIRT */
7883
7884
7885	/** @} */
7886

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 71875

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