HMSVMR0.cpp@ 46304

Last change on this file since 46304 was 46304, checked in by vboxsync, 12 years ago
VMM/HM: AMD-V bits and clean up.
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1	/* $Id: HMSVMR0.cpp 46304 2013-05-29 09:13:19Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21
22
23	/*******************************************************************************
24	* Internal Functions *
25	*******************************************************************************/
26
27
28	/*******************************************************************************
29	* Defined Constants And Macros *
30	*******************************************************************************/
31
32
33	/*******************************************************************************
34	* Global Variables *
35	*******************************************************************************/
36	/** Ring-0 memory object for the IO bitmap. */
37	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
38	/** Physical address of the IO bitmap. */
39	RTHCPHYS g_HCPhysIOBitmap = 0;
40	/** Virtual address of the IO bitmap. */
41	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
42
43
44	/**
45	* Sets up and activates AMD-V on the current CPU.
46	*
47	* @returns VBox status code.
48	* @param pCpu Pointer to the CPU info struct.
49	* @param pVM Pointer to the VM (can be NULL after a resume!).
50	* @param pvCpuPage Pointer to the global CPU page.
51	* @param HCPhysCpuPage Physical address of the global CPU page.
52	*/
53	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
54	{
55	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
56	AssertReturn( HCPhysCpuPage
57	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
58	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
59
60	/*
61	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
62	*/
63	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
64	if (u64HostEfer & MSR_K6_EFER_SVME)
65	{
66	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
67	if ( pVM
68	&& pVM->hm.s.svm.fIgnoreInUseError)
69	{
70	pCpu->fIgnoreAMDVInUseError = true;
71	}
72
73	if (!pCpu->fIgnoreAMDVInUseError)
74	return VERR_SVM_IN_USE;
75	}
76
77	/* Turn on AMD-V in the EFER MSR. */
78	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
79
80	/* Write the physical page address where the CPU will store the host state while executing the VM. */
81	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
82
83	/*
84	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
85	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
86	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
87	* to flush the TLB with before using a new ASID.
88	*/
89	pCpu->fFlushAsidBeforeUse = true;
90
91	/*
92	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
93	*/
94	++pCpu->cTlbFlushes;
95
96	return VINF_SUCCESS;
97	}
98
99
100	/**
101	* Deactivates AMD-V on the current CPU.
102	*
103	* @returns VBox status code.
104	* @param pCpu Pointer to the CPU info struct.
105	* @param pvCpuPage Pointer to the global CPU page.
106	* @param HCPhysCpuPage Physical address of the global CPU page.
107	*/
108	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
109	{
110	AssertReturn( HCPhysCpuPage
111	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
112	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
113	NOREF(pCpu);
114
115	/* Turn off AMD-V in the EFER MSR if AMD-V is active. */
116	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
117	if (u64HostEfer & MSR_K6_EFER_SVME)
118	{
119	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
120
121	/* Invalidate host state physical address. */
122	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
123	}
124
125	return VINF_SUCCESS;
126	}
127
128
129	/**
130	* Does global AMD-V initialization (called during module initialization).
131	*
132	* @returns VBox status code.
133	*/
134	VMMR0DECL(int) SVMR0GlobalInit(void)
135	{
136	/*
137	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
138	* once globally here instead of per-VM.
139	*/
140	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
141	if (RT_FAILURE(rc))
142	return rc;
143
144	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
145	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
146
147	/* Set all bits to intercept all IO accesses. */
148	ASMMemFill32(pVM->hm.s.svm.pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
149	}
150
151
152	/**
153	* Does global VT-x termination (called during module termination).
154	*/
155	VMMR0DECL(void) SVMR0GlobalTerm(void)
156	{
157	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
158	{
159	RTR0MemObjFree(pVM->hm.s.svm.hMemObjIOBitmap, false /* fFreeMappings */);
160	g_pvIOBitmap = NULL;
161	g_HCPhysIOBitmap = 0;
162	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
163	}
164	}
165
166
167	/**
168	* Frees any allocated per-VCPU structures for a VM.
169	*
170	* @param pVM Pointer to the VM.
171	*/
172	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
173	{
174	for (uint32_t i = 0; i < pVM->cCpus; i++)
175	{
176	PVMCPU pVCpu = &pVM->aCpus[i];
177
178	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
179	{
180	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
181	pVCpu->hm.s.svm.pvVmcbHost = 0;
182	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
183	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
184	}
185
186	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
187	{
188	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
189	pVCpu->hm.s.svm.pvVmcb = 0;
190	pVCpu->hm.s.svm.HCPhysVmcb = 0;
191	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
192	}
193
194	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
195	{
196	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
197	pVCpu->hm.s.svm.pvMsrBitmap = 0;
198	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
199	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
200	}
201	}
202	}
203
204
205	/**
206	* Does per-VM AMD-V initialization.
207	*
208	* @returns VBox status code.
209	* @param pVM Pointer to the VM.
210	*/
211	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
212	{
213	int rc;
214
215	/* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch. */
216	uint32_t u32Family;
217	uint32_t u32Model;
218	uint32_t u32Stepping;
219	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
220	{
221	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
222	pVM->hm.s.svm.fAlwaysFlushTLB = true;
223	}
224
225	/* Initialize the memory objects up-front so we can cleanup on allocation failures properly. */
226	for (uint32_t i = 0; i < pVM->cCpus; i++)
227	{
228	PVMCPU pVCpu = &pVM->aCpus[i];
229	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
230	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
231	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
232	}
233
234	/* Allocate a VMCB for each VCPU. */
235	for (uint32_t i = 0; i < pVM->cCpus; i++)
236	{
237	/* Allocate one page for the host context */
238	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
239	if (RT_FAILURE(rc))
240	goto failure_cleanup;
241
242	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
243	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0);
244	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
245	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
246
247	/* Allocate one page for the VM control block (VMCB). */
248	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
249	if (RT_FAILURE(rc))
250	goto failure_cleanup;
251
252	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
253	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0);
254	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
255	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
256
257	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
258	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
259	if (RT_FAILURE(rc))
260	failure_cleanup;
261
262	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
263	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0);
264	/* Set all bits to intercept all MSR accesses. */
265	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
266	}
267
268	return VINF_SUCCESS;
269
270	failure_cleanup:
271	hmR0SvmFreeVMStructs(pVM);
272	return rc;
273	}
274
275
276	/**
277	* Does per-VM AMD-V termination.
278	*
279	* @returns VBox status code.
280	* @param pVM Pointer to the VM.
281	*/
282	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
283	{
284	hmR0SvmFreeVMStructs(pVM);
285	return VINF_SUCCESS;
286	}
287
288
289

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 46304

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