HMSVMR0.cpp@ 46336

Last change on this file since 46336 was 46310, checked in by vboxsync, 12 years ago
VMM/HM: AMD-V bits. Bring VMCB layout up to latest spec.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 11.5 KB

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1	/* $Id: HMSVMR0.cpp 46310 2013-05-29 12:52:37Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21
22	#ifdef DEBUG_ramshankar
23	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
24	# define HMSVM_ALWAYS_TRAP_PF
25	#endif
26
27	/*******************************************************************************
28	* Internal Functions *
29	*******************************************************************************/
30
31
32	/*******************************************************************************
33	* Defined Constants And Macros *
34	*******************************************************************************/
35
36
37	/*******************************************************************************
38	* Global Variables *
39	*******************************************************************************/
40	/** Ring-0 memory object for the IO bitmap. */
41	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
42	/** Physical address of the IO bitmap. */
43	RTHCPHYS g_HCPhysIOBitmap = 0;
44	/** Virtual address of the IO bitmap. */
45	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
46
47
48	/**
49	* Sets up and activates AMD-V on the current CPU.
50	*
51	* @returns VBox status code.
52	* @param pCpu Pointer to the CPU info struct.
53	* @param pVM Pointer to the VM (can be NULL after a resume!).
54	* @param pvCpuPage Pointer to the global CPU page.
55	* @param HCPhysCpuPage Physical address of the global CPU page.
56	*/
57	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
58	{
59	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
60	AssertReturn( HCPhysCpuPage
61	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
62	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
63
64	/*
65	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
66	*/
67	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
68	if (u64HostEfer & MSR_K6_EFER_SVME)
69	{
70	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
71	if ( pVM
72	&& pVM->hm.s.svm.fIgnoreInUseError)
73	{
74	pCpu->fIgnoreAMDVInUseError = true;
75	}
76
77	if (!pCpu->fIgnoreAMDVInUseError)
78	return VERR_SVM_IN_USE;
79	}
80
81	/* Turn on AMD-V in the EFER MSR. */
82	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
83
84	/* Write the physical page address where the CPU will store the host state while executing the VM. */
85	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
86
87	/*
88	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
89	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
90	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
91	* to flush the TLB with before using a new ASID.
92	*/
93	pCpu->fFlushAsidBeforeUse = true;
94
95	/*
96	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
97	*/
98	++pCpu->cTlbFlushes;
99
100	return VINF_SUCCESS;
101	}
102
103
104	/**
105	* Deactivates AMD-V on the current CPU.
106	*
107	* @returns VBox status code.
108	* @param pCpu Pointer to the CPU info struct.
109	* @param pvCpuPage Pointer to the global CPU page.
110	* @param HCPhysCpuPage Physical address of the global CPU page.
111	*/
112	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
113	{
114	AssertReturn( HCPhysCpuPage
115	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
116	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
117	NOREF(pCpu);
118
119	/* Turn off AMD-V in the EFER MSR if AMD-V is active. */
120	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
121	if (u64HostEfer & MSR_K6_EFER_SVME)
122	{
123	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
124
125	/* Invalidate host state physical address. */
126	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
127	}
128
129	return VINF_SUCCESS;
130	}
131
132
133	/**
134	* Does global AMD-V initialization (called during module initialization).
135	*
136	* @returns VBox status code.
137	*/
138	VMMR0DECL(int) SVMR0GlobalInit(void)
139	{
140	/*
141	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
142	* once globally here instead of per-VM.
143	*/
144	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
145	if (RT_FAILURE(rc))
146	return rc;
147
148	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
149	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
150
151	/* Set all bits to intercept all IO accesses. */
152	ASMMemFill32(pVM->hm.s.svm.pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
153	}
154
155
156	/**
157	* Does global VT-x termination (called during module termination).
158	*/
159	VMMR0DECL(void) SVMR0GlobalTerm(void)
160	{
161	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
162	{
163	RTR0MemObjFree(pVM->hm.s.svm.hMemObjIOBitmap, false /* fFreeMappings */);
164	g_pvIOBitmap = NULL;
165	g_HCPhysIOBitmap = 0;
166	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
167	}
168	}
169
170
171	/**
172	* Frees any allocated per-VCPU structures for a VM.
173	*
174	* @param pVM Pointer to the VM.
175	*/
176	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
177	{
178	for (uint32_t i = 0; i < pVM->cCpus; i++)
179	{
180	PVMCPU pVCpu = &pVM->aCpus[i];
181
182	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
183	{
184	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
185	pVCpu->hm.s.svm.pvVmcbHost = 0;
186	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
187	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
188	}
189
190	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
191	{
192	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
193	pVCpu->hm.s.svm.pvVmcb = 0;
194	pVCpu->hm.s.svm.HCPhysVmcb = 0;
195	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
196	}
197
198	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
199	{
200	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
201	pVCpu->hm.s.svm.pvMsrBitmap = 0;
202	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
203	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
204	}
205	}
206	}
207
208
209	/**
210	* Does per-VM AMD-V initialization.
211	*
212	* @returns VBox status code.
213	* @param pVM Pointer to the VM.
214	*/
215	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
216	{
217	int rc = VERR_INTERNAL_ERROR_5;
218
219	/* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch. */
220	uint32_t u32Family;
221	uint32_t u32Model;
222	uint32_t u32Stepping;
223	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
224	{
225	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
226	pVM->hm.s.svm.fAlwaysFlushTLB = true;
227	}
228
229	/* Initialize the memory objects up-front so we can cleanup on allocation failures properly. */
230	for (uint32_t i = 0; i < pVM->cCpus; i++)
231	{
232	PVMCPU pVCpu = &pVM->aCpus[i];
233	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
234	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
235	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
236	}
237
238	/* Allocate a VMCB for each VCPU. */
239	for (uint32_t i = 0; i < pVM->cCpus; i++)
240	{
241	/* Allocate one page for the host context */
242	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
243	if (RT_FAILURE(rc))
244	goto failure_cleanup;
245
246	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
247	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
248	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
249	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
250
251	/* Allocate one page for the VM control block (VMCB). */
252	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
253	if (RT_FAILURE(rc))
254	goto failure_cleanup;
255
256	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
257	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
258	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
259	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
260
261	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
262	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
263	if (RT_FAILURE(rc))
264	failure_cleanup;
265
266	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
267	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
268	/* Set all bits to intercept all MSR accesses. */
269	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
270	}
271
272	return VINF_SUCCESS;
273
274	failure_cleanup:
275	hmR0SvmFreeVMStructs(pVM);
276	return rc;
277	}
278
279
280	/**
281	* Does per-VM AMD-V termination.
282	*
283	* @returns VBox status code.
284	* @param pVM Pointer to the VM.
285	*/
286	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
287	{
288	hmR0SvmFreeVMStructs(pVM);
289	return VINF_SUCCESS;
290	}
291
292
293	/**
294	* Sets up AMD-V for the specified VM.
295	* This function is only called once per-VM during initalization.
296	*
297	* @returns VBox status code.
298	* @param pVM Pointer to the VM.
299	*/
300	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
301	{
302	int rc = VINF_SUCCESS;
303
304	AssertReturn(pVM, VERR_INVALID_PARAMETER);
305	Assert(pVM->hm.s.svm.fSupported);
306
307	for (uint32_t i = 0; i < pVM->cCpus; i++)
308	{
309	PVMCPU pVCpu = &pVM->aCpus[i];
310	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
311
312	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
313
314	/* Intercept traps. */
315	#ifdef HMSVM_ALWAYS_TRAP_PF
316	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
317	#endif
318	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
319	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_BP)
320	\| RT_BIT(X86_XCPT_DB)
321	\| RT_BIT(X86_XCPT_DE)
322	\| RT_BIT(X86_XCPT_UD)
323	\| RT_BIT(X86_XCPT_NP)
324	\| RT_BIT(X86_XCPT_SS)
325	\| RT_BIT(X86_XCPT_GP)
326	\| RT_BIT(X86_XCPT_MF)
327	\| RT_BIT(X86_XCPT_PF);
328	#endif
329
330	/* -XXX- todo. */
331	}
332
333	return rc;
334	}
335

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 46336

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