HMSVMR0.cpp@ 46444

Last change on this file since 46444 was 46444, checked in by vboxsync, 12 years ago
VMM/HMSVMR0: AMD-V bits.
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1	/* $Id: HMSVMR0.cpp 46444 2013-06-07 17:02:46Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21
22	#ifdef DEBUG_ramshankar
23	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
24	# define HMSVM_ALWAYS_TRAP_PF
25	#endif
26
27
28	/*******************************************************************************
29	* Defined Constants And Macros *
30	*******************************************************************************/
31	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
32	*
33	* The CPU format of the segment attribute is described in X86DESCATTRBITS
34	* which is 16-bits (i.e. includes 4 bits of the segment limit).
35	*
36	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
37	* only the attribute bits and nothing else). Upper 4-bits are unused.
38	*
39	* @{ */
40	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) (a & 0xff) \| ((a & 0xf000) >> 4)
41	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) (a & 0xff) \| ((a & 0x0f00) << 4)
42	/** @} */
43
44	/** @name Macros for loading, storing segment registers to/from the VMCB.
45	* @{ */
46	#define HMSVM_LOAD_SEG_REG(REG, reg) \
47	do \
48	{ \
49	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
50	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
51	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
52	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
53	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
54	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
55	} while (0)
56
57	#define HMSVM_SAVE_SEG_REG(REG, reg) \
58	do \
59	{ \
60	pCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
61	pCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
62	pCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
63	pCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
64	pCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
65	pCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
66	} while (0)
67	/** @} */
68
69	/**
70	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
71	*/
72	typedef enum SVMMSREXITREAD
73	{
74	/** Reading this MSR causes a VM-exit. */
75	SVMMSREXIT_INTERCEPT_READ = 0xb,
76	/** Reading this MSR does not cause a VM-exit. */
77	SVMMSREXIT_PASSTHRU_READ
78	} VMXMSREXITREAD;
79
80	/**
81	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
82	*/
83	typedef enum SVMMSREXITWRITE
84	{
85	/** Writing to this MSR causes a VM-exit. */
86	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
87	/** Writing to this MSR does not cause a VM-exit. */
88	SVMMSREXIT_PASSTHRU_WRITE
89	} VMXMSREXITWRITE;
90
91
92	/*******************************************************************************
93	* Internal Functions *
94	*******************************************************************************/
95	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
96
97
98	/*******************************************************************************
99	* Global Variables *
100	*******************************************************************************/
101	/** Ring-0 memory object for the IO bitmap. */
102	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
103	/** Physical address of the IO bitmap. */
104	RTHCPHYS g_HCPhysIOBitmap = 0;
105	/** Virtual address of the IO bitmap. */
106	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
107
108
109	/**
110	* Sets up and activates AMD-V on the current CPU.
111	*
112	* @returns VBox status code.
113	* @param pCpu Pointer to the CPU info struct.
114	* @param pVM Pointer to the VM (can be NULL after a resume!).
115	* @param pvCpuPage Pointer to the global CPU page.
116	* @param HCPhysCpuPage Physical address of the global CPU page.
117	*/
118	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
119	{
120	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
121	AssertReturn( HCPhysCpuPage
122	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
123	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
124
125	/*
126	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
127	*/
128	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
129	if (u64HostEfer & MSR_K6_EFER_SVME)
130	{
131	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
132	if ( pVM
133	&& pVM->hm.s.svm.fIgnoreInUseError)
134	{
135	pCpu->fIgnoreAMDVInUseError = true;
136	}
137
138	if (!pCpu->fIgnoreAMDVInUseError)
139	return VERR_SVM_IN_USE;
140	}
141
142	/* Turn on AMD-V in the EFER MSR. */
143	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
144
145	/* Write the physical page address where the CPU will store the host state while executing the VM. */
146	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
147
148	/*
149	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
150	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
151	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
152	* to flush the TLB with before using a new ASID.
153	*/
154	pCpu->fFlushAsidBeforeUse = true;
155
156	/*
157	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
158	*/
159	++pCpu->cTlbFlushes;
160
161	return VINF_SUCCESS;
162	}
163
164
165	/**
166	* Deactivates AMD-V on the current CPU.
167	*
168	* @returns VBox status code.
169	* @param pCpu Pointer to the CPU info struct.
170	* @param pvCpuPage Pointer to the global CPU page.
171	* @param HCPhysCpuPage Physical address of the global CPU page.
172	*/
173	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
174	{
175	AssertReturn( HCPhysCpuPage
176	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
177	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
178	NOREF(pCpu);
179
180	/* Turn off AMD-V in the EFER MSR if AMD-V is active. */
181	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
182	if (u64HostEfer & MSR_K6_EFER_SVME)
183	{
184	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
185
186	/* Invalidate host state physical address. */
187	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
188	}
189
190	return VINF_SUCCESS;
191	}
192
193
194	/**
195	* Does global AMD-V initialization (called during module initialization).
196	*
197	* @returns VBox status code.
198	*/
199	VMMR0DECL(int) SVMR0GlobalInit(void)
200	{
201	/*
202	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
203	* once globally here instead of per-VM.
204	*/
205	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
206	if (RT_FAILURE(rc))
207	return rc;
208
209	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
210	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
211
212	/* Set all bits to intercept all IO accesses. */
213	ASMMemFill32(pVM->hm.s.svm.pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
214	}
215
216
217	/**
218	* Does global VT-x termination (called during module termination).
219	*/
220	VMMR0DECL(void) SVMR0GlobalTerm(void)
221	{
222	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
223	{
224	RTR0MemObjFree(pVM->hm.s.svm.hMemObjIOBitmap, false /* fFreeMappings */);
225	g_pvIOBitmap = NULL;
226	g_HCPhysIOBitmap = 0;
227	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
228	}
229	}
230
231
232	/**
233	* Frees any allocated per-VCPU structures for a VM.
234	*
235	* @param pVM Pointer to the VM.
236	*/
237	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
238	{
239	for (uint32_t i = 0; i < pVM->cCpus; i++)
240	{
241	PVMCPU pVCpu = &pVM->aCpus[i];
242	AssertPtr(pVCpu);
243
244	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
245	{
246	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
247	pVCpu->hm.s.svm.pvVmcbHost = 0;
248	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
249	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
250	}
251
252	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
253	{
254	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
255	pVCpu->hm.s.svm.pvVmcb = 0;
256	pVCpu->hm.s.svm.HCPhysVmcb = 0;
257	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
258	}
259
260	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
261	{
262	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
263	pVCpu->hm.s.svm.pvMsrBitmap = 0;
264	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
265	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
266	}
267	}
268	}
269
270
271	/**
272	* Does per-VM AMD-V initialization.
273	*
274	* @returns VBox status code.
275	* @param pVM Pointer to the VM.
276	*/
277	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
278	{
279	int rc = VERR_INTERNAL_ERROR_5;
280
281	/*
282	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
283	*/
284	uint32_t u32Family;
285	uint32_t u32Model;
286	uint32_t u32Stepping;
287	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
288	{
289	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
290	pVM->hm.s.svm.fAlwaysFlushTLB = true;
291	}
292
293	/*
294	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
295	*/
296	for (VMCPUID i = 0; i < pVM->cCpus; i++)
297	{
298	PVMCPU pVCpu = &pVM->aCpus[i];
299	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
300	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
301	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
302	}
303
304	for (VMCPUID i = 0; i < pVM->cCpus; i++)
305	{
306	/*
307	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
308	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
309	*/
310	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
311	if (RT_FAILURE(rc))
312	goto failure_cleanup;
313
314	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
315	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
316	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
317	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
318
319	/*
320	* Allocate one page for the guest-state VMCB.
321	*/
322	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
323	if (RT_FAILURE(rc))
324	goto failure_cleanup;
325
326	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
327	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
328	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
329	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
330
331	/*
332	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
333	* SVM to not require one.
334	*/
335	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
336	if (RT_FAILURE(rc))
337	failure_cleanup;
338
339	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
340	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
341	/* Set all bits to intercept all MSR accesses (changed later on). */
342	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
343	}
344
345	return VINF_SUCCESS;
346
347	failure_cleanup:
348	hmR0SvmFreeVMStructs(pVM);
349	return rc;
350	}
351
352
353	/**
354	* Does per-VM AMD-V termination.
355	*
356	* @returns VBox status code.
357	* @param pVM Pointer to the VM.
358	*/
359	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
360	{
361	hmR0SvmFreeVMStructs(pVM);
362	return VINF_SUCCESS;
363	}
364
365
366	/**
367	* Sets the permission bits for the specified MSR in the MSRPM.
368	*
369	* @param pVCpu Pointer to the VMCPU.
370	* @param uMsr The MSR.
371	* @param fRead Whether reading is allowed.
372	* @param fWrite Whether writing is allowed.
373	*/
374	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
375	{
376	unsigned ulBit;
377	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
378
379	/*
380	* Layout:
381	* Byte offset MSR range
382	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
383	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
384	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
385	* 0x1800 - 0x1fff Reserved
386	*/
387	if (uMsr <= 0x00001FFF)
388	{
389	/* Pentium-compatible MSRs */
390	ulBit = uMsr * 2;
391	}
392	else if ( uMsr >= 0xC0000000
393	&& uMsr <= 0xC0001FFF)
394	{
395	/* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
396	ulBit = (uMsr - 0xC0000000) * 2;
397	pbMsrBitmap += 0x800;
398	}
399	else if ( uMsr >= 0xC0010000
400	&& uMsr <= 0xC0011FFF)
401	{
402	/* AMD Seventh and Eighth Generation Processor MSRs */
403	ulBit = (uMsr - 0xC0001000) * 2;
404	pbMsrBitmap += 0x1000;
405	}
406	else
407	{
408	AssertFailed();
409	return;
410	}
411
412	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
413	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
414	ASMBitSet(pbMsrBitmap, ulBit);
415	else
416	ASMBitClear(pbMsrBitmap, ulBit);
417
418	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
419	ASMBitSet(pbMsrBitmap, ulBit + 1);
420	else
421	ASMBitClear(pbMsrBitmap, ulBit + 1);
422	}
423
424
425	/**
426	* Sets up AMD-V for the specified VM.
427	* This function is only called once per-VM during initalization.
428	*
429	* @returns VBox status code.
430	* @param pVM Pointer to the VM.
431	*/
432	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
433	{
434	int rc = VINF_SUCCESS;
435
436	AssertReturn(pVM, VERR_INVALID_PARAMETER);
437	Assert(pVM->hm.s.svm.fSupported);
438
439	for (VMCPUID i = 0; i < pVM->cCpus; i++)
440	{
441	PVMCPU pVCpu = &pVM->aCpus[i];
442	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcbGuest;
443
444	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
445
446	/* Trap exceptions unconditionally (debug purposes). */
447	#ifdef HMSVM_ALWAYS_TRAP_PF
448	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
449	#endif
450	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
451	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_BP)
452	\| RT_BIT(X86_XCPT_DB)
453	\| RT_BIT(X86_XCPT_DE)
454	\| RT_BIT(X86_XCPT_NM)
455	\| RT_BIT(X86_XCPT_UD)
456	\| RT_BIT(X86_XCPT_NP)
457	\| RT_BIT(X86_XCPT_SS)
458	\| RT_BIT(X86_XCPT_GP)
459	\| RT_BIT(X86_XCPT_PF)
460	\| RT_BIT(X86_XCPT_MF);
461	#endif
462
463	/* Set up unconditional intercepts and conditions. */
464	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
465	\| SVM_CTRL1_INTERCEPT_VINTR /* When guest enabled interrupts cause a VM-exit. */
466	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
467	\| SVM_CTRL1_INTERCEPT_SMI /* System Management Interrupt cause a VM-exit. */
468	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
469	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
470	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
471	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
472	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
473	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
474	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
475	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
476	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
477	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
478
479	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
480	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
481	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
482	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
483	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
484	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
485	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
486	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
487	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
488	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* MWAIT causes a VM-exit. */
489
490	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
491	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
492
493	/* CR0, CR4 writes must be intercepted for obvious reasons. */
494	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
495
496	/* Intercept all DRx reads and writes by default. Changed later on. */
497	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
498	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
499
500	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
501	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
502
503	/* Ignore the priority in the TPR; just deliver it to the guest when we tell it to. */
504	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
505
506	/* Set IO and MSR bitmap permission bitmap physical addresses. */
507	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
508	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
509
510	/* No LBR virtualization. */
511	pVmcb->ctrl.u64LBRVirt = 0;
512
513	/* The ASID must start at 1; the host uses 0. */
514	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
515
516	/*
517	* Setup the PAT MSR (applicable for Nested Paging only).
518	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
519	* so choose type 6 for all PAT slots.
520	*/
521	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
522
523	/* Without Nested Paging, we need additionally intercepts. */
524	if (!pVM->hm.s.fNestedPaging)
525	{
526	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
527	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
528	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
529
530	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
531	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
532	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
533
534	/* Page faults must be intercepted to implement shadow paging. */
535	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
536	}
537
538	/*
539	* The following MSRs are saved/restored automatically during the world-switch.
540	* Don't intercept guest read/write accesses to these MSRs.
541	*/
542	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
543	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
544	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
545	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
546	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
547	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
548	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
549	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
550	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
551	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
552	}
553
554	return rc;
555	}
556
557
558	/**
559	* Flushes the appropriate tagged-TLB entries.
560	*
561	* @param pVM Pointer to the VM.
562	* @param pVCpu Pointer to the VMCPU.
563	*/
564	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
565	{
566	PVM pVM = pVCpu->CTX_SUFF(pVM);
567	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcbGuest;
568	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
569
570	/*
571	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
572	* This can happen both for start & resume due to long jumps back to ring-3.
573	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
574	* so we cannot reuse the ASIDs without flushing.
575	*/
576	bool fNewAsid = false;
577	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
578	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
579	{
580	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
581	pVCpu->hm.s.fForceTLBFlush = true;
582	fNewAsid = true;
583	}
584
585	/* Set TLB flush state as checked until we return from the world switch. */
586	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
587
588	/* Check for explicit TLB shootdowns. */
589	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
590	{
591	pVCpu->hm.s.fForceTLBFlush = true;
592	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
593	}
594
595	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
596	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
597
598	if (pVM->hm.s.svm.fAlwaysFlushTLB)
599	{
600	/*
601	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
602	*/
603	pCpu->uCurrentAsid = 1;
604	pVCpu->hm.s.uCurrentAsid = 1;
605	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
606	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
607	}
608	else if (pVCpu->hm.s.fForceTLBFlush)
609	{
610	if (fNewAsid)
611	{
612	++pCpu->uCurrentAsid;
613	bool fHitASIDLimit = false;
614	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
615	{
616	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
617	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
618	fHitASIDLimit = true;
619
620	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
621	{
622	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
623	pCpu->fFlushAsidBeforeUse = true;
624	}
625	else
626	{
627	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
628	pCpu->fFlushAsidBeforeUse = false;
629	}
630	}
631
632	if ( !fHitASIDLimit
633	&& pCpu->fFlushAsidBeforeUse)
634	{
635	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
636	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
637	else
638	{
639	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
640	pCpu->fFlushAsidBeforeUse = false;
641	}
642	}
643
644	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
645	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
646	}
647	else
648	{
649	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
650	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
651	else
652	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
653	}
654
655	pVCpu->hm.s.fForceTLBFlush = false;
656	}
657	else
658	{
659	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
660	* not be executed. See hmQueueInvlPage() where it is commented
661	* out. Support individual entry flushing someday. */
662	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
663	{
664	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
665	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
666	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
667	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
668	}
669	}
670
671	pVCpu->hm.s.TlbShootdown.cPages = 0;
672	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
673
674	/* Update VMCB with the ASID. */
675	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
676
677	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
678	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
679	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
680	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
681	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
682	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
683
684	#ifdef VBOX_WITH_STATISTICS
685	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
686	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
687	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
688	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
689	{
690	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
691	}
692	else
693	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE)
694	#endif
695	}
696
697
698	/** @name 64-bit guest on 32-bit host OS helper functions.
699	*
700	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
701	* mode (code segment, paging). These wrappers/helpers perform the necessary
702	* bits for the 32->64 switcher.
703	*
704	* @{ */
705	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
706	/**
707	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
708	*
709	* @returns VBox status code.
710	* @param HCPhysVmcbHost Physical address of host VMCB.
711	* @param HCPhysVmcb Physical address of the VMCB.
712	* @param pCtx Pointer to the guest-CPU context.
713	* @param pVM Pointer to the VM.
714	* @param pVCpu Pointer to the VMCPU.
715	*/
716	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
717	{
718	uint32_t aParam[4];
719	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
720	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
721	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
722	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
723
724	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
725	}
726
727
728	/**
729	* Executes the specified VMRUN handler in 64-bit mode.
730	*
731	* @returns VBox status code.
732	* @param pVM Pointer to the VM.
733	* @param pVCpu Pointer to the VMCPU.
734	* @param pCtx Pointer to the guest-CPU context.
735	* @param enmOp The operation to perform.
736	* @param cbParam Number of parameters.
737	* @param paParam Array of 32-bit parameters.
738	*/
739	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
740	uint32_t *paParam)
741	{
742	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
743	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
744
745	/* Disable interrupts. */
746	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
747
748	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
749	RTCPUID idHostCpu = RTMpCpuId();
750	CPUMR0SetLApic(pVM, idHostCpu);
751	#endif
752
753	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
754	CPUMSetHyperEIP(pVCpu, enmOp);
755	for (int i = (int)cbParam - 1; i >= 0; i--)
756	CPUMPushHyper(pVCpu, paParam[i]);
757
758	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
759	/* Call the switcher. */
760	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
761	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
762
763	/* Restore interrupts. */
764	ASMSetFlags(uOldEFlags);
765	return rc;
766	}
767
768	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
769	/** @} */
770
771
772	/**
773	* Saves the host state.
774	*
775	* @returns VBox status code.
776	* @param pVM Pointer to the VM.
777	* @param pVCpu Pointer to the VMCPU.
778	*
779	* @remarks No-long-jump zone!!!
780	*/
781	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
782	{
783	NOREF(pVM);
784	NOREF(pVCpu);
785	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
786	return VINF_SUCCESS;
787	}
788
789
790	DECLINLINE(void) hmR0VmxSvmAddXcptIntercept(uint32_t u32Xcpt)
791	{
792	if (!(pVmcb->ctrl.u32InterceptException & u32Xcpt)
793	{
794	pVmcb->ctrl.u32InterceptException \|= u32Xcpt;
795	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_INTERCEPT_VECTORS;
796	}
797	}
798
799	DECLINLINE(void) hmR0VmxSvmRemoveXcptIntercept(uint32_t u32Xcpt)
800	{
801	if (pVmcb->ctrl.u32InterceptException & u32Xcpt)
802	{
803	pVmcb->ctrl.u32InterceptException &= ~u32Xcpt;
804	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_INTERCEPT_VECTORS;
805	}
806	}
807
808
809	/**
810	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
811	*
812	* @returns VBox status code.
813	* @param pVCpu Pointer to the VMCPU.
814	* @param pCtx Pointer the guest-CPU context.
815	*
816	* @remarks No-long-jump zone!!!
817	*/
818	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PCPUMCTX pCtx)
819	{
820	/*
821	* Guest CR0.
822	*/
823	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
824	{
825	uint64_t u64GuestCR0 = pCtx->cr0;
826
827	/* Always enable caching. */
828	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
829
830	/*
831	* With Nested Paging, the guest is allowed to run with paging disabled; guest-physical to host-physical translations
832	* will remain active through the Nested CR3. AMD supports paged real-mode, See AMD spec. 15.19 "Paged Real Mode".
833	*/
834	if (!pVM->hm.s.fNestedPaging)
835	{
836	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available use shadow page tables. */
837	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
838	}
839
840	/*
841	* Guest FPU bits.
842	*/
843	bool fInterceptNM = false;
844	bool fInterceptMF = false;
845	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
846	if (CPUMIsGuestFPUStateActive(pVCpu))
847	{
848	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
849	if (!(u64GuestCR0 & X86_CR0_NE))
850	{
851	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
852	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
853	fInterceptMF = true;
854	}
855	}
856	else
857	{
858	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
859	u32GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
860	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
861	}
862
863	/*
864	* Update the exception intercept bitmap.
865	*/
866	if (fInterceptNM)
867	hmR0VmxSvmAddXcptIntercept(RT_BIT(X86_XCPT_NM));
868	else
869	hmR0VmxSvmRemoveXcptIntercept(RT_BIT(X86_XCPT_NM));
870
871	if (fInterceptMF)
872	hmR0VmxSvmAddXcptIntercept(RT_BIT(X86_XCPT_MF));
873	else
874	hmR0VmxSvmRemoveXcptIntercept(RT_BIT(X86_XCPT_MF));
875
876	pVmcb->guest.u64CR0 = u64GuestCR0;
877	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
878	}
879
880	/*
881	* Guest CR2.
882	*/
883	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
884	{
885	pVmcb->guest.u64CR2 = pCtx->cr2;
886	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
887	}
888
889	/*
890	* Guest CR3.
891	*/
892	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
893	{
894	if (pVM->hm.s.fNestedPaging)
895	{
896	PGMMODE enmShwPagingMode;
897	#if HC_ARCH_BITS == 32
898	if (CPUMIsGuestInLongModeEx(pCtx))
899	enmShwPagingMode = PGMMODE_AMD64_NX;
900	else
901	#endif
902	enmShwPagingMode = PGMGetHostMode(pVM);
903
904	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
905	Assert(pVmcb->ctrl.u64NestedPagingCR3);
906	pVmcb->guest.u64CR3 = pCtx->cr3;
907	}
908	else
909	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
910
911	pVCpu->hm.s.fContextUseFlags &= HM_CHANGED_GUEST_CR3;
912	}
913
914	/*
915	* Guest CR4.
916	*/
917	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
918	{
919	uint64_t u64GuestCR4 = pCtx->cr4;
920	if (!pVM->hm.s.fNestedPaging)
921	{
922	switch (pVCpu->hm.s.enmShadowMode)
923	{
924	case PGMMODE_REAL:
925	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
926	AssertFailed();
927	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
928
929	case PGMMODE_32_BIT: /* 32-bit paging. */
930	u64GuestCR4 &= ~X86_CR4_PAE;
931	break;
932
933	case PGMMODE_PAE: /* PAE paging. */
934	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
935	/** Must use PAE paging as we could use physical memory > 4 GB */
936	u64GuestCR4 \|= X86_CR4_PAE;
937	break;
938
939	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
940	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
941	#ifdef VBOX_ENABLE_64_BITS_GUESTS
942	break;
943	#else
944	AssertFailed();
945	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
946	#endif
947
948	default: /* shut up gcc */
949	AssertFailed();
950	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
951	}
952	}
953
954	pVmcb->guest.u64CR4 = u64GuestCR4;
955	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
956	}
957
958	return VINF_SUCCESS;
959	}
960
961	/**
962	* Loads the guest segment registers into the VMCB.
963	*
964	* @returns VBox status code.
965	* @param pVCpu Pointer to the VMCPU.
966	* @param pCtx Pointer to the guest-CPU context.
967	*
968	* @remarks No-long-jump zone!!!
969	*/
970	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pCtx)
971	{
972	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
973	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
974	{
975	HMSVM_LOAD_SEG_REG(CS, cs);
976	HMSVM_LOAD_SEG_REG(SS, cs);
977	HMSVM_LOAD_SEG_REG(DS, cs);
978	HMSVM_LOAD_SEG_REG(ES, cs);
979	HMSVM_LOAD_SEG_REG(FS, cs);
980	HMSVM_LOAD_SEG_REG(GS, cs);
981
982	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
983	}
984
985	/* Guest TR. */
986	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
987	{
988	HMSVM_LOAD_SEG_REG(TR, tr);
989	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
990	}
991
992	/* Guest LDTR. */
993	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
994	{
995	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
996	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
997	}
998
999	/* Guest GDTR. */
1000	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1001	{
1002	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1003	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1004	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1005	}
1006
1007	/* Guest IDTR. */
1008	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1009	{
1010	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1011	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1012	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1013	}
1014	}
1015
1016
1017	/**
1018	* Loads the guest MSRs into the VMCB.
1019	*
1020	* @param pVCpu Pointer to the VMCPU.
1021	* @param pCtx Pointer to the guest-CPU context.
1022	*
1023	* @remarks No-long-jump zone!!!
1024	*/
1025	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pCtx)
1026	{
1027	/* Guest Sysenter MSRs. */
1028	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1029	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1030	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1031
1032	/* Guest EFER MSR. */
1033	/* AMD-V requires guest EFER.SVME to be set. Weird.
1034	See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks". */
1035	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1036
1037	/* 64-bit MSRs. */
1038	if (CPUMIsGuestInLongModeEx(pCtx))
1039	{
1040	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1041	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1042	}
1043	else
1044	{
1045	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1046	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1047	}
1048
1049	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1050	* be writable in 32-bit mode. Clarify with AMD spec. */
1051	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1052	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1053	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1054	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1055	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1056	}
1057
1058
1059	/**
1060	* Sets up the appropriate function to run guest code.
1061	*
1062	* @returns VBox status code.
1063	* @param pVCpu Pointer to the VMCPU.
1064	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1065	* out-of-sync. Make sure to update the required fields
1066	* before using them.
1067	*
1068	* @remarks No-long-jump zone!!!
1069	*/
1070	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1071	{
1072	if (CPUMIsGuestInLongModeEx(pCtx))
1073	{
1074	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1075	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1076	#endif
1077	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1078	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1079	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1080	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1081	#else
1082	/* 64-bit host or hybrid host. */
1083	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1084	#endif
1085	}
1086	else
1087	{
1088	/* Guest is not in long mode, use the 32-bit handler. */
1089	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1090	}
1091	return VINF_SUCCESS;
1092	}
1093
1094
1095	/**
1096	* Loads the guest state.
1097	*
1098	* @returns VBox status code.
1099	* @param pVM Pointer to the VM.
1100	* @param pVCpu Pointer to the VMCPU.
1101	* @param pCtx Pointer to the guest-CPU context.
1102	*
1103	* @remarks No-long-jump zone!!!
1104	*/
1105	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1106	{
1107	AssertPtr(pVM);
1108	AssertPtr(pVCpu);
1109	AssertPtr(pMixedCtx);
1110	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1111
1112	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1113	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1114
1115	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1116
1117	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pMixedCtx);
1118	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1119
1120	hmR0SvmLoadGuestSegmentRegs(pVCpu, pCtx);
1121	hmR0SvmLoadGuestMsrs(pVCpu, pCtx);
1122
1123	/* Guest RIP, RSP, RFLAGS, CPL. */
1124	pVmcb->guest.u64RIP = pCtx->rip;
1125	pVmcb->guest.u64RSP = pCtx->rsp;
1126	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1127	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1128
1129	/* Guest RAX (VMRUN uses RAX as an implicit parameter). */
1130	pVmcb->guest.u64RAX = pCtx->rax;
1131
1132	rc = hmR0SvmSetupVMRunHandler(pVCpu, pMixedCtx);
1133	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1134
1135	/* Clear any unused and reserved bits. */
1136	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_SYSENTER_CS_MSR
1137	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1138	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
1139
1140	AssertMsg(!pVCpu->hm.s.fContextUseFlags,
1141	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1142	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1143
1144	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1145
1146	return rc;
1147	}
1148

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 46444

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