HMSVMR0.cpp@ 46774

Last change on this file since 46774 was 46774, checked in by vboxsync, 12 years ago
VMM/HMSVMR0: AMD-V bits.
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1	/* $Id: HMSVMR0.cpp 46774 2013-06-25 12:27:49Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HWSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMVMX_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	#endif
38
39
40	/*******************************************************************************
41	* Defined Constants And Macros *
42	*******************************************************************************/
43	#ifdef VBOX_WITH_STATISTICS
44	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
45	if ((u64ExitCode) == SVM_EXIT_NPF) \
46	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
47	else \
48	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
49	} while (0)
50	#else
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
52	#endif
53
54	/** If we decide to use a function table approach this can be useful to
55	* switch to a "static DECLCALLBACK(int)". */
56	#define HMSVM_EXIT_DECL static int
57
58
59	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
60	*
61	* The CPU format of the segment attribute is described in X86DESCATTRBITS
62	* which is 16-bits (i.e. includes 4 bits of the segment limit).
63	*
64	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
65	* only the attribute bits and nothing else). Upper 4-bits are unused.
66	*
67	* @{ */
68	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) (a & 0xff) \| ((a & 0xf000) >> 4)
69	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) (a & 0xff) \| ((a & 0x0f00) << 4)
70	/** @} */
71
72
73	/** @name Macros for loading, storing segment registers to/from the VMCB.
74	* @{ */
75	#define HMSVM_LOAD_SEG_REG(REG, reg) \
76	do \
77	{ \
78	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
79	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
80	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
81	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
82	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
83	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
84	} while (0)
85
86	#define HMSVM_SAVE_SEG_REG(REG, reg) \
87	do \
88	{ \
89	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
90	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
92	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
93	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
94	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
95	} while (0)
96	/** @} */
97
98
99	/** @name Macro for checking and returning from the using function for
100	* #VMEXIT intercepts that maybe caused during delivering of another
101	* event in the guest. */
102	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
103	do \
104	{ \
105	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
106	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
107	return VINF_SUCCESS; \
108	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
109	return rc; \
110	} while (0)
111	/** @} */
112
113
114	/**
115	* @name Exception bitmap mask for all contributory exceptions.
116	*
117	* Page fault is deliberately excluded here as it's conditional as to whether
118	* it's contributory or benign. Page faults are handled separately.
119	*/
120	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
121	\| RT_BIT(X86_XCPT_DE))
122	/** @} */
123
124
125	/** @name VMCB Clean Bits.
126	*
127	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
128	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
129	* memory.
130	*
131	* @{ */
132	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
133	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
134	/** I/O permission bitmap, MSR permission bitmap. */
135	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
136	/** ASID. */
137	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
138	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
139	V_INTR_VECTOR. */
140	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
141	/** Nested Paging: Nested CR3 (nCR3), PAT. */
142	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
143	/** Control registers (CR0, CR3, CR4, EFER). */
144	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
145	/** Debug registers (DR6, DR7). */
146	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
147	/** GDT, IDT limit and base. */
148	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
149	/** Segment register: CS, SS, DS, ES limit and base. */
150	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
151	/** CR2.*/
152	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
153	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
154	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
155	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
156	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
157	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
158	/** Mask of all valid VMCB Clean bits. */
159	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
160	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
161	\| HMSVM_VMCB_CLEAN_ASID \
162	\| HMSVM_VMCB_CLEAN_TPR \
163	\| HMSVM_VMCB_CLEAN_NP \
164	\| HMSVM_VMCB_CLEAN_CRX_EFER \
165	\| HMSVM_VMCB_CLEAN_DRX \
166	\| HMSVM_VMCB_CLEAN_DT \
167	\| HMSVM_VMCB_CLEAN_SEG \
168	\| HMSVM_VMCB_CLEAN_CR2 \
169	\| HMSVM_VMCB_CLEAN_LBR \
170	\| HMSVM_VMCB_CLEAN_AVIC)
171	/** @} */
172
173	/** @name SVM transient.
174	*
175	* A state structure for holding miscellaneous information across AMD-V
176	* VMRUN/#VMEXIT operation, restored after the transition.
177	*
178	* @{ */
179	typedef struct SVMTRANSIENT
180	{
181	/** The host's rflags/eflags. */
182	RTCCUINTREG uEFlags;
183	#if HC_ARCH_BITS == 32
184	uint32_t u32Alignment0;
185	#endif
186
187	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
188	uint64_t u64ExitCode;
189	/** The guest's TPR value used for TPR shadowing. */
190	uint8_t u8GuestTpr;
191
192	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
193	* contributary exception or a page-fault. */
194	bool fVectoringPF;
195	} SVMTRANSIENT, *PSVMTRANSIENT;
196	/** @} */
197
198
199	/**
200	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
201	*/
202	typedef enum SVMMSREXITREAD
203	{
204	/** Reading this MSR causes a VM-exit. */
205	SVMMSREXIT_INTERCEPT_READ = 0xb,
206	/** Reading this MSR does not cause a VM-exit. */
207	SVMMSREXIT_PASSTHRU_READ
208	} SVMMSREXITREAD;
209
210	/**
211	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
212	*/
213	typedef enum SVMMSREXITWRITE
214	{
215	/** Writing to this MSR causes a VM-exit. */
216	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
217	/** Writing to this MSR does not cause a VM-exit. */
218	SVMMSREXIT_PASSTHRU_WRITE
219	} SVMMSREXITWRITE;
220
221
222	/*******************************************************************************
223	* Internal Functions *
224	*******************************************************************************/
225	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
226	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
227
228	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
229	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
230	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
231	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
232	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
233	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
234	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
235	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
236	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
237	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
238	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
239	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
240	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
241	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
242	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
243	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
244	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
245	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
246	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
247	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
248	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
249	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
250	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
251	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
252	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
253	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255
256	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
257
258
259	/*******************************************************************************
260	* Global Variables *
261	*******************************************************************************/
262	/** Ring-0 memory object for the IO bitmap. */
263	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
264	/** Physical address of the IO bitmap. */
265	RTHCPHYS g_HCPhysIOBitmap = 0;
266	/** Virtual address of the IO bitmap. */
267	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
268
269
270	/**
271	* Sets up and activates AMD-V on the current CPU.
272	*
273	* @returns VBox status code.
274	* @param pCpu Pointer to the CPU info struct.
275	* @param pVM Pointer to the VM (can be NULL after a resume!).
276	* @param pvCpuPage Pointer to the global CPU page.
277	* @param HCPhysCpuPage Physical address of the global CPU page.
278	*/
279	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
280	{
281	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
282	AssertReturn( HCPhysCpuPage
283	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
284	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
285
286	/*
287	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
288	*/
289	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
290	if (u64HostEfer & MSR_K6_EFER_SVME)
291	{
292	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
293	if ( pVM
294	&& pVM->hm.s.svm.fIgnoreInUseError)
295	{
296	pCpu->fIgnoreAMDVInUseError = true;
297	}
298
299	if (!pCpu->fIgnoreAMDVInUseError)
300	return VERR_SVM_IN_USE;
301	}
302
303	/* Turn on AMD-V in the EFER MSR. */
304	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
305
306	/* Write the physical page address where the CPU will store the host state while executing the VM. */
307	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
308
309	/*
310	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
311	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
312	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
313	* to flush the TLB with before using a new ASID.
314	*/
315	pCpu->fFlushAsidBeforeUse = true;
316
317	/*
318	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
319	*/
320	++pCpu->cTlbFlushes;
321
322	return VINF_SUCCESS;
323	}
324
325
326	/**
327	* Deactivates AMD-V on the current CPU.
328	*
329	* @returns VBox status code.
330	* @param pCpu Pointer to the CPU info struct.
331	* @param pvCpuPage Pointer to the global CPU page.
332	* @param HCPhysCpuPage Physical address of the global CPU page.
333	*/
334	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
335	{
336	AssertReturn( HCPhysCpuPage
337	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
338	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
339	NOREF(pCpu);
340
341	/* Turn off AMD-V in the EFER MSR if AMD-V is active. */
342	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
343	if (u64HostEfer & MSR_K6_EFER_SVME)
344	{
345	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
346
347	/* Invalidate host state physical address. */
348	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
349	}
350
351	return VINF_SUCCESS;
352	}
353
354
355	/**
356	* Does global AMD-V initialization (called during module initialization).
357	*
358	* @returns VBox status code.
359	*/
360	VMMR0DECL(int) SVMR0GlobalInit(void)
361	{
362	/*
363	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
364	* once globally here instead of per-VM.
365	*/
366	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
367	if (RT_FAILURE(rc))
368	return rc;
369
370	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
371	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
372
373	/* Set all bits to intercept all IO accesses. */
374	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
375	return VINF_SUCCESS;
376	}
377
378
379	/**
380	* Does global AMD-V termination (called during module termination).
381	*/
382	VMMR0DECL(void) SVMR0GlobalTerm(void)
383	{
384	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
385	{
386	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
387	g_pvIOBitmap = NULL;
388	g_HCPhysIOBitmap = 0;
389	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
390	}
391	}
392
393
394	/**
395	* Frees any allocated per-VCPU structures for a VM.
396	*
397	* @param pVM Pointer to the VM.
398	*/
399	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
400	{
401	for (uint32_t i = 0; i < pVM->cCpus; i++)
402	{
403	PVMCPU pVCpu = &pVM->aCpus[i];
404	AssertPtr(pVCpu);
405
406	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
407	{
408	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
409	pVCpu->hm.s.svm.pvVmcbHost = 0;
410	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
411	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
412	}
413
414	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
415	{
416	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
417	pVCpu->hm.s.svm.pvVmcb = 0;
418	pVCpu->hm.s.svm.HCPhysVmcb = 0;
419	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
420	}
421
422	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
423	{
424	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
425	pVCpu->hm.s.svm.pvMsrBitmap = 0;
426	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
427	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
428	}
429	}
430	}
431
432
433	/**
434	* Does per-VM AMD-V initialization.
435	*
436	* @returns VBox status code.
437	* @param pVM Pointer to the VM.
438	*/
439	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
440	{
441	int rc = VERR_INTERNAL_ERROR_5;
442
443	/*
444	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
445	*/
446	uint32_t u32Family;
447	uint32_t u32Model;
448	uint32_t u32Stepping;
449	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
450	{
451	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
452	pVM->hm.s.svm.fAlwaysFlushTLB = true;
453	}
454
455	/*
456	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
457	*/
458	for (VMCPUID i = 0; i < pVM->cCpus; i++)
459	{
460	PVMCPU pVCpu = &pVM->aCpus[i];
461	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
462	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
463	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
464	}
465
466	for (VMCPUID i = 0; i < pVM->cCpus; i++)
467	{
468	PVMCPU pVCpu = &pVM->aCpus[i];
469
470	/*
471	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
472	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
473	*/
474	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
475	if (RT_FAILURE(rc))
476	goto failure_cleanup;
477
478	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
479	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
480	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
481	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
482
483	/*
484	* Allocate one page for the guest-state VMCB.
485	*/
486	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
487	if (RT_FAILURE(rc))
488	goto failure_cleanup;
489
490	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
491	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
492	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
493	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
494
495	/*
496	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
497	* SVM to not require one.
498	*/
499	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
500	if (RT_FAILURE(rc))
501	goto failure_cleanup;
502
503	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
504	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
505	/* Set all bits to intercept all MSR accesses (changed later on). */
506	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
507	}
508
509	return VINF_SUCCESS;
510
511	failure_cleanup:
512	hmR0SvmFreeStructs(pVM);
513	return rc;
514	}
515
516
517	/**
518	* Does per-VM AMD-V termination.
519	*
520	* @returns VBox status code.
521	* @param pVM Pointer to the VM.
522	*/
523	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
524	{
525	hmR0SvmFreeStructs(pVM);
526	return VINF_SUCCESS;
527	}
528
529
530	/**
531	* Sets the permission bits for the specified MSR in the MSRPM.
532	*
533	* @param pVCpu Pointer to the VMCPU.
534	* @param uMsr The MSR for which the access permissions are being set.
535	* @param enmRead MSR read permissions.
536	* @param enmWrite MSR write permissions.
537	*/
538	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
539	{
540	unsigned ulBit;
541	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
542
543	/*
544	* Layout:
545	* Byte offset MSR range
546	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
547	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
548	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
549	* 0x1800 - 0x1fff Reserved
550	*/
551	if (uMsr <= 0x00001FFF)
552	{
553	/* Pentium-compatible MSRs. */
554	ulBit = uMsr * 2;
555	}
556	else if ( uMsr >= 0xC0000000
557	&& uMsr <= 0xC0001FFF)
558	{
559	/* AMD Sixth Generation x86 Processor MSRs. */
560	ulBit = (uMsr - 0xC0000000) * 2;
561	pbMsrBitmap += 0x800;
562	}
563	else if ( uMsr >= 0xC0010000
564	&& uMsr <= 0xC0011FFF)
565	{
566	/* AMD Seventh and Eighth Generation Processor MSRs. */
567	ulBit = (uMsr - 0xC0001000) * 2;
568	pbMsrBitmap += 0x1000;
569	}
570	else
571	{
572	AssertFailed();
573	return;
574	}
575
576	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
577	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
578	ASMBitSet(pbMsrBitmap, ulBit);
579	else
580	ASMBitClear(pbMsrBitmap, ulBit);
581
582	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
583	ASMBitSet(pbMsrBitmap, ulBit + 1);
584	else
585	ASMBitClear(pbMsrBitmap, ulBit + 1);
586
587	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
588	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
589	}
590
591
592	/**
593	* Sets up AMD-V for the specified VM.
594	* This function is only called once per-VM during initalization.
595	*
596	* @returns VBox status code.
597	* @param pVM Pointer to the VM.
598	*/
599	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
600	{
601	int rc = VINF_SUCCESS;
602
603	AssertReturn(pVM, VERR_INVALID_PARAMETER);
604	Assert(pVM->hm.s.svm.fSupported);
605
606	for (VMCPUID i = 0; i < pVM->cCpus; i++)
607	{
608	PVMCPU pVCpu = &pVM->aCpus[i];
609	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
610
611	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
612
613	/* Trap exceptions unconditionally (debug purposes). */
614	#ifdef HMSVM_ALWAYS_TRAP_PF
615	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
616	#endif
617	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
618	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
619	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_BP)
620	\| RT_BIT(X86_XCPT_DB)
621	\| RT_BIT(X86_XCPT_DE)
622	\| RT_BIT(X86_XCPT_NM)
623	\| RT_BIT(X86_XCPT_UD)
624	\| RT_BIT(X86_XCPT_NP)
625	\| RT_BIT(X86_XCPT_SS)
626	\| RT_BIT(X86_XCPT_GP)
627	\| RT_BIT(X86_XCPT_PF)
628	\| RT_BIT(X86_XCPT_MF);
629	#endif
630
631	/* Set up unconditional intercepts and conditions. */
632	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
633	\| SVM_CTRL1_INTERCEPT_VINTR /* Interrupt-window VM-exit. */
634	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
635	\| SVM_CTRL1_INTERCEPT_SMI /* System Management Interrupt cause a VM-exit. */
636	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
637	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
638	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
639	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
640	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
641	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
642	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
643	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
644	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
645	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
646
647	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
648	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
649	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
650	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
651	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
652	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
653	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
654	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
655	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
656	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
657
658	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
659	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
660
661	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
662	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
663
664	/* Intercept all DRx reads and writes by default. Changed later on. */
665	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
666	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
667
668	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
669	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
670
671	/* Ignore the priority in the TPR; we take into account the guest TPR anyway while delivering interrupts. */
672	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
673
674	/* Set IO and MSR bitmap permission bitmap physical addresses. */
675	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
676	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
677
678	/* No LBR virtualization. */
679	pVmcb->ctrl.u64LBRVirt = 0;
680
681	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from memory. */
682	pVmcb->ctrl.u64VmcbCleanBits = 0;
683
684	/* The guest ASID MBNZ, set it to 1. The host uses 0. */
685	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
686
687	/*
688	* Setup the PAT MSR (applicable for Nested Paging only).
689	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
690	* so choose type 6 for all PAT slots.
691	*/
692	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
693
694	/* Without Nested Paging, we need additionally intercepts. */
695	if (!pVM->hm.s.fNestedPaging)
696	{
697	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
698	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
699	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
700
701	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
702	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
703	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
704
705	/* Page faults must be intercepted to implement shadow paging. */
706	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
707	}
708
709	/*
710	* The following MSRs are saved/restored automatically during the world-switch.
711	* Don't intercept guest read/write accesses to these MSRs.
712	*/
713	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
714	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
715	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
716	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
717	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
718	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
719	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
720	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
721	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
722	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
723	}
724
725	return rc;
726	}
727
728
729	/**
730	* Invalidates a guest page by guest virtual address.
731	*
732	* @returns VBox status code.
733	* @param pVM Pointer to the VM.
734	* @param pVCpu Pointer to the VMCPU.
735	* @param GCVirt Guest virtual address of the page to invalidate.
736	*/
737	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
738	{
739	AssertReturn(pVM, VERR_INVALID_PARAMETER);
740	Assert(pVM->hm.s.svm.fSupported);
741
742	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
743
744	/* Skip it if a TLB flush is already pending. */
745	if (!fFlushPending)
746	{
747	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
748
749	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
750	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
751
752	#if HC_ARCH_BITS == 32
753	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
754	if (CPUMIsGuestInLongMode(pVCpu))
755	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
756	else
757	#endif
758	{
759	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
760	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
761	}
762	}
763	return VINF_SUCCESS;
764	}
765
766
767	/**
768	* Flushes the appropriate tagged-TLB entries.
769	*
770	* @param pVM Pointer to the VM.
771	* @param pVCpu Pointer to the VMCPU.
772	*/
773	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
774	{
775	PVM pVM = pVCpu->CTX_SUFF(pVM);
776	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
777	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
778
779	/*
780	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
781	* This can happen both for start & resume due to long jumps back to ring-3.
782	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
783	* so we cannot reuse the ASIDs without flushing.
784	*/
785	bool fNewAsid = false;
786	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
787	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
788	{
789	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
790	pVCpu->hm.s.fForceTLBFlush = true;
791	fNewAsid = true;
792	}
793
794	/* Set TLB flush state as checked until we return from the world switch. */
795	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
796
797	/* Check for explicit TLB shootdowns. */
798	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
799	{
800	pVCpu->hm.s.fForceTLBFlush = true;
801	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
802	}
803
804	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
805	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
806
807	if (pVM->hm.s.svm.fAlwaysFlushTLB)
808	{
809	/*
810	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
811	*/
812	pCpu->uCurrentAsid = 1;
813	pVCpu->hm.s.uCurrentAsid = 1;
814	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
815	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
816	}
817	else if (pVCpu->hm.s.fForceTLBFlush)
818	{
819	if (fNewAsid)
820	{
821	++pCpu->uCurrentAsid;
822	bool fHitASIDLimit = false;
823	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
824	{
825	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
826	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
827	fHitASIDLimit = true;
828
829	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
830	{
831	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
832	pCpu->fFlushAsidBeforeUse = true;
833	}
834	else
835	{
836	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
837	pCpu->fFlushAsidBeforeUse = false;
838	}
839	}
840
841	if ( !fHitASIDLimit
842	&& pCpu->fFlushAsidBeforeUse)
843	{
844	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
845	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
846	else
847	{
848	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
849	pCpu->fFlushAsidBeforeUse = false;
850	}
851	}
852
853	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
854	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
855	}
856	else
857	{
858	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
859	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
860	else
861	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
862	}
863
864	pVCpu->hm.s.fForceTLBFlush = false;
865	}
866	else
867	{
868	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
869	* not be executed. See hmQueueInvlPage() where it is commented
870	* out. Support individual entry flushing someday. */
871	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
872	{
873	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
874	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
875	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
876	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
877	}
878	}
879
880	pVCpu->hm.s.TlbShootdown.cPages = 0;
881	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
882
883	/* Update VMCB with the ASID. */
884	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
885	{
886	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
887	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
888	}
889
890	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
891	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
892	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
893	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
894	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
895	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
896
897	#ifdef VBOX_WITH_STATISTICS
898	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
899	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
900	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
901	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
902	{
903	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
904	}
905	else
906	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
907	#endif
908	}
909
910
911	/** @name 64-bit guest on 32-bit host OS helper functions.
912	*
913	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
914	* mode (code segment, paging). These wrappers/helpers perform the necessary
915	* bits for the 32->64 switcher.
916	*
917	* @{ */
918	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
919	/**
920	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
921	*
922	* @returns VBox status code.
923	* @param HCPhysVmcbHost Physical address of host VMCB.
924	* @param HCPhysVmcb Physical address of the VMCB.
925	* @param pCtx Pointer to the guest-CPU context.
926	* @param pVM Pointer to the VM.
927	* @param pVCpu Pointer to the VMCPU.
928	*/
929	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
930	{
931	uint32_t aParam[4];
932	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
933	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
934	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
935	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
936
937	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
938	}
939
940
941	/**
942	* Executes the specified VMRUN handler in 64-bit mode.
943	*
944	* @returns VBox status code.
945	* @param pVM Pointer to the VM.
946	* @param pVCpu Pointer to the VMCPU.
947	* @param pCtx Pointer to the guest-CPU context.
948	* @param enmOp The operation to perform.
949	* @param cbParam Number of parameters.
950	* @param paParam Array of 32-bit parameters.
951	*/
952	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
953	uint32_t *paParam)
954	{
955	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
956	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
957
958	/* Disable interrupts. */
959	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
960
961	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
962	RTCPUID idHostCpu = RTMpCpuId();
963	CPUMR0SetLApic(pVM, idHostCpu);
964	#endif
965
966	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
967	CPUMSetHyperEIP(pVCpu, enmOp);
968	for (int i = (int)cbParam - 1; i >= 0; i--)
969	CPUMPushHyper(pVCpu, paParam[i]);
970
971	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
972	/* Call the switcher. */
973	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
974	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
975
976	/* Restore interrupts. */
977	ASMSetFlags(uOldEFlags);
978	return rc;
979	}
980
981	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
982	/** @} */
983
984
985	/**
986	* Adds an exception to the intercept exception bitmap in the VMCB and updates
987	* the corresponding VMCB Clean Bit.
988	*
989	* @param pVmcb Pointer to the VMCB.
990	* @param u32Xcpt The value of the exception (X86_XCPT_*).
991	*/
992	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
993	{
994	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
995	{
996	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
997	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
998	}
999	}
1000
1001
1002	/**
1003	* Removes an exception from the intercept-exception bitmap in the VMCB and
1004	* updates the corresponding VMCB Clean Bit.
1005	*
1006	* @param pVmcb Pointer to the VMCB.
1007	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1008	*/
1009	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1010	{
1011	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1012	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1013	{
1014	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1015	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1016	}
1017	#endif
1018	}
1019
1020
1021	/**
1022	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1023	*
1024	* @returns VBox status code.
1025	* @param pVCpu Pointer to the VMCPU.
1026	* @param pVmcb Pointer to the VMCB.
1027	* @param pCtx Pointer the guest-CPU context.
1028	*
1029	* @remarks No-long-jump zone!!!
1030	*/
1031	DECLINLINE(int) hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1032	{
1033	/*
1034	* Guest CR0.
1035	*/
1036	PVM pVM = pVCpu->CTX_SUFF(pVM);
1037	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1038	{
1039	uint64_t u64GuestCR0 = pCtx->cr0;
1040
1041	/* Always enable caching. */
1042	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1043
1044	/*
1045	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1046	*/
1047	if (!pVM->hm.s.fNestedPaging)
1048	{
1049	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1050	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1051	}
1052
1053	/*
1054	* Guest FPU bits.
1055	*/
1056	bool fInterceptNM = false;
1057	bool fInterceptMF = false;
1058	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1059	if (CPUMIsGuestFPUStateActive(pVCpu))
1060	{
1061	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1062	if (!(u64GuestCR0 & X86_CR0_NE))
1063	{
1064	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1065	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
1066	fInterceptMF = true;
1067	}
1068	}
1069	else
1070	{
1071	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1072	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1073	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1074	}
1075
1076	/*
1077	* Update the exception intercept bitmap.
1078	*/
1079	if (fInterceptNM)
1080	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1081	else
1082	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1083
1084	if (fInterceptMF)
1085	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1086	else
1087	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1088
1089	pVmcb->guest.u64CR0 = u64GuestCR0;
1090	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1091	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1092	}
1093
1094	/*
1095	* Guest CR2.
1096	*/
1097	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1098	{
1099	pVmcb->guest.u64CR2 = pCtx->cr2;
1100	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1101	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1102	}
1103
1104	/*
1105	* Guest CR3.
1106	*/
1107	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1108	{
1109	if (pVM->hm.s.fNestedPaging)
1110	{
1111	PGMMODE enmShwPagingMode;
1112	#if HC_ARCH_BITS == 32
1113	if (CPUMIsGuestInLongModeEx(pCtx))
1114	enmShwPagingMode = PGMMODE_AMD64_NX;
1115	else
1116	#endif
1117	enmShwPagingMode = PGMGetHostMode(pVM);
1118
1119	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1120	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1121	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1122	pVmcb->guest.u64CR3 = pCtx->cr3;
1123	}
1124	else
1125	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1126
1127	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1128	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1129	}
1130
1131	/*
1132	* Guest CR4.
1133	*/
1134	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1135	{
1136	uint64_t u64GuestCR4 = pCtx->cr4;
1137	if (!pVM->hm.s.fNestedPaging)
1138	{
1139	switch (pVCpu->hm.s.enmShadowMode)
1140	{
1141	case PGMMODE_REAL:
1142	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1143	AssertFailed();
1144	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1145
1146	case PGMMODE_32_BIT: /* 32-bit paging. */
1147	u64GuestCR4 &= ~X86_CR4_PAE;
1148	break;
1149
1150	case PGMMODE_PAE: /* PAE paging. */
1151	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1152	/** Must use PAE paging as we could use physical memory > 4 GB */
1153	u64GuestCR4 \|= X86_CR4_PAE;
1154	break;
1155
1156	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1157	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1158	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1159	break;
1160	#else
1161	AssertFailed();
1162	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1163	#endif
1164
1165	default: /* shut up gcc */
1166	AssertFailed();
1167	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1168	}
1169	}
1170
1171	pVmcb->guest.u64CR4 = u64GuestCR4;
1172	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1173	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1174	}
1175
1176	return VINF_SUCCESS;
1177	}
1178
1179
1180	/**
1181	* Loads the guest segment registers into the VMCB.
1182	*
1183	* @returns VBox status code.
1184	* @param pVCpu Pointer to the VMCPU.
1185	* @param pVmcb Pointer to the VMCB.
1186	* @param pCtx Pointer to the guest-CPU context.
1187	*
1188	* @remarks No-long-jump zone!!!
1189	*/
1190	DECLINLINE(void) hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1191	{
1192	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1193	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1194	{
1195	HMSVM_LOAD_SEG_REG(CS, cs);
1196	HMSVM_LOAD_SEG_REG(SS, ss);
1197	HMSVM_LOAD_SEG_REG(DS, ds);
1198	HMSVM_LOAD_SEG_REG(ES, es);
1199	HMSVM_LOAD_SEG_REG(FS, fs);
1200	HMSVM_LOAD_SEG_REG(GS, gs);
1201
1202	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1203	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1204	}
1205
1206	/* Guest TR. */
1207	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1208	{
1209	HMSVM_LOAD_SEG_REG(TR, tr);
1210	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1211	}
1212
1213	/* Guest LDTR. */
1214	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1215	{
1216	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1217	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1218	}
1219
1220	/* Guest GDTR. */
1221	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1222	{
1223	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1224	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1225	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1226	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1227	}
1228
1229	/* Guest IDTR. */
1230	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1231	{
1232	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1233	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1234	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1235	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1236	}
1237	}
1238
1239
1240	/**
1241	* Loads the guest MSRs into the VMCB.
1242	*
1243	* @param pVCpu Pointer to the VMCPU.
1244	* @param pVmcb Pointer to the VMCB.
1245	* @param pCtx Pointer to the guest-CPU context.
1246	*
1247	* @remarks No-long-jump zone!!!
1248	*/
1249	DECLINLINE(void) hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1250	{
1251	/* Guest Sysenter MSRs. */
1252	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1253	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1254	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1255
1256	/*
1257	* Guest EFER MSR.
1258	* AMD-V requires guest EFER.SVME to be set. Weird. .
1259	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1260	*/
1261	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1262	{
1263	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1264	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1265	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1266	}
1267
1268	/* 64-bit MSRs. */
1269	if (CPUMIsGuestInLongModeEx(pCtx))
1270	{
1271	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1272	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1273	}
1274	else
1275	{
1276	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1277	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1278	{
1279	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1280	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1281	}
1282	}
1283
1284
1285	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1286	* be writable in 32-bit mode. Clarify with AMD spec. */
1287	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1288	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1289	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1290	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1291	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1292	}
1293
1294
1295	/**
1296	* Loads the guest debug registers into the VMCB.
1297	*
1298	* @param pVCpu Pointer to the VMCPU.
1299	* @param pVmcb Pointer to the VMCB.
1300	* @param pCtx Pointer to the guest-CPU context.
1301	*
1302	* @remarks No-long-jump zone!!!
1303	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1304	*/
1305	DECLINLINE(void) hmR0SvmLoadGuestDebugRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1306	{
1307	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1308	return;
1309
1310	/** @todo Turn these into assertions if possible. */
1311	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* Set reserved bits to 1. */
1312	pCtx->dr[6] &= ~RT_BIT(12); /* MBZ. */
1313
1314	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
1315	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
1316	pCtx->dr[7] \|= 0x400; /* MB1. */
1317
1318	/* Update DR6, DR7 with the guest values. */
1319	pVmcb->guest.u64DR7 = pCtx->dr[7];
1320	pVmcb->guest.u64DR6 = pCtx->dr[6];
1321	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1322
1323	bool fInterceptDB = false;
1324	bool fInterceptMovDRx = false;
1325	if (DBGFIsStepping(pVCpu))
1326	{
1327	/* AMD-V doesn't have any monitor-trap flag equivalent. Instead, enable tracing in the guest and trap #DB. */
1328	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1329	fInterceptDB = true;
1330	}
1331
1332	PVM pVM = pVCpu->CTX_SUFF(pVM);
1333	if (CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1334	{
1335	if (!CPUMIsHyperDebugStateActive(pVCpu))
1336	{
1337	int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1338	AssertRC(rc);
1339
1340	/* Update DR6, DR7 with the hypervisor values. */
1341	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1342	pVmcb->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
1343	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1344	}
1345	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1346	fInterceptMovDRx = true;
1347	}
1348	else if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1349	{
1350	if (!CPUMIsGuestDebugStateActive(pVCpu))
1351	{
1352	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1353	AssertRC(rc);
1354	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1355	}
1356	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1357	Assert(fInterceptMovDRx == false);
1358	}
1359	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1360	{
1361	/* For the first time we would need to intercept MOV DRx accesses even when the guest debug registers aren't loaded. */
1362	fInterceptMovDRx = true;
1363	}
1364
1365	if (fInterceptDB)
1366	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1367	else
1368	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1369
1370	if (fInterceptMovDRx)
1371	{
1372	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1373	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1374	{
1375	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1376	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1377	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1378	}
1379	}
1380	else
1381	{
1382	if ( pVmcb->ctrl.u16InterceptRdDRx
1383	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1384	{
1385	pVmcb->ctrl.u16InterceptRdDRx = 0;
1386	pVmcb->ctrl.u16InterceptWrDRx = 0;
1387	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1388	}
1389	}
1390
1391	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1392	}
1393
1394
1395	/**
1396	* Loads the guest APIC state (currently just the TPR).
1397	*
1398	* @returns VBox status code.
1399	* @param pVCpu Pointer to the VMCPU.
1400	* @param pVmcb Pointer to the VMCB.
1401	* @param pCtx Pointer to the guest-CPU context.
1402	*/
1403	DECLINLINE(int) hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1404	{
1405	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1406	return VINF_SUCCESS;
1407
1408	bool fPendingIntr;
1409	uint8_t u8Tpr;
1410	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1411	AssertRCReturn(rc, rc);
1412
1413	/** Assume that we need to trap all TPR accesses and thus need not check on
1414	* every #VMEXIT if we should update the TPR. */
1415	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1416	pVCpu->hm.s.svm.fSyncVTpr = false;
1417
1418	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1419	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1420	{
1421	pCtx->msrLSTAR = u8Tpr;
1422
1423	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1424	if (fPendingIntr)
1425	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1426	else
1427	{
1428	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1429	pVCpu->hm.s.svm.fSyncVTpr = true;
1430	}
1431
1432	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
1433	}
1434	else
1435	{
1436	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1437	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1438
1439	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1440	if (fPendingIntr)
1441	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1442	else
1443	{
1444	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1445	pVCpu->hm.s.svm.fSyncVTpr = true;
1446	}
1447
1448	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1449	}
1450
1451	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1452	return rc;
1453	}
1454
1455
1456	/**
1457	* Sets up the appropriate function to run guest code.
1458	*
1459	* @returns VBox status code.
1460	* @param pVCpu Pointer to the VMCPU.
1461	* @param pCtx Pointer to the guest-CPU context.
1462	*
1463	* @remarks No-long-jump zone!!!
1464	*/
1465	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1466	{
1467	if (CPUMIsGuestInLongModeEx(pCtx))
1468	{
1469	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1470	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1471	#endif
1472	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1473	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1474	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1475	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1476	#else
1477	/* 64-bit host or hybrid host. */
1478	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1479	#endif
1480	}
1481	else
1482	{
1483	/* Guest is not in long mode, use the 32-bit handler. */
1484	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1485	}
1486	return VINF_SUCCESS;
1487	}
1488
1489
1490	/**
1491	* Enters the AMD-V session.
1492	*
1493	* @returns VBox status code.
1494	* @param pVM Pointer to the VM.
1495	* @param pVCpu Pointer to the VMCPU.
1496	* @param pCpu Pointer to the CPU info struct.
1497	*/
1498	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
1499	{
1500	AssertPtr(pVM);
1501	AssertPtr(pVCpu);
1502	Assert(pVM->hm.s.svm.fSupported);
1503	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1504	NOREF(pCpu);
1505
1506	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1507
1508	/* Nothing to do here. */
1509	return VINF_SUCCESS;
1510	}
1511
1512
1513	/**
1514	* Leaves the AMD-V session.
1515	*
1516	* @returns VBox status code.
1517	* @param pVM Pointer to the VM.
1518	* @param pVCpu Pointer to the VMCPU.
1519	* @param pCtx Pointer to the guest-CPU context.
1520	*/
1521	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1522	{
1523	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1524	NOREF(pVM);
1525	NOREF(pVCpu);
1526	NOREF(pCtx);
1527
1528	/* Nothing to do here. Everything is taken care of in hmR0SvmLongJmpToRing3(). */
1529	return VINF_SUCCESS;
1530	}
1531
1532
1533	/**
1534	* Saves the host state.
1535	*
1536	* @returns VBox status code.
1537	* @param pVM Pointer to the VM.
1538	* @param pVCpu Pointer to the VMCPU.
1539	*
1540	* @remarks No-long-jump zone!!!
1541	*/
1542	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1543	{
1544	NOREF(pVM);
1545	NOREF(pVCpu);
1546	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1547	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1548	return VINF_SUCCESS;
1549	}
1550
1551
1552	/**
1553	* Worker for loading the guest-state into the VMCB.
1554	*
1555	* @returns VBox status code.
1556	* @param pVM Pointer to the VM.
1557	* @param pVCpu Pointer to the VMCPU.
1558	* @param pCtx Pointer to the guest-CPU context.
1559	*
1560	* @remarks No-long-jump zone!!!
1561	*/
1562	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1563	{
1564	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1565	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1566
1567	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1568
1569	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1570	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1571
1572	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1573	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1574
1575	pVmcb->guest.u64RIP = pCtx->rip;
1576	pVmcb->guest.u64RSP = pCtx->rsp;
1577	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1578	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1579	pVmcb->guest.u64RAX = pCtx->rax;
1580
1581	/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
1582	hmR0SvmLoadGuestDebugRegs(pVCpu, pVmcb, pCtx);
1583
1584	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1585	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1586
1587	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1588	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1589
1590	/* Clear any unused and reserved bits. */
1591	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_MSR /* Unused (legacy). */
1592	\| HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1593	\| HM_CHANGED_GUEST_RSP
1594	\| HM_CHANGED_GUEST_RFLAGS
1595	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1596	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1597	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1598	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1599	\| HM_CHANGED_SVM_RESERVED2
1600	\| HM_CHANGED_SVM_RESERVED3);
1601
1602	AssertMsg(!pVCpu->hm.s.fContextUseFlags,
1603	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1604	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1605
1606	Log4(("Load: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
1607
1608	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1609	return rc;
1610	}
1611
1612
1613	/**
1614	* Loads the guest state.
1615	*
1616	* @returns VBox status code.
1617	* @param pVM Pointer to the VM.
1618	* @param pVCpu Pointer to the VMCPU.
1619	* @param pCtx Pointer to the guest-CPU context.
1620	*
1621	* @remarks No-long-jump zone!!!
1622	*/
1623	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1624	{
1625	/* Nothing to do here. Loading is done below before VM-entry. */
1626	return VINF_SUCCESS;
1627	}
1628
1629
1630
1631	/**
1632	* Saves the entire guest state from the VMCB into the
1633	* guest-CPU context. Currently there is no residual state left in the CPU that
1634	* is not updated in the VMCB.
1635	*
1636	* @returns VBox status code.
1637	* @param pVCpu Pointer to the VMCPU.
1638	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1639	* out-of-sync. Make sure to update the required fields
1640	* before using them.
1641	*/
1642	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1643	{
1644	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1645
1646	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1647
1648	pMixedCtx->rip = pVmcb->guest.u64RIP;
1649	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1650	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1651	pMixedCtx->rax = pVmcb->guest.u64RAX;
1652
1653	/*
1654	* Guest interrupt shadow.
1655	*/
1656	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1657	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1658	else
1659	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1660
1661	/*
1662	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1663	*/
1664	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1665
1666	/*
1667	* Guest MSRs.
1668	*/
1669	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1670	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1671	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1672	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1673	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1674	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1675	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1676	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1677
1678	/*
1679	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1680	*/
1681	HMSVM_SAVE_SEG_REG(CS, cs);
1682	HMSVM_SAVE_SEG_REG(SS, ss);
1683	HMSVM_SAVE_SEG_REG(DS, ds);
1684	HMSVM_SAVE_SEG_REG(ES, es);
1685	HMSVM_SAVE_SEG_REG(FS, fs);
1686	HMSVM_SAVE_SEG_REG(GS, gs);
1687
1688	/*
1689	* Correct the hidden CS granularity flag. Haven't seen it being wrong in any other
1690	* register (yet).
1691	*/
1692	/** @todo Verify this. */
1693	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1694	&& pMixedCtx->cs.Attr.n.u1Present
1695	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1696	{
1697	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1698	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1699	}
1700	#ifdef VBOX_STRICT
1701	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1702	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1703	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1704	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1705	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1706	("Invalid Segment Attributes %#x %#x %#llx\n", pMixedCtx->reg.u32Limit, \
1707	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1708
1709	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1710	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1711	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1712	HMSVM_ASSERT_SEG_GRANULARITY(es);
1713	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1714	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1715
1716	# undef HMSVM_ASSERT_SEL_GRANULARITY
1717	#endif
1718
1719	/*
1720	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1721	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1722	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1723	* See AMD spec. 15.5.1 "Basic operation".
1724	*/
1725	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1726	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1727
1728	/*
1729	* Guest Descriptor-Table registers.
1730	*/
1731	HMSVM_SAVE_SEG_REG(TR, tr);
1732	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1733	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1734	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1735
1736	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1737	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1738
1739	/*
1740	* Guest Debug registers.
1741	*/
1742	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1743	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1744
1745	/*
1746	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1747	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1748	*/
1749	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1750	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1751	{
1752	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1753	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1754	}
1755	}
1756
1757
1758	/**
1759	* Does the necessary state syncing before doing a longjmp to ring-3.
1760	*
1761	* @param pVM Pointer to the VM.
1762	* @param pVCpu Pointer to the VMCPU.
1763	* @param pCtx Pointer to the guest-CPU context.
1764	* @param rcExit The reason for exiting to ring-3. Can be
1765	* VINF_VMM_UNKNOWN_RING3_CALL.
1766	*
1767	* @remarks No-long-jmp zone!!!
1768	*/
1769	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1770	{
1771	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1772	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1773
1774	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1775	if (CPUMIsGuestFPUStateActive(pVCpu))
1776	{
1777	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1778	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1779	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1780	}
1781
1782	/* Restore host debug registers if necessary and resync on next R0 reentry. */
1783	if (CPUMIsGuestDebugStateActive(pVCpu))
1784	{
1785	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
1786	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1787	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1788	}
1789	else if (CPUMIsHyperDebugStateActive(pVCpu))
1790	{
1791	CPUMR0LoadHostDebugState(pVM, pVCpu);
1792	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1793	#ifdef VBOX_STRICT
1794	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1795	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1796	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1797	#endif
1798	}
1799
1800	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1801	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1802	}
1803
1804
1805	/**
1806	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
1807	* any remaining host state) before we longjump to ring-3 and possibly get
1808	* preempted.
1809	*
1810	* @param pVCpu Pointer to the VMCPU.
1811	* @param enmOperation The operation causing the ring-3 longjump.
1812	* @param pvUser The user argument (pointer to the possibly
1813	* out-of-date guest-CPU context).
1814	*
1815	* @remarks Must never be called with @a enmOperation ==
1816	* VMMCALLRING3_VM_R0_ASSERTION.
1817	*/
1818	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1819	{
1820	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
1821	Assert(pVCpu);
1822	Assert(pvUser);
1823	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1824	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1825
1826	VMMRZCallRing3Disable(pVCpu);
1827	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1828	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
1829	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser, VINF_VMM_UNKNOWN_RING3_CALL);
1830	VMMRZCallRing3Enable(pVCpu);
1831	}
1832
1833
1834	/**
1835	* An action requires us to go back to ring-3. This function does the necessary
1836	* steps before we can safely return to ring-3. This is not the same as longjmps
1837	* to ring-3, this is voluntary.
1838	*
1839	* @param pVM Pointer to the VM.
1840	* @param pVCpu Pointer to the VMCPU.
1841	* @param pCtx Pointer to the guest-CPU context.
1842	* @param rcExit The reason for exiting to ring-3. Can be
1843	* VINF_VMM_UNKNOWN_RING3_CALL.
1844	*/
1845	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1846	{
1847	Assert(pVM);
1848	Assert(pVCpu);
1849	Assert(pCtx);
1850	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1851
1852	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
1853	{
1854	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
1855	return;
1856	}
1857
1858	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
1859	VMMRZCallRing3Disable(pVCpu);
1860	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
1861
1862	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
1863	if (pVCpu->hm.s.Event.fPending)
1864	{
1865	hmR0SvmPendingEventToTrpmTrap(pVCpu);
1866	Assert(!pVCpu->hm.s.Event.fPending);
1867	}
1868
1869	/* Sync. the guest state. */
1870	hmR0SvmLongJmpToRing3(pVM, pVCpu, pCtx, rcExit);
1871	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1872
1873	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1874	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
1875	\| CPUM_CHANGED_LDTR
1876	\| CPUM_CHANGED_GDTR
1877	\| CPUM_CHANGED_IDTR
1878	\| CPUM_CHANGED_TR
1879	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
1880
1881	/* On our way back from ring-3 the following needs to be done. */
1882	/** @todo This can change with preemption hooks. */
1883	if (rcExit == VINF_EM_RAW_INTERRUPT)
1884	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
1885	else
1886	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1887
1888	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
1889	VMMRZCallRing3Enable(pVCpu);
1890	}
1891
1892
1893	/**
1894	* Sets up the usage of TSC offsetting for the VCPU.
1895	*
1896	* @param pVCpu Pointer to the VMCPU.
1897	*
1898	* @remarks No-long-jump zone!!!
1899	*/
1900	static void hmR0SvmSetupTscOffsetting(PVMCPU pVCpu)
1901	{
1902	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1903	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
1904	{
1905	uint64_t u64CurTSC = ASMReadTSC();
1906	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
1907	{
1908	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
1909	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
1910	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
1911	}
1912	else
1913	{
1914	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1915	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1916	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
1917	}
1918	}
1919	else
1920	{
1921	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1922	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1923	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
1924	}
1925
1926	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1927	}
1928
1929
1930	/**
1931	* Sets an event as a pending event to be injected into the guest.
1932	*
1933	* @param pVCpu Pointer to the VMCPU.
1934	* @param pEvent Pointer to the SVM event.
1935	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
1936	* page-fault.
1937	*/
1938	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
1939	{
1940	Assert(!pVCpu->hm.s.Event.fPending);
1941	Assert(pEvent->n.u1Valid);
1942
1943	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
1944	pVCpu->hm.s.Event.fPending = true;
1945	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
1946
1947	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
1948	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
1949	}
1950
1951
1952	/**
1953	* Injects an event into the guest upon VMRUN by updating the relevant field
1954	* in the VMCB.
1955	*
1956	* @param pVCpu Pointer to the VMCPU.
1957	* @param pVmcb Pointer to the guest VMCB.
1958	* @param pCtx Pointer to the guest-CPU context.
1959	* @param pEvent Pointer to the event.
1960	*
1961	* @remarks No-long-jump zone!!!
1962	* @remarks Requires CR0!
1963	*/
1964	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
1965	{
1966	pVmcb->ctrl.EventInject.u = pEvent->u;
1967	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
1968
1969	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
1970	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
1971	}
1972
1973
1974
1975	/**
1976	* Converts any TRPM trap into a pending HM event. This is typically used when
1977	* entering from ring-3 (not longjmp returns).
1978	*
1979	* @param pVCpu Pointer to the VMCPU.
1980	*/
1981	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
1982	{
1983	Assert(TRPMHasTrap(pVCpu));
1984	Assert(!pVCpu->hm.s.Event.fPending);
1985
1986	uint8_t uVector;
1987	TRPMEVENT enmTrpmEvent;
1988	RTGCUINT uErrCode;
1989	RTGCUINTPTR GCPtrFaultAddress;
1990	uint8_t cbInstr;
1991
1992	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
1993	AssertRC(rc);
1994
1995	SVMEVENT Event;
1996	Event.u = 0;
1997	Event.n.u1Valid = 1;
1998
1999	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2000	if (enmTrpmEvent == TRPM_TRAP)
2001	{
2002	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2003	switch (uVector)
2004	{
2005	case X86_XCPT_PF:
2006	case X86_XCPT_DF:
2007	case X86_XCPT_TS:
2008	case X86_XCPT_NP:
2009	case X86_XCPT_SS:
2010	case X86_XCPT_GP:
2011	case X86_XCPT_AC:
2012	{
2013	Event.n.u1ErrorCodeValid = 1;
2014	Event.n.u32ErrorCode = uErrCode;
2015	break;
2016	}
2017	}
2018	}
2019	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2020	{
2021	if (uVector == X86_XCPT_NMI)
2022	Event.n.u3Type = SVM_EVENT_NMI;
2023	else
2024	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2025	}
2026	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2027	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2028	else
2029	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2030
2031	rc = TRPMResetTrap(pVCpu);
2032	AssertRC(rc);
2033
2034	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2035	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2036	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2037	}
2038
2039
2040	/**
2041	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2042	* AMD-V to execute any instruction.
2043	*
2044	* @param pvCpu Pointer to the VMCPU.
2045	*/
2046	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2047	{
2048	Assert(pVCpu->hm.s.Event.fPending);
2049	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2050
2051	SVMEVENT Event;
2052	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2053
2054	uint8_t uVector = Event.n.u8Vector;
2055	uint8_t uVectorType = Event.n.u3Type;
2056
2057	TRPMEVENT enmTrapType;
2058	switch (uVectorType)
2059	{
2060	case SVM_EVENT_EXTERNAL_IRQ:
2061	case SVM_EVENT_NMI:
2062	enmTrapType = TRPM_HARDWARE_INT;
2063	break;
2064	case SVM_EVENT_SOFTWARE_INT:
2065	enmTrapType = TRPM_SOFTWARE_INT;
2066	break;
2067	case SVM_EVENT_EXCEPTION:
2068	enmTrapType = TRPM_TRAP;
2069	break;
2070	default:
2071	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2072	enmTrapType = TRPM_32BIT_HACK;
2073	break;
2074	}
2075
2076	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2077
2078	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2079	AssertRC(rc);
2080
2081	if (Event.n.u1ErrorCodeValid)
2082	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2083
2084	if ( uVectorType == SVM_EVENT_EXCEPTION
2085	&& uVector == X86_XCPT_PF)
2086	{
2087	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2088	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2089	}
2090	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2091	{
2092	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2093	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2094	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2095	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2096	}
2097	pVCpu->hm.s.Event.fPending = false;
2098	}
2099
2100
2101	/**
2102	* Gets the guest's interrupt-shadow.
2103	*
2104	* @returns The guest's interrupt-shadow.
2105	* @param pVCpu Pointer to the VMCPU.
2106	* @param pCtx Pointer to the guest-CPU context.
2107	*
2108	* @remarks No-long-jump zone!!!
2109	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2110	*/
2111	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2112	{
2113	/*
2114	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2115	* inhibit interrupts or clear any existing interrupt-inhibition.
2116	*/
2117	uint32_t uIntrState = 0;
2118	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2119	{
2120	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2121	{
2122	/*
2123	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2124	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2125	*/
2126	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2127	}
2128	else
2129	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2130	}
2131	return uIntrState;
2132	}
2133
2134
2135	/**
2136	* Sets the virtual interrupt intercept control in the VMCB which
2137	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2138	* receive interrupts.
2139	*
2140	* @param pVmcb Pointer to the VMCB.
2141	*/
2142	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2143	{
2144	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2145	{
2146	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2147	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2148	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2149	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2150
2151	Log4(("Setting virtual interrupt intercept\n"));
2152	}
2153	}
2154
2155
2156	/**
2157	* Injects any pending events into the guest if the guest is in a state to
2158	* receive them.
2159	*
2160	* @param pVCpu Pointer to the VMCPU.
2161	* @param pCtx Pointer to the guest-CPU context.
2162	*/
2163	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2164	{
2165	Assert(!TRPMHasTrap(pVCpu));
2166
2167	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2168	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2169
2170	SVMEVENT Event;
2171	Event.u = 0;
2172	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2173	{
2174	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2175	Assert(Event.n.u1Valid);
2176	bool fInject = true;
2177	if ( fIntShadow
2178	&& ( Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
2179	\|\| Event.n.u3Type == SVM_EVENT_NMI))
2180	{
2181	fInject = false;
2182	}
2183
2184	if (fInject)
2185	{
2186	pVCpu->hm.s.Event.fPending = false;
2187	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2188	}
2189	else
2190	hmR0SvmSetVirtIntrIntercept(pVmcb);
2191	} /** @todo SMI. SMIs take priority over NMIs. */
2192	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2193	{
2194	if (!fIntShadow)
2195	{
2196	Log4(("Injecting NMI\n"));
2197
2198	Event.n.u1Valid = 1;
2199	Event.n.u8Vector = X86_XCPT_NMI;
2200	Event.n.u3Type = SVM_EVENT_NMI;
2201
2202	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2203	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2204	}
2205	else
2206	hmR0SvmSetVirtIntrIntercept(pVmcb);
2207	}
2208	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2209	{
2210	/* Check if there are guest external interrupts (PIC/APIC) pending and inject them, if the guest can receive them. */
2211	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2212	if ( !fBlockInt
2213	&& !fIntShadow)
2214	{
2215	uint8_t u8Interrupt;
2216	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2217	if (RT_SUCCESS(rc))
2218	{
2219	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2220
2221	Event.n.u1Valid = 1;
2222	Event.n.u8Vector = u8Interrupt;
2223	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2224
2225	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2226	STAM_COUNTER_INC(&pVCpu->hm.s.StatIntInject);
2227	}
2228	else
2229	{
2230	/** @todo Does this actually happen? If not turn it into an assertion. */
2231	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2232	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2233	}
2234	}
2235	else
2236	hmR0SvmSetVirtIntrIntercept(pVmcb);
2237	}
2238
2239	/* Update the guest interrupt shadow in the VMCB. */
2240	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2241	}
2242
2243
2244	/**
2245	* Reports world-switch error and dumps some useful debug info.
2246	*
2247	* @param pVM Pointer to the VM.
2248	* @param pVCpu Pointer to the VMCPU.
2249	* @param rcVMRun The return code from VMRUN (or
2250	* VERR_SVM_INVALID_GUEST_STATE for invalid
2251	* guest-state).
2252	* @param pCtx Pointer to the guest-CPU context.
2253	*/
2254	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2255	{
2256	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2257	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2258
2259	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2260	{
2261	HMDumpRegs(pVM, pVCpu, pCtx);
2262	#ifdef VBOX_STRICT
2263	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2264	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2265	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2266	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2267	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2268	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2269	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2270	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2271	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2272	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2273	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2274
2275	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2276	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2277	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2278
2279	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2280	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2281	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2282	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2283	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2284	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2285	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2286	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2287	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2288	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2289
2290	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2291	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2292	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2293	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2294	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2295	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2296	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2297	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2298	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2299	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2300	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2301	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2302	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2303	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2304	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2305	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2306	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2307
2308	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2309	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2310
2311	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2312	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2313	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2314	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2315	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2316	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2317	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2318	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2319	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2320	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2321	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2322	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2323	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2324	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2325	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2326	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2327	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2328	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2329	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2330	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2331
2332	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2333	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2334
2335	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2336	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2337	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2338	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2339
2340	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2341	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2342
2343	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2344	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2345	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2346	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2347
2348	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2349	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2350	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2351	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2352	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2353	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2354	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2355
2356	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2357	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2358	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2359	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2360
2361	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2362	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2363	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2364
2365	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2366	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2367	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2368	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2369	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2370	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2371	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2372	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2373	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2374	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2375	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2376	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2377	#endif
2378	}
2379	else
2380	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2381	}
2382
2383
2384	/**
2385	* Check per-VM and per-VCPU force flag actions that require us to go back to
2386	* ring-3 for one reason or another.
2387	*
2388	* @returns VBox status code (information status code included).
2389	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2390	* ring-3.
2391	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2392	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2393	* interrupts)
2394	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2395	* all EMTs to be in ring-3.
2396	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2397	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2398	* to the EM loop.
2399	*
2400	* @param pVM Pointer to the VM.
2401	* @param pVCpu Pointer to the VMCPU.
2402	* @param pCtx Pointer to the guest-CPU context.
2403	*/
2404	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2405	{
2406	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2407
2408	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
2409	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
2410	\| VMCPU_FF_REQUEST \| VMCPU_FF_HM_UPDATE_CR3))
2411	{
2412	/* Pending HM CR3 sync. No PAE PDPEs (VMCPU_FF_HM_UPDATE_PAE_PDPES) on AMD-V. */
2413	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2414	{
2415	int rc = PGMUpdateCR3(pVCpu, pCtx->cr3);
2416	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
2417	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2418	}
2419
2420	/* Pending PGM C3 sync. */
2421	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2422	{
2423	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2424	if (rc != VINF_SUCCESS)
2425	{
2426	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2427	return rc;
2428	}
2429	}
2430
2431	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2432	/* -XXX- what was that about single stepping? */
2433	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2434	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2435	{
2436	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2437	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2438	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2439	return rc;
2440	}
2441
2442	/* Pending VM request packets, such as hardware interrupts. */
2443	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2444	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2445	{
2446	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2447	return VINF_EM_PENDING_REQUEST;
2448	}
2449
2450	/* Pending PGM pool flushes. */
2451	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2452	{
2453	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2454	return VINF_PGM_POOL_FLUSH_PENDING;
2455	}
2456
2457	/* Pending DMA requests. */
2458	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2459	{
2460	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2461	return VINF_EM_RAW_TO_R3;
2462	}
2463	}
2464
2465	return VINF_SUCCESS;
2466	}
2467
2468
2469	/**
2470	* Does the preparations before executing guest code in AMD-V.
2471	*
2472	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2473	* recompiler. We must be cautious what we do here regarding committing
2474	* guest-state information into the the VMCB assuming we assuredly execute the
2475	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2476	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2477	* that the recompiler can (and should) use them when it resumes guest
2478	* execution. Otherwise such operations must be done when we can no longer
2479	* exit to ring-3.
2480	*
2481	* @returns VBox status code (informational status codes included).
2482	* @retval VINF_SUCCESS if we can proceed with running the guest.
2483	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2484	*
2485	* @param pVM Pointer to the VM.
2486	* @param pVCpu Pointer to the VMCPU.
2487	* @param pCtx Pointer to the guest-CPU context.
2488	* @param pSvmTransient Pointer to the SVM transient structure.
2489	*/
2490	DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2491	{
2492	/* Check force flag actions that might require us to go back to ring-3. */
2493	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2494	if (rc != VINF_SUCCESS)
2495	return rc;
2496
2497	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2498	/* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.) */
2499	pSvmTransient->uEFlags = ASMIntDisableFlags();
2500	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2501	{
2502	ASMSetFlags(pSvmTransient->uEFlags);
2503	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2504	/* Don't use VINF_EM_RAW_INTERRUPT_HYPER as we can't assume the host does kernel preemption. Maybe some day? */
2505	return VINF_EM_RAW_INTERRUPT;
2506	}
2507	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2508	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2509	#endif
2510
2511	/* Convert any pending TRPM traps to HM events for injection. */
2512	/** @todo Optimization: move this before disabling interrupts, restore state
2513	* using pVmcb->ctrl.EventInject.u. */
2514	if (TRPMHasTrap(pVCpu))
2515	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2516
2517	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2518
2519	return VINF_SUCCESS;
2520	}
2521
2522
2523	/**
2524	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2525	* means there is no backing out to ring-3 or anywhere else at this
2526	* point.
2527	*
2528	* @param pVM Pointer to the VM.
2529	* @param pVCpu Pointer to the VMCPU.
2530	* @param pCtx Pointer to the guest-CPU context.
2531	* @param pSvmTransient Pointer to the SVM transient structure.
2532	*
2533	* @remarks Called with preemption disabled.
2534	* @remarks No-long-jump zone!!!
2535	*/
2536	DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2537	{
2538	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2539	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2540
2541	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2542	/** @todo I don't see the point of this, VMMR0EntryFast() already disables interrupts for the entire period. */
2543	pSvmTransient->uEFlags = ASMIntDisableFlags();
2544	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2545	#endif
2546
2547	/*
2548	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2549	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2550	*/
2551	/** @todo The above assumption could be wrong. It's not documented what
2552	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2553	* hard way. */
2554	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2555	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2556
2557	#ifdef HMVMX_SYNC_FULL_GUEST_STATE
2558	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2559	#endif
2560
2561	/* Load the guest state. */
2562	int rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2563	AssertRC(rc);
2564	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
2565	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2566
2567	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2568	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2569	pVmcb->ctrl.u64VmcbCleanBits = 0;
2570
2571	/*
2572	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2573	* so we can update it on the way back if the guest changed the TPR.
2574	*/
2575	if (pVCpu->hm.s.svm.fSyncVTpr)
2576	{
2577	if (pVM->hm.s.fTPRPatchingActive)
2578	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2579	else
2580	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2581	}
2582
2583	/* Flush the appropriate tagged-TLB entries. */
2584	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2585	hmR0SvmFlushTaggedTlb(pVCpu);
2586	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2587
2588	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2589	to start executing. */
2590
2591	/*
2592	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2593	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2594	*
2595	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2596	*/
2597	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2598	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2599	{
2600	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2601	uint64_t u64GuestTscAux = 0;
2602	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2603	AssertRC(rc2);
2604	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2605	}
2606	}
2607
2608
2609	/**
2610	* Wrapper for running the guest code in AMD-V.
2611	*
2612	* @returns VBox strict status code.
2613	* @param pVM Pointer to the VM.
2614	* @param pVCpu Pointer to the VMCPU.
2615	* @param pCtx Pointer to the guest-CPU context.
2616	*
2617	* @remarks No-long-jump zone!!!
2618	*/
2619	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2620	{
2621	/*
2622	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2623	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2624	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2625	*/
2626	#ifdef VBOX_WITH_KERNEL_USING_XMM
2627	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2628	pVCpu->hm.s.svm.pfnVMRun);
2629	#else
2630	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2631	#endif
2632	}
2633
2634
2635	/**
2636	* Performs some essential restoration of state after running guest code in
2637	* AMD-V.
2638	*
2639	* @param pVM Pointer to the VM.
2640	* @param pVCpu Pointer to the VMCPU.
2641	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2642	* out-of-sync. Make sure to update the required fields
2643	* before using them.
2644	* @param pSvmTransient Pointer to the SVM transient structure.
2645	* @param rcVMRun Return code of VMRUN.
2646	*
2647	* @remarks Called with interrupts disabled.
2648	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2649	* unconditionally when it is safe to do so.
2650	*/
2651	DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2652	{
2653	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2654
2655	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2656	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2657
2658	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2659	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2660
2661	/* Restore host's TSC_AUX if required. */
2662	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2663	{
2664	if (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2665	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2666
2667	/** @todo Find a way to fix hardcoding a guestimate. */
2668	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() +
2669	pVmcb->ctrl.u64TSCOffset - 0x400);
2670	}
2671
2672	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2673	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2674
2675	Assert(!(ASMGetFlags() & X86_EFL_IF));
2676	ASMSetFlags(pSvmTransient->uEFlags); /* Enable interrupts. */
2677
2678	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pMixedCtx);
2679	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2680
2681	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2682	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2683	{
2684	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2685	return;
2686	}
2687
2688	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2689	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2690	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2691
2692	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2693	{
2694	if (pVCpu->hm.s.svm.fSyncVTpr)
2695	{
2696	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2697	if ( pVM->hm.s.fTPRPatchingActive
2698	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2699	{
2700	int rc = PDMApicSetTPR(pVCpu, (pMixedCtx->msrLSTAR & 0xff));
2701	AssertRC(rc);
2702	}
2703	else if ((uint8_t)(pSvmTransient->u8GuestTpr >> 4) != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2704	{
2705	int rc = PDMApicSetTPR(pVCpu, (pVmcb->ctrl.IntCtrl.n.u8VTPR << 4));
2706	AssertRC(rc);
2707	}
2708	}
2709	}
2710	}
2711
2712
2713	/**
2714	* Runs the guest code using AMD-V.
2715	*
2716	* @returns VBox status code.
2717	* @param pVM Pointer to the VM.
2718	* @param pVCpu Pointer to the VMCPU.
2719	* @param pCtx Pointer to the guest-CPU context.
2720	*/
2721	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2722	{
2723	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2724	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2725
2726	SVMTRANSIENT SvmTransient;
2727	uint32_t cLoops = 0;
2728	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2729	int rc = VERR_INTERNAL_ERROR_5;
2730
2731	for (;; cLoops++)
2732	{
2733	Assert(!HMR0SuspendPending());
2734	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
2735	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
2736	(unsigned)RTMpCpuId(), cLoops));
2737
2738	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
2739	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
2740	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
2741	if (rc != VINF_SUCCESS)
2742	break;
2743
2744	/*
2745	* No longjmps to ring-3 from this point on!!!
2746	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2747	* This also disables flushing of the R0-logger instance (if any).
2748	*/
2749	VMMRZCallRing3Disable(pVCpu);
2750	VMMRZCallRing3RemoveNotification(pVCpu);
2751	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
2752
2753	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
2754
2755	/*
2756	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
2757	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
2758	*/
2759	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
2760	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
2761	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
2762	{
2763	if (rc == VINF_SUCCESS)
2764	rc = VERR_SVM_INVALID_GUEST_STATE;
2765	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2766	return rc;
2767	}
2768
2769	/* Handle the #VMEXIT. */
2770	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
2771	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
2772	if (rc != VINF_SUCCESS)
2773	break;
2774	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
2775	{
2776	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
2777	rc = VINF_EM_RAW_INTERRUPT;
2778	break;
2779	}
2780	}
2781
2782	if (rc == VERR_EM_INTERPRETER)
2783	rc = VINF_EM_RAW_EMULATE_INSTR;
2784	else if (rc == VINF_EM_RESET)
2785	rc = VINF_EM_TRIPLE_FAULT;
2786	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
2787	return rc;
2788	}
2789
2790
2791	/**
2792	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
2793	*
2794	* @returns VBox status code (informational status codes included).
2795	* @param pVCpu Pointer to the VMCPU.
2796	* @param pCtx Pointer to the guest-CPU context.
2797	* @param pSvmTransient Pointer to the SVM transient structure.
2798	*/
2799	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2800	{
2801	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
2802	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
2803
2804	/*
2805	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
2806	* normal workloads (for some definition of "normal").
2807	*/
2808	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
2809	switch (pSvmTransient->u64ExitCode)
2810	{
2811	case SVM_EXIT_NPF:
2812	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
2813
2814	case SVM_EXIT_IOIO:
2815	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
2816
2817	case SVM_EXIT_RDTSC:
2818	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
2819
2820	case SVM_EXIT_RDTSCP:
2821	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
2822
2823	case SVM_EXIT_CPUID:
2824	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
2825
2826	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
2827	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
2828
2829	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
2830	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
2831
2832	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
2833	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
2834
2835	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
2836	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
2837
2838	case SVM_EXIT_MONITOR:
2839	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
2840
2841	case SVM_EXIT_MWAIT:
2842	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
2843
2844	case SVM_EXIT_HLT:
2845	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
2846
2847	case SVM_EXIT_READ_CR0:
2848	case SVM_EXIT_READ_CR3:
2849	case SVM_EXIT_READ_CR4:
2850	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
2851
2852	case SVM_EXIT_WRITE_CR0:
2853	case SVM_EXIT_WRITE_CR3:
2854	case SVM_EXIT_WRITE_CR4:
2855	case SVM_EXIT_WRITE_CR8:
2856	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
2857
2858	case SVM_EXIT_VINTR:
2859	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
2860
2861	case SVM_EXIT_INTR:
2862	case SVM_EXIT_FERR_FREEZE:
2863	case SVM_EXIT_NMI:
2864	case SVM_EXIT_INIT:
2865	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
2866
2867	case SVM_EXIT_MSR:
2868	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
2869
2870	case SVM_EXIT_INVLPG:
2871	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
2872
2873	case SVM_EXIT_WBINVD:
2874	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
2875
2876	case SVM_EXIT_INVD:
2877	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
2878
2879	case SVM_EXIT_RDPMC:
2880	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
2881
2882	default:
2883	{
2884	switch (pSvmTransient->u64ExitCode)
2885	{
2886	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2887	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
2888	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
2889	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2890	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
2891
2892	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2893	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
2894	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
2895	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2896	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
2897
2898	case SVM_EXIT_TASK_SWITCH:
2899	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
2900
2901	case SVM_EXIT_VMMCALL:
2902	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
2903
2904	case SVM_EXIT_SHUTDOWN:
2905	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
2906
2907	case SVM_EXIT_INVLPGA:
2908	case SVM_EXIT_RSM:
2909	case SVM_EXIT_VMRUN:
2910	case SVM_EXIT_VMLOAD:
2911	case SVM_EXIT_VMSAVE:
2912	case SVM_EXIT_STGI:
2913	case SVM_EXIT_CLGI:
2914	case SVM_EXIT_SKINIT:
2915	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
2916
2917	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2918	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
2919	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
2920	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
2921	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
2922	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
2923	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
2924	{
2925	SVMEVENT Event;
2926	Event.u = 0;
2927	Event.n.u1Valid = 1;
2928	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2929	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
2930
2931	switch (Event.n.u8Vector)
2932	{
2933	case X86_XCPT_DE:
2934	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
2935	break;
2936
2937	case X86_XCPT_BP:
2938	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
2939	* next instruction. */
2940	/** @todo Investigate this later. */
2941	break;
2942
2943	case X86_XCPT_UD:
2944	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
2945	break;
2946
2947	case X86_XCPT_NP:
2948	Event.n.u1ErrorCodeValid = 1;
2949	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
2950	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
2951	break;
2952
2953	case X86_XCPT_SS:
2954	Event.n.u1ErrorCodeValid = 1;
2955	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
2956	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
2957	break;
2958
2959	case X86_XCPT_GP:
2960	Event.n.u1ErrorCodeValid = 1;
2961	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
2962	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
2963	break;
2964	}
2965
2966	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
2967	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2968	return VINF_SUCCESS;
2969	}
2970	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
2971
2972	default:
2973	{
2974	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit code %#x\n", u32ExitCode));
2975	return VERR_SVM_UNEXPECTED_EXIT;
2976	}
2977	}
2978	}
2979	}
2980	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
2981	}
2982
2983
2984	#ifdef DEBUG
2985	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
2986	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
2987	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
2988
2989	# define HMSVM_ASSERT_PREEMPT_CPUID() \
2990	do \
2991	{ \
2992	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
2993	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
2994	} while (0)
2995
2996	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
2997	do { \
2998	AssertPtr(pVCpu); \
2999	AssertPtr(pCtx); \
3000	AssertPtr(pSvmTransient); \
3001	Assert(ASMIntAreEnabled()); \
3002	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3003	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3004	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3005	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3006	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3007	HMSVM_ASSERT_PREEMPT_CPUID(); \
3008	} while (0)
3009	#else /* Release builds */
3010	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3011	#endif
3012
3013
3014	/**
3015	* Worker for hmR0SvmInterpretInvlpg().
3016	*
3017	* @return VBox status code.
3018	* @param pVCpu Pointer to the VMCPU.
3019	* @param pCpu Pointer to the disassembler state.
3020	* @param pRegFrame Pointer to the register frame.
3021	*/
3022	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3023	{
3024	DISQPVPARAMVAL Param1;
3025	RTGCPTR GCPtrPage;
3026
3027	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3028	if (RT_FAILURE(rc))
3029	return VERR_EM_INTERPRETER;
3030
3031	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3032	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3033	{
3034	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3035	return VERR_EM_INTERPRETER;
3036
3037	GCPtrPage = Param1.val.val64;
3038	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3039	rc = VBOXSTRICTRC_VAL(rc2);
3040	}
3041	else
3042	{
3043	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3044	rc = VERR_EM_INTERPRETER;
3045	}
3046
3047	return rc;
3048	}
3049
3050
3051	/**
3052	* Interprets INVLPG.
3053	*
3054	* @returns VBox status code.
3055	* @retval VINF_* Scheduling instructions.
3056	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3057	* @retval VERR_* Fatal errors.
3058	*
3059	* @param pVM Pointer to the VM.
3060	* @param pRegFrame Pointer to the register frame.
3061	*
3062	* @remarks Updates the RIP if the instruction was executed successfully.
3063	*/
3064	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3065	{
3066	/* Only allow 32 & 64 bit code. */
3067	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3068	{
3069	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3070	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3071	if ( RT_SUCCESS(rc)
3072	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3073	{
3074	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3075	if (RT_SUCCESS(rc))
3076	pRegFrame->rip += pDis->cbInstr;
3077	return rc;
3078	}
3079	else
3080	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3081	}
3082	return VERR_EM_INTERPRETER;
3083	}
3084
3085
3086	/**
3087	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3088	*
3089	* @param pVCpu Pointer to the VMCPU.
3090	*/
3091	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3092	{
3093	SVMEVENT Event;
3094	Event.u = 0;
3095	Event.n.u1Valid = 1;
3096	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3097	Event.n.u8Vector = X86_XCPT_UD;
3098	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3099	}
3100
3101
3102	/**
3103	* Sets an debug (#DB) exception as pending-for-injection into the VM.
3104	*
3105	* @param pVCpu Pointer to the VMCPU.
3106	*/
3107	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3108	{
3109	SVMEVENT Event;
3110	Event.u = 0;
3111	Event.n.u1Valid = 1;
3112	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3113	Event.n.u8Vector = X86_XCPT_DB;
3114	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3115	}
3116
3117
3118	/**
3119	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3120	*
3121	* @param pVCpu Pointer to the VMCPU.
3122	* @param pCtx Pointer to the guest-CPU context.
3123	* @param u32ErrCode The error-code for the page-fault.
3124	* @param uFaultAddress The page fault address (CR2).
3125	*
3126	* @remarks This updates the guest CR2 with @a uFaultAddress!
3127	*/
3128	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3129	{
3130	SVMEVENT Event;
3131	Event.u = 0;
3132	Event.n.u1Valid = 1;
3133	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3134	Event.n.u8Vector = X86_XCPT_PF;
3135	Event.n.u1ErrorCodeValid = 1;
3136	Event.n.u32ErrorCode = u32ErrCode;
3137
3138	/* Update CR2 of the guest. */
3139	pCtx->cr2 = uFaultAddress;
3140
3141	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3142	}
3143
3144
3145	/**
3146	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3147	* VM.
3148	*
3149	* @param pVCpu Pointer to the VMCPU.
3150	*/
3151	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3152	{
3153	SVMEVENT Event;
3154	Event.u = 0;
3155	Event.n.u1Valid = 1;
3156	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3157	Event.n.u8Vector = X86_XCPT_NM;
3158	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3159	}
3160
3161
3162	/**
3163	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3164	*
3165	* @param pVCpu Pointer to the VMCPU.
3166	*/
3167	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3168	{
3169	SVMEVENT Event;
3170	Event.u = 0;
3171	Event.n.u1Valid = 1;
3172	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3173	Event.n.u8Vector = X86_XCPT_MF;
3174	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3175	}
3176
3177
3178	/**
3179	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3180	*
3181	* @param pVCpu Pointer to the VMCPU.
3182	*/
3183	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3184	{
3185	SVMEVENT Event;
3186	Event.u = 0;
3187	Event.n.u1Valid = 1;
3188	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3189	Event.n.u8Vector = X86_XCPT_DF;
3190	Event.n.u1ErrorCodeValid = 1;
3191	Event.n.u32ErrorCode = 0;
3192	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3193	}
3194
3195
3196	/**
3197	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3198	* guests. This simply looks up the patch record at EIP and does the required.
3199	*
3200	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3201	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3202	* TPR). See hmR3ReplaceTprInstr() for the details.
3203	*
3204	* @returns VBox status code.
3205	* @param pVM Pointer to the VM.
3206	* @param pVCpu Pointer to the VMCPU.
3207	* @param pCtx Pointer to the guest-CPU context.
3208	*/
3209	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3210	{
3211	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3212	for (;;)
3213	{
3214	bool fPending;
3215	uint8_t u8Tpr;
3216
3217	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3218	if (!pPatch)
3219	break;
3220
3221	switch (pPatch->enmType)
3222	{
3223	case HMTPRINSTR_READ:
3224	{
3225	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3226	AssertRC(rc);
3227
3228	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3229	AssertRC(rc);
3230	pCtx->rip += pPatch->cbOp;
3231	break;
3232	}
3233
3234	case HMTPRINSTR_WRITE_REG:
3235	case HMTPRINSTR_WRITE_IMM:
3236	{
3237	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3238	{
3239	uint32_t u32Val;
3240	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3241	AssertRC(rc);
3242	u8Tpr = u32Val;
3243	}
3244	else
3245	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3246
3247	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3248	AssertRC(rc2);
3249	pCtx->rip += pPatch->cbOp;
3250	break;
3251	}
3252
3253	default:
3254	AssertMsgFailedReturn(("Unexpected patch type %d\n", pPatch->enmType), VERR_SVM_UNEXPECTED_PATCH_TYPE);
3255	break;
3256	}
3257	}
3258
3259	return VINF_SUCCESS;
3260	}
3261
3262	/**
3263	* Determines if an exception is a contributory exception. Contributory
3264	* exceptions are ones which can cause double-faults. Page-fault is
3265	* intentionally not included here as it's a conditional contributory exception.
3266	*
3267	* @returns true if the exception is contributory, false otherwise.
3268	* @param uVector The exception vector.
3269	*/
3270	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3271	{
3272	switch (uVector)
3273	{
3274	case X86_XCPT_GP:
3275	case X86_XCPT_SS:
3276	case X86_XCPT_NP:
3277	case X86_XCPT_TS:
3278	case X86_XCPT_DE:
3279	return true;
3280	default:
3281	break;
3282	}
3283	return false;
3284	}
3285
3286
3287	/**
3288	* Handle a condition that occurred while delivering an event through the guest
3289	* IDT.
3290	*
3291	* @returns VBox status code (informational error codes included).
3292	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3293	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3294	* continue execution of the guest which will delivery the #DF.
3295	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3296	*
3297	* @param pVCpu Pointer to the VMCPU.
3298	* @param pCtx Pointer to the guest-CPU context.
3299	* @param pSvmTransient Pointer to the SVM transient structure.
3300	*
3301	* @remarks No-long-jump zone!!!
3302	*/
3303	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3304	{
3305	int rc = VINF_SUCCESS;
3306	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3307
3308	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3309	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3310	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3311	{
3312	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3313	uint8_t uExitVector = UINT8_MAX; /* Start off with an invalid vector, updated when it's valid. See below. */
3314
3315	typedef enum
3316	{
3317	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3318	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3319	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3320	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3321	} SVMREFLECTXCPT;
3322
3323	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3324	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3325	{
3326	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3327	{
3328	uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3329	if ( uExitVector == X86_XCPT_PF
3330	&& uIdtVector == X86_XCPT_PF)
3331	{
3332	pSvmTransient->fVectoringPF = true;
3333	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3334	}
3335	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3336	&& hmR0SvmIsContributoryXcpt(uExitVector)
3337	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3338	\|\| uIdtVector == X86_XCPT_PF))
3339	{
3340	enmReflect = SVMREFLECTXCPT_DF;
3341	Log4(("IDT: Pending vectoring #DF %#RX64 uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo, uExitVector));
3342	}
3343	else if (uIdtVector == X86_XCPT_DF)
3344	enmReflect = SVMREFLECTXCPT_TF;
3345	else
3346	enmReflect = SVMREFLECTXCPT_XCPT;
3347	}
3348	else
3349	{
3350	/*
3351	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3352	* exception to the guest after handling the VM-exit.
3353	*/
3354	enmReflect = SVMREFLECTXCPT_XCPT;
3355	}
3356	}
3357	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3358	{
3359	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3360	enmReflect = SVMREFLECTXCPT_XCPT;
3361	}
3362
3363	switch (enmReflect)
3364	{
3365	case SVMREFLECTXCPT_XCPT:
3366	{
3367	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3368
3369	pVCpu->hm.s.Event.u64IntrInfo = pVmcb->ctrl.ExitIntInfo.u;
3370	pVCpu->hm.s.Event.fPending = true;
3371
3372	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3373	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3374	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3375	break;
3376	}
3377
3378	case SVMREFLECTXCPT_DF:
3379	{
3380	hmR0SvmSetPendingXcptDF(pVCpu);
3381	rc = VINF_HM_DOUBLE_FAULT;
3382	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3383	uIdtVector, uExitVector));
3384	break;
3385	}
3386
3387	case SVMREFLECTXCPT_TF:
3388	{
3389	rc = VINF_EM_RESET;
3390	Log4(("IDT: Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", uIdtVector, uExitVector));
3391	break;
3392	}
3393
3394	default:
3395	Assert(rc == VINF_SUCCESS);
3396	break;
3397	}
3398	}
3399	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3400	return rc;
3401	}
3402
3403
3404	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3405	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3406	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3407
3408	/**
3409	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3410	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3411	*/
3412	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3413	{
3414	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3415	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3416	/* 32-bit Windows hosts (4 cores) has trouble with this on Intel; causes higher interrupt latency. Assuming the
3417	same for AMD-V.*/
3418	#if HC_ARCH_BITS == 64 && defined(VBOX_WITH_VMMR0_DISABLE_PREEMPTION)
3419	Assert(ASMIntAreEnabled());
3420	return VINF_SUCCESS;
3421	#else
3422	return VINF_EM_RAW_INTERRUPT;
3423	#endif
3424	}
3425
3426
3427	/**
3428	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3429	*/
3430	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3431	{
3432	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3433	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3434	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3435	return VINF_SUCCESS;
3436	}
3437
3438
3439	/**
3440	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3441	*/
3442	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3443	{
3444	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3445	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3446	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3447	return VINF_SUCCESS;
3448	}
3449
3450
3451	/**
3452	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3453	*/
3454	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3455	{
3456	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3457	PVM pVM = pVCpu->CTX_SUFF(pVM);
3458	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3459	if (RT_LIKELY(rc == VINF_SUCCESS))
3460	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3461	else
3462	{
3463	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3464	rc = VERR_EM_INTERPRETER;
3465	}
3466	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3467	return rc;
3468	}
3469
3470
3471	/**
3472	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3473	*/
3474	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3475	{
3476	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3477	PVM pVM = pVCpu->CTX_SUFF(pVM);
3478	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3479	if (RT_LIKELY(rc == VINF_SUCCESS))
3480	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3481	else
3482	{
3483	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3484	rc = VERR_EM_INTERPRETER;
3485	}
3486	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3487	return rc;
3488	}
3489
3490
3491	/**
3492	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3493	*/
3494	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3495	{
3496	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3497	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3498	if (RT_LIKELY(rc == VINF_SUCCESS))
3499	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3500	else
3501	{
3502	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3503	rc = VERR_EM_INTERPRETER;
3504	}
3505	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3506	return rc;
3507	}
3508
3509
3510	/**
3511	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3512	*/
3513	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3514	{
3515	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3516	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3517	if (RT_LIKELY(rc == VINF_SUCCESS))
3518	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3519	else
3520	{
3521	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3522	rc = VERR_EM_INTERPRETER;
3523	}
3524	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3525	return rc;
3526	}
3527
3528
3529	/**
3530	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3531	*/
3532	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3533	{
3534	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3535	PVM pVM = pVCpu->CTX_SUFF(pVM);
3536	Assert(!pVM->hm.s.fNestedPaging);
3537
3538	/** @todo Decode Assist. */
3539	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3540	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3541	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3542	return rc;
3543	}
3544
3545
3546	/**
3547	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3548	*/
3549	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3550	{
3551	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3552	pCtx->rip++; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3553	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3554	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3555	return rc;
3556	}
3557
3558
3559	/**
3560	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3561	*/
3562	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3563	{
3564	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3565	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3566	if (RT_LIKELY(rc == VINF_SUCCESS))
3567	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3568	else
3569	{
3570	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3571	rc = VERR_EM_INTERPRETER;
3572	}
3573	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3574	return rc;
3575	}
3576
3577
3578	/**
3579	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3580	*/
3581	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3582	{
3583	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3584	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3585	int rc = VBOXSTRICTRC_VAL(rc2);
3586	if ( rc == VINF_EM_HALT
3587	\|\| rc == VINF_SUCCESS)
3588	{
3589	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3590
3591	if ( rc == VINF_EM_HALT
3592	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3593	{
3594	rc = VINF_SUCCESS;
3595	}
3596	}
3597	else
3598	{
3599	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3600	rc = VERR_EM_INTERPRETER;
3601	}
3602	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3603	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3604	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3605	return rc;
3606	}
3607
3608
3609	/**
3610	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
3611	* Conditional #VMEXIT.
3612	*/
3613	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3614	{
3615	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3616	return VINF_EM_RESET;
3617	}
3618
3619
3620	/**
3621	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
3622	*/
3623	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3624	{
3625	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3626
3627	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3628
3629	/** @todo Decode Assist. */
3630	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3631	int rc = VBOXSTRICTRC_VAL(rc2);
3632	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
3633	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
3634	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
3635	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
3636	return rc;
3637	}
3638
3639
3640	/**
3641	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
3642	*/
3643	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3644	{
3645	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3646	/** @todo Decode Assist. */
3647	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3648	int rc = VBOXSTRICTRC_VAL(rc2);
3649	if (rc == VINF_SUCCESS)
3650	{
3651	/* RIP has been updated by EMInterpretInstruction(). */
3652	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
3653	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
3654	{
3655	case 0: /* CR0. */
3656	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
3657	break;
3658
3659	case 3: /* CR3. */
3660	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
3661	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
3662	break;
3663
3664	case 4: /* CR4. */
3665	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
3666	break;
3667
3668	case 8: /* CR8 (TPR). */
3669	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3670	break;
3671
3672	default:
3673	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
3674	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
3675	break;
3676	}
3677	}
3678	else
3679	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
3680	return rc;
3681	}
3682
3683
3684	/**
3685	* #VMEXIT handler for instructions that result in a #UD exception delivered to
3686	* the guest.
3687	*/
3688	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3689	{
3690	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3691	hmR0SvmSetPendingXcptUD(pVCpu);
3692	return VINF_SUCCESS;
3693	}
3694
3695
3696	/**
3697	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
3698	*/
3699	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3700	{
3701	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3702	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3703	PVM pVM = pVCpu->CTX_SUFF(pVM);
3704
3705	int rc;
3706	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
3707	{
3708	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
3709
3710	/* Handle TPR patching; intercepted LSTAR write. */
3711	if ( pVM->hm.s.fTPRPatchingActive
3712	&& pCtx->ecx == MSR_K8_LSTAR)
3713	{
3714	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
3715	{
3716	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
3717	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
3718	AssertRC(rc2);
3719	}
3720	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3721	return VINF_SUCCESS;
3722	}
3723
3724	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3725	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
3726
3727	if (pCtx->ecx == MSR_K6_EFER)
3728	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
3729	}
3730	else
3731	{
3732	/* MSR Read access. */
3733	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
3734	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3735	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
3736	}
3737
3738	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
3739	return rc;
3740	}
3741
3742
3743	/**
3744	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
3745	*/
3746	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3747	{
3748	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3749	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
3750
3751	/* We should -not- get this VM-exit if the guest is debugging. */
3752	if (CPUMIsGuestDebugStateActive(pVCpu))
3753	{
3754	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx));
3755	return VERR_SVM_UNEXPECTED_EXIT;
3756	}
3757
3758	if ( !DBGFIsStepping(pVCpu)
3759	&& !CPUMIsHyperDebugStateActive(pVCpu))
3760	{
3761	/* Don't intercept DRx read and writes. */
3762	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3763	pVmcb->ctrl.u16InterceptRdDRx = 0;
3764	pVmcb->ctrl.u16InterceptWrDRx = 0;
3765	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3766
3767	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
3768	PVM pVM = pVCpu->CTX_SUFF(pVM);
3769	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3770	AssertRC(rc);
3771	Assert(CPUMIsGuestDebugStateActive(pVCpu));
3772
3773	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
3774	return rc;
3775	}
3776
3777	/** @todo Decode assist. */
3778	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3779	int rc = VBOXSTRICTRC_VAL(rc2);
3780	if (RT_LIKELY(rc == VINF_SUCCESS))
3781	{
3782	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
3783	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3784	}
3785	else
3786	Assert(rc == VERR_EM_INTERPRETER);
3787	return rc;
3788	}
3789
3790
3791	/**
3792	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
3793	*/
3794	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3795	{
3796	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3797	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
3798	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3799	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
3800	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
3801	return rc;
3802	}
3803
3804
3805	/**
3806	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
3807	*/
3808	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3809	{
3810	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3811
3812	/* I/O operation lookup arrays. */
3813	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
3814	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
3815	the result (in AL/AX/EAX). */
3816	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3817
3818	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3819	PVM pVM = pVCpu->CTX_SUFF(pVM);
3820
3821	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
3822	SVMIOIOEXIT IoExitInfo;
3823	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
3824	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
3825	uint32_t uIOSize = s_aIOSize[uIOWidth];
3826	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
3827
3828	if (RT_UNLIKELY(!uIOSize))
3829	{
3830	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
3831	return VERR_EM_INTERPRETER;
3832	}
3833
3834	int rc;
3835	if (IoExitInfo.n.u1STR)
3836	{
3837	/* INS/OUTS - I/O String instruction. */
3838	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
3839
3840	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
3841	* in EXITINFO1? Investigate once this thing is up and running. */
3842
3843	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
3844	if (rc == VINF_SUCCESS)
3845	{
3846	if (IoExitInfo.n.u1Type == 0) /* OUT */
3847	{
3848	VBOXSTRICTRC rc2 = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
3849	(DISCPUMODE)pDis->uAddrMode, uIOSize);
3850	rc = VBOXSTRICTRC_VAL(rc2);
3851	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
3852	}
3853	else
3854	{
3855	VBOXSTRICTRC rc2 = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
3856	(DISCPUMODE)pDis->uAddrMode, uIOSize);
3857	rc = VBOXSTRICTRC_VAL(rc2);
3858	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
3859	}
3860	}
3861	else
3862	rc = VINF_EM_RAW_EMULATE_INSTR;
3863	}
3864	else
3865	{
3866	/* IN/OUT - I/O instruction. */
3867	Assert(!IoExitInfo.n.u1REP);
3868
3869	if (IoExitInfo.n.u1Type == 0) /* OUT */
3870	{
3871	VBOXSTRICTRC rc2 = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
3872	rc = VBOXSTRICTRC_VAL(rc2);
3873	if (rc == VINF_IOM_R3_IOPORT_WRITE)
3874	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
3875
3876	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
3877	}
3878	else
3879	{
3880	uint32_t u32Val = 0;
3881
3882	VBOXSTRICTRC rc2 = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, uIOSize);
3883	rc = VBOXSTRICTRC_VAL(rc2);
3884	if (IOM_SUCCESS(rc))
3885	{
3886	/* Save result of I/O IN instr. in AL/AX/EAX. */
3887	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
3888	}
3889	else if (rc == VINF_IOM_R3_IOPORT_READ)
3890	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
3891
3892	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
3893	}
3894	}
3895
3896	if (IOM_SUCCESS(rc))
3897	{
3898	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
3899	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
3900
3901	if (RT_LIKELY(rc == VINF_SUCCESS))
3902	{
3903	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3904	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3905	{
3906	/* I/O breakpoint length, in bytes. */
3907	static uint32_t const s_aIOBPLen[4] = { 1, 2, 0, 4 };
3908
3909	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
3910	for (unsigned i = 0; i < 4; i++)
3911	{
3912	unsigned uBPLen = s_aIOBPLen[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3913
3914	if ( IoExitInfo.n.u16Port >= pCtx->dr[i]
3915	&& IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen
3916	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
3917	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3918	{
3919	Assert(CPUMIsGuestDebugStateActive(pVCpu));
3920
3921	/* Clear all breakpoint status flags and set the one we just hit. */
3922	pCtx->dr[6] &= ~(X86_DR6_B0 \| X86_DR6_B1 \| X86_DR6_B2 \| X86_DR6_B3);
3923	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
3924
3925	/*
3926	* Note: AMD64 Architecture Programmer's Manual 13.1:
3927	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
3928	* by software after the contents have been read.
3929	*/
3930	pVmcb->guest.u64DR6 = pCtx->dr[6];
3931
3932	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3933	pCtx->dr[7] &= ~X86_DR7_GD;
3934
3935	/* Paranoia. */
3936	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
3937	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
3938	pCtx->dr[7] \|= 0x400; /* MB1. */
3939
3940	pVmcb->guest.u64DR7 = pCtx->dr[7];
3941	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
3942
3943	/* Inject the debug exception. */
3944	hmR0SvmSetPendingXcptDB(pVCpu);
3945	break;
3946	}
3947	}
3948	}
3949	}
3950	}
3951
3952	#ifdef DEBUG
3953	if (rc == VINF_IOM_R3_IOPORT_READ)
3954	Assert(IoExitInfo.n.u1Type != 0);
3955	else if (rc == VINF_IOM_R3_IOPORT_WRITE)
3956	Assert(IoExitInfo.n.u1Type == 0);
3957	else
3958	{
3959	AssertMsg( RT_FAILURE(rc)
3960	\|\| rc == VINF_SUCCESS
3961	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
3962	\|\| rc == VINF_EM_RAW_GUEST_TRAP
3963	\|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3964	}
3965	#endif
3966	return rc;
3967	}
3968
3969
3970	/**
3971	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
3972	* #VMEXIT.
3973	*/
3974	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3975	{
3976	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3977	PVM pVM = pVCpu->CTX_SUFF(pVM);
3978	Assert(pVM->hm.s.fNestedPaging);
3979
3980	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
3981
3982	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
3983	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3984	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
3985	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
3986
3987	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
3988
3989	#ifdef VBOX_HM_WITH_GUEST_PATCHING
3990	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
3991	if ( pVM->hm.s.fTRPPatchingAllowed
3992	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80
3993	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
3994	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
3995	&& !CPUMGetGuestCPL(pVCpu)
3996	&& !CPUMIsGuestInLongModeEx(pCtx)
3997	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
3998	{
3999	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4000	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4001
4002	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4003	{
4004	/* Only attempt to patch the instruction once. */
4005	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4006	if (!pPatch)
4007	return VINF_EM_HM_PATCH_TPR_INSTR;
4008	}
4009	}
4010	#endif
4011
4012	/*
4013	* Determine the nested paging mode.
4014	*/
4015	PGMMODE enmNestedPagingMode;
4016	#if HC_ARCH_BITS == 32
4017	if (CPUMIsGuestInLongModeEx(pCtx))
4018	enmNestedPagingMode = PGMMODE_AMD64_NX;
4019	else
4020	#endif
4021	enmNestedPagingMode = PGMGetHostMode(pVM);
4022
4023	/*
4024	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4025	*/
4026	int rc;
4027	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4028	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4029	{
4030	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4031	u32ErrCode);
4032	rc = VBOXSTRICTRC_VAL(rc2);
4033
4034	/*
4035	* If we succeed, resume guest execution.
4036	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4037	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4038	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4039	* weird case. See @bugref{6043}.
4040	*/
4041	if ( rc == VINF_SUCCESS
4042	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4043	\|\| rc == VERR_PAGE_NOT_PRESENT)
4044	{
4045	/* Successfully handled MMIO operation. */
4046	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4047	rc = VINF_SUCCESS;
4048	}
4049	return rc;
4050	}
4051
4052	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4053	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4054	TRPMResetTrap(pVCpu);
4055
4056	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4057
4058	/*
4059	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4060	*/
4061	if ( rc == VINF_SUCCESS
4062	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4063	\|\| rc == VERR_PAGE_NOT_PRESENT)
4064	{
4065	/* We've successfully synced our shadow page tables. */
4066	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4067	rc = VINF_SUCCESS;
4068	}
4069
4070	return rc;
4071	}
4072
4073
4074	/**
4075	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4076	*/
4077	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4078	{
4079	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4080
4081	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4082	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4083	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4084
4085	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4086	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4087	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4088
4089	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4090	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4091	return VINF_SUCCESS;
4092	}
4093
4094
4095	/**
4096	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4097	*/
4098	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4099	{
4100	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4101
4102	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4103	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4104	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4105	&& pVCpu->hm.s.Event.fPending)
4106	{
4107	/*
4108	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4109	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4110	* when the recompiler restarts the instruction.
4111	*/
4112	SVMEVENT Event;
4113	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4114	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4115	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4116	{
4117	pVCpu->hm.s.Event.fPending = false;
4118	}
4119	else
4120	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4121	}
4122
4123	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4124	* emulation. */
4125	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4126	return VERR_EM_INTERPRETER;
4127	}
4128
4129
4130	/**
4131	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4132	*/
4133	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4134	{
4135	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4136
4137	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4138	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4139	hmR0SvmSetPendingXcptUD(pVCpu);
4140	return VINF_SUCCESS;
4141	}
4142
4143
4144	/**
4145	* #VMEXIT handler for page faults (SVM_EXIT_PF). Conditional #VMEXIT.
4146	*/
4147	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4148	{
4149	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4150
4151	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4152
4153	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4154	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4155	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4156	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4157
4158	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4159	if (pVM->hm.s.fNestedPaging)
4160	{
4161	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4162	if (!pSvmTransient->fVectoringPF)
4163	{
4164	/* A genuine guest #PF, reflect it to the guest. */
4165	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4166	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4167	uFaultAddress, u32ErrCode));
4168	}
4169	else
4170	{
4171	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4172	hmR0SvmSetPendingXcptDF(pVCpu);
4173	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4174	}
4175	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4176	return VINF_SUCCESS;
4177	}
4178	#endif
4179
4180	PVM pVM = pVCpu->CTX_SUFF(pVM);
4181	Assert(!pVM->hm.s.fNestedPaging);
4182
4183	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4184	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4185	if ( pVM->hm.s.fTRPPatchingAllowed
4186	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4187	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4188	&& !CPUMGetGuestCPL(pVCpu)
4189	&& !CPUMIsGuestInLongModeEx(pCtx)
4190	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4191	{
4192	RTGCPHYS GCPhysApicBase;
4193	GCPhysApicBase = pCtx->msrApicBase;
4194	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4195
4196	/* Check if the page at the fault-address is the APIC base. */
4197	RTGCPHYS GCPhysPage;
4198	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4199	if ( rc2 == VINF_SUCCESS
4200	&& GCPhysPage == GCPhysApicBase)
4201	{
4202	/* Only attempt to patch the instruction once. */
4203	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4204	if (!pPatch)
4205	return VINF_EM_HM_PATCH_TPR_INSTR;
4206	}
4207	}
4208	#endif
4209
4210	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4211	pCtx->rip, u32ErrCode, pCtx->cr3));
4212
4213	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4214	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4215
4216	Log2(("#PF rc=%Rrc\n", rc));
4217	if (rc == VINF_SUCCESS)
4218	{
4219	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4220	TRPMResetTrap(pVCpu);
4221	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4222	return rc;
4223	}
4224	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4225	{
4226	if (!pSvmTransient->fVectoringPF)
4227	{
4228	/* It's a guest page fault and needs to be reflected to the guest. */
4229	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4230	TRPMResetTrap(pVCpu);
4231
4232	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4233	}
4234	else
4235	{
4236	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4237	TRPMResetTrap(pVCpu);
4238	pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
4239	hmR0SvmSetPendingXcptDF(pVCpu);
4240	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4241	}
4242
4243	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4244	return VINF_SUCCESS;
4245	}
4246
4247	TRPMResetTrap(pVCpu);
4248	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4249	return rc;
4250	}
4251
4252
4253	/**
4254	* #VMEXIT handler for device-not-available exception (SVM_EXIT_NM). Conditional
4255	* #VMEXIT.
4256	*/
4257	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4258	{
4259	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4260
4261	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4262
4263	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4264	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4265	#endif
4266
4267	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4268	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4269	if (rc == VINF_SUCCESS)
4270	{
4271	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4272	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4273	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4274	return VINF_SUCCESS;
4275	}
4276
4277	/* Forward #NM to the guest. */
4278	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4279	hmR0SvmSetPendingXcptNM(pVCpu);
4280	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4281	return VINF_SUCCESS;
4282	}
4283
4284
4285	/**
4286	* #VMEXIT handler for math-fault (SVM_EXIT_MF). Conditional #VMEXIT.
4287	*/
4288	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4289	{
4290	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4291
4292	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4293
4294	int rc;
4295	if (!(pCtx->cr0 & X86_CR0_NE))
4296	{
4297	/* Old-style FPU error reporting needs some extra work. */
4298	/** @todo don't fall back to the recompiler, but do it manually. */
4299	rc = VERR_EM_INTERPRETER;
4300	}
4301	else
4302	{
4303	hmR0SvmSetPendingXcptMF(pVCpu);
4304	rc = VINF_SUCCESS;
4305	}
4306	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4307	return rc;
4308	}
4309
4310
4311	/**
4312	* #VMEXIT handler for debug exception (SVM_EXIT_DB). Conditional #VMEXIT.
4313	*/
4314	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4315	{
4316	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4317
4318	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4319
4320	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4321
4322	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4323	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4324	PVM pVM = pVCpu->CTX_SUFF(pVM);
4325	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
4326	if (rc == VINF_EM_RAW_GUEST_TRAP)
4327	{
4328	/* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
4329	pCtx->dr[7] &= ~X86_DR7_GD;
4330
4331	/* Paranoia. */
4332	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
4333	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
4334	pCtx->dr[7] \|= 0x400; /* MB1. */
4335
4336	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4337	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4338
4339	/* Reflect the exception back to the guest. */
4340	SVMEVENT Event;
4341	Event.u = 0;
4342	Event.n.u1Valid = 1;
4343	Event.n.u3Type = SVM_EVENT_EXCEPTION;
4344	Event.n.u8Vector = X86_XCPT_DB;
4345	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
4346
4347	rc = VINF_SUCCESS;
4348	}
4349
4350	return rc;
4351	}
4352

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 46774

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