HMSVMR0.cpp@ 47080

Last change on this file since 47080 was 47080, checked in by vboxsync, 12 years ago
VMM/HMSVMR0: Fail on unexpected exception exits when HMSVM_ALWAYS_TRAP_ALL_XCPT is defined.
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1	/* $Id: HMSVMR0.cpp 47080 2013-07-10 14:32:58Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HWSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	#endif
38
39
40	/*******************************************************************************
41	* Defined Constants And Macros *
42	*******************************************************************************/
43	#ifdef VBOX_WITH_STATISTICS
44	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
45	if ((u64ExitCode) == SVM_EXIT_NPF) \
46	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
47	else \
48	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
49	} while (0)
50	#else
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
52	#endif
53
54	/** If we decide to use a function table approach this can be useful to
55	* switch to a "static DECLCALLBACK(int)". */
56	#define HMSVM_EXIT_DECL static int
57
58
59	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
60	*
61	* The CPU format of the segment attribute is described in X86DESCATTRBITS
62	* which is 16-bits (i.e. includes 4 bits of the segment limit).
63	*
64	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
65	* only the attribute bits and nothing else). Upper 4-bits are unused.
66	*
67	* @{ */
68	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) (a & 0xff) \| ((a & 0xf000) >> 4)
69	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) (a & 0xff) \| ((a & 0x0f00) << 4)
70	/** @} */
71
72
73	/** @name Macros for loading, storing segment registers to/from the VMCB.
74	* @{ */
75	#define HMSVM_LOAD_SEG_REG(REG, reg) \
76	do \
77	{ \
78	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
79	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
80	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
81	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
82	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
83	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
84	} while (0)
85
86	#define HMSVM_SAVE_SEG_REG(REG, reg) \
87	do \
88	{ \
89	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
90	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
92	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
93	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
94	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
95	} while (0)
96	/** @} */
97
98
99	/** @name Macro for checking and returning from the using function for
100	* #VMEXIT intercepts that maybe caused during delivering of another
101	* event in the guest. */
102	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
103	do \
104	{ \
105	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
106	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
107	return VINF_SUCCESS; \
108	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
109	return rc; \
110	} while (0)
111	/** @} */
112
113
114	/**
115	* @name Exception bitmap mask for all contributory exceptions.
116	*
117	* Page fault is deliberately excluded here as it's conditional as to whether
118	* it's contributory or benign. Page faults are handled separately.
119	*/
120	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
121	\| RT_BIT(X86_XCPT_DE))
122	/** @} */
123
124
125	/** @name VMCB Clean Bits.
126	*
127	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
128	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
129	* memory.
130	*
131	* @{ */
132	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
133	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
134	/** I/O permission bitmap, MSR permission bitmap. */
135	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
136	/** ASID. */
137	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
138	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
139	V_INTR_VECTOR. */
140	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
141	/** Nested Paging: Nested CR3 (nCR3), PAT. */
142	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
143	/** Control registers (CR0, CR3, CR4, EFER). */
144	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
145	/** Debug registers (DR6, DR7). */
146	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
147	/** GDT, IDT limit and base. */
148	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
149	/** Segment register: CS, SS, DS, ES limit and base. */
150	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
151	/** CR2.*/
152	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
153	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
154	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
155	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
156	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
157	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
158	/** Mask of all valid VMCB Clean bits. */
159	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
160	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
161	\| HMSVM_VMCB_CLEAN_ASID \
162	\| HMSVM_VMCB_CLEAN_TPR \
163	\| HMSVM_VMCB_CLEAN_NP \
164	\| HMSVM_VMCB_CLEAN_CRX_EFER \
165	\| HMSVM_VMCB_CLEAN_DRX \
166	\| HMSVM_VMCB_CLEAN_DT \
167	\| HMSVM_VMCB_CLEAN_SEG \
168	\| HMSVM_VMCB_CLEAN_CR2 \
169	\| HMSVM_VMCB_CLEAN_LBR \
170	\| HMSVM_VMCB_CLEAN_AVIC)
171	/** @} */
172
173	/** @name SVM transient.
174	*
175	* A state structure for holding miscellaneous information across AMD-V
176	* VMRUN/#VMEXIT operation, restored after the transition.
177	*
178	* @{ */
179	typedef struct SVMTRANSIENT
180	{
181	/** The host's rflags/eflags. */
182	RTCCUINTREG uEFlags;
183	#if HC_ARCH_BITS == 32
184	uint32_t u32Alignment0;
185	#endif
186
187	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
188	uint64_t u64ExitCode;
189	/** The guest's TPR value used for TPR shadowing. */
190	uint8_t u8GuestTpr;
191	/** Alignment. */
192	uint8_t abAlignment0[7];
193
194	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
195	bool fRestoreTscAuxMsr;
196	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
197	* contributary exception or a page-fault. */
198	bool fVectoringPF;
199	/** Whether the TSC offset mode needs to be updated. */
200	bool fUpdateTscOffsetting;
201	} SVMTRANSIENT, *PSVMTRANSIENT;
202	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
203	AssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
204	/** @} */
205
206
207	/**
208	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
209	*/
210	typedef enum SVMMSREXITREAD
211	{
212	/** Reading this MSR causes a VM-exit. */
213	SVMMSREXIT_INTERCEPT_READ = 0xb,
214	/** Reading this MSR does not cause a VM-exit. */
215	SVMMSREXIT_PASSTHRU_READ
216	} SVMMSREXITREAD;
217
218	/**
219	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
220	*/
221	typedef enum SVMMSREXITWRITE
222	{
223	/** Writing to this MSR causes a VM-exit. */
224	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
225	/** Writing to this MSR does not cause a VM-exit. */
226	SVMMSREXIT_PASSTHRU_WRITE
227	} SVMMSREXITWRITE;
228
229
230	/*******************************************************************************
231	* Internal Functions *
232	*******************************************************************************/
233	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
234	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
235
236	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
237	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
238	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
239	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
240	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
241	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
242	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
243	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
244	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
245	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
246	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
247	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
248	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
249	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
250	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
251	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
252	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
253	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
257	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
258	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
259	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
263
264	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
265
266
267	/*******************************************************************************
268	* Global Variables *
269	*******************************************************************************/
270	/** Ring-0 memory object for the IO bitmap. */
271	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
272	/** Physical address of the IO bitmap. */
273	RTHCPHYS g_HCPhysIOBitmap = 0;
274	/** Virtual address of the IO bitmap. */
275	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
276
277
278	/**
279	* Sets up and activates AMD-V on the current CPU.
280	*
281	* @returns VBox status code.
282	* @param pCpu Pointer to the CPU info struct.
283	* @param pVM Pointer to the VM (can be NULL after a resume!).
284	* @param pvCpuPage Pointer to the global CPU page.
285	* @param HCPhysCpuPage Physical address of the global CPU page.
286	*/
287	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
288	{
289	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
290	AssertReturn( HCPhysCpuPage
291	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
292	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
293
294	/*
295	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
296	*/
297	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
298	if (u64HostEfer & MSR_K6_EFER_SVME)
299	{
300	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
301	if ( pVM
302	&& pVM->hm.s.svm.fIgnoreInUseError)
303	{
304	pCpu->fIgnoreAMDVInUseError = true;
305	}
306
307	if (!pCpu->fIgnoreAMDVInUseError)
308	return VERR_SVM_IN_USE;
309	}
310
311	/* Turn on AMD-V in the EFER MSR. */
312	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
313
314	/* Write the physical page address where the CPU will store the host state while executing the VM. */
315	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
316
317	/*
318	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
319	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
320	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
321	* to flush the TLB with before using a new ASID.
322	*/
323	pCpu->fFlushAsidBeforeUse = true;
324
325	/*
326	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
327	*/
328	++pCpu->cTlbFlushes;
329
330	return VINF_SUCCESS;
331	}
332
333
334	/**
335	* Deactivates AMD-V on the current CPU.
336	*
337	* @returns VBox status code.
338	* @param pCpu Pointer to the CPU info struct.
339	* @param pvCpuPage Pointer to the global CPU page.
340	* @param HCPhysCpuPage Physical address of the global CPU page.
341	*/
342	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
343	{
344	AssertReturn( HCPhysCpuPage
345	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
346	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
347	NOREF(pCpu);
348
349	/* Turn off AMD-V in the EFER MSR. */
350	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
351	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
352
353	/* Invalidate host state physical address. */
354	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
355
356	return VINF_SUCCESS;
357	}
358
359
360	/**
361	* Does global AMD-V initialization (called during module initialization).
362	*
363	* @returns VBox status code.
364	*/
365	VMMR0DECL(int) SVMR0GlobalInit(void)
366	{
367	/*
368	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
369	* once globally here instead of per-VM.
370	*/
371	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
372	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
373	if (RT_FAILURE(rc))
374	return rc;
375
376	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
377	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
378
379	/* Set all bits to intercept all IO accesses. */
380	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
381	return VINF_SUCCESS;
382	}
383
384
385	/**
386	* Does global AMD-V termination (called during module termination).
387	*/
388	VMMR0DECL(void) SVMR0GlobalTerm(void)
389	{
390	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
391	{
392	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
393	g_pvIOBitmap = NULL;
394	g_HCPhysIOBitmap = 0;
395	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
396	}
397	}
398
399
400	/**
401	* Frees any allocated per-VCPU structures for a VM.
402	*
403	* @param pVM Pointer to the VM.
404	*/
405	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
406	{
407	for (uint32_t i = 0; i < pVM->cCpus; i++)
408	{
409	PVMCPU pVCpu = &pVM->aCpus[i];
410	AssertPtr(pVCpu);
411
412	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
413	{
414	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
415	pVCpu->hm.s.svm.pvVmcbHost = 0;
416	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
417	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
418	}
419
420	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
421	{
422	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
423	pVCpu->hm.s.svm.pvVmcb = 0;
424	pVCpu->hm.s.svm.HCPhysVmcb = 0;
425	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
426	}
427
428	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
429	{
430	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
431	pVCpu->hm.s.svm.pvMsrBitmap = 0;
432	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
433	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
434	}
435	}
436	}
437
438
439	/**
440	* Does per-VM AMD-V initialization.
441	*
442	* @returns VBox status code.
443	* @param pVM Pointer to the VM.
444	*/
445	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
446	{
447	int rc = VERR_INTERNAL_ERROR_5;
448
449	/*
450	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
451	*/
452	uint32_t u32Family;
453	uint32_t u32Model;
454	uint32_t u32Stepping;
455	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
456	{
457	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
458	pVM->hm.s.svm.fAlwaysFlushTLB = true;
459	}
460
461	/*
462	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
463	*/
464	for (VMCPUID i = 0; i < pVM->cCpus; i++)
465	{
466	PVMCPU pVCpu = &pVM->aCpus[i];
467	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
468	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
469	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
470	}
471
472	for (VMCPUID i = 0; i < pVM->cCpus; i++)
473	{
474	PVMCPU pVCpu = &pVM->aCpus[i];
475
476	/*
477	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
478	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
479	*/
480	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
481	if (RT_FAILURE(rc))
482	goto failure_cleanup;
483
484	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
485	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
486	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
487	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
488
489	/*
490	* Allocate one page for the guest-state VMCB.
491	*/
492	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
493	if (RT_FAILURE(rc))
494	goto failure_cleanup;
495
496	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
497	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
498	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
499	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
500
501	/*
502	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
503	* SVM to not require one.
504	*/
505	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
506	if (RT_FAILURE(rc))
507	goto failure_cleanup;
508
509	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
510	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
511	/* Set all bits to intercept all MSR accesses (changed later on). */
512	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
513	}
514
515	return VINF_SUCCESS;
516
517	failure_cleanup:
518	hmR0SvmFreeStructs(pVM);
519	return rc;
520	}
521
522
523	/**
524	* Does per-VM AMD-V termination.
525	*
526	* @returns VBox status code.
527	* @param pVM Pointer to the VM.
528	*/
529	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
530	{
531	hmR0SvmFreeStructs(pVM);
532	return VINF_SUCCESS;
533	}
534
535
536	/**
537	* Sets the permission bits for the specified MSR in the MSRPM.
538	*
539	* @param pVCpu Pointer to the VMCPU.
540	* @param uMsr The MSR for which the access permissions are being set.
541	* @param enmRead MSR read permissions.
542	* @param enmWrite MSR write permissions.
543	*/
544	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
545	{
546	unsigned ulBit;
547	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
548
549	/*
550	* Layout:
551	* Byte offset MSR range
552	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
553	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
554	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
555	* 0x1800 - 0x1fff Reserved
556	*/
557	if (uMsr <= 0x00001FFF)
558	{
559	/* Pentium-compatible MSRs. */
560	ulBit = uMsr * 2;
561	}
562	else if ( uMsr >= 0xC0000000
563	&& uMsr <= 0xC0001FFF)
564	{
565	/* AMD Sixth Generation x86 Processor MSRs. */
566	ulBit = (uMsr - 0xC0000000) * 2;
567	pbMsrBitmap += 0x800;
568	}
569	else if ( uMsr >= 0xC0010000
570	&& uMsr <= 0xC0011FFF)
571	{
572	/* AMD Seventh and Eighth Generation Processor MSRs. */
573	ulBit = (uMsr - 0xC0001000) * 2;
574	pbMsrBitmap += 0x1000;
575	}
576	else
577	{
578	AssertFailed();
579	return;
580	}
581
582	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
583	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
584	ASMBitSet(pbMsrBitmap, ulBit);
585	else
586	ASMBitClear(pbMsrBitmap, ulBit);
587
588	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
589	ASMBitSet(pbMsrBitmap, ulBit + 1);
590	else
591	ASMBitClear(pbMsrBitmap, ulBit + 1);
592
593	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
594	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
595	}
596
597
598	/**
599	* Sets up AMD-V for the specified VM.
600	* This function is only called once per-VM during initalization.
601	*
602	* @returns VBox status code.
603	* @param pVM Pointer to the VM.
604	*/
605	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
606	{
607	int rc = VINF_SUCCESS;
608
609	AssertReturn(pVM, VERR_INVALID_PARAMETER);
610	Assert(pVM->hm.s.svm.fSupported);
611
612	for (VMCPUID i = 0; i < pVM->cCpus; i++)
613	{
614	PVMCPU pVCpu = &pVM->aCpus[i];
615	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
616
617	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
618
619	/* Trap exceptions unconditionally (debug purposes). */
620	#ifdef HMSVM_ALWAYS_TRAP_PF
621	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
622	#endif
623	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
624	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
625	pVmcb->ctrl.u32InterceptException \|= 0
626	\| RT_BIT(X86_XCPT_BP)
627	\| RT_BIT(X86_XCPT_DB)
628	\| RT_BIT(X86_XCPT_DE)
629	\| RT_BIT(X86_XCPT_NM)
630	\| RT_BIT(X86_XCPT_UD)
631	\| RT_BIT(X86_XCPT_NP)
632	\| RT_BIT(X86_XCPT_SS)
633	\| RT_BIT(X86_XCPT_GP)
634	\| RT_BIT(X86_XCPT_PF)
635	\| RT_BIT(X86_XCPT_MF)
636	;
637	#endif
638
639	/* Set up unconditional intercepts and conditions. */
640	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
641	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
642	\| SVM_CTRL1_INTERCEPT_SMI /* System Management Interrupt cause a VM-exit. */
643	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
644	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
645	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
646	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
647	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
648	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
649	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
650	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
651	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
652	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
653
654	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
655	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
656	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
657	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
658	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
659	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
660	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
661	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
662	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
663	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
664
665	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
666	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
667
668	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
669	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
670
671	/* Intercept all DRx reads and writes by default. Changed later on. */
672	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
673	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
674
675	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
676	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
677
678	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
679	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
680	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
681
682	/* Set IO and MSR bitmap permission bitmap physical addresses. */
683	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
684	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
685
686	/* No LBR virtualization. */
687	pVmcb->ctrl.u64LBRVirt = 0;
688
689	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
690	pVmcb->ctrl.u64VmcbCleanBits = 0;
691
692	/* The host ASID MBZ, for the guest start with 1. */
693	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
694
695	/*
696	* Setup the PAT MSR (applicable for Nested Paging only).
697	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
698	* so choose type 6 for all PAT slots.
699	*/
700	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
701
702	/* Without Nested Paging, we need additionally intercepts. */
703	if (!pVM->hm.s.fNestedPaging)
704	{
705	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
706	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
707	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
708
709	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
710	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
711	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
712
713	/* Page faults must be intercepted to implement shadow paging. */
714	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
715	}
716
717	/*
718	* The following MSRs are saved/restored automatically during the world-switch.
719	* Don't intercept guest read/write accesses to these MSRs.
720	*/
721	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
722	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
723	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
724	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
725	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
726	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
727	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
728	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
729	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
730	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
731	}
732
733	return rc;
734	}
735
736
737	/**
738	* Invalidates a guest page by guest virtual address.
739	*
740	* @returns VBox status code.
741	* @param pVM Pointer to the VM.
742	* @param pVCpu Pointer to the VMCPU.
743	* @param GCVirt Guest virtual address of the page to invalidate.
744	*/
745	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
746	{
747	AssertReturn(pVM, VERR_INVALID_PARAMETER);
748	Assert(pVM->hm.s.svm.fSupported);
749
750	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
751
752	/* Skip it if a TLB flush is already pending. */
753	if (!fFlushPending)
754	{
755	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
756
757	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
758	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
759
760	#if HC_ARCH_BITS == 32
761	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
762	if (CPUMIsGuestInLongMode(pVCpu))
763	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
764	else
765	#endif
766	{
767	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
768	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
769	}
770	}
771	return VINF_SUCCESS;
772	}
773
774
775	/**
776	* Flushes the appropriate tagged-TLB entries.
777	*
778	* @param pVM Pointer to the VM.
779	* @param pVCpu Pointer to the VMCPU.
780	*/
781	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
782	{
783	PVM pVM = pVCpu->CTX_SUFF(pVM);
784	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
785	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
786
787	/*
788	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
789	* This can happen both for start & resume due to long jumps back to ring-3.
790	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
791	* so we cannot reuse the ASIDs without flushing.
792	*/
793	bool fNewAsid = false;
794	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
795	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
796	{
797	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
798	pVCpu->hm.s.fForceTLBFlush = true;
799	fNewAsid = true;
800	}
801
802	/* Set TLB flush state as checked until we return from the world switch. */
803	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
804
805	/* Check for explicit TLB shootdowns. */
806	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
807	{
808	pVCpu->hm.s.fForceTLBFlush = true;
809	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
810	}
811
812	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
813	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
814
815	if (pVM->hm.s.svm.fAlwaysFlushTLB)
816	{
817	/*
818	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
819	*/
820	pCpu->uCurrentAsid = 1;
821	pVCpu->hm.s.uCurrentAsid = 1;
822	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
823	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
824	}
825	else if (pVCpu->hm.s.fForceTLBFlush)
826	{
827	if (fNewAsid)
828	{
829	++pCpu->uCurrentAsid;
830	bool fHitASIDLimit = false;
831	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
832	{
833	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
834	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
835	fHitASIDLimit = true;
836
837	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
838	{
839	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
840	pCpu->fFlushAsidBeforeUse = true;
841	}
842	else
843	{
844	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
845	pCpu->fFlushAsidBeforeUse = false;
846	}
847	}
848
849	if ( !fHitASIDLimit
850	&& pCpu->fFlushAsidBeforeUse)
851	{
852	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
853	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
854	else
855	{
856	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
857	pCpu->fFlushAsidBeforeUse = false;
858	}
859	}
860
861	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
862	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
863	}
864	else
865	{
866	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
867	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
868	else
869	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
870	}
871
872	pVCpu->hm.s.fForceTLBFlush = false;
873	}
874	else
875	{
876	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
877	* not be executed. See hmQueueInvlPage() where it is commented
878	* out. Support individual entry flushing someday. */
879	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
880	{
881	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
882	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
883	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
884	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
885	}
886	}
887
888	pVCpu->hm.s.TlbShootdown.cPages = 0;
889	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
890
891	/* Update VMCB with the ASID. */
892	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
893	{
894	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
895	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
896	}
897
898	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
899	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
900	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
901	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
902	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
903	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
904
905	#ifdef VBOX_WITH_STATISTICS
906	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
907	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
908	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
909	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
910	{
911	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
912	}
913	else
914	{
915	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
916	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
917	}
918	#endif
919	}
920
921
922	/** @name 64-bit guest on 32-bit host OS helper functions.
923	*
924	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
925	* mode (code segment, paging). These wrappers/helpers perform the necessary
926	* bits for the 32->64 switcher.
927	*
928	* @{ */
929	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
930	/**
931	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
932	*
933	* @returns VBox status code.
934	* @param HCPhysVmcbHost Physical address of host VMCB.
935	* @param HCPhysVmcb Physical address of the VMCB.
936	* @param pCtx Pointer to the guest-CPU context.
937	* @param pVM Pointer to the VM.
938	* @param pVCpu Pointer to the VMCPU.
939	*/
940	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
941	{
942	uint32_t aParam[4];
943	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
944	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
945	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
946	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
947
948	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
949	}
950
951
952	/**
953	* Executes the specified VMRUN handler in 64-bit mode.
954	*
955	* @returns VBox status code.
956	* @param pVM Pointer to the VM.
957	* @param pVCpu Pointer to the VMCPU.
958	* @param pCtx Pointer to the guest-CPU context.
959	* @param enmOp The operation to perform.
960	* @param cbParam Number of parameters.
961	* @param paParam Array of 32-bit parameters.
962	*/
963	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
964	uint32_t *paParam)
965	{
966	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
967	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
968
969	/* Disable interrupts. */
970	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
971
972	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
973	RTCPUID idHostCpu = RTMpCpuId();
974	CPUMR0SetLApic(pVM, idHostCpu);
975	#endif
976
977	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
978	CPUMSetHyperEIP(pVCpu, enmOp);
979	for (int i = (int)cbParam - 1; i >= 0; i--)
980	CPUMPushHyper(pVCpu, paParam[i]);
981
982	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
983	/* Call the switcher. */
984	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
985	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
986
987	/* Restore interrupts. */
988	ASMSetFlags(uOldEFlags);
989	return rc;
990	}
991
992	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
993	/** @} */
994
995
996	/**
997	* Adds an exception to the intercept exception bitmap in the VMCB and updates
998	* the corresponding VMCB Clean Bit.
999	*
1000	* @param pVmcb Pointer to the VMCB.
1001	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1002	*/
1003	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1004	{
1005	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1006	{
1007	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1008	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1009	}
1010	}
1011
1012
1013	/**
1014	* Removes an exception from the intercept-exception bitmap in the VMCB and
1015	* updates the corresponding VMCB Clean Bit.
1016	*
1017	* @param pVmcb Pointer to the VMCB.
1018	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1019	*/
1020	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1021	{
1022	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1023	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1024	{
1025	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1026	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1027	}
1028	#endif
1029	}
1030
1031
1032	/**
1033	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1034	*
1035	* @returns VBox status code.
1036	* @param pVCpu Pointer to the VMCPU.
1037	* @param pVmcb Pointer to the VMCB.
1038	* @param pCtx Pointer the guest-CPU context.
1039	*
1040	* @remarks No-long-jump zone!!!
1041	*/
1042	DECLINLINE(int) hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1043	{
1044	/*
1045	* Guest CR0.
1046	*/
1047	PVM pVM = pVCpu->CTX_SUFF(pVM);
1048	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1049	{
1050	uint64_t u64GuestCR0 = pCtx->cr0;
1051
1052	/* Always enable caching. */
1053	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1054
1055	/*
1056	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1057	*/
1058	if (!pVM->hm.s.fNestedPaging)
1059	{
1060	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1061	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1062	}
1063
1064	/*
1065	* Guest FPU bits.
1066	*/
1067	bool fInterceptNM = false;
1068	bool fInterceptMF = false;
1069	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1070	if (CPUMIsGuestFPUStateActive(pVCpu))
1071	{
1072	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1073	if (!(u64GuestCR0 & X86_CR0_NE))
1074	{
1075	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1076	fInterceptMF = true;
1077	}
1078	}
1079	else
1080	{
1081	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1082	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1083	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1084	}
1085
1086	/*
1087	* Update the exception intercept bitmap.
1088	*/
1089	if (fInterceptNM)
1090	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1091	else
1092	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1093
1094	if (fInterceptMF)
1095	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1096	else
1097	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1098
1099	pVmcb->guest.u64CR0 = u64GuestCR0;
1100	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1101	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1102	}
1103
1104	/*
1105	* Guest CR2.
1106	*/
1107	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1108	{
1109	pVmcb->guest.u64CR2 = pCtx->cr2;
1110	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1111	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1112	}
1113
1114	/*
1115	* Guest CR3.
1116	*/
1117	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1118	{
1119	if (pVM->hm.s.fNestedPaging)
1120	{
1121	PGMMODE enmShwPagingMode;
1122	#if HC_ARCH_BITS == 32
1123	if (CPUMIsGuestInLongModeEx(pCtx))
1124	enmShwPagingMode = PGMMODE_AMD64_NX;
1125	else
1126	#endif
1127	enmShwPagingMode = PGMGetHostMode(pVM);
1128
1129	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1130	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1131	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1132	pVmcb->guest.u64CR3 = pCtx->cr3;
1133	}
1134	else
1135	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1136
1137	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1138	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1139	}
1140
1141	/*
1142	* Guest CR4.
1143	*/
1144	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1145	{
1146	uint64_t u64GuestCR4 = pCtx->cr4;
1147	if (!pVM->hm.s.fNestedPaging)
1148	{
1149	switch (pVCpu->hm.s.enmShadowMode)
1150	{
1151	case PGMMODE_REAL:
1152	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1153	AssertFailed();
1154	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1155
1156	case PGMMODE_32_BIT: /* 32-bit paging. */
1157	u64GuestCR4 &= ~X86_CR4_PAE;
1158	break;
1159
1160	case PGMMODE_PAE: /* PAE paging. */
1161	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1162	/** Must use PAE paging as we could use physical memory > 4 GB */
1163	u64GuestCR4 \|= X86_CR4_PAE;
1164	break;
1165
1166	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1167	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1168	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1169	break;
1170	#else
1171	AssertFailed();
1172	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1173	#endif
1174
1175	default: /* shut up gcc */
1176	AssertFailed();
1177	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1178	}
1179	}
1180
1181	pVmcb->guest.u64CR4 = u64GuestCR4;
1182	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1183	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1184	}
1185
1186	return VINF_SUCCESS;
1187	}
1188
1189
1190	/**
1191	* Loads the guest segment registers into the VMCB.
1192	*
1193	* @returns VBox status code.
1194	* @param pVCpu Pointer to the VMCPU.
1195	* @param pVmcb Pointer to the VMCB.
1196	* @param pCtx Pointer to the guest-CPU context.
1197	*
1198	* @remarks No-long-jump zone!!!
1199	*/
1200	DECLINLINE(void) hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1201	{
1202	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1203	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1204	{
1205	HMSVM_LOAD_SEG_REG(CS, cs);
1206	HMSVM_LOAD_SEG_REG(SS, ss);
1207	HMSVM_LOAD_SEG_REG(DS, ds);
1208	HMSVM_LOAD_SEG_REG(ES, es);
1209	HMSVM_LOAD_SEG_REG(FS, fs);
1210	HMSVM_LOAD_SEG_REG(GS, gs);
1211
1212	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1213	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1214	}
1215
1216	/* Guest TR. */
1217	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1218	{
1219	HMSVM_LOAD_SEG_REG(TR, tr);
1220	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1221	}
1222
1223	/* Guest LDTR. */
1224	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1225	{
1226	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1227	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1228	}
1229
1230	/* Guest GDTR. */
1231	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1232	{
1233	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1234	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1235	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1236	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1237	}
1238
1239	/* Guest IDTR. */
1240	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1241	{
1242	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1243	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1244	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1245	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1246	}
1247	}
1248
1249
1250	/**
1251	* Loads the guest MSRs into the VMCB.
1252	*
1253	* @param pVCpu Pointer to the VMCPU.
1254	* @param pVmcb Pointer to the VMCB.
1255	* @param pCtx Pointer to the guest-CPU context.
1256	*
1257	* @remarks No-long-jump zone!!!
1258	*/
1259	DECLINLINE(void) hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1260	{
1261	/* Guest Sysenter MSRs. */
1262	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1263	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1264	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1265
1266	/*
1267	* Guest EFER MSR.
1268	* AMD-V requires guest EFER.SVME to be set. Weird. .
1269	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1270	*/
1271	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1272	{
1273	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1274	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1275	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1276	}
1277
1278	/* 64-bit MSRs. */
1279	if (CPUMIsGuestInLongModeEx(pCtx))
1280	{
1281	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1282	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1283	}
1284	else
1285	{
1286	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1287	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1288	{
1289	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1290	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1291	}
1292	}
1293
1294
1295	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1296	* be writable in 32-bit mode. Clarify with AMD spec. */
1297	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1298	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1299	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1300	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1301	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1302	}
1303
1304
1305	/**
1306	* Loads the guest debug registers into the VMCB.
1307	*
1308	* @param pVCpu Pointer to the VMCPU.
1309	* @param pVmcb Pointer to the VMCB.
1310	* @param pCtx Pointer to the guest-CPU context.
1311	*
1312	* @remarks No-long-jump zone!!!
1313	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1314	*/
1315	DECLINLINE(void) hmR0SvmLoadGuestDebugRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1316	{
1317	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1318	return;
1319
1320	/** @todo Turn these into assertions if possible. */
1321	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* Set reserved bits to 1. */
1322	pCtx->dr[6] &= ~RT_BIT(12); /* MBZ. */
1323
1324	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
1325	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
1326	pCtx->dr[7] \|= 0x400; /* MB1. */
1327
1328	/* Update DR6, DR7 with the guest values. */
1329	pVmcb->guest.u64DR7 = pCtx->dr[7];
1330	pVmcb->guest.u64DR6 = pCtx->dr[6];
1331	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1332
1333	bool fInterceptDB = false;
1334	bool fInterceptMovDRx = false;
1335	if (DBGFIsStepping(pVCpu))
1336	{
1337	/* AMD-V doesn't have any monitor-trap flag equivalent. Instead, enable tracing in the guest and trap #DB. */
1338	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1339	fInterceptDB = true;
1340	}
1341
1342	PVM pVM = pVCpu->CTX_SUFF(pVM);
1343	if (CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1344	{
1345	if (!CPUMIsHyperDebugStateActive(pVCpu))
1346	{
1347	int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1348	AssertRC(rc);
1349
1350	/* Update DR6, DR7 with the hypervisor values. */
1351	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1352	pVmcb->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
1353	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1354	}
1355	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1356	fInterceptMovDRx = true;
1357	}
1358	else if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1359	{
1360	if (!CPUMIsGuestDebugStateActive(pVCpu))
1361	{
1362	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1363	AssertRC(rc);
1364	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1365	}
1366	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1367	Assert(fInterceptMovDRx == false);
1368	}
1369	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1370	{
1371	/* For the first time we would need to intercept MOV DRx accesses even when the guest debug registers aren't loaded. */
1372	fInterceptMovDRx = true;
1373	}
1374
1375	if (fInterceptDB)
1376	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1377	else
1378	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1379
1380	if (fInterceptMovDRx)
1381	{
1382	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1383	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1384	{
1385	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1386	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1387	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1388	}
1389	}
1390	else
1391	{
1392	if ( pVmcb->ctrl.u16InterceptRdDRx
1393	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1394	{
1395	pVmcb->ctrl.u16InterceptRdDRx = 0;
1396	pVmcb->ctrl.u16InterceptWrDRx = 0;
1397	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1398	}
1399	}
1400
1401	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1402	}
1403
1404
1405	/**
1406	* Loads the guest APIC state (currently just the TPR).
1407	*
1408	* @returns VBox status code.
1409	* @param pVCpu Pointer to the VMCPU.
1410	* @param pVmcb Pointer to the VMCB.
1411	* @param pCtx Pointer to the guest-CPU context.
1412	*/
1413	DECLINLINE(int) hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1414	{
1415	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1416	return VINF_SUCCESS;
1417
1418	bool fPendingIntr;
1419	uint8_t u8Tpr;
1420	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1421	AssertRCReturn(rc, rc);
1422
1423	/** Assume that we need to trap all TPR accesses and thus need not check on
1424	* every #VMEXIT if we should update the TPR. */
1425	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1426	pVCpu->hm.s.svm.fSyncVTpr = false;
1427
1428	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1429	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1430	{
1431	pCtx->msrLSTAR = u8Tpr;
1432
1433	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1434	if (fPendingIntr)
1435	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1436	else
1437	{
1438	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1439	pVCpu->hm.s.svm.fSyncVTpr = true;
1440	}
1441	}
1442	else
1443	{
1444	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1445	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1446
1447	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1448	if (fPendingIntr)
1449	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1450	else
1451	{
1452	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1453	pVCpu->hm.s.svm.fSyncVTpr = true;
1454	}
1455
1456	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1457	}
1458
1459	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1460	return rc;
1461	}
1462
1463
1464	/**
1465	* Sets up the appropriate function to run guest code.
1466	*
1467	* @returns VBox status code.
1468	* @param pVCpu Pointer to the VMCPU.
1469	* @param pCtx Pointer to the guest-CPU context.
1470	*
1471	* @remarks No-long-jump zone!!!
1472	*/
1473	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1474	{
1475	if (CPUMIsGuestInLongModeEx(pCtx))
1476	{
1477	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1478	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1479	#endif
1480	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1481	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1482	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1483	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1484	#else
1485	/* 64-bit host or hybrid host. */
1486	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1487	#endif
1488	}
1489	else
1490	{
1491	/* Guest is not in long mode, use the 32-bit handler. */
1492	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1493	}
1494	return VINF_SUCCESS;
1495	}
1496
1497
1498	/**
1499	* Enters the AMD-V session.
1500	*
1501	* @returns VBox status code.
1502	* @param pVM Pointer to the VM.
1503	* @param pVCpu Pointer to the VMCPU.
1504	* @param pCpu Pointer to the CPU info struct.
1505	*/
1506	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
1507	{
1508	AssertPtr(pVM);
1509	AssertPtr(pVCpu);
1510	Assert(pVM->hm.s.svm.fSupported);
1511	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1512	NOREF(pCpu);
1513
1514	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1515
1516	/* Nothing to do here. */
1517	return VINF_SUCCESS;
1518	}
1519
1520
1521	/**
1522	* Leaves the AMD-V session.
1523	*
1524	* @returns VBox status code.
1525	* @param pVM Pointer to the VM.
1526	* @param pVCpu Pointer to the VMCPU.
1527	* @param pCtx Pointer to the guest-CPU context.
1528	*/
1529	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1530	{
1531	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1532	NOREF(pVM);
1533	NOREF(pVCpu);
1534	NOREF(pCtx);
1535
1536	/* Nothing to do here. Everything is taken care of in hmR0SvmLongJmpToRing3(). */
1537	return VINF_SUCCESS;
1538	}
1539
1540
1541	/**
1542	* Saves the host state.
1543	*
1544	* @returns VBox status code.
1545	* @param pVM Pointer to the VM.
1546	* @param pVCpu Pointer to the VMCPU.
1547	*
1548	* @remarks No-long-jump zone!!!
1549	*/
1550	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1551	{
1552	NOREF(pVM);
1553	NOREF(pVCpu);
1554	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1555	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1556	return VINF_SUCCESS;
1557	}
1558
1559
1560	/**
1561	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1562	* fields on every successful VM-entry.
1563	*
1564	* Sets up the appropriate VMRUN function to execute guest code based
1565	* on the guest CPU mode.
1566	*
1567	* @returns VBox status code.
1568	* @param pVM Pointer to the VM.
1569	* @param pVCpu Pointer to the VMCPU.
1570	* @param pMixedCtx Pointer to the guest-CPU context.
1571	*
1572	* @remarks No-long-jump zone!!!
1573	*/
1574	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1575	{
1576	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1577	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1578
1579	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1580
1581	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1582	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1583
1584	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1585	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1586
1587	pVmcb->guest.u64RIP = pCtx->rip;
1588	pVmcb->guest.u64RSP = pCtx->rsp;
1589	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1590	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1591	pVmcb->guest.u64RAX = pCtx->rax;
1592
1593	/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
1594	hmR0SvmLoadGuestDebugRegs(pVCpu, pVmcb, pCtx);
1595
1596	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1597	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1598
1599	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1600	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1601
1602	/* Clear any unused and reserved bits. */
1603	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_MSR /* Unused (legacy). */
1604	\| HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1605	\| HM_CHANGED_GUEST_RSP
1606	\| HM_CHANGED_GUEST_RFLAGS
1607	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1608	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1609	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1610	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1611	\| HM_CHANGED_SVM_RESERVED2
1612	\| HM_CHANGED_SVM_RESERVED3);
1613
1614	AssertMsg(!pVCpu->hm.s.fContextUseFlags,
1615	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1616	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1617
1618	Log4(("Load: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
1619
1620	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1621	return rc;
1622	}
1623
1624
1625	/**
1626	* Loads the guest state on the way from ring-3.
1627	*
1628	* @returns VBox status code.
1629	* @param pVM Pointer to the VM.
1630	* @param pVCpu Pointer to the VMCPU.
1631	* @param pCtx Pointer to the guest-CPU context.
1632	*
1633	* @remarks No-long-jump zone!!!
1634	*/
1635	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1636	{
1637	/*
1638	* Avoid reloading the guest state on longjmp reentrants and do it lazily just before executing the guest.
1639	* This only helps when we get rescheduled more than once to a different host CPU on a longjmp trip before
1640	* finally executing guest code.
1641	*/
1642	return VINF_SUCCESS;
1643	}
1644
1645
1646	/**
1647	* Saves the entire guest state from the VMCB into the
1648	* guest-CPU context. Currently there is no residual state left in the CPU that
1649	* is not updated in the VMCB.
1650	*
1651	* @returns VBox status code.
1652	* @param pVCpu Pointer to the VMCPU.
1653	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1654	* out-of-sync. Make sure to update the required fields
1655	* before using them.
1656	*/
1657	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1658	{
1659	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1660
1661	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1662
1663	pMixedCtx->rip = pVmcb->guest.u64RIP;
1664	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1665	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1666	pMixedCtx->rax = pVmcb->guest.u64RAX;
1667
1668	/*
1669	* Guest interrupt shadow.
1670	*/
1671	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1672	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1673	else
1674	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1675
1676	/*
1677	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1678	*/
1679	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1680
1681	/*
1682	* Guest MSRs.
1683	*/
1684	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1685	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1686	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1687	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1688	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1689	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1690	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1691	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1692
1693	/*
1694	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1695	*/
1696	HMSVM_SAVE_SEG_REG(CS, cs);
1697	HMSVM_SAVE_SEG_REG(SS, ss);
1698	HMSVM_SAVE_SEG_REG(DS, ds);
1699	HMSVM_SAVE_SEG_REG(ES, es);
1700	HMSVM_SAVE_SEG_REG(FS, fs);
1701	HMSVM_SAVE_SEG_REG(GS, gs);
1702
1703	/*
1704	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1705	* register (yet).
1706	*/
1707	/** @todo SELM might need to be fixed as it too should not care about the
1708	* granularity bit. See @bugref{6785}. */
1709	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1710	&& pMixedCtx->cs.Attr.n.u1Present
1711	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1712	{
1713	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1714	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1715	}
1716
1717	#ifdef VBOX_STRICT
1718	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1719	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1720	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1721	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1722	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1723	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1724	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1725
1726	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1727	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1728	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1729	HMSVM_ASSERT_SEG_GRANULARITY(es);
1730	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1731	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1732
1733	# undef HMSVM_ASSERT_SEL_GRANULARITY
1734	#endif
1735
1736	/*
1737	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1738	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1739	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1740	* See AMD spec. 15.5.1 "Basic operation".
1741	*/
1742	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1743	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1744
1745	/*
1746	* Guest Descriptor-Table registers.
1747	*/
1748	HMSVM_SAVE_SEG_REG(TR, tr);
1749	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1750	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1751	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1752
1753	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1754	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1755
1756	/*
1757	* Guest Debug registers.
1758	*/
1759	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1760	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1761
1762	/*
1763	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1764	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1765	*/
1766	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1767	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1768	{
1769	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1770	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1771	}
1772	}
1773
1774
1775	/**
1776	* Does the necessary state syncing before doing a longjmp to ring-3.
1777	*
1778	* @param pVM Pointer to the VM.
1779	* @param pVCpu Pointer to the VMCPU.
1780	* @param pCtx Pointer to the guest-CPU context.
1781	* @param rcExit The reason for exiting to ring-3. Can be
1782	* VINF_VMM_UNKNOWN_RING3_CALL.
1783	*
1784	* @remarks No-long-jmp zone!!!
1785	*/
1786	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1787	{
1788	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1789	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1790
1791	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1792	if (CPUMIsGuestFPUStateActive(pVCpu))
1793	{
1794	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1795	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1796	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1797	}
1798
1799	/* Restore host debug registers if necessary and resync on next R0 reentry. */
1800	if (CPUMIsGuestDebugStateActive(pVCpu))
1801	{
1802	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
1803	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1804	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1805	}
1806	else if (CPUMIsHyperDebugStateActive(pVCpu))
1807	{
1808	CPUMR0LoadHostDebugState(pVM, pVCpu);
1809	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1810	#ifdef VBOX_STRICT
1811	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1812	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1813	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1814	#endif
1815	}
1816
1817	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
1818	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
1819	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1820	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1821	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1822
1823	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1824	}
1825
1826
1827	/**
1828	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
1829	* any remaining host state) before we longjump to ring-3 and possibly get
1830	* preempted.
1831	*
1832	* @param pVCpu Pointer to the VMCPU.
1833	* @param enmOperation The operation causing the ring-3 longjump.
1834	* @param pvUser The user argument (pointer to the possibly
1835	* out-of-date guest-CPU context).
1836	*
1837	* @remarks Must never be called with @a enmOperation ==
1838	* VMMCALLRING3_VM_R0_ASSERTION.
1839	*/
1840	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1841	{
1842	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
1843	Assert(pVCpu);
1844	Assert(pvUser);
1845	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1846	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1847
1848	VMMRZCallRing3Disable(pVCpu);
1849	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1850	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
1851	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser, VINF_VMM_UNKNOWN_RING3_CALL);
1852	VMMRZCallRing3Enable(pVCpu);
1853	}
1854
1855
1856	/**
1857	* An action requires us to go back to ring-3. This function does the necessary
1858	* steps before we can safely return to ring-3. This is not the same as longjmps
1859	* to ring-3, this is voluntary.
1860	*
1861	* @param pVM Pointer to the VM.
1862	* @param pVCpu Pointer to the VMCPU.
1863	* @param pCtx Pointer to the guest-CPU context.
1864	* @param rcExit The reason for exiting to ring-3. Can be
1865	* VINF_VMM_UNKNOWN_RING3_CALL.
1866	*/
1867	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1868	{
1869	Assert(pVM);
1870	Assert(pVCpu);
1871	Assert(pCtx);
1872	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1873
1874	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
1875	{
1876	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
1877	return;
1878	}
1879
1880	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
1881	VMMRZCallRing3Disable(pVCpu);
1882	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
1883
1884	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
1885	if (pVCpu->hm.s.Event.fPending)
1886	{
1887	hmR0SvmPendingEventToTrpmTrap(pVCpu);
1888	Assert(!pVCpu->hm.s.Event.fPending);
1889	}
1890
1891	/* Sync. the guest state. */
1892	hmR0SvmLongJmpToRing3(pVM, pVCpu, pCtx, rcExit);
1893	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1894
1895	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1896	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
1897	\| CPUM_CHANGED_LDTR
1898	\| CPUM_CHANGED_GDTR
1899	\| CPUM_CHANGED_IDTR
1900	\| CPUM_CHANGED_TR
1901	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
1902
1903	/* On our way back from ring-3 the following needs to be done. */
1904	/** @todo This can change with preemption hooks. */
1905	if (rcExit == VINF_EM_RAW_INTERRUPT)
1906	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
1907	else
1908	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1909
1910	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
1911	VMMRZCallRing3Enable(pVCpu);
1912	}
1913
1914
1915	/**
1916	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
1917	* intercepts.
1918	*
1919	* @param pVCpu Pointer to the VMCPU.
1920	*
1921	* @remarks No-long-jump zone!!!
1922	*/
1923	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
1924	{
1925	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1926	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
1927	{
1928	uint64_t u64CurTSC = ASMReadTSC();
1929	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
1930	{
1931	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
1932	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
1933	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
1934	}
1935	else
1936	{
1937	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1938	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1939	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
1940	}
1941	}
1942	else
1943	{
1944	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1945	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1946	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
1947	}
1948
1949	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1950	}
1951
1952
1953	/**
1954	* Sets an event as a pending event to be injected into the guest.
1955	*
1956	* @param pVCpu Pointer to the VMCPU.
1957	* @param pEvent Pointer to the SVM event.
1958	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
1959	* page-fault.
1960	*
1961	* @remarks Statistics counter assumes this is a guest event being reflected to
1962	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
1963	*/
1964	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
1965	{
1966	Assert(!pVCpu->hm.s.Event.fPending);
1967	Assert(pEvent->n.u1Valid);
1968
1969	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
1970	pVCpu->hm.s.Event.fPending = true;
1971	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
1972
1973	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
1974	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
1975
1976	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
1977	}
1978
1979
1980	/**
1981	* Injects an event into the guest upon VMRUN by updating the relevant field
1982	* in the VMCB.
1983	*
1984	* @param pVCpu Pointer to the VMCPU.
1985	* @param pVmcb Pointer to the guest VMCB.
1986	* @param pCtx Pointer to the guest-CPU context.
1987	* @param pEvent Pointer to the event.
1988	*
1989	* @remarks No-long-jump zone!!!
1990	* @remarks Requires CR0!
1991	*/
1992	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
1993	{
1994	pVmcb->ctrl.EventInject.u = pEvent->u;
1995	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
1996
1997	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
1998	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
1999	}
2000
2001
2002
2003	/**
2004	* Converts any TRPM trap into a pending HM event. This is typically used when
2005	* entering from ring-3 (not longjmp returns).
2006	*
2007	* @param pVCpu Pointer to the VMCPU.
2008	*/
2009	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2010	{
2011	Assert(TRPMHasTrap(pVCpu));
2012	Assert(!pVCpu->hm.s.Event.fPending);
2013
2014	uint8_t uVector;
2015	TRPMEVENT enmTrpmEvent;
2016	RTGCUINT uErrCode;
2017	RTGCUINTPTR GCPtrFaultAddress;
2018	uint8_t cbInstr;
2019
2020	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2021	AssertRC(rc);
2022
2023	SVMEVENT Event;
2024	Event.u = 0;
2025	Event.n.u1Valid = 1;
2026	Event.n.u8Vector = uVector;
2027
2028	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2029	if (enmTrpmEvent == TRPM_TRAP)
2030	{
2031	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2032	switch (uVector)
2033	{
2034	case X86_XCPT_PF:
2035	case X86_XCPT_DF:
2036	case X86_XCPT_TS:
2037	case X86_XCPT_NP:
2038	case X86_XCPT_SS:
2039	case X86_XCPT_GP:
2040	case X86_XCPT_AC:
2041	{
2042	Event.n.u1ErrorCodeValid = 1;
2043	Event.n.u32ErrorCode = uErrCode;
2044	break;
2045	}
2046	}
2047	}
2048	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2049	{
2050	if (uVector == X86_XCPT_NMI)
2051	Event.n.u3Type = SVM_EVENT_NMI;
2052	else
2053	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2054	}
2055	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2056	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2057	else
2058	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2059
2060	rc = TRPMResetTrap(pVCpu);
2061	AssertRC(rc);
2062
2063	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2064	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2065
2066	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2067	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2068	}
2069
2070
2071	/**
2072	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2073	* AMD-V to execute any instruction.
2074	*
2075	* @param pvCpu Pointer to the VMCPU.
2076	*/
2077	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2078	{
2079	Assert(pVCpu->hm.s.Event.fPending);
2080	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2081
2082	SVMEVENT Event;
2083	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2084
2085	uint8_t uVector = Event.n.u8Vector;
2086	uint8_t uVectorType = Event.n.u3Type;
2087
2088	TRPMEVENT enmTrapType;
2089	switch (uVectorType)
2090	{
2091	case SVM_EVENT_EXTERNAL_IRQ:
2092	case SVM_EVENT_NMI:
2093	enmTrapType = TRPM_HARDWARE_INT;
2094	break;
2095	case SVM_EVENT_SOFTWARE_INT:
2096	enmTrapType = TRPM_SOFTWARE_INT;
2097	break;
2098	case SVM_EVENT_EXCEPTION:
2099	enmTrapType = TRPM_TRAP;
2100	break;
2101	default:
2102	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2103	enmTrapType = TRPM_32BIT_HACK;
2104	break;
2105	}
2106
2107	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2108
2109	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2110	AssertRC(rc);
2111
2112	if (Event.n.u1ErrorCodeValid)
2113	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2114
2115	if ( uVectorType == SVM_EVENT_EXCEPTION
2116	&& uVector == X86_XCPT_PF)
2117	{
2118	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2119	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2120	}
2121	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2122	{
2123	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2124	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2125	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2126	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2127	}
2128	pVCpu->hm.s.Event.fPending = false;
2129	}
2130
2131
2132	/**
2133	* Gets the guest's interrupt-shadow.
2134	*
2135	* @returns The guest's interrupt-shadow.
2136	* @param pVCpu Pointer to the VMCPU.
2137	* @param pCtx Pointer to the guest-CPU context.
2138	*
2139	* @remarks No-long-jump zone!!!
2140	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2141	*/
2142	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2143	{
2144	/*
2145	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2146	* inhibit interrupts or clear any existing interrupt-inhibition.
2147	*/
2148	uint32_t uIntrState = 0;
2149	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2150	{
2151	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2152	{
2153	/*
2154	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2155	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2156	*/
2157	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2158	}
2159	else
2160	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2161	}
2162	return uIntrState;
2163	}
2164
2165
2166	/**
2167	* Sets the virtual interrupt intercept control in the VMCB which
2168	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2169	* receive interrupts.
2170	*
2171	* @param pVmcb Pointer to the VMCB.
2172	*/
2173	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2174	{
2175	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2176	{
2177	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2178	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2179	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2180	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2181
2182	Log4(("Setting VINTR intercept\n"));
2183	}
2184	}
2185
2186
2187	/**
2188	* Injects any pending events into the guest if the guest is in a state to
2189	* receive them.
2190	*
2191	* @param pVCpu Pointer to the VMCPU.
2192	* @param pCtx Pointer to the guest-CPU context.
2193	*/
2194	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2195	{
2196	Assert(!TRPMHasTrap(pVCpu));
2197	Log4Func(("\n"));
2198
2199	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2200	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2201	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2202
2203	SVMEVENT Event;
2204	Event.u = 0;
2205	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2206	{
2207	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2208	Assert(Event.n.u1Valid);
2209	bool fInject = true;
2210	if ( Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
2211	&& ( fBlockInt
2212	\|\| fIntShadow))
2213	{
2214	fInject = false;
2215	}
2216	else if ( Event.n.u3Type == SVM_EVENT_NMI
2217	&& fIntShadow)
2218	{
2219	fInject = false;
2220	}
2221
2222	if (fInject)
2223	{
2224	Log4(("Injecting pending HM event.\n"));
2225
2226	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2227	pVCpu->hm.s.Event.fPending = false;
2228
2229	#ifdef VBOX_WITH_STATISTICS
2230	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2231	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2232	else
2233	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2234	#endif
2235	}
2236	else
2237	hmR0SvmSetVirtIntrIntercept(pVmcb);
2238	} /** @todo SMI. SMIs take priority over NMIs. */
2239	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2240	{
2241	if (!fIntShadow)
2242	{
2243	Log4(("Injecting NMI\n"));
2244
2245	Event.n.u1Valid = 1;
2246	Event.n.u8Vector = X86_XCPT_NMI;
2247	Event.n.u3Type = SVM_EVENT_NMI;
2248
2249	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2250	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2251
2252	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2253	}
2254	else
2255	hmR0SvmSetVirtIntrIntercept(pVmcb);
2256	}
2257	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2258	{
2259	/* Check if there are guest external interrupts (PIC/APIC) pending and inject them, if the guest can receive them. */
2260	if ( !fBlockInt
2261	&& !fIntShadow)
2262	{
2263	uint8_t u8Interrupt;
2264	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2265	if (RT_SUCCESS(rc))
2266	{
2267	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2268
2269	Event.n.u1Valid = 1;
2270	Event.n.u8Vector = u8Interrupt;
2271	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2272
2273	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2274	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2275	}
2276	else
2277	{
2278	/** @todo Does this actually happen? If not turn it into an assertion. */
2279	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2280	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2281	}
2282	}
2283	else
2284	hmR0SvmSetVirtIntrIntercept(pVmcb);
2285	}
2286
2287	/* Update the guest interrupt shadow in the VMCB. */
2288	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2289	}
2290
2291
2292	/**
2293	* Reports world-switch error and dumps some useful debug info.
2294	*
2295	* @param pVM Pointer to the VM.
2296	* @param pVCpu Pointer to the VMCPU.
2297	* @param rcVMRun The return code from VMRUN (or
2298	* VERR_SVM_INVALID_GUEST_STATE for invalid
2299	* guest-state).
2300	* @param pCtx Pointer to the guest-CPU context.
2301	*/
2302	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2303	{
2304	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2305	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2306
2307	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2308	{
2309	HMDumpRegs(pVM, pVCpu, pCtx);
2310	#ifdef VBOX_STRICT
2311	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2312	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2313	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2314	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2315	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2316	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2317	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2318	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2319	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2320	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2321	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2322
2323	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2324	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2325	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2326
2327	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2328	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2329	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2330	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2331	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2332	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2333	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2334	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2335	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2336	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2337
2338	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2339	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2340	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2341	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2342	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2343	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2344	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2345	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2346	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2347	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2348	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2349	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2350	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2351	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2352	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2353	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2354	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2355
2356	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2357	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2358
2359	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2360	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2361	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2362	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2363	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2364	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2365	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2366	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2367	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2368	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2369	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2370	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2371	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2372	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2373	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2374	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2375	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2376	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2377	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2378	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2379
2380	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2381	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2382
2383	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2384	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2385	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2386	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2387
2388	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2389	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2390
2391	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2392	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2393	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2394	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2395
2396	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2397	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2398	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2399	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2400	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2401	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2402	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2403
2404	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2405	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2406	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2407	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2408
2409	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2410	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2411	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2412
2413	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2414	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2415	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2416	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2417	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2418	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2419	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2420	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2421	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2422	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2423	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2424	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2425	#endif
2426	}
2427	else
2428	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2429	}
2430
2431
2432	/**
2433	* Check per-VM and per-VCPU force flag actions that require us to go back to
2434	* ring-3 for one reason or another.
2435	*
2436	* @returns VBox status code (information status code included).
2437	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2438	* ring-3.
2439	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2440	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2441	* interrupts)
2442	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2443	* all EMTs to be in ring-3.
2444	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2445	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2446	* to the EM loop.
2447	*
2448	* @param pVM Pointer to the VM.
2449	* @param pVCpu Pointer to the VMCPU.
2450	* @param pCtx Pointer to the guest-CPU context.
2451	*/
2452	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2453	{
2454	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2455
2456	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2457	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2458	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2459
2460	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
2461	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
2462	\| VMCPU_FF_REQUEST))
2463	{
2464	/* Pending PGM C3 sync. */
2465	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2466	{
2467	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2468	if (rc != VINF_SUCCESS)
2469	{
2470	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2471	return rc;
2472	}
2473	}
2474
2475	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2476	/* -XXX- what was that about single stepping? */
2477	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2478	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2479	{
2480	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2481	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2482	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2483	return rc;
2484	}
2485
2486	/* Pending VM request packets, such as hardware interrupts. */
2487	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2488	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2489	{
2490	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2491	return VINF_EM_PENDING_REQUEST;
2492	}
2493
2494	/* Pending PGM pool flushes. */
2495	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2496	{
2497	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2498	return VINF_PGM_POOL_FLUSH_PENDING;
2499	}
2500
2501	/* Pending DMA requests. */
2502	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2503	{
2504	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2505	return VINF_EM_RAW_TO_R3;
2506	}
2507	}
2508
2509	return VINF_SUCCESS;
2510	}
2511
2512
2513	/**
2514	* Does the preparations before executing guest code in AMD-V.
2515	*
2516	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2517	* recompiler. We must be cautious what we do here regarding committing
2518	* guest-state information into the the VMCB assuming we assuredly execute the
2519	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2520	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2521	* that the recompiler can (and should) use them when it resumes guest
2522	* execution. Otherwise such operations must be done when we can no longer
2523	* exit to ring-3.
2524	*
2525	* @returns VBox status code (informational status codes included).
2526	* @retval VINF_SUCCESS if we can proceed with running the guest.
2527	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2528	*
2529	* @param pVM Pointer to the VM.
2530	* @param pVCpu Pointer to the VMCPU.
2531	* @param pCtx Pointer to the guest-CPU context.
2532	* @param pSvmTransient Pointer to the SVM transient structure.
2533	*/
2534	DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2535	{
2536	/* Check force flag actions that might require us to go back to ring-3. */
2537	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2538	if (rc != VINF_SUCCESS)
2539	return rc;
2540
2541	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2542	/* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.) */
2543	pSvmTransient->uEFlags = ASMIntDisableFlags();
2544	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2545	{
2546	ASMSetFlags(pSvmTransient->uEFlags);
2547	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2548	/* Don't use VINF_EM_RAW_INTERRUPT_HYPER as we can't assume the host does kernel preemption. Maybe some day? */
2549	return VINF_EM_RAW_INTERRUPT;
2550	}
2551	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2552	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2553	#endif
2554
2555	/* Convert any pending TRPM traps to HM events for injection. */
2556	/** @todo Optimization: move this before disabling interrupts, restore state
2557	* using pVmcb->ctrl.EventInject.u. */
2558	if (TRPMHasTrap(pVCpu))
2559	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2560
2561	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2562
2563	return VINF_SUCCESS;
2564	}
2565
2566
2567	/**
2568	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2569	* means there is no backing out to ring-3 or anywhere else at this
2570	* point.
2571	*
2572	* @param pVM Pointer to the VM.
2573	* @param pVCpu Pointer to the VMCPU.
2574	* @param pCtx Pointer to the guest-CPU context.
2575	* @param pSvmTransient Pointer to the SVM transient structure.
2576	*
2577	* @remarks Called with preemption disabled.
2578	* @remarks No-long-jump zone!!!
2579	*/
2580	DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2581	{
2582	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2583	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2584
2585	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2586	/** @todo I don't see the point of this, VMMR0EntryFast() already disables interrupts for the entire period. */
2587	pSvmTransient->uEFlags = ASMIntDisableFlags();
2588	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2589	#endif
2590
2591	/*
2592	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2593	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2594	*/
2595	/** @todo The above assumption could be wrong. It's not documented what
2596	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2597	* hard way. */
2598	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2599	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2600
2601	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2602	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2603	#endif
2604
2605	/* Load the guest state. */
2606	int rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2607	AssertRC(rc);
2608	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
2609	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2610
2611	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2612	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2613	pVmcb->ctrl.u64VmcbCleanBits = 0;
2614
2615	/*
2616	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2617	* so we can update it on the way back if the guest changed the TPR.
2618	*/
2619	if (pVCpu->hm.s.svm.fSyncVTpr)
2620	{
2621	if (pVM->hm.s.fTPRPatchingActive)
2622	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2623	else
2624	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2625	}
2626
2627	/* Setup TSC offsetting. */
2628	if ( pSvmTransient->fUpdateTscOffsetting
2629	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2630	{
2631	hmR0SvmUpdateTscOffsetting(pVCpu);
2632	pSvmTransient->fUpdateTscOffsetting = false;
2633	}
2634
2635	/* Flush the appropriate tagged-TLB entries. */
2636	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2637	hmR0SvmFlushTaggedTlb(pVCpu);
2638	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2639
2640	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2641
2642	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2643	to start executing. */
2644
2645	/*
2646	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2647	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2648	*
2649	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2650	*/
2651	pSvmTransient->fRestoreTscAuxMsr = false;
2652	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2653	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2654	{
2655	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2656	uint64_t u64GuestTscAux = 0;
2657	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2658	AssertRC(rc2);
2659	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2660	{
2661	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2662	pSvmTransient->fRestoreTscAuxMsr = true;
2663	}
2664	}
2665	}
2666
2667
2668	/**
2669	* Wrapper for running the guest code in AMD-V.
2670	*
2671	* @returns VBox strict status code.
2672	* @param pVM Pointer to the VM.
2673	* @param pVCpu Pointer to the VMCPU.
2674	* @param pCtx Pointer to the guest-CPU context.
2675	*
2676	* @remarks No-long-jump zone!!!
2677	*/
2678	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2679	{
2680	/*
2681	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2682	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2683	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2684	*/
2685	#ifdef VBOX_WITH_KERNEL_USING_XMM
2686	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2687	pVCpu->hm.s.svm.pfnVMRun);
2688	#else
2689	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2690	#endif
2691	}
2692
2693
2694	/**
2695	* Performs some essential restoration of state after running guest code in
2696	* AMD-V.
2697	*
2698	* @param pVM Pointer to the VM.
2699	* @param pVCpu Pointer to the VMCPU.
2700	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2701	* out-of-sync. Make sure to update the required fields
2702	* before using them.
2703	* @param pSvmTransient Pointer to the SVM transient structure.
2704	* @param rcVMRun Return code of VMRUN.
2705	*
2706	* @remarks Called with interrupts disabled.
2707	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2708	* unconditionally when it is safe to do so.
2709	*/
2710	DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2711	{
2712	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2713
2714	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2715	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2716
2717	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2718	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2719
2720	if (pSvmTransient->fRestoreTscAuxMsr)
2721	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2722
2723	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2724	{
2725	/** @todo Find a way to fix hardcoding a guestimate. */
2726	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
2727	}
2728
2729	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
2730	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2731	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2732
2733	Assert(!(ASMGetFlags() & X86_EFL_IF));
2734	ASMSetFlags(pSvmTransient->uEFlags); /* Enable interrupts. */
2735
2736	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pMixedCtx);
2737	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2738
2739	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2740	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2741	{
2742	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2743	return;
2744	}
2745
2746	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2747	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2748	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2749
2750	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2751	{
2752	if (pVCpu->hm.s.svm.fSyncVTpr)
2753	{
2754	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2755	if ( pVM->hm.s.fTPRPatchingActive
2756	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2757	{
2758	int rc = PDMApicSetTPR(pVCpu, (pMixedCtx->msrLSTAR & 0xff));
2759	AssertRC(rc);
2760	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2761	}
2762	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2763	{
2764	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
2765	AssertRC(rc);
2766	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2767	}
2768	}
2769	}
2770	}
2771
2772
2773	/**
2774	* Runs the guest code using AMD-V.
2775	*
2776	* @returns VBox status code.
2777	* @param pVM Pointer to the VM.
2778	* @param pVCpu Pointer to the VMCPU.
2779	* @param pCtx Pointer to the guest-CPU context.
2780	*/
2781	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2782	{
2783	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2784	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2785
2786	SVMTRANSIENT SvmTransient;
2787	SvmTransient.fUpdateTscOffsetting = true;
2788	uint32_t cLoops = 0;
2789	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2790	int rc = VERR_INTERNAL_ERROR_5;
2791
2792	for (;; cLoops++)
2793	{
2794	Assert(!HMR0SuspendPending());
2795	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
2796	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
2797	(unsigned)RTMpCpuId(), cLoops));
2798
2799	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
2800	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
2801	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
2802	if (rc != VINF_SUCCESS)
2803	break;
2804
2805	/*
2806	* No longjmps to ring-3 from this point on!!!
2807	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2808	* This also disables flushing of the R0-logger instance (if any).
2809	*/
2810	VMMRZCallRing3Disable(pVCpu);
2811	VMMRZCallRing3RemoveNotification(pVCpu);
2812	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
2813
2814	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
2815
2816	/*
2817	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
2818	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
2819	*/
2820	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
2821	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
2822	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
2823	{
2824	if (rc == VINF_SUCCESS)
2825	rc = VERR_SVM_INVALID_GUEST_STATE;
2826	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
2827	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2828	return rc;
2829	}
2830
2831	/* Handle the #VMEXIT. */
2832	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
2833	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
2834	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
2835	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
2836	if (rc != VINF_SUCCESS)
2837	break;
2838	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
2839	{
2840	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
2841	rc = VINF_EM_RAW_INTERRUPT;
2842	break;
2843	}
2844	}
2845
2846	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
2847	if (rc == VERR_EM_INTERPRETER)
2848	rc = VINF_EM_RAW_EMULATE_INSTR;
2849	else if (rc == VINF_EM_RESET)
2850	rc = VINF_EM_TRIPLE_FAULT;
2851	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
2852	return rc;
2853	}
2854
2855
2856	/**
2857	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
2858	*
2859	* @returns VBox status code (informational status codes included).
2860	* @param pVCpu Pointer to the VMCPU.
2861	* @param pCtx Pointer to the guest-CPU context.
2862	* @param pSvmTransient Pointer to the SVM transient structure.
2863	*/
2864	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2865	{
2866	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
2867	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
2868
2869	/*
2870	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
2871	* normal workloads (for some definition of "normal").
2872	*/
2873	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
2874	switch (pSvmTransient->u64ExitCode)
2875	{
2876	case SVM_EXIT_NPF:
2877	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
2878
2879	case SVM_EXIT_IOIO:
2880	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
2881
2882	case SVM_EXIT_RDTSC:
2883	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
2884
2885	case SVM_EXIT_RDTSCP:
2886	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
2887
2888	case SVM_EXIT_CPUID:
2889	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
2890
2891	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
2892	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
2893
2894	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
2895	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
2896
2897	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
2898	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
2899
2900	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
2901	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
2902
2903	case SVM_EXIT_MONITOR:
2904	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
2905
2906	case SVM_EXIT_MWAIT:
2907	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
2908
2909	case SVM_EXIT_HLT:
2910	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
2911
2912	case SVM_EXIT_READ_CR0:
2913	case SVM_EXIT_READ_CR3:
2914	case SVM_EXIT_READ_CR4:
2915	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
2916
2917	case SVM_EXIT_WRITE_CR0:
2918	case SVM_EXIT_WRITE_CR3:
2919	case SVM_EXIT_WRITE_CR4:
2920	case SVM_EXIT_WRITE_CR8:
2921	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
2922
2923	case SVM_EXIT_VINTR:
2924	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
2925
2926	case SVM_EXIT_INTR:
2927	case SVM_EXIT_FERR_FREEZE:
2928	case SVM_EXIT_NMI:
2929	case SVM_EXIT_INIT:
2930	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
2931
2932	case SVM_EXIT_MSR:
2933	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
2934
2935	case SVM_EXIT_INVLPG:
2936	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
2937
2938	case SVM_EXIT_WBINVD:
2939	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
2940
2941	case SVM_EXIT_INVD:
2942	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
2943
2944	case SVM_EXIT_RDPMC:
2945	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
2946
2947	default:
2948	{
2949	switch (pSvmTransient->u64ExitCode)
2950	{
2951	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2952	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
2953	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
2954	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2955	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
2956
2957	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2958	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
2959	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
2960	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2961	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
2962
2963	case SVM_EXIT_TASK_SWITCH:
2964	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
2965
2966	case SVM_EXIT_VMMCALL:
2967	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
2968
2969	case SVM_EXIT_SHUTDOWN:
2970	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
2971
2972	case SVM_EXIT_INVLPGA:
2973	case SVM_EXIT_RSM:
2974	case SVM_EXIT_VMRUN:
2975	case SVM_EXIT_VMLOAD:
2976	case SVM_EXIT_VMSAVE:
2977	case SVM_EXIT_STGI:
2978	case SVM_EXIT_CLGI:
2979	case SVM_EXIT_SKINIT:
2980	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
2981
2982	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2983	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
2984	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
2985	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
2986	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
2987	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
2988	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
2989	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
2990	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
2991	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
2992	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
2993	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
2994	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
2995	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
2996	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
2997	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
2998	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
2999	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3000	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3001	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3002
3003	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3004	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3005	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3006	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3007	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3008	{
3009	SVMEVENT Event;
3010	Event.u = 0;
3011	Event.n.u1Valid = 1;
3012	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3013	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3014
3015	switch (Event.n.u8Vector)
3016	{
3017	case X86_XCPT_DE:
3018	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3019	break;
3020
3021	case X86_XCPT_BP:
3022	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3023	* next instruction. */
3024	/** @todo Investigate this later. */
3025	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3026	break;
3027
3028	case X86_XCPT_UD:
3029	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3030	break;
3031
3032	case X86_XCPT_NP:
3033	Event.n.u1ErrorCodeValid = 1;
3034	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3035	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3036	break;
3037
3038	case X86_XCPT_SS:
3039	Event.n.u1ErrorCodeValid = 1;
3040	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3041	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3042	break;
3043
3044	case X86_XCPT_GP:
3045	Event.n.u1ErrorCodeValid = 1;
3046	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3047	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3048	break;
3049
3050	default:
3051	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3052	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3053	}
3054
3055	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3056	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3057	return VINF_SUCCESS;
3058	}
3059	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3060
3061	default:
3062	{
3063	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3064	return VERR_SVM_UNKNOWN_EXIT;
3065	}
3066	}
3067	}
3068	}
3069	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3070	}
3071
3072
3073	#ifdef DEBUG
3074	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3075	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3076	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3077
3078	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3079	do \
3080	{ \
3081	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3082	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3083	} while (0)
3084
3085	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3086	do { \
3087	AssertPtr(pVCpu); \
3088	AssertPtr(pCtx); \
3089	AssertPtr(pSvmTransient); \
3090	Assert(ASMIntAreEnabled()); \
3091	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3092	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3093	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3094	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3095	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3096	HMSVM_ASSERT_PREEMPT_CPUID(); \
3097	} while (0)
3098	#else /* Release builds */
3099	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3100	#endif
3101
3102
3103	/**
3104	* Worker for hmR0SvmInterpretInvlpg().
3105	*
3106	* @return VBox status code.
3107	* @param pVCpu Pointer to the VMCPU.
3108	* @param pCpu Pointer to the disassembler state.
3109	* @param pRegFrame Pointer to the register frame.
3110	*/
3111	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3112	{
3113	DISQPVPARAMVAL Param1;
3114	RTGCPTR GCPtrPage;
3115
3116	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3117	if (RT_FAILURE(rc))
3118	return VERR_EM_INTERPRETER;
3119
3120	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3121	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3122	{
3123	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3124	return VERR_EM_INTERPRETER;
3125
3126	GCPtrPage = Param1.val.val64;
3127	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3128	rc = VBOXSTRICTRC_VAL(rc2);
3129	}
3130	else
3131	{
3132	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3133	rc = VERR_EM_INTERPRETER;
3134	}
3135
3136	return rc;
3137	}
3138
3139
3140	/**
3141	* Interprets INVLPG.
3142	*
3143	* @returns VBox status code.
3144	* @retval VINF_* Scheduling instructions.
3145	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3146	* @retval VERR_* Fatal errors.
3147	*
3148	* @param pVM Pointer to the VM.
3149	* @param pRegFrame Pointer to the register frame.
3150	*
3151	* @remarks Updates the RIP if the instruction was executed successfully.
3152	*/
3153	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3154	{
3155	/* Only allow 32 & 64 bit code. */
3156	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3157	{
3158	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3159	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3160	if ( RT_SUCCESS(rc)
3161	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3162	{
3163	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3164	if (RT_SUCCESS(rc))
3165	pRegFrame->rip += pDis->cbInstr;
3166	return rc;
3167	}
3168	else
3169	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3170	}
3171	return VERR_EM_INTERPRETER;
3172	}
3173
3174
3175	/**
3176	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3177	*
3178	* @param pVCpu Pointer to the VMCPU.
3179	*/
3180	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3181	{
3182	SVMEVENT Event;
3183	Event.u = 0;
3184	Event.n.u1Valid = 1;
3185	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3186	Event.n.u8Vector = X86_XCPT_UD;
3187	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3188	}
3189
3190
3191	/**
3192	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3193	*
3194	* @param pVCpu Pointer to the VMCPU.
3195	*/
3196	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3197	{
3198	SVMEVENT Event;
3199	Event.u = 0;
3200	Event.n.u1Valid = 1;
3201	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3202	Event.n.u8Vector = X86_XCPT_DB;
3203	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3204	}
3205
3206
3207	/**
3208	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3209	*
3210	* @param pVCpu Pointer to the VMCPU.
3211	* @param pCtx Pointer to the guest-CPU context.
3212	* @param u32ErrCode The error-code for the page-fault.
3213	* @param uFaultAddress The page fault address (CR2).
3214	*
3215	* @remarks This updates the guest CR2 with @a uFaultAddress!
3216	*/
3217	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3218	{
3219	SVMEVENT Event;
3220	Event.u = 0;
3221	Event.n.u1Valid = 1;
3222	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3223	Event.n.u8Vector = X86_XCPT_PF;
3224	Event.n.u1ErrorCodeValid = 1;
3225	Event.n.u32ErrorCode = u32ErrCode;
3226
3227	/* Update CR2 of the guest. */
3228	if (pCtx->cr2 != uFaultAddress)
3229	{
3230	pCtx->cr2 = uFaultAddress;
3231	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR2;
3232	}
3233
3234	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3235	}
3236
3237
3238	/**
3239	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3240	* VM.
3241	*
3242	* @param pVCpu Pointer to the VMCPU.
3243	*/
3244	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3245	{
3246	SVMEVENT Event;
3247	Event.u = 0;
3248	Event.n.u1Valid = 1;
3249	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3250	Event.n.u8Vector = X86_XCPT_NM;
3251	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3252	}
3253
3254
3255	/**
3256	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3257	*
3258	* @param pVCpu Pointer to the VMCPU.
3259	*/
3260	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3261	{
3262	SVMEVENT Event;
3263	Event.u = 0;
3264	Event.n.u1Valid = 1;
3265	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3266	Event.n.u8Vector = X86_XCPT_MF;
3267	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3268	}
3269
3270
3271	/**
3272	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3273	*
3274	* @param pVCpu Pointer to the VMCPU.
3275	*/
3276	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3277	{
3278	SVMEVENT Event;
3279	Event.u = 0;
3280	Event.n.u1Valid = 1;
3281	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3282	Event.n.u8Vector = X86_XCPT_DF;
3283	Event.n.u1ErrorCodeValid = 1;
3284	Event.n.u32ErrorCode = 0;
3285	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3286	}
3287
3288
3289	/**
3290	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3291	* guests. This simply looks up the patch record at EIP and does the required.
3292	*
3293	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3294	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3295	* TPR). See hmR3ReplaceTprInstr() for the details.
3296	*
3297	* @returns VBox status code.
3298	* @param pVM Pointer to the VM.
3299	* @param pVCpu Pointer to the VMCPU.
3300	* @param pCtx Pointer to the guest-CPU context.
3301	*/
3302	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3303	{
3304	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3305	for (;;)
3306	{
3307	bool fPending;
3308	uint8_t u8Tpr;
3309
3310	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3311	if (!pPatch)
3312	break;
3313
3314	switch (pPatch->enmType)
3315	{
3316	case HMTPRINSTR_READ:
3317	{
3318	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3319	AssertRC(rc);
3320
3321	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3322	AssertRC(rc);
3323	pCtx->rip += pPatch->cbOp;
3324	break;
3325	}
3326
3327	case HMTPRINSTR_WRITE_REG:
3328	case HMTPRINSTR_WRITE_IMM:
3329	{
3330	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3331	{
3332	uint32_t u32Val;
3333	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3334	AssertRC(rc);
3335	u8Tpr = u32Val;
3336	}
3337	else
3338	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3339
3340	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3341	AssertRC(rc2);
3342	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3343
3344	pCtx->rip += pPatch->cbOp;
3345	break;
3346	}
3347
3348	default:
3349	AssertMsgFailedReturn(("Unexpected patch type %d\n", pPatch->enmType), VERR_SVM_UNEXPECTED_PATCH_TYPE);
3350	break;
3351	}
3352	}
3353
3354	return VINF_SUCCESS;
3355	}
3356
3357	/**
3358	* Determines if an exception is a contributory exception. Contributory
3359	* exceptions are ones which can cause double-faults. Page-fault is
3360	* intentionally not included here as it's a conditional contributory exception.
3361	*
3362	* @returns true if the exception is contributory, false otherwise.
3363	* @param uVector The exception vector.
3364	*/
3365	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3366	{
3367	switch (uVector)
3368	{
3369	case X86_XCPT_GP:
3370	case X86_XCPT_SS:
3371	case X86_XCPT_NP:
3372	case X86_XCPT_TS:
3373	case X86_XCPT_DE:
3374	return true;
3375	default:
3376	break;
3377	}
3378	return false;
3379	}
3380
3381
3382	/**
3383	* Handle a condition that occurred while delivering an event through the guest
3384	* IDT.
3385	*
3386	* @returns VBox status code (informational error codes included).
3387	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3388	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3389	* continue execution of the guest which will delivery the #DF.
3390	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3391	*
3392	* @param pVCpu Pointer to the VMCPU.
3393	* @param pCtx Pointer to the guest-CPU context.
3394	* @param pSvmTransient Pointer to the SVM transient structure.
3395	*
3396	* @remarks No-long-jump zone!!!
3397	*/
3398	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3399	{
3400	int rc = VINF_SUCCESS;
3401	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3402
3403	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3404	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3405	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3406	{
3407	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3408
3409	typedef enum
3410	{
3411	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3412	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3413	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3414	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3415	} SVMREFLECTXCPT;
3416
3417	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3418	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3419	{
3420	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3421	{
3422	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3423
3424	#ifdef VBOX_STRICT
3425	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3426	&& uExitVector == X86_XCPT_PF)
3427	{
3428	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3429	}
3430	#endif
3431	if ( uExitVector == X86_XCPT_PF
3432	&& uIdtVector == X86_XCPT_PF)
3433	{
3434	pSvmTransient->fVectoringPF = true;
3435	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3436	}
3437	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3438	&& hmR0SvmIsContributoryXcpt(uExitVector)
3439	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3440	\|\| uIdtVector == X86_XCPT_PF))
3441	{
3442	enmReflect = SVMREFLECTXCPT_DF;
3443	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3444	uIdtVector, uExitVector));
3445	}
3446	else if (uIdtVector == X86_XCPT_DF)
3447	{
3448	enmReflect = SVMREFLECTXCPT_TF;
3449	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3450	uIdtVector, uExitVector));
3451	}
3452	else
3453	enmReflect = SVMREFLECTXCPT_XCPT;
3454	}
3455	else
3456	{
3457	/*
3458	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3459	* exception to the guest after handling the VM-exit.
3460	*/
3461	enmReflect = SVMREFLECTXCPT_XCPT;
3462	}
3463	}
3464	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3465	{
3466	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3467	enmReflect = SVMREFLECTXCPT_XCPT;
3468	}
3469
3470	switch (enmReflect)
3471	{
3472	case SVMREFLECTXCPT_XCPT:
3473	{
3474	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3475	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3476
3477	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3478	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3479	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3480	break;
3481	}
3482
3483	case SVMREFLECTXCPT_DF:
3484	{
3485	hmR0SvmSetPendingXcptDF(pVCpu);
3486	rc = VINF_HM_DOUBLE_FAULT;
3487	break;
3488	}
3489
3490	case SVMREFLECTXCPT_TF:
3491	{
3492	rc = VINF_EM_RESET;
3493	break;
3494	}
3495
3496	default:
3497	Assert(rc == VINF_SUCCESS);
3498	break;
3499	}
3500	}
3501	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3502	return rc;
3503	}
3504
3505
3506	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3507	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3508	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3509
3510	/** @name VM-exit handlers.
3511	* @{
3512	*/
3513
3514	/**
3515	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3516	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3517	*/
3518	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3519	{
3520	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3521	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3522
3523	/*
3524	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3525	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3526	* interrupt it is until the host actually take the interrupt.
3527	*
3528	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3529	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3530	*/
3531	return VINF_EM_RAW_INTERRUPT;
3532	}
3533
3534
3535	/**
3536	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3537	*/
3538	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3539	{
3540	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3541	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3542	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3543	return VINF_SUCCESS;
3544	}
3545
3546
3547	/**
3548	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3549	*/
3550	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3551	{
3552	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3553	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3554	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3555	return VINF_SUCCESS;
3556	}
3557
3558
3559	/**
3560	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3561	*/
3562	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3563	{
3564	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3565	PVM pVM = pVCpu->CTX_SUFF(pVM);
3566	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3567	if (RT_LIKELY(rc == VINF_SUCCESS))
3568	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3569	else
3570	{
3571	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3572	rc = VERR_EM_INTERPRETER;
3573	}
3574	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3575	return rc;
3576	}
3577
3578
3579	/**
3580	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3581	*/
3582	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3583	{
3584	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3585	PVM pVM = pVCpu->CTX_SUFF(pVM);
3586	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3587	if (RT_LIKELY(rc == VINF_SUCCESS))
3588	{
3589	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3590	pSvmTransient->fUpdateTscOffsetting = true;
3591	}
3592	else
3593	{
3594	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3595	rc = VERR_EM_INTERPRETER;
3596	}
3597	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3598	return rc;
3599	}
3600
3601
3602	/**
3603	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3604	*/
3605	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3606	{
3607	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3608	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3609	if (RT_LIKELY(rc == VINF_SUCCESS))
3610	{
3611	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3612	pSvmTransient->fUpdateTscOffsetting = true;
3613	}
3614	else
3615	{
3616	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3617	rc = VERR_EM_INTERPRETER;
3618	}
3619	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3620	return rc;
3621	}
3622
3623
3624	/**
3625	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3626	*/
3627	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3628	{
3629	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3630	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3631	if (RT_LIKELY(rc == VINF_SUCCESS))
3632	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3633	else
3634	{
3635	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3636	rc = VERR_EM_INTERPRETER;
3637	}
3638	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3639	return rc;
3640	}
3641
3642
3643	/**
3644	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3645	*/
3646	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3647	{
3648	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3649	PVM pVM = pVCpu->CTX_SUFF(pVM);
3650	Assert(!pVM->hm.s.fNestedPaging);
3651
3652	/** @todo Decode Assist. */
3653	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3654	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3655	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3656	return rc;
3657	}
3658
3659
3660	/**
3661	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3662	*/
3663	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3664	{
3665	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3666	pCtx->rip++; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3667	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3668	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3669	return rc;
3670	}
3671
3672
3673	/**
3674	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3675	*/
3676	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3677	{
3678	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3679	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3680	if (RT_LIKELY(rc == VINF_SUCCESS))
3681	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3682	else
3683	{
3684	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3685	rc = VERR_EM_INTERPRETER;
3686	}
3687	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3688	return rc;
3689	}
3690
3691
3692	/**
3693	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3694	*/
3695	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3696	{
3697	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3698	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3699	int rc = VBOXSTRICTRC_VAL(rc2);
3700	if ( rc == VINF_EM_HALT
3701	\|\| rc == VINF_SUCCESS)
3702	{
3703	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3704
3705	if ( rc == VINF_EM_HALT
3706	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3707	{
3708	rc = VINF_SUCCESS;
3709	}
3710	}
3711	else
3712	{
3713	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3714	rc = VERR_EM_INTERPRETER;
3715	}
3716	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3717	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3718	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3719	return rc;
3720	}
3721
3722
3723	/**
3724	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
3725	* Conditional #VMEXIT.
3726	*/
3727	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3728	{
3729	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3730	return VINF_EM_RESET;
3731	}
3732
3733
3734	/**
3735	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
3736	*/
3737	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3738	{
3739	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3740
3741	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3742
3743	/** @todo Decode Assist. */
3744	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3745	int rc = VBOXSTRICTRC_VAL(rc2);
3746	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
3747	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
3748	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
3749	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
3750	return rc;
3751	}
3752
3753
3754	/**
3755	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
3756	*/
3757	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3758	{
3759	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3760	/** @todo Decode Assist. */
3761	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3762	int rc = VBOXSTRICTRC_VAL(rc2);
3763	if (rc == VINF_SUCCESS)
3764	{
3765	/* RIP has been updated by EMInterpretInstruction(). */
3766	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
3767	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
3768	{
3769	case 0: /* CR0. */
3770	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
3771	break;
3772
3773	case 3: /* CR3. */
3774	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
3775	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
3776	break;
3777
3778	case 4: /* CR4. */
3779	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
3780	break;
3781
3782	case 8: /* CR8 (TPR). */
3783	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3784	break;
3785
3786	default:
3787	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
3788	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
3789	break;
3790	}
3791	}
3792	else
3793	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
3794	return rc;
3795	}
3796
3797
3798	/**
3799	* #VMEXIT handler for instructions that result in a #UD exception delivered to
3800	* the guest.
3801	*/
3802	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3803	{
3804	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3805	hmR0SvmSetPendingXcptUD(pVCpu);
3806	return VINF_SUCCESS;
3807	}
3808
3809
3810	/**
3811	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
3812	*/
3813	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3814	{
3815	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3816	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3817	PVM pVM = pVCpu->CTX_SUFF(pVM);
3818
3819	/** @todo r=ramshankar: This cannot be right if prefixes are involved. When
3820	* NRIP_SAVE isn't available we have to disassemble the instruction. */
3821	int rc;
3822	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
3823	{
3824	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
3825
3826	/* Handle TPR patching; intercepted LSTAR write. */
3827	if ( pVM->hm.s.fTPRPatchingActive
3828	&& pCtx->ecx == MSR_K8_LSTAR)
3829	{
3830	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
3831	{
3832	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
3833	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
3834	AssertRC(rc2);
3835	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3836	}
3837	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3838	return VINF_SUCCESS;
3839	}
3840
3841	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3842	if (RT_LIKELY(rc == VINF_SUCCESS))
3843	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3844	else
3845	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
3846
3847	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
3848	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
3849	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
3850	{
3851	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
3852	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
3853	EMInterpretWrmsr() changes it. */
3854	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3855	}
3856	else if (pCtx->ecx == MSR_K6_EFER)
3857	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
3858	else if (pCtx->ecx == MSR_IA32_TSC)
3859	pSvmTransient->fUpdateTscOffsetting = true;
3860	}
3861	else
3862	{
3863	/* MSR Read access. */
3864	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
3865	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3866	if (RT_LIKELY(rc == VINF_SUCCESS))
3867	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3868	else
3869	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
3870	}
3871
3872	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
3873	return rc;
3874	}
3875
3876
3877	/**
3878	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
3879	*/
3880	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3881	{
3882	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3883	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
3884
3885	/* We should -not- get this VM-exit if the guest is debugging. */
3886	if (CPUMIsGuestDebugStateActive(pVCpu))
3887	{
3888	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx));
3889	return VERR_SVM_UNEXPECTED_EXIT;
3890	}
3891
3892	if ( !DBGFIsStepping(pVCpu)
3893	&& !CPUMIsHyperDebugStateActive(pVCpu))
3894	{
3895	/* Don't intercept DRx read and writes. */
3896	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3897	pVmcb->ctrl.u16InterceptRdDRx = 0;
3898	pVmcb->ctrl.u16InterceptWrDRx = 0;
3899	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3900
3901	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
3902	PVM pVM = pVCpu->CTX_SUFF(pVM);
3903	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3904	AssertRC(rc);
3905	Assert(CPUMIsGuestDebugStateActive(pVCpu));
3906
3907	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
3908	return rc;
3909	}
3910
3911	/** @todo Decode assist. */
3912	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3913	int rc = VBOXSTRICTRC_VAL(rc2);
3914	if (RT_LIKELY(rc == VINF_SUCCESS))
3915	{
3916	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
3917	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3918	}
3919	else
3920	Assert(rc == VERR_EM_INTERPRETER);
3921	return rc;
3922	}
3923
3924
3925	/**
3926	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
3927	*/
3928	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3929	{
3930	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3931	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
3932	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3933	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
3934	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
3935	return rc;
3936	}
3937
3938
3939	/**
3940	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
3941	*/
3942	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3943	{
3944	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3945
3946	/* I/O operation lookup arrays. */
3947	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
3948	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
3949	the result (in AL/AX/EAX). */
3950	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3951
3952	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3953	PVM pVM = pVCpu->CTX_SUFF(pVM);
3954
3955	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
3956	SVMIOIOEXIT IoExitInfo;
3957	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
3958	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
3959	uint32_t uIOSize = s_aIOSize[uIOWidth];
3960	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
3961
3962	if (RT_UNLIKELY(!uIOSize))
3963	{
3964	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
3965	return VERR_EM_INTERPRETER;
3966	}
3967
3968	int rc;
3969	if (IoExitInfo.n.u1STR)
3970	{
3971	/* INS/OUTS - I/O String instruction. */
3972	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
3973
3974	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
3975	* in EXITINFO1? Investigate once this thing is up and running. */
3976
3977	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
3978	if (rc == VINF_SUCCESS)
3979	{
3980	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
3981	{
3982	VBOXSTRICTRC rc2 = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
3983	(DISCPUMODE)pDis->uAddrMode, uIOSize);
3984	rc = VBOXSTRICTRC_VAL(rc2);
3985	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
3986	}
3987	else
3988	{
3989	VBOXSTRICTRC rc2 = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
3990	(DISCPUMODE)pDis->uAddrMode, uIOSize);
3991	rc = VBOXSTRICTRC_VAL(rc2);
3992	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
3993	}
3994	}
3995	else
3996	rc = VINF_EM_RAW_EMULATE_INSTR;
3997	}
3998	else
3999	{
4000	/* IN/OUT - I/O instruction. */
4001	Assert(!IoExitInfo.n.u1REP);
4002
4003	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4004	{
4005	VBOXSTRICTRC rc2 = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
4006	rc = VBOXSTRICTRC_VAL(rc2);
4007	if (rc == VINF_IOM_R3_IOPORT_WRITE)
4008	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
4009
4010	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4011	}
4012	else
4013	{
4014	uint32_t u32Val = 0;
4015
4016	VBOXSTRICTRC rc2 = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, uIOSize);
4017	rc = VBOXSTRICTRC_VAL(rc2);
4018	if (IOM_SUCCESS(rc))
4019	{
4020	/* Save result of I/O IN instr. in AL/AX/EAX. */
4021	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4022	}
4023	else if (rc == VINF_IOM_R3_IOPORT_READ)
4024	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
4025
4026	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4027	}
4028	}
4029
4030	if (IOM_SUCCESS(rc))
4031	{
4032	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4033	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4034
4035	if (RT_LIKELY(rc == VINF_SUCCESS))
4036	{
4037	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
4038	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
4039	{
4040	/* I/O breakpoint length, in bytes. */
4041	static uint32_t const s_aIOBPLen[4] = { 1, 2, 0, 4 };
4042
4043	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4044	for (unsigned i = 0; i < 4; i++)
4045	{
4046	unsigned uBPLen = s_aIOBPLen[X86_DR7_GET_LEN(pCtx->dr[7], i)];
4047
4048	if ( IoExitInfo.n.u16Port >= pCtx->dr[i]
4049	&& IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen
4050	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
4051	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
4052	{
4053	Assert(CPUMIsGuestDebugStateActive(pVCpu));
4054
4055	/* Clear all breakpoint status flags and set the one we just hit. */
4056	pCtx->dr[6] &= ~(X86_DR6_B0 \| X86_DR6_B1 \| X86_DR6_B2 \| X86_DR6_B3);
4057	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
4058
4059	/*
4060	* Note: AMD64 Architecture Programmer's Manual 13.1:
4061	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
4062	* by software after the contents have been read.
4063	*/
4064	pVmcb->guest.u64DR6 = pCtx->dr[6];
4065
4066	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
4067	pCtx->dr[7] &= ~X86_DR7_GD;
4068
4069	/* Paranoia. */
4070	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
4071	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
4072	pCtx->dr[7] \|= 0x400; /* MB1. */
4073
4074	pVmcb->guest.u64DR7 = pCtx->dr[7];
4075	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4076
4077	/* Inject the debug exception. */
4078	hmR0SvmSetPendingXcptDB(pVCpu);
4079	break;
4080	}
4081	}
4082	}
4083	}
4084	}
4085
4086	#ifdef VBOX_STRICT
4087	if (rc == VINF_IOM_R3_IOPORT_READ)
4088	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4089	else if (rc == VINF_IOM_R3_IOPORT_WRITE)
4090	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4091	else
4092	{
4093	AssertMsg( RT_FAILURE(rc)
4094	\|\| rc == VINF_SUCCESS
4095	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
4096	\|\| rc == VINF_EM_RAW_GUEST_TRAP
4097	\|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
4098	}
4099	#endif
4100	return rc;
4101	}
4102
4103
4104	/**
4105	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4106	* #VMEXIT.
4107	*/
4108	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4109	{
4110	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4111	PVM pVM = pVCpu->CTX_SUFF(pVM);
4112	Assert(pVM->hm.s.fNestedPaging);
4113
4114	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4115
4116	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4117	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4118	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4119	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4120
4121	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4122
4123	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4124	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4125	if ( pVM->hm.s.fTRPPatchingAllowed
4126	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80
4127	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4128	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4129	&& !CPUMGetGuestCPL(pVCpu)
4130	&& !CPUMIsGuestInLongModeEx(pCtx)
4131	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4132	{
4133	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4134	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4135
4136	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4137	{
4138	/* Only attempt to patch the instruction once. */
4139	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4140	if (!pPatch)
4141	return VINF_EM_HM_PATCH_TPR_INSTR;
4142	}
4143	}
4144	#endif
4145
4146	/*
4147	* Determine the nested paging mode.
4148	*/
4149	PGMMODE enmNestedPagingMode;
4150	#if HC_ARCH_BITS == 32
4151	if (CPUMIsGuestInLongModeEx(pCtx))
4152	enmNestedPagingMode = PGMMODE_AMD64_NX;
4153	else
4154	#endif
4155	enmNestedPagingMode = PGMGetHostMode(pVM);
4156
4157	/*
4158	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4159	*/
4160	int rc;
4161	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4162	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4163	{
4164	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4165	u32ErrCode);
4166	rc = VBOXSTRICTRC_VAL(rc2);
4167
4168	/*
4169	* If we succeed, resume guest execution.
4170	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4171	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4172	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4173	* weird case. See @bugref{6043}.
4174	*/
4175	if ( rc == VINF_SUCCESS
4176	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4177	\|\| rc == VERR_PAGE_NOT_PRESENT)
4178	{
4179	/* Successfully handled MMIO operation. */
4180	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4181	rc = VINF_SUCCESS;
4182	}
4183	return rc;
4184	}
4185
4186	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4187	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4188	TRPMResetTrap(pVCpu);
4189
4190	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4191
4192	/*
4193	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4194	*/
4195	if ( rc == VINF_SUCCESS
4196	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4197	\|\| rc == VERR_PAGE_NOT_PRESENT)
4198	{
4199	/* We've successfully synced our shadow page tables. */
4200	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4201	rc = VINF_SUCCESS;
4202	}
4203
4204	return rc;
4205	}
4206
4207
4208	/**
4209	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4210	*/
4211	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4212	{
4213	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4214
4215	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4216	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4217	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4218
4219	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4220	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4221	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4222
4223	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4224	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4225	return VINF_SUCCESS;
4226	}
4227
4228
4229	/**
4230	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4231	*/
4232	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4233	{
4234	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4235
4236	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4237	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4238	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4239	&& pVCpu->hm.s.Event.fPending)
4240	{
4241	/*
4242	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4243	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4244	* when the recompiler restarts the instruction.
4245	*/
4246	SVMEVENT Event;
4247	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4248	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4249	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4250	{
4251	pVCpu->hm.s.Event.fPending = false;
4252	}
4253	else
4254	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4255	}
4256
4257	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4258	* emulation. */
4259	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4260	return VERR_EM_INTERPRETER;
4261	}
4262
4263
4264	/**
4265	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4266	*/
4267	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4268	{
4269	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4270
4271	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4272	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4273	hmR0SvmSetPendingXcptUD(pVCpu);
4274	return VINF_SUCCESS;
4275	}
4276
4277
4278	/**
4279	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4280	* #VMEXIT.
4281	*/
4282	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4283	{
4284	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4285
4286	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4287
4288	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4289	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4290	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4291	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4292
4293	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4294	if (pVM->hm.s.fNestedPaging)
4295	{
4296	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4297	if (!pSvmTransient->fVectoringPF)
4298	{
4299	/* A genuine guest #PF, reflect it to the guest. */
4300	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4301	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4302	uFaultAddress, u32ErrCode));
4303	}
4304	else
4305	{
4306	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4307	hmR0SvmSetPendingXcptDF(pVCpu);
4308	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4309	}
4310	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4311	return VINF_SUCCESS;
4312	}
4313	#endif
4314
4315	PVM pVM = pVCpu->CTX_SUFF(pVM);
4316	Assert(!pVM->hm.s.fNestedPaging);
4317
4318	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4319	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4320	if ( pVM->hm.s.fTRPPatchingAllowed
4321	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4322	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4323	&& !CPUMGetGuestCPL(pVCpu)
4324	&& !CPUMIsGuestInLongModeEx(pCtx)
4325	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4326	{
4327	RTGCPHYS GCPhysApicBase;
4328	GCPhysApicBase = pCtx->msrApicBase;
4329	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4330
4331	/* Check if the page at the fault-address is the APIC base. */
4332	RTGCPHYS GCPhysPage;
4333	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4334	if ( rc2 == VINF_SUCCESS
4335	&& GCPhysPage == GCPhysApicBase)
4336	{
4337	/* Only attempt to patch the instruction once. */
4338	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4339	if (!pPatch)
4340	return VINF_EM_HM_PATCH_TPR_INSTR;
4341	}
4342	}
4343	#endif
4344
4345	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4346	pCtx->rip, u32ErrCode, pCtx->cr3));
4347
4348	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4349	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4350
4351	Log4(("#PF rc=%Rrc\n", rc));
4352
4353	if (rc == VINF_SUCCESS)
4354	{
4355	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4356	TRPMResetTrap(pVCpu);
4357	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4358	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4359	return rc;
4360	}
4361	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4362	{
4363	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4364
4365	if (!pSvmTransient->fVectoringPF)
4366	{
4367	/* It's a guest page fault and needs to be reflected to the guest. */
4368	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4369	TRPMResetTrap(pVCpu);
4370	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4371	}
4372	else
4373	{
4374	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4375	TRPMResetTrap(pVCpu);
4376	hmR0SvmSetPendingXcptDF(pVCpu);
4377	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4378	}
4379
4380	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4381	return VINF_SUCCESS;
4382	}
4383
4384	TRPMResetTrap(pVCpu);
4385	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4386	return rc;
4387	}
4388
4389
4390	/**
4391	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4392	* Conditional #VMEXIT.
4393	*/
4394	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4395	{
4396	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4397
4398	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4399
4400	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4401	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4402	#endif
4403
4404	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4405	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4406	if (rc == VINF_SUCCESS)
4407	{
4408	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4409	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4410	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4411	return VINF_SUCCESS;
4412	}
4413
4414	/* Forward #NM to the guest. */
4415	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4416	hmR0SvmSetPendingXcptNM(pVCpu);
4417	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4418	return VINF_SUCCESS;
4419	}
4420
4421
4422	/**
4423	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4424	* Conditional #VMEXIT.
4425	*/
4426	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4427	{
4428	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4429
4430	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4431
4432	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4433
4434	if (!(pCtx->cr0 & X86_CR0_NE))
4435	{
4436	/* Old-style FPU error reporting needs some extra work. */
4437	/** @todo don't fall back to the recompiler, but do it manually. */
4438	return VERR_EM_INTERPRETER;
4439	}
4440
4441	hmR0SvmSetPendingXcptMF(pVCpu);
4442	return VINF_SUCCESS;
4443	}
4444
4445
4446	/**
4447	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4448	* #VMEXIT.
4449	*/
4450	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4451	{
4452	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4453
4454	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4455
4456	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4457
4458	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4459	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4460	PVM pVM = pVCpu->CTX_SUFF(pVM);
4461	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
4462	if (rc == VINF_EM_RAW_GUEST_TRAP)
4463	{
4464	/* Reflect the exception back to the guest. */
4465	hmR0SvmSetPendingXcptDB(pVCpu);
4466	rc = VINF_SUCCESS;
4467	}
4468
4469	return rc;
4470	}
4471
4472	/** @} */
4473

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 47080

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