HMSVMR0.cpp@ 47123

Last change on this file since 47123 was 47123, checked in by vboxsync, 11 years ago
VMM/HM: Dispatch host NMIs on Intel. Added separate STAM counter for host NMIs with the necessary changes to old, new VT-x, AMD-V code.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 172.7 KB

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1	/* $Id: HMSVMR0.cpp 47123 2013-07-12 15:31:44Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HWSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	#endif
38
39
40	/*******************************************************************************
41	* Defined Constants And Macros *
42	*******************************************************************************/
43	#ifdef VBOX_WITH_STATISTICS
44	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
45	if ((u64ExitCode) == SVM_EXIT_NPF) \
46	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
47	else \
48	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
49	} while (0)
50	#else
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
52	#endif
53
54	/** If we decide to use a function table approach this can be useful to
55	* switch to a "static DECLCALLBACK(int)". */
56	#define HMSVM_EXIT_DECL static int
57
58
59	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
60	*
61	* The CPU format of the segment attribute is described in X86DESCATTRBITS
62	* which is 16-bits (i.e. includes 4 bits of the segment limit).
63	*
64	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
65	* only the attribute bits and nothing else). Upper 4-bits are unused.
66	*
67	* @{ */
68	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) (a & 0xff) \| ((a & 0xf000) >> 4)
69	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) (a & 0xff) \| ((a & 0x0f00) << 4)
70	/** @} */
71
72
73	/** @name Macros for loading, storing segment registers to/from the VMCB.
74	* @{ */
75	#define HMSVM_LOAD_SEG_REG(REG, reg) \
76	do \
77	{ \
78	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
79	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
80	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
81	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
82	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
83	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
84	} while (0)
85
86	#define HMSVM_SAVE_SEG_REG(REG, reg) \
87	do \
88	{ \
89	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
90	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
92	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
93	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
94	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
95	} while (0)
96	/** @} */
97
98
99	/** @name Macro for checking and returning from the using function for
100	* #VMEXIT intercepts that maybe caused during delivering of another
101	* event in the guest. */
102	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
103	do \
104	{ \
105	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
106	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
107	return VINF_SUCCESS; \
108	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
109	return rc; \
110	} while (0)
111	/** @} */
112
113
114	/**
115	* @name Exception bitmap mask for all contributory exceptions.
116	*
117	* Page fault is deliberately excluded here as it's conditional as to whether
118	* it's contributory or benign. Page faults are handled separately.
119	*/
120	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
121	\| RT_BIT(X86_XCPT_DE))
122	/** @} */
123
124
125	/** @name VMCB Clean Bits.
126	*
127	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
128	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
129	* memory.
130	*
131	* @{ */
132	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
133	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
134	/** I/O permission bitmap, MSR permission bitmap. */
135	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
136	/** ASID. */
137	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
138	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
139	V_INTR_VECTOR. */
140	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
141	/** Nested Paging: Nested CR3 (nCR3), PAT. */
142	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
143	/** Control registers (CR0, CR3, CR4, EFER). */
144	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
145	/** Debug registers (DR6, DR7). */
146	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
147	/** GDT, IDT limit and base. */
148	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
149	/** Segment register: CS, SS, DS, ES limit and base. */
150	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
151	/** CR2.*/
152	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
153	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
154	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
155	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
156	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
157	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
158	/** Mask of all valid VMCB Clean bits. */
159	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
160	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
161	\| HMSVM_VMCB_CLEAN_ASID \
162	\| HMSVM_VMCB_CLEAN_TPR \
163	\| HMSVM_VMCB_CLEAN_NP \
164	\| HMSVM_VMCB_CLEAN_CRX_EFER \
165	\| HMSVM_VMCB_CLEAN_DRX \
166	\| HMSVM_VMCB_CLEAN_DT \
167	\| HMSVM_VMCB_CLEAN_SEG \
168	\| HMSVM_VMCB_CLEAN_CR2 \
169	\| HMSVM_VMCB_CLEAN_LBR \
170	\| HMSVM_VMCB_CLEAN_AVIC)
171	/** @} */
172
173	/** @name SVM transient.
174	*
175	* A state structure for holding miscellaneous information across AMD-V
176	* VMRUN/#VMEXIT operation, restored after the transition.
177	*
178	* @{ */
179	typedef struct SVMTRANSIENT
180	{
181	/** The host's rflags/eflags. */
182	RTCCUINTREG uEFlags;
183	#if HC_ARCH_BITS == 32
184	uint32_t u32Alignment0;
185	#endif
186
187	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
188	uint64_t u64ExitCode;
189	/** The guest's TPR value used for TPR shadowing. */
190	uint8_t u8GuestTpr;
191	/** Alignment. */
192	uint8_t abAlignment0[7];
193
194	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
195	bool fRestoreTscAuxMsr;
196	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
197	* contributary exception or a page-fault. */
198	bool fVectoringPF;
199	/** Whether the TSC offset mode needs to be updated. */
200	bool fUpdateTscOffsetting;
201	} SVMTRANSIENT, *PSVMTRANSIENT;
202	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
203	AssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
204	/** @} */
205
206
207	/**
208	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
209	*/
210	typedef enum SVMMSREXITREAD
211	{
212	/** Reading this MSR causes a VM-exit. */
213	SVMMSREXIT_INTERCEPT_READ = 0xb,
214	/** Reading this MSR does not cause a VM-exit. */
215	SVMMSREXIT_PASSTHRU_READ
216	} SVMMSREXITREAD;
217
218	/**
219	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
220	*/
221	typedef enum SVMMSREXITWRITE
222	{
223	/** Writing to this MSR causes a VM-exit. */
224	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
225	/** Writing to this MSR does not cause a VM-exit. */
226	SVMMSREXIT_PASSTHRU_WRITE
227	} SVMMSREXITWRITE;
228
229
230	/*******************************************************************************
231	* Internal Functions *
232	*******************************************************************************/
233	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
234	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
235
236	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
237	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
238	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
239	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
240	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
241	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
242	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
243	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
244	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
245	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
246	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
247	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
248	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
249	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
250	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
251	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
252	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
253	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
257	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
258	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
259	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
263
264	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
265
266
267	/*******************************************************************************
268	* Global Variables *
269	*******************************************************************************/
270	/** Ring-0 memory object for the IO bitmap. */
271	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
272	/** Physical address of the IO bitmap. */
273	RTHCPHYS g_HCPhysIOBitmap = 0;
274	/** Virtual address of the IO bitmap. */
275	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
276
277
278	/**
279	* Sets up and activates AMD-V on the current CPU.
280	*
281	* @returns VBox status code.
282	* @param pCpu Pointer to the CPU info struct.
283	* @param pVM Pointer to the VM (can be NULL after a resume!).
284	* @param pvCpuPage Pointer to the global CPU page.
285	* @param HCPhysCpuPage Physical address of the global CPU page.
286	*/
287	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
288	{
289	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
290	AssertReturn( HCPhysCpuPage
291	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
292	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
293
294	/*
295	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
296	*/
297	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
298	if (u64HostEfer & MSR_K6_EFER_SVME)
299	{
300	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
301	if ( pVM
302	&& pVM->hm.s.svm.fIgnoreInUseError)
303	{
304	pCpu->fIgnoreAMDVInUseError = true;
305	}
306
307	if (!pCpu->fIgnoreAMDVInUseError)
308	return VERR_SVM_IN_USE;
309	}
310
311	/* Turn on AMD-V in the EFER MSR. */
312	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
313
314	/* Write the physical page address where the CPU will store the host state while executing the VM. */
315	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
316
317	/*
318	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
319	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
320	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
321	* to flush the TLB with before using a new ASID.
322	*/
323	pCpu->fFlushAsidBeforeUse = true;
324
325	/*
326	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
327	*/
328	++pCpu->cTlbFlushes;
329
330	return VINF_SUCCESS;
331	}
332
333
334	/**
335	* Deactivates AMD-V on the current CPU.
336	*
337	* @returns VBox status code.
338	* @param pCpu Pointer to the CPU info struct.
339	* @param pvCpuPage Pointer to the global CPU page.
340	* @param HCPhysCpuPage Physical address of the global CPU page.
341	*/
342	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
343	{
344	AssertReturn( HCPhysCpuPage
345	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
346	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
347	NOREF(pCpu);
348
349	/* Turn off AMD-V in the EFER MSR. */
350	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
351	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
352
353	/* Invalidate host state physical address. */
354	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
355
356	return VINF_SUCCESS;
357	}
358
359
360	/**
361	* Does global AMD-V initialization (called during module initialization).
362	*
363	* @returns VBox status code.
364	*/
365	VMMR0DECL(int) SVMR0GlobalInit(void)
366	{
367	/*
368	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
369	* once globally here instead of per-VM.
370	*/
371	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
372	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
373	if (RT_FAILURE(rc))
374	return rc;
375
376	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
377	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
378
379	/* Set all bits to intercept all IO accesses. */
380	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
381	return VINF_SUCCESS;
382	}
383
384
385	/**
386	* Does global AMD-V termination (called during module termination).
387	*/
388	VMMR0DECL(void) SVMR0GlobalTerm(void)
389	{
390	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
391	{
392	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
393	g_pvIOBitmap = NULL;
394	g_HCPhysIOBitmap = 0;
395	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
396	}
397	}
398
399
400	/**
401	* Frees any allocated per-VCPU structures for a VM.
402	*
403	* @param pVM Pointer to the VM.
404	*/
405	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
406	{
407	for (uint32_t i = 0; i < pVM->cCpus; i++)
408	{
409	PVMCPU pVCpu = &pVM->aCpus[i];
410	AssertPtr(pVCpu);
411
412	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
413	{
414	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
415	pVCpu->hm.s.svm.pvVmcbHost = 0;
416	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
417	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
418	}
419
420	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
421	{
422	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
423	pVCpu->hm.s.svm.pvVmcb = 0;
424	pVCpu->hm.s.svm.HCPhysVmcb = 0;
425	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
426	}
427
428	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
429	{
430	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
431	pVCpu->hm.s.svm.pvMsrBitmap = 0;
432	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
433	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
434	}
435	}
436	}
437
438
439	/**
440	* Does per-VM AMD-V initialization.
441	*
442	* @returns VBox status code.
443	* @param pVM Pointer to the VM.
444	*/
445	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
446	{
447	int rc = VERR_INTERNAL_ERROR_5;
448
449	/*
450	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
451	*/
452	uint32_t u32Family;
453	uint32_t u32Model;
454	uint32_t u32Stepping;
455	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
456	{
457	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
458	pVM->hm.s.svm.fAlwaysFlushTLB = true;
459	}
460
461	/*
462	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
463	*/
464	for (VMCPUID i = 0; i < pVM->cCpus; i++)
465	{
466	PVMCPU pVCpu = &pVM->aCpus[i];
467	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
468	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
469	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
470	}
471
472	for (VMCPUID i = 0; i < pVM->cCpus; i++)
473	{
474	PVMCPU pVCpu = &pVM->aCpus[i];
475
476	/*
477	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
478	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
479	*/
480	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
481	if (RT_FAILURE(rc))
482	goto failure_cleanup;
483
484	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
485	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
486	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
487	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
488
489	/*
490	* Allocate one page for the guest-state VMCB.
491	*/
492	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
493	if (RT_FAILURE(rc))
494	goto failure_cleanup;
495
496	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
497	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
498	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
499	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
500
501	/*
502	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
503	* SVM to not require one.
504	*/
505	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
506	if (RT_FAILURE(rc))
507	goto failure_cleanup;
508
509	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
510	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
511	/* Set all bits to intercept all MSR accesses (changed later on). */
512	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
513	}
514
515	return VINF_SUCCESS;
516
517	failure_cleanup:
518	hmR0SvmFreeStructs(pVM);
519	return rc;
520	}
521
522
523	/**
524	* Does per-VM AMD-V termination.
525	*
526	* @returns VBox status code.
527	* @param pVM Pointer to the VM.
528	*/
529	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
530	{
531	hmR0SvmFreeStructs(pVM);
532	return VINF_SUCCESS;
533	}
534
535
536	/**
537	* Sets the permission bits for the specified MSR in the MSRPM.
538	*
539	* @param pVCpu Pointer to the VMCPU.
540	* @param uMsr The MSR for which the access permissions are being set.
541	* @param enmRead MSR read permissions.
542	* @param enmWrite MSR write permissions.
543	*/
544	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
545	{
546	unsigned ulBit;
547	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
548
549	/*
550	* Layout:
551	* Byte offset MSR range
552	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
553	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
554	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
555	* 0x1800 - 0x1fff Reserved
556	*/
557	if (uMsr <= 0x00001FFF)
558	{
559	/* Pentium-compatible MSRs. */
560	ulBit = uMsr * 2;
561	}
562	else if ( uMsr >= 0xC0000000
563	&& uMsr <= 0xC0001FFF)
564	{
565	/* AMD Sixth Generation x86 Processor MSRs. */
566	ulBit = (uMsr - 0xC0000000) * 2;
567	pbMsrBitmap += 0x800;
568	}
569	else if ( uMsr >= 0xC0010000
570	&& uMsr <= 0xC0011FFF)
571	{
572	/* AMD Seventh and Eighth Generation Processor MSRs. */
573	ulBit = (uMsr - 0xC0001000) * 2;
574	pbMsrBitmap += 0x1000;
575	}
576	else
577	{
578	AssertFailed();
579	return;
580	}
581
582	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
583	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
584	ASMBitSet(pbMsrBitmap, ulBit);
585	else
586	ASMBitClear(pbMsrBitmap, ulBit);
587
588	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
589	ASMBitSet(pbMsrBitmap, ulBit + 1);
590	else
591	ASMBitClear(pbMsrBitmap, ulBit + 1);
592
593	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
594	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
595	}
596
597
598	/**
599	* Sets up AMD-V for the specified VM.
600	* This function is only called once per-VM during initalization.
601	*
602	* @returns VBox status code.
603	* @param pVM Pointer to the VM.
604	*/
605	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
606	{
607	int rc = VINF_SUCCESS;
608
609	AssertReturn(pVM, VERR_INVALID_PARAMETER);
610	Assert(pVM->hm.s.svm.fSupported);
611
612	for (VMCPUID i = 0; i < pVM->cCpus; i++)
613	{
614	PVMCPU pVCpu = &pVM->aCpus[i];
615	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
616
617	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
618
619	/* Trap exceptions unconditionally (debug purposes). */
620	#ifdef HMSVM_ALWAYS_TRAP_PF
621	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
622	#endif
623	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
624	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
625	pVmcb->ctrl.u32InterceptException \|= 0
626	\| RT_BIT(X86_XCPT_BP)
627	\| RT_BIT(X86_XCPT_DB)
628	\| RT_BIT(X86_XCPT_DE)
629	\| RT_BIT(X86_XCPT_NM)
630	\| RT_BIT(X86_XCPT_UD)
631	\| RT_BIT(X86_XCPT_NP)
632	\| RT_BIT(X86_XCPT_SS)
633	\| RT_BIT(X86_XCPT_GP)
634	\| RT_BIT(X86_XCPT_PF)
635	\| RT_BIT(X86_XCPT_MF)
636	;
637	#endif
638
639	/* Set up unconditional intercepts and conditions. */
640	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
641	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
642	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
643	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
644	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
645	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
646	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
647	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
648	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
649	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
650	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
651	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
652
653	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
654	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
655	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
656	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
657	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
658	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
659	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
660	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
661	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
662	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
663
664	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
665	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
666
667	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
668	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
669
670	/* Intercept all DRx reads and writes by default. Changed later on. */
671	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
672	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
673
674	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
675	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
676
677	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
678	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
679	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
680
681	/* Set IO and MSR bitmap permission bitmap physical addresses. */
682	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
683	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
684
685	/* No LBR virtualization. */
686	pVmcb->ctrl.u64LBRVirt = 0;
687
688	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
689	pVmcb->ctrl.u64VmcbCleanBits = 0;
690
691	/* The host ASID MBZ, for the guest start with 1. */
692	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
693
694	/*
695	* Setup the PAT MSR (applicable for Nested Paging only).
696	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
697	* so choose type 6 for all PAT slots.
698	*/
699	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
700
701	/* Without Nested Paging, we need additionally intercepts. */
702	if (!pVM->hm.s.fNestedPaging)
703	{
704	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
705	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
706	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
707
708	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
709	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
710	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
711
712	/* Page faults must be intercepted to implement shadow paging. */
713	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
714	}
715
716	/*
717	* The following MSRs are saved/restored automatically during the world-switch.
718	* Don't intercept guest read/write accesses to these MSRs.
719	*/
720	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
721	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
722	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
723	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
724	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
725	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
726	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
727	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
728	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
729	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
730	}
731
732	return rc;
733	}
734
735
736	/**
737	* Invalidates a guest page by guest virtual address.
738	*
739	* @returns VBox status code.
740	* @param pVM Pointer to the VM.
741	* @param pVCpu Pointer to the VMCPU.
742	* @param GCVirt Guest virtual address of the page to invalidate.
743	*/
744	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
745	{
746	AssertReturn(pVM, VERR_INVALID_PARAMETER);
747	Assert(pVM->hm.s.svm.fSupported);
748
749	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
750
751	/* Skip it if a TLB flush is already pending. */
752	if (!fFlushPending)
753	{
754	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
755
756	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
757	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
758
759	#if HC_ARCH_BITS == 32
760	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
761	if (CPUMIsGuestInLongMode(pVCpu))
762	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
763	else
764	#endif
765	{
766	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
767	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
768	}
769	}
770	return VINF_SUCCESS;
771	}
772
773
774	/**
775	* Flushes the appropriate tagged-TLB entries.
776	*
777	* @param pVM Pointer to the VM.
778	* @param pVCpu Pointer to the VMCPU.
779	*/
780	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
781	{
782	PVM pVM = pVCpu->CTX_SUFF(pVM);
783	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
784	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
785
786	/*
787	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
788	* This can happen both for start & resume due to long jumps back to ring-3.
789	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
790	* so we cannot reuse the ASIDs without flushing.
791	*/
792	bool fNewAsid = false;
793	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
794	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
795	{
796	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
797	pVCpu->hm.s.fForceTLBFlush = true;
798	fNewAsid = true;
799	}
800
801	/* Set TLB flush state as checked until we return from the world switch. */
802	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
803
804	/* Check for explicit TLB shootdowns. */
805	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
806	{
807	pVCpu->hm.s.fForceTLBFlush = true;
808	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
809	}
810
811	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
812	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
813
814	if (pVM->hm.s.svm.fAlwaysFlushTLB)
815	{
816	/*
817	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
818	*/
819	pCpu->uCurrentAsid = 1;
820	pVCpu->hm.s.uCurrentAsid = 1;
821	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
822	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
823	}
824	else if (pVCpu->hm.s.fForceTLBFlush)
825	{
826	if (fNewAsid)
827	{
828	++pCpu->uCurrentAsid;
829	bool fHitASIDLimit = false;
830	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
831	{
832	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
833	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
834	fHitASIDLimit = true;
835
836	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
837	{
838	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
839	pCpu->fFlushAsidBeforeUse = true;
840	}
841	else
842	{
843	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
844	pCpu->fFlushAsidBeforeUse = false;
845	}
846	}
847
848	if ( !fHitASIDLimit
849	&& pCpu->fFlushAsidBeforeUse)
850	{
851	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
852	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
853	else
854	{
855	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
856	pCpu->fFlushAsidBeforeUse = false;
857	}
858	}
859
860	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
861	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
862	}
863	else
864	{
865	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
866	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
867	else
868	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
869	}
870
871	pVCpu->hm.s.fForceTLBFlush = false;
872	}
873	else
874	{
875	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
876	* not be executed. See hmQueueInvlPage() where it is commented
877	* out. Support individual entry flushing someday. */
878	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
879	{
880	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
881	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
882	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
883	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
884	}
885	}
886
887	pVCpu->hm.s.TlbShootdown.cPages = 0;
888	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
889
890	/* Update VMCB with the ASID. */
891	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
892	{
893	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
894	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
895	}
896
897	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
898	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
899	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
900	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
901	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
902	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
903
904	#ifdef VBOX_WITH_STATISTICS
905	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
906	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
907	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
908	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
909	{
910	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
911	}
912	else
913	{
914	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
915	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
916	}
917	#endif
918	}
919
920
921	/** @name 64-bit guest on 32-bit host OS helper functions.
922	*
923	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
924	* mode (code segment, paging). These wrappers/helpers perform the necessary
925	* bits for the 32->64 switcher.
926	*
927	* @{ */
928	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
929	/**
930	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
931	*
932	* @returns VBox status code.
933	* @param HCPhysVmcbHost Physical address of host VMCB.
934	* @param HCPhysVmcb Physical address of the VMCB.
935	* @param pCtx Pointer to the guest-CPU context.
936	* @param pVM Pointer to the VM.
937	* @param pVCpu Pointer to the VMCPU.
938	*/
939	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
940	{
941	uint32_t aParam[4];
942	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
943	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
944	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
945	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
946
947	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
948	}
949
950
951	/**
952	* Executes the specified VMRUN handler in 64-bit mode.
953	*
954	* @returns VBox status code.
955	* @param pVM Pointer to the VM.
956	* @param pVCpu Pointer to the VMCPU.
957	* @param pCtx Pointer to the guest-CPU context.
958	* @param enmOp The operation to perform.
959	* @param cbParam Number of parameters.
960	* @param paParam Array of 32-bit parameters.
961	*/
962	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
963	uint32_t *paParam)
964	{
965	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
966	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
967
968	/* Disable interrupts. */
969	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
970
971	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
972	RTCPUID idHostCpu = RTMpCpuId();
973	CPUMR0SetLApic(pVM, idHostCpu);
974	#endif
975
976	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
977	CPUMSetHyperEIP(pVCpu, enmOp);
978	for (int i = (int)cbParam - 1; i >= 0; i--)
979	CPUMPushHyper(pVCpu, paParam[i]);
980
981	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
982	/* Call the switcher. */
983	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
984	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
985
986	/* Restore interrupts. */
987	ASMSetFlags(uOldEFlags);
988	return rc;
989	}
990
991	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
992	/** @} */
993
994
995	/**
996	* Adds an exception to the intercept exception bitmap in the VMCB and updates
997	* the corresponding VMCB Clean Bit.
998	*
999	* @param pVmcb Pointer to the VMCB.
1000	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1001	*/
1002	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1003	{
1004	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1005	{
1006	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1007	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1008	}
1009	}
1010
1011
1012	/**
1013	* Removes an exception from the intercept-exception bitmap in the VMCB and
1014	* updates the corresponding VMCB Clean Bit.
1015	*
1016	* @param pVmcb Pointer to the VMCB.
1017	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1018	*/
1019	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1020	{
1021	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1022	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1023	{
1024	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1025	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1026	}
1027	#endif
1028	}
1029
1030
1031	/**
1032	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1033	*
1034	* @returns VBox status code.
1035	* @param pVCpu Pointer to the VMCPU.
1036	* @param pVmcb Pointer to the VMCB.
1037	* @param pCtx Pointer the guest-CPU context.
1038	*
1039	* @remarks No-long-jump zone!!!
1040	*/
1041	DECLINLINE(int) hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1042	{
1043	/*
1044	* Guest CR0.
1045	*/
1046	PVM pVM = pVCpu->CTX_SUFF(pVM);
1047	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1048	{
1049	uint64_t u64GuestCR0 = pCtx->cr0;
1050
1051	/* Always enable caching. */
1052	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1053
1054	/*
1055	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1056	*/
1057	if (!pVM->hm.s.fNestedPaging)
1058	{
1059	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1060	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1061	}
1062
1063	/*
1064	* Guest FPU bits.
1065	*/
1066	bool fInterceptNM = false;
1067	bool fInterceptMF = false;
1068	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1069	if (CPUMIsGuestFPUStateActive(pVCpu))
1070	{
1071	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1072	if (!(u64GuestCR0 & X86_CR0_NE))
1073	{
1074	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1075	fInterceptMF = true;
1076	}
1077	}
1078	else
1079	{
1080	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1081	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1082	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1083	}
1084
1085	/*
1086	* Update the exception intercept bitmap.
1087	*/
1088	if (fInterceptNM)
1089	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1090	else
1091	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1092
1093	if (fInterceptMF)
1094	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1095	else
1096	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1097
1098	pVmcb->guest.u64CR0 = u64GuestCR0;
1099	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1100	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1101	}
1102
1103	/*
1104	* Guest CR2.
1105	*/
1106	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1107	{
1108	pVmcb->guest.u64CR2 = pCtx->cr2;
1109	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1110	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1111	}
1112
1113	/*
1114	* Guest CR3.
1115	*/
1116	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1117	{
1118	if (pVM->hm.s.fNestedPaging)
1119	{
1120	PGMMODE enmShwPagingMode;
1121	#if HC_ARCH_BITS == 32
1122	if (CPUMIsGuestInLongModeEx(pCtx))
1123	enmShwPagingMode = PGMMODE_AMD64_NX;
1124	else
1125	#endif
1126	enmShwPagingMode = PGMGetHostMode(pVM);
1127
1128	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1129	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1130	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1131	pVmcb->guest.u64CR3 = pCtx->cr3;
1132	}
1133	else
1134	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1135
1136	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1137	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1138	}
1139
1140	/*
1141	* Guest CR4.
1142	*/
1143	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1144	{
1145	uint64_t u64GuestCR4 = pCtx->cr4;
1146	if (!pVM->hm.s.fNestedPaging)
1147	{
1148	switch (pVCpu->hm.s.enmShadowMode)
1149	{
1150	case PGMMODE_REAL:
1151	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1152	AssertFailed();
1153	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1154
1155	case PGMMODE_32_BIT: /* 32-bit paging. */
1156	u64GuestCR4 &= ~X86_CR4_PAE;
1157	break;
1158
1159	case PGMMODE_PAE: /* PAE paging. */
1160	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1161	/** Must use PAE paging as we could use physical memory > 4 GB */
1162	u64GuestCR4 \|= X86_CR4_PAE;
1163	break;
1164
1165	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1166	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1167	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1168	break;
1169	#else
1170	AssertFailed();
1171	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1172	#endif
1173
1174	default: /* shut up gcc */
1175	AssertFailed();
1176	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1177	}
1178	}
1179
1180	pVmcb->guest.u64CR4 = u64GuestCR4;
1181	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1182	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1183	}
1184
1185	return VINF_SUCCESS;
1186	}
1187
1188
1189	/**
1190	* Loads the guest segment registers into the VMCB.
1191	*
1192	* @returns VBox status code.
1193	* @param pVCpu Pointer to the VMCPU.
1194	* @param pVmcb Pointer to the VMCB.
1195	* @param pCtx Pointer to the guest-CPU context.
1196	*
1197	* @remarks No-long-jump zone!!!
1198	*/
1199	DECLINLINE(void) hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1200	{
1201	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1202	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1203	{
1204	HMSVM_LOAD_SEG_REG(CS, cs);
1205	HMSVM_LOAD_SEG_REG(SS, ss);
1206	HMSVM_LOAD_SEG_REG(DS, ds);
1207	HMSVM_LOAD_SEG_REG(ES, es);
1208	HMSVM_LOAD_SEG_REG(FS, fs);
1209	HMSVM_LOAD_SEG_REG(GS, gs);
1210
1211	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1212	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1213	}
1214
1215	/* Guest TR. */
1216	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1217	{
1218	HMSVM_LOAD_SEG_REG(TR, tr);
1219	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1220	}
1221
1222	/* Guest LDTR. */
1223	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1224	{
1225	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1226	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1227	}
1228
1229	/* Guest GDTR. */
1230	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1231	{
1232	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1233	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1234	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1235	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1236	}
1237
1238	/* Guest IDTR. */
1239	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1240	{
1241	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1242	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1243	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1244	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1245	}
1246	}
1247
1248
1249	/**
1250	* Loads the guest MSRs into the VMCB.
1251	*
1252	* @param pVCpu Pointer to the VMCPU.
1253	* @param pVmcb Pointer to the VMCB.
1254	* @param pCtx Pointer to the guest-CPU context.
1255	*
1256	* @remarks No-long-jump zone!!!
1257	*/
1258	DECLINLINE(void) hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1259	{
1260	/* Guest Sysenter MSRs. */
1261	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1262	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1263	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1264
1265	/*
1266	* Guest EFER MSR.
1267	* AMD-V requires guest EFER.SVME to be set. Weird. .
1268	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1269	*/
1270	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1271	{
1272	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1273	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1274	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1275	}
1276
1277	/* 64-bit MSRs. */
1278	if (CPUMIsGuestInLongModeEx(pCtx))
1279	{
1280	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1281	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1282	}
1283	else
1284	{
1285	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1286	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1287	{
1288	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1289	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1290	}
1291	}
1292
1293
1294	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1295	* be writable in 32-bit mode. Clarify with AMD spec. */
1296	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1297	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1298	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1299	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1300	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1301	}
1302
1303
1304	/**
1305	* Loads the guest debug registers into the VMCB.
1306	*
1307	* @param pVCpu Pointer to the VMCPU.
1308	* @param pVmcb Pointer to the VMCB.
1309	* @param pCtx Pointer to the guest-CPU context.
1310	*
1311	* @remarks No-long-jump zone!!!
1312	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1313	*/
1314	DECLINLINE(void) hmR0SvmLoadGuestDebugRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1315	{
1316	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1317	return;
1318
1319	/** @todo Turn these into assertions if possible. */
1320	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* Set reserved bits to 1. */
1321	pCtx->dr[6] &= ~RT_BIT(12); /* MBZ. */
1322
1323	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
1324	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
1325	pCtx->dr[7] \|= 0x400; /* MB1. */
1326
1327	/* Update DR6, DR7 with the guest values. */
1328	pVmcb->guest.u64DR7 = pCtx->dr[7];
1329	pVmcb->guest.u64DR6 = pCtx->dr[6];
1330	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1331
1332	bool fInterceptDB = false;
1333	bool fInterceptMovDRx = false;
1334	if (DBGFIsStepping(pVCpu))
1335	{
1336	/* AMD-V doesn't have any monitor-trap flag equivalent. Instead, enable tracing in the guest and trap #DB. */
1337	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1338	fInterceptDB = true;
1339	}
1340
1341	PVM pVM = pVCpu->CTX_SUFF(pVM);
1342	if (CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1343	{
1344	if (!CPUMIsHyperDebugStateActive(pVCpu))
1345	{
1346	int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1347	AssertRC(rc);
1348
1349	/* Update DR6, DR7 with the hypervisor values. */
1350	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1351	pVmcb->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
1352	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1353	}
1354	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1355	fInterceptMovDRx = true;
1356	}
1357	else if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1358	{
1359	if (!CPUMIsGuestDebugStateActive(pVCpu))
1360	{
1361	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1362	AssertRC(rc);
1363	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1364	}
1365	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1366	Assert(fInterceptMovDRx == false);
1367	}
1368	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1369	{
1370	/* For the first time we would need to intercept MOV DRx accesses even when the guest debug registers aren't loaded. */
1371	fInterceptMovDRx = true;
1372	}
1373
1374	if (fInterceptDB)
1375	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1376	else
1377	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1378
1379	if (fInterceptMovDRx)
1380	{
1381	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1382	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1383	{
1384	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1385	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1386	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1387	}
1388	}
1389	else
1390	{
1391	if ( pVmcb->ctrl.u16InterceptRdDRx
1392	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1393	{
1394	pVmcb->ctrl.u16InterceptRdDRx = 0;
1395	pVmcb->ctrl.u16InterceptWrDRx = 0;
1396	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1397	}
1398	}
1399
1400	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1401	}
1402
1403
1404	/**
1405	* Loads the guest APIC state (currently just the TPR).
1406	*
1407	* @returns VBox status code.
1408	* @param pVCpu Pointer to the VMCPU.
1409	* @param pVmcb Pointer to the VMCB.
1410	* @param pCtx Pointer to the guest-CPU context.
1411	*/
1412	DECLINLINE(int) hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1413	{
1414	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1415	return VINF_SUCCESS;
1416
1417	bool fPendingIntr;
1418	uint8_t u8Tpr;
1419	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1420	AssertRCReturn(rc, rc);
1421
1422	/** Assume that we need to trap all TPR accesses and thus need not check on
1423	* every #VMEXIT if we should update the TPR. */
1424	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1425	pVCpu->hm.s.svm.fSyncVTpr = false;
1426
1427	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1428	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1429	{
1430	pCtx->msrLSTAR = u8Tpr;
1431
1432	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1433	if (fPendingIntr)
1434	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1435	else
1436	{
1437	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1438	pVCpu->hm.s.svm.fSyncVTpr = true;
1439	}
1440	}
1441	else
1442	{
1443	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1444	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1445
1446	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1447	if (fPendingIntr)
1448	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1449	else
1450	{
1451	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1452	pVCpu->hm.s.svm.fSyncVTpr = true;
1453	}
1454
1455	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1456	}
1457
1458	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1459	return rc;
1460	}
1461
1462
1463	/**
1464	* Sets up the appropriate function to run guest code.
1465	*
1466	* @returns VBox status code.
1467	* @param pVCpu Pointer to the VMCPU.
1468	* @param pCtx Pointer to the guest-CPU context.
1469	*
1470	* @remarks No-long-jump zone!!!
1471	*/
1472	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1473	{
1474	if (CPUMIsGuestInLongModeEx(pCtx))
1475	{
1476	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1477	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1478	#endif
1479	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1480	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1481	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1482	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1483	#else
1484	/* 64-bit host or hybrid host. */
1485	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1486	#endif
1487	}
1488	else
1489	{
1490	/* Guest is not in long mode, use the 32-bit handler. */
1491	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1492	}
1493	return VINF_SUCCESS;
1494	}
1495
1496
1497	/**
1498	* Enters the AMD-V session.
1499	*
1500	* @returns VBox status code.
1501	* @param pVM Pointer to the VM.
1502	* @param pVCpu Pointer to the VMCPU.
1503	* @param pCpu Pointer to the CPU info struct.
1504	*/
1505	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
1506	{
1507	AssertPtr(pVM);
1508	AssertPtr(pVCpu);
1509	Assert(pVM->hm.s.svm.fSupported);
1510	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1511	NOREF(pCpu);
1512
1513	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1514
1515	/* Nothing to do here. */
1516	return VINF_SUCCESS;
1517	}
1518
1519
1520	/**
1521	* Leaves the AMD-V session.
1522	*
1523	* @returns VBox status code.
1524	* @param pVM Pointer to the VM.
1525	* @param pVCpu Pointer to the VMCPU.
1526	* @param pCtx Pointer to the guest-CPU context.
1527	*/
1528	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1529	{
1530	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1531	NOREF(pVM);
1532	NOREF(pVCpu);
1533	NOREF(pCtx);
1534
1535	/* Nothing to do here. Everything is taken care of in hmR0SvmLongJmpToRing3(). */
1536	return VINF_SUCCESS;
1537	}
1538
1539
1540	/**
1541	* Saves the host state.
1542	*
1543	* @returns VBox status code.
1544	* @param pVM Pointer to the VM.
1545	* @param pVCpu Pointer to the VMCPU.
1546	*
1547	* @remarks No-long-jump zone!!!
1548	*/
1549	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1550	{
1551	NOREF(pVM);
1552	NOREF(pVCpu);
1553	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1554	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1555	return VINF_SUCCESS;
1556	}
1557
1558
1559	/**
1560	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1561	* fields on every successful VM-entry.
1562	*
1563	* Sets up the appropriate VMRUN function to execute guest code based
1564	* on the guest CPU mode.
1565	*
1566	* @returns VBox status code.
1567	* @param pVM Pointer to the VM.
1568	* @param pVCpu Pointer to the VMCPU.
1569	* @param pMixedCtx Pointer to the guest-CPU context.
1570	*
1571	* @remarks No-long-jump zone!!!
1572	*/
1573	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1574	{
1575	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1576	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1577
1578	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1579
1580	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1581	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1582
1583	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1584	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1585
1586	pVmcb->guest.u64RIP = pCtx->rip;
1587	pVmcb->guest.u64RSP = pCtx->rsp;
1588	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1589	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1590	pVmcb->guest.u64RAX = pCtx->rax;
1591
1592	/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
1593	hmR0SvmLoadGuestDebugRegs(pVCpu, pVmcb, pCtx);
1594
1595	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1596	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1597
1598	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1599	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1600
1601	/* Clear any unused and reserved bits. */
1602	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_MSR /* Unused (legacy). */
1603	\| HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1604	\| HM_CHANGED_GUEST_RSP
1605	\| HM_CHANGED_GUEST_RFLAGS
1606	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1607	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1608	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1609	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1610	\| HM_CHANGED_SVM_RESERVED2
1611	\| HM_CHANGED_SVM_RESERVED3);
1612
1613	AssertMsg(!pVCpu->hm.s.fContextUseFlags,
1614	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1615	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1616
1617	Log4(("Load: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
1618
1619	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1620	return rc;
1621	}
1622
1623
1624	/**
1625	* Loads the guest state on the way from ring-3.
1626	*
1627	* @returns VBox status code.
1628	* @param pVM Pointer to the VM.
1629	* @param pVCpu Pointer to the VMCPU.
1630	* @param pCtx Pointer to the guest-CPU context.
1631	*
1632	* @remarks No-long-jump zone!!!
1633	*/
1634	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1635	{
1636	/*
1637	* Avoid reloading the guest state on longjmp reentrants and do it lazily just before executing the guest.
1638	* This only helps when we get rescheduled more than once to a different host CPU on a longjmp trip before
1639	* finally executing guest code.
1640	*/
1641	return VINF_SUCCESS;
1642	}
1643
1644
1645	/**
1646	* Saves the entire guest state from the VMCB into the
1647	* guest-CPU context. Currently there is no residual state left in the CPU that
1648	* is not updated in the VMCB.
1649	*
1650	* @returns VBox status code.
1651	* @param pVCpu Pointer to the VMCPU.
1652	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1653	* out-of-sync. Make sure to update the required fields
1654	* before using them.
1655	*/
1656	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1657	{
1658	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1659
1660	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1661
1662	pMixedCtx->rip = pVmcb->guest.u64RIP;
1663	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1664	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1665	pMixedCtx->rax = pVmcb->guest.u64RAX;
1666
1667	/*
1668	* Guest interrupt shadow.
1669	*/
1670	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1671	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1672	else
1673	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1674
1675	/*
1676	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1677	*/
1678	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1679
1680	/*
1681	* Guest MSRs.
1682	*/
1683	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1684	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1685	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1686	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1687	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1688	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1689	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1690	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1691
1692	/*
1693	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1694	*/
1695	HMSVM_SAVE_SEG_REG(CS, cs);
1696	HMSVM_SAVE_SEG_REG(SS, ss);
1697	HMSVM_SAVE_SEG_REG(DS, ds);
1698	HMSVM_SAVE_SEG_REG(ES, es);
1699	HMSVM_SAVE_SEG_REG(FS, fs);
1700	HMSVM_SAVE_SEG_REG(GS, gs);
1701
1702	/*
1703	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1704	* register (yet).
1705	*/
1706	/** @todo SELM might need to be fixed as it too should not care about the
1707	* granularity bit. See @bugref{6785}. */
1708	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1709	&& pMixedCtx->cs.Attr.n.u1Present
1710	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1711	{
1712	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1713	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1714	}
1715
1716	#ifdef VBOX_STRICT
1717	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1718	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1719	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1720	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1721	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1722	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1723	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1724
1725	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1726	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1727	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1728	HMSVM_ASSERT_SEG_GRANULARITY(es);
1729	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1730	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1731
1732	# undef HMSVM_ASSERT_SEL_GRANULARITY
1733	#endif
1734
1735	/*
1736	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1737	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1738	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1739	* See AMD spec. 15.5.1 "Basic operation".
1740	*/
1741	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1742	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1743
1744	/*
1745	* Guest Descriptor-Table registers.
1746	*/
1747	HMSVM_SAVE_SEG_REG(TR, tr);
1748	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1749	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1750	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1751
1752	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1753	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1754
1755	/*
1756	* Guest Debug registers.
1757	*/
1758	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1759	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1760
1761	/*
1762	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1763	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1764	*/
1765	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1766	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1767	{
1768	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1769	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1770	}
1771	}
1772
1773
1774	/**
1775	* Does the necessary state syncing before doing a longjmp to ring-3.
1776	*
1777	* @param pVM Pointer to the VM.
1778	* @param pVCpu Pointer to the VMCPU.
1779	* @param pCtx Pointer to the guest-CPU context.
1780	* @param rcExit The reason for exiting to ring-3. Can be
1781	* VINF_VMM_UNKNOWN_RING3_CALL.
1782	*
1783	* @remarks No-long-jmp zone!!!
1784	*/
1785	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1786	{
1787	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1788	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1789
1790	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1791	if (CPUMIsGuestFPUStateActive(pVCpu))
1792	{
1793	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1794	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1795	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1796	}
1797
1798	/* Restore host debug registers if necessary and resync on next R0 reentry. */
1799	if (CPUMIsGuestDebugStateActive(pVCpu))
1800	{
1801	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
1802	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1803	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1804	}
1805	else if (CPUMIsHyperDebugStateActive(pVCpu))
1806	{
1807	CPUMR0LoadHostDebugState(pVM, pVCpu);
1808	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1809	#ifdef VBOX_STRICT
1810	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1811	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1812	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1813	#endif
1814	}
1815
1816	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
1817	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
1818	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1819	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1820	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1821
1822	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1823	}
1824
1825
1826	/**
1827	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
1828	* any remaining host state) before we longjump to ring-3 and possibly get
1829	* preempted.
1830	*
1831	* @param pVCpu Pointer to the VMCPU.
1832	* @param enmOperation The operation causing the ring-3 longjump.
1833	* @param pvUser The user argument (pointer to the possibly
1834	* out-of-date guest-CPU context).
1835	*
1836	* @remarks Must never be called with @a enmOperation ==
1837	* VMMCALLRING3_VM_R0_ASSERTION.
1838	*/
1839	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1840	{
1841	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
1842	Assert(pVCpu);
1843	Assert(pvUser);
1844	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1845	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1846
1847	VMMRZCallRing3Disable(pVCpu);
1848	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1849	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
1850	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser, VINF_VMM_UNKNOWN_RING3_CALL);
1851	VMMRZCallRing3Enable(pVCpu);
1852	}
1853
1854
1855	/**
1856	* An action requires us to go back to ring-3. This function does the necessary
1857	* steps before we can safely return to ring-3. This is not the same as longjmps
1858	* to ring-3, this is voluntary.
1859	*
1860	* @param pVM Pointer to the VM.
1861	* @param pVCpu Pointer to the VMCPU.
1862	* @param pCtx Pointer to the guest-CPU context.
1863	* @param rcExit The reason for exiting to ring-3. Can be
1864	* VINF_VMM_UNKNOWN_RING3_CALL.
1865	*/
1866	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1867	{
1868	Assert(pVM);
1869	Assert(pVCpu);
1870	Assert(pCtx);
1871	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1872
1873	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
1874	{
1875	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
1876	return;
1877	}
1878
1879	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
1880	VMMRZCallRing3Disable(pVCpu);
1881	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
1882
1883	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
1884	if (pVCpu->hm.s.Event.fPending)
1885	{
1886	hmR0SvmPendingEventToTrpmTrap(pVCpu);
1887	Assert(!pVCpu->hm.s.Event.fPending);
1888	}
1889
1890	/* Sync. the guest state. */
1891	hmR0SvmLongJmpToRing3(pVM, pVCpu, pCtx, rcExit);
1892	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1893
1894	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1895	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
1896	\| CPUM_CHANGED_LDTR
1897	\| CPUM_CHANGED_GDTR
1898	\| CPUM_CHANGED_IDTR
1899	\| CPUM_CHANGED_TR
1900	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
1901
1902	/* On our way back from ring-3 the following needs to be done. */
1903	/** @todo This can change with preemption hooks. */
1904	if (rcExit == VINF_EM_RAW_INTERRUPT)
1905	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
1906	else
1907	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1908
1909	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
1910	VMMRZCallRing3Enable(pVCpu);
1911	}
1912
1913
1914	/**
1915	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
1916	* intercepts.
1917	*
1918	* @param pVCpu Pointer to the VMCPU.
1919	*
1920	* @remarks No-long-jump zone!!!
1921	*/
1922	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
1923	{
1924	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1925	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
1926	{
1927	uint64_t u64CurTSC = ASMReadTSC();
1928	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
1929	{
1930	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
1931	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
1932	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
1933	}
1934	else
1935	{
1936	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1937	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1938	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
1939	}
1940	}
1941	else
1942	{
1943	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1944	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1945	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
1946	}
1947
1948	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1949	}
1950
1951
1952	/**
1953	* Sets an event as a pending event to be injected into the guest.
1954	*
1955	* @param pVCpu Pointer to the VMCPU.
1956	* @param pEvent Pointer to the SVM event.
1957	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
1958	* page-fault.
1959	*
1960	* @remarks Statistics counter assumes this is a guest event being reflected to
1961	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
1962	*/
1963	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
1964	{
1965	Assert(!pVCpu->hm.s.Event.fPending);
1966	Assert(pEvent->n.u1Valid);
1967
1968	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
1969	pVCpu->hm.s.Event.fPending = true;
1970	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
1971
1972	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
1973	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
1974
1975	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
1976	}
1977
1978
1979	/**
1980	* Injects an event into the guest upon VMRUN by updating the relevant field
1981	* in the VMCB.
1982	*
1983	* @param pVCpu Pointer to the VMCPU.
1984	* @param pVmcb Pointer to the guest VMCB.
1985	* @param pCtx Pointer to the guest-CPU context.
1986	* @param pEvent Pointer to the event.
1987	*
1988	* @remarks No-long-jump zone!!!
1989	* @remarks Requires CR0!
1990	*/
1991	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
1992	{
1993	pVmcb->ctrl.EventInject.u = pEvent->u;
1994	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
1995
1996	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
1997	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
1998	}
1999
2000
2001
2002	/**
2003	* Converts any TRPM trap into a pending HM event. This is typically used when
2004	* entering from ring-3 (not longjmp returns).
2005	*
2006	* @param pVCpu Pointer to the VMCPU.
2007	*/
2008	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2009	{
2010	Assert(TRPMHasTrap(pVCpu));
2011	Assert(!pVCpu->hm.s.Event.fPending);
2012
2013	uint8_t uVector;
2014	TRPMEVENT enmTrpmEvent;
2015	RTGCUINT uErrCode;
2016	RTGCUINTPTR GCPtrFaultAddress;
2017	uint8_t cbInstr;
2018
2019	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2020	AssertRC(rc);
2021
2022	SVMEVENT Event;
2023	Event.u = 0;
2024	Event.n.u1Valid = 1;
2025	Event.n.u8Vector = uVector;
2026
2027	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2028	if (enmTrpmEvent == TRPM_TRAP)
2029	{
2030	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2031	switch (uVector)
2032	{
2033	case X86_XCPT_PF:
2034	case X86_XCPT_DF:
2035	case X86_XCPT_TS:
2036	case X86_XCPT_NP:
2037	case X86_XCPT_SS:
2038	case X86_XCPT_GP:
2039	case X86_XCPT_AC:
2040	{
2041	Event.n.u1ErrorCodeValid = 1;
2042	Event.n.u32ErrorCode = uErrCode;
2043	break;
2044	}
2045	}
2046	}
2047	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2048	{
2049	if (uVector == X86_XCPT_NMI)
2050	Event.n.u3Type = SVM_EVENT_NMI;
2051	else
2052	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2053	}
2054	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2055	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2056	else
2057	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2058
2059	rc = TRPMResetTrap(pVCpu);
2060	AssertRC(rc);
2061
2062	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2063	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2064
2065	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2066	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2067	}
2068
2069
2070	/**
2071	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2072	* AMD-V to execute any instruction.
2073	*
2074	* @param pvCpu Pointer to the VMCPU.
2075	*/
2076	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2077	{
2078	Assert(pVCpu->hm.s.Event.fPending);
2079	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2080
2081	SVMEVENT Event;
2082	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2083
2084	uint8_t uVector = Event.n.u8Vector;
2085	uint8_t uVectorType = Event.n.u3Type;
2086
2087	TRPMEVENT enmTrapType;
2088	switch (uVectorType)
2089	{
2090	case SVM_EVENT_EXTERNAL_IRQ:
2091	case SVM_EVENT_NMI:
2092	enmTrapType = TRPM_HARDWARE_INT;
2093	break;
2094	case SVM_EVENT_SOFTWARE_INT:
2095	enmTrapType = TRPM_SOFTWARE_INT;
2096	break;
2097	case SVM_EVENT_EXCEPTION:
2098	enmTrapType = TRPM_TRAP;
2099	break;
2100	default:
2101	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2102	enmTrapType = TRPM_32BIT_HACK;
2103	break;
2104	}
2105
2106	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2107
2108	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2109	AssertRC(rc);
2110
2111	if (Event.n.u1ErrorCodeValid)
2112	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2113
2114	if ( uVectorType == SVM_EVENT_EXCEPTION
2115	&& uVector == X86_XCPT_PF)
2116	{
2117	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2118	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2119	}
2120	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2121	{
2122	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2123	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2124	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2125	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2126	}
2127	pVCpu->hm.s.Event.fPending = false;
2128	}
2129
2130
2131	/**
2132	* Gets the guest's interrupt-shadow.
2133	*
2134	* @returns The guest's interrupt-shadow.
2135	* @param pVCpu Pointer to the VMCPU.
2136	* @param pCtx Pointer to the guest-CPU context.
2137	*
2138	* @remarks No-long-jump zone!!!
2139	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2140	*/
2141	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2142	{
2143	/*
2144	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2145	* inhibit interrupts or clear any existing interrupt-inhibition.
2146	*/
2147	uint32_t uIntrState = 0;
2148	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2149	{
2150	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2151	{
2152	/*
2153	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2154	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2155	*/
2156	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2157	}
2158	else
2159	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2160	}
2161	return uIntrState;
2162	}
2163
2164
2165	/**
2166	* Sets the virtual interrupt intercept control in the VMCB which
2167	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2168	* receive interrupts.
2169	*
2170	* @param pVmcb Pointer to the VMCB.
2171	*/
2172	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2173	{
2174	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2175	{
2176	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2177	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2178	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2179	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2180
2181	Log4(("Setting VINTR intercept\n"));
2182	}
2183	}
2184
2185
2186	/**
2187	* Injects any pending events into the guest if the guest is in a state to
2188	* receive them.
2189	*
2190	* @param pVCpu Pointer to the VMCPU.
2191	* @param pCtx Pointer to the guest-CPU context.
2192	*/
2193	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2194	{
2195	Assert(!TRPMHasTrap(pVCpu));
2196	Log4Func(("\n"));
2197
2198	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2199	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2200	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2201
2202	SVMEVENT Event;
2203	Event.u = 0;
2204	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2205	{
2206	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2207	Assert(Event.n.u1Valid);
2208	bool fInject = true;
2209	if ( Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
2210	&& ( fBlockInt
2211	\|\| fIntShadow))
2212	{
2213	fInject = false;
2214	}
2215	else if ( Event.n.u3Type == SVM_EVENT_NMI
2216	&& fIntShadow)
2217	{
2218	fInject = false;
2219	}
2220
2221	if (fInject)
2222	{
2223	Log4(("Injecting pending HM event.\n"));
2224
2225	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2226	pVCpu->hm.s.Event.fPending = false;
2227
2228	#ifdef VBOX_WITH_STATISTICS
2229	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2230	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2231	else
2232	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2233	#endif
2234	}
2235	else
2236	hmR0SvmSetVirtIntrIntercept(pVmcb);
2237	} /** @todo SMI. SMIs take priority over NMIs. */
2238	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2239	{
2240	if (!fIntShadow)
2241	{
2242	Log4(("Injecting NMI\n"));
2243
2244	Event.n.u1Valid = 1;
2245	Event.n.u8Vector = X86_XCPT_NMI;
2246	Event.n.u3Type = SVM_EVENT_NMI;
2247
2248	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2249	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2250
2251	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2252	}
2253	else
2254	hmR0SvmSetVirtIntrIntercept(pVmcb);
2255	}
2256	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2257	{
2258	/* Check if there are guest external interrupts (PIC/APIC) pending and inject them, if the guest can receive them. */
2259	if ( !fBlockInt
2260	&& !fIntShadow)
2261	{
2262	uint8_t u8Interrupt;
2263	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2264	if (RT_SUCCESS(rc))
2265	{
2266	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2267
2268	Event.n.u1Valid = 1;
2269	Event.n.u8Vector = u8Interrupt;
2270	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2271
2272	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2273	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2274	}
2275	else
2276	{
2277	/** @todo Does this actually happen? If not turn it into an assertion. */
2278	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2279	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2280	}
2281	}
2282	else
2283	hmR0SvmSetVirtIntrIntercept(pVmcb);
2284	}
2285
2286	/* Update the guest interrupt shadow in the VMCB. */
2287	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2288	}
2289
2290
2291	/**
2292	* Reports world-switch error and dumps some useful debug info.
2293	*
2294	* @param pVM Pointer to the VM.
2295	* @param pVCpu Pointer to the VMCPU.
2296	* @param rcVMRun The return code from VMRUN (or
2297	* VERR_SVM_INVALID_GUEST_STATE for invalid
2298	* guest-state).
2299	* @param pCtx Pointer to the guest-CPU context.
2300	*/
2301	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2302	{
2303	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2304	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2305
2306	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2307	{
2308	HMDumpRegs(pVM, pVCpu, pCtx);
2309	#ifdef VBOX_STRICT
2310	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2311	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2312	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2313	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2314	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2315	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2316	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2317	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2318	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2319	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2320	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2321
2322	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2323	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2324	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2325
2326	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2327	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2328	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2329	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2330	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2331	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2332	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2333	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2334	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2335	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2336
2337	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2338	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2339	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2340	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2341	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2342	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2343	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2344	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2345	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2346	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2347	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2348	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2349	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2350	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2351	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2352	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2353	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2354
2355	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2356	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2357
2358	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2359	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2360	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2361	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2362	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2363	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2364	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2365	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2366	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2367	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2368	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2369	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2370	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2371	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2372	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2373	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2374	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2375	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2376	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2377	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2378
2379	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2380	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2381
2382	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2383	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2384	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2385	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2386
2387	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2388	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2389
2390	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2391	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2392	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2393	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2394
2395	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2396	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2397	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2398	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2399	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2400	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2401	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2402
2403	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2404	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2405	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2406	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2407
2408	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2409	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2410	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2411
2412	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2413	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2414	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2415	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2416	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2417	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2418	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2419	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2420	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2421	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2422	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2423	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2424	#endif
2425	}
2426	else
2427	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2428	}
2429
2430
2431	/**
2432	* Check per-VM and per-VCPU force flag actions that require us to go back to
2433	* ring-3 for one reason or another.
2434	*
2435	* @returns VBox status code (information status code included).
2436	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2437	* ring-3.
2438	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2439	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2440	* interrupts)
2441	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2442	* all EMTs to be in ring-3.
2443	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2444	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2445	* to the EM loop.
2446	*
2447	* @param pVM Pointer to the VM.
2448	* @param pVCpu Pointer to the VMCPU.
2449	* @param pCtx Pointer to the guest-CPU context.
2450	*/
2451	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2452	{
2453	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2454
2455	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2456	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2457	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2458
2459	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
2460	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
2461	\| VMCPU_FF_REQUEST))
2462	{
2463	/* Pending PGM C3 sync. */
2464	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2465	{
2466	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2467	if (rc != VINF_SUCCESS)
2468	{
2469	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2470	return rc;
2471	}
2472	}
2473
2474	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2475	/* -XXX- what was that about single stepping? */
2476	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2477	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2478	{
2479	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2480	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2481	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2482	return rc;
2483	}
2484
2485	/* Pending VM request packets, such as hardware interrupts. */
2486	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2487	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2488	{
2489	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2490	return VINF_EM_PENDING_REQUEST;
2491	}
2492
2493	/* Pending PGM pool flushes. */
2494	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2495	{
2496	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2497	return VINF_PGM_POOL_FLUSH_PENDING;
2498	}
2499
2500	/* Pending DMA requests. */
2501	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2502	{
2503	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2504	return VINF_EM_RAW_TO_R3;
2505	}
2506	}
2507
2508	return VINF_SUCCESS;
2509	}
2510
2511
2512	/**
2513	* Does the preparations before executing guest code in AMD-V.
2514	*
2515	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2516	* recompiler. We must be cautious what we do here regarding committing
2517	* guest-state information into the the VMCB assuming we assuredly execute the
2518	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2519	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2520	* that the recompiler can (and should) use them when it resumes guest
2521	* execution. Otherwise such operations must be done when we can no longer
2522	* exit to ring-3.
2523	*
2524	* @returns VBox status code (informational status codes included).
2525	* @retval VINF_SUCCESS if we can proceed with running the guest.
2526	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2527	*
2528	* @param pVM Pointer to the VM.
2529	* @param pVCpu Pointer to the VMCPU.
2530	* @param pCtx Pointer to the guest-CPU context.
2531	* @param pSvmTransient Pointer to the SVM transient structure.
2532	*/
2533	DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2534	{
2535	/* Check force flag actions that might require us to go back to ring-3. */
2536	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2537	if (rc != VINF_SUCCESS)
2538	return rc;
2539
2540	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2541	/* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.) */
2542	pSvmTransient->uEFlags = ASMIntDisableFlags();
2543	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2544	{
2545	ASMSetFlags(pSvmTransient->uEFlags);
2546	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2547	/* Don't use VINF_EM_RAW_INTERRUPT_HYPER as we can't assume the host does kernel preemption. Maybe some day? */
2548	return VINF_EM_RAW_INTERRUPT;
2549	}
2550	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2551	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2552	#endif
2553
2554	/* Convert any pending TRPM traps to HM events for injection. */
2555	/** @todo Optimization: move this before disabling interrupts, restore state
2556	* using pVmcb->ctrl.EventInject.u. */
2557	if (TRPMHasTrap(pVCpu))
2558	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2559
2560	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2561
2562	return VINF_SUCCESS;
2563	}
2564
2565
2566	/**
2567	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2568	* means there is no backing out to ring-3 or anywhere else at this
2569	* point.
2570	*
2571	* @param pVM Pointer to the VM.
2572	* @param pVCpu Pointer to the VMCPU.
2573	* @param pCtx Pointer to the guest-CPU context.
2574	* @param pSvmTransient Pointer to the SVM transient structure.
2575	*
2576	* @remarks Called with preemption disabled.
2577	* @remarks No-long-jump zone!!!
2578	*/
2579	DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2580	{
2581	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2582	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2583
2584	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2585	/** @todo I don't see the point of this, VMMR0EntryFast() already disables interrupts for the entire period. */
2586	pSvmTransient->uEFlags = ASMIntDisableFlags();
2587	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2588	#endif
2589
2590	/*
2591	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2592	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2593	*/
2594	/** @todo The above assumption could be wrong. It's not documented what
2595	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2596	* hard way. */
2597	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2598	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2599
2600	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2601	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2602	#endif
2603
2604	/* Load the guest state. */
2605	int rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2606	AssertRC(rc);
2607	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
2608	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2609
2610	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2611	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2612	pVmcb->ctrl.u64VmcbCleanBits = 0;
2613
2614	/*
2615	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2616	* so we can update it on the way back if the guest changed the TPR.
2617	*/
2618	if (pVCpu->hm.s.svm.fSyncVTpr)
2619	{
2620	if (pVM->hm.s.fTPRPatchingActive)
2621	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2622	else
2623	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2624	}
2625
2626	/* Setup TSC offsetting. */
2627	if ( pSvmTransient->fUpdateTscOffsetting
2628	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2629	{
2630	hmR0SvmUpdateTscOffsetting(pVCpu);
2631	pSvmTransient->fUpdateTscOffsetting = false;
2632	}
2633
2634	/* Flush the appropriate tagged-TLB entries. */
2635	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2636	hmR0SvmFlushTaggedTlb(pVCpu);
2637	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2638
2639	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2640
2641	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2642	to start executing. */
2643
2644	/*
2645	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2646	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2647	*
2648	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2649	*/
2650	pSvmTransient->fRestoreTscAuxMsr = false;
2651	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2652	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2653	{
2654	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2655	uint64_t u64GuestTscAux = 0;
2656	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2657	AssertRC(rc2);
2658	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2659	{
2660	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2661	pSvmTransient->fRestoreTscAuxMsr = true;
2662	}
2663	}
2664	}
2665
2666
2667	/**
2668	* Wrapper for running the guest code in AMD-V.
2669	*
2670	* @returns VBox strict status code.
2671	* @param pVM Pointer to the VM.
2672	* @param pVCpu Pointer to the VMCPU.
2673	* @param pCtx Pointer to the guest-CPU context.
2674	*
2675	* @remarks No-long-jump zone!!!
2676	*/
2677	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2678	{
2679	/*
2680	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2681	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2682	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2683	*/
2684	#ifdef VBOX_WITH_KERNEL_USING_XMM
2685	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2686	pVCpu->hm.s.svm.pfnVMRun);
2687	#else
2688	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2689	#endif
2690	}
2691
2692
2693	/**
2694	* Performs some essential restoration of state after running guest code in
2695	* AMD-V.
2696	*
2697	* @param pVM Pointer to the VM.
2698	* @param pVCpu Pointer to the VMCPU.
2699	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2700	* out-of-sync. Make sure to update the required fields
2701	* before using them.
2702	* @param pSvmTransient Pointer to the SVM transient structure.
2703	* @param rcVMRun Return code of VMRUN.
2704	*
2705	* @remarks Called with interrupts disabled.
2706	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2707	* unconditionally when it is safe to do so.
2708	*/
2709	DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2710	{
2711	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2712
2713	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2714	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2715
2716	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2717	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2718
2719	if (pSvmTransient->fRestoreTscAuxMsr)
2720	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2721
2722	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2723	{
2724	/** @todo Find a way to fix hardcoding a guestimate. */
2725	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
2726	}
2727
2728	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
2729	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2730	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2731
2732	Assert(!(ASMGetFlags() & X86_EFL_IF));
2733	ASMSetFlags(pSvmTransient->uEFlags); /* Enable interrupts. */
2734
2735	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pMixedCtx);
2736	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2737
2738	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2739	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2740	{
2741	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2742	return;
2743	}
2744
2745	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2746	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2747	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2748
2749	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2750	{
2751	if (pVCpu->hm.s.svm.fSyncVTpr)
2752	{
2753	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2754	if ( pVM->hm.s.fTPRPatchingActive
2755	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2756	{
2757	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
2758	AssertRC(rc);
2759	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2760	}
2761	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2762	{
2763	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
2764	AssertRC(rc);
2765	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2766	}
2767	}
2768	}
2769	}
2770
2771
2772	/**
2773	* Runs the guest code using AMD-V.
2774	*
2775	* @returns VBox status code.
2776	* @param pVM Pointer to the VM.
2777	* @param pVCpu Pointer to the VMCPU.
2778	* @param pCtx Pointer to the guest-CPU context.
2779	*/
2780	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2781	{
2782	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2783	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2784
2785	SVMTRANSIENT SvmTransient;
2786	SvmTransient.fUpdateTscOffsetting = true;
2787	uint32_t cLoops = 0;
2788	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2789	int rc = VERR_INTERNAL_ERROR_5;
2790
2791	for (;; cLoops++)
2792	{
2793	Assert(!HMR0SuspendPending());
2794	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
2795	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
2796	(unsigned)RTMpCpuId(), cLoops));
2797
2798	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
2799	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
2800	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
2801	if (rc != VINF_SUCCESS)
2802	break;
2803
2804	/*
2805	* No longjmps to ring-3 from this point on!!!
2806	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2807	* This also disables flushing of the R0-logger instance (if any).
2808	*/
2809	VMMRZCallRing3Disable(pVCpu);
2810	VMMRZCallRing3RemoveNotification(pVCpu);
2811	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
2812
2813	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
2814
2815	/*
2816	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
2817	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
2818	*/
2819	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
2820	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
2821	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
2822	{
2823	if (rc == VINF_SUCCESS)
2824	rc = VERR_SVM_INVALID_GUEST_STATE;
2825	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
2826	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2827	return rc;
2828	}
2829
2830	/* Handle the #VMEXIT. */
2831	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
2832	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
2833	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
2834	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
2835	if (rc != VINF_SUCCESS)
2836	break;
2837	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
2838	{
2839	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
2840	rc = VINF_EM_RAW_INTERRUPT;
2841	break;
2842	}
2843	}
2844
2845	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
2846	if (rc == VERR_EM_INTERPRETER)
2847	rc = VINF_EM_RAW_EMULATE_INSTR;
2848	else if (rc == VINF_EM_RESET)
2849	rc = VINF_EM_TRIPLE_FAULT;
2850	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
2851	return rc;
2852	}
2853
2854
2855	/**
2856	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
2857	*
2858	* @returns VBox status code (informational status codes included).
2859	* @param pVCpu Pointer to the VMCPU.
2860	* @param pCtx Pointer to the guest-CPU context.
2861	* @param pSvmTransient Pointer to the SVM transient structure.
2862	*/
2863	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2864	{
2865	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
2866	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
2867
2868	/*
2869	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
2870	* normal workloads (for some definition of "normal").
2871	*/
2872	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
2873	switch (pSvmTransient->u64ExitCode)
2874	{
2875	case SVM_EXIT_NPF:
2876	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
2877
2878	case SVM_EXIT_IOIO:
2879	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
2880
2881	case SVM_EXIT_RDTSC:
2882	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
2883
2884	case SVM_EXIT_RDTSCP:
2885	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
2886
2887	case SVM_EXIT_CPUID:
2888	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
2889
2890	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
2891	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
2892
2893	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
2894	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
2895
2896	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
2897	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
2898
2899	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
2900	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
2901
2902	case SVM_EXIT_MONITOR:
2903	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
2904
2905	case SVM_EXIT_MWAIT:
2906	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
2907
2908	case SVM_EXIT_HLT:
2909	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
2910
2911	case SVM_EXIT_READ_CR0:
2912	case SVM_EXIT_READ_CR3:
2913	case SVM_EXIT_READ_CR4:
2914	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
2915
2916	case SVM_EXIT_WRITE_CR0:
2917	case SVM_EXIT_WRITE_CR3:
2918	case SVM_EXIT_WRITE_CR4:
2919	case SVM_EXIT_WRITE_CR8:
2920	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
2921
2922	case SVM_EXIT_VINTR:
2923	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
2924
2925	case SVM_EXIT_INTR:
2926	case SVM_EXIT_FERR_FREEZE:
2927	case SVM_EXIT_NMI:
2928	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
2929
2930	case SVM_EXIT_MSR:
2931	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
2932
2933	case SVM_EXIT_INVLPG:
2934	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
2935
2936	case SVM_EXIT_WBINVD:
2937	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
2938
2939	case SVM_EXIT_INVD:
2940	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
2941
2942	case SVM_EXIT_RDPMC:
2943	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
2944
2945	default:
2946	{
2947	switch (pSvmTransient->u64ExitCode)
2948	{
2949	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2950	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
2951	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
2952	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2953	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
2954
2955	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2956	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
2957	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
2958	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2959	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
2960
2961	case SVM_EXIT_TASK_SWITCH:
2962	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
2963
2964	case SVM_EXIT_VMMCALL:
2965	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
2966
2967	case SVM_EXIT_SHUTDOWN:
2968	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
2969
2970	case SVM_EXIT_SMI:
2971	case SVM_EXIT_INIT:
2972	{
2973	/*
2974	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
2975	* we want to know about it so log the exit code and bail.
2976	*/
2977	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
2978	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
2979	return VERR_SVM_UNEXPECTED_EXIT;
2980	}
2981
2982	case SVM_EXIT_INVLPGA:
2983	case SVM_EXIT_RSM:
2984	case SVM_EXIT_VMRUN:
2985	case SVM_EXIT_VMLOAD:
2986	case SVM_EXIT_VMSAVE:
2987	case SVM_EXIT_STGI:
2988	case SVM_EXIT_CLGI:
2989	case SVM_EXIT_SKINIT:
2990	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
2991
2992	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2993	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
2994	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
2995	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
2996	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
2997	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
2998	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
2999	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3000	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3001	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3002	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3003	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3004	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3005	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3006	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3007	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3008	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3009	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3010	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3011	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3012
3013	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3014	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3015	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3016	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3017	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3018	{
3019	SVMEVENT Event;
3020	Event.u = 0;
3021	Event.n.u1Valid = 1;
3022	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3023	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3024
3025	switch (Event.n.u8Vector)
3026	{
3027	case X86_XCPT_DE:
3028	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3029	break;
3030
3031	case X86_XCPT_BP:
3032	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3033	* next instruction. */
3034	/** @todo Investigate this later. */
3035	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3036	break;
3037
3038	case X86_XCPT_UD:
3039	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3040	break;
3041
3042	case X86_XCPT_NP:
3043	Event.n.u1ErrorCodeValid = 1;
3044	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3045	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3046	break;
3047
3048	case X86_XCPT_SS:
3049	Event.n.u1ErrorCodeValid = 1;
3050	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3051	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3052	break;
3053
3054	case X86_XCPT_GP:
3055	Event.n.u1ErrorCodeValid = 1;
3056	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3057	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3058	break;
3059
3060	default:
3061	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3062	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3063	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3064	}
3065
3066	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3067	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3068	return VINF_SUCCESS;
3069	}
3070	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3071
3072	default:
3073	{
3074	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3075	pVCpu->hm.s.u32HMError = u32ExitCode;
3076	return VERR_SVM_UNKNOWN_EXIT;
3077	}
3078	}
3079	}
3080	}
3081	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3082	}
3083
3084
3085	#ifdef DEBUG
3086	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3087	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3088	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3089
3090	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3091	do \
3092	{ \
3093	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3094	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3095	} while (0)
3096
3097	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3098	do { \
3099	AssertPtr(pVCpu); \
3100	AssertPtr(pCtx); \
3101	AssertPtr(pSvmTransient); \
3102	Assert(ASMIntAreEnabled()); \
3103	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3104	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3105	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3106	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3107	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3108	HMSVM_ASSERT_PREEMPT_CPUID(); \
3109	} while (0)
3110	#else /* Release builds */
3111	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3112	#endif
3113
3114
3115	/**
3116	* Worker for hmR0SvmInterpretInvlpg().
3117	*
3118	* @return VBox status code.
3119	* @param pVCpu Pointer to the VMCPU.
3120	* @param pCpu Pointer to the disassembler state.
3121	* @param pRegFrame Pointer to the register frame.
3122	*/
3123	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3124	{
3125	DISQPVPARAMVAL Param1;
3126	RTGCPTR GCPtrPage;
3127
3128	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3129	if (RT_FAILURE(rc))
3130	return VERR_EM_INTERPRETER;
3131
3132	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3133	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3134	{
3135	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3136	return VERR_EM_INTERPRETER;
3137
3138	GCPtrPage = Param1.val.val64;
3139	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3140	rc = VBOXSTRICTRC_VAL(rc2);
3141	}
3142	else
3143	{
3144	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3145	rc = VERR_EM_INTERPRETER;
3146	}
3147
3148	return rc;
3149	}
3150
3151
3152	/**
3153	* Interprets INVLPG.
3154	*
3155	* @returns VBox status code.
3156	* @retval VINF_* Scheduling instructions.
3157	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3158	* @retval VERR_* Fatal errors.
3159	*
3160	* @param pVM Pointer to the VM.
3161	* @param pRegFrame Pointer to the register frame.
3162	*
3163	* @remarks Updates the RIP if the instruction was executed successfully.
3164	*/
3165	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3166	{
3167	/* Only allow 32 & 64 bit code. */
3168	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3169	{
3170	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3171	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3172	if ( RT_SUCCESS(rc)
3173	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3174	{
3175	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3176	if (RT_SUCCESS(rc))
3177	pRegFrame->rip += pDis->cbInstr;
3178	return rc;
3179	}
3180	else
3181	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3182	}
3183	return VERR_EM_INTERPRETER;
3184	}
3185
3186
3187	/**
3188	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3189	*
3190	* @param pVCpu Pointer to the VMCPU.
3191	*/
3192	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3193	{
3194	SVMEVENT Event;
3195	Event.u = 0;
3196	Event.n.u1Valid = 1;
3197	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3198	Event.n.u8Vector = X86_XCPT_UD;
3199	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3200	}
3201
3202
3203	/**
3204	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3205	*
3206	* @param pVCpu Pointer to the VMCPU.
3207	*/
3208	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3209	{
3210	SVMEVENT Event;
3211	Event.u = 0;
3212	Event.n.u1Valid = 1;
3213	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3214	Event.n.u8Vector = X86_XCPT_DB;
3215	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3216	}
3217
3218
3219	/**
3220	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3221	*
3222	* @param pVCpu Pointer to the VMCPU.
3223	* @param pCtx Pointer to the guest-CPU context.
3224	* @param u32ErrCode The error-code for the page-fault.
3225	* @param uFaultAddress The page fault address (CR2).
3226	*
3227	* @remarks This updates the guest CR2 with @a uFaultAddress!
3228	*/
3229	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3230	{
3231	SVMEVENT Event;
3232	Event.u = 0;
3233	Event.n.u1Valid = 1;
3234	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3235	Event.n.u8Vector = X86_XCPT_PF;
3236	Event.n.u1ErrorCodeValid = 1;
3237	Event.n.u32ErrorCode = u32ErrCode;
3238
3239	/* Update CR2 of the guest. */
3240	if (pCtx->cr2 != uFaultAddress)
3241	{
3242	pCtx->cr2 = uFaultAddress;
3243	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR2;
3244	}
3245
3246	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3247	}
3248
3249
3250	/**
3251	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3252	* VM.
3253	*
3254	* @param pVCpu Pointer to the VMCPU.
3255	*/
3256	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3257	{
3258	SVMEVENT Event;
3259	Event.u = 0;
3260	Event.n.u1Valid = 1;
3261	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3262	Event.n.u8Vector = X86_XCPT_NM;
3263	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3264	}
3265
3266
3267	/**
3268	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3269	*
3270	* @param pVCpu Pointer to the VMCPU.
3271	*/
3272	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3273	{
3274	SVMEVENT Event;
3275	Event.u = 0;
3276	Event.n.u1Valid = 1;
3277	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3278	Event.n.u8Vector = X86_XCPT_MF;
3279	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3280	}
3281
3282
3283	/**
3284	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3285	*
3286	* @param pVCpu Pointer to the VMCPU.
3287	*/
3288	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3289	{
3290	SVMEVENT Event;
3291	Event.u = 0;
3292	Event.n.u1Valid = 1;
3293	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3294	Event.n.u8Vector = X86_XCPT_DF;
3295	Event.n.u1ErrorCodeValid = 1;
3296	Event.n.u32ErrorCode = 0;
3297	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3298	}
3299
3300
3301	/**
3302	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3303	* guests. This simply looks up the patch record at EIP and does the required.
3304	*
3305	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3306	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3307	* TPR). See hmR3ReplaceTprInstr() for the details.
3308	*
3309	* @returns VBox status code.
3310	* @param pVM Pointer to the VM.
3311	* @param pVCpu Pointer to the VMCPU.
3312	* @param pCtx Pointer to the guest-CPU context.
3313	*/
3314	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3315	{
3316	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3317	for (;;)
3318	{
3319	bool fPending;
3320	uint8_t u8Tpr;
3321
3322	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3323	if (!pPatch)
3324	break;
3325
3326	switch (pPatch->enmType)
3327	{
3328	case HMTPRINSTR_READ:
3329	{
3330	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3331	AssertRC(rc);
3332
3333	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3334	AssertRC(rc);
3335	pCtx->rip += pPatch->cbOp;
3336	break;
3337	}
3338
3339	case HMTPRINSTR_WRITE_REG:
3340	case HMTPRINSTR_WRITE_IMM:
3341	{
3342	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3343	{
3344	uint32_t u32Val;
3345	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3346	AssertRC(rc);
3347	u8Tpr = u32Val;
3348	}
3349	else
3350	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3351
3352	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3353	AssertRC(rc2);
3354	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3355
3356	pCtx->rip += pPatch->cbOp;
3357	break;
3358	}
3359
3360	default:
3361	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3362	pVCpu->hm.s.u32HMError = pPatch->enmType;
3363	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3364	}
3365	}
3366
3367	return VINF_SUCCESS;
3368	}
3369
3370	/**
3371	* Determines if an exception is a contributory exception. Contributory
3372	* exceptions are ones which can cause double-faults. Page-fault is
3373	* intentionally not included here as it's a conditional contributory exception.
3374	*
3375	* @returns true if the exception is contributory, false otherwise.
3376	* @param uVector The exception vector.
3377	*/
3378	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3379	{
3380	switch (uVector)
3381	{
3382	case X86_XCPT_GP:
3383	case X86_XCPT_SS:
3384	case X86_XCPT_NP:
3385	case X86_XCPT_TS:
3386	case X86_XCPT_DE:
3387	return true;
3388	default:
3389	break;
3390	}
3391	return false;
3392	}
3393
3394
3395	/**
3396	* Handle a condition that occurred while delivering an event through the guest
3397	* IDT.
3398	*
3399	* @returns VBox status code (informational error codes included).
3400	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3401	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3402	* continue execution of the guest which will delivery the #DF.
3403	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3404	*
3405	* @param pVCpu Pointer to the VMCPU.
3406	* @param pCtx Pointer to the guest-CPU context.
3407	* @param pSvmTransient Pointer to the SVM transient structure.
3408	*
3409	* @remarks No-long-jump zone!!!
3410	*/
3411	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3412	{
3413	int rc = VINF_SUCCESS;
3414	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3415
3416	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3417	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3418	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3419	{
3420	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3421
3422	typedef enum
3423	{
3424	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3425	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3426	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3427	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3428	} SVMREFLECTXCPT;
3429
3430	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3431	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3432	{
3433	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3434	{
3435	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3436
3437	#ifdef VBOX_STRICT
3438	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3439	&& uExitVector == X86_XCPT_PF)
3440	{
3441	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3442	}
3443	#endif
3444	if ( uExitVector == X86_XCPT_PF
3445	&& uIdtVector == X86_XCPT_PF)
3446	{
3447	pSvmTransient->fVectoringPF = true;
3448	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3449	}
3450	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3451	&& hmR0SvmIsContributoryXcpt(uExitVector)
3452	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3453	\|\| uIdtVector == X86_XCPT_PF))
3454	{
3455	enmReflect = SVMREFLECTXCPT_DF;
3456	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3457	uIdtVector, uExitVector));
3458	}
3459	else if (uIdtVector == X86_XCPT_DF)
3460	{
3461	enmReflect = SVMREFLECTXCPT_TF;
3462	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3463	uIdtVector, uExitVector));
3464	}
3465	else
3466	enmReflect = SVMREFLECTXCPT_XCPT;
3467	}
3468	else
3469	{
3470	/*
3471	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3472	* exception to the guest after handling the VM-exit.
3473	*/
3474	enmReflect = SVMREFLECTXCPT_XCPT;
3475	}
3476	}
3477	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3478	{
3479	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3480	enmReflect = SVMREFLECTXCPT_XCPT;
3481	}
3482
3483	switch (enmReflect)
3484	{
3485	case SVMREFLECTXCPT_XCPT:
3486	{
3487	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3488	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3489
3490	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3491	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3492	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3493	break;
3494	}
3495
3496	case SVMREFLECTXCPT_DF:
3497	{
3498	hmR0SvmSetPendingXcptDF(pVCpu);
3499	rc = VINF_HM_DOUBLE_FAULT;
3500	break;
3501	}
3502
3503	case SVMREFLECTXCPT_TF:
3504	{
3505	rc = VINF_EM_RESET;
3506	break;
3507	}
3508
3509	default:
3510	Assert(rc == VINF_SUCCESS);
3511	break;
3512	}
3513	}
3514	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3515	return rc;
3516	}
3517
3518
3519	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3520	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3521	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3522
3523	/** @name VM-exit handlers.
3524	* @{
3525	*/
3526
3527	/**
3528	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3529	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3530	*/
3531	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3532	{
3533	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3534
3535	#ifdef VBOX_WITH_STATISTICS
3536	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
3537	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmi);
3538	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
3539	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3540	#endif
3541
3542	/*
3543	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3544	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3545	* interrupt it is until the host actually take the interrupt.
3546	*
3547	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3548	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3549	*/
3550	return VINF_EM_RAW_INTERRUPT;
3551	}
3552
3553
3554	/**
3555	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3556	*/
3557	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3558	{
3559	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3560	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3561	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3562	return VINF_SUCCESS;
3563	}
3564
3565
3566	/**
3567	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3568	*/
3569	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3570	{
3571	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3572	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3573	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3574	return VINF_SUCCESS;
3575	}
3576
3577
3578	/**
3579	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3580	*/
3581	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3582	{
3583	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3584	PVM pVM = pVCpu->CTX_SUFF(pVM);
3585	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3586	if (RT_LIKELY(rc == VINF_SUCCESS))
3587	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3588	else
3589	{
3590	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3591	rc = VERR_EM_INTERPRETER;
3592	}
3593	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3594	return rc;
3595	}
3596
3597
3598	/**
3599	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3600	*/
3601	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3602	{
3603	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3604	PVM pVM = pVCpu->CTX_SUFF(pVM);
3605	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3606	if (RT_LIKELY(rc == VINF_SUCCESS))
3607	{
3608	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3609	pSvmTransient->fUpdateTscOffsetting = true;
3610	}
3611	else
3612	{
3613	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3614	rc = VERR_EM_INTERPRETER;
3615	}
3616	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3617	return rc;
3618	}
3619
3620
3621	/**
3622	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3623	*/
3624	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3625	{
3626	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3627	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3628	if (RT_LIKELY(rc == VINF_SUCCESS))
3629	{
3630	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3631	pSvmTransient->fUpdateTscOffsetting = true;
3632	}
3633	else
3634	{
3635	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3636	rc = VERR_EM_INTERPRETER;
3637	}
3638	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3639	return rc;
3640	}
3641
3642
3643	/**
3644	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3645	*/
3646	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3647	{
3648	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3649	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3650	if (RT_LIKELY(rc == VINF_SUCCESS))
3651	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3652	else
3653	{
3654	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3655	rc = VERR_EM_INTERPRETER;
3656	}
3657	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3658	return rc;
3659	}
3660
3661
3662	/**
3663	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3664	*/
3665	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3666	{
3667	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3668	PVM pVM = pVCpu->CTX_SUFF(pVM);
3669	Assert(!pVM->hm.s.fNestedPaging);
3670
3671	/** @todo Decode Assist. */
3672	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3673	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3674	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3675	return rc;
3676	}
3677
3678
3679	/**
3680	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3681	*/
3682	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3683	{
3684	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3685	pCtx->rip++; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3686	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3687	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3688	return rc;
3689	}
3690
3691
3692	/**
3693	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3694	*/
3695	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3696	{
3697	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3698	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3699	if (RT_LIKELY(rc == VINF_SUCCESS))
3700	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3701	else
3702	{
3703	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3704	rc = VERR_EM_INTERPRETER;
3705	}
3706	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3707	return rc;
3708	}
3709
3710
3711	/**
3712	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3713	*/
3714	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3715	{
3716	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3717	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3718	int rc = VBOXSTRICTRC_VAL(rc2);
3719	if ( rc == VINF_EM_HALT
3720	\|\| rc == VINF_SUCCESS)
3721	{
3722	pCtx->rip += 3; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3723
3724	if ( rc == VINF_EM_HALT
3725	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3726	{
3727	rc = VINF_SUCCESS;
3728	}
3729	}
3730	else
3731	{
3732	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3733	rc = VERR_EM_INTERPRETER;
3734	}
3735	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3736	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3737	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3738	return rc;
3739	}
3740
3741
3742	/**
3743	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
3744	* Conditional #VMEXIT.
3745	*/
3746	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3747	{
3748	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3749	return VINF_EM_RESET;
3750	}
3751
3752
3753	/**
3754	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
3755	*/
3756	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3757	{
3758	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3759
3760	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3761
3762	/** @todo Decode Assist. */
3763	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3764	int rc = VBOXSTRICTRC_VAL(rc2);
3765	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
3766	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
3767	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
3768	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
3769	return rc;
3770	}
3771
3772
3773	/**
3774	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
3775	*/
3776	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3777	{
3778	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3779	/** @todo Decode Assist. */
3780	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3781	int rc = VBOXSTRICTRC_VAL(rc2);
3782	if (rc == VINF_SUCCESS)
3783	{
3784	/* RIP has been updated by EMInterpretInstruction(). */
3785	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
3786	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
3787	{
3788	case 0: /* CR0. */
3789	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
3790	break;
3791
3792	case 3: /* CR3. */
3793	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
3794	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
3795	break;
3796
3797	case 4: /* CR4. */
3798	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
3799	break;
3800
3801	case 8: /* CR8 (TPR). */
3802	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3803	break;
3804
3805	default:
3806	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
3807	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
3808	break;
3809	}
3810	}
3811	else
3812	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
3813	return rc;
3814	}
3815
3816
3817	/**
3818	* #VMEXIT handler for instructions that result in a #UD exception delivered to
3819	* the guest.
3820	*/
3821	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3822	{
3823	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3824	hmR0SvmSetPendingXcptUD(pVCpu);
3825	return VINF_SUCCESS;
3826	}
3827
3828
3829	/**
3830	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
3831	*/
3832	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3833	{
3834	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3835	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3836	PVM pVM = pVCpu->CTX_SUFF(pVM);
3837
3838	/** @todo r=ramshankar: This cannot be right if prefixes are involved. When
3839	* NRIP_SAVE isn't available we have to disassemble the instruction. */
3840	int rc;
3841	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
3842	{
3843	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
3844
3845	/* Handle TPR patching; intercepted LSTAR write. */
3846	if ( pVM->hm.s.fTPRPatchingActive
3847	&& pCtx->ecx == MSR_K8_LSTAR)
3848	{
3849	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
3850	{
3851	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
3852	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
3853	AssertRC(rc2);
3854	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3855	}
3856	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3857	return VINF_SUCCESS;
3858	}
3859
3860	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3861	if (RT_LIKELY(rc == VINF_SUCCESS))
3862	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3863	else
3864	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
3865
3866	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
3867	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
3868	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
3869	{
3870	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
3871	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
3872	EMInterpretWrmsr() changes it. */
3873	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3874	}
3875	else if (pCtx->ecx == MSR_K6_EFER)
3876	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
3877	else if (pCtx->ecx == MSR_IA32_TSC)
3878	pSvmTransient->fUpdateTscOffsetting = true;
3879	}
3880	else
3881	{
3882	/* MSR Read access. */
3883	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
3884	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3885	if (RT_LIKELY(rc == VINF_SUCCESS))
3886	pCtx->rip += 2; /* Hardcoded opcode, AMD-V doesn't give us this information. */
3887	else
3888	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
3889	}
3890
3891	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
3892	return rc;
3893	}
3894
3895
3896	/**
3897	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
3898	*/
3899	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3900	{
3901	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3902	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
3903
3904	/* We should -not- get this VM-exit if the guest is debugging. */
3905	if (CPUMIsGuestDebugStateActive(pVCpu))
3906	{
3907	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx));
3908	return VERR_SVM_UNEXPECTED_EXIT;
3909	}
3910
3911	if ( !DBGFIsStepping(pVCpu)
3912	&& !CPUMIsHyperDebugStateActive(pVCpu))
3913	{
3914	/* Don't intercept DRx read and writes. */
3915	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3916	pVmcb->ctrl.u16InterceptRdDRx = 0;
3917	pVmcb->ctrl.u16InterceptWrDRx = 0;
3918	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3919
3920	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
3921	PVM pVM = pVCpu->CTX_SUFF(pVM);
3922	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3923	AssertRC(rc);
3924	Assert(CPUMIsGuestDebugStateActive(pVCpu));
3925
3926	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
3927	return rc;
3928	}
3929
3930	/** @todo Decode assist. */
3931	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3932	int rc = VBOXSTRICTRC_VAL(rc2);
3933	if (RT_LIKELY(rc == VINF_SUCCESS))
3934	{
3935	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
3936	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3937	}
3938	else
3939	Assert(rc == VERR_EM_INTERPRETER);
3940	return rc;
3941	}
3942
3943
3944	/**
3945	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
3946	*/
3947	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3948	{
3949	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3950	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
3951	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3952	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
3953	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
3954	return rc;
3955	}
3956
3957
3958	/**
3959	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
3960	*/
3961	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3962	{
3963	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3964
3965	/* I/O operation lookup arrays. */
3966	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
3967	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
3968	the result (in AL/AX/EAX). */
3969	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3970
3971	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3972	PVM pVM = pVCpu->CTX_SUFF(pVM);
3973
3974	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
3975	SVMIOIOEXIT IoExitInfo;
3976	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
3977	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
3978	uint32_t uIOSize = s_aIOSize[uIOWidth];
3979	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
3980
3981	if (RT_UNLIKELY(!uIOSize))
3982	{
3983	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
3984	return VERR_EM_INTERPRETER;
3985	}
3986
3987	int rc;
3988	if (IoExitInfo.n.u1STR)
3989	{
3990	/* INS/OUTS - I/O String instruction. */
3991	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
3992
3993	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
3994	* in EXITINFO1? Investigate once this thing is up and running. */
3995
3996	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
3997	if (rc == VINF_SUCCESS)
3998	{
3999	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4000	{
4001	VBOXSTRICTRC rc2 = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4002	(DISCPUMODE)pDis->uAddrMode, uIOSize);
4003	rc = VBOXSTRICTRC_VAL(rc2);
4004	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4005	}
4006	else
4007	{
4008	VBOXSTRICTRC rc2 = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4009	(DISCPUMODE)pDis->uAddrMode, uIOSize);
4010	rc = VBOXSTRICTRC_VAL(rc2);
4011	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4012	}
4013	}
4014	else
4015	rc = VINF_EM_RAW_EMULATE_INSTR;
4016	}
4017	else
4018	{
4019	/* IN/OUT - I/O instruction. */
4020	Assert(!IoExitInfo.n.u1REP);
4021
4022	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4023	{
4024	VBOXSTRICTRC rc2 = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
4025	rc = VBOXSTRICTRC_VAL(rc2);
4026	if (rc == VINF_IOM_R3_IOPORT_WRITE)
4027	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
4028
4029	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4030	}
4031	else
4032	{
4033	uint32_t u32Val = 0;
4034
4035	VBOXSTRICTRC rc2 = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, uIOSize);
4036	rc = VBOXSTRICTRC_VAL(rc2);
4037	if (IOM_SUCCESS(rc))
4038	{
4039	/* Save result of I/O IN instr. in AL/AX/EAX. */
4040	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4041	}
4042	else if (rc == VINF_IOM_R3_IOPORT_READ)
4043	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
4044
4045	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4046	}
4047	}
4048
4049	if (IOM_SUCCESS(rc))
4050	{
4051	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4052	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4053
4054	if (RT_LIKELY(rc == VINF_SUCCESS))
4055	{
4056	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
4057	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
4058	{
4059	/* I/O breakpoint length, in bytes. */
4060	static uint32_t const s_aIOBPLen[4] = { 1, 2, 0, 4 };
4061
4062	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4063	for (unsigned i = 0; i < 4; i++)
4064	{
4065	unsigned uBPLen = s_aIOBPLen[X86_DR7_GET_LEN(pCtx->dr[7], i)];
4066
4067	if ( IoExitInfo.n.u16Port >= pCtx->dr[i]
4068	&& IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen
4069	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
4070	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
4071	{
4072	Assert(CPUMIsGuestDebugStateActive(pVCpu));
4073
4074	/* Clear all breakpoint status flags and set the one we just hit. */
4075	pCtx->dr[6] &= ~(X86_DR6_B0 \| X86_DR6_B1 \| X86_DR6_B2 \| X86_DR6_B3);
4076	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
4077
4078	/*
4079	* Note: AMD64 Architecture Programmer's Manual 13.1:
4080	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
4081	* by software after the contents have been read.
4082	*/
4083	pVmcb->guest.u64DR6 = pCtx->dr[6];
4084
4085	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
4086	pCtx->dr[7] &= ~X86_DR7_GD;
4087
4088	/* Paranoia. */
4089	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
4090	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
4091	pCtx->dr[7] \|= 0x400; /* MB1. */
4092
4093	pVmcb->guest.u64DR7 = pCtx->dr[7];
4094	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4095
4096	/* Inject the debug exception. */
4097	hmR0SvmSetPendingXcptDB(pVCpu);
4098	break;
4099	}
4100	}
4101	}
4102	}
4103	}
4104
4105	#ifdef VBOX_STRICT
4106	if (rc == VINF_IOM_R3_IOPORT_READ)
4107	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4108	else if (rc == VINF_IOM_R3_IOPORT_WRITE)
4109	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4110	else
4111	{
4112	AssertMsg( RT_FAILURE(rc)
4113	\|\| rc == VINF_SUCCESS
4114	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
4115	\|\| rc == VINF_EM_RAW_GUEST_TRAP
4116	\|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
4117	}
4118	#endif
4119	return rc;
4120	}
4121
4122
4123	/**
4124	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4125	* #VMEXIT.
4126	*/
4127	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4128	{
4129	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4130	PVM pVM = pVCpu->CTX_SUFF(pVM);
4131	Assert(pVM->hm.s.fNestedPaging);
4132
4133	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4134
4135	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4136	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4137	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4138	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4139
4140	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4141
4142	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4143	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4144	if ( pVM->hm.s.fTRPPatchingAllowed
4145	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4146	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4147	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4148	&& !CPUMGetGuestCPL(pVCpu)
4149	&& !CPUMIsGuestInLongModeEx(pCtx)
4150	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4151	{
4152	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4153	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4154
4155	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4156	{
4157	/* Only attempt to patch the instruction once. */
4158	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4159	if (!pPatch)
4160	return VINF_EM_HM_PATCH_TPR_INSTR;
4161	}
4162	}
4163	#endif
4164
4165	/*
4166	* Determine the nested paging mode.
4167	*/
4168	PGMMODE enmNestedPagingMode;
4169	#if HC_ARCH_BITS == 32
4170	if (CPUMIsGuestInLongModeEx(pCtx))
4171	enmNestedPagingMode = PGMMODE_AMD64_NX;
4172	else
4173	#endif
4174	enmNestedPagingMode = PGMGetHostMode(pVM);
4175
4176	/*
4177	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4178	*/
4179	int rc;
4180	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4181	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4182	{
4183	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4184	u32ErrCode);
4185	rc = VBOXSTRICTRC_VAL(rc2);
4186
4187	/*
4188	* If we succeed, resume guest execution.
4189	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4190	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4191	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4192	* weird case. See @bugref{6043}.
4193	*/
4194	if ( rc == VINF_SUCCESS
4195	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4196	\|\| rc == VERR_PAGE_NOT_PRESENT)
4197	{
4198	/* Successfully handled MMIO operation. */
4199	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4200	rc = VINF_SUCCESS;
4201	}
4202	return rc;
4203	}
4204
4205	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4206	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4207	TRPMResetTrap(pVCpu);
4208
4209	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4210
4211	/*
4212	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4213	*/
4214	if ( rc == VINF_SUCCESS
4215	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4216	\|\| rc == VERR_PAGE_NOT_PRESENT)
4217	{
4218	/* We've successfully synced our shadow page tables. */
4219	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4220	rc = VINF_SUCCESS;
4221	}
4222
4223	return rc;
4224	}
4225
4226
4227	/**
4228	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4229	*/
4230	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4231	{
4232	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4233
4234	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4235	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4236	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4237
4238	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4239	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4240	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4241
4242	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4243	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4244	return VINF_SUCCESS;
4245	}
4246
4247
4248	/**
4249	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4250	*/
4251	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4252	{
4253	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4254
4255	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4256	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4257	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4258	&& pVCpu->hm.s.Event.fPending)
4259	{
4260	/*
4261	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4262	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4263	* when the recompiler restarts the instruction.
4264	*/
4265	SVMEVENT Event;
4266	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4267	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4268	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4269	{
4270	pVCpu->hm.s.Event.fPending = false;
4271	}
4272	else
4273	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4274	}
4275
4276	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4277	* emulation. */
4278	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4279	return VERR_EM_INTERPRETER;
4280	}
4281
4282
4283	/**
4284	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4285	*/
4286	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4287	{
4288	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4289
4290	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4291	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4292	hmR0SvmSetPendingXcptUD(pVCpu);
4293	return VINF_SUCCESS;
4294	}
4295
4296
4297	/**
4298	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4299	* #VMEXIT.
4300	*/
4301	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4302	{
4303	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4304
4305	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4306
4307	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4308	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4309	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4310	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4311
4312	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4313	if (pVM->hm.s.fNestedPaging)
4314	{
4315	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4316	if (!pSvmTransient->fVectoringPF)
4317	{
4318	/* A genuine guest #PF, reflect it to the guest. */
4319	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4320	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4321	uFaultAddress, u32ErrCode));
4322	}
4323	else
4324	{
4325	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4326	hmR0SvmSetPendingXcptDF(pVCpu);
4327	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4328	}
4329	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4330	return VINF_SUCCESS;
4331	}
4332	#endif
4333
4334	PVM pVM = pVCpu->CTX_SUFF(pVM);
4335	Assert(!pVM->hm.s.fNestedPaging);
4336
4337	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4338	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4339	if ( pVM->hm.s.fTRPPatchingAllowed
4340	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4341	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
4342	&& !CPUMGetGuestCPL(pVCpu)
4343	&& !CPUMIsGuestInLongModeEx(pCtx)
4344	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4345	{
4346	RTGCPHYS GCPhysApicBase;
4347	GCPhysApicBase = pCtx->msrApicBase;
4348	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4349
4350	/* Check if the page at the fault-address is the APIC base. */
4351	RTGCPHYS GCPhysPage;
4352	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4353	if ( rc2 == VINF_SUCCESS
4354	&& GCPhysPage == GCPhysApicBase)
4355	{
4356	/* Only attempt to patch the instruction once. */
4357	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4358	if (!pPatch)
4359	return VINF_EM_HM_PATCH_TPR_INSTR;
4360	}
4361	}
4362	#endif
4363
4364	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4365	pCtx->rip, u32ErrCode, pCtx->cr3));
4366
4367	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4368	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4369
4370	Log4(("#PF rc=%Rrc\n", rc));
4371
4372	if (rc == VINF_SUCCESS)
4373	{
4374	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4375	TRPMResetTrap(pVCpu);
4376	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4377	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4378	return rc;
4379	}
4380	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4381	{
4382	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4383
4384	if (!pSvmTransient->fVectoringPF)
4385	{
4386	/* It's a guest page fault and needs to be reflected to the guest. */
4387	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4388	TRPMResetTrap(pVCpu);
4389	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4390	}
4391	else
4392	{
4393	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4394	TRPMResetTrap(pVCpu);
4395	hmR0SvmSetPendingXcptDF(pVCpu);
4396	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4397	}
4398
4399	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4400	return VINF_SUCCESS;
4401	}
4402
4403	TRPMResetTrap(pVCpu);
4404	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4405	return rc;
4406	}
4407
4408
4409	/**
4410	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4411	* Conditional #VMEXIT.
4412	*/
4413	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4414	{
4415	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4416
4417	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4418
4419	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4420	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4421	#endif
4422
4423	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4424	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4425	if (rc == VINF_SUCCESS)
4426	{
4427	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4428	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4429	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4430	return VINF_SUCCESS;
4431	}
4432
4433	/* Forward #NM to the guest. */
4434	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4435	hmR0SvmSetPendingXcptNM(pVCpu);
4436	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4437	return VINF_SUCCESS;
4438	}
4439
4440
4441	/**
4442	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4443	* Conditional #VMEXIT.
4444	*/
4445	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4446	{
4447	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4448
4449	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4450
4451	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4452
4453	if (!(pCtx->cr0 & X86_CR0_NE))
4454	{
4455	/* Old-style FPU error reporting needs some extra work. */
4456	/** @todo don't fall back to the recompiler, but do it manually. */
4457	return VERR_EM_INTERPRETER;
4458	}
4459
4460	hmR0SvmSetPendingXcptMF(pVCpu);
4461	return VINF_SUCCESS;
4462	}
4463
4464
4465	/**
4466	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4467	* #VMEXIT.
4468	*/
4469	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4470	{
4471	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4472
4473	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4474
4475	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4476
4477	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4478	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4479	PVM pVM = pVCpu->CTX_SUFF(pVM);
4480	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
4481	if (rc == VINF_EM_RAW_GUEST_TRAP)
4482	{
4483	/* Reflect the exception back to the guest. */
4484	hmR0SvmSetPendingXcptDB(pVCpu);
4485	rc = VINF_SUCCESS;
4486	}
4487
4488	return rc;
4489	}
4490
4491	/** @} */
4492

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 47123

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