HMSVMR0.cpp@ 47652

Last change on this file since 47652 was 47652, checked in by vboxsync, 12 years ago
VMM: Removed all VBOX_WITH_OLD_[VTX\|AMDV]_CODE bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 174.3 KB

Line
1	/* $Id: HMSVMR0.cpp 47652 2013-08-09 14:56:17Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HMSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
38	#endif
39
40
41	/*******************************************************************************
42	* Defined Constants And Macros *
43	*******************************************************************************/
44	#ifdef VBOX_WITH_STATISTICS
45	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
46	if ((u64ExitCode) == SVM_EXIT_NPF) \
47	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
48	else \
49	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
50	} while (0)
51	#else
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
53	#endif
54
55	/** If we decide to use a function table approach this can be useful to
56	* switch to a "static DECLCALLBACK(int)". */
57	#define HMSVM_EXIT_DECL static int
58
59
60	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
61	*
62	* The CPU format of the segment attribute is described in X86DESCATTRBITS
63	* which is 16-bits (i.e. includes 4 bits of the segment limit).
64	*
65	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
66	* only the attribute bits and nothing else). Upper 4-bits are unused.
67	*
68	* @{ */
69	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
70	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
71	/** @} */
72
73
74	/** @name Macros for loading, storing segment registers to/from the VMCB.
75	* @{ */
76	#define HMSVM_LOAD_SEG_REG(REG, reg) \
77	do \
78	{ \
79	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
80	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
81	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
82	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
83	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
84	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
85	} while (0)
86
87	#define HMSVM_SAVE_SEG_REG(REG, reg) \
88	do \
89	{ \
90	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
92	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
93	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
94	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
95	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
96	} while (0)
97	/** @} */
98
99
100	/** @name Macro for checking and returning from the using function for
101	* #VMEXIT intercepts that maybe caused during delivering of another
102	* event in the guest. */
103	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
104	do \
105	{ \
106	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
107	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
108	return VINF_SUCCESS; \
109	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
110	return rc; \
111	} while (0)
112	/** @} */
113
114
115	/**
116	* @name Exception bitmap mask for all contributory exceptions.
117	*
118	* Page fault is deliberately excluded here as it's conditional as to whether
119	* it's contributory or benign. Page faults are handled separately.
120	*/
121	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
122	\| RT_BIT(X86_XCPT_DE))
123	/** @} */
124
125
126	/** @name VMCB Clean Bits.
127	*
128	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
129	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
130	* memory.
131	*
132	* @{ */
133	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
134	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
135	/** I/O permission bitmap, MSR permission bitmap. */
136	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
137	/** ASID. */
138	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
139	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
140	V_INTR_VECTOR. */
141	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
142	/** Nested Paging: Nested CR3 (nCR3), PAT. */
143	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
144	/** Control registers (CR0, CR3, CR4, EFER). */
145	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
146	/** Debug registers (DR6, DR7). */
147	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
148	/** GDT, IDT limit and base. */
149	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
150	/** Segment register: CS, SS, DS, ES limit and base. */
151	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
152	/** CR2.*/
153	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
154	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
155	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
156	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
157	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
158	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
159	/** Mask of all valid VMCB Clean bits. */
160	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
161	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
162	\| HMSVM_VMCB_CLEAN_ASID \
163	\| HMSVM_VMCB_CLEAN_TPR \
164	\| HMSVM_VMCB_CLEAN_NP \
165	\| HMSVM_VMCB_CLEAN_CRX_EFER \
166	\| HMSVM_VMCB_CLEAN_DRX \
167	\| HMSVM_VMCB_CLEAN_DT \
168	\| HMSVM_VMCB_CLEAN_SEG \
169	\| HMSVM_VMCB_CLEAN_CR2 \
170	\| HMSVM_VMCB_CLEAN_LBR \
171	\| HMSVM_VMCB_CLEAN_AVIC)
172	/** @} */
173
174	/** @name SVM transient.
175	*
176	* A state structure for holding miscellaneous information across AMD-V
177	* VMRUN/#VMEXIT operation, restored after the transition.
178	*
179	* @{ */
180	typedef struct SVMTRANSIENT
181	{
182	/** The host's rflags/eflags. */
183	RTCCUINTREG uEFlags;
184	#if HC_ARCH_BITS == 32
185	uint32_t u32Alignment0;
186	#endif
187
188	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
189	uint64_t u64ExitCode;
190	/** The guest's TPR value used for TPR shadowing. */
191	uint8_t u8GuestTpr;
192	/** Alignment. */
193	uint8_t abAlignment0[7];
194
195	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
196	bool fRestoreTscAuxMsr;
197	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
198	* contributary exception or a page-fault. */
199	bool fVectoringPF;
200	/** Whether the TSC offset mode needs to be updated. */
201	bool fUpdateTscOffsetting;
202	} SVMTRANSIENT, *PSVMTRANSIENT;
203	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
204	AssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
205	/** @} */
206
207
208	/**
209	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
210	*/
211	typedef enum SVMMSREXITREAD
212	{
213	/** Reading this MSR causes a VM-exit. */
214	SVMMSREXIT_INTERCEPT_READ = 0xb,
215	/** Reading this MSR does not cause a VM-exit. */
216	SVMMSREXIT_PASSTHRU_READ
217	} SVMMSREXITREAD;
218
219	/**
220	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
221	*/
222	typedef enum SVMMSREXITWRITE
223	{
224	/** Writing to this MSR causes a VM-exit. */
225	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
226	/** Writing to this MSR does not cause a VM-exit. */
227	SVMMSREXIT_PASSTHRU_WRITE
228	} SVMMSREXITWRITE;
229
230
231	/*******************************************************************************
232	* Internal Functions *
233	*******************************************************************************/
234	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
235	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
236
237	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
238	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
239	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
240	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
241	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
242	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
243	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
244	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
245	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
246	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
247	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
248	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
249	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
250	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
251	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
252	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
253	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
257	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
258	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
259	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
263	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
264
265	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
266
267
268	/*******************************************************************************
269	* Global Variables *
270	*******************************************************************************/
271	/** Ring-0 memory object for the IO bitmap. */
272	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
273	/** Physical address of the IO bitmap. */
274	RTHCPHYS g_HCPhysIOBitmap = 0;
275	/** Virtual address of the IO bitmap. */
276	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
277
278
279	/**
280	* Sets up and activates AMD-V on the current CPU.
281	*
282	* @returns VBox status code.
283	* @param pCpu Pointer to the CPU info struct.
284	* @param pVM Pointer to the VM (can be NULL after a resume!).
285	* @param pvCpuPage Pointer to the global CPU page.
286	* @param HCPhysCpuPage Physical address of the global CPU page.
287	*/
288	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
289	{
290	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
291	AssertReturn( HCPhysCpuPage
292	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
293	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
294
295	/*
296	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
297	*/
298	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
299	if (u64HostEfer & MSR_K6_EFER_SVME)
300	{
301	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
302	if ( pVM
303	&& pVM->hm.s.svm.fIgnoreInUseError)
304	{
305	pCpu->fIgnoreAMDVInUseError = true;
306	}
307
308	if (!pCpu->fIgnoreAMDVInUseError)
309	return VERR_SVM_IN_USE;
310	}
311
312	/* Turn on AMD-V in the EFER MSR. */
313	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
314
315	/* Write the physical page address where the CPU will store the host state while executing the VM. */
316	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
317
318	/*
319	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
320	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
321	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
322	* to flush the TLB with before using a new ASID.
323	*/
324	pCpu->fFlushAsidBeforeUse = true;
325
326	/*
327	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
328	*/
329	++pCpu->cTlbFlushes;
330
331	return VINF_SUCCESS;
332	}
333
334
335	/**
336	* Deactivates AMD-V on the current CPU.
337	*
338	* @returns VBox status code.
339	* @param pCpu Pointer to the CPU info struct.
340	* @param pvCpuPage Pointer to the global CPU page.
341	* @param HCPhysCpuPage Physical address of the global CPU page.
342	*/
343	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
344	{
345	AssertReturn( HCPhysCpuPage
346	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
347	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
348	NOREF(pCpu);
349
350	/* Turn off AMD-V in the EFER MSR. */
351	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
352	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
353
354	/* Invalidate host state physical address. */
355	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
356
357	return VINF_SUCCESS;
358	}
359
360
361	/**
362	* Does global AMD-V initialization (called during module initialization).
363	*
364	* @returns VBox status code.
365	*/
366	VMMR0DECL(int) SVMR0GlobalInit(void)
367	{
368	/*
369	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
370	* once globally here instead of per-VM.
371	*/
372	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
373	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
374	if (RT_FAILURE(rc))
375	return rc;
376
377	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
378	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
379
380	/* Set all bits to intercept all IO accesses. */
381	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
382	return VINF_SUCCESS;
383	}
384
385
386	/**
387	* Does global AMD-V termination (called during module termination).
388	*/
389	VMMR0DECL(void) SVMR0GlobalTerm(void)
390	{
391	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
392	{
393	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
394	g_pvIOBitmap = NULL;
395	g_HCPhysIOBitmap = 0;
396	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
397	}
398	}
399
400
401	/**
402	* Frees any allocated per-VCPU structures for a VM.
403	*
404	* @param pVM Pointer to the VM.
405	*/
406	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
407	{
408	for (uint32_t i = 0; i < pVM->cCpus; i++)
409	{
410	PVMCPU pVCpu = &pVM->aCpus[i];
411	AssertPtr(pVCpu);
412
413	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
414	{
415	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
416	pVCpu->hm.s.svm.pvVmcbHost = 0;
417	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
418	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
419	}
420
421	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
422	{
423	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
424	pVCpu->hm.s.svm.pvVmcb = 0;
425	pVCpu->hm.s.svm.HCPhysVmcb = 0;
426	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
427	}
428
429	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
430	{
431	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
432	pVCpu->hm.s.svm.pvMsrBitmap = 0;
433	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
434	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
435	}
436	}
437	}
438
439
440	/**
441	* Does per-VM AMD-V initialization.
442	*
443	* @returns VBox status code.
444	* @param pVM Pointer to the VM.
445	*/
446	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
447	{
448	int rc = VERR_INTERNAL_ERROR_5;
449
450	/*
451	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
452	*/
453	uint32_t u32Family;
454	uint32_t u32Model;
455	uint32_t u32Stepping;
456	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
457	{
458	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
459	pVM->hm.s.svm.fAlwaysFlushTLB = true;
460	}
461
462	/*
463	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
464	*/
465	for (VMCPUID i = 0; i < pVM->cCpus; i++)
466	{
467	PVMCPU pVCpu = &pVM->aCpus[i];
468	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
469	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
470	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
471	}
472
473	for (VMCPUID i = 0; i < pVM->cCpus; i++)
474	{
475	PVMCPU pVCpu = &pVM->aCpus[i];
476
477	/*
478	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
479	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
480	*/
481	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
482	if (RT_FAILURE(rc))
483	goto failure_cleanup;
484
485	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
486	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
487	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
488	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
489
490	/*
491	* Allocate one page for the guest-state VMCB.
492	*/
493	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
494	if (RT_FAILURE(rc))
495	goto failure_cleanup;
496
497	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
498	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
499	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
500	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
501
502	/*
503	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
504	* SVM to not require one.
505	*/
506	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
507	if (RT_FAILURE(rc))
508	goto failure_cleanup;
509
510	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
511	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
512	/* Set all bits to intercept all MSR accesses (changed later on). */
513	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
514	}
515
516	return VINF_SUCCESS;
517
518	failure_cleanup:
519	hmR0SvmFreeStructs(pVM);
520	return rc;
521	}
522
523
524	/**
525	* Does per-VM AMD-V termination.
526	*
527	* @returns VBox status code.
528	* @param pVM Pointer to the VM.
529	*/
530	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
531	{
532	hmR0SvmFreeStructs(pVM);
533	return VINF_SUCCESS;
534	}
535
536
537	/**
538	* Sets the permission bits for the specified MSR in the MSRPM.
539	*
540	* @param pVCpu Pointer to the VMCPU.
541	* @param uMsr The MSR for which the access permissions are being set.
542	* @param enmRead MSR read permissions.
543	* @param enmWrite MSR write permissions.
544	*/
545	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
546	{
547	unsigned ulBit;
548	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
549
550	/*
551	* Layout:
552	* Byte offset MSR range
553	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
554	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
555	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
556	* 0x1800 - 0x1fff Reserved
557	*/
558	if (uMsr <= 0x00001FFF)
559	{
560	/* Pentium-compatible MSRs. */
561	ulBit = uMsr * 2;
562	}
563	else if ( uMsr >= 0xC0000000
564	&& uMsr <= 0xC0001FFF)
565	{
566	/* AMD Sixth Generation x86 Processor MSRs. */
567	ulBit = (uMsr - 0xC0000000) * 2;
568	pbMsrBitmap += 0x800;
569	}
570	else if ( uMsr >= 0xC0010000
571	&& uMsr <= 0xC0011FFF)
572	{
573	/* AMD Seventh and Eighth Generation Processor MSRs. */
574	ulBit = (uMsr - 0xC0001000) * 2;
575	pbMsrBitmap += 0x1000;
576	}
577	else
578	{
579	AssertFailed();
580	return;
581	}
582
583	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
584	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
585	ASMBitSet(pbMsrBitmap, ulBit);
586	else
587	ASMBitClear(pbMsrBitmap, ulBit);
588
589	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
590	ASMBitSet(pbMsrBitmap, ulBit + 1);
591	else
592	ASMBitClear(pbMsrBitmap, ulBit + 1);
593
594	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
595	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
596	}
597
598
599	/**
600	* Sets up AMD-V for the specified VM.
601	* This function is only called once per-VM during initalization.
602	*
603	* @returns VBox status code.
604	* @param pVM Pointer to the VM.
605	*/
606	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
607	{
608	int rc = VINF_SUCCESS;
609
610	AssertReturn(pVM, VERR_INVALID_PARAMETER);
611	Assert(pVM->hm.s.svm.fSupported);
612
613	for (VMCPUID i = 0; i < pVM->cCpus; i++)
614	{
615	PVMCPU pVCpu = &pVM->aCpus[i];
616	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
617
618	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
619
620	/* Trap exceptions unconditionally (debug purposes). */
621	#ifdef HMSVM_ALWAYS_TRAP_PF
622	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
623	#endif
624	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
625	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
626	pVmcb->ctrl.u32InterceptException \|= 0
627	\| RT_BIT(X86_XCPT_BP)
628	\| RT_BIT(X86_XCPT_DB)
629	\| RT_BIT(X86_XCPT_DE)
630	\| RT_BIT(X86_XCPT_NM)
631	\| RT_BIT(X86_XCPT_UD)
632	\| RT_BIT(X86_XCPT_NP)
633	\| RT_BIT(X86_XCPT_SS)
634	\| RT_BIT(X86_XCPT_GP)
635	\| RT_BIT(X86_XCPT_PF)
636	\| RT_BIT(X86_XCPT_MF)
637	;
638	#endif
639
640	/* Set up unconditional intercepts and conditions. */
641	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
642	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
643	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
644	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
645	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
646	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
647	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
648	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
649	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
650	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
651	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
652	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
653
654	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
655	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
656	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
657	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
658	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
659	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
660	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
661	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
662	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
663	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
664
665	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
666	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
667
668	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
669	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
670
671	/* Intercept all DRx reads and writes by default. Changed later on. */
672	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
673	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
674
675	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
676	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
677
678	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
679	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
680	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
681
682	/* Set IO and MSR bitmap permission bitmap physical addresses. */
683	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
684	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
685
686	/* No LBR virtualization. */
687	pVmcb->ctrl.u64LBRVirt = 0;
688
689	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
690	pVmcb->ctrl.u64VmcbCleanBits = 0;
691
692	/* The host ASID MBZ, for the guest start with 1. */
693	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
694
695	/*
696	* Setup the PAT MSR (applicable for Nested Paging only).
697	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
698	* so choose type 6 for all PAT slots.
699	*/
700	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
701
702	/* Without Nested Paging, we need additionally intercepts. */
703	if (!pVM->hm.s.fNestedPaging)
704	{
705	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
706	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
707	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
708
709	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
710	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
711	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
712
713	/* Page faults must be intercepted to implement shadow paging. */
714	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
715	}
716
717	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
718	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
719	#endif
720
721	/*
722	* The following MSRs are saved/restored automatically during the world-switch.
723	* Don't intercept guest read/write accesses to these MSRs.
724	*/
725	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
726	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
727	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
728	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
729	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
730	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
731	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
732	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
733	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
734	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
735	}
736
737	return rc;
738	}
739
740
741	/**
742	* Invalidates a guest page by guest virtual address.
743	*
744	* @returns VBox status code.
745	* @param pVM Pointer to the VM.
746	* @param pVCpu Pointer to the VMCPU.
747	* @param GCVirt Guest virtual address of the page to invalidate.
748	*/
749	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
750	{
751	AssertReturn(pVM, VERR_INVALID_PARAMETER);
752	Assert(pVM->hm.s.svm.fSupported);
753
754	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
755
756	/* Skip it if a TLB flush is already pending. */
757	if (!fFlushPending)
758	{
759	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
760
761	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
762	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
763
764	#if HC_ARCH_BITS == 32
765	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
766	if (CPUMIsGuestInLongMode(pVCpu))
767	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
768	else
769	#endif
770	{
771	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
772	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
773	}
774	}
775	return VINF_SUCCESS;
776	}
777
778
779	/**
780	* Flushes the appropriate tagged-TLB entries.
781	*
782	* @param pVM Pointer to the VM.
783	* @param pVCpu Pointer to the VMCPU.
784	*/
785	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
786	{
787	PVM pVM = pVCpu->CTX_SUFF(pVM);
788	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
789	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
790
791	/*
792	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
793	* This can happen both for start & resume due to long jumps back to ring-3.
794	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
795	* so we cannot reuse the ASIDs without flushing.
796	*/
797	bool fNewAsid = false;
798	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
799	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
800	{
801	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
802	pVCpu->hm.s.fForceTLBFlush = true;
803	fNewAsid = true;
804	}
805
806	/* Set TLB flush state as checked until we return from the world switch. */
807	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
808
809	/* Check for explicit TLB shootdowns. */
810	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
811	{
812	pVCpu->hm.s.fForceTLBFlush = true;
813	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
814	}
815
816	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
817	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
818
819	if (pVM->hm.s.svm.fAlwaysFlushTLB)
820	{
821	/*
822	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
823	*/
824	pCpu->uCurrentAsid = 1;
825	pVCpu->hm.s.uCurrentAsid = 1;
826	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
827	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
828	}
829	else if (pVCpu->hm.s.fForceTLBFlush)
830	{
831	if (fNewAsid)
832	{
833	++pCpu->uCurrentAsid;
834	bool fHitASIDLimit = false;
835	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
836	{
837	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
838	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
839	fHitASIDLimit = true;
840
841	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
842	{
843	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
844	pCpu->fFlushAsidBeforeUse = true;
845	}
846	else
847	{
848	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
849	pCpu->fFlushAsidBeforeUse = false;
850	}
851	}
852
853	if ( !fHitASIDLimit
854	&& pCpu->fFlushAsidBeforeUse)
855	{
856	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
857	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
858	else
859	{
860	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
861	pCpu->fFlushAsidBeforeUse = false;
862	}
863	}
864
865	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
866	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
867	}
868	else
869	{
870	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
871	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
872	else
873	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
874	}
875
876	pVCpu->hm.s.fForceTLBFlush = false;
877	}
878	else
879	{
880	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
881	* not be executed. See hmQueueInvlPage() where it is commented
882	* out. Support individual entry flushing someday. */
883	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
884	{
885	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
886	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
887	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
888	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
889	}
890	}
891
892	pVCpu->hm.s.TlbShootdown.cPages = 0;
893	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
894
895	/* Update VMCB with the ASID. */
896	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
897	{
898	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
899	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
900	}
901
902	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
903	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
904	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
905	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
906	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
907	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
908
909	#ifdef VBOX_WITH_STATISTICS
910	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
911	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
912	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
913	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
914	{
915	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
916	}
917	else
918	{
919	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
920	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
921	}
922	#endif
923	}
924
925
926	/** @name 64-bit guest on 32-bit host OS helper functions.
927	*
928	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
929	* mode (code segment, paging). These wrappers/helpers perform the necessary
930	* bits for the 32->64 switcher.
931	*
932	* @{ */
933	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
934	/**
935	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
936	*
937	* @returns VBox status code.
938	* @param HCPhysVmcbHost Physical address of host VMCB.
939	* @param HCPhysVmcb Physical address of the VMCB.
940	* @param pCtx Pointer to the guest-CPU context.
941	* @param pVM Pointer to the VM.
942	* @param pVCpu Pointer to the VMCPU.
943	*/
944	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
945	{
946	uint32_t aParam[4];
947	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
948	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
949	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
950	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
951
952	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
953	}
954
955
956	/**
957	* Executes the specified VMRUN handler in 64-bit mode.
958	*
959	* @returns VBox status code.
960	* @param pVM Pointer to the VM.
961	* @param pVCpu Pointer to the VMCPU.
962	* @param pCtx Pointer to the guest-CPU context.
963	* @param enmOp The operation to perform.
964	* @param cbParam Number of parameters.
965	* @param paParam Array of 32-bit parameters.
966	*/
967	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
968	uint32_t *paParam)
969	{
970	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
971	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
972
973	/* Disable interrupts. */
974	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
975
976	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
977	RTCPUID idHostCpu = RTMpCpuId();
978	CPUMR0SetLApic(pVM, idHostCpu);
979	#endif
980
981	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
982	CPUMSetHyperEIP(pVCpu, enmOp);
983	for (int i = (int)cbParam - 1; i >= 0; i--)
984	CPUMPushHyper(pVCpu, paParam[i]);
985
986	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
987	/* Call the switcher. */
988	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
989	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
990
991	/* Restore interrupts. */
992	ASMSetFlags(uOldEFlags);
993	return rc;
994	}
995
996	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
997	/** @} */
998
999
1000	/**
1001	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1002	* the corresponding VMCB Clean Bit.
1003	*
1004	* @param pVmcb Pointer to the VMCB.
1005	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1006	*/
1007	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1008	{
1009	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1010	{
1011	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1012	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1013	}
1014	}
1015
1016
1017	/**
1018	* Removes an exception from the intercept-exception bitmap in the VMCB and
1019	* updates the corresponding VMCB Clean Bit.
1020	*
1021	* @param pVmcb Pointer to the VMCB.
1022	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1023	*/
1024	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1025	{
1026	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1027	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1028	{
1029	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1030	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1031	}
1032	#endif
1033	}
1034
1035
1036	/**
1037	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1038	*
1039	* @returns VBox status code.
1040	* @param pVCpu Pointer to the VMCPU.
1041	* @param pVmcb Pointer to the VMCB.
1042	* @param pCtx Pointer the guest-CPU context.
1043	*
1044	* @remarks No-long-jump zone!!!
1045	*/
1046	DECLINLINE(int) hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1047	{
1048	/*
1049	* Guest CR0.
1050	*/
1051	PVM pVM = pVCpu->CTX_SUFF(pVM);
1052	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1053	{
1054	uint64_t u64GuestCR0 = pCtx->cr0;
1055
1056	/* Always enable caching. */
1057	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1058
1059	/*
1060	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1061	*/
1062	if (!pVM->hm.s.fNestedPaging)
1063	{
1064	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1065	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1066	}
1067
1068	/*
1069	* Guest FPU bits.
1070	*/
1071	bool fInterceptNM = false;
1072	bool fInterceptMF = false;
1073	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1074	if (CPUMIsGuestFPUStateActive(pVCpu))
1075	{
1076	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1077	if (!(u64GuestCR0 & X86_CR0_NE))
1078	{
1079	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1080	fInterceptMF = true;
1081	}
1082	}
1083	else
1084	{
1085	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1086	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1087	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1088	}
1089
1090	/*
1091	* Update the exception intercept bitmap.
1092	*/
1093	if (fInterceptNM)
1094	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1095	else
1096	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1097
1098	if (fInterceptMF)
1099	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1100	else
1101	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1102
1103	pVmcb->guest.u64CR0 = u64GuestCR0;
1104	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1105	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1106	}
1107
1108	/*
1109	* Guest CR2.
1110	*/
1111	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1112	{
1113	pVmcb->guest.u64CR2 = pCtx->cr2;
1114	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1115	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1116	}
1117
1118	/*
1119	* Guest CR3.
1120	*/
1121	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1122	{
1123	if (pVM->hm.s.fNestedPaging)
1124	{
1125	PGMMODE enmShwPagingMode;
1126	#if HC_ARCH_BITS == 32
1127	if (CPUMIsGuestInLongModeEx(pCtx))
1128	enmShwPagingMode = PGMMODE_AMD64_NX;
1129	else
1130	#endif
1131	enmShwPagingMode = PGMGetHostMode(pVM);
1132
1133	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1134	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1135	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1136	pVmcb->guest.u64CR3 = pCtx->cr3;
1137	}
1138	else
1139	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1140
1141	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1142	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1143	}
1144
1145	/*
1146	* Guest CR4.
1147	*/
1148	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1149	{
1150	uint64_t u64GuestCR4 = pCtx->cr4;
1151	if (!pVM->hm.s.fNestedPaging)
1152	{
1153	switch (pVCpu->hm.s.enmShadowMode)
1154	{
1155	case PGMMODE_REAL:
1156	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1157	AssertFailed();
1158	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1159
1160	case PGMMODE_32_BIT: /* 32-bit paging. */
1161	u64GuestCR4 &= ~X86_CR4_PAE;
1162	break;
1163
1164	case PGMMODE_PAE: /* PAE paging. */
1165	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1166	/** Must use PAE paging as we could use physical memory > 4 GB */
1167	u64GuestCR4 \|= X86_CR4_PAE;
1168	break;
1169
1170	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1171	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1172	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1173	break;
1174	#else
1175	AssertFailed();
1176	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1177	#endif
1178
1179	default: /* shut up gcc */
1180	AssertFailed();
1181	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1182	}
1183	}
1184
1185	pVmcb->guest.u64CR4 = u64GuestCR4;
1186	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1187	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1188	}
1189
1190	return VINF_SUCCESS;
1191	}
1192
1193
1194	/**
1195	* Loads the guest segment registers into the VMCB.
1196	*
1197	* @returns VBox status code.
1198	* @param pVCpu Pointer to the VMCPU.
1199	* @param pVmcb Pointer to the VMCB.
1200	* @param pCtx Pointer to the guest-CPU context.
1201	*
1202	* @remarks No-long-jump zone!!!
1203	*/
1204	DECLINLINE(void) hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1205	{
1206	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1207	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1208	{
1209	HMSVM_LOAD_SEG_REG(CS, cs);
1210	HMSVM_LOAD_SEG_REG(SS, ss);
1211	HMSVM_LOAD_SEG_REG(DS, ds);
1212	HMSVM_LOAD_SEG_REG(ES, es);
1213	HMSVM_LOAD_SEG_REG(FS, fs);
1214	HMSVM_LOAD_SEG_REG(GS, gs);
1215
1216	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1217	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1218	}
1219
1220	/* Guest TR. */
1221	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1222	{
1223	HMSVM_LOAD_SEG_REG(TR, tr);
1224	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1225	}
1226
1227	/* Guest LDTR. */
1228	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1229	{
1230	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1231	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1232	}
1233
1234	/* Guest GDTR. */
1235	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1236	{
1237	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1238	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1239	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1240	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1241	}
1242
1243	/* Guest IDTR. */
1244	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1245	{
1246	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1247	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1248	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1249	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1250	}
1251	}
1252
1253
1254	/**
1255	* Loads the guest MSRs into the VMCB.
1256	*
1257	* @param pVCpu Pointer to the VMCPU.
1258	* @param pVmcb Pointer to the VMCB.
1259	* @param pCtx Pointer to the guest-CPU context.
1260	*
1261	* @remarks No-long-jump zone!!!
1262	*/
1263	DECLINLINE(void) hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1264	{
1265	/* Guest Sysenter MSRs. */
1266	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1267	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1268	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1269
1270	/*
1271	* Guest EFER MSR.
1272	* AMD-V requires guest EFER.SVME to be set. Weird. .
1273	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1274	*/
1275	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1276	{
1277	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1278	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1279	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1280	}
1281
1282	/* 64-bit MSRs. */
1283	if (CPUMIsGuestInLongModeEx(pCtx))
1284	{
1285	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1286	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1287	}
1288	else
1289	{
1290	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1291	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1292	{
1293	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1294	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1295	}
1296	}
1297
1298
1299	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1300	* be writable in 32-bit mode. Clarify with AMD spec. */
1301	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1302	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1303	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1304	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1305	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1306	}
1307
1308
1309	/**
1310	* Loads the guest debug registers into the VMCB.
1311	*
1312	* @param pVCpu Pointer to the VMCPU.
1313	* @param pVmcb Pointer to the VMCB.
1314	* @param pCtx Pointer to the guest-CPU context.
1315	*
1316	* @remarks No-long-jump zone!!!
1317	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1318	*/
1319	DECLINLINE(void) hmR0SvmLoadGuestDebugRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1320	{
1321	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1322	return;
1323
1324	/** @todo Turn these into assertions if possible. */
1325	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* Set reserved bits to 1. */
1326	pCtx->dr[6] &= ~RT_BIT(12); /* MBZ. */
1327
1328	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
1329	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
1330	pCtx->dr[7] \|= X86_DR7_INIT_VAL; /* MB1. */
1331
1332	/* Update DR6, DR7 with the guest values. */
1333	pVmcb->guest.u64DR7 = pCtx->dr[7];
1334	pVmcb->guest.u64DR6 = pCtx->dr[6];
1335	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1336
1337	bool fInterceptDB = false;
1338	bool fInterceptMovDRx = false;
1339	if (DBGFIsStepping(pVCpu))
1340	{
1341	/* AMD-V doesn't have any monitor-trap flag equivalent. Instead, enable tracing in the guest and trap #DB. */
1342	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1343	fInterceptDB = true;
1344	}
1345
1346	PVM pVM = pVCpu->CTX_SUFF(pVM);
1347	if (CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1348	{
1349	if (!CPUMIsHyperDebugStateActive(pVCpu))
1350	{
1351	int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1352	AssertRC(rc);
1353
1354	/* Update DR6, DR7 with the hypervisor values. */
1355	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1356	pVmcb->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
1357	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1358	}
1359	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1360	fInterceptMovDRx = true;
1361	}
1362	else if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
1363	{
1364	if (!CPUMIsGuestDebugStateActive(pVCpu))
1365	{
1366	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1367	AssertRC(rc);
1368	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1369	}
1370	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1371	Assert(fInterceptMovDRx == false);
1372	}
1373	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1374	{
1375	/* For the first time we would need to intercept MOV DRx accesses even when the guest debug registers aren't loaded. */
1376	fInterceptMovDRx = true;
1377	}
1378
1379	if (fInterceptDB)
1380	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1381	else
1382	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1383
1384	if (fInterceptMovDRx)
1385	{
1386	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1387	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1388	{
1389	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1390	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1391	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1392	}
1393	}
1394	else
1395	{
1396	if ( pVmcb->ctrl.u16InterceptRdDRx
1397	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1398	{
1399	pVmcb->ctrl.u16InterceptRdDRx = 0;
1400	pVmcb->ctrl.u16InterceptWrDRx = 0;
1401	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1402	}
1403	}
1404
1405	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1406	}
1407
1408
1409	/**
1410	* Loads the guest APIC state (currently just the TPR).
1411	*
1412	* @returns VBox status code.
1413	* @param pVCpu Pointer to the VMCPU.
1414	* @param pVmcb Pointer to the VMCB.
1415	* @param pCtx Pointer to the guest-CPU context.
1416	*/
1417	DECLINLINE(int) hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1418	{
1419	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1420	return VINF_SUCCESS;
1421
1422	bool fPendingIntr;
1423	uint8_t u8Tpr;
1424	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1425	AssertRCReturn(rc, rc);
1426
1427	/** Assume that we need to trap all TPR accesses and thus need not check on
1428	* every #VMEXIT if we should update the TPR. */
1429	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1430	pVCpu->hm.s.svm.fSyncVTpr = false;
1431
1432	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1433	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1434	{
1435	pCtx->msrLSTAR = u8Tpr;
1436
1437	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1438	if (fPendingIntr)
1439	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1440	else
1441	{
1442	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1443	pVCpu->hm.s.svm.fSyncVTpr = true;
1444	}
1445	}
1446	else
1447	{
1448	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1449	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1450
1451	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1452	if (fPendingIntr)
1453	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1454	else
1455	{
1456	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1457	pVCpu->hm.s.svm.fSyncVTpr = true;
1458	}
1459
1460	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1461	}
1462
1463	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1464	return rc;
1465	}
1466
1467
1468	/**
1469	* Sets up the appropriate function to run guest code.
1470	*
1471	* @returns VBox status code.
1472	* @param pVCpu Pointer to the VMCPU.
1473	* @param pCtx Pointer to the guest-CPU context.
1474	*
1475	* @remarks No-long-jump zone!!!
1476	*/
1477	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1478	{
1479	if (CPUMIsGuestInLongModeEx(pCtx))
1480	{
1481	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1482	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1483	#endif
1484	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1485	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1486	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1487	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1488	#else
1489	/* 64-bit host or hybrid host. */
1490	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1491	#endif
1492	}
1493	else
1494	{
1495	/* Guest is not in long mode, use the 32-bit handler. */
1496	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1497	}
1498	return VINF_SUCCESS;
1499	}
1500
1501
1502	/**
1503	* Enters the AMD-V session.
1504	*
1505	* @returns VBox status code.
1506	* @param pVM Pointer to the VM.
1507	* @param pVCpu Pointer to the VMCPU.
1508	* @param pCpu Pointer to the CPU info struct.
1509	*/
1510	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
1511	{
1512	AssertPtr(pVM);
1513	AssertPtr(pVCpu);
1514	Assert(pVM->hm.s.svm.fSupported);
1515	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1516	NOREF(pCpu);
1517
1518	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1519
1520	/* Nothing to do here. */
1521	return VINF_SUCCESS;
1522	}
1523
1524
1525	/**
1526	* Leaves the AMD-V session.
1527	*
1528	* @returns VBox status code.
1529	* @param pVM Pointer to the VM.
1530	* @param pVCpu Pointer to the VMCPU.
1531	* @param pCtx Pointer to the guest-CPU context.
1532	*/
1533	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1534	{
1535	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1536	NOREF(pVM);
1537	NOREF(pVCpu);
1538	NOREF(pCtx);
1539
1540	/* Nothing to do here. Everything is taken care of in hmR0SvmLongJmpToRing3(). */
1541	return VINF_SUCCESS;
1542	}
1543
1544
1545	/**
1546	* Saves the host state.
1547	*
1548	* @returns VBox status code.
1549	* @param pVM Pointer to the VM.
1550	* @param pVCpu Pointer to the VMCPU.
1551	*
1552	* @remarks No-long-jump zone!!!
1553	*/
1554	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1555	{
1556	NOREF(pVM);
1557	NOREF(pVCpu);
1558	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1559	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1560	return VINF_SUCCESS;
1561	}
1562
1563
1564	/**
1565	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1566	* fields on every successful VM-entry.
1567	*
1568	* Sets up the appropriate VMRUN function to execute guest code based
1569	* on the guest CPU mode.
1570	*
1571	* @returns VBox status code.
1572	* @param pVM Pointer to the VM.
1573	* @param pVCpu Pointer to the VMCPU.
1574	* @param pMixedCtx Pointer to the guest-CPU context.
1575	*
1576	* @remarks No-long-jump zone!!!
1577	*/
1578	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1579	{
1580	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1581	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1582
1583	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1584
1585	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1586	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1587
1588	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1589	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1590
1591	pVmcb->guest.u64RIP = pCtx->rip;
1592	pVmcb->guest.u64RSP = pCtx->rsp;
1593	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1594	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1595	pVmcb->guest.u64RAX = pCtx->rax;
1596
1597	/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
1598	hmR0SvmLoadGuestDebugRegs(pVCpu, pVmcb, pCtx);
1599
1600	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1601	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1602
1603	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1604	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1605
1606	/* Clear any unused and reserved bits. */
1607	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1608	\| HM_CHANGED_GUEST_RSP
1609	\| HM_CHANGED_GUEST_RFLAGS
1610	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1611	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1612	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1613	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1614	\| HM_CHANGED_SVM_RESERVED2
1615	\| HM_CHANGED_SVM_RESERVED3);
1616
1617	AssertMsg(!pVCpu->hm.s.fContextUseFlags,
1618	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1619	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1620
1621	Log4(("Load: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
1622
1623	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1624	return rc;
1625	}
1626
1627
1628	/**
1629	* Loads the guest state on the way from ring-3.
1630	*
1631	* @returns VBox status code.
1632	* @param pVM Pointer to the VM.
1633	* @param pVCpu Pointer to the VMCPU.
1634	* @param pCtx Pointer to the guest-CPU context.
1635	*
1636	* @remarks No-long-jump zone!!!
1637	*/
1638	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1639	{
1640	/*
1641	* Avoid reloading the guest state on longjmp reentrants and do it lazily just before executing the guest.
1642	* This only helps when we get rescheduled more than once to a different host CPU on a longjmp trip before
1643	* finally executing guest code.
1644	*/
1645	return VINF_SUCCESS;
1646	}
1647
1648
1649	/**
1650	* Saves the entire guest state from the VMCB into the
1651	* guest-CPU context. Currently there is no residual state left in the CPU that
1652	* is not updated in the VMCB.
1653	*
1654	* @returns VBox status code.
1655	* @param pVCpu Pointer to the VMCPU.
1656	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1657	* out-of-sync. Make sure to update the required fields
1658	* before using them.
1659	*/
1660	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1661	{
1662	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1663
1664	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1665
1666	pMixedCtx->rip = pVmcb->guest.u64RIP;
1667	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1668	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1669	pMixedCtx->rax = pVmcb->guest.u64RAX;
1670
1671	/*
1672	* Guest interrupt shadow.
1673	*/
1674	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1675	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1676	else
1677	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1678
1679	/*
1680	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1681	*/
1682	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1683
1684	/*
1685	* Guest MSRs.
1686	*/
1687	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1688	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1689	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1690	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1691	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1692	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1693	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1694	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1695
1696	/*
1697	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1698	*/
1699	HMSVM_SAVE_SEG_REG(CS, cs);
1700	HMSVM_SAVE_SEG_REG(SS, ss);
1701	HMSVM_SAVE_SEG_REG(DS, ds);
1702	HMSVM_SAVE_SEG_REG(ES, es);
1703	HMSVM_SAVE_SEG_REG(FS, fs);
1704	HMSVM_SAVE_SEG_REG(GS, gs);
1705
1706	/*
1707	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1708	* register (yet).
1709	*/
1710	/** @todo SELM might need to be fixed as it too should not care about the
1711	* granularity bit. See @bugref{6785}. */
1712	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1713	&& pMixedCtx->cs.Attr.n.u1Present
1714	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1715	{
1716	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1717	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1718	}
1719
1720	#ifdef VBOX_STRICT
1721	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1722	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1723	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1724	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1725	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1726	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1727	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1728
1729	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1730	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1731	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1732	HMSVM_ASSERT_SEG_GRANULARITY(es);
1733	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1734	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1735
1736	# undef HMSVM_ASSERT_SEL_GRANULARITY
1737	#endif
1738
1739	/*
1740	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1741	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1742	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1743	* See AMD spec. 15.5.1 "Basic operation".
1744	*/
1745	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1746	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1747
1748	/*
1749	* Guest Descriptor-Table registers.
1750	*/
1751	HMSVM_SAVE_SEG_REG(TR, tr);
1752	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1753	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1754	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1755
1756	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1757	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1758
1759	/*
1760	* Guest Debug registers.
1761	*/
1762	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1763	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1764
1765	/*
1766	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1767	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1768	*/
1769	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1770	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1771	{
1772	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1773	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1774	}
1775	}
1776
1777
1778	/**
1779	* Does the necessary state syncing before doing a longjmp to ring-3.
1780	*
1781	* @param pVM Pointer to the VM.
1782	* @param pVCpu Pointer to the VMCPU.
1783	* @param pCtx Pointer to the guest-CPU context.
1784	* @param rcExit The reason for exiting to ring-3. Can be
1785	* VINF_VMM_UNKNOWN_RING3_CALL.
1786	*
1787	* @remarks No-long-jmp zone!!!
1788	*/
1789	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1790	{
1791	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1792	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1793
1794	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1795	if (CPUMIsGuestFPUStateActive(pVCpu))
1796	{
1797	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1798	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1799	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1800	}
1801
1802	/* Restore host debug registers if necessary and resync on next R0 reentry. */
1803	if (CPUMIsGuestDebugStateActive(pVCpu))
1804	{
1805	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
1806	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1807	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1808	}
1809	else if (CPUMIsHyperDebugStateActive(pVCpu))
1810	{
1811	CPUMR0LoadHostDebugState(pVM, pVCpu);
1812	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1813	#ifdef VBOX_STRICT
1814	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1815	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1816	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1817	#endif
1818	}
1819
1820	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
1821	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
1822	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1823	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1824	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1825
1826	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1827	}
1828
1829
1830	/**
1831	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
1832	* any remaining host state) before we longjump to ring-3 and possibly get
1833	* preempted.
1834	*
1835	* @param pVCpu Pointer to the VMCPU.
1836	* @param enmOperation The operation causing the ring-3 longjump.
1837	* @param pvUser The user argument (pointer to the possibly
1838	* out-of-date guest-CPU context).
1839	*
1840	* @remarks Must never be called with @a enmOperation ==
1841	* VMMCALLRING3_VM_R0_ASSERTION.
1842	*/
1843	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1844	{
1845	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
1846	Assert(pVCpu);
1847	Assert(pvUser);
1848	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1849	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1850
1851	VMMRZCallRing3Disable(pVCpu);
1852	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1853	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
1854	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser, VINF_VMM_UNKNOWN_RING3_CALL);
1855	VMMRZCallRing3Enable(pVCpu);
1856	}
1857
1858
1859	/**
1860	* An action requires us to go back to ring-3. This function does the necessary
1861	* steps before we can safely return to ring-3. This is not the same as longjmps
1862	* to ring-3, this is voluntary.
1863	*
1864	* @param pVM Pointer to the VM.
1865	* @param pVCpu Pointer to the VMCPU.
1866	* @param pCtx Pointer to the guest-CPU context.
1867	* @param rcExit The reason for exiting to ring-3. Can be
1868	* VINF_VMM_UNKNOWN_RING3_CALL.
1869	*/
1870	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
1871	{
1872	Assert(pVM);
1873	Assert(pVCpu);
1874	Assert(pCtx);
1875	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1876
1877	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
1878	{
1879	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
1880	return;
1881	}
1882
1883	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
1884	VMMRZCallRing3Disable(pVCpu);
1885	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
1886
1887	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
1888	if (pVCpu->hm.s.Event.fPending)
1889	{
1890	hmR0SvmPendingEventToTrpmTrap(pVCpu);
1891	Assert(!pVCpu->hm.s.Event.fPending);
1892	}
1893
1894	/* Sync. the guest state. */
1895	hmR0SvmLongJmpToRing3(pVM, pVCpu, pCtx, rcExit);
1896	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1897
1898	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1899	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
1900	\| CPUM_CHANGED_LDTR
1901	\| CPUM_CHANGED_GDTR
1902	\| CPUM_CHANGED_IDTR
1903	\| CPUM_CHANGED_TR
1904	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
1905
1906	/* On our way back from ring-3 the following needs to be done. */
1907	/** @todo This can change with preemption hooks. */
1908	if (rcExit == VINF_EM_RAW_INTERRUPT)
1909	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
1910	else
1911	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1912
1913	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
1914	VMMRZCallRing3Enable(pVCpu);
1915	}
1916
1917
1918	/**
1919	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
1920	* intercepts.
1921	*
1922	* @param pVCpu Pointer to the VMCPU.
1923	*
1924	* @remarks No-long-jump zone!!!
1925	*/
1926	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
1927	{
1928	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1929	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
1930	{
1931	uint64_t u64CurTSC = ASMReadTSC();
1932	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
1933	{
1934	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
1935	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
1936	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
1937	}
1938	else
1939	{
1940	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1941	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1942	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
1943	}
1944	}
1945	else
1946	{
1947	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1948	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1949	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
1950	}
1951
1952	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1953	}
1954
1955
1956	/**
1957	* Sets an event as a pending event to be injected into the guest.
1958	*
1959	* @param pVCpu Pointer to the VMCPU.
1960	* @param pEvent Pointer to the SVM event.
1961	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
1962	* page-fault.
1963	*
1964	* @remarks Statistics counter assumes this is a guest event being reflected to
1965	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
1966	*/
1967	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
1968	{
1969	Assert(!pVCpu->hm.s.Event.fPending);
1970	Assert(pEvent->n.u1Valid);
1971
1972	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
1973	pVCpu->hm.s.Event.fPending = true;
1974	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
1975
1976	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
1977	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
1978
1979	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
1980	}
1981
1982
1983	/**
1984	* Injects an event into the guest upon VMRUN by updating the relevant field
1985	* in the VMCB.
1986	*
1987	* @param pVCpu Pointer to the VMCPU.
1988	* @param pVmcb Pointer to the guest VMCB.
1989	* @param pCtx Pointer to the guest-CPU context.
1990	* @param pEvent Pointer to the event.
1991	*
1992	* @remarks No-long-jump zone!!!
1993	* @remarks Requires CR0!
1994	*/
1995	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
1996	{
1997	pVmcb->ctrl.EventInject.u = pEvent->u;
1998	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
1999
2000	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2001	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2002	}
2003
2004
2005
2006	/**
2007	* Converts any TRPM trap into a pending HM event. This is typically used when
2008	* entering from ring-3 (not longjmp returns).
2009	*
2010	* @param pVCpu Pointer to the VMCPU.
2011	*/
2012	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2013	{
2014	Assert(TRPMHasTrap(pVCpu));
2015	Assert(!pVCpu->hm.s.Event.fPending);
2016
2017	uint8_t uVector;
2018	TRPMEVENT enmTrpmEvent;
2019	RTGCUINT uErrCode;
2020	RTGCUINTPTR GCPtrFaultAddress;
2021	uint8_t cbInstr;
2022
2023	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2024	AssertRC(rc);
2025
2026	SVMEVENT Event;
2027	Event.u = 0;
2028	Event.n.u1Valid = 1;
2029	Event.n.u8Vector = uVector;
2030
2031	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2032	if (enmTrpmEvent == TRPM_TRAP)
2033	{
2034	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2035	switch (uVector)
2036	{
2037	case X86_XCPT_PF:
2038	case X86_XCPT_DF:
2039	case X86_XCPT_TS:
2040	case X86_XCPT_NP:
2041	case X86_XCPT_SS:
2042	case X86_XCPT_GP:
2043	case X86_XCPT_AC:
2044	{
2045	Event.n.u1ErrorCodeValid = 1;
2046	Event.n.u32ErrorCode = uErrCode;
2047	break;
2048	}
2049	}
2050	}
2051	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2052	{
2053	if (uVector == X86_XCPT_NMI)
2054	Event.n.u3Type = SVM_EVENT_NMI;
2055	else
2056	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2057	}
2058	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2059	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2060	else
2061	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2062
2063	rc = TRPMResetTrap(pVCpu);
2064	AssertRC(rc);
2065
2066	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2067	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2068
2069	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2070	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2071	}
2072
2073
2074	/**
2075	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2076	* AMD-V to execute any instruction.
2077	*
2078	* @param pvCpu Pointer to the VMCPU.
2079	*/
2080	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2081	{
2082	Assert(pVCpu->hm.s.Event.fPending);
2083	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2084
2085	SVMEVENT Event;
2086	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2087
2088	uint8_t uVector = Event.n.u8Vector;
2089	uint8_t uVectorType = Event.n.u3Type;
2090
2091	TRPMEVENT enmTrapType;
2092	switch (uVectorType)
2093	{
2094	case SVM_EVENT_EXTERNAL_IRQ:
2095	case SVM_EVENT_NMI:
2096	enmTrapType = TRPM_HARDWARE_INT;
2097	break;
2098	case SVM_EVENT_SOFTWARE_INT:
2099	enmTrapType = TRPM_SOFTWARE_INT;
2100	break;
2101	case SVM_EVENT_EXCEPTION:
2102	enmTrapType = TRPM_TRAP;
2103	break;
2104	default:
2105	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2106	enmTrapType = TRPM_32BIT_HACK;
2107	break;
2108	}
2109
2110	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2111
2112	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2113	AssertRC(rc);
2114
2115	if (Event.n.u1ErrorCodeValid)
2116	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2117
2118	if ( uVectorType == SVM_EVENT_EXCEPTION
2119	&& uVector == X86_XCPT_PF)
2120	{
2121	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2122	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2123	}
2124	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2125	{
2126	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2127	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2128	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2129	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2130	}
2131	pVCpu->hm.s.Event.fPending = false;
2132	}
2133
2134
2135	/**
2136	* Gets the guest's interrupt-shadow.
2137	*
2138	* @returns The guest's interrupt-shadow.
2139	* @param pVCpu Pointer to the VMCPU.
2140	* @param pCtx Pointer to the guest-CPU context.
2141	*
2142	* @remarks No-long-jump zone!!!
2143	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2144	*/
2145	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2146	{
2147	/*
2148	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2149	* inhibit interrupts or clear any existing interrupt-inhibition.
2150	*/
2151	uint32_t uIntrState = 0;
2152	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2153	{
2154	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2155	{
2156	/*
2157	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2158	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2159	*/
2160	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2161	}
2162	else
2163	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2164	}
2165	return uIntrState;
2166	}
2167
2168
2169	/**
2170	* Sets the virtual interrupt intercept control in the VMCB which
2171	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2172	* receive interrupts.
2173	*
2174	* @param pVmcb Pointer to the VMCB.
2175	*/
2176	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2177	{
2178	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2179	{
2180	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2181	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2182	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2183	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2184
2185	Log4(("Setting VINTR intercept\n"));
2186	}
2187	}
2188
2189
2190	/**
2191	* Injects any pending events into the guest if the guest is in a state to
2192	* receive them.
2193	*
2194	* @param pVCpu Pointer to the VMCPU.
2195	* @param pCtx Pointer to the guest-CPU context.
2196	*/
2197	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2198	{
2199	Assert(!TRPMHasTrap(pVCpu));
2200	Log4Func(("\n"));
2201
2202	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2203	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2204	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2205
2206	SVMEVENT Event;
2207	Event.u = 0;
2208	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2209	{
2210	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2211	Assert(Event.n.u1Valid);
2212	bool fInject = true;
2213	if ( Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
2214	&& ( fBlockInt
2215	\|\| fIntShadow))
2216	{
2217	fInject = false;
2218	}
2219	else if ( Event.n.u3Type == SVM_EVENT_NMI
2220	&& fIntShadow)
2221	{
2222	fInject = false;
2223	}
2224
2225	if (fInject)
2226	{
2227	Log4(("Injecting pending HM event.\n"));
2228
2229	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2230	pVCpu->hm.s.Event.fPending = false;
2231
2232	#ifdef VBOX_WITH_STATISTICS
2233	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2234	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2235	else
2236	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2237	#endif
2238	}
2239	else
2240	hmR0SvmSetVirtIntrIntercept(pVmcb);
2241	} /** @todo SMI. SMIs take priority over NMIs. */
2242	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2243	{
2244	if (!fIntShadow)
2245	{
2246	Log4(("Injecting NMI\n"));
2247
2248	Event.n.u1Valid = 1;
2249	Event.n.u8Vector = X86_XCPT_NMI;
2250	Event.n.u3Type = SVM_EVENT_NMI;
2251
2252	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2253	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2254
2255	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2256	}
2257	else
2258	hmR0SvmSetVirtIntrIntercept(pVmcb);
2259	}
2260	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2261	{
2262	/* Check if there are guest external interrupts (PIC/APIC) pending and inject them, if the guest can receive them. */
2263	if ( !fBlockInt
2264	&& !fIntShadow)
2265	{
2266	uint8_t u8Interrupt;
2267	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2268	if (RT_SUCCESS(rc))
2269	{
2270	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2271
2272	Event.n.u1Valid = 1;
2273	Event.n.u8Vector = u8Interrupt;
2274	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2275
2276	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2277	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2278	}
2279	else
2280	{
2281	/** @todo Does this actually happen? If not turn it into an assertion. */
2282	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2283	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2284	}
2285	}
2286	else
2287	hmR0SvmSetVirtIntrIntercept(pVmcb);
2288	}
2289
2290	/* Update the guest interrupt shadow in the VMCB. */
2291	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2292	}
2293
2294
2295	/**
2296	* Reports world-switch error and dumps some useful debug info.
2297	*
2298	* @param pVM Pointer to the VM.
2299	* @param pVCpu Pointer to the VMCPU.
2300	* @param rcVMRun The return code from VMRUN (or
2301	* VERR_SVM_INVALID_GUEST_STATE for invalid
2302	* guest-state).
2303	* @param pCtx Pointer to the guest-CPU context.
2304	*/
2305	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2306	{
2307	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2308	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2309
2310	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2311	{
2312	HMDumpRegs(pVM, pVCpu, pCtx);
2313	#ifdef VBOX_STRICT
2314	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2315	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2316	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2317	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2318	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2319	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2320	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2321	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2322	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2323	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2324	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2325
2326	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2327	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2328	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2329
2330	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2331	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2332	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2333	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2334	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2335	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2336	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2337	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2338	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2339	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2340
2341	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2342	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2343	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2344	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2345	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2346	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2347	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2348	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2349	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2350	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2351	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2352	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2353	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2354	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2355	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2356	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2357	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2358
2359	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2360	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2361
2362	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2363	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2364	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2365	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2366	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2367	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2368	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2369	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2370	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2371	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2372	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2373	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2374	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2375	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2376	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2377	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2378	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2379	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2380	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2381	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2382
2383	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2384	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2385
2386	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2387	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2388	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2389	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2390
2391	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2392	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2393
2394	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2395	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2396	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2397	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2398
2399	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2400	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2401	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2402	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2403	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2404	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2405	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2406
2407	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2408	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2409	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2410	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2411
2412	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2413	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2414	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2415
2416	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2417	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2418	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2419	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2420	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2421	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2422	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2423	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2424	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2425	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2426	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2427	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2428	#endif
2429	}
2430	else
2431	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2432	}
2433
2434
2435	/**
2436	* Check per-VM and per-VCPU force flag actions that require us to go back to
2437	* ring-3 for one reason or another.
2438	*
2439	* @returns VBox status code (information status code included).
2440	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2441	* ring-3.
2442	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2443	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2444	* interrupts)
2445	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2446	* all EMTs to be in ring-3.
2447	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2448	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2449	* to the EM loop.
2450	*
2451	* @param pVM Pointer to the VM.
2452	* @param pVCpu Pointer to the VMCPU.
2453	* @param pCtx Pointer to the guest-CPU context.
2454	*/
2455	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2456	{
2457	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2458
2459	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2460	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2461	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2462
2463	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
2464	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
2465	\| VMCPU_FF_REQUEST))
2466	{
2467	/* Pending PGM C3 sync. */
2468	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2469	{
2470	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2471	if (rc != VINF_SUCCESS)
2472	{
2473	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2474	return rc;
2475	}
2476	}
2477
2478	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2479	/* -XXX- what was that about single stepping? */
2480	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2481	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2482	{
2483	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2484	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2485	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2486	return rc;
2487	}
2488
2489	/* Pending VM request packets, such as hardware interrupts. */
2490	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2491	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2492	{
2493	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2494	return VINF_EM_PENDING_REQUEST;
2495	}
2496
2497	/* Pending PGM pool flushes. */
2498	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2499	{
2500	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2501	return VINF_PGM_POOL_FLUSH_PENDING;
2502	}
2503
2504	/* Pending DMA requests. */
2505	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2506	{
2507	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2508	return VINF_EM_RAW_TO_R3;
2509	}
2510	}
2511
2512	return VINF_SUCCESS;
2513	}
2514
2515
2516	/**
2517	* Does the preparations before executing guest code in AMD-V.
2518	*
2519	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2520	* recompiler. We must be cautious what we do here regarding committing
2521	* guest-state information into the the VMCB assuming we assuredly execute the
2522	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2523	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2524	* that the recompiler can (and should) use them when it resumes guest
2525	* execution. Otherwise such operations must be done when we can no longer
2526	* exit to ring-3.
2527	*
2528	* @returns VBox status code (informational status codes included).
2529	* @retval VINF_SUCCESS if we can proceed with running the guest.
2530	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2531	*
2532	* @param pVM Pointer to the VM.
2533	* @param pVCpu Pointer to the VMCPU.
2534	* @param pCtx Pointer to the guest-CPU context.
2535	* @param pSvmTransient Pointer to the SVM transient structure.
2536	*/
2537	DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2538	{
2539	/* Check force flag actions that might require us to go back to ring-3. */
2540	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2541	if (rc != VINF_SUCCESS)
2542	return rc;
2543
2544	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2545	/* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.) */
2546	pSvmTransient->uEFlags = ASMIntDisableFlags();
2547	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2548	{
2549	ASMSetFlags(pSvmTransient->uEFlags);
2550	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2551	/* Don't use VINF_EM_RAW_INTERRUPT_HYPER as we can't assume the host does kernel preemption. Maybe some day? */
2552	return VINF_EM_RAW_INTERRUPT;
2553	}
2554	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2555	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2556	#endif
2557
2558	/* Convert any pending TRPM traps to HM events for injection. */
2559	/** @todo Optimization: move this before disabling interrupts, restore state
2560	* using pVmcb->ctrl.EventInject.u. */
2561	if (TRPMHasTrap(pVCpu))
2562	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2563
2564	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2565
2566	return VINF_SUCCESS;
2567	}
2568
2569
2570	/**
2571	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2572	* means there is no backing out to ring-3 or anywhere else at this
2573	* point.
2574	*
2575	* @param pVM Pointer to the VM.
2576	* @param pVCpu Pointer to the VMCPU.
2577	* @param pCtx Pointer to the guest-CPU context.
2578	* @param pSvmTransient Pointer to the SVM transient structure.
2579	*
2580	* @remarks Called with preemption disabled.
2581	* @remarks No-long-jump zone!!!
2582	*/
2583	DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2584	{
2585	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2586	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2587
2588	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2589	/** @todo I don't see the point of this, VMMR0EntryFast() already disables interrupts for the entire period. */
2590	pSvmTransient->uEFlags = ASMIntDisableFlags();
2591	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2592	#endif
2593
2594	/*
2595	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2596	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2597	*/
2598	/** @todo The above assumption could be wrong. It's not documented what
2599	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2600	* hard way. */
2601	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2602	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2603
2604	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2605	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2606	#endif
2607
2608	/* Load the guest state. */
2609	int rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2610	AssertRC(rc);
2611	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
2612	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2613
2614	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2615	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2616	pVmcb->ctrl.u64VmcbCleanBits = 0;
2617
2618	/*
2619	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2620	* so we can update it on the way back if the guest changed the TPR.
2621	*/
2622	if (pVCpu->hm.s.svm.fSyncVTpr)
2623	{
2624	if (pVM->hm.s.fTPRPatchingActive)
2625	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2626	else
2627	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2628	}
2629
2630	/* Setup TSC offsetting. */
2631	if ( pSvmTransient->fUpdateTscOffsetting
2632	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2633	{
2634	hmR0SvmUpdateTscOffsetting(pVCpu);
2635	pSvmTransient->fUpdateTscOffsetting = false;
2636	}
2637
2638	/* Flush the appropriate tagged-TLB entries. */
2639	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2640	hmR0SvmFlushTaggedTlb(pVCpu);
2641	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2642
2643	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2644
2645	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2646	to start executing. */
2647
2648	/*
2649	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2650	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2651	*
2652	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2653	*/
2654	pSvmTransient->fRestoreTscAuxMsr = false;
2655	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2656	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2657	{
2658	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2659	uint64_t u64GuestTscAux = 0;
2660	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2661	AssertRC(rc2);
2662	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2663	{
2664	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2665	pSvmTransient->fRestoreTscAuxMsr = true;
2666	}
2667	}
2668	}
2669
2670
2671	/**
2672	* Wrapper for running the guest code in AMD-V.
2673	*
2674	* @returns VBox strict status code.
2675	* @param pVM Pointer to the VM.
2676	* @param pVCpu Pointer to the VMCPU.
2677	* @param pCtx Pointer to the guest-CPU context.
2678	*
2679	* @remarks No-long-jump zone!!!
2680	*/
2681	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2682	{
2683	/*
2684	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2685	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2686	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2687	*/
2688	#ifdef VBOX_WITH_KERNEL_USING_XMM
2689	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2690	pVCpu->hm.s.svm.pfnVMRun);
2691	#else
2692	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2693	#endif
2694	}
2695
2696
2697	/**
2698	* Performs some essential restoration of state after running guest code in
2699	* AMD-V.
2700	*
2701	* @param pVM Pointer to the VM.
2702	* @param pVCpu Pointer to the VMCPU.
2703	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2704	* out-of-sync. Make sure to update the required fields
2705	* before using them.
2706	* @param pSvmTransient Pointer to the SVM transient structure.
2707	* @param rcVMRun Return code of VMRUN.
2708	*
2709	* @remarks Called with interrupts disabled.
2710	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2711	* unconditionally when it is safe to do so.
2712	*/
2713	DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2714	{
2715	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2716
2717	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2718	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2719
2720	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2721	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2722
2723	if (pSvmTransient->fRestoreTscAuxMsr)
2724	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2725
2726	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2727	{
2728	/** @todo Find a way to fix hardcoding a guestimate. */
2729	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
2730	}
2731
2732	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
2733	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2734	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2735
2736	Assert(!(ASMGetFlags() & X86_EFL_IF));
2737	ASMSetFlags(pSvmTransient->uEFlags); /* Enable interrupts. */
2738
2739	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pMixedCtx);
2740	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2741
2742	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2743	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2744	{
2745	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2746	return;
2747	}
2748
2749	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2750	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2751	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2752
2753	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2754	{
2755	if (pVCpu->hm.s.svm.fSyncVTpr)
2756	{
2757	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2758	if ( pVM->hm.s.fTPRPatchingActive
2759	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2760	{
2761	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
2762	AssertRC(rc);
2763	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2764	}
2765	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2766	{
2767	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
2768	AssertRC(rc);
2769	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2770	}
2771	}
2772	}
2773	}
2774
2775
2776	/**
2777	* Runs the guest code using AMD-V.
2778	*
2779	* @returns VBox status code.
2780	* @param pVM Pointer to the VM.
2781	* @param pVCpu Pointer to the VMCPU.
2782	* @param pCtx Pointer to the guest-CPU context.
2783	*/
2784	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2785	{
2786	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2787	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2788
2789	SVMTRANSIENT SvmTransient;
2790	SvmTransient.fUpdateTscOffsetting = true;
2791	uint32_t cLoops = 0;
2792	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2793	int rc = VERR_INTERNAL_ERROR_5;
2794
2795	for (;; cLoops++)
2796	{
2797	Assert(!HMR0SuspendPending());
2798	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
2799	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
2800	(unsigned)RTMpCpuId(), cLoops));
2801
2802	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
2803	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
2804	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
2805	if (rc != VINF_SUCCESS)
2806	break;
2807
2808	/*
2809	* No longjmps to ring-3 from this point on!!!
2810	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2811	* This also disables flushing of the R0-logger instance (if any).
2812	*/
2813	VMMRZCallRing3Disable(pVCpu);
2814	VMMRZCallRing3RemoveNotification(pVCpu);
2815	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
2816
2817	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
2818
2819	/*
2820	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
2821	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
2822	*/
2823	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
2824	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
2825	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
2826	{
2827	if (rc == VINF_SUCCESS)
2828	rc = VERR_SVM_INVALID_GUEST_STATE;
2829	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
2830	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2831	return rc;
2832	}
2833
2834	/* Handle the #VMEXIT. */
2835	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
2836	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
2837	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
2838	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
2839	if (rc != VINF_SUCCESS)
2840	break;
2841	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
2842	{
2843	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
2844	rc = VINF_EM_RAW_INTERRUPT;
2845	break;
2846	}
2847	}
2848
2849	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
2850	if (rc == VERR_EM_INTERPRETER)
2851	rc = VINF_EM_RAW_EMULATE_INSTR;
2852	else if (rc == VINF_EM_RESET)
2853	rc = VINF_EM_TRIPLE_FAULT;
2854	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
2855	return rc;
2856	}
2857
2858
2859	/**
2860	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
2861	*
2862	* @returns VBox status code (informational status codes included).
2863	* @param pVCpu Pointer to the VMCPU.
2864	* @param pCtx Pointer to the guest-CPU context.
2865	* @param pSvmTransient Pointer to the SVM transient structure.
2866	*/
2867	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2868	{
2869	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
2870	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
2871
2872	/*
2873	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
2874	* normal workloads (for some definition of "normal").
2875	*/
2876	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
2877	switch (pSvmTransient->u64ExitCode)
2878	{
2879	case SVM_EXIT_NPF:
2880	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
2881
2882	case SVM_EXIT_IOIO:
2883	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
2884
2885	case SVM_EXIT_RDTSC:
2886	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
2887
2888	case SVM_EXIT_RDTSCP:
2889	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
2890
2891	case SVM_EXIT_CPUID:
2892	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
2893
2894	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
2895	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
2896
2897	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
2898	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
2899
2900	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
2901	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
2902
2903	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
2904	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
2905
2906	case SVM_EXIT_MONITOR:
2907	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
2908
2909	case SVM_EXIT_MWAIT:
2910	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
2911
2912	case SVM_EXIT_HLT:
2913	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
2914
2915	case SVM_EXIT_READ_CR0:
2916	case SVM_EXIT_READ_CR3:
2917	case SVM_EXIT_READ_CR4:
2918	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
2919
2920	case SVM_EXIT_WRITE_CR0:
2921	case SVM_EXIT_WRITE_CR3:
2922	case SVM_EXIT_WRITE_CR4:
2923	case SVM_EXIT_WRITE_CR8:
2924	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
2925
2926	case SVM_EXIT_VINTR:
2927	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
2928
2929	case SVM_EXIT_INTR:
2930	case SVM_EXIT_FERR_FREEZE:
2931	case SVM_EXIT_NMI:
2932	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
2933
2934	case SVM_EXIT_MSR:
2935	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
2936
2937	case SVM_EXIT_INVLPG:
2938	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
2939
2940	case SVM_EXIT_WBINVD:
2941	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
2942
2943	case SVM_EXIT_INVD:
2944	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
2945
2946	case SVM_EXIT_RDPMC:
2947	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
2948
2949	default:
2950	{
2951	switch (pSvmTransient->u64ExitCode)
2952	{
2953	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2954	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
2955	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
2956	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2957	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
2958
2959	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2960	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
2961	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
2962	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2963	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
2964
2965	case SVM_EXIT_TASK_SWITCH:
2966	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
2967
2968	case SVM_EXIT_VMMCALL:
2969	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
2970
2971	case SVM_EXIT_SHUTDOWN:
2972	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
2973
2974	case SVM_EXIT_SMI:
2975	case SVM_EXIT_INIT:
2976	{
2977	/*
2978	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
2979	* we want to know about it so log the exit code and bail.
2980	*/
2981	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
2982	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
2983	return VERR_SVM_UNEXPECTED_EXIT;
2984	}
2985
2986	case SVM_EXIT_INVLPGA:
2987	case SVM_EXIT_RSM:
2988	case SVM_EXIT_VMRUN:
2989	case SVM_EXIT_VMLOAD:
2990	case SVM_EXIT_VMSAVE:
2991	case SVM_EXIT_STGI:
2992	case SVM_EXIT_CLGI:
2993	case SVM_EXIT_SKINIT:
2994	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
2995
2996	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2997	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
2998	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
2999	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3000	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3001	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3002	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3003	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3004	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3005	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3006	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3007	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3008	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3009	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3010	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3011	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3012	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3013	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3014	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3015	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3016
3017	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3018	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3019	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3020	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3021	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3022	{
3023	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3024	SVMEVENT Event;
3025	Event.u = 0;
3026	Event.n.u1Valid = 1;
3027	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3028	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3029
3030	switch (Event.n.u8Vector)
3031	{
3032	case X86_XCPT_DE:
3033	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3034	break;
3035
3036	case X86_XCPT_BP:
3037	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3038	* next instruction. */
3039	/** @todo Investigate this later. */
3040	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3041	break;
3042
3043	case X86_XCPT_UD:
3044	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3045	break;
3046
3047	case X86_XCPT_NP:
3048	Event.n.u1ErrorCodeValid = 1;
3049	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3050	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3051	break;
3052
3053	case X86_XCPT_SS:
3054	Event.n.u1ErrorCodeValid = 1;
3055	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3056	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3057	break;
3058
3059	case X86_XCPT_GP:
3060	Event.n.u1ErrorCodeValid = 1;
3061	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3062	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3063	break;
3064
3065	default:
3066	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3067	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3068	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3069	}
3070
3071	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3072	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3073	return VINF_SUCCESS;
3074	}
3075	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3076
3077	default:
3078	{
3079	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3080	pVCpu->hm.s.u32HMError = u32ExitCode;
3081	return VERR_SVM_UNKNOWN_EXIT;
3082	}
3083	}
3084	}
3085	}
3086	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3087	}
3088
3089
3090	#ifdef DEBUG
3091	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3092	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3093	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3094
3095	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3096	do \
3097	{ \
3098	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3099	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3100	} while (0)
3101
3102	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3103	do { \
3104	AssertPtr(pVCpu); \
3105	AssertPtr(pCtx); \
3106	AssertPtr(pSvmTransient); \
3107	Assert(ASMIntAreEnabled()); \
3108	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3109	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3110	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3111	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD)); \
3112	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3113	HMSVM_ASSERT_PREEMPT_CPUID(); \
3114	} while (0)
3115	#else /* Release builds */
3116	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3117	#endif
3118
3119
3120	/**
3121	* Worker for hmR0SvmInterpretInvlpg().
3122	*
3123	* @return VBox status code.
3124	* @param pVCpu Pointer to the VMCPU.
3125	* @param pCpu Pointer to the disassembler state.
3126	* @param pRegFrame Pointer to the register frame.
3127	*/
3128	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3129	{
3130	DISQPVPARAMVAL Param1;
3131	RTGCPTR GCPtrPage;
3132
3133	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3134	if (RT_FAILURE(rc))
3135	return VERR_EM_INTERPRETER;
3136
3137	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3138	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3139	{
3140	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3141	return VERR_EM_INTERPRETER;
3142
3143	GCPtrPage = Param1.val.val64;
3144	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3145	rc = VBOXSTRICTRC_VAL(rc2);
3146	}
3147	else
3148	{
3149	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3150	rc = VERR_EM_INTERPRETER;
3151	}
3152
3153	return rc;
3154	}
3155
3156
3157	/**
3158	* Interprets INVLPG.
3159	*
3160	* @returns VBox status code.
3161	* @retval VINF_* Scheduling instructions.
3162	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3163	* @retval VERR_* Fatal errors.
3164	*
3165	* @param pVM Pointer to the VM.
3166	* @param pRegFrame Pointer to the register frame.
3167	*
3168	* @remarks Updates the RIP if the instruction was executed successfully.
3169	*/
3170	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3171	{
3172	/* Only allow 32 & 64 bit code. */
3173	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3174	{
3175	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3176	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3177	if ( RT_SUCCESS(rc)
3178	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3179	{
3180	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3181	if (RT_SUCCESS(rc))
3182	pRegFrame->rip += pDis->cbInstr;
3183	return rc;
3184	}
3185	else
3186	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3187	}
3188	return VERR_EM_INTERPRETER;
3189	}
3190
3191
3192	/**
3193	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3194	*
3195	* @param pVCpu Pointer to the VMCPU.
3196	*/
3197	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3198	{
3199	SVMEVENT Event;
3200	Event.u = 0;
3201	Event.n.u1Valid = 1;
3202	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3203	Event.n.u8Vector = X86_XCPT_UD;
3204	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3205	}
3206
3207
3208	/**
3209	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3210	*
3211	* @param pVCpu Pointer to the VMCPU.
3212	*/
3213	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3214	{
3215	SVMEVENT Event;
3216	Event.u = 0;
3217	Event.n.u1Valid = 1;
3218	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3219	Event.n.u8Vector = X86_XCPT_DB;
3220	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3221	}
3222
3223
3224	/**
3225	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3226	*
3227	* @param pVCpu Pointer to the VMCPU.
3228	* @param pCtx Pointer to the guest-CPU context.
3229	* @param u32ErrCode The error-code for the page-fault.
3230	* @param uFaultAddress The page fault address (CR2).
3231	*
3232	* @remarks This updates the guest CR2 with @a uFaultAddress!
3233	*/
3234	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3235	{
3236	SVMEVENT Event;
3237	Event.u = 0;
3238	Event.n.u1Valid = 1;
3239	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3240	Event.n.u8Vector = X86_XCPT_PF;
3241	Event.n.u1ErrorCodeValid = 1;
3242	Event.n.u32ErrorCode = u32ErrCode;
3243
3244	/* Update CR2 of the guest. */
3245	if (pCtx->cr2 != uFaultAddress)
3246	{
3247	pCtx->cr2 = uFaultAddress;
3248	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR2;
3249	}
3250
3251	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3252	}
3253
3254
3255	/**
3256	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3257	* VM.
3258	*
3259	* @param pVCpu Pointer to the VMCPU.
3260	*/
3261	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3262	{
3263	SVMEVENT Event;
3264	Event.u = 0;
3265	Event.n.u1Valid = 1;
3266	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3267	Event.n.u8Vector = X86_XCPT_NM;
3268	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3269	}
3270
3271
3272	/**
3273	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3274	*
3275	* @param pVCpu Pointer to the VMCPU.
3276	*/
3277	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3278	{
3279	SVMEVENT Event;
3280	Event.u = 0;
3281	Event.n.u1Valid = 1;
3282	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3283	Event.n.u8Vector = X86_XCPT_MF;
3284	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3285	}
3286
3287
3288	/**
3289	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3290	*
3291	* @param pVCpu Pointer to the VMCPU.
3292	*/
3293	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3294	{
3295	SVMEVENT Event;
3296	Event.u = 0;
3297	Event.n.u1Valid = 1;
3298	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3299	Event.n.u8Vector = X86_XCPT_DF;
3300	Event.n.u1ErrorCodeValid = 1;
3301	Event.n.u32ErrorCode = 0;
3302	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3303	}
3304
3305
3306	/**
3307	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3308	* guests. This simply looks up the patch record at EIP and does the required.
3309	*
3310	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3311	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3312	* TPR). See hmR3ReplaceTprInstr() for the details.
3313	*
3314	* @returns VBox status code.
3315	* @param pVM Pointer to the VM.
3316	* @param pVCpu Pointer to the VMCPU.
3317	* @param pCtx Pointer to the guest-CPU context.
3318	*/
3319	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3320	{
3321	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3322	for (;;)
3323	{
3324	bool fPending;
3325	uint8_t u8Tpr;
3326
3327	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3328	if (!pPatch)
3329	break;
3330
3331	switch (pPatch->enmType)
3332	{
3333	case HMTPRINSTR_READ:
3334	{
3335	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3336	AssertRC(rc);
3337
3338	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3339	AssertRC(rc);
3340	pCtx->rip += pPatch->cbOp;
3341	break;
3342	}
3343
3344	case HMTPRINSTR_WRITE_REG:
3345	case HMTPRINSTR_WRITE_IMM:
3346	{
3347	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3348	{
3349	uint32_t u32Val;
3350	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3351	AssertRC(rc);
3352	u8Tpr = u32Val;
3353	}
3354	else
3355	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3356
3357	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3358	AssertRC(rc2);
3359	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3360
3361	pCtx->rip += pPatch->cbOp;
3362	break;
3363	}
3364
3365	default:
3366	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3367	pVCpu->hm.s.u32HMError = pPatch->enmType;
3368	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3369	}
3370	}
3371
3372	return VINF_SUCCESS;
3373	}
3374
3375	/**
3376	* Determines if an exception is a contributory exception. Contributory
3377	* exceptions are ones which can cause double-faults. Page-fault is
3378	* intentionally not included here as it's a conditional contributory exception.
3379	*
3380	* @returns true if the exception is contributory, false otherwise.
3381	* @param uVector The exception vector.
3382	*/
3383	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3384	{
3385	switch (uVector)
3386	{
3387	case X86_XCPT_GP:
3388	case X86_XCPT_SS:
3389	case X86_XCPT_NP:
3390	case X86_XCPT_TS:
3391	case X86_XCPT_DE:
3392	return true;
3393	default:
3394	break;
3395	}
3396	return false;
3397	}
3398
3399
3400	/**
3401	* Handle a condition that occurred while delivering an event through the guest
3402	* IDT.
3403	*
3404	* @returns VBox status code (informational error codes included).
3405	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3406	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3407	* continue execution of the guest which will delivery the #DF.
3408	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3409	*
3410	* @param pVCpu Pointer to the VMCPU.
3411	* @param pCtx Pointer to the guest-CPU context.
3412	* @param pSvmTransient Pointer to the SVM transient structure.
3413	*
3414	* @remarks No-long-jump zone!!!
3415	*/
3416	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3417	{
3418	int rc = VINF_SUCCESS;
3419	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3420
3421	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3422	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3423	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3424	{
3425	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3426
3427	typedef enum
3428	{
3429	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3430	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3431	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3432	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3433	} SVMREFLECTXCPT;
3434
3435	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3436	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3437	{
3438	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3439	{
3440	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3441
3442	#ifdef VBOX_STRICT
3443	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3444	&& uExitVector == X86_XCPT_PF)
3445	{
3446	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3447	}
3448	#endif
3449	if ( uExitVector == X86_XCPT_PF
3450	&& uIdtVector == X86_XCPT_PF)
3451	{
3452	pSvmTransient->fVectoringPF = true;
3453	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3454	}
3455	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3456	&& hmR0SvmIsContributoryXcpt(uExitVector)
3457	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3458	\|\| uIdtVector == X86_XCPT_PF))
3459	{
3460	enmReflect = SVMREFLECTXCPT_DF;
3461	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3462	uIdtVector, uExitVector));
3463	}
3464	else if (uIdtVector == X86_XCPT_DF)
3465	{
3466	enmReflect = SVMREFLECTXCPT_TF;
3467	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3468	uIdtVector, uExitVector));
3469	}
3470	else
3471	enmReflect = SVMREFLECTXCPT_XCPT;
3472	}
3473	else
3474	{
3475	/*
3476	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3477	* exception to the guest after handling the VM-exit.
3478	*/
3479	enmReflect = SVMREFLECTXCPT_XCPT;
3480	}
3481	}
3482	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3483	{
3484	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3485	enmReflect = SVMREFLECTXCPT_XCPT;
3486	}
3487
3488	switch (enmReflect)
3489	{
3490	case SVMREFLECTXCPT_XCPT:
3491	{
3492	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3493	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3494
3495	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3496	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3497	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3498	break;
3499	}
3500
3501	case SVMREFLECTXCPT_DF:
3502	{
3503	hmR0SvmSetPendingXcptDF(pVCpu);
3504	rc = VINF_HM_DOUBLE_FAULT;
3505	break;
3506	}
3507
3508	case SVMREFLECTXCPT_TF:
3509	{
3510	rc = VINF_EM_RESET;
3511	break;
3512	}
3513
3514	default:
3515	Assert(rc == VINF_SUCCESS);
3516	break;
3517	}
3518	}
3519	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3520	return rc;
3521	}
3522
3523
3524	/**
3525	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
3526	* CPU, otherwise advances the RIP by @a cb bytes.
3527	*
3528	* @param pVCpu Pointer to the VMCPU.
3529	* @param pCtx Pointer to the guest-CPU context.
3530	* @param cb RIP increment value in bytes.
3531	*
3532	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
3533	* when NRIP_SAVE is supported by the CPU!
3534	*/
3535	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
3536	{
3537	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3538	{
3539	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3540	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3541	}
3542	else
3543	pCtx->rip += cb;
3544	}
3545
3546
3547	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3548	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3549	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3550
3551	/** @name VM-exit handlers.
3552	* @{
3553	*/
3554
3555	/**
3556	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3557	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3558	*/
3559	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3560	{
3561	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3562
3563	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
3564	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmi);
3565	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
3566	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3567
3568	/*
3569	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3570	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3571	* interrupt it is until the host actually take the interrupt.
3572	*
3573	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3574	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3575	*/
3576	return VINF_EM_RAW_INTERRUPT;
3577	}
3578
3579
3580	/**
3581	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3582	*/
3583	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3584	{
3585	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3586
3587	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3588	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3589	return VINF_SUCCESS;
3590	}
3591
3592
3593	/**
3594	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3595	*/
3596	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3597	{
3598	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3599
3600	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3601	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3602	return VINF_SUCCESS;
3603	}
3604
3605
3606	/**
3607	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3608	*/
3609	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3610	{
3611	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3612	PVM pVM = pVCpu->CTX_SUFF(pVM);
3613	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3614	if (RT_LIKELY(rc == VINF_SUCCESS))
3615	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3616	else
3617	{
3618	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3619	rc = VERR_EM_INTERPRETER;
3620	}
3621	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3622	return rc;
3623	}
3624
3625
3626	/**
3627	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3628	*/
3629	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3630	{
3631	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3632	PVM pVM = pVCpu->CTX_SUFF(pVM);
3633	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3634	if (RT_LIKELY(rc == VINF_SUCCESS))
3635	{
3636	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3637	pSvmTransient->fUpdateTscOffsetting = true;
3638	}
3639	else
3640	{
3641	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3642	rc = VERR_EM_INTERPRETER;
3643	}
3644	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3645	return rc;
3646	}
3647
3648
3649	/**
3650	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3651	*/
3652	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3653	{
3654	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3655	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3656	if (RT_LIKELY(rc == VINF_SUCCESS))
3657	{
3658	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3659	pSvmTransient->fUpdateTscOffsetting = true;
3660	}
3661	else
3662	{
3663	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3664	rc = VERR_EM_INTERPRETER;
3665	}
3666	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3667	return rc;
3668	}
3669
3670
3671	/**
3672	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3673	*/
3674	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3675	{
3676	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3677	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3678	if (RT_LIKELY(rc == VINF_SUCCESS))
3679	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3680	else
3681	{
3682	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3683	rc = VERR_EM_INTERPRETER;
3684	}
3685	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3686	return rc;
3687	}
3688
3689
3690	/**
3691	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3692	*/
3693	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3694	{
3695	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3696	PVM pVM = pVCpu->CTX_SUFF(pVM);
3697	Assert(!pVM->hm.s.fNestedPaging);
3698
3699	/** @todo Decode Assist. */
3700	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3701	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3702	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3703	return rc;
3704	}
3705
3706
3707	/**
3708	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3709	*/
3710	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3711	{
3712	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3713	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
3714	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3715	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3716	return rc;
3717	}
3718
3719
3720	/**
3721	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3722	*/
3723	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3724	{
3725	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3726	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3727	if (RT_LIKELY(rc == VINF_SUCCESS))
3728	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3729	else
3730	{
3731	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3732	rc = VERR_EM_INTERPRETER;
3733	}
3734	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3735	return rc;
3736	}
3737
3738
3739	/**
3740	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3741	*/
3742	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3743	{
3744	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3745	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3746	int rc = VBOXSTRICTRC_VAL(rc2);
3747	if ( rc == VINF_EM_HALT
3748	\|\| rc == VINF_SUCCESS)
3749	{
3750	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3751
3752	if ( rc == VINF_EM_HALT
3753	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3754	{
3755	rc = VINF_SUCCESS;
3756	}
3757	}
3758	else
3759	{
3760	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3761	rc = VERR_EM_INTERPRETER;
3762	}
3763	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3764	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3765	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3766	return rc;
3767	}
3768
3769
3770	/**
3771	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
3772	* Conditional #VMEXIT.
3773	*/
3774	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3775	{
3776	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3777	return VINF_EM_RESET;
3778	}
3779
3780
3781	/**
3782	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
3783	*/
3784	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3785	{
3786	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3787
3788	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3789
3790	/** @todo Decode Assist. */
3791	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3792	int rc = VBOXSTRICTRC_VAL(rc2);
3793	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
3794	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
3795	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
3796	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
3797	return rc;
3798	}
3799
3800
3801	/**
3802	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
3803	*/
3804	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3805	{
3806	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3807	/** @todo Decode Assist. */
3808	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3809	int rc = VBOXSTRICTRC_VAL(rc2);
3810	if (rc == VINF_SUCCESS)
3811	{
3812	/* RIP has been updated by EMInterpretInstruction(). */
3813	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
3814	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
3815	{
3816	case 0: /* CR0. */
3817	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
3818	break;
3819
3820	case 3: /* CR3. */
3821	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
3822	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
3823	break;
3824
3825	case 4: /* CR4. */
3826	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
3827	break;
3828
3829	case 8: /* CR8 (TPR). */
3830	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3831	break;
3832
3833	default:
3834	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
3835	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
3836	break;
3837	}
3838	}
3839	else
3840	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
3841	return rc;
3842	}
3843
3844
3845	/**
3846	* #VMEXIT handler for instructions that result in a #UD exception delivered to
3847	* the guest.
3848	*/
3849	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3850	{
3851	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3852	hmR0SvmSetPendingXcptUD(pVCpu);
3853	return VINF_SUCCESS;
3854	}
3855
3856
3857	/**
3858	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
3859	*/
3860	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3861	{
3862	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3863	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3864	PVM pVM = pVCpu->CTX_SUFF(pVM);
3865
3866	int rc;
3867	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
3868	{
3869	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
3870
3871	/* Handle TPR patching; intercepted LSTAR write. */
3872	if ( pVM->hm.s.fTPRPatchingActive
3873	&& pCtx->ecx == MSR_K8_LSTAR)
3874	{
3875	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
3876	{
3877	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
3878	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
3879	AssertRC(rc2);
3880	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3881	}
3882	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3883	return VINF_SUCCESS;
3884	}
3885
3886	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3887	{
3888	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3889	if (RT_LIKELY(rc == VINF_SUCCESS))
3890	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3891	else
3892	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
3893	}
3894	else
3895	{
3896	VBOXSTRICTRC rcStrict = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3897	rc = VBOXSTRICTRC_VAL(rcStrict);
3898	if (RT_UNLIKELY(rc != VINF_SUCCESS))
3899	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
3900	/* RIP updated by EMInterpretInstruction(). */
3901	}
3902
3903	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
3904	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
3905	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
3906	{
3907	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
3908	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
3909	EMInterpretWrmsr() changes it. */
3910	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3911	}
3912	else if (pCtx->ecx == MSR_K6_EFER)
3913	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
3914	else if (pCtx->ecx == MSR_IA32_TSC)
3915	pSvmTransient->fUpdateTscOffsetting = true;
3916	}
3917	else
3918	{
3919	/* MSR Read access. */
3920	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
3921	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
3922
3923	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3924	{
3925	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3926	if (RT_LIKELY(rc == VINF_SUCCESS))
3927	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3928	else
3929	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
3930	}
3931	else
3932	{
3933	VBOXSTRICTRC rcStrict = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
3934	rc = VBOXSTRICTRC_VAL(rcStrict);
3935	if (RT_UNLIKELY(rc != VINF_SUCCESS))
3936	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
3937	/* RIP updated by EMInterpretInstruction(). */
3938	}
3939	}
3940
3941	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
3942	return rc;
3943	}
3944
3945
3946	/**
3947	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
3948	*/
3949	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3950	{
3951	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3952	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
3953
3954	/* We should -not- get this VM-exit if the guest is debugging. */
3955	if (CPUMIsGuestDebugStateActive(pVCpu))
3956	{
3957	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx));
3958	return VERR_SVM_UNEXPECTED_EXIT;
3959	}
3960
3961	if ( !DBGFIsStepping(pVCpu)
3962	&& !CPUMIsHyperDebugStateActive(pVCpu))
3963	{
3964	/* Don't intercept DRx read and writes. */
3965	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3966	pVmcb->ctrl.u16InterceptRdDRx = 0;
3967	pVmcb->ctrl.u16InterceptWrDRx = 0;
3968	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3969
3970	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
3971	PVM pVM = pVCpu->CTX_SUFF(pVM);
3972	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3973	AssertRC(rc);
3974	Assert(CPUMIsGuestDebugStateActive(pVCpu));
3975
3976	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
3977	return rc;
3978	}
3979
3980	/** @todo Decode assist. */
3981	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3982	int rc = VBOXSTRICTRC_VAL(rc2);
3983	if (RT_LIKELY(rc == VINF_SUCCESS))
3984	{
3985	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
3986	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3987	}
3988	else
3989	Assert(rc == VERR_EM_INTERPRETER);
3990	return rc;
3991	}
3992
3993
3994	/**
3995	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
3996	*/
3997	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3998	{
3999	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4000	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4001	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4002	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4003	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4004	return rc;
4005	}
4006
4007
4008	/**
4009	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4010	*/
4011	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4012	{
4013	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4014
4015	/* I/O operation lookup arrays. */
4016	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4017	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4018	the result (in AL/AX/EAX). */
4019	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4020
4021	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4022	PVM pVM = pVCpu->CTX_SUFF(pVM);
4023
4024	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4025	SVMIOIOEXIT IoExitInfo;
4026	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4027	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4028	uint32_t uIOSize = s_aIOSize[uIOWidth];
4029	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4030
4031	if (RT_UNLIKELY(!uIOSize))
4032	{
4033	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4034	return VERR_EM_INTERPRETER;
4035	}
4036
4037	int rc;
4038	if (IoExitInfo.n.u1STR)
4039	{
4040	/* INS/OUTS - I/O String instruction. */
4041	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4042
4043	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4044	* in EXITINFO1? Investigate once this thing is up and running. */
4045
4046	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4047	if (rc == VINF_SUCCESS)
4048	{
4049	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4050	{
4051	VBOXSTRICTRC rc2 = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4052	(DISCPUMODE)pDis->uAddrMode, uIOSize);
4053	rc = VBOXSTRICTRC_VAL(rc2);
4054	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4055	}
4056	else
4057	{
4058	VBOXSTRICTRC rc2 = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4059	(DISCPUMODE)pDis->uAddrMode, uIOSize);
4060	rc = VBOXSTRICTRC_VAL(rc2);
4061	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4062	}
4063	}
4064	else
4065	rc = VINF_EM_RAW_EMULATE_INSTR;
4066	}
4067	else
4068	{
4069	/* IN/OUT - I/O instruction. */
4070	Assert(!IoExitInfo.n.u1REP);
4071
4072	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4073	{
4074	VBOXSTRICTRC rc2 = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
4075	rc = VBOXSTRICTRC_VAL(rc2);
4076	if (rc == VINF_IOM_R3_IOPORT_WRITE)
4077	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
4078
4079	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4080	}
4081	else
4082	{
4083	uint32_t u32Val = 0;
4084
4085	VBOXSTRICTRC rc2 = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, uIOSize);
4086	rc = VBOXSTRICTRC_VAL(rc2);
4087	if (IOM_SUCCESS(rc))
4088	{
4089	/* Save result of I/O IN instr. in AL/AX/EAX. */
4090	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4091	}
4092	else if (rc == VINF_IOM_R3_IOPORT_READ)
4093	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
4094
4095	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4096	}
4097	}
4098
4099	if (IOM_SUCCESS(rc))
4100	{
4101	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4102	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4103
4104	if (RT_LIKELY(rc == VINF_SUCCESS))
4105	{
4106	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
4107	/** @todo This is inefficient and wrong according to intel and amd specs
4108	* (regardless of which is correct). See the same code in the VT-x case.
4109	* write testcase and refactor the code to use a mostly shared
4110	* implementation after the initial DR7/CR4 checks. */
4111	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
4112	{
4113	/* I/O breakpoint length, in bytes. */
4114	static uint32_t const s_aIOBPLen[4] = { 1, 2, 0, 4 };
4115
4116	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4117	for (unsigned i = 0; i < 4; i++)
4118	{
4119	unsigned uBPLen = s_aIOBPLen[X86_DR7_GET_LEN(pCtx->dr[7], i)];
4120
4121	if ( IoExitInfo.n.u16Port >= pCtx->dr[i]
4122	&& IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen
4123	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
4124	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
4125	{
4126	Assert(CPUMIsGuestDebugStateActive(pVCpu));
4127
4128	/* Clear all breakpoint status flags and set the one we just hit. */
4129	pCtx->dr[6] &= ~(X86_DR6_B0 \| X86_DR6_B1 \| X86_DR6_B2 \| X86_DR6_B3);
4130	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
4131
4132	/*
4133	* Note: AMD64 Architecture Programmer's Manual 13.1:
4134	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
4135	* by software after the contents have been read.
4136	*/
4137	pVmcb->guest.u64DR6 = pCtx->dr[6];
4138
4139	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
4140	pCtx->dr[7] &= ~X86_DR7_GD;
4141
4142	/* Paranoia. */
4143	pCtx->dr[7] &= 0xffffffff; /* Upper 32 bits MBZ. */
4144	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* MBZ. */
4145	pCtx->dr[7] \|= 0x400; /* MB1. */
4146
4147	pVmcb->guest.u64DR7 = pCtx->dr[7];
4148	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4149
4150	/* Inject the debug exception. */
4151	hmR0SvmSetPendingXcptDB(pVCpu);
4152	break;
4153	}
4154	}
4155	}
4156	}
4157	}
4158
4159	#ifdef VBOX_STRICT
4160	if (rc == VINF_IOM_R3_IOPORT_READ)
4161	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4162	else if (rc == VINF_IOM_R3_IOPORT_WRITE)
4163	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4164	else
4165	{
4166	AssertMsg( RT_FAILURE(rc)
4167	\|\| rc == VINF_SUCCESS
4168	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
4169	\|\| rc == VINF_EM_RAW_GUEST_TRAP
4170	\|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
4171	}
4172	#endif
4173	return rc;
4174	}
4175
4176
4177	/**
4178	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4179	* #VMEXIT.
4180	*/
4181	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4182	{
4183	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4184	PVM pVM = pVCpu->CTX_SUFF(pVM);
4185	Assert(pVM->hm.s.fNestedPaging);
4186
4187	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4188
4189	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4190	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4191	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4192	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4193
4194	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4195
4196	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4197	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4198	if ( pVM->hm.s.fTRPPatchingAllowed
4199	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4200	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4201	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4202	&& !CPUMGetGuestCPL(pVCpu)
4203	&& !CPUMIsGuestInLongModeEx(pCtx)
4204	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4205	{
4206	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4207	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4208
4209	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4210	{
4211	/* Only attempt to patch the instruction once. */
4212	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4213	if (!pPatch)
4214	return VINF_EM_HM_PATCH_TPR_INSTR;
4215	}
4216	}
4217	#endif
4218
4219	/*
4220	* Determine the nested paging mode.
4221	*/
4222	PGMMODE enmNestedPagingMode;
4223	#if HC_ARCH_BITS == 32
4224	if (CPUMIsGuestInLongModeEx(pCtx))
4225	enmNestedPagingMode = PGMMODE_AMD64_NX;
4226	else
4227	#endif
4228	enmNestedPagingMode = PGMGetHostMode(pVM);
4229
4230	/*
4231	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4232	*/
4233	int rc;
4234	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4235	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4236	{
4237	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4238	u32ErrCode);
4239	rc = VBOXSTRICTRC_VAL(rc2);
4240
4241	/*
4242	* If we succeed, resume guest execution.
4243	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4244	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4245	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4246	* weird case. See @bugref{6043}.
4247	*/
4248	if ( rc == VINF_SUCCESS
4249	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4250	\|\| rc == VERR_PAGE_NOT_PRESENT)
4251	{
4252	/* Successfully handled MMIO operation. */
4253	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4254	rc = VINF_SUCCESS;
4255	}
4256	return rc;
4257	}
4258
4259	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4260	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4261	TRPMResetTrap(pVCpu);
4262
4263	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4264
4265	/*
4266	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4267	*/
4268	if ( rc == VINF_SUCCESS
4269	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4270	\|\| rc == VERR_PAGE_NOT_PRESENT)
4271	{
4272	/* We've successfully synced our shadow page tables. */
4273	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4274	rc = VINF_SUCCESS;
4275	}
4276
4277	return rc;
4278	}
4279
4280
4281	/**
4282	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4283	*/
4284	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4285	{
4286	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4287
4288	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4289	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4290	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4291
4292	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4293	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4294	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4295
4296	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4297	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4298	return VINF_SUCCESS;
4299	}
4300
4301
4302	/**
4303	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4304	*/
4305	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4306	{
4307	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4308
4309	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4310	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4311	#endif
4312
4313	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4314	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4315	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4316	&& pVCpu->hm.s.Event.fPending)
4317	{
4318	/*
4319	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4320	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4321	* when the recompiler restarts the instruction.
4322	*/
4323	SVMEVENT Event;
4324	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4325	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4326	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4327	{
4328	pVCpu->hm.s.Event.fPending = false;
4329	}
4330	else
4331	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4332	}
4333
4334	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4335	* emulation. */
4336	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4337	return VERR_EM_INTERPRETER;
4338	}
4339
4340
4341	/**
4342	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4343	*/
4344	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4345	{
4346	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4347
4348	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4349	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4350	hmR0SvmSetPendingXcptUD(pVCpu);
4351	return VINF_SUCCESS;
4352	}
4353
4354
4355	/**
4356	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4357	* #VMEXIT.
4358	*/
4359	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4360	{
4361	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4362
4363	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4364
4365	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4366	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4367	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4368	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4369	PVM pVM = pVCpu->CTX_SUFF(pVM);
4370
4371	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4372	if (pVM->hm.s.fNestedPaging)
4373	{
4374	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4375	if (!pSvmTransient->fVectoringPF)
4376	{
4377	/* A genuine guest #PF, reflect it to the guest. */
4378	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4379	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4380	uFaultAddress, u32ErrCode));
4381	}
4382	else
4383	{
4384	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4385	hmR0SvmSetPendingXcptDF(pVCpu);
4386	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4387	}
4388	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4389	return VINF_SUCCESS;
4390	}
4391	#endif
4392
4393	Assert(!pVM->hm.s.fNestedPaging);
4394
4395	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4396	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4397	if ( pVM->hm.s.fTRPPatchingAllowed
4398	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4399	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
4400	&& !CPUMGetGuestCPL(pVCpu)
4401	&& !CPUMIsGuestInLongModeEx(pCtx)
4402	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4403	{
4404	RTGCPHYS GCPhysApicBase;
4405	GCPhysApicBase = pCtx->msrApicBase;
4406	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4407
4408	/* Check if the page at the fault-address is the APIC base. */
4409	RTGCPHYS GCPhysPage;
4410	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4411	if ( rc2 == VINF_SUCCESS
4412	&& GCPhysPage == GCPhysApicBase)
4413	{
4414	/* Only attempt to patch the instruction once. */
4415	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4416	if (!pPatch)
4417	return VINF_EM_HM_PATCH_TPR_INSTR;
4418	}
4419	}
4420	#endif
4421
4422	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4423	pCtx->rip, u32ErrCode, pCtx->cr3));
4424
4425	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4426	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4427
4428	Log4(("#PF rc=%Rrc\n", rc));
4429
4430	if (rc == VINF_SUCCESS)
4431	{
4432	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4433	TRPMResetTrap(pVCpu);
4434	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4435	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4436	return rc;
4437	}
4438	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4439	{
4440	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4441
4442	if (!pSvmTransient->fVectoringPF)
4443	{
4444	/* It's a guest page fault and needs to be reflected to the guest. */
4445	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4446	TRPMResetTrap(pVCpu);
4447	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4448	}
4449	else
4450	{
4451	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4452	TRPMResetTrap(pVCpu);
4453	hmR0SvmSetPendingXcptDF(pVCpu);
4454	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4455	}
4456
4457	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4458	return VINF_SUCCESS;
4459	}
4460
4461	TRPMResetTrap(pVCpu);
4462	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4463	return rc;
4464	}
4465
4466
4467	/**
4468	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4469	* Conditional #VMEXIT.
4470	*/
4471	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4472	{
4473	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4474
4475	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4476
4477	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4478	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4479	#endif
4480
4481	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4482	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4483	if (rc == VINF_SUCCESS)
4484	{
4485	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4486	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4487	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4488	return VINF_SUCCESS;
4489	}
4490
4491	/* Forward #NM to the guest. */
4492	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4493	hmR0SvmSetPendingXcptNM(pVCpu);
4494	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4495	return VINF_SUCCESS;
4496	}
4497
4498
4499	/**
4500	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4501	* Conditional #VMEXIT.
4502	*/
4503	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4504	{
4505	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4506
4507	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4508
4509	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4510
4511	if (!(pCtx->cr0 & X86_CR0_NE))
4512	{
4513	/* Old-style FPU error reporting needs some extra work. */
4514	/** @todo don't fall back to the recompiler, but do it manually. */
4515	return VERR_EM_INTERPRETER;
4516	}
4517
4518	hmR0SvmSetPendingXcptMF(pVCpu);
4519	return VINF_SUCCESS;
4520	}
4521
4522
4523	/**
4524	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4525	* #VMEXIT.
4526	*/
4527	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4528	{
4529	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4530
4531	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4532
4533	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4534
4535	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4536	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4537	PVM pVM = pVCpu->CTX_SUFF(pVM);
4538	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
4539	if (rc == VINF_EM_RAW_GUEST_TRAP)
4540	{
4541	/* Reflect the exception back to the guest. */
4542	hmR0SvmSetPendingXcptDB(pVCpu);
4543	rc = VINF_SUCCESS;
4544	}
4545
4546	return rc;
4547	}
4548
4549	/** @} */
4550

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 47652

Download in other formats: