HMSVMR0.cpp@ 47989

Last change on this file since 47989 was 47989, checked in by vboxsync, 11 years ago
VMM/VMMR0: Preemption hooks implemented and enabled for Solaris and Linux hosts.
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1	/* $Id: HMSVMR0.cpp 47989 2013-08-22 13:56:52Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HMSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
38	#endif
39
40
41	/*******************************************************************************
42	* Defined Constants And Macros *
43	*******************************************************************************/
44	#ifdef VBOX_WITH_STATISTICS
45	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
46	if ((u64ExitCode) == SVM_EXIT_NPF) \
47	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
48	else \
49	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
50	} while (0)
51	#else
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
53	#endif
54
55	/** If we decide to use a function table approach this can be useful to
56	* switch to a "static DECLCALLBACK(int)". */
57	#define HMSVM_EXIT_DECL static int
58
59
60	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
61	*
62	* The CPU format of the segment attribute is described in X86DESCATTRBITS
63	* which is 16-bits (i.e. includes 4 bits of the segment limit).
64	*
65	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
66	* only the attribute bits and nothing else). Upper 4-bits are unused.
67	*
68	* @{ */
69	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
70	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
71	/** @} */
72
73
74	/** @name Macros for loading, storing segment registers to/from the VMCB.
75	* @{ */
76	#define HMSVM_LOAD_SEG_REG(REG, reg) \
77	do \
78	{ \
79	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
80	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
81	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
82	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
83	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
84	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
85	} while (0)
86
87	#define HMSVM_SAVE_SEG_REG(REG, reg) \
88	do \
89	{ \
90	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
92	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
93	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
94	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
95	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
96	} while (0)
97	/** @} */
98
99
100	/** Macro for checking and returning from the using function for
101	* \#VMEXIT intercepts that maybe caused during delivering of another
102	* event in the guest. */
103	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
104	do \
105	{ \
106	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
107	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
108	return VINF_SUCCESS; \
109	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
110	return rc; \
111	} while (0)
112
113	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
114	* instruction that exited. */
115	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
116	do { \
117	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
118	(a_rc) = VINF_EM_DBG_STEPPED; \
119	} while (0)
120
121	/** Assert that preemption is disabled or covered by thread-context hooks. */
122	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
123	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
124
125	/** Assert that we haven't migrated CPUs when thread-context hooks are not
126	* used. */
127	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
128	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
129	("Illegal migration! Entered on CPU %u Current %u\n", \
130	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
131
132	/** Exception bitmap mask for all contributory exceptions.
133	*
134	* Page fault is deliberately excluded here as it's conditional as to whether
135	* it's contributory or benign. Page faults are handled separately.
136	*/
137	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
138	\| RT_BIT(X86_XCPT_DE))
139
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG uEFlags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
211	bool fRestoreTscAuxMsr;
212	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
213	* contributary exception or a page-fault. */
214	bool fVectoringPF;
215	/** Whether the TSC offset mode needs to be updated. */
216	bool fUpdateTscOffsetting;
217	} SVMTRANSIENT, *PSVMTRANSIENT;
218	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
219	AssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
220	/** @} */
221
222
223	/**
224	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
225	*/
226	typedef enum SVMMSREXITREAD
227	{
228	/** Reading this MSR causes a VM-exit. */
229	SVMMSREXIT_INTERCEPT_READ = 0xb,
230	/** Reading this MSR does not cause a VM-exit. */
231	SVMMSREXIT_PASSTHRU_READ
232	} SVMMSREXITREAD;
233
234	/**
235	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
236	*/
237	typedef enum SVMMSREXITWRITE
238	{
239	/** Writing to this MSR causes a VM-exit. */
240	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
241	/** Writing to this MSR does not cause a VM-exit. */
242	SVMMSREXIT_PASSTHRU_WRITE
243	} SVMMSREXITWRITE;
244
245
246	/*******************************************************************************
247	* Internal Functions *
248	*******************************************************************************/
249	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
250	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
251	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
252
253	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
257	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
258	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
259	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
263	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
264	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
265	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
266	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
267	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
268	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
269	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
270	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
271	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
272	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
273	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
274	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
275	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
276	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
277	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
278	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
279	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
280
281	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
282
283
284	/*******************************************************************************
285	* Global Variables *
286	*******************************************************************************/
287	/** Ring-0 memory object for the IO bitmap. */
288	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
289	/** Physical address of the IO bitmap. */
290	RTHCPHYS g_HCPhysIOBitmap = 0;
291	/** Virtual address of the IO bitmap. */
292	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
293
294
295	/**
296	* Sets up and activates AMD-V on the current CPU.
297	*
298	* @returns VBox status code.
299	* @param pCpu Pointer to the CPU info struct.
300	* @param pVM Pointer to the VM (can be NULL after a resume!).
301	* @param pvCpuPage Pointer to the global CPU page.
302	* @param HCPhysCpuPage Physical address of the global CPU page.
303	*/
304	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
305	{
306	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
307	AssertReturn( HCPhysCpuPage
308	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
309	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
310
311	/*
312	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
313	*/
314	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
315	if (u64HostEfer & MSR_K6_EFER_SVME)
316	{
317	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
318	if ( pVM
319	&& pVM->hm.s.svm.fIgnoreInUseError)
320	{
321	pCpu->fIgnoreAMDVInUseError = true;
322	}
323
324	if (!pCpu->fIgnoreAMDVInUseError)
325	return VERR_SVM_IN_USE;
326	}
327
328	/* Turn on AMD-V in the EFER MSR. */
329	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
330
331	/* Write the physical page address where the CPU will store the host state while executing the VM. */
332	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
333
334	/*
335	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
336	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
337	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
338	* to flush the TLB with before using a new ASID.
339	*/
340	pCpu->fFlushAsidBeforeUse = true;
341
342	/*
343	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
344	*/
345	++pCpu->cTlbFlushes;
346
347	return VINF_SUCCESS;
348	}
349
350
351	/**
352	* Deactivates AMD-V on the current CPU.
353	*
354	* @returns VBox status code.
355	* @param pCpu Pointer to the CPU info struct.
356	* @param pvCpuPage Pointer to the global CPU page.
357	* @param HCPhysCpuPage Physical address of the global CPU page.
358	*/
359	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
360	{
361	AssertReturn( HCPhysCpuPage
362	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
363	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
364	NOREF(pCpu);
365
366	/* Turn off AMD-V in the EFER MSR. */
367	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
368	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
369
370	/* Invalidate host state physical address. */
371	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
372
373	return VINF_SUCCESS;
374	}
375
376
377	/**
378	* Does global AMD-V initialization (called during module initialization).
379	*
380	* @returns VBox status code.
381	*/
382	VMMR0DECL(int) SVMR0GlobalInit(void)
383	{
384	/*
385	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
386	* once globally here instead of per-VM.
387	*/
388	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
389	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
390	if (RT_FAILURE(rc))
391	return rc;
392
393	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
394	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
395
396	/* Set all bits to intercept all IO accesses. */
397	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
398	return VINF_SUCCESS;
399	}
400
401
402	/**
403	* Does global AMD-V termination (called during module termination).
404	*/
405	VMMR0DECL(void) SVMR0GlobalTerm(void)
406	{
407	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
408	{
409	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
410	g_pvIOBitmap = NULL;
411	g_HCPhysIOBitmap = 0;
412	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
413	}
414	}
415
416
417	/**
418	* Frees any allocated per-VCPU structures for a VM.
419	*
420	* @param pVM Pointer to the VM.
421	*/
422	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
423	{
424	for (uint32_t i = 0; i < pVM->cCpus; i++)
425	{
426	PVMCPU pVCpu = &pVM->aCpus[i];
427	AssertPtr(pVCpu);
428
429	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
430	{
431	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
432	pVCpu->hm.s.svm.pvVmcbHost = 0;
433	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
434	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
435	}
436
437	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
438	{
439	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
440	pVCpu->hm.s.svm.pvVmcb = 0;
441	pVCpu->hm.s.svm.HCPhysVmcb = 0;
442	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
443	}
444
445	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
446	{
447	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
448	pVCpu->hm.s.svm.pvMsrBitmap = 0;
449	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
450	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
451	}
452	}
453	}
454
455
456	/**
457	* Does per-VM AMD-V initialization.
458	*
459	* @returns VBox status code.
460	* @param pVM Pointer to the VM.
461	*/
462	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
463	{
464	int rc = VERR_INTERNAL_ERROR_5;
465
466	/*
467	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
468	*/
469	uint32_t u32Family;
470	uint32_t u32Model;
471	uint32_t u32Stepping;
472	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
473	{
474	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
475	pVM->hm.s.svm.fAlwaysFlushTLB = true;
476	}
477
478	/*
479	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
480	*/
481	for (VMCPUID i = 0; i < pVM->cCpus; i++)
482	{
483	PVMCPU pVCpu = &pVM->aCpus[i];
484	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
485	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
486	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
487	}
488
489	for (VMCPUID i = 0; i < pVM->cCpus; i++)
490	{
491	PVMCPU pVCpu = &pVM->aCpus[i];
492
493	/*
494	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
495	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
496	*/
497	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
498	if (RT_FAILURE(rc))
499	goto failure_cleanup;
500
501	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
502	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
503	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
504	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
505
506	/*
507	* Allocate one page for the guest-state VMCB.
508	*/
509	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
510	if (RT_FAILURE(rc))
511	goto failure_cleanup;
512
513	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
514	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
515	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
516	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
517
518	/*
519	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
520	* SVM to not require one.
521	*/
522	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
523	if (RT_FAILURE(rc))
524	goto failure_cleanup;
525
526	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
527	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
528	/* Set all bits to intercept all MSR accesses (changed later on). */
529	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
530	}
531
532	return VINF_SUCCESS;
533
534	failure_cleanup:
535	hmR0SvmFreeStructs(pVM);
536	return rc;
537	}
538
539
540	/**
541	* Does per-VM AMD-V termination.
542	*
543	* @returns VBox status code.
544	* @param pVM Pointer to the VM.
545	*/
546	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
547	{
548	hmR0SvmFreeStructs(pVM);
549	return VINF_SUCCESS;
550	}
551
552
553	/**
554	* Sets the permission bits for the specified MSR in the MSRPM.
555	*
556	* @param pVCpu Pointer to the VMCPU.
557	* @param uMsr The MSR for which the access permissions are being set.
558	* @param enmRead MSR read permissions.
559	* @param enmWrite MSR write permissions.
560	*/
561	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
562	{
563	unsigned ulBit;
564	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
565
566	/*
567	* Layout:
568	* Byte offset MSR range
569	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
570	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
571	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
572	* 0x1800 - 0x1fff Reserved
573	*/
574	if (uMsr <= 0x00001FFF)
575	{
576	/* Pentium-compatible MSRs. */
577	ulBit = uMsr * 2;
578	}
579	else if ( uMsr >= 0xC0000000
580	&& uMsr <= 0xC0001FFF)
581	{
582	/* AMD Sixth Generation x86 Processor MSRs. */
583	ulBit = (uMsr - 0xC0000000) * 2;
584	pbMsrBitmap += 0x800;
585	}
586	else if ( uMsr >= 0xC0010000
587	&& uMsr <= 0xC0011FFF)
588	{
589	/* AMD Seventh and Eighth Generation Processor MSRs. */
590	ulBit = (uMsr - 0xC0001000) * 2;
591	pbMsrBitmap += 0x1000;
592	}
593	else
594	{
595	AssertFailed();
596	return;
597	}
598
599	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
600	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
601	ASMBitSet(pbMsrBitmap, ulBit);
602	else
603	ASMBitClear(pbMsrBitmap, ulBit);
604
605	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
606	ASMBitSet(pbMsrBitmap, ulBit + 1);
607	else
608	ASMBitClear(pbMsrBitmap, ulBit + 1);
609
610	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
611	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
612	}
613
614
615	/**
616	* Sets up AMD-V for the specified VM.
617	* This function is only called once per-VM during initalization.
618	*
619	* @returns VBox status code.
620	* @param pVM Pointer to the VM.
621	*/
622	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
623	{
624	int rc = VINF_SUCCESS;
625
626	AssertReturn(pVM, VERR_INVALID_PARAMETER);
627	Assert(pVM->hm.s.svm.fSupported);
628
629	for (VMCPUID i = 0; i < pVM->cCpus; i++)
630	{
631	PVMCPU pVCpu = &pVM->aCpus[i];
632	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
633
634	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
635
636	/* Trap exceptions unconditionally (debug purposes). */
637	#ifdef HMSVM_ALWAYS_TRAP_PF
638	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
639	#endif
640	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
641	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
642	pVmcb->ctrl.u32InterceptException \|= 0
643	\| RT_BIT(X86_XCPT_BP)
644	\| RT_BIT(X86_XCPT_DB)
645	\| RT_BIT(X86_XCPT_DE)
646	\| RT_BIT(X86_XCPT_NM)
647	\| RT_BIT(X86_XCPT_UD)
648	\| RT_BIT(X86_XCPT_NP)
649	\| RT_BIT(X86_XCPT_SS)
650	\| RT_BIT(X86_XCPT_GP)
651	\| RT_BIT(X86_XCPT_PF)
652	\| RT_BIT(X86_XCPT_MF)
653	;
654	#endif
655
656	/* Set up unconditional intercepts and conditions. */
657	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
658	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
659	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
660	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
661	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
662	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
663	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
664	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
665	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
666	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
667	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
668	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
669
670	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
671	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
672	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
673	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
674	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
675	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
676	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
677	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
678	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
679	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
680
681	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
682	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
683
684	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
685	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
686
687	/* Intercept all DRx reads and writes by default. Changed later on. */
688	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
689	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
690
691	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
692	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
693
694	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
695	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
696	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
697
698	/* Set IO and MSR bitmap permission bitmap physical addresses. */
699	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
700	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
701
702	/* No LBR virtualization. */
703	pVmcb->ctrl.u64LBRVirt = 0;
704
705	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
706	pVmcb->ctrl.u64VmcbCleanBits = 0;
707
708	/* The host ASID MBZ, for the guest start with 1. */
709	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
710
711	/*
712	* Setup the PAT MSR (applicable for Nested Paging only).
713	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
714	* so choose type 6 for all PAT slots.
715	*/
716	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
717
718	/* Without Nested Paging, we need additionally intercepts. */
719	if (!pVM->hm.s.fNestedPaging)
720	{
721	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
722	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
723	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
724
725	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
726	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
727	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
728
729	/* Page faults must be intercepted to implement shadow paging. */
730	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
731	}
732
733	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
734	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
735	#endif
736
737	/*
738	* The following MSRs are saved/restored automatically during the world-switch.
739	* Don't intercept guest read/write accesses to these MSRs.
740	*/
741	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
742	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
743	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
744	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
745	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
746	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
747	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
748	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
749	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
750	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
751	}
752
753	return rc;
754	}
755
756
757	/**
758	* Invalidates a guest page by guest virtual address.
759	*
760	* @returns VBox status code.
761	* @param pVM Pointer to the VM.
762	* @param pVCpu Pointer to the VMCPU.
763	* @param GCVirt Guest virtual address of the page to invalidate.
764	*/
765	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
766	{
767	AssertReturn(pVM, VERR_INVALID_PARAMETER);
768	Assert(pVM->hm.s.svm.fSupported);
769
770	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
771
772	/* Skip it if a TLB flush is already pending. */
773	if (!fFlushPending)
774	{
775	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
776
777	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
778	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
779
780	#if HC_ARCH_BITS == 32
781	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
782	if (CPUMIsGuestInLongMode(pVCpu))
783	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
784	else
785	#endif
786	{
787	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
788	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
789	}
790	}
791	return VINF_SUCCESS;
792	}
793
794
795	/**
796	* Flushes the appropriate tagged-TLB entries.
797	*
798	* @param pVM Pointer to the VM.
799	* @param pVCpu Pointer to the VMCPU.
800	*/
801	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
802	{
803	PVM pVM = pVCpu->CTX_SUFF(pVM);
804	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
805	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
806
807	/*
808	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
809	* This can happen both for start & resume due to long jumps back to ring-3.
810	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
811	* so we cannot reuse the ASIDs without flushing.
812	*/
813	bool fNewAsid = false;
814	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
815	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
816	{
817	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
818	pVCpu->hm.s.fForceTLBFlush = true;
819	fNewAsid = true;
820	}
821
822	/* Set TLB flush state as checked until we return from the world switch. */
823	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
824
825	/* Check for explicit TLB shootdowns. */
826	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
827	{
828	pVCpu->hm.s.fForceTLBFlush = true;
829	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
830	}
831
832	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
833	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
834
835	if (pVM->hm.s.svm.fAlwaysFlushTLB)
836	{
837	/*
838	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
839	*/
840	pCpu->uCurrentAsid = 1;
841	pVCpu->hm.s.uCurrentAsid = 1;
842	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
843	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
844	}
845	else if (pVCpu->hm.s.fForceTLBFlush)
846	{
847	if (fNewAsid)
848	{
849	++pCpu->uCurrentAsid;
850	bool fHitASIDLimit = false;
851	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
852	{
853	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
854	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
855	fHitASIDLimit = true;
856
857	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
858	{
859	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
860	pCpu->fFlushAsidBeforeUse = true;
861	}
862	else
863	{
864	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
865	pCpu->fFlushAsidBeforeUse = false;
866	}
867	}
868
869	if ( !fHitASIDLimit
870	&& pCpu->fFlushAsidBeforeUse)
871	{
872	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
873	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
874	else
875	{
876	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
877	pCpu->fFlushAsidBeforeUse = false;
878	}
879	}
880
881	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
882	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
883	}
884	else
885	{
886	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
887	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
888	else
889	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
890	}
891
892	pVCpu->hm.s.fForceTLBFlush = false;
893	}
894	else
895	{
896	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
897	* not be executed. See hmQueueInvlPage() where it is commented
898	* out. Support individual entry flushing someday. */
899	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
900	{
901	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
902	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
903	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
904	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
905	}
906	}
907
908	pVCpu->hm.s.TlbShootdown.cPages = 0;
909	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
910
911	/* Update VMCB with the ASID. */
912	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
913	{
914	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
915	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
916	}
917
918	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
919	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
920	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
921	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
922	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
923	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
924
925	#ifdef VBOX_WITH_STATISTICS
926	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
927	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
928	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
929	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
930	{
931	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
932	}
933	else
934	{
935	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
936	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
937	}
938	#endif
939	}
940
941
942	/** @name 64-bit guest on 32-bit host OS helper functions.
943	*
944	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
945	* mode (code segment, paging). These wrappers/helpers perform the necessary
946	* bits for the 32->64 switcher.
947	*
948	* @{ */
949	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
950	/**
951	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
952	*
953	* @returns VBox status code.
954	* @param HCPhysVmcbHost Physical address of host VMCB.
955	* @param HCPhysVmcb Physical address of the VMCB.
956	* @param pCtx Pointer to the guest-CPU context.
957	* @param pVM Pointer to the VM.
958	* @param pVCpu Pointer to the VMCPU.
959	*/
960	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
961	{
962	uint32_t aParam[4];
963	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
964	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
965	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
966	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
967
968	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
969	}
970
971
972	/**
973	* Executes the specified VMRUN handler in 64-bit mode.
974	*
975	* @returns VBox status code.
976	* @param pVM Pointer to the VM.
977	* @param pVCpu Pointer to the VMCPU.
978	* @param pCtx Pointer to the guest-CPU context.
979	* @param enmOp The operation to perform.
980	* @param cbParam Number of parameters.
981	* @param paParam Array of 32-bit parameters.
982	*/
983	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
984	uint32_t *paParam)
985	{
986	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
987	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
988
989	/* Disable interrupts. */
990	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
991
992	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
993	RTCPUID idHostCpu = RTMpCpuId();
994	CPUMR0SetLApic(pVCpu, idHostCpu);
995	#endif
996
997	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
998	CPUMSetHyperEIP(pVCpu, enmOp);
999	for (int i = (int)cbParam - 1; i >= 0; i--)
1000	CPUMPushHyper(pVCpu, paParam[i]);
1001
1002	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1003	/* Call the switcher. */
1004	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1005	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1006
1007	/* Restore interrupts. */
1008	ASMSetFlags(uOldEFlags);
1009	return rc;
1010	}
1011
1012	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1013	/** @} */
1014
1015
1016	/**
1017	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1018	* the corresponding VMCB Clean Bit.
1019	*
1020	* @param pVmcb Pointer to the VMCB.
1021	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1022	*/
1023	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1024	{
1025	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1026	{
1027	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1028	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1029	}
1030	}
1031
1032
1033	/**
1034	* Removes an exception from the intercept-exception bitmap in the VMCB and
1035	* updates the corresponding VMCB Clean Bit.
1036	*
1037	* @param pVmcb Pointer to the VMCB.
1038	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1039	*/
1040	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1041	{
1042	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1043	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1044	{
1045	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1046	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1047	}
1048	#endif
1049	}
1050
1051
1052	/**
1053	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1054	*
1055	* @returns VBox status code.
1056	* @param pVCpu Pointer to the VMCPU.
1057	* @param pVmcb Pointer to the VMCB.
1058	* @param pCtx Pointer the guest-CPU context.
1059	*
1060	* @remarks No-long-jump zone!!!
1061	*/
1062	DECLINLINE(int) hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1063	{
1064	/*
1065	* Guest CR0.
1066	*/
1067	PVM pVM = pVCpu->CTX_SUFF(pVM);
1068	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1069	{
1070	uint64_t u64GuestCR0 = pCtx->cr0;
1071
1072	/* Always enable caching. */
1073	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1074
1075	/*
1076	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1077	*/
1078	if (!pVM->hm.s.fNestedPaging)
1079	{
1080	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1081	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1082	}
1083
1084	/*
1085	* Guest FPU bits.
1086	*/
1087	bool fInterceptNM = false;
1088	bool fInterceptMF = false;
1089	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1090	if (CPUMIsGuestFPUStateActive(pVCpu))
1091	{
1092	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1093	if (!(u64GuestCR0 & X86_CR0_NE))
1094	{
1095	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1096	fInterceptMF = true;
1097	}
1098	}
1099	else
1100	{
1101	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1102	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1103	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1104	}
1105
1106	/*
1107	* Update the exception intercept bitmap.
1108	*/
1109	if (fInterceptNM)
1110	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1111	else
1112	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1113
1114	if (fInterceptMF)
1115	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1116	else
1117	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1118
1119	pVmcb->guest.u64CR0 = u64GuestCR0;
1120	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1121	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1122	}
1123
1124	/*
1125	* Guest CR2.
1126	*/
1127	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1128	{
1129	pVmcb->guest.u64CR2 = pCtx->cr2;
1130	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1131	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1132	}
1133
1134	/*
1135	* Guest CR3.
1136	*/
1137	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1138	{
1139	if (pVM->hm.s.fNestedPaging)
1140	{
1141	PGMMODE enmShwPagingMode;
1142	#if HC_ARCH_BITS == 32
1143	if (CPUMIsGuestInLongModeEx(pCtx))
1144	enmShwPagingMode = PGMMODE_AMD64_NX;
1145	else
1146	#endif
1147	enmShwPagingMode = PGMGetHostMode(pVM);
1148
1149	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1150	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1151	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1152	pVmcb->guest.u64CR3 = pCtx->cr3;
1153	}
1154	else
1155	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1156
1157	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1158	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1159	}
1160
1161	/*
1162	* Guest CR4.
1163	*/
1164	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1165	{
1166	uint64_t u64GuestCR4 = pCtx->cr4;
1167	if (!pVM->hm.s.fNestedPaging)
1168	{
1169	switch (pVCpu->hm.s.enmShadowMode)
1170	{
1171	case PGMMODE_REAL:
1172	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1173	AssertFailed();
1174	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1175
1176	case PGMMODE_32_BIT: /* 32-bit paging. */
1177	u64GuestCR4 &= ~X86_CR4_PAE;
1178	break;
1179
1180	case PGMMODE_PAE: /* PAE paging. */
1181	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1182	/** Must use PAE paging as we could use physical memory > 4 GB */
1183	u64GuestCR4 \|= X86_CR4_PAE;
1184	break;
1185
1186	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1187	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1188	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1189	break;
1190	#else
1191	AssertFailed();
1192	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1193	#endif
1194
1195	default: /* shut up gcc */
1196	AssertFailed();
1197	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1198	}
1199	}
1200
1201	pVmcb->guest.u64CR4 = u64GuestCR4;
1202	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1203	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1204	}
1205
1206	return VINF_SUCCESS;
1207	}
1208
1209
1210	/**
1211	* Loads the guest segment registers into the VMCB.
1212	*
1213	* @returns VBox status code.
1214	* @param pVCpu Pointer to the VMCPU.
1215	* @param pVmcb Pointer to the VMCB.
1216	* @param pCtx Pointer to the guest-CPU context.
1217	*
1218	* @remarks No-long-jump zone!!!
1219	*/
1220	DECLINLINE(void) hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1221	{
1222	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1223	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1224	{
1225	HMSVM_LOAD_SEG_REG(CS, cs);
1226	HMSVM_LOAD_SEG_REG(SS, ss);
1227	HMSVM_LOAD_SEG_REG(DS, ds);
1228	HMSVM_LOAD_SEG_REG(ES, es);
1229	HMSVM_LOAD_SEG_REG(FS, fs);
1230	HMSVM_LOAD_SEG_REG(GS, gs);
1231
1232	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1233	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1234	}
1235
1236	/* Guest TR. */
1237	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1238	{
1239	HMSVM_LOAD_SEG_REG(TR, tr);
1240	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1241	}
1242
1243	/* Guest LDTR. */
1244	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1245	{
1246	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1247	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1248	}
1249
1250	/* Guest GDTR. */
1251	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1252	{
1253	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1254	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1255	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1256	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1257	}
1258
1259	/* Guest IDTR. */
1260	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1261	{
1262	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1263	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1264	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1265	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1266	}
1267	}
1268
1269
1270	/**
1271	* Loads the guest MSRs into the VMCB.
1272	*
1273	* @param pVCpu Pointer to the VMCPU.
1274	* @param pVmcb Pointer to the VMCB.
1275	* @param pCtx Pointer to the guest-CPU context.
1276	*
1277	* @remarks No-long-jump zone!!!
1278	*/
1279	DECLINLINE(void) hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1280	{
1281	/* Guest Sysenter MSRs. */
1282	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1283	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1284	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1285
1286	/*
1287	* Guest EFER MSR.
1288	* AMD-V requires guest EFER.SVME to be set. Weird. .
1289	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1290	*/
1291	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1292	{
1293	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1294	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1295	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1296	}
1297
1298	/* 64-bit MSRs. */
1299	if (CPUMIsGuestInLongModeEx(pCtx))
1300	{
1301	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1302	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1303	}
1304	else
1305	{
1306	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1307	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1308	{
1309	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1310	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1311	}
1312	}
1313
1314
1315	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1316	* be writable in 32-bit mode. Clarify with AMD spec. */
1317	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1318	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1319	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1320	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1321	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1322	}
1323
1324
1325	/**
1326	* Loads the guest debug registers into the VMCB.
1327	*
1328	* @param pVCpu Pointer to the VMCPU.
1329	* @param pVmcb Pointer to the VMCB.
1330	* @param pCtx Pointer to the guest-CPU context.
1331	*
1332	* @remarks No-long-jump zone!!!
1333	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1334	*/
1335	DECLINLINE(void) hmR0SvmLoadGuestDebugRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1336	{
1337	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1338	return;
1339	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1340	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1341
1342	bool fInterceptDB = false;
1343	bool fInterceptMovDRx = false;
1344
1345	/*
1346	* Anyone single stepping on the host side? If so, we'll have to use the
1347	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1348	* the VMM level like VT-x implementations does.
1349	*/
1350	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1351	if (fStepping)
1352	{
1353	pVCpu->hm.s.fClearTrapFlag = true;
1354	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1355	fInterceptDB = true;
1356	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1357	}
1358
1359	PVM pVM = pVCpu->CTX_SUFF(pVM);
1360	if (fStepping \|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1361	{
1362	/*
1363	* Use the combined guest and host DRx values found in the hypervisor
1364	* register set because the debugger has breakpoints active or someone
1365	* is single stepping on the host side.
1366	*
1367	* Note! DBGF expects a clean DR6 state before executing guest code.
1368	*/
1369	if (!CPUMIsHyperDebugStateActive(pVCpu))
1370	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1371	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1372	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1373
1374	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1375	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1376	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu) )
1377	{
1378	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1379	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1380	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1381	}
1382
1383	/** @todo If we cared, we could optimize to allow the guest to read registers
1384	* with the same values. */
1385	fInterceptDB = true;
1386	fInterceptMovDRx = true;
1387	Log5(("hm: Loaded hyper DRx\n"));
1388	}
1389	else
1390	{
1391	/*
1392	* Update DR6, DR7 with the guest values if necessary.
1393	*/
1394	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1395	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1396	{
1397	pVmcb->guest.u64DR7 = pCtx->dr[7];
1398	pVmcb->guest.u64DR6 = pCtx->dr[6];
1399	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1400	}
1401
1402	/*
1403	* If the guest has enabled debug registers, we need to load them prior to
1404	* executing guest code so they'll trigger at the right time.
1405	*/
1406	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1407	{
1408	if (!CPUMIsGuestDebugStateActive(pVCpu))
1409	{
1410	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1411	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1412	}
1413	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1414	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1415	Log5(("hm: Loaded guest DRx\n"));
1416	}
1417	/*
1418	* If no debugging enabled, we'll lazy load DR0-3.
1419	*/
1420	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1421	fInterceptMovDRx = true;
1422	}
1423
1424	/*
1425	* Set up the intercepts.
1426	*/
1427	if (fInterceptDB)
1428	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1429	else
1430	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1431
1432	if (fInterceptMovDRx)
1433	{
1434	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1435	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1436	{
1437	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1438	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1439	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1440	}
1441	}
1442	else
1443	{
1444	if ( pVmcb->ctrl.u16InterceptRdDRx
1445	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1446	{
1447	pVmcb->ctrl.u16InterceptRdDRx = 0;
1448	pVmcb->ctrl.u16InterceptWrDRx = 0;
1449	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1450	}
1451	}
1452
1453	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1454	}
1455
1456
1457	/**
1458	* Loads the guest APIC state (currently just the TPR).
1459	*
1460	* @returns VBox status code.
1461	* @param pVCpu Pointer to the VMCPU.
1462	* @param pVmcb Pointer to the VMCB.
1463	* @param pCtx Pointer to the guest-CPU context.
1464	*/
1465	DECLINLINE(int) hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1466	{
1467	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1468	return VINF_SUCCESS;
1469
1470	bool fPendingIntr;
1471	uint8_t u8Tpr;
1472	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1473	AssertRCReturn(rc, rc);
1474
1475	/** Assume that we need to trap all TPR accesses and thus need not check on
1476	* every #VMEXIT if we should update the TPR. */
1477	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1478	pVCpu->hm.s.svm.fSyncVTpr = false;
1479
1480	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1481	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1482	{
1483	pCtx->msrLSTAR = u8Tpr;
1484
1485	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1486	if (fPendingIntr)
1487	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1488	else
1489	{
1490	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1491	pVCpu->hm.s.svm.fSyncVTpr = true;
1492	}
1493	}
1494	else
1495	{
1496	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1497	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1498
1499	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1500	if (fPendingIntr)
1501	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1502	else
1503	{
1504	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1505	pVCpu->hm.s.svm.fSyncVTpr = true;
1506	}
1507
1508	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1509	}
1510
1511	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1512	return rc;
1513	}
1514
1515
1516	/**
1517	* Sets up the appropriate function to run guest code.
1518	*
1519	* @returns VBox status code.
1520	* @param pVCpu Pointer to the VMCPU.
1521	* @param pCtx Pointer to the guest-CPU context.
1522	*
1523	* @remarks No-long-jump zone!!!
1524	*/
1525	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1526	{
1527	if (CPUMIsGuestInLongModeEx(pCtx))
1528	{
1529	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1530	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1531	#endif
1532	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1533	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1534	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1535	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1536	#else
1537	/* 64-bit host or hybrid host. */
1538	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1539	#endif
1540	}
1541	else
1542	{
1543	/* Guest is not in long mode, use the 32-bit handler. */
1544	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1545	}
1546	return VINF_SUCCESS;
1547	}
1548
1549
1550	/**
1551	* Enters the AMD-V session.
1552	*
1553	* @returns VBox status code.
1554	* @param pVM Pointer to the VM.
1555	* @param pVCpu Pointer to the VMCPU.
1556	* @param pCpu Pointer to the CPU info struct.
1557	*/
1558	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1559	{
1560	AssertPtr(pVM);
1561	AssertPtr(pVCpu);
1562	Assert(pVM->hm.s.svm.fSupported);
1563	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1564	NOREF(pCpu);
1565
1566	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1567
1568	pVCpu->hm.s.fLeaveDone = false;
1569	return VINF_SUCCESS;
1570	}
1571
1572
1573	/**
1574	* Leaves the AMD-V session.
1575	*
1576	* @returns VBox status code.
1577	* @param pVM Pointer to the VM.
1578	* @param pVCpu Pointer to the VMCPU.
1579	* @param pCtx Pointer to the guest-CPU context.
1580	*/
1581	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1582	{
1583	NOREF(pVM);
1584	NOREF(pVCpu);
1585	NOREF(pCtx);
1586
1587	/* Nothing to do here. Everything is taken care of in hmR0SvmLeave(). */
1588	return VINF_SUCCESS;
1589	}
1590
1591
1592	/**
1593	* Thread-context callback for AMD-V.
1594	*
1595	* @param enmEvent The thread-context event.
1596	* @param pVCpu Pointer to the VMCPU.
1597	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1598	*/
1599	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1600	{
1601	switch (enmEvent)
1602	{
1603	case RTTHREADCTXEVENT_PREEMPTING:
1604	{
1605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1606	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1607	VMCPU_ASSERT_EMT(pVCpu);
1608
1609	PVM pVM = pVCpu->CTX_SUFF(pVM);
1610	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1611	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1612
1613	hmR0SvmLeave(pVM, pVCpu, pCtx);
1614
1615	int rc = HMR0LeaveEx(pVCpu); /* Leave HM context, takes care of local init (term). */
1616	AssertRC(rc); NOREF(rc);
1617
1618	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1619	break;
1620	}
1621
1622	case RTTHREADCTXEVENT_RESUMED:
1623	{
1624	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1625	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1626	VMCPU_ASSERT_EMT(pVCpu);
1627
1628	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1629
1630	/*
1631	* Initialize the bare minimum state required for HM. This takes care of
1632	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1633	*/
1634	HMR0EnterEx(pVCpu);
1635	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_GUEST_CR0));
1636
1637	pVCpu->hm.s.fLeaveDone = false;
1638	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1639	break;
1640	}
1641
1642	default:
1643	break;
1644	}
1645	}
1646
1647
1648	/**
1649	* Saves the host state.
1650	*
1651	* @returns VBox status code.
1652	* @param pVM Pointer to the VM.
1653	* @param pVCpu Pointer to the VMCPU.
1654	*
1655	* @remarks No-long-jump zone!!!
1656	*/
1657	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1658	{
1659	NOREF(pVM);
1660	NOREF(pVCpu);
1661	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1662	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1663	return VINF_SUCCESS;
1664	}
1665
1666
1667	/**
1668	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1669	* fields on every successful VM-entry.
1670	*
1671	* Sets up the appropriate VMRUN function to execute guest code based
1672	* on the guest CPU mode.
1673	*
1674	* @returns VBox status code.
1675	* @param pVM Pointer to the VM.
1676	* @param pVCpu Pointer to the VMCPU.
1677	* @param pMixedCtx Pointer to the guest-CPU context.
1678	*
1679	* @remarks No-long-jump zone!!!
1680	*/
1681	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1682	{
1683	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1684	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1685
1686	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1687
1688	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1689	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1690
1691	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1692	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1693
1694	pVmcb->guest.u64RIP = pCtx->rip;
1695	pVmcb->guest.u64RSP = pCtx->rsp;
1696	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1697	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1698	pVmcb->guest.u64RAX = pCtx->rax;
1699
1700	/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
1701	hmR0SvmLoadGuestDebugRegs(pVCpu, pVmcb, pCtx);
1702
1703	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1704	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1705
1706	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1707	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1708
1709	/* Clear any unused and reserved bits. */
1710	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1711	\| HM_CHANGED_GUEST_RSP
1712	\| HM_CHANGED_GUEST_RFLAGS
1713	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1714	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1715	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1716	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1717	\| HM_CHANGED_SVM_RESERVED2
1718	\| HM_CHANGED_SVM_RESERVED3);
1719
1720	AssertMsg(!pVCpu->hm.s.fContextUseFlags,
1721	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1722	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1723
1724	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1725
1726	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1727	return rc;
1728	}
1729
1730
1731	/**
1732	* Loads the guest state on the way from ring-3.
1733	*
1734	* @returns VBox status code.
1735	* @param pVM Pointer to the VM.
1736	* @param pVCpu Pointer to the VMCPU.
1737	* @param pCtx Pointer to the guest-CPU context.
1738	*
1739	* @remarks No-long-jump zone!!!
1740	*/
1741	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1742	{
1743	/*
1744	* Avoid reloading the guest state on longjmp reentrants and do it lazily just before executing the guest.
1745	* This only helps when we get rescheduled more than once to a different host CPU on a longjmp trip before
1746	* finally executing guest code.
1747	*/
1748	return VINF_SUCCESS;
1749	}
1750
1751
1752	/**
1753	* Saves the entire guest state from the VMCB into the
1754	* guest-CPU context. Currently there is no residual state left in the CPU that
1755	* is not updated in the VMCB.
1756	*
1757	* @returns VBox status code.
1758	* @param pVCpu Pointer to the VMCPU.
1759	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1760	* out-of-sync. Make sure to update the required fields
1761	* before using them.
1762	*/
1763	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1764	{
1765	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1766
1767	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1768
1769	pMixedCtx->rip = pVmcb->guest.u64RIP;
1770	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1771	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1772	pMixedCtx->rax = pVmcb->guest.u64RAX;
1773
1774	/*
1775	* Guest interrupt shadow.
1776	*/
1777	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1778	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1779	else
1780	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1781
1782	/*
1783	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1784	*/
1785	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1786
1787	/*
1788	* Guest MSRs.
1789	*/
1790	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1791	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1792	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1793	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1794	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1795	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1796	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1797	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1798
1799	/*
1800	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1801	*/
1802	HMSVM_SAVE_SEG_REG(CS, cs);
1803	HMSVM_SAVE_SEG_REG(SS, ss);
1804	HMSVM_SAVE_SEG_REG(DS, ds);
1805	HMSVM_SAVE_SEG_REG(ES, es);
1806	HMSVM_SAVE_SEG_REG(FS, fs);
1807	HMSVM_SAVE_SEG_REG(GS, gs);
1808
1809	/*
1810	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1811	* register (yet).
1812	*/
1813	/** @todo SELM might need to be fixed as it too should not care about the
1814	* granularity bit. See @bugref{6785}. */
1815	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1816	&& pMixedCtx->cs.Attr.n.u1Present
1817	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1818	{
1819	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1820	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1821	}
1822
1823	#ifdef VBOX_STRICT
1824	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1825	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1826	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1827	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1828	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1829	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1830	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1831
1832	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1833	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1834	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1835	HMSVM_ASSERT_SEG_GRANULARITY(es);
1836	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1837	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1838
1839	# undef HMSVM_ASSERT_SEL_GRANULARITY
1840	#endif
1841
1842	/*
1843	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1844	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1845	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1846	* See AMD spec. 15.5.1 "Basic operation".
1847	*/
1848	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1849	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1850
1851	/*
1852	* Guest Descriptor-Table registers.
1853	*/
1854	HMSVM_SAVE_SEG_REG(TR, tr);
1855	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1856	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1857	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1858
1859	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1860	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1861
1862	/*
1863	* Guest Debug registers.
1864	*/
1865	if (!CPUMIsHyperDebugStateActive(pVCpu))
1866	{
1867	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1868	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1869	}
1870	else
1871	{
1872	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
1873	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
1874	}
1875
1876	/*
1877	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1878	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1879	*/
1880	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1881	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1882	{
1883	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1884	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1885	}
1886	}
1887
1888
1889	/**
1890	* Does the necessary state syncing before returning to ring-3 for any reason
1891	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
1892	*
1893	* @param pVM Pointer to the VM.
1894	* @param pVCpu Pointer to the VMCPU.
1895	* @param pMixedCtx Pointer to the guest-CPU context.
1896	*
1897	* @remarks No-long-jmp zone!!!
1898	*/
1899	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1900	{
1901	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1902	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1903
1904	/* Avoid repeating this work when thread-context hooks are used and we had been preempted before
1905	which would've done this work from the SVMR0ThreadCtxCallback(). */
1906	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1907	bool fPreemptDisabled = false;
1908	if (RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1909	{
1910	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1911	RTThreadPreemptDisable(&PreemptState);
1912	fPreemptDisabled = true;
1913	}
1914
1915	if (!pVCpu->hm.s.fLeaveDone)
1916	{
1917	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1918	if (CPUMIsGuestFPUStateActive(pVCpu))
1919	{
1920	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1921	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1922	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1923	}
1924
1925	/*
1926	* Restore host debug registers if necessary and resync on next R0 reentry.
1927	*/
1928	#ifdef VBOX_STRICT
1929	if (CPUMIsHyperDebugStateActive(pVCpu))
1930	{
1931	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1932	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1933	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1934	}
1935	#endif
1936	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
1937	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1938
1939	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1940	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1941
1942	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
1943	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
1944	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1945	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1946	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1947
1948	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1949
1950	pVCpu->hm.s.fLeaveDone = true;
1951	}
1952
1953	/* Restore preemption if we previous disabled it ourselves. */
1954	if (fPreemptDisabled)
1955	RTThreadPreemptRestore(&PreemptState);
1956	}
1957
1958
1959	/**
1960	* Does the necessary state syncing before doing a longjmp to ring-3.
1961	*
1962	* @param pVM Pointer to the VM.
1963	* @param pVCpu Pointer to the VMCPU.
1964	* @param pCtx Pointer to the guest-CPU context.
1965	*
1966	* @remarks No-long-jmp zone!!!
1967	*/
1968	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1969	{
1970	hmR0SvmLeave(pVM, pVCpu, pCtx);
1971	}
1972
1973
1974	/**
1975	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
1976	* any remaining host state) before we longjump to ring-3 and possibly get
1977	* preempted.
1978	*
1979	* @param pVCpu Pointer to the VMCPU.
1980	* @param enmOperation The operation causing the ring-3 longjump.
1981	* @param pvUser The user argument (pointer to the possibly
1982	* out-of-date guest-CPU context).
1983	*
1984	* @remarks Must never be called with @a enmOperation ==
1985	* VMMCALLRING3_VM_R0_ASSERTION.
1986	*/
1987	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1988	{
1989	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
1990	Assert(pVCpu);
1991	Assert(pvUser);
1992	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1993	HMSVM_ASSERT_PREEMPT_SAFE();
1994
1995	VMMRZCallRing3Disable(pVCpu);
1996	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1997
1998	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
1999	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2000
2001	VMMRZCallRing3Enable(pVCpu);
2002	}
2003
2004
2005	/**
2006	* Take necessary actions before going back to ring-3.
2007	*
2008	* An action requires us to go back to ring-3. This function does the necessary
2009	* steps before we can safely return to ring-3. This is not the same as longjmps
2010	* to ring-3, this is voluntary.
2011	*
2012	* @param pVM Pointer to the VM.
2013	* @param pVCpu Pointer to the VMCPU.
2014	* @param pCtx Pointer to the guest-CPU context.
2015	* @param rcExit The reason for exiting to ring-3. Can be
2016	* VINF_VMM_UNKNOWN_RING3_CALL.
2017	*/
2018	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2019	{
2020	Assert(pVM);
2021	Assert(pVCpu);
2022	Assert(pCtx);
2023	HMSVM_ASSERT_PREEMPT_SAFE();
2024
2025	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
2026	{
2027	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
2028	return;
2029	}
2030
2031	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2032	VMMRZCallRing3Disable(pVCpu);
2033	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2034
2035	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2036	if (pVCpu->hm.s.Event.fPending)
2037	{
2038	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2039	Assert(!pVCpu->hm.s.Event.fPending);
2040	}
2041
2042	/* Sync. the necessary state for going back to ring-3. */
2043	hmR0SvmLeave(pVM, pVCpu, pCtx);
2044	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2045
2046	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2047	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2048	\| CPUM_CHANGED_LDTR
2049	\| CPUM_CHANGED_GDTR
2050	\| CPUM_CHANGED_IDTR
2051	\| CPUM_CHANGED_TR
2052	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2053	if ( pVM->hm.s.fNestedPaging
2054	&& CPUMIsGuestPagingEnabledEx(pCtx))
2055	{
2056	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2057	}
2058
2059	/* Make sure we've undo the trap flag if we tried to single step something. */
2060	if (pVCpu->hm.s.fClearTrapFlag)
2061	{
2062	pCtx->eflags.Bits.u1TF = 0;
2063	pVCpu->hm.s.fClearTrapFlag = false;
2064	}
2065
2066	/* On our way back from ring-3 the following needs to be done. */
2067	/** @todo This can change with preemption hooks. */
2068	if (rcExit == VINF_EM_RAW_INTERRUPT)
2069	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
2070	else
2071	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2072
2073	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2074	VMMRZCallRing3Enable(pVCpu);
2075	}
2076
2077
2078	/**
2079	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2080	* intercepts.
2081	*
2082	* @param pVCpu Pointer to the VMCPU.
2083	*
2084	* @remarks No-long-jump zone!!!
2085	*/
2086	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
2087	{
2088	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2089	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
2090	{
2091	uint64_t u64CurTSC = ASMReadTSC();
2092	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
2093	{
2094	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2095	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2096	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2097	}
2098	else
2099	{
2100	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2101	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2102	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
2103	}
2104	}
2105	else
2106	{
2107	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2108	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2109	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2110	}
2111
2112	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2113	}
2114
2115
2116	/**
2117	* Sets an event as a pending event to be injected into the guest.
2118	*
2119	* @param pVCpu Pointer to the VMCPU.
2120	* @param pEvent Pointer to the SVM event.
2121	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2122	* page-fault.
2123	*
2124	* @remarks Statistics counter assumes this is a guest event being reflected to
2125	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2126	*/
2127	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2128	{
2129	Assert(!pVCpu->hm.s.Event.fPending);
2130	Assert(pEvent->n.u1Valid);
2131
2132	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
2133	pVCpu->hm.s.Event.fPending = true;
2134	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2135
2136	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2137	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2138
2139	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2140	}
2141
2142
2143	/**
2144	* Injects an event into the guest upon VMRUN by updating the relevant field
2145	* in the VMCB.
2146	*
2147	* @param pVCpu Pointer to the VMCPU.
2148	* @param pVmcb Pointer to the guest VMCB.
2149	* @param pCtx Pointer to the guest-CPU context.
2150	* @param pEvent Pointer to the event.
2151	*
2152	* @remarks No-long-jump zone!!!
2153	* @remarks Requires CR0!
2154	*/
2155	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2156	{
2157	pVmcb->ctrl.EventInject.u = pEvent->u;
2158	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2159
2160	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2161	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2162	}
2163
2164
2165
2166	/**
2167	* Converts any TRPM trap into a pending HM event. This is typically used when
2168	* entering from ring-3 (not longjmp returns).
2169	*
2170	* @param pVCpu Pointer to the VMCPU.
2171	*/
2172	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2173	{
2174	Assert(TRPMHasTrap(pVCpu));
2175	Assert(!pVCpu->hm.s.Event.fPending);
2176
2177	uint8_t uVector;
2178	TRPMEVENT enmTrpmEvent;
2179	RTGCUINT uErrCode;
2180	RTGCUINTPTR GCPtrFaultAddress;
2181	uint8_t cbInstr;
2182
2183	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2184	AssertRC(rc);
2185
2186	SVMEVENT Event;
2187	Event.u = 0;
2188	Event.n.u1Valid = 1;
2189	Event.n.u8Vector = uVector;
2190
2191	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2192	if (enmTrpmEvent == TRPM_TRAP)
2193	{
2194	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2195	switch (uVector)
2196	{
2197	case X86_XCPT_PF:
2198	case X86_XCPT_DF:
2199	case X86_XCPT_TS:
2200	case X86_XCPT_NP:
2201	case X86_XCPT_SS:
2202	case X86_XCPT_GP:
2203	case X86_XCPT_AC:
2204	{
2205	Event.n.u1ErrorCodeValid = 1;
2206	Event.n.u32ErrorCode = uErrCode;
2207	break;
2208	}
2209	}
2210	}
2211	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2212	{
2213	if (uVector == X86_XCPT_NMI)
2214	Event.n.u3Type = SVM_EVENT_NMI;
2215	else
2216	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2217	}
2218	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2219	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2220	else
2221	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2222
2223	rc = TRPMResetTrap(pVCpu);
2224	AssertRC(rc);
2225
2226	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2227	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2228
2229	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2230	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2231	}
2232
2233
2234	/**
2235	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2236	* AMD-V to execute any instruction.
2237	*
2238	* @param pvCpu Pointer to the VMCPU.
2239	*/
2240	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2241	{
2242	Assert(pVCpu->hm.s.Event.fPending);
2243	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2244
2245	SVMEVENT Event;
2246	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2247
2248	uint8_t uVector = Event.n.u8Vector;
2249	uint8_t uVectorType = Event.n.u3Type;
2250
2251	TRPMEVENT enmTrapType;
2252	switch (uVectorType)
2253	{
2254	case SVM_EVENT_EXTERNAL_IRQ:
2255	case SVM_EVENT_NMI:
2256	enmTrapType = TRPM_HARDWARE_INT;
2257	break;
2258	case SVM_EVENT_SOFTWARE_INT:
2259	enmTrapType = TRPM_SOFTWARE_INT;
2260	break;
2261	case SVM_EVENT_EXCEPTION:
2262	enmTrapType = TRPM_TRAP;
2263	break;
2264	default:
2265	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2266	enmTrapType = TRPM_32BIT_HACK;
2267	break;
2268	}
2269
2270	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2271
2272	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2273	AssertRC(rc);
2274
2275	if (Event.n.u1ErrorCodeValid)
2276	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2277
2278	if ( uVectorType == SVM_EVENT_EXCEPTION
2279	&& uVector == X86_XCPT_PF)
2280	{
2281	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2282	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2283	}
2284	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2285	{
2286	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2287	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2288	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2289	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2290	}
2291	pVCpu->hm.s.Event.fPending = false;
2292	}
2293
2294
2295	/**
2296	* Gets the guest's interrupt-shadow.
2297	*
2298	* @returns The guest's interrupt-shadow.
2299	* @param pVCpu Pointer to the VMCPU.
2300	* @param pCtx Pointer to the guest-CPU context.
2301	*
2302	* @remarks No-long-jump zone!!!
2303	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2304	*/
2305	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2306	{
2307	/*
2308	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2309	* inhibit interrupts or clear any existing interrupt-inhibition.
2310	*/
2311	uint32_t uIntrState = 0;
2312	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2313	{
2314	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2315	{
2316	/*
2317	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2318	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2319	*/
2320	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2321	}
2322	else
2323	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2324	}
2325	return uIntrState;
2326	}
2327
2328
2329	/**
2330	* Sets the virtual interrupt intercept control in the VMCB which
2331	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2332	* receive interrupts.
2333	*
2334	* @param pVmcb Pointer to the VMCB.
2335	*/
2336	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2337	{
2338	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2339	{
2340	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2341	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2342	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2343	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2344
2345	Log4(("Setting VINTR intercept\n"));
2346	}
2347	}
2348
2349
2350	/**
2351	* Injects any pending events into the guest if the guest is in a state to
2352	* receive them.
2353	*
2354	* @param pVCpu Pointer to the VMCPU.
2355	* @param pCtx Pointer to the guest-CPU context.
2356	*/
2357	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2358	{
2359	Assert(!TRPMHasTrap(pVCpu));
2360	Log4Func(("\n"));
2361
2362	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2363	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2364	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2365
2366	SVMEVENT Event;
2367	Event.u = 0;
2368	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2369	{
2370	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2371	Assert(Event.n.u1Valid);
2372	bool fInject = true;
2373	if ( Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
2374	&& ( fBlockInt
2375	\|\| fIntShadow))
2376	{
2377	fInject = false;
2378	}
2379	else if ( Event.n.u3Type == SVM_EVENT_NMI
2380	&& fIntShadow)
2381	{
2382	fInject = false;
2383	}
2384
2385	if (fInject)
2386	{
2387	Log4(("Injecting pending HM event.\n"));
2388
2389	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2390	pVCpu->hm.s.Event.fPending = false;
2391
2392	#ifdef VBOX_WITH_STATISTICS
2393	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2394	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2395	else
2396	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2397	#endif
2398	}
2399	else
2400	hmR0SvmSetVirtIntrIntercept(pVmcb);
2401	} /** @todo SMI. SMIs take priority over NMIs. */
2402	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2403	{
2404	if (!fIntShadow)
2405	{
2406	Log4(("Injecting NMI\n"));
2407
2408	Event.n.u1Valid = 1;
2409	Event.n.u8Vector = X86_XCPT_NMI;
2410	Event.n.u3Type = SVM_EVENT_NMI;
2411
2412	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2413	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2414
2415	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2416	}
2417	else
2418	hmR0SvmSetVirtIntrIntercept(pVmcb);
2419	}
2420	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2421	{
2422	/* Check if there are guest external interrupts (PIC/APIC) pending and inject them, if the guest can receive them. */
2423	if ( !fBlockInt
2424	&& !fIntShadow)
2425	{
2426	uint8_t u8Interrupt;
2427	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2428	if (RT_SUCCESS(rc))
2429	{
2430	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2431
2432	Event.n.u1Valid = 1;
2433	Event.n.u8Vector = u8Interrupt;
2434	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2435
2436	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2437	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2438	}
2439	else
2440	{
2441	/** @todo Does this actually happen? If not turn it into an assertion. */
2442	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2443	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2444	}
2445	}
2446	else
2447	hmR0SvmSetVirtIntrIntercept(pVmcb);
2448	}
2449
2450	/* Update the guest interrupt shadow in the VMCB. */
2451	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2452	}
2453
2454
2455	/**
2456	* Reports world-switch error and dumps some useful debug info.
2457	*
2458	* @param pVM Pointer to the VM.
2459	* @param pVCpu Pointer to the VMCPU.
2460	* @param rcVMRun The return code from VMRUN (or
2461	* VERR_SVM_INVALID_GUEST_STATE for invalid
2462	* guest-state).
2463	* @param pCtx Pointer to the guest-CPU context.
2464	*/
2465	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2466	{
2467	HMSVM_ASSERT_PREEMPT_SAFE();
2468	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2469
2470	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2471	{
2472	HMDumpRegs(pVM, pVCpu, pCtx);
2473	#ifdef VBOX_STRICT
2474	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2475	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2476	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2477	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2478	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2479	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2480	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2481	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2482	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2483	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2484	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2485
2486	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2487	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2488	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2489
2490	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2491	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2492	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2493	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2494	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2495	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2496	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2497	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2498	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2499	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2500
2501	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2502	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2503	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2504	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2505	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2506	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2507	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2508	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2509	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2510	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2511	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2512	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2513	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2514	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2515	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2516	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2517	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2518
2519	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2520	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2521
2522	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2523	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2524	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2525	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2526	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2527	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2528	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2529	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2530	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2531	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2532	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2533	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2534	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2535	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2536	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2537	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2538	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2539	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2540	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2541	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2542
2543	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2544	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2545
2546	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2547	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2548	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2549	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2550
2551	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2552	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2553
2554	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2555	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2556	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2557	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2558
2559	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2560	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2561	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2562	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2563	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2564	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2565	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2566
2567	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2568	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2569	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2570	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2571
2572	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2573	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2574	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2575
2576	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2577	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2578	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2579	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2580	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2581	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2582	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2583	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2584	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2585	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2586	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2587	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2588	#endif
2589	}
2590	else
2591	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2592	}
2593
2594
2595	/**
2596	* Check per-VM and per-VCPU force flag actions that require us to go back to
2597	* ring-3 for one reason or another.
2598	*
2599	* @returns VBox status code (information status code included).
2600	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2601	* ring-3.
2602	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2603	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2604	* interrupts)
2605	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2606	* all EMTs to be in ring-3.
2607	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2608	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2609	* to the EM loop.
2610	*
2611	* @param pVM Pointer to the VM.
2612	* @param pVCpu Pointer to the VMCPU.
2613	* @param pCtx Pointer to the guest-CPU context.
2614	*/
2615	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2616	{
2617	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2618
2619	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2620	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2621	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2622
2623	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2624	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2625	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2626	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2627	{
2628	/* Pending PGM C3 sync. */
2629	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2630	{
2631	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2632	if (rc != VINF_SUCCESS)
2633	{
2634	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2635	return rc;
2636	}
2637	}
2638
2639	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2640	/* -XXX- what was that about single stepping? */
2641	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2642	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2643	{
2644	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2645	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2646	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2647	return rc;
2648	}
2649
2650	/* Pending VM request packets, such as hardware interrupts. */
2651	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2652	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2653	{
2654	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2655	return VINF_EM_PENDING_REQUEST;
2656	}
2657
2658	/* Pending PGM pool flushes. */
2659	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2660	{
2661	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2662	return VINF_PGM_POOL_FLUSH_PENDING;
2663	}
2664
2665	/* Pending DMA requests. */
2666	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2667	{
2668	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2669	return VINF_EM_RAW_TO_R3;
2670	}
2671	}
2672
2673	return VINF_SUCCESS;
2674	}
2675
2676
2677	/**
2678	* Does the preparations before executing guest code in AMD-V.
2679	*
2680	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2681	* recompiler. We must be cautious what we do here regarding committing
2682	* guest-state information into the the VMCB assuming we assuredly execute the
2683	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2684	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2685	* that the recompiler can (and should) use them when it resumes guest
2686	* execution. Otherwise such operations must be done when we can no longer
2687	* exit to ring-3.
2688	*
2689	* @returns VBox status code (informational status codes included).
2690	* @retval VINF_SUCCESS if we can proceed with running the guest.
2691	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2692	*
2693	* @param pVM Pointer to the VM.
2694	* @param pVCpu Pointer to the VMCPU.
2695	* @param pCtx Pointer to the guest-CPU context.
2696	* @param pSvmTransient Pointer to the SVM transient structure.
2697	*/
2698	DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2699	{
2700	/* Check force flag actions that might require us to go back to ring-3. */
2701	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2702	if (rc != VINF_SUCCESS)
2703	return rc;
2704
2705	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2706	/* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.) */
2707	pSvmTransient->uEFlags = ASMIntDisableFlags();
2708	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2709	{
2710	ASMSetFlags(pSvmTransient->uEFlags);
2711	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2712	/* Don't use VINF_EM_RAW_INTERRUPT_HYPER as we can't assume the host does kernel preemption. Maybe some day? */
2713	return VINF_EM_RAW_INTERRUPT;
2714	}
2715	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2716	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2717	#endif
2718
2719	/* Convert any pending TRPM traps to HM events for injection. */
2720	/** @todo Optimization: move this before disabling interrupts, restore state
2721	* using pVmcb->ctrl.EventInject.u. */
2722	if (TRPMHasTrap(pVCpu))
2723	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2724
2725	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2726
2727	return VINF_SUCCESS;
2728	}
2729
2730
2731	/**
2732	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2733	* means there is no backing out to ring-3 or anywhere else at this
2734	* point.
2735	*
2736	* @param pVM Pointer to the VM.
2737	* @param pVCpu Pointer to the VMCPU.
2738	* @param pCtx Pointer to the guest-CPU context.
2739	* @param pSvmTransient Pointer to the SVM transient structure.
2740	*
2741	* @remarks Called with preemption disabled.
2742	* @remarks No-long-jump zone!!!
2743	*/
2744	DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2745	{
2746	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2747	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2748
2749	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2750	/** @todo I don't see the point of this, VMMR0EntryFast() already disables interrupts for the entire period. */
2751	pSvmTransient->uEFlags = ASMIntDisableFlags();
2752	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2753	#endif
2754
2755	/*
2756	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2757	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2758	*/
2759	/** @todo The above assumption could be wrong. It's not documented what
2760	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2761	* hard way. */
2762	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2763	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2764
2765	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2766	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2767	#endif
2768
2769	/* Load the guest state. */
2770	int rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2771	AssertRC(rc);
2772	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
2773	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2774
2775	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2776	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2777	pVmcb->ctrl.u64VmcbCleanBits = 0;
2778
2779	/*
2780	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2781	* so we can update it on the way back if the guest changed the TPR.
2782	*/
2783	if (pVCpu->hm.s.svm.fSyncVTpr)
2784	{
2785	if (pVM->hm.s.fTPRPatchingActive)
2786	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2787	else
2788	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2789	}
2790
2791	/* Setup TSC offsetting. */
2792	if ( pSvmTransient->fUpdateTscOffsetting
2793	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2794	{
2795	hmR0SvmUpdateTscOffsetting(pVCpu);
2796	pSvmTransient->fUpdateTscOffsetting = false;
2797	}
2798
2799	/* Flush the appropriate tagged-TLB entries. */
2800	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2801	hmR0SvmFlushTaggedTlb(pVCpu);
2802	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2803
2804	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2805
2806	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2807	to start executing. */
2808
2809	/*
2810	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2811	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2812	*
2813	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2814	*/
2815	pSvmTransient->fRestoreTscAuxMsr = false;
2816	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2817	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2818	{
2819	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2820	uint64_t u64GuestTscAux = 0;
2821	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2822	AssertRC(rc2);
2823	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2824	{
2825	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2826	pSvmTransient->fRestoreTscAuxMsr = true;
2827	}
2828	}
2829	}
2830
2831
2832	/**
2833	* Wrapper for running the guest code in AMD-V.
2834	*
2835	* @returns VBox strict status code.
2836	* @param pVM Pointer to the VM.
2837	* @param pVCpu Pointer to the VMCPU.
2838	* @param pCtx Pointer to the guest-CPU context.
2839	*
2840	* @remarks No-long-jump zone!!!
2841	*/
2842	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2843	{
2844	/*
2845	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2846	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2847	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2848	*/
2849	#ifdef VBOX_WITH_KERNEL_USING_XMM
2850	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2851	pVCpu->hm.s.svm.pfnVMRun);
2852	#else
2853	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2854	#endif
2855	}
2856
2857
2858	/**
2859	* Performs some essential restoration of state after running guest code in
2860	* AMD-V.
2861	*
2862	* @param pVM Pointer to the VM.
2863	* @param pVCpu Pointer to the VMCPU.
2864	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2865	* out-of-sync. Make sure to update the required fields
2866	* before using them.
2867	* @param pSvmTransient Pointer to the SVM transient structure.
2868	* @param rcVMRun Return code of VMRUN.
2869	*
2870	* @remarks Called with interrupts disabled.
2871	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2872	* unconditionally when it is safe to do so.
2873	*/
2874	DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2875	{
2876	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2877
2878	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2879	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2880
2881	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2882	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2883
2884	if (pSvmTransient->fRestoreTscAuxMsr)
2885	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2886
2887	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2888	{
2889	/** @todo Find a way to fix hardcoding a guestimate. */
2890	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
2891	}
2892
2893	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
2894	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2895	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2896
2897	Assert(!(ASMGetFlags() & X86_EFL_IF));
2898	ASMSetFlags(pSvmTransient->uEFlags); /* Enable interrupts. */
2899
2900	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pMixedCtx);
2901	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2902
2903	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2904	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2905	{
2906	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2907	return;
2908	}
2909
2910	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2911	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2912	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2913
2914	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2915	{
2916	if (pVCpu->hm.s.svm.fSyncVTpr)
2917	{
2918	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2919	if ( pVM->hm.s.fTPRPatchingActive
2920	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2921	{
2922	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
2923	AssertRC(rc);
2924	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2925	}
2926	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2927	{
2928	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
2929	AssertRC(rc);
2930	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2931	}
2932	}
2933	}
2934	}
2935
2936
2937	/**
2938	* Runs the guest code using AMD-V.
2939	*
2940	* @returns VBox status code.
2941	* @param pVM Pointer to the VM.
2942	* @param pVCpu Pointer to the VMCPU.
2943	* @param pCtx Pointer to the guest-CPU context.
2944	*/
2945	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2946	{
2947	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2948	HMSVM_ASSERT_PREEMPT_SAFE();
2949
2950	SVMTRANSIENT SvmTransient;
2951	SvmTransient.fUpdateTscOffsetting = true;
2952	uint32_t cLoops = 0;
2953	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2954	int rc = VERR_INTERNAL_ERROR_5;
2955
2956	for (;; cLoops++)
2957	{
2958	Assert(!HMR0SuspendPending());
2959	HMSVM_ASSERT_CPU_SAFE();
2960
2961	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
2962	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
2963	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
2964	if (rc != VINF_SUCCESS)
2965	break;
2966
2967	/*
2968	* No longjmps to ring-3 from this point on!!!
2969	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2970	* This also disables flushing of the R0-logger instance (if any).
2971	*/
2972	VMMRZCallRing3Disable(pVCpu);
2973	VMMRZCallRing3RemoveNotification(pVCpu);
2974	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
2975
2976	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
2977
2978	/*
2979	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
2980	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
2981	*/
2982	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
2983	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
2984	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
2985	{
2986	if (rc == VINF_SUCCESS)
2987	rc = VERR_SVM_INVALID_GUEST_STATE;
2988	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
2989	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2990	return rc;
2991	}
2992
2993	/* Handle the #VMEXIT. */
2994	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
2995	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
2996	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
2997	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
2998	if (rc != VINF_SUCCESS)
2999	break;
3000	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
3001	{
3002	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3003	rc = VINF_EM_RAW_INTERRUPT;
3004	break;
3005	}
3006	}
3007
3008	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3009	if (rc == VERR_EM_INTERPRETER)
3010	rc = VINF_EM_RAW_EMULATE_INSTR;
3011	else if (rc == VINF_EM_RESET)
3012	rc = VINF_EM_TRIPLE_FAULT;
3013	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3014	return rc;
3015	}
3016
3017
3018	/**
3019	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3020	*
3021	* @returns VBox status code (informational status codes included).
3022	* @param pVCpu Pointer to the VMCPU.
3023	* @param pCtx Pointer to the guest-CPU context.
3024	* @param pSvmTransient Pointer to the SVM transient structure.
3025	*/
3026	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3027	{
3028	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3029	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3030
3031	/*
3032	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
3033	* normal workloads (for some definition of "normal").
3034	*/
3035	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3036	switch (pSvmTransient->u64ExitCode)
3037	{
3038	case SVM_EXIT_NPF:
3039	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3040
3041	case SVM_EXIT_IOIO:
3042	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3043
3044	case SVM_EXIT_RDTSC:
3045	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3046
3047	case SVM_EXIT_RDTSCP:
3048	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3049
3050	case SVM_EXIT_CPUID:
3051	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3052
3053	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3054	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3055
3056	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3057	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3058
3059	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3060	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3061
3062	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3063	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3064
3065	case SVM_EXIT_MONITOR:
3066	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3067
3068	case SVM_EXIT_MWAIT:
3069	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3070
3071	case SVM_EXIT_HLT:
3072	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3073
3074	case SVM_EXIT_READ_CR0:
3075	case SVM_EXIT_READ_CR3:
3076	case SVM_EXIT_READ_CR4:
3077	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3078
3079	case SVM_EXIT_WRITE_CR0:
3080	case SVM_EXIT_WRITE_CR3:
3081	case SVM_EXIT_WRITE_CR4:
3082	case SVM_EXIT_WRITE_CR8:
3083	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3084
3085	case SVM_EXIT_VINTR:
3086	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3087
3088	case SVM_EXIT_INTR:
3089	case SVM_EXIT_FERR_FREEZE:
3090	case SVM_EXIT_NMI:
3091	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3092
3093	case SVM_EXIT_MSR:
3094	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3095
3096	case SVM_EXIT_INVLPG:
3097	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3098
3099	case SVM_EXIT_WBINVD:
3100	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3101
3102	case SVM_EXIT_INVD:
3103	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3104
3105	case SVM_EXIT_RDPMC:
3106	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3107
3108	default:
3109	{
3110	switch (pSvmTransient->u64ExitCode)
3111	{
3112	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3113	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3114	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3115	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3116	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3117
3118	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3119	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3120	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3121	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3122	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3123
3124	case SVM_EXIT_TASK_SWITCH:
3125	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3126
3127	case SVM_EXIT_VMMCALL:
3128	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3129
3130	case SVM_EXIT_SHUTDOWN:
3131	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3132
3133	case SVM_EXIT_SMI:
3134	case SVM_EXIT_INIT:
3135	{
3136	/*
3137	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3138	* we want to know about it so log the exit code and bail.
3139	*/
3140	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3141	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3142	return VERR_SVM_UNEXPECTED_EXIT;
3143	}
3144
3145	case SVM_EXIT_INVLPGA:
3146	case SVM_EXIT_RSM:
3147	case SVM_EXIT_VMRUN:
3148	case SVM_EXIT_VMLOAD:
3149	case SVM_EXIT_VMSAVE:
3150	case SVM_EXIT_STGI:
3151	case SVM_EXIT_CLGI:
3152	case SVM_EXIT_SKINIT:
3153	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3154
3155	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3156	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3157	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3158	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3159	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3160	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3161	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3162	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3163	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3164	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3165	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3166	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3167	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3168	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3169	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3170	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3171	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3172	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3173	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3174	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3175
3176	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3177	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3178	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3179	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3180	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3181	{
3182	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3183	SVMEVENT Event;
3184	Event.u = 0;
3185	Event.n.u1Valid = 1;
3186	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3187	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3188
3189	switch (Event.n.u8Vector)
3190	{
3191	case X86_XCPT_DE:
3192	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3193	break;
3194
3195	case X86_XCPT_BP:
3196	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3197	* next instruction. */
3198	/** @todo Investigate this later. */
3199	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3200	break;
3201
3202	case X86_XCPT_UD:
3203	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3204	break;
3205
3206	case X86_XCPT_NP:
3207	Event.n.u1ErrorCodeValid = 1;
3208	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3209	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3210	break;
3211
3212	case X86_XCPT_SS:
3213	Event.n.u1ErrorCodeValid = 1;
3214	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3215	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3216	break;
3217
3218	case X86_XCPT_GP:
3219	Event.n.u1ErrorCodeValid = 1;
3220	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3221	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3222	break;
3223
3224	default:
3225	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3226	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3227	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3228	}
3229
3230	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3231	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3232	return VINF_SUCCESS;
3233	}
3234	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3235
3236	default:
3237	{
3238	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3239	pVCpu->hm.s.u32HMError = u32ExitCode;
3240	return VERR_SVM_UNKNOWN_EXIT;
3241	}
3242	}
3243	}
3244	}
3245	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3246	}
3247
3248
3249	#ifdef DEBUG
3250	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3251	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3252	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3253
3254	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3255	do \
3256	{ \
3257	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3258	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3259	} while (0)
3260
3261	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3262	do { \
3263	AssertPtr(pVCpu); \
3264	AssertPtr(pCtx); \
3265	AssertPtr(pSvmTransient); \
3266	Assert(ASMIntAreEnabled()); \
3267	HMSVM_ASSERT_PREEMPT_SAFE(); \
3268	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3269	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3270	HMSVM_ASSERT_PREEMPT_SAFE(); \
3271	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3272	HMSVM_ASSERT_PREEMPT_CPUID(); \
3273	} while (0)
3274	#else /* Release builds */
3275	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3276	#endif
3277
3278
3279	/**
3280	* Worker for hmR0SvmInterpretInvlpg().
3281	*
3282	* @return VBox status code.
3283	* @param pVCpu Pointer to the VMCPU.
3284	* @param pCpu Pointer to the disassembler state.
3285	* @param pRegFrame Pointer to the register frame.
3286	*/
3287	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3288	{
3289	DISQPVPARAMVAL Param1;
3290	RTGCPTR GCPtrPage;
3291
3292	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3293	if (RT_FAILURE(rc))
3294	return VERR_EM_INTERPRETER;
3295
3296	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3297	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3298	{
3299	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3300	return VERR_EM_INTERPRETER;
3301
3302	GCPtrPage = Param1.val.val64;
3303	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3304	rc = VBOXSTRICTRC_VAL(rc2);
3305	}
3306	else
3307	{
3308	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3309	rc = VERR_EM_INTERPRETER;
3310	}
3311
3312	return rc;
3313	}
3314
3315
3316	/**
3317	* Interprets INVLPG.
3318	*
3319	* @returns VBox status code.
3320	* @retval VINF_* Scheduling instructions.
3321	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3322	* @retval VERR_* Fatal errors.
3323	*
3324	* @param pVM Pointer to the VM.
3325	* @param pRegFrame Pointer to the register frame.
3326	*
3327	* @remarks Updates the RIP if the instruction was executed successfully.
3328	*/
3329	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3330	{
3331	/* Only allow 32 & 64 bit code. */
3332	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3333	{
3334	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3335	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3336	if ( RT_SUCCESS(rc)
3337	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3338	{
3339	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3340	if (RT_SUCCESS(rc))
3341	pRegFrame->rip += pDis->cbInstr;
3342	return rc;
3343	}
3344	else
3345	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3346	}
3347	return VERR_EM_INTERPRETER;
3348	}
3349
3350
3351	/**
3352	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3353	*
3354	* @param pVCpu Pointer to the VMCPU.
3355	*/
3356	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3357	{
3358	SVMEVENT Event;
3359	Event.u = 0;
3360	Event.n.u1Valid = 1;
3361	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3362	Event.n.u8Vector = X86_XCPT_UD;
3363	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3364	}
3365
3366
3367	/**
3368	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3369	*
3370	* @param pVCpu Pointer to the VMCPU.
3371	*/
3372	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3373	{
3374	SVMEVENT Event;
3375	Event.u = 0;
3376	Event.n.u1Valid = 1;
3377	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3378	Event.n.u8Vector = X86_XCPT_DB;
3379	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3380	}
3381
3382
3383	/**
3384	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3385	*
3386	* @param pVCpu Pointer to the VMCPU.
3387	* @param pCtx Pointer to the guest-CPU context.
3388	* @param u32ErrCode The error-code for the page-fault.
3389	* @param uFaultAddress The page fault address (CR2).
3390	*
3391	* @remarks This updates the guest CR2 with @a uFaultAddress!
3392	*/
3393	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3394	{
3395	SVMEVENT Event;
3396	Event.u = 0;
3397	Event.n.u1Valid = 1;
3398	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3399	Event.n.u8Vector = X86_XCPT_PF;
3400	Event.n.u1ErrorCodeValid = 1;
3401	Event.n.u32ErrorCode = u32ErrCode;
3402
3403	/* Update CR2 of the guest. */
3404	if (pCtx->cr2 != uFaultAddress)
3405	{
3406	pCtx->cr2 = uFaultAddress;
3407	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR2;
3408	}
3409
3410	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3411	}
3412
3413
3414	/**
3415	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3416	* VM.
3417	*
3418	* @param pVCpu Pointer to the VMCPU.
3419	*/
3420	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3421	{
3422	SVMEVENT Event;
3423	Event.u = 0;
3424	Event.n.u1Valid = 1;
3425	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3426	Event.n.u8Vector = X86_XCPT_NM;
3427	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3428	}
3429
3430
3431	/**
3432	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3433	*
3434	* @param pVCpu Pointer to the VMCPU.
3435	*/
3436	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3437	{
3438	SVMEVENT Event;
3439	Event.u = 0;
3440	Event.n.u1Valid = 1;
3441	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3442	Event.n.u8Vector = X86_XCPT_MF;
3443	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3444	}
3445
3446
3447	/**
3448	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3449	*
3450	* @param pVCpu Pointer to the VMCPU.
3451	*/
3452	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3453	{
3454	SVMEVENT Event;
3455	Event.u = 0;
3456	Event.n.u1Valid = 1;
3457	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3458	Event.n.u8Vector = X86_XCPT_DF;
3459	Event.n.u1ErrorCodeValid = 1;
3460	Event.n.u32ErrorCode = 0;
3461	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3462	}
3463
3464
3465	/**
3466	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3467	* guests. This simply looks up the patch record at EIP and does the required.
3468	*
3469	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3470	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3471	* TPR). See hmR3ReplaceTprInstr() for the details.
3472	*
3473	* @returns VBox status code.
3474	* @param pVM Pointer to the VM.
3475	* @param pVCpu Pointer to the VMCPU.
3476	* @param pCtx Pointer to the guest-CPU context.
3477	*/
3478	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3479	{
3480	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3481	for (;;)
3482	{
3483	bool fPending;
3484	uint8_t u8Tpr;
3485
3486	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3487	if (!pPatch)
3488	break;
3489
3490	switch (pPatch->enmType)
3491	{
3492	case HMTPRINSTR_READ:
3493	{
3494	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3495	AssertRC(rc);
3496
3497	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3498	AssertRC(rc);
3499	pCtx->rip += pPatch->cbOp;
3500	break;
3501	}
3502
3503	case HMTPRINSTR_WRITE_REG:
3504	case HMTPRINSTR_WRITE_IMM:
3505	{
3506	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3507	{
3508	uint32_t u32Val;
3509	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3510	AssertRC(rc);
3511	u8Tpr = u32Val;
3512	}
3513	else
3514	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3515
3516	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3517	AssertRC(rc2);
3518	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3519
3520	pCtx->rip += pPatch->cbOp;
3521	break;
3522	}
3523
3524	default:
3525	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3526	pVCpu->hm.s.u32HMError = pPatch->enmType;
3527	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3528	}
3529	}
3530
3531	return VINF_SUCCESS;
3532	}
3533
3534	/**
3535	* Determines if an exception is a contributory exception. Contributory
3536	* exceptions are ones which can cause double-faults. Page-fault is
3537	* intentionally not included here as it's a conditional contributory exception.
3538	*
3539	* @returns true if the exception is contributory, false otherwise.
3540	* @param uVector The exception vector.
3541	*/
3542	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3543	{
3544	switch (uVector)
3545	{
3546	case X86_XCPT_GP:
3547	case X86_XCPT_SS:
3548	case X86_XCPT_NP:
3549	case X86_XCPT_TS:
3550	case X86_XCPT_DE:
3551	return true;
3552	default:
3553	break;
3554	}
3555	return false;
3556	}
3557
3558
3559	/**
3560	* Handle a condition that occurred while delivering an event through the guest
3561	* IDT.
3562	*
3563	* @returns VBox status code (informational error codes included).
3564	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3565	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3566	* continue execution of the guest which will delivery the #DF.
3567	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3568	*
3569	* @param pVCpu Pointer to the VMCPU.
3570	* @param pCtx Pointer to the guest-CPU context.
3571	* @param pSvmTransient Pointer to the SVM transient structure.
3572	*
3573	* @remarks No-long-jump zone!!!
3574	*/
3575	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3576	{
3577	int rc = VINF_SUCCESS;
3578	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3579
3580	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3581	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3582	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3583	{
3584	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3585
3586	typedef enum
3587	{
3588	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3589	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3590	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3591	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3592	} SVMREFLECTXCPT;
3593
3594	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3595	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3596	{
3597	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3598	{
3599	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3600
3601	#ifdef VBOX_STRICT
3602	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3603	&& uExitVector == X86_XCPT_PF)
3604	{
3605	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3606	}
3607	#endif
3608	if ( uExitVector == X86_XCPT_PF
3609	&& uIdtVector == X86_XCPT_PF)
3610	{
3611	pSvmTransient->fVectoringPF = true;
3612	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3613	}
3614	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3615	&& hmR0SvmIsContributoryXcpt(uExitVector)
3616	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3617	\|\| uIdtVector == X86_XCPT_PF))
3618	{
3619	enmReflect = SVMREFLECTXCPT_DF;
3620	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3621	uIdtVector, uExitVector));
3622	}
3623	else if (uIdtVector == X86_XCPT_DF)
3624	{
3625	enmReflect = SVMREFLECTXCPT_TF;
3626	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3627	uIdtVector, uExitVector));
3628	}
3629	else
3630	enmReflect = SVMREFLECTXCPT_XCPT;
3631	}
3632	else
3633	{
3634	/*
3635	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3636	* exception to the guest after handling the VM-exit.
3637	*/
3638	enmReflect = SVMREFLECTXCPT_XCPT;
3639	}
3640	}
3641	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3642	{
3643	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3644	enmReflect = SVMREFLECTXCPT_XCPT;
3645	}
3646
3647	switch (enmReflect)
3648	{
3649	case SVMREFLECTXCPT_XCPT:
3650	{
3651	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3652	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3653
3654	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3655	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3656	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3657	break;
3658	}
3659
3660	case SVMREFLECTXCPT_DF:
3661	{
3662	hmR0SvmSetPendingXcptDF(pVCpu);
3663	rc = VINF_HM_DOUBLE_FAULT;
3664	break;
3665	}
3666
3667	case SVMREFLECTXCPT_TF:
3668	{
3669	rc = VINF_EM_RESET;
3670	break;
3671	}
3672
3673	default:
3674	Assert(rc == VINF_SUCCESS);
3675	break;
3676	}
3677	}
3678	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3679	return rc;
3680	}
3681
3682
3683	/**
3684	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
3685	* CPU, otherwise advances the RIP by @a cb bytes.
3686	*
3687	* @param pVCpu Pointer to the VMCPU.
3688	* @param pCtx Pointer to the guest-CPU context.
3689	* @param cb RIP increment value in bytes.
3690	*
3691	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
3692	* when NRIP_SAVE is supported by the CPU!
3693	*/
3694	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
3695	{
3696	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3697	{
3698	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3699	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3700	}
3701	else
3702	pCtx->rip += cb;
3703	}
3704
3705
3706	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3707	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3708	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3709
3710	/** @name VM-exit handlers.
3711	* @{
3712	*/
3713
3714	/**
3715	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3716	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3717	*/
3718	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3719	{
3720	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3721
3722	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
3723	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmi);
3724	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
3725	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3726
3727	/*
3728	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3729	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3730	* interrupt it is until the host actually take the interrupt.
3731	*
3732	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3733	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3734	*/
3735	return VINF_EM_RAW_INTERRUPT;
3736	}
3737
3738
3739	/**
3740	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3741	*/
3742	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3743	{
3744	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3745
3746	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3747	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3748	int rc = VINF_SUCCESS;
3749	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3750	return rc;
3751	}
3752
3753
3754	/**
3755	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3756	*/
3757	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3758	{
3759	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3760
3761	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3762	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3763	int rc = VINF_SUCCESS;
3764	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3765	return rc;
3766	}
3767
3768
3769	/**
3770	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3771	*/
3772	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3773	{
3774	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3775	PVM pVM = pVCpu->CTX_SUFF(pVM);
3776	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3777	if (RT_LIKELY(rc == VINF_SUCCESS))
3778	{
3779	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3780	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3781	}
3782	else
3783	{
3784	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3785	rc = VERR_EM_INTERPRETER;
3786	}
3787	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3788	return rc;
3789	}
3790
3791
3792	/**
3793	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3794	*/
3795	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3796	{
3797	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3798	PVM pVM = pVCpu->CTX_SUFF(pVM);
3799	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3800	if (RT_LIKELY(rc == VINF_SUCCESS))
3801	{
3802	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3803	pSvmTransient->fUpdateTscOffsetting = true;
3804
3805	/* Single step check. */
3806	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3807	}
3808	else
3809	{
3810	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3811	rc = VERR_EM_INTERPRETER;
3812	}
3813	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3814	return rc;
3815	}
3816
3817
3818	/**
3819	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3820	*/
3821	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3822	{
3823	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3824	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3825	if (RT_LIKELY(rc == VINF_SUCCESS))
3826	{
3827	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3828	pSvmTransient->fUpdateTscOffsetting = true;
3829	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3830	}
3831	else
3832	{
3833	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3834	rc = VERR_EM_INTERPRETER;
3835	}
3836	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3837	return rc;
3838	}
3839
3840
3841	/**
3842	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3843	*/
3844	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3845	{
3846	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3847	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3848	if (RT_LIKELY(rc == VINF_SUCCESS))
3849	{
3850	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3851	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3852	}
3853	else
3854	{
3855	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3856	rc = VERR_EM_INTERPRETER;
3857	}
3858	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3859	return rc;
3860	}
3861
3862
3863	/**
3864	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3865	*/
3866	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3867	{
3868	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3869	PVM pVM = pVCpu->CTX_SUFF(pVM);
3870	Assert(!pVM->hm.s.fNestedPaging);
3871
3872	/** @todo Decode Assist. */
3873	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3874	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3875	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3876	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3877	return rc;
3878	}
3879
3880
3881	/**
3882	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3883	*/
3884	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3885	{
3886	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3887	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
3888	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3889	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3890	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3891	return rc;
3892	}
3893
3894
3895	/**
3896	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3897	*/
3898	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3899	{
3900	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3901	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3902	if (RT_LIKELY(rc == VINF_SUCCESS))
3903	{
3904	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3905	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3906	}
3907	else
3908	{
3909	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3910	rc = VERR_EM_INTERPRETER;
3911	}
3912	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3913	return rc;
3914	}
3915
3916
3917	/**
3918	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3919	*/
3920	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3921	{
3922	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3923	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3924	int rc = VBOXSTRICTRC_VAL(rc2);
3925	if ( rc == VINF_EM_HALT
3926	\|\| rc == VINF_SUCCESS)
3927	{
3928	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3929
3930	if ( rc == VINF_EM_HALT
3931	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3932	{
3933	rc = VINF_SUCCESS;
3934	}
3935	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3936	}
3937	else
3938	{
3939	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3940	rc = VERR_EM_INTERPRETER;
3941	}
3942	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3943	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3944	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3945	return rc;
3946	}
3947
3948
3949	/**
3950	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
3951	* Conditional #VMEXIT.
3952	*/
3953	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3954	{
3955	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3956	return VINF_EM_RESET;
3957	}
3958
3959
3960	/**
3961	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
3962	*/
3963	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3964	{
3965	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3966
3967	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3968
3969	/** @todo Decode Assist. */
3970	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3971	int rc = VBOXSTRICTRC_VAL(rc2);
3972	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
3973	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
3974	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
3975	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
3976	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3977	return rc;
3978	}
3979
3980
3981	/**
3982	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
3983	*/
3984	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3985	{
3986	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3987	/** @todo Decode Assist. */
3988	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3989	int rc = VBOXSTRICTRC_VAL(rc2);
3990	if (rc == VINF_SUCCESS)
3991	{
3992	/* RIP has been updated by EMInterpretInstruction(). */
3993	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
3994	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
3995	{
3996	case 0: /* CR0. */
3997	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
3998	break;
3999
4000	case 3: /* CR3. */
4001	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4002	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
4003	break;
4004
4005	case 4: /* CR4. */
4006	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
4007	break;
4008
4009	case 8: /* CR8 (TPR). */
4010	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4011	break;
4012
4013	default:
4014	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4015	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4016	break;
4017	}
4018	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4019	}
4020	else
4021	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
4022	return rc;
4023	}
4024
4025
4026	/**
4027	* #VMEXIT handler for instructions that result in a #UD exception delivered to
4028	* the guest.
4029	*/
4030	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4031	{
4032	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4033	hmR0SvmSetPendingXcptUD(pVCpu);
4034	return VINF_SUCCESS;
4035	}
4036
4037
4038	/**
4039	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4040	*/
4041	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4042	{
4043	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4044	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4045	PVM pVM = pVCpu->CTX_SUFF(pVM);
4046
4047	int rc;
4048	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4049	{
4050	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4051
4052	/* Handle TPR patching; intercepted LSTAR write. */
4053	if ( pVM->hm.s.fTPRPatchingActive
4054	&& pCtx->ecx == MSR_K8_LSTAR)
4055	{
4056	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4057	{
4058	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4059	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4060	AssertRC(rc2);
4061	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4062	}
4063	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4064	rc = VINF_SUCCESS;
4065	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4066	return rc;
4067	}
4068
4069	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4070	{
4071	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4072	if (RT_LIKELY(rc == VINF_SUCCESS))
4073	{
4074	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4075	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4076	}
4077	else
4078	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4079	}
4080	else
4081	{
4082	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4083	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4084	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4085	/* RIP updated by EMInterpretInstruction(). */
4086	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4087	}
4088
4089	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4090	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4091	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4092	{
4093	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4094	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4095	EMInterpretWrmsr() changes it. */
4096	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4097	}
4098	else if (pCtx->ecx == MSR_K6_EFER)
4099	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
4100	else if (pCtx->ecx == MSR_IA32_TSC)
4101	pSvmTransient->fUpdateTscOffsetting = true;
4102	}
4103	else
4104	{
4105	/* MSR Read access. */
4106	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4107	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4108
4109	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4110	{
4111	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4112	if (RT_LIKELY(rc == VINF_SUCCESS))
4113	{
4114	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4115	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4116	}
4117	else
4118	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4119	}
4120	else
4121	{
4122	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4123	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4124	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4125	/* RIP updated by EMInterpretInstruction(). */
4126	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4127	}
4128	}
4129
4130	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4131	return rc;
4132	}
4133
4134
4135	/**
4136	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4137	*/
4138	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4139	{
4140	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4141	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4142
4143	/* We should -not- get this VM-exit if the guest is debugging. */
4144	AssertMsgReturn(!CPUMIsGuestDebugStateActive(pVCpu),
4145	("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx),
4146	VERR_SVM_UNEXPECTED_EXIT);
4147
4148	/*
4149	* Lazy DR0-3 loading?
4150	*/
4151	if (!CPUMIsHyperDebugStateActive(pVCpu))
4152	{
4153	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4154	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4155
4156	/* Don't intercept DRx read and writes. */
4157	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4158	pVmcb->ctrl.u16InterceptRdDRx = 0;
4159	pVmcb->ctrl.u16InterceptWrDRx = 0;
4160	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4161
4162	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4163	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4164	Assert(CPUMIsGuestDebugStateActive(pVCpu));
4165
4166	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4167	return VINF_SUCCESS;
4168	}
4169
4170	/*
4171	* Interpret the read/writing of DRx.
4172	*/
4173	/** @todo Decode assist. */
4174	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4175	Log5(("hmR0SvmExitReadDRx: Emulatined DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4176	if (RT_LIKELY(rc == VINF_SUCCESS))
4177	{
4178	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4179	/** @todo CPUM should set this flag! */
4180	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4181	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4182	}
4183	else
4184	Assert(rc == VERR_EM_INTERPRETER);
4185	return VBOXSTRICTRC_TODO(rc);
4186	}
4187
4188
4189	/**
4190	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4191	*/
4192	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4193	{
4194	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4195	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4196	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4197	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4198	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4199	return rc;
4200	}
4201
4202
4203	/**
4204	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4205	*/
4206	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4207	{
4208	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4209
4210	/* I/O operation lookup arrays. */
4211	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4212	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4213	the result (in AL/AX/EAX). */
4214	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4215
4216	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4217	PVM pVM = pVCpu->CTX_SUFF(pVM);
4218
4219	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4220	SVMIOIOEXIT IoExitInfo;
4221	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4222	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4223	uint32_t cbValue = s_aIOSize[uIOWidth];
4224	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4225
4226	if (RT_UNLIKELY(!cbValue))
4227	{
4228	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4229	return VERR_EM_INTERPRETER;
4230	}
4231
4232	VBOXSTRICTRC rcStrict;
4233	if (IoExitInfo.n.u1STR)
4234	{
4235	/* INS/OUTS - I/O String instruction. */
4236	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4237
4238	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4239	* in EXITINFO1? Investigate once this thing is up and running. */
4240
4241	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4242	if (rcStrict == VINF_SUCCESS)
4243	{
4244	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4245	{
4246	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4247	(DISCPUMODE)pDis->uAddrMode, cbValue);
4248	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4249	}
4250	else
4251	{
4252	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4253	(DISCPUMODE)pDis->uAddrMode, cbValue);
4254	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4255	}
4256	}
4257	else
4258	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4259	}
4260	else
4261	{
4262	/* IN/OUT - I/O instruction. */
4263	Assert(!IoExitInfo.n.u1REP);
4264
4265	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4266	{
4267	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4268	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4269	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4270
4271	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4272	}
4273	else
4274	{
4275	uint32_t u32Val = 0;
4276
4277	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4278	if (IOM_SUCCESS(rcStrict))
4279	{
4280	/* Save result of I/O IN instr. in AL/AX/EAX. */
4281	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4282	}
4283	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4284	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4285
4286	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4287	}
4288	}
4289
4290	if (IOM_SUCCESS(rcStrict))
4291	{
4292	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4293	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4294
4295	/*
4296	* If any I/O breakpoints are armed, we need to check if one triggered
4297	* and take appropriate action.
4298	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4299	*/
4300	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4301	* execution engines about whether hyper BPs and such are pending. */
4302	uint32_t const uDr7 = pCtx->dr[7];
4303	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4304	&& X86_DR7_ANY_RW_IO(uDr7)
4305	&& (pCtx->cr4 & X86_CR4_DE))
4306	\|\| DBGFBpIsHwIoArmed(pVM)))
4307	{
4308	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4309	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
4310
4311	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4312	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4313	{
4314	/* Raise #DB. */
4315	pVmcb->guest.u64DR6 = pCtx->dr[6];
4316	pVmcb->guest.u64DR7 = pCtx->dr[7];
4317	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4318	hmR0SvmSetPendingXcptDB(pVCpu);
4319	}
4320	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4321	else if ( rcStrict2 != VINF_SUCCESS
4322	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
4323	rcStrict = rcStrict2;
4324	}
4325
4326	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4327	}
4328
4329	#ifdef VBOX_STRICT
4330	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4331	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4332	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4333	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4334	else
4335	{
4336	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4337	* statuses, that the VMM device and some others may return. See
4338	* IOM_SUCCESS() for guidance. */
4339	AssertMsg( RT_FAILURE(rcStrict)
4340	\|\| rcStrict == VINF_SUCCESS
4341	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
4342	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
4343	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
4344	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4345	}
4346	#endif
4347	return VBOXSTRICTRC_TODO(rcStrict);
4348	}
4349
4350
4351	/**
4352	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4353	* #VMEXIT.
4354	*/
4355	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4356	{
4357	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4358	PVM pVM = pVCpu->CTX_SUFF(pVM);
4359	Assert(pVM->hm.s.fNestedPaging);
4360
4361	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4362
4363	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4364	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4365	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4366	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4367
4368	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4369
4370	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4371	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4372	if ( pVM->hm.s.fTRPPatchingAllowed
4373	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4374	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4375	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4376	&& !CPUMGetGuestCPL(pVCpu)
4377	&& !CPUMIsGuestInLongModeEx(pCtx)
4378	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4379	{
4380	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4381	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4382
4383	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4384	{
4385	/* Only attempt to patch the instruction once. */
4386	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4387	if (!pPatch)
4388	return VINF_EM_HM_PATCH_TPR_INSTR;
4389	}
4390	}
4391	#endif
4392
4393	/*
4394	* Determine the nested paging mode.
4395	*/
4396	PGMMODE enmNestedPagingMode;
4397	#if HC_ARCH_BITS == 32
4398	if (CPUMIsGuestInLongModeEx(pCtx))
4399	enmNestedPagingMode = PGMMODE_AMD64_NX;
4400	else
4401	#endif
4402	enmNestedPagingMode = PGMGetHostMode(pVM);
4403
4404	/*
4405	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4406	*/
4407	int rc;
4408	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4409	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4410	{
4411	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4412	u32ErrCode);
4413	rc = VBOXSTRICTRC_VAL(rc2);
4414
4415	/*
4416	* If we succeed, resume guest execution.
4417	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4418	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4419	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4420	* weird case. See @bugref{6043}.
4421	*/
4422	if ( rc == VINF_SUCCESS
4423	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4424	\|\| rc == VERR_PAGE_NOT_PRESENT)
4425	{
4426	/* Successfully handled MMIO operation. */
4427	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4428	rc = VINF_SUCCESS;
4429	}
4430	return rc;
4431	}
4432
4433	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4434	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4435	TRPMResetTrap(pVCpu);
4436
4437	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4438
4439	/*
4440	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4441	*/
4442	if ( rc == VINF_SUCCESS
4443	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4444	\|\| rc == VERR_PAGE_NOT_PRESENT)
4445	{
4446	/* We've successfully synced our shadow page tables. */
4447	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4448	rc = VINF_SUCCESS;
4449	}
4450
4451	return rc;
4452	}
4453
4454
4455	/**
4456	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4457	*/
4458	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4459	{
4460	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4461
4462	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4463	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4464	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4465
4466	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4467	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4468	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4469
4470	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4471	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4472	return VINF_SUCCESS;
4473	}
4474
4475
4476	/**
4477	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4478	*/
4479	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4480	{
4481	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4482
4483	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4484	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4485	#endif
4486
4487	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4488	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4489	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4490	&& pVCpu->hm.s.Event.fPending)
4491	{
4492	/*
4493	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4494	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4495	* when the recompiler restarts the instruction.
4496	*/
4497	SVMEVENT Event;
4498	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4499	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4500	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4501	{
4502	pVCpu->hm.s.Event.fPending = false;
4503	}
4504	else
4505	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4506	}
4507
4508	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4509	* emulation. */
4510	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4511	return VERR_EM_INTERPRETER;
4512	}
4513
4514
4515	/**
4516	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4517	*/
4518	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4519	{
4520	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4521
4522	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4523	if (RT_LIKELY(rc == VINF_SUCCESS))
4524	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4525	else
4526	hmR0SvmSetPendingXcptUD(pVCpu);
4527	return VINF_SUCCESS;
4528	}
4529
4530
4531	/**
4532	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4533	* #VMEXIT.
4534	*/
4535	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4536	{
4537	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4538
4539	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4540
4541	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4542	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4543	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4544	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4545	PVM pVM = pVCpu->CTX_SUFF(pVM);
4546
4547	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4548	if (pVM->hm.s.fNestedPaging)
4549	{
4550	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4551	if (!pSvmTransient->fVectoringPF)
4552	{
4553	/* A genuine guest #PF, reflect it to the guest. */
4554	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4555	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4556	uFaultAddress, u32ErrCode));
4557	}
4558	else
4559	{
4560	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4561	hmR0SvmSetPendingXcptDF(pVCpu);
4562	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4563	}
4564	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4565	return VINF_SUCCESS;
4566	}
4567	#endif
4568
4569	Assert(!pVM->hm.s.fNestedPaging);
4570
4571	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4572	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4573	if ( pVM->hm.s.fTRPPatchingAllowed
4574	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4575	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
4576	&& !CPUMGetGuestCPL(pVCpu)
4577	&& !CPUMIsGuestInLongModeEx(pCtx)
4578	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4579	{
4580	RTGCPHYS GCPhysApicBase;
4581	GCPhysApicBase = pCtx->msrApicBase;
4582	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4583
4584	/* Check if the page at the fault-address is the APIC base. */
4585	RTGCPHYS GCPhysPage;
4586	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4587	if ( rc2 == VINF_SUCCESS
4588	&& GCPhysPage == GCPhysApicBase)
4589	{
4590	/* Only attempt to patch the instruction once. */
4591	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4592	if (!pPatch)
4593	return VINF_EM_HM_PATCH_TPR_INSTR;
4594	}
4595	}
4596	#endif
4597
4598	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4599	pCtx->rip, u32ErrCode, pCtx->cr3));
4600
4601	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4602	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4603
4604	Log4(("#PF rc=%Rrc\n", rc));
4605
4606	if (rc == VINF_SUCCESS)
4607	{
4608	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4609	TRPMResetTrap(pVCpu);
4610	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4611	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4612	return rc;
4613	}
4614	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4615	{
4616	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4617
4618	if (!pSvmTransient->fVectoringPF)
4619	{
4620	/* It's a guest page fault and needs to be reflected to the guest. */
4621	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4622	TRPMResetTrap(pVCpu);
4623	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4624	}
4625	else
4626	{
4627	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4628	TRPMResetTrap(pVCpu);
4629	hmR0SvmSetPendingXcptDF(pVCpu);
4630	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4631	}
4632
4633	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4634	return VINF_SUCCESS;
4635	}
4636
4637	TRPMResetTrap(pVCpu);
4638	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4639	return rc;
4640	}
4641
4642
4643	/**
4644	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4645	* Conditional #VMEXIT.
4646	*/
4647	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4648	{
4649	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4650
4651	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4652
4653	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4654	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4655	#endif
4656
4657	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4658	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4659	if (rc == VINF_SUCCESS)
4660	{
4661	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4662	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4663	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4664	return VINF_SUCCESS;
4665	}
4666
4667	/* Forward #NM to the guest. */
4668	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4669	hmR0SvmSetPendingXcptNM(pVCpu);
4670	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4671	return VINF_SUCCESS;
4672	}
4673
4674
4675	/**
4676	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4677	* Conditional #VMEXIT.
4678	*/
4679	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4680	{
4681	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4682
4683	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4684
4685	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4686
4687	if (!(pCtx->cr0 & X86_CR0_NE))
4688	{
4689	/* Old-style FPU error reporting needs some extra work. */
4690	/** @todo don't fall back to the recompiler, but do it manually. */
4691	return VERR_EM_INTERPRETER;
4692	}
4693
4694	hmR0SvmSetPendingXcptMF(pVCpu);
4695	return VINF_SUCCESS;
4696	}
4697
4698
4699	/**
4700	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4701	* #VMEXIT.
4702	*/
4703	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4704	{
4705	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4706
4707	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4708
4709	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4710
4711	/* If we set the trap flag above, we have to clear it. */
4712	if (pVCpu->hm.s.fClearTrapFlag)
4713	{
4714	pVCpu->hm.s.fClearTrapFlag = false;
4715	pCtx->eflags.Bits.u1TF = 0;
4716	}
4717
4718	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4719	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4720	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4721	PVM pVM = pVCpu->CTX_SUFF(pVM);
4722	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
4723	if (rc == VINF_EM_RAW_GUEST_TRAP)
4724	{
4725	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
4726	if (CPUMIsHyperDebugStateActive(pVCpu))
4727	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
4728
4729	/* Reflect the exception back to the guest. */
4730	hmR0SvmSetPendingXcptDB(pVCpu);
4731	rc = VINF_SUCCESS;
4732	}
4733
4734	/*
4735	* Update DR6.
4736	*/
4737	if (CPUMIsHyperDebugStateActive(pVCpu))
4738	{
4739	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
4740	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
4741	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4742	}
4743	else
4744	{
4745	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
4746	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
4747	}
4748
4749	return rc;
4750	}
4751
4752	/** @} */
4753

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 47989

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