HMSVMR0.cpp@ 48037

Last change on this file since 48037 was 48037, checked in by vboxsync, 11 years ago
VMM/HM: Preemption hooks, work in progress. Hopefully I didn't break the non-hook case.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 181.8 KB

Line
1	/* $Id: HMSVMR0.cpp 48037 2013-08-23 18:11:36Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HMSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
38	#endif
39
40
41	/*******************************************************************************
42	* Defined Constants And Macros *
43	*******************************************************************************/
44	#ifdef VBOX_WITH_STATISTICS
45	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
46	if ((u64ExitCode) == SVM_EXIT_NPF) \
47	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
48	else \
49	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
50	} while (0)
51	#else
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
53	#endif
54
55	/** If we decide to use a function table approach this can be useful to
56	* switch to a "static DECLCALLBACK(int)". */
57	#define HMSVM_EXIT_DECL static int
58
59
60	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
61	*
62	* The CPU format of the segment attribute is described in X86DESCATTRBITS
63	* which is 16-bits (i.e. includes 4 bits of the segment limit).
64	*
65	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
66	* only the attribute bits and nothing else). Upper 4-bits are unused.
67	*
68	* @{ */
69	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
70	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
71	/** @} */
72
73
74	/** @name Macros for loading, storing segment registers to/from the VMCB.
75	* @{ */
76	#define HMSVM_LOAD_SEG_REG(REG, reg) \
77	do \
78	{ \
79	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
80	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
81	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
82	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
83	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
84	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
85	} while (0)
86
87	#define HMSVM_SAVE_SEG_REG(REG, reg) \
88	do \
89	{ \
90	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
92	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
93	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
94	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
95	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
96	} while (0)
97	/** @} */
98
99
100	/** Macro for checking and returning from the using function for
101	* \#VMEXIT intercepts that maybe caused during delivering of another
102	* event in the guest. */
103	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
104	do \
105	{ \
106	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
107	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
108	return VINF_SUCCESS; \
109	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
110	return rc; \
111	} while (0)
112
113	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
114	* instruction that exited. */
115	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
116	do { \
117	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
118	(a_rc) = VINF_EM_DBG_STEPPED; \
119	} while (0)
120
121	/** Assert that preemption is disabled or covered by thread-context hooks. */
122	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
123	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
124
125	/** Assert that we haven't migrated CPUs when thread-context hooks are not
126	* used. */
127	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
128	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
129	("Illegal migration! Entered on CPU %u Current %u\n", \
130	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
131
132	/** Exception bitmap mask for all contributory exceptions.
133	*
134	* Page fault is deliberately excluded here as it's conditional as to whether
135	* it's contributory or benign. Page faults are handled separately.
136	*/
137	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
138	\| RT_BIT(X86_XCPT_DE))
139
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG uEFlags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
211	bool fRestoreTscAuxMsr;
212	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
213	* contributary exception or a page-fault. */
214	bool fVectoringPF;
215	/** Whether the TSC offset mode needs to be updated. */
216	bool fUpdateTscOffsetting;
217	} SVMTRANSIENT, *PSVMTRANSIENT;
218	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
219	AssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
220	/** @} */
221
222
223	/**
224	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
225	*/
226	typedef enum SVMMSREXITREAD
227	{
228	/** Reading this MSR causes a VM-exit. */
229	SVMMSREXIT_INTERCEPT_READ = 0xb,
230	/** Reading this MSR does not cause a VM-exit. */
231	SVMMSREXIT_PASSTHRU_READ
232	} SVMMSREXITREAD;
233
234	/**
235	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
236	*/
237	typedef enum SVMMSREXITWRITE
238	{
239	/** Writing to this MSR causes a VM-exit. */
240	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
241	/** Writing to this MSR does not cause a VM-exit. */
242	SVMMSREXIT_PASSTHRU_WRITE
243	} SVMMSREXITWRITE;
244
245
246	/*******************************************************************************
247	* Internal Functions *
248	*******************************************************************************/
249	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
250	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
251	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
252
253	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
257	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
258	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
259	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
263	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
264	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
265	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
266	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
267	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
268	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
269	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
270	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
271	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
272	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
273	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
274	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
275	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
276	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
277	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
278	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
279	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
280
281	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
282
283
284	/*******************************************************************************
285	* Global Variables *
286	*******************************************************************************/
287	/** Ring-0 memory object for the IO bitmap. */
288	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
289	/** Physical address of the IO bitmap. */
290	RTHCPHYS g_HCPhysIOBitmap = 0;
291	/** Virtual address of the IO bitmap. */
292	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
293
294
295	/**
296	* Sets up and activates AMD-V on the current CPU.
297	*
298	* @returns VBox status code.
299	* @param pCpu Pointer to the CPU info struct.
300	* @param pVM Pointer to the VM (can be NULL after a resume!).
301	* @param pvCpuPage Pointer to the global CPU page.
302	* @param HCPhysCpuPage Physical address of the global CPU page.
303	*/
304	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
305	{
306	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
307	AssertReturn( HCPhysCpuPage
308	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
309	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
310
311	/*
312	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
313	*/
314	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
315	if (u64HostEfer & MSR_K6_EFER_SVME)
316	{
317	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
318	if ( pVM
319	&& pVM->hm.s.svm.fIgnoreInUseError)
320	{
321	pCpu->fIgnoreAMDVInUseError = true;
322	}
323
324	if (!pCpu->fIgnoreAMDVInUseError)
325	return VERR_SVM_IN_USE;
326	}
327
328	/* Turn on AMD-V in the EFER MSR. */
329	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
330
331	/* Write the physical page address where the CPU will store the host state while executing the VM. */
332	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
333
334	/*
335	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
336	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
337	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
338	* to flush the TLB with before using a new ASID.
339	*/
340	pCpu->fFlushAsidBeforeUse = true;
341
342	/*
343	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
344	*/
345	++pCpu->cTlbFlushes;
346
347	return VINF_SUCCESS;
348	}
349
350
351	/**
352	* Deactivates AMD-V on the current CPU.
353	*
354	* @returns VBox status code.
355	* @param pCpu Pointer to the CPU info struct.
356	* @param pvCpuPage Pointer to the global CPU page.
357	* @param HCPhysCpuPage Physical address of the global CPU page.
358	*/
359	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
360	{
361	AssertReturn( HCPhysCpuPage
362	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
363	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
364	NOREF(pCpu);
365
366	/* Turn off AMD-V in the EFER MSR. */
367	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
368	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
369
370	/* Invalidate host state physical address. */
371	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
372
373	return VINF_SUCCESS;
374	}
375
376
377	/**
378	* Does global AMD-V initialization (called during module initialization).
379	*
380	* @returns VBox status code.
381	*/
382	VMMR0DECL(int) SVMR0GlobalInit(void)
383	{
384	/*
385	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
386	* once globally here instead of per-VM.
387	*/
388	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
389	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
390	if (RT_FAILURE(rc))
391	return rc;
392
393	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
394	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
395
396	/* Set all bits to intercept all IO accesses. */
397	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
398	return VINF_SUCCESS;
399	}
400
401
402	/**
403	* Does global AMD-V termination (called during module termination).
404	*/
405	VMMR0DECL(void) SVMR0GlobalTerm(void)
406	{
407	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
408	{
409	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
410	g_pvIOBitmap = NULL;
411	g_HCPhysIOBitmap = 0;
412	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
413	}
414	}
415
416
417	/**
418	* Frees any allocated per-VCPU structures for a VM.
419	*
420	* @param pVM Pointer to the VM.
421	*/
422	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
423	{
424	for (uint32_t i = 0; i < pVM->cCpus; i++)
425	{
426	PVMCPU pVCpu = &pVM->aCpus[i];
427	AssertPtr(pVCpu);
428
429	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
430	{
431	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
432	pVCpu->hm.s.svm.pvVmcbHost = 0;
433	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
434	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
435	}
436
437	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
438	{
439	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
440	pVCpu->hm.s.svm.pvVmcb = 0;
441	pVCpu->hm.s.svm.HCPhysVmcb = 0;
442	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
443	}
444
445	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
446	{
447	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
448	pVCpu->hm.s.svm.pvMsrBitmap = 0;
449	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
450	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
451	}
452	}
453	}
454
455
456	/**
457	* Does per-VM AMD-V initialization.
458	*
459	* @returns VBox status code.
460	* @param pVM Pointer to the VM.
461	*/
462	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
463	{
464	int rc = VERR_INTERNAL_ERROR_5;
465
466	/*
467	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
468	*/
469	uint32_t u32Family;
470	uint32_t u32Model;
471	uint32_t u32Stepping;
472	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
473	{
474	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
475	pVM->hm.s.svm.fAlwaysFlushTLB = true;
476	}
477
478	/*
479	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
480	*/
481	for (VMCPUID i = 0; i < pVM->cCpus; i++)
482	{
483	PVMCPU pVCpu = &pVM->aCpus[i];
484	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
485	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
486	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
487	}
488
489	for (VMCPUID i = 0; i < pVM->cCpus; i++)
490	{
491	PVMCPU pVCpu = &pVM->aCpus[i];
492
493	/*
494	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
495	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
496	*/
497	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
498	if (RT_FAILURE(rc))
499	goto failure_cleanup;
500
501	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
502	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
503	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
504	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
505
506	/*
507	* Allocate one page for the guest-state VMCB.
508	*/
509	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
510	if (RT_FAILURE(rc))
511	goto failure_cleanup;
512
513	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
514	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
515	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
516	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
517
518	/*
519	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
520	* SVM to not require one.
521	*/
522	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
523	if (RT_FAILURE(rc))
524	goto failure_cleanup;
525
526	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
527	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
528	/* Set all bits to intercept all MSR accesses (changed later on). */
529	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
530	}
531
532	return VINF_SUCCESS;
533
534	failure_cleanup:
535	hmR0SvmFreeStructs(pVM);
536	return rc;
537	}
538
539
540	/**
541	* Does per-VM AMD-V termination.
542	*
543	* @returns VBox status code.
544	* @param pVM Pointer to the VM.
545	*/
546	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
547	{
548	hmR0SvmFreeStructs(pVM);
549	return VINF_SUCCESS;
550	}
551
552
553	/**
554	* Sets the permission bits for the specified MSR in the MSRPM.
555	*
556	* @param pVCpu Pointer to the VMCPU.
557	* @param uMsr The MSR for which the access permissions are being set.
558	* @param enmRead MSR read permissions.
559	* @param enmWrite MSR write permissions.
560	*/
561	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
562	{
563	unsigned ulBit;
564	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
565
566	/*
567	* Layout:
568	* Byte offset MSR range
569	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
570	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
571	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
572	* 0x1800 - 0x1fff Reserved
573	*/
574	if (uMsr <= 0x00001FFF)
575	{
576	/* Pentium-compatible MSRs. */
577	ulBit = uMsr * 2;
578	}
579	else if ( uMsr >= 0xC0000000
580	&& uMsr <= 0xC0001FFF)
581	{
582	/* AMD Sixth Generation x86 Processor MSRs. */
583	ulBit = (uMsr - 0xC0000000) * 2;
584	pbMsrBitmap += 0x800;
585	}
586	else if ( uMsr >= 0xC0010000
587	&& uMsr <= 0xC0011FFF)
588	{
589	/* AMD Seventh and Eighth Generation Processor MSRs. */
590	ulBit = (uMsr - 0xC0001000) * 2;
591	pbMsrBitmap += 0x1000;
592	}
593	else
594	{
595	AssertFailed();
596	return;
597	}
598
599	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
600	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
601	ASMBitSet(pbMsrBitmap, ulBit);
602	else
603	ASMBitClear(pbMsrBitmap, ulBit);
604
605	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
606	ASMBitSet(pbMsrBitmap, ulBit + 1);
607	else
608	ASMBitClear(pbMsrBitmap, ulBit + 1);
609
610	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
611	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
612	}
613
614
615	/**
616	* Sets up AMD-V for the specified VM.
617	* This function is only called once per-VM during initalization.
618	*
619	* @returns VBox status code.
620	* @param pVM Pointer to the VM.
621	*/
622	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
623	{
624	int rc = VINF_SUCCESS;
625
626	AssertReturn(pVM, VERR_INVALID_PARAMETER);
627	Assert(pVM->hm.s.svm.fSupported);
628
629	for (VMCPUID i = 0; i < pVM->cCpus; i++)
630	{
631	PVMCPU pVCpu = &pVM->aCpus[i];
632	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
633
634	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
635
636	/* Trap exceptions unconditionally (debug purposes). */
637	#ifdef HMSVM_ALWAYS_TRAP_PF
638	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
639	#endif
640	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
641	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
642	pVmcb->ctrl.u32InterceptException \|= 0
643	\| RT_BIT(X86_XCPT_BP)
644	\| RT_BIT(X86_XCPT_DB)
645	\| RT_BIT(X86_XCPT_DE)
646	\| RT_BIT(X86_XCPT_NM)
647	\| RT_BIT(X86_XCPT_UD)
648	\| RT_BIT(X86_XCPT_NP)
649	\| RT_BIT(X86_XCPT_SS)
650	\| RT_BIT(X86_XCPT_GP)
651	\| RT_BIT(X86_XCPT_PF)
652	\| RT_BIT(X86_XCPT_MF)
653	;
654	#endif
655
656	/* Set up unconditional intercepts and conditions. */
657	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
658	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
659	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
660	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
661	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
662	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
663	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
664	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
665	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
666	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
667	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
668	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
669
670	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
671	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
672	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
673	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
674	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
675	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
676	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
677	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
678	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
679	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
680
681	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
682	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
683
684	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
685	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
686
687	/* Intercept all DRx reads and writes by default. Changed later on. */
688	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
689	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
690
691	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
692	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
693
694	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
695	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
696	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
697
698	/* Set IO and MSR bitmap permission bitmap physical addresses. */
699	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
700	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
701
702	/* No LBR virtualization. */
703	pVmcb->ctrl.u64LBRVirt = 0;
704
705	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
706	pVmcb->ctrl.u64VmcbCleanBits = 0;
707
708	/* The host ASID MBZ, for the guest start with 1. */
709	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
710
711	/*
712	* Setup the PAT MSR (applicable for Nested Paging only).
713	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
714	* so choose type 6 for all PAT slots.
715	*/
716	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
717
718	/* Without Nested Paging, we need additionally intercepts. */
719	if (!pVM->hm.s.fNestedPaging)
720	{
721	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
722	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
723	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
724
725	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
726	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
727	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
728
729	/* Page faults must be intercepted to implement shadow paging. */
730	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
731	}
732
733	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
734	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
735	#endif
736
737	/*
738	* The following MSRs are saved/restored automatically during the world-switch.
739	* Don't intercept guest read/write accesses to these MSRs.
740	*/
741	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
742	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
743	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
744	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
745	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
746	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
747	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
748	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
749	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
750	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
751	}
752
753	return rc;
754	}
755
756
757	/**
758	* Invalidates a guest page by guest virtual address.
759	*
760	* @returns VBox status code.
761	* @param pVM Pointer to the VM.
762	* @param pVCpu Pointer to the VMCPU.
763	* @param GCVirt Guest virtual address of the page to invalidate.
764	*/
765	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
766	{
767	AssertReturn(pVM, VERR_INVALID_PARAMETER);
768	Assert(pVM->hm.s.svm.fSupported);
769
770	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
771
772	/* Skip it if a TLB flush is already pending. */
773	if (!fFlushPending)
774	{
775	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
776
777	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
778	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
779
780	#if HC_ARCH_BITS == 32
781	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
782	if (CPUMIsGuestInLongMode(pVCpu))
783	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
784	else
785	#endif
786	{
787	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
788	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
789	}
790	}
791	return VINF_SUCCESS;
792	}
793
794
795	/**
796	* Flushes the appropriate tagged-TLB entries.
797	*
798	* @param pVM Pointer to the VM.
799	* @param pVCpu Pointer to the VMCPU.
800	*/
801	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
802	{
803	PVM pVM = pVCpu->CTX_SUFF(pVM);
804	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
805	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
806
807	/*
808	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
809	* This can happen both for start & resume due to long jumps back to ring-3.
810	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
811	* so we cannot reuse the ASIDs without flushing.
812	*/
813	bool fNewAsid = false;
814	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
815	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
816	{
817	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
818	pVCpu->hm.s.fForceTLBFlush = true;
819	fNewAsid = true;
820	}
821
822	/* Set TLB flush state as checked until we return from the world switch. */
823	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
824
825	/* Check for explicit TLB shootdowns. */
826	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
827	{
828	pVCpu->hm.s.fForceTLBFlush = true;
829	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
830	}
831
832	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
833	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
834
835	if (pVM->hm.s.svm.fAlwaysFlushTLB)
836	{
837	/*
838	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
839	*/
840	pCpu->uCurrentAsid = 1;
841	pVCpu->hm.s.uCurrentAsid = 1;
842	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
843	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
844	}
845	else if (pVCpu->hm.s.fForceTLBFlush)
846	{
847	if (fNewAsid)
848	{
849	++pCpu->uCurrentAsid;
850	bool fHitASIDLimit = false;
851	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
852	{
853	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
854	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
855	fHitASIDLimit = true;
856
857	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
858	{
859	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
860	pCpu->fFlushAsidBeforeUse = true;
861	}
862	else
863	{
864	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
865	pCpu->fFlushAsidBeforeUse = false;
866	}
867	}
868
869	if ( !fHitASIDLimit
870	&& pCpu->fFlushAsidBeforeUse)
871	{
872	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
873	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
874	else
875	{
876	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
877	pCpu->fFlushAsidBeforeUse = false;
878	}
879	}
880
881	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
882	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
883	}
884	else
885	{
886	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
887	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
888	else
889	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
890	}
891
892	pVCpu->hm.s.fForceTLBFlush = false;
893	}
894	else
895	{
896	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
897	* not be executed. See hmQueueInvlPage() where it is commented
898	* out. Support individual entry flushing someday. */
899	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
900	{
901	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
902	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
903	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
904	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
905	}
906	}
907
908	pVCpu->hm.s.TlbShootdown.cPages = 0;
909	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
910
911	/* Update VMCB with the ASID. */
912	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
913	{
914	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
915	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
916	}
917
918	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
919	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
920	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
921	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
922	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
923	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
924
925	#ifdef VBOX_WITH_STATISTICS
926	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
927	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
928	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
929	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
930	{
931	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
932	}
933	else
934	{
935	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
936	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
937	}
938	#endif
939	}
940
941
942	/** @name 64-bit guest on 32-bit host OS helper functions.
943	*
944	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
945	* mode (code segment, paging). These wrappers/helpers perform the necessary
946	* bits for the 32->64 switcher.
947	*
948	* @{ */
949	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
950	/**
951	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
952	*
953	* @returns VBox status code.
954	* @param HCPhysVmcbHost Physical address of host VMCB.
955	* @param HCPhysVmcb Physical address of the VMCB.
956	* @param pCtx Pointer to the guest-CPU context.
957	* @param pVM Pointer to the VM.
958	* @param pVCpu Pointer to the VMCPU.
959	*/
960	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
961	{
962	uint32_t aParam[4];
963	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
964	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
965	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
966	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
967
968	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
969	}
970
971
972	/**
973	* Executes the specified VMRUN handler in 64-bit mode.
974	*
975	* @returns VBox status code.
976	* @param pVM Pointer to the VM.
977	* @param pVCpu Pointer to the VMCPU.
978	* @param pCtx Pointer to the guest-CPU context.
979	* @param enmOp The operation to perform.
980	* @param cbParam Number of parameters.
981	* @param paParam Array of 32-bit parameters.
982	*/
983	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
984	uint32_t *paParam)
985	{
986	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
987	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
988
989	/* Disable interrupts. */
990	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
991
992	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
993	RTCPUID idHostCpu = RTMpCpuId();
994	CPUMR0SetLApic(pVCpu, idHostCpu);
995	#endif
996
997	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
998	CPUMSetHyperEIP(pVCpu, enmOp);
999	for (int i = (int)cbParam - 1; i >= 0; i--)
1000	CPUMPushHyper(pVCpu, paParam[i]);
1001
1002	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1003	/* Call the switcher. */
1004	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1005	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1006
1007	/* Restore interrupts. */
1008	ASMSetFlags(uOldEFlags);
1009	return rc;
1010	}
1011
1012	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1013	/** @} */
1014
1015
1016	/**
1017	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1018	* the corresponding VMCB Clean Bit.
1019	*
1020	* @param pVmcb Pointer to the VMCB.
1021	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1022	*/
1023	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1024	{
1025	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1026	{
1027	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1028	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1029	}
1030	}
1031
1032
1033	/**
1034	* Removes an exception from the intercept-exception bitmap in the VMCB and
1035	* updates the corresponding VMCB Clean Bit.
1036	*
1037	* @param pVmcb Pointer to the VMCB.
1038	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1039	*/
1040	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1041	{
1042	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1043	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1044	{
1045	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1046	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1047	}
1048	#endif
1049	}
1050
1051
1052	/**
1053	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1054	*
1055	* @returns VBox status code.
1056	* @param pVCpu Pointer to the VMCPU.
1057	* @param pVmcb Pointer to the VMCB.
1058	* @param pCtx Pointer the guest-CPU context.
1059	*
1060	* @remarks No-long-jump zone!!!
1061	*/
1062	DECLINLINE(int) hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1063	{
1064	/*
1065	* Guest CR0.
1066	*/
1067	PVM pVM = pVCpu->CTX_SUFF(pVM);
1068	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1069	{
1070	uint64_t u64GuestCR0 = pCtx->cr0;
1071
1072	/* Always enable caching. */
1073	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1074
1075	/*
1076	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1077	*/
1078	if (!pVM->hm.s.fNestedPaging)
1079	{
1080	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1081	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1082	}
1083
1084	/*
1085	* Guest FPU bits.
1086	*/
1087	bool fInterceptNM = false;
1088	bool fInterceptMF = false;
1089	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1090	if (CPUMIsGuestFPUStateActive(pVCpu))
1091	{
1092	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1093	if (!(u64GuestCR0 & X86_CR0_NE))
1094	{
1095	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1096	fInterceptMF = true;
1097	}
1098	}
1099	else
1100	{
1101	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1102	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1103	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1104	}
1105
1106	/*
1107	* Update the exception intercept bitmap.
1108	*/
1109	if (fInterceptNM)
1110	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1111	else
1112	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1113
1114	if (fInterceptMF)
1115	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1116	else
1117	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1118
1119	pVmcb->guest.u64CR0 = u64GuestCR0;
1120	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1121	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1122	}
1123
1124	/*
1125	* Guest CR2.
1126	*/
1127	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1128	{
1129	pVmcb->guest.u64CR2 = pCtx->cr2;
1130	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1131	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1132	}
1133
1134	/*
1135	* Guest CR3.
1136	*/
1137	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1138	{
1139	if (pVM->hm.s.fNestedPaging)
1140	{
1141	PGMMODE enmShwPagingMode;
1142	#if HC_ARCH_BITS == 32
1143	if (CPUMIsGuestInLongModeEx(pCtx))
1144	enmShwPagingMode = PGMMODE_AMD64_NX;
1145	else
1146	#endif
1147	enmShwPagingMode = PGMGetHostMode(pVM);
1148
1149	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1150	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1151	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1152	pVmcb->guest.u64CR3 = pCtx->cr3;
1153	}
1154	else
1155	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1156
1157	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1158	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1159	}
1160
1161	/*
1162	* Guest CR4.
1163	*/
1164	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1165	{
1166	uint64_t u64GuestCR4 = pCtx->cr4;
1167	if (!pVM->hm.s.fNestedPaging)
1168	{
1169	switch (pVCpu->hm.s.enmShadowMode)
1170	{
1171	case PGMMODE_REAL:
1172	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1173	AssertFailed();
1174	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1175
1176	case PGMMODE_32_BIT: /* 32-bit paging. */
1177	u64GuestCR4 &= ~X86_CR4_PAE;
1178	break;
1179
1180	case PGMMODE_PAE: /* PAE paging. */
1181	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1182	/** Must use PAE paging as we could use physical memory > 4 GB */
1183	u64GuestCR4 \|= X86_CR4_PAE;
1184	break;
1185
1186	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1187	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1188	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1189	break;
1190	#else
1191	AssertFailed();
1192	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1193	#endif
1194
1195	default: /* shut up gcc */
1196	AssertFailed();
1197	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1198	}
1199	}
1200
1201	pVmcb->guest.u64CR4 = u64GuestCR4;
1202	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1203	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1204	}
1205
1206	return VINF_SUCCESS;
1207	}
1208
1209
1210	/**
1211	* Loads the guest segment registers into the VMCB.
1212	*
1213	* @returns VBox status code.
1214	* @param pVCpu Pointer to the VMCPU.
1215	* @param pVmcb Pointer to the VMCB.
1216	* @param pCtx Pointer to the guest-CPU context.
1217	*
1218	* @remarks No-long-jump zone!!!
1219	*/
1220	DECLINLINE(void) hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1221	{
1222	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1223	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1224	{
1225	HMSVM_LOAD_SEG_REG(CS, cs);
1226	HMSVM_LOAD_SEG_REG(SS, ss);
1227	HMSVM_LOAD_SEG_REG(DS, ds);
1228	HMSVM_LOAD_SEG_REG(ES, es);
1229	HMSVM_LOAD_SEG_REG(FS, fs);
1230	HMSVM_LOAD_SEG_REG(GS, gs);
1231
1232	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1233	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1234	}
1235
1236	/* Guest TR. */
1237	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1238	{
1239	HMSVM_LOAD_SEG_REG(TR, tr);
1240	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1241	}
1242
1243	/* Guest LDTR. */
1244	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1245	{
1246	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1247	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1248	}
1249
1250	/* Guest GDTR. */
1251	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1252	{
1253	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1254	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1255	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1256	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1257	}
1258
1259	/* Guest IDTR. */
1260	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1261	{
1262	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1263	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1264	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1265	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1266	}
1267	}
1268
1269
1270	/**
1271	* Loads the guest MSRs into the VMCB.
1272	*
1273	* @param pVCpu Pointer to the VMCPU.
1274	* @param pVmcb Pointer to the VMCB.
1275	* @param pCtx Pointer to the guest-CPU context.
1276	*
1277	* @remarks No-long-jump zone!!!
1278	*/
1279	DECLINLINE(void) hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1280	{
1281	/* Guest Sysenter MSRs. */
1282	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1283	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1284	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1285
1286	/*
1287	* Guest EFER MSR.
1288	* AMD-V requires guest EFER.SVME to be set. Weird. .
1289	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1290	*/
1291	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1292	{
1293	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1294	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1295	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1296	}
1297
1298	/* 64-bit MSRs. */
1299	if (CPUMIsGuestInLongModeEx(pCtx))
1300	{
1301	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1302	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1303	}
1304	else
1305	{
1306	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1307	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1308	{
1309	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1310	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1311	}
1312	}
1313
1314
1315	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1316	* be writable in 32-bit mode. Clarify with AMD spec. */
1317	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1318	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1319	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1320	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1321	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1322	}
1323
1324
1325	/**
1326	* Loads the guest debug registers into the VMCB.
1327	*
1328	* @param pVCpu Pointer to the VMCPU.
1329	* @param pVmcb Pointer to the VMCB.
1330	* @param pCtx Pointer to the guest-CPU context.
1331	*
1332	* @remarks No-long-jump zone!!!
1333	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1334	*/
1335	DECLINLINE(void) hmR0SvmLoadGuestDebugRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1336	{
1337	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1338	return;
1339	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1340	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1341
1342	bool fInterceptDB = false;
1343	bool fInterceptMovDRx = false;
1344
1345	/*
1346	* Anyone single stepping on the host side? If so, we'll have to use the
1347	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1348	* the VMM level like VT-x implementations does.
1349	*/
1350	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1351	if (fStepping)
1352	{
1353	pVCpu->hm.s.fClearTrapFlag = true;
1354	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1355	fInterceptDB = true;
1356	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1357	}
1358
1359	PVM pVM = pVCpu->CTX_SUFF(pVM);
1360	if (fStepping \|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1361	{
1362	/*
1363	* Use the combined guest and host DRx values found in the hypervisor
1364	* register set because the debugger has breakpoints active or someone
1365	* is single stepping on the host side.
1366	*
1367	* Note! DBGF expects a clean DR6 state before executing guest code.
1368	*/
1369	if (!CPUMIsHyperDebugStateActive(pVCpu))
1370	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1371	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1372	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1373
1374	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1375	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1376	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu) )
1377	{
1378	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1379	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1380	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1381	}
1382
1383	/** @todo If we cared, we could optimize to allow the guest to read registers
1384	* with the same values. */
1385	fInterceptDB = true;
1386	fInterceptMovDRx = true;
1387	Log5(("hm: Loaded hyper DRx\n"));
1388	}
1389	else
1390	{
1391	/*
1392	* Update DR6, DR7 with the guest values if necessary.
1393	*/
1394	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1395	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1396	{
1397	pVmcb->guest.u64DR7 = pCtx->dr[7];
1398	pVmcb->guest.u64DR6 = pCtx->dr[6];
1399	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1400	}
1401
1402	/*
1403	* If the guest has enabled debug registers, we need to load them prior to
1404	* executing guest code so they'll trigger at the right time.
1405	*/
1406	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1407	{
1408	if (!CPUMIsGuestDebugStateActive(pVCpu))
1409	{
1410	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1411	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1412	}
1413	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1414	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1415	Log5(("hm: Loaded guest DRx\n"));
1416	}
1417	/*
1418	* If no debugging enabled, we'll lazy load DR0-3.
1419	*/
1420	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1421	fInterceptMovDRx = true;
1422	}
1423
1424	/*
1425	* Set up the intercepts.
1426	*/
1427	if (fInterceptDB)
1428	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1429	else
1430	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1431
1432	if (fInterceptMovDRx)
1433	{
1434	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1435	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1436	{
1437	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1438	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1439	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1440	}
1441	}
1442	else
1443	{
1444	if ( pVmcb->ctrl.u16InterceptRdDRx
1445	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1446	{
1447	pVmcb->ctrl.u16InterceptRdDRx = 0;
1448	pVmcb->ctrl.u16InterceptWrDRx = 0;
1449	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1450	}
1451	}
1452
1453	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1454	}
1455
1456
1457	/**
1458	* Loads the guest APIC state (currently just the TPR).
1459	*
1460	* @returns VBox status code.
1461	* @param pVCpu Pointer to the VMCPU.
1462	* @param pVmcb Pointer to the VMCB.
1463	* @param pCtx Pointer to the guest-CPU context.
1464	*/
1465	DECLINLINE(int) hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1466	{
1467	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1468	return VINF_SUCCESS;
1469
1470	bool fPendingIntr;
1471	uint8_t u8Tpr;
1472	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1473	AssertRCReturn(rc, rc);
1474
1475	/** Assume that we need to trap all TPR accesses and thus need not check on
1476	* every #VMEXIT if we should update the TPR. */
1477	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1478	pVCpu->hm.s.svm.fSyncVTpr = false;
1479
1480	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1481	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1482	{
1483	pCtx->msrLSTAR = u8Tpr;
1484
1485	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1486	if (fPendingIntr)
1487	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1488	else
1489	{
1490	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1491	pVCpu->hm.s.svm.fSyncVTpr = true;
1492	}
1493	}
1494	else
1495	{
1496	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1497	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1498
1499	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1500	if (fPendingIntr)
1501	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1502	else
1503	{
1504	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1505	pVCpu->hm.s.svm.fSyncVTpr = true;
1506	}
1507
1508	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1509	}
1510
1511	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1512	return rc;
1513	}
1514
1515
1516	/**
1517	* Sets up the appropriate function to run guest code.
1518	*
1519	* @returns VBox status code.
1520	* @param pVCpu Pointer to the VMCPU.
1521	* @param pCtx Pointer to the guest-CPU context.
1522	*
1523	* @remarks No-long-jump zone!!!
1524	*/
1525	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1526	{
1527	if (CPUMIsGuestInLongModeEx(pCtx))
1528	{
1529	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1530	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1531	#endif
1532	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1533	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1534	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1535	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1536	#else
1537	/* 64-bit host or hybrid host. */
1538	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1539	#endif
1540	}
1541	else
1542	{
1543	/* Guest is not in long mode, use the 32-bit handler. */
1544	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1545	}
1546	return VINF_SUCCESS;
1547	}
1548
1549
1550	/**
1551	* Enters the AMD-V session.
1552	*
1553	* @returns VBox status code.
1554	* @param pVM Pointer to the VM.
1555	* @param pVCpu Pointer to the VMCPU.
1556	* @param pCpu Pointer to the CPU info struct.
1557	*/
1558	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1559	{
1560	AssertPtr(pVM);
1561	AssertPtr(pVCpu);
1562	Assert(pVM->hm.s.svm.fSupported);
1563	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1564	NOREF(pCpu);
1565
1566	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1567
1568	pVCpu->hm.s.fLeaveDone = false;
1569	return VINF_SUCCESS;
1570	}
1571
1572
1573	/**
1574	* Leaves the AMD-V session.
1575	*
1576	* @returns VBox status code.
1577	* @param pVM Pointer to the VM.
1578	* @param pVCpu Pointer to the VMCPU.
1579	* @param pCtx Pointer to the guest-CPU context.
1580	*/
1581	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1582	{
1583	NOREF(pVM);
1584	NOREF(pVCpu);
1585	NOREF(pCtx);
1586
1587	/* Nothing to do here. Everything is taken care of in hmR0SvmLeave(). */
1588	return VINF_SUCCESS;
1589	}
1590
1591
1592	/**
1593	* Thread-context callback for AMD-V.
1594	*
1595	* @param enmEvent The thread-context event.
1596	* @param pVCpu Pointer to the VMCPU.
1597	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1598	*/
1599	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1600	{
1601	switch (enmEvent)
1602	{
1603	case RTTHREADCTXEVENT_PREEMPTING:
1604	{
1605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1606	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1607	VMCPU_ASSERT_EMT(pVCpu);
1608
1609	PVM pVM = pVCpu->CTX_SUFF(pVM);
1610	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1611	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1612
1613	if (!pVCpu->hm.s.fLeaveDone)
1614	{
1615	hmR0SvmLeave(pVM, pVCpu, pCtx);
1616	pVCpu->hm.s.fLeaveDone = true;
1617	}
1618
1619	int rc = HMR0LeaveCpu(pVCpu); /* Leave HM context, takes care of local init (term). */
1620	AssertRC(rc); NOREF(rc);
1621
1622	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1623	break;
1624	}
1625
1626	case RTTHREADCTXEVENT_RESUMED:
1627	{
1628	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1629	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1630	VMCPU_ASSERT_EMT(pVCpu);
1631
1632	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1633
1634	/*
1635	* Initialize the bare minimum state required for HM. This takes care of
1636	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1637	*/
1638	int rc = HMR0EnterCpu(pVCpu);
1639	AssertRC(rc); NOREF(rc);
1640	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1641
1642	pVCpu->hm.s.fLeaveDone = false;
1643	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1644	break;
1645	}
1646
1647	default:
1648	break;
1649	}
1650	}
1651
1652
1653	/**
1654	* Saves the host state.
1655	*
1656	* @returns VBox status code.
1657	* @param pVM Pointer to the VM.
1658	* @param pVCpu Pointer to the VMCPU.
1659	*
1660	* @remarks No-long-jump zone!!!
1661	*/
1662	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1663	{
1664	NOREF(pVM);
1665	NOREF(pVCpu);
1666	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1667	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1668	return VINF_SUCCESS;
1669	}
1670
1671
1672	/**
1673	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1674	* fields on every successful VM-entry.
1675	*
1676	* Sets up the appropriate VMRUN function to execute guest code based
1677	* on the guest CPU mode.
1678	*
1679	* @returns VBox status code.
1680	* @param pVM Pointer to the VM.
1681	* @param pVCpu Pointer to the VMCPU.
1682	* @param pMixedCtx Pointer to the guest-CPU context.
1683	*
1684	* @remarks No-long-jump zone!!!
1685	*/
1686	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1687	{
1688	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1689	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1690
1691	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1692
1693	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1694	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1695
1696	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1697	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1698
1699	pVmcb->guest.u64RIP = pCtx->rip;
1700	pVmcb->guest.u64RSP = pCtx->rsp;
1701	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1702	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1703	pVmcb->guest.u64RAX = pCtx->rax;
1704
1705	/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
1706	hmR0SvmLoadGuestDebugRegs(pVCpu, pVmcb, pCtx);
1707
1708	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1709	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1710
1711	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1712	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1713
1714	/* Clear any unused and reserved bits. */
1715	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1716	\| HM_CHANGED_GUEST_RSP
1717	\| HM_CHANGED_GUEST_RFLAGS
1718	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1719	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1720	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1721	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1722	\| HM_CHANGED_SVM_RESERVED2
1723	\| HM_CHANGED_SVM_RESERVED3);
1724
1725	/* All the guest state bits should be loaded except maybe the host context and shared host/guest bits. */
1726	AssertMsg( !(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_ALL_GUEST)
1727	\|\| !(pVCpu->hm.s.fContextUseFlags & ~(HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE)),
1728	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1729	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1730
1731	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1732
1733	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1734	return rc;
1735	}
1736
1737
1738	/**
1739	* Loads the guest state on the way from ring-3.
1740	*
1741	* @returns VBox status code.
1742	* @param pVM Pointer to the VM.
1743	* @param pVCpu Pointer to the VMCPU.
1744	* @param pCtx Pointer to the guest-CPU context.
1745	*
1746	* @remarks No-long-jump zone!!!
1747	*/
1748	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1749	{
1750	/*
1751	* Avoid reloading the guest state on longjmp reentrants and do it lazily just before executing the guest.
1752	* This only helps when we get rescheduled more than once to a different host CPU on a longjmp trip before
1753	* finally executing guest code.
1754	*/
1755	return VINF_SUCCESS;
1756	}
1757
1758
1759	/**
1760	* Saves the entire guest state from the VMCB into the
1761	* guest-CPU context. Currently there is no residual state left in the CPU that
1762	* is not updated in the VMCB.
1763	*
1764	* @returns VBox status code.
1765	* @param pVCpu Pointer to the VMCPU.
1766	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1767	* out-of-sync. Make sure to update the required fields
1768	* before using them.
1769	*/
1770	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1771	{
1772	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1773
1774	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1775
1776	pMixedCtx->rip = pVmcb->guest.u64RIP;
1777	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1778	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1779	pMixedCtx->rax = pVmcb->guest.u64RAX;
1780
1781	/*
1782	* Guest interrupt shadow.
1783	*/
1784	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1785	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1786	else
1787	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1788
1789	/*
1790	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1791	*/
1792	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1793
1794	/*
1795	* Guest MSRs.
1796	*/
1797	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1798	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1799	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1800	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1801	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1802	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1803	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1804	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1805
1806	/*
1807	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1808	*/
1809	HMSVM_SAVE_SEG_REG(CS, cs);
1810	HMSVM_SAVE_SEG_REG(SS, ss);
1811	HMSVM_SAVE_SEG_REG(DS, ds);
1812	HMSVM_SAVE_SEG_REG(ES, es);
1813	HMSVM_SAVE_SEG_REG(FS, fs);
1814	HMSVM_SAVE_SEG_REG(GS, gs);
1815
1816	/*
1817	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1818	* register (yet).
1819	*/
1820	/** @todo SELM might need to be fixed as it too should not care about the
1821	* granularity bit. See @bugref{6785}. */
1822	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1823	&& pMixedCtx->cs.Attr.n.u1Present
1824	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1825	{
1826	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1827	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1828	}
1829
1830	#ifdef VBOX_STRICT
1831	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1832	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1833	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1834	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1835	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1836	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1837	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1838
1839	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1840	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1841	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1842	HMSVM_ASSERT_SEG_GRANULARITY(es);
1843	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1844	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1845
1846	# undef HMSVM_ASSERT_SEL_GRANULARITY
1847	#endif
1848
1849	/*
1850	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1851	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1852	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1853	* See AMD spec. 15.5.1 "Basic operation".
1854	*/
1855	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1856	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1857
1858	/*
1859	* Guest Descriptor-Table registers.
1860	*/
1861	HMSVM_SAVE_SEG_REG(TR, tr);
1862	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1863	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1864	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1865
1866	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1867	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1868
1869	/*
1870	* Guest Debug registers.
1871	*/
1872	if (!CPUMIsHyperDebugStateActive(pVCpu))
1873	{
1874	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1875	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1876	}
1877	else
1878	{
1879	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
1880	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
1881	}
1882
1883	/*
1884	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1885	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1886	*/
1887	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1888	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1889	{
1890	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1891	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1892	}
1893	}
1894
1895
1896	/**
1897	* Does the necessary state syncing before returning to ring-3 for any reason
1898	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
1899	*
1900	* @param pVM Pointer to the VM.
1901	* @param pVCpu Pointer to the VMCPU.
1902	* @param pMixedCtx Pointer to the guest-CPU context.
1903	*
1904	* @remarks No-long-jmp zone!!!
1905	*/
1906	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1907	{
1908	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1909	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1910	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1911
1912	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1913	if (CPUMIsGuestFPUStateActive(pVCpu))
1914	{
1915	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1916	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1917	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1918	}
1919
1920	/*
1921	* Restore host debug registers if necessary and resync on next R0 reentry.
1922	*/
1923	#ifdef VBOX_STRICT
1924	if (CPUMIsHyperDebugStateActive(pVCpu))
1925	{
1926	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1927	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1928	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1929	}
1930	#endif
1931	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
1932	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1933
1934	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1935	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1936
1937	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
1938	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
1939	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1940	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1941	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1942
1943	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1944	}
1945
1946
1947	DECLINLINE(void) hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1948	{
1949	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1950
1951	/* Avoid repeating this work when thread-context hooks are used and we had been preempted before
1952	which would've done this work from the VMXR0ThreadCtxCallback(). */
1953	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1954	bool fPreemptDisabled = false;
1955	if (RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1956	{
1957	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1958	RTThreadPreemptDisable(&PreemptState);
1959	fPreemptDisabled = true;
1960	}
1961
1962	if (!pVCpu->hm.s.fLeaveDone)
1963	{
1964	hmR0SvmLeave(pVM, pVCpu, pCtx);
1965	pVCpu->hm.s.fLeaveDone = true;
1966	}
1967
1968	/* Deregister hook now that we've left HM context before re-enabling preemption. */
1969	/** @todo This is bad. Deregistering here means we need to VMCLEAR always
1970	* (longjmp/exit-to-r3) in VT-x which is not efficient. */
1971	if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
1972	VMMR0ThreadCtxHooksDeregister(pVCpu);
1973
1974	/* Leave HM context. This takes care of local init (term). */
1975	int rc = HMR0LeaveCpu(pVCpu);
1976	AssertRC(rc); NOREF(rc);
1977
1978	/* Restore preemption if we previous disabled it ourselves. */
1979	if (fPreemptDisabled)
1980	RTThreadPreemptRestore(&PreemptState);
1981	}
1982
1983
1984	/**
1985	* Does the necessary state syncing before doing a longjmp to ring-3.
1986	*
1987	* @param pVM Pointer to the VM.
1988	* @param pVCpu Pointer to the VMCPU.
1989	* @param pCtx Pointer to the guest-CPU context.
1990	*
1991	* @remarks No-long-jmp zone!!!
1992	*/
1993	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1994	{
1995	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
1996	}
1997
1998
1999	/**
2000	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2001	* any remaining host state) before we longjump to ring-3 and possibly get
2002	* preempted.
2003	*
2004	* @param pVCpu Pointer to the VMCPU.
2005	* @param enmOperation The operation causing the ring-3 longjump.
2006	* @param pvUser The user argument (pointer to the possibly
2007	* out-of-date guest-CPU context).
2008	*
2009	* @remarks Must never be called with @a enmOperation ==
2010	* VMMCALLRING3_VM_R0_ASSERTION.
2011	*/
2012	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2013	{
2014	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
2015	Assert(pVCpu);
2016	Assert(pvUser);
2017	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2018	HMSVM_ASSERT_PREEMPT_SAFE();
2019
2020	VMMRZCallRing3Disable(pVCpu);
2021	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2022
2023	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2024	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2025
2026	VMMRZCallRing3Enable(pVCpu);
2027	}
2028
2029
2030	/**
2031	* Take necessary actions before going back to ring-3.
2032	*
2033	* An action requires us to go back to ring-3. This function does the necessary
2034	* steps before we can safely return to ring-3. This is not the same as longjmps
2035	* to ring-3, this is voluntary.
2036	*
2037	* @param pVM Pointer to the VM.
2038	* @param pVCpu Pointer to the VMCPU.
2039	* @param pCtx Pointer to the guest-CPU context.
2040	* @param rcExit The reason for exiting to ring-3. Can be
2041	* VINF_VMM_UNKNOWN_RING3_CALL.
2042	*/
2043	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2044	{
2045	Assert(pVM);
2046	Assert(pVCpu);
2047	Assert(pCtx);
2048	HMSVM_ASSERT_PREEMPT_SAFE();
2049
2050	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
2051	{
2052	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
2053	return;
2054	}
2055
2056	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2057	VMMRZCallRing3Disable(pVCpu);
2058	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2059
2060	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2061	if (pVCpu->hm.s.Event.fPending)
2062	{
2063	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2064	Assert(!pVCpu->hm.s.Event.fPending);
2065	}
2066
2067	/* Sync. the necessary state for going back to ring-3. */
2068	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2069	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2070
2071	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2072	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2073	\| CPUM_CHANGED_LDTR
2074	\| CPUM_CHANGED_GDTR
2075	\| CPUM_CHANGED_IDTR
2076	\| CPUM_CHANGED_TR
2077	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2078	if ( pVM->hm.s.fNestedPaging
2079	&& CPUMIsGuestPagingEnabledEx(pCtx))
2080	{
2081	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2082	}
2083
2084	/* Make sure we've undo the trap flag if we tried to single step something. */
2085	if (pVCpu->hm.s.fClearTrapFlag)
2086	{
2087	pCtx->eflags.Bits.u1TF = 0;
2088	pVCpu->hm.s.fClearTrapFlag = false;
2089	}
2090
2091	/* On our way back from ring-3 the following needs to be done. */
2092	/** @todo This can change with preemption hooks. */
2093	if (rcExit == VINF_EM_RAW_INTERRUPT)
2094	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
2095	else
2096	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2097
2098	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2099	VMMRZCallRing3Enable(pVCpu);
2100	}
2101
2102
2103	/**
2104	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2105	* intercepts.
2106	*
2107	* @param pVCpu Pointer to the VMCPU.
2108	*
2109	* @remarks No-long-jump zone!!!
2110	*/
2111	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
2112	{
2113	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2114	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
2115	{
2116	uint64_t u64CurTSC = ASMReadTSC();
2117	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
2118	{
2119	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2120	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2121	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2122	}
2123	else
2124	{
2125	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2126	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2127	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
2128	}
2129	}
2130	else
2131	{
2132	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2133	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2134	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2135	}
2136
2137	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2138	}
2139
2140
2141	/**
2142	* Sets an event as a pending event to be injected into the guest.
2143	*
2144	* @param pVCpu Pointer to the VMCPU.
2145	* @param pEvent Pointer to the SVM event.
2146	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2147	* page-fault.
2148	*
2149	* @remarks Statistics counter assumes this is a guest event being reflected to
2150	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2151	*/
2152	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2153	{
2154	Assert(!pVCpu->hm.s.Event.fPending);
2155	Assert(pEvent->n.u1Valid);
2156
2157	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
2158	pVCpu->hm.s.Event.fPending = true;
2159	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2160
2161	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2162	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2163
2164	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2165	}
2166
2167
2168	/**
2169	* Injects an event into the guest upon VMRUN by updating the relevant field
2170	* in the VMCB.
2171	*
2172	* @param pVCpu Pointer to the VMCPU.
2173	* @param pVmcb Pointer to the guest VMCB.
2174	* @param pCtx Pointer to the guest-CPU context.
2175	* @param pEvent Pointer to the event.
2176	*
2177	* @remarks No-long-jump zone!!!
2178	* @remarks Requires CR0!
2179	*/
2180	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2181	{
2182	pVmcb->ctrl.EventInject.u = pEvent->u;
2183	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2184
2185	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2186	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2187	}
2188
2189
2190
2191	/**
2192	* Converts any TRPM trap into a pending HM event. This is typically used when
2193	* entering from ring-3 (not longjmp returns).
2194	*
2195	* @param pVCpu Pointer to the VMCPU.
2196	*/
2197	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2198	{
2199	Assert(TRPMHasTrap(pVCpu));
2200	Assert(!pVCpu->hm.s.Event.fPending);
2201
2202	uint8_t uVector;
2203	TRPMEVENT enmTrpmEvent;
2204	RTGCUINT uErrCode;
2205	RTGCUINTPTR GCPtrFaultAddress;
2206	uint8_t cbInstr;
2207
2208	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2209	AssertRC(rc);
2210
2211	SVMEVENT Event;
2212	Event.u = 0;
2213	Event.n.u1Valid = 1;
2214	Event.n.u8Vector = uVector;
2215
2216	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2217	if (enmTrpmEvent == TRPM_TRAP)
2218	{
2219	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2220	switch (uVector)
2221	{
2222	case X86_XCPT_PF:
2223	case X86_XCPT_DF:
2224	case X86_XCPT_TS:
2225	case X86_XCPT_NP:
2226	case X86_XCPT_SS:
2227	case X86_XCPT_GP:
2228	case X86_XCPT_AC:
2229	{
2230	Event.n.u1ErrorCodeValid = 1;
2231	Event.n.u32ErrorCode = uErrCode;
2232	break;
2233	}
2234	}
2235	}
2236	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2237	{
2238	if (uVector == X86_XCPT_NMI)
2239	Event.n.u3Type = SVM_EVENT_NMI;
2240	else
2241	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2242	}
2243	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2244	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2245	else
2246	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2247
2248	rc = TRPMResetTrap(pVCpu);
2249	AssertRC(rc);
2250
2251	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2252	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2253
2254	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2255	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2256	}
2257
2258
2259	/**
2260	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2261	* AMD-V to execute any instruction.
2262	*
2263	* @param pvCpu Pointer to the VMCPU.
2264	*/
2265	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2266	{
2267	Assert(pVCpu->hm.s.Event.fPending);
2268	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2269
2270	SVMEVENT Event;
2271	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2272
2273	uint8_t uVector = Event.n.u8Vector;
2274	uint8_t uVectorType = Event.n.u3Type;
2275
2276	TRPMEVENT enmTrapType;
2277	switch (uVectorType)
2278	{
2279	case SVM_EVENT_EXTERNAL_IRQ:
2280	case SVM_EVENT_NMI:
2281	enmTrapType = TRPM_HARDWARE_INT;
2282	break;
2283	case SVM_EVENT_SOFTWARE_INT:
2284	enmTrapType = TRPM_SOFTWARE_INT;
2285	break;
2286	case SVM_EVENT_EXCEPTION:
2287	enmTrapType = TRPM_TRAP;
2288	break;
2289	default:
2290	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2291	enmTrapType = TRPM_32BIT_HACK;
2292	break;
2293	}
2294
2295	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2296
2297	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2298	AssertRC(rc);
2299
2300	if (Event.n.u1ErrorCodeValid)
2301	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2302
2303	if ( uVectorType == SVM_EVENT_EXCEPTION
2304	&& uVector == X86_XCPT_PF)
2305	{
2306	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2307	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2308	}
2309	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2310	{
2311	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2312	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2313	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2314	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2315	}
2316	pVCpu->hm.s.Event.fPending = false;
2317	}
2318
2319
2320	/**
2321	* Gets the guest's interrupt-shadow.
2322	*
2323	* @returns The guest's interrupt-shadow.
2324	* @param pVCpu Pointer to the VMCPU.
2325	* @param pCtx Pointer to the guest-CPU context.
2326	*
2327	* @remarks No-long-jump zone!!!
2328	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2329	*/
2330	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2331	{
2332	/*
2333	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2334	* inhibit interrupts or clear any existing interrupt-inhibition.
2335	*/
2336	uint32_t uIntrState = 0;
2337	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2338	{
2339	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2340	{
2341	/*
2342	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2343	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2344	*/
2345	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2346	}
2347	else
2348	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2349	}
2350	return uIntrState;
2351	}
2352
2353
2354	/**
2355	* Sets the virtual interrupt intercept control in the VMCB which
2356	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2357	* receive interrupts.
2358	*
2359	* @param pVmcb Pointer to the VMCB.
2360	*/
2361	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2362	{
2363	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2364	{
2365	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2366	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2367	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2368	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2369
2370	Log4(("Setting VINTR intercept\n"));
2371	}
2372	}
2373
2374
2375	/**
2376	* Injects any pending events into the guest if the guest is in a state to
2377	* receive them.
2378	*
2379	* @param pVCpu Pointer to the VMCPU.
2380	* @param pCtx Pointer to the guest-CPU context.
2381	*/
2382	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2383	{
2384	Assert(!TRPMHasTrap(pVCpu));
2385	Log4Func(("\n"));
2386
2387	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2388	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2389	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2390
2391	SVMEVENT Event;
2392	Event.u = 0;
2393	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2394	{
2395	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2396	Assert(Event.n.u1Valid);
2397	bool fInject = true;
2398	if ( Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
2399	&& ( fBlockInt
2400	\|\| fIntShadow))
2401	{
2402	fInject = false;
2403	}
2404	else if ( Event.n.u3Type == SVM_EVENT_NMI
2405	&& fIntShadow)
2406	{
2407	fInject = false;
2408	}
2409
2410	if (fInject)
2411	{
2412	Log4(("Injecting pending HM event.\n"));
2413
2414	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2415	pVCpu->hm.s.Event.fPending = false;
2416
2417	#ifdef VBOX_WITH_STATISTICS
2418	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2419	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2420	else
2421	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2422	#endif
2423	}
2424	else
2425	hmR0SvmSetVirtIntrIntercept(pVmcb);
2426	} /** @todo SMI. SMIs take priority over NMIs. */
2427	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2428	{
2429	if (!fIntShadow)
2430	{
2431	Log4(("Injecting NMI\n"));
2432
2433	Event.n.u1Valid = 1;
2434	Event.n.u8Vector = X86_XCPT_NMI;
2435	Event.n.u3Type = SVM_EVENT_NMI;
2436
2437	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2438	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2439
2440	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2441	}
2442	else
2443	hmR0SvmSetVirtIntrIntercept(pVmcb);
2444	}
2445	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2446	{
2447	/* Check if there are guest external interrupts (PIC/APIC) pending and inject them, if the guest can receive them. */
2448	if ( !fBlockInt
2449	&& !fIntShadow)
2450	{
2451	uint8_t u8Interrupt;
2452	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2453	if (RT_SUCCESS(rc))
2454	{
2455	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2456
2457	Event.n.u1Valid = 1;
2458	Event.n.u8Vector = u8Interrupt;
2459	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2460
2461	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2462	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2463	}
2464	else
2465	{
2466	/** @todo Does this actually happen? If not turn it into an assertion. */
2467	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2468	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2469	}
2470	}
2471	else
2472	hmR0SvmSetVirtIntrIntercept(pVmcb);
2473	}
2474
2475	/* Update the guest interrupt shadow in the VMCB. */
2476	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2477	}
2478
2479
2480	/**
2481	* Reports world-switch error and dumps some useful debug info.
2482	*
2483	* @param pVM Pointer to the VM.
2484	* @param pVCpu Pointer to the VMCPU.
2485	* @param rcVMRun The return code from VMRUN (or
2486	* VERR_SVM_INVALID_GUEST_STATE for invalid
2487	* guest-state).
2488	* @param pCtx Pointer to the guest-CPU context.
2489	*/
2490	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2491	{
2492	HMSVM_ASSERT_PREEMPT_SAFE();
2493	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2494
2495	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2496	{
2497	HMDumpRegs(pVM, pVCpu, pCtx);
2498	#ifdef VBOX_STRICT
2499	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2500	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2501	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2502	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2503	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2504	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2505	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2506	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2507	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2508	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2509	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2510
2511	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2512	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2513	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2514
2515	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2516	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2517	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2518	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2519	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2520	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2521	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2522	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2523	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2524	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2525
2526	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2527	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2528	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2529	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2530	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2531	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2532	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2533	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2534	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2535	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2536	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2537	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2538	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2539	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2540	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2541	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2542	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2543
2544	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2545	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2546
2547	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2548	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2549	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2550	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2551	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2552	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2553	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2554	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2555	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2556	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2557	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2558	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2559	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2560	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2561	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2562	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2563	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2564	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2565	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2566	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2567
2568	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2569	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2570
2571	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2572	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2573	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2574	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2575
2576	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2577	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2578
2579	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2580	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2581	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2582	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2583
2584	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2585	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2586	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2587	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2588	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2589	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2590	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2591
2592	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2593	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2594	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2595	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2596
2597	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2598	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2599	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2600
2601	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2602	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2603	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2604	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2605	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2606	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2607	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2608	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2609	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2610	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2611	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2612	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2613	#endif
2614	}
2615	else
2616	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2617	}
2618
2619
2620	/**
2621	* Check per-VM and per-VCPU force flag actions that require us to go back to
2622	* ring-3 for one reason or another.
2623	*
2624	* @returns VBox status code (information status code included).
2625	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2626	* ring-3.
2627	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2628	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2629	* interrupts)
2630	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2631	* all EMTs to be in ring-3.
2632	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2633	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2634	* to the EM loop.
2635	*
2636	* @param pVM Pointer to the VM.
2637	* @param pVCpu Pointer to the VMCPU.
2638	* @param pCtx Pointer to the guest-CPU context.
2639	*/
2640	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2641	{
2642	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2643
2644	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2645	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2646	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2647
2648	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2649	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2650	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2651	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2652	{
2653	/* Pending PGM C3 sync. */
2654	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2655	{
2656	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2657	if (rc != VINF_SUCCESS)
2658	{
2659	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2660	return rc;
2661	}
2662	}
2663
2664	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2665	/* -XXX- what was that about single stepping? */
2666	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2667	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2668	{
2669	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2670	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2671	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2672	return rc;
2673	}
2674
2675	/* Pending VM request packets, such as hardware interrupts. */
2676	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2677	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2678	{
2679	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2680	return VINF_EM_PENDING_REQUEST;
2681	}
2682
2683	/* Pending PGM pool flushes. */
2684	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2685	{
2686	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2687	return VINF_PGM_POOL_FLUSH_PENDING;
2688	}
2689
2690	/* Pending DMA requests. */
2691	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2692	{
2693	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2694	return VINF_EM_RAW_TO_R3;
2695	}
2696	}
2697
2698	return VINF_SUCCESS;
2699	}
2700
2701
2702	/**
2703	* Does the preparations before executing guest code in AMD-V.
2704	*
2705	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2706	* recompiler. We must be cautious what we do here regarding committing
2707	* guest-state information into the the VMCB assuming we assuredly execute the
2708	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2709	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2710	* that the recompiler can (and should) use them when it resumes guest
2711	* execution. Otherwise such operations must be done when we can no longer
2712	* exit to ring-3.
2713	*
2714	* @returns VBox status code (informational status codes included).
2715	* @retval VINF_SUCCESS if we can proceed with running the guest.
2716	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2717	*
2718	* @param pVM Pointer to the VM.
2719	* @param pVCpu Pointer to the VMCPU.
2720	* @param pCtx Pointer to the guest-CPU context.
2721	* @param pSvmTransient Pointer to the SVM transient structure.
2722	*/
2723	DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2724	{
2725	/* Check force flag actions that might require us to go back to ring-3. */
2726	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2727	if (rc != VINF_SUCCESS)
2728	return rc;
2729
2730	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2731	/* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.) */
2732	pSvmTransient->uEFlags = ASMIntDisableFlags();
2733	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2734	{
2735	ASMSetFlags(pSvmTransient->uEFlags);
2736	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2737	/* Don't use VINF_EM_RAW_INTERRUPT_HYPER as we can't assume the host does kernel preemption. Maybe some day? */
2738	return VINF_EM_RAW_INTERRUPT;
2739	}
2740	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2741	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2742	#endif
2743
2744	/* Convert any pending TRPM traps to HM events for injection. */
2745	/** @todo Optimization: move this before disabling interrupts, restore state
2746	* using pVmcb->ctrl.EventInject.u. */
2747	if (TRPMHasTrap(pVCpu))
2748	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2749
2750	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2751
2752	return VINF_SUCCESS;
2753	}
2754
2755
2756	/**
2757	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2758	* means there is no backing out to ring-3 or anywhere else at this
2759	* point.
2760	*
2761	* @param pVM Pointer to the VM.
2762	* @param pVCpu Pointer to the VMCPU.
2763	* @param pCtx Pointer to the guest-CPU context.
2764	* @param pSvmTransient Pointer to the SVM transient structure.
2765	*
2766	* @remarks Called with preemption disabled.
2767	* @remarks No-long-jump zone!!!
2768	*/
2769	DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2770	{
2771	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2772	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2773
2774	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2775	/** @todo I don't see the point of this, VMMR0EntryFast() already disables interrupts for the entire period. */
2776	pSvmTransient->uEFlags = ASMIntDisableFlags();
2777	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2778	#endif
2779
2780	/*
2781	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2782	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2783	*/
2784	/** @todo The above assumption could be wrong. It's not documented what
2785	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2786	* hard way. */
2787	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2788	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2789
2790	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2791	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2792	#endif
2793
2794	/* Load the guest state. */
2795	int rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2796	AssertRC(rc);
2797	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
2798	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
2799	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2800
2801	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2802	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2803	pVmcb->ctrl.u64VmcbCleanBits = 0;
2804
2805	/*
2806	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2807	* so we can update it on the way back if the guest changed the TPR.
2808	*/
2809	if (pVCpu->hm.s.svm.fSyncVTpr)
2810	{
2811	if (pVM->hm.s.fTPRPatchingActive)
2812	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2813	else
2814	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2815	}
2816
2817	/* Setup TSC offsetting. */
2818	if ( pSvmTransient->fUpdateTscOffsetting
2819	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2820	{
2821	hmR0SvmUpdateTscOffsetting(pVCpu);
2822	pSvmTransient->fUpdateTscOffsetting = false;
2823	}
2824
2825	/* Flush the appropriate tagged-TLB entries. */
2826	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2827	hmR0SvmFlushTaggedTlb(pVCpu);
2828	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2829
2830	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2831
2832	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2833	to start executing. */
2834
2835	/*
2836	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2837	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2838	*
2839	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2840	*/
2841	pSvmTransient->fRestoreTscAuxMsr = false;
2842	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2843	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2844	{
2845	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2846	uint64_t u64GuestTscAux = 0;
2847	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2848	AssertRC(rc2);
2849	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2850	{
2851	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2852	pSvmTransient->fRestoreTscAuxMsr = true;
2853	}
2854	}
2855	}
2856
2857
2858	/**
2859	* Wrapper for running the guest code in AMD-V.
2860	*
2861	* @returns VBox strict status code.
2862	* @param pVM Pointer to the VM.
2863	* @param pVCpu Pointer to the VMCPU.
2864	* @param pCtx Pointer to the guest-CPU context.
2865	*
2866	* @remarks No-long-jump zone!!!
2867	*/
2868	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2869	{
2870	/*
2871	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2872	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2873	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2874	*/
2875	#ifdef VBOX_WITH_KERNEL_USING_XMM
2876	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2877	pVCpu->hm.s.svm.pfnVMRun);
2878	#else
2879	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2880	#endif
2881	}
2882
2883
2884	/**
2885	* Performs some essential restoration of state after running guest code in
2886	* AMD-V.
2887	*
2888	* @param pVM Pointer to the VM.
2889	* @param pVCpu Pointer to the VMCPU.
2890	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2891	* out-of-sync. Make sure to update the required fields
2892	* before using them.
2893	* @param pSvmTransient Pointer to the SVM transient structure.
2894	* @param rcVMRun Return code of VMRUN.
2895	*
2896	* @remarks Called with interrupts disabled.
2897	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2898	* unconditionally when it is safe to do so.
2899	*/
2900	DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2901	{
2902	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2903
2904	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2905	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2906
2907	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2908	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2909
2910	if (pSvmTransient->fRestoreTscAuxMsr)
2911	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2912
2913	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2914	{
2915	/** @todo Find a way to fix hardcoding a guestimate. */
2916	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
2917	}
2918
2919	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
2920	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2921	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2922
2923	Assert(!(ASMGetFlags() & X86_EFL_IF));
2924	ASMSetFlags(pSvmTransient->uEFlags); /* Enable interrupts. */
2925
2926	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pMixedCtx);
2927	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2928
2929	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2930	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2931	{
2932	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2933	return;
2934	}
2935
2936	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2937	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2938	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2939
2940	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2941	{
2942	if (pVCpu->hm.s.svm.fSyncVTpr)
2943	{
2944	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2945	if ( pVM->hm.s.fTPRPatchingActive
2946	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2947	{
2948	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
2949	AssertRC(rc);
2950	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2951	}
2952	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2953	{
2954	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
2955	AssertRC(rc);
2956	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2957	}
2958	}
2959	}
2960	}
2961
2962
2963	/**
2964	* Runs the guest code using AMD-V.
2965	*
2966	* @returns VBox status code.
2967	* @param pVM Pointer to the VM.
2968	* @param pVCpu Pointer to the VMCPU.
2969	* @param pCtx Pointer to the guest-CPU context.
2970	*/
2971	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2972	{
2973	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2974	HMSVM_ASSERT_PREEMPT_SAFE();
2975
2976	SVMTRANSIENT SvmTransient;
2977	SvmTransient.fUpdateTscOffsetting = true;
2978	uint32_t cLoops = 0;
2979	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2980	int rc = VERR_INTERNAL_ERROR_5;
2981
2982	for (;; cLoops++)
2983	{
2984	Assert(!HMR0SuspendPending());
2985	HMSVM_ASSERT_CPU_SAFE();
2986
2987	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
2988	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
2989	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
2990	if (rc != VINF_SUCCESS)
2991	break;
2992
2993	/*
2994	* No longjmps to ring-3 from this point on!!!
2995	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2996	* This also disables flushing of the R0-logger instance (if any).
2997	*/
2998	VMMRZCallRing3Disable(pVCpu);
2999	VMMRZCallRing3RemoveNotification(pVCpu);
3000	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3001
3002	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3003
3004	/*
3005	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3006	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3007	*/
3008	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3009	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3010	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3011	{
3012	if (rc == VINF_SUCCESS)
3013	rc = VERR_SVM_INVALID_GUEST_STATE;
3014	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3015	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3016	return rc;
3017	}
3018
3019	/* Handle the #VMEXIT. */
3020	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3021	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3022	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3023	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3024	if (rc != VINF_SUCCESS)
3025	break;
3026	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
3027	{
3028	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3029	rc = VINF_EM_RAW_INTERRUPT;
3030	break;
3031	}
3032	}
3033
3034	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3035	if (rc == VERR_EM_INTERPRETER)
3036	rc = VINF_EM_RAW_EMULATE_INSTR;
3037	else if (rc == VINF_EM_RESET)
3038	rc = VINF_EM_TRIPLE_FAULT;
3039	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3040	return rc;
3041	}
3042
3043
3044	/**
3045	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3046	*
3047	* @returns VBox status code (informational status codes included).
3048	* @param pVCpu Pointer to the VMCPU.
3049	* @param pCtx Pointer to the guest-CPU context.
3050	* @param pSvmTransient Pointer to the SVM transient structure.
3051	*/
3052	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3053	{
3054	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3055	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3056
3057	/*
3058	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
3059	* normal workloads (for some definition of "normal").
3060	*/
3061	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3062	switch (pSvmTransient->u64ExitCode)
3063	{
3064	case SVM_EXIT_NPF:
3065	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3066
3067	case SVM_EXIT_IOIO:
3068	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3069
3070	case SVM_EXIT_RDTSC:
3071	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3072
3073	case SVM_EXIT_RDTSCP:
3074	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3075
3076	case SVM_EXIT_CPUID:
3077	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3078
3079	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3080	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3081
3082	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3083	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3084
3085	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3086	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3087
3088	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3089	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3090
3091	case SVM_EXIT_MONITOR:
3092	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3093
3094	case SVM_EXIT_MWAIT:
3095	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3096
3097	case SVM_EXIT_HLT:
3098	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3099
3100	case SVM_EXIT_READ_CR0:
3101	case SVM_EXIT_READ_CR3:
3102	case SVM_EXIT_READ_CR4:
3103	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3104
3105	case SVM_EXIT_WRITE_CR0:
3106	case SVM_EXIT_WRITE_CR3:
3107	case SVM_EXIT_WRITE_CR4:
3108	case SVM_EXIT_WRITE_CR8:
3109	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3110
3111	case SVM_EXIT_VINTR:
3112	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3113
3114	case SVM_EXIT_INTR:
3115	case SVM_EXIT_FERR_FREEZE:
3116	case SVM_EXIT_NMI:
3117	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3118
3119	case SVM_EXIT_MSR:
3120	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3121
3122	case SVM_EXIT_INVLPG:
3123	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3124
3125	case SVM_EXIT_WBINVD:
3126	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3127
3128	case SVM_EXIT_INVD:
3129	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3130
3131	case SVM_EXIT_RDPMC:
3132	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3133
3134	default:
3135	{
3136	switch (pSvmTransient->u64ExitCode)
3137	{
3138	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3139	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3140	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3141	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3142	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3143
3144	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3145	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3146	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3147	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3148	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3149
3150	case SVM_EXIT_TASK_SWITCH:
3151	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3152
3153	case SVM_EXIT_VMMCALL:
3154	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3155
3156	case SVM_EXIT_SHUTDOWN:
3157	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3158
3159	case SVM_EXIT_SMI:
3160	case SVM_EXIT_INIT:
3161	{
3162	/*
3163	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3164	* we want to know about it so log the exit code and bail.
3165	*/
3166	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3167	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3168	return VERR_SVM_UNEXPECTED_EXIT;
3169	}
3170
3171	case SVM_EXIT_INVLPGA:
3172	case SVM_EXIT_RSM:
3173	case SVM_EXIT_VMRUN:
3174	case SVM_EXIT_VMLOAD:
3175	case SVM_EXIT_VMSAVE:
3176	case SVM_EXIT_STGI:
3177	case SVM_EXIT_CLGI:
3178	case SVM_EXIT_SKINIT:
3179	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3180
3181	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3182	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3183	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3184	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3185	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3186	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3187	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3188	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3189	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3190	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3191	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3192	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3193	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3194	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3195	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3196	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3197	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3198	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3199	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3200	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3201
3202	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3203	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3204	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3205	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3206	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3207	{
3208	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3209	SVMEVENT Event;
3210	Event.u = 0;
3211	Event.n.u1Valid = 1;
3212	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3213	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3214
3215	switch (Event.n.u8Vector)
3216	{
3217	case X86_XCPT_DE:
3218	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3219	break;
3220
3221	case X86_XCPT_BP:
3222	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3223	* next instruction. */
3224	/** @todo Investigate this later. */
3225	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3226	break;
3227
3228	case X86_XCPT_UD:
3229	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3230	break;
3231
3232	case X86_XCPT_NP:
3233	Event.n.u1ErrorCodeValid = 1;
3234	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3235	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3236	break;
3237
3238	case X86_XCPT_SS:
3239	Event.n.u1ErrorCodeValid = 1;
3240	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3241	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3242	break;
3243
3244	case X86_XCPT_GP:
3245	Event.n.u1ErrorCodeValid = 1;
3246	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3247	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3248	break;
3249
3250	default:
3251	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3252	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3253	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3254	}
3255
3256	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3257	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3258	return VINF_SUCCESS;
3259	}
3260	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3261
3262	default:
3263	{
3264	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3265	pVCpu->hm.s.u32HMError = u32ExitCode;
3266	return VERR_SVM_UNKNOWN_EXIT;
3267	}
3268	}
3269	}
3270	}
3271	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3272	}
3273
3274
3275	#ifdef DEBUG
3276	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3277	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3278	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3279
3280	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3281	do \
3282	{ \
3283	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3284	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3285	} while (0)
3286
3287	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3288	do { \
3289	AssertPtr(pVCpu); \
3290	AssertPtr(pCtx); \
3291	AssertPtr(pSvmTransient); \
3292	Assert(ASMIntAreEnabled()); \
3293	HMSVM_ASSERT_PREEMPT_SAFE(); \
3294	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3295	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3296	HMSVM_ASSERT_PREEMPT_SAFE(); \
3297	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3298	HMSVM_ASSERT_PREEMPT_CPUID(); \
3299	} while (0)
3300	#else /* Release builds */
3301	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3302	#endif
3303
3304
3305	/**
3306	* Worker for hmR0SvmInterpretInvlpg().
3307	*
3308	* @return VBox status code.
3309	* @param pVCpu Pointer to the VMCPU.
3310	* @param pCpu Pointer to the disassembler state.
3311	* @param pRegFrame Pointer to the register frame.
3312	*/
3313	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3314	{
3315	DISQPVPARAMVAL Param1;
3316	RTGCPTR GCPtrPage;
3317
3318	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3319	if (RT_FAILURE(rc))
3320	return VERR_EM_INTERPRETER;
3321
3322	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3323	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3324	{
3325	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3326	return VERR_EM_INTERPRETER;
3327
3328	GCPtrPage = Param1.val.val64;
3329	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3330	rc = VBOXSTRICTRC_VAL(rc2);
3331	}
3332	else
3333	{
3334	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3335	rc = VERR_EM_INTERPRETER;
3336	}
3337
3338	return rc;
3339	}
3340
3341
3342	/**
3343	* Interprets INVLPG.
3344	*
3345	* @returns VBox status code.
3346	* @retval VINF_* Scheduling instructions.
3347	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3348	* @retval VERR_* Fatal errors.
3349	*
3350	* @param pVM Pointer to the VM.
3351	* @param pRegFrame Pointer to the register frame.
3352	*
3353	* @remarks Updates the RIP if the instruction was executed successfully.
3354	*/
3355	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3356	{
3357	/* Only allow 32 & 64 bit code. */
3358	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3359	{
3360	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3361	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3362	if ( RT_SUCCESS(rc)
3363	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3364	{
3365	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3366	if (RT_SUCCESS(rc))
3367	pRegFrame->rip += pDis->cbInstr;
3368	return rc;
3369	}
3370	else
3371	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3372	}
3373	return VERR_EM_INTERPRETER;
3374	}
3375
3376
3377	/**
3378	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3379	*
3380	* @param pVCpu Pointer to the VMCPU.
3381	*/
3382	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3383	{
3384	SVMEVENT Event;
3385	Event.u = 0;
3386	Event.n.u1Valid = 1;
3387	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3388	Event.n.u8Vector = X86_XCPT_UD;
3389	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3390	}
3391
3392
3393	/**
3394	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3395	*
3396	* @param pVCpu Pointer to the VMCPU.
3397	*/
3398	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3399	{
3400	SVMEVENT Event;
3401	Event.u = 0;
3402	Event.n.u1Valid = 1;
3403	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3404	Event.n.u8Vector = X86_XCPT_DB;
3405	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3406	}
3407
3408
3409	/**
3410	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3411	*
3412	* @param pVCpu Pointer to the VMCPU.
3413	* @param pCtx Pointer to the guest-CPU context.
3414	* @param u32ErrCode The error-code for the page-fault.
3415	* @param uFaultAddress The page fault address (CR2).
3416	*
3417	* @remarks This updates the guest CR2 with @a uFaultAddress!
3418	*/
3419	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3420	{
3421	SVMEVENT Event;
3422	Event.u = 0;
3423	Event.n.u1Valid = 1;
3424	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3425	Event.n.u8Vector = X86_XCPT_PF;
3426	Event.n.u1ErrorCodeValid = 1;
3427	Event.n.u32ErrorCode = u32ErrCode;
3428
3429	/* Update CR2 of the guest. */
3430	if (pCtx->cr2 != uFaultAddress)
3431	{
3432	pCtx->cr2 = uFaultAddress;
3433	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR2;
3434	}
3435
3436	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3437	}
3438
3439
3440	/**
3441	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3442	* VM.
3443	*
3444	* @param pVCpu Pointer to the VMCPU.
3445	*/
3446	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3447	{
3448	SVMEVENT Event;
3449	Event.u = 0;
3450	Event.n.u1Valid = 1;
3451	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3452	Event.n.u8Vector = X86_XCPT_NM;
3453	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3454	}
3455
3456
3457	/**
3458	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3459	*
3460	* @param pVCpu Pointer to the VMCPU.
3461	*/
3462	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3463	{
3464	SVMEVENT Event;
3465	Event.u = 0;
3466	Event.n.u1Valid = 1;
3467	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3468	Event.n.u8Vector = X86_XCPT_MF;
3469	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3470	}
3471
3472
3473	/**
3474	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3475	*
3476	* @param pVCpu Pointer to the VMCPU.
3477	*/
3478	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3479	{
3480	SVMEVENT Event;
3481	Event.u = 0;
3482	Event.n.u1Valid = 1;
3483	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3484	Event.n.u8Vector = X86_XCPT_DF;
3485	Event.n.u1ErrorCodeValid = 1;
3486	Event.n.u32ErrorCode = 0;
3487	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3488	}
3489
3490
3491	/**
3492	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3493	* guests. This simply looks up the patch record at EIP and does the required.
3494	*
3495	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3496	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3497	* TPR). See hmR3ReplaceTprInstr() for the details.
3498	*
3499	* @returns VBox status code.
3500	* @param pVM Pointer to the VM.
3501	* @param pVCpu Pointer to the VMCPU.
3502	* @param pCtx Pointer to the guest-CPU context.
3503	*/
3504	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3505	{
3506	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3507	for (;;)
3508	{
3509	bool fPending;
3510	uint8_t u8Tpr;
3511
3512	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3513	if (!pPatch)
3514	break;
3515
3516	switch (pPatch->enmType)
3517	{
3518	case HMTPRINSTR_READ:
3519	{
3520	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3521	AssertRC(rc);
3522
3523	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3524	AssertRC(rc);
3525	pCtx->rip += pPatch->cbOp;
3526	break;
3527	}
3528
3529	case HMTPRINSTR_WRITE_REG:
3530	case HMTPRINSTR_WRITE_IMM:
3531	{
3532	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3533	{
3534	uint32_t u32Val;
3535	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3536	AssertRC(rc);
3537	u8Tpr = u32Val;
3538	}
3539	else
3540	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3541
3542	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3543	AssertRC(rc2);
3544	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3545
3546	pCtx->rip += pPatch->cbOp;
3547	break;
3548	}
3549
3550	default:
3551	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3552	pVCpu->hm.s.u32HMError = pPatch->enmType;
3553	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3554	}
3555	}
3556
3557	return VINF_SUCCESS;
3558	}
3559
3560	/**
3561	* Determines if an exception is a contributory exception. Contributory
3562	* exceptions are ones which can cause double-faults. Page-fault is
3563	* intentionally not included here as it's a conditional contributory exception.
3564	*
3565	* @returns true if the exception is contributory, false otherwise.
3566	* @param uVector The exception vector.
3567	*/
3568	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3569	{
3570	switch (uVector)
3571	{
3572	case X86_XCPT_GP:
3573	case X86_XCPT_SS:
3574	case X86_XCPT_NP:
3575	case X86_XCPT_TS:
3576	case X86_XCPT_DE:
3577	return true;
3578	default:
3579	break;
3580	}
3581	return false;
3582	}
3583
3584
3585	/**
3586	* Handle a condition that occurred while delivering an event through the guest
3587	* IDT.
3588	*
3589	* @returns VBox status code (informational error codes included).
3590	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3591	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3592	* continue execution of the guest which will delivery the #DF.
3593	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3594	*
3595	* @param pVCpu Pointer to the VMCPU.
3596	* @param pCtx Pointer to the guest-CPU context.
3597	* @param pSvmTransient Pointer to the SVM transient structure.
3598	*
3599	* @remarks No-long-jump zone!!!
3600	*/
3601	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3602	{
3603	int rc = VINF_SUCCESS;
3604	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3605
3606	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3607	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3608	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3609	{
3610	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3611
3612	typedef enum
3613	{
3614	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3615	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3616	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3617	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3618	} SVMREFLECTXCPT;
3619
3620	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3621	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3622	{
3623	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3624	{
3625	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3626
3627	#ifdef VBOX_STRICT
3628	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3629	&& uExitVector == X86_XCPT_PF)
3630	{
3631	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3632	}
3633	#endif
3634	if ( uExitVector == X86_XCPT_PF
3635	&& uIdtVector == X86_XCPT_PF)
3636	{
3637	pSvmTransient->fVectoringPF = true;
3638	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3639	}
3640	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3641	&& hmR0SvmIsContributoryXcpt(uExitVector)
3642	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3643	\|\| uIdtVector == X86_XCPT_PF))
3644	{
3645	enmReflect = SVMREFLECTXCPT_DF;
3646	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3647	uIdtVector, uExitVector));
3648	}
3649	else if (uIdtVector == X86_XCPT_DF)
3650	{
3651	enmReflect = SVMREFLECTXCPT_TF;
3652	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3653	uIdtVector, uExitVector));
3654	}
3655	else
3656	enmReflect = SVMREFLECTXCPT_XCPT;
3657	}
3658	else
3659	{
3660	/*
3661	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3662	* exception to the guest after handling the VM-exit.
3663	*/
3664	enmReflect = SVMREFLECTXCPT_XCPT;
3665	}
3666	}
3667	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3668	{
3669	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3670	enmReflect = SVMREFLECTXCPT_XCPT;
3671	}
3672
3673	switch (enmReflect)
3674	{
3675	case SVMREFLECTXCPT_XCPT:
3676	{
3677	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3678	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3679
3680	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3681	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3682	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3683	break;
3684	}
3685
3686	case SVMREFLECTXCPT_DF:
3687	{
3688	hmR0SvmSetPendingXcptDF(pVCpu);
3689	rc = VINF_HM_DOUBLE_FAULT;
3690	break;
3691	}
3692
3693	case SVMREFLECTXCPT_TF:
3694	{
3695	rc = VINF_EM_RESET;
3696	break;
3697	}
3698
3699	default:
3700	Assert(rc == VINF_SUCCESS);
3701	break;
3702	}
3703	}
3704	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3705	return rc;
3706	}
3707
3708
3709	/**
3710	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
3711	* CPU, otherwise advances the RIP by @a cb bytes.
3712	*
3713	* @param pVCpu Pointer to the VMCPU.
3714	* @param pCtx Pointer to the guest-CPU context.
3715	* @param cb RIP increment value in bytes.
3716	*
3717	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
3718	* when NRIP_SAVE is supported by the CPU!
3719	*/
3720	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
3721	{
3722	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3723	{
3724	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3725	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3726	}
3727	else
3728	pCtx->rip += cb;
3729	}
3730
3731
3732	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3733	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3734	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3735
3736	/** @name VM-exit handlers.
3737	* @{
3738	*/
3739
3740	/**
3741	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3742	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3743	*/
3744	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3745	{
3746	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3747
3748	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
3749	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmi);
3750	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
3751	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3752
3753	/*
3754	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3755	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3756	* interrupt it is until the host actually take the interrupt.
3757	*
3758	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3759	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3760	*/
3761	return VINF_EM_RAW_INTERRUPT;
3762	}
3763
3764
3765	/**
3766	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3767	*/
3768	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3769	{
3770	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3771
3772	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3773	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3774	int rc = VINF_SUCCESS;
3775	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3776	return rc;
3777	}
3778
3779
3780	/**
3781	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3782	*/
3783	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3784	{
3785	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3786
3787	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3788	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3789	int rc = VINF_SUCCESS;
3790	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3791	return rc;
3792	}
3793
3794
3795	/**
3796	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3797	*/
3798	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3799	{
3800	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3801	PVM pVM = pVCpu->CTX_SUFF(pVM);
3802	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3803	if (RT_LIKELY(rc == VINF_SUCCESS))
3804	{
3805	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3806	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3807	}
3808	else
3809	{
3810	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3811	rc = VERR_EM_INTERPRETER;
3812	}
3813	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3814	return rc;
3815	}
3816
3817
3818	/**
3819	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3820	*/
3821	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3822	{
3823	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3824	PVM pVM = pVCpu->CTX_SUFF(pVM);
3825	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3826	if (RT_LIKELY(rc == VINF_SUCCESS))
3827	{
3828	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3829	pSvmTransient->fUpdateTscOffsetting = true;
3830
3831	/* Single step check. */
3832	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3833	}
3834	else
3835	{
3836	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3837	rc = VERR_EM_INTERPRETER;
3838	}
3839	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3840	return rc;
3841	}
3842
3843
3844	/**
3845	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3846	*/
3847	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3848	{
3849	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3850	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3851	if (RT_LIKELY(rc == VINF_SUCCESS))
3852	{
3853	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3854	pSvmTransient->fUpdateTscOffsetting = true;
3855	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3856	}
3857	else
3858	{
3859	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3860	rc = VERR_EM_INTERPRETER;
3861	}
3862	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3863	return rc;
3864	}
3865
3866
3867	/**
3868	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3869	*/
3870	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3871	{
3872	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3873	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3874	if (RT_LIKELY(rc == VINF_SUCCESS))
3875	{
3876	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3877	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3878	}
3879	else
3880	{
3881	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3882	rc = VERR_EM_INTERPRETER;
3883	}
3884	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3885	return rc;
3886	}
3887
3888
3889	/**
3890	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3891	*/
3892	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3893	{
3894	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3895	PVM pVM = pVCpu->CTX_SUFF(pVM);
3896	Assert(!pVM->hm.s.fNestedPaging);
3897
3898	/** @todo Decode Assist. */
3899	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3900	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3901	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3902	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3903	return rc;
3904	}
3905
3906
3907	/**
3908	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3909	*/
3910	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3911	{
3912	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3913	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
3914	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3915	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3916	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3917	return rc;
3918	}
3919
3920
3921	/**
3922	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3923	*/
3924	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3925	{
3926	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3927	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3928	if (RT_LIKELY(rc == VINF_SUCCESS))
3929	{
3930	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3931	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3932	}
3933	else
3934	{
3935	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3936	rc = VERR_EM_INTERPRETER;
3937	}
3938	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3939	return rc;
3940	}
3941
3942
3943	/**
3944	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3945	*/
3946	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3947	{
3948	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3949	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3950	int rc = VBOXSTRICTRC_VAL(rc2);
3951	if ( rc == VINF_EM_HALT
3952	\|\| rc == VINF_SUCCESS)
3953	{
3954	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3955
3956	if ( rc == VINF_EM_HALT
3957	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3958	{
3959	rc = VINF_SUCCESS;
3960	}
3961	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3962	}
3963	else
3964	{
3965	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3966	rc = VERR_EM_INTERPRETER;
3967	}
3968	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3969	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3970	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3971	return rc;
3972	}
3973
3974
3975	/**
3976	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
3977	* Conditional #VMEXIT.
3978	*/
3979	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3980	{
3981	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3982	return VINF_EM_RESET;
3983	}
3984
3985
3986	/**
3987	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
3988	*/
3989	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3990	{
3991	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3992
3993	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3994
3995	/** @todo Decode Assist. */
3996	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
3997	int rc = VBOXSTRICTRC_VAL(rc2);
3998	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
3999	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4000	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4001	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4002	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4003	return rc;
4004	}
4005
4006
4007	/**
4008	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
4009	*/
4010	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4011	{
4012	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4013	/** @todo Decode Assist. */
4014	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4015	int rc = VBOXSTRICTRC_VAL(rc2);
4016	if (rc == VINF_SUCCESS)
4017	{
4018	/* RIP has been updated by EMInterpretInstruction(). */
4019	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4020	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4021	{
4022	case 0: /* CR0. */
4023	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4024	break;
4025
4026	case 3: /* CR3. */
4027	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4028	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
4029	break;
4030
4031	case 4: /* CR4. */
4032	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
4033	break;
4034
4035	case 8: /* CR8 (TPR). */
4036	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4037	break;
4038
4039	default:
4040	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4041	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4042	break;
4043	}
4044	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4045	}
4046	else
4047	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
4048	return rc;
4049	}
4050
4051
4052	/**
4053	* #VMEXIT handler for instructions that result in a #UD exception delivered to
4054	* the guest.
4055	*/
4056	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4057	{
4058	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4059	hmR0SvmSetPendingXcptUD(pVCpu);
4060	return VINF_SUCCESS;
4061	}
4062
4063
4064	/**
4065	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4066	*/
4067	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4068	{
4069	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4070	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4071	PVM pVM = pVCpu->CTX_SUFF(pVM);
4072
4073	int rc;
4074	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4075	{
4076	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4077
4078	/* Handle TPR patching; intercepted LSTAR write. */
4079	if ( pVM->hm.s.fTPRPatchingActive
4080	&& pCtx->ecx == MSR_K8_LSTAR)
4081	{
4082	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4083	{
4084	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4085	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4086	AssertRC(rc2);
4087	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4088	}
4089	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4090	rc = VINF_SUCCESS;
4091	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4092	return rc;
4093	}
4094
4095	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4096	{
4097	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4098	if (RT_LIKELY(rc == VINF_SUCCESS))
4099	{
4100	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4101	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4102	}
4103	else
4104	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4105	}
4106	else
4107	{
4108	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4109	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4110	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4111	/* RIP updated by EMInterpretInstruction(). */
4112	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4113	}
4114
4115	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4116	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4117	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4118	{
4119	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4120	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4121	EMInterpretWrmsr() changes it. */
4122	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4123	}
4124	else if (pCtx->ecx == MSR_K6_EFER)
4125	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
4126	else if (pCtx->ecx == MSR_IA32_TSC)
4127	pSvmTransient->fUpdateTscOffsetting = true;
4128	}
4129	else
4130	{
4131	/* MSR Read access. */
4132	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4133	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4134
4135	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4136	{
4137	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4138	if (RT_LIKELY(rc == VINF_SUCCESS))
4139	{
4140	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4141	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4142	}
4143	else
4144	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4145	}
4146	else
4147	{
4148	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4149	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4150	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4151	/* RIP updated by EMInterpretInstruction(). */
4152	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4153	}
4154	}
4155
4156	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4157	return rc;
4158	}
4159
4160
4161	/**
4162	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4163	*/
4164	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4165	{
4166	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4167	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4168
4169	/* We should -not- get this VM-exit if the guest is debugging. */
4170	AssertMsgReturn(!CPUMIsGuestDebugStateActive(pVCpu),
4171	("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx),
4172	VERR_SVM_UNEXPECTED_EXIT);
4173
4174	/*
4175	* Lazy DR0-3 loading?
4176	*/
4177	if (!CPUMIsHyperDebugStateActive(pVCpu))
4178	{
4179	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4180	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4181
4182	/* Don't intercept DRx read and writes. */
4183	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4184	pVmcb->ctrl.u16InterceptRdDRx = 0;
4185	pVmcb->ctrl.u16InterceptWrDRx = 0;
4186	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4187
4188	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4189	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4190	Assert(CPUMIsGuestDebugStateActive(pVCpu));
4191
4192	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4193	return VINF_SUCCESS;
4194	}
4195
4196	/*
4197	* Interpret the read/writing of DRx.
4198	*/
4199	/** @todo Decode assist. */
4200	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4201	Log5(("hmR0SvmExitReadDRx: Emulatined DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4202	if (RT_LIKELY(rc == VINF_SUCCESS))
4203	{
4204	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4205	/** @todo CPUM should set this flag! */
4206	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4207	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4208	}
4209	else
4210	Assert(rc == VERR_EM_INTERPRETER);
4211	return VBOXSTRICTRC_TODO(rc);
4212	}
4213
4214
4215	/**
4216	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4217	*/
4218	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4219	{
4220	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4221	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4222	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4223	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4224	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4225	return rc;
4226	}
4227
4228
4229	/**
4230	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4231	*/
4232	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4233	{
4234	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4235
4236	/* I/O operation lookup arrays. */
4237	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4238	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4239	the result (in AL/AX/EAX). */
4240	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4241
4242	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4243	PVM pVM = pVCpu->CTX_SUFF(pVM);
4244
4245	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4246	SVMIOIOEXIT IoExitInfo;
4247	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4248	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4249	uint32_t cbValue = s_aIOSize[uIOWidth];
4250	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4251
4252	if (RT_UNLIKELY(!cbValue))
4253	{
4254	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4255	return VERR_EM_INTERPRETER;
4256	}
4257
4258	VBOXSTRICTRC rcStrict;
4259	if (IoExitInfo.n.u1STR)
4260	{
4261	/* INS/OUTS - I/O String instruction. */
4262	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4263
4264	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4265	* in EXITINFO1? Investigate once this thing is up and running. */
4266
4267	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4268	if (rcStrict == VINF_SUCCESS)
4269	{
4270	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4271	{
4272	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4273	(DISCPUMODE)pDis->uAddrMode, cbValue);
4274	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4275	}
4276	else
4277	{
4278	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4279	(DISCPUMODE)pDis->uAddrMode, cbValue);
4280	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4281	}
4282	}
4283	else
4284	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4285	}
4286	else
4287	{
4288	/* IN/OUT - I/O instruction. */
4289	Assert(!IoExitInfo.n.u1REP);
4290
4291	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4292	{
4293	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4294	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4295	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4296
4297	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4298	}
4299	else
4300	{
4301	uint32_t u32Val = 0;
4302
4303	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4304	if (IOM_SUCCESS(rcStrict))
4305	{
4306	/* Save result of I/O IN instr. in AL/AX/EAX. */
4307	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4308	}
4309	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4310	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4311
4312	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4313	}
4314	}
4315
4316	if (IOM_SUCCESS(rcStrict))
4317	{
4318	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4319	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4320
4321	/*
4322	* If any I/O breakpoints are armed, we need to check if one triggered
4323	* and take appropriate action.
4324	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4325	*/
4326	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4327	* execution engines about whether hyper BPs and such are pending. */
4328	uint32_t const uDr7 = pCtx->dr[7];
4329	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4330	&& X86_DR7_ANY_RW_IO(uDr7)
4331	&& (pCtx->cr4 & X86_CR4_DE))
4332	\|\| DBGFBpIsHwIoArmed(pVM)))
4333	{
4334	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4335	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
4336
4337	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4338	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4339	{
4340	/* Raise #DB. */
4341	pVmcb->guest.u64DR6 = pCtx->dr[6];
4342	pVmcb->guest.u64DR7 = pCtx->dr[7];
4343	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4344	hmR0SvmSetPendingXcptDB(pVCpu);
4345	}
4346	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4347	else if ( rcStrict2 != VINF_SUCCESS
4348	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
4349	rcStrict = rcStrict2;
4350	}
4351
4352	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4353	}
4354
4355	#ifdef VBOX_STRICT
4356	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4357	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4358	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4359	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4360	else
4361	{
4362	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4363	* statuses, that the VMM device and some others may return. See
4364	* IOM_SUCCESS() for guidance. */
4365	AssertMsg( RT_FAILURE(rcStrict)
4366	\|\| rcStrict == VINF_SUCCESS
4367	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
4368	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
4369	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
4370	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4371	}
4372	#endif
4373	return VBOXSTRICTRC_TODO(rcStrict);
4374	}
4375
4376
4377	/**
4378	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4379	* #VMEXIT.
4380	*/
4381	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4382	{
4383	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4384	PVM pVM = pVCpu->CTX_SUFF(pVM);
4385	Assert(pVM->hm.s.fNestedPaging);
4386
4387	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4388
4389	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4390	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4391	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4392	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4393
4394	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4395
4396	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4397	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4398	if ( pVM->hm.s.fTRPPatchingAllowed
4399	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4400	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4401	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4402	&& !CPUMGetGuestCPL(pVCpu)
4403	&& !CPUMIsGuestInLongModeEx(pCtx)
4404	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4405	{
4406	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4407	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4408
4409	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4410	{
4411	/* Only attempt to patch the instruction once. */
4412	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4413	if (!pPatch)
4414	return VINF_EM_HM_PATCH_TPR_INSTR;
4415	}
4416	}
4417	#endif
4418
4419	/*
4420	* Determine the nested paging mode.
4421	*/
4422	PGMMODE enmNestedPagingMode;
4423	#if HC_ARCH_BITS == 32
4424	if (CPUMIsGuestInLongModeEx(pCtx))
4425	enmNestedPagingMode = PGMMODE_AMD64_NX;
4426	else
4427	#endif
4428	enmNestedPagingMode = PGMGetHostMode(pVM);
4429
4430	/*
4431	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4432	*/
4433	int rc;
4434	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4435	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4436	{
4437	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4438	u32ErrCode);
4439	rc = VBOXSTRICTRC_VAL(rc2);
4440
4441	/*
4442	* If we succeed, resume guest execution.
4443	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4444	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4445	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4446	* weird case. See @bugref{6043}.
4447	*/
4448	if ( rc == VINF_SUCCESS
4449	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4450	\|\| rc == VERR_PAGE_NOT_PRESENT)
4451	{
4452	/* Successfully handled MMIO operation. */
4453	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4454	rc = VINF_SUCCESS;
4455	}
4456	return rc;
4457	}
4458
4459	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4460	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4461	TRPMResetTrap(pVCpu);
4462
4463	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4464
4465	/*
4466	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4467	*/
4468	if ( rc == VINF_SUCCESS
4469	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4470	\|\| rc == VERR_PAGE_NOT_PRESENT)
4471	{
4472	/* We've successfully synced our shadow page tables. */
4473	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4474	rc = VINF_SUCCESS;
4475	}
4476
4477	return rc;
4478	}
4479
4480
4481	/**
4482	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4483	*/
4484	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4485	{
4486	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4487
4488	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4489	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4490	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4491
4492	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4493	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4494	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4495
4496	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4497	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4498	return VINF_SUCCESS;
4499	}
4500
4501
4502	/**
4503	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4504	*/
4505	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4506	{
4507	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4508
4509	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4510	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4511	#endif
4512
4513	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4514	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4515	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4516	&& pVCpu->hm.s.Event.fPending)
4517	{
4518	/*
4519	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4520	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4521	* when the recompiler restarts the instruction.
4522	*/
4523	SVMEVENT Event;
4524	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4525	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4526	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4527	{
4528	pVCpu->hm.s.Event.fPending = false;
4529	}
4530	else
4531	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4532	}
4533
4534	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4535	* emulation. */
4536	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4537	return VERR_EM_INTERPRETER;
4538	}
4539
4540
4541	/**
4542	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4543	*/
4544	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4545	{
4546	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4547
4548	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4549	if (RT_LIKELY(rc == VINF_SUCCESS))
4550	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4551	else
4552	hmR0SvmSetPendingXcptUD(pVCpu);
4553	return VINF_SUCCESS;
4554	}
4555
4556
4557	/**
4558	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4559	* #VMEXIT.
4560	*/
4561	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4562	{
4563	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4564
4565	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4566
4567	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4568	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4569	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4570	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4571	PVM pVM = pVCpu->CTX_SUFF(pVM);
4572
4573	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4574	if (pVM->hm.s.fNestedPaging)
4575	{
4576	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4577	if (!pSvmTransient->fVectoringPF)
4578	{
4579	/* A genuine guest #PF, reflect it to the guest. */
4580	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4581	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4582	uFaultAddress, u32ErrCode));
4583	}
4584	else
4585	{
4586	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4587	hmR0SvmSetPendingXcptDF(pVCpu);
4588	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4589	}
4590	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4591	return VINF_SUCCESS;
4592	}
4593	#endif
4594
4595	Assert(!pVM->hm.s.fNestedPaging);
4596
4597	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4598	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4599	if ( pVM->hm.s.fTRPPatchingAllowed
4600	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4601	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
4602	&& !CPUMGetGuestCPL(pVCpu)
4603	&& !CPUMIsGuestInLongModeEx(pCtx)
4604	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4605	{
4606	RTGCPHYS GCPhysApicBase;
4607	GCPhysApicBase = pCtx->msrApicBase;
4608	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4609
4610	/* Check if the page at the fault-address is the APIC base. */
4611	RTGCPHYS GCPhysPage;
4612	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4613	if ( rc2 == VINF_SUCCESS
4614	&& GCPhysPage == GCPhysApicBase)
4615	{
4616	/* Only attempt to patch the instruction once. */
4617	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4618	if (!pPatch)
4619	return VINF_EM_HM_PATCH_TPR_INSTR;
4620	}
4621	}
4622	#endif
4623
4624	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4625	pCtx->rip, u32ErrCode, pCtx->cr3));
4626
4627	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4628	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4629
4630	Log4(("#PF rc=%Rrc\n", rc));
4631
4632	if (rc == VINF_SUCCESS)
4633	{
4634	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4635	TRPMResetTrap(pVCpu);
4636	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4637	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4638	return rc;
4639	}
4640	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4641	{
4642	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4643
4644	if (!pSvmTransient->fVectoringPF)
4645	{
4646	/* It's a guest page fault and needs to be reflected to the guest. */
4647	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4648	TRPMResetTrap(pVCpu);
4649	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4650	}
4651	else
4652	{
4653	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4654	TRPMResetTrap(pVCpu);
4655	hmR0SvmSetPendingXcptDF(pVCpu);
4656	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4657	}
4658
4659	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4660	return VINF_SUCCESS;
4661	}
4662
4663	TRPMResetTrap(pVCpu);
4664	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4665	return rc;
4666	}
4667
4668
4669	/**
4670	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4671	* Conditional #VMEXIT.
4672	*/
4673	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4674	{
4675	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4676
4677	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4678
4679	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4680	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4681	#endif
4682
4683	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4684	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4685	if (rc == VINF_SUCCESS)
4686	{
4687	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4688	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4689	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4690	return VINF_SUCCESS;
4691	}
4692
4693	/* Forward #NM to the guest. */
4694	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4695	hmR0SvmSetPendingXcptNM(pVCpu);
4696	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4697	return VINF_SUCCESS;
4698	}
4699
4700
4701	/**
4702	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4703	* Conditional #VMEXIT.
4704	*/
4705	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4706	{
4707	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4708
4709	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4710
4711	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4712
4713	if (!(pCtx->cr0 & X86_CR0_NE))
4714	{
4715	/* Old-style FPU error reporting needs some extra work. */
4716	/** @todo don't fall back to the recompiler, but do it manually. */
4717	return VERR_EM_INTERPRETER;
4718	}
4719
4720	hmR0SvmSetPendingXcptMF(pVCpu);
4721	return VINF_SUCCESS;
4722	}
4723
4724
4725	/**
4726	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4727	* #VMEXIT.
4728	*/
4729	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4730	{
4731	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4732
4733	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4734
4735	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4736
4737	/* If we set the trap flag above, we have to clear it. */
4738	if (pVCpu->hm.s.fClearTrapFlag)
4739	{
4740	pVCpu->hm.s.fClearTrapFlag = false;
4741	pCtx->eflags.Bits.u1TF = 0;
4742	}
4743
4744	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4745	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4746	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4747	PVM pVM = pVCpu->CTX_SUFF(pVM);
4748	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
4749	if (rc == VINF_EM_RAW_GUEST_TRAP)
4750	{
4751	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
4752	if (CPUMIsHyperDebugStateActive(pVCpu))
4753	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
4754
4755	/* Reflect the exception back to the guest. */
4756	hmR0SvmSetPendingXcptDB(pVCpu);
4757	rc = VINF_SUCCESS;
4758	}
4759
4760	/*
4761	* Update DR6.
4762	*/
4763	if (CPUMIsHyperDebugStateActive(pVCpu))
4764	{
4765	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
4766	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
4767	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4768	}
4769	else
4770	{
4771	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
4772	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
4773	}
4774
4775	return rc;
4776	}
4777
4778	/** @} */
4779

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 48037

Download in other formats: