HMSVMR0.cpp@ 48140

Last change on this file since 48140 was 48140, checked in by vboxsync, 11 years ago
VMM/HMVMXR0: Safer longjmp coverage, only restore host state when altered by VT-x. VMM/HMSVMR0: Exit normally while getting errors during the world-switch.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 182.1 KB

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1	/* $Id: HMSVMR0.cpp 48140 2013-08-29 09:39:53Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HMSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
38	#endif
39
40
41	/*******************************************************************************
42	* Defined Constants And Macros *
43	*******************************************************************************/
44	#ifdef VBOX_WITH_STATISTICS
45	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
46	if ((u64ExitCode) == SVM_EXIT_NPF) \
47	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
48	else \
49	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
50	} while (0)
51	#else
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
53	#endif
54
55	/** If we decide to use a function table approach this can be useful to
56	* switch to a "static DECLCALLBACK(int)". */
57	#define HMSVM_EXIT_DECL static int
58
59
60	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
61	*
62	* The CPU format of the segment attribute is described in X86DESCATTRBITS
63	* which is 16-bits (i.e. includes 4 bits of the segment limit).
64	*
65	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
66	* only the attribute bits and nothing else). Upper 4-bits are unused.
67	*
68	* @{ */
69	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
70	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
71	/** @} */
72
73
74	/** @name Macros for loading, storing segment registers to/from the VMCB.
75	* @{ */
76	#define HMSVM_LOAD_SEG_REG(REG, reg) \
77	do \
78	{ \
79	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
80	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
81	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
82	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
83	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
84	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
85	} while (0)
86
87	#define HMSVM_SAVE_SEG_REG(REG, reg) \
88	do \
89	{ \
90	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
92	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
93	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
94	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
95	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
96	} while (0)
97	/** @} */
98
99
100	/** Macro for checking and returning from the using function for
101	* \#VMEXIT intercepts that maybe caused during delivering of another
102	* event in the guest. */
103	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
104	do \
105	{ \
106	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
107	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
108	return VINF_SUCCESS; \
109	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
110	return rc; \
111	} while (0)
112
113	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
114	* instruction that exited. */
115	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
116	do { \
117	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
118	(a_rc) = VINF_EM_DBG_STEPPED; \
119	} while (0)
120
121	/** Assert that preemption is disabled or covered by thread-context hooks. */
122	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
123	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
124
125	/** Assert that we haven't migrated CPUs when thread-context hooks are not
126	* used. */
127	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
128	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
129	("Illegal migration! Entered on CPU %u Current %u\n", \
130	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
131
132	/** Exception bitmap mask for all contributory exceptions.
133	*
134	* Page fault is deliberately excluded here as it's conditional as to whether
135	* it's contributory or benign. Page faults are handled separately.
136	*/
137	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
138	\| RT_BIT(X86_XCPT_DE))
139
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG uEflags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
211	bool fRestoreTscAuxMsr;
212	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
213	* contributary exception or a page-fault. */
214	bool fVectoringPF;
215	/** Whether the TSC offset mode needs to be updated. */
216	bool fUpdateTscOffsetting;
217	} SVMTRANSIENT, *PSVMTRANSIENT;
218	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
219	AssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
220	/** @} */
221
222
223	/**
224	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
225	*/
226	typedef enum SVMMSREXITREAD
227	{
228	/** Reading this MSR causes a VM-exit. */
229	SVMMSREXIT_INTERCEPT_READ = 0xb,
230	/** Reading this MSR does not cause a VM-exit. */
231	SVMMSREXIT_PASSTHRU_READ
232	} SVMMSREXITREAD;
233
234	/**
235	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
236	*/
237	typedef enum SVMMSREXITWRITE
238	{
239	/** Writing to this MSR causes a VM-exit. */
240	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
241	/** Writing to this MSR does not cause a VM-exit. */
242	SVMMSREXIT_PASSTHRU_WRITE
243	} SVMMSREXITWRITE;
244
245
246	/*******************************************************************************
247	* Internal Functions *
248	*******************************************************************************/
249	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
250	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
251	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
252
253	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
257	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
258	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
259	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
263	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
264	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
265	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
266	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
267	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
268	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
269	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
270	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
271	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
272	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
273	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
274	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
275	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
276	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
277	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
278	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
279	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
280
281	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
282
283
284	/*******************************************************************************
285	* Global Variables *
286	*******************************************************************************/
287	/** Ring-0 memory object for the IO bitmap. */
288	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
289	/** Physical address of the IO bitmap. */
290	RTHCPHYS g_HCPhysIOBitmap = 0;
291	/** Virtual address of the IO bitmap. */
292	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
293
294
295	/**
296	* Sets up and activates AMD-V on the current CPU.
297	*
298	* @returns VBox status code.
299	* @param pCpu Pointer to the CPU info struct.
300	* @param pVM Pointer to the VM (can be NULL after a resume!).
301	* @param pvCpuPage Pointer to the global CPU page.
302	* @param HCPhysCpuPage Physical address of the global CPU page.
303	*/
304	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
305	{
306	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
307	AssertReturn( HCPhysCpuPage
308	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
309	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
310
311	/*
312	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
313	*/
314	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
315	if (u64HostEfer & MSR_K6_EFER_SVME)
316	{
317	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
318	if ( pVM
319	&& pVM->hm.s.svm.fIgnoreInUseError)
320	{
321	pCpu->fIgnoreAMDVInUseError = true;
322	}
323
324	if (!pCpu->fIgnoreAMDVInUseError)
325	return VERR_SVM_IN_USE;
326	}
327
328	/* Turn on AMD-V in the EFER MSR. */
329	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
330
331	/* Write the physical page address where the CPU will store the host state while executing the VM. */
332	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
333
334	/*
335	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
336	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
337	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
338	* to flush the TLB with before using a new ASID.
339	*/
340	pCpu->fFlushAsidBeforeUse = true;
341
342	/*
343	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
344	*/
345	++pCpu->cTlbFlushes;
346
347	return VINF_SUCCESS;
348	}
349
350
351	/**
352	* Deactivates AMD-V on the current CPU.
353	*
354	* @returns VBox status code.
355	* @param pCpu Pointer to the CPU info struct.
356	* @param pvCpuPage Pointer to the global CPU page.
357	* @param HCPhysCpuPage Physical address of the global CPU page.
358	*/
359	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
360	{
361	AssertReturn( HCPhysCpuPage
362	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
363	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
364	NOREF(pCpu);
365
366	/* Turn off AMD-V in the EFER MSR. */
367	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
368	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
369
370	/* Invalidate host state physical address. */
371	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
372
373	return VINF_SUCCESS;
374	}
375
376
377	/**
378	* Does global AMD-V initialization (called during module initialization).
379	*
380	* @returns VBox status code.
381	*/
382	VMMR0DECL(int) SVMR0GlobalInit(void)
383	{
384	/*
385	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
386	* once globally here instead of per-VM.
387	*/
388	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
389	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
390	if (RT_FAILURE(rc))
391	return rc;
392
393	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
394	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
395
396	/* Set all bits to intercept all IO accesses. */
397	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
398	return VINF_SUCCESS;
399	}
400
401
402	/**
403	* Does global AMD-V termination (called during module termination).
404	*/
405	VMMR0DECL(void) SVMR0GlobalTerm(void)
406	{
407	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
408	{
409	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
410	g_pvIOBitmap = NULL;
411	g_HCPhysIOBitmap = 0;
412	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
413	}
414	}
415
416
417	/**
418	* Frees any allocated per-VCPU structures for a VM.
419	*
420	* @param pVM Pointer to the VM.
421	*/
422	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
423	{
424	for (uint32_t i = 0; i < pVM->cCpus; i++)
425	{
426	PVMCPU pVCpu = &pVM->aCpus[i];
427	AssertPtr(pVCpu);
428
429	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
430	{
431	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
432	pVCpu->hm.s.svm.pvVmcbHost = 0;
433	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
434	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
435	}
436
437	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
438	{
439	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
440	pVCpu->hm.s.svm.pvVmcb = 0;
441	pVCpu->hm.s.svm.HCPhysVmcb = 0;
442	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
443	}
444
445	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
446	{
447	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
448	pVCpu->hm.s.svm.pvMsrBitmap = 0;
449	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
450	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
451	}
452	}
453	}
454
455
456	/**
457	* Does per-VM AMD-V initialization.
458	*
459	* @returns VBox status code.
460	* @param pVM Pointer to the VM.
461	*/
462	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
463	{
464	int rc = VERR_INTERNAL_ERROR_5;
465
466	/*
467	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
468	*/
469	uint32_t u32Family;
470	uint32_t u32Model;
471	uint32_t u32Stepping;
472	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
473	{
474	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
475	pVM->hm.s.svm.fAlwaysFlushTLB = true;
476	}
477
478	/*
479	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
480	*/
481	for (VMCPUID i = 0; i < pVM->cCpus; i++)
482	{
483	PVMCPU pVCpu = &pVM->aCpus[i];
484	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
485	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
486	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
487	}
488
489	for (VMCPUID i = 0; i < pVM->cCpus; i++)
490	{
491	PVMCPU pVCpu = &pVM->aCpus[i];
492
493	/*
494	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
495	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
496	*/
497	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
498	if (RT_FAILURE(rc))
499	goto failure_cleanup;
500
501	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
502	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
503	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
504	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
505
506	/*
507	* Allocate one page for the guest-state VMCB.
508	*/
509	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
510	if (RT_FAILURE(rc))
511	goto failure_cleanup;
512
513	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
514	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
515	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
516	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
517
518	/*
519	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
520	* SVM to not require one.
521	*/
522	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
523	if (RT_FAILURE(rc))
524	goto failure_cleanup;
525
526	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
527	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
528	/* Set all bits to intercept all MSR accesses (changed later on). */
529	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
530	}
531
532	return VINF_SUCCESS;
533
534	failure_cleanup:
535	hmR0SvmFreeStructs(pVM);
536	return rc;
537	}
538
539
540	/**
541	* Does per-VM AMD-V termination.
542	*
543	* @returns VBox status code.
544	* @param pVM Pointer to the VM.
545	*/
546	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
547	{
548	hmR0SvmFreeStructs(pVM);
549	return VINF_SUCCESS;
550	}
551
552
553	/**
554	* Sets the permission bits for the specified MSR in the MSRPM.
555	*
556	* @param pVCpu Pointer to the VMCPU.
557	* @param uMsr The MSR for which the access permissions are being set.
558	* @param enmRead MSR read permissions.
559	* @param enmWrite MSR write permissions.
560	*/
561	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
562	{
563	unsigned ulBit;
564	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
565
566	/*
567	* Layout:
568	* Byte offset MSR range
569	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
570	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
571	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
572	* 0x1800 - 0x1fff Reserved
573	*/
574	if (uMsr <= 0x00001FFF)
575	{
576	/* Pentium-compatible MSRs. */
577	ulBit = uMsr * 2;
578	}
579	else if ( uMsr >= 0xC0000000
580	&& uMsr <= 0xC0001FFF)
581	{
582	/* AMD Sixth Generation x86 Processor MSRs. */
583	ulBit = (uMsr - 0xC0000000) * 2;
584	pbMsrBitmap += 0x800;
585	}
586	else if ( uMsr >= 0xC0010000
587	&& uMsr <= 0xC0011FFF)
588	{
589	/* AMD Seventh and Eighth Generation Processor MSRs. */
590	ulBit = (uMsr - 0xC0001000) * 2;
591	pbMsrBitmap += 0x1000;
592	}
593	else
594	{
595	AssertFailed();
596	return;
597	}
598
599	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
600	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
601	ASMBitSet(pbMsrBitmap, ulBit);
602	else
603	ASMBitClear(pbMsrBitmap, ulBit);
604
605	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
606	ASMBitSet(pbMsrBitmap, ulBit + 1);
607	else
608	ASMBitClear(pbMsrBitmap, ulBit + 1);
609
610	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
611	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
612	}
613
614
615	/**
616	* Sets up AMD-V for the specified VM.
617	* This function is only called once per-VM during initalization.
618	*
619	* @returns VBox status code.
620	* @param pVM Pointer to the VM.
621	*/
622	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
623	{
624	int rc = VINF_SUCCESS;
625
626	AssertReturn(pVM, VERR_INVALID_PARAMETER);
627	Assert(pVM->hm.s.svm.fSupported);
628
629	for (VMCPUID i = 0; i < pVM->cCpus; i++)
630	{
631	PVMCPU pVCpu = &pVM->aCpus[i];
632	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
633
634	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
635
636	/* Trap exceptions unconditionally (debug purposes). */
637	#ifdef HMSVM_ALWAYS_TRAP_PF
638	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
639	#endif
640	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
641	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
642	pVmcb->ctrl.u32InterceptException \|= 0
643	\| RT_BIT(X86_XCPT_BP)
644	\| RT_BIT(X86_XCPT_DB)
645	\| RT_BIT(X86_XCPT_DE)
646	\| RT_BIT(X86_XCPT_NM)
647	\| RT_BIT(X86_XCPT_UD)
648	\| RT_BIT(X86_XCPT_NP)
649	\| RT_BIT(X86_XCPT_SS)
650	\| RT_BIT(X86_XCPT_GP)
651	\| RT_BIT(X86_XCPT_PF)
652	\| RT_BIT(X86_XCPT_MF)
653	;
654	#endif
655
656	/* Set up unconditional intercepts and conditions. */
657	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
658	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
659	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
660	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
661	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
662	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
663	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
664	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
665	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
666	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
667	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
668	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
669
670	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
671	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
672	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
673	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
674	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
675	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
676	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
677	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
678	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
679	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
680
681	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
682	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
683
684	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
685	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
686
687	/* Intercept all DRx reads and writes by default. Changed later on. */
688	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
689	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
690
691	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
692	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
693
694	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
695	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
696	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
697
698	/* Set IO and MSR bitmap permission bitmap physical addresses. */
699	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
700	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
701
702	/* No LBR virtualization. */
703	pVmcb->ctrl.u64LBRVirt = 0;
704
705	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
706	pVmcb->ctrl.u64VmcbCleanBits = 0;
707
708	/* The host ASID MBZ, for the guest start with 1. */
709	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
710
711	/*
712	* Setup the PAT MSR (applicable for Nested Paging only).
713	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
714	* so choose type 6 for all PAT slots.
715	*/
716	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
717
718	/* Without Nested Paging, we need additionally intercepts. */
719	if (!pVM->hm.s.fNestedPaging)
720	{
721	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
722	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
723	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
724
725	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
726	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
727	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
728
729	/* Page faults must be intercepted to implement shadow paging. */
730	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
731	}
732
733	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
734	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
735	#endif
736
737	/*
738	* The following MSRs are saved/restored automatically during the world-switch.
739	* Don't intercept guest read/write accesses to these MSRs.
740	*/
741	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
742	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
743	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
744	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
745	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
746	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
747	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
748	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
749	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
750	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
751	}
752
753	return rc;
754	}
755
756
757	/**
758	* Invalidates a guest page by guest virtual address.
759	*
760	* @returns VBox status code.
761	* @param pVM Pointer to the VM.
762	* @param pVCpu Pointer to the VMCPU.
763	* @param GCVirt Guest virtual address of the page to invalidate.
764	*/
765	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
766	{
767	AssertReturn(pVM, VERR_INVALID_PARAMETER);
768	Assert(pVM->hm.s.svm.fSupported);
769
770	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
771
772	/* Skip it if a TLB flush is already pending. */
773	if (!fFlushPending)
774	{
775	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
776
777	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
778	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
779
780	#if HC_ARCH_BITS == 32
781	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
782	if (CPUMIsGuestInLongMode(pVCpu))
783	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
784	else
785	#endif
786	{
787	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
788	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
789	}
790	}
791	return VINF_SUCCESS;
792	}
793
794
795	/**
796	* Flushes the appropriate tagged-TLB entries.
797	*
798	* @param pVM Pointer to the VM.
799	* @param pVCpu Pointer to the VMCPU.
800	*/
801	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
802	{
803	PVM pVM = pVCpu->CTX_SUFF(pVM);
804	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
805	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
806
807	/*
808	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
809	* This can happen both for start & resume due to long jumps back to ring-3.
810	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
811	* so we cannot reuse the ASIDs without flushing.
812	*/
813	bool fNewAsid = false;
814	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
815	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
816	{
817	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
818	pVCpu->hm.s.fForceTLBFlush = true;
819	fNewAsid = true;
820	}
821
822	/* Set TLB flush state as checked until we return from the world switch. */
823	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
824
825	/* Check for explicit TLB shootdowns. */
826	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
827	{
828	pVCpu->hm.s.fForceTLBFlush = true;
829	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
830	}
831
832	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
833	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
834
835	if (pVM->hm.s.svm.fAlwaysFlushTLB)
836	{
837	/*
838	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
839	*/
840	pCpu->uCurrentAsid = 1;
841	pVCpu->hm.s.uCurrentAsid = 1;
842	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
843	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
844	}
845	else if (pVCpu->hm.s.fForceTLBFlush)
846	{
847	if (fNewAsid)
848	{
849	++pCpu->uCurrentAsid;
850	bool fHitASIDLimit = false;
851	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
852	{
853	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
854	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
855	fHitASIDLimit = true;
856
857	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
858	{
859	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
860	pCpu->fFlushAsidBeforeUse = true;
861	}
862	else
863	{
864	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
865	pCpu->fFlushAsidBeforeUse = false;
866	}
867	}
868
869	if ( !fHitASIDLimit
870	&& pCpu->fFlushAsidBeforeUse)
871	{
872	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
873	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
874	else
875	{
876	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
877	pCpu->fFlushAsidBeforeUse = false;
878	}
879	}
880
881	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
882	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
883	}
884	else
885	{
886	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
887	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
888	else
889	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
890	}
891
892	pVCpu->hm.s.fForceTLBFlush = false;
893	}
894	else
895	{
896	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
897	* not be executed. See hmQueueInvlPage() where it is commented
898	* out. Support individual entry flushing someday. */
899	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
900	{
901	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
902	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
903	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
904	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
905	}
906	}
907
908	pVCpu->hm.s.TlbShootdown.cPages = 0;
909	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
910
911	/* Update VMCB with the ASID. */
912	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
913	{
914	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
915	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
916	}
917
918	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
919	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
920	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
921	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
922	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
923	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
924
925	#ifdef VBOX_WITH_STATISTICS
926	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
927	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
928	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
929	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
930	{
931	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
932	}
933	else
934	{
935	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
936	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
937	}
938	#endif
939	}
940
941
942	/** @name 64-bit guest on 32-bit host OS helper functions.
943	*
944	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
945	* mode (code segment, paging). These wrappers/helpers perform the necessary
946	* bits for the 32->64 switcher.
947	*
948	* @{ */
949	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
950	/**
951	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
952	*
953	* @returns VBox status code.
954	* @param HCPhysVmcbHost Physical address of host VMCB.
955	* @param HCPhysVmcb Physical address of the VMCB.
956	* @param pCtx Pointer to the guest-CPU context.
957	* @param pVM Pointer to the VM.
958	* @param pVCpu Pointer to the VMCPU.
959	*/
960	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
961	{
962	uint32_t aParam[4];
963	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
964	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
965	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
966	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
967
968	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
969	}
970
971
972	/**
973	* Executes the specified VMRUN handler in 64-bit mode.
974	*
975	* @returns VBox status code.
976	* @param pVM Pointer to the VM.
977	* @param pVCpu Pointer to the VMCPU.
978	* @param pCtx Pointer to the guest-CPU context.
979	* @param enmOp The operation to perform.
980	* @param cbParam Number of parameters.
981	* @param paParam Array of 32-bit parameters.
982	*/
983	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
984	uint32_t *paParam)
985	{
986	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
987	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
988
989	/* Disable interrupts. */
990	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
991
992	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
993	RTCPUID idHostCpu = RTMpCpuId();
994	CPUMR0SetLApic(pVCpu, idHostCpu);
995	#endif
996
997	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
998	CPUMSetHyperEIP(pVCpu, enmOp);
999	for (int i = (int)cbParam - 1; i >= 0; i--)
1000	CPUMPushHyper(pVCpu, paParam[i]);
1001
1002	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1003	/* Call the switcher. */
1004	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1005	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1006
1007	/* Restore interrupts. */
1008	ASMSetFlags(uOldEFlags);
1009	return rc;
1010	}
1011
1012	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1013	/** @} */
1014
1015
1016	/**
1017	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1018	* the corresponding VMCB Clean Bit.
1019	*
1020	* @param pVmcb Pointer to the VMCB.
1021	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1022	*/
1023	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1024	{
1025	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1026	{
1027	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1028	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1029	}
1030	}
1031
1032
1033	/**
1034	* Removes an exception from the intercept-exception bitmap in the VMCB and
1035	* updates the corresponding VMCB Clean Bit.
1036	*
1037	* @param pVmcb Pointer to the VMCB.
1038	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1039	*/
1040	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1041	{
1042	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1043	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1044	{
1045	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1046	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1047	}
1048	#endif
1049	}
1050
1051
1052	/**
1053	* Loads the guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1054	*
1055	* @returns VBox status code.
1056	* @param pVCpu Pointer to the VMCPU.
1057	* @param pVmcb Pointer to the VMCB.
1058	* @param pCtx Pointer the guest-CPU context.
1059	*
1060	* @remarks No-long-jump zone!!!
1061	*/
1062	DECLINLINE(int) hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1063	{
1064	/*
1065	* Guest CR0.
1066	*/
1067	PVM pVM = pVCpu->CTX_SUFF(pVM);
1068	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1069	{
1070	uint64_t u64GuestCR0 = pCtx->cr0;
1071
1072	/* Always enable caching. */
1073	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1074
1075	/*
1076	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1077	*/
1078	if (!pVM->hm.s.fNestedPaging)
1079	{
1080	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1081	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1082	}
1083
1084	/*
1085	* Guest FPU bits.
1086	*/
1087	bool fInterceptNM = false;
1088	bool fInterceptMF = false;
1089	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1090	if (CPUMIsGuestFPUStateActive(pVCpu))
1091	{
1092	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1093	if (!(u64GuestCR0 & X86_CR0_NE))
1094	{
1095	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1096	fInterceptMF = true;
1097	}
1098	}
1099	else
1100	{
1101	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1102	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1103	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1104	}
1105
1106	/*
1107	* Update the exception intercept bitmap.
1108	*/
1109	if (fInterceptNM)
1110	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1111	else
1112	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1113
1114	if (fInterceptMF)
1115	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1116	else
1117	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1118
1119	pVmcb->guest.u64CR0 = u64GuestCR0;
1120	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1121	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1122	}
1123
1124	/*
1125	* Guest CR2.
1126	*/
1127	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1128	{
1129	pVmcb->guest.u64CR2 = pCtx->cr2;
1130	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1131	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1132	}
1133
1134	/*
1135	* Guest CR3.
1136	*/
1137	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1138	{
1139	if (pVM->hm.s.fNestedPaging)
1140	{
1141	PGMMODE enmShwPagingMode;
1142	#if HC_ARCH_BITS == 32
1143	if (CPUMIsGuestInLongModeEx(pCtx))
1144	enmShwPagingMode = PGMMODE_AMD64_NX;
1145	else
1146	#endif
1147	enmShwPagingMode = PGMGetHostMode(pVM);
1148
1149	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1150	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1151	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1152	pVmcb->guest.u64CR3 = pCtx->cr3;
1153	}
1154	else
1155	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1156
1157	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1158	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1159	}
1160
1161	/*
1162	* Guest CR4.
1163	*/
1164	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1165	{
1166	uint64_t u64GuestCR4 = pCtx->cr4;
1167	if (!pVM->hm.s.fNestedPaging)
1168	{
1169	switch (pVCpu->hm.s.enmShadowMode)
1170	{
1171	case PGMMODE_REAL:
1172	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1173	AssertFailed();
1174	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1175
1176	case PGMMODE_32_BIT: /* 32-bit paging. */
1177	u64GuestCR4 &= ~X86_CR4_PAE;
1178	break;
1179
1180	case PGMMODE_PAE: /* PAE paging. */
1181	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1182	/** Must use PAE paging as we could use physical memory > 4 GB */
1183	u64GuestCR4 \|= X86_CR4_PAE;
1184	break;
1185
1186	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1187	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1188	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1189	break;
1190	#else
1191	AssertFailed();
1192	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1193	#endif
1194
1195	default: /* shut up gcc */
1196	AssertFailed();
1197	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1198	}
1199	}
1200
1201	pVmcb->guest.u64CR4 = u64GuestCR4;
1202	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1203	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1204	}
1205
1206	return VINF_SUCCESS;
1207	}
1208
1209
1210	/**
1211	* Loads the guest segment registers into the VMCB.
1212	*
1213	* @returns VBox status code.
1214	* @param pVCpu Pointer to the VMCPU.
1215	* @param pVmcb Pointer to the VMCB.
1216	* @param pCtx Pointer to the guest-CPU context.
1217	*
1218	* @remarks No-long-jump zone!!!
1219	*/
1220	DECLINLINE(void) hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1221	{
1222	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1223	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1224	{
1225	HMSVM_LOAD_SEG_REG(CS, cs);
1226	HMSVM_LOAD_SEG_REG(SS, ss);
1227	HMSVM_LOAD_SEG_REG(DS, ds);
1228	HMSVM_LOAD_SEG_REG(ES, es);
1229	HMSVM_LOAD_SEG_REG(FS, fs);
1230	HMSVM_LOAD_SEG_REG(GS, gs);
1231
1232	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1233	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1234	}
1235
1236	/* Guest TR. */
1237	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1238	{
1239	HMSVM_LOAD_SEG_REG(TR, tr);
1240	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1241	}
1242
1243	/* Guest LDTR. */
1244	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1245	{
1246	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1247	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1248	}
1249
1250	/* Guest GDTR. */
1251	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1252	{
1253	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1254	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1255	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1256	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1257	}
1258
1259	/* Guest IDTR. */
1260	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1261	{
1262	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1263	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1264	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1265	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1266	}
1267	}
1268
1269
1270	/**
1271	* Loads the guest MSRs into the VMCB.
1272	*
1273	* @param pVCpu Pointer to the VMCPU.
1274	* @param pVmcb Pointer to the VMCB.
1275	* @param pCtx Pointer to the guest-CPU context.
1276	*
1277	* @remarks No-long-jump zone!!!
1278	*/
1279	DECLINLINE(void) hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1280	{
1281	/* Guest Sysenter MSRs. */
1282	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1283	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1284	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1285
1286	/*
1287	* Guest EFER MSR.
1288	* AMD-V requires guest EFER.SVME to be set. Weird. .
1289	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1290	*/
1291	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1292	{
1293	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1294	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1295	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1296	}
1297
1298	/* 64-bit MSRs. */
1299	if (CPUMIsGuestInLongModeEx(pCtx))
1300	{
1301	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1302	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1303	}
1304	else
1305	{
1306	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1307	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1308	{
1309	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1310	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1311	}
1312	}
1313
1314
1315	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1316	* be writable in 32-bit mode. Clarify with AMD spec. */
1317	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1318	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1319	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1320	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1321	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1322	}
1323
1324
1325	/**
1326	* Loads the guest debug registers into the VMCB.
1327	*
1328	* @param pVCpu Pointer to the VMCPU.
1329	* @param pVmcb Pointer to the VMCB.
1330	* @param pCtx Pointer to the guest-CPU context.
1331	*
1332	* @remarks No-long-jump zone!!!
1333	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1334	*/
1335	DECLINLINE(void) hmR0SvmLoadGuestDebugRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1336	{
1337	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1338	return;
1339	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1340	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1341
1342	bool fInterceptDB = false;
1343	bool fInterceptMovDRx = false;
1344
1345	/*
1346	* Anyone single stepping on the host side? If so, we'll have to use the
1347	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1348	* the VMM level like VT-x implementations does.
1349	*/
1350	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1351	if (fStepping)
1352	{
1353	pVCpu->hm.s.fClearTrapFlag = true;
1354	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1355	fInterceptDB = true;
1356	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1357	}
1358
1359	PVM pVM = pVCpu->CTX_SUFF(pVM);
1360	if (fStepping \|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1361	{
1362	/*
1363	* Use the combined guest and host DRx values found in the hypervisor
1364	* register set because the debugger has breakpoints active or someone
1365	* is single stepping on the host side.
1366	*
1367	* Note! DBGF expects a clean DR6 state before executing guest code.
1368	*/
1369	if (!CPUMIsHyperDebugStateActive(pVCpu))
1370	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1371	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1372	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1373
1374	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1375	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1376	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu) )
1377	{
1378	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1379	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1380	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1381	}
1382
1383	/** @todo If we cared, we could optimize to allow the guest to read registers
1384	* with the same values. */
1385	fInterceptDB = true;
1386	fInterceptMovDRx = true;
1387	Log5(("hm: Loaded hyper DRx\n"));
1388	}
1389	else
1390	{
1391	/*
1392	* Update DR6, DR7 with the guest values if necessary.
1393	*/
1394	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1395	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1396	{
1397	pVmcb->guest.u64DR7 = pCtx->dr[7];
1398	pVmcb->guest.u64DR6 = pCtx->dr[6];
1399	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1400	}
1401
1402	/*
1403	* If the guest has enabled debug registers, we need to load them prior to
1404	* executing guest code so they'll trigger at the right time.
1405	*/
1406	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1407	{
1408	if (!CPUMIsGuestDebugStateActive(pVCpu))
1409	{
1410	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1411	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1412	}
1413	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1414	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1415	Log5(("hm: Loaded guest DRx\n"));
1416	}
1417	/*
1418	* If no debugging enabled, we'll lazy load DR0-3.
1419	*/
1420	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1421	fInterceptMovDRx = true;
1422	}
1423
1424	/*
1425	* Set up the intercepts.
1426	*/
1427	if (fInterceptDB)
1428	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1429	else
1430	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1431
1432	if (fInterceptMovDRx)
1433	{
1434	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1435	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1436	{
1437	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1438	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1439	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1440	}
1441	}
1442	else
1443	{
1444	if ( pVmcb->ctrl.u16InterceptRdDRx
1445	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1446	{
1447	pVmcb->ctrl.u16InterceptRdDRx = 0;
1448	pVmcb->ctrl.u16InterceptWrDRx = 0;
1449	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1450	}
1451	}
1452
1453	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1454	}
1455
1456
1457	/**
1458	* Loads the guest APIC state (currently just the TPR).
1459	*
1460	* @returns VBox status code.
1461	* @param pVCpu Pointer to the VMCPU.
1462	* @param pVmcb Pointer to the VMCB.
1463	* @param pCtx Pointer to the guest-CPU context.
1464	*/
1465	DECLINLINE(int) hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1466	{
1467	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1468	return VINF_SUCCESS;
1469
1470	bool fPendingIntr;
1471	uint8_t u8Tpr;
1472	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1473	AssertRCReturn(rc, rc);
1474
1475	/** Assume that we need to trap all TPR accesses and thus need not check on
1476	* every #VMEXIT if we should update the TPR. */
1477	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1478	pVCpu->hm.s.svm.fSyncVTpr = false;
1479
1480	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1481	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1482	{
1483	pCtx->msrLSTAR = u8Tpr;
1484
1485	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1486	if (fPendingIntr)
1487	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1488	else
1489	{
1490	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1491	pVCpu->hm.s.svm.fSyncVTpr = true;
1492	}
1493	}
1494	else
1495	{
1496	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1497	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1498
1499	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1500	if (fPendingIntr)
1501	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1502	else
1503	{
1504	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1505	pVCpu->hm.s.svm.fSyncVTpr = true;
1506	}
1507
1508	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1509	}
1510
1511	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1512	return rc;
1513	}
1514
1515
1516	/**
1517	* Sets up the appropriate function to run guest code.
1518	*
1519	* @returns VBox status code.
1520	* @param pVCpu Pointer to the VMCPU.
1521	* @param pCtx Pointer to the guest-CPU context.
1522	*
1523	* @remarks No-long-jump zone!!!
1524	*/
1525	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1526	{
1527	if (CPUMIsGuestInLongModeEx(pCtx))
1528	{
1529	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1530	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1531	#endif
1532	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1533	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1534	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1535	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1536	#else
1537	/* 64-bit host or hybrid host. */
1538	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1539	#endif
1540	}
1541	else
1542	{
1543	/* Guest is not in long mode, use the 32-bit handler. */
1544	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1545	}
1546	return VINF_SUCCESS;
1547	}
1548
1549
1550	/**
1551	* Enters the AMD-V session.
1552	*
1553	* @returns VBox status code.
1554	* @param pVM Pointer to the VM.
1555	* @param pVCpu Pointer to the VMCPU.
1556	* @param pCpu Pointer to the CPU info struct.
1557	*/
1558	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1559	{
1560	AssertPtr(pVM);
1561	AssertPtr(pVCpu);
1562	Assert(pVM->hm.s.svm.fSupported);
1563	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1564	NOREF(pCpu);
1565
1566	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1567
1568	pVCpu->hm.s.fLeaveDone = false;
1569	return VINF_SUCCESS;
1570	}
1571
1572
1573	/**
1574	* Thread-context callback for AMD-V.
1575	*
1576	* @param enmEvent The thread-context event.
1577	* @param pVCpu Pointer to the VMCPU.
1578	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1579	*/
1580	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1581	{
1582	switch (enmEvent)
1583	{
1584	case RTTHREADCTXEVENT_PREEMPTING:
1585	{
1586	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1587	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1588	VMCPU_ASSERT_EMT(pVCpu);
1589
1590	PVM pVM = pVCpu->CTX_SUFF(pVM);
1591	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1592	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1593
1594	if (!pVCpu->hm.s.fLeaveDone)
1595	{
1596	hmR0SvmLeave(pVM, pVCpu, pCtx);
1597	pVCpu->hm.s.fLeaveDone = true;
1598	}
1599
1600	int rc = HMR0LeaveCpu(pVCpu); /* Leave HM context, takes care of local init (term). */
1601	AssertRC(rc); NOREF(rc);
1602
1603	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1604	break;
1605	}
1606
1607	case RTTHREADCTXEVENT_RESUMED:
1608	{
1609	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1610	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1611	VMCPU_ASSERT_EMT(pVCpu);
1612
1613	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1614
1615	/*
1616	* Initialize the bare minimum state required for HM. This takes care of
1617	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1618	*/
1619	int rc = HMR0EnterCpu(pVCpu);
1620	AssertRC(rc); NOREF(rc);
1621	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1622
1623	pVCpu->hm.s.fLeaveDone = false;
1624	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1625	break;
1626	}
1627
1628	default:
1629	break;
1630	}
1631	}
1632
1633
1634	/**
1635	* Saves the host state.
1636	*
1637	* @returns VBox status code.
1638	* @param pVM Pointer to the VM.
1639	* @param pVCpu Pointer to the VMCPU.
1640	*
1641	* @remarks No-long-jump zone!!!
1642	*/
1643	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1644	{
1645	NOREF(pVM);
1646	NOREF(pVCpu);
1647	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1648	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1649	return VINF_SUCCESS;
1650	}
1651
1652
1653	/**
1654	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1655	* fields on every successful VM-entry.
1656	*
1657	* Sets up the appropriate VMRUN function to execute guest code based
1658	* on the guest CPU mode.
1659	*
1660	* @returns VBox status code.
1661	* @param pVM Pointer to the VM.
1662	* @param pVCpu Pointer to the VMCPU.
1663	* @param pMixedCtx Pointer to the guest-CPU context.
1664	*
1665	* @remarks No-long-jump zone!!!
1666	*/
1667	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1668	{
1669	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1670	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1671
1672	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1673
1674	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1675	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1676
1677	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1678	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1679
1680	pVmcb->guest.u64RIP = pCtx->rip;
1681	pVmcb->guest.u64RSP = pCtx->rsp;
1682	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1683	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1684	pVmcb->guest.u64RAX = pCtx->rax;
1685
1686	/* hmR0SvmLoadGuestDebugRegs() must be called -after- updating guest RFLAGS as the RFLAGS may need to be changed. */
1687	hmR0SvmLoadGuestDebugRegs(pVCpu, pVmcb, pCtx);
1688
1689	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1690	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1691
1692	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1693	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1694
1695	/* Clear any unused and reserved bits. */
1696	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1697	\| HM_CHANGED_GUEST_RSP
1698	\| HM_CHANGED_GUEST_RFLAGS
1699	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1700	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1701	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1702	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1703	\| HM_CHANGED_SVM_RESERVED2
1704	\| HM_CHANGED_SVM_RESERVED3);
1705
1706	/* All the guest state bits should be loaded except maybe the host context and shared host/guest bits. */
1707	AssertMsg( !(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_ALL_GUEST)
1708	\|\| !(pVCpu->hm.s.fContextUseFlags & ~(HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE)),
1709	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1710	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1711
1712	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1713
1714	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1715	return rc;
1716	}
1717
1718
1719	/**
1720	* Loads the guest state on the way from ring-3.
1721	*
1722	* @returns VBox status code.
1723	* @param pVM Pointer to the VM.
1724	* @param pVCpu Pointer to the VMCPU.
1725	* @param pCtx Pointer to the guest-CPU context.
1726	*
1727	* @remarks No-long-jump zone!!!
1728	*/
1729	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1730	{
1731	/*
1732	* Avoid reloading the guest state on longjmp reentrants and do it lazily just before executing the guest.
1733	* This only helps when we get rescheduled more than once to a different host CPU on a longjmp trip before
1734	* finally executing guest code.
1735	*/
1736	return VINF_SUCCESS;
1737	}
1738
1739
1740	/**
1741	* Saves the entire guest state from the VMCB into the
1742	* guest-CPU context. Currently there is no residual state left in the CPU that
1743	* is not updated in the VMCB.
1744	*
1745	* @returns VBox status code.
1746	* @param pVCpu Pointer to the VMCPU.
1747	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1748	* out-of-sync. Make sure to update the required fields
1749	* before using them.
1750	*/
1751	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1752	{
1753	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1754
1755	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1756
1757	pMixedCtx->rip = pVmcb->guest.u64RIP;
1758	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1759	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1760	pMixedCtx->rax = pVmcb->guest.u64RAX;
1761
1762	/*
1763	* Guest interrupt shadow.
1764	*/
1765	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1766	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1767	else
1768	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1769
1770	/*
1771	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1772	*/
1773	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1774
1775	/*
1776	* Guest MSRs.
1777	*/
1778	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1779	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1780	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1781	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1782	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1783	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1784	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1785	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1786
1787	/*
1788	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1789	*/
1790	HMSVM_SAVE_SEG_REG(CS, cs);
1791	HMSVM_SAVE_SEG_REG(SS, ss);
1792	HMSVM_SAVE_SEG_REG(DS, ds);
1793	HMSVM_SAVE_SEG_REG(ES, es);
1794	HMSVM_SAVE_SEG_REG(FS, fs);
1795	HMSVM_SAVE_SEG_REG(GS, gs);
1796
1797	/*
1798	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1799	* register (yet).
1800	*/
1801	/** @todo SELM might need to be fixed as it too should not care about the
1802	* granularity bit. See @bugref{6785}. */
1803	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1804	&& pMixedCtx->cs.Attr.n.u1Present
1805	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1806	{
1807	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1808	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1809	}
1810
1811	#ifdef VBOX_STRICT
1812	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1813	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1814	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1815	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1816	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1817	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1818	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1819
1820	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1821	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1822	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1823	HMSVM_ASSERT_SEG_GRANULARITY(es);
1824	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1825	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1826
1827	# undef HMSVM_ASSERT_SEL_GRANULARITY
1828	#endif
1829
1830	/*
1831	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1832	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1833	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1834	* See AMD spec. 15.5.1 "Basic operation".
1835	*/
1836	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1837	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1838
1839	/*
1840	* Guest Descriptor-Table registers.
1841	*/
1842	HMSVM_SAVE_SEG_REG(TR, tr);
1843	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1844	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1845	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1846
1847	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1848	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1849
1850	/*
1851	* Guest Debug registers.
1852	*/
1853	if (!CPUMIsHyperDebugStateActive(pVCpu))
1854	{
1855	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1856	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1857	}
1858	else
1859	{
1860	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
1861	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
1862	}
1863
1864	/*
1865	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1866	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1867	*/
1868	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1869	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1870	{
1871	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1872	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1873	}
1874	}
1875
1876
1877	/**
1878	* Does the necessary state syncing before returning to ring-3 for any reason
1879	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
1880	*
1881	* @param pVM Pointer to the VM.
1882	* @param pVCpu Pointer to the VMCPU.
1883	* @param pMixedCtx Pointer to the guest-CPU context.
1884	*
1885	* @remarks No-long-jmp zone!!!
1886	*/
1887	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1888	{
1889	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1890	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1891	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1892
1893	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1894	if (CPUMIsGuestFPUStateActive(pVCpu))
1895	{
1896	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1897	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1898	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1899	}
1900
1901	/*
1902	* Restore host debug registers if necessary and resync on next R0 reentry.
1903	*/
1904	#ifdef VBOX_STRICT
1905	if (CPUMIsHyperDebugStateActive(pVCpu))
1906	{
1907	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1908	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1909	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1910	}
1911	#endif
1912	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
1913	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1914
1915	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1916	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1917
1918	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
1919	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
1920	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1921	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1922	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1923
1924	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1925	}
1926
1927
1928	/**
1929	* Leaves the AMD-V session.
1930	*
1931	* @returns VBox status code.
1932	* @param pVM Pointer to the VM.
1933	* @param pVCpu Pointer to the VMCPU.
1934	* @param pCtx Pointer to the guest-CPU context.
1935	*/
1936	DECLINLINE(void) hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1937	{
1938	HM_DISABLE_PREEMPT_IF_NEEDED();
1939	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1940	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1941
1942	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
1943	and done this from the VMXR0ThreadCtxCallback(). */
1944	if (!pVCpu->hm.s.fLeaveDone)
1945	{
1946	hmR0SvmLeave(pVM, pVCpu, pCtx);
1947	pVCpu->hm.s.fLeaveDone = true;
1948	}
1949
1950	/* Deregister hook now that we've left HM context before re-enabling preemption. */
1951	/** @todo This is bad. Deregistering here means we need to VMCLEAR always
1952	* (longjmp/exit-to-r3) in VT-x which is not efficient. */
1953	if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
1954	VMMR0ThreadCtxHooksDeregister(pVCpu);
1955
1956	/* Leave HM context. This takes care of local init (term). */
1957	int rc = HMR0LeaveCpu(pVCpu);
1958	AssertRC(rc); NOREF(rc);
1959
1960	HM_RESTORE_PREEMPT_IF_NEEDED();
1961	}
1962
1963
1964	/**
1965	* Does the necessary state syncing before doing a longjmp to ring-3.
1966	*
1967	* @param pVM Pointer to the VM.
1968	* @param pVCpu Pointer to the VMCPU.
1969	* @param pCtx Pointer to the guest-CPU context.
1970	*
1971	* @remarks No-long-jmp zone!!!
1972	*/
1973	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1974	{
1975	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
1976	}
1977
1978
1979	/**
1980	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
1981	* any remaining host state) before we longjump to ring-3 and possibly get
1982	* preempted.
1983	*
1984	* @param pVCpu Pointer to the VMCPU.
1985	* @param enmOperation The operation causing the ring-3 longjump.
1986	* @param pvUser The user argument (pointer to the possibly
1987	* out-of-date guest-CPU context).
1988	*
1989	* @remarks Must never be called with @a enmOperation ==
1990	* VMMCALLRING3_VM_R0_ASSERTION.
1991	*/
1992	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
1993	{
1994	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
1995	Assert(pVCpu);
1996	Assert(pvUser);
1997	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1998	HMSVM_ASSERT_PREEMPT_SAFE();
1999
2000	VMMRZCallRing3Disable(pVCpu);
2001	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2002
2003	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2004	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2005
2006	VMMRZCallRing3Enable(pVCpu);
2007	}
2008
2009
2010	/**
2011	* Take necessary actions before going back to ring-3.
2012	*
2013	* An action requires us to go back to ring-3. This function does the necessary
2014	* steps before we can safely return to ring-3. This is not the same as longjmps
2015	* to ring-3, this is voluntary.
2016	*
2017	* @param pVM Pointer to the VM.
2018	* @param pVCpu Pointer to the VMCPU.
2019	* @param pCtx Pointer to the guest-CPU context.
2020	* @param rcExit The reason for exiting to ring-3. Can be
2021	* VINF_VMM_UNKNOWN_RING3_CALL.
2022	*/
2023	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2024	{
2025	Assert(pVM);
2026	Assert(pVCpu);
2027	Assert(pCtx);
2028	HMSVM_ASSERT_PREEMPT_SAFE();
2029
2030	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
2031	{
2032	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
2033	return;
2034	}
2035
2036	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2037	VMMRZCallRing3Disable(pVCpu);
2038	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2039
2040	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2041	if (pVCpu->hm.s.Event.fPending)
2042	{
2043	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2044	Assert(!pVCpu->hm.s.Event.fPending);
2045	}
2046
2047	/* Sync. the necessary state for going back to ring-3. */
2048	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2049	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2050
2051	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2052	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2053	\| CPUM_CHANGED_LDTR
2054	\| CPUM_CHANGED_GDTR
2055	\| CPUM_CHANGED_IDTR
2056	\| CPUM_CHANGED_TR
2057	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2058	if ( pVM->hm.s.fNestedPaging
2059	&& CPUMIsGuestPagingEnabledEx(pCtx))
2060	{
2061	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2062	}
2063
2064	/* Make sure we've undo the trap flag if we tried to single step something. */
2065	if (pVCpu->hm.s.fClearTrapFlag)
2066	{
2067	pCtx->eflags.Bits.u1TF = 0;
2068	pVCpu->hm.s.fClearTrapFlag = false;
2069	}
2070
2071	/* On our way back from ring-3 the following needs to be done. */
2072	/** @todo This can change with preemption hooks. */
2073	if (rcExit == VINF_EM_RAW_INTERRUPT)
2074	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
2075	else
2076	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2077
2078	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2079	VMMRZCallRing3Enable(pVCpu);
2080	}
2081
2082
2083	/**
2084	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2085	* intercepts.
2086	*
2087	* @param pVCpu Pointer to the VMCPU.
2088	*
2089	* @remarks No-long-jump zone!!!
2090	*/
2091	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
2092	{
2093	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2094	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
2095	{
2096	uint64_t u64CurTSC = ASMReadTSC();
2097	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
2098	{
2099	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2100	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2101	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2102	}
2103	else
2104	{
2105	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2106	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2107	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
2108	}
2109	}
2110	else
2111	{
2112	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2113	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2114	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2115	}
2116
2117	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2118	}
2119
2120
2121	/**
2122	* Sets an event as a pending event to be injected into the guest.
2123	*
2124	* @param pVCpu Pointer to the VMCPU.
2125	* @param pEvent Pointer to the SVM event.
2126	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2127	* page-fault.
2128	*
2129	* @remarks Statistics counter assumes this is a guest event being reflected to
2130	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2131	*/
2132	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2133	{
2134	Assert(!pVCpu->hm.s.Event.fPending);
2135	Assert(pEvent->n.u1Valid);
2136
2137	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
2138	pVCpu->hm.s.Event.fPending = true;
2139	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2140
2141	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2142	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2143
2144	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2145	}
2146
2147
2148	/**
2149	* Injects an event into the guest upon VMRUN by updating the relevant field
2150	* in the VMCB.
2151	*
2152	* @param pVCpu Pointer to the VMCPU.
2153	* @param pVmcb Pointer to the guest VMCB.
2154	* @param pCtx Pointer to the guest-CPU context.
2155	* @param pEvent Pointer to the event.
2156	*
2157	* @remarks No-long-jump zone!!!
2158	* @remarks Requires CR0!
2159	*/
2160	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2161	{
2162	pVmcb->ctrl.EventInject.u = pEvent->u;
2163	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2164
2165	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2166	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2167	}
2168
2169
2170
2171	/**
2172	* Converts any TRPM trap into a pending HM event. This is typically used when
2173	* entering from ring-3 (not longjmp returns).
2174	*
2175	* @param pVCpu Pointer to the VMCPU.
2176	*/
2177	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2178	{
2179	Assert(TRPMHasTrap(pVCpu));
2180	Assert(!pVCpu->hm.s.Event.fPending);
2181
2182	uint8_t uVector;
2183	TRPMEVENT enmTrpmEvent;
2184	RTGCUINT uErrCode;
2185	RTGCUINTPTR GCPtrFaultAddress;
2186	uint8_t cbInstr;
2187
2188	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2189	AssertRC(rc);
2190
2191	SVMEVENT Event;
2192	Event.u = 0;
2193	Event.n.u1Valid = 1;
2194	Event.n.u8Vector = uVector;
2195
2196	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2197	if (enmTrpmEvent == TRPM_TRAP)
2198	{
2199	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2200	switch (uVector)
2201	{
2202	case X86_XCPT_PF:
2203	case X86_XCPT_DF:
2204	case X86_XCPT_TS:
2205	case X86_XCPT_NP:
2206	case X86_XCPT_SS:
2207	case X86_XCPT_GP:
2208	case X86_XCPT_AC:
2209	{
2210	Event.n.u1ErrorCodeValid = 1;
2211	Event.n.u32ErrorCode = uErrCode;
2212	break;
2213	}
2214	}
2215	}
2216	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2217	{
2218	if (uVector == X86_XCPT_NMI)
2219	Event.n.u3Type = SVM_EVENT_NMI;
2220	else
2221	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2222	}
2223	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2224	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2225	else
2226	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2227
2228	rc = TRPMResetTrap(pVCpu);
2229	AssertRC(rc);
2230
2231	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2232	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2233
2234	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2235	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2236	}
2237
2238
2239	/**
2240	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2241	* AMD-V to execute any instruction.
2242	*
2243	* @param pvCpu Pointer to the VMCPU.
2244	*/
2245	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2246	{
2247	Assert(pVCpu->hm.s.Event.fPending);
2248	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2249
2250	SVMEVENT Event;
2251	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2252
2253	uint8_t uVector = Event.n.u8Vector;
2254	uint8_t uVectorType = Event.n.u3Type;
2255
2256	TRPMEVENT enmTrapType;
2257	switch (uVectorType)
2258	{
2259	case SVM_EVENT_EXTERNAL_IRQ:
2260	case SVM_EVENT_NMI:
2261	enmTrapType = TRPM_HARDWARE_INT;
2262	break;
2263	case SVM_EVENT_SOFTWARE_INT:
2264	enmTrapType = TRPM_SOFTWARE_INT;
2265	break;
2266	case SVM_EVENT_EXCEPTION:
2267	enmTrapType = TRPM_TRAP;
2268	break;
2269	default:
2270	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2271	enmTrapType = TRPM_32BIT_HACK;
2272	break;
2273	}
2274
2275	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2276
2277	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2278	AssertRC(rc);
2279
2280	if (Event.n.u1ErrorCodeValid)
2281	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2282
2283	if ( uVectorType == SVM_EVENT_EXCEPTION
2284	&& uVector == X86_XCPT_PF)
2285	{
2286	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2287	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2288	}
2289	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2290	{
2291	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2292	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2293	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2294	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2295	}
2296	pVCpu->hm.s.Event.fPending = false;
2297	}
2298
2299
2300	/**
2301	* Gets the guest's interrupt-shadow.
2302	*
2303	* @returns The guest's interrupt-shadow.
2304	* @param pVCpu Pointer to the VMCPU.
2305	* @param pCtx Pointer to the guest-CPU context.
2306	*
2307	* @remarks No-long-jump zone!!!
2308	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2309	*/
2310	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2311	{
2312	/*
2313	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2314	* inhibit interrupts or clear any existing interrupt-inhibition.
2315	*/
2316	uint32_t uIntrState = 0;
2317	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2318	{
2319	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2320	{
2321	/*
2322	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2323	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2324	*/
2325	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2326	}
2327	else
2328	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2329	}
2330	return uIntrState;
2331	}
2332
2333
2334	/**
2335	* Sets the virtual interrupt intercept control in the VMCB which
2336	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2337	* receive interrupts.
2338	*
2339	* @param pVmcb Pointer to the VMCB.
2340	*/
2341	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2342	{
2343	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2344	{
2345	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2346	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2347	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2348	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2349
2350	Log4(("Setting VINTR intercept\n"));
2351	}
2352	}
2353
2354
2355	/**
2356	* Evaluates the event to be delivered to the guest and sets it as the pending
2357	* event.
2358	*
2359	* @param pVCpu Pointer to the VMCPU.
2360	* @param pCtx Pointer to the guest-CPU context.
2361	*/
2362	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2363	{
2364	Assert(!pVCpu->hm.s.Event.fPending);
2365	Log4Func(("\n"));
2366
2367	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2368	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2369	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2370
2371	SVMEVENT Event;
2372	Event.u = 0;
2373	/** @todo SMI. SMIs take priority over NMIs. */
2374	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2375	{
2376	if (!fIntShadow)
2377	{
2378	Log4(("Pending NMI\n"));
2379
2380	Event.n.u1Valid = 1;
2381	Event.n.u8Vector = X86_XCPT_NMI;
2382	Event.n.u3Type = SVM_EVENT_NMI;
2383
2384	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2385	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2386	}
2387	else
2388	hmR0SvmSetVirtIntrIntercept(pVmcb);
2389	}
2390	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2391	{
2392	/*
2393	* Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
2394	* the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
2395	* evaluated here and not set as pending, solely based on the force-flags.
2396	*/
2397	if ( !fBlockInt
2398	&& !fIntShadow)
2399	{
2400	uint8_t u8Interrupt;
2401	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2402	if (RT_SUCCESS(rc))
2403	{
2404	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2405
2406	Event.n.u1Valid = 1;
2407	Event.n.u8Vector = u8Interrupt;
2408	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2409
2410	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2411	}
2412	else
2413	{
2414	/** @todo Does this actually happen? If not turn it into an assertion. */
2415	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2416	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2417	}
2418	}
2419	else
2420	hmR0SvmSetVirtIntrIntercept(pVmcb);
2421	}
2422	}
2423
2424
2425	/**
2426	* Injects any pending events into the guest if the guest is in a state to
2427	* receive them.
2428	*
2429	* @param pVCpu Pointer to the VMCPU.
2430	* @param pCtx Pointer to the guest-CPU context.
2431	*/
2432	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2433	{
2434	Assert(!TRPMHasTrap(pVCpu));
2435	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2436	Log4Func(("\n"));
2437
2438	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2439	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2440	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2441
2442	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2443	{
2444	SVMEVENT Event;
2445	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2446	Assert(Event.n.u1Valid);
2447	#ifdef VBOX_STRICT
2448	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2449	{
2450	Assert(!fBlockInt);
2451	Assert(!fIntShadow);
2452	}
2453	else if (Event.n.u3Type == SVM_EVENT_NMI)
2454	Assert(!fIntShadow);
2455	#endif
2456
2457	Log4(("Injecting pending HM event.\n"));
2458	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2459	pVCpu->hm.s.Event.fPending = false;
2460
2461	#ifdef VBOX_WITH_STATISTICS
2462	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2463	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2464	else
2465	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2466	#endif
2467	}
2468
2469	/* Update the guest interrupt shadow in the VMCB. */
2470	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2471	}
2472
2473
2474	/**
2475	* Reports world-switch error and dumps some useful debug info.
2476	*
2477	* @param pVM Pointer to the VM.
2478	* @param pVCpu Pointer to the VMCPU.
2479	* @param rcVMRun The return code from VMRUN (or
2480	* VERR_SVM_INVALID_GUEST_STATE for invalid
2481	* guest-state).
2482	* @param pCtx Pointer to the guest-CPU context.
2483	*/
2484	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2485	{
2486	HMSVM_ASSERT_PREEMPT_SAFE();
2487	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2488
2489	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2490	{
2491	HMDumpRegs(pVM, pVCpu, pCtx);
2492	#ifdef VBOX_STRICT
2493	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2494	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2495	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2496	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2497	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2498	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2499	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2500	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2501	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2502	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2503	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2504
2505	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2506	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2507	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2508
2509	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2510	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2511	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2512	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2513	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2514	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2515	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2516	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2517	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2518	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2519
2520	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2521	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2522	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2523	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2524	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2525	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2526	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2527	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2528	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2529	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2530	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2531	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2532	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2533	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2534	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2535	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2536	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2537
2538	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2539	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2540
2541	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2542	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2543	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2544	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2545	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2546	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2547	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2548	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2549	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2550	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2551	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2552	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2553	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2554	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2555	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2556	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2557	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2558	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2559	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2560	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2561
2562	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2563	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2564
2565	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2566	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2567	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2568	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2569
2570	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2571	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2572
2573	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2574	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2575	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2576	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2577
2578	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2579	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2580	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2581	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2582	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2583	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2584	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2585
2586	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2587	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2588	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2589	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2590
2591	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2592	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2593	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2594
2595	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2596	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2597	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2598	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2599	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2600	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2601	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2602	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2603	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2604	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2605	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2606	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2607	#endif
2608	}
2609	else
2610	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2611	}
2612
2613
2614	/**
2615	* Check per-VM and per-VCPU force flag actions that require us to go back to
2616	* ring-3 for one reason or another.
2617	*
2618	* @returns VBox status code (information status code included).
2619	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2620	* ring-3.
2621	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2622	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2623	* interrupts)
2624	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2625	* all EMTs to be in ring-3.
2626	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2627	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2628	* to the EM loop.
2629	*
2630	* @param pVM Pointer to the VM.
2631	* @param pVCpu Pointer to the VMCPU.
2632	* @param pCtx Pointer to the guest-CPU context.
2633	*/
2634	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2635	{
2636	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2637
2638	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2639	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2640	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2641
2642	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2643	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2644	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2645	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2646	{
2647	/* Pending PGM C3 sync. */
2648	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2649	{
2650	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2651	if (rc != VINF_SUCCESS)
2652	{
2653	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2654	return rc;
2655	}
2656	}
2657
2658	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2659	/* -XXX- what was that about single stepping? */
2660	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2661	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2662	{
2663	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2664	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2665	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2666	return rc;
2667	}
2668
2669	/* Pending VM request packets, such as hardware interrupts. */
2670	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2671	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2672	{
2673	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2674	return VINF_EM_PENDING_REQUEST;
2675	}
2676
2677	/* Pending PGM pool flushes. */
2678	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2679	{
2680	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2681	return VINF_PGM_POOL_FLUSH_PENDING;
2682	}
2683
2684	/* Pending DMA requests. */
2685	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2686	{
2687	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2688	return VINF_EM_RAW_TO_R3;
2689	}
2690	}
2691
2692	return VINF_SUCCESS;
2693	}
2694
2695
2696	/**
2697	* Does the preparations before executing guest code in AMD-V.
2698	*
2699	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2700	* recompiler. We must be cautious what we do here regarding committing
2701	* guest-state information into the the VMCB assuming we assuredly execute the
2702	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2703	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2704	* that the recompiler can (and should) use them when it resumes guest
2705	* execution. Otherwise such operations must be done when we can no longer
2706	* exit to ring-3.
2707	*
2708	* @returns VBox status code (informational status codes included).
2709	* @retval VINF_SUCCESS if we can proceed with running the guest.
2710	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2711	*
2712	* @param pVM Pointer to the VM.
2713	* @param pVCpu Pointer to the VMCPU.
2714	* @param pCtx Pointer to the guest-CPU context.
2715	* @param pSvmTransient Pointer to the SVM transient structure.
2716	*/
2717	DECLINLINE(int) hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2718	{
2719	/* Check force flag actions that might require us to go back to ring-3. */
2720	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2721	if (rc != VINF_SUCCESS)
2722	return rc;
2723
2724	if (TRPMHasTrap(pVCpu))
2725	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2726	else if (!pVCpu->hm.s.Event.fPending)
2727	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2728
2729	/*
2730	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
2731	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
2732	*
2733	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
2734	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
2735	*
2736	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
2737	* executing guest code.
2738	*/
2739	pSvmTransient->uEflags = ASMIntDisableFlags();
2740	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2741	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2742	{
2743	ASMSetFlags(pSvmTransient->uEflags);
2744	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2745	return VINF_EM_RAW_TO_R3;
2746	}
2747	else if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2748	{
2749	ASMSetFlags(pSvmTransient->uEflags);
2750	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2751	return VINF_EM_RAW_INTERRUPT;
2752	}
2753
2754	/* Indicate the start of guest execution. No more longjmps or returns to ring-3 from this point!!! */
2755	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2756	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2757
2758	return VINF_SUCCESS;
2759	}
2760
2761
2762	/**
2763	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2764	* means there is no backing out to ring-3 or anywhere else at this
2765	* point.
2766	*
2767	* @param pVM Pointer to the VM.
2768	* @param pVCpu Pointer to the VMCPU.
2769	* @param pCtx Pointer to the guest-CPU context.
2770	* @param pSvmTransient Pointer to the SVM transient structure.
2771	*
2772	* @remarks Called with preemption disabled.
2773	* @remarks No-long-jump zone!!!
2774	*/
2775	DECLINLINE(void) hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2776	{
2777	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2778	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2779
2780	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2781
2782	/*
2783	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2784	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2785	*/
2786	/** @todo The above assumption could be wrong. It's not documented what
2787	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2788	* hard way. */
2789	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2790	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2791
2792	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2793	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2794	#endif
2795
2796	/* Load the guest state. */
2797	int rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2798	AssertRC(rc);
2799	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
2800	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags =%#x\n", pVCpu->hm.s.fContextUseFlags));
2801	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2802
2803	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2804	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2805	pVmcb->ctrl.u64VmcbCleanBits = 0;
2806
2807	/*
2808	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2809	* so we can update it on the way back if the guest changed the TPR.
2810	*/
2811	if (pVCpu->hm.s.svm.fSyncVTpr)
2812	{
2813	if (pVM->hm.s.fTPRPatchingActive)
2814	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2815	else
2816	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2817	}
2818
2819	/* Setup TSC offsetting. */
2820	if ( pSvmTransient->fUpdateTscOffsetting
2821	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2822	{
2823	hmR0SvmUpdateTscOffsetting(pVCpu);
2824	pSvmTransient->fUpdateTscOffsetting = false;
2825	}
2826
2827	/* Flush the appropriate tagged-TLB entries. */
2828	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2829	hmR0SvmFlushTaggedTlb(pVCpu);
2830	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2831
2832	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2833
2834	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2835	to start executing. */
2836
2837	/*
2838	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2839	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2840	*
2841	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2842	*/
2843	pSvmTransient->fRestoreTscAuxMsr = false;
2844	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2845	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2846	{
2847	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2848	uint64_t u64GuestTscAux = 0;
2849	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2850	AssertRC(rc2);
2851	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2852	{
2853	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2854	pSvmTransient->fRestoreTscAuxMsr = true;
2855	}
2856	}
2857	}
2858
2859
2860	/**
2861	* Wrapper for running the guest code in AMD-V.
2862	*
2863	* @returns VBox strict status code.
2864	* @param pVM Pointer to the VM.
2865	* @param pVCpu Pointer to the VMCPU.
2866	* @param pCtx Pointer to the guest-CPU context.
2867	*
2868	* @remarks No-long-jump zone!!!
2869	*/
2870	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2871	{
2872	/*
2873	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2874	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2875	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2876	*/
2877	#ifdef VBOX_WITH_KERNEL_USING_XMM
2878	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2879	pVCpu->hm.s.svm.pfnVMRun);
2880	#else
2881	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2882	#endif
2883	}
2884
2885
2886	/**
2887	* Performs some essential restoration of state after running guest code in
2888	* AMD-V.
2889	*
2890	* @param pVM Pointer to the VM.
2891	* @param pVCpu Pointer to the VMCPU.
2892	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2893	* out-of-sync. Make sure to update the required fields
2894	* before using them.
2895	* @param pSvmTransient Pointer to the SVM transient structure.
2896	* @param rcVMRun Return code of VMRUN.
2897	*
2898	* @remarks Called with interrupts disabled.
2899	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2900	* unconditionally when it is safe to do so.
2901	*/
2902	DECLINLINE(void) hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2903	{
2904	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2905
2906	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2907	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2908
2909	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2910	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2911
2912	if (pSvmTransient->fRestoreTscAuxMsr)
2913	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2914
2915	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2916	{
2917	/** @todo Find a way to fix hardcoding a guestimate. */
2918	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
2919	}
2920
2921	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
2922	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2923	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2924
2925	Assert(!(ASMGetFlags() & X86_EFL_IF));
2926	ASMSetFlags(pSvmTransient->uEflags); /* Enable interrupts. */
2927
2928	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2929
2930	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2931	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2932	{
2933	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2934	return;
2935	}
2936
2937	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2938	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2939	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2940
2941	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2942	{
2943	if (pVCpu->hm.s.svm.fSyncVTpr)
2944	{
2945	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2946	if ( pVM->hm.s.fTPRPatchingActive
2947	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2948	{
2949	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
2950	AssertRC(rc);
2951	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2952	}
2953	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2954	{
2955	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
2956	AssertRC(rc);
2957	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2958	}
2959	}
2960	}
2961	}
2962
2963
2964	/**
2965	* Runs the guest code using AMD-V.
2966	*
2967	* @returns VBox status code.
2968	* @param pVM Pointer to the VM.
2969	* @param pVCpu Pointer to the VMCPU.
2970	* @param pCtx Pointer to the guest-CPU context.
2971	*/
2972	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2973	{
2974	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2975	HMSVM_ASSERT_PREEMPT_SAFE();
2976	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
2977
2978	SVMTRANSIENT SvmTransient;
2979	SvmTransient.fUpdateTscOffsetting = true;
2980	uint32_t cLoops = 0;
2981	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2982	int rc = VERR_INTERNAL_ERROR_5;
2983
2984	for (;; cLoops++)
2985	{
2986	Assert(!HMR0SuspendPending());
2987	HMSVM_ASSERT_CPU_SAFE();
2988
2989	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
2990	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
2991	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
2992	if (rc != VINF_SUCCESS)
2993	break;
2994
2995	/*
2996	* No longjmps to ring-3 from this point on!!!
2997	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2998	* This also disables flushing of the R0-logger instance (if any).
2999	*/
3000	VMMRZCallRing3Disable(pVCpu);
3001	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3002
3003	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3004
3005	/*
3006	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3007	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3008	*/
3009	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3010	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3011	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3012	{
3013	if (rc == VINF_SUCCESS)
3014	rc = VERR_SVM_INVALID_GUEST_STATE;
3015	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3016	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3017	break;
3018	}
3019
3020	/* Handle the #VMEXIT. */
3021	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3022	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3023	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3024	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3025	if (rc != VINF_SUCCESS)
3026	break;
3027	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
3028	{
3029	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3030	rc = VINF_EM_RAW_INTERRUPT;
3031	break;
3032	}
3033	}
3034
3035	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3036	if (rc == VERR_EM_INTERPRETER)
3037	rc = VINF_EM_RAW_EMULATE_INSTR;
3038	else if (rc == VINF_EM_RESET)
3039	rc = VINF_EM_TRIPLE_FAULT;
3040
3041	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3042	VMMRZCallRing3RemoveNotification(pVCpu);
3043	return rc;
3044	}
3045
3046
3047	/**
3048	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3049	*
3050	* @returns VBox status code (informational status codes included).
3051	* @param pVCpu Pointer to the VMCPU.
3052	* @param pCtx Pointer to the guest-CPU context.
3053	* @param pSvmTransient Pointer to the SVM transient structure.
3054	*/
3055	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3056	{
3057	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3058	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3059
3060	/*
3061	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
3062	* normal workloads (for some definition of "normal").
3063	*/
3064	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3065	switch (pSvmTransient->u64ExitCode)
3066	{
3067	case SVM_EXIT_NPF:
3068	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3069
3070	case SVM_EXIT_IOIO:
3071	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3072
3073	case SVM_EXIT_RDTSC:
3074	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3075
3076	case SVM_EXIT_RDTSCP:
3077	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3078
3079	case SVM_EXIT_CPUID:
3080	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3081
3082	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3083	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3084
3085	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3086	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3087
3088	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3089	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3090
3091	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3092	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3093
3094	case SVM_EXIT_MONITOR:
3095	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3096
3097	case SVM_EXIT_MWAIT:
3098	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3099
3100	case SVM_EXIT_HLT:
3101	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3102
3103	case SVM_EXIT_READ_CR0:
3104	case SVM_EXIT_READ_CR3:
3105	case SVM_EXIT_READ_CR4:
3106	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3107
3108	case SVM_EXIT_WRITE_CR0:
3109	case SVM_EXIT_WRITE_CR3:
3110	case SVM_EXIT_WRITE_CR4:
3111	case SVM_EXIT_WRITE_CR8:
3112	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3113
3114	case SVM_EXIT_VINTR:
3115	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3116
3117	case SVM_EXIT_INTR:
3118	case SVM_EXIT_FERR_FREEZE:
3119	case SVM_EXIT_NMI:
3120	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3121
3122	case SVM_EXIT_MSR:
3123	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3124
3125	case SVM_EXIT_INVLPG:
3126	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3127
3128	case SVM_EXIT_WBINVD:
3129	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3130
3131	case SVM_EXIT_INVD:
3132	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3133
3134	case SVM_EXIT_RDPMC:
3135	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3136
3137	default:
3138	{
3139	switch (pSvmTransient->u64ExitCode)
3140	{
3141	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3142	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3143	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3144	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3145	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3146
3147	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3148	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3149	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3150	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3151	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3152
3153	case SVM_EXIT_TASK_SWITCH:
3154	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3155
3156	case SVM_EXIT_VMMCALL:
3157	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3158
3159	case SVM_EXIT_SHUTDOWN:
3160	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3161
3162	case SVM_EXIT_SMI:
3163	case SVM_EXIT_INIT:
3164	{
3165	/*
3166	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3167	* we want to know about it so log the exit code and bail.
3168	*/
3169	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3170	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3171	return VERR_SVM_UNEXPECTED_EXIT;
3172	}
3173
3174	case SVM_EXIT_INVLPGA:
3175	case SVM_EXIT_RSM:
3176	case SVM_EXIT_VMRUN:
3177	case SVM_EXIT_VMLOAD:
3178	case SVM_EXIT_VMSAVE:
3179	case SVM_EXIT_STGI:
3180	case SVM_EXIT_CLGI:
3181	case SVM_EXIT_SKINIT:
3182	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3183
3184	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3185	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3186	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3187	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3188	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3189	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3190	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3191	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3192	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3193	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3194	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3195	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3196	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3197	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3198	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3199	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3200	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3201	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3202	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3203	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3204
3205	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3206	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3207	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3208	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3209	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3210	{
3211	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3212	SVMEVENT Event;
3213	Event.u = 0;
3214	Event.n.u1Valid = 1;
3215	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3216	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3217
3218	switch (Event.n.u8Vector)
3219	{
3220	case X86_XCPT_DE:
3221	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3222	break;
3223
3224	case X86_XCPT_BP:
3225	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3226	* next instruction. */
3227	/** @todo Investigate this later. */
3228	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3229	break;
3230
3231	case X86_XCPT_UD:
3232	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3233	break;
3234
3235	case X86_XCPT_NP:
3236	Event.n.u1ErrorCodeValid = 1;
3237	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3238	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3239	break;
3240
3241	case X86_XCPT_SS:
3242	Event.n.u1ErrorCodeValid = 1;
3243	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3244	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3245	break;
3246
3247	case X86_XCPT_GP:
3248	Event.n.u1ErrorCodeValid = 1;
3249	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3250	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3251	break;
3252
3253	default:
3254	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3255	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3256	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3257	}
3258
3259	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3260	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3261	return VINF_SUCCESS;
3262	}
3263	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3264
3265	default:
3266	{
3267	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3268	pVCpu->hm.s.u32HMError = u32ExitCode;
3269	return VERR_SVM_UNKNOWN_EXIT;
3270	}
3271	}
3272	}
3273	}
3274	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3275	}
3276
3277
3278	#ifdef DEBUG
3279	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3280	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3281	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3282
3283	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3284	do \
3285	{ \
3286	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3287	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3288	} while (0)
3289
3290	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3291	do { \
3292	AssertPtr(pVCpu); \
3293	AssertPtr(pCtx); \
3294	AssertPtr(pSvmTransient); \
3295	Assert(ASMIntAreEnabled()); \
3296	HMSVM_ASSERT_PREEMPT_SAFE(); \
3297	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3298	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3299	HMSVM_ASSERT_PREEMPT_SAFE(); \
3300	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3301	HMSVM_ASSERT_PREEMPT_CPUID(); \
3302	} while (0)
3303	#else /* Release builds */
3304	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3305	#endif
3306
3307
3308	/**
3309	* Worker for hmR0SvmInterpretInvlpg().
3310	*
3311	* @return VBox status code.
3312	* @param pVCpu Pointer to the VMCPU.
3313	* @param pCpu Pointer to the disassembler state.
3314	* @param pRegFrame Pointer to the register frame.
3315	*/
3316	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3317	{
3318	DISQPVPARAMVAL Param1;
3319	RTGCPTR GCPtrPage;
3320
3321	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3322	if (RT_FAILURE(rc))
3323	return VERR_EM_INTERPRETER;
3324
3325	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3326	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3327	{
3328	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3329	return VERR_EM_INTERPRETER;
3330
3331	GCPtrPage = Param1.val.val64;
3332	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3333	rc = VBOXSTRICTRC_VAL(rc2);
3334	}
3335	else
3336	{
3337	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3338	rc = VERR_EM_INTERPRETER;
3339	}
3340
3341	return rc;
3342	}
3343
3344
3345	/**
3346	* Interprets INVLPG.
3347	*
3348	* @returns VBox status code.
3349	* @retval VINF_* Scheduling instructions.
3350	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3351	* @retval VERR_* Fatal errors.
3352	*
3353	* @param pVM Pointer to the VM.
3354	* @param pRegFrame Pointer to the register frame.
3355	*
3356	* @remarks Updates the RIP if the instruction was executed successfully.
3357	*/
3358	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3359	{
3360	/* Only allow 32 & 64 bit code. */
3361	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3362	{
3363	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3364	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3365	if ( RT_SUCCESS(rc)
3366	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3367	{
3368	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3369	if (RT_SUCCESS(rc))
3370	pRegFrame->rip += pDis->cbInstr;
3371	return rc;
3372	}
3373	else
3374	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3375	}
3376	return VERR_EM_INTERPRETER;
3377	}
3378
3379
3380	/**
3381	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3382	*
3383	* @param pVCpu Pointer to the VMCPU.
3384	*/
3385	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3386	{
3387	SVMEVENT Event;
3388	Event.u = 0;
3389	Event.n.u1Valid = 1;
3390	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3391	Event.n.u8Vector = X86_XCPT_UD;
3392	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3393	}
3394
3395
3396	/**
3397	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3398	*
3399	* @param pVCpu Pointer to the VMCPU.
3400	*/
3401	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3402	{
3403	SVMEVENT Event;
3404	Event.u = 0;
3405	Event.n.u1Valid = 1;
3406	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3407	Event.n.u8Vector = X86_XCPT_DB;
3408	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3409	}
3410
3411
3412	/**
3413	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3414	*
3415	* @param pVCpu Pointer to the VMCPU.
3416	* @param pCtx Pointer to the guest-CPU context.
3417	* @param u32ErrCode The error-code for the page-fault.
3418	* @param uFaultAddress The page fault address (CR2).
3419	*
3420	* @remarks This updates the guest CR2 with @a uFaultAddress!
3421	*/
3422	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3423	{
3424	SVMEVENT Event;
3425	Event.u = 0;
3426	Event.n.u1Valid = 1;
3427	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3428	Event.n.u8Vector = X86_XCPT_PF;
3429	Event.n.u1ErrorCodeValid = 1;
3430	Event.n.u32ErrorCode = u32ErrCode;
3431
3432	/* Update CR2 of the guest. */
3433	if (pCtx->cr2 != uFaultAddress)
3434	{
3435	pCtx->cr2 = uFaultAddress;
3436	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR2;
3437	}
3438
3439	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3440	}
3441
3442
3443	/**
3444	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3445	* VM.
3446	*
3447	* @param pVCpu Pointer to the VMCPU.
3448	*/
3449	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3450	{
3451	SVMEVENT Event;
3452	Event.u = 0;
3453	Event.n.u1Valid = 1;
3454	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3455	Event.n.u8Vector = X86_XCPT_NM;
3456	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3457	}
3458
3459
3460	/**
3461	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3462	*
3463	* @param pVCpu Pointer to the VMCPU.
3464	*/
3465	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3466	{
3467	SVMEVENT Event;
3468	Event.u = 0;
3469	Event.n.u1Valid = 1;
3470	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3471	Event.n.u8Vector = X86_XCPT_MF;
3472	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3473	}
3474
3475
3476	/**
3477	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3478	*
3479	* @param pVCpu Pointer to the VMCPU.
3480	*/
3481	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3482	{
3483	SVMEVENT Event;
3484	Event.u = 0;
3485	Event.n.u1Valid = 1;
3486	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3487	Event.n.u8Vector = X86_XCPT_DF;
3488	Event.n.u1ErrorCodeValid = 1;
3489	Event.n.u32ErrorCode = 0;
3490	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3491	}
3492
3493
3494	/**
3495	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3496	* guests. This simply looks up the patch record at EIP and does the required.
3497	*
3498	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3499	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3500	* TPR). See hmR3ReplaceTprInstr() for the details.
3501	*
3502	* @returns VBox status code.
3503	* @param pVM Pointer to the VM.
3504	* @param pVCpu Pointer to the VMCPU.
3505	* @param pCtx Pointer to the guest-CPU context.
3506	*/
3507	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3508	{
3509	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3510	for (;;)
3511	{
3512	bool fPending;
3513	uint8_t u8Tpr;
3514
3515	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3516	if (!pPatch)
3517	break;
3518
3519	switch (pPatch->enmType)
3520	{
3521	case HMTPRINSTR_READ:
3522	{
3523	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3524	AssertRC(rc);
3525
3526	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3527	AssertRC(rc);
3528	pCtx->rip += pPatch->cbOp;
3529	break;
3530	}
3531
3532	case HMTPRINSTR_WRITE_REG:
3533	case HMTPRINSTR_WRITE_IMM:
3534	{
3535	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3536	{
3537	uint32_t u32Val;
3538	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3539	AssertRC(rc);
3540	u8Tpr = u32Val;
3541	}
3542	else
3543	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3544
3545	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3546	AssertRC(rc2);
3547	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3548
3549	pCtx->rip += pPatch->cbOp;
3550	break;
3551	}
3552
3553	default:
3554	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3555	pVCpu->hm.s.u32HMError = pPatch->enmType;
3556	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3557	}
3558	}
3559
3560	return VINF_SUCCESS;
3561	}
3562
3563	/**
3564	* Determines if an exception is a contributory exception. Contributory
3565	* exceptions are ones which can cause double-faults. Page-fault is
3566	* intentionally not included here as it's a conditional contributory exception.
3567	*
3568	* @returns true if the exception is contributory, false otherwise.
3569	* @param uVector The exception vector.
3570	*/
3571	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3572	{
3573	switch (uVector)
3574	{
3575	case X86_XCPT_GP:
3576	case X86_XCPT_SS:
3577	case X86_XCPT_NP:
3578	case X86_XCPT_TS:
3579	case X86_XCPT_DE:
3580	return true;
3581	default:
3582	break;
3583	}
3584	return false;
3585	}
3586
3587
3588	/**
3589	* Handle a condition that occurred while delivering an event through the guest
3590	* IDT.
3591	*
3592	* @returns VBox status code (informational error codes included).
3593	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3594	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3595	* continue execution of the guest which will delivery the #DF.
3596	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3597	*
3598	* @param pVCpu Pointer to the VMCPU.
3599	* @param pCtx Pointer to the guest-CPU context.
3600	* @param pSvmTransient Pointer to the SVM transient structure.
3601	*
3602	* @remarks No-long-jump zone!!!
3603	*/
3604	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3605	{
3606	int rc = VINF_SUCCESS;
3607	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3608
3609	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3610	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3611	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3612	{
3613	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3614
3615	typedef enum
3616	{
3617	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3618	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3619	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3620	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3621	} SVMREFLECTXCPT;
3622
3623	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3624	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3625	{
3626	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3627	{
3628	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3629
3630	#ifdef VBOX_STRICT
3631	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3632	&& uExitVector == X86_XCPT_PF)
3633	{
3634	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3635	}
3636	#endif
3637	if ( uExitVector == X86_XCPT_PF
3638	&& uIdtVector == X86_XCPT_PF)
3639	{
3640	pSvmTransient->fVectoringPF = true;
3641	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3642	}
3643	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3644	&& hmR0SvmIsContributoryXcpt(uExitVector)
3645	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3646	\|\| uIdtVector == X86_XCPT_PF))
3647	{
3648	enmReflect = SVMREFLECTXCPT_DF;
3649	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3650	uIdtVector, uExitVector));
3651	}
3652	else if (uIdtVector == X86_XCPT_DF)
3653	{
3654	enmReflect = SVMREFLECTXCPT_TF;
3655	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3656	uIdtVector, uExitVector));
3657	}
3658	else
3659	enmReflect = SVMREFLECTXCPT_XCPT;
3660	}
3661	else
3662	{
3663	/*
3664	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3665	* exception to the guest after handling the VM-exit.
3666	*/
3667	enmReflect = SVMREFLECTXCPT_XCPT;
3668	}
3669	}
3670	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3671	{
3672	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3673	enmReflect = SVMREFLECTXCPT_XCPT;
3674	}
3675
3676	switch (enmReflect)
3677	{
3678	case SVMREFLECTXCPT_XCPT:
3679	{
3680	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3681	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3682
3683	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3684	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3685	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3686	break;
3687	}
3688
3689	case SVMREFLECTXCPT_DF:
3690	{
3691	hmR0SvmSetPendingXcptDF(pVCpu);
3692	rc = VINF_HM_DOUBLE_FAULT;
3693	break;
3694	}
3695
3696	case SVMREFLECTXCPT_TF:
3697	{
3698	rc = VINF_EM_RESET;
3699	break;
3700	}
3701
3702	default:
3703	Assert(rc == VINF_SUCCESS);
3704	break;
3705	}
3706	}
3707	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3708	return rc;
3709	}
3710
3711
3712	/**
3713	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
3714	* CPU, otherwise advances the RIP by @a cb bytes.
3715	*
3716	* @param pVCpu Pointer to the VMCPU.
3717	* @param pCtx Pointer to the guest-CPU context.
3718	* @param cb RIP increment value in bytes.
3719	*
3720	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
3721	* when NRIP_SAVE is supported by the CPU!
3722	*/
3723	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
3724	{
3725	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3726	{
3727	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3728	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3729	}
3730	else
3731	pCtx->rip += cb;
3732	}
3733
3734
3735	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3736	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3737	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3738
3739	/** @name VM-exit handlers.
3740	* @{
3741	*/
3742
3743	/**
3744	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3745	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3746	*/
3747	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3748	{
3749	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3750
3751	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
3752	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmi);
3753	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
3754	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3755
3756	/*
3757	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3758	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3759	* interrupt it is until the host actually take the interrupt.
3760	*
3761	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3762	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3763	*/
3764	return VINF_EM_RAW_INTERRUPT;
3765	}
3766
3767
3768	/**
3769	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3770	*/
3771	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3772	{
3773	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3774
3775	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3776	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3777	int rc = VINF_SUCCESS;
3778	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3779	return rc;
3780	}
3781
3782
3783	/**
3784	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3785	*/
3786	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3787	{
3788	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3789
3790	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3791	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3792	int rc = VINF_SUCCESS;
3793	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3794	return rc;
3795	}
3796
3797
3798	/**
3799	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3800	*/
3801	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3802	{
3803	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3804	PVM pVM = pVCpu->CTX_SUFF(pVM);
3805	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3806	if (RT_LIKELY(rc == VINF_SUCCESS))
3807	{
3808	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3809	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3810	}
3811	else
3812	{
3813	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3814	rc = VERR_EM_INTERPRETER;
3815	}
3816	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3817	return rc;
3818	}
3819
3820
3821	/**
3822	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3823	*/
3824	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3825	{
3826	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3827	PVM pVM = pVCpu->CTX_SUFF(pVM);
3828	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3829	if (RT_LIKELY(rc == VINF_SUCCESS))
3830	{
3831	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3832	pSvmTransient->fUpdateTscOffsetting = true;
3833
3834	/* Single step check. */
3835	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3836	}
3837	else
3838	{
3839	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3840	rc = VERR_EM_INTERPRETER;
3841	}
3842	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3843	return rc;
3844	}
3845
3846
3847	/**
3848	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3849	*/
3850	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3851	{
3852	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3853	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3854	if (RT_LIKELY(rc == VINF_SUCCESS))
3855	{
3856	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3857	pSvmTransient->fUpdateTscOffsetting = true;
3858	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3859	}
3860	else
3861	{
3862	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3863	rc = VERR_EM_INTERPRETER;
3864	}
3865	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3866	return rc;
3867	}
3868
3869
3870	/**
3871	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3872	*/
3873	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3874	{
3875	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3876	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3877	if (RT_LIKELY(rc == VINF_SUCCESS))
3878	{
3879	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3880	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3881	}
3882	else
3883	{
3884	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3885	rc = VERR_EM_INTERPRETER;
3886	}
3887	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3888	return rc;
3889	}
3890
3891
3892	/**
3893	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3894	*/
3895	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3896	{
3897	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3898	PVM pVM = pVCpu->CTX_SUFF(pVM);
3899	Assert(!pVM->hm.s.fNestedPaging);
3900
3901	/** @todo Decode Assist. */
3902	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3903	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3904	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3905	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3906	return rc;
3907	}
3908
3909
3910	/**
3911	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3912	*/
3913	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3914	{
3915	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3916	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
3917	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3918	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3919	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3920	return rc;
3921	}
3922
3923
3924	/**
3925	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3926	*/
3927	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3928	{
3929	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3930	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3931	if (RT_LIKELY(rc == VINF_SUCCESS))
3932	{
3933	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3934	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3935	}
3936	else
3937	{
3938	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3939	rc = VERR_EM_INTERPRETER;
3940	}
3941	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3942	return rc;
3943	}
3944
3945
3946	/**
3947	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3948	*/
3949	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3950	{
3951	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3952	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3953	int rc = VBOXSTRICTRC_VAL(rc2);
3954	if ( rc == VINF_EM_HALT
3955	\|\| rc == VINF_SUCCESS)
3956	{
3957	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3958
3959	if ( rc == VINF_EM_HALT
3960	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3961	{
3962	rc = VINF_SUCCESS;
3963	}
3964	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3965	}
3966	else
3967	{
3968	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3969	rc = VERR_EM_INTERPRETER;
3970	}
3971	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3972	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3973	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3974	return rc;
3975	}
3976
3977
3978	/**
3979	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
3980	* Conditional #VMEXIT.
3981	*/
3982	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3983	{
3984	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3985	return VINF_EM_RESET;
3986	}
3987
3988
3989	/**
3990	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
3991	*/
3992	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3993	{
3994	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3995
3996	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
3997
3998	/** @todo Decode Assist. */
3999	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4000	int rc = VBOXSTRICTRC_VAL(rc2);
4001	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4002	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4003	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4004	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4005	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4006	return rc;
4007	}
4008
4009
4010	/**
4011	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
4012	*/
4013	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4014	{
4015	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4016	/** @todo Decode Assist. */
4017	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4018	int rc = VBOXSTRICTRC_VAL(rc2);
4019	if (rc == VINF_SUCCESS)
4020	{
4021	/* RIP has been updated by EMInterpretInstruction(). */
4022	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4023	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4024	{
4025	case 0: /* CR0. */
4026	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4027	break;
4028
4029	case 3: /* CR3. */
4030	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4031	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
4032	break;
4033
4034	case 4: /* CR4. */
4035	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
4036	break;
4037
4038	case 8: /* CR8 (TPR). */
4039	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4040	break;
4041
4042	default:
4043	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4044	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4045	break;
4046	}
4047	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4048	}
4049	else
4050	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
4051	return rc;
4052	}
4053
4054
4055	/**
4056	* #VMEXIT handler for instructions that result in a #UD exception delivered to
4057	* the guest.
4058	*/
4059	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4060	{
4061	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4062	hmR0SvmSetPendingXcptUD(pVCpu);
4063	return VINF_SUCCESS;
4064	}
4065
4066
4067	/**
4068	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4069	*/
4070	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4071	{
4072	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4073	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4074	PVM pVM = pVCpu->CTX_SUFF(pVM);
4075
4076	int rc;
4077	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4078	{
4079	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4080
4081	/* Handle TPR patching; intercepted LSTAR write. */
4082	if ( pVM->hm.s.fTPRPatchingActive
4083	&& pCtx->ecx == MSR_K8_LSTAR)
4084	{
4085	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4086	{
4087	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4088	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4089	AssertRC(rc2);
4090	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4091	}
4092	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4093	rc = VINF_SUCCESS;
4094	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4095	return rc;
4096	}
4097
4098	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4099	{
4100	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4101	if (RT_LIKELY(rc == VINF_SUCCESS))
4102	{
4103	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4104	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4105	}
4106	else
4107	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4108	}
4109	else
4110	{
4111	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4112	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4113	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4114	/* RIP updated by EMInterpretInstruction(). */
4115	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4116	}
4117
4118	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4119	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4120	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4121	{
4122	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4123	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4124	EMInterpretWrmsr() changes it. */
4125	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4126	}
4127	else if (pCtx->ecx == MSR_K6_EFER)
4128	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
4129	else if (pCtx->ecx == MSR_IA32_TSC)
4130	pSvmTransient->fUpdateTscOffsetting = true;
4131	}
4132	else
4133	{
4134	/* MSR Read access. */
4135	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4136	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4137
4138	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4139	{
4140	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4141	if (RT_LIKELY(rc == VINF_SUCCESS))
4142	{
4143	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4144	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4145	}
4146	else
4147	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4148	}
4149	else
4150	{
4151	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4152	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4153	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4154	/* RIP updated by EMInterpretInstruction(). */
4155	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4156	}
4157	}
4158
4159	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4160	return rc;
4161	}
4162
4163
4164	/**
4165	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4166	*/
4167	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4168	{
4169	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4170	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4171
4172	/* We should -not- get this VM-exit if the guest is debugging. */
4173	AssertMsgReturn(!CPUMIsGuestDebugStateActive(pVCpu),
4174	("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx),
4175	VERR_SVM_UNEXPECTED_EXIT);
4176
4177	/*
4178	* Lazy DR0-3 loading?
4179	*/
4180	if (!CPUMIsHyperDebugStateActive(pVCpu))
4181	{
4182	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4183	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4184
4185	/* Don't intercept DRx read and writes. */
4186	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4187	pVmcb->ctrl.u16InterceptRdDRx = 0;
4188	pVmcb->ctrl.u16InterceptWrDRx = 0;
4189	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4190
4191	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4192	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4193	Assert(CPUMIsGuestDebugStateActive(pVCpu));
4194
4195	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4196	return VINF_SUCCESS;
4197	}
4198
4199	/*
4200	* Interpret the read/writing of DRx.
4201	*/
4202	/** @todo Decode assist. */
4203	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4204	Log5(("hmR0SvmExitReadDRx: Emulatined DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4205	if (RT_LIKELY(rc == VINF_SUCCESS))
4206	{
4207	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4208	/** @todo CPUM should set this flag! */
4209	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4210	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4211	}
4212	else
4213	Assert(rc == VERR_EM_INTERPRETER);
4214	return VBOXSTRICTRC_TODO(rc);
4215	}
4216
4217
4218	/**
4219	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4220	*/
4221	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4222	{
4223	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4224	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4225	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4226	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4227	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4228	return rc;
4229	}
4230
4231
4232	/**
4233	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4234	*/
4235	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4236	{
4237	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4238
4239	/* I/O operation lookup arrays. */
4240	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4241	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4242	the result (in AL/AX/EAX). */
4243	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4244
4245	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4246	PVM pVM = pVCpu->CTX_SUFF(pVM);
4247
4248	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4249	SVMIOIOEXIT IoExitInfo;
4250	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4251	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4252	uint32_t cbValue = s_aIOSize[uIOWidth];
4253	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4254
4255	if (RT_UNLIKELY(!cbValue))
4256	{
4257	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4258	return VERR_EM_INTERPRETER;
4259	}
4260
4261	VBOXSTRICTRC rcStrict;
4262	if (IoExitInfo.n.u1STR)
4263	{
4264	/* INS/OUTS - I/O String instruction. */
4265	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4266
4267	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4268	* in EXITINFO1? Investigate once this thing is up and running. */
4269
4270	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4271	if (rcStrict == VINF_SUCCESS)
4272	{
4273	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4274	{
4275	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4276	(DISCPUMODE)pDis->uAddrMode, cbValue);
4277	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4278	}
4279	else
4280	{
4281	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4282	(DISCPUMODE)pDis->uAddrMode, cbValue);
4283	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4284	}
4285	}
4286	else
4287	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4288	}
4289	else
4290	{
4291	/* IN/OUT - I/O instruction. */
4292	Assert(!IoExitInfo.n.u1REP);
4293
4294	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4295	{
4296	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4297	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4298	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4299
4300	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4301	}
4302	else
4303	{
4304	uint32_t u32Val = 0;
4305
4306	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4307	if (IOM_SUCCESS(rcStrict))
4308	{
4309	/* Save result of I/O IN instr. in AL/AX/EAX. */
4310	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4311	}
4312	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4313	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4314
4315	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4316	}
4317	}
4318
4319	if (IOM_SUCCESS(rcStrict))
4320	{
4321	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4322	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4323
4324	/*
4325	* If any I/O breakpoints are armed, we need to check if one triggered
4326	* and take appropriate action.
4327	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4328	*/
4329	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4330	* execution engines about whether hyper BPs and such are pending. */
4331	uint32_t const uDr7 = pCtx->dr[7];
4332	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4333	&& X86_DR7_ANY_RW_IO(uDr7)
4334	&& (pCtx->cr4 & X86_CR4_DE))
4335	\|\| DBGFBpIsHwIoArmed(pVM)))
4336	{
4337	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4338	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
4339
4340	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4341	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4342	{
4343	/* Raise #DB. */
4344	pVmcb->guest.u64DR6 = pCtx->dr[6];
4345	pVmcb->guest.u64DR7 = pCtx->dr[7];
4346	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4347	hmR0SvmSetPendingXcptDB(pVCpu);
4348	}
4349	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4350	else if ( rcStrict2 != VINF_SUCCESS
4351	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
4352	rcStrict = rcStrict2;
4353	}
4354
4355	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4356	}
4357
4358	#ifdef VBOX_STRICT
4359	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4360	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4361	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4362	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4363	else
4364	{
4365	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4366	* statuses, that the VMM device and some others may return. See
4367	* IOM_SUCCESS() for guidance. */
4368	AssertMsg( RT_FAILURE(rcStrict)
4369	\|\| rcStrict == VINF_SUCCESS
4370	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
4371	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
4372	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
4373	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4374	}
4375	#endif
4376	return VBOXSTRICTRC_TODO(rcStrict);
4377	}
4378
4379
4380	/**
4381	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4382	* #VMEXIT.
4383	*/
4384	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4385	{
4386	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4387	PVM pVM = pVCpu->CTX_SUFF(pVM);
4388	Assert(pVM->hm.s.fNestedPaging);
4389
4390	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4391
4392	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4393	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4394	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4395	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4396
4397	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4398
4399	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4400	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4401	if ( pVM->hm.s.fTRPPatchingAllowed
4402	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4403	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4404	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4405	&& !CPUMGetGuestCPL(pVCpu)
4406	&& !CPUMIsGuestInLongModeEx(pCtx)
4407	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4408	{
4409	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4410	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4411
4412	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4413	{
4414	/* Only attempt to patch the instruction once. */
4415	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4416	if (!pPatch)
4417	return VINF_EM_HM_PATCH_TPR_INSTR;
4418	}
4419	}
4420	#endif
4421
4422	/*
4423	* Determine the nested paging mode.
4424	*/
4425	PGMMODE enmNestedPagingMode;
4426	#if HC_ARCH_BITS == 32
4427	if (CPUMIsGuestInLongModeEx(pCtx))
4428	enmNestedPagingMode = PGMMODE_AMD64_NX;
4429	else
4430	#endif
4431	enmNestedPagingMode = PGMGetHostMode(pVM);
4432
4433	/*
4434	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4435	*/
4436	int rc;
4437	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4438	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4439	{
4440	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4441	u32ErrCode);
4442	rc = VBOXSTRICTRC_VAL(rc2);
4443
4444	/*
4445	* If we succeed, resume guest execution.
4446	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4447	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4448	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4449	* weird case. See @bugref{6043}.
4450	*/
4451	if ( rc == VINF_SUCCESS
4452	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4453	\|\| rc == VERR_PAGE_NOT_PRESENT)
4454	{
4455	/* Successfully handled MMIO operation. */
4456	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4457	rc = VINF_SUCCESS;
4458	}
4459	return rc;
4460	}
4461
4462	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4463	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4464	TRPMResetTrap(pVCpu);
4465
4466	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4467
4468	/*
4469	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4470	*/
4471	if ( rc == VINF_SUCCESS
4472	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4473	\|\| rc == VERR_PAGE_NOT_PRESENT)
4474	{
4475	/* We've successfully synced our shadow page tables. */
4476	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4477	rc = VINF_SUCCESS;
4478	}
4479
4480	return rc;
4481	}
4482
4483
4484	/**
4485	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4486	*/
4487	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4488	{
4489	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4490
4491	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4492	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4493	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4494
4495	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4496	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4497	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4498
4499	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4500	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4501	return VINF_SUCCESS;
4502	}
4503
4504
4505	/**
4506	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4507	*/
4508	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4509	{
4510	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4511
4512	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4513	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4514	#endif
4515
4516	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4517	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4518	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4519	&& pVCpu->hm.s.Event.fPending)
4520	{
4521	/*
4522	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4523	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4524	* when the recompiler restarts the instruction.
4525	*/
4526	SVMEVENT Event;
4527	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4528	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4529	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4530	{
4531	pVCpu->hm.s.Event.fPending = false;
4532	}
4533	else
4534	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4535	}
4536
4537	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4538	* emulation. */
4539	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4540	return VERR_EM_INTERPRETER;
4541	}
4542
4543
4544	/**
4545	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4546	*/
4547	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4548	{
4549	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4550
4551	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4552	if (RT_LIKELY(rc == VINF_SUCCESS))
4553	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4554	else
4555	hmR0SvmSetPendingXcptUD(pVCpu);
4556	return VINF_SUCCESS;
4557	}
4558
4559
4560	/**
4561	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4562	* #VMEXIT.
4563	*/
4564	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4565	{
4566	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4567
4568	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4569
4570	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4571	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4572	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4573	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4574	PVM pVM = pVCpu->CTX_SUFF(pVM);
4575
4576	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4577	if (pVM->hm.s.fNestedPaging)
4578	{
4579	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4580	if (!pSvmTransient->fVectoringPF)
4581	{
4582	/* A genuine guest #PF, reflect it to the guest. */
4583	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4584	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4585	uFaultAddress, u32ErrCode));
4586	}
4587	else
4588	{
4589	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4590	hmR0SvmSetPendingXcptDF(pVCpu);
4591	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4592	}
4593	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4594	return VINF_SUCCESS;
4595	}
4596	#endif
4597
4598	Assert(!pVM->hm.s.fNestedPaging);
4599
4600	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4601	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4602	if ( pVM->hm.s.fTRPPatchingAllowed
4603	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4604	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
4605	&& !CPUMGetGuestCPL(pVCpu)
4606	&& !CPUMIsGuestInLongModeEx(pCtx)
4607	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4608	{
4609	RTGCPHYS GCPhysApicBase;
4610	GCPhysApicBase = pCtx->msrApicBase;
4611	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4612
4613	/* Check if the page at the fault-address is the APIC base. */
4614	RTGCPHYS GCPhysPage;
4615	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4616	if ( rc2 == VINF_SUCCESS
4617	&& GCPhysPage == GCPhysApicBase)
4618	{
4619	/* Only attempt to patch the instruction once. */
4620	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4621	if (!pPatch)
4622	return VINF_EM_HM_PATCH_TPR_INSTR;
4623	}
4624	}
4625	#endif
4626
4627	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4628	pCtx->rip, u32ErrCode, pCtx->cr3));
4629
4630	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4631	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4632
4633	Log4(("#PF rc=%Rrc\n", rc));
4634
4635	if (rc == VINF_SUCCESS)
4636	{
4637	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4638	TRPMResetTrap(pVCpu);
4639	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4640	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4641	return rc;
4642	}
4643	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4644	{
4645	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4646
4647	if (!pSvmTransient->fVectoringPF)
4648	{
4649	/* It's a guest page fault and needs to be reflected to the guest. */
4650	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4651	TRPMResetTrap(pVCpu);
4652	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4653	}
4654	else
4655	{
4656	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4657	TRPMResetTrap(pVCpu);
4658	hmR0SvmSetPendingXcptDF(pVCpu);
4659	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4660	}
4661
4662	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4663	return VINF_SUCCESS;
4664	}
4665
4666	TRPMResetTrap(pVCpu);
4667	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4668	return rc;
4669	}
4670
4671
4672	/**
4673	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4674	* Conditional #VMEXIT.
4675	*/
4676	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4677	{
4678	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4679
4680	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4681
4682	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4683	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4684	#endif
4685
4686	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4687	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4688	if (rc == VINF_SUCCESS)
4689	{
4690	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4691	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4692	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4693	return VINF_SUCCESS;
4694	}
4695
4696	/* Forward #NM to the guest. */
4697	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4698	hmR0SvmSetPendingXcptNM(pVCpu);
4699	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4700	return VINF_SUCCESS;
4701	}
4702
4703
4704	/**
4705	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4706	* Conditional #VMEXIT.
4707	*/
4708	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4709	{
4710	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4711
4712	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4713
4714	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4715
4716	if (!(pCtx->cr0 & X86_CR0_NE))
4717	{
4718	/* Old-style FPU error reporting needs some extra work. */
4719	/** @todo don't fall back to the recompiler, but do it manually. */
4720	return VERR_EM_INTERPRETER;
4721	}
4722
4723	hmR0SvmSetPendingXcptMF(pVCpu);
4724	return VINF_SUCCESS;
4725	}
4726
4727
4728	/**
4729	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4730	* #VMEXIT.
4731	*/
4732	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4733	{
4734	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4735
4736	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4737
4738	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4739
4740	/* If we set the trap flag above, we have to clear it. */
4741	if (pVCpu->hm.s.fClearTrapFlag)
4742	{
4743	pVCpu->hm.s.fClearTrapFlag = false;
4744	pCtx->eflags.Bits.u1TF = 0;
4745	}
4746
4747	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4748	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4749	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4750	PVM pVM = pVCpu->CTX_SUFF(pVM);
4751	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
4752	if (rc == VINF_EM_RAW_GUEST_TRAP)
4753	{
4754	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
4755	if (CPUMIsHyperDebugStateActive(pVCpu))
4756	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
4757
4758	/* Reflect the exception back to the guest. */
4759	hmR0SvmSetPendingXcptDB(pVCpu);
4760	rc = VINF_SUCCESS;
4761	}
4762
4763	/*
4764	* Update DR6.
4765	*/
4766	if (CPUMIsHyperDebugStateActive(pVCpu))
4767	{
4768	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
4769	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
4770	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4771	}
4772	else
4773	{
4774	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
4775	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
4776	}
4777
4778	return rc;
4779	}
4780
4781	/** @} */
4782

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 48140

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