HMSVMR0.cpp@ 48201

Last change on this file since 48201 was 48200, checked in by vboxsync, 11 years ago
VMM/HMSVMR0: Fewer inline hints.
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1	/* $Id: HMSVMR0.cpp 48200 2013-08-30 15:13:58Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HMSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32
33	#ifdef DEBUG_ramshankar
34	# define HMSVM_SYNC_FULL_GUEST_STATE
35	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
36	# define HMSVM_ALWAYS_TRAP_PF
37	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
38	#endif
39
40
41	/*******************************************************************************
42	* Defined Constants And Macros *
43	*******************************************************************************/
44	#ifdef VBOX_WITH_STATISTICS
45	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
46	if ((u64ExitCode) == SVM_EXIT_NPF) \
47	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
48	else \
49	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
50	} while (0)
51	#else
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
53	#endif
54
55	/** If we decide to use a function table approach this can be useful to
56	* switch to a "static DECLCALLBACK(int)". */
57	#define HMSVM_EXIT_DECL static int
58
59
60	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
61	*
62	* The CPU format of the segment attribute is described in X86DESCATTRBITS
63	* which is 16-bits (i.e. includes 4 bits of the segment limit).
64	*
65	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
66	* only the attribute bits and nothing else). Upper 4-bits are unused.
67	*
68	* @{ */
69	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
70	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
71	/** @} */
72
73
74	/** @name Macros for loading, storing segment registers to/from the VMCB.
75	* @{ */
76	#define HMSVM_LOAD_SEG_REG(REG, reg) \
77	do \
78	{ \
79	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
80	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
81	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
82	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
83	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
84	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
85	} while (0)
86
87	#define HMSVM_SAVE_SEG_REG(REG, reg) \
88	do \
89	{ \
90	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
92	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
93	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
94	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
95	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
96	} while (0)
97	/** @} */
98
99
100	/** Macro for checking and returning from the using function for
101	* \#VMEXIT intercepts that maybe caused during delivering of another
102	* event in the guest. */
103	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
104	do \
105	{ \
106	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
107	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
108	return VINF_SUCCESS; \
109	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
110	return rc; \
111	} while (0)
112
113	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
114	* instruction that exited. */
115	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
116	do { \
117	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
118	(a_rc) = VINF_EM_DBG_STEPPED; \
119	} while (0)
120
121	/** Assert that preemption is disabled or covered by thread-context hooks. */
122	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
123	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
124
125	/** Assert that we haven't migrated CPUs when thread-context hooks are not
126	* used. */
127	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
128	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
129	("Illegal migration! Entered on CPU %u Current %u\n", \
130	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
131
132	/** Exception bitmap mask for all contributory exceptions.
133	*
134	* Page fault is deliberately excluded here as it's conditional as to whether
135	* it's contributory or benign. Page faults are handled separately.
136	*/
137	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
138	\| RT_BIT(X86_XCPT_DE))
139
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean Bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG uEflags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
211	bool fRestoreTscAuxMsr;
212	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
213	* contributary exception or a page-fault. */
214	bool fVectoringPF;
215	/** Whether the TSC offset mode needs to be updated. */
216	bool fUpdateTscOffsetting;
217	} SVMTRANSIENT, *PSVMTRANSIENT;
218	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
219	AssertCompileMemberAlignment(SVMTRANSIENT, fRestoreTscAuxMsr, sizeof(uint64_t));
220	/** @} */
221
222
223	/**
224	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
225	*/
226	typedef enum SVMMSREXITREAD
227	{
228	/** Reading this MSR causes a VM-exit. */
229	SVMMSREXIT_INTERCEPT_READ = 0xb,
230	/** Reading this MSR does not cause a VM-exit. */
231	SVMMSREXIT_PASSTHRU_READ
232	} SVMMSREXITREAD;
233
234	/**
235	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
236	*/
237	typedef enum SVMMSREXITWRITE
238	{
239	/** Writing to this MSR causes a VM-exit. */
240	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
241	/** Writing to this MSR does not cause a VM-exit. */
242	SVMMSREXIT_PASSTHRU_WRITE
243	} SVMMSREXITWRITE;
244
245
246	/*******************************************************************************
247	* Internal Functions *
248	*******************************************************************************/
249	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
250	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
251	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
252
253	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
254	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
255	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
256	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
257	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
258	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
259	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
263	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
264	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
265	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
266	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
267	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
268	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
269	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
270	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
271	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
272	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
273	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
274	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
275	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
276	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
277	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
278	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
279	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
280
281	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
282
283
284	/*******************************************************************************
285	* Global Variables *
286	*******************************************************************************/
287	/** Ring-0 memory object for the IO bitmap. */
288	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
289	/** Physical address of the IO bitmap. */
290	RTHCPHYS g_HCPhysIOBitmap = 0;
291	/** Virtual address of the IO bitmap. */
292	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
293
294
295	/**
296	* Sets up and activates AMD-V on the current CPU.
297	*
298	* @returns VBox status code.
299	* @param pCpu Pointer to the CPU info struct.
300	* @param pVM Pointer to the VM (can be NULL after a resume!).
301	* @param pvCpuPage Pointer to the global CPU page.
302	* @param HCPhysCpuPage Physical address of the global CPU page.
303	*/
304	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
305	{
306	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
307	AssertReturn( HCPhysCpuPage
308	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
309	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
310
311	/*
312	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
313	*/
314	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
315	if (u64HostEfer & MSR_K6_EFER_SVME)
316	{
317	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
318	if ( pVM
319	&& pVM->hm.s.svm.fIgnoreInUseError)
320	{
321	pCpu->fIgnoreAMDVInUseError = true;
322	}
323
324	if (!pCpu->fIgnoreAMDVInUseError)
325	return VERR_SVM_IN_USE;
326	}
327
328	/* Turn on AMD-V in the EFER MSR. */
329	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
330
331	/* Write the physical page address where the CPU will store the host state while executing the VM. */
332	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
333
334	/*
335	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
336	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
337	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
338	* to flush the TLB with before using a new ASID.
339	*/
340	pCpu->fFlushAsidBeforeUse = true;
341
342	/*
343	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
344	*/
345	++pCpu->cTlbFlushes;
346
347	return VINF_SUCCESS;
348	}
349
350
351	/**
352	* Deactivates AMD-V on the current CPU.
353	*
354	* @returns VBox status code.
355	* @param pCpu Pointer to the CPU info struct.
356	* @param pvCpuPage Pointer to the global CPU page.
357	* @param HCPhysCpuPage Physical address of the global CPU page.
358	*/
359	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
360	{
361	AssertReturn( HCPhysCpuPage
362	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
363	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
364	NOREF(pCpu);
365
366	/* Turn off AMD-V in the EFER MSR. */
367	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
368	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
369
370	/* Invalidate host state physical address. */
371	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
372
373	return VINF_SUCCESS;
374	}
375
376
377	/**
378	* Does global AMD-V initialization (called during module initialization).
379	*
380	* @returns VBox status code.
381	*/
382	VMMR0DECL(int) SVMR0GlobalInit(void)
383	{
384	/*
385	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
386	* once globally here instead of per-VM.
387	*/
388	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
389	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
390	if (RT_FAILURE(rc))
391	return rc;
392
393	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
394	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
395
396	/* Set all bits to intercept all IO accesses. */
397	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
398	return VINF_SUCCESS;
399	}
400
401
402	/**
403	* Does global AMD-V termination (called during module termination).
404	*/
405	VMMR0DECL(void) SVMR0GlobalTerm(void)
406	{
407	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
408	{
409	RTR0MemObjFree(g_hMemObjIOBitmap, false /* fFreeMappings */);
410	g_pvIOBitmap = NULL;
411	g_HCPhysIOBitmap = 0;
412	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
413	}
414	}
415
416
417	/**
418	* Frees any allocated per-VCPU structures for a VM.
419	*
420	* @param pVM Pointer to the VM.
421	*/
422	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
423	{
424	for (uint32_t i = 0; i < pVM->cCpus; i++)
425	{
426	PVMCPU pVCpu = &pVM->aCpus[i];
427	AssertPtr(pVCpu);
428
429	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
430	{
431	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
432	pVCpu->hm.s.svm.pvVmcbHost = 0;
433	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
434	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
435	}
436
437	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
438	{
439	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
440	pVCpu->hm.s.svm.pvVmcb = 0;
441	pVCpu->hm.s.svm.HCPhysVmcb = 0;
442	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
443	}
444
445	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
446	{
447	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
448	pVCpu->hm.s.svm.pvMsrBitmap = 0;
449	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
450	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
451	}
452	}
453	}
454
455
456	/**
457	* Does per-VM AMD-V initialization.
458	*
459	* @returns VBox status code.
460	* @param pVM Pointer to the VM.
461	*/
462	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
463	{
464	int rc = VERR_INTERNAL_ERROR_5;
465
466	/*
467	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
468	*/
469	uint32_t u32Family;
470	uint32_t u32Model;
471	uint32_t u32Stepping;
472	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
473	{
474	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
475	pVM->hm.s.svm.fAlwaysFlushTLB = true;
476	}
477
478	/*
479	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
480	*/
481	for (VMCPUID i = 0; i < pVM->cCpus; i++)
482	{
483	PVMCPU pVCpu = &pVM->aCpus[i];
484	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
485	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
486	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
487	}
488
489	for (VMCPUID i = 0; i < pVM->cCpus; i++)
490	{
491	PVMCPU pVCpu = &pVM->aCpus[i];
492
493	/*
494	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
495	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
496	*/
497	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
498	if (RT_FAILURE(rc))
499	goto failure_cleanup;
500
501	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
502	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
503	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
504	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
505
506	/*
507	* Allocate one page for the guest-state VMCB.
508	*/
509	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
510	if (RT_FAILURE(rc))
511	goto failure_cleanup;
512
513	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
514	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
515	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
516	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
517
518	/*
519	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
520	* SVM to not require one.
521	*/
522	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
523	if (RT_FAILURE(rc))
524	goto failure_cleanup;
525
526	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
527	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
528	/* Set all bits to intercept all MSR accesses (changed later on). */
529	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
530	}
531
532	return VINF_SUCCESS;
533
534	failure_cleanup:
535	hmR0SvmFreeStructs(pVM);
536	return rc;
537	}
538
539
540	/**
541	* Does per-VM AMD-V termination.
542	*
543	* @returns VBox status code.
544	* @param pVM Pointer to the VM.
545	*/
546	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
547	{
548	hmR0SvmFreeStructs(pVM);
549	return VINF_SUCCESS;
550	}
551
552
553	/**
554	* Sets the permission bits for the specified MSR in the MSRPM.
555	*
556	* @param pVCpu Pointer to the VMCPU.
557	* @param uMsr The MSR for which the access permissions are being set.
558	* @param enmRead MSR read permissions.
559	* @param enmWrite MSR write permissions.
560	*/
561	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
562	{
563	unsigned ulBit;
564	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
565
566	/*
567	* Layout:
568	* Byte offset MSR range
569	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
570	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
571	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
572	* 0x1800 - 0x1fff Reserved
573	*/
574	if (uMsr <= 0x00001FFF)
575	{
576	/* Pentium-compatible MSRs. */
577	ulBit = uMsr * 2;
578	}
579	else if ( uMsr >= 0xC0000000
580	&& uMsr <= 0xC0001FFF)
581	{
582	/* AMD Sixth Generation x86 Processor MSRs. */
583	ulBit = (uMsr - 0xC0000000) * 2;
584	pbMsrBitmap += 0x800;
585	}
586	else if ( uMsr >= 0xC0010000
587	&& uMsr <= 0xC0011FFF)
588	{
589	/* AMD Seventh and Eighth Generation Processor MSRs. */
590	ulBit = (uMsr - 0xC0001000) * 2;
591	pbMsrBitmap += 0x1000;
592	}
593	else
594	{
595	AssertFailed();
596	return;
597	}
598
599	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
600	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
601	ASMBitSet(pbMsrBitmap, ulBit);
602	else
603	ASMBitClear(pbMsrBitmap, ulBit);
604
605	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
606	ASMBitSet(pbMsrBitmap, ulBit + 1);
607	else
608	ASMBitClear(pbMsrBitmap, ulBit + 1);
609
610	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
611	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
612	}
613
614
615	/**
616	* Sets up AMD-V for the specified VM.
617	* This function is only called once per-VM during initalization.
618	*
619	* @returns VBox status code.
620	* @param pVM Pointer to the VM.
621	*/
622	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
623	{
624	int rc = VINF_SUCCESS;
625
626	AssertReturn(pVM, VERR_INVALID_PARAMETER);
627	Assert(pVM->hm.s.svm.fSupported);
628
629	for (VMCPUID i = 0; i < pVM->cCpus; i++)
630	{
631	PVMCPU pVCpu = &pVM->aCpus[i];
632	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
633
634	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
635
636	/* Trap exceptions unconditionally (debug purposes). */
637	#ifdef HMSVM_ALWAYS_TRAP_PF
638	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
639	#endif
640	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
641	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
642	pVmcb->ctrl.u32InterceptException \|= 0
643	\| RT_BIT(X86_XCPT_BP)
644	\| RT_BIT(X86_XCPT_DB)
645	\| RT_BIT(X86_XCPT_DE)
646	\| RT_BIT(X86_XCPT_NM)
647	\| RT_BIT(X86_XCPT_UD)
648	\| RT_BIT(X86_XCPT_NP)
649	\| RT_BIT(X86_XCPT_SS)
650	\| RT_BIT(X86_XCPT_GP)
651	\| RT_BIT(X86_XCPT_PF)
652	\| RT_BIT(X86_XCPT_MF)
653	;
654	#endif
655
656	/* Set up unconditional intercepts and conditions. */
657	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a VM-exit. */
658	\| SVM_CTRL1_INTERCEPT_NMI /* Non-Maskable Interrupts causes a VM-exit. */
659	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a VM-exit. */
660	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a VM-exit. */
661	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a VM-exit. */
662	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a VM-exit. */
663	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a VM-exit. */
664	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO VM-exits. */
665	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a VM-exit.*/
666	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a VM-exit. */
667	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a VM-exit. */
668	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
669
670	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a VM-exit. */
671	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a VM-exit. */
672	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a VM-exit. */
673	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a VM-exit. */
674	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a VM-exit. */
675	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a VM-exit. */
676	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a VM-exit. */
677	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a VM-exit. */
678	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a VM-exit. */
679	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a VM-exit. */
680
681	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
682	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
683
684	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
685	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
686
687	/* Intercept all DRx reads and writes by default. Changed later on. */
688	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
689	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
690
691	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
692	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
693
694	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
695	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
696	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
697
698	/* Set IO and MSR bitmap permission bitmap physical addresses. */
699	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
700	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
701
702	/* No LBR virtualization. */
703	pVmcb->ctrl.u64LBRVirt = 0;
704
705	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
706	pVmcb->ctrl.u64VmcbCleanBits = 0;
707
708	/* The host ASID MBZ, for the guest start with 1. */
709	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
710
711	/*
712	* Setup the PAT MSR (applicable for Nested Paging only).
713	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
714	* so choose type 6 for all PAT slots.
715	*/
716	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
717
718	/* Without Nested Paging, we need additionally intercepts. */
719	if (!pVM->hm.s.fNestedPaging)
720	{
721	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
722	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
723	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
724
725	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
726	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
727	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
728
729	/* Page faults must be intercepted to implement shadow paging. */
730	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
731	}
732
733	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
734	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
735	#endif
736
737	/*
738	* The following MSRs are saved/restored automatically during the world-switch.
739	* Don't intercept guest read/write accesses to these MSRs.
740	*/
741	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
742	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
743	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
744	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
745	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
746	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
747	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
748	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
749	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
750	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
751	}
752
753	return rc;
754	}
755
756
757	/**
758	* Invalidates a guest page by guest virtual address.
759	*
760	* @returns VBox status code.
761	* @param pVM Pointer to the VM.
762	* @param pVCpu Pointer to the VMCPU.
763	* @param GCVirt Guest virtual address of the page to invalidate.
764	*/
765	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
766	{
767	AssertReturn(pVM, VERR_INVALID_PARAMETER);
768	Assert(pVM->hm.s.svm.fSupported);
769
770	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
771
772	/* Skip it if a TLB flush is already pending. */
773	if (!fFlushPending)
774	{
775	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
776
777	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
778	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
779
780	#if HC_ARCH_BITS == 32
781	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
782	if (CPUMIsGuestInLongMode(pVCpu))
783	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
784	else
785	#endif
786	{
787	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
788	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
789	}
790	}
791	return VINF_SUCCESS;
792	}
793
794
795	/**
796	* Flushes the appropriate tagged-TLB entries.
797	*
798	* @param pVM Pointer to the VM.
799	* @param pVCpu Pointer to the VMCPU.
800	*/
801	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
802	{
803	PVM pVM = pVCpu->CTX_SUFF(pVM);
804	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
805	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
806
807	/*
808	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
809	* This can happen both for start & resume due to long jumps back to ring-3.
810	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
811	* so we cannot reuse the ASIDs without flushing.
812	*/
813	bool fNewAsid = false;
814	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
815	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
816	{
817	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
818	pVCpu->hm.s.fForceTLBFlush = true;
819	fNewAsid = true;
820	}
821
822	/* Set TLB flush state as checked until we return from the world switch. */
823	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
824
825	/* Check for explicit TLB shootdowns. */
826	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
827	{
828	pVCpu->hm.s.fForceTLBFlush = true;
829	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
830	}
831
832	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
833	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
834
835	if (pVM->hm.s.svm.fAlwaysFlushTLB)
836	{
837	/*
838	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
839	*/
840	pCpu->uCurrentAsid = 1;
841	pVCpu->hm.s.uCurrentAsid = 1;
842	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
843	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
844	}
845	else if (pVCpu->hm.s.fForceTLBFlush)
846	{
847	if (fNewAsid)
848	{
849	++pCpu->uCurrentAsid;
850	bool fHitASIDLimit = false;
851	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
852	{
853	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
854	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
855	fHitASIDLimit = true;
856
857	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
858	{
859	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
860	pCpu->fFlushAsidBeforeUse = true;
861	}
862	else
863	{
864	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
865	pCpu->fFlushAsidBeforeUse = false;
866	}
867	}
868
869	if ( !fHitASIDLimit
870	&& pCpu->fFlushAsidBeforeUse)
871	{
872	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
873	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
874	else
875	{
876	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
877	pCpu->fFlushAsidBeforeUse = false;
878	}
879	}
880
881	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
882	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
883	}
884	else
885	{
886	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
887	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
888	else
889	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
890	}
891
892	pVCpu->hm.s.fForceTLBFlush = false;
893	}
894	else
895	{
896	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
897	* not be executed. See hmQueueInvlPage() where it is commented
898	* out. Support individual entry flushing someday. */
899	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
900	{
901	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
902	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
903	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
904	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
905	}
906	}
907
908	pVCpu->hm.s.TlbShootdown.cPages = 0;
909	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
910
911	/* Update VMCB with the ASID. */
912	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
913	{
914	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
915	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
916	}
917
918	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
919	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
920	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
921	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
922	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
923	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
924
925	#ifdef VBOX_WITH_STATISTICS
926	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
927	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
928	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
929	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
930	{
931	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
932	}
933	else
934	{
935	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
936	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
937	}
938	#endif
939	}
940
941
942	/** @name 64-bit guest on 32-bit host OS helper functions.
943	*
944	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
945	* mode (code segment, paging). These wrappers/helpers perform the necessary
946	* bits for the 32->64 switcher.
947	*
948	* @{ */
949	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
950	/**
951	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
952	*
953	* @returns VBox status code.
954	* @param HCPhysVmcbHost Physical address of host VMCB.
955	* @param HCPhysVmcb Physical address of the VMCB.
956	* @param pCtx Pointer to the guest-CPU context.
957	* @param pVM Pointer to the VM.
958	* @param pVCpu Pointer to the VMCPU.
959	*/
960	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
961	{
962	uint32_t aParam[4];
963	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
964	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
965	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
966	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
967
968	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
969	}
970
971
972	/**
973	* Executes the specified VMRUN handler in 64-bit mode.
974	*
975	* @returns VBox status code.
976	* @param pVM Pointer to the VM.
977	* @param pVCpu Pointer to the VMCPU.
978	* @param pCtx Pointer to the guest-CPU context.
979	* @param enmOp The operation to perform.
980	* @param cbParam Number of parameters.
981	* @param paParam Array of 32-bit parameters.
982	*/
983	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
984	uint32_t *paParam)
985	{
986	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
987	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
988
989	/* Disable interrupts. */
990	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
991
992	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
993	RTCPUID idHostCpu = RTMpCpuId();
994	CPUMR0SetLApic(pVCpu, idHostCpu);
995	#endif
996
997	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
998	CPUMSetHyperEIP(pVCpu, enmOp);
999	for (int i = (int)cbParam - 1; i >= 0; i--)
1000	CPUMPushHyper(pVCpu, paParam[i]);
1001
1002	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1003	/* Call the switcher. */
1004	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1005	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1006
1007	/* Restore interrupts. */
1008	ASMSetFlags(uOldEFlags);
1009	return rc;
1010	}
1011
1012	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1013	/** @} */
1014
1015
1016	/**
1017	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1018	* the corresponding VMCB Clean Bit.
1019	*
1020	* @param pVmcb Pointer to the VMCB.
1021	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1022	*/
1023	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1024	{
1025	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1026	{
1027	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1028	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1029	}
1030	}
1031
1032
1033	/**
1034	* Removes an exception from the intercept-exception bitmap in the VMCB and
1035	* updates the corresponding VMCB Clean Bit.
1036	*
1037	* @param pVmcb Pointer to the VMCB.
1038	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1039	*/
1040	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1041	{
1042	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1043	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1044	{
1045	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1046	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1047	}
1048	#endif
1049	}
1050
1051
1052	/**
1053	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1054	* Although the guest CR0 is a separate field in the VMCB we have to consider
1055	* the FPU state itself which is shared between the host and the guest.
1056	*
1057	* @returns VBox status code.
1058	* @param pVM Pointer to the VMCPU.
1059	* @param pVmcb Pointer to the VMCB.
1060	* @param pCtx Pointer to the guest-CPU context.
1061	*
1062	* @remarks No-long-jump zone!!!
1063	*/
1064	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1065	{
1066	/*
1067	* Guest CR0.
1068	*/
1069	PVM pVM = pVCpu->CTX_SUFF(pVM);
1070	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1071	{
1072	uint64_t u64GuestCR0 = pCtx->cr0;
1073
1074	/* Always enable caching. */
1075	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1076
1077	/*
1078	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1079	*/
1080	if (!pVM->hm.s.fNestedPaging)
1081	{
1082	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1083	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
1084	}
1085
1086	/*
1087	* Guest FPU bits.
1088	*/
1089	bool fInterceptNM = false;
1090	bool fInterceptMF = false;
1091	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1092	if (CPUMIsGuestFPUStateActive(pVCpu))
1093	{
1094	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1095	if (!(u64GuestCR0 & X86_CR0_NE))
1096	{
1097	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1098	fInterceptMF = true;
1099	}
1100	}
1101	else
1102	{
1103	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
1104	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1105	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1106	}
1107
1108	/*
1109	* Update the exception intercept bitmap.
1110	*/
1111	if (fInterceptNM)
1112	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1113	else
1114	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1115
1116	if (fInterceptMF)
1117	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1118	else
1119	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1120
1121	pVmcb->guest.u64CR0 = u64GuestCR0;
1122	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1123	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
1124	}
1125	}
1126
1127
1128	/**
1129	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1130	*
1131	* @returns VBox status code.
1132	* @param pVCpu Pointer to the VMCPU.
1133	* @param pVmcb Pointer to the VMCB.
1134	* @param pCtx Pointer to the guest-CPU context.
1135	*
1136	* @remarks No-long-jump zone!!!
1137	*/
1138	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1139	{
1140	PVM pVM = pVCpu->CTX_SUFF(pVM);
1141
1142	/*
1143	* Guest CR2.
1144	*/
1145	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR2)
1146	{
1147	pVmcb->guest.u64CR2 = pCtx->cr2;
1148	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1149	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
1150	}
1151
1152	/*
1153	* Guest CR3.
1154	*/
1155	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
1156	{
1157	if (pVM->hm.s.fNestedPaging)
1158	{
1159	PGMMODE enmShwPagingMode;
1160	#if HC_ARCH_BITS == 32
1161	if (CPUMIsGuestInLongModeEx(pCtx))
1162	enmShwPagingMode = PGMMODE_AMD64_NX;
1163	else
1164	#endif
1165	enmShwPagingMode = PGMGetHostMode(pVM);
1166
1167	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1168	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1169	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1170	pVmcb->guest.u64CR3 = pCtx->cr3;
1171	}
1172	else
1173	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1174
1175	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1176	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
1177	}
1178
1179	/*
1180	* Guest CR4.
1181	*/
1182	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
1183	{
1184	uint64_t u64GuestCR4 = pCtx->cr4;
1185	if (!pVM->hm.s.fNestedPaging)
1186	{
1187	switch (pVCpu->hm.s.enmShadowMode)
1188	{
1189	case PGMMODE_REAL:
1190	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1191	AssertFailed();
1192	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1193
1194	case PGMMODE_32_BIT: /* 32-bit paging. */
1195	u64GuestCR4 &= ~X86_CR4_PAE;
1196	break;
1197
1198	case PGMMODE_PAE: /* PAE paging. */
1199	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1200	/** Must use PAE paging as we could use physical memory > 4 GB */
1201	u64GuestCR4 \|= X86_CR4_PAE;
1202	break;
1203
1204	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1205	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1206	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1207	break;
1208	#else
1209	AssertFailed();
1210	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1211	#endif
1212
1213	default: /* shut up gcc */
1214	AssertFailed();
1215	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1216	}
1217	}
1218
1219	pVmcb->guest.u64CR4 = u64GuestCR4;
1220	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1221	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
1222	}
1223
1224	return VINF_SUCCESS;
1225	}
1226
1227
1228	/**
1229	* Loads the guest segment registers into the VMCB.
1230	*
1231	* @returns VBox status code.
1232	* @param pVCpu Pointer to the VMCPU.
1233	* @param pVmcb Pointer to the VMCB.
1234	* @param pCtx Pointer to the guest-CPU context.
1235	*
1236	* @remarks No-long-jump zone!!!
1237	*/
1238	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1239	{
1240	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1241	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
1242	{
1243	HMSVM_LOAD_SEG_REG(CS, cs);
1244	HMSVM_LOAD_SEG_REG(SS, ss);
1245	HMSVM_LOAD_SEG_REG(DS, ds);
1246	HMSVM_LOAD_SEG_REG(ES, es);
1247	HMSVM_LOAD_SEG_REG(FS, fs);
1248	HMSVM_LOAD_SEG_REG(GS, gs);
1249
1250	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1251	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
1252	}
1253
1254	/* Guest TR. */
1255	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
1256	{
1257	HMSVM_LOAD_SEG_REG(TR, tr);
1258	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
1259	}
1260
1261	/* Guest LDTR. */
1262	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
1263	{
1264	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1265	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
1266	}
1267
1268	/* Guest GDTR. */
1269	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
1270	{
1271	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1272	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1273	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1274	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
1275	}
1276
1277	/* Guest IDTR. */
1278	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
1279	{
1280	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1281	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1282	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1283	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
1284	}
1285	}
1286
1287
1288	/**
1289	* Loads the guest MSRs into the VMCB.
1290	*
1291	* @param pVCpu Pointer to the VMCPU.
1292	* @param pVmcb Pointer to the VMCB.
1293	* @param pCtx Pointer to the guest-CPU context.
1294	*
1295	* @remarks No-long-jump zone!!!
1296	*/
1297	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1298	{
1299	/* Guest Sysenter MSRs. */
1300	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1301	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1302	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1303
1304	/*
1305	* Guest EFER MSR.
1306	* AMD-V requires guest EFER.SVME to be set. Weird. .
1307	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1308	*/
1309	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_EFER_MSR)
1310	{
1311	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1312	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1313	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_EFER_MSR;
1314	}
1315
1316	/* 64-bit MSRs. */
1317	if (CPUMIsGuestInLongModeEx(pCtx))
1318	{
1319	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1320	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1321	}
1322	else
1323	{
1324	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1325	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1326	{
1327	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1328	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1329	}
1330	}
1331
1332
1333	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1334	* be writable in 32-bit mode. Clarify with AMD spec. */
1335	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1336	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1337	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1338	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1339	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1340	}
1341
1342
1343	/**
1344	* Loads the guest state into the VMCB and programs the necessary intercepts
1345	* accordingly.
1346	*
1347	* @param pVCpu Pointer to the VMCPU.
1348	* @param pVmcb Pointer to the VMCB.
1349	* @param pCtx Pointer to the guest-CPU context.
1350	*
1351	* @remarks No-long-jump zone!!!
1352	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1353	*/
1354	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1355	{
1356	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
1357	return;
1358	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1359	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1360
1361	bool fInterceptDB = false;
1362	bool fInterceptMovDRx = false;
1363
1364	/*
1365	* Anyone single stepping on the host side? If so, we'll have to use the
1366	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1367	* the VMM level like VT-x implementations does.
1368	*/
1369	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1370	if (fStepping)
1371	{
1372	pVCpu->hm.s.fClearTrapFlag = true;
1373	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1374	fInterceptDB = true;
1375	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1376	}
1377
1378	PVM pVM = pVCpu->CTX_SUFF(pVM);
1379	if (fStepping \|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1380	{
1381	/*
1382	* Use the combined guest and host DRx values found in the hypervisor
1383	* register set because the debugger has breakpoints active or someone
1384	* is single stepping on the host side.
1385	*
1386	* Note! DBGF expects a clean DR6 state before executing guest code.
1387	*/
1388	if (!CPUMIsHyperDebugStateActive(pVCpu))
1389	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1390	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1391	Assert(CPUMIsHyperDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
1392
1393	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1394	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1395	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu) )
1396	{
1397	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1398	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1399	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1400	}
1401
1402	/** @todo If we cared, we could optimize to allow the guest to read registers
1403	* with the same values. */
1404	fInterceptDB = true;
1405	fInterceptMovDRx = true;
1406	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1407	}
1408	else
1409	{
1410	/*
1411	* Update DR6, DR7 with the guest values if necessary.
1412	*/
1413	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1414	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1415	{
1416	pVmcb->guest.u64DR7 = pCtx->dr[7];
1417	pVmcb->guest.u64DR6 = pCtx->dr[6];
1418	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1419	}
1420
1421	/*
1422	* If the guest has enabled debug registers, we need to load them prior to
1423	* executing guest code so they'll trigger at the right time.
1424	*/
1425	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1426	{
1427	if (!CPUMIsGuestDebugStateActive(pVCpu))
1428	{
1429	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1430	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1431	}
1432	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1433	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
1434	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1435	}
1436	/*
1437	* If no debugging enabled, we'll lazy load DR0-3.
1438	*/
1439	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1440	fInterceptMovDRx = true;
1441	}
1442
1443	/*
1444	* Set up the intercepts.
1445	*/
1446	if (fInterceptDB)
1447	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1448	else
1449	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1450
1451	if (fInterceptMovDRx)
1452	{
1453	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1454	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1455	{
1456	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1457	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1458	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1459	}
1460	}
1461	else
1462	{
1463	if ( pVmcb->ctrl.u16InterceptRdDRx
1464	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1465	{
1466	pVmcb->ctrl.u16InterceptRdDRx = 0;
1467	pVmcb->ctrl.u16InterceptWrDRx = 0;
1468	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1469	}
1470	}
1471
1472	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
1473	}
1474
1475
1476	/**
1477	* Loads the guest APIC state (currently just the TPR).
1478	*
1479	* @returns VBox status code.
1480	* @param pVCpu Pointer to the VMCPU.
1481	* @param pVmcb Pointer to the VMCB.
1482	* @param pCtx Pointer to the guest-CPU context.
1483	*/
1484	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1485	{
1486	if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_SVM_GUEST_APIC_STATE))
1487	return VINF_SUCCESS;
1488
1489	bool fPendingIntr;
1490	uint8_t u8Tpr;
1491	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1492	AssertRCReturn(rc, rc);
1493
1494	/** Assume that we need to trap all TPR accesses and thus need not check on
1495	* every #VMEXIT if we should update the TPR. */
1496	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1497	pVCpu->hm.s.svm.fSyncVTpr = false;
1498
1499	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1500	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1501	{
1502	pCtx->msrLSTAR = u8Tpr;
1503
1504	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1505	if (fPendingIntr)
1506	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1507	else
1508	{
1509	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1510	pVCpu->hm.s.svm.fSyncVTpr = true;
1511	}
1512	}
1513	else
1514	{
1515	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1516	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1517
1518	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1519	if (fPendingIntr)
1520	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1521	else
1522	{
1523	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1524	pVCpu->hm.s.svm.fSyncVTpr = true;
1525	}
1526
1527	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1528	}
1529
1530	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_SVM_GUEST_APIC_STATE;
1531	return rc;
1532	}
1533
1534
1535	/**
1536	* Sets up the appropriate function to run guest code.
1537	*
1538	* @returns VBox status code.
1539	* @param pVCpu Pointer to the VMCPU.
1540	* @param pCtx Pointer to the guest-CPU context.
1541	*
1542	* @remarks No-long-jump zone!!!
1543	*/
1544	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1545	{
1546	if (CPUMIsGuestInLongModeEx(pCtx))
1547	{
1548	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1549	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1550	#endif
1551	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1552	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1553	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1554	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1555	#else
1556	/* 64-bit host or hybrid host. */
1557	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1558	#endif
1559	}
1560	else
1561	{
1562	/* Guest is not in long mode, use the 32-bit handler. */
1563	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1564	}
1565	return VINF_SUCCESS;
1566	}
1567
1568
1569	/**
1570	* Enters the AMD-V session.
1571	*
1572	* @returns VBox status code.
1573	* @param pVM Pointer to the VM.
1574	* @param pVCpu Pointer to the VMCPU.
1575	* @param pCpu Pointer to the CPU info struct.
1576	*/
1577	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1578	{
1579	AssertPtr(pVM);
1580	AssertPtr(pVCpu);
1581	Assert(pVM->hm.s.svm.fSupported);
1582	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1583	NOREF(pCpu);
1584
1585	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1586
1587	pVCpu->hm.s.fLeaveDone = false;
1588	return VINF_SUCCESS;
1589	}
1590
1591
1592	/**
1593	* Thread-context callback for AMD-V.
1594	*
1595	* @param enmEvent The thread-context event.
1596	* @param pVCpu Pointer to the VMCPU.
1597	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1598	*/
1599	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1600	{
1601	switch (enmEvent)
1602	{
1603	case RTTHREADCTXEVENT_PREEMPTING:
1604	{
1605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1606	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1607	VMCPU_ASSERT_EMT(pVCpu);
1608
1609	PVM pVM = pVCpu->CTX_SUFF(pVM);
1610	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1611	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1612
1613	if (!pVCpu->hm.s.fLeaveDone)
1614	{
1615	hmR0SvmLeave(pVM, pVCpu, pCtx);
1616	pVCpu->hm.s.fLeaveDone = true;
1617	}
1618
1619	int rc = HMR0LeaveCpu(pVCpu); /* Leave HM context, takes care of local init (term). */
1620	AssertRC(rc); NOREF(rc);
1621
1622	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1623	break;
1624	}
1625
1626	case RTTHREADCTXEVENT_RESUMED:
1627	{
1628	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1629	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1630	VMCPU_ASSERT_EMT(pVCpu);
1631
1632	VMMRZCallRing3Disable(pVCpu); /* No longjmps (log-flush, locks) in this fragile context. */
1633
1634	/*
1635	* Initialize the bare minimum state required for HM. This takes care of
1636	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1637	*/
1638	int rc = HMR0EnterCpu(pVCpu);
1639	AssertRC(rc); NOREF(rc);
1640	Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1641
1642	pVCpu->hm.s.fLeaveDone = false;
1643	VMMRZCallRing3Enable(pVCpu); /* Restore longjmp state. */
1644	break;
1645	}
1646
1647	default:
1648	break;
1649	}
1650	}
1651
1652
1653	/**
1654	* Saves the host state.
1655	*
1656	* @returns VBox status code.
1657	* @param pVM Pointer to the VM.
1658	* @param pVCpu Pointer to the VMCPU.
1659	*
1660	* @remarks No-long-jump zone!!!
1661	*/
1662	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1663	{
1664	NOREF(pVM);
1665	NOREF(pVCpu);
1666	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1667	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
1668	return VINF_SUCCESS;
1669	}
1670
1671
1672	/**
1673	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1674	* fields on every successful VM-entry.
1675	*
1676	* Sets up the appropriate VMRUN function to execute guest code based
1677	* on the guest CPU mode.
1678	*
1679	* @returns VBox status code.
1680	* @param pVM Pointer to the VM.
1681	* @param pVCpu Pointer to the VMCPU.
1682	* @param pMixedCtx Pointer to the guest-CPU context.
1683	*
1684	* @remarks No-long-jump zone!!!
1685	*/
1686	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1687	{
1688	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1689	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1690
1691	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1692
1693	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1694	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1695
1696	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1697	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1698
1699	pVmcb->guest.u64RIP = pCtx->rip;
1700	pVmcb->guest.u64RSP = pCtx->rsp;
1701	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1702	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1703	pVmcb->guest.u64RAX = pCtx->rax;
1704
1705	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1706	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1707
1708	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1709	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1710
1711	/* Clear any unused and reserved bits. */
1712	pVCpu->hm.s.fContextUseFlags &= ~( HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1713	\| HM_CHANGED_GUEST_RSP
1714	\| HM_CHANGED_GUEST_RFLAGS
1715	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1716	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1717	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1718	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1719	\| HM_CHANGED_SVM_RESERVED2
1720	\| HM_CHANGED_SVM_RESERVED3);
1721
1722	/* All the guest state bits should be loaded except maybe the host context and shared host/guest bits. */
1723	AssertMsg( !(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_ALL_GUEST)
1724	\|\| !(pVCpu->hm.s.fContextUseFlags & ~(HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE)),
1725	("Missed updating flags while loading guest state. pVM=%p pVCpu=%p fContextUseFlags=%#RX32\n",
1726	pVM, pVCpu, pVCpu->hm.s.fContextUseFlags));
1727
1728	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1729
1730	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1731	return rc;
1732	}
1733
1734
1735	/**
1736	* Loads the state shared between the host and guest into the
1737	* VMCB.
1738	*
1739	* @param pVM Pointer to the VM.
1740	* @param pVCpu Pointer to the VMCPU.
1741	* @param pCtx Pointer to the guest-CPU context.
1742	*
1743	* @remarks No-long-jump zone!!!
1744	*/
1745	static void hmR0VmxLoadSharedState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1746	{
1747	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1748	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1749	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1750
1751	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
1752	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1753
1754	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG)
1755	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1756
1757	AssertMsg(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE), ("fContextUseFlags=%#x\n",
1758	pVCpu->hm.s.fContextUseFlags));
1759	}
1760
1761
1762	/**
1763	* Saves the entire guest state from the VMCB into the
1764	* guest-CPU context. Currently there is no residual state left in the CPU that
1765	* is not updated in the VMCB.
1766	*
1767	* @returns VBox status code.
1768	* @param pVCpu Pointer to the VMCPU.
1769	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1770	* out-of-sync. Make sure to update the required fields
1771	* before using them.
1772	*/
1773	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1774	{
1775	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1776
1777	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1778
1779	pMixedCtx->rip = pVmcb->guest.u64RIP;
1780	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1781	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1782	pMixedCtx->rax = pVmcb->guest.u64RAX;
1783
1784	/*
1785	* Guest interrupt shadow.
1786	*/
1787	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1788	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1789	else
1790	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1791
1792	/*
1793	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1794	*/
1795	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1796
1797	/*
1798	* Guest MSRs.
1799	*/
1800	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1801	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1802	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1803	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1804	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1805	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1806	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1807	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1808
1809	/*
1810	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1811	*/
1812	HMSVM_SAVE_SEG_REG(CS, cs);
1813	HMSVM_SAVE_SEG_REG(SS, ss);
1814	HMSVM_SAVE_SEG_REG(DS, ds);
1815	HMSVM_SAVE_SEG_REG(ES, es);
1816	HMSVM_SAVE_SEG_REG(FS, fs);
1817	HMSVM_SAVE_SEG_REG(GS, gs);
1818
1819	/*
1820	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1821	* register (yet).
1822	*/
1823	/** @todo SELM might need to be fixed as it too should not care about the
1824	* granularity bit. See @bugref{6785}. */
1825	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1826	&& pMixedCtx->cs.Attr.n.u1Present
1827	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1828	{
1829	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1830	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1831	}
1832
1833	#ifdef VBOX_STRICT
1834	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1835	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1836	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1837	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1838	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1839	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1840	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1841
1842	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1843	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1844	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1845	HMSVM_ASSERT_SEG_GRANULARITY(es);
1846	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1847	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1848
1849	# undef HMSVM_ASSERT_SEL_GRANULARITY
1850	#endif
1851
1852	/*
1853	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1854	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1855	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1856	* See AMD spec. 15.5.1 "Basic operation".
1857	*/
1858	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1859	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1860
1861	/*
1862	* Guest Descriptor-Table registers.
1863	*/
1864	HMSVM_SAVE_SEG_REG(TR, tr);
1865	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1866	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1867	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1868
1869	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1870	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1871
1872	/*
1873	* Guest Debug registers.
1874	*/
1875	if (!CPUMIsHyperDebugStateActive(pVCpu))
1876	{
1877	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1878	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1879	}
1880	else
1881	{
1882	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
1883	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
1884	}
1885
1886	/*
1887	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
1888	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
1889	*/
1890	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
1891	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
1892	{
1893	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1894	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1895	}
1896	}
1897
1898
1899	/**
1900	* Does the necessary state syncing before returning to ring-3 for any reason
1901	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
1902	*
1903	* @param pVM Pointer to the VM.
1904	* @param pVCpu Pointer to the VMCPU.
1905	* @param pMixedCtx Pointer to the guest-CPU context.
1906	*
1907	* @remarks No-long-jmp zone!!!
1908	*/
1909	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1910	{
1911	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1912	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1913	Assert(VMMR0IsLogFlushDisabled(pVCpu));
1914
1915	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
1916	if (CPUMIsGuestFPUStateActive(pVCpu))
1917	{
1918	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1919	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1920	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1921	}
1922
1923	/*
1924	* Restore host debug registers if necessary and resync on next R0 reentry.
1925	*/
1926	#ifdef VBOX_STRICT
1927	if (CPUMIsHyperDebugStateActive(pVCpu))
1928	{
1929	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1930	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
1931	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
1932	}
1933	#endif
1934	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
1935	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
1936
1937	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1938	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1939
1940	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
1941	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
1942	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1943	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1944	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
1945
1946	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
1947	}
1948
1949
1950	/**
1951	* Leaves the AMD-V session.
1952	*
1953	* @returns VBox status code.
1954	* @param pVM Pointer to the VM.
1955	* @param pVCpu Pointer to the VMCPU.
1956	* @param pCtx Pointer to the guest-CPU context.
1957	*/
1958	static void hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1959	{
1960	HM_DISABLE_PREEMPT_IF_NEEDED();
1961	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1962	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1963
1964	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
1965	and done this from the VMXR0ThreadCtxCallback(). */
1966	if (!pVCpu->hm.s.fLeaveDone)
1967	{
1968	hmR0SvmLeave(pVM, pVCpu, pCtx);
1969	pVCpu->hm.s.fLeaveDone = true;
1970	}
1971
1972	/* Deregister hook now that we've left HM context before re-enabling preemption. */
1973	if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
1974	VMMR0ThreadCtxHooksDeregister(pVCpu);
1975
1976	/* Leave HM context. This takes care of local init (term). */
1977	int rc = HMR0LeaveCpu(pVCpu);
1978	AssertRC(rc); NOREF(rc);
1979
1980	HM_RESTORE_PREEMPT_IF_NEEDED();
1981	}
1982
1983
1984	/**
1985	* Does the necessary state syncing before doing a longjmp to ring-3.
1986	*
1987	* @param pVM Pointer to the VM.
1988	* @param pVCpu Pointer to the VMCPU.
1989	* @param pCtx Pointer to the guest-CPU context.
1990	*
1991	* @remarks No-long-jmp zone!!!
1992	*/
1993	static void hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1994	{
1995	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
1996	}
1997
1998
1999	/**
2000	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2001	* any remaining host state) before we longjump to ring-3 and possibly get
2002	* preempted.
2003	*
2004	* @param pVCpu Pointer to the VMCPU.
2005	* @param enmOperation The operation causing the ring-3 longjump.
2006	* @param pvUser The user argument (pointer to the possibly
2007	* out-of-date guest-CPU context).
2008	*
2009	* @remarks Must never be called with @a enmOperation ==
2010	* VMMCALLRING3_VM_R0_ASSERTION.
2011	*/
2012	DECLCALLBACK(void) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2013	{
2014	/* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion, */
2015	Assert(pVCpu);
2016	Assert(pvUser);
2017	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2018	HMSVM_ASSERT_PREEMPT_SAFE();
2019
2020	VMMRZCallRing3Disable(pVCpu);
2021	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2022
2023	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2024	hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2025
2026	VMMRZCallRing3Enable(pVCpu);
2027	}
2028
2029
2030	/**
2031	* Take necessary actions before going back to ring-3.
2032	*
2033	* An action requires us to go back to ring-3. This function does the necessary
2034	* steps before we can safely return to ring-3. This is not the same as longjmps
2035	* to ring-3, this is voluntary.
2036	*
2037	* @param pVM Pointer to the VM.
2038	* @param pVCpu Pointer to the VMCPU.
2039	* @param pCtx Pointer to the guest-CPU context.
2040	* @param rcExit The reason for exiting to ring-3. Can be
2041	* VINF_VMM_UNKNOWN_RING3_CALL.
2042	*/
2043	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2044	{
2045	Assert(pVM);
2046	Assert(pVCpu);
2047	Assert(pCtx);
2048	HMSVM_ASSERT_PREEMPT_SAFE();
2049
2050	if (RT_UNLIKELY(rcExit == VERR_SVM_INVALID_GUEST_STATE))
2051	{
2052	/* We don't need to do any syncing here, we're not going to come back to execute anything again. */
2053	return;
2054	}
2055
2056	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2057	VMMRZCallRing3Disable(pVCpu);
2058	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2059
2060	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2061	if (pVCpu->hm.s.Event.fPending)
2062	{
2063	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2064	Assert(!pVCpu->hm.s.Event.fPending);
2065	}
2066
2067	/* Sync. the necessary state for going back to ring-3. */
2068	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2069	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2070
2071	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2072	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2073	\| CPUM_CHANGED_LDTR
2074	\| CPUM_CHANGED_GDTR
2075	\| CPUM_CHANGED_IDTR
2076	\| CPUM_CHANGED_TR
2077	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2078	if ( pVM->hm.s.fNestedPaging
2079	&& CPUMIsGuestPagingEnabledEx(pCtx))
2080	{
2081	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2082	}
2083
2084	/* Make sure we've undo the trap flag if we tried to single step something. */
2085	if (pVCpu->hm.s.fClearTrapFlag)
2086	{
2087	pCtx->eflags.Bits.u1TF = 0;
2088	pVCpu->hm.s.fClearTrapFlag = false;
2089	}
2090
2091	/* On our way back from ring-3 the following needs to be done. */
2092	/** @todo This can change with preemption hooks. */
2093	if (rcExit == VINF_EM_RAW_INTERRUPT)
2094	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
2095	else
2096	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2097
2098	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2099	VMMRZCallRing3Enable(pVCpu);
2100	}
2101
2102
2103	/**
2104	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2105	* intercepts.
2106	*
2107	* @param pVCpu Pointer to the VMCPU.
2108	*
2109	* @remarks No-long-jump zone!!!
2110	*/
2111	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
2112	{
2113	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2114	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
2115	{
2116	uint64_t u64CurTSC = ASMReadTSC();
2117	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
2118	{
2119	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2120	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2121	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2122	}
2123	else
2124	{
2125	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2126	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2127	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
2128	}
2129	}
2130	else
2131	{
2132	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2133	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2134	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2135	}
2136
2137	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2138	}
2139
2140
2141	/**
2142	* Sets an event as a pending event to be injected into the guest.
2143	*
2144	* @param pVCpu Pointer to the VMCPU.
2145	* @param pEvent Pointer to the SVM event.
2146	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2147	* page-fault.
2148	*
2149	* @remarks Statistics counter assumes this is a guest event being reflected to
2150	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2151	*/
2152	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2153	{
2154	Assert(!pVCpu->hm.s.Event.fPending);
2155	Assert(pEvent->n.u1Valid);
2156
2157	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
2158	pVCpu->hm.s.Event.fPending = true;
2159	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2160
2161	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2162	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2163
2164	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2165	}
2166
2167
2168	/**
2169	* Injects an event into the guest upon VMRUN by updating the relevant field
2170	* in the VMCB.
2171	*
2172	* @param pVCpu Pointer to the VMCPU.
2173	* @param pVmcb Pointer to the guest VMCB.
2174	* @param pCtx Pointer to the guest-CPU context.
2175	* @param pEvent Pointer to the event.
2176	*
2177	* @remarks No-long-jump zone!!!
2178	* @remarks Requires CR0!
2179	*/
2180	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2181	{
2182	pVmcb->ctrl.EventInject.u = pEvent->u;
2183	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2184
2185	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2186	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2187	}
2188
2189
2190
2191	/**
2192	* Converts any TRPM trap into a pending HM event. This is typically used when
2193	* entering from ring-3 (not longjmp returns).
2194	*
2195	* @param pVCpu Pointer to the VMCPU.
2196	*/
2197	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2198	{
2199	Assert(TRPMHasTrap(pVCpu));
2200	Assert(!pVCpu->hm.s.Event.fPending);
2201
2202	uint8_t uVector;
2203	TRPMEVENT enmTrpmEvent;
2204	RTGCUINT uErrCode;
2205	RTGCUINTPTR GCPtrFaultAddress;
2206	uint8_t cbInstr;
2207
2208	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2209	AssertRC(rc);
2210
2211	SVMEVENT Event;
2212	Event.u = 0;
2213	Event.n.u1Valid = 1;
2214	Event.n.u8Vector = uVector;
2215
2216	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2217	if (enmTrpmEvent == TRPM_TRAP)
2218	{
2219	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2220	switch (uVector)
2221	{
2222	case X86_XCPT_PF:
2223	case X86_XCPT_DF:
2224	case X86_XCPT_TS:
2225	case X86_XCPT_NP:
2226	case X86_XCPT_SS:
2227	case X86_XCPT_GP:
2228	case X86_XCPT_AC:
2229	{
2230	Event.n.u1ErrorCodeValid = 1;
2231	Event.n.u32ErrorCode = uErrCode;
2232	break;
2233	}
2234	}
2235	}
2236	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2237	{
2238	if (uVector == X86_XCPT_NMI)
2239	Event.n.u3Type = SVM_EVENT_NMI;
2240	else
2241	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2242	}
2243	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2244	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2245	else
2246	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2247
2248	rc = TRPMResetTrap(pVCpu);
2249	AssertRC(rc);
2250
2251	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2252	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2253
2254	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2255	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2256	}
2257
2258
2259	/**
2260	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2261	* AMD-V to execute any instruction.
2262	*
2263	* @param pvCpu Pointer to the VMCPU.
2264	*/
2265	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2266	{
2267	Assert(pVCpu->hm.s.Event.fPending);
2268	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2269
2270	SVMEVENT Event;
2271	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2272
2273	uint8_t uVector = Event.n.u8Vector;
2274	uint8_t uVectorType = Event.n.u3Type;
2275
2276	TRPMEVENT enmTrapType;
2277	switch (uVectorType)
2278	{
2279	case SVM_EVENT_EXTERNAL_IRQ:
2280	case SVM_EVENT_NMI:
2281	enmTrapType = TRPM_HARDWARE_INT;
2282	break;
2283	case SVM_EVENT_SOFTWARE_INT:
2284	enmTrapType = TRPM_SOFTWARE_INT;
2285	break;
2286	case SVM_EVENT_EXCEPTION:
2287	enmTrapType = TRPM_TRAP;
2288	break;
2289	default:
2290	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2291	enmTrapType = TRPM_32BIT_HACK;
2292	break;
2293	}
2294
2295	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2296
2297	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2298	AssertRC(rc);
2299
2300	if (Event.n.u1ErrorCodeValid)
2301	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2302
2303	if ( uVectorType == SVM_EVENT_EXCEPTION
2304	&& uVector == X86_XCPT_PF)
2305	{
2306	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2307	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2308	}
2309	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2310	{
2311	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2312	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2313	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2314	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2315	}
2316	pVCpu->hm.s.Event.fPending = false;
2317	}
2318
2319
2320	/**
2321	* Gets the guest's interrupt-shadow.
2322	*
2323	* @returns The guest's interrupt-shadow.
2324	* @param pVCpu Pointer to the VMCPU.
2325	* @param pCtx Pointer to the guest-CPU context.
2326	*
2327	* @remarks No-long-jump zone!!!
2328	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2329	*/
2330	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2331	{
2332	/*
2333	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2334	* inhibit interrupts or clear any existing interrupt-inhibition.
2335	*/
2336	uint32_t uIntrState = 0;
2337	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2338	{
2339	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2340	{
2341	/*
2342	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2343	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2344	*/
2345	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2346	}
2347	else
2348	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2349	}
2350	return uIntrState;
2351	}
2352
2353
2354	/**
2355	* Sets the virtual interrupt intercept control in the VMCB which
2356	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2357	* receive interrupts.
2358	*
2359	* @param pVmcb Pointer to the VMCB.
2360	*/
2361	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2362	{
2363	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2364	{
2365	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2366	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2367	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2368	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2369
2370	Log4(("Setting VINTR intercept\n"));
2371	}
2372	}
2373
2374
2375	/**
2376	* Evaluates the event to be delivered to the guest and sets it as the pending
2377	* event.
2378	*
2379	* @param pVCpu Pointer to the VMCPU.
2380	* @param pCtx Pointer to the guest-CPU context.
2381	*/
2382	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2383	{
2384	Assert(!pVCpu->hm.s.Event.fPending);
2385	Log4Func(("\n"));
2386
2387	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2388	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2389	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2390
2391	SVMEVENT Event;
2392	Event.u = 0;
2393	/** @todo SMI. SMIs take priority over NMIs. */
2394	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2395	{
2396	if (!fIntShadow)
2397	{
2398	Log4(("Pending NMI\n"));
2399
2400	Event.n.u1Valid = 1;
2401	Event.n.u8Vector = X86_XCPT_NMI;
2402	Event.n.u3Type = SVM_EVENT_NMI;
2403
2404	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2405	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2406	}
2407	else
2408	hmR0SvmSetVirtIntrIntercept(pVmcb);
2409	}
2410	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2411	{
2412	/*
2413	* Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
2414	* the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
2415	* evaluated here and not set as pending, solely based on the force-flags.
2416	*/
2417	if ( !fBlockInt
2418	&& !fIntShadow)
2419	{
2420	uint8_t u8Interrupt;
2421	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2422	if (RT_SUCCESS(rc))
2423	{
2424	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2425
2426	Event.n.u1Valid = 1;
2427	Event.n.u8Vector = u8Interrupt;
2428	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2429
2430	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2431	}
2432	else
2433	{
2434	/** @todo Does this actually happen? If not turn it into an assertion. */
2435	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2436	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2437	}
2438	}
2439	else
2440	hmR0SvmSetVirtIntrIntercept(pVmcb);
2441	}
2442	}
2443
2444
2445	/**
2446	* Injects any pending events into the guest if the guest is in a state to
2447	* receive them.
2448	*
2449	* @param pVCpu Pointer to the VMCPU.
2450	* @param pCtx Pointer to the guest-CPU context.
2451	*/
2452	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2453	{
2454	Assert(!TRPMHasTrap(pVCpu));
2455	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2456	Log4Func(("\n"));
2457
2458	const bool fIntShadow = !!hmR0SvmGetGuestIntrShadow(pVCpu, pCtx);
2459	const bool fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2460	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2461
2462	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2463	{
2464	SVMEVENT Event;
2465	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2466	Assert(Event.n.u1Valid);
2467	#ifdef VBOX_STRICT
2468	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2469	{
2470	Assert(!fBlockInt);
2471	Assert(!fIntShadow);
2472	}
2473	else if (Event.n.u3Type == SVM_EVENT_NMI)
2474	Assert(!fIntShadow);
2475	#endif
2476
2477	Log4(("Injecting pending HM event.\n"));
2478	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2479	pVCpu->hm.s.Event.fPending = false;
2480
2481	#ifdef VBOX_WITH_STATISTICS
2482	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2483	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2484	else
2485	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2486	#endif
2487	}
2488
2489	/* Update the guest interrupt shadow in the VMCB. */
2490	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2491	}
2492
2493
2494	/**
2495	* Reports world-switch error and dumps some useful debug info.
2496	*
2497	* @param pVM Pointer to the VM.
2498	* @param pVCpu Pointer to the VMCPU.
2499	* @param rcVMRun The return code from VMRUN (or
2500	* VERR_SVM_INVALID_GUEST_STATE for invalid
2501	* guest-state).
2502	* @param pCtx Pointer to the guest-CPU context.
2503	*/
2504	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2505	{
2506	HMSVM_ASSERT_PREEMPT_SAFE();
2507	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2508
2509	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2510	{
2511	HMDumpRegs(pVM, pVCpu, pCtx);
2512	#ifdef VBOX_STRICT
2513	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2514	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2515	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2516	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2517	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2518	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2519	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2520	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2521	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2522	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2523	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2524
2525	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2526	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2527	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2528
2529	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2530	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2531	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2532	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2533	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2534	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2535	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2536	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2537	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2538	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2539
2540	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2541	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2542	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2543	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2544	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2545	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2546	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2547	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2548	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2549	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2550	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2551	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2552	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2553	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2554	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2555	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2556	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2557
2558	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2559	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2560
2561	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2562	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2563	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2564	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2565	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2566	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2567	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2568	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2569	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2570	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2571	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2572	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2573	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2574	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2575	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2576	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2577	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2578	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2579	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2580	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2581
2582	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2583	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2584
2585	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2586	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2587	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2588	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2589
2590	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2591	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2592
2593	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2594	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2595	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2596	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2597
2598	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2599	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2600	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2601	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2602	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2603	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2604	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2605
2606	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2607	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2608	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2609	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2610
2611	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2612	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2613	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2614
2615	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2616	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2617	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2618	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2619	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2620	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2621	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2622	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2623	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2624	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2625	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2626	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2627	#endif
2628	}
2629	else
2630	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2631	}
2632
2633
2634	/**
2635	* Check per-VM and per-VCPU force flag actions that require us to go back to
2636	* ring-3 for one reason or another.
2637	*
2638	* @returns VBox status code (information status code included).
2639	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2640	* ring-3.
2641	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2642	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2643	* interrupts)
2644	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2645	* all EMTs to be in ring-3.
2646	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2647	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2648	* to the EM loop.
2649	*
2650	* @param pVM Pointer to the VM.
2651	* @param pVCpu Pointer to the VMCPU.
2652	* @param pCtx Pointer to the guest-CPU context.
2653	*/
2654	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2655	{
2656	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2657
2658	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2659	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2660	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2661
2662	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2663	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2664	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2665	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2666	{
2667	/* Pending PGM C3 sync. */
2668	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2669	{
2670	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2671	if (rc != VINF_SUCCESS)
2672	{
2673	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2674	return rc;
2675	}
2676	}
2677
2678	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2679	/* -XXX- what was that about single stepping? */
2680	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2681	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2682	{
2683	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2684	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2685	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2686	return rc;
2687	}
2688
2689	/* Pending VM request packets, such as hardware interrupts. */
2690	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2691	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2692	{
2693	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2694	return VINF_EM_PENDING_REQUEST;
2695	}
2696
2697	/* Pending PGM pool flushes. */
2698	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2699	{
2700	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2701	return VINF_PGM_POOL_FLUSH_PENDING;
2702	}
2703
2704	/* Pending DMA requests. */
2705	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2706	{
2707	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2708	return VINF_EM_RAW_TO_R3;
2709	}
2710	}
2711
2712	return VINF_SUCCESS;
2713	}
2714
2715
2716	/**
2717	* Does the preparations before executing guest code in AMD-V.
2718	*
2719	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2720	* recompiler. We must be cautious what we do here regarding committing
2721	* guest-state information into the the VMCB assuming we assuredly execute the
2722	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2723	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2724	* that the recompiler can (and should) use them when it resumes guest
2725	* execution. Otherwise such operations must be done when we can no longer
2726	* exit to ring-3.
2727	*
2728	* @returns VBox status code (informational status codes included).
2729	* @retval VINF_SUCCESS if we can proceed with running the guest.
2730	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2731	*
2732	* @param pVM Pointer to the VM.
2733	* @param pVCpu Pointer to the VMCPU.
2734	* @param pCtx Pointer to the guest-CPU context.
2735	* @param pSvmTransient Pointer to the SVM transient structure.
2736	*/
2737	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2738	{
2739	/* Check force flag actions that might require us to go back to ring-3. */
2740	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2741	if (rc != VINF_SUCCESS)
2742	return rc;
2743
2744	if (TRPMHasTrap(pVCpu))
2745	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2746	else if (!pVCpu->hm.s.Event.fPending)
2747	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2748
2749	/*
2750	* Re-enable nested paging (automatically disabled on every VM-exit). See AMD spec. 15.25.3 "Enabling Nested Paging".
2751	* We avoid changing the corresponding VMCB Clean Bit as we're not changing it to a different value since the previous run.
2752	*/
2753	/** @todo The above assumption could be wrong. It's not documented what
2754	* should be done wrt to the VMCB Clean Bit, but we'll find out the
2755	* hard way. */
2756	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2757	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
2758
2759	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2760	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_ALL_GUEST;
2761	#endif
2762
2763	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
2764	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2765	AssertRCReturn(rc, rc);
2766	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2767
2768	/*
2769	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2770	* so we can update it on the way back if the guest changed the TPR.
2771	*/
2772	if (pVCpu->hm.s.svm.fSyncVTpr)
2773	{
2774	if (pVM->hm.s.fTPRPatchingActive)
2775	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2776	else
2777	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2778	}
2779
2780	/*
2781	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
2782	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
2783	*
2784	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
2785	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
2786	*
2787	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
2788	* executing guest code.
2789	*/
2790	pSvmTransient->uEflags = ASMIntDisableFlags();
2791	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2792	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2793	{
2794	ASMSetFlags(pSvmTransient->uEflags);
2795	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2796	return VINF_EM_RAW_TO_R3;
2797	}
2798	else if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2799	{
2800	ASMSetFlags(pSvmTransient->uEflags);
2801	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
2802	return VINF_EM_RAW_INTERRUPT;
2803	}
2804
2805	/* Indicate the start of guest execution. No more longjmps or returns to ring-3 from this point!!! */
2806	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2807	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2808
2809	return VINF_SUCCESS;
2810	}
2811
2812
2813	/**
2814	* Prepares to run guest code in AMD-V and we've committed to doing so. This
2815	* means there is no backing out to ring-3 or anywhere else at this
2816	* point.
2817	*
2818	* @param pVM Pointer to the VM.
2819	* @param pVCpu Pointer to the VMCPU.
2820	* @param pCtx Pointer to the guest-CPU context.
2821	* @param pSvmTransient Pointer to the SVM transient structure.
2822	*
2823	* @remarks Called with preemption disabled.
2824	* @remarks No-long-jump zone!!!
2825	*/
2826	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2827	{
2828	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2829	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2830
2831	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
2832
2833	/* Load the state shared between host and guest (FPU, debug). */
2834	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE)
2835	hmR0VmxLoadSharedState(pVM, pVCpu, pCtx);
2836	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
2837	AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags=%#x\n", pVCpu->hm.s.fContextUseFlags));
2838
2839	/* If VMCB Clean Bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
2840	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2841	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
2842	pVmcb->ctrl.u64VmcbCleanBits = 0;
2843
2844	/* Setup TSC offsetting. */
2845	if ( pSvmTransient->fUpdateTscOffsetting
2846	\|\| HMR0GetCurrentCpu()->idCpu != pVCpu->hm.s.idLastCpu)
2847	{
2848	hmR0SvmUpdateTscOffsetting(pVCpu);
2849	pSvmTransient->fUpdateTscOffsetting = false;
2850	}
2851
2852	/* Flush the appropriate tagged-TLB entries. */
2853	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
2854	hmR0SvmFlushTaggedTlb(pVCpu);
2855	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
2856
2857	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
2858
2859	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
2860	to start executing. */
2861
2862	/*
2863	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
2864	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
2865	*
2866	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
2867	*/
2868	pSvmTransient->fRestoreTscAuxMsr = false;
2869	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
2870	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
2871	{
2872	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
2873	uint64_t u64GuestTscAux = 0;
2874	int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
2875	AssertRC(rc2);
2876	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
2877	{
2878	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
2879	pSvmTransient->fRestoreTscAuxMsr = true;
2880	}
2881	}
2882	}
2883
2884
2885	/**
2886	* Wrapper for running the guest code in AMD-V.
2887	*
2888	* @returns VBox strict status code.
2889	* @param pVM Pointer to the VM.
2890	* @param pVCpu Pointer to the VMCPU.
2891	* @param pCtx Pointer to the guest-CPU context.
2892	*
2893	* @remarks No-long-jump zone!!!
2894	*/
2895	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2896	{
2897	/*
2898	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
2899	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
2900	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
2901	*/
2902	#ifdef VBOX_WITH_KERNEL_USING_XMM
2903	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
2904	pVCpu->hm.s.svm.pfnVMRun);
2905	#else
2906	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
2907	#endif
2908	}
2909
2910
2911	/**
2912	* Performs some essential restoration of state after running guest code in
2913	* AMD-V.
2914	*
2915	* @param pVM Pointer to the VM.
2916	* @param pVCpu Pointer to the VMCPU.
2917	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
2918	* out-of-sync. Make sure to update the required fields
2919	* before using them.
2920	* @param pSvmTransient Pointer to the SVM transient structure.
2921	* @param rcVMRun Return code of VMRUN.
2922	*
2923	* @remarks Called with interrupts disabled.
2924	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
2925	* unconditionally when it is safe to do so.
2926	*/
2927	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
2928	{
2929	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2930
2931	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
2932	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
2933
2934	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2935	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
2936
2937	if (pSvmTransient->fRestoreTscAuxMsr)
2938	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
2939
2940	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
2941	{
2942	/** @todo Find a way to fix hardcoding a guestimate. */
2943	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset - 0x400);
2944	}
2945
2946	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
2947	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
2948	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
2949
2950	Assert(!(ASMGetFlags() & X86_EFL_IF));
2951	ASMSetFlags(pSvmTransient->uEflags); /* Enable interrupts. */
2952
2953	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
2954
2955	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
2956	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
2957	{
2958	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
2959	return;
2960	}
2961
2962	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
2963	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
2964	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
2965
2966	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
2967	{
2968	if (pVCpu->hm.s.svm.fSyncVTpr)
2969	{
2970	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
2971	if ( pVM->hm.s.fTPRPatchingActive
2972	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
2973	{
2974	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
2975	AssertRC(rc);
2976	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2977	}
2978	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
2979	{
2980	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
2981	AssertRC(rc);
2982	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
2983	}
2984	}
2985	}
2986	}
2987
2988
2989	/**
2990	* Runs the guest code using AMD-V.
2991	*
2992	* @returns VBox status code.
2993	* @param pVM Pointer to the VM.
2994	* @param pVCpu Pointer to the VMCPU.
2995	* @param pCtx Pointer to the guest-CPU context.
2996	*/
2997	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2998	{
2999	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3000	HMSVM_ASSERT_PREEMPT_SAFE();
3001	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3002
3003	SVMTRANSIENT SvmTransient;
3004	SvmTransient.fUpdateTscOffsetting = true;
3005	uint32_t cLoops = 0;
3006	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3007	int rc = VERR_INTERNAL_ERROR_5;
3008
3009	for (;; cLoops++)
3010	{
3011	Assert(!HMR0SuspendPending());
3012	HMSVM_ASSERT_CPU_SAFE();
3013
3014	/* Preparatory work for running guest code, this may return to ring-3 for some last minute updates. */
3015	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3016	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3017	if (rc != VINF_SUCCESS)
3018	break;
3019
3020	/*
3021	* No longjmps to ring-3 from this point on!!!
3022	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3023	* This also disables flushing of the R0-logger instance (if any).
3024	*/
3025	VMMRZCallRing3Disable(pVCpu);
3026	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3027
3028	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3029
3030	/*
3031	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3032	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3033	*/
3034	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3035	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3036	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3037	{
3038	if (rc == VINF_SUCCESS)
3039	rc = VERR_SVM_INVALID_GUEST_STATE;
3040	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3041	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3042	break;
3043	}
3044
3045	/* Handle the #VMEXIT. */
3046	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3047	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3048	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3049	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3050	if (rc != VINF_SUCCESS)
3051	break;
3052	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
3053	{
3054	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3055	rc = VINF_EM_RAW_INTERRUPT;
3056	break;
3057	}
3058	}
3059
3060	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3061	if (rc == VERR_EM_INTERPRETER)
3062	rc = VINF_EM_RAW_EMULATE_INSTR;
3063	else if (rc == VINF_EM_RESET)
3064	rc = VINF_EM_TRIPLE_FAULT;
3065
3066	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3067	VMMRZCallRing3RemoveNotification(pVCpu);
3068	return rc;
3069	}
3070
3071
3072	/**
3073	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3074	*
3075	* @returns VBox status code (informational status codes included).
3076	* @param pVCpu Pointer to the VMCPU.
3077	* @param pCtx Pointer to the guest-CPU context.
3078	* @param pSvmTransient Pointer to the SVM transient structure.
3079	*/
3080	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3081	{
3082	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3083	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3084
3085	/*
3086	* The ordering of the case labels is based on most-frequently-occurring VM-exits for most guests under
3087	* normal workloads (for some definition of "normal").
3088	*/
3089	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3090	switch (pSvmTransient->u64ExitCode)
3091	{
3092	case SVM_EXIT_NPF:
3093	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3094
3095	case SVM_EXIT_IOIO:
3096	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3097
3098	case SVM_EXIT_RDTSC:
3099	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3100
3101	case SVM_EXIT_RDTSCP:
3102	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3103
3104	case SVM_EXIT_CPUID:
3105	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3106
3107	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3108	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3109
3110	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3111	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3112
3113	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3114	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3115
3116	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3117	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3118
3119	case SVM_EXIT_MONITOR:
3120	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3121
3122	case SVM_EXIT_MWAIT:
3123	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3124
3125	case SVM_EXIT_HLT:
3126	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3127
3128	case SVM_EXIT_READ_CR0:
3129	case SVM_EXIT_READ_CR3:
3130	case SVM_EXIT_READ_CR4:
3131	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3132
3133	case SVM_EXIT_WRITE_CR0:
3134	case SVM_EXIT_WRITE_CR3:
3135	case SVM_EXIT_WRITE_CR4:
3136	case SVM_EXIT_WRITE_CR8:
3137	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3138
3139	case SVM_EXIT_VINTR:
3140	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3141
3142	case SVM_EXIT_INTR:
3143	case SVM_EXIT_FERR_FREEZE:
3144	case SVM_EXIT_NMI:
3145	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3146
3147	case SVM_EXIT_MSR:
3148	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3149
3150	case SVM_EXIT_INVLPG:
3151	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3152
3153	case SVM_EXIT_WBINVD:
3154	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3155
3156	case SVM_EXIT_INVD:
3157	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3158
3159	case SVM_EXIT_RDPMC:
3160	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3161
3162	default:
3163	{
3164	switch (pSvmTransient->u64ExitCode)
3165	{
3166	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3167	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3168	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3169	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3170	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3171
3172	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3173	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3174	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3175	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3176	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3177
3178	case SVM_EXIT_TASK_SWITCH:
3179	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3180
3181	case SVM_EXIT_VMMCALL:
3182	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3183
3184	case SVM_EXIT_SHUTDOWN:
3185	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3186
3187	case SVM_EXIT_SMI:
3188	case SVM_EXIT_INIT:
3189	{
3190	/*
3191	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3192	* we want to know about it so log the exit code and bail.
3193	*/
3194	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3195	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3196	return VERR_SVM_UNEXPECTED_EXIT;
3197	}
3198
3199	case SVM_EXIT_INVLPGA:
3200	case SVM_EXIT_RSM:
3201	case SVM_EXIT_VMRUN:
3202	case SVM_EXIT_VMLOAD:
3203	case SVM_EXIT_VMSAVE:
3204	case SVM_EXIT_STGI:
3205	case SVM_EXIT_CLGI:
3206	case SVM_EXIT_SKINIT:
3207	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3208
3209	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3210	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3211	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3212	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3213	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3214	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3215	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3216	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3217	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3218	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3219	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3220	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3221	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3222	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3223	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3224	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3225	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3226	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3227	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3228	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3229
3230	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3231	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3232	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3233	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3234	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3235	{
3236	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3237	SVMEVENT Event;
3238	Event.u = 0;
3239	Event.n.u1Valid = 1;
3240	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3241	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3242
3243	switch (Event.n.u8Vector)
3244	{
3245	case X86_XCPT_DE:
3246	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3247	break;
3248
3249	case X86_XCPT_BP:
3250	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3251	* next instruction. */
3252	/** @todo Investigate this later. */
3253	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3254	break;
3255
3256	case X86_XCPT_UD:
3257	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3258	break;
3259
3260	case X86_XCPT_NP:
3261	Event.n.u1ErrorCodeValid = 1;
3262	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3263	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3264	break;
3265
3266	case X86_XCPT_SS:
3267	Event.n.u1ErrorCodeValid = 1;
3268	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3269	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3270	break;
3271
3272	case X86_XCPT_GP:
3273	Event.n.u1ErrorCodeValid = 1;
3274	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3275	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3276	break;
3277
3278	default:
3279	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3280	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3281	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3282	}
3283
3284	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3285	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3286	return VINF_SUCCESS;
3287	}
3288	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3289
3290	default:
3291	{
3292	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3293	pVCpu->hm.s.u32HMError = u32ExitCode;
3294	return VERR_SVM_UNKNOWN_EXIT;
3295	}
3296	}
3297	}
3298	}
3299	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3300	}
3301
3302
3303	#ifdef DEBUG
3304	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3305	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3306	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3307
3308	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3309	do \
3310	{ \
3311	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3312	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3313	} while (0)
3314
3315	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3316	do { \
3317	AssertPtr(pVCpu); \
3318	AssertPtr(pCtx); \
3319	AssertPtr(pSvmTransient); \
3320	Assert(ASMIntAreEnabled()); \
3321	HMSVM_ASSERT_PREEMPT_SAFE(); \
3322	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3323	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3324	HMSVM_ASSERT_PREEMPT_SAFE(); \
3325	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3326	HMSVM_ASSERT_PREEMPT_CPUID(); \
3327	} while (0)
3328	#else /* Release builds */
3329	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { } while(0)
3330	#endif
3331
3332
3333	/**
3334	* Worker for hmR0SvmInterpretInvlpg().
3335	*
3336	* @return VBox status code.
3337	* @param pVCpu Pointer to the VMCPU.
3338	* @param pCpu Pointer to the disassembler state.
3339	* @param pRegFrame Pointer to the register frame.
3340	*/
3341	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3342	{
3343	DISQPVPARAMVAL Param1;
3344	RTGCPTR GCPtrPage;
3345
3346	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3347	if (RT_FAILURE(rc))
3348	return VERR_EM_INTERPRETER;
3349
3350	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3351	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3352	{
3353	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3354	return VERR_EM_INTERPRETER;
3355
3356	GCPtrPage = Param1.val.val64;
3357	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3358	rc = VBOXSTRICTRC_VAL(rc2);
3359	}
3360	else
3361	{
3362	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3363	rc = VERR_EM_INTERPRETER;
3364	}
3365
3366	return rc;
3367	}
3368
3369
3370	/**
3371	* Interprets INVLPG.
3372	*
3373	* @returns VBox status code.
3374	* @retval VINF_* Scheduling instructions.
3375	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3376	* @retval VERR_* Fatal errors.
3377	*
3378	* @param pVM Pointer to the VM.
3379	* @param pRegFrame Pointer to the register frame.
3380	*
3381	* @remarks Updates the RIP if the instruction was executed successfully.
3382	*/
3383	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3384	{
3385	/* Only allow 32 & 64 bit code. */
3386	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3387	{
3388	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3389	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3390	if ( RT_SUCCESS(rc)
3391	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3392	{
3393	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3394	if (RT_SUCCESS(rc))
3395	pRegFrame->rip += pDis->cbInstr;
3396	return rc;
3397	}
3398	else
3399	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3400	}
3401	return VERR_EM_INTERPRETER;
3402	}
3403
3404
3405	/**
3406	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3407	*
3408	* @param pVCpu Pointer to the VMCPU.
3409	*/
3410	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3411	{
3412	SVMEVENT Event;
3413	Event.u = 0;
3414	Event.n.u1Valid = 1;
3415	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3416	Event.n.u8Vector = X86_XCPT_UD;
3417	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3418	}
3419
3420
3421	/**
3422	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3423	*
3424	* @param pVCpu Pointer to the VMCPU.
3425	*/
3426	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3427	{
3428	SVMEVENT Event;
3429	Event.u = 0;
3430	Event.n.u1Valid = 1;
3431	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3432	Event.n.u8Vector = X86_XCPT_DB;
3433	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3434	}
3435
3436
3437	/**
3438	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3439	*
3440	* @param pVCpu Pointer to the VMCPU.
3441	* @param pCtx Pointer to the guest-CPU context.
3442	* @param u32ErrCode The error-code for the page-fault.
3443	* @param uFaultAddress The page fault address (CR2).
3444	*
3445	* @remarks This updates the guest CR2 with @a uFaultAddress!
3446	*/
3447	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3448	{
3449	SVMEVENT Event;
3450	Event.u = 0;
3451	Event.n.u1Valid = 1;
3452	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3453	Event.n.u8Vector = X86_XCPT_PF;
3454	Event.n.u1ErrorCodeValid = 1;
3455	Event.n.u32ErrorCode = u32ErrCode;
3456
3457	/* Update CR2 of the guest. */
3458	if (pCtx->cr2 != uFaultAddress)
3459	{
3460	pCtx->cr2 = uFaultAddress;
3461	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR2;
3462	}
3463
3464	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3465	}
3466
3467
3468	/**
3469	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3470	* VM.
3471	*
3472	* @param pVCpu Pointer to the VMCPU.
3473	*/
3474	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3475	{
3476	SVMEVENT Event;
3477	Event.u = 0;
3478	Event.n.u1Valid = 1;
3479	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3480	Event.n.u8Vector = X86_XCPT_NM;
3481	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3482	}
3483
3484
3485	/**
3486	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3487	*
3488	* @param pVCpu Pointer to the VMCPU.
3489	*/
3490	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3491	{
3492	SVMEVENT Event;
3493	Event.u = 0;
3494	Event.n.u1Valid = 1;
3495	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3496	Event.n.u8Vector = X86_XCPT_MF;
3497	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3498	}
3499
3500
3501	/**
3502	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3503	*
3504	* @param pVCpu Pointer to the VMCPU.
3505	*/
3506	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3507	{
3508	SVMEVENT Event;
3509	Event.u = 0;
3510	Event.n.u1Valid = 1;
3511	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3512	Event.n.u8Vector = X86_XCPT_DF;
3513	Event.n.u1ErrorCodeValid = 1;
3514	Event.n.u32ErrorCode = 0;
3515	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3516	}
3517
3518
3519	/**
3520	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3521	* guests. This simply looks up the patch record at EIP and does the required.
3522	*
3523	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3524	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3525	* TPR). See hmR3ReplaceTprInstr() for the details.
3526	*
3527	* @returns VBox status code.
3528	* @param pVM Pointer to the VM.
3529	* @param pVCpu Pointer to the VMCPU.
3530	* @param pCtx Pointer to the guest-CPU context.
3531	*/
3532	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3533	{
3534	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3535	for (;;)
3536	{
3537	bool fPending;
3538	uint8_t u8Tpr;
3539
3540	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3541	if (!pPatch)
3542	break;
3543
3544	switch (pPatch->enmType)
3545	{
3546	case HMTPRINSTR_READ:
3547	{
3548	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3549	AssertRC(rc);
3550
3551	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3552	AssertRC(rc);
3553	pCtx->rip += pPatch->cbOp;
3554	break;
3555	}
3556
3557	case HMTPRINSTR_WRITE_REG:
3558	case HMTPRINSTR_WRITE_IMM:
3559	{
3560	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3561	{
3562	uint32_t u32Val;
3563	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3564	AssertRC(rc);
3565	u8Tpr = u32Val;
3566	}
3567	else
3568	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3569
3570	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3571	AssertRC(rc2);
3572	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
3573
3574	pCtx->rip += pPatch->cbOp;
3575	break;
3576	}
3577
3578	default:
3579	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3580	pVCpu->hm.s.u32HMError = pPatch->enmType;
3581	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3582	}
3583	}
3584
3585	return VINF_SUCCESS;
3586	}
3587
3588	/**
3589	* Determines if an exception is a contributory exception. Contributory
3590	* exceptions are ones which can cause double-faults. Page-fault is
3591	* intentionally not included here as it's a conditional contributory exception.
3592	*
3593	* @returns true if the exception is contributory, false otherwise.
3594	* @param uVector The exception vector.
3595	*/
3596	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3597	{
3598	switch (uVector)
3599	{
3600	case X86_XCPT_GP:
3601	case X86_XCPT_SS:
3602	case X86_XCPT_NP:
3603	case X86_XCPT_TS:
3604	case X86_XCPT_DE:
3605	return true;
3606	default:
3607	break;
3608	}
3609	return false;
3610	}
3611
3612
3613	/**
3614	* Handle a condition that occurred while delivering an event through the guest
3615	* IDT.
3616	*
3617	* @returns VBox status code (informational error codes included).
3618	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
3619	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
3620	* continue execution of the guest which will delivery the #DF.
3621	* @retval VINF_EM_RESET if we detected a triple-fault condition.
3622	*
3623	* @param pVCpu Pointer to the VMCPU.
3624	* @param pCtx Pointer to the guest-CPU context.
3625	* @param pSvmTransient Pointer to the SVM transient structure.
3626	*
3627	* @remarks No-long-jump zone!!!
3628	*/
3629	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3630	{
3631	int rc = VINF_SUCCESS;
3632	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3633
3634	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
3635	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
3636	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
3637	{
3638	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
3639
3640	typedef enum
3641	{
3642	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
3643	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
3644	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
3645	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
3646	} SVMREFLECTXCPT;
3647
3648	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
3649	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
3650	{
3651	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
3652	{
3653	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
3654
3655	#ifdef VBOX_STRICT
3656	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
3657	&& uExitVector == X86_XCPT_PF)
3658	{
3659	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
3660	}
3661	#endif
3662	if ( uExitVector == X86_XCPT_PF
3663	&& uIdtVector == X86_XCPT_PF)
3664	{
3665	pSvmTransient->fVectoringPF = true;
3666	Log4(("IDT: Vectoring #PF uCR2=%#RX64\n", pCtx->cr2));
3667	}
3668	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
3669	&& hmR0SvmIsContributoryXcpt(uExitVector)
3670	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
3671	\|\| uIdtVector == X86_XCPT_PF))
3672	{
3673	enmReflect = SVMREFLECTXCPT_DF;
3674	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3675	uIdtVector, uExitVector));
3676	}
3677	else if (uIdtVector == X86_XCPT_DF)
3678	{
3679	enmReflect = SVMREFLECTXCPT_TF;
3680	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntrInfo,
3681	uIdtVector, uExitVector));
3682	}
3683	else
3684	enmReflect = SVMREFLECTXCPT_XCPT;
3685	}
3686	else
3687	{
3688	/*
3689	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
3690	* exception to the guest after handling the VM-exit.
3691	*/
3692	enmReflect = SVMREFLECTXCPT_XCPT;
3693	}
3694	}
3695	else if (pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
3696	{
3697	/* Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
3698	enmReflect = SVMREFLECTXCPT_XCPT;
3699	}
3700
3701	switch (enmReflect)
3702	{
3703	case SVMREFLECTXCPT_XCPT:
3704	{
3705	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
3706	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
3707
3708	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
3709	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
3710	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3711	break;
3712	}
3713
3714	case SVMREFLECTXCPT_DF:
3715	{
3716	hmR0SvmSetPendingXcptDF(pVCpu);
3717	rc = VINF_HM_DOUBLE_FAULT;
3718	break;
3719	}
3720
3721	case SVMREFLECTXCPT_TF:
3722	{
3723	rc = VINF_EM_RESET;
3724	break;
3725	}
3726
3727	default:
3728	Assert(rc == VINF_SUCCESS);
3729	break;
3730	}
3731	}
3732	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
3733	return rc;
3734	}
3735
3736
3737	/**
3738	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
3739	* CPU, otherwise advances the RIP by @a cb bytes.
3740	*
3741	* @param pVCpu Pointer to the VMCPU.
3742	* @param pCtx Pointer to the guest-CPU context.
3743	* @param cb RIP increment value in bytes.
3744	*
3745	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
3746	* when NRIP_SAVE is supported by the CPU!
3747	*/
3748	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
3749	{
3750	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
3751	{
3752	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3753	pCtx->rip = pVmcb->ctrl.u64NextRIP;
3754	}
3755	else
3756	pCtx->rip += cb;
3757	}
3758
3759
3760	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3761	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
3762	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
3763
3764	/** @name VM-exit handlers.
3765	* @{
3766	*/
3767
3768	/**
3769	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
3770	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
3771	*/
3772	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3773	{
3774	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3775
3776	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
3777	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmi);
3778	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
3779	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
3780
3781	/*
3782	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
3783	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
3784	* interrupt it is until the host actually take the interrupt.
3785	*
3786	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
3787	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
3788	*/
3789	return VINF_EM_RAW_INTERRUPT;
3790	}
3791
3792
3793	/**
3794	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
3795	*/
3796	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3797	{
3798	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3799
3800	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3801	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
3802	int rc = VINF_SUCCESS;
3803	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3804	return rc;
3805	}
3806
3807
3808	/**
3809	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
3810	*/
3811	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3812	{
3813	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3814
3815	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3816	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
3817	int rc = VINF_SUCCESS;
3818	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3819	return rc;
3820	}
3821
3822
3823	/**
3824	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
3825	*/
3826	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3827	{
3828	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3829	PVM pVM = pVCpu->CTX_SUFF(pVM);
3830	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3831	if (RT_LIKELY(rc == VINF_SUCCESS))
3832	{
3833	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3834	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3835	}
3836	else
3837	{
3838	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
3839	rc = VERR_EM_INTERPRETER;
3840	}
3841	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
3842	return rc;
3843	}
3844
3845
3846	/**
3847	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
3848	*/
3849	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3850	{
3851	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3852	PVM pVM = pVCpu->CTX_SUFF(pVM);
3853	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3854	if (RT_LIKELY(rc == VINF_SUCCESS))
3855	{
3856	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3857	pSvmTransient->fUpdateTscOffsetting = true;
3858
3859	/* Single step check. */
3860	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3861	}
3862	else
3863	{
3864	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
3865	rc = VERR_EM_INTERPRETER;
3866	}
3867	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
3868	return rc;
3869	}
3870
3871
3872	/**
3873	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
3874	*/
3875	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3876	{
3877	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3878	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
3879	if (RT_LIKELY(rc == VINF_SUCCESS))
3880	{
3881	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3882	pSvmTransient->fUpdateTscOffsetting = true;
3883	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3884	}
3885	else
3886	{
3887	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
3888	rc = VERR_EM_INTERPRETER;
3889	}
3890	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
3891	return rc;
3892	}
3893
3894
3895	/**
3896	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
3897	*/
3898	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3899	{
3900	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3901	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3902	if (RT_LIKELY(rc == VINF_SUCCESS))
3903	{
3904	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
3905	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3906	}
3907	else
3908	{
3909	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
3910	rc = VERR_EM_INTERPRETER;
3911	}
3912	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
3913	return rc;
3914	}
3915
3916
3917	/**
3918	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
3919	*/
3920	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3921	{
3922	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3923	PVM pVM = pVCpu->CTX_SUFF(pVM);
3924	Assert(!pVM->hm.s.fNestedPaging);
3925
3926	/** @todo Decode Assist. */
3927	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
3928	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
3929	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
3930	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3931	return rc;
3932	}
3933
3934
3935	/**
3936	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
3937	*/
3938	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3939	{
3940	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3941	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
3942	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
3943	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3944	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
3945	return rc;
3946	}
3947
3948
3949	/**
3950	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
3951	*/
3952	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3953	{
3954	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3955	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3956	if (RT_LIKELY(rc == VINF_SUCCESS))
3957	{
3958	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3959	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3960	}
3961	else
3962	{
3963	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
3964	rc = VERR_EM_INTERPRETER;
3965	}
3966	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
3967	return rc;
3968	}
3969
3970
3971	/**
3972	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
3973	*/
3974	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3975	{
3976	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
3977	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
3978	int rc = VBOXSTRICTRC_VAL(rc2);
3979	if ( rc == VINF_EM_HALT
3980	\|\| rc == VINF_SUCCESS)
3981	{
3982	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
3983
3984	if ( rc == VINF_EM_HALT
3985	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
3986	{
3987	rc = VINF_SUCCESS;
3988	}
3989	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
3990	}
3991	else
3992	{
3993	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
3994	rc = VERR_EM_INTERPRETER;
3995	}
3996	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
3997	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
3998	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
3999	return rc;
4000	}
4001
4002
4003	/**
4004	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
4005	* Conditional #VMEXIT.
4006	*/
4007	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4008	{
4009	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4010	return VINF_EM_RESET;
4011	}
4012
4013
4014	/**
4015	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
4016	*/
4017	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4018	{
4019	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4020
4021	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4022
4023	/** @todo Decode Assist. */
4024	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4025	int rc = VBOXSTRICTRC_VAL(rc2);
4026	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4027	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4028	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4029	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4030	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4031	return rc;
4032	}
4033
4034
4035	/**
4036	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
4037	*/
4038	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4039	{
4040	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4041	/** @todo Decode Assist. */
4042	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4043	int rc = VBOXSTRICTRC_VAL(rc2);
4044	if (rc == VINF_SUCCESS)
4045	{
4046	/* RIP has been updated by EMInterpretInstruction(). */
4047	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4048	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4049	{
4050	case 0: /* CR0. */
4051	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4052	break;
4053
4054	case 3: /* CR3. */
4055	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4056	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
4057	break;
4058
4059	case 4: /* CR4. */
4060	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
4061	break;
4062
4063	case 8: /* CR8 (TPR). */
4064	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4065	break;
4066
4067	default:
4068	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4069	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4070	break;
4071	}
4072	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4073	}
4074	else
4075	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
4076	return rc;
4077	}
4078
4079
4080	/**
4081	* #VMEXIT handler for instructions that result in a #UD exception delivered to
4082	* the guest.
4083	*/
4084	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4085	{
4086	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4087	hmR0SvmSetPendingXcptUD(pVCpu);
4088	return VINF_SUCCESS;
4089	}
4090
4091
4092	/**
4093	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4094	*/
4095	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4096	{
4097	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4098	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4099	PVM pVM = pVCpu->CTX_SUFF(pVM);
4100
4101	int rc;
4102	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4103	{
4104	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4105
4106	/* Handle TPR patching; intercepted LSTAR write. */
4107	if ( pVM->hm.s.fTPRPatchingActive
4108	&& pCtx->ecx == MSR_K8_LSTAR)
4109	{
4110	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4111	{
4112	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4113	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4114	AssertRC(rc2);
4115	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4116	}
4117	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4118	rc = VINF_SUCCESS;
4119	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4120	return rc;
4121	}
4122
4123	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4124	{
4125	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4126	if (RT_LIKELY(rc == VINF_SUCCESS))
4127	{
4128	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4129	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4130	}
4131	else
4132	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4133	}
4134	else
4135	{
4136	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4137	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4138	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4139	/* RIP updated by EMInterpretInstruction(). */
4140	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4141	}
4142
4143	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4144	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4145	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4146	{
4147	/* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4148	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4149	EMInterpretWrmsr() changes it. */
4150	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4151	}
4152	else if (pCtx->ecx == MSR_K6_EFER)
4153	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_EFER_MSR;
4154	else if (pCtx->ecx == MSR_IA32_TSC)
4155	pSvmTransient->fUpdateTscOffsetting = true;
4156	}
4157	else
4158	{
4159	/* MSR Read access. */
4160	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4161	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4162
4163	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4164	{
4165	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4166	if (RT_LIKELY(rc == VINF_SUCCESS))
4167	{
4168	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4169	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4170	}
4171	else
4172	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4173	}
4174	else
4175	{
4176	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4177	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4178	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4179	/* RIP updated by EMInterpretInstruction(). */
4180	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4181	}
4182	}
4183
4184	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4185	return rc;
4186	}
4187
4188
4189	/**
4190	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4191	*/
4192	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4193	{
4194	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4195	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4196
4197	/* We should -not- get this VM-exit if the guest is debugging. */
4198	AssertMsgReturn(!CPUMIsGuestDebugStateActive(pVCpu),
4199	("hmR0SvmExitReadDRx: Unexpected exit. pVCpu=%p pCtx=%p\n", pVCpu, pCtx),
4200	VERR_SVM_UNEXPECTED_EXIT);
4201
4202	/*
4203	* Lazy DR0-3 loading?
4204	*/
4205	if (!CPUMIsHyperDebugStateActive(pVCpu))
4206	{
4207	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4208	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4209
4210	/* Don't intercept DRx read and writes. */
4211	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4212	pVmcb->ctrl.u16InterceptRdDRx = 0;
4213	pVmcb->ctrl.u16InterceptWrDRx = 0;
4214	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4215
4216	/* We're playing with the host CPU state here, make sure we don't preempt. */
4217	HM_DISABLE_PREEMPT_IF_NEEDED();
4218
4219	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4220	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4221	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4222
4223	HM_RESTORE_PREEMPT_IF_NEEDED();
4224
4225	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4226	return VINF_SUCCESS;
4227	}
4228
4229	/*
4230	* Interpret the read/writing of DRx.
4231	*/
4232	/** @todo Decode assist. */
4233	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4234	Log5(("hmR0SvmExitReadDRx: Emulatined DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4235	if (RT_LIKELY(rc == VINF_SUCCESS))
4236	{
4237	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4238	/** @todo CPUM should set this flag! */
4239	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4240	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4241	}
4242	else
4243	Assert(rc == VERR_EM_INTERPRETER);
4244	return VBOXSTRICTRC_TODO(rc);
4245	}
4246
4247
4248	/**
4249	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4250	*/
4251	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4252	{
4253	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4254	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4255	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4256	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4257	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4258	return rc;
4259	}
4260
4261
4262	/**
4263	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4264	*/
4265	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4266	{
4267	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4268
4269	/* I/O operation lookup arrays. */
4270	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4271	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4272	the result (in AL/AX/EAX). */
4273	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4274
4275	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4276	PVM pVM = pVCpu->CTX_SUFF(pVM);
4277
4278	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4279	SVMIOIOEXIT IoExitInfo;
4280	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4281	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4282	uint32_t cbValue = s_aIOSize[uIOWidth];
4283	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4284
4285	if (RT_UNLIKELY(!cbValue))
4286	{
4287	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4288	return VERR_EM_INTERPRETER;
4289	}
4290
4291	VBOXSTRICTRC rcStrict;
4292	if (IoExitInfo.n.u1STR)
4293	{
4294	/* INS/OUTS - I/O String instruction. */
4295	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4296
4297	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4298	* in EXITINFO1? Investigate once this thing is up and running. */
4299
4300	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4301	if (rcStrict == VINF_SUCCESS)
4302	{
4303	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4304	{
4305	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4306	(DISCPUMODE)pDis->uAddrMode, cbValue);
4307	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4308	}
4309	else
4310	{
4311	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4312	(DISCPUMODE)pDis->uAddrMode, cbValue);
4313	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4314	}
4315	}
4316	else
4317	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4318	}
4319	else
4320	{
4321	/* IN/OUT - I/O instruction. */
4322	Assert(!IoExitInfo.n.u1REP);
4323
4324	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4325	{
4326	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4327	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4328	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4329
4330	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4331	}
4332	else
4333	{
4334	uint32_t u32Val = 0;
4335
4336	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4337	if (IOM_SUCCESS(rcStrict))
4338	{
4339	/* Save result of I/O IN instr. in AL/AX/EAX. */
4340	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4341	}
4342	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4343	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4344
4345	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4346	}
4347	}
4348
4349	if (IOM_SUCCESS(rcStrict))
4350	{
4351	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4352	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4353
4354	/*
4355	* If any I/O breakpoints are armed, we need to check if one triggered
4356	* and take appropriate action.
4357	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4358	*/
4359	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4360	* execution engines about whether hyper BPs and such are pending. */
4361	uint32_t const uDr7 = pCtx->dr[7];
4362	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4363	&& X86_DR7_ANY_RW_IO(uDr7)
4364	&& (pCtx->cr4 & X86_CR4_DE))
4365	\|\| DBGFBpIsHwIoArmed(pVM)))
4366	{
4367	/* We're playing with the host CPU state here, make sure we don't preempt. */
4368	HM_DISABLE_PREEMPT_IF_NEEDED();
4369
4370	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4371	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
4372
4373	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4374	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4375	{
4376	/* Raise #DB. */
4377	pVmcb->guest.u64DR6 = pCtx->dr[6];
4378	pVmcb->guest.u64DR7 = pCtx->dr[7];
4379	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4380	hmR0SvmSetPendingXcptDB(pVCpu);
4381	}
4382	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4383	else if ( rcStrict2 != VINF_SUCCESS
4384	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
4385	rcStrict = rcStrict2;
4386
4387	HM_RESTORE_PREEMPT_IF_NEEDED();
4388	}
4389
4390	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4391	}
4392
4393	#ifdef VBOX_STRICT
4394	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4395	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4396	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4397	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4398	else
4399	{
4400	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4401	* statuses, that the VMM device and some others may return. See
4402	* IOM_SUCCESS() for guidance. */
4403	AssertMsg( RT_FAILURE(rcStrict)
4404	\|\| rcStrict == VINF_SUCCESS
4405	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
4406	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
4407	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
4408	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4409	}
4410	#endif
4411	return VBOXSTRICTRC_TODO(rcStrict);
4412	}
4413
4414
4415	/**
4416	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4417	* #VMEXIT.
4418	*/
4419	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4420	{
4421	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4422	PVM pVM = pVCpu->CTX_SUFF(pVM);
4423	Assert(pVM->hm.s.fNestedPaging);
4424
4425	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4426
4427	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4428	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4429	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4430	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4431
4432	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4433
4434	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4435	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4436	if ( pVM->hm.s.fTRPPatchingAllowed
4437	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4438	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4439	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4440	&& !CPUMGetGuestCPL(pVCpu)
4441	&& !CPUMIsGuestInLongModeEx(pCtx)
4442	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4443	{
4444	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4445	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4446
4447	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4448	{
4449	/* Only attempt to patch the instruction once. */
4450	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4451	if (!pPatch)
4452	return VINF_EM_HM_PATCH_TPR_INSTR;
4453	}
4454	}
4455	#endif
4456
4457	/*
4458	* Determine the nested paging mode.
4459	*/
4460	PGMMODE enmNestedPagingMode;
4461	#if HC_ARCH_BITS == 32
4462	if (CPUMIsGuestInLongModeEx(pCtx))
4463	enmNestedPagingMode = PGMMODE_AMD64_NX;
4464	else
4465	#endif
4466	enmNestedPagingMode = PGMGetHostMode(pVM);
4467
4468	/*
4469	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4470	*/
4471	int rc;
4472	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4473	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4474	{
4475	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4476	u32ErrCode);
4477	rc = VBOXSTRICTRC_VAL(rc2);
4478
4479	/*
4480	* If we succeed, resume guest execution.
4481	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4482	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4483	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4484	* weird case. See @bugref{6043}.
4485	*/
4486	if ( rc == VINF_SUCCESS
4487	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4488	\|\| rc == VERR_PAGE_NOT_PRESENT)
4489	{
4490	/* Successfully handled MMIO operation. */
4491	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4492	rc = VINF_SUCCESS;
4493	}
4494	return rc;
4495	}
4496
4497	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4498	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4499	TRPMResetTrap(pVCpu);
4500
4501	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4502
4503	/*
4504	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4505	*/
4506	if ( rc == VINF_SUCCESS
4507	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4508	\|\| rc == VERR_PAGE_NOT_PRESENT)
4509	{
4510	/* We've successfully synced our shadow page tables. */
4511	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4512	rc = VINF_SUCCESS;
4513	}
4514
4515	return rc;
4516	}
4517
4518
4519	/**
4520	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4521	*/
4522	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4523	{
4524	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4525
4526	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4527	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one before reentry. */
4528	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4529
4530	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
4531	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4532	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4533
4534	/* Deliver the pending interrupt via hmR0SvmPreRunGuest()->hmR0SvmInjectEventVmcb() and resume guest execution. */
4535	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4536	return VINF_SUCCESS;
4537	}
4538
4539
4540	/**
4541	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4542	*/
4543	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4544	{
4545	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4546
4547	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4548	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4549	#endif
4550
4551	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4552	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4553	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4554	&& pVCpu->hm.s.Event.fPending)
4555	{
4556	/*
4557	* AMD-V does not provide us with the original exception but we have it in u64IntrInfo since we
4558	* injected the event during VM-entry. Software interrupts and exceptions will be regenerated
4559	* when the recompiler restarts the instruction.
4560	*/
4561	SVMEVENT Event;
4562	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
4563	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
4564	\|\| Event.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4565	{
4566	pVCpu->hm.s.Event.fPending = false;
4567	}
4568	else
4569	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery. Kept pending u8Vector=%#x\n", Event.n.u8Vector));
4570	}
4571
4572	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4573	* emulation. */
4574	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4575	return VERR_EM_INTERPRETER;
4576	}
4577
4578
4579	/**
4580	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4581	*/
4582	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4583	{
4584	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4585
4586	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4587	if (RT_LIKELY(rc == VINF_SUCCESS))
4588	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4589	else
4590	hmR0SvmSetPendingXcptUD(pVCpu);
4591	return VINF_SUCCESS;
4592	}
4593
4594
4595	/**
4596	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
4597	* #VMEXIT.
4598	*/
4599	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4600	{
4601	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4602
4603	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4604
4605	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
4606	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4607	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4608	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
4609	PVM pVM = pVCpu->CTX_SUFF(pVM);
4610
4611	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
4612	if (pVM->hm.s.fNestedPaging)
4613	{
4614	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4615	if (!pSvmTransient->fVectoringPF)
4616	{
4617	/* A genuine guest #PF, reflect it to the guest. */
4618	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4619	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
4620	uFaultAddress, u32ErrCode));
4621	}
4622	else
4623	{
4624	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4625	hmR0SvmSetPendingXcptDF(pVCpu);
4626	Log4(("Pending #DF due to vectoring #PF. NP\n"));
4627	}
4628	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4629	return VINF_SUCCESS;
4630	}
4631	#endif
4632
4633	Assert(!pVM->hm.s.fNestedPaging);
4634
4635	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4636	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
4637	if ( pVM->hm.s.fTRPPatchingAllowed
4638	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
4639	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
4640	&& !CPUMGetGuestCPL(pVCpu)
4641	&& !CPUMIsGuestInLongModeEx(pCtx)
4642	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4643	{
4644	RTGCPHYS GCPhysApicBase;
4645	GCPhysApicBase = pCtx->msrApicBase;
4646	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4647
4648	/* Check if the page at the fault-address is the APIC base. */
4649	RTGCPHYS GCPhysPage;
4650	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
4651	if ( rc2 == VINF_SUCCESS
4652	&& GCPhysPage == GCPhysApicBase)
4653	{
4654	/* Only attempt to patch the instruction once. */
4655	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4656	if (!pPatch)
4657	return VINF_EM_HM_PATCH_TPR_INSTR;
4658	}
4659	}
4660	#endif
4661
4662	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
4663	pCtx->rip, u32ErrCode, pCtx->cr3));
4664
4665	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
4666	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
4667
4668	Log4(("#PF rc=%Rrc\n", rc));
4669
4670	if (rc == VINF_SUCCESS)
4671	{
4672	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
4673	TRPMResetTrap(pVCpu);
4674	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4675	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_SVM_GUEST_APIC_STATE;
4676	return rc;
4677	}
4678	else if (rc == VINF_EM_RAW_GUEST_TRAP)
4679	{
4680	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
4681
4682	if (!pSvmTransient->fVectoringPF)
4683	{
4684	/* It's a guest page fault and needs to be reflected to the guest. */
4685	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
4686	TRPMResetTrap(pVCpu);
4687	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4688	}
4689	else
4690	{
4691	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
4692	TRPMResetTrap(pVCpu);
4693	hmR0SvmSetPendingXcptDF(pVCpu);
4694	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
4695	}
4696
4697	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
4698	return VINF_SUCCESS;
4699	}
4700
4701	TRPMResetTrap(pVCpu);
4702	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
4703	return rc;
4704	}
4705
4706
4707	/**
4708	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
4709	* Conditional #VMEXIT.
4710	*/
4711	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4712	{
4713	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4714
4715	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4716
4717	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
4718	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
4719	#endif
4720
4721	/* We're playing with the host CPU state here, make sure we don't preempt. */
4722	HM_DISABLE_PREEMPT_IF_NEEDED();
4723
4724	/* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
4725	int rc = CPUMR0LoadGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4726	if (rc == VINF_SUCCESS)
4727	{
4728	Assert(CPUMIsGuestFPUStateActive(pVCpu));
4729	HM_RESTORE_PREEMPT_IF_NEEDED();
4730
4731	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
4732	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
4733	return VINF_SUCCESS;
4734	}
4735
4736	HM_RESTORE_PREEMPT_IF_NEEDED();
4737
4738	/* Forward #NM to the guest. */
4739	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
4740	hmR0SvmSetPendingXcptNM(pVCpu);
4741	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
4742	return VINF_SUCCESS;
4743	}
4744
4745
4746	/**
4747	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
4748	* Conditional #VMEXIT.
4749	*/
4750	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4751	{
4752	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4753
4754	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4755
4756	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
4757
4758	if (!(pCtx->cr0 & X86_CR0_NE))
4759	{
4760	/* Old-style FPU error reporting needs some extra work. */
4761	/** @todo don't fall back to the recompiler, but do it manually. */
4762	return VERR_EM_INTERPRETER;
4763	}
4764
4765	hmR0SvmSetPendingXcptMF(pVCpu);
4766	return VINF_SUCCESS;
4767	}
4768
4769
4770	/**
4771	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
4772	* #VMEXIT.
4773	*/
4774	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4775	{
4776	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4777
4778	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4779
4780	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
4781
4782	/* If we set the trap flag above, we have to clear it. */
4783	if (pVCpu->hm.s.fClearTrapFlag)
4784	{
4785	pVCpu->hm.s.fClearTrapFlag = false;
4786	pCtx->eflags.Bits.u1TF = 0;
4787	}
4788
4789	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
4790	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
4791	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4792	PVM pVM = pVCpu->CTX_SUFF(pVM);
4793	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
4794	if (rc == VINF_EM_RAW_GUEST_TRAP)
4795	{
4796	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
4797	if (CPUMIsHyperDebugStateActive(pVCpu))
4798	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
4799
4800	/* Reflect the exception back to the guest. */
4801	hmR0SvmSetPendingXcptDB(pVCpu);
4802	rc = VINF_SUCCESS;
4803	}
4804
4805	/*
4806	* Update DR6.
4807	*/
4808	if (CPUMIsHyperDebugStateActive(pVCpu))
4809	{
4810	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
4811	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
4812	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4813	}
4814	else
4815	{
4816	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
4817	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
4818	}
4819
4820	return rc;
4821	}
4822
4823	/** @} */
4824

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 48201

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