HMSVMR0.cpp@ 53349

Last change on this file since 53349 was 53325, checked in by vboxsync, 10 years ago
VMM: Fix sign inconsistency in the RealUseTSC case.
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1	/* $Id: HMSVMR0.cpp 53325 2014-11-14 13:46:38Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <iprt/asm-amd64-x86.h>
23	#include <iprt/thread.h>
24
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include "HMSVMR0.h"
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33
34	#ifdef DEBUG_ramshankar
35	# define HMSVM_SYNC_FULL_GUEST_STATE
36	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
37	# define HMSVM_ALWAYS_TRAP_PF
38	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
39	#endif
40
41
42	/*******************************************************************************
43	* Defined Constants And Macros *
44	*******************************************************************************/
45	#ifdef VBOX_WITH_STATISTICS
46	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
47	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
48	if ((u64ExitCode) == SVM_EXIT_NPF) \
49	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
50	else \
51	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
52	} while (0)
53	#else
54	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
55	#endif
56
57	/** If we decide to use a function table approach this can be useful to
58	* switch to a "static DECLCALLBACK(int)". */
59	#define HMSVM_EXIT_DECL static int
60
61	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
62	*
63	* The CPU format of the segment attribute is described in X86DESCATTRBITS
64	* which is 16-bits (i.e. includes 4 bits of the segment limit).
65	*
66	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
67	* only the attribute bits and nothing else). Upper 4-bits are unused.
68	*
69	* @{ */
70	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
71	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
72	/** @} */
73
74	/** @name Macros for loading, storing segment registers to/from the VMCB.
75	* @{ */
76	#define HMSVM_LOAD_SEG_REG(REG, reg) \
77	do \
78	{ \
79	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
80	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
81	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
82	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
83	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
84	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
85	} while (0)
86
87	#define HMSVM_SAVE_SEG_REG(REG, reg) \
88	do \
89	{ \
90	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
91	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
92	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
93	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
94	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
95	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
96	} while (0)
97	/** @} */
98
99	/** Macro for checking and returning from the using function for
100	* \#VMEXIT intercepts that maybe caused during delivering of another
101	* event in the guest. */
102	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
103	do \
104	{ \
105	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
106	if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
107	return VINF_SUCCESS; \
108	else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
109	return rc; \
110	} while (0)
111
112	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
113	* instruction that exited. */
114	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
115	do { \
116	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
117	(a_rc) = VINF_EM_DBG_STEPPED; \
118	} while (0)
119
120	/** Assert that preemption is disabled or covered by thread-context hooks. */
121	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
122	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
123
124	/** Assert that we haven't migrated CPUs when thread-context hooks are not
125	* used. */
126	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
127	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
128	("Illegal migration! Entered on CPU %u Current %u\n", \
129	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
130
131	/** Exception bitmap mask for all contributory exceptions.
132	*
133	* Page fault is deliberately excluded here as it's conditional as to whether
134	* it's contributory or benign. Page faults are handled separately.
135	*/
136	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
137	\| RT_BIT(X86_XCPT_DE))
138
139	/** @name VMCB Clean Bits.
140	*
141	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
142	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
143	* memory.
144	*
145	* @{ */
146	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
147	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
148	/** I/O permission bitmap, MSR permission bitmap. */
149	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
150	/** ASID. */
151	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
152	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
153	V_INTR_VECTOR. */
154	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
155	/** Nested Paging: Nested CR3 (nCR3), PAT. */
156	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
157	/** Control registers (CR0, CR3, CR4, EFER). */
158	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
159	/** Debug registers (DR6, DR7). */
160	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
161	/** GDT, IDT limit and base. */
162	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
163	/** Segment register: CS, SS, DS, ES limit and base. */
164	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
165	/** CR2.*/
166	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
167	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
168	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
169	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
170	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
171	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
172	/** Mask of all valid VMCB Clean bits. */
173	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
174	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
175	\| HMSVM_VMCB_CLEAN_ASID \
176	\| HMSVM_VMCB_CLEAN_TPR \
177	\| HMSVM_VMCB_CLEAN_NP \
178	\| HMSVM_VMCB_CLEAN_CRX_EFER \
179	\| HMSVM_VMCB_CLEAN_DRX \
180	\| HMSVM_VMCB_CLEAN_DT \
181	\| HMSVM_VMCB_CLEAN_SEG \
182	\| HMSVM_VMCB_CLEAN_CR2 \
183	\| HMSVM_VMCB_CLEAN_LBR \
184	\| HMSVM_VMCB_CLEAN_AVIC)
185	/** @} */
186
187	/** @name SVM transient.
188	*
189	* A state structure for holding miscellaneous information across AMD-V
190	* VMRUN/#VMEXIT operation, restored after the transition.
191	*
192	* @{ */
193	typedef struct SVMTRANSIENT
194	{
195	/** The host's rflags/eflags. */
196	RTCCUINTREG uEflags;
197	#if HC_ARCH_BITS == 32
198	uint32_t u32Alignment0;
199	#endif
200
201	/** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
202	uint64_t u64ExitCode;
203	/** The guest's TPR value used for TPR shadowing. */
204	uint8_t u8GuestTpr;
205	/** Alignment. */
206	uint8_t abAlignment0[7];
207
208	/** Whether the guest FPU state was active at the time of #VMEXIT. */
209	bool fWasGuestFPUStateActive;
210	/** Whether the guest debug state was active at the time of #VMEXIT. */
211	bool fWasGuestDebugStateActive;
212	/** Whether the hyper debug state was active at the time of #VMEXIT. */
213	bool fWasHyperDebugStateActive;
214	/** Whether the TSC offset mode needs to be updated. */
215	bool fUpdateTscOffsetting;
216	/** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
217	bool fRestoreTscAuxMsr;
218	/** Whether the #VMEXIT was caused by a page-fault during delivery of a
219	* contributary exception or a page-fault. */
220	bool fVectoringDoublePF;
221	/** Whether the #VMEXIT was caused by a page-fault during delivery of an
222	* external interrupt or NMI. */
223	bool fVectoringPF;
224	} SVMTRANSIENT, *PSVMTRANSIENT;
225	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
226	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
227	/** @} */
228
229	/**
230	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
231	*/
232	typedef enum SVMMSREXITREAD
233	{
234	/** Reading this MSR causes a #VMEXIT. */
235	SVMMSREXIT_INTERCEPT_READ = 0xb,
236	/** Reading this MSR does not cause a #VMEXIT. */
237	SVMMSREXIT_PASSTHRU_READ
238	} SVMMSREXITREAD;
239
240	/**
241	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
242	*/
243	typedef enum SVMMSREXITWRITE
244	{
245	/** Writing to this MSR causes a #VMEXIT. */
246	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
247	/** Writing to this MSR does not cause a #VMEXIT. */
248	SVMMSREXIT_PASSTHRU_WRITE
249	} SVMMSREXITWRITE;
250
251	/**
252	* SVM #VMEXIT handler.
253	*
254	* @returns VBox status code.
255	* @param pVCpu Pointer to the VMCPU.
256	* @param pMixedCtx Pointer to the guest-CPU context.
257	* @param pSvmTransient Pointer to the SVM-transient structure.
258	*/
259	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
260
261	/*******************************************************************************
262	* Internal Functions *
263	*******************************************************************************/
264	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
265	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
266	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
267
268	/** @name #VMEXIT handlers.
269	* @{
270	*/
271	static FNSVMEXITHANDLER hmR0SvmExitIntr;
272	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
273	static FNSVMEXITHANDLER hmR0SvmExitInvd;
274	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
275	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
276	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
277	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
278	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
279	static FNSVMEXITHANDLER hmR0SvmExitHlt;
280	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
281	static FNSVMEXITHANDLER hmR0SvmExitMwait;
282	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
283	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
284	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
285	static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
286	static FNSVMEXITHANDLER hmR0SvmExitMsr;
287	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
288	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
289	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
290	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
291	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
292	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
293	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
294	static FNSVMEXITHANDLER hmR0SvmExitIret;
295	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
296	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
297	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
298	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
299	/** @} */
300
301	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
302
303	/*******************************************************************************
304	* Global Variables *
305	*******************************************************************************/
306	/** Ring-0 memory object for the IO bitmap. */
307	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
308	/** Physical address of the IO bitmap. */
309	RTHCPHYS g_HCPhysIOBitmap = 0;
310	/** Virtual address of the IO bitmap. */
311	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
312
313
314	/**
315	* Sets up and activates AMD-V on the current CPU.
316	*
317	* @returns VBox status code.
318	* @param pCpu Pointer to the CPU info struct.
319	* @param pVM Pointer to the VM (can be NULL after a resume!).
320	* @param pvCpuPage Pointer to the global CPU page.
321	* @param HCPhysCpuPage Physical address of the global CPU page.
322	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
323	* @param pvArg Unused on AMD-V.
324	*/
325	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
326	void *pvArg)
327	{
328	Assert(!fEnabledByHost);
329	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
330	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
331	Assert(pvCpuPage);
332	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
333
334	NOREF(pvArg);
335	NOREF(fEnabledByHost);
336
337	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
338	RTCCUINTREG uEflags = ASMIntDisableFlags();
339
340	/*
341	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
342	*/
343	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
344	if (u64HostEfer & MSR_K6_EFER_SVME)
345	{
346	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
347	if ( pVM
348	&& pVM->hm.s.svm.fIgnoreInUseError)
349	{
350	pCpu->fIgnoreAMDVInUseError = true;
351	}
352
353	if (!pCpu->fIgnoreAMDVInUseError)
354	{
355	ASMSetFlags(uEflags);
356	return VERR_SVM_IN_USE;
357	}
358	}
359
360	/* Turn on AMD-V in the EFER MSR. */
361	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
362
363	/* Write the physical page address where the CPU will store the host state while executing the VM. */
364	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
365
366	/* Restore interrupts. */
367	ASMSetFlags(uEflags);
368
369	/*
370	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
371	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
372	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
373	* to flush the TLB with before using a new ASID.
374	*/
375	pCpu->fFlushAsidBeforeUse = true;
376
377	/*
378	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
379	*/
380	++pCpu->cTlbFlushes;
381
382	return VINF_SUCCESS;
383	}
384
385
386	/**
387	* Deactivates AMD-V on the current CPU.
388	*
389	* @returns VBox status code.
390	* @param pCpu Pointer to the CPU info struct.
391	* @param pvCpuPage Pointer to the global CPU page.
392	* @param HCPhysCpuPage Physical address of the global CPU page.
393	*/
394	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
395	{
396	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
397	AssertReturn( HCPhysCpuPage
398	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
399	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
400	NOREF(pCpu);
401
402	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
403	RTCCUINTREG uEflags = ASMIntDisableFlags();
404
405	/* Turn off AMD-V in the EFER MSR. */
406	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
407	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
408
409	/* Invalidate host state physical address. */
410	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
411
412	/* Restore interrupts. */
413	ASMSetFlags(uEflags);
414
415	return VINF_SUCCESS;
416	}
417
418
419	/**
420	* Does global AMD-V initialization (called during module initialization).
421	*
422	* @returns VBox status code.
423	*/
424	VMMR0DECL(int) SVMR0GlobalInit(void)
425	{
426	/*
427	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
428	* once globally here instead of per-VM.
429	*/
430	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
431	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
432	if (RT_FAILURE(rc))
433	return rc;
434
435	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
436	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
437
438	/* Set all bits to intercept all IO accesses. */
439	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
440	return VINF_SUCCESS;
441	}
442
443
444	/**
445	* Does global AMD-V termination (called during module termination).
446	*/
447	VMMR0DECL(void) SVMR0GlobalTerm(void)
448	{
449	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
450	{
451	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
452	g_pvIOBitmap = NULL;
453	g_HCPhysIOBitmap = 0;
454	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
455	}
456	}
457
458
459	/**
460	* Frees any allocated per-VCPU structures for a VM.
461	*
462	* @param pVM Pointer to the VM.
463	*/
464	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
465	{
466	for (uint32_t i = 0; i < pVM->cCpus; i++)
467	{
468	PVMCPU pVCpu = &pVM->aCpus[i];
469	AssertPtr(pVCpu);
470
471	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
472	{
473	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
474	pVCpu->hm.s.svm.pvVmcbHost = 0;
475	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
476	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
477	}
478
479	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
480	{
481	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
482	pVCpu->hm.s.svm.pvVmcb = 0;
483	pVCpu->hm.s.svm.HCPhysVmcb = 0;
484	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
485	}
486
487	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
488	{
489	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
490	pVCpu->hm.s.svm.pvMsrBitmap = 0;
491	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
492	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
493	}
494	}
495	}
496
497
498	/**
499	* Does per-VM AMD-V initialization.
500	*
501	* @returns VBox status code.
502	* @param pVM Pointer to the VM.
503	*/
504	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
505	{
506	int rc = VERR_INTERNAL_ERROR_5;
507
508	/*
509	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
510	*/
511	uint32_t u32Family;
512	uint32_t u32Model;
513	uint32_t u32Stepping;
514	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
515	{
516	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
517	pVM->hm.s.svm.fAlwaysFlushTLB = true;
518	}
519
520	/*
521	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
522	*/
523	for (VMCPUID i = 0; i < pVM->cCpus; i++)
524	{
525	PVMCPU pVCpu = &pVM->aCpus[i];
526	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
527	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
528	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
529	}
530
531	for (VMCPUID i = 0; i < pVM->cCpus; i++)
532	{
533	PVMCPU pVCpu = &pVM->aCpus[i];
534
535	/*
536	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
537	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
538	*/
539	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
540	if (RT_FAILURE(rc))
541	goto failure_cleanup;
542
543	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
544	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
545	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
546	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
547
548	/*
549	* Allocate one page for the guest-state VMCB.
550	*/
551	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
552	if (RT_FAILURE(rc))
553	goto failure_cleanup;
554
555	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
556	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
557	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
558	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
559
560	/*
561	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
562	* SVM to not require one.
563	*/
564	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
565	if (RT_FAILURE(rc))
566	goto failure_cleanup;
567
568	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
569	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
570	/* Set all bits to intercept all MSR accesses (changed later on). */
571	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, UINT32_C(0xffffffff));
572	}
573
574	return VINF_SUCCESS;
575
576	failure_cleanup:
577	hmR0SvmFreeStructs(pVM);
578	return rc;
579	}
580
581
582	/**
583	* Does per-VM AMD-V termination.
584	*
585	* @returns VBox status code.
586	* @param pVM Pointer to the VM.
587	*/
588	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
589	{
590	hmR0SvmFreeStructs(pVM);
591	return VINF_SUCCESS;
592	}
593
594
595	/**
596	* Sets the permission bits for the specified MSR in the MSRPM.
597	*
598	* @param pVCpu Pointer to the VMCPU.
599	* @param uMsr The MSR for which the access permissions are being set.
600	* @param enmRead MSR read permissions.
601	* @param enmWrite MSR write permissions.
602	*/
603	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
604	{
605	unsigned ulBit;
606	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
607
608	/*
609	* Layout:
610	* Byte offset MSR range
611	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
612	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
613	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
614	* 0x1800 - 0x1fff Reserved
615	*/
616	if (uMsr <= 0x00001FFF)
617	{
618	/* Pentium-compatible MSRs. */
619	ulBit = uMsr * 2;
620	}
621	else if ( uMsr >= 0xC0000000
622	&& uMsr <= 0xC0001FFF)
623	{
624	/* AMD Sixth Generation x86 Processor MSRs. */
625	ulBit = (uMsr - 0xC0000000) * 2;
626	pbMsrBitmap += 0x800;
627	}
628	else if ( uMsr >= 0xC0010000
629	&& uMsr <= 0xC0011FFF)
630	{
631	/* AMD Seventh and Eighth Generation Processor MSRs. */
632	ulBit = (uMsr - 0xC0001000) * 2;
633	pbMsrBitmap += 0x1000;
634	}
635	else
636	{
637	AssertFailed();
638	return;
639	}
640
641	Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
642	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
643	ASMBitSet(pbMsrBitmap, ulBit);
644	else
645	ASMBitClear(pbMsrBitmap, ulBit);
646
647	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
648	ASMBitSet(pbMsrBitmap, ulBit + 1);
649	else
650	ASMBitClear(pbMsrBitmap, ulBit + 1);
651
652	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
653	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
654	}
655
656
657	/**
658	* Sets up AMD-V for the specified VM.
659	* This function is only called once per-VM during initalization.
660	*
661	* @returns VBox status code.
662	* @param pVM Pointer to the VM.
663	*/
664	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
665	{
666	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
667	AssertReturn(pVM, VERR_INVALID_PARAMETER);
668	Assert(pVM->hm.s.svm.fSupported);
669
670	for (VMCPUID i = 0; i < pVM->cCpus; i++)
671	{
672	PVMCPU pVCpu = &pVM->aCpus[i];
673	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
674
675	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
676
677	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
678	Assert(!pVCpu->hm.s.idxExitHistoryFree);
679	HMCPU_EXIT_HISTORY_RESET(pVCpu);
680
681	/* Trap exceptions unconditionally (debug purposes). */
682	#ifdef HMSVM_ALWAYS_TRAP_PF
683	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
684	#endif
685	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
686	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
687	pVmcb->ctrl.u32InterceptException \|= 0
688	\| RT_BIT(X86_XCPT_BP)
689	\| RT_BIT(X86_XCPT_DB)
690	\| RT_BIT(X86_XCPT_DE)
691	\| RT_BIT(X86_XCPT_NM)
692	\| RT_BIT(X86_XCPT_UD)
693	\| RT_BIT(X86_XCPT_NP)
694	\| RT_BIT(X86_XCPT_SS)
695	\| RT_BIT(X86_XCPT_GP)
696	\| RT_BIT(X86_XCPT_PF)
697	\| RT_BIT(X86_XCPT_MF)
698	;
699	#endif
700
701	/* Set up unconditional intercepts and conditions. */
702	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a #VMEXIT. */
703	\| SVM_CTRL1_INTERCEPT_NMI /* Non-maskable interrupts causes a #VMEXIT. */
704	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a #VMEXIT. */
705	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a #VMEXIT. */
706	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a #VMEXIT. */
707	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a #VMEXIT. */
708	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a #VMEXIT. */
709	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO #VMEXITs. */
710	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a #VMEXIT.*/
711	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */
712	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */
713	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
714
715	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a #VMEXIT. */
716	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a #VMEXIT. */
717	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a #VMEXIT. */
718	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a #VMEXIT. */
719	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a #VMEXIT. */
720	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a #VMEXIT. */
721	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a #VMEXIT. */
722	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a #VMEXIT. */
723	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a #VMEXIT. */
724	\| SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a #VMEXIT. */
725
726	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
727	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
728
729	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
730	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
731
732	/* Intercept all DRx reads and writes by default. Changed later on. */
733	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
734	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
735
736	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
737	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
738
739	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
740	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
741	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
742
743	/* Set IO and MSR bitmap permission bitmap physical addresses. */
744	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
745	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
746
747	/* No LBR virtualization. */
748	pVmcb->ctrl.u64LBRVirt = 0;
749
750	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
751	pVmcb->ctrl.u64VmcbCleanBits = 0;
752
753	/* The host ASID MBZ, for the guest start with 1. */
754	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
755
756	/*
757	* Setup the PAT MSR (applicable for Nested Paging only).
758	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
759	* so choose type 6 for all PAT slots.
760	*/
761	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
762
763	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
764	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
765
766	/* Without Nested Paging, we need additionally intercepts. */
767	if (!pVM->hm.s.fNestedPaging)
768	{
769	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
770	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
771	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
772
773	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
774	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
775	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
776
777	/* Page faults must be intercepted to implement shadow paging. */
778	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
779	}
780
781	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
782	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
783	#endif
784
785	/*
786	* The following MSRs are saved/restored automatically during the world-switch.
787	* Don't intercept guest read/write accesses to these MSRs.
788	*/
789	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
790	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
791	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
792	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
793	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
794	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
795	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
796	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
797	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
798	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
799	}
800
801	return VINF_SUCCESS;
802	}
803
804
805	/**
806	* Invalidates a guest page by guest virtual address.
807	*
808	* @returns VBox status code.
809	* @param pVM Pointer to the VM.
810	* @param pVCpu Pointer to the VMCPU.
811	* @param GCVirt Guest virtual address of the page to invalidate.
812	*/
813	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
814	{
815	AssertReturn(pVM, VERR_INVALID_PARAMETER);
816	Assert(pVM->hm.s.svm.fSupported);
817
818	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
819
820	/* Skip it if a TLB flush is already pending. */
821	if (!fFlushPending)
822	{
823	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
824
825	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
826	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
827
828	#if HC_ARCH_BITS == 32
829	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
830	if (CPUMIsGuestInLongMode(pVCpu))
831	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
832	else
833	#endif
834	{
835	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
836	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
837	}
838	}
839	return VINF_SUCCESS;
840	}
841
842
843	/**
844	* Flushes the appropriate tagged-TLB entries.
845	*
846	* @param pVM Pointer to the VM.
847	* @param pVCpu Pointer to the VMCPU.
848	*/
849	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
850	{
851	PVM pVM = pVCpu->CTX_SUFF(pVM);
852	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
853	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
854
855	/*
856	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
857	* This can happen both for start & resume due to long jumps back to ring-3.
858	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
859	* so we cannot reuse the ASIDs without flushing.
860	*/
861	bool fNewAsid = false;
862	Assert(pCpu->idCpu != NIL_RTCPUID);
863	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
864	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
865	{
866	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
867	pVCpu->hm.s.fForceTLBFlush = true;
868	fNewAsid = true;
869	}
870
871	/* Set TLB flush state as checked until we return from the world switch. */
872	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
873
874	/* Check for explicit TLB shootdowns. */
875	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
876	{
877	pVCpu->hm.s.fForceTLBFlush = true;
878	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
879	}
880
881	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
882
883	if (pVM->hm.s.svm.fAlwaysFlushTLB)
884	{
885	/*
886	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
887	*/
888	pCpu->uCurrentAsid = 1;
889	pVCpu->hm.s.uCurrentAsid = 1;
890	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
891	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
892
893	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
894	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
895	}
896	else if (pVCpu->hm.s.fForceTLBFlush)
897	{
898	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
899	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
900
901	if (fNewAsid)
902	{
903	++pCpu->uCurrentAsid;
904	bool fHitASIDLimit = false;
905	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
906	{
907	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
908	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
909	fHitASIDLimit = true;
910
911	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
912	{
913	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
914	pCpu->fFlushAsidBeforeUse = true;
915	}
916	else
917	{
918	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
919	pCpu->fFlushAsidBeforeUse = false;
920	}
921	}
922
923	if ( !fHitASIDLimit
924	&& pCpu->fFlushAsidBeforeUse)
925	{
926	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
927	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
928	else
929	{
930	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
931	pCpu->fFlushAsidBeforeUse = false;
932	}
933	}
934
935	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
936	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
937	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
938	}
939	else
940	{
941	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
942	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
943	else
944	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
945	}
946
947	pVCpu->hm.s.fForceTLBFlush = false;
948	}
949	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
950	* not be executed. See hmQueueInvlPage() where it is commented
951	* out. Support individual entry flushing someday. */
952	#if 0
953	else
954	{
955	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
956	{
957	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
958	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
959	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
960	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
961
962	pVCpu->hm.s.TlbShootdown.cPages = 0;
963	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
964	}
965	}
966	#endif
967
968
969	/* Update VMCB with the ASID. */
970	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
971	{
972	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
973	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
974	}
975
976	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
977	("vcpu idLastCpu=%x pcpu idCpu=%x\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
978	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
979	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
980	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
981	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
982	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
983	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
984
985	#ifdef VBOX_WITH_STATISTICS
986	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
987	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
988	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
989	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
990	{
991	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
992	}
993	else
994	{
995	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
996	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
997	}
998	#endif
999	}
1000
1001
1002	/** @name 64-bit guest on 32-bit host OS helper functions.
1003	*
1004	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1005	* mode (code segment, paging). These wrappers/helpers perform the necessary
1006	* bits for the 32->64 switcher.
1007	*
1008	* @{ */
1009	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1010	/**
1011	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1012	*
1013	* @returns VBox status code.
1014	* @param HCPhysVmcbHost Physical address of host VMCB.
1015	* @param HCPhysVmcb Physical address of the VMCB.
1016	* @param pCtx Pointer to the guest-CPU context.
1017	* @param pVM Pointer to the VM.
1018	* @param pVCpu Pointer to the VMCPU.
1019	*/
1020	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1021	{
1022	uint32_t aParam[4];
1023	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1024	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
1025	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1026	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
1027
1028	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
1029	}
1030
1031
1032	/**
1033	* Executes the specified VMRUN handler in 64-bit mode.
1034	*
1035	* @returns VBox status code.
1036	* @param pVM Pointer to the VM.
1037	* @param pVCpu Pointer to the VMCPU.
1038	* @param pCtx Pointer to the guest-CPU context.
1039	* @param enmOp The operation to perform.
1040	* @param cbParam Number of parameters.
1041	* @param paParam Array of 32-bit parameters.
1042	*/
1043	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
1044	uint32_t *paParam)
1045	{
1046	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1047	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1048
1049	/* Disable interrupts. */
1050	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1051
1052	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1053	RTCPUID idHostCpu = RTMpCpuId();
1054	CPUMR0SetLApic(pVCpu, idHostCpu);
1055	#endif
1056
1057	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1058	CPUMSetHyperEIP(pVCpu, enmOp);
1059	for (int i = (int)cbParam - 1; i >= 0; i--)
1060	CPUMPushHyper(pVCpu, paParam[i]);
1061
1062	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1063	/* Call the switcher. */
1064	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1065	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1066
1067	/* Restore interrupts. */
1068	ASMSetFlags(uOldEFlags);
1069	return rc;
1070	}
1071
1072	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1073	/** @} */
1074
1075
1076	/**
1077	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1078	* the corresponding VMCB Clean bit.
1079	*
1080	* @param pVmcb Pointer to the VM control block.
1081	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1082	*/
1083	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1084	{
1085	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1086	{
1087	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1088	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1089	}
1090	}
1091
1092
1093	/**
1094	* Removes an exception from the intercept-exception bitmap in the VMCB and
1095	* updates the corresponding VMCB Clean bit.
1096	*
1097	* @param pVmcb Pointer to the VM control block.
1098	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1099	*/
1100	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1101	{
1102	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1103	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1104	{
1105	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1106	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1107	}
1108	#endif
1109	}
1110
1111
1112	/**
1113	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1114	* Although the guest CR0 is a separate field in the VMCB we have to consider
1115	* the FPU state itself which is shared between the host and the guest.
1116	*
1117	* @returns VBox status code.
1118	* @param pVM Pointer to the VMCPU.
1119	* @param pVmcb Pointer to the VM control block.
1120	* @param pCtx Pointer to the guest-CPU context.
1121	*
1122	* @remarks No-long-jump zone!!!
1123	*/
1124	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1125	{
1126	/*
1127	* Guest CR0.
1128	*/
1129	PVM pVM = pVCpu->CTX_SUFF(pVM);
1130	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1131	{
1132	uint64_t u64GuestCR0 = pCtx->cr0;
1133
1134	/* Always enable caching. */
1135	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1136
1137	/*
1138	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1139	*/
1140	if (!pVM->hm.s.fNestedPaging)
1141	{
1142	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1143	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1144	}
1145
1146	/*
1147	* Guest FPU bits.
1148	*/
1149	bool fInterceptNM = false;
1150	bool fInterceptMF = false;
1151	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1152	if (CPUMIsGuestFPUStateActive(pVCpu))
1153	{
1154	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1155	if (!(pCtx->cr0 & X86_CR0_NE))
1156	{
1157	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1158	fInterceptMF = true;
1159	}
1160	}
1161	else
1162	{
1163	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1164	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1165	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1166	}
1167
1168	/*
1169	* Update the exception intercept bitmap.
1170	*/
1171	if (fInterceptNM)
1172	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1173	else
1174	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1175
1176	if (fInterceptMF)
1177	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1178	else
1179	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1180
1181	pVmcb->guest.u64CR0 = u64GuestCR0;
1182	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1183	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1184	}
1185	}
1186
1187
1188	/**
1189	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1190	*
1191	* @returns VBox status code.
1192	* @param pVCpu Pointer to the VMCPU.
1193	* @param pVmcb Pointer to the VM control block.
1194	* @param pCtx Pointer to the guest-CPU context.
1195	*
1196	* @remarks No-long-jump zone!!!
1197	*/
1198	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1199	{
1200	PVM pVM = pVCpu->CTX_SUFF(pVM);
1201
1202	/*
1203	* Guest CR2.
1204	*/
1205	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1206	{
1207	pVmcb->guest.u64CR2 = pCtx->cr2;
1208	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1209	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1210	}
1211
1212	/*
1213	* Guest CR3.
1214	*/
1215	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1216	{
1217	if (pVM->hm.s.fNestedPaging)
1218	{
1219	PGMMODE enmShwPagingMode;
1220	#if HC_ARCH_BITS == 32
1221	if (CPUMIsGuestInLongModeEx(pCtx))
1222	enmShwPagingMode = PGMMODE_AMD64_NX;
1223	else
1224	#endif
1225	enmShwPagingMode = PGMGetHostMode(pVM);
1226
1227	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1228	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1229	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1230	pVmcb->guest.u64CR3 = pCtx->cr3;
1231	}
1232	else
1233	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1234
1235	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1236	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1237	}
1238
1239	/*
1240	* Guest CR4.
1241	*/
1242	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1243	{
1244	uint64_t u64GuestCR4 = pCtx->cr4;
1245	if (!pVM->hm.s.fNestedPaging)
1246	{
1247	switch (pVCpu->hm.s.enmShadowMode)
1248	{
1249	case PGMMODE_REAL:
1250	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1251	AssertFailed();
1252	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1253
1254	case PGMMODE_32_BIT: /* 32-bit paging. */
1255	u64GuestCR4 &= ~X86_CR4_PAE;
1256	break;
1257
1258	case PGMMODE_PAE: /* PAE paging. */
1259	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1260	/** Must use PAE paging as we could use physical memory > 4 GB */
1261	u64GuestCR4 \|= X86_CR4_PAE;
1262	break;
1263
1264	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1265	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1266	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1267	break;
1268	#else
1269	AssertFailed();
1270	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1271	#endif
1272
1273	default: /* shut up gcc */
1274	AssertFailed();
1275	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1276	}
1277	}
1278
1279	pVmcb->guest.u64CR4 = u64GuestCR4;
1280	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1281	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1282	}
1283
1284	return VINF_SUCCESS;
1285	}
1286
1287
1288	/**
1289	* Loads the guest segment registers into the VMCB.
1290	*
1291	* @returns VBox status code.
1292	* @param pVCpu Pointer to the VMCPU.
1293	* @param pVmcb Pointer to the VM control block.
1294	* @param pCtx Pointer to the guest-CPU context.
1295	*
1296	* @remarks No-long-jump zone!!!
1297	*/
1298	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1299	{
1300	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1301	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1302	{
1303	HMSVM_LOAD_SEG_REG(CS, cs);
1304	HMSVM_LOAD_SEG_REG(SS, ss);
1305	HMSVM_LOAD_SEG_REG(DS, ds);
1306	HMSVM_LOAD_SEG_REG(ES, es);
1307	HMSVM_LOAD_SEG_REG(FS, fs);
1308	HMSVM_LOAD_SEG_REG(GS, gs);
1309
1310	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1311	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1312	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1313	}
1314
1315	/* Guest TR. */
1316	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1317	{
1318	HMSVM_LOAD_SEG_REG(TR, tr);
1319	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1320	}
1321
1322	/* Guest LDTR. */
1323	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1324	{
1325	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1326	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1327	}
1328
1329	/* Guest GDTR. */
1330	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1331	{
1332	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1333	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1334	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1335	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1336	}
1337
1338	/* Guest IDTR. */
1339	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1340	{
1341	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1342	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1343	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1344	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1345	}
1346	}
1347
1348
1349	/**
1350	* Loads the guest MSRs into the VMCB.
1351	*
1352	* @param pVCpu Pointer to the VMCPU.
1353	* @param pVmcb Pointer to the VM control block.
1354	* @param pCtx Pointer to the guest-CPU context.
1355	*
1356	* @remarks No-long-jump zone!!!
1357	*/
1358	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1359	{
1360	/* Guest Sysenter MSRs. */
1361	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1362	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1363	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1364
1365	/*
1366	* Guest EFER MSR.
1367	* AMD-V requires guest EFER.SVME to be set. Weird.
1368	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1369	*/
1370	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1371	{
1372	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1373	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1374	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1375	}
1376
1377	/* 64-bit MSRs. */
1378	if (CPUMIsGuestInLongModeEx(pCtx))
1379	{
1380	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1381	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1382	}
1383	else
1384	{
1385	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1386	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1387	{
1388	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1389	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1390	}
1391	}
1392
1393
1394	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1395	* be writable in 32-bit mode. Clarify with AMD spec. */
1396	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1397	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1398	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1399	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1400	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1401	}
1402
1403
1404	/**
1405	* Loads the guest state into the VMCB and programs the necessary intercepts
1406	* accordingly.
1407	*
1408	* @param pVCpu Pointer to the VMCPU.
1409	* @param pVmcb Pointer to the VM control block.
1410	* @param pCtx Pointer to the guest-CPU context.
1411	*
1412	* @remarks No-long-jump zone!!!
1413	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1414	*/
1415	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1416	{
1417	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1418	return;
1419	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1420	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1421
1422	bool fInterceptDB = false;
1423	bool fInterceptMovDRx = false;
1424
1425	/*
1426	* Anyone single stepping on the host side? If so, we'll have to use the
1427	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1428	* the VMM level like the VT-x implementations does.
1429	*/
1430	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1431	if (fStepping)
1432	{
1433	pVCpu->hm.s.fClearTrapFlag = true;
1434	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1435	fInterceptDB = true;
1436	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1437	}
1438
1439	if ( fStepping
1440	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1441	{
1442	/*
1443	* Use the combined guest and host DRx values found in the hypervisor
1444	* register set because the debugger has breakpoints active or someone
1445	* is single stepping on the host side.
1446	*
1447	* Note! DBGF expects a clean DR6 state before executing guest code.
1448	*/
1449	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1450	if ( CPUMIsGuestInLongModeEx(pCtx)
1451	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1452	{
1453	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1454	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1455	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1456	}
1457	else
1458	#endif
1459	if (!CPUMIsHyperDebugStateActive(pVCpu))
1460	{
1461	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1462	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1463	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1464	}
1465
1466	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1467	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1468	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1469	{
1470	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1471	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1472	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1473	pVCpu->hm.s.fUsingHyperDR7 = true;
1474	}
1475
1476	/** @todo If we cared, we could optimize to allow the guest to read registers
1477	* with the same values. */
1478	fInterceptDB = true;
1479	fInterceptMovDRx = true;
1480	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1481	}
1482	else
1483	{
1484	/*
1485	* Update DR6, DR7 with the guest values if necessary.
1486	*/
1487	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1488	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1489	{
1490	pVmcb->guest.u64DR7 = pCtx->dr[7];
1491	pVmcb->guest.u64DR6 = pCtx->dr[6];
1492	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1493	pVCpu->hm.s.fUsingHyperDR7 = false;
1494	}
1495
1496	/*
1497	* If the guest has enabled debug registers, we need to load them prior to
1498	* executing guest code so they'll trigger at the right time.
1499	*/
1500	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1501	{
1502	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1503	if ( CPUMIsGuestInLongModeEx(pCtx)
1504	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1505	{
1506	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1507	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1508	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1509	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1510	}
1511	else
1512	#endif
1513	if (!CPUMIsGuestDebugStateActive(pVCpu))
1514	{
1515	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1516	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1517	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1518	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1519	}
1520	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1521	}
1522	/*
1523	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1524	* intercept #DB as DR6 is updated in the VMCB.
1525	*/
1526	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1527	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1528	&& !CPUMIsGuestDebugStateActive(pVCpu))
1529	#else
1530	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1531	#endif
1532	{
1533	fInterceptMovDRx = true;
1534	}
1535	}
1536
1537	/*
1538	* Set up the intercepts.
1539	*/
1540	if (fInterceptDB)
1541	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1542	else
1543	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1544
1545	if (fInterceptMovDRx)
1546	{
1547	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1548	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1549	{
1550	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1551	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1552	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1553	}
1554	}
1555	else
1556	{
1557	if ( pVmcb->ctrl.u16InterceptRdDRx
1558	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1559	{
1560	pVmcb->ctrl.u16InterceptRdDRx = 0;
1561	pVmcb->ctrl.u16InterceptWrDRx = 0;
1562	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1563	}
1564	}
1565
1566	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1567	}
1568
1569
1570	/**
1571	* Loads the guest APIC state (currently just the TPR).
1572	*
1573	* @returns VBox status code.
1574	* @param pVCpu Pointer to the VMCPU.
1575	* @param pVmcb Pointer to the VM control block.
1576	* @param pCtx Pointer to the guest-CPU context.
1577	*/
1578	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1579	{
1580	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1581	return VINF_SUCCESS;
1582
1583	bool fPendingIntr;
1584	uint8_t u8Tpr;
1585	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1586	AssertRCReturn(rc, rc);
1587
1588	/* Assume that we need to trap all TPR accesses and thus need not check on
1589	every #VMEXIT if we should update the TPR. */
1590	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1591	pVCpu->hm.s.svm.fSyncVTpr = false;
1592
1593	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1594	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1595	{
1596	pCtx->msrLSTAR = u8Tpr;
1597
1598	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1599	if (fPendingIntr)
1600	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1601	else
1602	{
1603	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1604	pVCpu->hm.s.svm.fSyncVTpr = true;
1605	}
1606	}
1607	else
1608	{
1609	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1610	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1611
1612	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1613	if (fPendingIntr)
1614	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1615	else
1616	{
1617	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1618	pVCpu->hm.s.svm.fSyncVTpr = true;
1619	}
1620
1621	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1622	}
1623
1624	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1625	return rc;
1626	}
1627
1628
1629	/**
1630	* Sets up the appropriate function to run guest code.
1631	*
1632	* @returns VBox status code.
1633	* @param pVCpu Pointer to the VMCPU.
1634	* @param pCtx Pointer to the guest-CPU context.
1635	*
1636	* @remarks No-long-jump zone!!!
1637	*/
1638	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1639	{
1640	if (CPUMIsGuestInLongModeEx(pCtx))
1641	{
1642	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1643	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1644	#endif
1645	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1646	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1647	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1648	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1649	#else
1650	/* 64-bit host or hybrid host. */
1651	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1652	#endif
1653	}
1654	else
1655	{
1656	/* Guest is not in long mode, use the 32-bit handler. */
1657	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1658	}
1659	return VINF_SUCCESS;
1660	}
1661
1662
1663	/**
1664	* Enters the AMD-V session.
1665	*
1666	* @returns VBox status code.
1667	* @param pVM Pointer to the VM.
1668	* @param pVCpu Pointer to the VMCPU.
1669	* @param pCpu Pointer to the CPU info struct.
1670	*/
1671	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1672	{
1673	AssertPtr(pVM);
1674	AssertPtr(pVCpu);
1675	Assert(pVM->hm.s.svm.fSupported);
1676	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1677	NOREF(pVM); NOREF(pCpu);
1678
1679	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1680	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1681
1682	pVCpu->hm.s.fLeaveDone = false;
1683	return VINF_SUCCESS;
1684	}
1685
1686
1687	/**
1688	* Thread-context callback for AMD-V.
1689	*
1690	* @param enmEvent The thread-context event.
1691	* @param pVCpu Pointer to the VMCPU.
1692	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1693	* @thread EMT(pVCpu)
1694	*/
1695	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1696	{
1697	NOREF(fGlobalInit);
1698
1699	switch (enmEvent)
1700	{
1701	case RTTHREADCTXEVENT_PREEMPTING:
1702	{
1703	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1704	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1705	VMCPU_ASSERT_EMT(pVCpu);
1706
1707	PVM pVM = pVCpu->CTX_SUFF(pVM);
1708	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1709
1710	/* No longjmps (log-flush, locks) in this fragile context. */
1711	VMMRZCallRing3Disable(pVCpu);
1712
1713	if (!pVCpu->hm.s.fLeaveDone)
1714	{
1715	hmR0SvmLeave(pVM, pVCpu, pCtx);
1716	pVCpu->hm.s.fLeaveDone = true;
1717	}
1718
1719	/* Leave HM context, takes care of local init (term). */
1720	int rc = HMR0LeaveCpu(pVCpu);
1721	AssertRC(rc); NOREF(rc);
1722
1723	/* Restore longjmp state. */
1724	VMMRZCallRing3Enable(pVCpu);
1725	STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptPreempting);
1726	break;
1727	}
1728
1729	case RTTHREADCTXEVENT_RESUMED:
1730	{
1731	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1732	Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1733	VMCPU_ASSERT_EMT(pVCpu);
1734
1735	/* No longjmps (log-flush, locks) in this fragile context. */
1736	VMMRZCallRing3Disable(pVCpu);
1737
1738	/*
1739	* Initialize the bare minimum state required for HM. This takes care of
1740	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1741	*/
1742	int rc = HMR0EnterCpu(pVCpu);
1743	AssertRC(rc); NOREF(rc);
1744	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1745
1746	pVCpu->hm.s.fLeaveDone = false;
1747
1748	/* Restore longjmp state. */
1749	VMMRZCallRing3Enable(pVCpu);
1750	break;
1751	}
1752
1753	default:
1754	break;
1755	}
1756	}
1757
1758
1759	/**
1760	* Saves the host state.
1761	*
1762	* @returns VBox status code.
1763	* @param pVM Pointer to the VM.
1764	* @param pVCpu Pointer to the VMCPU.
1765	*
1766	* @remarks No-long-jump zone!!!
1767	*/
1768	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1769	{
1770	NOREF(pVM);
1771	NOREF(pVCpu);
1772	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1773	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1774	return VINF_SUCCESS;
1775	}
1776
1777
1778	/**
1779	* Loads the guest state into the VMCB. The CPU state will be loaded from these
1780	* fields on every successful VM-entry.
1781	*
1782	* Also sets up the appropriate VMRUN function to execute guest code based on
1783	* the guest CPU mode.
1784	*
1785	* @returns VBox status code.
1786	* @param pVM Pointer to the VM.
1787	* @param pVCpu Pointer to the VMCPU.
1788	* @param pCtx Pointer to the guest-CPU context.
1789	*
1790	* @remarks No-long-jump zone!!!
1791	*/
1792	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1793	{
1794	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1795	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1796
1797	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1798
1799	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1800	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1801
1802	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1803	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1804
1805	pVmcb->guest.u64RIP = pCtx->rip;
1806	pVmcb->guest.u64RSP = pCtx->rsp;
1807	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1808	pVmcb->guest.u64RAX = pCtx->rax;
1809
1810	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1811	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1812
1813	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1814	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1815
1816	/* Clear any unused and reserved bits. */
1817	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1818	\| HM_CHANGED_GUEST_RSP
1819	\| HM_CHANGED_GUEST_RFLAGS
1820	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1821	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1822	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1823	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1824	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1825	\| HM_CHANGED_SVM_RESERVED2
1826	\| HM_CHANGED_SVM_RESERVED3
1827	\| HM_CHANGED_SVM_RESERVED4);
1828
1829	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1830	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1831	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1832	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1833
1834	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1835	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1836	return rc;
1837	}
1838
1839
1840	/**
1841	* Loads the state shared between the host and guest into the
1842	* VMCB.
1843	*
1844	* @param pVCpu Pointer to the VMCPU.
1845	* @param pVmcb Pointer to the VM control block.
1846	* @param pCtx Pointer to the guest-CPU context.
1847	*
1848	* @remarks No-long-jump zone!!!
1849	*/
1850	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1851	{
1852	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1853	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1854
1855	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1856	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1857
1858	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1859	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1860
1861	/* Unused on AMD-V. */
1862	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
1863
1864	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1865	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1866	}
1867
1868
1869	/**
1870	* Saves the entire guest state from the VMCB into the
1871	* guest-CPU context. Currently there is no residual state left in the CPU that
1872	* is not updated in the VMCB.
1873	*
1874	* @returns VBox status code.
1875	* @param pVCpu Pointer to the VMCPU.
1876	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1877	* out-of-sync. Make sure to update the required fields
1878	* before using them.
1879	*/
1880	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1881	{
1882	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1883
1884	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1885
1886	pMixedCtx->rip = pVmcb->guest.u64RIP;
1887	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1888	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1889	pMixedCtx->rax = pVmcb->guest.u64RAX;
1890
1891	/*
1892	* Guest interrupt shadow.
1893	*/
1894	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1895	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1896	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1897	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1898
1899	/*
1900	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1901	*/
1902	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1903
1904	/*
1905	* Guest MSRs.
1906	*/
1907	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1908	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1909	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1910	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1911	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1912	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1913	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1914	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1915
1916	/*
1917	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1918	*/
1919	HMSVM_SAVE_SEG_REG(CS, cs);
1920	HMSVM_SAVE_SEG_REG(SS, ss);
1921	HMSVM_SAVE_SEG_REG(DS, ds);
1922	HMSVM_SAVE_SEG_REG(ES, es);
1923	HMSVM_SAVE_SEG_REG(FS, fs);
1924	HMSVM_SAVE_SEG_REG(GS, gs);
1925
1926	/*
1927	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1928	* register (yet).
1929	*/
1930	/** @todo SELM might need to be fixed as it too should not care about the
1931	* granularity bit. See @bugref{6785}. */
1932	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1933	&& pMixedCtx->cs.Attr.n.u1Present
1934	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1935	{
1936	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1937	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1938	}
1939
1940	#ifdef VBOX_STRICT
1941	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1942	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1943	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1944	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1945	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1946	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1947	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1948
1949	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1950	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1951	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1952	HMSVM_ASSERT_SEG_GRANULARITY(es);
1953	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1954	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1955
1956	# undef HMSVM_ASSERT_SEL_GRANULARITY
1957	#endif
1958
1959	/*
1960	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1961	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1962	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1963	* See AMD spec. 15.5.1 "Basic operation".
1964	*/
1965	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1966	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1967
1968	/*
1969	* Guest TR.
1970	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
1971	* between Intel and AMD. See @bugref{6208} comment #39.
1972	*/
1973	HMSVM_SAVE_SEG_REG(TR, tr);
1974	if (CPUMIsGuestInLongModeEx(pMixedCtx))
1975	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1976
1977	/*
1978	* Guest Descriptor-Table registers.
1979	*/
1980	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1981	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1982	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1983
1984	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1985	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1986
1987	/*
1988	* Guest Debug registers.
1989	*/
1990	if (!pVCpu->hm.s.fUsingHyperDR7)
1991	{
1992	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1993	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1994	}
1995	else
1996	{
1997	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
1998	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
1999	}
2000
2001	/*
2002	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2003	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2004	*/
2005	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
2006	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2007	{
2008	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2009	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2010	}
2011	}
2012
2013
2014	/**
2015	* Does the necessary state syncing before returning to ring-3 for any reason
2016	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2017	*
2018	* @param pVM Pointer to the VM.
2019	* @param pVCpu Pointer to the VMCPU.
2020	* @param pMixedCtx Pointer to the guest-CPU context.
2021	*
2022	* @remarks No-long-jmp zone!!!
2023	*/
2024	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2025	{
2026	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2027	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2028	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2029
2030	/*
2031	* !!! IMPORTANT !!!
2032	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2033	*/
2034
2035	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2036	if (CPUMIsGuestFPUStateActive(pVCpu))
2037	{
2038	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
2039	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2040	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2041	}
2042
2043	/*
2044	* Restore host debug registers if necessary and resync on next R0 reentry.
2045	*/
2046	#ifdef VBOX_STRICT
2047	if (CPUMIsHyperDebugStateActive(pVCpu))
2048	{
2049	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2050	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2051	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2052	}
2053	#endif
2054	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2055	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2056
2057	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2058	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2059
2060	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2061	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2062	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2063	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2064	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2065
2066	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2067	}
2068
2069
2070	/**
2071	* Leaves the AMD-V session.
2072	*
2073	* @returns VBox status code.
2074	* @param pVM Pointer to the VM.
2075	* @param pVCpu Pointer to the VMCPU.
2076	* @param pCtx Pointer to the guest-CPU context.
2077	*/
2078	static int hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2079	{
2080	HM_DISABLE_PREEMPT_IF_NEEDED();
2081	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2082	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2083
2084	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2085	and done this from the SVMR0ThreadCtxCallback(). */
2086	if (!pVCpu->hm.s.fLeaveDone)
2087	{
2088	hmR0SvmLeave(pVM, pVCpu, pCtx);
2089	pVCpu->hm.s.fLeaveDone = true;
2090	}
2091
2092	/*
2093	* !!! IMPORTANT !!!
2094	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2095	*/
2096
2097	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2098	if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
2099	VMMR0ThreadCtxHooksDeregister(pVCpu);
2100
2101	/* Leave HM context. This takes care of local init (term). */
2102	int rc = HMR0LeaveCpu(pVCpu);
2103
2104	HM_RESTORE_PREEMPT_IF_NEEDED();
2105	return rc;
2106	}
2107
2108
2109	/**
2110	* Does the necessary state syncing before doing a longjmp to ring-3.
2111	*
2112	* @returns VBox status code.
2113	* @param pVM Pointer to the VM.
2114	* @param pVCpu Pointer to the VMCPU.
2115	* @param pCtx Pointer to the guest-CPU context.
2116	*
2117	* @remarks No-long-jmp zone!!!
2118	*/
2119	static int hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2120	{
2121	return hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2122	}
2123
2124
2125	/**
2126	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2127	* any remaining host state) before we longjump to ring-3 and possibly get
2128	* preempted.
2129	*
2130	* @param pVCpu Pointer to the VMCPU.
2131	* @param enmOperation The operation causing the ring-3 longjump.
2132	* @param pvUser The user argument (pointer to the possibly
2133	* out-of-date guest-CPU context).
2134	*/
2135	DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2136	{
2137	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2138	{
2139	/*
2140	* !!! IMPORTANT !!!
2141	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2142	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2143	*/
2144	VMMRZCallRing3RemoveNotification(pVCpu);
2145	VMMRZCallRing3Disable(pVCpu);
2146	HM_DISABLE_PREEMPT_IF_NEEDED();
2147
2148	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2149	if (CPUMIsGuestFPUStateActive(pVCpu))
2150	CPUMR0SaveGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2151
2152	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2153	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2154
2155	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2156	if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
2157	VMMR0ThreadCtxHooksDeregister(pVCpu);
2158
2159	/* Leave HM context. This takes care of local init (term). */
2160	HMR0LeaveCpu(pVCpu);
2161
2162	HM_RESTORE_PREEMPT_IF_NEEDED();
2163	return VINF_SUCCESS;
2164	}
2165
2166	Assert(pVCpu);
2167	Assert(pvUser);
2168	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2169	HMSVM_ASSERT_PREEMPT_SAFE();
2170
2171	VMMRZCallRing3Disable(pVCpu);
2172	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2173
2174	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2175	int rc = hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2176	AssertRCReturn(rc, rc);
2177
2178	VMMRZCallRing3Enable(pVCpu);
2179	return VINF_SUCCESS;
2180	}
2181
2182
2183	/**
2184	* Take necessary actions before going back to ring-3.
2185	*
2186	* An action requires us to go back to ring-3. This function does the necessary
2187	* steps before we can safely return to ring-3. This is not the same as longjmps
2188	* to ring-3, this is voluntary.
2189	*
2190	* @param pVM Pointer to the VM.
2191	* @param pVCpu Pointer to the VMCPU.
2192	* @param pCtx Pointer to the guest-CPU context.
2193	* @param rcExit The reason for exiting to ring-3. Can be
2194	* VINF_VMM_UNKNOWN_RING3_CALL.
2195	*/
2196	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2197	{
2198	Assert(pVM);
2199	Assert(pVCpu);
2200	Assert(pCtx);
2201	HMSVM_ASSERT_PREEMPT_SAFE();
2202
2203	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2204	VMMRZCallRing3Disable(pVCpu);
2205	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2206
2207	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2208	if (pVCpu->hm.s.Event.fPending)
2209	{
2210	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2211	Assert(!pVCpu->hm.s.Event.fPending);
2212	}
2213
2214	/* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2215	and if we're injecting an event we should have a TRPM trap pending. */
2216	Assert(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu));
2217	Assert(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu));
2218
2219	/* Sync. the necessary state for going back to ring-3. */
2220	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2221	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2222
2223	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2224	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2225	\| CPUM_CHANGED_LDTR
2226	\| CPUM_CHANGED_GDTR
2227	\| CPUM_CHANGED_IDTR
2228	\| CPUM_CHANGED_TR
2229	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2230	if ( pVM->hm.s.fNestedPaging
2231	&& CPUMIsGuestPagingEnabledEx(pCtx))
2232	{
2233	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2234	}
2235
2236	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2237	if (rcExit != VINF_EM_RAW_INTERRUPT)
2238	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2239
2240	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2241
2242	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2243	VMMRZCallRing3RemoveNotification(pVCpu);
2244	VMMRZCallRing3Enable(pVCpu);
2245	}
2246
2247
2248	/**
2249	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2250	* intercepts.
2251	*
2252	* @param pVCpu Pointer to the VMCPU.
2253	*
2254	* @remarks No-long-jump zone!!!
2255	*/
2256	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
2257	{
2258	bool fParavirtTsc = false;
2259	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2260	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc))
2261	{
2262	uint64_t u64CurTSC = ASMReadTSC();
2263	uint64_t u64LastTick = TMCpuTickGetLastSeen(pVCpu);
2264
2265	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
2266	{
2267	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2268	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2269	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2270	}
2271	else
2272	{
2273	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2274	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2275	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
2276	}
2277	}
2278	else
2279	{
2280	Assert(!fParavirtTsc);
2281	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2282	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2283	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2284	}
2285
2286	if (fParavirtTsc)
2287	{
2288	int rc = GIMR0UpdateParavirtTsc(pVCpu->CTX_SUFF(pVM), 0 /* u64Offset */);
2289	AssertRC(rc);
2290	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2291	}
2292
2293	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2294	}
2295
2296
2297	/**
2298	* Sets an event as a pending event to be injected into the guest.
2299	*
2300	* @param pVCpu Pointer to the VMCPU.
2301	* @param pEvent Pointer to the SVM event.
2302	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2303	* page-fault.
2304	*
2305	* @remarks Statistics counter assumes this is a guest event being reflected to
2306	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2307	*/
2308	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2309	{
2310	Assert(!pVCpu->hm.s.Event.fPending);
2311	Assert(pEvent->n.u1Valid);
2312
2313	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2314	pVCpu->hm.s.Event.fPending = true;
2315	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2316
2317	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2318	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2319
2320	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2321	}
2322
2323
2324	/**
2325	* Injects an event into the guest upon VMRUN by updating the relevant field
2326	* in the VMCB.
2327	*
2328	* @param pVCpu Pointer to the VMCPU.
2329	* @param pVmcb Pointer to the guest VM control block.
2330	* @param pCtx Pointer to the guest-CPU context.
2331	* @param pEvent Pointer to the event.
2332	*
2333	* @remarks No-long-jump zone!!!
2334	* @remarks Requires CR0!
2335	*/
2336	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2337	{
2338	NOREF(pVCpu); NOREF(pCtx);
2339
2340	pVmcb->ctrl.EventInject.u = pEvent->u;
2341	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2342
2343	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2344	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2345	}
2346
2347
2348
2349	/**
2350	* Converts any TRPM trap into a pending HM event. This is typically used when
2351	* entering from ring-3 (not longjmp returns).
2352	*
2353	* @param pVCpu Pointer to the VMCPU.
2354	*/
2355	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2356	{
2357	Assert(TRPMHasTrap(pVCpu));
2358	Assert(!pVCpu->hm.s.Event.fPending);
2359
2360	uint8_t uVector;
2361	TRPMEVENT enmTrpmEvent;
2362	RTGCUINT uErrCode;
2363	RTGCUINTPTR GCPtrFaultAddress;
2364	uint8_t cbInstr;
2365
2366	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2367	AssertRC(rc);
2368
2369	SVMEVENT Event;
2370	Event.u = 0;
2371	Event.n.u1Valid = 1;
2372	Event.n.u8Vector = uVector;
2373
2374	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2375	if (enmTrpmEvent == TRPM_TRAP)
2376	{
2377	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2378	switch (uVector)
2379	{
2380	case X86_XCPT_NMI:
2381	{
2382	Event.n.u3Type = SVM_EVENT_NMI;
2383	break;
2384	}
2385
2386	case X86_XCPT_PF:
2387	case X86_XCPT_DF:
2388	case X86_XCPT_TS:
2389	case X86_XCPT_NP:
2390	case X86_XCPT_SS:
2391	case X86_XCPT_GP:
2392	case X86_XCPT_AC:
2393	{
2394	Event.n.u1ErrorCodeValid = 1;
2395	Event.n.u32ErrorCode = uErrCode;
2396	break;
2397	}
2398	}
2399	}
2400	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2401	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2402	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2403	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2404	else
2405	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2406
2407	rc = TRPMResetTrap(pVCpu);
2408	AssertRC(rc);
2409
2410	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2411	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2412
2413	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2414	STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2415	}
2416
2417
2418	/**
2419	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2420	* AMD-V to execute any instruction.
2421	*
2422	* @param pvCpu Pointer to the VMCPU.
2423	*/
2424	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2425	{
2426	Assert(pVCpu->hm.s.Event.fPending);
2427	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2428
2429	SVMEVENT Event;
2430	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2431
2432	uint8_t uVector = Event.n.u8Vector;
2433	uint8_t uVectorType = Event.n.u3Type;
2434
2435	TRPMEVENT enmTrapType;
2436	switch (uVectorType)
2437	{
2438	case SVM_EVENT_EXTERNAL_IRQ:
2439	enmTrapType = TRPM_HARDWARE_INT;
2440	break;
2441	case SVM_EVENT_SOFTWARE_INT:
2442	enmTrapType = TRPM_SOFTWARE_INT;
2443	break;
2444	case SVM_EVENT_EXCEPTION:
2445	case SVM_EVENT_NMI:
2446	enmTrapType = TRPM_TRAP;
2447	break;
2448	default:
2449	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2450	enmTrapType = TRPM_32BIT_HACK;
2451	break;
2452	}
2453
2454	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2455
2456	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2457	AssertRC(rc);
2458
2459	if (Event.n.u1ErrorCodeValid)
2460	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2461
2462	if ( uVectorType == SVM_EVENT_EXCEPTION
2463	&& uVector == X86_XCPT_PF)
2464	{
2465	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2466	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2467	}
2468	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2469	{
2470	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2471	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2472	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2473	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2474	}
2475	pVCpu->hm.s.Event.fPending = false;
2476	}
2477
2478
2479	/**
2480	* Gets the guest's interrupt-shadow.
2481	*
2482	* @returns The guest's interrupt-shadow.
2483	* @param pVCpu Pointer to the VMCPU.
2484	* @param pCtx Pointer to the guest-CPU context.
2485	*
2486	* @remarks No-long-jump zone!!!
2487	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2488	*/
2489	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2490	{
2491	/*
2492	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2493	* inhibit interrupts or clear any existing interrupt-inhibition.
2494	*/
2495	uint32_t uIntrState = 0;
2496	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2497	{
2498	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2499	{
2500	/*
2501	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2502	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2503	*/
2504	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2505	}
2506	else
2507	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2508	}
2509	return uIntrState;
2510	}
2511
2512
2513	/**
2514	* Sets the virtual interrupt intercept control in the VMCB which
2515	* instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2516	* receive interrupts.
2517	*
2518	* @param pVmcb Pointer to the VM control block.
2519	*/
2520	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2521	{
2522	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2523	{
2524	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2525	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2526	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2527	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2528
2529	Log4(("Setting VINTR intercept\n"));
2530	}
2531	}
2532
2533
2534	/**
2535	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2536	* #VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
2537	* virtual NMIs.
2538	*
2539	* @param pVmcb Pointer to the VM control block.
2540	*/
2541	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
2542	{
2543	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET))
2544	{
2545	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_IRET;
2546	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2547
2548	Log4(("Setting IRET intercept\n"));
2549	}
2550	}
2551
2552
2553	/**
2554	* Clears the IRET intercept control in the VMCB.
2555	*
2556	* @param pVmcb Pointer to the VM control block.
2557	*/
2558	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
2559	{
2560	if (pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET)
2561	{
2562	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_IRET;
2563	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2564
2565	Log4(("Clearing IRET intercept\n"));
2566	}
2567	}
2568
2569
2570	/**
2571	* Evaluates the event to be delivered to the guest and sets it as the pending
2572	* event.
2573	*
2574	* @param pVCpu Pointer to the VMCPU.
2575	* @param pCtx Pointer to the guest-CPU context.
2576	*/
2577	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2578	{
2579	Assert(!pVCpu->hm.s.Event.fPending);
2580	Log4Func(("\n"));
2581
2582	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2583	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2584	bool const fBlockNmi = RT_BOOL(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
2585	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2586
2587	SVMEVENT Event;
2588	Event.u = 0;
2589	/** @todo SMI. SMIs take priority over NMIs. */
2590	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2591	{
2592	if (fBlockNmi)
2593	hmR0SvmSetIretIntercept(pVmcb);
2594	else if (fIntShadow)
2595	hmR0SvmSetVirtIntrIntercept(pVmcb);
2596	else
2597	{
2598	Log4(("Pending NMI\n"));
2599
2600	Event.n.u1Valid = 1;
2601	Event.n.u8Vector = X86_XCPT_NMI;
2602	Event.n.u3Type = SVM_EVENT_NMI;
2603
2604	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2605	hmR0SvmSetIretIntercept(pVmcb);
2606	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2607	}
2608	}
2609	else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)))
2610	{
2611	/*
2612	* Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
2613	* the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
2614	* evaluated here and not set as pending, solely based on the force-flags.
2615	*/
2616	if ( !fBlockInt
2617	&& !fIntShadow)
2618	{
2619	uint8_t u8Interrupt;
2620	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2621	if (RT_SUCCESS(rc))
2622	{
2623	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2624
2625	Event.n.u1Valid = 1;
2626	Event.n.u8Vector = u8Interrupt;
2627	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2628
2629	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2630	}
2631	else
2632	{
2633	/** @todo Does this actually happen? If not turn it into an assertion. */
2634	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
2635	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2636	}
2637	}
2638	else
2639	hmR0SvmSetVirtIntrIntercept(pVmcb);
2640	}
2641	}
2642
2643
2644	/**
2645	* Injects any pending events into the guest if the guest is in a state to
2646	* receive them.
2647	*
2648	* @param pVCpu Pointer to the VMCPU.
2649	* @param pCtx Pointer to the guest-CPU context.
2650	*/
2651	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2652	{
2653	Assert(!TRPMHasTrap(pVCpu));
2654	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2655	Log4Func(("\n"));
2656
2657	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2658	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2659	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2660
2661	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2662	{
2663	SVMEVENT Event;
2664	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2665	Assert(Event.n.u1Valid);
2666	#ifdef VBOX_STRICT
2667	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2668	{
2669	Assert(!fBlockInt);
2670	Assert(!fIntShadow);
2671	}
2672	else if (Event.n.u3Type == SVM_EVENT_NMI)
2673	Assert(!fIntShadow);
2674	#endif
2675
2676	Log4(("Injecting pending HM event.\n"));
2677	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2678	pVCpu->hm.s.Event.fPending = false;
2679
2680	#ifdef VBOX_WITH_STATISTICS
2681	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2682	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2683	else
2684	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2685	#endif
2686	}
2687
2688	/* Update the guest interrupt shadow in the VMCB. */
2689	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2690	NOREF(fBlockInt);
2691	}
2692
2693
2694	/**
2695	* Reports world-switch error and dumps some useful debug info.
2696	*
2697	* @param pVM Pointer to the VM.
2698	* @param pVCpu Pointer to the VMCPU.
2699	* @param rcVMRun The return code from VMRUN (or
2700	* VERR_SVM_INVALID_GUEST_STATE for invalid
2701	* guest-state).
2702	* @param pCtx Pointer to the guest-CPU context.
2703	*/
2704	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2705	{
2706	NOREF(pCtx);
2707	HMSVM_ASSERT_PREEMPT_SAFE();
2708	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2709
2710	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2711	{
2712	HMDumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
2713	#ifdef VBOX_STRICT
2714	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2715	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2716	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2717	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2718	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2719	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2720	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2721	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2722	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2723	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2724	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2725
2726	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2727	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2728	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2729
2730	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2731	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2732	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2733	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2734	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2735	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2736	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2737	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2738	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2739	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2740
2741	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2742	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2743	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2744	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2745	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2746	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2747	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2748	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2749	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2750	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2751	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2752	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2753	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2754	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2755	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2756	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2757	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2758
2759	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2760	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2761
2762	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2763	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2764	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2765	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2766	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2767	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2768	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2769	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2770	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2771	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2772	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2773	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2774	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2775	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2776	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2777	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2778	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2779	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2780	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2781	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2782
2783	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2784	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2785
2786	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2787	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2788	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2789	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2790
2791	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2792	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2793
2794	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2795	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2796	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2797	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2798
2799	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2800	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2801	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2802	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2803	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2804	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2805	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2806
2807	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2808	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2809	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2810	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2811
2812	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2813	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2814	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2815
2816	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2817	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2818	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2819	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2820	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2821	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2822	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2823	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2824	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2825	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2826	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2827	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2828	#else
2829	NOREF(pVmcb);
2830	#endif /* VBOX_STRICT */
2831	}
2832	else
2833	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2834	}
2835
2836
2837	/**
2838	* Check per-VM and per-VCPU force flag actions that require us to go back to
2839	* ring-3 for one reason or another.
2840	*
2841	* @returns VBox status code (information status code included).
2842	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2843	* ring-3.
2844	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2845	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2846	* interrupts)
2847	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2848	* all EMTs to be in ring-3.
2849	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2850	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2851	* to the EM loop.
2852	*
2853	* @param pVM Pointer to the VM.
2854	* @param pVCpu Pointer to the VMCPU.
2855	* @param pCtx Pointer to the guest-CPU context.
2856	*/
2857	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2858	{
2859	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2860
2861	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2862	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2863	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2864
2865	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2866	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2867	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2868	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2869	{
2870	/* Pending PGM C3 sync. */
2871	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2872	{
2873	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2874	if (rc != VINF_SUCCESS)
2875	{
2876	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2877	return rc;
2878	}
2879	}
2880
2881	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2882	/* -XXX- what was that about single stepping? */
2883	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2884	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2885	{
2886	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2887	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2888	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2889	return rc;
2890	}
2891
2892	/* Pending VM request packets, such as hardware interrupts. */
2893	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2894	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2895	{
2896	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2897	return VINF_EM_PENDING_REQUEST;
2898	}
2899
2900	/* Pending PGM pool flushes. */
2901	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2902	{
2903	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2904	return VINF_PGM_POOL_FLUSH_PENDING;
2905	}
2906
2907	/* Pending DMA requests. */
2908	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2909	{
2910	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2911	return VINF_EM_RAW_TO_R3;
2912	}
2913	}
2914
2915	return VINF_SUCCESS;
2916	}
2917
2918
2919	/**
2920	* Does the preparations before executing guest code in AMD-V.
2921	*
2922	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2923	* recompiler. We must be cautious what we do here regarding committing
2924	* guest-state information into the the VMCB assuming we assuredly execute the
2925	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2926	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2927	* that the recompiler can (and should) use them when it resumes guest
2928	* execution. Otherwise such operations must be done when we can no longer
2929	* exit to ring-3.
2930	*
2931	* @returns VBox status code (informational status codes included).
2932	* @retval VINF_SUCCESS if we can proceed with running the guest.
2933	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2934	*
2935	* @param pVM Pointer to the VM.
2936	* @param pVCpu Pointer to the VMCPU.
2937	* @param pCtx Pointer to the guest-CPU context.
2938	* @param pSvmTransient Pointer to the SVM transient structure.
2939	*/
2940	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2941	{
2942	HMSVM_ASSERT_PREEMPT_SAFE();
2943
2944	/* Check force flag actions that might require us to go back to ring-3. */
2945	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2946	if (rc != VINF_SUCCESS)
2947	return rc;
2948
2949	if (TRPMHasTrap(pVCpu))
2950	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2951	else if (!pVCpu->hm.s.Event.fPending)
2952	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2953
2954	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2955	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2956	#endif
2957
2958	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
2959	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2960	AssertRCReturn(rc, rc);
2961	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2962
2963	/*
2964	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2965	* so we can update it on the way back if the guest changed the TPR.
2966	*/
2967	if (pVCpu->hm.s.svm.fSyncVTpr)
2968	{
2969	if (pVM->hm.s.fTPRPatchingActive)
2970	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2971	else
2972	{
2973	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2974	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2975	}
2976	}
2977
2978	/*
2979	* No longjmps to ring-3 from this point on!!!
2980	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2981	* This also disables flushing of the R0-logger instance (if any).
2982	*/
2983	VMMRZCallRing3Disable(pVCpu);
2984
2985	/*
2986	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
2987	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
2988	*
2989	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
2990	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
2991	*
2992	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
2993	* executing guest code.
2994	*/
2995	pSvmTransient->uEflags = ASMIntDisableFlags();
2996	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2997	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2998	{
2999	ASMSetFlags(pSvmTransient->uEflags);
3000	VMMRZCallRing3Enable(pVCpu);
3001	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3002	return VINF_EM_RAW_TO_R3;
3003	}
3004	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3005	{
3006	ASMSetFlags(pSvmTransient->uEflags);
3007	VMMRZCallRing3Enable(pVCpu);
3008	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3009	return VINF_EM_RAW_INTERRUPT;
3010	}
3011
3012	/*
3013	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3014	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3015	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3016	*
3017	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3018	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3019	*/
3020	if (pVCpu->hm.s.Event.fPending)
3021	{
3022	SVMEVENT Event;
3023	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3024	if ( Event.n.u1Valid
3025	&& Event.n.u3Type == SVM_EVENT_NMI
3026	&& Event.n.u8Vector == X86_XCPT_NMI
3027	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3028	{
3029	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3030	}
3031	}
3032
3033	return VINF_SUCCESS;
3034	}
3035
3036
3037	/**
3038	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3039	* means there is no backing out to ring-3 or anywhere else at this
3040	* point.
3041	*
3042	* @param pVM Pointer to the VM.
3043	* @param pVCpu Pointer to the VMCPU.
3044	* @param pCtx Pointer to the guest-CPU context.
3045	* @param pSvmTransient Pointer to the SVM transient structure.
3046	*
3047	* @remarks Called with preemption disabled.
3048	* @remarks No-long-jump zone!!!
3049	*/
3050	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3051	{
3052	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3053	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3054	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3055
3056	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3057	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3058
3059	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
3060
3061	if ( pVCpu->hm.s.fUseGuestFpu
3062	&& !CPUMIsGuestFPUStateActive(pVCpu))
3063	{
3064	CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
3065	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3066	}
3067
3068	/* Load the state shared between host and guest (FPU, debug). */
3069	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3070	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3071	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3072	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3073	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3074
3075	/* Setup TSC offsetting. */
3076	RTCPUID idCurrentCpu = HMR0GetCurrentCpu()->idCpu;
3077	if ( pSvmTransient->fUpdateTscOffsetting
3078	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3079	{
3080	hmR0SvmUpdateTscOffsetting(pVCpu);
3081	pSvmTransient->fUpdateTscOffsetting = false;
3082	}
3083
3084	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3085	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3086	pVmcb->ctrl.u64VmcbCleanBits = 0;
3087
3088	/* Store status of the shared guest-host state at the time of VMRUN. */
3089	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3090	if (CPUMIsGuestInLongModeEx(pCtx))
3091	{
3092	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3093	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3094	}
3095	else
3096	#endif
3097	{
3098	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3099	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3100	}
3101	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3102
3103	/* Flush the appropriate tagged-TLB entries. */
3104	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
3105	hmR0SvmFlushTaggedTlb(pVCpu);
3106	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3107
3108	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3109
3110	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3111	to start executing. */
3112
3113	/*
3114	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3115	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3116	*
3117	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3118	*/
3119	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3120	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
3121	{
3122	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3123	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3124	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3125	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3126	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3127	pSvmTransient->fRestoreTscAuxMsr = true;
3128	}
3129	else
3130	{
3131	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3132	pSvmTransient->fRestoreTscAuxMsr = false;
3133	}
3134
3135	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
3136	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
3137	pVmcb->ctrl.u64VmcbCleanBits = 0;
3138	}
3139
3140
3141	/**
3142	* Wrapper for running the guest code in AMD-V.
3143	*
3144	* @returns VBox strict status code.
3145	* @param pVM Pointer to the VM.
3146	* @param pVCpu Pointer to the VMCPU.
3147	* @param pCtx Pointer to the guest-CPU context.
3148	*
3149	* @remarks No-long-jump zone!!!
3150	*/
3151	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3152	{
3153	/*
3154	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
3155	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3156	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3157	*/
3158	#ifdef VBOX_WITH_KERNEL_USING_XMM
3159	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3160	pVCpu->hm.s.svm.pfnVMRun);
3161	#else
3162	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3163	#endif
3164	}
3165
3166
3167	/**
3168	* Performs some essential restoration of state after running guest code in
3169	* AMD-V.
3170	*
3171	* @param pVM Pointer to the VM.
3172	* @param pVCpu Pointer to the VMCPU.
3173	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3174	* out-of-sync. Make sure to update the required fields
3175	* before using them.
3176	* @param pSvmTransient Pointer to the SVM transient structure.
3177	* @param rcVMRun Return code of VMRUN.
3178	*
3179	* @remarks Called with interrupts disabled.
3180	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
3181	* unconditionally when it is safe to do so.
3182	*/
3183	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3184	{
3185	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3186
3187	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
3188	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
3189
3190	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3191	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3192
3193	if (pSvmTransient->fRestoreTscAuxMsr)
3194	{
3195	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
3196	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
3197	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
3198	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3199	}
3200
3201	/** @todo Last-seen-tick shouldn't be necessary when TM supports invariant
3202	* mode. */
3203	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
3204	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
3205
3206	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3207	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3208	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3209
3210	Assert(!(ASMGetFlags() & X86_EFL_IF));
3211	ASMSetFlags(pSvmTransient->uEflags); /* Enable interrupts. */
3212	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3213
3214	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3215	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3216	{
3217	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3218	return;
3219	}
3220
3221	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3222	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
3223	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
3224	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3225
3226	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3227
3228	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
3229	{
3230	if (pVCpu->hm.s.svm.fSyncVTpr)
3231	{
3232	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3233	if ( pVM->hm.s.fTPRPatchingActive
3234	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3235	{
3236	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3237	AssertRC(rc);
3238	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3239	}
3240	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3241	{
3242	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3243	AssertRC(rc);
3244	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3245	}
3246	}
3247	}
3248	}
3249
3250
3251	/**
3252	* Runs the guest code using AMD-V.
3253	*
3254	* @returns VBox status code.
3255	* @param pVM Pointer to the VM.
3256	* @param pVCpu Pointer to the VMCPU.
3257	*/
3258	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3259	{
3260	SVMTRANSIENT SvmTransient;
3261	SvmTransient.fUpdateTscOffsetting = true;
3262	uint32_t cLoops = 0;
3263	int rc = VERR_INTERNAL_ERROR_5;
3264
3265	for (;; cLoops++)
3266	{
3267	Assert(!HMR0SuspendPending());
3268	HMSVM_ASSERT_CPU_SAFE();
3269
3270	/* Preparatory work for running guest code, this may force us to return
3271	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3272	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3273	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3274	if (rc != VINF_SUCCESS)
3275	break;
3276
3277	/*
3278	* No longjmps to ring-3 from this point on!!!
3279	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3280	* This also disables flushing of the R0-logger instance (if any).
3281	*/
3282	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3283	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3284
3285	/* Restore any residual host-state and save any bits shared between host
3286	and guest into the guest-CPU state. Re-enables interrupts! */
3287	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3288
3289	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3290	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3291	{
3292	if (rc == VINF_SUCCESS)
3293	rc = VERR_SVM_INVALID_GUEST_STATE;
3294	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3295	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3296	break;
3297	}
3298
3299	/* Handle the #VMEXIT. */
3300	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3301	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3302	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3303	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3304	if (rc != VINF_SUCCESS)
3305	break;
3306	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
3307	{
3308	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3309	rc = VINF_EM_RAW_INTERRUPT;
3310	break;
3311	}
3312	}
3313
3314	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3315	return rc;
3316	}
3317
3318
3319	/**
3320	* Runs the guest code using AMD-V in single step mode.
3321	*
3322	* @returns VBox status code.
3323	* @param pVM Pointer to the VM.
3324	* @param pVCpu Pointer to the VMCPU.
3325	* @param pCtx Pointer to the guest-CPU context.
3326	*/
3327	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3328	{
3329	SVMTRANSIENT SvmTransient;
3330	SvmTransient.fUpdateTscOffsetting = true;
3331	uint32_t cLoops = 0;
3332	int rc = VERR_INTERNAL_ERROR_5;
3333	uint16_t uCsStart = pCtx->cs.Sel;
3334	uint64_t uRipStart = pCtx->rip;
3335
3336	for (;; cLoops++)
3337	{
3338	Assert(!HMR0SuspendPending());
3339	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
3340	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
3341	(unsigned)RTMpCpuId(), cLoops));
3342
3343	/* Preparatory work for running guest code, this may force us to return
3344	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3345	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3346	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3347	if (rc != VINF_SUCCESS)
3348	break;
3349
3350	/*
3351	* No longjmps to ring-3 from this point on!!!
3352	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3353	* This also disables flushing of the R0-logger instance (if any).
3354	*/
3355	VMMRZCallRing3Disable(pVCpu);
3356	VMMRZCallRing3RemoveNotification(pVCpu);
3357	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3358
3359	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3360
3361	/*
3362	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3363	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3364	*/
3365	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3366	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3367	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3368	{
3369	if (rc == VINF_SUCCESS)
3370	rc = VERR_SVM_INVALID_GUEST_STATE;
3371	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3372	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3373	return rc;
3374	}
3375
3376	/* Handle the #VMEXIT. */
3377	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3378	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3379	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3380	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3381	if (rc != VINF_SUCCESS)
3382	break;
3383	else if (cLoops > pVM->hm.s.cMaxResumeLoops)
3384	{
3385	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3386	rc = VINF_EM_RAW_INTERRUPT;
3387	break;
3388	}
3389
3390	/*
3391	* Did the RIP change, if so, consider it a single step.
3392	* Otherwise, make sure one of the TFs gets set.
3393	*/
3394	if ( pCtx->rip != uRipStart
3395	\|\| pCtx->cs.Sel != uCsStart)
3396	{
3397	rc = VINF_EM_DBG_STEPPED;
3398	break;
3399	}
3400	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3401	}
3402
3403	/*
3404	* Clear the X86_EFL_TF if necessary.
3405	*/
3406	if (pVCpu->hm.s.fClearTrapFlag)
3407	{
3408	pVCpu->hm.s.fClearTrapFlag = false;
3409	pCtx->eflags.Bits.u1TF = 0;
3410	}
3411
3412	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3413	return rc;
3414	}
3415
3416
3417	/**
3418	* Runs the guest code using AMD-V.
3419	*
3420	* @returns VBox status code.
3421	* @param pVM Pointer to the VM.
3422	* @param pVCpu Pointer to the VMCPU.
3423	* @param pCtx Pointer to the guest-CPU context.
3424	*/
3425	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3426	{
3427	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3428	HMSVM_ASSERT_PREEMPT_SAFE();
3429	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3430
3431	int rc;
3432	if (!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu))
3433	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx);
3434	else
3435	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx);
3436
3437	if (rc == VERR_EM_INTERPRETER)
3438	rc = VINF_EM_RAW_EMULATE_INSTR;
3439	else if (rc == VINF_EM_RESET)
3440	rc = VINF_EM_TRIPLE_FAULT;
3441
3442	/* Prepare to return to ring-3. This will remove longjmp notifications. */
3443	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3444	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3445	return rc;
3446	}
3447
3448
3449	/**
3450	* Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3451	*
3452	* @returns VBox status code (informational status codes included).
3453	* @param pVCpu Pointer to the VMCPU.
3454	* @param pCtx Pointer to the guest-CPU context.
3455	* @param pSvmTransient Pointer to the SVM transient structure.
3456	*/
3457	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3458	{
3459	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3460	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3461
3462	/*
3463	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
3464	* normal workloads (for some definition of "normal").
3465	*/
3466	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3467	switch (pSvmTransient->u64ExitCode)
3468	{
3469	case SVM_EXIT_NPF:
3470	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3471
3472	case SVM_EXIT_IOIO:
3473	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3474
3475	case SVM_EXIT_RDTSC:
3476	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3477
3478	case SVM_EXIT_RDTSCP:
3479	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3480
3481	case SVM_EXIT_CPUID:
3482	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3483
3484	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3485	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3486
3487	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3488	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3489
3490	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3491	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3492
3493	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3494	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3495
3496	case SVM_EXIT_MONITOR:
3497	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3498
3499	case SVM_EXIT_MWAIT:
3500	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3501
3502	case SVM_EXIT_HLT:
3503	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3504
3505	case SVM_EXIT_READ_CR0:
3506	case SVM_EXIT_READ_CR3:
3507	case SVM_EXIT_READ_CR4:
3508	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3509
3510	case SVM_EXIT_WRITE_CR0:
3511	case SVM_EXIT_WRITE_CR3:
3512	case SVM_EXIT_WRITE_CR4:
3513	case SVM_EXIT_WRITE_CR8:
3514	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3515
3516	case SVM_EXIT_VINTR:
3517	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3518
3519	case SVM_EXIT_INTR:
3520	case SVM_EXIT_FERR_FREEZE:
3521	case SVM_EXIT_NMI:
3522	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3523
3524	case SVM_EXIT_MSR:
3525	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3526
3527	case SVM_EXIT_INVLPG:
3528	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3529
3530	case SVM_EXIT_WBINVD:
3531	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3532
3533	case SVM_EXIT_INVD:
3534	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3535
3536	case SVM_EXIT_RDPMC:
3537	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3538
3539	default:
3540	{
3541	switch (pSvmTransient->u64ExitCode)
3542	{
3543	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3544	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3545	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3546	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3547	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3548
3549	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3550	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3551	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3552	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3553	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3554
3555	case SVM_EXIT_TASK_SWITCH:
3556	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3557
3558	case SVM_EXIT_VMMCALL:
3559	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3560
3561	case SVM_EXIT_IRET:
3562	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
3563
3564	case SVM_EXIT_SHUTDOWN:
3565	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3566
3567	case SVM_EXIT_SMI:
3568	case SVM_EXIT_INIT:
3569	{
3570	/*
3571	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3572	* we want to know about it so log the exit code and bail.
3573	*/
3574	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3575	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3576	return VERR_SVM_UNEXPECTED_EXIT;
3577	}
3578
3579	case SVM_EXIT_INVLPGA:
3580	case SVM_EXIT_RSM:
3581	case SVM_EXIT_VMRUN:
3582	case SVM_EXIT_VMLOAD:
3583	case SVM_EXIT_VMSAVE:
3584	case SVM_EXIT_STGI:
3585	case SVM_EXIT_CLGI:
3586	case SVM_EXIT_SKINIT:
3587	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3588
3589	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3590	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3591	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3592	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3593	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3594	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3595	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3596	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3597	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3598	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3599	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3600	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3601	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3602	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3603	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3604	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3605	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3606	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3607	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3608	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3609	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3610	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3611	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3612	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3613	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3614	{
3615	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3616	SVMEVENT Event;
3617	Event.u = 0;
3618	Event.n.u1Valid = 1;
3619	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3620	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3621
3622	switch (Event.n.u8Vector)
3623	{
3624	case X86_XCPT_DE:
3625	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3626	break;
3627
3628	case X86_XCPT_BP:
3629	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3630	* next instruction. */
3631	/** @todo Investigate this later. */
3632	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3633	break;
3634
3635	case X86_XCPT_UD:
3636	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3637	break;
3638
3639	case X86_XCPT_NP:
3640	Event.n.u1ErrorCodeValid = 1;
3641	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3642	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3643	break;
3644
3645	case X86_XCPT_SS:
3646	Event.n.u1ErrorCodeValid = 1;
3647	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3648	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3649	break;
3650
3651	case X86_XCPT_GP:
3652	Event.n.u1ErrorCodeValid = 1;
3653	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3654	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3655	break;
3656
3657	default:
3658	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3659	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3660	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3661	}
3662
3663	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3664	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3665	return VINF_SUCCESS;
3666	}
3667	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3668
3669	default:
3670	{
3671	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3672	pVCpu->hm.s.u32HMError = u32ExitCode;
3673	return VERR_SVM_UNKNOWN_EXIT;
3674	}
3675	}
3676	}
3677	}
3678	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3679	}
3680
3681
3682	#ifdef DEBUG
3683	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3684	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3685	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3686
3687	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3688	do \
3689	{ \
3690	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3691	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3692	} while (0)
3693
3694	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3695	do { \
3696	AssertPtr(pVCpu); \
3697	AssertPtr(pCtx); \
3698	AssertPtr(pSvmTransient); \
3699	Assert(ASMIntAreEnabled()); \
3700	HMSVM_ASSERT_PREEMPT_SAFE(); \
3701	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3702	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3703	HMSVM_ASSERT_PREEMPT_SAFE(); \
3704	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3705	HMSVM_ASSERT_PREEMPT_CPUID(); \
3706	} while (0)
3707	#else /* Release builds */
3708	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
3709	#endif
3710
3711
3712	/**
3713	* Worker for hmR0SvmInterpretInvlpg().
3714	*
3715	* @return VBox status code.
3716	* @param pVCpu Pointer to the VMCPU.
3717	* @param pCpu Pointer to the disassembler state.
3718	* @param pRegFrame Pointer to the register frame.
3719	*/
3720	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3721	{
3722	DISQPVPARAMVAL Param1;
3723	RTGCPTR GCPtrPage;
3724
3725	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3726	if (RT_FAILURE(rc))
3727	return VERR_EM_INTERPRETER;
3728
3729	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3730	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3731	{
3732	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3733	return VERR_EM_INTERPRETER;
3734
3735	GCPtrPage = Param1.val.val64;
3736	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3737	rc = VBOXSTRICTRC_VAL(rc2);
3738	}
3739	else
3740	{
3741	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3742	rc = VERR_EM_INTERPRETER;
3743	}
3744
3745	return rc;
3746	}
3747
3748
3749	/**
3750	* Interprets INVLPG.
3751	*
3752	* @returns VBox status code.
3753	* @retval VINF_* Scheduling instructions.
3754	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3755	* @retval VERR_* Fatal errors.
3756	*
3757	* @param pVM Pointer to the VM.
3758	* @param pRegFrame Pointer to the register frame.
3759	*
3760	* @remarks Updates the RIP if the instruction was executed successfully.
3761	*/
3762	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3763	{
3764	/* Only allow 32 & 64 bit code. */
3765	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3766	{
3767	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3768	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3769	if ( RT_SUCCESS(rc)
3770	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3771	{
3772	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3773	if (RT_SUCCESS(rc))
3774	pRegFrame->rip += pDis->cbInstr;
3775	return rc;
3776	}
3777	else
3778	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3779	}
3780	return VERR_EM_INTERPRETER;
3781	}
3782
3783
3784	/**
3785	* Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3786	*
3787	* @param pVCpu Pointer to the VMCPU.
3788	*/
3789	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3790	{
3791	SVMEVENT Event;
3792	Event.u = 0;
3793	Event.n.u1Valid = 1;
3794	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3795	Event.n.u8Vector = X86_XCPT_UD;
3796	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3797	}
3798
3799
3800	/**
3801	* Sets a debug (#DB) exception as pending-for-injection into the VM.
3802	*
3803	* @param pVCpu Pointer to the VMCPU.
3804	*/
3805	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3806	{
3807	SVMEVENT Event;
3808	Event.u = 0;
3809	Event.n.u1Valid = 1;
3810	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3811	Event.n.u8Vector = X86_XCPT_DB;
3812	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3813	}
3814
3815
3816	/**
3817	* Sets a page fault (#PF) exception as pending-for-injection into the VM.
3818	*
3819	* @param pVCpu Pointer to the VMCPU.
3820	* @param pCtx Pointer to the guest-CPU context.
3821	* @param u32ErrCode The error-code for the page-fault.
3822	* @param uFaultAddress The page fault address (CR2).
3823	*
3824	* @remarks This updates the guest CR2 with @a uFaultAddress!
3825	*/
3826	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3827	{
3828	SVMEVENT Event;
3829	Event.u = 0;
3830	Event.n.u1Valid = 1;
3831	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3832	Event.n.u8Vector = X86_XCPT_PF;
3833	Event.n.u1ErrorCodeValid = 1;
3834	Event.n.u32ErrorCode = u32ErrCode;
3835
3836	/* Update CR2 of the guest. */
3837	if (pCtx->cr2 != uFaultAddress)
3838	{
3839	pCtx->cr2 = uFaultAddress;
3840	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3841	}
3842
3843	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3844	}
3845
3846
3847	/**
3848	* Sets a device-not-available (#NM) exception as pending-for-injection into the
3849	* VM.
3850	*
3851	* @param pVCpu Pointer to the VMCPU.
3852	*/
3853	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3854	{
3855	SVMEVENT Event;
3856	Event.u = 0;
3857	Event.n.u1Valid = 1;
3858	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3859	Event.n.u8Vector = X86_XCPT_NM;
3860	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3861	}
3862
3863
3864	/**
3865	* Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3866	*
3867	* @param pVCpu Pointer to the VMCPU.
3868	*/
3869	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3870	{
3871	SVMEVENT Event;
3872	Event.u = 0;
3873	Event.n.u1Valid = 1;
3874	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3875	Event.n.u8Vector = X86_XCPT_MF;
3876	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3877	}
3878
3879
3880	/**
3881	* Sets a double fault (#DF) exception as pending-for-injection into the VM.
3882	*
3883	* @param pVCpu Pointer to the VMCPU.
3884	*/
3885	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3886	{
3887	SVMEVENT Event;
3888	Event.u = 0;
3889	Event.n.u1Valid = 1;
3890	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3891	Event.n.u8Vector = X86_XCPT_DF;
3892	Event.n.u1ErrorCodeValid = 1;
3893	Event.n.u32ErrorCode = 0;
3894	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3895	}
3896
3897
3898	/**
3899	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3900	* guests. This simply looks up the patch record at EIP and does the required.
3901	*
3902	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3903	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3904	* TPR). See hmR3ReplaceTprInstr() for the details.
3905	*
3906	* @returns VBox status code.
3907	* @retval VINF_SUCCESS if the access was handled successfully.
3908	* @retval VERR_NOT_FOUND if no patch record for this eip could be found.
3909	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
3910	*
3911	* @param pVM Pointer to the VM.
3912	* @param pVCpu Pointer to the VMCPU.
3913	* @param pCtx Pointer to the guest-CPU context.
3914	*/
3915	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3916	{
3917	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3918
3919	/*
3920	* We do this in a loop as we increment the RIP after a successful emulation
3921	* and the new RIP may be a patched instruction which needs emulation as well.
3922	*/
3923	bool fPatchFound = false;
3924	for (;;)
3925	{
3926	bool fPending;
3927	uint8_t u8Tpr;
3928
3929	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3930	if (!pPatch)
3931	break;
3932
3933	fPatchFound = true;
3934	switch (pPatch->enmType)
3935	{
3936	case HMTPRINSTR_READ:
3937	{
3938	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3939	AssertRC(rc);
3940
3941	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3942	AssertRC(rc);
3943	pCtx->rip += pPatch->cbOp;
3944	break;
3945	}
3946
3947	case HMTPRINSTR_WRITE_REG:
3948	case HMTPRINSTR_WRITE_IMM:
3949	{
3950	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3951	{
3952	uint32_t u32Val;
3953	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3954	AssertRC(rc);
3955	u8Tpr = u32Val;
3956	}
3957	else
3958	u8Tpr = (uint8_t)pPatch->uSrcOperand;
3959
3960	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3961	AssertRC(rc2);
3962	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3963
3964	pCtx->rip += pPatch->cbOp;
3965	break;
3966	}
3967
3968	default:
3969	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3970	pVCpu->hm.s.u32HMError = pPatch->enmType;
3971	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3972	}
3973	}
3974
3975	if (fPatchFound)
3976	return VINF_SUCCESS;
3977	return VERR_NOT_FOUND;
3978	}
3979
3980
3981	/**
3982	* Determines if an exception is a contributory exception. Contributory
3983	* exceptions are ones which can cause double-faults. Page-fault is
3984	* intentionally not included here as it's a conditional contributory exception.
3985	*
3986	* @returns true if the exception is contributory, false otherwise.
3987	* @param uVector The exception vector.
3988	*/
3989	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3990	{
3991	switch (uVector)
3992	{
3993	case X86_XCPT_GP:
3994	case X86_XCPT_SS:
3995	case X86_XCPT_NP:
3996	case X86_XCPT_TS:
3997	case X86_XCPT_DE:
3998	return true;
3999	default:
4000	break;
4001	}
4002	return false;
4003	}
4004
4005
4006	/**
4007	* Handle a condition that occurred while delivering an event through the guest
4008	* IDT.
4009	*
4010	* @returns VBox status code (informational error codes included).
4011	* @retval VINF_SUCCESS if we should continue handling the #VMEXIT.
4012	* @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
4013	* continue execution of the guest which will delivery the #DF.
4014	* @retval VINF_EM_RESET if we detected a triple-fault condition.
4015	*
4016	* @param pVCpu Pointer to the VMCPU.
4017	* @param pCtx Pointer to the guest-CPU context.
4018	* @param pSvmTransient Pointer to the SVM transient structure.
4019	*
4020	* @remarks No-long-jump zone!!!
4021	*/
4022	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4023	{
4024	int rc = VINF_SUCCESS;
4025	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4026
4027	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
4028	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
4029	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
4030	{
4031	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4032
4033	typedef enum
4034	{
4035	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4036	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4037	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4038	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
4039	} SVMREFLECTXCPT;
4040
4041	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
4042	bool fReflectingNmi = false;
4043	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
4044	{
4045	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4046	{
4047	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4048
4049	#ifdef VBOX_STRICT
4050	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
4051	&& uExitVector == X86_XCPT_PF)
4052	{
4053	Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
4054	}
4055	#endif
4056	if ( uExitVector == X86_XCPT_PF
4057	&& uIdtVector == X86_XCPT_PF)
4058	{
4059	pSvmTransient->fVectoringDoublePF = true;
4060	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
4061	}
4062	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
4063	&& hmR0SvmIsContributoryXcpt(uExitVector)
4064	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
4065	\|\| uIdtVector == X86_XCPT_PF))
4066	{
4067	enmReflect = SVMREFLECTXCPT_DF;
4068	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
4069	uIdtVector, uExitVector));
4070	}
4071	else if (uIdtVector == X86_XCPT_DF)
4072	{
4073	enmReflect = SVMREFLECTXCPT_TF;
4074	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
4075	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
4076	}
4077	else
4078	enmReflect = SVMREFLECTXCPT_XCPT;
4079	}
4080	else
4081	{
4082	/*
4083	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
4084	* exception to the guest after handling the #VMEXIT.
4085	*/
4086	enmReflect = SVMREFLECTXCPT_XCPT;
4087	}
4088	}
4089	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
4090	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4091	{
4092	enmReflect = SVMREFLECTXCPT_XCPT;
4093	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
4094
4095	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4096	{
4097	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4098	if (uExitVector == X86_XCPT_PF)
4099	{
4100	pSvmTransient->fVectoringPF = true;
4101	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
4102	}
4103	}
4104	}
4105	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
4106
4107	switch (enmReflect)
4108	{
4109	case SVMREFLECTXCPT_XCPT:
4110	{
4111	/* If we are re-injecting the NMI, clear NMI blocking. */
4112	if (fReflectingNmi)
4113	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4114
4115	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4116	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
4117
4118	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
4119	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
4120	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4121	break;
4122	}
4123
4124	case SVMREFLECTXCPT_DF:
4125	{
4126	hmR0SvmSetPendingXcptDF(pVCpu);
4127	rc = VINF_HM_DOUBLE_FAULT;
4128	break;
4129	}
4130
4131	case SVMREFLECTXCPT_TF:
4132	{
4133	rc = VINF_EM_RESET;
4134	break;
4135	}
4136
4137	default:
4138	Assert(rc == VINF_SUCCESS);
4139	break;
4140	}
4141	}
4142	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET);
4143	NOREF(pCtx);
4144	return rc;
4145	}
4146
4147
4148	/**
4149	* Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
4150	* CPU, otherwise advances the RIP by @a cb bytes.
4151	*
4152	* @param pVCpu Pointer to the VMCPU.
4153	* @param pCtx Pointer to the guest-CPU context.
4154	* @param cb RIP increment value in bytes.
4155	*
4156	* @remarks Use this function only from #VMEXIT's where the NRIP value is valid
4157	* when NRIP_SAVE is supported by the CPU!
4158	*/
4159	DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4160	{
4161	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4162	{
4163	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4164	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4165	}
4166	else
4167	pCtx->rip += cb;
4168	}
4169
4170
4171	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4172	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
4173	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4174
4175	/** @name #VMEXIT handlers.
4176	* @{
4177	*/
4178
4179	/**
4180	* #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
4181	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
4182	*/
4183	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4184	{
4185	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4186
4187	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
4188	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
4189	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
4190	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
4191
4192	/*
4193	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
4194	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
4195	* interrupt it is until the host actually take the interrupt.
4196	*
4197	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
4198	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
4199	*/
4200	return VINF_EM_RAW_INTERRUPT;
4201	}
4202
4203
4204	/**
4205	* #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
4206	*/
4207	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4208	{
4209	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4210
4211	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4212	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
4213	int rc = VINF_SUCCESS;
4214	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4215	return rc;
4216	}
4217
4218
4219	/**
4220	* #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
4221	*/
4222	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4223	{
4224	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4225
4226	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4227	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
4228	int rc = VINF_SUCCESS;
4229	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4230	return rc;
4231	}
4232
4233
4234	/**
4235	* #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
4236	*/
4237	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4238	{
4239	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4240	PVM pVM = pVCpu->CTX_SUFF(pVM);
4241	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4242	if (RT_LIKELY(rc == VINF_SUCCESS))
4243	{
4244	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4245	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4246	}
4247	else
4248	{
4249	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4250	rc = VERR_EM_INTERPRETER;
4251	}
4252	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
4253	return rc;
4254	}
4255
4256
4257	/**
4258	* #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
4259	*/
4260	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4261	{
4262	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4263	PVM pVM = pVCpu->CTX_SUFF(pVM);
4264	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4265	if (RT_LIKELY(rc == VINF_SUCCESS))
4266	{
4267	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4268	pSvmTransient->fUpdateTscOffsetting = true;
4269
4270	/* Single step check. */
4271	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4272	}
4273	else
4274	{
4275	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
4276	rc = VERR_EM_INTERPRETER;
4277	}
4278	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
4279	return rc;
4280	}
4281
4282
4283	/**
4284	* #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
4285	*/
4286	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4287	{
4288	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4289	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4290	if (RT_LIKELY(rc == VINF_SUCCESS))
4291	{
4292	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4293	pSvmTransient->fUpdateTscOffsetting = true;
4294	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4295	}
4296	else
4297	{
4298	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
4299	rc = VERR_EM_INTERPRETER;
4300	}
4301	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
4302	return rc;
4303	}
4304
4305
4306	/**
4307	* #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
4308	*/
4309	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4310	{
4311	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4312	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4313	if (RT_LIKELY(rc == VINF_SUCCESS))
4314	{
4315	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4316	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4317	}
4318	else
4319	{
4320	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4321	rc = VERR_EM_INTERPRETER;
4322	}
4323	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4324	return rc;
4325	}
4326
4327
4328	/**
4329	* #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
4330	*/
4331	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4332	{
4333	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4334	PVM pVM = pVCpu->CTX_SUFF(pVM);
4335	Assert(!pVM->hm.s.fNestedPaging);
4336
4337	/** @todo Decode Assist. */
4338	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
4339	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4340	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
4341	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4342	return rc;
4343	}
4344
4345
4346	/**
4347	* #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
4348	*/
4349	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4350	{
4351	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4352	hmR0SvmUpdateRip(pVCpu, pCtx, 1);
4353	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4354	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4355	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4356	return rc;
4357	}
4358
4359
4360	/**
4361	* #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
4362	*/
4363	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4364	{
4365	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4366	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4367	if (RT_LIKELY(rc == VINF_SUCCESS))
4368	{
4369	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4370	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4371	}
4372	else
4373	{
4374	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4375	rc = VERR_EM_INTERPRETER;
4376	}
4377	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4378	return rc;
4379	}
4380
4381
4382	/**
4383	* #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
4384	*/
4385	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4386	{
4387	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4388	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4389	int rc = VBOXSTRICTRC_VAL(rc2);
4390	if ( rc == VINF_EM_HALT
4391	\|\| rc == VINF_SUCCESS)
4392	{
4393	hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4394
4395	if ( rc == VINF_EM_HALT
4396	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
4397	{
4398	rc = VINF_SUCCESS;
4399	}
4400	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4401	}
4402	else
4403	{
4404	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4405	rc = VERR_EM_INTERPRETER;
4406	}
4407	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
4408	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4409	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4410	return rc;
4411	}
4412
4413
4414	/**
4415	* #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
4416	* Conditional #VMEXIT.
4417	*/
4418	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4419	{
4420	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4421	return VINF_EM_RESET;
4422	}
4423
4424
4425	/**
4426	* #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
4427	*/
4428	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4429	{
4430	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4431
4432	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4433
4434	/** @todo Decode Assist. */
4435	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4436	int rc = VBOXSTRICTRC_VAL(rc2);
4437	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4438	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4439	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4440	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4441	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4442	return rc;
4443	}
4444
4445
4446	/**
4447	* #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
4448	*/
4449	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4450	{
4451	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4452	/** @todo Decode Assist. */
4453	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4454	int rc = VBOXSTRICTRC_VAL(rc2);
4455	if (rc == VINF_SUCCESS)
4456	{
4457	/* RIP has been updated by EMInterpretInstruction(). */
4458	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4459	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4460	{
4461	case 0: /* CR0. */
4462	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4463	break;
4464
4465	case 3: /* CR3. */
4466	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4467	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4468	break;
4469
4470	case 4: /* CR4. */
4471	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4472	break;
4473
4474	case 8: /* CR8 (TPR). */
4475	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4476	break;
4477
4478	default:
4479	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4480	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4481	break;
4482	}
4483	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4484	}
4485	else
4486	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
4487	return rc;
4488	}
4489
4490
4491	/**
4492	* #VMEXIT handler for instructions that result in a #UD exception delivered to
4493	* the guest.
4494	*/
4495	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4496	{
4497	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4498	hmR0SvmSetPendingXcptUD(pVCpu);
4499	return VINF_SUCCESS;
4500	}
4501
4502
4503	/**
4504	* #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4505	*/
4506	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4507	{
4508	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4509	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4510	PVM pVM = pVCpu->CTX_SUFF(pVM);
4511
4512	int rc;
4513	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4514	{
4515	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4516
4517	/* Handle TPR patching; intercepted LSTAR write. */
4518	if ( pVM->hm.s.fTPRPatchingActive
4519	&& pCtx->ecx == MSR_K8_LSTAR)
4520	{
4521	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4522	{
4523	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4524	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4525	AssertRC(rc2);
4526	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4527	}
4528	hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4529	rc = VINF_SUCCESS;
4530	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4531	return rc;
4532	}
4533
4534	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4535	{
4536	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4537	if (RT_LIKELY(rc == VINF_SUCCESS))
4538	{
4539	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4540	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4541	}
4542	else
4543	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4544	}
4545	else
4546	{
4547	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4548	if (RT_LIKELY(rc == VINF_SUCCESS))
4549	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
4550	else
4551	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4552	}
4553
4554	if (rc == VINF_SUCCESS)
4555	{
4556	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4557	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4558	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4559	{
4560	/*
4561	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4562	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4563	* EMInterpretWrmsr() changes it.
4564	*/
4565	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4566	}
4567	else if (pCtx->ecx == MSR_K6_EFER)
4568	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4569	else if (pCtx->ecx == MSR_IA32_TSC)
4570	pSvmTransient->fUpdateTscOffsetting = true;
4571	}
4572	}
4573	else
4574	{
4575	/* MSR Read access. */
4576	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4577	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4578
4579	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4580	{
4581	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4582	if (RT_LIKELY(rc == VINF_SUCCESS))
4583	{
4584	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4585	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4586	}
4587	else
4588	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4589	}
4590	else
4591	{
4592	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4593	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4594	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4595	/* RIP updated by EMInterpretInstruction(). */
4596	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4597	}
4598	}
4599
4600	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4601	return rc;
4602	}
4603
4604
4605	/**
4606	* #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4607	*/
4608	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4609	{
4610	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4611	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4612
4613	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
4614	if (pSvmTransient->fWasGuestDebugStateActive)
4615	{
4616	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
4617	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
4618	return VERR_SVM_UNEXPECTED_EXIT;
4619	}
4620
4621	/*
4622	* Lazy DR0-3 loading.
4623	*/
4624	if (!pSvmTransient->fWasHyperDebugStateActive)
4625	{
4626	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4627	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4628
4629	/* Don't intercept DRx read and writes. */
4630	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4631	pVmcb->ctrl.u16InterceptRdDRx = 0;
4632	pVmcb->ctrl.u16InterceptWrDRx = 0;
4633	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4634
4635	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4636	VMMRZCallRing3Disable(pVCpu);
4637	HM_DISABLE_PREEMPT_IF_NEEDED();
4638
4639	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4640	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4641	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4642
4643	HM_RESTORE_PREEMPT_IF_NEEDED();
4644	VMMRZCallRing3Enable(pVCpu);
4645
4646	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4647	return VINF_SUCCESS;
4648	}
4649
4650	/*
4651	* Interpret the read/writing of DRx.
4652	*/
4653	/** @todo Decode assist. */
4654	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4655	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4656	if (RT_LIKELY(rc == VINF_SUCCESS))
4657	{
4658	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4659	/** @todo CPUM should set this flag! */
4660	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4661	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4662	}
4663	else
4664	Assert(rc == VERR_EM_INTERPRETER);
4665	return VBOXSTRICTRC_TODO(rc);
4666	}
4667
4668
4669	/**
4670	* #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4671	*/
4672	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4673	{
4674	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4675	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4676	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4677	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4678	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4679	return rc;
4680	}
4681
4682
4683	/**
4684	* #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4685	*/
4686	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4687	{
4688	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4689
4690	/* I/O operation lookup arrays. */
4691	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4692	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4693	the result (in AL/AX/EAX). */
4694	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4695
4696	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4697	PVM pVM = pVCpu->CTX_SUFF(pVM);
4698
4699	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4700	SVMIOIOEXIT IoExitInfo;
4701	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4702	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4703	uint32_t cbValue = s_aIOSize[uIOWidth];
4704	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4705
4706	if (RT_UNLIKELY(!cbValue))
4707	{
4708	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4709	return VERR_EM_INTERPRETER;
4710	}
4711
4712	VBOXSTRICTRC rcStrict;
4713	if (IoExitInfo.n.u1STR)
4714	{
4715	/* INS/OUTS - I/O String instruction. */
4716	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4717
4718	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4719	* in EXITINFO1? Investigate once this thing is up and running. */
4720
4721	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4722	if (rcStrict == VINF_SUCCESS)
4723	{
4724	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4725	{
4726	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4727	(DISCPUMODE)pDis->uAddrMode, cbValue);
4728	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4729	}
4730	else
4731	{
4732	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4733	(DISCPUMODE)pDis->uAddrMode, cbValue);
4734	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4735	}
4736	}
4737	else
4738	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4739	}
4740	else
4741	{
4742	/* IN/OUT - I/O instruction. */
4743	Assert(!IoExitInfo.n.u1REP);
4744
4745	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4746	{
4747	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4748	if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4749	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4750
4751	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4752	}
4753	else
4754	{
4755	uint32_t u32Val = 0;
4756
4757	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4758	if (IOM_SUCCESS(rcStrict))
4759	{
4760	/* Save result of I/O IN instr. in AL/AX/EAX. */
4761	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4762	}
4763	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4764	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4765
4766	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4767	}
4768	}
4769
4770	if (IOM_SUCCESS(rcStrict))
4771	{
4772	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4773	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4774
4775	/*
4776	* If any I/O breakpoints are armed, we need to check if one triggered
4777	* and take appropriate action.
4778	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4779	*/
4780	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4781	* execution engines about whether hyper BPs and such are pending. */
4782	uint32_t const uDr7 = pCtx->dr[7];
4783	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4784	&& X86_DR7_ANY_RW_IO(uDr7)
4785	&& (pCtx->cr4 & X86_CR4_DE))
4786	\|\| DBGFBpIsHwIoArmed(pVM)))
4787	{
4788	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4789	VMMRZCallRing3Disable(pVCpu);
4790	HM_DISABLE_PREEMPT_IF_NEEDED();
4791
4792	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4793	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
4794
4795	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4796	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4797	{
4798	/* Raise #DB. */
4799	pVmcb->guest.u64DR6 = pCtx->dr[6];
4800	pVmcb->guest.u64DR7 = pCtx->dr[7];
4801	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4802	hmR0SvmSetPendingXcptDB(pVCpu);
4803	}
4804	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4805	else if ( rcStrict2 != VINF_SUCCESS
4806	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
4807	rcStrict = rcStrict2;
4808
4809	HM_RESTORE_PREEMPT_IF_NEEDED();
4810	VMMRZCallRing3Enable(pVCpu);
4811	}
4812
4813	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4814	}
4815
4816	#ifdef VBOX_STRICT
4817	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4818	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4819	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4820	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4821	else
4822	{
4823	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4824	* statuses, that the VMM device and some others may return. See
4825	* IOM_SUCCESS() for guidance. */
4826	AssertMsg( RT_FAILURE(rcStrict)
4827	\|\| rcStrict == VINF_SUCCESS
4828	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
4829	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
4830	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
4831	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4832	}
4833	#endif
4834	return VBOXSTRICTRC_TODO(rcStrict);
4835	}
4836
4837
4838	/**
4839	* #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4840	* #VMEXIT.
4841	*/
4842	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4843	{
4844	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4845	PVM pVM = pVCpu->CTX_SUFF(pVM);
4846	Assert(pVM->hm.s.fNestedPaging);
4847
4848	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4849
4850	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4851	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4852	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4853	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4854
4855	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4856
4857	#ifdef VBOX_HM_WITH_GUEST_PATCHING
4858	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4859	if ( pVM->hm.s.fTprPatchingAllowed
4860	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4861	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4862	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
4863	&& !CPUMIsGuestInLongModeEx(pCtx)
4864	&& !CPUMGetGuestCPL(pVCpu)
4865	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4866	{
4867	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4868	GCPhysApicBase &= PAGE_BASE_GC_MASK;
4869
4870	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4871	{
4872	/* Only attempt to patch the instruction once. */
4873	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4874	if (!pPatch)
4875	return VINF_EM_HM_PATCH_TPR_INSTR;
4876	}
4877	}
4878	#endif
4879
4880	/*
4881	* Determine the nested paging mode.
4882	*/
4883	PGMMODE enmNestedPagingMode;
4884	#if HC_ARCH_BITS == 32
4885	if (CPUMIsGuestInLongModeEx(pCtx))
4886	enmNestedPagingMode = PGMMODE_AMD64_NX;
4887	else
4888	#endif
4889	enmNestedPagingMode = PGMGetHostMode(pVM);
4890
4891	/*
4892	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4893	*/
4894	int rc;
4895	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4896	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
4897	{
4898	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4899	u32ErrCode);
4900	rc = VBOXSTRICTRC_VAL(rc2);
4901
4902	/*
4903	* If we succeed, resume guest execution.
4904	* If we fail in interpreting the instruction because we couldn't get the guest physical address
4905	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4906	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4907	* weird case. See @bugref{6043}.
4908	*/
4909	if ( rc == VINF_SUCCESS
4910	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4911	\|\| rc == VERR_PAGE_NOT_PRESENT)
4912	{
4913	/* Successfully handled MMIO operation. */
4914	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4915	rc = VINF_SUCCESS;
4916	}
4917	return rc;
4918	}
4919
4920	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4921	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4922	TRPMResetTrap(pVCpu);
4923
4924	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4925
4926	/*
4927	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4928	*/
4929	if ( rc == VINF_SUCCESS
4930	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
4931	\|\| rc == VERR_PAGE_NOT_PRESENT)
4932	{
4933	/* We've successfully synced our shadow page tables. */
4934	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4935	rc = VINF_SUCCESS;
4936	}
4937
4938	return rc;
4939	}
4940
4941
4942	/**
4943	* #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4944	*/
4945	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4946	{
4947	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4948
4949	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4950	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
4951	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4952
4953	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
4954	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4955	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
4956
4957	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
4958	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4959	return VINF_SUCCESS;
4960	}
4961
4962
4963	/**
4964	* #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4965	*/
4966	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4967	{
4968	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4969
4970	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4971	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4972	#endif
4973
4974	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
4975	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4976	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
4977	&& pVCpu->hm.s.Event.fPending) /** @todo fPending cannot be 'true', see hmR0SvmInjectPendingEvent(). See @bugref{7362}.*/
4978	{
4979	/*
4980	* AMD-V does not provide us with the original exception but we have it in u64IntInfo since we
4981	* injected the event during VM-entry.
4982	*/
4983	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
4984	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4985	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4986	}
4987
4988	/** @todo Emulate task switch someday, currently just going back to ring-3 for
4989	* emulation. */
4990	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4991	return VERR_EM_INTERPRETER;
4992	}
4993
4994
4995	/**
4996	* #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4997	*/
4998	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4999	{
5000	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5001
5002	/* First check if this is a patched VMMCALL for mov TPR */
5003	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5004	if (rc == VINF_SUCCESS)
5005	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5006	else if (rc == VERR_NOT_FOUND)
5007	{
5008	/* Handle GIM provider hypercalls. */
5009	rc = VERR_NOT_SUPPORTED;
5010	if (GIMAreHypercallsEnabled(pVCpu))
5011	rc = GIMHypercall(pVCpu, pCtx);
5012	}
5013
5014	if (rc != VINF_SUCCESS)
5015	hmR0SvmSetPendingXcptUD(pVCpu);
5016	return VINF_SUCCESS;
5017	}
5018
5019
5020	/**
5021	* #VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional #VMEXIT.
5022	*/
5023	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5024	{
5025	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5026
5027	/* Clear NMI blocking. */
5028	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5029
5030	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
5031	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5032	hmR0SvmClearIretIntercept(pVmcb);
5033
5034	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5035	return VINF_SUCCESS;
5036	}
5037
5038
5039	/**
5040	* #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
5041	* #VMEXIT.
5042	*/
5043	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5044	{
5045	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5046
5047	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5048
5049	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
5050	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5051	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5052	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
5053	PVM pVM = pVCpu->CTX_SUFF(pVM);
5054
5055	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
5056	if (pVM->hm.s.fNestedPaging)
5057	{
5058	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5059	if (!pSvmTransient->fVectoringDoublePF)
5060	{
5061	/* A genuine guest #PF, reflect it to the guest. */
5062	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5063	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
5064	uFaultAddress, u32ErrCode));
5065	}
5066	else
5067	{
5068	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5069	hmR0SvmSetPendingXcptDF(pVCpu);
5070	Log4(("Pending #DF due to vectoring #PF. NP\n"));
5071	}
5072	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5073	return VINF_SUCCESS;
5074	}
5075	#endif
5076
5077	Assert(!pVM->hm.s.fNestedPaging);
5078
5079	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5080	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
5081	if ( pVM->hm.s.fTprPatchingAllowed
5082	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
5083	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
5084	&& !CPUMIsGuestInLongModeEx(pCtx)
5085	&& !CPUMGetGuestCPL(pVCpu)
5086	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5087	{
5088	RTGCPHYS GCPhysApicBase;
5089	GCPhysApicBase = pCtx->msrApicBase;
5090	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5091
5092	/* Check if the page at the fault-address is the APIC base. */
5093	RTGCPHYS GCPhysPage;
5094	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
5095	if ( rc2 == VINF_SUCCESS
5096	&& GCPhysPage == GCPhysApicBase)
5097	{
5098	/* Only attempt to patch the instruction once. */
5099	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5100	if (!pPatch)
5101	return VINF_EM_HM_PATCH_TPR_INSTR;
5102	}
5103	}
5104	#endif
5105
5106	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
5107	pCtx->rip, u32ErrCode, pCtx->cr3));
5108
5109	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
5110	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
5111	if (pSvmTransient->fVectoringPF)
5112	{
5113	Assert(pVCpu->hm.s.Event.fPending);
5114	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5115	}
5116
5117	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
5118	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
5119
5120	Log4(("#PF rc=%Rrc\n", rc));
5121
5122	if (rc == VINF_SUCCESS)
5123	{
5124	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
5125	TRPMResetTrap(pVCpu);
5126	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5127	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5128	return rc;
5129	}
5130	else if (rc == VINF_EM_RAW_GUEST_TRAP)
5131	{
5132	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5133
5134	if (!pSvmTransient->fVectoringDoublePF)
5135	{
5136	/* It's a guest page fault and needs to be reflected to the guest. */
5137	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
5138	TRPMResetTrap(pVCpu);
5139	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5140	}
5141	else
5142	{
5143	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5144	TRPMResetTrap(pVCpu);
5145	hmR0SvmSetPendingXcptDF(pVCpu);
5146	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
5147	}
5148
5149	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5150	return VINF_SUCCESS;
5151	}
5152
5153	TRPMResetTrap(pVCpu);
5154	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
5155	return rc;
5156	}
5157
5158
5159	/**
5160	* #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
5161	* Conditional #VMEXIT.
5162	*/
5163	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5164	{
5165	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5166
5167	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5168
5169	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5170	VMMRZCallRing3Disable(pVCpu);
5171	HM_DISABLE_PREEMPT_IF_NEEDED();
5172
5173	int rc;
5174	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
5175	if (pSvmTransient->fWasGuestFPUStateActive)
5176	{
5177	rc = VINF_EM_RAW_GUEST_TRAP;
5178	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
5179	}
5180	else
5181	{
5182	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5183	Assert(!pSvmTransient->fWasGuestFPUStateActive);
5184	#endif
5185	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5186	Assert(rc == VINF_EM_RAW_GUEST_TRAP \|\| (rc == VINF_SUCCESS && CPUMIsGuestFPUStateActive(pVCpu)));
5187	}
5188
5189	HM_RESTORE_PREEMPT_IF_NEEDED();
5190	VMMRZCallRing3Enable(pVCpu);
5191
5192	if (rc == VINF_SUCCESS)
5193	{
5194	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
5195	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
5196	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
5197	pVCpu->hm.s.fUseGuestFpu = true;
5198	}
5199	else
5200	{
5201	/* Forward #NM to the guest. */
5202	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
5203	hmR0SvmSetPendingXcptNM(pVCpu);
5204	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
5205	}
5206	return VINF_SUCCESS;
5207	}
5208
5209
5210	/**
5211	* #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
5212	* Conditional #VMEXIT.
5213	*/
5214	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5215	{
5216	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5217
5218	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5219
5220	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
5221
5222	if (!(pCtx->cr0 & X86_CR0_NE))
5223	{
5224	PVM pVM = pVCpu->CTX_SUFF(pVM);
5225	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5226	unsigned cbOp;
5227	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
5228	if (RT_SUCCESS(rc))
5229	{
5230	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
5231	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
5232	if (RT_SUCCESS(rc))
5233	pCtx->rip += cbOp;
5234	}
5235	else
5236	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5237	return rc;
5238	}
5239
5240	hmR0SvmSetPendingXcptMF(pVCpu);
5241	return VINF_SUCCESS;
5242	}
5243
5244
5245	/**
5246	* #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
5247	* #VMEXIT.
5248	*/
5249	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5250	{
5251	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5252
5253	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5254
5255	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
5256
5257	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
5258	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
5259	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5260	PVM pVM = pVCpu->CTX_SUFF(pVM);
5261	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
5262	if (rc == VINF_EM_RAW_GUEST_TRAP)
5263	{
5264	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
5265	if (CPUMIsHyperDebugStateActive(pVCpu))
5266	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
5267
5268	/* Reflect the exception back to the guest. */
5269	hmR0SvmSetPendingXcptDB(pVCpu);
5270	rc = VINF_SUCCESS;
5271	}
5272
5273	/*
5274	* Update DR6.
5275	*/
5276	if (CPUMIsHyperDebugStateActive(pVCpu))
5277	{
5278	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
5279	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
5280	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5281	}
5282	else
5283	{
5284	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
5285	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
5286	}
5287
5288	return rc;
5289	}
5290
5291	/** @} */
5292

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 53349

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