HMSVMR0.cpp@ 61649

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1	/* $Id: HMSVMR0.cpp 61649 2016-06-10 10:50:42Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/thread.h>
25
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#ifdef VBOX_WITH_NEW_APIC
33	# include <VBox/vmm/apic.h>
34	#endif
35	#include "HMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include "HMSVMR0.h"
38	#include "dtrace/VBoxVMM.h"
39
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
43	# define HMSVM_ALWAYS_TRAP_PF
44	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
45	#endif
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	#ifdef VBOX_WITH_STATISTICS
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
53	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
54	if ((u64ExitCode) == SVM_EXIT_NPF) \
55	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
56	else \
57	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
58	} while (0)
59	#else
60	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
61	#endif
62
63	/** If we decide to use a function table approach this can be useful to
64	* switch to a "static DECLCALLBACK(int)". */
65	#define HMSVM_EXIT_DECL static int
66
67	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
68	*
69	* The CPU format of the segment attribute is described in X86DESCATTRBITS
70	* which is 16-bits (i.e. includes 4 bits of the segment limit).
71	*
72	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
73	* only the attribute bits and nothing else). Upper 4-bits are unused.
74	*
75	* @{ */
76	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
77	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
78	/** @} */
79
80	/** @name Macros for loading, storing segment registers to/from the VMCB.
81	* @{ */
82	#define HMSVM_LOAD_SEG_REG(REG, reg) \
83	do \
84	{ \
85	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
86	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
87	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
88	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
89	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
90	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
91	} while (0)
92
93	#define HMSVM_SAVE_SEG_REG(REG, reg) \
94	do \
95	{ \
96	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
97	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
98	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
99	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
100	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
101	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
102	} while (0)
103	/** @} */
104
105	/** Macro for checking and returning from the using function for
106	* \#VMEXIT intercepts that maybe caused during delivering of another
107	* event in the guest. */
108	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
109	do \
110	{ \
111	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
112	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
113	else if (rc == VINF_HM_DOUBLE_FAULT) \
114	return VINF_SUCCESS; \
115	else \
116	return rc; \
117	} while (0)
118
119	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
120	* instruction that exited. */
121	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
122	do { \
123	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
124	(a_rc) = VINF_EM_DBG_STEPPED; \
125	} while (0)
126
127	/** Assert that preemption is disabled or covered by thread-context hooks. */
128	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
129	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
130
131	/** Assert that we haven't migrated CPUs when thread-context hooks are not
132	* used. */
133	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
134	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
135	("Illegal migration! Entered on CPU %u Current %u\n", \
136	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
137
138	/** Exception bitmap mask for all contributory exceptions.
139	*
140	* Page fault is deliberately excluded here as it's conditional as to whether
141	* it's contributory or benign. Page faults are handled separately.
142	*/
143	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
144	\| RT_BIT(X86_XCPT_DE))
145
146	/** @name VMCB Clean Bits.
147	*
148	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
149	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
150	* memory.
151	*
152	* @{ */
153	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
154	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
155	/** I/O permission bitmap, MSR permission bitmap. */
156	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
157	/** ASID. */
158	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
159	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
160	V_INTR_VECTOR. */
161	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
162	/** Nested Paging: Nested CR3 (nCR3), PAT. */
163	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
164	/** Control registers (CR0, CR3, CR4, EFER). */
165	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
166	/** Debug registers (DR6, DR7). */
167	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
168	/** GDT, IDT limit and base. */
169	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
170	/** Segment register: CS, SS, DS, ES limit and base. */
171	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
172	/** CR2.*/
173	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
174	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
175	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
176	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
177	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
178	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
179	/** Mask of all valid VMCB Clean bits. */
180	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
181	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
182	\| HMSVM_VMCB_CLEAN_ASID \
183	\| HMSVM_VMCB_CLEAN_TPR \
184	\| HMSVM_VMCB_CLEAN_NP \
185	\| HMSVM_VMCB_CLEAN_CRX_EFER \
186	\| HMSVM_VMCB_CLEAN_DRX \
187	\| HMSVM_VMCB_CLEAN_DT \
188	\| HMSVM_VMCB_CLEAN_SEG \
189	\| HMSVM_VMCB_CLEAN_CR2 \
190	\| HMSVM_VMCB_CLEAN_LBR \
191	\| HMSVM_VMCB_CLEAN_AVIC)
192	/** @} */
193
194	/** @name SVM transient.
195	*
196	* A state structure for holding miscellaneous information across AMD-V
197	* VMRUN/\#VMEXIT operation, restored after the transition.
198	*
199	* @{ */
200	typedef struct SVMTRANSIENT
201	{
202	/** The host's rflags/eflags. */
203	RTCCUINTREG fEFlags;
204	#if HC_ARCH_BITS == 32
205	uint32_t u32Alignment0;
206	#endif
207
208	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
209	uint64_t u64ExitCode;
210	/** The guest's TPR value used for TPR shadowing. */
211	uint8_t u8GuestTpr;
212	/** Alignment. */
213	uint8_t abAlignment0[7];
214
215	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
216	bool fWasGuestFPUStateActive;
217	/** Whether the guest debug state was active at the time of \#VMEXIT. */
218	bool fWasGuestDebugStateActive;
219	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
220	bool fWasHyperDebugStateActive;
221	/** Whether the TSC offset mode needs to be updated. */
222	bool fUpdateTscOffsetting;
223	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
224	bool fRestoreTscAuxMsr;
225	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
226	* contributary exception or a page-fault. */
227	bool fVectoringDoublePF;
228	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
229	* external interrupt or NMI. */
230	bool fVectoringPF;
231	} SVMTRANSIENT, *PSVMTRANSIENT;
232	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
233	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
234	/** @} */
235
236	/**
237	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
238	*/
239	typedef enum SVMMSREXITREAD
240	{
241	/** Reading this MSR causes a \#VMEXIT. */
242	SVMMSREXIT_INTERCEPT_READ = 0xb,
243	/** Reading this MSR does not cause a \#VMEXIT. */
244	SVMMSREXIT_PASSTHRU_READ
245	} SVMMSREXITREAD;
246
247	/**
248	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
249	*/
250	typedef enum SVMMSREXITWRITE
251	{
252	/** Writing to this MSR causes a \#VMEXIT. */
253	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
254	/** Writing to this MSR does not cause a \#VMEXIT. */
255	SVMMSREXIT_PASSTHRU_WRITE
256	} SVMMSREXITWRITE;
257
258	/**
259	* SVM \#VMEXIT handler.
260	*
261	* @returns VBox status code.
262	* @param pVCpu The cross context virtual CPU structure.
263	* @param pMixedCtx Pointer to the guest-CPU context.
264	* @param pSvmTransient Pointer to the SVM-transient structure.
265	*/
266	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
267
268
269	/*********************************************************************************************************************************
270	* Internal Functions *
271	*********************************************************************************************************************************/
272	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
273	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
274	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
275
276	/** @name \#VMEXIT handlers.
277	* @{
278	*/
279	static FNSVMEXITHANDLER hmR0SvmExitIntr;
280	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
281	static FNSVMEXITHANDLER hmR0SvmExitInvd;
282	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
283	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
284	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
285	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
286	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
287	static FNSVMEXITHANDLER hmR0SvmExitHlt;
288	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
289	static FNSVMEXITHANDLER hmR0SvmExitMwait;
290	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
291	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
292	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
293	static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
294	static FNSVMEXITHANDLER hmR0SvmExitMsr;
295	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
296	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
297	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
298	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
299	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
300	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
301	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
302	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
303	static FNSVMEXITHANDLER hmR0SvmExitPause;
304	static FNSVMEXITHANDLER hmR0SvmExitIret;
305	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
306	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
307	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
308	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
309	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
310	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
311	/** @} */
312
313	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
314
315
316	/*********************************************************************************************************************************
317	* Global Variables *
318	*********************************************************************************************************************************/
319	/** Ring-0 memory object for the IO bitmap. */
320	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
321	/** Physical address of the IO bitmap. */
322	RTHCPHYS g_HCPhysIOBitmap = 0;
323	/** Virtual address of the IO bitmap. */
324	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
325
326
327	/**
328	* Sets up and activates AMD-V on the current CPU.
329	*
330	* @returns VBox status code.
331	* @param pCpu Pointer to the CPU info struct.
332	* @param pVM The cross context VM structure. Can be
333	* NULL after a resume!
334	* @param pvCpuPage Pointer to the global CPU page.
335	* @param HCPhysCpuPage Physical address of the global CPU page.
336	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
337	* @param pvArg Unused on AMD-V.
338	*/
339	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
340	void *pvArg)
341	{
342	Assert(!fEnabledByHost);
343	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
344	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
345	Assert(pvCpuPage); NOREF(pvCpuPage);
346	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
347
348	NOREF(pvArg);
349	NOREF(fEnabledByHost);
350
351	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
352	RTCCUINTREG fEFlags = ASMIntDisableFlags();
353
354	/*
355	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
356	*/
357	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
358	if (u64HostEfer & MSR_K6_EFER_SVME)
359	{
360	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
361	if ( pVM
362	&& pVM->hm.s.svm.fIgnoreInUseError)
363	{
364	pCpu->fIgnoreAMDVInUseError = true;
365	}
366
367	if (!pCpu->fIgnoreAMDVInUseError)
368	{
369	ASMSetFlags(fEFlags);
370	return VERR_SVM_IN_USE;
371	}
372	}
373
374	/* Turn on AMD-V in the EFER MSR. */
375	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
376
377	/* Write the physical page address where the CPU will store the host state while executing the VM. */
378	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
379
380	/* Restore interrupts. */
381	ASMSetFlags(fEFlags);
382
383	/*
384	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
385	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
386	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
387	* to flush the TLB with before using a new ASID.
388	*/
389	pCpu->fFlushAsidBeforeUse = true;
390
391	/*
392	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
393	*/
394	++pCpu->cTlbFlushes;
395
396	return VINF_SUCCESS;
397	}
398
399
400	/**
401	* Deactivates AMD-V on the current CPU.
402	*
403	* @returns VBox status code.
404	* @param pCpu Pointer to the CPU info struct.
405	* @param pvCpuPage Pointer to the global CPU page.
406	* @param HCPhysCpuPage Physical address of the global CPU page.
407	*/
408	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
409	{
410	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
411	AssertReturn( HCPhysCpuPage
412	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
413	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
414	NOREF(pCpu);
415
416	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
417	RTCCUINTREG fEFlags = ASMIntDisableFlags();
418
419	/* Turn off AMD-V in the EFER MSR. */
420	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
421	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
422
423	/* Invalidate host state physical address. */
424	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
425
426	/* Restore interrupts. */
427	ASMSetFlags(fEFlags);
428
429	return VINF_SUCCESS;
430	}
431
432
433	/**
434	* Does global AMD-V initialization (called during module initialization).
435	*
436	* @returns VBox status code.
437	*/
438	VMMR0DECL(int) SVMR0GlobalInit(void)
439	{
440	/*
441	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
442	* once globally here instead of per-VM.
443	*/
444	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
445	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
446	if (RT_FAILURE(rc))
447	return rc;
448
449	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
450	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
451
452	/* Set all bits to intercept all IO accesses. */
453	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
454	return VINF_SUCCESS;
455	}
456
457
458	/**
459	* Does global AMD-V termination (called during module termination).
460	*/
461	VMMR0DECL(void) SVMR0GlobalTerm(void)
462	{
463	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
464	{
465	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
466	g_pvIOBitmap = NULL;
467	g_HCPhysIOBitmap = 0;
468	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
469	}
470	}
471
472
473	/**
474	* Frees any allocated per-VCPU structures for a VM.
475	*
476	* @param pVM The cross context VM structure.
477	*/
478	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
479	{
480	for (uint32_t i = 0; i < pVM->cCpus; i++)
481	{
482	PVMCPU pVCpu = &pVM->aCpus[i];
483	AssertPtr(pVCpu);
484
485	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
486	{
487	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
488	pVCpu->hm.s.svm.pvVmcbHost = 0;
489	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
490	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
491	}
492
493	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
494	{
495	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
496	pVCpu->hm.s.svm.pvVmcb = 0;
497	pVCpu->hm.s.svm.HCPhysVmcb = 0;
498	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
499	}
500
501	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
502	{
503	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
504	pVCpu->hm.s.svm.pvMsrBitmap = 0;
505	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
506	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
507	}
508	}
509	}
510
511
512	/**
513	* Does per-VM AMD-V initialization.
514	*
515	* @returns VBox status code.
516	* @param pVM The cross context VM structure.
517	*/
518	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
519	{
520	int rc = VERR_INTERNAL_ERROR_5;
521
522	/*
523	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
524	*/
525	uint32_t u32Family;
526	uint32_t u32Model;
527	uint32_t u32Stepping;
528	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
529	{
530	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
531	pVM->hm.s.svm.fAlwaysFlushTLB = true;
532	}
533
534	/*
535	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
536	*/
537	for (VMCPUID i = 0; i < pVM->cCpus; i++)
538	{
539	PVMCPU pVCpu = &pVM->aCpus[i];
540	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
541	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
542	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
543	}
544
545	for (VMCPUID i = 0; i < pVM->cCpus; i++)
546	{
547	PVMCPU pVCpu = &pVM->aCpus[i];
548
549	/*
550	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
551	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
552	*/
553	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
554	if (RT_FAILURE(rc))
555	goto failure_cleanup;
556
557	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
558	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
559	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
560	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
561
562	/*
563	* Allocate one page for the guest-state VMCB.
564	*/
565	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
566	if (RT_FAILURE(rc))
567	goto failure_cleanup;
568
569	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
570	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
571	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
572	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
573
574	/*
575	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
576	* SVM to not require one.
577	*/
578	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
579	if (RT_FAILURE(rc))
580	goto failure_cleanup;
581
582	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
583	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
584	/* Set all bits to intercept all MSR accesses (changed later on). */
585	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, UINT32_C(0xffffffff));
586	}
587
588	return VINF_SUCCESS;
589
590	failure_cleanup:
591	hmR0SvmFreeStructs(pVM);
592	return rc;
593	}
594
595
596	/**
597	* Does per-VM AMD-V termination.
598	*
599	* @returns VBox status code.
600	* @param pVM The cross context VM structure.
601	*/
602	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
603	{
604	hmR0SvmFreeStructs(pVM);
605	return VINF_SUCCESS;
606	}
607
608
609	/**
610	* Sets the permission bits for the specified MSR in the MSRPM.
611	*
612	* @param pVCpu The cross context virtual CPU structure.
613	* @param uMsr The MSR for which the access permissions are being set.
614	* @param enmRead MSR read permissions.
615	* @param enmWrite MSR write permissions.
616	*/
617	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
618	{
619	unsigned uBit;
620	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
621
622	/*
623	* Layout:
624	* Byte offset MSR range
625	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
626	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
627	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
628	* 0x1800 - 0x1fff Reserved
629	*/
630	if (uMsr <= 0x00001FFF)
631	{
632	/* Pentium-compatible MSRs. */
633	uBit = uMsr * 2;
634	}
635	else if ( uMsr >= 0xC0000000
636	&& uMsr <= 0xC0001FFF)
637	{
638	/* AMD Sixth Generation x86 Processor MSRs. */
639	uBit = (uMsr - 0xC0000000) * 2;
640	pbMsrBitmap += 0x800;
641	}
642	else if ( uMsr >= 0xC0010000
643	&& uMsr <= 0xC0011FFF)
644	{
645	/* AMD Seventh and Eighth Generation Processor MSRs. */
646	uBit = (uMsr - 0xC0001000) * 2;
647	pbMsrBitmap += 0x1000;
648	}
649	else
650	{
651	AssertFailed();
652	return;
653	}
654
655	Assert(uBit < 0x3fff /* 16 * 1024 - 1 */);
656	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
657	ASMBitSet(pbMsrBitmap, uBit);
658	else
659	ASMBitClear(pbMsrBitmap, uBit);
660
661	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
662	ASMBitSet(pbMsrBitmap, uBit + 1);
663	else
664	ASMBitClear(pbMsrBitmap, uBit + 1);
665
666	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
667	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
668	}
669
670
671	/**
672	* Sets up AMD-V for the specified VM.
673	* This function is only called once per-VM during initalization.
674	*
675	* @returns VBox status code.
676	* @param pVM The cross context VM structure.
677	*/
678	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
679	{
680	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
681	AssertReturn(pVM, VERR_INVALID_PARAMETER);
682	Assert(pVM->hm.s.svm.fSupported);
683
684	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
685	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
686	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
687
688	for (VMCPUID i = 0; i < pVM->cCpus; i++)
689	{
690	PVMCPU pVCpu = &pVM->aCpus[i];
691	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
692
693	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
694
695	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
696	Assert(!pVCpu->hm.s.idxExitHistoryFree);
697	HMCPU_EXIT_HISTORY_RESET(pVCpu);
698
699	/* Always trap #AC for reasons of security. */
700	pVmcb->ctrl.u32InterceptException \|= RT_BIT_32(X86_XCPT_AC);
701
702	/* Always trap #DB for reasons of security. */
703	pVmcb->ctrl.u32InterceptException \|= RT_BIT_32(X86_XCPT_DB);
704
705	/* Trap exceptions unconditionally (debug purposes). */
706	#ifdef HMSVM_ALWAYS_TRAP_PF
707	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
708	#endif
709	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
710	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
711	pVmcb->ctrl.u32InterceptException \|= 0
712	\| RT_BIT(X86_XCPT_BP)
713	\| RT_BIT(X86_XCPT_DE)
714	\| RT_BIT(X86_XCPT_NM)
715	\| RT_BIT(X86_XCPT_UD)
716	\| RT_BIT(X86_XCPT_NP)
717	\| RT_BIT(X86_XCPT_SS)
718	\| RT_BIT(X86_XCPT_GP)
719	\| RT_BIT(X86_XCPT_PF)
720	\| RT_BIT(X86_XCPT_MF)
721	;
722	#endif
723
724	/* Set up unconditional intercepts and conditions. */
725	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a #VMEXIT. */
726	\| SVM_CTRL1_INTERCEPT_NMI /* Non-maskable interrupts causes a #VMEXIT. */
727	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a #VMEXIT. */
728	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a #VMEXIT. */
729	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a #VMEXIT. */
730	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a #VMEXIT. */
731	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a #VMEXIT. */
732	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO #VMEXITs. */
733	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a #VMEXIT.*/
734	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */
735	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */
736	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
737
738	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a #VMEXIT. */
739	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a #VMEXIT. */
740	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a #VMEXIT. */
741	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a #VMEXIT. */
742	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a #VMEXIT. */
743	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a #VMEXIT. */
744	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a #VMEXIT. */
745	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a #VMEXIT. */
746	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a #VMEXIT. */
747	\| SVM_CTRL2_INTERCEPT_MWAIT /* MWAIT causes a #VMEXIT. */
748	\| SVM_CTRL2_INTERCEPT_XSETBV; /* XSETBV causes a #VMEXIT. */
749
750	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
751	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
752
753	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
754	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
755
756	/* Intercept all DRx reads and writes by default. Changed later on. */
757	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
758	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
759
760	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
761	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
762
763	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
764	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
765	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
766
767	/* Set IO and MSR bitmap permission bitmap physical addresses. */
768	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
769	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
770
771	/* No LBR virtualization. */
772	pVmcb->ctrl.u64LBRVirt = 0;
773
774	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
775	pVmcb->ctrl.u64VmcbCleanBits = 0;
776
777	/* The host ASID MBZ, for the guest start with 1. */
778	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
779
780	/*
781	* Setup the PAT MSR (applicable for Nested Paging only).
782	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
783	* so choose type 6 for all PAT slots.
784	*/
785	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
786
787	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
788	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
789
790	/* Without Nested Paging, we need additionally intercepts. */
791	if (!pVM->hm.s.fNestedPaging)
792	{
793	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
794	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
795	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
796
797	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
798	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
799	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
800
801	/* Page faults must be intercepted to implement shadow paging. */
802	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
803	}
804
805	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
806	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
807	#endif
808
809	/* Apply the exceptions intercepts needed by the GIM provider. */
810	if (pVCpu->hm.s.fGIMTrapXcptUD)
811	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_UD);
812
813	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
814	if (fUsePauseFilter)
815	{
816	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
817	if (fPauseFilterThreshold)
818	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
819	}
820
821	/*
822	* The following MSRs are saved/restored automatically during the world-switch.
823	* Don't intercept guest read/write accesses to these MSRs.
824	*/
825	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
826	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
827	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
828	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
829	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
830	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
831	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
832	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
833	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
834	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
835	}
836
837	return VINF_SUCCESS;
838	}
839
840
841	/**
842	* Invalidates a guest page by guest virtual address.
843	*
844	* @returns VBox status code.
845	* @param pVM The cross context VM structure.
846	* @param pVCpu The cross context virtual CPU structure.
847	* @param GCVirt Guest virtual address of the page to invalidate.
848	*/
849	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
850	{
851	AssertReturn(pVM, VERR_INVALID_PARAMETER);
852	Assert(pVM->hm.s.svm.fSupported);
853
854	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
855
856	/* Skip it if a TLB flush is already pending. */
857	if (!fFlushPending)
858	{
859	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
860
861	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
862	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
863
864	#if HC_ARCH_BITS == 32
865	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
866	if (CPUMIsGuestInLongMode(pVCpu))
867	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
868	else
869	#endif
870	{
871	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
872	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
873	}
874	}
875	return VINF_SUCCESS;
876	}
877
878
879	/**
880	* Flushes the appropriate tagged-TLB entries.
881	*
882	* @param pVCpu The cross context virtual CPU structure.
883	*/
884	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
885	{
886	PVM pVM = pVCpu->CTX_SUFF(pVM);
887	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
888	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
889
890	/*
891	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
892	* This can happen both for start & resume due to long jumps back to ring-3.
893	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
894	* so we cannot reuse the ASIDs without flushing.
895	*/
896	bool fNewAsid = false;
897	Assert(pCpu->idCpu != NIL_RTCPUID);
898	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
899	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
900	{
901	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
902	pVCpu->hm.s.fForceTLBFlush = true;
903	fNewAsid = true;
904	}
905
906	/* Set TLB flush state as checked until we return from the world switch. */
907	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
908
909	/* Check for explicit TLB flushes. */
910	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
911	{
912	pVCpu->hm.s.fForceTLBFlush = true;
913	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
914	}
915
916	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
917
918	if (pVM->hm.s.svm.fAlwaysFlushTLB)
919	{
920	/*
921	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
922	*/
923	pCpu->uCurrentAsid = 1;
924	pVCpu->hm.s.uCurrentAsid = 1;
925	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
926	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
927
928	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
929	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
930	}
931	else if (pVCpu->hm.s.fForceTLBFlush)
932	{
933	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
934	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
935
936	if (fNewAsid)
937	{
938	++pCpu->uCurrentAsid;
939	bool fHitASIDLimit = false;
940	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
941	{
942	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
943	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
944	fHitASIDLimit = true;
945
946	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
947	{
948	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
949	pCpu->fFlushAsidBeforeUse = true;
950	}
951	else
952	{
953	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
954	pCpu->fFlushAsidBeforeUse = false;
955	}
956	}
957
958	if ( !fHitASIDLimit
959	&& pCpu->fFlushAsidBeforeUse)
960	{
961	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
962	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
963	else
964	{
965	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
966	pCpu->fFlushAsidBeforeUse = false;
967	}
968	}
969
970	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
971	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
972	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
973	}
974	else
975	{
976	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
977	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
978	else
979	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
980	}
981
982	pVCpu->hm.s.fForceTLBFlush = false;
983	}
984
985	/* Update VMCB with the ASID. */
986	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
987	{
988	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
989	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
990	}
991
992	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
993	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
994	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
995	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
996	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
997	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
998	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
999	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1000
1001	#ifdef VBOX_WITH_STATISTICS
1002	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1003	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1004	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1005	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1006	{
1007	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1008	}
1009	else
1010	{
1011	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1012	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1013	}
1014	#endif
1015	}
1016
1017
1018	/** @name 64-bit guest on 32-bit host OS helper functions.
1019	*
1020	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1021	* mode (code segment, paging). These wrappers/helpers perform the necessary
1022	* bits for the 32->64 switcher.
1023	*
1024	* @{ */
1025	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1026	/**
1027	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1028	*
1029	* @returns VBox status code.
1030	* @param HCPhysVmcbHost Physical address of host VMCB.
1031	* @param HCPhysVmcb Physical address of the VMCB.
1032	* @param pCtx Pointer to the guest-CPU context.
1033	* @param pVM The cross context VM structure.
1034	* @param pVCpu The cross context virtual CPU structure.
1035	*/
1036	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1037	{
1038	uint32_t aParam[8];
1039	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1040	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
1041	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1042	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
1043	aParam[4] = VM_RC_ADDR(pVM, pVM);
1044	aParam[5] = 0;
1045	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1046	aParam[7] = 0;
1047
1048	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1049	}
1050
1051
1052	/**
1053	* Executes the specified VMRUN handler in 64-bit mode.
1054	*
1055	* @returns VBox status code.
1056	* @param pVM The cross context VM structure.
1057	* @param pVCpu The cross context virtual CPU structure.
1058	* @param pCtx Pointer to the guest-CPU context.
1059	* @param enmOp The operation to perform.
1060	* @param cParams Number of parameters.
1061	* @param paParam Array of 32-bit parameters.
1062	*/
1063	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1064	uint32_t cParams, uint32_t *paParam)
1065	{
1066	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1067	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1068
1069	NOREF(pCtx);
1070
1071	/* Disable interrupts. */
1072	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1073
1074	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1075	RTCPUID idHostCpu = RTMpCpuId();
1076	CPUMR0SetLApic(pVCpu, idHostCpu);
1077	#endif
1078
1079	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1080	CPUMSetHyperEIP(pVCpu, enmOp);
1081	for (int i = (int)cParams - 1; i >= 0; i--)
1082	CPUMPushHyper(pVCpu, paParam[i]);
1083
1084	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1085	/* Call the switcher. */
1086	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1087	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1088
1089	/* Restore interrupts. */
1090	ASMSetFlags(uOldEFlags);
1091	return rc;
1092	}
1093
1094	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1095	/** @} */
1096
1097
1098	/**
1099	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1100	* the corresponding VMCB Clean bit.
1101	*
1102	* @param pVmcb Pointer to the VM control block.
1103	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1104	*/
1105	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1106	{
1107	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1108	{
1109	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1110	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1111	}
1112	}
1113
1114
1115	/**
1116	* Removes an exception from the intercept-exception bitmap in the VMCB and
1117	* updates the corresponding VMCB Clean bit.
1118	*
1119	* @param pVmcb Pointer to the VM control block.
1120	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1121	*/
1122	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1123	{
1124	Assert(u32Xcpt != X86_XCPT_DB);
1125	Assert(u32Xcpt != X86_XCPT_AC);
1126	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1127	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1128	{
1129	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1130	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1131	}
1132	#endif
1133	}
1134
1135
1136	/**
1137	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1138	* Although the guest CR0 is a separate field in the VMCB we have to consider
1139	* the FPU state itself which is shared between the host and the guest.
1140	*
1141	* @returns VBox status code.
1142	* @param pVCpu The cross context virtual CPU structure.
1143	* @param pVmcb Pointer to the VM control block.
1144	* @param pCtx Pointer to the guest-CPU context.
1145	*
1146	* @remarks No-long-jump zone!!!
1147	*/
1148	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1149	{
1150	/*
1151	* Guest CR0.
1152	*/
1153	PVM pVM = pVCpu->CTX_SUFF(pVM);
1154	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1155	{
1156	uint64_t u64GuestCR0 = pCtx->cr0;
1157
1158	/* Always enable caching. */
1159	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1160
1161	/*
1162	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1163	*/
1164	if (!pVM->hm.s.fNestedPaging)
1165	{
1166	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1167	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1168	}
1169
1170	/*
1171	* Guest FPU bits.
1172	*/
1173	bool fInterceptNM = false;
1174	bool fInterceptMF = false;
1175	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1176	if (CPUMIsGuestFPUStateActive(pVCpu))
1177	{
1178	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1179	if (!(pCtx->cr0 & X86_CR0_NE))
1180	{
1181	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1182	fInterceptMF = true;
1183	}
1184	}
1185	else
1186	{
1187	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1188	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1189	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1190	}
1191
1192	/*
1193	* Update the exception intercept bitmap.
1194	*/
1195	if (fInterceptNM)
1196	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1197	else
1198	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1199
1200	if (fInterceptMF)
1201	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1202	else
1203	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1204
1205	pVmcb->guest.u64CR0 = u64GuestCR0;
1206	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1207	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1208	}
1209	}
1210
1211
1212	/**
1213	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1214	*
1215	* @returns VBox status code.
1216	* @param pVCpu The cross context virtual CPU structure.
1217	* @param pVmcb Pointer to the VM control block.
1218	* @param pCtx Pointer to the guest-CPU context.
1219	*
1220	* @remarks No-long-jump zone!!!
1221	*/
1222	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1223	{
1224	PVM pVM = pVCpu->CTX_SUFF(pVM);
1225
1226	/*
1227	* Guest CR2.
1228	*/
1229	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1230	{
1231	pVmcb->guest.u64CR2 = pCtx->cr2;
1232	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1233	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1234	}
1235
1236	/*
1237	* Guest CR3.
1238	*/
1239	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1240	{
1241	if (pVM->hm.s.fNestedPaging)
1242	{
1243	PGMMODE enmShwPagingMode;
1244	#if HC_ARCH_BITS == 32
1245	if (CPUMIsGuestInLongModeEx(pCtx))
1246	enmShwPagingMode = PGMMODE_AMD64_NX;
1247	else
1248	#endif
1249	enmShwPagingMode = PGMGetHostMode(pVM);
1250
1251	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1252	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1253	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1254	pVmcb->guest.u64CR3 = pCtx->cr3;
1255	}
1256	else
1257	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1258
1259	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1260	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1261	}
1262
1263	/*
1264	* Guest CR4.
1265	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1266	*/
1267	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1268	{
1269	uint64_t u64GuestCR4 = pCtx->cr4;
1270	if (!pVM->hm.s.fNestedPaging)
1271	{
1272	switch (pVCpu->hm.s.enmShadowMode)
1273	{
1274	case PGMMODE_REAL:
1275	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1276	AssertFailed();
1277	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1278
1279	case PGMMODE_32_BIT: /* 32-bit paging. */
1280	u64GuestCR4 &= ~X86_CR4_PAE;
1281	break;
1282
1283	case PGMMODE_PAE: /* PAE paging. */
1284	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1285	/** Must use PAE paging as we could use physical memory > 4 GB */
1286	u64GuestCR4 \|= X86_CR4_PAE;
1287	break;
1288
1289	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1290	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1291	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1292	break;
1293	#else
1294	AssertFailed();
1295	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1296	#endif
1297
1298	default: /* shut up gcc */
1299	AssertFailed();
1300	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1301	}
1302	}
1303
1304	pVmcb->guest.u64CR4 = u64GuestCR4;
1305	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1306
1307	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1308	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1309
1310	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1311	}
1312
1313	return VINF_SUCCESS;
1314	}
1315
1316
1317	/**
1318	* Loads the guest segment registers into the VMCB.
1319	*
1320	* @returns VBox status code.
1321	* @param pVCpu The cross context virtual CPU structure.
1322	* @param pVmcb Pointer to the VM control block.
1323	* @param pCtx Pointer to the guest-CPU context.
1324	*
1325	* @remarks No-long-jump zone!!!
1326	*/
1327	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1328	{
1329	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1330	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1331	{
1332	HMSVM_LOAD_SEG_REG(CS, cs);
1333	HMSVM_LOAD_SEG_REG(SS, ss);
1334	HMSVM_LOAD_SEG_REG(DS, ds);
1335	HMSVM_LOAD_SEG_REG(ES, es);
1336	HMSVM_LOAD_SEG_REG(FS, fs);
1337	HMSVM_LOAD_SEG_REG(GS, gs);
1338
1339	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1340	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1341	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1342	}
1343
1344	/* Guest TR. */
1345	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1346	{
1347	HMSVM_LOAD_SEG_REG(TR, tr);
1348	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1349	}
1350
1351	/* Guest LDTR. */
1352	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1353	{
1354	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1355	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1356	}
1357
1358	/* Guest GDTR. */
1359	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1360	{
1361	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1362	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1363	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1364	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1365	}
1366
1367	/* Guest IDTR. */
1368	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1369	{
1370	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1371	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1372	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1373	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1374	}
1375	}
1376
1377
1378	/**
1379	* Loads the guest MSRs into the VMCB.
1380	*
1381	* @param pVCpu The cross context virtual CPU structure.
1382	* @param pVmcb Pointer to the VM control block.
1383	* @param pCtx Pointer to the guest-CPU context.
1384	*
1385	* @remarks No-long-jump zone!!!
1386	*/
1387	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1388	{
1389	/* Guest Sysenter MSRs. */
1390	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1391	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1392	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1393
1394	/*
1395	* Guest EFER MSR.
1396	* AMD-V requires guest EFER.SVME to be set. Weird.
1397	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1398	*/
1399	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1400	{
1401	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1402	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1403	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1404	}
1405
1406	/* 64-bit MSRs. */
1407	if (CPUMIsGuestInLongModeEx(pCtx))
1408	{
1409	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1410	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1411	}
1412	else
1413	{
1414	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1415	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1416	{
1417	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1418	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1419	}
1420	}
1421
1422
1423	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1424	* be writable in 32-bit mode. Clarify with AMD spec. */
1425	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1426	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1427	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1428	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1429	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1430	}
1431
1432
1433	/**
1434	* Loads the guest state into the VMCB and programs the necessary intercepts
1435	* accordingly.
1436	*
1437	* @param pVCpu The cross context virtual CPU structure.
1438	* @param pVmcb Pointer to the VM control block.
1439	* @param pCtx Pointer to the guest-CPU context.
1440	*
1441	* @remarks No-long-jump zone!!!
1442	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1443	*/
1444	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1445	{
1446	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1447	return;
1448	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1449	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1450
1451	bool fInterceptMovDRx = false;
1452
1453	/*
1454	* Anyone single stepping on the host side? If so, we'll have to use the
1455	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1456	* the VMM level like the VT-x implementations does.
1457	*/
1458	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1459	if (fStepping)
1460	{
1461	pVCpu->hm.s.fClearTrapFlag = true;
1462	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1463	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1464	}
1465	else
1466	Assert(!DBGFIsStepping(pVCpu));
1467
1468	if ( fStepping
1469	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1470	{
1471	/*
1472	* Use the combined guest and host DRx values found in the hypervisor
1473	* register set because the debugger has breakpoints active or someone
1474	* is single stepping on the host side.
1475	*
1476	* Note! DBGF expects a clean DR6 state before executing guest code.
1477	*/
1478	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1479	if ( CPUMIsGuestInLongModeEx(pCtx)
1480	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1481	{
1482	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1483	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1484	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1485	}
1486	else
1487	#endif
1488	if (!CPUMIsHyperDebugStateActive(pVCpu))
1489	{
1490	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1491	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1492	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1493	}
1494
1495	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1496	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1497	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1498	{
1499	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1500	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1501	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1502	pVCpu->hm.s.fUsingHyperDR7 = true;
1503	}
1504
1505	/** @todo If we cared, we could optimize to allow the guest to read registers
1506	* with the same values. */
1507	fInterceptMovDRx = true;
1508	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1509	}
1510	else
1511	{
1512	/*
1513	* Update DR6, DR7 with the guest values if necessary.
1514	*/
1515	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1516	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1517	{
1518	pVmcb->guest.u64DR7 = pCtx->dr[7];
1519	pVmcb->guest.u64DR6 = pCtx->dr[6];
1520	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1521	pVCpu->hm.s.fUsingHyperDR7 = false;
1522	}
1523
1524	/*
1525	* If the guest has enabled debug registers, we need to load them prior to
1526	* executing guest code so they'll trigger at the right time.
1527	*/
1528	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1529	{
1530	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1531	if ( CPUMIsGuestInLongModeEx(pCtx)
1532	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1533	{
1534	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1535	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1536	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1537	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1538	}
1539	else
1540	#endif
1541	if (!CPUMIsGuestDebugStateActive(pVCpu))
1542	{
1543	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1544	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1545	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1546	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1547	}
1548	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1549	}
1550	/*
1551	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1552	* intercept #DB as DR6 is updated in the VMCB.
1553	*
1554	* Note! If we cared and dared, we could skip intercepting \#DB here.
1555	* However, \#DB shouldn't be performance critical, so we'll play safe
1556	* and keep the code similar to the VT-x code and always intercept it.
1557	*/
1558	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1559	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1560	&& !CPUMIsGuestDebugStateActive(pVCpu))
1561	#else
1562	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1563	#endif
1564	{
1565	fInterceptMovDRx = true;
1566	}
1567	}
1568
1569	Assert(pVmcb->ctrl.u32InterceptException & RT_BIT_32(X86_XCPT_DB));
1570	if (fInterceptMovDRx)
1571	{
1572	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1573	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1574	{
1575	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1576	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1577	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1578	}
1579	}
1580	else
1581	{
1582	if ( pVmcb->ctrl.u16InterceptRdDRx
1583	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1584	{
1585	pVmcb->ctrl.u16InterceptRdDRx = 0;
1586	pVmcb->ctrl.u16InterceptWrDRx = 0;
1587	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1588	}
1589	}
1590
1591	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1592	}
1593
1594
1595	/**
1596	* Loads the guest APIC state (currently just the TPR).
1597	*
1598	* @returns VBox status code.
1599	* @param pVCpu The cross context virtual CPU structure.
1600	* @param pVmcb Pointer to the VM control block.
1601	* @param pCtx Pointer to the guest-CPU context.
1602	*/
1603	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1604	{
1605	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1606	return VINF_SUCCESS;
1607
1608	bool fPendingIntr;
1609	uint8_t u8Tpr;
1610	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1611	AssertRCReturn(rc, rc);
1612
1613	/* Assume that we need to trap all TPR accesses and thus need not check on
1614	every #VMEXIT if we should update the TPR. */
1615	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1616	pVCpu->hm.s.svm.fSyncVTpr = false;
1617
1618	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1619	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1620	{
1621	pCtx->msrLSTAR = u8Tpr;
1622
1623	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1624	if (fPendingIntr)
1625	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1626	else
1627	{
1628	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1629	pVCpu->hm.s.svm.fSyncVTpr = true;
1630	}
1631	}
1632	else
1633	{
1634	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1635	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1636
1637	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1638	if (fPendingIntr)
1639	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1640	else
1641	{
1642	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1643	pVCpu->hm.s.svm.fSyncVTpr = true;
1644	}
1645
1646	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1647	}
1648
1649	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1650	return rc;
1651	}
1652
1653
1654	/**
1655	* Loads the exception interrupts required for guest execution in the VMCB.
1656	*
1657	* @returns VBox status code.
1658	* @param pVCpu The cross context virtual CPU structure.
1659	* @param pVmcb Pointer to the VM control block.
1660	* @param pCtx Pointer to the guest-CPU context.
1661	*/
1662	static int hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1663	{
1664	int rc = VINF_SUCCESS;
1665	NOREF(pCtx);
1666	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1667	{
1668	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1669	if (pVCpu->hm.s.fGIMTrapXcptUD)
1670	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1671	else
1672	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1673	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1674	}
1675	return rc;
1676	}
1677
1678
1679	/**
1680	* Sets up the appropriate function to run guest code.
1681	*
1682	* @returns VBox status code.
1683	* @param pVCpu The cross context virtual CPU structure.
1684	* @param pCtx Pointer to the guest-CPU context.
1685	*
1686	* @remarks No-long-jump zone!!!
1687	*/
1688	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1689	{
1690	if (CPUMIsGuestInLongModeEx(pCtx))
1691	{
1692	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1693	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1694	#endif
1695	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1696	#if HC_ARCH_BITS == 32
1697	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1698	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1699	#else
1700	/* 64-bit host or hybrid host. */
1701	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1702	#endif
1703	}
1704	else
1705	{
1706	/* Guest is not in long mode, use the 32-bit handler. */
1707	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1708	}
1709	return VINF_SUCCESS;
1710	}
1711
1712
1713	/**
1714	* Enters the AMD-V session.
1715	*
1716	* @returns VBox status code.
1717	* @param pVM The cross context VM structure.
1718	* @param pVCpu The cross context virtual CPU structure.
1719	* @param pCpu Pointer to the CPU info struct.
1720	*/
1721	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1722	{
1723	AssertPtr(pVM);
1724	AssertPtr(pVCpu);
1725	Assert(pVM->hm.s.svm.fSupported);
1726	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1727	NOREF(pVM); NOREF(pCpu);
1728
1729	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1730	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1731
1732	pVCpu->hm.s.fLeaveDone = false;
1733	return VINF_SUCCESS;
1734	}
1735
1736
1737	/**
1738	* Thread-context callback for AMD-V.
1739	*
1740	* @param enmEvent The thread-context event.
1741	* @param pVCpu The cross context virtual CPU structure.
1742	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1743	* @thread EMT(pVCpu)
1744	*/
1745	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1746	{
1747	NOREF(fGlobalInit);
1748
1749	switch (enmEvent)
1750	{
1751	case RTTHREADCTXEVENT_OUT:
1752	{
1753	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1754	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1755	VMCPU_ASSERT_EMT(pVCpu);
1756
1757	PVM pVM = pVCpu->CTX_SUFF(pVM);
1758	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1759
1760	/* No longjmps (log-flush, locks) in this fragile context. */
1761	VMMRZCallRing3Disable(pVCpu);
1762
1763	if (!pVCpu->hm.s.fLeaveDone)
1764	{
1765	hmR0SvmLeave(pVM, pVCpu, pCtx);
1766	pVCpu->hm.s.fLeaveDone = true;
1767	}
1768
1769	/* Leave HM context, takes care of local init (term). */
1770	int rc = HMR0LeaveCpu(pVCpu);
1771	AssertRC(rc); NOREF(rc);
1772
1773	/* Restore longjmp state. */
1774	VMMRZCallRing3Enable(pVCpu);
1775	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
1776	break;
1777	}
1778
1779	case RTTHREADCTXEVENT_IN:
1780	{
1781	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1782	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1783	VMCPU_ASSERT_EMT(pVCpu);
1784
1785	/* No longjmps (log-flush, locks) in this fragile context. */
1786	VMMRZCallRing3Disable(pVCpu);
1787
1788	/*
1789	* Initialize the bare minimum state required for HM. This takes care of
1790	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1791	*/
1792	int rc = HMR0EnterCpu(pVCpu);
1793	AssertRC(rc); NOREF(rc);
1794	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1795
1796	pVCpu->hm.s.fLeaveDone = false;
1797
1798	/* Restore longjmp state. */
1799	VMMRZCallRing3Enable(pVCpu);
1800	break;
1801	}
1802
1803	default:
1804	break;
1805	}
1806	}
1807
1808
1809	/**
1810	* Saves the host state.
1811	*
1812	* @returns VBox status code.
1813	* @param pVM The cross context VM structure.
1814	* @param pVCpu The cross context virtual CPU structure.
1815	*
1816	* @remarks No-long-jump zone!!!
1817	*/
1818	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1819	{
1820	NOREF(pVM);
1821	NOREF(pVCpu);
1822	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1823	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1824	return VINF_SUCCESS;
1825	}
1826
1827
1828	/**
1829	* Loads the guest state into the VMCB.
1830	*
1831	* The CPU state will be loaded from these fields on every successful VM-entry.
1832	* Also sets up the appropriate VMRUN function to execute guest code based on
1833	* the guest CPU mode.
1834	*
1835	* @returns VBox status code.
1836	* @param pVM The cross context VM structure.
1837	* @param pVCpu The cross context virtual CPU structure.
1838	* @param pCtx Pointer to the guest-CPU context.
1839	*
1840	* @remarks No-long-jump zone!!!
1841	*/
1842	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1843	{
1844	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1845	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1846
1847	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1848
1849	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1850	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1851
1852	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1853	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1854
1855	pVmcb->guest.u64RIP = pCtx->rip;
1856	pVmcb->guest.u64RSP = pCtx->rsp;
1857	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1858	pVmcb->guest.u64RAX = pCtx->rax;
1859
1860	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1861	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1862
1863	rc = hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1864	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1865
1866	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1867	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1868
1869	/* Clear any unused and reserved bits. */
1870	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1871	\| HM_CHANGED_GUEST_RSP
1872	\| HM_CHANGED_GUEST_RFLAGS
1873	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1874	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1875	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1876	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1877	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1878	\| HM_CHANGED_SVM_RESERVED2
1879	\| HM_CHANGED_SVM_RESERVED3
1880	\| HM_CHANGED_SVM_RESERVED4);
1881
1882	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1883	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1884	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1885	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1886
1887	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss.Sel, pCtx->rsp));
1888	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1889	return rc;
1890	}
1891
1892
1893	/**
1894	* Loads the state shared between the host and guest into the
1895	* VMCB.
1896	*
1897	* @param pVCpu The cross context virtual CPU structure.
1898	* @param pVmcb Pointer to the VM control block.
1899	* @param pCtx Pointer to the guest-CPU context.
1900	*
1901	* @remarks No-long-jump zone!!!
1902	*/
1903	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1904	{
1905	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1906	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1907
1908	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1909	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1910
1911	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1912	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1913
1914	/* Unused on AMD-V. */
1915	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
1916
1917	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1918	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1919	}
1920
1921
1922	/**
1923	* Saves the entire guest state from the VMCB into the
1924	* guest-CPU context. Currently there is no residual state left in the CPU that
1925	* is not updated in the VMCB.
1926	*
1927	* @returns VBox status code.
1928	* @param pVCpu The cross context virtual CPU structure.
1929	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1930	* out-of-sync. Make sure to update the required fields
1931	* before using them.
1932	*/
1933	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1934	{
1935	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1936
1937	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1938
1939	pMixedCtx->rip = pVmcb->guest.u64RIP;
1940	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1941	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1942	pMixedCtx->rax = pVmcb->guest.u64RAX;
1943
1944	/*
1945	* Guest interrupt shadow.
1946	*/
1947	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1948	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1949	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1950	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1951
1952	/*
1953	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1954	*/
1955	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1956
1957	/*
1958	* Guest MSRs.
1959	*/
1960	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1961	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1962	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1963	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1964	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1965	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1966	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1967	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1968
1969	/*
1970	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1971	*/
1972	HMSVM_SAVE_SEG_REG(CS, cs);
1973	HMSVM_SAVE_SEG_REG(SS, ss);
1974	HMSVM_SAVE_SEG_REG(DS, ds);
1975	HMSVM_SAVE_SEG_REG(ES, es);
1976	HMSVM_SAVE_SEG_REG(FS, fs);
1977	HMSVM_SAVE_SEG_REG(GS, gs);
1978
1979	/*
1980	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1981	* register (yet).
1982	*/
1983	/** @todo SELM might need to be fixed as it too should not care about the
1984	* granularity bit. See @bugref{6785}. */
1985	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1986	&& pMixedCtx->cs.Attr.n.u1Present
1987	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1988	{
1989	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1990	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1991	}
1992
1993	#ifdef VBOX_STRICT
1994	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1995	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1996	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1997	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1998	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1999	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
2000	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
2001
2002	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2003	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2004	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2005	HMSVM_ASSERT_SEG_GRANULARITY(es);
2006	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2007	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2008
2009	# undef HMSVM_ASSERT_SEL_GRANULARITY
2010	#endif
2011
2012	/*
2013	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2014	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2015	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2016	* See AMD spec. 15.5.1 "Basic operation".
2017	*/
2018	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2019	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2020
2021	/*
2022	* Guest TR.
2023	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2024	* between Intel and AMD. See @bugref{6208#c39}.
2025	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2026	*/
2027	HMSVM_SAVE_SEG_REG(TR, tr);
2028	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2029	{
2030	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2031	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2032	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2033	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2034	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2035	}
2036
2037	/*
2038	* Guest Descriptor-Table registers.
2039	*/
2040	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
2041	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2042	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2043
2044	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2045	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2046
2047	/*
2048	* Guest Debug registers.
2049	*/
2050	if (!pVCpu->hm.s.fUsingHyperDR7)
2051	{
2052	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2053	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2054	}
2055	else
2056	{
2057	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2058	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2059	}
2060
2061	/*
2062	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2063	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2064	*/
2065	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
2066	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2067	{
2068	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2069	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2070	}
2071	}
2072
2073
2074	/**
2075	* Does the necessary state syncing before returning to ring-3 for any reason
2076	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2077	*
2078	* @param pVM The cross context VM structure.
2079	* @param pVCpu The cross context virtual CPU structure.
2080	* @param pCtx Pointer to the guest-CPU context.
2081	*
2082	* @remarks No-long-jmp zone!!!
2083	*/
2084	static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2085	{
2086	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2087	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2088	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2089
2090	/*
2091	* !!! IMPORTANT !!!
2092	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2093	*/
2094
2095	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2096	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2097	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2098
2099	/*
2100	* Restore host debug registers if necessary and resync on next R0 reentry.
2101	*/
2102	#ifdef VBOX_STRICT
2103	if (CPUMIsHyperDebugStateActive(pVCpu))
2104	{
2105	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2106	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2107	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2108	}
2109	#endif
2110	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2111	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2112
2113	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2114	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2115
2116	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2117	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2118	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2119	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2120	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2121
2122	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2123	}
2124
2125
2126	/**
2127	* Leaves the AMD-V session.
2128	*
2129	* @returns VBox status code.
2130	* @param pVM The cross context VM structure.
2131	* @param pVCpu The cross context virtual CPU structure.
2132	* @param pCtx Pointer to the guest-CPU context.
2133	*/
2134	static int hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2135	{
2136	HM_DISABLE_PREEMPT();
2137	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2138	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2139
2140	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2141	and done this from the SVMR0ThreadCtxCallback(). */
2142	if (!pVCpu->hm.s.fLeaveDone)
2143	{
2144	hmR0SvmLeave(pVM, pVCpu, pCtx);
2145	pVCpu->hm.s.fLeaveDone = true;
2146	}
2147
2148	/*
2149	* !!! IMPORTANT !!!
2150	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2151	*/
2152
2153	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2154	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2155	VMMR0ThreadCtxHookDisable(pVCpu);
2156
2157	/* Leave HM context. This takes care of local init (term). */
2158	int rc = HMR0LeaveCpu(pVCpu);
2159
2160	HM_RESTORE_PREEMPT();
2161	return rc;
2162	}
2163
2164
2165	/**
2166	* Does the necessary state syncing before doing a longjmp to ring-3.
2167	*
2168	* @returns VBox status code.
2169	* @param pVM The cross context VM structure.
2170	* @param pVCpu The cross context virtual CPU structure.
2171	* @param pCtx Pointer to the guest-CPU context.
2172	*
2173	* @remarks No-long-jmp zone!!!
2174	*/
2175	static int hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2176	{
2177	return hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2178	}
2179
2180
2181	/**
2182	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2183	* any remaining host state) before we longjump to ring-3 and possibly get
2184	* preempted.
2185	*
2186	* @param pVCpu The cross context virtual CPU structure.
2187	* @param enmOperation The operation causing the ring-3 longjump.
2188	* @param pvUser The user argument (pointer to the possibly
2189	* out-of-date guest-CPU context).
2190	*/
2191	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2192	{
2193	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2194	{
2195	/*
2196	* !!! IMPORTANT !!!
2197	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2198	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2199	*/
2200	VMMRZCallRing3RemoveNotification(pVCpu);
2201	VMMRZCallRing3Disable(pVCpu);
2202	HM_DISABLE_PREEMPT();
2203
2204	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2205	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2206
2207	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2208	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2209
2210	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2211	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2212	VMMR0ThreadCtxHookDisable(pVCpu);
2213
2214	/* Leave HM context. This takes care of local init (term). */
2215	HMR0LeaveCpu(pVCpu);
2216
2217	HM_RESTORE_PREEMPT();
2218	return VINF_SUCCESS;
2219	}
2220
2221	Assert(pVCpu);
2222	Assert(pvUser);
2223	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2224	HMSVM_ASSERT_PREEMPT_SAFE();
2225
2226	VMMRZCallRing3Disable(pVCpu);
2227	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2228
2229	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2230	int rc = hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2231	AssertRCReturn(rc, rc);
2232
2233	VMMRZCallRing3Enable(pVCpu);
2234	return VINF_SUCCESS;
2235	}
2236
2237
2238	/**
2239	* Take necessary actions before going back to ring-3.
2240	*
2241	* An action requires us to go back to ring-3. This function does the necessary
2242	* steps before we can safely return to ring-3. This is not the same as longjmps
2243	* to ring-3, this is voluntary.
2244	*
2245	* @param pVM The cross context VM structure.
2246	* @param pVCpu The cross context virtual CPU structure.
2247	* @param pCtx Pointer to the guest-CPU context.
2248	* @param rcExit The reason for exiting to ring-3. Can be
2249	* VINF_VMM_UNKNOWN_RING3_CALL.
2250	*/
2251	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2252	{
2253	Assert(pVM);
2254	Assert(pVCpu);
2255	Assert(pCtx);
2256	HMSVM_ASSERT_PREEMPT_SAFE();
2257
2258	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2259	VMMRZCallRing3Disable(pVCpu);
2260	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2261
2262	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2263	if (pVCpu->hm.s.Event.fPending)
2264	{
2265	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2266	Assert(!pVCpu->hm.s.Event.fPending);
2267	}
2268
2269	/* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2270	and if we're injecting an event we should have a TRPM trap pending. */
2271	AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu), ("rcExit=%Rrc\n", rcExit));
2272	AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu), ("rcExit=%Rrc\n", rcExit));
2273
2274	/* Sync. the necessary state for going back to ring-3. */
2275	hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2276	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2277
2278	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2279	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2280	\| CPUM_CHANGED_LDTR
2281	\| CPUM_CHANGED_GDTR
2282	\| CPUM_CHANGED_IDTR
2283	\| CPUM_CHANGED_TR
2284	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2285	if ( pVM->hm.s.fNestedPaging
2286	&& CPUMIsGuestPagingEnabledEx(pCtx))
2287	{
2288	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2289	}
2290
2291	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2292	if (rcExit != VINF_EM_RAW_INTERRUPT)
2293	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2294
2295	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2296
2297	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2298	VMMRZCallRing3RemoveNotification(pVCpu);
2299	VMMRZCallRing3Enable(pVCpu);
2300	}
2301
2302
2303	/**
2304	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2305	* intercepts.
2306	*
2307	* @param pVM The cross context VM structure.
2308	* @param pVCpu The cross context virtual CPU structure.
2309	*
2310	* @remarks No-long-jump zone!!!
2311	*/
2312	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu)
2313	{
2314	bool fParavirtTsc;
2315	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2316	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2317	if (fCanUseRealTsc)
2318	{
2319	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2320	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2321	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2322	}
2323	else
2324	{
2325	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2326	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2327	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2328	}
2329	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2330
2331	/** @todo later optimize this to be done elsewhere and not before every
2332	* VM-entry. */
2333	if (fParavirtTsc)
2334	{
2335	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2336	information before every VM-entry, hence disable it for performance sake. */
2337	#if 0
2338	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2339	AssertRC(rc);
2340	#endif
2341	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2342	}
2343	}
2344
2345
2346	/**
2347	* Sets an event as a pending event to be injected into the guest.
2348	*
2349	* @param pVCpu The cross context virtual CPU structure.
2350	* @param pEvent Pointer to the SVM event.
2351	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2352	* page-fault.
2353	*
2354	* @remarks Statistics counter assumes this is a guest event being reflected to
2355	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2356	*/
2357	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2358	{
2359	Assert(!pVCpu->hm.s.Event.fPending);
2360	Assert(pEvent->n.u1Valid);
2361
2362	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2363	pVCpu->hm.s.Event.fPending = true;
2364	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2365
2366	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2367	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2368	}
2369
2370
2371	/**
2372	* Injects an event into the guest upon VMRUN by updating the relevant field
2373	* in the VMCB.
2374	*
2375	* @param pVCpu The cross context virtual CPU structure.
2376	* @param pVmcb Pointer to the guest VM control block.
2377	* @param pCtx Pointer to the guest-CPU context.
2378	* @param pEvent Pointer to the event.
2379	*
2380	* @remarks No-long-jump zone!!!
2381	* @remarks Requires CR0!
2382	*/
2383	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2384	{
2385	NOREF(pVCpu); NOREF(pCtx);
2386
2387	pVmcb->ctrl.EventInject.u = pEvent->u;
2388	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2389
2390	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2391	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2392	}
2393
2394
2395
2396	/**
2397	* Converts any TRPM trap into a pending HM event. This is typically used when
2398	* entering from ring-3 (not longjmp returns).
2399	*
2400	* @param pVCpu The cross context virtual CPU structure.
2401	*/
2402	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2403	{
2404	Assert(TRPMHasTrap(pVCpu));
2405	Assert(!pVCpu->hm.s.Event.fPending);
2406
2407	uint8_t uVector;
2408	TRPMEVENT enmTrpmEvent;
2409	RTGCUINT uErrCode;
2410	RTGCUINTPTR GCPtrFaultAddress;
2411	uint8_t cbInstr;
2412
2413	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2414	AssertRC(rc);
2415
2416	SVMEVENT Event;
2417	Event.u = 0;
2418	Event.n.u1Valid = 1;
2419	Event.n.u8Vector = uVector;
2420
2421	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2422	if (enmTrpmEvent == TRPM_TRAP)
2423	{
2424	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2425	switch (uVector)
2426	{
2427	case X86_XCPT_NMI:
2428	{
2429	Event.n.u3Type = SVM_EVENT_NMI;
2430	break;
2431	}
2432
2433	case X86_XCPT_PF:
2434	case X86_XCPT_DF:
2435	case X86_XCPT_TS:
2436	case X86_XCPT_NP:
2437	case X86_XCPT_SS:
2438	case X86_XCPT_GP:
2439	case X86_XCPT_AC:
2440	{
2441	Event.n.u1ErrorCodeValid = 1;
2442	Event.n.u32ErrorCode = uErrCode;
2443	break;
2444	}
2445	}
2446	}
2447	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2448	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2449	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2450	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2451	else
2452	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2453
2454	rc = TRPMResetTrap(pVCpu);
2455	AssertRC(rc);
2456
2457	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2458	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2459
2460	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2461	}
2462
2463
2464	/**
2465	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2466	* AMD-V to execute any instruction.
2467	*
2468	* @param pVCpu The cross context virtual CPU structure.
2469	*/
2470	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2471	{
2472	Assert(pVCpu->hm.s.Event.fPending);
2473	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2474
2475	SVMEVENT Event;
2476	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2477
2478	uint8_t uVector = Event.n.u8Vector;
2479	uint8_t uVectorType = Event.n.u3Type;
2480
2481	TRPMEVENT enmTrapType;
2482	switch (uVectorType)
2483	{
2484	case SVM_EVENT_EXTERNAL_IRQ:
2485	enmTrapType = TRPM_HARDWARE_INT;
2486	break;
2487	case SVM_EVENT_SOFTWARE_INT:
2488	enmTrapType = TRPM_SOFTWARE_INT;
2489	break;
2490	case SVM_EVENT_EXCEPTION:
2491	case SVM_EVENT_NMI:
2492	enmTrapType = TRPM_TRAP;
2493	break;
2494	default:
2495	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2496	enmTrapType = TRPM_32BIT_HACK;
2497	break;
2498	}
2499
2500	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2501
2502	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2503	AssertRC(rc);
2504
2505	if (Event.n.u1ErrorCodeValid)
2506	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2507
2508	if ( uVectorType == SVM_EVENT_EXCEPTION
2509	&& uVector == X86_XCPT_PF)
2510	{
2511	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2512	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2513	}
2514	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2515	{
2516	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2517	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2518	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2519	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2520	}
2521	pVCpu->hm.s.Event.fPending = false;
2522	}
2523
2524
2525	/**
2526	* Gets the guest's interrupt-shadow.
2527	*
2528	* @returns The guest's interrupt-shadow.
2529	* @param pVCpu The cross context virtual CPU structure.
2530	* @param pCtx Pointer to the guest-CPU context.
2531	*
2532	* @remarks No-long-jump zone!!!
2533	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2534	*/
2535	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2536	{
2537	/*
2538	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2539	* inhibit interrupts or clear any existing interrupt-inhibition.
2540	*/
2541	uint32_t uIntrState = 0;
2542	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2543	{
2544	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2545	{
2546	/*
2547	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2548	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2549	*/
2550	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2551	}
2552	else
2553	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2554	}
2555	return uIntrState;
2556	}
2557
2558
2559	/**
2560	* Sets the virtual interrupt intercept control in the VMCB which
2561	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
2562	* receive interrupts.
2563	*
2564	* @param pVmcb Pointer to the VM control block.
2565	*/
2566	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2567	{
2568	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2569	{
2570	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2571	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2572	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2573	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2574
2575	Log4(("Setting VINTR intercept\n"));
2576	}
2577	}
2578
2579
2580	/**
2581	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2582	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
2583	* virtual NMIs.
2584	*
2585	* @param pVmcb Pointer to the VM control block.
2586	*/
2587	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
2588	{
2589	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET))
2590	{
2591	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_IRET;
2592	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2593
2594	Log4(("Setting IRET intercept\n"));
2595	}
2596	}
2597
2598
2599	/**
2600	* Clears the IRET intercept control in the VMCB.
2601	*
2602	* @param pVmcb Pointer to the VM control block.
2603	*/
2604	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
2605	{
2606	if (pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET)
2607	{
2608	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_IRET;
2609	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2610
2611	Log4(("Clearing IRET intercept\n"));
2612	}
2613	}
2614
2615
2616	/**
2617	* Evaluates the event to be delivered to the guest and sets it as the pending
2618	* event.
2619	*
2620	* @param pVCpu The cross context virtual CPU structure.
2621	* @param pCtx Pointer to the guest-CPU context.
2622	*/
2623	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2624	{
2625	Assert(!pVCpu->hm.s.Event.fPending);
2626	Log4Func(("\n"));
2627
2628	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2629	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2630	bool const fBlockNmi = RT_BOOL(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
2631	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2632
2633	#ifdef VBOX_WITH_NEW_APIC
2634	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2635	APICUpdatePendingInterrupts(pVCpu);
2636	#endif
2637
2638	SVMEVENT Event;
2639	Event.u = 0;
2640	/** @todo SMI. SMIs take priority over NMIs. */
2641	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2642	{
2643	if (fBlockNmi)
2644	hmR0SvmSetIretIntercept(pVmcb);
2645	else if (fIntShadow)
2646	hmR0SvmSetVirtIntrIntercept(pVmcb);
2647	else
2648	{
2649	Log4(("Pending NMI\n"));
2650
2651	Event.n.u1Valid = 1;
2652	Event.n.u8Vector = X86_XCPT_NMI;
2653	Event.n.u3Type = SVM_EVENT_NMI;
2654
2655	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2656	hmR0SvmSetIretIntercept(pVmcb);
2657	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2658	}
2659	}
2660	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
2661	&& !pVCpu->hm.s.fSingleInstruction)
2662	{
2663	/*
2664	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
2665	* a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
2666	*/
2667	if ( !fBlockInt
2668	&& !fIntShadow)
2669	{
2670	uint8_t u8Interrupt;
2671	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2672	if (RT_SUCCESS(rc))
2673	{
2674	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2675
2676	Event.n.u1Valid = 1;
2677	Event.n.u8Vector = u8Interrupt;
2678	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2679
2680	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2681	}
2682	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
2683	{
2684	/*
2685	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
2686	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
2687	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
2688	*/
2689	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
2690	}
2691	else
2692	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2693	}
2694	else
2695	hmR0SvmSetVirtIntrIntercept(pVmcb);
2696	}
2697	}
2698
2699
2700	/**
2701	* Injects any pending events into the guest if the guest is in a state to
2702	* receive them.
2703	*
2704	* @param pVCpu The cross context virtual CPU structure.
2705	* @param pCtx Pointer to the guest-CPU context.
2706	*/
2707	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2708	{
2709	Assert(!TRPMHasTrap(pVCpu));
2710	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2711
2712	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2713	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2714	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2715
2716	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2717	{
2718	SVMEVENT Event;
2719	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2720	Assert(Event.n.u1Valid);
2721	#ifdef VBOX_STRICT
2722	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2723	{
2724	Assert(!fBlockInt);
2725	Assert(!fIntShadow);
2726	}
2727	else if (Event.n.u3Type == SVM_EVENT_NMI)
2728	Assert(!fIntShadow);
2729	#endif
2730
2731	Log4(("Injecting pending HM event.\n"));
2732	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2733	pVCpu->hm.s.Event.fPending = false;
2734
2735	#ifdef VBOX_WITH_STATISTICS
2736	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2737	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2738	else
2739	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2740	#endif
2741	}
2742
2743	/* Update the guest interrupt shadow in the VMCB. */
2744	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2745	NOREF(fBlockInt);
2746	}
2747
2748
2749	/**
2750	* Reports world-switch error and dumps some useful debug info.
2751	*
2752	* @param pVM The cross context VM structure.
2753	* @param pVCpu The cross context virtual CPU structure.
2754	* @param rcVMRun The return code from VMRUN (or
2755	* VERR_SVM_INVALID_GUEST_STATE for invalid
2756	* guest-state).
2757	* @param pCtx Pointer to the guest-CPU context.
2758	*/
2759	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2760	{
2761	NOREF(pCtx);
2762	HMSVM_ASSERT_PREEMPT_SAFE();
2763	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2764
2765	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2766	{
2767	HMDumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
2768	#ifdef VBOX_STRICT
2769	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2770	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2771	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2772	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2773	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2774	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2775	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2776	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2777	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2778	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2779	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2780
2781	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2782	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2783	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2784
2785	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2786	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2787	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2788	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2789	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2790	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2791	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2792	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2793	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2794	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2795
2796	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2797	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2798	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2799	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2800	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2801	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2802	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2803	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2804	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2805	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2806	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2807	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2808	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2809	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2810	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2811	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2812	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2813
2814	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2815	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2816
2817	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2818	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2819	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2820	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2821	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2822	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2823	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2824	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2825	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2826	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2827	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2828	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2829	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2830	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2831	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2832	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2833	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2834	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2835	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2836	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2837
2838	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2839	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2840
2841	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2842	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2843	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2844	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2845
2846	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2847	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2848
2849	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2850	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2851	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2852	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2853
2854	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2855	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2856	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2857	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2858	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2859	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2860	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2861
2862	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2863	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2864	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2865	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2866
2867	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2868	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2869	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2870
2871	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2872	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2873	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2874	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2875	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2876	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2877	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2878	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2879	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2880	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2881	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2882	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2883	#endif /* VBOX_STRICT */
2884	}
2885	else
2886	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2887
2888	NOREF(pVmcb);
2889	}
2890
2891
2892	/**
2893	* Check per-VM and per-VCPU force flag actions that require us to go back to
2894	* ring-3 for one reason or another.
2895	*
2896	* @returns VBox status code (information status code included).
2897	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2898	* ring-3.
2899	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2900	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2901	* interrupts)
2902	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2903	* all EMTs to be in ring-3.
2904	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2905	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2906	* to the EM loop.
2907	*
2908	* @param pVM The cross context VM structure.
2909	* @param pVCpu The cross context virtual CPU structure.
2910	* @param pCtx Pointer to the guest-CPU context.
2911	*/
2912	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2913	{
2914	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2915
2916	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2917	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2918	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2919
2920	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2921	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2922	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2923	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2924	{
2925	/* Pending PGM C3 sync. */
2926	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2927	{
2928	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2929	if (rc != VINF_SUCCESS)
2930	{
2931	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2932	return rc;
2933	}
2934	}
2935
2936	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2937	/* -XXX- what was that about single stepping? */
2938	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2939	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2940	{
2941	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2942	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2943	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2944	return rc;
2945	}
2946
2947	/* Pending VM request packets, such as hardware interrupts. */
2948	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2949	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2950	{
2951	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2952	return VINF_EM_PENDING_REQUEST;
2953	}
2954
2955	/* Pending PGM pool flushes. */
2956	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2957	{
2958	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2959	return VINF_PGM_POOL_FLUSH_PENDING;
2960	}
2961
2962	/* Pending DMA requests. */
2963	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2964	{
2965	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2966	return VINF_EM_RAW_TO_R3;
2967	}
2968	}
2969
2970	return VINF_SUCCESS;
2971	}
2972
2973
2974	/**
2975	* Does the preparations before executing guest code in AMD-V.
2976	*
2977	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2978	* recompiler. We must be cautious what we do here regarding committing
2979	* guest-state information into the the VMCB assuming we assuredly execute the
2980	* guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2981	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2982	* that the recompiler can (and should) use them when it resumes guest
2983	* execution. Otherwise such operations must be done when we can no longer
2984	* exit to ring-3.
2985	*
2986	* @returns VBox status code (informational status codes included).
2987	* @retval VINF_SUCCESS if we can proceed with running the guest.
2988	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2989	*
2990	* @param pVM The cross context VM structure.
2991	* @param pVCpu The cross context virtual CPU structure.
2992	* @param pCtx Pointer to the guest-CPU context.
2993	* @param pSvmTransient Pointer to the SVM transient structure.
2994	*/
2995	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2996	{
2997	HMSVM_ASSERT_PREEMPT_SAFE();
2998
2999	/* Check force flag actions that might require us to go back to ring-3. */
3000	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3001	if (rc != VINF_SUCCESS)
3002	return rc;
3003
3004	if (TRPMHasTrap(pVCpu))
3005	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3006	else if (!pVCpu->hm.s.Event.fPending)
3007	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
3008
3009	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
3010	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3011	#endif
3012
3013	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3014	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3015	AssertRCReturn(rc, rc);
3016	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3017
3018	/*
3019	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3020	* so we can update it on the way back if the guest changed the TPR.
3021	*/
3022	if (pVCpu->hm.s.svm.fSyncVTpr)
3023	{
3024	if (pVM->hm.s.fTPRPatchingActive)
3025	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3026	else
3027	{
3028	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3029	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3030	}
3031	}
3032
3033	/*
3034	* No longjmps to ring-3 from this point on!!!
3035	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3036	* This also disables flushing of the R0-logger instance (if any).
3037	*/
3038	VMMRZCallRing3Disable(pVCpu);
3039
3040	/*
3041	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3042	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3043	*
3044	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3045	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3046	*
3047	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3048	* executing guest code.
3049	*/
3050	pSvmTransient->fEFlags = ASMIntDisableFlags();
3051	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3052	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3053	{
3054	ASMSetFlags(pSvmTransient->fEFlags);
3055	VMMRZCallRing3Enable(pVCpu);
3056	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3057	return VINF_EM_RAW_TO_R3;
3058	}
3059	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3060	{
3061	ASMSetFlags(pSvmTransient->fEFlags);
3062	VMMRZCallRing3Enable(pVCpu);
3063	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3064	return VINF_EM_RAW_INTERRUPT;
3065	}
3066
3067	/*
3068	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3069	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3070	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3071	*
3072	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3073	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3074	*/
3075	if (pVCpu->hm.s.Event.fPending)
3076	{
3077	SVMEVENT Event;
3078	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3079	if ( Event.n.u1Valid
3080	&& Event.n.u3Type == SVM_EVENT_NMI
3081	&& Event.n.u8Vector == X86_XCPT_NMI
3082	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3083	{
3084	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3085	}
3086	}
3087
3088	return VINF_SUCCESS;
3089	}
3090
3091
3092	/**
3093	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3094	* means there is no backing out to ring-3 or anywhere else at this
3095	* point.
3096	*
3097	* @param pVM The cross context VM structure.
3098	* @param pVCpu The cross context virtual CPU structure.
3099	* @param pCtx Pointer to the guest-CPU context.
3100	* @param pSvmTransient Pointer to the SVM transient structure.
3101	*
3102	* @remarks Called with preemption disabled.
3103	* @remarks No-long-jump zone!!!
3104	*/
3105	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3106	{
3107	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3108	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3109	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3110
3111	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3112	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3113
3114	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
3115
3116	if ( pVCpu->hm.s.fPreloadGuestFpu
3117	&& !CPUMIsGuestFPUStateActive(pVCpu))
3118	{
3119	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3120	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3121	}
3122
3123	/* Load the state shared between host and guest (FPU, debug). */
3124	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3125	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3126	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3127	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3128	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3129
3130	/* Setup TSC offsetting. */
3131	RTCPUID idCurrentCpu = HMR0GetCurrentCpu()->idCpu;
3132	if ( pSvmTransient->fUpdateTscOffsetting
3133	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3134	{
3135	hmR0SvmUpdateTscOffsetting(pVM, pVCpu);
3136	pSvmTransient->fUpdateTscOffsetting = false;
3137	}
3138
3139	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3140	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3141	pVmcb->ctrl.u64VmcbCleanBits = 0;
3142
3143	/* Store status of the shared guest-host state at the time of VMRUN. */
3144	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3145	if (CPUMIsGuestInLongModeEx(pCtx))
3146	{
3147	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3148	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3149	}
3150	else
3151	#endif
3152	{
3153	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3154	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3155	}
3156	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3157
3158	/* Flush the appropriate tagged-TLB entries. */
3159	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3160	hmR0SvmFlushTaggedTlb(pVCpu);
3161	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3162
3163	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3164
3165	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3166	to start executing. */
3167
3168	/*
3169	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3170	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3171	*
3172	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3173	*/
3174	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3175	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
3176	{
3177	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3178	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3179	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3180	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3181	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3182	pSvmTransient->fRestoreTscAuxMsr = true;
3183	}
3184	else
3185	{
3186	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3187	pSvmTransient->fRestoreTscAuxMsr = false;
3188	}
3189
3190	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
3191	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
3192	pVmcb->ctrl.u64VmcbCleanBits = 0;
3193	}
3194
3195
3196	/**
3197	* Wrapper for running the guest code in AMD-V.
3198	*
3199	* @returns VBox strict status code.
3200	* @param pVM The cross context VM structure.
3201	* @param pVCpu The cross context virtual CPU structure.
3202	* @param pCtx Pointer to the guest-CPU context.
3203	*
3204	* @remarks No-long-jump zone!!!
3205	*/
3206	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3207	{
3208	/*
3209	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
3210	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3211	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3212	*/
3213	#ifdef VBOX_WITH_KERNEL_USING_XMM
3214	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3215	pVCpu->hm.s.svm.pfnVMRun);
3216	#else
3217	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3218	#endif
3219	}
3220
3221
3222	/**
3223	* Performs some essential restoration of state after running guest code in
3224	* AMD-V.
3225	*
3226	* @param pVM The cross context VM structure.
3227	* @param pVCpu The cross context virtual CPU structure.
3228	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3229	* out-of-sync. Make sure to update the required fields
3230	* before using them.
3231	* @param pSvmTransient Pointer to the SVM transient structure.
3232	* @param rcVMRun Return code of VMRUN.
3233	*
3234	* @remarks Called with interrupts disabled.
3235	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
3236	* unconditionally when it is safe to do so.
3237	*/
3238	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3239	{
3240	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3241
3242	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
3243	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
3244
3245	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3246	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3247
3248	if (pSvmTransient->fRestoreTscAuxMsr)
3249	{
3250	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
3251	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
3252	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
3253	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3254	}
3255
3256	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
3257	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
3258
3259	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3260	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3261	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3262
3263	Assert(!(ASMGetFlags() & X86_EFL_IF));
3264	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
3265	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3266
3267	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3268	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3269	{
3270	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3271	return;
3272	}
3273
3274	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3275	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
3276	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
3277	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3278
3279	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3280
3281	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
3282	{
3283	if (pVCpu->hm.s.svm.fSyncVTpr)
3284	{
3285	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3286	if ( pVM->hm.s.fTPRPatchingActive
3287	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3288	{
3289	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3290	AssertRC(rc);
3291	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3292	}
3293	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3294	{
3295	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3296	AssertRC(rc);
3297	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3298	}
3299	}
3300	}
3301	}
3302
3303
3304	/**
3305	* Runs the guest code using AMD-V.
3306	*
3307	* @returns VBox status code.
3308	* @param pVM The cross context VM structure.
3309	* @param pVCpu The cross context virtual CPU structure.
3310	* @param pCtx Pointer to the guest-CPU context.
3311	*/
3312	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3313	{
3314	SVMTRANSIENT SvmTransient;
3315	SvmTransient.fUpdateTscOffsetting = true;
3316	uint32_t cLoops = 0;
3317	int rc = VERR_INTERNAL_ERROR_5;
3318
3319	for (;; cLoops++)
3320	{
3321	Assert(!HMR0SuspendPending());
3322	HMSVM_ASSERT_CPU_SAFE();
3323
3324	/* Preparatory work for running guest code, this may force us to return
3325	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3326	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3327	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3328	if (rc != VINF_SUCCESS)
3329	break;
3330
3331	/*
3332	* No longjmps to ring-3 from this point on!!!
3333	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3334	* This also disables flushing of the R0-logger instance (if any).
3335	*/
3336	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3337	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3338
3339	/* Restore any residual host-state and save any bits shared between host
3340	and guest into the guest-CPU state. Re-enables interrupts! */
3341	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3342
3343	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3344	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3345	{
3346	if (rc == VINF_SUCCESS)
3347	rc = VERR_SVM_INVALID_GUEST_STATE;
3348	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3349	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3350	break;
3351	}
3352
3353	/* Handle the #VMEXIT. */
3354	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3355	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3356	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3357	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3358	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3359	if (rc != VINF_SUCCESS)
3360	break;
3361	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3362	{
3363	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3364	rc = VINF_EM_RAW_INTERRUPT;
3365	break;
3366	}
3367	}
3368
3369	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3370	return rc;
3371	}
3372
3373
3374	/**
3375	* Runs the guest code using AMD-V in single step mode.
3376	*
3377	* @returns VBox status code.
3378	* @param pVM The cross context VM structure.
3379	* @param pVCpu The cross context virtual CPU structure.
3380	* @param pCtx Pointer to the guest-CPU context.
3381	*/
3382	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3383	{
3384	SVMTRANSIENT SvmTransient;
3385	SvmTransient.fUpdateTscOffsetting = true;
3386	uint32_t cLoops = 0;
3387	int rc = VERR_INTERNAL_ERROR_5;
3388	uint16_t uCsStart = pCtx->cs.Sel;
3389	uint64_t uRipStart = pCtx->rip;
3390
3391	for (;; cLoops++)
3392	{
3393	Assert(!HMR0SuspendPending());
3394	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
3395	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
3396	(unsigned)RTMpCpuId(), cLoops));
3397
3398	/* Preparatory work for running guest code, this may force us to return
3399	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3400	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3401	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3402	if (rc != VINF_SUCCESS)
3403	break;
3404
3405	/*
3406	* No longjmps to ring-3 from this point on!!!
3407	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3408	* This also disables flushing of the R0-logger instance (if any).
3409	*/
3410	VMMRZCallRing3Disable(pVCpu);
3411	VMMRZCallRing3RemoveNotification(pVCpu);
3412	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3413
3414	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3415
3416	/*
3417	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3418	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3419	*/
3420	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3421	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3422	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3423	{
3424	if (rc == VINF_SUCCESS)
3425	rc = VERR_SVM_INVALID_GUEST_STATE;
3426	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3427	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3428	return rc;
3429	}
3430
3431	/* Handle the #VMEXIT. */
3432	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3433	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3434	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3435	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3436	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3437	if (rc != VINF_SUCCESS)
3438	break;
3439	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3440	{
3441	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3442	rc = VINF_EM_RAW_INTERRUPT;
3443	break;
3444	}
3445
3446	/*
3447	* Did the RIP change, if so, consider it a single step.
3448	* Otherwise, make sure one of the TFs gets set.
3449	*/
3450	if ( pCtx->rip != uRipStart
3451	\|\| pCtx->cs.Sel != uCsStart)
3452	{
3453	rc = VINF_EM_DBG_STEPPED;
3454	break;
3455	}
3456	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3457	}
3458
3459	/*
3460	* Clear the X86_EFL_TF if necessary.
3461	*/
3462	if (pVCpu->hm.s.fClearTrapFlag)
3463	{
3464	pVCpu->hm.s.fClearTrapFlag = false;
3465	pCtx->eflags.Bits.u1TF = 0;
3466	}
3467
3468	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3469	return rc;
3470	}
3471
3472
3473	/**
3474	* Runs the guest code using AMD-V.
3475	*
3476	* @returns Strict VBox status code.
3477	* @param pVM The cross context VM structure.
3478	* @param pVCpu The cross context virtual CPU structure.
3479	* @param pCtx Pointer to the guest-CPU context.
3480	*/
3481	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3482	{
3483	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3484	HMSVM_ASSERT_PREEMPT_SAFE();
3485	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3486
3487	int rc;
3488	if (!pVCpu->hm.s.fSingleInstruction)
3489	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx);
3490	else
3491	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx);
3492
3493	if (rc == VERR_EM_INTERPRETER)
3494	rc = VINF_EM_RAW_EMULATE_INSTR;
3495	else if (rc == VINF_EM_RESET)
3496	rc = VINF_EM_TRIPLE_FAULT;
3497
3498	/* Prepare to return to ring-3. This will remove longjmp notifications. */
3499	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3500	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3501	return rc;
3502	}
3503
3504
3505	/**
3506	* Handles a \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3507	*
3508	* @returns VBox status code (informational status codes included).
3509	* @param pVCpu The cross context virtual CPU structure.
3510	* @param pCtx Pointer to the guest-CPU context.
3511	* @param pSvmTransient Pointer to the SVM transient structure.
3512	*/
3513	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3514	{
3515	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3516	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3517
3518	/*
3519	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
3520	* normal workloads (for some definition of "normal").
3521	*/
3522	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3523	switch (pSvmTransient->u64ExitCode)
3524	{
3525	case SVM_EXIT_NPF:
3526	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3527
3528	case SVM_EXIT_IOIO:
3529	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3530
3531	case SVM_EXIT_RDTSC:
3532	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3533
3534	case SVM_EXIT_RDTSCP:
3535	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3536
3537	case SVM_EXIT_CPUID:
3538	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3539
3540	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3541	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3542
3543	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3544	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3545
3546	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3547	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
3548
3549	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3550	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3551
3552	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3553	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3554
3555	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3556	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
3557
3558	case SVM_EXIT_MONITOR:
3559	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3560
3561	case SVM_EXIT_MWAIT:
3562	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3563
3564	case SVM_EXIT_HLT:
3565	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3566
3567	case SVM_EXIT_READ_CR0:
3568	case SVM_EXIT_READ_CR3:
3569	case SVM_EXIT_READ_CR4:
3570	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3571
3572	case SVM_EXIT_WRITE_CR0:
3573	case SVM_EXIT_WRITE_CR3:
3574	case SVM_EXIT_WRITE_CR4:
3575	case SVM_EXIT_WRITE_CR8:
3576	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3577
3578	case SVM_EXIT_PAUSE:
3579	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
3580
3581	case SVM_EXIT_VMMCALL:
3582	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3583
3584	case SVM_EXIT_VINTR:
3585	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3586
3587	case SVM_EXIT_INTR:
3588	case SVM_EXIT_FERR_FREEZE:
3589	case SVM_EXIT_NMI:
3590	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3591
3592	case SVM_EXIT_MSR:
3593	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3594
3595	case SVM_EXIT_INVLPG:
3596	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3597
3598	case SVM_EXIT_WBINVD:
3599	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3600
3601	case SVM_EXIT_INVD:
3602	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3603
3604	case SVM_EXIT_RDPMC:
3605	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3606
3607	default:
3608	{
3609	switch (pSvmTransient->u64ExitCode)
3610	{
3611	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3612	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3613	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3614	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3615	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3616
3617	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3618	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3619	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3620	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3621	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3622
3623	case SVM_EXIT_XSETBV:
3624	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
3625
3626	case SVM_EXIT_TASK_SWITCH:
3627	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3628
3629	case SVM_EXIT_IRET:
3630	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
3631
3632	case SVM_EXIT_SHUTDOWN:
3633	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3634
3635	case SVM_EXIT_SMI:
3636	case SVM_EXIT_INIT:
3637	{
3638	/*
3639	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3640	* we want to know about it so log the exit code and bail.
3641	*/
3642	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3643	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3644	return VERR_SVM_UNEXPECTED_EXIT;
3645	}
3646
3647	case SVM_EXIT_INVLPGA:
3648	case SVM_EXIT_RSM:
3649	case SVM_EXIT_VMRUN:
3650	case SVM_EXIT_VMLOAD:
3651	case SVM_EXIT_VMSAVE:
3652	case SVM_EXIT_STGI:
3653	case SVM_EXIT_CLGI:
3654	case SVM_EXIT_SKINIT:
3655	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3656
3657	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3658	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3659	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3660	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3661	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3662	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3663	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3664	/* case SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
3665	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3666	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3667	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3668	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3669	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3670	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3671	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3672	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3673	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3674	/* SVM_EXIT_EXCEPTION_11: / / X86_XCPT_AC - Handled above. */
3675	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3676	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3677	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3678	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3679	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3680	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3681	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3682	{
3683	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3684	SVMEVENT Event;
3685	Event.u = 0;
3686	Event.n.u1Valid = 1;
3687	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3688	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3689
3690	switch (Event.n.u8Vector)
3691	{
3692	case X86_XCPT_DE:
3693	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3694	break;
3695
3696	case X86_XCPT_BP:
3697	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3698	* next instruction. */
3699	/** @todo Investigate this later. */
3700	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3701	break;
3702
3703	case X86_XCPT_NP:
3704	Event.n.u1ErrorCodeValid = 1;
3705	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3706	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3707	break;
3708
3709	case X86_XCPT_SS:
3710	Event.n.u1ErrorCodeValid = 1;
3711	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3712	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3713	break;
3714
3715	case X86_XCPT_GP:
3716	Event.n.u1ErrorCodeValid = 1;
3717	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3718	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3719	break;
3720
3721	default:
3722	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3723	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3724	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3725	}
3726
3727	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3728	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3729	return VINF_SUCCESS;
3730	}
3731	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3732
3733	default:
3734	{
3735	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3736	pVCpu->hm.s.u32HMError = u32ExitCode;
3737	return VERR_SVM_UNKNOWN_EXIT;
3738	}
3739	}
3740	}
3741	}
3742	return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3743	}
3744
3745
3746	#ifdef DEBUG
3747	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3748	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3749	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3750
3751	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3752	do \
3753	{ \
3754	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3755	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3756	} while (0)
3757
3758	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3759	do { \
3760	AssertPtr(pVCpu); \
3761	AssertPtr(pCtx); \
3762	AssertPtr(pSvmTransient); \
3763	Assert(ASMIntAreEnabled()); \
3764	HMSVM_ASSERT_PREEMPT_SAFE(); \
3765	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3766	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3767	HMSVM_ASSERT_PREEMPT_SAFE(); \
3768	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3769	HMSVM_ASSERT_PREEMPT_CPUID(); \
3770	} while (0)
3771	#else /* Release builds */
3772	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
3773	#endif
3774
3775
3776	/**
3777	* Worker for hmR0SvmInterpretInvlpg().
3778	*
3779	* @return VBox status code.
3780	* @param pVCpu The cross context virtual CPU structure.
3781	* @param pCpu Pointer to the disassembler state.
3782	* @param pCtx The guest CPU context.
3783	*/
3784	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
3785	{
3786	DISQPVPARAMVAL Param1;
3787	RTGCPTR GCPtrPage;
3788
3789	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3790	if (RT_FAILURE(rc))
3791	return VERR_EM_INTERPRETER;
3792
3793	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3794	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3795	{
3796	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3797	return VERR_EM_INTERPRETER;
3798
3799	GCPtrPage = Param1.val.val64;
3800	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
3801	rc = VBOXSTRICTRC_VAL(rc2);
3802	}
3803	else
3804	{
3805	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3806	rc = VERR_EM_INTERPRETER;
3807	}
3808
3809	return rc;
3810	}
3811
3812
3813	/**
3814	* Interprets INVLPG.
3815	*
3816	* @returns VBox status code.
3817	* @retval VINF_* Scheduling instructions.
3818	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3819	* @retval VERR_* Fatal errors.
3820	*
3821	* @param pVM The cross context VM structure.
3822	* @param pVCpu The cross context virtual CPU structure.
3823	* @param pCtx The guest CPU context.
3824	*
3825	* @remarks Updates the RIP if the instruction was executed successfully.
3826	*/
3827	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3828	{
3829	/* Only allow 32 & 64 bit code. */
3830	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3831	{
3832	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3833	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3834	if ( RT_SUCCESS(rc)
3835	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3836	{
3837	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
3838	if (RT_SUCCESS(rc))
3839	pCtx->rip += pDis->cbInstr;
3840	return rc;
3841	}
3842	else
3843	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3844	}
3845	return VERR_EM_INTERPRETER;
3846	}
3847
3848
3849	/**
3850	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3851	*
3852	* @param pVCpu The cross context virtual CPU structure.
3853	*/
3854	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3855	{
3856	SVMEVENT Event;
3857	Event.u = 0;
3858	Event.n.u1Valid = 1;
3859	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3860	Event.n.u8Vector = X86_XCPT_UD;
3861	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3862	}
3863
3864
3865	/**
3866	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3867	*
3868	* @param pVCpu The cross context virtual CPU structure.
3869	*/
3870	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3871	{
3872	SVMEVENT Event;
3873	Event.u = 0;
3874	Event.n.u1Valid = 1;
3875	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3876	Event.n.u8Vector = X86_XCPT_DB;
3877	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3878	}
3879
3880
3881	/**
3882	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3883	*
3884	* @param pVCpu The cross context virtual CPU structure.
3885	* @param pCtx Pointer to the guest-CPU context.
3886	* @param u32ErrCode The error-code for the page-fault.
3887	* @param uFaultAddress The page fault address (CR2).
3888	*
3889	* @remarks This updates the guest CR2 with @a uFaultAddress!
3890	*/
3891	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3892	{
3893	SVMEVENT Event;
3894	Event.u = 0;
3895	Event.n.u1Valid = 1;
3896	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3897	Event.n.u8Vector = X86_XCPT_PF;
3898	Event.n.u1ErrorCodeValid = 1;
3899	Event.n.u32ErrorCode = u32ErrCode;
3900
3901	/* Update CR2 of the guest. */
3902	if (pCtx->cr2 != uFaultAddress)
3903	{
3904	pCtx->cr2 = uFaultAddress;
3905	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3906	}
3907
3908	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3909	}
3910
3911
3912	/**
3913	* Sets a device-not-available (\#NM) exception as pending-for-injection into
3914	* the VM.
3915	*
3916	* @param pVCpu The cross context virtual CPU structure.
3917	*/
3918	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3919	{
3920	SVMEVENT Event;
3921	Event.u = 0;
3922	Event.n.u1Valid = 1;
3923	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3924	Event.n.u8Vector = X86_XCPT_NM;
3925	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3926	}
3927
3928
3929	/**
3930	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3931	*
3932	* @param pVCpu The cross context virtual CPU structure.
3933	*/
3934	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3935	{
3936	SVMEVENT Event;
3937	Event.u = 0;
3938	Event.n.u1Valid = 1;
3939	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3940	Event.n.u8Vector = X86_XCPT_MF;
3941	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3942	}
3943
3944
3945	/**
3946	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3947	*
3948	* @param pVCpu The cross context virtual CPU structure.
3949	*/
3950	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3951	{
3952	SVMEVENT Event;
3953	Event.u = 0;
3954	Event.n.u1Valid = 1;
3955	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3956	Event.n.u8Vector = X86_XCPT_DF;
3957	Event.n.u1ErrorCodeValid = 1;
3958	Event.n.u32ErrorCode = 0;
3959	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3960	}
3961
3962
3963	/**
3964	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3965	* guests. This simply looks up the patch record at EIP and does the required.
3966	*
3967	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3968	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3969	* TPR). See hmR3ReplaceTprInstr() for the details.
3970	*
3971	* @returns VBox status code.
3972	* @retval VINF_SUCCESS if the access was handled successfully.
3973	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
3974	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
3975	*
3976	* @param pVM The cross context VM structure.
3977	* @param pVCpu The cross context virtual CPU structure.
3978	* @param pCtx Pointer to the guest-CPU context.
3979	*/
3980	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3981	{
3982	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3983
3984	/*
3985	* We do this in a loop as we increment the RIP after a successful emulation
3986	* and the new RIP may be a patched instruction which needs emulation as well.
3987	*/
3988	bool fPatchFound = false;
3989	for (;;)
3990	{
3991	bool fPending;
3992	uint8_t u8Tpr;
3993
3994	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3995	if (!pPatch)
3996	break;
3997
3998	fPatchFound = true;
3999	switch (pPatch->enmType)
4000	{
4001	case HMTPRINSTR_READ:
4002	{
4003	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
4004	AssertRC(rc);
4005
4006	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
4007	AssertRC(rc);
4008	pCtx->rip += pPatch->cbOp;
4009	break;
4010	}
4011
4012	case HMTPRINSTR_WRITE_REG:
4013	case HMTPRINSTR_WRITE_IMM:
4014	{
4015	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
4016	{
4017	uint32_t u32Val;
4018	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
4019	AssertRC(rc);
4020	u8Tpr = u32Val;
4021	}
4022	else
4023	u8Tpr = (uint8_t)pPatch->uSrcOperand;
4024
4025	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
4026	AssertRC(rc2);
4027	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4028
4029	pCtx->rip += pPatch->cbOp;
4030	break;
4031	}
4032
4033	default:
4034	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
4035	pVCpu->hm.s.u32HMError = pPatch->enmType;
4036	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
4037	}
4038	}
4039
4040	if (fPatchFound)
4041	return VINF_SUCCESS;
4042	return VERR_NOT_FOUND;
4043	}
4044
4045
4046	/**
4047	* Determines if an exception is a contributory exception.
4048	*
4049	* Contributory exceptions are ones which can cause double-faults unless the
4050	* original exception was a benign exception. Page-fault is intentionally not
4051	* included here as it's a conditional contributory exception.
4052	*
4053	* @returns true if the exception is contributory, false otherwise.
4054	* @param uVector The exception vector.
4055	*/
4056	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
4057	{
4058	switch (uVector)
4059	{
4060	case X86_XCPT_GP:
4061	case X86_XCPT_SS:
4062	case X86_XCPT_NP:
4063	case X86_XCPT_TS:
4064	case X86_XCPT_DE:
4065	return true;
4066	default:
4067	break;
4068	}
4069	return false;
4070	}
4071
4072
4073	/**
4074	* Handle a condition that occurred while delivering an event through the guest
4075	* IDT.
4076	*
4077	* @returns VBox status code (informational error codes included).
4078	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
4079	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
4080	* continue execution of the guest which will delivery the \#DF.
4081	* @retval VINF_EM_RESET if we detected a triple-fault condition.
4082	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
4083	*
4084	* @param pVCpu The cross context virtual CPU structure.
4085	* @param pCtx Pointer to the guest-CPU context.
4086	* @param pSvmTransient Pointer to the SVM transient structure.
4087	*
4088	* @remarks No-long-jump zone!!!
4089	*/
4090	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4091	{
4092	int rc = VINF_SUCCESS;
4093	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4094
4095	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
4096	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
4097	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
4098	{
4099	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4100
4101	typedef enum
4102	{
4103	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4104	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4105	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4106	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
4107	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
4108	} SVMREFLECTXCPT;
4109
4110	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
4111	bool fReflectingNmi = false;
4112	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
4113	{
4114	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4115	{
4116	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4117
4118	#ifdef VBOX_STRICT
4119	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
4120	&& uExitVector == X86_XCPT_PF)
4121	{
4122	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
4123	}
4124	#endif
4125
4126	if ( uIdtVector == X86_XCPT_BP
4127	\|\| uIdtVector == X86_XCPT_OF)
4128	{
4129	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
4130	}
4131	else if ( uExitVector == X86_XCPT_PF
4132	&& uIdtVector == X86_XCPT_PF)
4133	{
4134	pSvmTransient->fVectoringDoublePF = true;
4135	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
4136	}
4137	else if ( uExitVector == X86_XCPT_AC
4138	&& uIdtVector == X86_XCPT_AC)
4139	{
4140	enmReflect = SVMREFLECTXCPT_HANG;
4141	Log4(("IDT: Nested #AC - Bad guest\n"));
4142	}
4143	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
4144	&& hmR0SvmIsContributoryXcpt(uExitVector)
4145	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
4146	\|\| uIdtVector == X86_XCPT_PF))
4147	{
4148	enmReflect = SVMREFLECTXCPT_DF;
4149	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
4150	uIdtVector, uExitVector));
4151	}
4152	else if (uIdtVector == X86_XCPT_DF)
4153	{
4154	enmReflect = SVMREFLECTXCPT_TF;
4155	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
4156	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
4157	}
4158	else
4159	enmReflect = SVMREFLECTXCPT_XCPT;
4160	}
4161	else
4162	{
4163	/*
4164	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
4165	* exception to the guest after handling the #VMEXIT.
4166	*/
4167	enmReflect = SVMREFLECTXCPT_XCPT;
4168	}
4169	}
4170	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
4171	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4172	{
4173	enmReflect = SVMREFLECTXCPT_XCPT;
4174	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
4175
4176	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4177	{
4178	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4179	if (uExitVector == X86_XCPT_PF)
4180	{
4181	pSvmTransient->fVectoringPF = true;
4182	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
4183	}
4184	}
4185	}
4186	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
4187
4188	switch (enmReflect)
4189	{
4190	case SVMREFLECTXCPT_XCPT:
4191	{
4192	/* If we are re-injecting the NMI, clear NMI blocking. */
4193	if (fReflectingNmi)
4194	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4195
4196	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4197	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4198	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
4199
4200	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
4201	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
4202	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4203	break;
4204	}
4205
4206	case SVMREFLECTXCPT_DF:
4207	{
4208	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4209	hmR0SvmSetPendingXcptDF(pVCpu);
4210	rc = VINF_HM_DOUBLE_FAULT;
4211	break;
4212	}
4213
4214	case SVMREFLECTXCPT_TF:
4215	{
4216	rc = VINF_EM_RESET;
4217	break;
4218	}
4219
4220	case SVMREFLECTXCPT_HANG:
4221	{
4222	rc = VERR_EM_GUEST_CPU_HANG;
4223	break;
4224	}
4225
4226	default:
4227	Assert(rc == VINF_SUCCESS);
4228	break;
4229	}
4230	}
4231	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
4232	NOREF(pCtx);
4233	return rc;
4234	}
4235
4236	/**
4237	* Updates interrupt shadow for the current RIP.
4238	*/
4239	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
4240	do { \
4241	/* Update interrupt shadow. */ \
4242	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
4243	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
4244	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
4245	} while (0)
4246
4247	/**
4248	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
4249	* supported, otherwise advances the RIP by the number of bytes specified in
4250	* @a cb.
4251	*
4252	* @param pVCpu The cross context virtual CPU structure.
4253	* @param pCtx Pointer to the guest-CPU context.
4254	* @param cb RIP increment value in bytes.
4255	*
4256	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
4257	* when NRIP_SAVE is supported by the CPU, otherwise use
4258	* hmR0SvmAdvanceRipDumb!
4259	*/
4260	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4261	{
4262	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4263	{
4264	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4265	Assert(pVmcb->ctrl.u64NextRIP);
4266	Assert(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb);
4267	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4268	}
4269	else
4270	pCtx->rip += cb;
4271
4272	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4273	}
4274
4275
4276	/**
4277	* Advances the guest RIP by the number of bytes specified in @a cb. This does
4278	* not make use of any hardware features to determine the instruction length.
4279	*
4280	* @param pVCpu The cross context virtual CPU structure.
4281	* @param pCtx Pointer to the guest-CPU context.
4282	* @param cb RIP increment value in bytes.
4283	*/
4284	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4285	{
4286	pCtx->rip += cb;
4287	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4288	}
4289	#undef HMSVM_UPDATE_INTR_SHADOW
4290
4291
4292	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4293	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
4294	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4295
4296	/** @name \#VMEXIT handlers.
4297	* @{
4298	*/
4299
4300	/**
4301	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
4302	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
4303	*/
4304	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4305	{
4306	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4307
4308	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
4309	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
4310	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
4311	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
4312
4313	/*
4314	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
4315	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
4316	* interrupt it is until the host actually take the interrupt.
4317	*
4318	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
4319	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
4320	*/
4321	return VINF_EM_RAW_INTERRUPT;
4322	}
4323
4324
4325	/**
4326	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
4327	*/
4328	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4329	{
4330	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4331
4332	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4333	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
4334	int rc = VINF_SUCCESS;
4335	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4336	return rc;
4337	}
4338
4339
4340	/**
4341	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
4342	*/
4343	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4344	{
4345	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4346
4347	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4348	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
4349	int rc = VINF_SUCCESS;
4350	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4351	return rc;
4352	}
4353
4354
4355	/**
4356	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
4357	*/
4358	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4359	{
4360	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4361	PVM pVM = pVCpu->CTX_SUFF(pVM);
4362	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4363	if (RT_LIKELY(rc == VINF_SUCCESS))
4364	{
4365	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4366	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4367	}
4368	else
4369	{
4370	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4371	rc = VERR_EM_INTERPRETER;
4372	}
4373	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
4374	return rc;
4375	}
4376
4377
4378	/**
4379	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
4380	*/
4381	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4382	{
4383	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4384	PVM pVM = pVCpu->CTX_SUFF(pVM);
4385	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4386	if (RT_LIKELY(rc == VINF_SUCCESS))
4387	{
4388	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4389	pSvmTransient->fUpdateTscOffsetting = true;
4390
4391	/* Single step check. */
4392	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4393	}
4394	else
4395	{
4396	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
4397	rc = VERR_EM_INTERPRETER;
4398	}
4399	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
4400	return rc;
4401	}
4402
4403
4404	/**
4405	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
4406	*/
4407	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4408	{
4409	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4410	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4411	if (RT_LIKELY(rc == VINF_SUCCESS))
4412	{
4413	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4414	pSvmTransient->fUpdateTscOffsetting = true;
4415	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4416	}
4417	else
4418	{
4419	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
4420	rc = VERR_EM_INTERPRETER;
4421	}
4422	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
4423	return rc;
4424	}
4425
4426
4427	/**
4428	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
4429	*/
4430	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4431	{
4432	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4433	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4434	if (RT_LIKELY(rc == VINF_SUCCESS))
4435	{
4436	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4437	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4438	}
4439	else
4440	{
4441	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4442	rc = VERR_EM_INTERPRETER;
4443	}
4444	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4445	return rc;
4446	}
4447
4448
4449	/**
4450	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
4451	*/
4452	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4453	{
4454	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4455	PVM pVM = pVCpu->CTX_SUFF(pVM);
4456	Assert(!pVM->hm.s.fNestedPaging);
4457
4458	/** @todo Decode Assist. */
4459	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
4460	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4461	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
4462	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4463	return rc;
4464	}
4465
4466
4467	/**
4468	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
4469	*/
4470	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4471	{
4472	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4473
4474	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
4475	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4476	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4477	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4478	if (rc != VINF_SUCCESS)
4479	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
4480	return rc;
4481	}
4482
4483
4484	/**
4485	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
4486	*/
4487	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4488	{
4489	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4490	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4491	if (RT_LIKELY(rc == VINF_SUCCESS))
4492	{
4493	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4494	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4495	}
4496	else
4497	{
4498	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4499	rc = VERR_EM_INTERPRETER;
4500	}
4501	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4502	return rc;
4503	}
4504
4505
4506	/**
4507	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
4508	*/
4509	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4510	{
4511	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4512	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4513	int rc = VBOXSTRICTRC_VAL(rc2);
4514	if ( rc == VINF_EM_HALT
4515	\|\| rc == VINF_SUCCESS)
4516	{
4517	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4518
4519	if ( rc == VINF_EM_HALT
4520	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
4521	{
4522	rc = VINF_SUCCESS;
4523	}
4524	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4525	}
4526	else
4527	{
4528	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4529	rc = VERR_EM_INTERPRETER;
4530	}
4531	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
4532	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4533	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4534	return rc;
4535	}
4536
4537
4538	/**
4539	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
4540	* \#VMEXIT.
4541	*/
4542	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4543	{
4544	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4545	return VINF_EM_RESET;
4546	}
4547
4548
4549	/**
4550	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
4551	*/
4552	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4553	{
4554	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4555
4556	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4557
4558	/** @todo Decode Assist. */
4559	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4560	int rc = VBOXSTRICTRC_VAL(rc2);
4561	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4562	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4563	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4564	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4565	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4566	return rc;
4567	}
4568
4569
4570	/**
4571	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
4572	*/
4573	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4574	{
4575	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4576
4577	/** @todo Decode Assist. */
4578	VBOXSTRICTRC rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
4579	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
4580	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
4581	rcStrict = VERR_EM_INTERPRETER;
4582	if (rcStrict == VINF_SUCCESS)
4583	{
4584	/* RIP has been updated by EMInterpretInstruction(). */
4585	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4586	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4587	{
4588	case 0: /* CR0. */
4589	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4590	break;
4591
4592	case 3: /* CR3. */
4593	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4594	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4595	break;
4596
4597	case 4: /* CR4. */
4598	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4599	break;
4600
4601	case 8: /* CR8 (TPR). */
4602	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4603	break;
4604
4605	default:
4606	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
4607	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4608	break;
4609	}
4610	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4611	}
4612	else
4613	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
4614	return VBOXSTRICTRC_TODO(rcStrict);
4615	}
4616
4617
4618	/**
4619	* \#VMEXIT handler for instructions that result in a \#UD exception delivered
4620	* to the guest.
4621	*/
4622	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4623	{
4624	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4625	hmR0SvmSetPendingXcptUD(pVCpu);
4626	return VINF_SUCCESS;
4627	}
4628
4629
4630	/**
4631	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
4632	* \#VMEXIT.
4633	*/
4634	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4635	{
4636	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4637	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4638	PVM pVM = pVCpu->CTX_SUFF(pVM);
4639
4640	int rc;
4641	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4642	{
4643	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4644
4645	/* Handle TPR patching; intercepted LSTAR write. */
4646	if ( pVM->hm.s.fTPRPatchingActive
4647	&& pCtx->ecx == MSR_K8_LSTAR)
4648	{
4649	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4650	{
4651	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4652	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4653	AssertRC(rc2);
4654	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4655	}
4656	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4657	rc = VINF_SUCCESS;
4658	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4659	return rc;
4660	}
4661
4662	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4663	{
4664	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4665	if (RT_LIKELY(rc == VINF_SUCCESS))
4666	{
4667	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4668	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4669	}
4670	else
4671	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4672	}
4673	else
4674	{
4675	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4676	if (RT_LIKELY(rc == VINF_SUCCESS))
4677	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
4678	else
4679	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4680	}
4681
4682	if (rc == VINF_SUCCESS)
4683	{
4684	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4685	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4686	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4687	{
4688	/*
4689	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4690	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4691	* EMInterpretWrmsr() changes it.
4692	*/
4693	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4694	}
4695	else if (pCtx->ecx == MSR_K6_EFER)
4696	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4697	else if (pCtx->ecx == MSR_IA32_TSC)
4698	pSvmTransient->fUpdateTscOffsetting = true;
4699	}
4700	}
4701	else
4702	{
4703	/* MSR Read access. */
4704	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4705	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4706
4707	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4708	{
4709	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4710	if (RT_LIKELY(rc == VINF_SUCCESS))
4711	{
4712	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4713	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4714	}
4715	else
4716	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4717	}
4718	else
4719	{
4720	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4721	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4722	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4723	/* RIP updated by EMInterpretInstruction(). */
4724	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4725	}
4726	}
4727
4728	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4729	return rc;
4730	}
4731
4732
4733	/**
4734	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
4735	*/
4736	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4737	{
4738	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4739	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4740
4741	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
4742	if (pSvmTransient->fWasGuestDebugStateActive)
4743	{
4744	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
4745	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
4746	return VERR_SVM_UNEXPECTED_EXIT;
4747	}
4748
4749	/*
4750	* Lazy DR0-3 loading.
4751	*/
4752	if (!pSvmTransient->fWasHyperDebugStateActive)
4753	{
4754	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4755	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4756
4757	/* Don't intercept DRx read and writes. */
4758	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4759	pVmcb->ctrl.u16InterceptRdDRx = 0;
4760	pVmcb->ctrl.u16InterceptWrDRx = 0;
4761	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4762
4763	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4764	VMMRZCallRing3Disable(pVCpu);
4765	HM_DISABLE_PREEMPT();
4766
4767	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4768	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4769	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4770
4771	HM_RESTORE_PREEMPT();
4772	VMMRZCallRing3Enable(pVCpu);
4773
4774	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4775	return VINF_SUCCESS;
4776	}
4777
4778	/*
4779	* Interpret the read/writing of DRx.
4780	*/
4781	/** @todo Decode assist. */
4782	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4783	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4784	if (RT_LIKELY(rc == VINF_SUCCESS))
4785	{
4786	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4787	/** @todo CPUM should set this flag! */
4788	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4789	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4790	}
4791	else
4792	Assert(rc == VERR_EM_INTERPRETER);
4793	return VBOXSTRICTRC_TODO(rc);
4794	}
4795
4796
4797	/**
4798	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
4799	*/
4800	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4801	{
4802	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4803	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4804	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4805	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4806	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4807	return rc;
4808	}
4809
4810
4811	/**
4812	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
4813	*/
4814	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4815	{
4816	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4817
4818	/** @todo decode assists... */
4819	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
4820	if (rcStrict == VINF_IEM_RAISED_XCPT)
4821	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4822
4823	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4824	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
4825	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
4826
4827	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4828	return VBOXSTRICTRC_TODO(rcStrict);
4829	}
4830
4831
4832	/**
4833	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
4834	*/
4835	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4836	{
4837	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4838
4839	/* I/O operation lookup arrays. */
4840	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4841	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4842	the result (in AL/AX/EAX). */
4843	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4844
4845	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4846	PVM pVM = pVCpu->CTX_SUFF(pVM);
4847
4848	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4849	SVMIOIOEXIT IoExitInfo;
4850	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4851	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4852	uint32_t cbValue = s_aIOSize[uIOWidth];
4853	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4854
4855	if (RT_UNLIKELY(!cbValue))
4856	{
4857	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4858	return VERR_EM_INTERPRETER;
4859	}
4860
4861	VBOXSTRICTRC rcStrict;
4862	bool fUpdateRipAlready = false;
4863	if (IoExitInfo.n.u1STR)
4864	{
4865	#ifdef VBOX_WITH_2ND_IEM_STEP
4866	/* INS/OUTS - I/O String instruction. */
4867	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4868	* in EXITINFO1? Investigate once this thing is up and running. */
4869	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
4870	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
4871	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
4872	static IEMMODE const s_aenmAddrMode[8] =
4873	{
4874	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
4875	};
4876	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
4877	if (enmAddrMode != (IEMMODE)-1)
4878	{
4879	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
4880	if (cbInstr <= 15 && cbInstr >= 1)
4881	{
4882	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
4883	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4884	{
4885	/* Don't know exactly how to detect whether u3SEG is valid, currently
4886	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
4887	2384 Opterons when only checking NRIP. */
4888	if ( (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4889	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
4890	{
4891	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
4892	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
4893	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
4894	IoExitInfo.n.u3SEG, true /fIoChecked/);
4895	}
4896	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
4897	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
4898	X86_SREG_DS, true /fIoChecked/);
4899	else
4900	rcStrict = IEMExecOne(pVCpu);
4901	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4902	}
4903	else
4904	{
4905	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
4906	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
4907	true /fIoChecked/);
4908	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4909	}
4910	}
4911	else
4912	{
4913	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
4914	rcStrict = IEMExecOne(pVCpu);
4915	}
4916	}
4917	else
4918	{
4919	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
4920	rcStrict = IEMExecOne(pVCpu);
4921	}
4922	fUpdateRipAlready = true;
4923
4924	#else
4925	/* INS/OUTS - I/O String instruction. */
4926	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4927
4928	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4929	* in EXITINFO1? Investigate once this thing is up and running. */
4930
4931	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4932	if (rcStrict == VINF_SUCCESS)
4933	{
4934	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4935	{
4936	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4937	(DISCPUMODE)pDis->uAddrMode, cbValue);
4938	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4939	}
4940	else
4941	{
4942	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4943	(DISCPUMODE)pDis->uAddrMode, cbValue);
4944	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4945	}
4946	}
4947	else
4948	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4949	#endif
4950	}
4951	else
4952	{
4953	/* IN/OUT - I/O instruction. */
4954	Assert(!IoExitInfo.n.u1REP);
4955
4956	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4957	{
4958	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4959	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4960	}
4961	else
4962	{
4963	uint32_t u32Val = 0;
4964	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4965	if (IOM_SUCCESS(rcStrict))
4966	{
4967	/* Save result of I/O IN instr. in AL/AX/EAX. */
4968	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
4969	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4970	}
4971	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4972	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4973
4974	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4975	}
4976	}
4977
4978	if (IOM_SUCCESS(rcStrict))
4979	{
4980	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4981	if (!fUpdateRipAlready)
4982	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4983
4984	/*
4985	* If any I/O breakpoints are armed, we need to check if one triggered
4986	* and take appropriate action.
4987	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4988	*/
4989	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4990	* execution engines about whether hyper BPs and such are pending. */
4991	uint32_t const uDr7 = pCtx->dr[7];
4992	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4993	&& X86_DR7_ANY_RW_IO(uDr7)
4994	&& (pCtx->cr4 & X86_CR4_DE))
4995	\|\| DBGFBpIsHwIoArmed(pVM)))
4996	{
4997	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4998	VMMRZCallRing3Disable(pVCpu);
4999	HM_DISABLE_PREEMPT();
5000
5001	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
5002	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
5003
5004	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
5005	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
5006	{
5007	/* Raise #DB. */
5008	pVmcb->guest.u64DR6 = pCtx->dr[6];
5009	pVmcb->guest.u64DR7 = pCtx->dr[7];
5010	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5011	hmR0SvmSetPendingXcptDB(pVCpu);
5012	}
5013	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
5014	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
5015	else if ( rcStrict2 != VINF_SUCCESS
5016	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
5017	rcStrict = rcStrict2;
5018	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
5019
5020	HM_RESTORE_PREEMPT();
5021	VMMRZCallRing3Enable(pVCpu);
5022	}
5023
5024	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5025	}
5026
5027	#ifdef VBOX_STRICT
5028	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
5029	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
5030	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
5031	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
5032	else
5033	{
5034	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
5035	* statuses, that the VMM device and some others may return. See
5036	* IOM_SUCCESS() for guidance. */
5037	AssertMsg( RT_FAILURE(rcStrict)
5038	\|\| rcStrict == VINF_SUCCESS
5039	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
5040	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
5041	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
5042	\|\| rcStrict == VINF_EM_RAW_TO_R3
5043	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
5044	}
5045	#endif
5046	return VBOXSTRICTRC_TODO(rcStrict);
5047	}
5048
5049
5050	/**
5051	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
5052	*/
5053	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5054	{
5055	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5056	PVM pVM = pVCpu->CTX_SUFF(pVM);
5057	Assert(pVM->hm.s.fNestedPaging);
5058
5059	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5060
5061	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
5062	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5063	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5064	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
5065
5066	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
5067
5068	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5069	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
5070	if ( pVM->hm.s.fTprPatchingAllowed
5071	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
5072	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
5073	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
5074	&& !CPUMIsGuestInLongModeEx(pCtx)
5075	&& !CPUMGetGuestCPL(pVCpu)
5076	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5077	{
5078	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
5079	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5080
5081	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
5082	{
5083	/* Only attempt to patch the instruction once. */
5084	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5085	if (!pPatch)
5086	return VINF_EM_HM_PATCH_TPR_INSTR;
5087	}
5088	}
5089	#endif
5090
5091	/*
5092	* Determine the nested paging mode.
5093	*/
5094	PGMMODE enmNestedPagingMode;
5095	#if HC_ARCH_BITS == 32
5096	if (CPUMIsGuestInLongModeEx(pCtx))
5097	enmNestedPagingMode = PGMMODE_AMD64_NX;
5098	else
5099	#endif
5100	enmNestedPagingMode = PGMGetHostMode(pVM);
5101
5102	/*
5103	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
5104	*/
5105	int rc;
5106	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
5107	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
5108	{
5109	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
5110	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
5111	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5112	return VERR_EM_INTERPRETER;
5113
5114	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
5115	u32ErrCode);
5116	rc = VBOXSTRICTRC_VAL(rc2);
5117
5118	/*
5119	* If we succeed, resume guest execution.
5120	* If we fail in interpreting the instruction because we couldn't get the guest physical address
5121	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
5122	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
5123	* weird case. See @bugref{6043}.
5124	*/
5125	if ( rc == VINF_SUCCESS
5126	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5127	\|\| rc == VERR_PAGE_NOT_PRESENT)
5128	{
5129	/* Successfully handled MMIO operation. */
5130	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5131	rc = VINF_SUCCESS;
5132	}
5133	return rc;
5134	}
5135
5136	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
5137	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
5138	TRPMResetTrap(pVCpu);
5139
5140	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
5141
5142	/*
5143	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
5144	*/
5145	if ( rc == VINF_SUCCESS
5146	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5147	\|\| rc == VERR_PAGE_NOT_PRESENT)
5148	{
5149	/* We've successfully synced our shadow page tables. */
5150	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5151	rc = VINF_SUCCESS;
5152	}
5153
5154	return rc;
5155	}
5156
5157
5158	/**
5159	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
5160	* \#VMEXIT.
5161	*/
5162	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5163	{
5164	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5165
5166	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5167	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
5168	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
5169
5170	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
5171	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
5172	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
5173
5174	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5175	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
5176	return VINF_SUCCESS;
5177	}
5178
5179
5180	/**
5181	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
5182	* \#VMEXIT.
5183	*/
5184	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5185	{
5186	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5187
5188	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5189
5190	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
5191	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5192	#endif
5193
5194	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
5195	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
5196	{
5197	/*
5198	* AMD-V provides us with the exception which caused the TS; we collect
5199	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
5200	*/
5201	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
5202	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5203	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5204	}
5205
5206	/** @todo Emulate task switch someday, currently just going back to ring-3 for
5207	* emulation. */
5208	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5209	return VERR_EM_INTERPRETER;
5210	}
5211
5212
5213	/**
5214	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5215	*/
5216	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5217	{
5218	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5219	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
5220
5221	/* First check if this is a patched VMMCALL for mov TPR */
5222	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5223	if (rc == VINF_SUCCESS)
5224	{
5225	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5226	return VINF_SUCCESS;
5227	}
5228
5229	if (rc == VERR_NOT_FOUND)
5230	{
5231	if (pVCpu->hm.s.fHypercallsEnabled)
5232	{
5233	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, pCtx);
5234	if (RT_SUCCESS(VBOXSTRICTRC_VAL(rcStrict)))
5235	{
5236	if (rcStrict == VINF_SUCCESS)
5237	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
5238	else
5239	Assert( rcStrict == VINF_GIM_HYPERCALL_CONTINUING
5240	\|\| rcStrict == VINF_GIM_R3_HYPERCALL);
5241
5242	/* If the hypercall changes anything other than guest's general-purpose registers,
5243	we would need to reload the guest changed bits here before VM-entry. */
5244	}
5245	rc = VBOXSTRICTRC_VAL(rcStrict);
5246	}
5247	else
5248	Log4(("hmR0SvmExitVmmCall: Hypercalls not enabled\n"));
5249	}
5250
5251	/* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
5252	if (RT_FAILURE(rc))
5253	{
5254	hmR0SvmSetPendingXcptUD(pVCpu);
5255	rc = VINF_SUCCESS;
5256	}
5257
5258	return rc;
5259	}
5260
5261
5262	/**
5263	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5264	*/
5265	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5266	{
5267	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5268	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
5269	return VINF_EM_RAW_INTERRUPT;
5270	}
5271
5272
5273	/**
5274	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
5275	*/
5276	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5277	{
5278	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5279
5280	/* Clear NMI blocking. */
5281	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5282
5283	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
5284	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5285	hmR0SvmClearIretIntercept(pVmcb);
5286
5287	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5288	return VINF_SUCCESS;
5289	}
5290
5291
5292	/**
5293	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E).
5294	* Conditional \#VMEXIT.
5295	*/
5296	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5297	{
5298	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5299
5300	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5301
5302	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
5303	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5304	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5305	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
5306	PVM pVM = pVCpu->CTX_SUFF(pVM);
5307
5308	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
5309	if (pVM->hm.s.fNestedPaging)
5310	{
5311	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5312	if (!pSvmTransient->fVectoringDoublePF)
5313	{
5314	/* A genuine guest #PF, reflect it to the guest. */
5315	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5316	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
5317	uFaultAddress, u32ErrCode));
5318	}
5319	else
5320	{
5321	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5322	hmR0SvmSetPendingXcptDF(pVCpu);
5323	Log4(("Pending #DF due to vectoring #PF. NP\n"));
5324	}
5325	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5326	return VINF_SUCCESS;
5327	}
5328	#endif
5329
5330	Assert(!pVM->hm.s.fNestedPaging);
5331
5332	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5333	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
5334	if ( pVM->hm.s.fTprPatchingAllowed
5335	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
5336	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
5337	&& !CPUMIsGuestInLongModeEx(pCtx)
5338	&& !CPUMGetGuestCPL(pVCpu)
5339	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5340	{
5341	RTGCPHYS GCPhysApicBase;
5342	GCPhysApicBase = pCtx->msrApicBase;
5343	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5344
5345	/* Check if the page at the fault-address is the APIC base. */
5346	RTGCPHYS GCPhysPage;
5347	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
5348	if ( rc2 == VINF_SUCCESS
5349	&& GCPhysPage == GCPhysApicBase)
5350	{
5351	/* Only attempt to patch the instruction once. */
5352	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5353	if (!pPatch)
5354	return VINF_EM_HM_PATCH_TPR_INSTR;
5355	}
5356	}
5357	#endif
5358
5359	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
5360	pCtx->rip, u32ErrCode, pCtx->cr3));
5361
5362	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
5363	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
5364	if (pSvmTransient->fVectoringPF)
5365	{
5366	Assert(pVCpu->hm.s.Event.fPending);
5367	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5368	}
5369
5370	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
5371	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
5372
5373	Log4(("#PF rc=%Rrc\n", rc));
5374
5375	if (rc == VINF_SUCCESS)
5376	{
5377	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
5378	TRPMResetTrap(pVCpu);
5379	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5380	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5381	return rc;
5382	}
5383	else if (rc == VINF_EM_RAW_GUEST_TRAP)
5384	{
5385	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5386
5387	if (!pSvmTransient->fVectoringDoublePF)
5388	{
5389	/* It's a guest page fault and needs to be reflected to the guest. */
5390	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
5391	TRPMResetTrap(pVCpu);
5392	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5393	}
5394	else
5395	{
5396	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5397	TRPMResetTrap(pVCpu);
5398	hmR0SvmSetPendingXcptDF(pVCpu);
5399	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
5400	}
5401
5402	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5403	return VINF_SUCCESS;
5404	}
5405
5406	TRPMResetTrap(pVCpu);
5407	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
5408	return rc;
5409	}
5410
5411
5412	/**
5413	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
5414	* Conditional \#VMEXIT.
5415	*/
5416	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5417	{
5418	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5419
5420	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5421	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5422	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5423
5424	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5425	VMMRZCallRing3Disable(pVCpu);
5426	HM_DISABLE_PREEMPT();
5427
5428	int rc;
5429	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
5430	if (pSvmTransient->fWasGuestFPUStateActive)
5431	{
5432	rc = VINF_EM_RAW_GUEST_TRAP;
5433	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
5434	}
5435	else
5436	{
5437	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5438	Assert(!pSvmTransient->fWasGuestFPUStateActive);
5439	#endif
5440	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
5441	Assert( rc == VINF_EM_RAW_GUEST_TRAP
5442	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
5443	}
5444
5445	HM_RESTORE_PREEMPT();
5446	VMMRZCallRing3Enable(pVCpu);
5447
5448	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
5449	{
5450	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
5451	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
5452	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
5453	pVCpu->hm.s.fPreloadGuestFpu = true;
5454	}
5455	else
5456	{
5457	/* Forward #NM to the guest. */
5458	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
5459	hmR0SvmSetPendingXcptNM(pVCpu);
5460	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
5461	}
5462	return VINF_SUCCESS;
5463	}
5464
5465
5466	/**
5467	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
5468	* Conditional \#VMEXIT.
5469	*/
5470	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5471	{
5472	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5473
5474	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5475	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5476	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5477
5478	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
5479	if (pVCpu->hm.s.fGIMTrapXcptUD)
5480	{
5481	uint8_t cbInstr = 0;
5482	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
5483	if (rcStrict == VINF_SUCCESS)
5484	{
5485	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
5486	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
5487	rc = VINF_SUCCESS;
5488	}
5489	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
5490	rc = VINF_SUCCESS;
5491	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
5492	rc = VINF_GIM_R3_HYPERCALL;
5493	else
5494	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
5495	}
5496
5497	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
5498	if (RT_FAILURE(rc))
5499	{
5500	hmR0SvmSetPendingXcptUD(pVCpu);
5501	rc = VINF_SUCCESS;
5502	}
5503
5504	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
5505	return rc;
5506	}
5507
5508
5509	/**
5510	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
5511	* Conditional \#VMEXIT.
5512	*/
5513	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5514	{
5515	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5516
5517	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5518	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5519	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5520
5521	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
5522
5523	if (!(pCtx->cr0 & X86_CR0_NE))
5524	{
5525	PVM pVM = pVCpu->CTX_SUFF(pVM);
5526	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5527	unsigned cbOp;
5528	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
5529	if (RT_SUCCESS(rc))
5530	{
5531	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
5532	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
5533	if (RT_SUCCESS(rc))
5534	pCtx->rip += cbOp;
5535	}
5536	else
5537	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5538	return rc;
5539	}
5540
5541	hmR0SvmSetPendingXcptMF(pVCpu);
5542	return VINF_SUCCESS;
5543	}
5544
5545
5546	/**
5547	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
5548	* \#VMEXIT.
5549	*/
5550	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5551	{
5552	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5553
5554	/* If this #DB is the result of delivering an event, go back to the interpreter. */
5555	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5556	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5557	{
5558	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
5559	return VERR_EM_INTERPRETER;
5560	}
5561
5562	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
5563
5564	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
5565	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
5566	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5567	PVM pVM = pVCpu->CTX_SUFF(pVM);
5568	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
5569	if (rc == VINF_EM_RAW_GUEST_TRAP)
5570	{
5571	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
5572	if (CPUMIsHyperDebugStateActive(pVCpu))
5573	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
5574
5575	/* Reflect the exception back to the guest. */
5576	hmR0SvmSetPendingXcptDB(pVCpu);
5577	rc = VINF_SUCCESS;
5578	}
5579
5580	/*
5581	* Update DR6.
5582	*/
5583	if (CPUMIsHyperDebugStateActive(pVCpu))
5584	{
5585	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
5586	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
5587	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5588	}
5589	else
5590	{
5591	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
5592	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
5593	}
5594
5595	return rc;
5596	}
5597
5598
5599	/**
5600	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_11).
5601	* Conditional \#VMEXIT.
5602	*/
5603	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5604	{
5605	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5606
5607	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5608
5609	SVMEVENT Event;
5610	Event.u = 0;
5611	Event.n.u1Valid = 1;
5612	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5613	Event.n.u8Vector = X86_XCPT_AC;
5614	Event.n.u1ErrorCodeValid = 1;
5615	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5616	return VINF_SUCCESS;
5617	}
5618
5619	/** @} */
5620

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 61649

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