HMSVMR0.cpp@ 64468

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1	/* $Id: HMSVMR0.cpp 62606 2016-07-27 16:33:40Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/thread.h>
25
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#ifdef VBOX_WITH_NEW_APIC
33	# include <VBox/vmm/apic.h>
34	#endif
35	#include "HMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include "HMSVMR0.h"
38	#include "dtrace/VBoxVMM.h"
39
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
43	# define HMSVM_ALWAYS_TRAP_PF
44	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
45	#endif
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	#ifdef VBOX_WITH_STATISTICS
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
53	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
54	if ((u64ExitCode) == SVM_EXIT_NPF) \
55	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
56	else \
57	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
58	} while (0)
59	#else
60	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
61	#endif
62
63	/** If we decide to use a function table approach this can be useful to
64	* switch to a "static DECLCALLBACK(int)". */
65	#define HMSVM_EXIT_DECL static int
66
67	/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
68	*
69	* The CPU format of the segment attribute is described in X86DESCATTRBITS
70	* which is 16-bits (i.e. includes 4 bits of the segment limit).
71	*
72	* The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
73	* only the attribute bits and nothing else). Upper 4-bits are unused.
74	*
75	* @{ */
76	#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0xf000) >> 4) )
77	#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) \| (((a) & 0x0f00) << 4) )
78	/** @} */
79
80	/** @name Macros for loading, storing segment registers to/from the VMCB.
81	* @{ */
82	#define HMSVM_LOAD_SEG_REG(REG, reg) \
83	do \
84	{ \
85	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
86	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
87	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
88	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
89	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
90	pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
91	} while (0)
92
93	#define HMSVM_SAVE_SEG_REG(REG, reg) \
94	do \
95	{ \
96	pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
97	pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
98	pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
99	pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
100	pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
101	pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
102	} while (0)
103	/** @} */
104
105	/** Macro for checking and returning from the using function for
106	* \#VMEXIT intercepts that maybe caused during delivering of another
107	* event in the guest. */
108	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
109	do \
110	{ \
111	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
112	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
113	else if (rc == VINF_HM_DOUBLE_FAULT) \
114	return VINF_SUCCESS; \
115	else \
116	return rc; \
117	} while (0)
118
119	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
120	* instruction that exited. */
121	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
122	do { \
123	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
124	(a_rc) = VINF_EM_DBG_STEPPED; \
125	} while (0)
126
127	/** Assert that preemption is disabled or covered by thread-context hooks. */
128	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
129	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
130
131	/** Assert that we haven't migrated CPUs when thread-context hooks are not
132	* used. */
133	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
134	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
135	("Illegal migration! Entered on CPU %u Current %u\n", \
136	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
137
138	/** Exception bitmap mask for all contributory exceptions.
139	*
140	* Page fault is deliberately excluded here as it's conditional as to whether
141	* it's contributory or benign. Page faults are handled separately.
142	*/
143	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
144	\| RT_BIT(X86_XCPT_DE))
145
146	/** @name VMCB Clean Bits.
147	*
148	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
149	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
150	* memory.
151	*
152	* @{ */
153	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
154	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
155	/** I/O permission bitmap, MSR permission bitmap. */
156	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
157	/** ASID. */
158	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
159	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
160	V_INTR_VECTOR. */
161	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
162	/** Nested Paging: Nested CR3 (nCR3), PAT. */
163	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
164	/** Control registers (CR0, CR3, CR4, EFER). */
165	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
166	/** Debug registers (DR6, DR7). */
167	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
168	/** GDT, IDT limit and base. */
169	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
170	/** Segment register: CS, SS, DS, ES limit and base. */
171	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
172	/** CR2.*/
173	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
174	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
175	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
176	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
177	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
178	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
179	/** Mask of all valid VMCB Clean bits. */
180	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
181	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
182	\| HMSVM_VMCB_CLEAN_ASID \
183	\| HMSVM_VMCB_CLEAN_TPR \
184	\| HMSVM_VMCB_CLEAN_NP \
185	\| HMSVM_VMCB_CLEAN_CRX_EFER \
186	\| HMSVM_VMCB_CLEAN_DRX \
187	\| HMSVM_VMCB_CLEAN_DT \
188	\| HMSVM_VMCB_CLEAN_SEG \
189	\| HMSVM_VMCB_CLEAN_CR2 \
190	\| HMSVM_VMCB_CLEAN_LBR \
191	\| HMSVM_VMCB_CLEAN_AVIC)
192	/** @} */
193
194	/** @name SVM transient.
195	*
196	* A state structure for holding miscellaneous information across AMD-V
197	* VMRUN/\#VMEXIT operation, restored after the transition.
198	*
199	* @{ */
200	typedef struct SVMTRANSIENT
201	{
202	/** The host's rflags/eflags. */
203	RTCCUINTREG fEFlags;
204	#if HC_ARCH_BITS == 32
205	uint32_t u32Alignment0;
206	#endif
207
208	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
209	uint64_t u64ExitCode;
210	/** The guest's TPR value used for TPR shadowing. */
211	uint8_t u8GuestTpr;
212	/** Alignment. */
213	uint8_t abAlignment0[7];
214
215	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
216	bool fWasGuestFPUStateActive;
217	/** Whether the guest debug state was active at the time of \#VMEXIT. */
218	bool fWasGuestDebugStateActive;
219	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
220	bool fWasHyperDebugStateActive;
221	/** Whether the TSC offset mode needs to be updated. */
222	bool fUpdateTscOffsetting;
223	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
224	bool fRestoreTscAuxMsr;
225	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
226	* contributary exception or a page-fault. */
227	bool fVectoringDoublePF;
228	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
229	* external interrupt or NMI. */
230	bool fVectoringPF;
231	} SVMTRANSIENT, *PSVMTRANSIENT;
232	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
233	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
234	/** @} */
235
236	/**
237	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
238	*/
239	typedef enum SVMMSREXITREAD
240	{
241	/** Reading this MSR causes a \#VMEXIT. */
242	SVMMSREXIT_INTERCEPT_READ = 0xb,
243	/** Reading this MSR does not cause a \#VMEXIT. */
244	SVMMSREXIT_PASSTHRU_READ
245	} SVMMSREXITREAD;
246
247	/**
248	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
249	*/
250	typedef enum SVMMSREXITWRITE
251	{
252	/** Writing to this MSR causes a \#VMEXIT. */
253	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
254	/** Writing to this MSR does not cause a \#VMEXIT. */
255	SVMMSREXIT_PASSTHRU_WRITE
256	} SVMMSREXITWRITE;
257
258	/**
259	* SVM \#VMEXIT handler.
260	*
261	* @returns VBox status code.
262	* @param pVCpu The cross context virtual CPU structure.
263	* @param pMixedCtx Pointer to the guest-CPU context.
264	* @param pSvmTransient Pointer to the SVM-transient structure.
265	*/
266	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
267
268
269	/*********************************************************************************************************************************
270	* Internal Functions *
271	*********************************************************************************************************************************/
272	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
273	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
274	static void hmR0SvmLeave(PVMCPU pVCpu);
275
276	/** @name \#VMEXIT handlers.
277	* @{
278	*/
279	static FNSVMEXITHANDLER hmR0SvmExitIntr;
280	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
281	static FNSVMEXITHANDLER hmR0SvmExitInvd;
282	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
283	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
284	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
285	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
286	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
287	static FNSVMEXITHANDLER hmR0SvmExitHlt;
288	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
289	static FNSVMEXITHANDLER hmR0SvmExitMwait;
290	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
291	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
292	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
293	static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
294	static FNSVMEXITHANDLER hmR0SvmExitMsr;
295	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
296	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
297	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
298	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
299	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
300	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
301	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
302	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
303	static FNSVMEXITHANDLER hmR0SvmExitPause;
304	static FNSVMEXITHANDLER hmR0SvmExitIret;
305	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
306	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
307	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
308	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
309	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
310	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
311	/** @} */
312
313	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
314
315
316	/*********************************************************************************************************************************
317	* Global Variables *
318	*********************************************************************************************************************************/
319	/** Ring-0 memory object for the IO bitmap. */
320	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
321	/** Physical address of the IO bitmap. */
322	RTHCPHYS g_HCPhysIOBitmap = 0;
323	/** Virtual address of the IO bitmap. */
324	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
325
326
327	/**
328	* Sets up and activates AMD-V on the current CPU.
329	*
330	* @returns VBox status code.
331	* @param pCpu Pointer to the CPU info struct.
332	* @param pVM The cross context VM structure. Can be
333	* NULL after a resume!
334	* @param pvCpuPage Pointer to the global CPU page.
335	* @param HCPhysCpuPage Physical address of the global CPU page.
336	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
337	* @param pvArg Unused on AMD-V.
338	*/
339	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
340	void *pvArg)
341	{
342	Assert(!fEnabledByHost);
343	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
344	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
345	Assert(pvCpuPage); NOREF(pvCpuPage);
346	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
347
348	NOREF(pvArg);
349	NOREF(fEnabledByHost);
350
351	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
352	RTCCUINTREG fEFlags = ASMIntDisableFlags();
353
354	/*
355	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
356	*/
357	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
358	if (u64HostEfer & MSR_K6_EFER_SVME)
359	{
360	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
361	if ( pVM
362	&& pVM->hm.s.svm.fIgnoreInUseError)
363	{
364	pCpu->fIgnoreAMDVInUseError = true;
365	}
366
367	if (!pCpu->fIgnoreAMDVInUseError)
368	{
369	ASMSetFlags(fEFlags);
370	return VERR_SVM_IN_USE;
371	}
372	}
373
374	/* Turn on AMD-V in the EFER MSR. */
375	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
376
377	/* Write the physical page address where the CPU will store the host state while executing the VM. */
378	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
379
380	/* Restore interrupts. */
381	ASMSetFlags(fEFlags);
382
383	/*
384	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
385	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
386	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
387	* to flush the TLB with before using a new ASID.
388	*/
389	pCpu->fFlushAsidBeforeUse = true;
390
391	/*
392	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
393	*/
394	++pCpu->cTlbFlushes;
395
396	return VINF_SUCCESS;
397	}
398
399
400	/**
401	* Deactivates AMD-V on the current CPU.
402	*
403	* @returns VBox status code.
404	* @param pCpu Pointer to the CPU info struct.
405	* @param pvCpuPage Pointer to the global CPU page.
406	* @param HCPhysCpuPage Physical address of the global CPU page.
407	*/
408	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
409	{
410	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
411	AssertReturn( HCPhysCpuPage
412	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
413	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
414	NOREF(pCpu);
415
416	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
417	RTCCUINTREG fEFlags = ASMIntDisableFlags();
418
419	/* Turn off AMD-V in the EFER MSR. */
420	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
421	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
422
423	/* Invalidate host state physical address. */
424	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
425
426	/* Restore interrupts. */
427	ASMSetFlags(fEFlags);
428
429	return VINF_SUCCESS;
430	}
431
432
433	/**
434	* Does global AMD-V initialization (called during module initialization).
435	*
436	* @returns VBox status code.
437	*/
438	VMMR0DECL(int) SVMR0GlobalInit(void)
439	{
440	/*
441	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
442	* once globally here instead of per-VM.
443	*/
444	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
445	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
446	if (RT_FAILURE(rc))
447	return rc;
448
449	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
450	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
451
452	/* Set all bits to intercept all IO accesses. */
453	ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
454	return VINF_SUCCESS;
455	}
456
457
458	/**
459	* Does global AMD-V termination (called during module termination).
460	*/
461	VMMR0DECL(void) SVMR0GlobalTerm(void)
462	{
463	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
464	{
465	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
466	g_pvIOBitmap = NULL;
467	g_HCPhysIOBitmap = 0;
468	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
469	}
470	}
471
472
473	/**
474	* Frees any allocated per-VCPU structures for a VM.
475	*
476	* @param pVM The cross context VM structure.
477	*/
478	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
479	{
480	for (uint32_t i = 0; i < pVM->cCpus; i++)
481	{
482	PVMCPU pVCpu = &pVM->aCpus[i];
483	AssertPtr(pVCpu);
484
485	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
486	{
487	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
488	pVCpu->hm.s.svm.pvVmcbHost = 0;
489	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
490	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
491	}
492
493	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
494	{
495	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
496	pVCpu->hm.s.svm.pvVmcb = 0;
497	pVCpu->hm.s.svm.HCPhysVmcb = 0;
498	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
499	}
500
501	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
502	{
503	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
504	pVCpu->hm.s.svm.pvMsrBitmap = 0;
505	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
506	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
507	}
508	}
509	}
510
511
512	/**
513	* Does per-VM AMD-V initialization.
514	*
515	* @returns VBox status code.
516	* @param pVM The cross context VM structure.
517	*/
518	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
519	{
520	int rc = VERR_INTERNAL_ERROR_5;
521
522	/*
523	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
524	*/
525	uint32_t u32Family;
526	uint32_t u32Model;
527	uint32_t u32Stepping;
528	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
529	{
530	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
531	pVM->hm.s.svm.fAlwaysFlushTLB = true;
532	}
533
534	/*
535	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
536	*/
537	for (VMCPUID i = 0; i < pVM->cCpus; i++)
538	{
539	PVMCPU pVCpu = &pVM->aCpus[i];
540	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
541	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
542	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
543	}
544
545	for (VMCPUID i = 0; i < pVM->cCpus; i++)
546	{
547	PVMCPU pVCpu = &pVM->aCpus[i];
548
549	/*
550	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
551	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
552	*/
553	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
554	if (RT_FAILURE(rc))
555	goto failure_cleanup;
556
557	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
558	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
559	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
560	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
561
562	/*
563	* Allocate one page for the guest-state VMCB.
564	*/
565	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
566	if (RT_FAILURE(rc))
567	goto failure_cleanup;
568
569	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
570	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
571	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
572	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
573
574	/*
575	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
576	* SVM to not require one.
577	*/
578	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
579	if (RT_FAILURE(rc))
580	goto failure_cleanup;
581
582	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
583	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
584	/* Set all bits to intercept all MSR accesses (changed later on). */
585	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, UINT32_C(0xffffffff));
586	}
587
588	return VINF_SUCCESS;
589
590	failure_cleanup:
591	hmR0SvmFreeStructs(pVM);
592	return rc;
593	}
594
595
596	/**
597	* Does per-VM AMD-V termination.
598	*
599	* @returns VBox status code.
600	* @param pVM The cross context VM structure.
601	*/
602	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
603	{
604	hmR0SvmFreeStructs(pVM);
605	return VINF_SUCCESS;
606	}
607
608
609	/**
610	* Sets the permission bits for the specified MSR in the MSRPM.
611	*
612	* @param pVCpu The cross context virtual CPU structure.
613	* @param uMsr The MSR for which the access permissions are being set.
614	* @param enmRead MSR read permissions.
615	* @param enmWrite MSR write permissions.
616	*/
617	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
618	{
619	unsigned uBit;
620	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
621
622	/*
623	* Layout:
624	* Byte offset MSR range
625	* 0x000 - 0x7ff 0x00000000 - 0x00001fff
626	* 0x800 - 0xfff 0xc0000000 - 0xc0001fff
627	* 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
628	* 0x1800 - 0x1fff Reserved
629	*/
630	if (uMsr <= 0x00001FFF)
631	{
632	/* Pentium-compatible MSRs. */
633	uBit = uMsr * 2;
634	}
635	else if ( uMsr >= 0xC0000000
636	&& uMsr <= 0xC0001FFF)
637	{
638	/* AMD Sixth Generation x86 Processor MSRs. */
639	uBit = (uMsr - 0xC0000000) * 2;
640	pbMsrBitmap += 0x800;
641	}
642	else if ( uMsr >= 0xC0010000
643	&& uMsr <= 0xC0011FFF)
644	{
645	/* AMD Seventh and Eighth Generation Processor MSRs. */
646	uBit = (uMsr - 0xC0001000) * 2;
647	pbMsrBitmap += 0x1000;
648	}
649	else
650	{
651	AssertFailed();
652	return;
653	}
654
655	Assert(uBit < 0x3fff /* 16 * 1024 - 1 */);
656	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
657	ASMBitSet(pbMsrBitmap, uBit);
658	else
659	ASMBitClear(pbMsrBitmap, uBit);
660
661	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
662	ASMBitSet(pbMsrBitmap, uBit + 1);
663	else
664	ASMBitClear(pbMsrBitmap, uBit + 1);
665
666	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
667	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
668	}
669
670
671	/**
672	* Sets up AMD-V for the specified VM.
673	* This function is only called once per-VM during initalization.
674	*
675	* @returns VBox status code.
676	* @param pVM The cross context VM structure.
677	*/
678	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
679	{
680	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
681	AssertReturn(pVM, VERR_INVALID_PARAMETER);
682	Assert(pVM->hm.s.svm.fSupported);
683
684	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
685	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
686	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
687
688	for (VMCPUID i = 0; i < pVM->cCpus; i++)
689	{
690	PVMCPU pVCpu = &pVM->aCpus[i];
691	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
692
693	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
694
695	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
696	Assert(!pVCpu->hm.s.idxExitHistoryFree);
697	HMCPU_EXIT_HISTORY_RESET(pVCpu);
698
699	/* Always trap #AC for reasons of security. */
700	pVmcb->ctrl.u32InterceptException \|= RT_BIT_32(X86_XCPT_AC);
701
702	/* Always trap #DB for reasons of security. */
703	pVmcb->ctrl.u32InterceptException \|= RT_BIT_32(X86_XCPT_DB);
704
705	/* Trap exceptions unconditionally (debug purposes). */
706	#ifdef HMSVM_ALWAYS_TRAP_PF
707	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
708	#endif
709	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
710	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
711	pVmcb->ctrl.u32InterceptException \|= 0
712	\| RT_BIT(X86_XCPT_BP)
713	\| RT_BIT(X86_XCPT_DE)
714	\| RT_BIT(X86_XCPT_NM)
715	\| RT_BIT(X86_XCPT_UD)
716	\| RT_BIT(X86_XCPT_NP)
717	\| RT_BIT(X86_XCPT_SS)
718	\| RT_BIT(X86_XCPT_GP)
719	\| RT_BIT(X86_XCPT_PF)
720	\| RT_BIT(X86_XCPT_MF)
721	;
722	#endif
723
724	/* Set up unconditional intercepts and conditions. */
725	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a #VMEXIT. */
726	\| SVM_CTRL1_INTERCEPT_NMI /* Non-maskable interrupts causes a #VMEXIT. */
727	\| SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a #VMEXIT. */
728	\| SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a #VMEXIT. */
729	\| SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a #VMEXIT. */
730	\| SVM_CTRL1_INTERCEPT_RSM /* RSM causes a #VMEXIT. */
731	\| SVM_CTRL1_INTERCEPT_HLT /* HLT causes a #VMEXIT. */
732	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO #VMEXITs. */
733	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a #VMEXIT.*/
734	\| SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */
735	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */
736	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
737
738	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a #VMEXIT. */
739	\| SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a #VMEXIT. */
740	\| SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a #VMEXIT. */
741	\| SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a #VMEXIT. */
742	\| SVM_CTRL2_INTERCEPT_STGI /* STGI causes a #VMEXIT. */
743	\| SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a #VMEXIT. */
744	\| SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a #VMEXIT. */
745	\| SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a #VMEXIT. */
746	\| SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a #VMEXIT. */
747	\| SVM_CTRL2_INTERCEPT_MWAIT /* MWAIT causes a #VMEXIT. */
748	\| SVM_CTRL2_INTERCEPT_XSETBV; /* XSETBV causes a #VMEXIT. */
749
750	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
751	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
752
753	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
754	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
755
756	/* Intercept all DRx reads and writes by default. Changed later on. */
757	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
758	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
759
760	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
761	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
762
763	/* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
764	deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
765	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
766
767	/* Set IO and MSR bitmap permission bitmap physical addresses. */
768	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
769	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
770
771	/* No LBR virtualization. */
772	pVmcb->ctrl.u64LBRVirt = 0;
773
774	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
775	pVmcb->ctrl.u64VmcbCleanBits = 0;
776
777	/* The host ASID MBZ, for the guest start with 1. */
778	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
779
780	/*
781	* Setup the PAT MSR (applicable for Nested Paging only).
782	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
783	* so choose type 6 for all PAT slots.
784	*/
785	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
786
787	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
788	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
789
790	/* Without Nested Paging, we need additionally intercepts. */
791	if (!pVM->hm.s.fNestedPaging)
792	{
793	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
794	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
795	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
796
797	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
798	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
799	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
800
801	/* Page faults must be intercepted to implement shadow paging. */
802	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
803	}
804
805	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
806	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
807	#endif
808
809	/* Apply the exceptions intercepts needed by the GIM provider. */
810	if (pVCpu->hm.s.fGIMTrapXcptUD)
811	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_UD);
812
813	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
814	if (fUsePauseFilter)
815	{
816	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
817	if (fPauseFilterThreshold)
818	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
819	}
820
821	/*
822	* The following MSRs are saved/restored automatically during the world-switch.
823	* Don't intercept guest read/write accesses to these MSRs.
824	*/
825	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
826	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
827	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
828	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
829	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
830	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
831	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
832	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
833	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
834	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
835	}
836
837	return VINF_SUCCESS;
838	}
839
840
841	/**
842	* Invalidates a guest page by guest virtual address.
843	*
844	* @returns VBox status code.
845	* @param pVM The cross context VM structure.
846	* @param pVCpu The cross context virtual CPU structure.
847	* @param GCVirt Guest virtual address of the page to invalidate.
848	*/
849	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
850	{
851	AssertReturn(pVM, VERR_INVALID_PARAMETER);
852	Assert(pVM->hm.s.svm.fSupported);
853
854	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
855
856	/* Skip it if a TLB flush is already pending. */
857	if (!fFlushPending)
858	{
859	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
860
861	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
862	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
863
864	#if HC_ARCH_BITS == 32
865	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
866	if (CPUMIsGuestInLongMode(pVCpu))
867	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
868	else
869	#endif
870	{
871	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
872	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
873	}
874	}
875	return VINF_SUCCESS;
876	}
877
878
879	/**
880	* Flushes the appropriate tagged-TLB entries.
881	*
882	* @param pVCpu The cross context virtual CPU structure.
883	*/
884	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
885	{
886	PVM pVM = pVCpu->CTX_SUFF(pVM);
887	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
888	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
889
890	/*
891	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
892	* This can happen both for start & resume due to long jumps back to ring-3.
893	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
894	* so we cannot reuse the ASIDs without flushing.
895	*/
896	bool fNewAsid = false;
897	Assert(pCpu->idCpu != NIL_RTCPUID);
898	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
899	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
900	{
901	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
902	pVCpu->hm.s.fForceTLBFlush = true;
903	fNewAsid = true;
904	}
905
906	/* Set TLB flush state as checked until we return from the world switch. */
907	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
908
909	/* Check for explicit TLB flushes. */
910	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
911	{
912	pVCpu->hm.s.fForceTLBFlush = true;
913	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
914	}
915
916	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
917
918	if (pVM->hm.s.svm.fAlwaysFlushTLB)
919	{
920	/*
921	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
922	*/
923	pCpu->uCurrentAsid = 1;
924	pVCpu->hm.s.uCurrentAsid = 1;
925	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
926	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
927
928	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
929	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
930
931	/* Keep track of last CPU ID even when flushing all the time. */
932	if (fNewAsid)
933	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
934	}
935	else if (pVCpu->hm.s.fForceTLBFlush)
936	{
937	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
938	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
939
940	if (fNewAsid)
941	{
942	++pCpu->uCurrentAsid;
943	bool fHitASIDLimit = false;
944	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
945	{
946	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
947	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
948	fHitASIDLimit = true;
949
950	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
951	{
952	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
953	pCpu->fFlushAsidBeforeUse = true;
954	}
955	else
956	{
957	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
958	pCpu->fFlushAsidBeforeUse = false;
959	}
960	}
961
962	if ( !fHitASIDLimit
963	&& pCpu->fFlushAsidBeforeUse)
964	{
965	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
966	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
967	else
968	{
969	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
970	pCpu->fFlushAsidBeforeUse = false;
971	}
972	}
973
974	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
975	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
976	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
977	}
978	else
979	{
980	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
981	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
982	else
983	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
984	}
985
986	pVCpu->hm.s.fForceTLBFlush = false;
987	}
988
989	/* Update VMCB with the ASID. */
990	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
991	{
992	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
993	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
994	}
995
996	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
997	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
998	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
999	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1000	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1001	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1002	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1003	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1004
1005	#ifdef VBOX_WITH_STATISTICS
1006	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1007	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1008	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1009	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1010	{
1011	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1012	}
1013	else
1014	{
1015	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1016	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1017	}
1018	#endif
1019	}
1020
1021
1022	/** @name 64-bit guest on 32-bit host OS helper functions.
1023	*
1024	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1025	* mode (code segment, paging). These wrappers/helpers perform the necessary
1026	* bits for the 32->64 switcher.
1027	*
1028	* @{ */
1029	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1030	/**
1031	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1032	*
1033	* @returns VBox status code.
1034	* @param HCPhysVmcbHost Physical address of host VMCB.
1035	* @param HCPhysVmcb Physical address of the VMCB.
1036	* @param pCtx Pointer to the guest-CPU context.
1037	* @param pVM The cross context VM structure.
1038	* @param pVCpu The cross context virtual CPU structure.
1039	*/
1040	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1041	{
1042	uint32_t aParam[8];
1043	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1044	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
1045	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1046	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
1047	aParam[4] = VM_RC_ADDR(pVM, pVM);
1048	aParam[5] = 0;
1049	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1050	aParam[7] = 0;
1051
1052	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1053	}
1054
1055
1056	/**
1057	* Executes the specified VMRUN handler in 64-bit mode.
1058	*
1059	* @returns VBox status code.
1060	* @param pVM The cross context VM structure.
1061	* @param pVCpu The cross context virtual CPU structure.
1062	* @param pCtx Pointer to the guest-CPU context.
1063	* @param enmOp The operation to perform.
1064	* @param cParams Number of parameters.
1065	* @param paParam Array of 32-bit parameters.
1066	*/
1067	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1068	uint32_t cParams, uint32_t *paParam)
1069	{
1070	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1071	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1072
1073	NOREF(pCtx);
1074
1075	/* Disable interrupts. */
1076	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1077
1078	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1079	RTCPUID idHostCpu = RTMpCpuId();
1080	CPUMR0SetLApic(pVCpu, idHostCpu);
1081	#endif
1082
1083	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1084	CPUMSetHyperEIP(pVCpu, enmOp);
1085	for (int i = (int)cParams - 1; i >= 0; i--)
1086	CPUMPushHyper(pVCpu, paParam[i]);
1087
1088	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1089	/* Call the switcher. */
1090	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1091	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1092
1093	/* Restore interrupts. */
1094	ASMSetFlags(uOldEFlags);
1095	return rc;
1096	}
1097
1098	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1099	/** @} */
1100
1101
1102	/**
1103	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1104	* the corresponding VMCB Clean bit.
1105	*
1106	* @param pVmcb Pointer to the VM control block.
1107	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1108	*/
1109	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1110	{
1111	if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1112	{
1113	pVmcb->ctrl.u32InterceptException \|= RT_BIT(u32Xcpt);
1114	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1115	}
1116	}
1117
1118
1119	/**
1120	* Removes an exception from the intercept-exception bitmap in the VMCB and
1121	* updates the corresponding VMCB Clean bit.
1122	*
1123	* @param pVmcb Pointer to the VM control block.
1124	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1125	*/
1126	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1127	{
1128	Assert(u32Xcpt != X86_XCPT_DB);
1129	Assert(u32Xcpt != X86_XCPT_AC);
1130	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1131	if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1132	{
1133	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1134	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1135	}
1136	#endif
1137	}
1138
1139
1140	/**
1141	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1142	* Although the guest CR0 is a separate field in the VMCB we have to consider
1143	* the FPU state itself which is shared between the host and the guest.
1144	*
1145	* @returns VBox status code.
1146	* @param pVCpu The cross context virtual CPU structure.
1147	* @param pVmcb Pointer to the VM control block.
1148	* @param pCtx Pointer to the guest-CPU context.
1149	*
1150	* @remarks No-long-jump zone!!!
1151	*/
1152	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1153	{
1154	/*
1155	* Guest CR0.
1156	*/
1157	PVM pVM = pVCpu->CTX_SUFF(pVM);
1158	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1159	{
1160	uint64_t u64GuestCR0 = pCtx->cr0;
1161
1162	/* Always enable caching. */
1163	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1164
1165	/*
1166	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1167	*/
1168	if (!pVM->hm.s.fNestedPaging)
1169	{
1170	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1171	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1172	}
1173
1174	/*
1175	* Guest FPU bits.
1176	*/
1177	bool fInterceptNM = false;
1178	bool fInterceptMF = false;
1179	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1180	if (CPUMIsGuestFPUStateActive(pVCpu))
1181	{
1182	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1183	if (!(pCtx->cr0 & X86_CR0_NE))
1184	{
1185	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1186	fInterceptMF = true;
1187	}
1188	}
1189	else
1190	{
1191	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1192	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1193	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1194	}
1195
1196	/*
1197	* Update the exception intercept bitmap.
1198	*/
1199	if (fInterceptNM)
1200	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1201	else
1202	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1203
1204	if (fInterceptMF)
1205	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1206	else
1207	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1208
1209	pVmcb->guest.u64CR0 = u64GuestCR0;
1210	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1211	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1212	}
1213	}
1214
1215
1216	/**
1217	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1218	*
1219	* @returns VBox status code.
1220	* @param pVCpu The cross context virtual CPU structure.
1221	* @param pVmcb Pointer to the VM control block.
1222	* @param pCtx Pointer to the guest-CPU context.
1223	*
1224	* @remarks No-long-jump zone!!!
1225	*/
1226	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1227	{
1228	PVM pVM = pVCpu->CTX_SUFF(pVM);
1229
1230	/*
1231	* Guest CR2.
1232	*/
1233	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1234	{
1235	pVmcb->guest.u64CR2 = pCtx->cr2;
1236	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1237	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1238	}
1239
1240	/*
1241	* Guest CR3.
1242	*/
1243	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1244	{
1245	if (pVM->hm.s.fNestedPaging)
1246	{
1247	PGMMODE enmShwPagingMode;
1248	#if HC_ARCH_BITS == 32
1249	if (CPUMIsGuestInLongModeEx(pCtx))
1250	enmShwPagingMode = PGMMODE_AMD64_NX;
1251	else
1252	#endif
1253	enmShwPagingMode = PGMGetHostMode(pVM);
1254
1255	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1256	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1257	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1258	pVmcb->guest.u64CR3 = pCtx->cr3;
1259	}
1260	else
1261	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1262
1263	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1264	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1265	}
1266
1267	/*
1268	* Guest CR4.
1269	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1270	*/
1271	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1272	{
1273	uint64_t u64GuestCR4 = pCtx->cr4;
1274	if (!pVM->hm.s.fNestedPaging)
1275	{
1276	switch (pVCpu->hm.s.enmShadowMode)
1277	{
1278	case PGMMODE_REAL:
1279	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1280	AssertFailed();
1281	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1282
1283	case PGMMODE_32_BIT: /* 32-bit paging. */
1284	u64GuestCR4 &= ~X86_CR4_PAE;
1285	break;
1286
1287	case PGMMODE_PAE: /* PAE paging. */
1288	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1289	/** Must use PAE paging as we could use physical memory > 4 GB */
1290	u64GuestCR4 \|= X86_CR4_PAE;
1291	break;
1292
1293	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1294	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1295	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1296	break;
1297	#else
1298	AssertFailed();
1299	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1300	#endif
1301
1302	default: /* shut up gcc */
1303	AssertFailed();
1304	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1305	}
1306	}
1307
1308	pVmcb->guest.u64CR4 = u64GuestCR4;
1309	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1310
1311	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1312	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1313
1314	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1315	}
1316
1317	return VINF_SUCCESS;
1318	}
1319
1320
1321	/**
1322	* Loads the guest segment registers into the VMCB.
1323	*
1324	* @returns VBox status code.
1325	* @param pVCpu The cross context virtual CPU structure.
1326	* @param pVmcb Pointer to the VM control block.
1327	* @param pCtx Pointer to the guest-CPU context.
1328	*
1329	* @remarks No-long-jump zone!!!
1330	*/
1331	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1332	{
1333	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1334	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1335	{
1336	HMSVM_LOAD_SEG_REG(CS, cs);
1337	HMSVM_LOAD_SEG_REG(SS, ss);
1338	HMSVM_LOAD_SEG_REG(DS, ds);
1339	HMSVM_LOAD_SEG_REG(ES, es);
1340	HMSVM_LOAD_SEG_REG(FS, fs);
1341	HMSVM_LOAD_SEG_REG(GS, gs);
1342
1343	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1344	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1345	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1346	}
1347
1348	/* Guest TR. */
1349	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1350	{
1351	HMSVM_LOAD_SEG_REG(TR, tr);
1352	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1353	}
1354
1355	/* Guest LDTR. */
1356	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1357	{
1358	HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1359	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1360	}
1361
1362	/* Guest GDTR. */
1363	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1364	{
1365	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1366	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1367	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1368	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1369	}
1370
1371	/* Guest IDTR. */
1372	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1373	{
1374	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1375	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1376	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1377	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1378	}
1379	}
1380
1381
1382	/**
1383	* Loads the guest MSRs into the VMCB.
1384	*
1385	* @param pVCpu The cross context virtual CPU structure.
1386	* @param pVmcb Pointer to the VM control block.
1387	* @param pCtx Pointer to the guest-CPU context.
1388	*
1389	* @remarks No-long-jump zone!!!
1390	*/
1391	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1392	{
1393	/* Guest Sysenter MSRs. */
1394	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1395	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1396	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1397
1398	/*
1399	* Guest EFER MSR.
1400	* AMD-V requires guest EFER.SVME to be set. Weird.
1401	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1402	*/
1403	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1404	{
1405	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1406	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1407	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1408	}
1409
1410	/* 64-bit MSRs. */
1411	if (CPUMIsGuestInLongModeEx(pCtx))
1412	{
1413	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1414	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1415	}
1416	else
1417	{
1418	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1419	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1420	{
1421	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1422	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1423	}
1424	}
1425
1426
1427	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1428	* be writable in 32-bit mode. Clarify with AMD spec. */
1429	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1430	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1431	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1432	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1433	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1434	}
1435
1436
1437	/**
1438	* Loads the guest state into the VMCB and programs the necessary intercepts
1439	* accordingly.
1440	*
1441	* @param pVCpu The cross context virtual CPU structure.
1442	* @param pVmcb Pointer to the VM control block.
1443	* @param pCtx Pointer to the guest-CPU context.
1444	*
1445	* @remarks No-long-jump zone!!!
1446	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1447	*/
1448	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1449	{
1450	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1451	return;
1452	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1453	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1454
1455	bool fInterceptMovDRx = false;
1456
1457	/*
1458	* Anyone single stepping on the host side? If so, we'll have to use the
1459	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1460	* the VMM level like the VT-x implementations does.
1461	*/
1462	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1463	if (fStepping)
1464	{
1465	pVCpu->hm.s.fClearTrapFlag = true;
1466	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1467	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1468	}
1469	else
1470	Assert(!DBGFIsStepping(pVCpu));
1471
1472	if ( fStepping
1473	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1474	{
1475	/*
1476	* Use the combined guest and host DRx values found in the hypervisor
1477	* register set because the debugger has breakpoints active or someone
1478	* is single stepping on the host side.
1479	*
1480	* Note! DBGF expects a clean DR6 state before executing guest code.
1481	*/
1482	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1483	if ( CPUMIsGuestInLongModeEx(pCtx)
1484	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1485	{
1486	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1487	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1488	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1489	}
1490	else
1491	#endif
1492	if (!CPUMIsHyperDebugStateActive(pVCpu))
1493	{
1494	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1495	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1496	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1497	}
1498
1499	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1500	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1501	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1502	{
1503	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1504	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1505	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1506	pVCpu->hm.s.fUsingHyperDR7 = true;
1507	}
1508
1509	/** @todo If we cared, we could optimize to allow the guest to read registers
1510	* with the same values. */
1511	fInterceptMovDRx = true;
1512	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1513	}
1514	else
1515	{
1516	/*
1517	* Update DR6, DR7 with the guest values if necessary.
1518	*/
1519	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1520	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1521	{
1522	pVmcb->guest.u64DR7 = pCtx->dr[7];
1523	pVmcb->guest.u64DR6 = pCtx->dr[6];
1524	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1525	pVCpu->hm.s.fUsingHyperDR7 = false;
1526	}
1527
1528	/*
1529	* If the guest has enabled debug registers, we need to load them prior to
1530	* executing guest code so they'll trigger at the right time.
1531	*/
1532	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1533	{
1534	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1535	if ( CPUMIsGuestInLongModeEx(pCtx)
1536	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1537	{
1538	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1539	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1540	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1541	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1542	}
1543	else
1544	#endif
1545	if (!CPUMIsGuestDebugStateActive(pVCpu))
1546	{
1547	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1548	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1549	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1550	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1551	}
1552	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1553	}
1554	/*
1555	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1556	* intercept #DB as DR6 is updated in the VMCB.
1557	*
1558	* Note! If we cared and dared, we could skip intercepting \#DB here.
1559	* However, \#DB shouldn't be performance critical, so we'll play safe
1560	* and keep the code similar to the VT-x code and always intercept it.
1561	*/
1562	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1563	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1564	&& !CPUMIsGuestDebugStateActive(pVCpu))
1565	#else
1566	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1567	#endif
1568	{
1569	fInterceptMovDRx = true;
1570	}
1571	}
1572
1573	Assert(pVmcb->ctrl.u32InterceptException & RT_BIT_32(X86_XCPT_DB));
1574	if (fInterceptMovDRx)
1575	{
1576	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1577	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1578	{
1579	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1580	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1581	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1582	}
1583	}
1584	else
1585	{
1586	if ( pVmcb->ctrl.u16InterceptRdDRx
1587	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1588	{
1589	pVmcb->ctrl.u16InterceptRdDRx = 0;
1590	pVmcb->ctrl.u16InterceptWrDRx = 0;
1591	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1592	}
1593	}
1594
1595	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1596	}
1597
1598
1599	/**
1600	* Loads the guest APIC state (currently just the TPR).
1601	*
1602	* @returns VBox status code.
1603	* @param pVCpu The cross context virtual CPU structure.
1604	* @param pVmcb Pointer to the VM control block.
1605	* @param pCtx Pointer to the guest-CPU context.
1606	*/
1607	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1608	{
1609	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1610	return VINF_SUCCESS;
1611
1612	bool fPendingIntr;
1613	uint8_t u8Tpr;
1614	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1615	AssertRCReturn(rc, rc);
1616
1617	/* Assume that we need to trap all TPR accesses and thus need not check on
1618	every #VMEXIT if we should update the TPR. */
1619	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1620	pVCpu->hm.s.svm.fSyncVTpr = false;
1621
1622	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1623	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1624	{
1625	pCtx->msrLSTAR = u8Tpr;
1626
1627	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1628	if (fPendingIntr)
1629	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1630	else
1631	{
1632	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1633	pVCpu->hm.s.svm.fSyncVTpr = true;
1634	}
1635	}
1636	else
1637	{
1638	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1639	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1640
1641	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1642	if (fPendingIntr)
1643	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1644	else
1645	{
1646	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1647	pVCpu->hm.s.svm.fSyncVTpr = true;
1648	}
1649
1650	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1651	}
1652
1653	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1654	return rc;
1655	}
1656
1657
1658	/**
1659	* Loads the exception interrupts required for guest execution in the VMCB.
1660	*
1661	* @returns VBox status code.
1662	* @param pVCpu The cross context virtual CPU structure.
1663	* @param pVmcb Pointer to the VM control block.
1664	* @param pCtx Pointer to the guest-CPU context.
1665	*/
1666	static int hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1667	{
1668	int rc = VINF_SUCCESS;
1669	NOREF(pCtx);
1670	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1671	{
1672	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1673	if (pVCpu->hm.s.fGIMTrapXcptUD)
1674	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1675	else
1676	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1677	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1678	}
1679	return rc;
1680	}
1681
1682
1683	/**
1684	* Sets up the appropriate function to run guest code.
1685	*
1686	* @returns VBox status code.
1687	* @param pVCpu The cross context virtual CPU structure.
1688	* @param pCtx Pointer to the guest-CPU context.
1689	*
1690	* @remarks No-long-jump zone!!!
1691	*/
1692	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1693	{
1694	if (CPUMIsGuestInLongModeEx(pCtx))
1695	{
1696	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1697	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1698	#endif
1699	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1700	#if HC_ARCH_BITS == 32
1701	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1702	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1703	#else
1704	/* 64-bit host or hybrid host. */
1705	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1706	#endif
1707	}
1708	else
1709	{
1710	/* Guest is not in long mode, use the 32-bit handler. */
1711	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1712	}
1713	return VINF_SUCCESS;
1714	}
1715
1716
1717	/**
1718	* Enters the AMD-V session.
1719	*
1720	* @returns VBox status code.
1721	* @param pVM The cross context VM structure.
1722	* @param pVCpu The cross context virtual CPU structure.
1723	* @param pCpu Pointer to the CPU info struct.
1724	*/
1725	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1726	{
1727	AssertPtr(pVM);
1728	AssertPtr(pVCpu);
1729	Assert(pVM->hm.s.svm.fSupported);
1730	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1731	NOREF(pVM); NOREF(pCpu);
1732
1733	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1734	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1735
1736	pVCpu->hm.s.fLeaveDone = false;
1737	return VINF_SUCCESS;
1738	}
1739
1740
1741	/**
1742	* Thread-context callback for AMD-V.
1743	*
1744	* @param enmEvent The thread-context event.
1745	* @param pVCpu The cross context virtual CPU structure.
1746	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1747	* @thread EMT(pVCpu)
1748	*/
1749	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1750	{
1751	NOREF(fGlobalInit);
1752
1753	switch (enmEvent)
1754	{
1755	case RTTHREADCTXEVENT_OUT:
1756	{
1757	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1758	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1759	VMCPU_ASSERT_EMT(pVCpu);
1760
1761	/* No longjmps (log-flush, locks) in this fragile context. */
1762	VMMRZCallRing3Disable(pVCpu);
1763
1764	if (!pVCpu->hm.s.fLeaveDone)
1765	{
1766	hmR0SvmLeave(pVCpu);
1767	pVCpu->hm.s.fLeaveDone = true;
1768	}
1769
1770	/* Leave HM context, takes care of local init (term). */
1771	int rc = HMR0LeaveCpu(pVCpu);
1772	AssertRC(rc); NOREF(rc);
1773
1774	/* Restore longjmp state. */
1775	VMMRZCallRing3Enable(pVCpu);
1776	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
1777	break;
1778	}
1779
1780	case RTTHREADCTXEVENT_IN:
1781	{
1782	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1783	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1784	VMCPU_ASSERT_EMT(pVCpu);
1785
1786	/* No longjmps (log-flush, locks) in this fragile context. */
1787	VMMRZCallRing3Disable(pVCpu);
1788
1789	/*
1790	* Initialize the bare minimum state required for HM. This takes care of
1791	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1792	*/
1793	int rc = HMR0EnterCpu(pVCpu);
1794	AssertRC(rc); NOREF(rc);
1795	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1796
1797	pVCpu->hm.s.fLeaveDone = false;
1798
1799	/* Restore longjmp state. */
1800	VMMRZCallRing3Enable(pVCpu);
1801	break;
1802	}
1803
1804	default:
1805	break;
1806	}
1807	}
1808
1809
1810	/**
1811	* Saves the host state.
1812	*
1813	* @returns VBox status code.
1814	* @param pVM The cross context VM structure.
1815	* @param pVCpu The cross context virtual CPU structure.
1816	*
1817	* @remarks No-long-jump zone!!!
1818	*/
1819	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1820	{
1821	NOREF(pVM);
1822	NOREF(pVCpu);
1823	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1824	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1825	return VINF_SUCCESS;
1826	}
1827
1828
1829	/**
1830	* Loads the guest state into the VMCB.
1831	*
1832	* The CPU state will be loaded from these fields on every successful VM-entry.
1833	* Also sets up the appropriate VMRUN function to execute guest code based on
1834	* the guest CPU mode.
1835	*
1836	* @returns VBox status code.
1837	* @param pVM The cross context VM structure.
1838	* @param pVCpu The cross context virtual CPU structure.
1839	* @param pCtx Pointer to the guest-CPU context.
1840	*
1841	* @remarks No-long-jump zone!!!
1842	*/
1843	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1844	{
1845	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1846	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1847
1848	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1849
1850	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1851	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1852
1853	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1854	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1855
1856	pVmcb->guest.u64RIP = pCtx->rip;
1857	pVmcb->guest.u64RSP = pCtx->rsp;
1858	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1859	pVmcb->guest.u64RAX = pCtx->rax;
1860
1861	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1862	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1863
1864	rc = hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1865	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1866
1867	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1868	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1869
1870	/* Clear any unused and reserved bits. */
1871	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1872	\| HM_CHANGED_GUEST_RSP
1873	\| HM_CHANGED_GUEST_RFLAGS
1874	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1875	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1876	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1877	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1878	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1879	\| HM_CHANGED_SVM_RESERVED2
1880	\| HM_CHANGED_SVM_RESERVED3
1881	\| HM_CHANGED_SVM_RESERVED4);
1882
1883	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1884	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1885	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1886	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1887
1888	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss.Sel, pCtx->rsp));
1889	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1890	return rc;
1891	}
1892
1893
1894	/**
1895	* Loads the state shared between the host and guest into the
1896	* VMCB.
1897	*
1898	* @param pVCpu The cross context virtual CPU structure.
1899	* @param pVmcb Pointer to the VM control block.
1900	* @param pCtx Pointer to the guest-CPU context.
1901	*
1902	* @remarks No-long-jump zone!!!
1903	*/
1904	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1905	{
1906	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1907	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1908
1909	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1910	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1911
1912	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1913	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1914
1915	/* Unused on AMD-V. */
1916	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
1917
1918	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1919	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1920	}
1921
1922
1923	/**
1924	* Saves the entire guest state from the VMCB into the
1925	* guest-CPU context. Currently there is no residual state left in the CPU that
1926	* is not updated in the VMCB.
1927	*
1928	* @returns VBox status code.
1929	* @param pVCpu The cross context virtual CPU structure.
1930	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1931	* out-of-sync. Make sure to update the required fields
1932	* before using them.
1933	*/
1934	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1935	{
1936	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1937
1938	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1939
1940	pMixedCtx->rip = pVmcb->guest.u64RIP;
1941	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1942	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1943	pMixedCtx->rax = pVmcb->guest.u64RAX;
1944
1945	/*
1946	* Guest interrupt shadow.
1947	*/
1948	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1949	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1950	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1951	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1952
1953	/*
1954	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1955	*/
1956	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1957
1958	/*
1959	* Guest MSRs.
1960	*/
1961	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1962	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1963	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1964	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1965	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1966	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1967	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1968	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1969
1970	/*
1971	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1972	*/
1973	HMSVM_SAVE_SEG_REG(CS, cs);
1974	HMSVM_SAVE_SEG_REG(SS, ss);
1975	HMSVM_SAVE_SEG_REG(DS, ds);
1976	HMSVM_SAVE_SEG_REG(ES, es);
1977	HMSVM_SAVE_SEG_REG(FS, fs);
1978	HMSVM_SAVE_SEG_REG(GS, gs);
1979
1980	/*
1981	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1982	* register (yet).
1983	*/
1984	/** @todo SELM might need to be fixed as it too should not care about the
1985	* granularity bit. See @bugref{6785}. */
1986	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1987	&& pMixedCtx->cs.Attr.n.u1Present
1988	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1989	{
1990	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1991	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1992	}
1993
1994	#ifdef VBOX_STRICT
1995	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1996	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1997	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1998	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1999	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
2000	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
2001	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
2002
2003	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2004	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2005	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2006	HMSVM_ASSERT_SEG_GRANULARITY(es);
2007	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2008	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2009
2010	# undef HMSVM_ASSERT_SEL_GRANULARITY
2011	#endif
2012
2013	/*
2014	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2015	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2016	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2017	* See AMD spec. 15.5.1 "Basic operation".
2018	*/
2019	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2020	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2021
2022	/*
2023	* Guest TR.
2024	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2025	* between Intel and AMD. See @bugref{6208#c39}.
2026	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2027	*/
2028	HMSVM_SAVE_SEG_REG(TR, tr);
2029	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2030	{
2031	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2032	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2033	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2034	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2035	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2036	}
2037
2038	/*
2039	* Guest Descriptor-Table registers.
2040	*/
2041	HMSVM_SAVE_SEG_REG(LDTR, ldtr);
2042	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2043	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2044
2045	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2046	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2047
2048	/*
2049	* Guest Debug registers.
2050	*/
2051	if (!pVCpu->hm.s.fUsingHyperDR7)
2052	{
2053	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2054	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2055	}
2056	else
2057	{
2058	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2059	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2060	}
2061
2062	/*
2063	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2064	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2065	*/
2066	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
2067	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2068	{
2069	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2070	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2071	}
2072	}
2073
2074
2075	/**
2076	* Does the necessary state syncing before returning to ring-3 for any reason
2077	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2078	*
2079	* @param pVCpu The cross context virtual CPU structure.
2080	*
2081	* @remarks No-long-jmp zone!!!
2082	*/
2083	static void hmR0SvmLeave(PVMCPU pVCpu)
2084	{
2085	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2086	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2087	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2088
2089	/*
2090	* !!! IMPORTANT !!!
2091	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2092	*/
2093
2094	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2095	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2096	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2097
2098	/*
2099	* Restore host debug registers if necessary and resync on next R0 reentry.
2100	*/
2101	#ifdef VBOX_STRICT
2102	if (CPUMIsHyperDebugStateActive(pVCpu))
2103	{
2104	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2105	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2106	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2107	}
2108	#endif
2109	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2110	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2111
2112	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2113	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2114
2115	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2116	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2117	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2118	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2119	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2120
2121	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2122	}
2123
2124
2125	/**
2126	* Leaves the AMD-V session.
2127	*
2128	* @returns VBox status code.
2129	* @param pVCpu The cross context virtual CPU structure.
2130	*/
2131	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2132	{
2133	HM_DISABLE_PREEMPT();
2134	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2135	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2136
2137	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2138	and done this from the SVMR0ThreadCtxCallback(). */
2139	if (!pVCpu->hm.s.fLeaveDone)
2140	{
2141	hmR0SvmLeave(pVCpu);
2142	pVCpu->hm.s.fLeaveDone = true;
2143	}
2144
2145	/*
2146	* !!! IMPORTANT !!!
2147	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2148	*/
2149
2150	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2151	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2152	VMMR0ThreadCtxHookDisable(pVCpu);
2153
2154	/* Leave HM context. This takes care of local init (term). */
2155	int rc = HMR0LeaveCpu(pVCpu);
2156
2157	HM_RESTORE_PREEMPT();
2158	return rc;
2159	}
2160
2161
2162	/**
2163	* Does the necessary state syncing before doing a longjmp to ring-3.
2164	*
2165	* @returns VBox status code.
2166	* @param pVCpu The cross context virtual CPU structure.
2167	*
2168	* @remarks No-long-jmp zone!!!
2169	*/
2170	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2171	{
2172	return hmR0SvmLeaveSession(pVCpu);
2173	}
2174
2175
2176	/**
2177	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2178	* any remaining host state) before we longjump to ring-3 and possibly get
2179	* preempted.
2180	*
2181	* @param pVCpu The cross context virtual CPU structure.
2182	* @param enmOperation The operation causing the ring-3 longjump.
2183	* @param pvUser The user argument (pointer to the possibly
2184	* out-of-date guest-CPU context).
2185	*/
2186	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2187	{
2188	RT_NOREF_PV(pvUser);
2189
2190	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2191	{
2192	/*
2193	* !!! IMPORTANT !!!
2194	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2195	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2196	*/
2197	VMMRZCallRing3RemoveNotification(pVCpu);
2198	VMMRZCallRing3Disable(pVCpu);
2199	HM_DISABLE_PREEMPT();
2200
2201	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2202	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2203
2204	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2205	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2206
2207	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2208	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2209	VMMR0ThreadCtxHookDisable(pVCpu);
2210
2211	/* Leave HM context. This takes care of local init (term). */
2212	HMR0LeaveCpu(pVCpu);
2213
2214	HM_RESTORE_PREEMPT();
2215	return VINF_SUCCESS;
2216	}
2217
2218	Assert(pVCpu);
2219	Assert(pvUser);
2220	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2221	HMSVM_ASSERT_PREEMPT_SAFE();
2222
2223	VMMRZCallRing3Disable(pVCpu);
2224	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2225
2226	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2227	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2228	AssertRCReturn(rc, rc);
2229
2230	VMMRZCallRing3Enable(pVCpu);
2231	return VINF_SUCCESS;
2232	}
2233
2234
2235	/**
2236	* Take necessary actions before going back to ring-3.
2237	*
2238	* An action requires us to go back to ring-3. This function does the necessary
2239	* steps before we can safely return to ring-3. This is not the same as longjmps
2240	* to ring-3, this is voluntary.
2241	*
2242	* @param pVM The cross context VM structure.
2243	* @param pVCpu The cross context virtual CPU structure.
2244	* @param pCtx Pointer to the guest-CPU context.
2245	* @param rcExit The reason for exiting to ring-3. Can be
2246	* VINF_VMM_UNKNOWN_RING3_CALL.
2247	*/
2248	static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2249	{
2250	Assert(pVM);
2251	Assert(pVCpu);
2252	Assert(pCtx);
2253	HMSVM_ASSERT_PREEMPT_SAFE();
2254
2255	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2256	VMMRZCallRing3Disable(pVCpu);
2257	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2258
2259	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2260	if (pVCpu->hm.s.Event.fPending)
2261	{
2262	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2263	Assert(!pVCpu->hm.s.Event.fPending);
2264	}
2265
2266	/* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2267	and if we're injecting an event we should have a TRPM trap pending. */
2268	AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu), ("rcExit=%Rrc\n", rcExit));
2269	AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu), ("rcExit=%Rrc\n", rcExit));
2270
2271	/* Sync. the necessary state for going back to ring-3. */
2272	hmR0SvmLeaveSession(pVCpu);
2273	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2274
2275	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2276	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2277	\| CPUM_CHANGED_LDTR
2278	\| CPUM_CHANGED_GDTR
2279	\| CPUM_CHANGED_IDTR
2280	\| CPUM_CHANGED_TR
2281	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2282	if ( pVM->hm.s.fNestedPaging
2283	&& CPUMIsGuestPagingEnabledEx(pCtx))
2284	{
2285	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2286	}
2287
2288	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2289	if (rcExit != VINF_EM_RAW_INTERRUPT)
2290	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2291
2292	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2293
2294	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2295	VMMRZCallRing3RemoveNotification(pVCpu);
2296	VMMRZCallRing3Enable(pVCpu);
2297	}
2298
2299
2300	/**
2301	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2302	* intercepts.
2303	*
2304	* @param pVM The cross context VM structure.
2305	* @param pVCpu The cross context virtual CPU structure.
2306	*
2307	* @remarks No-long-jump zone!!!
2308	*/
2309	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu)
2310	{
2311	bool fParavirtTsc;
2312	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2313	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2314	if (fCanUseRealTsc)
2315	{
2316	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2317	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2318	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2319	}
2320	else
2321	{
2322	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
2323	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
2324	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2325	}
2326	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2327
2328	/** @todo later optimize this to be done elsewhere and not before every
2329	* VM-entry. */
2330	if (fParavirtTsc)
2331	{
2332	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2333	information before every VM-entry, hence disable it for performance sake. */
2334	#if 0
2335	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2336	AssertRC(rc);
2337	#endif
2338	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2339	}
2340	}
2341
2342
2343	/**
2344	* Sets an event as a pending event to be injected into the guest.
2345	*
2346	* @param pVCpu The cross context virtual CPU structure.
2347	* @param pEvent Pointer to the SVM event.
2348	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2349	* page-fault.
2350	*
2351	* @remarks Statistics counter assumes this is a guest event being reflected to
2352	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2353	*/
2354	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2355	{
2356	Assert(!pVCpu->hm.s.Event.fPending);
2357	Assert(pEvent->n.u1Valid);
2358
2359	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2360	pVCpu->hm.s.Event.fPending = true;
2361	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2362
2363	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2364	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2365	}
2366
2367
2368	/**
2369	* Injects an event into the guest upon VMRUN by updating the relevant field
2370	* in the VMCB.
2371	*
2372	* @param pVCpu The cross context virtual CPU structure.
2373	* @param pVmcb Pointer to the guest VM control block.
2374	* @param pCtx Pointer to the guest-CPU context.
2375	* @param pEvent Pointer to the event.
2376	*
2377	* @remarks No-long-jump zone!!!
2378	* @remarks Requires CR0!
2379	*/
2380	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2381	{
2382	NOREF(pVCpu); NOREF(pCtx);
2383
2384	pVmcb->ctrl.EventInject.u = pEvent->u;
2385	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2386
2387	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2388	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2389	}
2390
2391
2392
2393	/**
2394	* Converts any TRPM trap into a pending HM event. This is typically used when
2395	* entering from ring-3 (not longjmp returns).
2396	*
2397	* @param pVCpu The cross context virtual CPU structure.
2398	*/
2399	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2400	{
2401	Assert(TRPMHasTrap(pVCpu));
2402	Assert(!pVCpu->hm.s.Event.fPending);
2403
2404	uint8_t uVector;
2405	TRPMEVENT enmTrpmEvent;
2406	RTGCUINT uErrCode;
2407	RTGCUINTPTR GCPtrFaultAddress;
2408	uint8_t cbInstr;
2409
2410	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2411	AssertRC(rc);
2412
2413	SVMEVENT Event;
2414	Event.u = 0;
2415	Event.n.u1Valid = 1;
2416	Event.n.u8Vector = uVector;
2417
2418	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2419	if (enmTrpmEvent == TRPM_TRAP)
2420	{
2421	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2422	switch (uVector)
2423	{
2424	case X86_XCPT_NMI:
2425	{
2426	Event.n.u3Type = SVM_EVENT_NMI;
2427	break;
2428	}
2429
2430	case X86_XCPT_PF:
2431	case X86_XCPT_DF:
2432	case X86_XCPT_TS:
2433	case X86_XCPT_NP:
2434	case X86_XCPT_SS:
2435	case X86_XCPT_GP:
2436	case X86_XCPT_AC:
2437	{
2438	Event.n.u1ErrorCodeValid = 1;
2439	Event.n.u32ErrorCode = uErrCode;
2440	break;
2441	}
2442	}
2443	}
2444	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2445	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2446	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2447	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2448	else
2449	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2450
2451	rc = TRPMResetTrap(pVCpu);
2452	AssertRC(rc);
2453
2454	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2455	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2456
2457	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2458	}
2459
2460
2461	/**
2462	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2463	* AMD-V to execute any instruction.
2464	*
2465	* @param pVCpu The cross context virtual CPU structure.
2466	*/
2467	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2468	{
2469	Assert(pVCpu->hm.s.Event.fPending);
2470	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2471
2472	SVMEVENT Event;
2473	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2474
2475	uint8_t uVector = Event.n.u8Vector;
2476	uint8_t uVectorType = Event.n.u3Type;
2477
2478	TRPMEVENT enmTrapType;
2479	switch (uVectorType)
2480	{
2481	case SVM_EVENT_EXTERNAL_IRQ:
2482	enmTrapType = TRPM_HARDWARE_INT;
2483	break;
2484	case SVM_EVENT_SOFTWARE_INT:
2485	enmTrapType = TRPM_SOFTWARE_INT;
2486	break;
2487	case SVM_EVENT_EXCEPTION:
2488	case SVM_EVENT_NMI:
2489	enmTrapType = TRPM_TRAP;
2490	break;
2491	default:
2492	AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2493	enmTrapType = TRPM_32BIT_HACK;
2494	break;
2495	}
2496
2497	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2498
2499	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2500	AssertRC(rc);
2501
2502	if (Event.n.u1ErrorCodeValid)
2503	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2504
2505	if ( uVectorType == SVM_EVENT_EXCEPTION
2506	&& uVector == X86_XCPT_PF)
2507	{
2508	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2509	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2510	}
2511	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2512	{
2513	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2514	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2515	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2516	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2517	}
2518	pVCpu->hm.s.Event.fPending = false;
2519	}
2520
2521
2522	/**
2523	* Gets the guest's interrupt-shadow.
2524	*
2525	* @returns The guest's interrupt-shadow.
2526	* @param pVCpu The cross context virtual CPU structure.
2527	* @param pCtx Pointer to the guest-CPU context.
2528	*
2529	* @remarks No-long-jump zone!!!
2530	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2531	*/
2532	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2533	{
2534	/*
2535	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2536	* inhibit interrupts or clear any existing interrupt-inhibition.
2537	*/
2538	uint32_t uIntrState = 0;
2539	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2540	{
2541	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2542	{
2543	/*
2544	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2545	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2546	*/
2547	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2548	}
2549	else
2550	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2551	}
2552	return uIntrState;
2553	}
2554
2555
2556	/**
2557	* Sets the virtual interrupt intercept control in the VMCB which
2558	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
2559	* receive interrupts.
2560	*
2561	* @param pVmcb Pointer to the VM control block.
2562	*/
2563	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2564	{
2565	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2566	{
2567	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2568	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2569	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
2570	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2571
2572	Log4(("Setting VINTR intercept\n"));
2573	}
2574	}
2575
2576
2577	/**
2578	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2579	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
2580	* virtual NMIs.
2581	*
2582	* @param pVmcb Pointer to the VM control block.
2583	*/
2584	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
2585	{
2586	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET))
2587	{
2588	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_IRET;
2589	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2590
2591	Log4(("Setting IRET intercept\n"));
2592	}
2593	}
2594
2595
2596	/**
2597	* Clears the IRET intercept control in the VMCB.
2598	*
2599	* @param pVmcb Pointer to the VM control block.
2600	*/
2601	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
2602	{
2603	if (pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET)
2604	{
2605	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_IRET;
2606	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2607
2608	Log4(("Clearing IRET intercept\n"));
2609	}
2610	}
2611
2612
2613	/**
2614	* Evaluates the event to be delivered to the guest and sets it as the pending
2615	* event.
2616	*
2617	* @param pVCpu The cross context virtual CPU structure.
2618	* @param pCtx Pointer to the guest-CPU context.
2619	*/
2620	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2621	{
2622	Assert(!pVCpu->hm.s.Event.fPending);
2623	Log4Func(("\n"));
2624
2625	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2626	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2627	bool const fBlockNmi = RT_BOOL(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
2628	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2629
2630	#ifdef VBOX_WITH_NEW_APIC
2631	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2632	APICUpdatePendingInterrupts(pVCpu);
2633	#endif
2634
2635	SVMEVENT Event;
2636	Event.u = 0;
2637	/** @todo SMI. SMIs take priority over NMIs. */
2638	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2639	{
2640	if (fBlockNmi)
2641	hmR0SvmSetIretIntercept(pVmcb);
2642	else if (fIntShadow)
2643	hmR0SvmSetVirtIntrIntercept(pVmcb);
2644	else
2645	{
2646	Log4(("Pending NMI\n"));
2647
2648	Event.n.u1Valid = 1;
2649	Event.n.u8Vector = X86_XCPT_NMI;
2650	Event.n.u3Type = SVM_EVENT_NMI;
2651
2652	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2653	hmR0SvmSetIretIntercept(pVmcb);
2654	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2655	}
2656	}
2657	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
2658	&& !pVCpu->hm.s.fSingleInstruction)
2659	{
2660	/*
2661	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
2662	* a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
2663	*/
2664	if ( !fBlockInt
2665	&& !fIntShadow)
2666	{
2667	uint8_t u8Interrupt;
2668	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2669	if (RT_SUCCESS(rc))
2670	{
2671	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2672
2673	Event.n.u1Valid = 1;
2674	Event.n.u8Vector = u8Interrupt;
2675	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2676
2677	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2678	}
2679	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
2680	{
2681	/*
2682	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
2683	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
2684	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
2685	*/
2686	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
2687	}
2688	else
2689	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2690	}
2691	else
2692	hmR0SvmSetVirtIntrIntercept(pVmcb);
2693	}
2694	}
2695
2696
2697	/**
2698	* Injects any pending events into the guest if the guest is in a state to
2699	* receive them.
2700	*
2701	* @param pVCpu The cross context virtual CPU structure.
2702	* @param pCtx Pointer to the guest-CPU context.
2703	*/
2704	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2705	{
2706	Assert(!TRPMHasTrap(pVCpu));
2707	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2708
2709	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2710	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2711	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2712
2713	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2714	{
2715	SVMEVENT Event;
2716	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2717	Assert(Event.n.u1Valid);
2718	#ifdef VBOX_STRICT
2719	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2720	{
2721	Assert(!fBlockInt);
2722	Assert(!fIntShadow);
2723	}
2724	else if (Event.n.u3Type == SVM_EVENT_NMI)
2725	Assert(!fIntShadow);
2726	#endif
2727
2728	Log4(("Injecting pending HM event.\n"));
2729	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2730	pVCpu->hm.s.Event.fPending = false;
2731
2732	#ifdef VBOX_WITH_STATISTICS
2733	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2734	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2735	else
2736	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2737	#endif
2738	}
2739
2740	/* Update the guest interrupt shadow in the VMCB. */
2741	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2742	NOREF(fBlockInt);
2743	}
2744
2745
2746	/**
2747	* Reports world-switch error and dumps some useful debug info.
2748	*
2749	* @param pVM The cross context VM structure.
2750	* @param pVCpu The cross context virtual CPU structure.
2751	* @param rcVMRun The return code from VMRUN (or
2752	* VERR_SVM_INVALID_GUEST_STATE for invalid
2753	* guest-state).
2754	* @param pCtx Pointer to the guest-CPU context.
2755	*/
2756	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2757	{
2758	NOREF(pCtx);
2759	HMSVM_ASSERT_PREEMPT_SAFE();
2760	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2761
2762	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2763	{
2764	HMDumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
2765	#ifdef VBOX_STRICT
2766	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2767	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2768	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2769	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2770	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2771	Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2772	Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2773	Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2774	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2775	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2776	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2777
2778	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2779	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2780	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2781
2782	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2783	Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2784	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2785	Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2786	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2787	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2788	Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2789	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2790	Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2791	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2792
2793	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2794	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2795	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2796	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2797	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2798	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2799	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2800	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2801	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2802	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2803	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2804	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2805	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2806	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2807	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2808	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2809	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2810
2811	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2812	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2813
2814	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2815	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2816	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2817	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2818	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2819	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2820	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2821	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2822	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2823	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2824	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2825	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2826	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2827	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2828	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2829	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2830	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2831	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2832	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2833	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2834
2835	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2836	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2837
2838	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2839	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2840	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2841	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2842
2843	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2844	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2845
2846	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2847	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2848	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2849	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2850
2851	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2852	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2853	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2854	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2855	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2856	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2857	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2858
2859	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2860	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2861	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2862	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2863
2864	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2865	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2866	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2867
2868	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2869	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2870	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2871	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2872	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2873	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2874	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2875	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2876	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2877	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2878	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2879	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2880	#endif /* VBOX_STRICT */
2881	}
2882	else
2883	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2884
2885	NOREF(pVmcb);
2886	}
2887
2888
2889	/**
2890	* Check per-VM and per-VCPU force flag actions that require us to go back to
2891	* ring-3 for one reason or another.
2892	*
2893	* @returns VBox status code (information status code included).
2894	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2895	* ring-3.
2896	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2897	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2898	* interrupts)
2899	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2900	* all EMTs to be in ring-3.
2901	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2902	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2903	* to the EM loop.
2904	*
2905	* @param pVM The cross context VM structure.
2906	* @param pVCpu The cross context virtual CPU structure.
2907	* @param pCtx Pointer to the guest-CPU context.
2908	*/
2909	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2910	{
2911	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2912
2913	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2914	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2915	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2916
2917	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2918	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2919	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2920	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2921	{
2922	/* Pending PGM C3 sync. */
2923	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2924	{
2925	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2926	if (rc != VINF_SUCCESS)
2927	{
2928	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2929	return rc;
2930	}
2931	}
2932
2933	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2934	/* -XXX- what was that about single stepping? */
2935	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2936	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2937	{
2938	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2939	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2940	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2941	return rc;
2942	}
2943
2944	/* Pending VM request packets, such as hardware interrupts. */
2945	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2946	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2947	{
2948	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2949	return VINF_EM_PENDING_REQUEST;
2950	}
2951
2952	/* Pending PGM pool flushes. */
2953	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2954	{
2955	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2956	return VINF_PGM_POOL_FLUSH_PENDING;
2957	}
2958
2959	/* Pending DMA requests. */
2960	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2961	{
2962	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2963	return VINF_EM_RAW_TO_R3;
2964	}
2965	}
2966
2967	return VINF_SUCCESS;
2968	}
2969
2970
2971	/**
2972	* Does the preparations before executing guest code in AMD-V.
2973	*
2974	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2975	* recompiler. We must be cautious what we do here regarding committing
2976	* guest-state information into the VMCB assuming we assuredly execute the guest
2977	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
2978	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2979	* that the recompiler can (and should) use them when it resumes guest
2980	* execution. Otherwise such operations must be done when we can no longer
2981	* exit to ring-3.
2982	*
2983	* @returns VBox status code (informational status codes included).
2984	* @retval VINF_SUCCESS if we can proceed with running the guest.
2985	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2986	*
2987	* @param pVM The cross context VM structure.
2988	* @param pVCpu The cross context virtual CPU structure.
2989	* @param pCtx Pointer to the guest-CPU context.
2990	* @param pSvmTransient Pointer to the SVM transient structure.
2991	*/
2992	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2993	{
2994	HMSVM_ASSERT_PREEMPT_SAFE();
2995
2996	/* Check force flag actions that might require us to go back to ring-3. */
2997	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2998	if (rc != VINF_SUCCESS)
2999	return rc;
3000
3001	if (TRPMHasTrap(pVCpu))
3002	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3003	else if (!pVCpu->hm.s.Event.fPending)
3004	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
3005
3006	/*
3007	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3008	* Just do it in software, see @bugref{8411}.
3009	* NB: If we could continue a task switch exit we wouldn't need to do this.
3010	*/
3011	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
3012	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
3013	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3014
3015	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
3016	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3017	#endif
3018
3019	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3020	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3021	AssertRCReturn(rc, rc);
3022	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3023
3024	/*
3025	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3026	* so we can update it on the way back if the guest changed the TPR.
3027	*/
3028	if (pVCpu->hm.s.svm.fSyncVTpr)
3029	{
3030	if (pVM->hm.s.fTPRPatchingActive)
3031	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3032	else
3033	{
3034	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3035	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3036	}
3037	}
3038
3039	/*
3040	* No longjmps to ring-3 from this point on!!!
3041	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3042	* This also disables flushing of the R0-logger instance (if any).
3043	*/
3044	VMMRZCallRing3Disable(pVCpu);
3045
3046	/*
3047	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3048	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3049	*
3050	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3051	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3052	*
3053	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3054	* executing guest code.
3055	*/
3056	pSvmTransient->fEFlags = ASMIntDisableFlags();
3057	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3058	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3059	{
3060	ASMSetFlags(pSvmTransient->fEFlags);
3061	VMMRZCallRing3Enable(pVCpu);
3062	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3063	return VINF_EM_RAW_TO_R3;
3064	}
3065	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3066	{
3067	ASMSetFlags(pSvmTransient->fEFlags);
3068	VMMRZCallRing3Enable(pVCpu);
3069	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3070	return VINF_EM_RAW_INTERRUPT;
3071	}
3072
3073	/*
3074	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3075	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3076	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3077	*
3078	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3079	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3080	*/
3081	if (pVCpu->hm.s.Event.fPending)
3082	{
3083	SVMEVENT Event;
3084	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3085	if ( Event.n.u1Valid
3086	&& Event.n.u3Type == SVM_EVENT_NMI
3087	&& Event.n.u8Vector == X86_XCPT_NMI
3088	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3089	{
3090	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3091	}
3092	}
3093
3094	return VINF_SUCCESS;
3095	}
3096
3097
3098	/**
3099	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3100	* means there is no backing out to ring-3 or anywhere else at this
3101	* point.
3102	*
3103	* @param pVM The cross context VM structure.
3104	* @param pVCpu The cross context virtual CPU structure.
3105	* @param pCtx Pointer to the guest-CPU context.
3106	* @param pSvmTransient Pointer to the SVM transient structure.
3107	*
3108	* @remarks Called with preemption disabled.
3109	* @remarks No-long-jump zone!!!
3110	*/
3111	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3112	{
3113	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3114	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3115	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3116
3117	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3118	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3119
3120	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
3121
3122	if ( pVCpu->hm.s.fPreloadGuestFpu
3123	&& !CPUMIsGuestFPUStateActive(pVCpu))
3124	{
3125	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3126	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3127	}
3128
3129	/* Load the state shared between host and guest (FPU, debug). */
3130	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3131	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3132	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3133	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3134	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3135
3136	/* Setup TSC offsetting. */
3137	RTCPUID idCurrentCpu = HMR0GetCurrentCpu()->idCpu;
3138	if ( pSvmTransient->fUpdateTscOffsetting
3139	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3140	{
3141	hmR0SvmUpdateTscOffsetting(pVM, pVCpu);
3142	pSvmTransient->fUpdateTscOffsetting = false;
3143	}
3144
3145	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3146	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3147	pVmcb->ctrl.u64VmcbCleanBits = 0;
3148
3149	/* Store status of the shared guest-host state at the time of VMRUN. */
3150	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3151	if (CPUMIsGuestInLongModeEx(pCtx))
3152	{
3153	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3154	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3155	}
3156	else
3157	#endif
3158	{
3159	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3160	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3161	}
3162	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3163
3164	/* Flush the appropriate tagged-TLB entries. */
3165	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3166	hmR0SvmFlushTaggedTlb(pVCpu);
3167	Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3168
3169	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3170
3171	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3172	to start executing. */
3173
3174	/*
3175	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3176	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3177	*
3178	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3179	*/
3180	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3181	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
3182	{
3183	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3184	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3185	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3186	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3187	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3188	pSvmTransient->fRestoreTscAuxMsr = true;
3189	}
3190	else
3191	{
3192	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3193	pSvmTransient->fRestoreTscAuxMsr = false;
3194	}
3195
3196	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
3197	if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
3198	pVmcb->ctrl.u64VmcbCleanBits = 0;
3199	}
3200
3201
3202	/**
3203	* Wrapper for running the guest code in AMD-V.
3204	*
3205	* @returns VBox strict status code.
3206	* @param pVM The cross context VM structure.
3207	* @param pVCpu The cross context virtual CPU structure.
3208	* @param pCtx Pointer to the guest-CPU context.
3209	*
3210	* @remarks No-long-jump zone!!!
3211	*/
3212	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3213	{
3214	/*
3215	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
3216	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3217	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3218	*/
3219	#ifdef VBOX_WITH_KERNEL_USING_XMM
3220	return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3221	pVCpu->hm.s.svm.pfnVMRun);
3222	#else
3223	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3224	#endif
3225	}
3226
3227
3228	/**
3229	* Performs some essential restoration of state after running guest code in
3230	* AMD-V.
3231	*
3232	* @param pVM The cross context VM structure.
3233	* @param pVCpu The cross context virtual CPU structure.
3234	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3235	* out-of-sync. Make sure to update the required fields
3236	* before using them.
3237	* @param pSvmTransient Pointer to the SVM transient structure.
3238	* @param rcVMRun Return code of VMRUN.
3239	*
3240	* @remarks Called with interrupts disabled.
3241	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
3242	* unconditionally when it is safe to do so.
3243	*/
3244	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3245	{
3246	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3247
3248	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
3249	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
3250
3251	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3252	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3253
3254	/* TSC read must be done early for maximum accuracy. */
3255	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
3256	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
3257
3258	if (pSvmTransient->fRestoreTscAuxMsr)
3259	{
3260	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
3261	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
3262	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
3263	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3264	}
3265
3266	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3267	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3268	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3269
3270	Assert(!(ASMGetFlags() & X86_EFL_IF));
3271	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
3272	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3273
3274	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3275	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3276	{
3277	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3278	return;
3279	}
3280
3281	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3282	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
3283	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
3284	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3285
3286	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3287
3288	if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
3289	{
3290	if (pVCpu->hm.s.svm.fSyncVTpr)
3291	{
3292	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3293	if ( pVM->hm.s.fTPRPatchingActive
3294	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3295	{
3296	int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3297	AssertRC(rc);
3298	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3299	}
3300	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3301	{
3302	int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3303	AssertRC(rc);
3304	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3305	}
3306	}
3307	}
3308	}
3309
3310
3311	/**
3312	* Runs the guest code using AMD-V.
3313	*
3314	* @returns VBox status code.
3315	* @param pVM The cross context VM structure.
3316	* @param pVCpu The cross context virtual CPU structure.
3317	* @param pCtx Pointer to the guest-CPU context.
3318	*/
3319	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3320	{
3321	SVMTRANSIENT SvmTransient;
3322	SvmTransient.fUpdateTscOffsetting = true;
3323	uint32_t cLoops = 0;
3324	int rc = VERR_INTERNAL_ERROR_5;
3325
3326	for (;; cLoops++)
3327	{
3328	Assert(!HMR0SuspendPending());
3329	HMSVM_ASSERT_CPU_SAFE();
3330
3331	/* Preparatory work for running guest code, this may force us to return
3332	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3333	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3334	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3335	if (rc != VINF_SUCCESS)
3336	break;
3337
3338	/*
3339	* No longjmps to ring-3 from this point on!!!
3340	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3341	* This also disables flushing of the R0-logger instance (if any).
3342	*/
3343	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3344	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3345
3346	/* Restore any residual host-state and save any bits shared between host
3347	and guest into the guest-CPU state. Re-enables interrupts! */
3348	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3349
3350	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3351	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3352	{
3353	if (rc == VINF_SUCCESS)
3354	rc = VERR_SVM_INVALID_GUEST_STATE;
3355	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3356	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3357	break;
3358	}
3359
3360	/* Handle the #VMEXIT. */
3361	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3362	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3363	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3364	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3365	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3366	if (rc != VINF_SUCCESS)
3367	break;
3368	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3369	{
3370	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3371	rc = VINF_EM_RAW_INTERRUPT;
3372	break;
3373	}
3374	}
3375
3376	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3377	return rc;
3378	}
3379
3380
3381	/**
3382	* Runs the guest code using AMD-V in single step mode.
3383	*
3384	* @returns VBox status code.
3385	* @param pVM The cross context VM structure.
3386	* @param pVCpu The cross context virtual CPU structure.
3387	* @param pCtx Pointer to the guest-CPU context.
3388	*/
3389	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3390	{
3391	SVMTRANSIENT SvmTransient;
3392	SvmTransient.fUpdateTscOffsetting = true;
3393	uint32_t cLoops = 0;
3394	int rc = VERR_INTERNAL_ERROR_5;
3395	uint16_t uCsStart = pCtx->cs.Sel;
3396	uint64_t uRipStart = pCtx->rip;
3397
3398	for (;; cLoops++)
3399	{
3400	Assert(!HMR0SuspendPending());
3401	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
3402	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
3403	(unsigned)RTMpCpuId(), cLoops));
3404
3405	/* Preparatory work for running guest code, this may force us to return
3406	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3407	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3408	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3409	if (rc != VINF_SUCCESS)
3410	break;
3411
3412	/*
3413	* No longjmps to ring-3 from this point on!!!
3414	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3415	* This also disables flushing of the R0-logger instance (if any).
3416	*/
3417	VMMRZCallRing3Disable(pVCpu);
3418	VMMRZCallRing3RemoveNotification(pVCpu);
3419	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3420
3421	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3422
3423	/*
3424	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3425	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3426	*/
3427	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3428	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3429	\|\| SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3430	{
3431	if (rc == VINF_SUCCESS)
3432	rc = VERR_SVM_INVALID_GUEST_STATE;
3433	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3434	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3435	return rc;
3436	}
3437
3438	/* Handle the #VMEXIT. */
3439	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3440	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3441	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3442	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3443	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3444	if (rc != VINF_SUCCESS)
3445	break;
3446	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3447	{
3448	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3449	rc = VINF_EM_RAW_INTERRUPT;
3450	break;
3451	}
3452
3453	/*
3454	* Did the RIP change, if so, consider it a single step.
3455	* Otherwise, make sure one of the TFs gets set.
3456	*/
3457	if ( pCtx->rip != uRipStart
3458	\|\| pCtx->cs.Sel != uCsStart)
3459	{
3460	rc = VINF_EM_DBG_STEPPED;
3461	break;
3462	}
3463	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3464	}
3465
3466	/*
3467	* Clear the X86_EFL_TF if necessary.
3468	*/
3469	if (pVCpu->hm.s.fClearTrapFlag)
3470	{
3471	pVCpu->hm.s.fClearTrapFlag = false;
3472	pCtx->eflags.Bits.u1TF = 0;
3473	}
3474
3475	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3476	return rc;
3477	}
3478
3479
3480	/**
3481	* Runs the guest code using AMD-V.
3482	*
3483	* @returns Strict VBox status code.
3484	* @param pVM The cross context VM structure.
3485	* @param pVCpu The cross context virtual CPU structure.
3486	* @param pCtx Pointer to the guest-CPU context.
3487	*/
3488	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3489	{
3490	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3491	HMSVM_ASSERT_PREEMPT_SAFE();
3492	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3493
3494	int rc;
3495	if (!pVCpu->hm.s.fSingleInstruction)
3496	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx);
3497	else
3498	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx);
3499
3500	if (rc == VERR_EM_INTERPRETER)
3501	rc = VINF_EM_RAW_EMULATE_INSTR;
3502	else if (rc == VINF_EM_RESET)
3503	rc = VINF_EM_TRIPLE_FAULT;
3504
3505	/* Prepare to return to ring-3. This will remove longjmp notifications. */
3506	hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3507	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3508	return rc;
3509	}
3510
3511
3512	/**
3513	* Handles a \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3514	*
3515	* @returns VBox status code (informational status codes included).
3516	* @param pVCpu The cross context virtual CPU structure.
3517	* @param pCtx Pointer to the guest-CPU context.
3518	* @param pSvmTransient Pointer to the SVM transient structure.
3519	*/
3520	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3521	{
3522	Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3523	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3524
3525	/*
3526	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
3527	* normal workloads (for some definition of "normal").
3528	*/
3529	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3530	switch (pSvmTransient->u64ExitCode)
3531	{
3532	case SVM_EXIT_NPF:
3533	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3534
3535	case SVM_EXIT_IOIO:
3536	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3537
3538	case SVM_EXIT_RDTSC:
3539	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3540
3541	case SVM_EXIT_RDTSCP:
3542	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3543
3544	case SVM_EXIT_CPUID:
3545	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3546
3547	case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3548	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3549
3550	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3551	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3552
3553	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3554	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
3555
3556	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3557	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3558
3559	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3560	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3561
3562	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3563	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
3564
3565	case SVM_EXIT_MONITOR:
3566	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3567
3568	case SVM_EXIT_MWAIT:
3569	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3570
3571	case SVM_EXIT_HLT:
3572	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3573
3574	case SVM_EXIT_READ_CR0:
3575	case SVM_EXIT_READ_CR3:
3576	case SVM_EXIT_READ_CR4:
3577	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3578
3579	case SVM_EXIT_WRITE_CR0:
3580	case SVM_EXIT_WRITE_CR3:
3581	case SVM_EXIT_WRITE_CR4:
3582	case SVM_EXIT_WRITE_CR8:
3583	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3584
3585	case SVM_EXIT_PAUSE:
3586	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
3587
3588	case SVM_EXIT_VMMCALL:
3589	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3590
3591	case SVM_EXIT_VINTR:
3592	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3593
3594	case SVM_EXIT_INTR:
3595	case SVM_EXIT_FERR_FREEZE:
3596	case SVM_EXIT_NMI:
3597	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3598
3599	case SVM_EXIT_MSR:
3600	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3601
3602	case SVM_EXIT_INVLPG:
3603	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3604
3605	case SVM_EXIT_WBINVD:
3606	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3607
3608	case SVM_EXIT_INVD:
3609	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3610
3611	case SVM_EXIT_RDPMC:
3612	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3613
3614	default:
3615	{
3616	switch (pSvmTransient->u64ExitCode)
3617	{
3618	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3619	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3620	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3621	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3622	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3623
3624	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3625	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3626	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3627	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3628	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3629
3630	case SVM_EXIT_XSETBV:
3631	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
3632
3633	case SVM_EXIT_TASK_SWITCH:
3634	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3635
3636	case SVM_EXIT_IRET:
3637	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
3638
3639	case SVM_EXIT_SHUTDOWN:
3640	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3641
3642	case SVM_EXIT_SMI:
3643	case SVM_EXIT_INIT:
3644	{
3645	/*
3646	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3647	* we want to know about it so log the exit code and bail.
3648	*/
3649	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3650	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3651	return VERR_SVM_UNEXPECTED_EXIT;
3652	}
3653
3654	case SVM_EXIT_INVLPGA:
3655	case SVM_EXIT_RSM:
3656	case SVM_EXIT_VMRUN:
3657	case SVM_EXIT_VMLOAD:
3658	case SVM_EXIT_VMSAVE:
3659	case SVM_EXIT_STGI:
3660	case SVM_EXIT_CLGI:
3661	case SVM_EXIT_SKINIT:
3662	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3663
3664	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3665	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3666	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3667	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3668	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3669	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3670	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3671	/* case SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
3672	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3673	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3674	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3675	case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3676	case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3677	case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3678	case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3679	/* SVM_EXIT_EXCEPTION_E: / / X86_XCPT_PF - Handled above. */
3680	/* SVM_EXIT_EXCEPTION_10: / / X86_XCPT_MF - Handled above. */
3681	/* SVM_EXIT_EXCEPTION_11: / / X86_XCPT_AC - Handled above. */
3682	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3683	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3684	case SVM_EXIT_EXCEPTION_F: /* Reserved */
3685	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3686	case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3687	case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3688	case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3689	{
3690	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3691	SVMEVENT Event;
3692	Event.u = 0;
3693	Event.n.u1Valid = 1;
3694	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3695	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3696
3697	switch (Event.n.u8Vector)
3698	{
3699	case X86_XCPT_DE:
3700	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3701	break;
3702
3703	case X86_XCPT_BP:
3704	/** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3705	* next instruction. */
3706	/** @todo Investigate this later. */
3707	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3708	break;
3709
3710	case X86_XCPT_NP:
3711	Event.n.u1ErrorCodeValid = 1;
3712	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3713	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3714	break;
3715
3716	case X86_XCPT_SS:
3717	Event.n.u1ErrorCodeValid = 1;
3718	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3719	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3720	break;
3721
3722	case X86_XCPT_GP:
3723	Event.n.u1ErrorCodeValid = 1;
3724	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3725	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3726	break;
3727
3728	default:
3729	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3730	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3731	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3732	}
3733
3734	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3735	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3736	return VINF_SUCCESS;
3737	}
3738	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3739
3740	default:
3741	{
3742	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3743	pVCpu->hm.s.u32HMError = u32ExitCode;
3744	return VERR_SVM_UNKNOWN_EXIT;
3745	}
3746	}
3747	}
3748	}
3749	/* not reached */
3750	}
3751
3752
3753	#ifdef DEBUG
3754	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3755	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3756	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3757
3758	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3759	do \
3760	{ \
3761	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3762	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3763	} while (0)
3764
3765	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3766	do { \
3767	AssertPtr(pVCpu); \
3768	AssertPtr(pCtx); \
3769	AssertPtr(pSvmTransient); \
3770	Assert(ASMIntAreEnabled()); \
3771	HMSVM_ASSERT_PREEMPT_SAFE(); \
3772	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3773	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3774	HMSVM_ASSERT_PREEMPT_SAFE(); \
3775	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3776	HMSVM_ASSERT_PREEMPT_CPUID(); \
3777	} while (0)
3778	#else /* Release builds */
3779	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
3780	#endif
3781
3782
3783	/**
3784	* Worker for hmR0SvmInterpretInvlpg().
3785	*
3786	* @return VBox status code.
3787	* @param pVCpu The cross context virtual CPU structure.
3788	* @param pCpu Pointer to the disassembler state.
3789	* @param pCtx The guest CPU context.
3790	*/
3791	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
3792	{
3793	DISQPVPARAMVAL Param1;
3794	RTGCPTR GCPtrPage;
3795
3796	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3797	if (RT_FAILURE(rc))
3798	return VERR_EM_INTERPRETER;
3799
3800	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3801	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3802	{
3803	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3804	return VERR_EM_INTERPRETER;
3805
3806	GCPtrPage = Param1.val.val64;
3807	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
3808	rc = VBOXSTRICTRC_VAL(rc2);
3809	}
3810	else
3811	{
3812	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3813	rc = VERR_EM_INTERPRETER;
3814	}
3815
3816	return rc;
3817	}
3818
3819
3820	/**
3821	* Interprets INVLPG.
3822	*
3823	* @returns VBox status code.
3824	* @retval VINF_* Scheduling instructions.
3825	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3826	* @retval VERR_* Fatal errors.
3827	*
3828	* @param pVM The cross context VM structure.
3829	* @param pVCpu The cross context virtual CPU structure.
3830	* @param pCtx The guest CPU context.
3831	*
3832	* @remarks Updates the RIP if the instruction was executed successfully.
3833	*/
3834	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3835	{
3836	/* Only allow 32 & 64 bit code. */
3837	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3838	{
3839	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3840	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3841	if ( RT_SUCCESS(rc)
3842	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3843	{
3844	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
3845	if (RT_SUCCESS(rc))
3846	pCtx->rip += pDis->cbInstr;
3847	return rc;
3848	}
3849	else
3850	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3851	}
3852	return VERR_EM_INTERPRETER;
3853	}
3854
3855
3856	/**
3857	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3858	*
3859	* @param pVCpu The cross context virtual CPU structure.
3860	*/
3861	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3862	{
3863	SVMEVENT Event;
3864	Event.u = 0;
3865	Event.n.u1Valid = 1;
3866	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3867	Event.n.u8Vector = X86_XCPT_UD;
3868	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3869	}
3870
3871
3872	/**
3873	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3874	*
3875	* @param pVCpu The cross context virtual CPU structure.
3876	*/
3877	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3878	{
3879	SVMEVENT Event;
3880	Event.u = 0;
3881	Event.n.u1Valid = 1;
3882	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3883	Event.n.u8Vector = X86_XCPT_DB;
3884	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3885	}
3886
3887
3888	/**
3889	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3890	*
3891	* @param pVCpu The cross context virtual CPU structure.
3892	* @param pCtx Pointer to the guest-CPU context.
3893	* @param u32ErrCode The error-code for the page-fault.
3894	* @param uFaultAddress The page fault address (CR2).
3895	*
3896	* @remarks This updates the guest CR2 with @a uFaultAddress!
3897	*/
3898	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3899	{
3900	SVMEVENT Event;
3901	Event.u = 0;
3902	Event.n.u1Valid = 1;
3903	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3904	Event.n.u8Vector = X86_XCPT_PF;
3905	Event.n.u1ErrorCodeValid = 1;
3906	Event.n.u32ErrorCode = u32ErrCode;
3907
3908	/* Update CR2 of the guest. */
3909	if (pCtx->cr2 != uFaultAddress)
3910	{
3911	pCtx->cr2 = uFaultAddress;
3912	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3913	}
3914
3915	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3916	}
3917
3918
3919	/**
3920	* Sets a device-not-available (\#NM) exception as pending-for-injection into
3921	* the VM.
3922	*
3923	* @param pVCpu The cross context virtual CPU structure.
3924	*/
3925	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3926	{
3927	SVMEVENT Event;
3928	Event.u = 0;
3929	Event.n.u1Valid = 1;
3930	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3931	Event.n.u8Vector = X86_XCPT_NM;
3932	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3933	}
3934
3935
3936	/**
3937	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3938	*
3939	* @param pVCpu The cross context virtual CPU structure.
3940	*/
3941	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3942	{
3943	SVMEVENT Event;
3944	Event.u = 0;
3945	Event.n.u1Valid = 1;
3946	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3947	Event.n.u8Vector = X86_XCPT_MF;
3948	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3949	}
3950
3951
3952	/**
3953	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3954	*
3955	* @param pVCpu The cross context virtual CPU structure.
3956	*/
3957	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3958	{
3959	SVMEVENT Event;
3960	Event.u = 0;
3961	Event.n.u1Valid = 1;
3962	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3963	Event.n.u8Vector = X86_XCPT_DF;
3964	Event.n.u1ErrorCodeValid = 1;
3965	Event.n.u32ErrorCode = 0;
3966	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3967	}
3968
3969
3970	/**
3971	* Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3972	* guests. This simply looks up the patch record at EIP and does the required.
3973	*
3974	* This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3975	* like how we want it to be (e.g. not followed by shr 4 as is usually done for
3976	* TPR). See hmR3ReplaceTprInstr() for the details.
3977	*
3978	* @returns VBox status code.
3979	* @retval VINF_SUCCESS if the access was handled successfully.
3980	* @retval VERR_NOT_FOUND if no patch record for this RIP could be found.
3981	* @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
3982	*
3983	* @param pVM The cross context VM structure.
3984	* @param pVCpu The cross context virtual CPU structure.
3985	* @param pCtx Pointer to the guest-CPU context.
3986	*/
3987	static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3988	{
3989	Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3990
3991	/*
3992	* We do this in a loop as we increment the RIP after a successful emulation
3993	* and the new RIP may be a patched instruction which needs emulation as well.
3994	*/
3995	bool fPatchFound = false;
3996	for (;;)
3997	{
3998	bool fPending;
3999	uint8_t u8Tpr;
4000
4001	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4002	if (!pPatch)
4003	break;
4004
4005	fPatchFound = true;
4006	switch (pPatch->enmType)
4007	{
4008	case HMTPRINSTR_READ:
4009	{
4010	int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
4011	AssertRC(rc);
4012
4013	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
4014	AssertRC(rc);
4015	pCtx->rip += pPatch->cbOp;
4016	break;
4017	}
4018
4019	case HMTPRINSTR_WRITE_REG:
4020	case HMTPRINSTR_WRITE_IMM:
4021	{
4022	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
4023	{
4024	uint32_t u32Val;
4025	int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
4026	AssertRC(rc);
4027	u8Tpr = u32Val;
4028	}
4029	else
4030	u8Tpr = (uint8_t)pPatch->uSrcOperand;
4031
4032	int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
4033	AssertRC(rc2);
4034	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4035
4036	pCtx->rip += pPatch->cbOp;
4037	break;
4038	}
4039
4040	default:
4041	AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
4042	pVCpu->hm.s.u32HMError = pPatch->enmType;
4043	return VERR_SVM_UNEXPECTED_PATCH_TYPE;
4044	}
4045	}
4046
4047	if (fPatchFound)
4048	return VINF_SUCCESS;
4049	return VERR_NOT_FOUND;
4050	}
4051
4052
4053	/**
4054	* Determines if an exception is a contributory exception.
4055	*
4056	* Contributory exceptions are ones which can cause double-faults unless the
4057	* original exception was a benign exception. Page-fault is intentionally not
4058	* included here as it's a conditional contributory exception.
4059	*
4060	* @returns true if the exception is contributory, false otherwise.
4061	* @param uVector The exception vector.
4062	*/
4063	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
4064	{
4065	switch (uVector)
4066	{
4067	case X86_XCPT_GP:
4068	case X86_XCPT_SS:
4069	case X86_XCPT_NP:
4070	case X86_XCPT_TS:
4071	case X86_XCPT_DE:
4072	return true;
4073	default:
4074	break;
4075	}
4076	return false;
4077	}
4078
4079
4080	/**
4081	* Handle a condition that occurred while delivering an event through the guest
4082	* IDT.
4083	*
4084	* @returns VBox status code (informational error codes included).
4085	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
4086	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
4087	* continue execution of the guest which will delivery the \#DF.
4088	* @retval VINF_EM_RESET if we detected a triple-fault condition.
4089	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
4090	*
4091	* @param pVCpu The cross context virtual CPU structure.
4092	* @param pCtx Pointer to the guest-CPU context.
4093	* @param pSvmTransient Pointer to the SVM transient structure.
4094	*
4095	* @remarks No-long-jump zone!!!
4096	*/
4097	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4098	{
4099	int rc = VINF_SUCCESS;
4100	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4101
4102	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
4103	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
4104	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
4105
4106	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
4107	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
4108	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
4109	{
4110	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4111
4112	typedef enum
4113	{
4114	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4115	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4116	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4117	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
4118	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
4119	} SVMREFLECTXCPT;
4120
4121	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
4122	bool fReflectingNmi = false;
4123	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
4124	{
4125	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4126	{
4127	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4128
4129	#ifdef VBOX_STRICT
4130	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
4131	&& uExitVector == X86_XCPT_PF)
4132	{
4133	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
4134	}
4135	#endif
4136
4137	if ( uIdtVector == X86_XCPT_BP
4138	\|\| uIdtVector == X86_XCPT_OF)
4139	{
4140	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
4141	}
4142	else if ( uExitVector == X86_XCPT_PF
4143	&& uIdtVector == X86_XCPT_PF)
4144	{
4145	pSvmTransient->fVectoringDoublePF = true;
4146	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
4147	}
4148	else if ( uExitVector == X86_XCPT_AC
4149	&& uIdtVector == X86_XCPT_AC)
4150	{
4151	enmReflect = SVMREFLECTXCPT_HANG;
4152	Log4(("IDT: Nested #AC - Bad guest\n"));
4153	}
4154	else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
4155	&& hmR0SvmIsContributoryXcpt(uExitVector)
4156	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
4157	\|\| uIdtVector == X86_XCPT_PF))
4158	{
4159	enmReflect = SVMREFLECTXCPT_DF;
4160	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
4161	uIdtVector, uExitVector));
4162	}
4163	else if (uIdtVector == X86_XCPT_DF)
4164	{
4165	enmReflect = SVMREFLECTXCPT_TF;
4166	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
4167	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
4168	}
4169	else
4170	enmReflect = SVMREFLECTXCPT_XCPT;
4171	}
4172	else
4173	{
4174	/*
4175	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
4176	* exception to the guest after handling the #VMEXIT.
4177	*/
4178	enmReflect = SVMREFLECTXCPT_XCPT;
4179	}
4180	}
4181	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
4182	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4183	{
4184	enmReflect = SVMREFLECTXCPT_XCPT;
4185	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
4186
4187	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4188	{
4189	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4190	if (uExitVector == X86_XCPT_PF)
4191	{
4192	pSvmTransient->fVectoringPF = true;
4193	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
4194	}
4195	}
4196	}
4197	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
4198
4199	switch (enmReflect)
4200	{
4201	case SVMREFLECTXCPT_XCPT:
4202	{
4203	/* If we are re-injecting the NMI, clear NMI blocking. */
4204	if (fReflectingNmi)
4205	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4206
4207	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4208	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4209	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
4210
4211	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
4212	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
4213	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4214	break;
4215	}
4216
4217	case SVMREFLECTXCPT_DF:
4218	{
4219	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4220	hmR0SvmSetPendingXcptDF(pVCpu);
4221	rc = VINF_HM_DOUBLE_FAULT;
4222	break;
4223	}
4224
4225	case SVMREFLECTXCPT_TF:
4226	{
4227	rc = VINF_EM_RESET;
4228	break;
4229	}
4230
4231	case SVMREFLECTXCPT_HANG:
4232	{
4233	rc = VERR_EM_GUEST_CPU_HANG;
4234	break;
4235	}
4236
4237	default:
4238	Assert(rc == VINF_SUCCESS);
4239	break;
4240	}
4241	}
4242	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
4243	NOREF(pCtx);
4244	return rc;
4245	}
4246
4247	/**
4248	* Updates interrupt shadow for the current RIP.
4249	*/
4250	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
4251	do { \
4252	/* Update interrupt shadow. */ \
4253	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
4254	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
4255	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
4256	} while (0)
4257
4258	/**
4259	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
4260	* supported, otherwise advances the RIP by the number of bytes specified in
4261	* @a cb.
4262	*
4263	* @param pVCpu The cross context virtual CPU structure.
4264	* @param pCtx Pointer to the guest-CPU context.
4265	* @param cb RIP increment value in bytes.
4266	*
4267	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
4268	* when NRIP_SAVE is supported by the CPU, otherwise use
4269	* hmR0SvmAdvanceRipDumb!
4270	*/
4271	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4272	{
4273	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4274	{
4275	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4276	Assert(pVmcb->ctrl.u64NextRIP);
4277	Assert(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb);
4278	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4279	}
4280	else
4281	pCtx->rip += cb;
4282
4283	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4284	}
4285
4286
4287	/**
4288	* Advances the guest RIP by the number of bytes specified in @a cb. This does
4289	* not make use of any hardware features to determine the instruction length.
4290	*
4291	* @param pVCpu The cross context virtual CPU structure.
4292	* @param pCtx Pointer to the guest-CPU context.
4293	* @param cb RIP increment value in bytes.
4294	*/
4295	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4296	{
4297	pCtx->rip += cb;
4298	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4299	}
4300	#undef HMSVM_UPDATE_INTR_SHADOW
4301
4302
4303	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4304	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
4305	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4306
4307	/** @name \#VMEXIT handlers.
4308	* @{
4309	*/
4310
4311	/**
4312	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
4313	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
4314	*/
4315	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4316	{
4317	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4318
4319	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
4320	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
4321	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
4322	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
4323
4324	/*
4325	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
4326	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
4327	* interrupt it is until the host actually take the interrupt.
4328	*
4329	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
4330	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
4331	*/
4332	return VINF_EM_RAW_INTERRUPT;
4333	}
4334
4335
4336	/**
4337	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
4338	*/
4339	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4340	{
4341	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4342
4343	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4344	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
4345	int rc = VINF_SUCCESS;
4346	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4347	return rc;
4348	}
4349
4350
4351	/**
4352	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
4353	*/
4354	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4355	{
4356	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4357
4358	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4359	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
4360	int rc = VINF_SUCCESS;
4361	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4362	return rc;
4363	}
4364
4365
4366	/**
4367	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
4368	*/
4369	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4370	{
4371	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4372	PVM pVM = pVCpu->CTX_SUFF(pVM);
4373	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4374	if (RT_LIKELY(rc == VINF_SUCCESS))
4375	{
4376	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4377	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4378	}
4379	else
4380	{
4381	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4382	rc = VERR_EM_INTERPRETER;
4383	}
4384	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
4385	return rc;
4386	}
4387
4388
4389	/**
4390	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
4391	*/
4392	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4393	{
4394	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4395	PVM pVM = pVCpu->CTX_SUFF(pVM);
4396	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4397	if (RT_LIKELY(rc == VINF_SUCCESS))
4398	{
4399	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4400	pSvmTransient->fUpdateTscOffsetting = true;
4401
4402	/* Single step check. */
4403	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4404	}
4405	else
4406	{
4407	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
4408	rc = VERR_EM_INTERPRETER;
4409	}
4410	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
4411	return rc;
4412	}
4413
4414
4415	/**
4416	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
4417	*/
4418	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4419	{
4420	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4421	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4422	if (RT_LIKELY(rc == VINF_SUCCESS))
4423	{
4424	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4425	pSvmTransient->fUpdateTscOffsetting = true;
4426	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4427	}
4428	else
4429	{
4430	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
4431	rc = VERR_EM_INTERPRETER;
4432	}
4433	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
4434	return rc;
4435	}
4436
4437
4438	/**
4439	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
4440	*/
4441	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4442	{
4443	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4444	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4445	if (RT_LIKELY(rc == VINF_SUCCESS))
4446	{
4447	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4448	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4449	}
4450	else
4451	{
4452	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4453	rc = VERR_EM_INTERPRETER;
4454	}
4455	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4456	return rc;
4457	}
4458
4459
4460	/**
4461	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
4462	*/
4463	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4464	{
4465	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4466	PVM pVM = pVCpu->CTX_SUFF(pVM);
4467	Assert(!pVM->hm.s.fNestedPaging);
4468
4469	/** @todo Decode Assist. */
4470	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
4471	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4472	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
4473	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4474	return rc;
4475	}
4476
4477
4478	/**
4479	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
4480	*/
4481	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4482	{
4483	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4484
4485	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
4486	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4487	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4488	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4489	if (rc != VINF_SUCCESS)
4490	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
4491	return rc;
4492	}
4493
4494
4495	/**
4496	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
4497	*/
4498	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4499	{
4500	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4501	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4502	if (RT_LIKELY(rc == VINF_SUCCESS))
4503	{
4504	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4505	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4506	}
4507	else
4508	{
4509	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4510	rc = VERR_EM_INTERPRETER;
4511	}
4512	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4513	return rc;
4514	}
4515
4516
4517	/**
4518	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
4519	*/
4520	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4521	{
4522	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4523	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4524	int rc = VBOXSTRICTRC_VAL(rc2);
4525	if ( rc == VINF_EM_HALT
4526	\|\| rc == VINF_SUCCESS)
4527	{
4528	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4529
4530	if ( rc == VINF_EM_HALT
4531	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
4532	{
4533	rc = VINF_SUCCESS;
4534	}
4535	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4536	}
4537	else
4538	{
4539	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4540	rc = VERR_EM_INTERPRETER;
4541	}
4542	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
4543	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4544	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4545	return rc;
4546	}
4547
4548
4549	/**
4550	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
4551	* \#VMEXIT.
4552	*/
4553	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4554	{
4555	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4556	return VINF_EM_RESET;
4557	}
4558
4559
4560	/**
4561	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
4562	*/
4563	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4564	{
4565	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4566
4567	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4568
4569	/** @todo Decode Assist. */
4570	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4571	int rc = VBOXSTRICTRC_VAL(rc2);
4572	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4573	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4574	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4575	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4576	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4577	return rc;
4578	}
4579
4580
4581	/**
4582	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
4583	*/
4584	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4585	{
4586	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4587
4588	/** @todo Decode Assist. */
4589	VBOXSTRICTRC rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
4590	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
4591	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
4592	rcStrict = VERR_EM_INTERPRETER;
4593	if (rcStrict == VINF_SUCCESS)
4594	{
4595	/* RIP has been updated by EMInterpretInstruction(). */
4596	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4597	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4598	{
4599	case 0: /* CR0. */
4600	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4601	break;
4602
4603	case 3: /* CR3. */
4604	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4605	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4606	break;
4607
4608	case 4: /* CR4. */
4609	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4610	break;
4611
4612	case 8: /* CR8 (TPR). */
4613	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4614	break;
4615
4616	default:
4617	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
4618	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4619	break;
4620	}
4621	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4622	}
4623	else
4624	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
4625	return VBOXSTRICTRC_TODO(rcStrict);
4626	}
4627
4628
4629	/**
4630	* \#VMEXIT handler for instructions that result in a \#UD exception delivered
4631	* to the guest.
4632	*/
4633	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4634	{
4635	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4636	hmR0SvmSetPendingXcptUD(pVCpu);
4637	return VINF_SUCCESS;
4638	}
4639
4640
4641	/**
4642	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
4643	* \#VMEXIT.
4644	*/
4645	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4646	{
4647	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4648	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4649	PVM pVM = pVCpu->CTX_SUFF(pVM);
4650
4651	int rc;
4652	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4653	{
4654	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4655
4656	/* Handle TPR patching; intercepted LSTAR write. */
4657	if ( pVM->hm.s.fTPRPatchingActive
4658	&& pCtx->ecx == MSR_K8_LSTAR)
4659	{
4660	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4661	{
4662	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4663	int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4664	AssertRC(rc2);
4665	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4666	}
4667	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4668	rc = VINF_SUCCESS;
4669	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4670	return rc;
4671	}
4672
4673	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4674	{
4675	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4676	if (RT_LIKELY(rc == VINF_SUCCESS))
4677	{
4678	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4679	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4680	}
4681	else
4682	AssertMsg( rc == VERR_EM_INTERPRETER
4683	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4684	}
4685	else
4686	{
4687	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4688	if (RT_LIKELY(rc == VINF_SUCCESS))
4689	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
4690	else
4691	AssertMsg( rc == VERR_EM_INTERPRETER
4692	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4693	}
4694
4695	if (rc == VINF_SUCCESS)
4696	{
4697	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4698	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4699	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4700	{
4701	/*
4702	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4703	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4704	* EMInterpretWrmsr() changes it.
4705	*/
4706	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4707	}
4708	else if (pCtx->ecx == MSR_K6_EFER)
4709	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4710	else if (pCtx->ecx == MSR_IA32_TSC)
4711	pSvmTransient->fUpdateTscOffsetting = true;
4712	}
4713	}
4714	else
4715	{
4716	/* MSR Read access. */
4717	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4718	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4719
4720	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4721	{
4722	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4723	if (RT_LIKELY(rc == VINF_SUCCESS))
4724	{
4725	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4726	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4727	}
4728	else
4729	AssertMsg( rc == VERR_EM_INTERPRETER
4730	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4731	}
4732	else
4733	{
4734	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4735	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4736	{
4737	AssertMsg( rc == VERR_EM_INTERPRETER
4738	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4739	}
4740	/* RIP updated by EMInterpretInstruction(). */
4741	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4742	}
4743	}
4744
4745	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4746	return rc;
4747	}
4748
4749
4750	/**
4751	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
4752	*/
4753	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4754	{
4755	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4756	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4757
4758	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
4759	if (pSvmTransient->fWasGuestDebugStateActive)
4760	{
4761	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
4762	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
4763	return VERR_SVM_UNEXPECTED_EXIT;
4764	}
4765
4766	/*
4767	* Lazy DR0-3 loading.
4768	*/
4769	if (!pSvmTransient->fWasHyperDebugStateActive)
4770	{
4771	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4772	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4773
4774	/* Don't intercept DRx read and writes. */
4775	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4776	pVmcb->ctrl.u16InterceptRdDRx = 0;
4777	pVmcb->ctrl.u16InterceptWrDRx = 0;
4778	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4779
4780	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4781	VMMRZCallRing3Disable(pVCpu);
4782	HM_DISABLE_PREEMPT();
4783
4784	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4785	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4786	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4787
4788	HM_RESTORE_PREEMPT();
4789	VMMRZCallRing3Enable(pVCpu);
4790
4791	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4792	return VINF_SUCCESS;
4793	}
4794
4795	/*
4796	* Interpret the read/writing of DRx.
4797	*/
4798	/** @todo Decode assist. */
4799	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4800	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4801	if (RT_LIKELY(rc == VINF_SUCCESS))
4802	{
4803	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4804	/** @todo CPUM should set this flag! */
4805	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4806	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4807	}
4808	else
4809	Assert(rc == VERR_EM_INTERPRETER);
4810	return VBOXSTRICTRC_TODO(rc);
4811	}
4812
4813
4814	/**
4815	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
4816	*/
4817	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4818	{
4819	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4820	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4821	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4822	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4823	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4824	return rc;
4825	}
4826
4827
4828	/**
4829	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
4830	*/
4831	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4832	{
4833	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4834
4835	/** @todo decode assists... */
4836	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
4837	if (rcStrict == VINF_IEM_RAISED_XCPT)
4838	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4839
4840	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4841	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
4842	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
4843
4844	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4845	return VBOXSTRICTRC_TODO(rcStrict);
4846	}
4847
4848
4849	/**
4850	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
4851	*/
4852	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4853	{
4854	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4855
4856	/* I/O operation lookup arrays. */
4857	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4858	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4859	the result (in AL/AX/EAX). */
4860	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4861
4862	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4863	PVM pVM = pVCpu->CTX_SUFF(pVM);
4864
4865	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4866	SVMIOIOEXIT IoExitInfo;
4867	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4868	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4869	uint32_t cbValue = s_aIOSize[uIOWidth];
4870	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4871
4872	if (RT_UNLIKELY(!cbValue))
4873	{
4874	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4875	return VERR_EM_INTERPRETER;
4876	}
4877
4878	VBOXSTRICTRC rcStrict;
4879	bool fUpdateRipAlready = false;
4880	if (IoExitInfo.n.u1STR)
4881	{
4882	#ifdef VBOX_WITH_2ND_IEM_STEP
4883	/* INS/OUTS - I/O String instruction. */
4884	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4885	* in EXITINFO1? Investigate once this thing is up and running. */
4886	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
4887	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
4888	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
4889	static IEMMODE const s_aenmAddrMode[8] =
4890	{
4891	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
4892	};
4893	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
4894	if (enmAddrMode != (IEMMODE)-1)
4895	{
4896	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
4897	if (cbInstr <= 15 && cbInstr >= 1)
4898	{
4899	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
4900	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4901	{
4902	/* Don't know exactly how to detect whether u3SEG is valid, currently
4903	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
4904	2384 Opterons when only checking NRIP. */
4905	if ( (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4906	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
4907	{
4908	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
4909	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
4910	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
4911	IoExitInfo.n.u3SEG, true /fIoChecked/);
4912	}
4913	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
4914	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
4915	X86_SREG_DS, true /fIoChecked/);
4916	else
4917	rcStrict = IEMExecOne(pVCpu);
4918	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4919	}
4920	else
4921	{
4922	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
4923	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
4924	true /fIoChecked/);
4925	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4926	}
4927	}
4928	else
4929	{
4930	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
4931	rcStrict = IEMExecOne(pVCpu);
4932	}
4933	}
4934	else
4935	{
4936	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
4937	rcStrict = IEMExecOne(pVCpu);
4938	}
4939	fUpdateRipAlready = true;
4940
4941	#else
4942	/* INS/OUTS - I/O String instruction. */
4943	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4944
4945	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4946	* in EXITINFO1? Investigate once this thing is up and running. */
4947
4948	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4949	if (rcStrict == VINF_SUCCESS)
4950	{
4951	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4952	{
4953	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4954	(DISCPUMODE)pDis->uAddrMode, cbValue);
4955	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4956	}
4957	else
4958	{
4959	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4960	(DISCPUMODE)pDis->uAddrMode, cbValue);
4961	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4962	}
4963	}
4964	else
4965	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4966	#endif
4967	}
4968	else
4969	{
4970	/* IN/OUT - I/O instruction. */
4971	Assert(!IoExitInfo.n.u1REP);
4972
4973	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4974	{
4975	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4976	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4977	}
4978	else
4979	{
4980	uint32_t u32Val = 0;
4981	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4982	if (IOM_SUCCESS(rcStrict))
4983	{
4984	/* Save result of I/O IN instr. in AL/AX/EAX. */
4985	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
4986	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
4987	}
4988	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4989	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4990
4991	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4992	}
4993	}
4994
4995	if (IOM_SUCCESS(rcStrict))
4996	{
4997	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4998	if (!fUpdateRipAlready)
4999	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
5000
5001	/*
5002	* If any I/O breakpoints are armed, we need to check if one triggered
5003	* and take appropriate action.
5004	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
5005	*/
5006	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
5007	* execution engines about whether hyper BPs and such are pending. */
5008	uint32_t const uDr7 = pCtx->dr[7];
5009	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
5010	&& X86_DR7_ANY_RW_IO(uDr7)
5011	&& (pCtx->cr4 & X86_CR4_DE))
5012	\|\| DBGFBpIsHwIoArmed(pVM)))
5013	{
5014	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5015	VMMRZCallRing3Disable(pVCpu);
5016	HM_DISABLE_PREEMPT();
5017
5018	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
5019	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
5020
5021	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
5022	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
5023	{
5024	/* Raise #DB. */
5025	pVmcb->guest.u64DR6 = pCtx->dr[6];
5026	pVmcb->guest.u64DR7 = pCtx->dr[7];
5027	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5028	hmR0SvmSetPendingXcptDB(pVCpu);
5029	}
5030	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
5031	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
5032	else if ( rcStrict2 != VINF_SUCCESS
5033	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
5034	rcStrict = rcStrict2;
5035	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
5036
5037	HM_RESTORE_PREEMPT();
5038	VMMRZCallRing3Enable(pVCpu);
5039	}
5040
5041	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5042	}
5043
5044	#ifdef VBOX_STRICT
5045	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
5046	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
5047	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
5048	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
5049	else
5050	{
5051	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
5052	* statuses, that the VMM device and some others may return. See
5053	* IOM_SUCCESS() for guidance. */
5054	AssertMsg( RT_FAILURE(rcStrict)
5055	\|\| rcStrict == VINF_SUCCESS
5056	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
5057	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
5058	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
5059	\|\| rcStrict == VINF_EM_RAW_TO_R3
5060	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
5061	}
5062	#endif
5063	return VBOXSTRICTRC_TODO(rcStrict);
5064	}
5065
5066
5067	/**
5068	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
5069	*/
5070	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5071	{
5072	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5073	PVM pVM = pVCpu->CTX_SUFF(pVM);
5074	Assert(pVM->hm.s.fNestedPaging);
5075
5076	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5077
5078	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
5079	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5080	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5081	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
5082
5083	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
5084
5085	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5086	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
5087	if ( pVM->hm.s.fTprPatchingAllowed
5088	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
5089	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
5090	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
5091	&& !CPUMIsGuestInLongModeEx(pCtx)
5092	&& !CPUMGetGuestCPL(pVCpu)
5093	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5094	{
5095	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
5096	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5097
5098	if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
5099	{
5100	/* Only attempt to patch the instruction once. */
5101	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5102	if (!pPatch)
5103	return VINF_EM_HM_PATCH_TPR_INSTR;
5104	}
5105	}
5106	#endif
5107
5108	/*
5109	* Determine the nested paging mode.
5110	*/
5111	PGMMODE enmNestedPagingMode;
5112	#if HC_ARCH_BITS == 32
5113	if (CPUMIsGuestInLongModeEx(pCtx))
5114	enmNestedPagingMode = PGMMODE_AMD64_NX;
5115	else
5116	#endif
5117	enmNestedPagingMode = PGMGetHostMode(pVM);
5118
5119	/*
5120	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
5121	*/
5122	int rc;
5123	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
5124	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
5125	{
5126	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
5127	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
5128	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5129	return VERR_EM_INTERPRETER;
5130
5131	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
5132	u32ErrCode);
5133	rc = VBOXSTRICTRC_VAL(rc2);
5134
5135	/*
5136	* If we succeed, resume guest execution.
5137	* If we fail in interpreting the instruction because we couldn't get the guest physical address
5138	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
5139	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
5140	* weird case. See @bugref{6043}.
5141	*/
5142	if ( rc == VINF_SUCCESS
5143	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5144	\|\| rc == VERR_PAGE_NOT_PRESENT)
5145	{
5146	/* Successfully handled MMIO operation. */
5147	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5148	rc = VINF_SUCCESS;
5149	}
5150	return rc;
5151	}
5152
5153	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
5154	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
5155	TRPMResetTrap(pVCpu);
5156
5157	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
5158
5159	/*
5160	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
5161	*/
5162	if ( rc == VINF_SUCCESS
5163	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5164	\|\| rc == VERR_PAGE_NOT_PRESENT)
5165	{
5166	/* We've successfully synced our shadow page tables. */
5167	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5168	rc = VINF_SUCCESS;
5169	}
5170
5171	return rc;
5172	}
5173
5174
5175	/**
5176	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
5177	* \#VMEXIT.
5178	*/
5179	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5180	{
5181	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5182
5183	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5184	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
5185	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
5186
5187	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
5188	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
5189	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
5190
5191	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5192	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
5193	return VINF_SUCCESS;
5194	}
5195
5196
5197	/**
5198	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
5199	* \#VMEXIT.
5200	*/
5201	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5202	{
5203	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5204
5205	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5206
5207	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
5208	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5209	#endif
5210
5211	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
5212	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
5213	{
5214	/*
5215	* AMD-V provides us with the exception which caused the TS; we collect
5216	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
5217	*/
5218	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
5219	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5220	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5221	}
5222
5223	/** @todo Emulate task switch someday, currently just going back to ring-3 for
5224	* emulation. */
5225	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5226	return VERR_EM_INTERPRETER;
5227	}
5228
5229
5230	/**
5231	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5232	*/
5233	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5234	{
5235	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5236	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
5237
5238	/* First check if this is a patched VMMCALL for mov TPR */
5239	int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5240	if (rc == VINF_SUCCESS)
5241	{
5242	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5243	return VINF_SUCCESS;
5244	}
5245
5246	if (rc == VERR_NOT_FOUND)
5247	{
5248	if (pVCpu->hm.s.fHypercallsEnabled)
5249	{
5250	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, pCtx);
5251	if (RT_SUCCESS(VBOXSTRICTRC_VAL(rcStrict)))
5252	{
5253	if (rcStrict == VINF_SUCCESS)
5254	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
5255	else
5256	Assert( rcStrict == VINF_GIM_HYPERCALL_CONTINUING
5257	\|\| rcStrict == VINF_GIM_R3_HYPERCALL);
5258
5259	/* If the hypercall changes anything other than guest's general-purpose registers,
5260	we would need to reload the guest changed bits here before VM-entry. */
5261	}
5262	rc = VBOXSTRICTRC_VAL(rcStrict);
5263	}
5264	else
5265	Log4(("hmR0SvmExitVmmCall: Hypercalls not enabled\n"));
5266	}
5267
5268	/* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
5269	if (RT_FAILURE(rc))
5270	{
5271	hmR0SvmSetPendingXcptUD(pVCpu);
5272	rc = VINF_SUCCESS;
5273	}
5274
5275	return rc;
5276	}
5277
5278
5279	/**
5280	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5281	*/
5282	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5283	{
5284	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5285	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
5286	return VINF_EM_RAW_INTERRUPT;
5287	}
5288
5289
5290	/**
5291	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
5292	*/
5293	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5294	{
5295	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5296
5297	/* Clear NMI blocking. */
5298	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5299
5300	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
5301	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5302	hmR0SvmClearIretIntercept(pVmcb);
5303
5304	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5305	return VINF_SUCCESS;
5306	}
5307
5308
5309	/**
5310	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E).
5311	* Conditional \#VMEXIT.
5312	*/
5313	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5314	{
5315	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5316
5317	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5318
5319	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
5320	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5321	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5322	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
5323	PVM pVM = pVCpu->CTX_SUFF(pVM);
5324
5325	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
5326	if (pVM->hm.s.fNestedPaging)
5327	{
5328	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5329	if (!pSvmTransient->fVectoringDoublePF)
5330	{
5331	/* A genuine guest #PF, reflect it to the guest. */
5332	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5333	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
5334	uFaultAddress, u32ErrCode));
5335	}
5336	else
5337	{
5338	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5339	hmR0SvmSetPendingXcptDF(pVCpu);
5340	Log4(("Pending #DF due to vectoring #PF. NP\n"));
5341	}
5342	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5343	return VINF_SUCCESS;
5344	}
5345	#endif
5346
5347	Assert(!pVM->hm.s.fNestedPaging);
5348
5349	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5350	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
5351	if ( pVM->hm.s.fTprPatchingAllowed
5352	&& (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
5353	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
5354	&& !CPUMIsGuestInLongModeEx(pCtx)
5355	&& !CPUMGetGuestCPL(pVCpu)
5356	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5357	{
5358	RTGCPHYS GCPhysApicBase;
5359	GCPhysApicBase = pCtx->msrApicBase;
5360	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5361
5362	/* Check if the page at the fault-address is the APIC base. */
5363	RTGCPHYS GCPhysPage;
5364	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
5365	if ( rc2 == VINF_SUCCESS
5366	&& GCPhysPage == GCPhysApicBase)
5367	{
5368	/* Only attempt to patch the instruction once. */
5369	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5370	if (!pPatch)
5371	return VINF_EM_HM_PATCH_TPR_INSTR;
5372	}
5373	}
5374	#endif
5375
5376	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
5377	pCtx->rip, u32ErrCode, pCtx->cr3));
5378
5379	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
5380	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
5381	if (pSvmTransient->fVectoringPF)
5382	{
5383	Assert(pVCpu->hm.s.Event.fPending);
5384	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5385	}
5386
5387	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
5388	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
5389
5390	Log4(("#PF rc=%Rrc\n", rc));
5391
5392	if (rc == VINF_SUCCESS)
5393	{
5394	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
5395	TRPMResetTrap(pVCpu);
5396	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5397	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
5398	return rc;
5399	}
5400	else if (rc == VINF_EM_RAW_GUEST_TRAP)
5401	{
5402	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5403
5404	if (!pSvmTransient->fVectoringDoublePF)
5405	{
5406	/* It's a guest page fault and needs to be reflected to the guest. */
5407	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
5408	TRPMResetTrap(pVCpu);
5409	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5410	}
5411	else
5412	{
5413	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5414	TRPMResetTrap(pVCpu);
5415	hmR0SvmSetPendingXcptDF(pVCpu);
5416	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
5417	}
5418
5419	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5420	return VINF_SUCCESS;
5421	}
5422
5423	TRPMResetTrap(pVCpu);
5424	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
5425	return rc;
5426	}
5427
5428
5429	/**
5430	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
5431	* Conditional \#VMEXIT.
5432	*/
5433	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5434	{
5435	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5436
5437	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5438	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5439	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5440
5441	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5442	VMMRZCallRing3Disable(pVCpu);
5443	HM_DISABLE_PREEMPT();
5444
5445	int rc;
5446	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
5447	if (pSvmTransient->fWasGuestFPUStateActive)
5448	{
5449	rc = VINF_EM_RAW_GUEST_TRAP;
5450	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
5451	}
5452	else
5453	{
5454	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5455	Assert(!pSvmTransient->fWasGuestFPUStateActive);
5456	#endif
5457	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
5458	Assert( rc == VINF_EM_RAW_GUEST_TRAP
5459	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
5460	}
5461
5462	HM_RESTORE_PREEMPT();
5463	VMMRZCallRing3Enable(pVCpu);
5464
5465	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
5466	{
5467	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
5468	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
5469	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
5470	pVCpu->hm.s.fPreloadGuestFpu = true;
5471	}
5472	else
5473	{
5474	/* Forward #NM to the guest. */
5475	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
5476	hmR0SvmSetPendingXcptNM(pVCpu);
5477	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
5478	}
5479	return VINF_SUCCESS;
5480	}
5481
5482
5483	/**
5484	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
5485	* Conditional \#VMEXIT.
5486	*/
5487	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5488	{
5489	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5490
5491	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5492	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5493	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5494
5495	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
5496	if (pVCpu->hm.s.fGIMTrapXcptUD)
5497	{
5498	uint8_t cbInstr = 0;
5499	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
5500	if (rcStrict == VINF_SUCCESS)
5501	{
5502	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
5503	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
5504	rc = VINF_SUCCESS;
5505	}
5506	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
5507	rc = VINF_SUCCESS;
5508	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
5509	rc = VINF_GIM_R3_HYPERCALL;
5510	else
5511	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
5512	}
5513
5514	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
5515	if (RT_FAILURE(rc))
5516	{
5517	hmR0SvmSetPendingXcptUD(pVCpu);
5518	rc = VINF_SUCCESS;
5519	}
5520
5521	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
5522	return rc;
5523	}
5524
5525
5526	/**
5527	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
5528	* Conditional \#VMEXIT.
5529	*/
5530	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5531	{
5532	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5533
5534	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5535	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5536	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5537
5538	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
5539
5540	if (!(pCtx->cr0 & X86_CR0_NE))
5541	{
5542	PVM pVM = pVCpu->CTX_SUFF(pVM);
5543	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5544	unsigned cbOp;
5545	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
5546	if (RT_SUCCESS(rc))
5547	{
5548	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
5549	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
5550	if (RT_SUCCESS(rc))
5551	pCtx->rip += cbOp;
5552	}
5553	else
5554	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5555	return rc;
5556	}
5557
5558	hmR0SvmSetPendingXcptMF(pVCpu);
5559	return VINF_SUCCESS;
5560	}
5561
5562
5563	/**
5564	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
5565	* \#VMEXIT.
5566	*/
5567	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5568	{
5569	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5570
5571	/* If this #DB is the result of delivering an event, go back to the interpreter. */
5572	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5573	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5574	{
5575	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
5576	return VERR_EM_INTERPRETER;
5577	}
5578
5579	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
5580
5581	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
5582	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
5583	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5584	PVM pVM = pVCpu->CTX_SUFF(pVM);
5585	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
5586	if (rc == VINF_EM_RAW_GUEST_TRAP)
5587	{
5588	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
5589	if (CPUMIsHyperDebugStateActive(pVCpu))
5590	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
5591
5592	/* Reflect the exception back to the guest. */
5593	hmR0SvmSetPendingXcptDB(pVCpu);
5594	rc = VINF_SUCCESS;
5595	}
5596
5597	/*
5598	* Update DR6.
5599	*/
5600	if (CPUMIsHyperDebugStateActive(pVCpu))
5601	{
5602	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
5603	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
5604	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5605	}
5606	else
5607	{
5608	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
5609	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
5610	}
5611
5612	return rc;
5613	}
5614
5615
5616	/**
5617	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_11).
5618	* Conditional \#VMEXIT.
5619	*/
5620	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5621	{
5622	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5623
5624	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5625
5626	SVMEVENT Event;
5627	Event.u = 0;
5628	Event.n.u1Valid = 1;
5629	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5630	Event.n.u8Vector = X86_XCPT_AC;
5631	Event.n.u1ErrorCodeValid = 1;
5632	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5633	return VINF_SUCCESS;
5634	}
5635
5636	/** @} */
5637

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 64468

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