HMSVMR0.cpp@ 66987

Last change on this file since 66987 was 66984, checked in by vboxsync, 8 years ago
VMM/HMSVMR0: Add a release assertion to check if CR2 isn't getting updated properly.
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1	/* $Id: HMSVMR0.cpp 66984 2017-05-19 14:10:10Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/thread.h>
25
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#include <VBox/vmm/apic.h>
33	#include "HMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include "HMSVMR0.h"
36	#include "dtrace/VBoxVMM.h"
37
38	#define HMSVM_USE_IEM_EVENT_REFLECTION
39	#ifdef DEBUG_ramshankar
40	# define HMSVM_SYNC_FULL_GUEST_STATE
41	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
42	# define HMSVM_ALWAYS_TRAP_PF
43	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
44	#endif
45
46
47	/*********************************************************************************************************************************
48	* Defined Constants And Macros *
49	*********************************************************************************************************************************/
50	#ifdef VBOX_WITH_STATISTICS
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
52	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
53	if ((u64ExitCode) == SVM_EXIT_NPF) \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
55	else \
56	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
57	} while (0)
58	#else
59	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
60	#endif
61
62	/** If we decide to use a function table approach this can be useful to
63	* switch to a "static DECLCALLBACK(int)". */
64	#define HMSVM_EXIT_DECL static int
65
66	/** Macro for checking and returning from the using function for
67	* \#VMEXIT intercepts that maybe caused during delivering of another
68	* event in the guest. */
69	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
70	do \
71	{ \
72	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
73	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
74	else if (rc == VINF_HM_DOUBLE_FAULT) \
75	return VINF_SUCCESS; \
76	else \
77	return rc; \
78	} while (0)
79
80	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
81	* instruction that exited. */
82	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
83	do { \
84	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
85	(a_rc) = VINF_EM_DBG_STEPPED; \
86	} while (0)
87
88	/** Assert that preemption is disabled or covered by thread-context hooks. */
89	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
90	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
91
92	/** Assert that we haven't migrated CPUs when thread-context hooks are not
93	* used. */
94	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
95	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
96	("Illegal migration! Entered on CPU %u Current %u\n", \
97	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
98
99	/** Exception bitmap mask for all contributory exceptions.
100	*
101	* Page fault is deliberately excluded here as it's conditional as to whether
102	* it's contributory or benign. Page faults are handled separately.
103	*/
104	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
105	\| RT_BIT(X86_XCPT_DE))
106
107	/** @name VMCB Clean Bits.
108	*
109	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
110	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
111	* memory.
112	*
113	* @{ */
114	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
115	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
116	/** I/O permission bitmap, MSR permission bitmap. */
117	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
118	/** ASID. */
119	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
120	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
121	V_INTR_VECTOR. */
122	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
123	/** Nested Paging: Nested CR3 (nCR3), PAT. */
124	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
125	/** Control registers (CR0, CR3, CR4, EFER). */
126	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
127	/** Debug registers (DR6, DR7). */
128	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
129	/** GDT, IDT limit and base. */
130	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
131	/** Segment register: CS, SS, DS, ES limit and base. */
132	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
133	/** CR2.*/
134	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
135	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
136	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
137	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
138	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
139	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
140	/** Mask of all valid VMCB Clean bits. */
141	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
142	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
143	\| HMSVM_VMCB_CLEAN_ASID \
144	\| HMSVM_VMCB_CLEAN_TPR \
145	\| HMSVM_VMCB_CLEAN_NP \
146	\| HMSVM_VMCB_CLEAN_CRX_EFER \
147	\| HMSVM_VMCB_CLEAN_DRX \
148	\| HMSVM_VMCB_CLEAN_DT \
149	\| HMSVM_VMCB_CLEAN_SEG \
150	\| HMSVM_VMCB_CLEAN_CR2 \
151	\| HMSVM_VMCB_CLEAN_LBR \
152	\| HMSVM_VMCB_CLEAN_AVIC)
153	/** @} */
154
155	/** @name SVM transient.
156	*
157	* A state structure for holding miscellaneous information across AMD-V
158	* VMRUN/\#VMEXIT operation, restored after the transition.
159	*
160	* @{ */
161	typedef struct SVMTRANSIENT
162	{
163	/** The host's rflags/eflags. */
164	RTCCUINTREG fEFlags;
165	#if HC_ARCH_BITS == 32
166	uint32_t u32Alignment0;
167	#endif
168
169	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
170	uint64_t u64ExitCode;
171	/** The guest's TPR value used for TPR shadowing. */
172	uint8_t u8GuestTpr;
173	/** Alignment. */
174	uint8_t abAlignment0[7];
175
176	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
177	bool fWasGuestFPUStateActive;
178	/** Whether the guest debug state was active at the time of \#VMEXIT. */
179	bool fWasGuestDebugStateActive;
180	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
181	bool fWasHyperDebugStateActive;
182	/** Whether the TSC offset mode needs to be updated. */
183	bool fUpdateTscOffsetting;
184	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
185	bool fRestoreTscAuxMsr;
186	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
187	* contributary exception or a page-fault. */
188	bool fVectoringDoublePF;
189	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
190	* external interrupt or NMI. */
191	bool fVectoringPF;
192	} SVMTRANSIENT, *PSVMTRANSIENT;
193	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
194	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
195	/** @} */
196
197	/**
198	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
199	*/
200	typedef enum SVMMSREXITREAD
201	{
202	/** Reading this MSR causes a \#VMEXIT. */
203	SVMMSREXIT_INTERCEPT_READ = 0xb,
204	/** Reading this MSR does not cause a \#VMEXIT. */
205	SVMMSREXIT_PASSTHRU_READ
206	} SVMMSREXITREAD;
207
208	/**
209	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
210	*/
211	typedef enum SVMMSREXITWRITE
212	{
213	/** Writing to this MSR causes a \#VMEXIT. */
214	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
215	/** Writing to this MSR does not cause a \#VMEXIT. */
216	SVMMSREXIT_PASSTHRU_WRITE
217	} SVMMSREXITWRITE;
218
219	/**
220	* SVM \#VMEXIT handler.
221	*
222	* @returns VBox status code.
223	* @param pVCpu The cross context virtual CPU structure.
224	* @param pMixedCtx Pointer to the guest-CPU context.
225	* @param pSvmTransient Pointer to the SVM-transient structure.
226	*/
227	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
228
229
230	/*********************************************************************************************************************************
231	* Internal Functions *
232	*********************************************************************************************************************************/
233	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
234	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
235	static void hmR0SvmLeave(PVMCPU pVCpu);
236
237	/** @name \#VMEXIT handlers.
238	* @{
239	*/
240	static FNSVMEXITHANDLER hmR0SvmExitIntr;
241	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
242	static FNSVMEXITHANDLER hmR0SvmExitInvd;
243	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
244	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
245	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
246	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
247	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
248	static FNSVMEXITHANDLER hmR0SvmExitHlt;
249	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
250	static FNSVMEXITHANDLER hmR0SvmExitMwait;
251	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
252	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
253	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
254	static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
255	static FNSVMEXITHANDLER hmR0SvmExitMsr;
256	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
257	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
258	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
259	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
260	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
261	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
262	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
263	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
264	static FNSVMEXITHANDLER hmR0SvmExitPause;
265	static FNSVMEXITHANDLER hmR0SvmExitIret;
266	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
267	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
268	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
269	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
270	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
271	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
272	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
273	#ifdef VBOX_WITH_NESTED_HWVIRT
274	static FNSVMEXITHANDLER hmR0SvmExitClgi;
275	static FNSVMEXITHANDLER hmR0SvmExitStgi;
276	static FNSVMEXITHANDLER hmR0SvmExitVmload;
277	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
278	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
279	#endif
280	/** @} */
281
282	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
283
284
285	/*********************************************************************************************************************************
286	* Global Variables *
287	*********************************************************************************************************************************/
288	/** Ring-0 memory object for the IO bitmap. */
289	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
290	/** Physical address of the IO bitmap. */
291	RTHCPHYS g_HCPhysIOBitmap = 0;
292	/** Virtual address of the IO bitmap. */
293	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
294
295
296	/**
297	* Sets up and activates AMD-V on the current CPU.
298	*
299	* @returns VBox status code.
300	* @param pCpu Pointer to the CPU info struct.
301	* @param pVM The cross context VM structure. Can be
302	* NULL after a resume!
303	* @param pvCpuPage Pointer to the global CPU page.
304	* @param HCPhysCpuPage Physical address of the global CPU page.
305	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
306	* @param pvArg Unused on AMD-V.
307	*/
308	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
309	void *pvArg)
310	{
311	Assert(!fEnabledByHost);
312	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
313	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
314	Assert(pvCpuPage); NOREF(pvCpuPage);
315	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
316
317	NOREF(pvArg);
318	NOREF(fEnabledByHost);
319
320	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
321	RTCCUINTREG fEFlags = ASMIntDisableFlags();
322
323	/*
324	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
325	*/
326	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
327	if (u64HostEfer & MSR_K6_EFER_SVME)
328	{
329	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
330	if ( pVM
331	&& pVM->hm.s.svm.fIgnoreInUseError)
332	{
333	pCpu->fIgnoreAMDVInUseError = true;
334	}
335
336	if (!pCpu->fIgnoreAMDVInUseError)
337	{
338	ASMSetFlags(fEFlags);
339	return VERR_SVM_IN_USE;
340	}
341	}
342
343	/* Turn on AMD-V in the EFER MSR. */
344	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
345
346	/* Write the physical page address where the CPU will store the host state while executing the VM. */
347	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
348
349	/* Restore interrupts. */
350	ASMSetFlags(fEFlags);
351
352	/*
353	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
354	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
355	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
356	* to flush the TLB with before using a new ASID.
357	*/
358	pCpu->fFlushAsidBeforeUse = true;
359
360	/*
361	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
362	*/
363	++pCpu->cTlbFlushes;
364
365	return VINF_SUCCESS;
366	}
367
368
369	/**
370	* Deactivates AMD-V on the current CPU.
371	*
372	* @returns VBox status code.
373	* @param pCpu Pointer to the CPU info struct.
374	* @param pvCpuPage Pointer to the global CPU page.
375	* @param HCPhysCpuPage Physical address of the global CPU page.
376	*/
377	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
378	{
379	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
380	AssertReturn( HCPhysCpuPage
381	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
382	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
383	NOREF(pCpu);
384
385	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
386	RTCCUINTREG fEFlags = ASMIntDisableFlags();
387
388	/* Turn off AMD-V in the EFER MSR. */
389	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
390	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
391
392	/* Invalidate host state physical address. */
393	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
394
395	/* Restore interrupts. */
396	ASMSetFlags(fEFlags);
397
398	return VINF_SUCCESS;
399	}
400
401
402	/**
403	* Does global AMD-V initialization (called during module initialization).
404	*
405	* @returns VBox status code.
406	*/
407	VMMR0DECL(int) SVMR0GlobalInit(void)
408	{
409	/*
410	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
411	* once globally here instead of per-VM.
412	*/
413	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
414	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
415	if (RT_FAILURE(rc))
416	return rc;
417
418	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
419	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
420
421	/* Set all bits to intercept all IO accesses. */
422	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
423	return VINF_SUCCESS;
424	}
425
426
427	/**
428	* Does global AMD-V termination (called during module termination).
429	*/
430	VMMR0DECL(void) SVMR0GlobalTerm(void)
431	{
432	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
433	{
434	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
435	g_pvIOBitmap = NULL;
436	g_HCPhysIOBitmap = 0;
437	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
438	}
439	}
440
441
442	/**
443	* Frees any allocated per-VCPU structures for a VM.
444	*
445	* @param pVM The cross context VM structure.
446	*/
447	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
448	{
449	for (uint32_t i = 0; i < pVM->cCpus; i++)
450	{
451	PVMCPU pVCpu = &pVM->aCpus[i];
452	AssertPtr(pVCpu);
453
454	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
455	{
456	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
457	pVCpu->hm.s.svm.pvVmcbHost = 0;
458	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
459	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
460	}
461
462	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
463	{
464	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
465	pVCpu->hm.s.svm.pvVmcb = 0;
466	pVCpu->hm.s.svm.HCPhysVmcb = 0;
467	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
468	}
469
470	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
471	{
472	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
473	pVCpu->hm.s.svm.pvMsrBitmap = 0;
474	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
475	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
476	}
477	}
478	}
479
480
481	/**
482	* Does per-VM AMD-V initialization.
483	*
484	* @returns VBox status code.
485	* @param pVM The cross context VM structure.
486	*/
487	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
488	{
489	int rc = VERR_INTERNAL_ERROR_5;
490
491	/*
492	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
493	*/
494	uint32_t u32Family;
495	uint32_t u32Model;
496	uint32_t u32Stepping;
497	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
498	{
499	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
500	pVM->hm.s.svm.fAlwaysFlushTLB = true;
501	}
502
503	/*
504	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
505	*/
506	for (VMCPUID i = 0; i < pVM->cCpus; i++)
507	{
508	PVMCPU pVCpu = &pVM->aCpus[i];
509	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
510	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
511	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
512	}
513
514	for (VMCPUID i = 0; i < pVM->cCpus; i++)
515	{
516	PVMCPU pVCpu = &pVM->aCpus[i];
517
518	/*
519	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
520	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
521	*/
522	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
523	if (RT_FAILURE(rc))
524	goto failure_cleanup;
525
526	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
527	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
528	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
529	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
530
531	/*
532	* Allocate one page for the guest-state VMCB.
533	*/
534	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
535	if (RT_FAILURE(rc))
536	goto failure_cleanup;
537
538	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
539	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
540	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
541	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
542
543	/*
544	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
545	* SVM to not require one.
546	*/
547	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
548	false /* fExecutable */);
549	if (RT_FAILURE(rc))
550	goto failure_cleanup;
551
552	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
553	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
554	/* Set all bits to intercept all MSR accesses (changed later on). */
555	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
556	}
557
558	return VINF_SUCCESS;
559
560	failure_cleanup:
561	hmR0SvmFreeStructs(pVM);
562	return rc;
563	}
564
565
566	/**
567	* Does per-VM AMD-V termination.
568	*
569	* @returns VBox status code.
570	* @param pVM The cross context VM structure.
571	*/
572	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
573	{
574	hmR0SvmFreeStructs(pVM);
575	return VINF_SUCCESS;
576	}
577
578
579	/**
580	* Sets the permission bits for the specified MSR in the MSRPM.
581	*
582	* @param pVCpu The cross context virtual CPU structure.
583	* @param uMsr The MSR for which the access permissions are being set.
584	* @param enmRead MSR read permissions.
585	* @param enmWrite MSR write permissions.
586	*/
587	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
588	{
589	uint16_t offMsrpm;
590	uint32_t uMsrpmBit;
591	int rc = hmSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
592	AssertRC(rc);
593
594	Assert(uMsrpmBit < 0x3fff);
595	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
596
597	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
598	pbMsrBitmap += offMsrpm;
599
600	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
601	ASMBitSet(pbMsrBitmap, uMsrpmBit);
602	else
603	ASMBitClear(pbMsrBitmap, uMsrpmBit);
604
605	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
606	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
607	else
608	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
609
610	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
611	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
612	}
613
614
615	/**
616	* Sets up AMD-V for the specified VM.
617	* This function is only called once per-VM during initalization.
618	*
619	* @returns VBox status code.
620	* @param pVM The cross context VM structure.
621	*/
622	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
623	{
624	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
625	AssertReturn(pVM, VERR_INVALID_PARAMETER);
626	Assert(pVM->hm.s.svm.fSupported);
627
628	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
629	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
630	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
631
632	for (VMCPUID i = 0; i < pVM->cCpus; i++)
633	{
634	PVMCPU pVCpu = &pVM->aCpus[i];
635	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
636
637	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
638
639	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
640	Assert(!pVCpu->hm.s.idxExitHistoryFree);
641	HMCPU_EXIT_HISTORY_RESET(pVCpu);
642
643	/* Always trap #AC for reasons of security. */
644	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
645
646	/* Always trap #DB for reasons of security. */
647	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
648
649	/* Trap exceptions unconditionally (debug purposes). */
650	#ifdef HMSVM_ALWAYS_TRAP_PF
651	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
652	#endif
653	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
654	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
655	pVmcb->ctrl.u32InterceptXcpt \|= 0
656	\| RT_BIT(X86_XCPT_BP)
657	\| RT_BIT(X86_XCPT_DE)
658	\| RT_BIT(X86_XCPT_NM)
659	\| RT_BIT(X86_XCPT_UD)
660	\| RT_BIT(X86_XCPT_NP)
661	\| RT_BIT(X86_XCPT_SS)
662	\| RT_BIT(X86_XCPT_GP)
663	\| RT_BIT(X86_XCPT_PF)
664	\| RT_BIT(X86_XCPT_MF)
665	;
666	#endif
667
668	/* Set up unconditional intercepts and conditions. */
669	pVmcb->ctrl.u64InterceptCtrl = SVM_CTRL_INTERCEPT_INTR /* External interrupt causes a #VMEXIT. */
670	\| SVM_CTRL_INTERCEPT_NMI /* Non-maskable interrupts causes a #VMEXIT. */
671	\| SVM_CTRL_INTERCEPT_INIT /* INIT signal causes a #VMEXIT. */
672	\| SVM_CTRL_INTERCEPT_RDPMC /* RDPMC causes a #VMEXIT. */
673	\| SVM_CTRL_INTERCEPT_CPUID /* CPUID causes a #VMEXIT. */
674	\| SVM_CTRL_INTERCEPT_RSM /* RSM causes a #VMEXIT. */
675	\| SVM_CTRL_INTERCEPT_HLT /* HLT causes a #VMEXIT. */
676	\| SVM_CTRL_INTERCEPT_IOIO_PROT /* Use the IOPM to cause IOIO #VMEXITs. */
677	\| SVM_CTRL_INTERCEPT_MSR_PROT /* MSR access not covered by MSRPM causes a #VMEXIT.*/
678	\| SVM_CTRL_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */
679	\| SVM_CTRL_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */
680	\| SVM_CTRL_INTERCEPT_FERR_FREEZE /* Intercept "freezing" during legacy FPU handling. */
681	\| SVM_CTRL_INTERCEPT_VMRUN /* VMRUN causes a #VMEXIT. */
682	\| SVM_CTRL_INTERCEPT_VMMCALL /* VMMCALL causes a #VMEXIT. */
683	\| SVM_CTRL_INTERCEPT_VMLOAD /* VMLOAD causes a #VMEXIT. */
684	\| SVM_CTRL_INTERCEPT_VMSAVE /* VMSAVE causes a #VMEXIT. */
685	\| SVM_CTRL_INTERCEPT_STGI /* STGI causes a #VMEXIT. */
686	\| SVM_CTRL_INTERCEPT_CLGI /* CLGI causes a #VMEXIT. */
687	\| SVM_CTRL_INTERCEPT_SKINIT /* SKINIT causes a #VMEXIT. */
688	\| SVM_CTRL_INTERCEPT_WBINVD /* WBINVD causes a #VMEXIT. */
689	\| SVM_CTRL_INTERCEPT_MONITOR /* MONITOR causes a #VMEXIT. */
690	\| SVM_CTRL_INTERCEPT_MWAIT /* MWAIT causes a #VMEXIT. */
691	\| SVM_CTRL_INTERCEPT_XSETBV; /* XSETBV causes a #VMEXIT. */
692
693	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
694	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
695
696	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
697	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
698
699	/* Intercept all DRx reads and writes by default. Changed later on. */
700	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
701	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
702
703	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
704	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
705
706	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
707	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
708	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
709
710	/* Set IO and MSR bitmap permission bitmap physical addresses. */
711	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
712	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
713
714	/* No LBR virtualization. */
715	pVmcb->ctrl.u64LBRVirt = 0;
716
717	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
718	pVmcb->ctrl.u64VmcbCleanBits = 0;
719
720	/* The host ASID MBZ, for the guest start with 1. */
721	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
722
723	/*
724	* Setup the PAT MSR (applicable for Nested Paging only).
725	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
726	* so choose type 6 for all PAT slots.
727	*/
728	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
729
730	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
731	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
732
733	/* Without Nested Paging, we need additionally intercepts. */
734	if (!pVM->hm.s.fNestedPaging)
735	{
736	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
737	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
738	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
739
740	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
741	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
742	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
743
744	/* Page faults must be intercepted to implement shadow paging. */
745	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
746	}
747
748	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
749	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
750	#endif
751
752	/* Apply the exceptions intercepts needed by the GIM provider. */
753	if (pVCpu->hm.s.fGIMTrapXcptUD)
754	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
755
756	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
757	if (fUsePauseFilter)
758	{
759	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
760	if (fPauseFilterThreshold)
761	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
762	}
763
764	/*
765	* The following MSRs are saved/restored automatically during the world-switch.
766	* Don't intercept guest read/write accesses to these MSRs.
767	*/
768	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
769	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
770	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
771	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
772	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
773	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
774	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
775	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
776	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
777	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
778	}
779
780	return VINF_SUCCESS;
781	}
782
783
784	/**
785	* Invalidates a guest page by guest virtual address.
786	*
787	* @returns VBox status code.
788	* @param pVM The cross context VM structure.
789	* @param pVCpu The cross context virtual CPU structure.
790	* @param GCVirt Guest virtual address of the page to invalidate.
791	*/
792	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
793	{
794	AssertReturn(pVM, VERR_INVALID_PARAMETER);
795	Assert(pVM->hm.s.svm.fSupported);
796
797	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
798
799	/* Skip it if a TLB flush is already pending. */
800	if (!fFlushPending)
801	{
802	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
803
804	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
805	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
806
807	#if HC_ARCH_BITS == 32
808	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
809	if (CPUMIsGuestInLongMode(pVCpu))
810	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
811	else
812	#endif
813	{
814	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
815	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
816	}
817	}
818	return VINF_SUCCESS;
819	}
820
821
822	/**
823	* Flushes the appropriate tagged-TLB entries.
824	*
825	* @param pVCpu The cross context virtual CPU structure.
826	*/
827	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
828	{
829	PVM pVM = pVCpu->CTX_SUFF(pVM);
830	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
831	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
832
833	/*
834	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
835	* This can happen both for start & resume due to long jumps back to ring-3.
836	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
837	* so we cannot reuse the ASIDs without flushing.
838	*/
839	bool fNewAsid = false;
840	Assert(pCpu->idCpu != NIL_RTCPUID);
841	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
842	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
843	{
844	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
845	pVCpu->hm.s.fForceTLBFlush = true;
846	fNewAsid = true;
847	}
848
849	/* Set TLB flush state as checked until we return from the world switch. */
850	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
851
852	/* Check for explicit TLB flushes. */
853	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
854	{
855	pVCpu->hm.s.fForceTLBFlush = true;
856	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
857	}
858
859	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
860
861	if (pVM->hm.s.svm.fAlwaysFlushTLB)
862	{
863	/*
864	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
865	*/
866	pCpu->uCurrentAsid = 1;
867	pVCpu->hm.s.uCurrentAsid = 1;
868	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
869	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
870
871	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
872	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
873
874	/* Keep track of last CPU ID even when flushing all the time. */
875	if (fNewAsid)
876	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
877	}
878	else if (pVCpu->hm.s.fForceTLBFlush)
879	{
880	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
881	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
882
883	if (fNewAsid)
884	{
885	++pCpu->uCurrentAsid;
886	bool fHitASIDLimit = false;
887	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
888	{
889	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
890	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
891	fHitASIDLimit = true;
892
893	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
894	{
895	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
896	pCpu->fFlushAsidBeforeUse = true;
897	}
898	else
899	{
900	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
901	pCpu->fFlushAsidBeforeUse = false;
902	}
903	}
904
905	if ( !fHitASIDLimit
906	&& pCpu->fFlushAsidBeforeUse)
907	{
908	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
909	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
910	else
911	{
912	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
913	pCpu->fFlushAsidBeforeUse = false;
914	}
915	}
916
917	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
918	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
919	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
920	}
921	else
922	{
923	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
924	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
925	else
926	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
927	}
928
929	pVCpu->hm.s.fForceTLBFlush = false;
930	}
931
932	/* Update VMCB with the ASID. */
933	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
934	{
935	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
936	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
937	}
938
939	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
940	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
941	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
942	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
943	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
944	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
945	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
946	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
947
948	#ifdef VBOX_WITH_STATISTICS
949	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
950	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
951	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
952	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
953	{
954	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
955	}
956	else
957	{
958	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
959	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
960	}
961	#endif
962	}
963
964
965	/** @name 64-bit guest on 32-bit host OS helper functions.
966	*
967	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
968	* mode (code segment, paging). These wrappers/helpers perform the necessary
969	* bits for the 32->64 switcher.
970	*
971	* @{ */
972	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
973	/**
974	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
975	*
976	* @returns VBox status code.
977	* @param HCPhysVmcbHost Physical address of host VMCB.
978	* @param HCPhysVmcb Physical address of the VMCB.
979	* @param pCtx Pointer to the guest-CPU context.
980	* @param pVM The cross context VM structure.
981	* @param pVCpu The cross context virtual CPU structure.
982	*/
983	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
984	{
985	uint32_t aParam[8];
986	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
987	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
988	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
989	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
990	aParam[4] = VM_RC_ADDR(pVM, pVM);
991	aParam[5] = 0;
992	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
993	aParam[7] = 0;
994
995	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
996	}
997
998
999	/**
1000	* Executes the specified VMRUN handler in 64-bit mode.
1001	*
1002	* @returns VBox status code.
1003	* @param pVM The cross context VM structure.
1004	* @param pVCpu The cross context virtual CPU structure.
1005	* @param pCtx Pointer to the guest-CPU context.
1006	* @param enmOp The operation to perform.
1007	* @param cParams Number of parameters.
1008	* @param paParam Array of 32-bit parameters.
1009	*/
1010	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1011	uint32_t cParams, uint32_t *paParam)
1012	{
1013	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1014	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1015
1016	NOREF(pCtx);
1017
1018	/* Disable interrupts. */
1019	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1020
1021	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1022	RTCPUID idHostCpu = RTMpCpuId();
1023	CPUMR0SetLApic(pVCpu, idHostCpu);
1024	#endif
1025
1026	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1027	CPUMSetHyperEIP(pVCpu, enmOp);
1028	for (int i = (int)cParams - 1; i >= 0; i--)
1029	CPUMPushHyper(pVCpu, paParam[i]);
1030
1031	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1032	/* Call the switcher. */
1033	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1034	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1035
1036	/* Restore interrupts. */
1037	ASMSetFlags(uOldEFlags);
1038	return rc;
1039	}
1040
1041	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1042	/** @} */
1043
1044
1045	/**
1046	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1047	* the corresponding VMCB Clean bit.
1048	*
1049	* @param pVmcb Pointer to the VM control block.
1050	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1051	*/
1052	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1053	{
1054	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1055	{
1056	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1057	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1058	}
1059	}
1060
1061
1062	/**
1063	* Removes an exception from the intercept-exception bitmap in the VMCB and
1064	* updates the corresponding VMCB Clean bit.
1065	*
1066	* @param pVmcb Pointer to the VM control block.
1067	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1068	*/
1069	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1070	{
1071	Assert(u32Xcpt != X86_XCPT_DB);
1072	Assert(u32Xcpt != X86_XCPT_AC);
1073	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1074	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1075	{
1076	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1077	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1078	}
1079	#endif
1080	}
1081
1082
1083	/**
1084	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1085	* Although the guest CR0 is a separate field in the VMCB we have to consider
1086	* the FPU state itself which is shared between the host and the guest.
1087	*
1088	* @returns VBox status code.
1089	* @param pVCpu The cross context virtual CPU structure.
1090	* @param pVmcb Pointer to the VM control block.
1091	* @param pCtx Pointer to the guest-CPU context.
1092	*
1093	* @remarks No-long-jump zone!!!
1094	*/
1095	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1096	{
1097	/*
1098	* Guest CR0.
1099	*/
1100	PVM pVM = pVCpu->CTX_SUFF(pVM);
1101	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1102	{
1103	uint64_t u64GuestCR0 = pCtx->cr0;
1104
1105	/* Always enable caching. */
1106	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1107
1108	/*
1109	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1110	*/
1111	if (!pVM->hm.s.fNestedPaging)
1112	{
1113	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1114	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1115	}
1116
1117	/*
1118	* Guest FPU bits.
1119	*/
1120	bool fInterceptNM = false;
1121	bool fInterceptMF = false;
1122	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1123	if (CPUMIsGuestFPUStateActive(pVCpu))
1124	{
1125	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1126	if (!(pCtx->cr0 & X86_CR0_NE))
1127	{
1128	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1129	fInterceptMF = true;
1130	}
1131	}
1132	else
1133	{
1134	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1135	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1136	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1137	}
1138
1139	/*
1140	* Update the exception intercept bitmap.
1141	*/
1142	if (fInterceptNM)
1143	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1144	else
1145	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1146
1147	if (fInterceptMF)
1148	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1149	else
1150	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1151
1152	pVmcb->guest.u64CR0 = u64GuestCR0;
1153	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1154	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1155	}
1156	}
1157
1158
1159	/**
1160	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1161	*
1162	* @returns VBox status code.
1163	* @param pVCpu The cross context virtual CPU structure.
1164	* @param pVmcb Pointer to the VM control block.
1165	* @param pCtx Pointer to the guest-CPU context.
1166	*
1167	* @remarks No-long-jump zone!!!
1168	*/
1169	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1170	{
1171	PVM pVM = pVCpu->CTX_SUFF(pVM);
1172
1173	/*
1174	* Guest CR2.
1175	*/
1176	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1177	{
1178	pVmcb->guest.u64CR2 = pCtx->cr2;
1179	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1180	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1181	}
1182
1183	/*
1184	* Guest CR3.
1185	*/
1186	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1187	{
1188	if (pVM->hm.s.fNestedPaging)
1189	{
1190	PGMMODE enmShwPagingMode;
1191	#if HC_ARCH_BITS == 32
1192	if (CPUMIsGuestInLongModeEx(pCtx))
1193	enmShwPagingMode = PGMMODE_AMD64_NX;
1194	else
1195	#endif
1196	enmShwPagingMode = PGMGetHostMode(pVM);
1197
1198	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1199	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1200	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1201	pVmcb->guest.u64CR3 = pCtx->cr3;
1202	}
1203	else
1204	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1205
1206	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1207	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1208	}
1209
1210	/*
1211	* Guest CR4.
1212	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1213	*/
1214	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1215	{
1216	uint64_t u64GuestCR4 = pCtx->cr4;
1217	if (!pVM->hm.s.fNestedPaging)
1218	{
1219	switch (pVCpu->hm.s.enmShadowMode)
1220	{
1221	case PGMMODE_REAL:
1222	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1223	AssertFailed();
1224	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1225
1226	case PGMMODE_32_BIT: /* 32-bit paging. */
1227	u64GuestCR4 &= ~X86_CR4_PAE;
1228	break;
1229
1230	case PGMMODE_PAE: /* PAE paging. */
1231	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1232	/** Must use PAE paging as we could use physical memory > 4 GB */
1233	u64GuestCR4 \|= X86_CR4_PAE;
1234	break;
1235
1236	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1237	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1238	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1239	break;
1240	#else
1241	AssertFailed();
1242	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1243	#endif
1244
1245	default: /* shut up gcc */
1246	AssertFailed();
1247	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1248	}
1249	}
1250
1251	pVmcb->guest.u64CR4 = u64GuestCR4;
1252	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1253
1254	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1255	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1256
1257	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1258	}
1259
1260	return VINF_SUCCESS;
1261	}
1262
1263
1264	/**
1265	* Loads the guest segment registers into the VMCB.
1266	*
1267	* @returns VBox status code.
1268	* @param pVCpu The cross context virtual CPU structure.
1269	* @param pVmcb Pointer to the VM control block.
1270	* @param pCtx Pointer to the guest-CPU context.
1271	*
1272	* @remarks No-long-jump zone!!!
1273	*/
1274	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1275	{
1276	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1277	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1278	{
1279	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1280	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1281	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1282	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1283	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1284	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1285
1286	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1287	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1288	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1289	}
1290
1291	/* Guest TR. */
1292	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1293	{
1294	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1295	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1296	}
1297
1298	/* Guest LDTR. */
1299	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1300	{
1301	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1302	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1303	}
1304
1305	/* Guest GDTR. */
1306	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1307	{
1308	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1309	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1310	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1311	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1312	}
1313
1314	/* Guest IDTR. */
1315	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1316	{
1317	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1318	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1319	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1320	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1321	}
1322	}
1323
1324
1325	/**
1326	* Loads the guest MSRs into the VMCB.
1327	*
1328	* @param pVCpu The cross context virtual CPU structure.
1329	* @param pVmcb Pointer to the VM control block.
1330	* @param pCtx Pointer to the guest-CPU context.
1331	*
1332	* @remarks No-long-jump zone!!!
1333	*/
1334	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1335	{
1336	/* Guest Sysenter MSRs. */
1337	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1338	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1339	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1340
1341	/*
1342	* Guest EFER MSR.
1343	* AMD-V requires guest EFER.SVME to be set. Weird.
1344	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1345	*/
1346	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1347	{
1348	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1349	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1350	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1351	}
1352
1353	/* 64-bit MSRs. */
1354	if (CPUMIsGuestInLongModeEx(pCtx))
1355	{
1356	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1357	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1358	}
1359	else
1360	{
1361	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1362	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1363	{
1364	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1365	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1366	}
1367	}
1368
1369
1370	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1371	* be writable in 32-bit mode. Clarify with AMD spec. */
1372	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1373	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1374	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1375	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1376	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1377	}
1378
1379
1380	/**
1381	* Loads the guest state into the VMCB and programs the necessary intercepts
1382	* accordingly.
1383	*
1384	* @param pVCpu The cross context virtual CPU structure.
1385	* @param pVmcb Pointer to the VM control block.
1386	* @param pCtx Pointer to the guest-CPU context.
1387	*
1388	* @remarks No-long-jump zone!!!
1389	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1390	*/
1391	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1392	{
1393	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1394	return;
1395	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1396	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1397
1398	bool fInterceptMovDRx = false;
1399
1400	/*
1401	* Anyone single stepping on the host side? If so, we'll have to use the
1402	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1403	* the VMM level like the VT-x implementations does.
1404	*/
1405	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1406	if (fStepping)
1407	{
1408	pVCpu->hm.s.fClearTrapFlag = true;
1409	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1410	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1411	}
1412	else
1413	Assert(!DBGFIsStepping(pVCpu));
1414
1415	if ( fStepping
1416	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1417	{
1418	/*
1419	* Use the combined guest and host DRx values found in the hypervisor
1420	* register set because the debugger has breakpoints active or someone
1421	* is single stepping on the host side.
1422	*
1423	* Note! DBGF expects a clean DR6 state before executing guest code.
1424	*/
1425	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1426	if ( CPUMIsGuestInLongModeEx(pCtx)
1427	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1428	{
1429	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1430	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1431	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1432	}
1433	else
1434	#endif
1435	if (!CPUMIsHyperDebugStateActive(pVCpu))
1436	{
1437	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1438	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1439	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1440	}
1441
1442	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1443	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1444	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1445	{
1446	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1447	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1448	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1449	pVCpu->hm.s.fUsingHyperDR7 = true;
1450	}
1451
1452	/** @todo If we cared, we could optimize to allow the guest to read registers
1453	* with the same values. */
1454	fInterceptMovDRx = true;
1455	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1456	}
1457	else
1458	{
1459	/*
1460	* Update DR6, DR7 with the guest values if necessary.
1461	*/
1462	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1463	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1464	{
1465	pVmcb->guest.u64DR7 = pCtx->dr[7];
1466	pVmcb->guest.u64DR6 = pCtx->dr[6];
1467	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1468	pVCpu->hm.s.fUsingHyperDR7 = false;
1469	}
1470
1471	/*
1472	* If the guest has enabled debug registers, we need to load them prior to
1473	* executing guest code so they'll trigger at the right time.
1474	*/
1475	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1476	{
1477	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1478	if ( CPUMIsGuestInLongModeEx(pCtx)
1479	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1480	{
1481	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1482	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1483	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1484	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1485	}
1486	else
1487	#endif
1488	if (!CPUMIsGuestDebugStateActive(pVCpu))
1489	{
1490	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1491	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1492	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1493	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1494	}
1495	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1496	}
1497	/*
1498	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1499	* intercept #DB as DR6 is updated in the VMCB.
1500	*
1501	* Note! If we cared and dared, we could skip intercepting \#DB here.
1502	* However, \#DB shouldn't be performance critical, so we'll play safe
1503	* and keep the code similar to the VT-x code and always intercept it.
1504	*/
1505	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1506	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1507	&& !CPUMIsGuestDebugStateActive(pVCpu))
1508	#else
1509	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1510	#endif
1511	{
1512	fInterceptMovDRx = true;
1513	}
1514	}
1515
1516	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1517	if (fInterceptMovDRx)
1518	{
1519	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1520	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1521	{
1522	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1523	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1524	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1525	}
1526	}
1527	else
1528	{
1529	if ( pVmcb->ctrl.u16InterceptRdDRx
1530	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1531	{
1532	pVmcb->ctrl.u16InterceptRdDRx = 0;
1533	pVmcb->ctrl.u16InterceptWrDRx = 0;
1534	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1535	}
1536	}
1537
1538	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1539	}
1540
1541
1542	/**
1543	* Loads the guest APIC state (currently just the TPR).
1544	*
1545	* @returns VBox status code.
1546	* @param pVCpu The cross context virtual CPU structure.
1547	* @param pVmcb Pointer to the VM control block.
1548	* @param pCtx Pointer to the guest-CPU context.
1549	*/
1550	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1551	{
1552	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1553	return VINF_SUCCESS;
1554
1555	int rc = VINF_SUCCESS;
1556	PVM pVM = pVCpu->CTX_SUFF(pVM);
1557	if ( PDMHasApic(pVM)
1558	&& APICIsEnabled(pVCpu))
1559	{
1560	bool fPendingIntr;
1561	uint8_t u8Tpr;
1562	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1563	AssertRCReturn(rc, rc);
1564
1565	/* Assume that we need to trap all TPR accesses and thus need not check on
1566	every #VMEXIT if we should update the TPR. */
1567	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1568	pVCpu->hm.s.svm.fSyncVTpr = false;
1569
1570	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1571	if (pVM->hm.s.fTPRPatchingActive)
1572	{
1573	pCtx->msrLSTAR = u8Tpr;
1574
1575	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1576	if (fPendingIntr)
1577	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1578	else
1579	{
1580	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1581	pVCpu->hm.s.svm.fSyncVTpr = true;
1582	}
1583	}
1584	else
1585	{
1586	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1587	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1588
1589	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1590	if (fPendingIntr)
1591	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1592	else
1593	{
1594	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1595	pVCpu->hm.s.svm.fSyncVTpr = true;
1596	}
1597
1598	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1599	}
1600	}
1601
1602	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1603	return rc;
1604	}
1605
1606
1607	/**
1608	* Loads the exception interrupts required for guest execution in the VMCB.
1609	*
1610	* @returns VBox status code.
1611	* @param pVCpu The cross context virtual CPU structure.
1612	* @param pVmcb Pointer to the VM control block.
1613	* @param pCtx Pointer to the guest-CPU context.
1614	*/
1615	static int hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1616	{
1617	NOREF(pCtx);
1618	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1619	{
1620	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1621	if (pVCpu->hm.s.fGIMTrapXcptUD)
1622	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1623	else
1624	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1625
1626	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1627	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1628	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1629	else
1630	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_BP);
1631
1632	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1633	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1634	}
1635	return VINF_SUCCESS;
1636	}
1637
1638
1639	/**
1640	* Sets up the appropriate function to run guest code.
1641	*
1642	* @returns VBox status code.
1643	* @param pVCpu The cross context virtual CPU structure.
1644	* @param pCtx Pointer to the guest-CPU context.
1645	*
1646	* @remarks No-long-jump zone!!!
1647	*/
1648	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1649	{
1650	if (CPUMIsGuestInLongModeEx(pCtx))
1651	{
1652	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1653	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1654	#endif
1655	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1656	#if HC_ARCH_BITS == 32
1657	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1658	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1659	#else
1660	/* 64-bit host or hybrid host. */
1661	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1662	#endif
1663	}
1664	else
1665	{
1666	/* Guest is not in long mode, use the 32-bit handler. */
1667	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1668	}
1669	return VINF_SUCCESS;
1670	}
1671
1672
1673	/**
1674	* Enters the AMD-V session.
1675	*
1676	* @returns VBox status code.
1677	* @param pVM The cross context VM structure.
1678	* @param pVCpu The cross context virtual CPU structure.
1679	* @param pCpu Pointer to the CPU info struct.
1680	*/
1681	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1682	{
1683	AssertPtr(pVM);
1684	AssertPtr(pVCpu);
1685	Assert(pVM->hm.s.svm.fSupported);
1686	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1687	NOREF(pVM); NOREF(pCpu);
1688
1689	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1690	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1691
1692	pVCpu->hm.s.fLeaveDone = false;
1693	return VINF_SUCCESS;
1694	}
1695
1696
1697	/**
1698	* Thread-context callback for AMD-V.
1699	*
1700	* @param enmEvent The thread-context event.
1701	* @param pVCpu The cross context virtual CPU structure.
1702	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1703	* @thread EMT(pVCpu)
1704	*/
1705	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1706	{
1707	NOREF(fGlobalInit);
1708
1709	switch (enmEvent)
1710	{
1711	case RTTHREADCTXEVENT_OUT:
1712	{
1713	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1714	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1715	VMCPU_ASSERT_EMT(pVCpu);
1716
1717	/* No longjmps (log-flush, locks) in this fragile context. */
1718	VMMRZCallRing3Disable(pVCpu);
1719
1720	if (!pVCpu->hm.s.fLeaveDone)
1721	{
1722	hmR0SvmLeave(pVCpu);
1723	pVCpu->hm.s.fLeaveDone = true;
1724	}
1725
1726	/* Leave HM context, takes care of local init (term). */
1727	int rc = HMR0LeaveCpu(pVCpu);
1728	AssertRC(rc); NOREF(rc);
1729
1730	/* Restore longjmp state. */
1731	VMMRZCallRing3Enable(pVCpu);
1732	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
1733	break;
1734	}
1735
1736	case RTTHREADCTXEVENT_IN:
1737	{
1738	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1739	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1740	VMCPU_ASSERT_EMT(pVCpu);
1741
1742	/* No longjmps (log-flush, locks) in this fragile context. */
1743	VMMRZCallRing3Disable(pVCpu);
1744
1745	/*
1746	* Initialize the bare minimum state required for HM. This takes care of
1747	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1748	*/
1749	int rc = HMR0EnterCpu(pVCpu);
1750	AssertRC(rc); NOREF(rc);
1751	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1752
1753	pVCpu->hm.s.fLeaveDone = false;
1754
1755	/* Restore longjmp state. */
1756	VMMRZCallRing3Enable(pVCpu);
1757	break;
1758	}
1759
1760	default:
1761	break;
1762	}
1763	}
1764
1765
1766	/**
1767	* Saves the host state.
1768	*
1769	* @returns VBox status code.
1770	* @param pVM The cross context VM structure.
1771	* @param pVCpu The cross context virtual CPU structure.
1772	*
1773	* @remarks No-long-jump zone!!!
1774	*/
1775	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1776	{
1777	NOREF(pVM);
1778	NOREF(pVCpu);
1779	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1780	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1781	return VINF_SUCCESS;
1782	}
1783
1784
1785	/**
1786	* Loads the guest state into the VMCB.
1787	*
1788	* The CPU state will be loaded from these fields on every successful VM-entry.
1789	* Also sets up the appropriate VMRUN function to execute guest code based on
1790	* the guest CPU mode.
1791	*
1792	* @returns VBox status code.
1793	* @param pVM The cross context VM structure.
1794	* @param pVCpu The cross context virtual CPU structure.
1795	* @param pCtx Pointer to the guest-CPU context.
1796	*
1797	* @remarks No-long-jump zone!!!
1798	*/
1799	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1800	{
1801	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1802	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1803
1804	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1805
1806	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1807	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1808
1809	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1810	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1811
1812	pVmcb->guest.u64RIP = pCtx->rip;
1813	pVmcb->guest.u64RSP = pCtx->rsp;
1814	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1815	pVmcb->guest.u64RAX = pCtx->rax;
1816
1817	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1818	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1819
1820	rc = hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1821	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1822
1823	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1824	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1825
1826	/* Clear any unused and reserved bits. */
1827	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1828	\| HM_CHANGED_GUEST_RSP
1829	\| HM_CHANGED_GUEST_RFLAGS
1830	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1831	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1832	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1833	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1834	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1835	\| HM_CHANGED_SVM_RESERVED2
1836	\| HM_CHANGED_SVM_RESERVED3
1837	\| HM_CHANGED_SVM_RESERVED4);
1838
1839	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1840	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1841	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1842	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1843
1844	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss.Sel, pCtx->rsp));
1845	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1846	return rc;
1847	}
1848
1849
1850	/**
1851	* Loads the state shared between the host and guest into the
1852	* VMCB.
1853	*
1854	* @param pVCpu The cross context virtual CPU structure.
1855	* @param pVmcb Pointer to the VM control block.
1856	* @param pCtx Pointer to the guest-CPU context.
1857	*
1858	* @remarks No-long-jump zone!!!
1859	*/
1860	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1861	{
1862	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1863	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1864
1865	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1866	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1867
1868	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1869	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1870
1871	/* Unused on AMD-V. */
1872	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
1873
1874	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1875	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1876	}
1877
1878
1879	/**
1880	* Saves the entire guest state from the VMCB into the
1881	* guest-CPU context. Currently there is no residual state left in the CPU that
1882	* is not updated in the VMCB.
1883	*
1884	* @returns VBox status code.
1885	* @param pVCpu The cross context virtual CPU structure.
1886	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1887	* out-of-sync. Make sure to update the required fields
1888	* before using them.
1889	*/
1890	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1891	{
1892	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1893
1894	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1895
1896	pMixedCtx->rip = pVmcb->guest.u64RIP;
1897	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1898	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1899	pMixedCtx->rax = pVmcb->guest.u64RAX;
1900
1901	/*
1902	* Guest interrupt shadow.
1903	*/
1904	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1905	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1906	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1907	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1908
1909	/*
1910	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1911	*/
1912	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1913
1914	/*
1915	* Guest MSRs.
1916	*/
1917	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1918	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1919	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1920	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1921	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1922	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1923	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1924	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1925
1926	/*
1927	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1928	*/
1929	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
1930	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
1931	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
1932	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
1933	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
1934	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
1935
1936	/*
1937	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1938	* register (yet).
1939	*/
1940	/** @todo SELM might need to be fixed as it too should not care about the
1941	* granularity bit. See @bugref{6785}. */
1942	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1943	&& pMixedCtx->cs.Attr.n.u1Present
1944	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1945	{
1946	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1947	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1948	}
1949
1950	#ifdef VBOX_STRICT
1951	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1952	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1953	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1954	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1955	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1956	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1957	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1958
1959	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1960	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1961	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1962	HMSVM_ASSERT_SEG_GRANULARITY(es);
1963	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1964	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1965
1966	# undef HMSVM_ASSERT_SEL_GRANULARITY
1967	#endif
1968
1969	/*
1970	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1971	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1972	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1973	* See AMD spec. 15.5.1 "Basic operation".
1974	*/
1975	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1976	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1977
1978	/*
1979	* Guest TR.
1980	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
1981	* between Intel and AMD. See @bugref{6208#c39}.
1982	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
1983	*/
1984	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
1985	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1986	{
1987	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1988	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
1989	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1990	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1991	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1992	}
1993
1994	/*
1995	* Guest Descriptor-Table registers.
1996	*/
1997	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
1998	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1999	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2000
2001	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2002	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2003
2004	/*
2005	* Guest Debug registers.
2006	*/
2007	if (!pVCpu->hm.s.fUsingHyperDR7)
2008	{
2009	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2010	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2011	}
2012	else
2013	{
2014	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2015	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2016	}
2017
2018	/*
2019	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2020	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2021	*/
2022	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
2023	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2024	{
2025	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2026	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2027	}
2028	}
2029
2030
2031	/**
2032	* Does the necessary state syncing before returning to ring-3 for any reason
2033	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2034	*
2035	* @param pVCpu The cross context virtual CPU structure.
2036	*
2037	* @remarks No-long-jmp zone!!!
2038	*/
2039	static void hmR0SvmLeave(PVMCPU pVCpu)
2040	{
2041	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2042	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2043	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2044
2045	/*
2046	* !!! IMPORTANT !!!
2047	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2048	*/
2049
2050	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2051	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2052	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2053
2054	/*
2055	* Restore host debug registers if necessary and resync on next R0 reentry.
2056	*/
2057	#ifdef VBOX_STRICT
2058	if (CPUMIsHyperDebugStateActive(pVCpu))
2059	{
2060	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2061	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2062	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2063	}
2064	#endif
2065	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2066	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2067
2068	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2069	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2070
2071	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2072	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2073	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2074	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2075	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2076
2077	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2078	}
2079
2080
2081	/**
2082	* Leaves the AMD-V session.
2083	*
2084	* @returns VBox status code.
2085	* @param pVCpu The cross context virtual CPU structure.
2086	*/
2087	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2088	{
2089	HM_DISABLE_PREEMPT();
2090	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2091	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2092
2093	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2094	and done this from the SVMR0ThreadCtxCallback(). */
2095	if (!pVCpu->hm.s.fLeaveDone)
2096	{
2097	hmR0SvmLeave(pVCpu);
2098	pVCpu->hm.s.fLeaveDone = true;
2099	}
2100
2101	/*
2102	* !!! IMPORTANT !!!
2103	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2104	*/
2105
2106	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2107	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2108	VMMR0ThreadCtxHookDisable(pVCpu);
2109
2110	/* Leave HM context. This takes care of local init (term). */
2111	int rc = HMR0LeaveCpu(pVCpu);
2112
2113	HM_RESTORE_PREEMPT();
2114	return rc;
2115	}
2116
2117
2118	/**
2119	* Does the necessary state syncing before doing a longjmp to ring-3.
2120	*
2121	* @returns VBox status code.
2122	* @param pVCpu The cross context virtual CPU structure.
2123	*
2124	* @remarks No-long-jmp zone!!!
2125	*/
2126	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2127	{
2128	return hmR0SvmLeaveSession(pVCpu);
2129	}
2130
2131
2132	/**
2133	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2134	* any remaining host state) before we longjump to ring-3 and possibly get
2135	* preempted.
2136	*
2137	* @param pVCpu The cross context virtual CPU structure.
2138	* @param enmOperation The operation causing the ring-3 longjump.
2139	* @param pvUser The user argument (pointer to the possibly
2140	* out-of-date guest-CPU context).
2141	*/
2142	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2143	{
2144	RT_NOREF_PV(pvUser);
2145
2146	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2147	{
2148	/*
2149	* !!! IMPORTANT !!!
2150	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2151	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2152	*/
2153	VMMRZCallRing3RemoveNotification(pVCpu);
2154	VMMRZCallRing3Disable(pVCpu);
2155	HM_DISABLE_PREEMPT();
2156
2157	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2158	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2159
2160	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2161	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2162
2163	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2164	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2165	VMMR0ThreadCtxHookDisable(pVCpu);
2166
2167	/* Leave HM context. This takes care of local init (term). */
2168	HMR0LeaveCpu(pVCpu);
2169
2170	HM_RESTORE_PREEMPT();
2171	return VINF_SUCCESS;
2172	}
2173
2174	Assert(pVCpu);
2175	Assert(pvUser);
2176	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2177	HMSVM_ASSERT_PREEMPT_SAFE();
2178
2179	VMMRZCallRing3Disable(pVCpu);
2180	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2181
2182	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2183	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2184	AssertRCReturn(rc, rc);
2185
2186	VMMRZCallRing3Enable(pVCpu);
2187	return VINF_SUCCESS;
2188	}
2189
2190
2191	/**
2192	* Take necessary actions before going back to ring-3.
2193	*
2194	* An action requires us to go back to ring-3. This function does the necessary
2195	* steps before we can safely return to ring-3. This is not the same as longjmps
2196	* to ring-3, this is voluntary.
2197	*
2198	* @returns VBox status code.
2199	* @param pVM The cross context VM structure.
2200	* @param pVCpu The cross context virtual CPU structure.
2201	* @param pCtx Pointer to the guest-CPU context.
2202	* @param rcExit The reason for exiting to ring-3. Can be
2203	* VINF_VMM_UNKNOWN_RING3_CALL.
2204	*/
2205	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2206	{
2207	Assert(pVM);
2208	Assert(pVCpu);
2209	Assert(pCtx);
2210	HMSVM_ASSERT_PREEMPT_SAFE();
2211
2212	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2213	VMMRZCallRing3Disable(pVCpu);
2214	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2215
2216	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2217	if (pVCpu->hm.s.Event.fPending)
2218	{
2219	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2220	Assert(!pVCpu->hm.s.Event.fPending);
2221	}
2222
2223	/* Sync. the necessary state for going back to ring-3. */
2224	hmR0SvmLeaveSession(pVCpu);
2225	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2226
2227	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2228	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2229	\| CPUM_CHANGED_LDTR
2230	\| CPUM_CHANGED_GDTR
2231	\| CPUM_CHANGED_IDTR
2232	\| CPUM_CHANGED_TR
2233	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2234	if ( pVM->hm.s.fNestedPaging
2235	&& CPUMIsGuestPagingEnabledEx(pCtx))
2236	{
2237	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2238	}
2239
2240	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2241	if (rcExit != VINF_EM_RAW_INTERRUPT)
2242	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2243
2244	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2245
2246	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2247	VMMRZCallRing3RemoveNotification(pVCpu);
2248	VMMRZCallRing3Enable(pVCpu);
2249
2250	/*
2251	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2252	* and if we're injecting an event we should have a TRPM trap pending.
2253	*/
2254	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2255	pVCpu->hm.s.u32HMError = rcExit,
2256	VERR_SVM_IPE_5);
2257	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2258	pVCpu->hm.s.u32HMError = rcExit,
2259	VERR_SVM_IPE_4);
2260
2261	return rcExit;
2262	}
2263
2264
2265	/**
2266	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2267	* intercepts.
2268	*
2269	* @param pVM The cross context VM structure.
2270	* @param pVCpu The cross context virtual CPU structure.
2271	*
2272	* @remarks No-long-jump zone!!!
2273	*/
2274	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu)
2275	{
2276	bool fParavirtTsc;
2277	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2278	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2279	if (fCanUseRealTsc)
2280	{
2281	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2282	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2283	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2284	}
2285	else
2286	{
2287	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2288	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2289	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2290	}
2291	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2292
2293	/** @todo later optimize this to be done elsewhere and not before every
2294	* VM-entry. */
2295	if (fParavirtTsc)
2296	{
2297	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2298	information before every VM-entry, hence disable it for performance sake. */
2299	#if 0
2300	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2301	AssertRC(rc);
2302	#endif
2303	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2304	}
2305	}
2306
2307
2308	/**
2309	* Sets an event as a pending event to be injected into the guest.
2310	*
2311	* @param pVCpu The cross context virtual CPU structure.
2312	* @param pEvent Pointer to the SVM event.
2313	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2314	* page-fault.
2315	*
2316	* @remarks Statistics counter assumes this is a guest event being reflected to
2317	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2318	*/
2319	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2320	{
2321	Assert(!pVCpu->hm.s.Event.fPending);
2322	Assert(pEvent->n.u1Valid);
2323
2324	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2325	pVCpu->hm.s.Event.fPending = true;
2326	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2327
2328	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2329	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2330	}
2331
2332
2333	/**
2334	* Injects an event into the guest upon VMRUN by updating the relevant field
2335	* in the VMCB.
2336	*
2337	* @param pVCpu The cross context virtual CPU structure.
2338	* @param pVmcb Pointer to the guest VM control block.
2339	* @param pCtx Pointer to the guest-CPU context.
2340	* @param pEvent Pointer to the event.
2341	*
2342	* @remarks No-long-jump zone!!!
2343	* @remarks Requires CR0!
2344	*/
2345	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2346	{
2347	NOREF(pVCpu); NOREF(pCtx);
2348
2349	pVmcb->ctrl.EventInject.u = pEvent->u;
2350	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2351
2352	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2353	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2354	}
2355
2356
2357
2358	/**
2359	* Converts any TRPM trap into a pending HM event. This is typically used when
2360	* entering from ring-3 (not longjmp returns).
2361	*
2362	* @param pVCpu The cross context virtual CPU structure.
2363	*/
2364	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2365	{
2366	Assert(TRPMHasTrap(pVCpu));
2367	Assert(!pVCpu->hm.s.Event.fPending);
2368
2369	uint8_t uVector;
2370	TRPMEVENT enmTrpmEvent;
2371	RTGCUINT uErrCode;
2372	RTGCUINTPTR GCPtrFaultAddress;
2373	uint8_t cbInstr;
2374
2375	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2376	AssertRC(rc);
2377
2378	SVMEVENT Event;
2379	Event.u = 0;
2380	Event.n.u1Valid = 1;
2381	Event.n.u8Vector = uVector;
2382
2383	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2384	if (enmTrpmEvent == TRPM_TRAP)
2385	{
2386	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2387	switch (uVector)
2388	{
2389	case X86_XCPT_NMI:
2390	{
2391	Event.n.u3Type = SVM_EVENT_NMI;
2392	break;
2393	}
2394
2395	case X86_XCPT_PF:
2396	case X86_XCPT_DF:
2397	case X86_XCPT_TS:
2398	case X86_XCPT_NP:
2399	case X86_XCPT_SS:
2400	case X86_XCPT_GP:
2401	case X86_XCPT_AC:
2402	{
2403	Event.n.u1ErrorCodeValid = 1;
2404	Event.n.u32ErrorCode = uErrCode;
2405	break;
2406	}
2407	}
2408	}
2409	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2410	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2411	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2412	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2413	else
2414	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2415
2416	rc = TRPMResetTrap(pVCpu);
2417	AssertRC(rc);
2418
2419	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2420	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2421
2422	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2423	}
2424
2425
2426	/**
2427	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2428	* AMD-V to execute any instruction.
2429	*
2430	* @param pVCpu The cross context virtual CPU structure.
2431	*/
2432	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2433	{
2434	Assert(pVCpu->hm.s.Event.fPending);
2435	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2436
2437	SVMEVENT Event;
2438	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2439
2440	uint8_t uVector = Event.n.u8Vector;
2441	uint8_t uVectorType = Event.n.u3Type;
2442	TRPMEVENT enmTrapType = hmSvmEventToTrpmEventType(&Event);
2443
2444	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2445
2446	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2447	AssertRC(rc);
2448
2449	if (Event.n.u1ErrorCodeValid)
2450	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2451
2452	if ( uVectorType == SVM_EVENT_EXCEPTION
2453	&& uVector == X86_XCPT_PF)
2454	{
2455	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2456	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2457	}
2458	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2459	{
2460	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2461	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2462	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2463	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2464	}
2465	pVCpu->hm.s.Event.fPending = false;
2466	}
2467
2468
2469	/**
2470	* Gets the guest's interrupt-shadow.
2471	*
2472	* @returns The guest's interrupt-shadow.
2473	* @param pVCpu The cross context virtual CPU structure.
2474	* @param pCtx Pointer to the guest-CPU context.
2475	*
2476	* @remarks No-long-jump zone!!!
2477	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2478	*/
2479	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2480	{
2481	/*
2482	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2483	* inhibit interrupts or clear any existing interrupt-inhibition.
2484	*/
2485	uint32_t uIntrState = 0;
2486	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2487	{
2488	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2489	{
2490	/*
2491	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2492	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2493	*/
2494	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2495	}
2496	else
2497	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2498	}
2499	return uIntrState;
2500	}
2501
2502
2503	/**
2504	* Sets the virtual interrupt intercept control in the VMCB which
2505	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
2506	* receive interrupts.
2507	*
2508	* @param pVmcb Pointer to the VM control block.
2509	*/
2510	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2511	{
2512	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
2513	{
2514	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1; /* A virtual interrupt is pending. */
2515	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0; /* Vector not necessary as we #VMEXIT for delivering the interrupt. */
2516	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
2517	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2518
2519	Log4(("Setting VINTR intercept\n"));
2520	}
2521	}
2522
2523
2524	#if 0
2525	/**
2526	* Clears the virtual interrupt intercept control in the VMCB as
2527	* we are figured the guest is unable process any interrupts
2528	* at this point of time.
2529	*
2530	* @param pVmcb Pointer to the VM control block.
2531	*/
2532	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
2533	{
2534	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
2535	{
2536	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
2537	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2538	Log4(("Clearing VINTR intercept\n"));
2539	}
2540	}
2541	#endif
2542
2543
2544	/**
2545	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2546	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
2547	* virtual NMIs.
2548	*
2549	* @param pVmcb Pointer to the VM control block.
2550	*/
2551	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
2552	{
2553	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
2554	{
2555	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
2556	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2557
2558	Log4(("Setting IRET intercept\n"));
2559	}
2560	}
2561
2562
2563	/**
2564	* Clears the IRET intercept control in the VMCB.
2565	*
2566	* @param pVmcb Pointer to the VM control block.
2567	*/
2568	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
2569	{
2570	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
2571	{
2572	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
2573	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2574
2575	Log4(("Clearing IRET intercept\n"));
2576	}
2577	}
2578
2579
2580	/**
2581	* Evaluates the event to be delivered to the guest and sets it as the pending
2582	* event.
2583	*
2584	* @param pVCpu The cross context virtual CPU structure.
2585	* @param pCtx Pointer to the guest-CPU context.
2586	*/
2587	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2588	{
2589	Assert(!pVCpu->hm.s.Event.fPending);
2590	Log4Func(("\n"));
2591
2592	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2593	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2594	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
2595	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2596
2597	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2598	APICUpdatePendingInterrupts(pVCpu);
2599
2600	SVMEVENT Event;
2601	Event.u = 0;
2602	/** @todo SMI. SMIs take priority over NMIs. */
2603	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2604	{
2605	if (fBlockNmi)
2606	hmR0SvmSetIretIntercept(pVmcb);
2607	else if (fIntShadow)
2608	hmR0SvmSetVirtIntrIntercept(pVmcb);
2609	else
2610	{
2611	Log4(("Pending NMI\n"));
2612
2613	Event.n.u1Valid = 1;
2614	Event.n.u8Vector = X86_XCPT_NMI;
2615	Event.n.u3Type = SVM_EVENT_NMI;
2616
2617	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2618	hmR0SvmSetIretIntercept(pVmcb);
2619	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2620	}
2621	}
2622	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
2623	&& !pVCpu->hm.s.fSingleInstruction)
2624	{
2625	/*
2626	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
2627	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
2628	*/
2629	if ( !fBlockInt
2630	&& !fIntShadow)
2631	{
2632	uint8_t u8Interrupt;
2633	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2634	if (RT_SUCCESS(rc))
2635	{
2636	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2637
2638	Event.n.u1Valid = 1;
2639	Event.n.u8Vector = u8Interrupt;
2640	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2641
2642	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2643	}
2644	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
2645	{
2646	/*
2647	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
2648	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
2649	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
2650	*/
2651	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
2652	}
2653	else
2654	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2655	}
2656	else
2657	hmR0SvmSetVirtIntrIntercept(pVmcb);
2658	}
2659	}
2660
2661
2662	/**
2663	* Injects any pending events into the guest if the guest is in a state to
2664	* receive them.
2665	*
2666	* @param pVCpu The cross context virtual CPU structure.
2667	* @param pCtx Pointer to the guest-CPU context.
2668	*/
2669	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2670	{
2671	Assert(!TRPMHasTrap(pVCpu));
2672	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2673
2674	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2675	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2676	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2677
2678	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2679	{
2680	SVMEVENT Event;
2681	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2682	Assert(Event.n.u1Valid);
2683	#ifdef VBOX_STRICT
2684	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2685	{
2686	Assert(!fBlockInt);
2687	Assert(!fIntShadow);
2688	}
2689	else if (Event.n.u3Type == SVM_EVENT_NMI)
2690	Assert(!fIntShadow);
2691	#endif
2692
2693	#ifndef RT_OS_WINDOWS
2694	/* Temporary test for returning guru, later make this function return void as before. */
2695	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
2696	&& Event.n.u8Vector == X86_XCPT_PF)
2697	{
2698	AssertRelease(pCtx->cr2 == pVCpu->hm.s.Event.GCPtrFaultAddress);
2699	}
2700	#endif
2701
2702	Log4(("Injecting pending HM event.\n"));
2703	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2704	pVCpu->hm.s.Event.fPending = false;
2705
2706	#ifdef VBOX_WITH_STATISTICS
2707	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2708	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2709	else
2710	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2711	#endif
2712	}
2713
2714	/* Update the guest interrupt shadow in the VMCB. */
2715	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2716	NOREF(fBlockInt);
2717	}
2718
2719
2720	/**
2721	* Reports world-switch error and dumps some useful debug info.
2722	*
2723	* @param pVM The cross context VM structure.
2724	* @param pVCpu The cross context virtual CPU structure.
2725	* @param rcVMRun The return code from VMRUN (or
2726	* VERR_SVM_INVALID_GUEST_STATE for invalid
2727	* guest-state).
2728	* @param pCtx Pointer to the guest-CPU context.
2729	*/
2730	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2731	{
2732	NOREF(pCtx);
2733	HMSVM_ASSERT_PREEMPT_SAFE();
2734	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2735
2736	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2737	{
2738	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
2739	#ifdef VBOX_STRICT
2740	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2741	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2742	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2743	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2744	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2745	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
2746	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
2747	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2748	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2749	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2750
2751	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2752	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2753	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2754
2755	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2756	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
2757	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2758	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
2759	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2760	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2761	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
2762	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2763	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
2764	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2765
2766	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2767	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2768	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2769	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2770	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2771	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2772	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2773	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2774	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2775	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2776	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2777	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2778	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2779	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2780	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2781	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2782	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2783
2784	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2785	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2786
2787	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2788	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2789	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2790	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2791	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2792	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2793	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2794	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2795	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2796	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2797	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2798	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2799	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2800	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2801	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2802	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2803	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2804	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2805	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2806	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2807
2808	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2809	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2810
2811	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2812	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2813	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2814	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2815
2816	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2817	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2818
2819	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2820	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2821	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2822	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2823
2824	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2825	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2826	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2827	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2828	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2829	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2830	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2831
2832	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2833	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2834	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2835	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2836
2837	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2838	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2839	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2840
2841	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2842	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2843	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2844	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2845	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2846	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2847	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2848	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2849	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2850	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2851	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2852	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2853	#endif /* VBOX_STRICT */
2854	}
2855	else
2856	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2857
2858	NOREF(pVmcb);
2859	}
2860
2861
2862	/**
2863	* Check per-VM and per-VCPU force flag actions that require us to go back to
2864	* ring-3 for one reason or another.
2865	*
2866	* @returns VBox status code (information status code included).
2867	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2868	* ring-3.
2869	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2870	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2871	* interrupts)
2872	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2873	* all EMTs to be in ring-3.
2874	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2875	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2876	* to the EM loop.
2877	*
2878	* @param pVM The cross context VM structure.
2879	* @param pVCpu The cross context virtual CPU structure.
2880	* @param pCtx Pointer to the guest-CPU context.
2881	*/
2882	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2883	{
2884	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2885
2886	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2887	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2888	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2889
2890	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2891	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2892	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2893	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2894	{
2895	/* Pending PGM C3 sync. */
2896	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2897	{
2898	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2899	if (rc != VINF_SUCCESS)
2900	{
2901	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2902	return rc;
2903	}
2904	}
2905
2906	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2907	/* -XXX- what was that about single stepping? */
2908	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2909	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2910	{
2911	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2912	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2913	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2914	return rc;
2915	}
2916
2917	/* Pending VM request packets, such as hardware interrupts. */
2918	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2919	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2920	{
2921	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2922	return VINF_EM_PENDING_REQUEST;
2923	}
2924
2925	/* Pending PGM pool flushes. */
2926	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2927	{
2928	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2929	return VINF_PGM_POOL_FLUSH_PENDING;
2930	}
2931
2932	/* Pending DMA requests. */
2933	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2934	{
2935	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2936	return VINF_EM_RAW_TO_R3;
2937	}
2938	}
2939
2940	return VINF_SUCCESS;
2941	}
2942
2943
2944	/**
2945	* Does the preparations before executing guest code in AMD-V.
2946	*
2947	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2948	* recompiler. We must be cautious what we do here regarding committing
2949	* guest-state information into the VMCB assuming we assuredly execute the guest
2950	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
2951	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2952	* that the recompiler can (and should) use them when it resumes guest
2953	* execution. Otherwise such operations must be done when we can no longer
2954	* exit to ring-3.
2955	*
2956	* @returns VBox status code (informational status codes included).
2957	* @retval VINF_SUCCESS if we can proceed with running the guest.
2958	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2959	*
2960	* @param pVM The cross context VM structure.
2961	* @param pVCpu The cross context virtual CPU structure.
2962	* @param pCtx Pointer to the guest-CPU context.
2963	* @param pSvmTransient Pointer to the SVM transient structure.
2964	*/
2965	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2966	{
2967	HMSVM_ASSERT_PREEMPT_SAFE();
2968
2969	/* Check force flag actions that might require us to go back to ring-3. */
2970	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2971	if (rc != VINF_SUCCESS)
2972	return rc;
2973
2974	if (TRPMHasTrap(pVCpu))
2975	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2976	else if (!pVCpu->hm.s.Event.fPending)
2977	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2978
2979	/*
2980	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
2981	* Just do it in software, see @bugref{8411}.
2982	* NB: If we could continue a task switch exit we wouldn't need to do this.
2983	*/
2984	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
2985	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
2986	return VINF_EM_RAW_INJECT_TRPM_EVENT;
2987
2988	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2989	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2990	#endif
2991
2992	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
2993	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2994	AssertRCReturn(rc, rc);
2995	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2996
2997	/*
2998	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2999	* so we can update it on the way back if the guest changed the TPR.
3000	*/
3001	if (pVCpu->hm.s.svm.fSyncVTpr)
3002	{
3003	if (pVM->hm.s.fTPRPatchingActive)
3004	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3005	else
3006	{
3007	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3008	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3009	}
3010	}
3011
3012	/*
3013	* No longjmps to ring-3 from this point on!!!
3014	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3015	* This also disables flushing of the R0-logger instance (if any).
3016	*/
3017	VMMRZCallRing3Disable(pVCpu);
3018
3019	/*
3020	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3021	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3022	*
3023	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3024	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3025	*
3026	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3027	* executing guest code.
3028	*/
3029	pSvmTransient->fEFlags = ASMIntDisableFlags();
3030	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3031	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3032	{
3033	ASMSetFlags(pSvmTransient->fEFlags);
3034	VMMRZCallRing3Enable(pVCpu);
3035	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3036	return VINF_EM_RAW_TO_R3;
3037	}
3038	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3039	{
3040	ASMSetFlags(pSvmTransient->fEFlags);
3041	VMMRZCallRing3Enable(pVCpu);
3042	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3043	return VINF_EM_RAW_INTERRUPT;
3044	}
3045
3046	/*
3047	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3048	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3049	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3050	*
3051	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3052	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3053	*/
3054	if (pVCpu->hm.s.Event.fPending)
3055	{
3056	SVMEVENT Event;
3057	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3058	if ( Event.n.u1Valid
3059	&& Event.n.u3Type == SVM_EVENT_NMI
3060	&& Event.n.u8Vector == X86_XCPT_NMI
3061	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3062	{
3063	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3064	}
3065	}
3066
3067	return VINF_SUCCESS;
3068	}
3069
3070
3071	/**
3072	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3073	* means there is no backing out to ring-3 or anywhere else at this
3074	* point.
3075	*
3076	* @param pVM The cross context VM structure.
3077	* @param pVCpu The cross context virtual CPU structure.
3078	* @param pCtx Pointer to the guest-CPU context.
3079	* @param pSvmTransient Pointer to the SVM transient structure.
3080	*
3081	* @remarks Called with preemption disabled.
3082	* @remarks No-long-jump zone!!!
3083	*/
3084	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3085	{
3086	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3087	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3088	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3089
3090	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3091	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3092
3093	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
3094
3095	if ( pVCpu->hm.s.fPreloadGuestFpu
3096	&& !CPUMIsGuestFPUStateActive(pVCpu))
3097	{
3098	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3099	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3100	}
3101
3102	/* Load the state shared between host and guest (FPU, debug). */
3103	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3104	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3105	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3106	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3107	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3108
3109	/* Setup TSC offsetting. */
3110	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3111	if ( pSvmTransient->fUpdateTscOffsetting
3112	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3113	{
3114	hmR0SvmUpdateTscOffsetting(pVM, pVCpu);
3115	pSvmTransient->fUpdateTscOffsetting = false;
3116	}
3117
3118	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3119	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3120	pVmcb->ctrl.u64VmcbCleanBits = 0;
3121
3122	/* Store status of the shared guest-host state at the time of VMRUN. */
3123	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3124	if (CPUMIsGuestInLongModeEx(pCtx))
3125	{
3126	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3127	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3128	}
3129	else
3130	#endif
3131	{
3132	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3133	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3134	}
3135	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3136
3137	/* Flush the appropriate tagged-TLB entries. */
3138	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3139	hmR0SvmFlushTaggedTlb(pVCpu);
3140	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3141
3142	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3143
3144	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3145	to start executing. */
3146
3147	/*
3148	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3149	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3150	*
3151	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3152	*/
3153	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3154	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
3155	{
3156	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3157	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3158	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3159	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3160	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3161	pSvmTransient->fRestoreTscAuxMsr = true;
3162	}
3163	else
3164	{
3165	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3166	pSvmTransient->fRestoreTscAuxMsr = false;
3167	}
3168
3169	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
3170	if (!(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
3171	pVmcb->ctrl.u64VmcbCleanBits = 0;
3172	}
3173
3174
3175	/**
3176	* Wrapper for running the guest code in AMD-V.
3177	*
3178	* @returns VBox strict status code.
3179	* @param pVM The cross context VM structure.
3180	* @param pVCpu The cross context virtual CPU structure.
3181	* @param pCtx Pointer to the guest-CPU context.
3182	*
3183	* @remarks No-long-jump zone!!!
3184	*/
3185	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3186	{
3187	/*
3188	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
3189	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3190	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3191	*/
3192	#ifdef VBOX_WITH_KERNEL_USING_XMM
3193	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3194	pVCpu->hm.s.svm.pfnVMRun);
3195	#else
3196	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3197	#endif
3198	}
3199
3200
3201	/**
3202	* Performs some essential restoration of state after running guest code in
3203	* AMD-V.
3204	*
3205	* @param pVM The cross context VM structure.
3206	* @param pVCpu The cross context virtual CPU structure.
3207	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3208	* out-of-sync. Make sure to update the required fields
3209	* before using them.
3210	* @param pSvmTransient Pointer to the SVM transient structure.
3211	* @param rcVMRun Return code of VMRUN.
3212	*
3213	* @remarks Called with interrupts disabled.
3214	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
3215	* unconditionally when it is safe to do so.
3216	*/
3217	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3218	{
3219	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3220
3221	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
3222	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
3223
3224	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3225	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3226
3227	/* TSC read must be done early for maximum accuracy. */
3228	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
3229	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
3230
3231	if (pSvmTransient->fRestoreTscAuxMsr)
3232	{
3233	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
3234	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
3235	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
3236	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3237	}
3238
3239	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3240	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3241	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3242
3243	Assert(!(ASMGetFlags() & X86_EFL_IF));
3244	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
3245	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3246
3247	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3248	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3249	{
3250	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3251	return;
3252	}
3253
3254	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3255	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
3256	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
3257	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3258
3259	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3260
3261	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
3262	{
3263	if (pVCpu->hm.s.svm.fSyncVTpr)
3264	{
3265	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3266	if ( pVM->hm.s.fTPRPatchingActive
3267	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3268	{
3269	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3270	AssertRC(rc);
3271	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3272	}
3273	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3274	{
3275	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3276	AssertRC(rc);
3277	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3278	}
3279	}
3280	}
3281	}
3282
3283
3284	/**
3285	* Runs the guest code using AMD-V.
3286	*
3287	* @returns VBox status code.
3288	* @param pVM The cross context VM structure.
3289	* @param pVCpu The cross context virtual CPU structure.
3290	* @param pCtx Pointer to the guest-CPU context.
3291	*/
3292	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3293	{
3294	SVMTRANSIENT SvmTransient;
3295	SvmTransient.fUpdateTscOffsetting = true;
3296	uint32_t cLoops = 0;
3297	int rc = VERR_INTERNAL_ERROR_5;
3298
3299	for (;; cLoops++)
3300	{
3301	Assert(!HMR0SuspendPending());
3302	HMSVM_ASSERT_CPU_SAFE();
3303
3304	/* Preparatory work for running guest code, this may force us to return
3305	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3306	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3307	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3308	if (rc != VINF_SUCCESS)
3309	break;
3310
3311	/*
3312	* No longjmps to ring-3 from this point on!!!
3313	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3314	* This also disables flushing of the R0-logger instance (if any).
3315	*/
3316	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3317	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3318
3319	/* Restore any residual host-state and save any bits shared between host
3320	and guest into the guest-CPU state. Re-enables interrupts! */
3321	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3322
3323	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3324	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3325	{
3326	if (rc == VINF_SUCCESS)
3327	rc = VERR_SVM_INVALID_GUEST_STATE;
3328	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3329	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3330	break;
3331	}
3332
3333	/* Handle the #VMEXIT. */
3334	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3335	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3336	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3337	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3338	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3339	if (rc != VINF_SUCCESS)
3340	break;
3341	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3342	{
3343	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3344	rc = VINF_EM_RAW_INTERRUPT;
3345	break;
3346	}
3347	}
3348
3349	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3350	return rc;
3351	}
3352
3353
3354	/**
3355	* Runs the guest code using AMD-V in single step mode.
3356	*
3357	* @returns VBox status code.
3358	* @param pVM The cross context VM structure.
3359	* @param pVCpu The cross context virtual CPU structure.
3360	* @param pCtx Pointer to the guest-CPU context.
3361	*/
3362	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3363	{
3364	SVMTRANSIENT SvmTransient;
3365	SvmTransient.fUpdateTscOffsetting = true;
3366	uint32_t cLoops = 0;
3367	int rc = VERR_INTERNAL_ERROR_5;
3368	uint16_t uCsStart = pCtx->cs.Sel;
3369	uint64_t uRipStart = pCtx->rip;
3370
3371	for (;; cLoops++)
3372	{
3373	Assert(!HMR0SuspendPending());
3374	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
3375	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
3376	(unsigned)RTMpCpuId(), cLoops));
3377
3378	/* Preparatory work for running guest code, this may force us to return
3379	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3380	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3381	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3382	if (rc != VINF_SUCCESS)
3383	break;
3384
3385	/*
3386	* No longjmps to ring-3 from this point on!!!
3387	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3388	* This also disables flushing of the R0-logger instance (if any).
3389	*/
3390	VMMRZCallRing3Disable(pVCpu);
3391	VMMRZCallRing3RemoveNotification(pVCpu);
3392	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3393
3394	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3395
3396	/*
3397	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3398	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3399	*/
3400	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3401	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3402	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3403	{
3404	if (rc == VINF_SUCCESS)
3405	rc = VERR_SVM_INVALID_GUEST_STATE;
3406	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3407	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3408	return rc;
3409	}
3410
3411	/* Handle the #VMEXIT. */
3412	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3413	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3414	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3415	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3416	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3417	if (rc != VINF_SUCCESS)
3418	break;
3419	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3420	{
3421	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3422	rc = VINF_EM_RAW_INTERRUPT;
3423	break;
3424	}
3425
3426	/*
3427	* Did the RIP change, if so, consider it a single step.
3428	* Otherwise, make sure one of the TFs gets set.
3429	*/
3430	if ( pCtx->rip != uRipStart
3431	\|\| pCtx->cs.Sel != uCsStart)
3432	{
3433	rc = VINF_EM_DBG_STEPPED;
3434	break;
3435	}
3436	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3437	}
3438
3439	/*
3440	* Clear the X86_EFL_TF if necessary.
3441	*/
3442	if (pVCpu->hm.s.fClearTrapFlag)
3443	{
3444	pVCpu->hm.s.fClearTrapFlag = false;
3445	pCtx->eflags.Bits.u1TF = 0;
3446	}
3447
3448	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3449	return rc;
3450	}
3451
3452
3453	/**
3454	* Runs the guest code using AMD-V.
3455	*
3456	* @returns Strict VBox status code.
3457	* @param pVM The cross context VM structure.
3458	* @param pVCpu The cross context virtual CPU structure.
3459	* @param pCtx Pointer to the guest-CPU context.
3460	*/
3461	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3462	{
3463	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3464	HMSVM_ASSERT_PREEMPT_SAFE();
3465	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3466
3467	int rc;
3468	if (!pVCpu->hm.s.fSingleInstruction)
3469	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx);
3470	else
3471	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx);
3472
3473	if (rc == VERR_EM_INTERPRETER)
3474	rc = VINF_EM_RAW_EMULATE_INSTR;
3475	else if (rc == VINF_EM_RESET)
3476	rc = VINF_EM_TRIPLE_FAULT;
3477
3478	/* Prepare to return to ring-3. This will remove longjmp notifications. */
3479	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3480	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3481	return rc;
3482	}
3483
3484
3485	/**
3486	* Handles a \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3487	*
3488	* @returns VBox status code (informational status codes included).
3489	* @param pVCpu The cross context virtual CPU structure.
3490	* @param pCtx Pointer to the guest-CPU context.
3491	* @param pSvmTransient Pointer to the SVM transient structure.
3492	*/
3493	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3494	{
3495	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
3496	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3497
3498	/*
3499	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
3500	* normal workloads (for some definition of "normal").
3501	*/
3502	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3503	switch (pSvmTransient->u64ExitCode)
3504	{
3505	case SVM_EXIT_NPF:
3506	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3507
3508	case SVM_EXIT_IOIO:
3509	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3510
3511	case SVM_EXIT_RDTSC:
3512	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3513
3514	case SVM_EXIT_RDTSCP:
3515	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3516
3517	case SVM_EXIT_CPUID:
3518	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3519
3520	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
3521	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3522
3523	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3524	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3525
3526	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3527	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
3528
3529	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
3530	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3531
3532	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3533	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3534
3535	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
3536	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
3537
3538	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3539	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
3540
3541	case SVM_EXIT_MONITOR:
3542	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3543
3544	case SVM_EXIT_MWAIT:
3545	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3546
3547	case SVM_EXIT_HLT:
3548	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3549
3550	case SVM_EXIT_READ_CR0:
3551	case SVM_EXIT_READ_CR3:
3552	case SVM_EXIT_READ_CR4:
3553	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3554
3555	case SVM_EXIT_WRITE_CR0:
3556	case SVM_EXIT_WRITE_CR3:
3557	case SVM_EXIT_WRITE_CR4:
3558	case SVM_EXIT_WRITE_CR8:
3559	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3560
3561	case SVM_EXIT_PAUSE:
3562	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
3563
3564	case SVM_EXIT_VMMCALL:
3565	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3566
3567	case SVM_EXIT_VINTR:
3568	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3569
3570	case SVM_EXIT_INTR:
3571	case SVM_EXIT_FERR_FREEZE:
3572	case SVM_EXIT_NMI:
3573	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3574
3575	case SVM_EXIT_MSR:
3576	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3577
3578	case SVM_EXIT_INVLPG:
3579	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3580
3581	case SVM_EXIT_WBINVD:
3582	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3583
3584	case SVM_EXIT_INVD:
3585	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3586
3587	case SVM_EXIT_RDPMC:
3588	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3589
3590	default:
3591	{
3592	switch (pSvmTransient->u64ExitCode)
3593	{
3594	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3595	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3596	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3597	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3598	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3599
3600	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3601	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3602	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3603	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3604	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3605
3606	case SVM_EXIT_XSETBV:
3607	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
3608
3609	case SVM_EXIT_TASK_SWITCH:
3610	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3611
3612	case SVM_EXIT_IRET:
3613	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
3614
3615	case SVM_EXIT_SHUTDOWN:
3616	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3617
3618	case SVM_EXIT_SMI:
3619	case SVM_EXIT_INIT:
3620	{
3621	/*
3622	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3623	* we want to know about it so log the exit code and bail.
3624	*/
3625	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3626	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3627	return VERR_SVM_UNEXPECTED_EXIT;
3628	}
3629
3630	#ifdef VBOX_WITH_NESTED_HWVIRT
3631	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
3632	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
3633	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
3634	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
3635	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
3636	#else
3637	case SVM_EXIT_CLGI:
3638	case SVM_EXIT_STGI:
3639	case SVM_EXIT_VMLOAD:
3640	case SVM_EXIT_VMSAVE:
3641	case SVM_EXIT_INVLPGA:
3642	#endif
3643	case SVM_EXIT_RSM:
3644	case SVM_EXIT_VMRUN:
3645	case SVM_EXIT_SKINIT:
3646	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3647
3648	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3649	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3650	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3651	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3652	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
3653	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3654	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3655	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
3656	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3657	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3658	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3659	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
3660	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
3661	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
3662	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
3663	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
3664	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
3665	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
3666	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
3667	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
3668	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
3669	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
3670	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
3671	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
3672	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
3673	{
3674	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3675	SVMEVENT Event;
3676	Event.u = 0;
3677	Event.n.u1Valid = 1;
3678	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3679	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3680
3681	switch (Event.n.u8Vector)
3682	{
3683	case X86_XCPT_DE:
3684	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3685	break;
3686
3687	case X86_XCPT_NP:
3688	Event.n.u1ErrorCodeValid = 1;
3689	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3690	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3691	break;
3692
3693	case X86_XCPT_SS:
3694	Event.n.u1ErrorCodeValid = 1;
3695	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3696	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3697	break;
3698
3699	case X86_XCPT_GP:
3700	Event.n.u1ErrorCodeValid = 1;
3701	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3702	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3703	break;
3704
3705	default:
3706	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3707	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3708	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3709	}
3710
3711	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3712	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3713	return VINF_SUCCESS;
3714	}
3715	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3716
3717	default:
3718	{
3719	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3720	pVCpu->hm.s.u32HMError = u32ExitCode;
3721	return VERR_SVM_UNKNOWN_EXIT;
3722	}
3723	}
3724	}
3725	}
3726	/* not reached */
3727	}
3728
3729
3730	#ifdef DEBUG
3731	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3732	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3733	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3734
3735	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3736	do \
3737	{ \
3738	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3739	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3740	} while (0)
3741
3742	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3743	do { \
3744	AssertPtr(pVCpu); \
3745	AssertPtr(pCtx); \
3746	AssertPtr(pSvmTransient); \
3747	Assert(ASMIntAreEnabled()); \
3748	HMSVM_ASSERT_PREEMPT_SAFE(); \
3749	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3750	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3751	HMSVM_ASSERT_PREEMPT_SAFE(); \
3752	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3753	HMSVM_ASSERT_PREEMPT_CPUID(); \
3754	} while (0)
3755	#else /* Release builds */
3756	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
3757	#endif
3758
3759
3760	/**
3761	* Worker for hmR0SvmInterpretInvlpg().
3762	*
3763	* @return VBox status code.
3764	* @param pVCpu The cross context virtual CPU structure.
3765	* @param pCpu Pointer to the disassembler state.
3766	* @param pCtx The guest CPU context.
3767	*/
3768	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
3769	{
3770	DISQPVPARAMVAL Param1;
3771	RTGCPTR GCPtrPage;
3772
3773	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3774	if (RT_FAILURE(rc))
3775	return VERR_EM_INTERPRETER;
3776
3777	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3778	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3779	{
3780	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3781	return VERR_EM_INTERPRETER;
3782
3783	GCPtrPage = Param1.val.val64;
3784	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
3785	rc = VBOXSTRICTRC_VAL(rc2);
3786	}
3787	else
3788	{
3789	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3790	rc = VERR_EM_INTERPRETER;
3791	}
3792
3793	return rc;
3794	}
3795
3796
3797	/**
3798	* Interprets INVLPG.
3799	*
3800	* @returns VBox status code.
3801	* @retval VINF_* Scheduling instructions.
3802	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3803	* @retval VERR_* Fatal errors.
3804	*
3805	* @param pVM The cross context VM structure.
3806	* @param pVCpu The cross context virtual CPU structure.
3807	* @param pCtx The guest CPU context.
3808	*
3809	* @remarks Updates the RIP if the instruction was executed successfully.
3810	*/
3811	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3812	{
3813	/* Only allow 32 & 64 bit code. */
3814	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3815	{
3816	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3817	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3818	if ( RT_SUCCESS(rc)
3819	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3820	{
3821	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
3822	if (RT_SUCCESS(rc))
3823	pCtx->rip += pDis->cbInstr;
3824	return rc;
3825	}
3826	else
3827	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3828	}
3829	return VERR_EM_INTERPRETER;
3830	}
3831
3832
3833	/**
3834	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3835	*
3836	* @param pVCpu The cross context virtual CPU structure.
3837	*/
3838	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3839	{
3840	SVMEVENT Event;
3841	Event.u = 0;
3842	Event.n.u1Valid = 1;
3843	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3844	Event.n.u8Vector = X86_XCPT_UD;
3845	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3846	}
3847
3848
3849	/**
3850	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3851	*
3852	* @param pVCpu The cross context virtual CPU structure.
3853	*/
3854	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3855	{
3856	SVMEVENT Event;
3857	Event.u = 0;
3858	Event.n.u1Valid = 1;
3859	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3860	Event.n.u8Vector = X86_XCPT_DB;
3861	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3862	}
3863
3864
3865	/**
3866	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3867	*
3868	* @param pVCpu The cross context virtual CPU structure.
3869	* @param pCtx Pointer to the guest-CPU context.
3870	* @param u32ErrCode The error-code for the page-fault.
3871	* @param uFaultAddress The page fault address (CR2).
3872	*
3873	* @remarks This updates the guest CR2 with @a uFaultAddress!
3874	*/
3875	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3876	{
3877	SVMEVENT Event;
3878	Event.u = 0;
3879	Event.n.u1Valid = 1;
3880	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3881	Event.n.u8Vector = X86_XCPT_PF;
3882	Event.n.u1ErrorCodeValid = 1;
3883	Event.n.u32ErrorCode = u32ErrCode;
3884
3885	/* Update CR2 of the guest. */
3886	if (pCtx->cr2 != uFaultAddress)
3887	{
3888	pCtx->cr2 = uFaultAddress;
3889	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3890	}
3891
3892	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3893	}
3894
3895
3896	/**
3897	* Sets a device-not-available (\#NM) exception as pending-for-injection into
3898	* the VM.
3899	*
3900	* @param pVCpu The cross context virtual CPU structure.
3901	*/
3902	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3903	{
3904	SVMEVENT Event;
3905	Event.u = 0;
3906	Event.n.u1Valid = 1;
3907	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3908	Event.n.u8Vector = X86_XCPT_NM;
3909	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3910	}
3911
3912
3913	/**
3914	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3915	*
3916	* @param pVCpu The cross context virtual CPU structure.
3917	*/
3918	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3919	{
3920	SVMEVENT Event;
3921	Event.u = 0;
3922	Event.n.u1Valid = 1;
3923	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3924	Event.n.u8Vector = X86_XCPT_MF;
3925	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3926	}
3927
3928
3929	/**
3930	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3931	*
3932	* @param pVCpu The cross context virtual CPU structure.
3933	*/
3934	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3935	{
3936	SVMEVENT Event;
3937	Event.u = 0;
3938	Event.n.u1Valid = 1;
3939	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3940	Event.n.u8Vector = X86_XCPT_DF;
3941	Event.n.u1ErrorCodeValid = 1;
3942	Event.n.u32ErrorCode = 0;
3943	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3944	}
3945
3946	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
3947	/**
3948	* Gets the IEM exception flags for the specified SVM event.
3949	*
3950	* @returns The IEM exception flags.
3951	* @param pEvent Pointer to the SVM event.
3952	*
3953	* @remarks This function currently only constructs flags required for
3954	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
3955	* and CR2 aspects of an exception are not included).
3956	*/
3957	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
3958	{
3959	uint8_t const uEventType = pEvent->n.u3Type;
3960	uint32_t fIemXcptFlags;
3961	switch (uEventType)
3962	{
3963	case SVM_EVENT_EXCEPTION:
3964	/*
3965	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
3966	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
3967	*/
3968	if (pEvent->n.u8Vector == X86_XCPT_BP)
3969	{
3970	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
3971	break;
3972	}
3973	if (pEvent->n.u8Vector == X86_XCPT_OF)
3974	{
3975	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
3976	break;
3977	}
3978	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
3979	/* fall thru */
3980	case SVM_EVENT_NMI:
3981	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
3982	break;
3983
3984	case SVM_EVENT_EXTERNAL_IRQ:
3985	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
3986	break;
3987
3988	case SVM_EVENT_SOFTWARE_INT:
3989	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
3990	break;
3991
3992	default:
3993	fIemXcptFlags = 0;
3994	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
3995	break;
3996	}
3997	return fIemXcptFlags;
3998	}
3999
4000	#else
4001	/**
4002	* Determines if an exception is a contributory exception.
4003	*
4004	* Contributory exceptions are ones which can cause double-faults unless the
4005	* original exception was a benign exception. Page-fault is intentionally not
4006	* included here as it's a conditional contributory exception.
4007	*
4008	* @returns true if the exception is contributory, false otherwise.
4009	* @param uVector The exception vector.
4010	*/
4011	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
4012	{
4013	switch (uVector)
4014	{
4015	case X86_XCPT_GP:
4016	case X86_XCPT_SS:
4017	case X86_XCPT_NP:
4018	case X86_XCPT_TS:
4019	case X86_XCPT_DE:
4020	return true;
4021	default:
4022	break;
4023	}
4024	return false;
4025	}
4026	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
4027
4028
4029	/**
4030	* Handle a condition that occurred while delivering an event through the guest
4031	* IDT.
4032	*
4033	* @returns VBox status code (informational error codes included).
4034	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
4035	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
4036	* continue execution of the guest which will delivery the \#DF.
4037	* @retval VINF_EM_RESET if we detected a triple-fault condition.
4038	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
4039	*
4040	* @param pVCpu The cross context virtual CPU structure.
4041	* @param pCtx Pointer to the guest-CPU context.
4042	* @param pSvmTransient Pointer to the SVM transient structure.
4043	*
4044	* @remarks No-long-jump zone!!!
4045	*/
4046	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4047	{
4048	int rc = VINF_SUCCESS;
4049	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4050
4051	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
4052	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
4053	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
4054
4055	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
4056	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
4057	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
4058	{
4059	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
4060	IEMXCPTRAISE enmRaise;
4061	IEMXCPTRAISEINFO fRaiseInfo;
4062	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
4063	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4064	if (fExitIsHwXcpt)
4065	{
4066	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
4067	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
4068	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
4069	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
4070	}
4071	else
4072	{
4073	/*
4074	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
4075	* end up here.
4076	*
4077	* If the event was:
4078	* - a software interrupt, we can re-execute the instruction which will regenerate
4079	* the event.
4080	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
4081	* - a hardware exception or external interrupt, we re-inject it.
4082	*/
4083	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
4084	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4085	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
4086	else
4087	enmRaise = IEMXCPTRAISE_PREV_EVENT;
4088	}
4089
4090	switch (enmRaise)
4091	{
4092	case IEMXCPTRAISE_CURRENT_XCPT:
4093	case IEMXCPTRAISE_PREV_EVENT:
4094	{
4095	/* For software interrupts, we shall re-execute the instruction. */
4096	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
4097	{
4098	RTGCUINTPTR GCPtrFaultAddress = 0;
4099
4100	/* If we are re-injecting an NMI, clear NMI blocking. */
4101	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4102	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4103
4104	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
4105	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
4106	pSvmTransient->fVectoringPF = true;
4107	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
4108	&& uIdtVector == X86_XCPT_PF)
4109	{
4110	/*
4111	* If the previous exception was a #PF, we need to recover the CR2 value.
4112	* This can't happen with shadow paging.
4113	*/
4114	GCPtrFaultAddress = pCtx->cr2;
4115	}
4116
4117	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4118	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4119	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
4120
4121	/** @todo r=michaln: The comment makes no sense with nested paging on! */
4122	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF,
4123	see hmR0SvmExitXcptPF(). */
4124	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
4125	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
4126	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
4127	}
4128	break;
4129	}
4130
4131	case IEMXCPTRAISE_REEXEC_INSTR:
4132	{
4133	Assert(rc == VINF_SUCCESS);
4134	break;
4135	}
4136
4137	case IEMXCPTRAISE_DOUBLE_FAULT:
4138	{
4139	/*
4140	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
4141	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
4142	*/
4143	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
4144	{
4145	pSvmTransient->fVectoringDoublePF = true;
4146	Assert(rc == VINF_SUCCESS);
4147	}
4148	else
4149	{
4150	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4151	hmR0SvmSetPendingXcptDF(pVCpu);
4152	rc = VINF_HM_DOUBLE_FAULT;
4153	}
4154	break;
4155	}
4156
4157	case IEMXCPTRAISE_TRIPLE_FAULT:
4158	{
4159	rc = VINF_EM_RESET;
4160	break;
4161	}
4162
4163	case IEMXCPTRAISE_CPU_HANG:
4164	{
4165	rc = VERR_EM_GUEST_CPU_HANG;
4166	break;
4167	}
4168
4169	default:
4170	{
4171	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4172	rc = VERR_SVM_IPE_2;
4173	break;
4174	}
4175	}
4176	#else
4177	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4178
4179	typedef enum
4180	{
4181	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4182	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4183	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4184	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
4185	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
4186	} SVMREFLECTXCPT;
4187
4188	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
4189	bool fReflectingNmi = false;
4190	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
4191	{
4192	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
4193	{
4194	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4195
4196	#ifdef VBOX_STRICT
4197	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
4198	&& uExitVector == X86_XCPT_PF)
4199	{
4200	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
4201	}
4202	#endif
4203
4204	if ( uIdtVector == X86_XCPT_BP
4205	\|\| uIdtVector == X86_XCPT_OF)
4206	{
4207	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
4208	}
4209	else if ( uExitVector == X86_XCPT_PF
4210	&& uIdtVector == X86_XCPT_PF)
4211	{
4212	pSvmTransient->fVectoringDoublePF = true;
4213	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
4214	}
4215	else if ( uExitVector == X86_XCPT_AC
4216	&& uIdtVector == X86_XCPT_AC)
4217	{
4218	enmReflect = SVMREFLECTXCPT_HANG;
4219	Log4(("IDT: Nested #AC - Bad guest\n"));
4220	}
4221	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
4222	&& hmR0SvmIsContributoryXcpt(uExitVector)
4223	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
4224	\|\| uIdtVector == X86_XCPT_PF))
4225	{
4226	enmReflect = SVMREFLECTXCPT_DF;
4227	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
4228	uIdtVector, uExitVector));
4229	}
4230	else if (uIdtVector == X86_XCPT_DF)
4231	{
4232	enmReflect = SVMREFLECTXCPT_TF;
4233	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
4234	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
4235	}
4236	else
4237	enmReflect = SVMREFLECTXCPT_XCPT;
4238	}
4239	else
4240	{
4241	/*
4242	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
4243	* exception to the guest after handling the #VMEXIT.
4244	*/
4245	enmReflect = SVMREFLECTXCPT_XCPT;
4246	}
4247	}
4248	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
4249	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4250	{
4251	enmReflect = SVMREFLECTXCPT_XCPT;
4252	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
4253
4254	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
4255	{
4256	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4257	if (uExitVector == X86_XCPT_PF)
4258	{
4259	pSvmTransient->fVectoringPF = true;
4260	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
4261	}
4262	}
4263	}
4264	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
4265
4266	switch (enmReflect)
4267	{
4268	case SVMREFLECTXCPT_XCPT:
4269	{
4270	/* If we are re-injecting the NMI, clear NMI blocking. */
4271	if (fReflectingNmi)
4272	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4273
4274	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4275	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4276	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
4277
4278	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
4279	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
4280	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4281	break;
4282	}
4283
4284	case SVMREFLECTXCPT_DF:
4285	{
4286	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4287	hmR0SvmSetPendingXcptDF(pVCpu);
4288	rc = VINF_HM_DOUBLE_FAULT;
4289	break;
4290	}
4291
4292	case SVMREFLECTXCPT_TF:
4293	{
4294	rc = VINF_EM_RESET;
4295	break;
4296	}
4297
4298	case SVMREFLECTXCPT_HANG:
4299	{
4300	rc = VERR_EM_GUEST_CPU_HANG;
4301	break;
4302	}
4303
4304	default:
4305	Assert(rc == VINF_SUCCESS);
4306	break;
4307	}
4308	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
4309	}
4310	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
4311	NOREF(pCtx);
4312	return rc;
4313	}
4314
4315
4316	/**
4317	* Updates interrupt shadow for the current RIP.
4318	*/
4319	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
4320	do { \
4321	/* Update interrupt shadow. */ \
4322	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
4323	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
4324	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
4325	} while (0)
4326
4327
4328	/**
4329	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
4330	* supported, otherwise advances the RIP by the number of bytes specified in
4331	* @a cb.
4332	*
4333	* @param pVCpu The cross context virtual CPU structure.
4334	* @param pCtx Pointer to the guest-CPU context.
4335	* @param cb RIP increment value in bytes.
4336	*
4337	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
4338	* when NRIP_SAVE is supported by the CPU, otherwise use
4339	* hmR0SvmAdvanceRipDumb!
4340	*/
4341	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4342	{
4343	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4344	{
4345	PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4346	Assert(pVmcb->ctrl.u64NextRIP);
4347	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
4348	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4349	}
4350	else
4351	pCtx->rip += cb;
4352
4353	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4354	}
4355
4356	/* Currently only used by nested hw.virt instructions, so ifdef'd as such, otherwise compilers start whining. */
4357	#ifdef VBOX_WITH_NESTED_HWVIRT
4358	/**
4359	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
4360	* feature. Otherwise, returns the value in @a cbLikely.
4361	*
4362	* @param pVCpu The cross context virtual CPU structure.
4363	* @param pCtx Pointer to the guest-CPU context.
4364	* @param cbLikely The likely instruction length.
4365	*/
4366	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
4367	{
4368	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
4369	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4370	{
4371	PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4372	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
4373	Assert(cbInstr == cbLikely);
4374	return cbInstr;
4375	}
4376	return cbLikely;
4377	}
4378	#endif
4379
4380	/**
4381	* Advances the guest RIP by the number of bytes specified in @a cb. This does
4382	* not make use of any hardware features to determine the instruction length.
4383	*
4384	* @param pVCpu The cross context virtual CPU structure.
4385	* @param pCtx Pointer to the guest-CPU context.
4386	* @param cb RIP increment value in bytes.
4387	*/
4388	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4389	{
4390	pCtx->rip += cb;
4391	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4392	}
4393	#undef HMSVM_UPDATE_INTR_SHADOW
4394
4395
4396	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4397	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
4398	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4399
4400	/** @name \#VMEXIT handlers.
4401	* @{
4402	*/
4403
4404	/**
4405	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
4406	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
4407	*/
4408	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4409	{
4410	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4411
4412	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
4413	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
4414	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
4415	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
4416
4417	/*
4418	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
4419	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
4420	* interrupt it is until the host actually take the interrupt.
4421	*
4422	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
4423	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
4424	*/
4425	return VINF_EM_RAW_INTERRUPT;
4426	}
4427
4428
4429	/**
4430	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
4431	*/
4432	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4433	{
4434	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4435
4436	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4437	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
4438	int rc = VINF_SUCCESS;
4439	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4440	return rc;
4441	}
4442
4443
4444	/**
4445	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
4446	*/
4447	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4448	{
4449	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4450
4451	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4452	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
4453	int rc = VINF_SUCCESS;
4454	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4455	return rc;
4456	}
4457
4458
4459	/**
4460	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
4461	*/
4462	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4463	{
4464	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4465	PVM pVM = pVCpu->CTX_SUFF(pVM);
4466	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4467	if (RT_LIKELY(rc == VINF_SUCCESS))
4468	{
4469	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4470	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4471	}
4472	else
4473	{
4474	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4475	rc = VERR_EM_INTERPRETER;
4476	}
4477	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
4478	return rc;
4479	}
4480
4481
4482	/**
4483	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
4484	*/
4485	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4486	{
4487	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4488	PVM pVM = pVCpu->CTX_SUFF(pVM);
4489	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4490	if (RT_LIKELY(rc == VINF_SUCCESS))
4491	{
4492	pSvmTransient->fUpdateTscOffsetting = true;
4493	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4494	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4495	}
4496	else
4497	{
4498	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
4499	rc = VERR_EM_INTERPRETER;
4500	}
4501	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
4502	return rc;
4503	}
4504
4505
4506	/**
4507	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
4508	*/
4509	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4510	{
4511	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4512	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4513	if (RT_LIKELY(rc == VINF_SUCCESS))
4514	{
4515	pSvmTransient->fUpdateTscOffsetting = true;
4516	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4517	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4518	}
4519	else
4520	{
4521	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
4522	rc = VERR_EM_INTERPRETER;
4523	}
4524	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
4525	return rc;
4526	}
4527
4528
4529	/**
4530	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
4531	*/
4532	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4533	{
4534	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4535	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4536	if (RT_LIKELY(rc == VINF_SUCCESS))
4537	{
4538	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4539	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4540	}
4541	else
4542	{
4543	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4544	rc = VERR_EM_INTERPRETER;
4545	}
4546	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4547	return rc;
4548	}
4549
4550
4551	/**
4552	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
4553	*/
4554	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4555	{
4556	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4557	PVM pVM = pVCpu->CTX_SUFF(pVM);
4558	Assert(!pVM->hm.s.fNestedPaging);
4559
4560	/** @todo Decode Assist. */
4561	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
4562	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4563	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
4564	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4565	return rc;
4566	}
4567
4568
4569	/**
4570	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
4571	*/
4572	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4573	{
4574	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4575
4576	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
4577	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4578	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4579	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4580	if (rc != VINF_SUCCESS)
4581	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
4582	return rc;
4583	}
4584
4585
4586	/**
4587	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
4588	*/
4589	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4590	{
4591	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4592	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4593	if (RT_LIKELY(rc == VINF_SUCCESS))
4594	{
4595	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4596	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4597	}
4598	else
4599	{
4600	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4601	rc = VERR_EM_INTERPRETER;
4602	}
4603	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4604	return rc;
4605	}
4606
4607
4608	/**
4609	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
4610	*/
4611	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4612	{
4613	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4614	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4615	int rc = VBOXSTRICTRC_VAL(rc2);
4616	if ( rc == VINF_EM_HALT
4617	\|\| rc == VINF_SUCCESS)
4618	{
4619	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4620
4621	if ( rc == VINF_EM_HALT
4622	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
4623	{
4624	rc = VINF_SUCCESS;
4625	}
4626	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4627	}
4628	else
4629	{
4630	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4631	rc = VERR_EM_INTERPRETER;
4632	}
4633	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
4634	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4635	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4636	return rc;
4637	}
4638
4639
4640	/**
4641	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
4642	* \#VMEXIT.
4643	*/
4644	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4645	{
4646	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4647	return VINF_EM_RESET;
4648	}
4649
4650
4651	/**
4652	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
4653	*/
4654	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4655	{
4656	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4657
4658	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4659
4660	/** @todo Decode Assist. */
4661	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4662	int rc = VBOXSTRICTRC_VAL(rc2);
4663	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4664	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4665	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4666	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4667	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4668	return rc;
4669	}
4670
4671
4672	/**
4673	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
4674	*/
4675	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4676	{
4677	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4678
4679	/** @todo Decode Assist. */
4680	VBOXSTRICTRC rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
4681	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
4682	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
4683	rcStrict = VERR_EM_INTERPRETER;
4684	if (rcStrict == VINF_SUCCESS)
4685	{
4686	/* RIP has been updated by EMInterpretInstruction(). */
4687	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4688	switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4689	{
4690	case 0: /* CR0. */
4691	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4692	break;
4693
4694	case 3: /* CR3. */
4695	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4696	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4697	break;
4698
4699	case 4: /* CR4. */
4700	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4701	break;
4702
4703	case 8: /* CR8 (TPR). */
4704	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4705	break;
4706
4707	default:
4708	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
4709	pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4710	break;
4711	}
4712	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4713	}
4714	else
4715	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
4716	return VBOXSTRICTRC_TODO(rcStrict);
4717	}
4718
4719
4720	/**
4721	* \#VMEXIT handler for instructions that result in a \#UD exception delivered
4722	* to the guest.
4723	*/
4724	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4725	{
4726	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4727	hmR0SvmSetPendingXcptUD(pVCpu);
4728	return VINF_SUCCESS;
4729	}
4730
4731
4732	/**
4733	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
4734	* \#VMEXIT.
4735	*/
4736	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4737	{
4738	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4739	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4740	PVM pVM = pVCpu->CTX_SUFF(pVM);
4741
4742	int rc;
4743	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4744	{
4745	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4746
4747	/* Handle TPR patching; intercepted LSTAR write. */
4748	if ( pVM->hm.s.fTPRPatchingActive
4749	&& pCtx->ecx == MSR_K8_LSTAR)
4750	{
4751	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4752	{
4753	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4754	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
4755	AssertRC(rc2);
4756	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4757	}
4758	rc = VINF_SUCCESS;
4759	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4760	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4761	return rc;
4762	}
4763
4764	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4765	{
4766	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4767	if (RT_LIKELY(rc == VINF_SUCCESS))
4768	{
4769	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4770	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4771	}
4772	else
4773	AssertMsg( rc == VERR_EM_INTERPRETER
4774	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4775	}
4776	else
4777	{
4778	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4779	if (RT_LIKELY(rc == VINF_SUCCESS))
4780	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
4781	else
4782	AssertMsg( rc == VERR_EM_INTERPRETER
4783	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4784	}
4785
4786	if (rc == VINF_SUCCESS)
4787	{
4788	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4789	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4790	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4791	{
4792	/*
4793	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4794	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4795	* EMInterpretWrmsr() changes it.
4796	*/
4797	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4798	}
4799	else if (pCtx->ecx == MSR_K6_EFER)
4800	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4801	else if (pCtx->ecx == MSR_IA32_TSC)
4802	pSvmTransient->fUpdateTscOffsetting = true;
4803	}
4804	}
4805	else
4806	{
4807	/* MSR Read access. */
4808	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4809	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4810
4811	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4812	{
4813	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4814	if (RT_LIKELY(rc == VINF_SUCCESS))
4815	{
4816	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4817	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4818	}
4819	else
4820	AssertMsg( rc == VERR_EM_INTERPRETER
4821	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4822	}
4823	else
4824	{
4825	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4826	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4827	{
4828	AssertMsg( rc == VERR_EM_INTERPRETER
4829	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4830	}
4831	/* RIP updated by EMInterpretInstruction(). */
4832	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4833	}
4834	}
4835
4836	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4837	return rc;
4838	}
4839
4840
4841	/**
4842	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
4843	*/
4844	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4845	{
4846	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4847	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4848
4849	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
4850	if (pSvmTransient->fWasGuestDebugStateActive)
4851	{
4852	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
4853	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
4854	return VERR_SVM_UNEXPECTED_EXIT;
4855	}
4856
4857	/*
4858	* Lazy DR0-3 loading.
4859	*/
4860	if (!pSvmTransient->fWasHyperDebugStateActive)
4861	{
4862	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4863	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4864
4865	/* Don't intercept DRx read and writes. */
4866	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4867	pVmcb->ctrl.u16InterceptRdDRx = 0;
4868	pVmcb->ctrl.u16InterceptWrDRx = 0;
4869	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4870
4871	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4872	VMMRZCallRing3Disable(pVCpu);
4873	HM_DISABLE_PREEMPT();
4874
4875	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4876	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4877	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4878
4879	HM_RESTORE_PREEMPT();
4880	VMMRZCallRing3Enable(pVCpu);
4881
4882	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4883	return VINF_SUCCESS;
4884	}
4885
4886	/*
4887	* Interpret the read/writing of DRx.
4888	*/
4889	/** @todo Decode assist. */
4890	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4891	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4892	if (RT_LIKELY(rc == VINF_SUCCESS))
4893	{
4894	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4895	/** @todo CPUM should set this flag! */
4896	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4897	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4898	}
4899	else
4900	Assert(rc == VERR_EM_INTERPRETER);
4901	return VBOXSTRICTRC_TODO(rc);
4902	}
4903
4904
4905	/**
4906	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
4907	*/
4908	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4909	{
4910	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4911	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4912	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4913	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4914	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4915	return rc;
4916	}
4917
4918
4919	/**
4920	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
4921	*/
4922	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4923	{
4924	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4925
4926	/** @todo decode assists... */
4927	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
4928	if (rcStrict == VINF_IEM_RAISED_XCPT)
4929	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4930
4931	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4932	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
4933	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
4934
4935	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4936	return VBOXSTRICTRC_TODO(rcStrict);
4937	}
4938
4939
4940	/**
4941	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
4942	*/
4943	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4944	{
4945	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4946
4947	/* I/O operation lookup arrays. */
4948	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4949	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4950	the result (in AL/AX/EAX). */
4951	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4952
4953	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4954	PVM pVM = pVCpu->CTX_SUFF(pVM);
4955
4956	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4957	SVMIOIOEXITINFO IoExitInfo;
4958	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4959	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4960	uint32_t cbValue = s_aIOSize[uIOWidth];
4961	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4962
4963	if (RT_UNLIKELY(!cbValue))
4964	{
4965	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4966	return VERR_EM_INTERPRETER;
4967	}
4968
4969	VBOXSTRICTRC rcStrict;
4970	bool fUpdateRipAlready = false;
4971	if (IoExitInfo.n.u1STR)
4972	{
4973	#ifdef VBOX_WITH_2ND_IEM_STEP
4974	/* INS/OUTS - I/O String instruction. */
4975	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
4976	* in EXITINFO1? Investigate once this thing is up and running. */
4977	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
4978	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
4979	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
4980	static IEMMODE const s_aenmAddrMode[8] =
4981	{
4982	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
4983	};
4984	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
4985	if (enmAddrMode != (IEMMODE)-1)
4986	{
4987	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
4988	if (cbInstr <= 15 && cbInstr >= 1)
4989	{
4990	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
4991	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4992	{
4993	/* Don't know exactly how to detect whether u3SEG is valid, currently
4994	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
4995	2384 Opterons when only checking NRIP. */
4996	if ( (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4997	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
4998	{
4999	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
5000	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
5001	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
5002	IoExitInfo.n.u3SEG, true /fIoChecked/);
5003	}
5004	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
5005	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
5006	X86_SREG_DS, true /fIoChecked/);
5007	else
5008	rcStrict = IEMExecOne(pVCpu);
5009	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
5010	}
5011	else
5012	{
5013	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
5014	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
5015	true /fIoChecked/);
5016	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
5017	}
5018	}
5019	else
5020	{
5021	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
5022	rcStrict = IEMExecOne(pVCpu);
5023	}
5024	}
5025	else
5026	{
5027	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
5028	rcStrict = IEMExecOne(pVCpu);
5029	}
5030	fUpdateRipAlready = true;
5031
5032	#else
5033	/* INS/OUTS - I/O String instruction. */
5034	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
5035
5036	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
5037	* in EXITINFO1? Investigate once this thing is up and running. */
5038
5039	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
5040	if (rcStrict == VINF_SUCCESS)
5041	{
5042	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
5043	{
5044	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
5045	(DISCPUMODE)pDis->uAddrMode, cbValue);
5046	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
5047	}
5048	else
5049	{
5050	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
5051	(DISCPUMODE)pDis->uAddrMode, cbValue);
5052	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
5053	}
5054	}
5055	else
5056	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
5057	#endif
5058	}
5059	else
5060	{
5061	/* IN/OUT - I/O instruction. */
5062	Assert(!IoExitInfo.n.u1REP);
5063
5064	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
5065	{
5066	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
5067	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
5068	}
5069	else
5070	{
5071	uint32_t u32Val = 0;
5072	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
5073	if (IOM_SUCCESS(rcStrict))
5074	{
5075	/* Save result of I/O IN instr. in AL/AX/EAX. */
5076	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
5077	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
5078	}
5079	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
5080	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
5081
5082	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
5083	}
5084	}
5085
5086	if (IOM_SUCCESS(rcStrict))
5087	{
5088	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
5089	if (!fUpdateRipAlready)
5090	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
5091
5092	/*
5093	* If any I/O breakpoints are armed, we need to check if one triggered
5094	* and take appropriate action.
5095	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
5096	*/
5097	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
5098	* execution engines about whether hyper BPs and such are pending. */
5099	uint32_t const uDr7 = pCtx->dr[7];
5100	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
5101	&& X86_DR7_ANY_RW_IO(uDr7)
5102	&& (pCtx->cr4 & X86_CR4_DE))
5103	\|\| DBGFBpIsHwIoArmed(pVM)))
5104	{
5105	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5106	VMMRZCallRing3Disable(pVCpu);
5107	HM_DISABLE_PREEMPT();
5108
5109	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
5110	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
5111
5112	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
5113	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
5114	{
5115	/* Raise #DB. */
5116	pVmcb->guest.u64DR6 = pCtx->dr[6];
5117	pVmcb->guest.u64DR7 = pCtx->dr[7];
5118	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5119	hmR0SvmSetPendingXcptDB(pVCpu);
5120	}
5121	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
5122	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
5123	else if ( rcStrict2 != VINF_SUCCESS
5124	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
5125	rcStrict = rcStrict2;
5126	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
5127
5128	HM_RESTORE_PREEMPT();
5129	VMMRZCallRing3Enable(pVCpu);
5130	}
5131
5132	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5133	}
5134
5135	#ifdef VBOX_STRICT
5136	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
5137	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
5138	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
5139	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
5140	else
5141	{
5142	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
5143	* statuses, that the VMM device and some others may return. See
5144	* IOM_SUCCESS() for guidance. */
5145	AssertMsg( RT_FAILURE(rcStrict)
5146	\|\| rcStrict == VINF_SUCCESS
5147	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
5148	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
5149	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
5150	\|\| rcStrict == VINF_EM_RAW_TO_R3
5151	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
5152	}
5153	#endif
5154	return VBOXSTRICTRC_TODO(rcStrict);
5155	}
5156
5157
5158	/**
5159	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
5160	*/
5161	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5162	{
5163	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5164	PVM pVM = pVCpu->CTX_SUFF(pVM);
5165	Assert(pVM->hm.s.fNestedPaging);
5166
5167	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5168
5169	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
5170	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5171	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5172	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
5173
5174	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
5175
5176	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5177	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
5178	if ( pVM->hm.s.fTprPatchingAllowed
5179	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
5180	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
5181	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
5182	&& !CPUMIsGuestInLongModeEx(pCtx)
5183	&& !CPUMGetGuestCPL(pVCpu)
5184	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5185	{
5186	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
5187	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5188
5189	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
5190	{
5191	/* Only attempt to patch the instruction once. */
5192	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5193	if (!pPatch)
5194	return VINF_EM_HM_PATCH_TPR_INSTR;
5195	}
5196	}
5197	#endif
5198
5199	/*
5200	* Determine the nested paging mode.
5201	*/
5202	PGMMODE enmNestedPagingMode;
5203	#if HC_ARCH_BITS == 32
5204	if (CPUMIsGuestInLongModeEx(pCtx))
5205	enmNestedPagingMode = PGMMODE_AMD64_NX;
5206	else
5207	#endif
5208	enmNestedPagingMode = PGMGetHostMode(pVM);
5209
5210	/*
5211	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
5212	*/
5213	int rc;
5214	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
5215	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
5216	{
5217	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
5218	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
5219	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5220	{
5221	/** @todo this should return VINF_EM_RAW_INJECT_TRPM_EVENT. */
5222	return VERR_EM_INTERPRETER;
5223	}
5224
5225	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
5226	u32ErrCode);
5227	rc = VBOXSTRICTRC_VAL(rc2);
5228
5229	/*
5230	* If we succeed, resume guest execution.
5231	* If we fail in interpreting the instruction because we couldn't get the guest physical address
5232	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
5233	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
5234	* weird case. See @bugref{6043}.
5235	*/
5236	if ( rc == VINF_SUCCESS
5237	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5238	\|\| rc == VERR_PAGE_NOT_PRESENT)
5239	{
5240	/* Successfully handled MMIO operation. */
5241	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5242	rc = VINF_SUCCESS;
5243	}
5244	return rc;
5245	}
5246
5247	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
5248	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
5249	TRPMResetTrap(pVCpu);
5250
5251	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
5252
5253	/*
5254	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
5255	*/
5256	if ( rc == VINF_SUCCESS
5257	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5258	\|\| rc == VERR_PAGE_NOT_PRESENT)
5259	{
5260	/* We've successfully synced our shadow page tables. */
5261	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5262	rc = VINF_SUCCESS;
5263	}
5264
5265	return rc;
5266	}
5267
5268
5269	/**
5270	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
5271	* \#VMEXIT.
5272	*/
5273	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5274	{
5275	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5276
5277	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5278	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
5279	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;
5280
5281	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
5282	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
5283	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
5284
5285	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5286	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
5287	return VINF_SUCCESS;
5288	}
5289
5290
5291	/**
5292	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
5293	* \#VMEXIT.
5294	*/
5295	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5296	{
5297	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5298
5299	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5300
5301	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
5302	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5303	#endif
5304
5305	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
5306	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
5307	{
5308	/*
5309	* AMD-V provides us with the exception which caused the TS; we collect
5310	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
5311	*/
5312	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
5313	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5314	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5315	}
5316
5317	/** @todo Emulate task switch someday, currently just going back to ring-3 for
5318	* emulation. */
5319	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5320	return VERR_EM_INTERPRETER;
5321	}
5322
5323
5324	/**
5325	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5326	*/
5327	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5328	{
5329	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5330	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
5331
5332	bool fRipUpdated;
5333	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
5334	if (RT_SUCCESS(rcStrict))
5335	{
5336	if (!fRipUpdated)
5337	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
5338
5339	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
5340	we would need to reload the guest changed bits here before VM-entry. */
5341	return VBOXSTRICTRC_VAL(rcStrict);
5342	}
5343
5344	hmR0SvmSetPendingXcptUD(pVCpu);
5345	return VINF_SUCCESS;
5346	}
5347
5348
5349	/**
5350	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5351	*/
5352	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5353	{
5354	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5355	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
5356	return VINF_EM_RAW_INTERRUPT;
5357	}
5358
5359
5360	/**
5361	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
5362	*/
5363	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5364	{
5365	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5366
5367	/* Clear NMI blocking. */
5368	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5369
5370	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
5371	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5372	hmR0SvmClearIretIntercept(pVmcb);
5373
5374	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5375	return VINF_SUCCESS;
5376	}
5377
5378
5379	/**
5380	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
5381	* Conditional \#VMEXIT.
5382	*/
5383	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5384	{
5385	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5386
5387	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5388
5389	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
5390	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5391	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5392	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
5393	PVM pVM = pVCpu->CTX_SUFF(pVM);
5394
5395	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
5396	if (pVM->hm.s.fNestedPaging)
5397	{
5398	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5399	if (!pSvmTransient->fVectoringDoublePF)
5400	{
5401	/* A genuine guest #PF, reflect it to the guest. */
5402	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5403	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
5404	uFaultAddress, u32ErrCode));
5405	}
5406	else
5407	{
5408	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5409	hmR0SvmSetPendingXcptDF(pVCpu);
5410	Log4(("Pending #DF due to vectoring #PF. NP\n"));
5411	}
5412	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5413	return VINF_SUCCESS;
5414	}
5415	#endif
5416
5417	Assert(!pVM->hm.s.fNestedPaging);
5418
5419	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5420	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
5421	if ( pVM->hm.s.fTprPatchingAllowed
5422	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
5423	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
5424	&& !CPUMIsGuestInLongModeEx(pCtx)
5425	&& !CPUMGetGuestCPL(pVCpu)
5426	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5427	{
5428	RTGCPHYS GCPhysApicBase;
5429	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
5430	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5431
5432	/* Check if the page at the fault-address is the APIC base. */
5433	RTGCPHYS GCPhysPage;
5434	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
5435	if ( rc2 == VINF_SUCCESS
5436	&& GCPhysPage == GCPhysApicBase)
5437	{
5438	/* Only attempt to patch the instruction once. */
5439	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5440	if (!pPatch)
5441	return VINF_EM_HM_PATCH_TPR_INSTR;
5442	}
5443	}
5444	#endif
5445
5446	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
5447	pCtx->rip, u32ErrCode, pCtx->cr3));
5448
5449	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
5450	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
5451	if (pSvmTransient->fVectoringPF)
5452	{
5453	Assert(pVCpu->hm.s.Event.fPending);
5454	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5455	}
5456
5457	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
5458	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
5459
5460	Log4(("#PF rc=%Rrc\n", rc));
5461
5462	if (rc == VINF_SUCCESS)
5463	{
5464	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
5465	TRPMResetTrap(pVCpu);
5466	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5467	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
5468	return rc;
5469	}
5470	else if (rc == VINF_EM_RAW_GUEST_TRAP)
5471	{
5472	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5473
5474	if (!pSvmTransient->fVectoringDoublePF)
5475	{
5476	/* It's a guest page fault and needs to be reflected to the guest. */
5477	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
5478	TRPMResetTrap(pVCpu);
5479	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5480	}
5481	else
5482	{
5483	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5484	TRPMResetTrap(pVCpu);
5485	hmR0SvmSetPendingXcptDF(pVCpu);
5486	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
5487	}
5488
5489	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5490	return VINF_SUCCESS;
5491	}
5492
5493	TRPMResetTrap(pVCpu);
5494	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
5495	return rc;
5496	}
5497
5498
5499	/**
5500	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
5501	* Conditional \#VMEXIT.
5502	*/
5503	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5504	{
5505	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5506
5507	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5508	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5509	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5510
5511	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5512	VMMRZCallRing3Disable(pVCpu);
5513	HM_DISABLE_PREEMPT();
5514
5515	int rc;
5516	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
5517	if (pSvmTransient->fWasGuestFPUStateActive)
5518	{
5519	rc = VINF_EM_RAW_GUEST_TRAP;
5520	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
5521	}
5522	else
5523	{
5524	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5525	Assert(!pSvmTransient->fWasGuestFPUStateActive);
5526	#endif
5527	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
5528	Assert( rc == VINF_EM_RAW_GUEST_TRAP
5529	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
5530	}
5531
5532	HM_RESTORE_PREEMPT();
5533	VMMRZCallRing3Enable(pVCpu);
5534
5535	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
5536	{
5537	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
5538	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
5539	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
5540	pVCpu->hm.s.fPreloadGuestFpu = true;
5541	}
5542	else
5543	{
5544	/* Forward #NM to the guest. */
5545	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
5546	hmR0SvmSetPendingXcptNM(pVCpu);
5547	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
5548	}
5549	return VINF_SUCCESS;
5550	}
5551
5552
5553	/**
5554	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
5555	* Conditional \#VMEXIT.
5556	*/
5557	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5558	{
5559	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5560
5561	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5562	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5563	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5564
5565	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
5566	if (pVCpu->hm.s.fGIMTrapXcptUD)
5567	{
5568	uint8_t cbInstr = 0;
5569	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
5570	if (rcStrict == VINF_SUCCESS)
5571	{
5572	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
5573	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
5574	rc = VINF_SUCCESS;
5575	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5576	}
5577	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
5578	rc = VINF_SUCCESS;
5579	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
5580	rc = VINF_GIM_R3_HYPERCALL;
5581	else
5582	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
5583	}
5584
5585	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
5586	if (RT_FAILURE(rc))
5587	{
5588	hmR0SvmSetPendingXcptUD(pVCpu);
5589	rc = VINF_SUCCESS;
5590	}
5591
5592	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
5593	return rc;
5594	}
5595
5596
5597	/**
5598	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
5599	* Conditional \#VMEXIT.
5600	*/
5601	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5602	{
5603	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5604
5605	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5606	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5607	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5608
5609	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
5610
5611	if (!(pCtx->cr0 & X86_CR0_NE))
5612	{
5613	PVM pVM = pVCpu->CTX_SUFF(pVM);
5614	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5615	unsigned cbOp;
5616	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
5617	if (RT_SUCCESS(rc))
5618	{
5619	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
5620	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
5621	if (RT_SUCCESS(rc))
5622	pCtx->rip += cbOp;
5623	}
5624	else
5625	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5626	return rc;
5627	}
5628
5629	hmR0SvmSetPendingXcptMF(pVCpu);
5630	return VINF_SUCCESS;
5631	}
5632
5633
5634	/**
5635	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
5636	* \#VMEXIT.
5637	*/
5638	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5639	{
5640	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5641
5642	/* If this #DB is the result of delivering an event, go back to the interpreter. */
5643	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5644	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5645	{
5646	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
5647	/** @todo this should return VINF_EM_RAW_INJECT_TRPM_EVENT. */
5648	return VERR_EM_INTERPRETER;
5649	}
5650
5651	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
5652
5653	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
5654	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
5655	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5656	PVM pVM = pVCpu->CTX_SUFF(pVM);
5657	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
5658	if (rc == VINF_EM_RAW_GUEST_TRAP)
5659	{
5660	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
5661	if (CPUMIsHyperDebugStateActive(pVCpu))
5662	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
5663
5664	/* Reflect the exception back to the guest. */
5665	hmR0SvmSetPendingXcptDB(pVCpu);
5666	rc = VINF_SUCCESS;
5667	}
5668
5669	/*
5670	* Update DR6.
5671	*/
5672	if (CPUMIsHyperDebugStateActive(pVCpu))
5673	{
5674	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
5675	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
5676	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5677	}
5678	else
5679	{
5680	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
5681	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
5682	}
5683
5684	return rc;
5685	}
5686
5687
5688	/**
5689	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
5690	* Conditional \#VMEXIT.
5691	*/
5692	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5693	{
5694	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5695
5696	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5697
5698	SVMEVENT Event;
5699	Event.u = 0;
5700	Event.n.u1Valid = 1;
5701	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5702	Event.n.u8Vector = X86_XCPT_AC;
5703	Event.n.u1ErrorCodeValid = 1;
5704	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5705	return VINF_SUCCESS;
5706	}
5707
5708
5709	/**
5710	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
5711	* Conditional \#VMEXIT.
5712	*/
5713	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5714	{
5715	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5716
5717	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5718
5719	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
5720	if (rc == VINF_EM_RAW_GUEST_TRAP)
5721	{
5722	SVMEVENT Event;
5723	Event.u = 0;
5724	Event.n.u1Valid = 1;
5725	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5726	Event.n.u8Vector = X86_XCPT_BP;
5727	Event.n.u1ErrorCodeValid = 0;
5728	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5729	}
5730
5731	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
5732	return rc;
5733	}
5734
5735
5736	#ifdef VBOX_WITH_NESTED_HWVIRT
5737	/**
5738	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
5739	*/
5740	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5741	{
5742	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5743	/** @todo Stat. */
5744	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
5745	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5746	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
5747	return VBOXSTRICTRC_VAL(rcStrict);
5748	}
5749
5750
5751	/**
5752	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
5753	*/
5754	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5755	{
5756	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5757	/** @todo Stat. */
5758	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
5759	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5760	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
5761	return VBOXSTRICTRC_VAL(rcStrict);
5762	}
5763
5764
5765	/**
5766	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
5767	*/
5768	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5769	{
5770	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5771	/** @todo Stat. */
5772	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
5773	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5774	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
5775	return VBOXSTRICTRC_VAL(rcStrict);
5776	}
5777
5778
5779	/**
5780	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
5781	*/
5782	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5783	{
5784	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5785	/** @todo Stat. */
5786	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
5787	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5788	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
5789	return VBOXSTRICTRC_VAL(rcStrict);
5790	}
5791
5792
5793	/**
5794	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
5795	*/
5796	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5797	{
5798	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5799	/** @todo Stat. */
5800	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
5801	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5802	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
5803	return VBOXSTRICTRC_VAL(rcStrict);
5804	}
5805	#endif /* VBOX_WITH_NESTED_HWVIRT */
5806
5807
5808	/** @} */
5809

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 66987

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