HMSVMR0.cpp@ 69474

Last change on this file since 69474 was 69414, checked in by vboxsync, 7 years ago
VMM/HMSVMR0: Doxygen leading to removing unused code.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 290.2 KB

Line
1	/* $Id: HMSVMR0.cpp 69414 2017-10-27 09:42:59Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/thread.h>
25
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#include <VBox/vmm/apic.h>
33	#include "HMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include "HMSVMR0.h"
36	#include "dtrace/VBoxVMM.h"
37
38	#define HMSVM_USE_IEM_EVENT_REFLECTION
39	#ifdef DEBUG_ramshankar
40	# define HMSVM_SYNC_FULL_GUEST_STATE
41	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
42	# define HMSVM_ALWAYS_TRAP_PF
43	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
44	#endif
45
46
47	/*********************************************************************************************************************************
48	* Defined Constants And Macros *
49	*********************************************************************************************************************************/
50	#ifdef VBOX_WITH_STATISTICS
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
52	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
53	if ((u64ExitCode) == SVM_EXIT_NPF) \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
55	else \
56	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
57	} while (0)
58	#else
59	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
60	#endif
61
62	/** If we decide to use a function table approach this can be useful to
63	* switch to a "static DECLCALLBACK(int)". */
64	#define HMSVM_EXIT_DECL static int
65
66	/** Macro for checking and returning from the using function for
67	* \#VMEXIT intercepts that maybe caused during delivering of another
68	* event in the guest. */
69	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
70	do \
71	{ \
72	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
73	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
74	else if (rc == VINF_HM_DOUBLE_FAULT) \
75	return VINF_SUCCESS; \
76	else \
77	return rc; \
78	} while (0)
79
80	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
81	* instruction that exited. */
82	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
83	do { \
84	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
85	(a_rc) = VINF_EM_DBG_STEPPED; \
86	} while (0)
87
88	/** Assert that preemption is disabled or covered by thread-context hooks. */
89	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
90	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
91
92	/** Assert that we haven't migrated CPUs when thread-context hooks are not
93	* used. */
94	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
95	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
96	("Illegal migration! Entered on CPU %u Current %u\n", \
97	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
98
99	/**
100	* Exception bitmap mask for all contributory exceptions.
101	*
102	* Page fault is deliberately excluded here as it's conditional as to whether
103	* it's contributory or benign. Page faults are handled separately.
104	*/
105	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
106	\| RT_BIT(X86_XCPT_DE))
107
108	/**
109	* Mandatory/unconditional guest control intercepts.
110	*/
111	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
112	\| SVM_CTRL_INTERCEPT_NMI \
113	\| SVM_CTRL_INTERCEPT_INIT \
114	\| SVM_CTRL_INTERCEPT_RDPMC \
115	\| SVM_CTRL_INTERCEPT_CPUID \
116	\| SVM_CTRL_INTERCEPT_RSM \
117	\| SVM_CTRL_INTERCEPT_HLT \
118	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
119	\| SVM_CTRL_INTERCEPT_MSR_PROT \
120	\| SVM_CTRL_INTERCEPT_INVLPGA \
121	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
122	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
123	\| SVM_CTRL_INTERCEPT_VMRUN \
124	\| SVM_CTRL_INTERCEPT_VMMCALL \
125	\| SVM_CTRL_INTERCEPT_VMLOAD \
126	\| SVM_CTRL_INTERCEPT_VMSAVE \
127	\| SVM_CTRL_INTERCEPT_STGI \
128	\| SVM_CTRL_INTERCEPT_CLGI \
129	\| SVM_CTRL_INTERCEPT_SKINIT \
130	\| SVM_CTRL_INTERCEPT_WBINVD \
131	\| SVM_CTRL_INTERCEPT_MONITOR \
132	\| SVM_CTRL_INTERCEPT_MWAIT \
133	\| SVM_CTRL_INTERCEPT_XSETBV)
134
135	/**
136	* Mandatory/unconditional nested-guest control intercepts.
137	*/
138	#define HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS ( HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS \
139	\| SVM_CTRL_INTERCEPT_SMI)
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/\#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG fEFlags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
211	bool fWasGuestFPUStateActive;
212	/** Whether the guest debug state was active at the time of \#VMEXIT. */
213	bool fWasGuestDebugStateActive;
214	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
215	bool fWasHyperDebugStateActive;
216	/** Whether the TSC offset mode needs to be updated. */
217	bool fUpdateTscOffsetting;
218	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
219	bool fRestoreTscAuxMsr;
220	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
221	* contributary exception or a page-fault. */
222	bool fVectoringDoublePF;
223	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
224	* external interrupt or NMI. */
225	bool fVectoringPF;
226	} SVMTRANSIENT, *PSVMTRANSIENT;
227	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
228	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
229	/** @} */
230
231	/**
232	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
233	*/
234	typedef enum SVMMSREXITREAD
235	{
236	/** Reading this MSR causes a \#VMEXIT. */
237	SVMMSREXIT_INTERCEPT_READ = 0xb,
238	/** Reading this MSR does not cause a \#VMEXIT. */
239	SVMMSREXIT_PASSTHRU_READ
240	} SVMMSREXITREAD;
241
242	/**
243	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
244	*/
245	typedef enum SVMMSREXITWRITE
246	{
247	/** Writing to this MSR causes a \#VMEXIT. */
248	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
249	/** Writing to this MSR does not cause a \#VMEXIT. */
250	SVMMSREXIT_PASSTHRU_WRITE
251	} SVMMSREXITWRITE;
252
253	/**
254	* SVM \#VMEXIT handler.
255	*
256	* @returns VBox status code.
257	* @param pVCpu The cross context virtual CPU structure.
258	* @param pMixedCtx Pointer to the guest-CPU context.
259	* @param pSvmTransient Pointer to the SVM-transient structure.
260	*/
261	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262
263
264	/*********************************************************************************************************************************
265	* Internal Functions *
266	*********************************************************************************************************************************/
267	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
268	SVMMSREXITWRITE enmWrite);
269	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
270	static void hmR0SvmLeave(PVMCPU pVCpu);
271
272	/** @name \#VMEXIT handlers.
273	* @{
274	*/
275	static FNSVMEXITHANDLER hmR0SvmExitIntr;
276	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
277	static FNSVMEXITHANDLER hmR0SvmExitInvd;
278	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
279	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
280	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
281	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
282	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
283	static FNSVMEXITHANDLER hmR0SvmExitHlt;
284	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
285	static FNSVMEXITHANDLER hmR0SvmExitMwait;
286	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
287	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
288	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
289	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
290	static FNSVMEXITHANDLER hmR0SvmExitMsr;
291	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
292	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
293	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
294	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
295	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
296	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
297	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
298	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
299	static FNSVMEXITHANDLER hmR0SvmExitPause;
300	static FNSVMEXITHANDLER hmR0SvmExitIret;
301	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
302	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
303	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
304	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
305	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
306	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
307	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
308	#ifdef VBOX_WITH_NESTED_HWVIRT
309	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
310	static FNSVMEXITHANDLER hmR0SvmExitClgi;
311	static FNSVMEXITHANDLER hmR0SvmExitStgi;
312	static FNSVMEXITHANDLER hmR0SvmExitVmload;
313	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
314	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
315	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
316	static FNSVMEXITHANDLER hmR0SvmNestedExitIret;
317	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
318	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
319	#endif
320	/** @} */
321
322	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
323	#ifdef VBOX_WITH_NESTED_HWVIRT
324	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
325	#endif
326
327
328	/*********************************************************************************************************************************
329	* Global Variables *
330	*********************************************************************************************************************************/
331	/** Ring-0 memory object for the IO bitmap. */
332	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
333	/** Physical address of the IO bitmap. */
334	RTHCPHYS g_HCPhysIOBitmap = 0;
335	/** Pointer to the IO bitmap. */
336	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
337
338	#ifdef VBOX_WITH_NESTED_HWVIRT
339	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
340	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
341	/** Physical address of the nested-guest MSRPM bitmap. */
342	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
343	/** Pointer to the nested-guest MSRPM bitmap. */
344	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
345	#endif
346
347	/**
348	* Sets up and activates AMD-V on the current CPU.
349	*
350	* @returns VBox status code.
351	* @param pCpu Pointer to the CPU info struct.
352	* @param pVM The cross context VM structure. Can be
353	* NULL after a resume!
354	* @param pvCpuPage Pointer to the global CPU page.
355	* @param HCPhysCpuPage Physical address of the global CPU page.
356	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
357	* @param pvArg Unused on AMD-V.
358	*/
359	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
360	void *pvArg)
361	{
362	Assert(!fEnabledByHost);
363	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
364	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
365	Assert(pvCpuPage); NOREF(pvCpuPage);
366	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
367
368	NOREF(pvArg);
369	NOREF(fEnabledByHost);
370
371	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
372	RTCCUINTREG fEFlags = ASMIntDisableFlags();
373
374	/*
375	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
376	*/
377	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
378	if (u64HostEfer & MSR_K6_EFER_SVME)
379	{
380	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
381	if ( pVM
382	&& pVM->hm.s.svm.fIgnoreInUseError)
383	{
384	pCpu->fIgnoreAMDVInUseError = true;
385	}
386
387	if (!pCpu->fIgnoreAMDVInUseError)
388	{
389	ASMSetFlags(fEFlags);
390	return VERR_SVM_IN_USE;
391	}
392	}
393
394	/* Turn on AMD-V in the EFER MSR. */
395	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
396
397	/* Write the physical page address where the CPU will store the host state while executing the VM. */
398	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
399
400	/* Restore interrupts. */
401	ASMSetFlags(fEFlags);
402
403	/*
404	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
405	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
406	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
407	* guest code.
408	*/
409	pCpu->fFlushAsidBeforeUse = true;
410
411	/*
412	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
413	*/
414	++pCpu->cTlbFlushes;
415
416	return VINF_SUCCESS;
417	}
418
419
420	/**
421	* Deactivates AMD-V on the current CPU.
422	*
423	* @returns VBox status code.
424	* @param pCpu Pointer to the CPU info struct.
425	* @param pvCpuPage Pointer to the global CPU page.
426	* @param HCPhysCpuPage Physical address of the global CPU page.
427	*/
428	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
429	{
430	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
431	AssertReturn( HCPhysCpuPage
432	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
433	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
434	NOREF(pCpu);
435
436	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
437	RTCCUINTREG fEFlags = ASMIntDisableFlags();
438
439	/* Turn off AMD-V in the EFER MSR. */
440	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
441	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
442
443	/* Invalidate host state physical address. */
444	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
445
446	/* Restore interrupts. */
447	ASMSetFlags(fEFlags);
448
449	return VINF_SUCCESS;
450	}
451
452
453	/**
454	* Does global AMD-V initialization (called during module initialization).
455	*
456	* @returns VBox status code.
457	*/
458	VMMR0DECL(int) SVMR0GlobalInit(void)
459	{
460	/*
461	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
462	* once globally here instead of per-VM.
463	*/
464	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
465	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
466	if (RT_FAILURE(rc))
467	return rc;
468
469	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
470	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
471
472	/* Set all bits to intercept all IO accesses. */
473	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
474
475	#ifdef VBOX_WITH_NESTED_HWVIRT
476	/*
477	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
478	*/
479	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
480	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
481	if (RT_FAILURE(rc))
482	return rc;
483
484	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
485	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
486
487	/* Set all bits to intercept all MSR accesses. */
488	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
489	#endif
490
491	return VINF_SUCCESS;
492	}
493
494
495	/**
496	* Does global AMD-V termination (called during module termination).
497	*/
498	VMMR0DECL(void) SVMR0GlobalTerm(void)
499	{
500	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
501	{
502	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
503	g_pvIOBitmap = NULL;
504	g_HCPhysIOBitmap = 0;
505	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
506	}
507
508	#ifdef VBOX_WITH_NESTED_HWVIRT
509	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
510	{
511	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
512	g_pvNstGstMsrBitmap = NULL;
513	g_HCPhysNstGstMsrBitmap = 0;
514	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
515	}
516	#endif
517	}
518
519
520	/**
521	* Frees any allocated per-VCPU structures for a VM.
522	*
523	* @param pVM The cross context VM structure.
524	*/
525	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
526	{
527	for (uint32_t i = 0; i < pVM->cCpus; i++)
528	{
529	PVMCPU pVCpu = &pVM->aCpus[i];
530	AssertPtr(pVCpu);
531
532	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
533	{
534	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
535	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
536	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
537	}
538
539	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
540	{
541	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
542	pVCpu->hm.s.svm.pVmcb = NULL;
543	pVCpu->hm.s.svm.HCPhysVmcb = 0;
544	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
545	}
546
547	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
548	{
549	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
550	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
551	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
552	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
553	}
554	}
555	}
556
557
558	/**
559	* Does per-VM AMD-V initialization.
560	*
561	* @returns VBox status code.
562	* @param pVM The cross context VM structure.
563	*/
564	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
565	{
566	int rc = VERR_INTERNAL_ERROR_5;
567
568	/*
569	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
570	*/
571	uint32_t u32Family;
572	uint32_t u32Model;
573	uint32_t u32Stepping;
574	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
575	{
576	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
577	pVM->hm.s.svm.fAlwaysFlushTLB = true;
578	}
579
580	/*
581	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
582	*/
583	for (VMCPUID i = 0; i < pVM->cCpus; i++)
584	{
585	PVMCPU pVCpu = &pVM->aCpus[i];
586	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
587	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
588	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
589	}
590
591	for (VMCPUID i = 0; i < pVM->cCpus; i++)
592	{
593	PVMCPU pVCpu = &pVM->aCpus[i];
594
595	/*
596	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
597	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
598	*/
599	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
600	if (RT_FAILURE(rc))
601	goto failure_cleanup;
602
603	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
604	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
605	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
606	ASMMemZeroPage(pvVmcbHost);
607
608	/*
609	* Allocate one page for the guest-state VMCB.
610	*/
611	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
612	if (RT_FAILURE(rc))
613	goto failure_cleanup;
614
615	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
616	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
617	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
618	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
619
620	/*
621	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
622	* SVM to not require one.
623	*/
624	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
625	false /* fExecutable */);
626	if (RT_FAILURE(rc))
627	goto failure_cleanup;
628
629	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
630	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
631	/* Set all bits to intercept all MSR accesses (changed later on). */
632	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
633	}
634
635	return VINF_SUCCESS;
636
637	failure_cleanup:
638	hmR0SvmFreeStructs(pVM);
639	return rc;
640	}
641
642
643	/**
644	* Does per-VM AMD-V termination.
645	*
646	* @returns VBox status code.
647	* @param pVM The cross context VM structure.
648	*/
649	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
650	{
651	hmR0SvmFreeStructs(pVM);
652	return VINF_SUCCESS;
653	}
654
655
656	/**
657	* Sets the permission bits for the specified MSR in the MSRPM.
658	*
659	* @param pVmcb Pointer to the VM control block.
660	* @param pbMsrBitmap Pointer to the MSR bitmap.
661	* @param uMsr The MSR for which the access permissions are being set.
662	* @param enmRead MSR read permissions.
663	* @param enmWrite MSR write permissions.
664	*/
665	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
666	SVMMSREXITWRITE enmWrite)
667	{
668	uint16_t offMsrpm;
669	uint32_t uMsrpmBit;
670	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
671	AssertRC(rc);
672
673	Assert(uMsrpmBit < 0x3fff);
674	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
675
676	pbMsrBitmap += offMsrpm;
677	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
678	ASMBitSet(pbMsrBitmap, uMsrpmBit);
679	else
680	ASMBitClear(pbMsrBitmap, uMsrpmBit);
681
682	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
683	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
684	else
685	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
686
687	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
688	}
689
690
691	/**
692	* Sets up AMD-V for the specified VM.
693	* This function is only called once per-VM during initalization.
694	*
695	* @returns VBox status code.
696	* @param pVM The cross context VM structure.
697	*/
698	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
699	{
700	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
701	AssertReturn(pVM, VERR_INVALID_PARAMETER);
702	Assert(pVM->hm.s.svm.fSupported);
703
704	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
705	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
706	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
707
708	for (VMCPUID i = 0; i < pVM->cCpus; i++)
709	{
710	PVMCPU pVCpu = &pVM->aCpus[i];
711	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
712
713	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
714
715	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
716	Assert(!pVCpu->hm.s.idxExitHistoryFree);
717	HMCPU_EXIT_HISTORY_RESET(pVCpu);
718
719	/* Always trap #AC for reasons of security. */
720	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
721
722	/* Always trap #DB for reasons of security. */
723	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
724
725	/* Trap exceptions unconditionally (debug purposes). */
726	#ifdef HMSVM_ALWAYS_TRAP_PF
727	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
728	#endif
729	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
730	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
731	pVmcb->ctrl.u32InterceptXcpt \|= 0
732	\| RT_BIT(X86_XCPT_BP)
733	\| RT_BIT(X86_XCPT_DE)
734	\| RT_BIT(X86_XCPT_NM)
735	\| RT_BIT(X86_XCPT_UD)
736	\| RT_BIT(X86_XCPT_NP)
737	\| RT_BIT(X86_XCPT_SS)
738	\| RT_BIT(X86_XCPT_GP)
739	\| RT_BIT(X86_XCPT_PF)
740	\| RT_BIT(X86_XCPT_MF)
741	;
742	#endif
743
744	/* Set up unconditional intercepts and conditions. */
745	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
746
747	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
748	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
749
750	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
751	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
752
753	/* Intercept all DRx reads and writes by default. Changed later on. */
754	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
755	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
756
757	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
758	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
759
760	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
761	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
762	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
763
764	/* Set IO and MSR bitmap permission bitmap physical addresses. */
765	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
766	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
767
768	/* No LBR virtualization. */
769	pVmcb->ctrl.u64LBRVirt = 0;
770
771	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
772	pVmcb->ctrl.u64VmcbCleanBits = 0;
773
774	/* The host ASID MBZ, for the guest start with 1. */
775	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
776
777	/*
778	* Setup the PAT MSR (applicable for Nested Paging only).
779	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
780	* so choose type 6 for all PAT slots.
781	*/
782	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
783
784	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
785	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
786
787	/* Without Nested Paging, we need additionally intercepts. */
788	if (!pVM->hm.s.fNestedPaging)
789	{
790	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
791	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
792	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
793
794	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
795	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
796	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
797
798	/* Page faults must be intercepted to implement shadow paging. */
799	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
800	}
801
802	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
803	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
804	#endif
805
806	/* Apply the exceptions intercepts needed by the GIM provider. */
807	if (pVCpu->hm.s.fGIMTrapXcptUD)
808	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
809
810	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
811	if (fUsePauseFilter)
812	{
813	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
814	if (fPauseFilterThreshold)
815	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
816	}
817
818	/*
819	* The following MSRs are saved/restored automatically during the world-switch.
820	* Don't intercept guest read/write accesses to these MSRs.
821	*/
822	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
823	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
824	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
825	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
826	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
827	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
828	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
829	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
830	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
831	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
832	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
833	}
834
835	return VINF_SUCCESS;
836	}
837
838
839	/**
840	* Invalidates a guest page by guest virtual address.
841	*
842	* @returns VBox status code.
843	* @param pVM The cross context VM structure.
844	* @param pVCpu The cross context virtual CPU structure.
845	* @param GCVirt Guest virtual address of the page to invalidate.
846	*/
847	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
848	{
849	AssertReturn(pVM, VERR_INVALID_PARAMETER);
850	Assert(pVM->hm.s.svm.fSupported);
851
852	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
853
854	/* Skip it if a TLB flush is already pending. */
855	if (!fFlushPending)
856	{
857	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
858
859	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
860	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
861
862	#if HC_ARCH_BITS == 32
863	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
864	if (CPUMIsGuestInLongMode(pVCpu))
865	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
866	else
867	#endif
868	{
869	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
870	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
871	}
872	}
873	return VINF_SUCCESS;
874	}
875
876
877	/**
878	* Flushes the appropriate tagged-TLB entries.
879	*
880	* @param pVCpu The cross context virtual CPU structure.
881	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
882	* @param pVmcb Pointer to the VM control block.
883	*/
884	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
885	{
886	PVM pVM = pVCpu->CTX_SUFF(pVM);
887	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
888
889	/*
890	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
891	* This can happen both for start & resume due to long jumps back to ring-3.
892	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
893	* so we cannot reuse the ASIDs without flushing.
894	*/
895	bool fNewAsid = false;
896	Assert(pCpu->idCpu != NIL_RTCPUID);
897	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
898	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
899	{
900	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
901	pVCpu->hm.s.fForceTLBFlush = true;
902	fNewAsid = true;
903	}
904
905	/* Set TLB flush state as checked until we return from the world switch. */
906	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
907
908	/* Check for explicit TLB flushes. */
909	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
910	{
911	pVCpu->hm.s.fForceTLBFlush = true;
912	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
913	}
914
915	/*
916	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
917	* This Host CPU requirement takes precedence.
918	*/
919	if (pVM->hm.s.svm.fAlwaysFlushTLB)
920	{
921	pCpu->uCurrentAsid = 1;
922	pVCpu->hm.s.uCurrentAsid = 1;
923	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
924	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
925
926	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
927	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
928
929	/* Keep track of last CPU ID even when flushing all the time. */
930	if (fNewAsid)
931	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
932	}
933	else
934	{
935	#ifdef VBOX_WITH_NESTED_HWVIRT
936	/*
937	* Only if the nested hypervisor says it does not need to flush anything in the TLB,
938	* can we possibly apply it on the host. Otherwise, the nested-guest TLB flush setting
939	* should be used and then the host settings be added on top.
940	*/
941	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
942	{
943	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
944	if (pVmcbNstGstCache->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
945	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
946	else
947	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = pVmcbNstGstCache->TLBCtrl.n.u8TLBFlush;
948	}
949	#else
950	RT_NOREF(pCtx);
951	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
952	#endif
953	if (pVCpu->hm.s.fForceTLBFlush)
954	{
955	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
956	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
957
958	if (fNewAsid)
959	{
960	++pCpu->uCurrentAsid;
961
962	bool fHitASIDLimit = false;
963	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
964	{
965	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
966	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
967	fHitASIDLimit = true;
968	}
969
970	if ( fHitASIDLimit
971	\|\| pCpu->fFlushAsidBeforeUse)
972	{
973	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
974	pCpu->fFlushAsidBeforeUse = false;
975	}
976
977	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
978	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
979	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
980	}
981	else
982	{
983	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
984	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
985	else
986	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
987	}
988
989	pVCpu->hm.s.fForceTLBFlush = false;
990	}
991	}
992
993	/* Update VMCB with the ASID. */
994	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
995	{
996	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
997	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
998	}
999
1000	#ifdef VBOX_WITH_NESTED_HWVIRT
1001	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx) \|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_NOTHING);
1002	#endif
1003
1004	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
1005	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1006	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1007	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1008	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1009	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1010	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1011	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1012
1013	#ifdef VBOX_WITH_STATISTICS
1014	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1015	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1016	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1017	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1018	{
1019	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1020	}
1021	else
1022	{
1023	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1024	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1025	}
1026	#endif
1027	}
1028
1029
1030	/** @name 64-bit guest on 32-bit host OS helper functions.
1031	*
1032	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1033	* mode (code segment, paging). These wrappers/helpers perform the necessary
1034	* bits for the 32->64 switcher.
1035	*
1036	* @{ */
1037	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1038	/**
1039	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1040	*
1041	* @returns VBox status code.
1042	* @param HCPhysVmcbHost Physical address of host VMCB.
1043	* @param HCPhysVmcb Physical address of the VMCB.
1044	* @param pCtx Pointer to the guest-CPU context.
1045	* @param pVM The cross context VM structure.
1046	* @param pVCpu The cross context virtual CPU structure.
1047	*/
1048	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1049	{
1050	uint32_t aParam[8];
1051	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1052	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1053	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1054	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1055	aParam[4] = VM_RC_ADDR(pVM, pVM);
1056	aParam[5] = 0;
1057	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1058	aParam[7] = 0;
1059
1060	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1061	}
1062
1063
1064	/**
1065	* Executes the specified VMRUN handler in 64-bit mode.
1066	*
1067	* @returns VBox status code.
1068	* @param pVM The cross context VM structure.
1069	* @param pVCpu The cross context virtual CPU structure.
1070	* @param pCtx Pointer to the guest-CPU context.
1071	* @param enmOp The operation to perform.
1072	* @param cParams Number of parameters.
1073	* @param paParam Array of 32-bit parameters.
1074	*/
1075	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1076	uint32_t cParams, uint32_t *paParam)
1077	{
1078	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1079	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1080
1081	NOREF(pCtx);
1082
1083	/* Disable interrupts. */
1084	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1085
1086	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1087	RTCPUID idHostCpu = RTMpCpuId();
1088	CPUMR0SetLApic(pVCpu, idHostCpu);
1089	#endif
1090
1091	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1092	CPUMSetHyperEIP(pVCpu, enmOp);
1093	for (int i = (int)cParams - 1; i >= 0; i--)
1094	CPUMPushHyper(pVCpu, paParam[i]);
1095
1096	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1097	/* Call the switcher. */
1098	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1099	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1100
1101	/* Restore interrupts. */
1102	ASMSetFlags(uOldEFlags);
1103	return rc;
1104	}
1105
1106	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1107	/** @} */
1108
1109
1110	/**
1111	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1112	* the corresponding VMCB Clean bit.
1113	*
1114	* @param pVmcb Pointer to the VM control block.
1115	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1116	*/
1117	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1118	{
1119	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1120	{
1121	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1122	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1123	}
1124	}
1125
1126
1127	/**
1128	* Removes an exception from the intercept-exception bitmap in the VMCB and
1129	* updates the corresponding VMCB Clean bit.
1130	*
1131	* @param pVmcb Pointer to the VM control block.
1132	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1133	*/
1134	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1135	{
1136	Assert(u32Xcpt != X86_XCPT_DB);
1137	Assert(u32Xcpt != X86_XCPT_AC);
1138	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1139	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1140	{
1141	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1142	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1143	}
1144	#endif
1145	}
1146
1147
1148	/**
1149	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1150	* Although the guest CR0 is a separate field in the VMCB we have to consider
1151	* the FPU state itself which is shared between the host and the guest.
1152	*
1153	* @returns VBox status code.
1154	* @param pVCpu The cross context virtual CPU structure.
1155	* @param pVmcb Pointer to the VM control block.
1156	* @param pCtx Pointer to the guest-CPU context.
1157	*
1158	* @remarks No-long-jump zone!!!
1159	*/
1160	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1161	{
1162	uint64_t u64GuestCR0 = pCtx->cr0;
1163
1164	/* Always enable caching. */
1165	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1166
1167	/*
1168	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1169	*/
1170	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1171	{
1172	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1173	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1174	}
1175
1176	/*
1177	* Guest FPU bits.
1178	*/
1179	bool fInterceptNM = false;
1180	bool fInterceptMF = false;
1181	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1182	if (CPUMIsGuestFPUStateActive(pVCpu))
1183	{
1184	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1185	if (!(pCtx->cr0 & X86_CR0_NE))
1186	{
1187	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1188	fInterceptMF = true;
1189	}
1190	}
1191	else
1192	{
1193	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1194	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1195	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1196	}
1197
1198	/*
1199	* Update the exception intercept bitmap.
1200	*/
1201	if (fInterceptNM)
1202	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1203	else
1204	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1205
1206	if (fInterceptMF)
1207	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1208	else
1209	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1210
1211	pVmcb->guest.u64CR0 = u64GuestCR0;
1212	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1213	}
1214
1215
1216	/**
1217	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1218	*
1219	* @returns VBox status code.
1220	* @param pVCpu The cross context virtual CPU structure.
1221	* @param pVmcb Pointer to the VM control block.
1222	* @param pCtx Pointer to the guest-CPU context.
1223	*
1224	* @remarks No-long-jump zone!!!
1225	*/
1226	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1227	{
1228	PVM pVM = pVCpu->CTX_SUFF(pVM);
1229
1230	/*
1231	* Guest CR2.
1232	*/
1233	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1234	{
1235	pVmcb->guest.u64CR2 = pCtx->cr2;
1236	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1237	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1238	}
1239
1240	/*
1241	* Guest CR3.
1242	*/
1243	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1244	{
1245	if (pVM->hm.s.fNestedPaging)
1246	{
1247	PGMMODE enmShwPagingMode;
1248	#if HC_ARCH_BITS == 32
1249	if (CPUMIsGuestInLongModeEx(pCtx))
1250	enmShwPagingMode = PGMMODE_AMD64_NX;
1251	else
1252	#endif
1253	enmShwPagingMode = PGMGetHostMode(pVM);
1254
1255	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1256	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1257	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1258	pVmcb->guest.u64CR3 = pCtx->cr3;
1259	}
1260	else
1261	{
1262	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1263	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1264	}
1265
1266	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1267	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1268	}
1269
1270	/*
1271	* Guest CR4.
1272	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1273	*/
1274	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1275	{
1276	uint64_t u64GuestCR4 = pCtx->cr4;
1277	Assert(RT_HI_U32(u64GuestCR4) == 0);
1278	if (!pVM->hm.s.fNestedPaging)
1279	{
1280	switch (pVCpu->hm.s.enmShadowMode)
1281	{
1282	case PGMMODE_REAL:
1283	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1284	AssertFailed();
1285	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1286
1287	case PGMMODE_32_BIT: /* 32-bit paging. */
1288	u64GuestCR4 &= ~X86_CR4_PAE;
1289	break;
1290
1291	case PGMMODE_PAE: /* PAE paging. */
1292	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1293	/** Must use PAE paging as we could use physical memory > 4 GB */
1294	u64GuestCR4 \|= X86_CR4_PAE;
1295	break;
1296
1297	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1298	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1299	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1300	break;
1301	#else
1302	AssertFailed();
1303	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1304	#endif
1305
1306	default: /* shut up gcc */
1307	AssertFailed();
1308	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1309	}
1310	}
1311
1312	pVmcb->guest.u64CR4 = u64GuestCR4;
1313	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1314
1315	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1316	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1317
1318	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1319	}
1320
1321	return VINF_SUCCESS;
1322	}
1323
1324
1325	#ifdef VBOX_WITH_NESTED_HWVIRT
1326	/**
1327	* Loads the nested-guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1328	*
1329	* @returns VBox status code.
1330	* @param pVCpu The cross context virtual CPU structure.
1331	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1332	* @param pCtx Pointer to the guest-CPU context.
1333	*
1334	* @remarks No-long-jump zone!!!
1335	*/
1336	static int hmR0SvmLoadGuestControlRegsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1337	{
1338	/*
1339	* Guest CR0.
1340	*/
1341	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1342	{
1343	pVmcbNstGst->guest.u64CR0 = pCtx->cr0;
1344	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1345	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1346	}
1347
1348	return hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
1349	}
1350	#endif
1351
1352
1353	/**
1354	* Loads the guest segment registers into the VMCB.
1355	*
1356	* @returns VBox status code.
1357	* @param pVCpu The cross context virtual CPU structure.
1358	* @param pVmcb Pointer to the VM control block.
1359	* @param pCtx Pointer to the guest-CPU context.
1360	*
1361	* @remarks No-long-jump zone!!!
1362	*/
1363	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1364	{
1365	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1366	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1367	{
1368	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1369	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1370	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1371	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1372	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1373	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1374
1375	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1376	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1377	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1378	}
1379
1380	/* Guest TR. */
1381	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1382	{
1383	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1384	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1385	}
1386
1387	/* Guest LDTR. */
1388	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1389	{
1390	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1391	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1392	}
1393
1394	/* Guest GDTR. */
1395	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1396	{
1397	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1398	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1399	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1400	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1401	}
1402
1403	/* Guest IDTR. */
1404	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1405	{
1406	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1407	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1408	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1409	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1410	}
1411	}
1412
1413
1414	/**
1415	* Loads the guest MSRs into the VMCB.
1416	*
1417	* @param pVCpu The cross context virtual CPU structure.
1418	* @param pVmcb Pointer to the VM control block.
1419	* @param pCtx Pointer to the guest-CPU context.
1420	*
1421	* @remarks No-long-jump zone!!!
1422	*/
1423	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1424	{
1425	/* Guest Sysenter MSRs. */
1426	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1427	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1428	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1429
1430	/*
1431	* Guest EFER MSR.
1432	* AMD-V requires guest EFER.SVME to be set. Weird.
1433	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1434	*/
1435	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1436	{
1437	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1438	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1439	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1440	}
1441
1442	/* 64-bit MSRs. */
1443	if (CPUMIsGuestInLongModeEx(pCtx))
1444	{
1445	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1446	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1447	}
1448	else
1449	{
1450	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1451	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1452	{
1453	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1454	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1455	}
1456	}
1457
1458	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1459	* be writable in 32-bit mode. Clarify with AMD spec. */
1460	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1461	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1462	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1463	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1464	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1465	}
1466
1467
1468	/**
1469	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1470	* necessary intercepts accordingly.
1471	*
1472	* @param pVCpu The cross context virtual CPU structure.
1473	* @param pVmcb Pointer to the VM control block.
1474	* @param pCtx Pointer to the guest-CPU context.
1475	*
1476	* @remarks No-long-jump zone!!!
1477	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1478	*/
1479	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1480	{
1481	bool fInterceptMovDRx = false;
1482
1483	/*
1484	* Anyone single stepping on the host side? If so, we'll have to use the
1485	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1486	* the VMM level like the VT-x implementations does.
1487	*/
1488	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1489	if (fStepping)
1490	{
1491	pVCpu->hm.s.fClearTrapFlag = true;
1492	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1493	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1494	}
1495	else
1496	Assert(!DBGFIsStepping(pVCpu));
1497
1498	if ( fStepping
1499	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1500	{
1501	/*
1502	* Use the combined guest and host DRx values found in the hypervisor
1503	* register set because the debugger has breakpoints active or someone
1504	* is single stepping on the host side.
1505	*
1506	* Note! DBGF expects a clean DR6 state before executing guest code.
1507	*/
1508	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1509	if ( CPUMIsGuestInLongModeEx(pCtx)
1510	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1511	{
1512	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1513	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1514	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1515	}
1516	else
1517	#endif
1518	if (!CPUMIsHyperDebugStateActive(pVCpu))
1519	{
1520	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1521	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1522	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1523	}
1524
1525	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1526	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1527	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1528	{
1529	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1530	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1531	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1532	pVCpu->hm.s.fUsingHyperDR7 = true;
1533	}
1534
1535	/** @todo If we cared, we could optimize to allow the guest to read registers
1536	* with the same values. */
1537	fInterceptMovDRx = true;
1538	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1539	}
1540	else
1541	{
1542	/*
1543	* Update DR6, DR7 with the guest values if necessary.
1544	*/
1545	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1546	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1547	{
1548	pVmcb->guest.u64DR7 = pCtx->dr[7];
1549	pVmcb->guest.u64DR6 = pCtx->dr[6];
1550	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1551	pVCpu->hm.s.fUsingHyperDR7 = false;
1552	}
1553
1554	/*
1555	* If the guest has enabled debug registers, we need to load them prior to
1556	* executing guest code so they'll trigger at the right time.
1557	*/
1558	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1559	{
1560	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1561	if ( CPUMIsGuestInLongModeEx(pCtx)
1562	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1563	{
1564	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1565	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1566	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1567	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1568	}
1569	else
1570	#endif
1571	if (!CPUMIsGuestDebugStateActive(pVCpu))
1572	{
1573	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1574	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1575	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1576	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1577	}
1578	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1579	}
1580	/*
1581	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1582	* intercept #DB as DR6 is updated in the VMCB.
1583	*
1584	* Note! If we cared and dared, we could skip intercepting \#DB here.
1585	* However, \#DB shouldn't be performance critical, so we'll play safe
1586	* and keep the code similar to the VT-x code and always intercept it.
1587	*/
1588	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1589	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1590	&& !CPUMIsGuestDebugStateActive(pVCpu))
1591	#else
1592	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1593	#endif
1594	{
1595	fInterceptMovDRx = true;
1596	}
1597	}
1598
1599	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1600	if (fInterceptMovDRx)
1601	{
1602	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1603	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1604	{
1605	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1606	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1607	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1608	}
1609	}
1610	else
1611	{
1612	if ( pVmcb->ctrl.u16InterceptRdDRx
1613	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1614	{
1615	pVmcb->ctrl.u16InterceptRdDRx = 0;
1616	pVmcb->ctrl.u16InterceptWrDRx = 0;
1617	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1618	}
1619	}
1620	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1621	}
1622
1623
1624	#ifdef VBOX_WITH_NESTED_HWVIRT
1625	/**
1626	* Loads the nested-guest APIC state (currently just the TPR).
1627	*
1628	* @param pVCpu The cross context virtual CPU structure.
1629	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1630	*/
1631	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1632	{
1633	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1634	{
1635	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1636	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1637	pVCpu->hm.s.svm.fSyncVTpr = false;
1638	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1639
1640	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1641	}
1642	}
1643	#endif
1644
1645	/**
1646	* Loads the guest APIC state (currently just the TPR).
1647	*
1648	* @returns VBox status code.
1649	* @param pVCpu The cross context virtual CPU structure.
1650	* @param pVmcb Pointer to the VM control block.
1651	* @param pCtx Pointer to the guest-CPU context.
1652	*/
1653	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1654	{
1655	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1656	return VINF_SUCCESS;
1657
1658	int rc = VINF_SUCCESS;
1659	PVM pVM = pVCpu->CTX_SUFF(pVM);
1660	if ( PDMHasApic(pVM)
1661	&& APICIsEnabled(pVCpu))
1662	{
1663	bool fPendingIntr;
1664	uint8_t u8Tpr;
1665	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1666	AssertRCReturn(rc, rc);
1667
1668	/* Assume that we need to trap all TPR accesses and thus need not check on
1669	every #VMEXIT if we should update the TPR. */
1670	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1671	pVCpu->hm.s.svm.fSyncVTpr = false;
1672
1673	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1674	if (pVM->hm.s.fTPRPatchingActive)
1675	{
1676	pCtx->msrLSTAR = u8Tpr;
1677	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1678
1679	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1680	if (fPendingIntr)
1681	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1682	else
1683	{
1684	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1685	pVCpu->hm.s.svm.fSyncVTpr = true;
1686	}
1687	}
1688	else
1689	{
1690	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1691	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1692
1693	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1694	if (fPendingIntr)
1695	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1696	else
1697	{
1698	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1699	pVCpu->hm.s.svm.fSyncVTpr = true;
1700	}
1701
1702	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1703	}
1704	}
1705
1706	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1707	return rc;
1708	}
1709
1710
1711	/**
1712	* Loads the exception interrupts required for guest (or nested-guest) execution in
1713	* the VMCB.
1714	*
1715	* @param pVCpu The cross context virtual CPU structure.
1716	* @param pVmcb Pointer to the VM control block.
1717	*/
1718	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb)
1719	{
1720	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1721	{
1722	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1723	if (pVCpu->hm.s.fGIMTrapXcptUD)
1724	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1725	else
1726	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1727
1728	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1729	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1730	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1731	else
1732	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_BP);
1733
1734	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1735	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1736	}
1737	}
1738
1739
1740	#ifdef VBOX_WITH_NESTED_HWVIRT
1741	/**
1742	* Loads the intercepts required for nested-guest execution in the VMCB.
1743	*
1744	* This merges the guest and nested-guest intercepts in a way that if the outer
1745	* guest intercepts an exception we need to intercept it in the nested-guest as
1746	* well and handle it accordingly.
1747	*
1748	* @param pVCpu The cross context virtual CPU structure.
1749	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1750	*/
1751	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1752	{
1753	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1754	{
1755	/* First, load the guest intercepts into the guest VMCB. */
1756	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1757	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb);
1758
1759	/* Next, merge the intercepts into the nested-guest VMCB. */
1760	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1761	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1762
1763	/*
1764	* CR3, CR4 reads and writes are intercepted as we modify them before
1765	* hardware-assisted SVM execution. In addition, PGM needs to be up to date
1766	* on paging mode changes in the nested-guest.
1767	*
1768	* CR0 writes are intercepted in case of paging mode changes. CR0 reads are not
1769	* intercepted as we currently don't modify CR0 while executing the nested-guest.
1770	*/
1771	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(4) \| RT_BIT(3);
1772	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(0);
1773
1774	/** @todo Figure out debugging with nested-guests, till then just intercept
1775	* all DR[0-15] accesses. */
1776	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
1777	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
1778
1779	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
1780	pVmcbNstGst->ctrl.u64InterceptCtrl \|= pVmcb->ctrl.u64InterceptCtrl
1781	\| HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS;
1782	/*
1783	* Remove control intercepts that we don't need while executing the nested-guest.
1784	*
1785	* VMMCALL when not intercepted raises a \#UD exception in the guest. However,
1786	* other SVM instructions like VMSAVE when not intercept can cause havoc on the
1787	* host as they can write to any location in physical memory, hence they always
1788	* need to be intercepted (they are included in HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS).
1789	*/
1790	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
1791	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
1792	pVmcbNstGst->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VMMCALL;
1793
1794	/* Remove exception intercepts that we don't need while executing the nested-guest. */
1795	pVmcbNstGst->ctrl.u32InterceptXcpt &= ~RT_BIT(X86_XCPT_UD);
1796
1797	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
1798	}
1799	}
1800	#endif
1801
1802
1803	/**
1804	* Sets up the appropriate function to run guest code.
1805	*
1806	* @returns VBox status code.
1807	* @param pVCpu The cross context virtual CPU structure.
1808	*
1809	* @remarks No-long-jump zone!!!
1810	*/
1811	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
1812	{
1813	if (CPUMIsGuestInLongMode(pVCpu))
1814	{
1815	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1816	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1817	#endif
1818	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1819	#if HC_ARCH_BITS == 32
1820	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1821	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1822	#else
1823	/* 64-bit host or hybrid host. */
1824	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1825	#endif
1826	}
1827	else
1828	{
1829	/* Guest is not in long mode, use the 32-bit handler. */
1830	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1831	}
1832	return VINF_SUCCESS;
1833	}
1834
1835
1836	/**
1837	* Enters the AMD-V session.
1838	*
1839	* @returns VBox status code.
1840	* @param pVM The cross context VM structure.
1841	* @param pVCpu The cross context virtual CPU structure.
1842	* @param pCpu Pointer to the CPU info struct.
1843	*/
1844	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1845	{
1846	AssertPtr(pVM);
1847	AssertPtr(pVCpu);
1848	Assert(pVM->hm.s.svm.fSupported);
1849	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1850	NOREF(pVM); NOREF(pCpu);
1851
1852	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1853	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1854
1855	pVCpu->hm.s.fLeaveDone = false;
1856	return VINF_SUCCESS;
1857	}
1858
1859
1860	/**
1861	* Thread-context callback for AMD-V.
1862	*
1863	* @param enmEvent The thread-context event.
1864	* @param pVCpu The cross context virtual CPU structure.
1865	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1866	* @thread EMT(pVCpu)
1867	*/
1868	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1869	{
1870	NOREF(fGlobalInit);
1871
1872	switch (enmEvent)
1873	{
1874	case RTTHREADCTXEVENT_OUT:
1875	{
1876	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1877	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1878	VMCPU_ASSERT_EMT(pVCpu);
1879
1880	/* No longjmps (log-flush, locks) in this fragile context. */
1881	VMMRZCallRing3Disable(pVCpu);
1882
1883	if (!pVCpu->hm.s.fLeaveDone)
1884	{
1885	hmR0SvmLeave(pVCpu);
1886	pVCpu->hm.s.fLeaveDone = true;
1887	}
1888
1889	/* Leave HM context, takes care of local init (term). */
1890	int rc = HMR0LeaveCpu(pVCpu);
1891	AssertRC(rc); NOREF(rc);
1892
1893	/* Restore longjmp state. */
1894	VMMRZCallRing3Enable(pVCpu);
1895	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
1896	break;
1897	}
1898
1899	case RTTHREADCTXEVENT_IN:
1900	{
1901	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1902	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1903	VMCPU_ASSERT_EMT(pVCpu);
1904
1905	/* No longjmps (log-flush, locks) in this fragile context. */
1906	VMMRZCallRing3Disable(pVCpu);
1907
1908	/*
1909	* Initialize the bare minimum state required for HM. This takes care of
1910	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1911	*/
1912	int rc = HMR0EnterCpu(pVCpu);
1913	AssertRC(rc); NOREF(rc);
1914	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1915
1916	pVCpu->hm.s.fLeaveDone = false;
1917
1918	/* Restore longjmp state. */
1919	VMMRZCallRing3Enable(pVCpu);
1920	break;
1921	}
1922
1923	default:
1924	break;
1925	}
1926	}
1927
1928
1929	/**
1930	* Saves the host state.
1931	*
1932	* @returns VBox status code.
1933	* @param pVM The cross context VM structure.
1934	* @param pVCpu The cross context virtual CPU structure.
1935	*
1936	* @remarks No-long-jump zone!!!
1937	*/
1938	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1939	{
1940	NOREF(pVM);
1941	NOREF(pVCpu);
1942	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1943	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1944	return VINF_SUCCESS;
1945	}
1946
1947
1948	/**
1949	* Loads the guest state into the VMCB.
1950	*
1951	* The CPU state will be loaded from these fields on every successful VM-entry.
1952	* Also sets up the appropriate VMRUN function to execute guest code based on
1953	* the guest CPU mode.
1954	*
1955	* @returns VBox status code.
1956	* @param pVM The cross context VM structure.
1957	* @param pVCpu The cross context virtual CPU structure.
1958	* @param pCtx Pointer to the guest-CPU context.
1959	*
1960	* @remarks No-long-jump zone!!!
1961	*/
1962	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1963	{
1964	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1965	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1966
1967	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1968
1969	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1970	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1971
1972	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1973	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1974
1975	pVmcb->guest.u64RIP = pCtx->rip;
1976	pVmcb->guest.u64RSP = pCtx->rsp;
1977	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1978	pVmcb->guest.u64RAX = pCtx->rax;
1979
1980	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1981	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1982
1983	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb);
1984
1985	rc = hmR0SvmSetupVMRunHandler(pVCpu);
1986	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1987
1988	/* Clear any unused and reserved bits. */
1989	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1990	\| HM_CHANGED_GUEST_RSP
1991	\| HM_CHANGED_GUEST_RFLAGS
1992	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1993	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1994	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1995	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1996	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1997	\| HM_CHANGED_SVM_RESERVED2
1998	\| HM_CHANGED_SVM_RESERVED3
1999	\| HM_CHANGED_SVM_RESERVED4);
2000
2001	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2002	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2003	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2004	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2005
2006	Log4(("hmR0SvmLoadGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32\n", pCtx->cs.Sel, pCtx->rip,
2007	pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
2008	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2009	return rc;
2010	}
2011
2012
2013	#ifdef VBOX_WITH_NESTED_HWVIRT
2014	/**
2015	* Caches the nested-guest VMCB fields before we modify them for execution using
2016	* hardware-assisted SVM.
2017	*
2018	* @param pCtx Pointer to the guest-CPU context.
2019	*
2020	* @sa HMSvmNstGstVmExitNotify.
2021	*/
2022	static void hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2023	{
2024	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2025	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2026	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2027	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2028
2029	/*
2030	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2031	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2032	*/
2033	if (!pNstGstVmcbCache->fValid)
2034	{
2035	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2036	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2037	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2038	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2039	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2040	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2041	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2042	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2043	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2044	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2045	pNstGstVmcbCache->u64VmcbCleanBits = pVmcbNstGstCtrl->u64VmcbCleanBits;
2046	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2047	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2048	pNstGstVmcbCache->NestedPagingCtrl = pVmcbNstGstCtrl->NestedPaging;
2049	pNstGstVmcbCache->fValid = true;
2050	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2051	}
2052	}
2053
2054
2055	/**
2056	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2057	*
2058	* @param pVCpu The cross context virtual CPU structure.
2059	* @param pCtx Pointer to the guest-CPU context.
2060	*/
2061	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2062	{
2063	RT_NOREF(pVCpu);
2064	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2065	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2066
2067	/*
2068	* First cache the nested-guest VMCB fields we may potentially modify.
2069	*/
2070	hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2071
2072	/*
2073	* The IOPM of the nested-guest can be ignored because the the guest always
2074	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2075	* into the nested-guest one and swap it back on the #VMEXIT.
2076	*/
2077	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2078
2079	/*
2080	* Load the host-physical address into the MSRPM rather than the nested-guest
2081	* physical address (currently we trap all MSRs in the nested-guest).
2082	*/
2083	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2084
2085	/*
2086	* Use the same nested-paging as the "outer" guest. We can't dynamically
2087	* switch off nested-paging suddenly while executing a VM (see assertion at the
2088	* end of Trap0eHandler in PGMAllBth.h).
2089	*/
2090	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2091	}
2092
2093
2094	/**
2095	* Loads the nested-guest state into the VMCB.
2096	*
2097	* @returns VBox status code.
2098	* @param pVCpu The cross context virtual CPU structure.
2099	* @param pCtx Pointer to the guest-CPU context.
2100	*
2101	* @remarks No-long-jump zone!!!
2102	*/
2103	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2104	{
2105	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2106
2107	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2108	Assert(pVmcbNstGst);
2109
2110	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2111
2112	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2113	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2114
2115	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2116	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2117	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2118	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2119
2120	int rc = hmR0SvmLoadGuestControlRegsNested(pVCpu, pVmcbNstGst, pCtx);
2121	AssertRCReturn(rc, rc);
2122
2123	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2124	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst);
2125
2126	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2127	AssertRCReturn(rc, rc);
2128
2129	/* Clear any unused and reserved bits. */
2130	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2131	\| HM_CHANGED_GUEST_RSP
2132	\| HM_CHANGED_GUEST_RFLAGS
2133	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2134	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2135	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2136	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2137	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2138	\| HM_CHANGED_SVM_RESERVED2
2139	\| HM_CHANGED_SVM_RESERVED3
2140	\| HM_CHANGED_SVM_RESERVED4);
2141
2142	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2143	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2144	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2145	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2146
2147	Log4(("hmR0SvmLoadGuestStateNested: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 (HyperCR3=%#RX64) CR4=%#RX32 rc=%d\n",
2148	pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pVmcbNstGst->guest.u64CR3, pCtx->cr4, rc));
2149	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2150	return rc;
2151	}
2152	#endif
2153
2154
2155	/**
2156	* Loads the state shared between the host and guest or nested-guest into the
2157	* VMCB.
2158	*
2159	* @param pVCpu The cross context virtual CPU structure.
2160	* @param pVmcb Pointer to the VM control block.
2161	* @param pCtx Pointer to the guest-CPU context.
2162	*
2163	* @remarks No-long-jump zone!!!
2164	*/
2165	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2166	{
2167	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2168	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2169
2170	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2171	{
2172	#ifdef VBOX_WITH_NESTED_HWVIRT
2173	/* We use nested-guest CR0 unmodified, hence nothing to do here. */
2174	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2175	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2176	else
2177	Assert(pVmcb->guest.u64CR0 == pCtx->cr0);
2178	#else
2179	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2180	#endif
2181	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2182	}
2183
2184	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2185	{
2186	/* We use nested-guest CR0 unmodified, hence nothing to do here. */
2187	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2188	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2189	else
2190	{
2191	pVmcb->guest.u64DR6 = pCtx->dr[6];
2192	pVmcb->guest.u64DR7 = pCtx->dr[7];
2193	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2194	}
2195
2196	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2197	}
2198
2199	/* Unused on AMD-V. */
2200	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2201
2202	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2203	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2204	}
2205
2206
2207	/**
2208	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU context.
2209	*
2210	* Currently there is no residual state left in the CPU that is not updated in the
2211	* VMCB.
2212	*
2213	* @returns VBox status code.
2214	* @param pVCpu The cross context virtual CPU structure.
2215	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2216	* out-of-sync. Make sure to update the required fields
2217	* before using them.
2218	* @param pVmcb Pointer to the VM control block.
2219	*/
2220	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2221	{
2222	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2223
2224	pMixedCtx->rip = pVmcb->guest.u64RIP;
2225	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2226	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2227	pMixedCtx->rax = pVmcb->guest.u64RAX;
2228
2229	/*
2230	* Guest interrupt shadow.
2231	*/
2232	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
2233	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2234	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2235	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2236
2237	/*
2238	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2239	*/
2240	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2241
2242	#ifdef VBOX_WITH_NESTED_GUEST
2243	/*
2244	* The nested hypervisor might not be intercepting these control registers,
2245	*/
2246	if (CPUMIsGuestInNestedHwVirtMode(pMixedCtx))
2247	{
2248	pMixedCtx->cr4 = pVmcb->guest.u64CR4;
2249	pMixedCtx->cr0 = pVmcb->guest.u64CR0;
2250	}
2251	#endif
2252
2253	/*
2254	* Guest MSRs.
2255	*/
2256	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2257	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2258	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2259	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2260	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2261	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2262	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2263	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2264
2265	/*
2266	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2267	*/
2268	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2269	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2270	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2271	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2272	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2273	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2274
2275	/*
2276	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2277	* register (yet).
2278	*/
2279	/** @todo SELM might need to be fixed as it too should not care about the
2280	* granularity bit. See @bugref{6785}. */
2281	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2282	&& pMixedCtx->cs.Attr.n.u1Present
2283	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2284	{
2285	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2286	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2287	}
2288
2289	#ifdef VBOX_STRICT
2290	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
2291	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
2292	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
2293	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
2294	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
2295	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
2296	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
2297
2298	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2299	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2300	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2301	HMSVM_ASSERT_SEG_GRANULARITY(es);
2302	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2303	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2304
2305	# undef HMSVM_ASSERT_SEL_GRANULARITY
2306	#endif
2307
2308	/*
2309	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2310	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2311	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2312	* See AMD spec. 15.5.1 "Basic operation".
2313	*/
2314	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2315	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2316
2317	/*
2318	* Guest TR.
2319	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2320	* between Intel and AMD. See @bugref{6208#c39}.
2321	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2322	*/
2323	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2324	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2325	{
2326	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2327	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2328	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2329	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2330	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2331	}
2332
2333	/*
2334	* Guest Descriptor-Table registers.
2335	*/
2336	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2337	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2338	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2339
2340	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2341	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2342
2343	/*
2344	* Guest Debug registers.
2345	*/
2346	if (!pVCpu->hm.s.fUsingHyperDR7)
2347	{
2348	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2349	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2350	}
2351	else
2352	{
2353	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2354	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2355	}
2356
2357	/*
2358	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2359	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2360	*/
2361	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2362	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2363	{
2364	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2365	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2366	}
2367	}
2368
2369
2370	/**
2371	* Does the necessary state syncing before returning to ring-3 for any reason
2372	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2373	*
2374	* @param pVCpu The cross context virtual CPU structure.
2375	*
2376	* @remarks No-long-jmp zone!!!
2377	*/
2378	static void hmR0SvmLeave(PVMCPU pVCpu)
2379	{
2380	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2381	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2382	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2383
2384	/*
2385	* !!! IMPORTANT !!!
2386	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2387	*/
2388
2389	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2390	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2391	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2392
2393	/*
2394	* Restore host debug registers if necessary and resync on next R0 reentry.
2395	*/
2396	#ifdef VBOX_STRICT
2397	if (CPUMIsHyperDebugStateActive(pVCpu))
2398	{
2399	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2400	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2401	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2402	}
2403	#endif
2404	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2405	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2406
2407	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2408	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2409
2410	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2411	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2412	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2413	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2414	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2415
2416	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2417	}
2418
2419
2420	/**
2421	* Leaves the AMD-V session.
2422	*
2423	* @returns VBox status code.
2424	* @param pVCpu The cross context virtual CPU structure.
2425	*/
2426	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2427	{
2428	HM_DISABLE_PREEMPT();
2429	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2430	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2431
2432	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2433	and done this from the SVMR0ThreadCtxCallback(). */
2434	if (!pVCpu->hm.s.fLeaveDone)
2435	{
2436	hmR0SvmLeave(pVCpu);
2437	pVCpu->hm.s.fLeaveDone = true;
2438	}
2439
2440	/*
2441	* !!! IMPORTANT !!!
2442	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2443	*/
2444
2445	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2446	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2447	VMMR0ThreadCtxHookDisable(pVCpu);
2448
2449	/* Leave HM context. This takes care of local init (term). */
2450	int rc = HMR0LeaveCpu(pVCpu);
2451
2452	HM_RESTORE_PREEMPT();
2453	return rc;
2454	}
2455
2456
2457	/**
2458	* Does the necessary state syncing before doing a longjmp to ring-3.
2459	*
2460	* @returns VBox status code.
2461	* @param pVCpu The cross context virtual CPU structure.
2462	*
2463	* @remarks No-long-jmp zone!!!
2464	*/
2465	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2466	{
2467	return hmR0SvmLeaveSession(pVCpu);
2468	}
2469
2470
2471	/**
2472	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2473	* any remaining host state) before we longjump to ring-3 and possibly get
2474	* preempted.
2475	*
2476	* @param pVCpu The cross context virtual CPU structure.
2477	* @param enmOperation The operation causing the ring-3 longjump.
2478	* @param pvUser The user argument (pointer to the possibly
2479	* out-of-date guest-CPU context).
2480	*/
2481	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2482	{
2483	RT_NOREF_PV(pvUser);
2484
2485	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2486	{
2487	/*
2488	* !!! IMPORTANT !!!
2489	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2490	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2491	*/
2492	VMMRZCallRing3RemoveNotification(pVCpu);
2493	VMMRZCallRing3Disable(pVCpu);
2494	HM_DISABLE_PREEMPT();
2495
2496	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2497	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2498
2499	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2500	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2501
2502	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2503	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2504	VMMR0ThreadCtxHookDisable(pVCpu);
2505
2506	/* Leave HM context. This takes care of local init (term). */
2507	HMR0LeaveCpu(pVCpu);
2508
2509	HM_RESTORE_PREEMPT();
2510	return VINF_SUCCESS;
2511	}
2512
2513	Assert(pVCpu);
2514	Assert(pvUser);
2515	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2516	HMSVM_ASSERT_PREEMPT_SAFE();
2517
2518	VMMRZCallRing3Disable(pVCpu);
2519	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2520
2521	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2522	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2523	AssertRCReturn(rc, rc);
2524
2525	VMMRZCallRing3Enable(pVCpu);
2526	return VINF_SUCCESS;
2527	}
2528
2529
2530	/**
2531	* Take necessary actions before going back to ring-3.
2532	*
2533	* An action requires us to go back to ring-3. This function does the necessary
2534	* steps before we can safely return to ring-3. This is not the same as longjmps
2535	* to ring-3, this is voluntary.
2536	*
2537	* @returns VBox status code.
2538	* @param pVM The cross context VM structure.
2539	* @param pVCpu The cross context virtual CPU structure.
2540	* @param pCtx Pointer to the guest-CPU context.
2541	* @param rcExit The reason for exiting to ring-3. Can be
2542	* VINF_VMM_UNKNOWN_RING3_CALL.
2543	*/
2544	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2545	{
2546	Assert(pVM);
2547	Assert(pVCpu);
2548	Assert(pCtx);
2549	HMSVM_ASSERT_PREEMPT_SAFE();
2550
2551	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2552	VMMRZCallRing3Disable(pVCpu);
2553	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2554
2555	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2556	if (pVCpu->hm.s.Event.fPending)
2557	{
2558	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2559	Assert(!pVCpu->hm.s.Event.fPending);
2560	}
2561
2562	/* Sync. the necessary state for going back to ring-3. */
2563	hmR0SvmLeaveSession(pVCpu);
2564	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2565
2566	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2567	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2568	\| CPUM_CHANGED_LDTR
2569	\| CPUM_CHANGED_GDTR
2570	\| CPUM_CHANGED_IDTR
2571	\| CPUM_CHANGED_TR
2572	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2573	if ( pVM->hm.s.fNestedPaging
2574	&& CPUMIsGuestPagingEnabledEx(pCtx))
2575	{
2576	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2577	}
2578
2579	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2580	if (rcExit != VINF_EM_RAW_INTERRUPT)
2581	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2582
2583	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2584
2585	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2586	VMMRZCallRing3RemoveNotification(pVCpu);
2587	VMMRZCallRing3Enable(pVCpu);
2588
2589	/*
2590	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2591	* and if we're injecting an event we should have a TRPM trap pending.
2592	*/
2593	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2594	pVCpu->hm.s.u32HMError = rcExit,
2595	VERR_SVM_IPE_5);
2596	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2597	pVCpu->hm.s.u32HMError = rcExit,
2598	VERR_SVM_IPE_4);
2599
2600	return rcExit;
2601	}
2602
2603
2604	/**
2605	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2606	* intercepts.
2607	*
2608	* @param pVM The cross context VM structure.
2609	* @param pVCpu The cross context virtual CPU structure.
2610	* @param pVmcb Pointer to the VM control block.
2611	*
2612	* @remarks No-long-jump zone!!!
2613	*/
2614	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2615	{
2616	bool fParavirtTsc;
2617	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2618	if (fCanUseRealTsc)
2619	{
2620	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2621	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2622	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2623	}
2624	else
2625	{
2626	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2627	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2628	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2629	}
2630	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2631
2632	/** @todo later optimize this to be done elsewhere and not before every
2633	* VM-entry. */
2634	if (fParavirtTsc)
2635	{
2636	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2637	information before every VM-entry, hence disable it for performance sake. */
2638	#if 0
2639	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2640	AssertRC(rc);
2641	#endif
2642	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2643	}
2644	}
2645
2646
2647	/**
2648	* Sets an event as a pending event to be injected into the guest.
2649	*
2650	* @param pVCpu The cross context virtual CPU structure.
2651	* @param pEvent Pointer to the SVM event.
2652	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2653	* page-fault.
2654	*
2655	* @remarks Statistics counter assumes this is a guest event being reflected to
2656	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2657	*/
2658	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2659	{
2660	Assert(!pVCpu->hm.s.Event.fPending);
2661	Assert(pEvent->n.u1Valid);
2662
2663	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2664	pVCpu->hm.s.Event.fPending = true;
2665	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2666
2667	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2668	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2669	}
2670
2671
2672	/**
2673	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
2674	*
2675	* @param pVCpu The cross context virtual CPU structure.
2676	*/
2677	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
2678	{
2679	SVMEVENT Event;
2680	Event.u = 0;
2681	Event.n.u1Valid = 1;
2682	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2683	Event.n.u8Vector = X86_XCPT_UD;
2684	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2685	}
2686
2687
2688	/**
2689	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
2690	*
2691	* @param pVCpu The cross context virtual CPU structure.
2692	*/
2693	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
2694	{
2695	SVMEVENT Event;
2696	Event.u = 0;
2697	Event.n.u1Valid = 1;
2698	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2699	Event.n.u8Vector = X86_XCPT_DB;
2700	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2701	}
2702
2703
2704	/**
2705	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
2706	*
2707	* @param pVCpu The cross context virtual CPU structure.
2708	* @param pCtx Pointer to the guest-CPU context.
2709	* @param u32ErrCode The error-code for the page-fault.
2710	* @param uFaultAddress The page fault address (CR2).
2711	*
2712	* @remarks This updates the guest CR2 with @a uFaultAddress!
2713	*/
2714	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
2715	{
2716	SVMEVENT Event;
2717	Event.u = 0;
2718	Event.n.u1Valid = 1;
2719	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2720	Event.n.u8Vector = X86_XCPT_PF;
2721	Event.n.u1ErrorCodeValid = 1;
2722	Event.n.u32ErrorCode = u32ErrCode;
2723
2724	/* Update CR2 of the guest. */
2725	if (pCtx->cr2 != uFaultAddress)
2726	{
2727	pCtx->cr2 = uFaultAddress;
2728	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
2729	}
2730
2731	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
2732	}
2733
2734
2735	/**
2736	* Sets a device-not-available (\#NM) exception as pending-for-injection into
2737	* the VM.
2738	*
2739	* @param pVCpu The cross context virtual CPU structure.
2740	*/
2741	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
2742	{
2743	SVMEVENT Event;
2744	Event.u = 0;
2745	Event.n.u1Valid = 1;
2746	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2747	Event.n.u8Vector = X86_XCPT_NM;
2748	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2749	}
2750
2751
2752	/**
2753	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
2754	*
2755	* @param pVCpu The cross context virtual CPU structure.
2756	*/
2757	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
2758	{
2759	SVMEVENT Event;
2760	Event.u = 0;
2761	Event.n.u1Valid = 1;
2762	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2763	Event.n.u8Vector = X86_XCPT_MF;
2764	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2765	}
2766
2767
2768	/**
2769	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
2770	*
2771	* @param pVCpu The cross context virtual CPU structure.
2772	*/
2773	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
2774	{
2775	SVMEVENT Event;
2776	Event.u = 0;
2777	Event.n.u1Valid = 1;
2778	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2779	Event.n.u8Vector = X86_XCPT_DF;
2780	Event.n.u1ErrorCodeValid = 1;
2781	Event.n.u32ErrorCode = 0;
2782	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2783	}
2784
2785
2786	/**
2787	* Injects an event into the guest upon VMRUN by updating the relevant field
2788	* in the VMCB.
2789	*
2790	* @param pVCpu The cross context virtual CPU structure.
2791	* @param pVmcb Pointer to the guest VM control block.
2792	* @param pCtx Pointer to the guest-CPU context.
2793	* @param pEvent Pointer to the event.
2794	*
2795	* @remarks No-long-jump zone!!!
2796	* @remarks Requires CR0!
2797	*/
2798	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2799	{
2800	NOREF(pVCpu); NOREF(pCtx);
2801
2802	pVmcb->ctrl.EventInject.u = pEvent->u;
2803	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2804
2805	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2806	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2807	}
2808
2809
2810
2811	/**
2812	* Converts any TRPM trap into a pending HM event. This is typically used when
2813	* entering from ring-3 (not longjmp returns).
2814	*
2815	* @param pVCpu The cross context virtual CPU structure.
2816	*/
2817	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2818	{
2819	Assert(TRPMHasTrap(pVCpu));
2820	Assert(!pVCpu->hm.s.Event.fPending);
2821
2822	uint8_t uVector;
2823	TRPMEVENT enmTrpmEvent;
2824	RTGCUINT uErrCode;
2825	RTGCUINTPTR GCPtrFaultAddress;
2826	uint8_t cbInstr;
2827
2828	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2829	AssertRC(rc);
2830
2831	SVMEVENT Event;
2832	Event.u = 0;
2833	Event.n.u1Valid = 1;
2834	Event.n.u8Vector = uVector;
2835
2836	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2837	if (enmTrpmEvent == TRPM_TRAP)
2838	{
2839	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2840	switch (uVector)
2841	{
2842	case X86_XCPT_NMI:
2843	{
2844	Event.n.u3Type = SVM_EVENT_NMI;
2845	break;
2846	}
2847
2848	case X86_XCPT_PF:
2849	case X86_XCPT_DF:
2850	case X86_XCPT_TS:
2851	case X86_XCPT_NP:
2852	case X86_XCPT_SS:
2853	case X86_XCPT_GP:
2854	case X86_XCPT_AC:
2855	{
2856	Event.n.u1ErrorCodeValid = 1;
2857	Event.n.u32ErrorCode = uErrCode;
2858	break;
2859	}
2860	}
2861	}
2862	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2863	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2864	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2865	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2866	else
2867	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2868
2869	rc = TRPMResetTrap(pVCpu);
2870	AssertRC(rc);
2871
2872	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2873	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2874
2875	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2876	}
2877
2878
2879	/**
2880	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2881	* AMD-V to execute any instruction.
2882	*
2883	* @param pVCpu The cross context virtual CPU structure.
2884	*/
2885	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2886	{
2887	Assert(pVCpu->hm.s.Event.fPending);
2888	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2889
2890	SVMEVENT Event;
2891	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2892
2893	uint8_t uVector = Event.n.u8Vector;
2894	uint8_t uVectorType = Event.n.u3Type;
2895	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
2896
2897	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2898
2899	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2900	AssertRC(rc);
2901
2902	if (Event.n.u1ErrorCodeValid)
2903	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2904
2905	if ( uVectorType == SVM_EVENT_EXCEPTION
2906	&& uVector == X86_XCPT_PF)
2907	{
2908	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2909	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2910	}
2911	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2912	{
2913	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2914	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2915	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2916	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2917	}
2918	pVCpu->hm.s.Event.fPending = false;
2919	}
2920
2921
2922	/**
2923	* Checks if the guest (or nested-guest) has an interrupt shadow active right
2924	* now.
2925	*
2926	* @returns true if the interrupt shadow is active, false otherwise.
2927	* @param pVCpu The cross context virtual CPU structure.
2928	* @param pCtx Pointer to the guest-CPU context.
2929	*
2930	* @remarks No-long-jump zone!!!
2931	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2932	*/
2933	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
2934	{
2935	/*
2936	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2937	* inhibit interrupts or clear any existing interrupt-inhibition.
2938	*/
2939	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2940	{
2941	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2942	{
2943	/*
2944	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2945	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2946	*/
2947	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2948	return false;
2949	}
2950	return true;
2951	}
2952	return false;
2953	}
2954
2955
2956	/**
2957	* Sets the virtual interrupt intercept control in the VMCB which
2958	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
2959	* receive interrupts.
2960	*
2961	* @param pVmcb Pointer to the VM control block.
2962	*/
2963	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2964	{
2965	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
2966	{
2967	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1; /* A virtual interrupt is pending. */
2968	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0; /* Vector not necessary as we #VMEXIT for delivering the interrupt. */
2969	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
2970	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2971
2972	Log4(("Setting VINTR intercept\n"));
2973	}
2974	}
2975
2976
2977	#if 0
2978	/**
2979	* Clears the virtual interrupt intercept control in the VMCB as
2980	* we are figured the guest is unable process any interrupts
2981	* at this point of time.
2982	*
2983	* @param pVmcb Pointer to the VM control block.
2984	*/
2985	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
2986	{
2987	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
2988	{
2989	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
2990	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2991	Log4(("Clearing VINTR intercept\n"));
2992	}
2993	}
2994	#endif
2995
2996
2997	/**
2998	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2999	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3000	* virtual NMIs.
3001	*
3002	* @param pVmcb Pointer to the VM control block.
3003	*/
3004	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3005	{
3006	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3007	{
3008	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3009	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3010
3011	Log4(("Setting IRET intercept\n"));
3012	}
3013	}
3014
3015
3016	/**
3017	* Clears the IRET intercept control in the VMCB.
3018	*
3019	* @param pVmcb Pointer to the VM control block.
3020	*/
3021	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3022	{
3023	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3024	{
3025	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3026	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3027
3028	Log4(("Clearing IRET intercept\n"));
3029	}
3030	}
3031
3032	#ifdef VBOX_WITH_NESTED_HWVIRT
3033	/**
3034	* Evaluates the event to be delivered to the nested-guest and sets it as the
3035	* pending event.
3036	*
3037	* @returns VBox strict status code.
3038	* @param pVCpu The cross context virtual CPU structure.
3039	* @param pCtx Pointer to the guest-CPU context.
3040	*/
3041	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3042	{
3043	Log4Func(("\n"));
3044
3045	Assert(!pVCpu->hm.s.Event.fPending);
3046
3047	bool const fGif = pCtx->hwvirt.svm.fGif;
3048	if (fGif)
3049	{
3050	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3051
3052	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3053
3054	/*
3055	* Check if the nested-guest can receive NMIs.
3056	* NMIs are higher priority than regular interrupts.
3057	*/
3058	/** @todo SMI. SMIs take priority over NMIs. */
3059	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3060	{
3061	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3062	if (fBlockNmi)
3063	hmR0SvmSetIretIntercept(pVmcbNstGst);
3064	else if (fIntShadow)
3065	{
3066	/** @todo Figure this out, how we shall manage virt. intercept if the
3067	* nested-guest already has one set and/or if we really need it? */
3068	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3069	}
3070	else
3071	{
3072	Log4(("Pending NMI\n"));
3073
3074	SVMEVENT Event;
3075	Event.u = 0;
3076	Event.n.u1Valid = 1;
3077	Event.n.u8Vector = X86_XCPT_NMI;
3078	Event.n.u3Type = SVM_EVENT_NMI;
3079
3080	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3081	hmR0SvmSetIretIntercept(pVmcbNstGst);
3082	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3083	return VINF_SUCCESS;
3084	}
3085	}
3086
3087	/*
3088	* Check if the nested-guest can receive external interrupts (generated by
3089	* the guest's PIC/APIC).
3090	*
3091	* External intercepts from the physical CPU are -always- intercepted when
3092	* executing using hardware-assisted SVM, see HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS.
3093	*
3094	* External interrupts that are generated for the outer guest may be intercepted
3095	* depending on how the nested-guest VMCB was programmed by guest software.
3096	*
3097	* Physical interrupts always take priority over virtual interrupts,
3098	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3099	*/
3100	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3101	&& !fIntShadow
3102	&& !pVCpu->hm.s.fSingleInstruction
3103	&& CPUMCanSvmNstGstTakePhysIntr(pCtx))
3104	{
3105	if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_INTR))
3106	{
3107	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3108	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3109	}
3110
3111	uint8_t u8Interrupt;
3112	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3113	if (RT_SUCCESS(rc))
3114	{
3115	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3116
3117	SVMEVENT Event;
3118	Event.u = 0;
3119	Event.n.u1Valid = 1;
3120	Event.n.u8Vector = u8Interrupt;
3121	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3122
3123	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3124	}
3125	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3126	{
3127	/*
3128	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3129	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3130	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3131	*/
3132	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3133	}
3134	else
3135	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3136	}
3137
3138	/*
3139	* Check if the nested-guest can receive virtual (injected by VMRUN) interrupts.
3140	* We can call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any
3141	* nested-guest VMCB interrupt control fields besides V_INTR_MASKING, see hmR0SvmVmRunCacheVmcb.
3142	*/
3143	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3144	&& CPUMCanSvmNstGstTakeVirtIntr(pCtx)
3145	&& CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_VINTR))
3146	{
3147	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3148	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3149	}
3150	}
3151
3152	return VINF_SUCCESS;
3153	}
3154	#endif
3155
3156	/**
3157	* Evaluates the event to be delivered to the guest and sets it as the pending
3158	* event.
3159	*
3160	* @param pVCpu The cross context virtual CPU structure.
3161	* @param pCtx Pointer to the guest-CPU context.
3162	*/
3163	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3164	{
3165	Assert(!pVCpu->hm.s.Event.fPending);
3166
3167	#ifdef VBOX_WITH_NESTED_HWVIRT
3168	bool const fGif = pCtx->hwvirt.svm.fGif;
3169	#else
3170	bool const fGif = true;
3171	#endif
3172	Log4Func(("fGif=%RTbool\n", fGif));
3173
3174	/*
3175	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3176	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3177	*/
3178	if (fGif)
3179	{
3180	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3181	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3182	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3183	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3184
3185	Log4Func(("fGif=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fGif, fBlockInt, fIntShadow,
3186	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3187
3188	/** @todo SMI. SMIs take priority over NMIs. */
3189	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3190	{
3191	if (fBlockNmi)
3192	hmR0SvmSetIretIntercept(pVmcb);
3193	else if (fIntShadow)
3194	hmR0SvmSetVirtIntrIntercept(pVmcb);
3195	else
3196	{
3197	Log4(("Pending NMI\n"));
3198
3199	SVMEVENT Event;
3200	Event.u = 0;
3201	Event.n.u1Valid = 1;
3202	Event.n.u8Vector = X86_XCPT_NMI;
3203	Event.n.u3Type = SVM_EVENT_NMI;
3204
3205	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3206	hmR0SvmSetIretIntercept(pVmcb);
3207	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3208	return;
3209	}
3210	}
3211	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3212	&& !pVCpu->hm.s.fSingleInstruction)
3213	{
3214	/*
3215	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3216	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3217	*/
3218	if ( !fBlockInt
3219	&& !fIntShadow)
3220	{
3221	uint8_t u8Interrupt;
3222	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3223	if (RT_SUCCESS(rc))
3224	{
3225	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3226
3227	SVMEVENT Event;
3228	Event.u = 0;
3229	Event.n.u1Valid = 1;
3230	Event.n.u8Vector = u8Interrupt;
3231	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3232
3233	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3234	}
3235	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3236	{
3237	/*
3238	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3239	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3240	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3241	*/
3242	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3243	}
3244	else
3245	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3246	}
3247	else
3248	hmR0SvmSetVirtIntrIntercept(pVmcb);
3249	}
3250	}
3251	}
3252
3253
3254	/**
3255	* Injects any pending events into the guest or nested-guest.
3256	*
3257	* @param pVCpu The cross context virtual CPU structure.
3258	* @param pCtx Pointer to the guest-CPU context.
3259	* @param pVmcb Pointer to the VM control block.
3260	*/
3261	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3262	{
3263	Assert(!TRPMHasTrap(pVCpu));
3264	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3265
3266	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3267
3268	/*
3269	* When executing the nested-guest, we avoid assertions on whether the
3270	* event injection is valid purely based on EFLAGS, as V_INTR_MASKING
3271	* affects the interpretation of interruptibility (see CPUMCanSvmNstGstTakePhysIntr).
3272	*/
3273	#ifndef VBOX_WITH_NESTED_HWVIRT
3274	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3275	#endif
3276
3277	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
3278	{
3279	SVMEVENT Event;
3280	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3281	Assert(Event.n.u1Valid);
3282
3283	#ifndef VBOX_WITH_NESTED_HWVIRT
3284	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3285	{
3286	Assert(!fBlockInt);
3287	Assert(!fIntShadow);
3288	}
3289	else if (Event.n.u3Type == SVM_EVENT_NMI)
3290	Assert(!fIntShadow);
3291	NOREF(fBlockInt);
3292	#else
3293	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3294	#endif
3295
3296	Log4(("Injecting pending HM event\n"));
3297	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3298	pVCpu->hm.s.Event.fPending = false;
3299
3300	#ifdef VBOX_WITH_STATISTICS
3301	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3302	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3303	else
3304	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3305	#endif
3306	}
3307
3308	/*
3309	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3310	*
3311	* For nested-guests: We need to update it too for the scenario where IEM executes
3312	* the nested-guest but execution later continues here with an interrupt shadow active.
3313	*/
3314	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
3315	}
3316
3317
3318	/**
3319	* Reports world-switch error and dumps some useful debug info.
3320	*
3321	* @param pVM The cross context VM structure.
3322	* @param pVCpu The cross context virtual CPU structure.
3323	* @param rcVMRun The return code from VMRUN (or
3324	* VERR_SVM_INVALID_GUEST_STATE for invalid
3325	* guest-state).
3326	* @param pCtx Pointer to the guest-CPU context.
3327	*/
3328	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3329	{
3330	NOREF(pCtx);
3331	HMSVM_ASSERT_PREEMPT_SAFE();
3332	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3333
3334	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3335	{
3336	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3337	#ifdef VBOX_STRICT
3338	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
3339	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3340	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3341	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3342	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3343	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3344	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3345	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3346	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3347	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3348
3349	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3350	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3351	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3352
3353	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3354	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3355	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
3356	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3357	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3358	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3359	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3360	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3361	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3362	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3363
3364	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
3365	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3366	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3367	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3368	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3369	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3370	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3371	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3372	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3373	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3374	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
3375	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3376	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3377	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3378	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3379	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3380	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3381
3382	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3383	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
3384
3385	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3386	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3387	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3388	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3389	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3390	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3391	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3392	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3393	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3394	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3395	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3396	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3397	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3398	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3399	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3400	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3401	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3402	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3403	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3404	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3405
3406	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3407	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3408
3409	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3410	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3411	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3412	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3413
3414	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3415	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3416
3417	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3418	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3419	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3420	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3421
3422	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3423	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3424	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3425	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3426	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3427	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3428	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3429
3430	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3431	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3432	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3433	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3434
3435	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3436	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3437	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3438
3439	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3440	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3441	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3442	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3443	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3444	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3445	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3446	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3447	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3448	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3449	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3450	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3451	#endif /* VBOX_STRICT */
3452	}
3453	else
3454	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3455
3456	NOREF(pVmcb);
3457	}
3458
3459
3460	/**
3461	* Check per-VM and per-VCPU force flag actions that require us to go back to
3462	* ring-3 for one reason or another.
3463	*
3464	* @returns VBox status code (information status code included).
3465	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3466	* ring-3.
3467	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3468	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3469	* interrupts)
3470	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3471	* all EMTs to be in ring-3.
3472	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3473	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3474	* to the EM loop.
3475	*
3476	* @param pVM The cross context VM structure.
3477	* @param pVCpu The cross context virtual CPU structure.
3478	* @param pCtx Pointer to the guest-CPU context.
3479	*/
3480	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3481	{
3482	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3483
3484	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3485	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3486	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3487
3488	/* Update pending interrupts into the APIC's IRR. */
3489	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3490	APICUpdatePendingInterrupts(pVCpu);
3491
3492	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3493	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3494	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3495	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3496	{
3497	/* Pending PGM C3 sync. */
3498	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3499	{
3500	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3501	if (rc != VINF_SUCCESS)
3502	{
3503	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3504	return rc;
3505	}
3506	}
3507
3508	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3509	/* -XXX- what was that about single stepping? */
3510	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3511	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3512	{
3513	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3514	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3515	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3516	return rc;
3517	}
3518
3519	/* Pending VM request packets, such as hardware interrupts. */
3520	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3521	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3522	{
3523	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3524	return VINF_EM_PENDING_REQUEST;
3525	}
3526
3527	/* Pending PGM pool flushes. */
3528	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3529	{
3530	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3531	return VINF_PGM_POOL_FLUSH_PENDING;
3532	}
3533
3534	/* Pending DMA requests. */
3535	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3536	{
3537	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3538	return VINF_EM_RAW_TO_R3;
3539	}
3540	}
3541
3542	return VINF_SUCCESS;
3543	}
3544
3545
3546	#ifdef VBOX_WITH_NESTED_HWVIRT
3547	/**
3548	* Does the preparations before executing nested-guest code in AMD-V.
3549	*
3550	* @returns VBox status code (informational status codes included).
3551	* @retval VINF_SUCCESS if we can proceed with running the guest.
3552	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3553	*
3554	* @param pVM The cross context VM structure.
3555	* @param pVCpu The cross context virtual CPU structure.
3556	* @param pCtx Pointer to the guest-CPU context.
3557	* @param pSvmTransient Pointer to the SVM transient structure.
3558	*
3559	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3560	* @sa hmR0SvmPreRunGuest.
3561	*/
3562	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3563	{
3564	HMSVM_ASSERT_PREEMPT_SAFE();
3565
3566	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3567	{
3568	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3569	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3570	return VINF_EM_RESCHEDULE_REM;
3571	#endif
3572	}
3573	else
3574	return VINF_SVM_VMEXIT;
3575
3576	/* Check force flag actions that might require us to go back to ring-3. */
3577	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3578	if (rc != VINF_SUCCESS)
3579	return rc;
3580
3581	if (TRPMHasTrap(pVCpu))
3582	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3583	else if (!pVCpu->hm.s.Event.fPending)
3584	{
3585	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3586	if (rcStrict != VINF_SUCCESS)
3587	return VBOXSTRICTRC_VAL(rcStrict);
3588	}
3589
3590	/*
3591	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3592	* Just do it in software, see @bugref{8411}.
3593	* NB: If we could continue a task switch exit we wouldn't need to do this.
3594	*/
3595	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3596	&& pVCpu->hm.s.Event.fPending
3597	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
3598	{
3599	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3600	}
3601
3602	/*
3603	* Load the nested-guest state.
3604	*/
3605	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
3606	AssertRCReturn(rc, rc);
3607	/** @todo Get new STAM counter for this? */
3608	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3609
3610	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fValid);
3611
3612	/*
3613	* No longjmps to ring-3 from this point on!!!
3614	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3615	* This also disables flushing of the R0-logger instance (if any).
3616	*/
3617	VMMRZCallRing3Disable(pVCpu);
3618
3619	/*
3620	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3621	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3622	*
3623	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3624	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3625	*
3626	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3627	* executing guest code.
3628	*/
3629	pSvmTransient->fEFlags = ASMIntDisableFlags();
3630	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3631	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3632	{
3633	ASMSetFlags(pSvmTransient->fEFlags);
3634	VMMRZCallRing3Enable(pVCpu);
3635	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3636	return VINF_EM_RAW_TO_R3;
3637	}
3638	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3639	{
3640	ASMSetFlags(pSvmTransient->fEFlags);
3641	VMMRZCallRing3Enable(pVCpu);
3642	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3643	return VINF_EM_RAW_INTERRUPT;
3644	}
3645
3646	/*
3647	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3648	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3649	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3650	*
3651	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3652	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3653	*/
3654	if (pVCpu->hm.s.Event.fPending)
3655	{
3656	SVMEVENT Event;
3657	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3658	if ( Event.n.u1Valid
3659	&& Event.n.u3Type == SVM_EVENT_NMI
3660	&& Event.n.u8Vector == X86_XCPT_NMI
3661	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3662	{
3663	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3664	}
3665	}
3666
3667	return VINF_SUCCESS;
3668	}
3669	#endif
3670
3671
3672	/**
3673	* Does the preparations before executing guest code in AMD-V.
3674	*
3675	* This may cause longjmps to ring-3 and may even result in rescheduling to the
3676	* recompiler. We must be cautious what we do here regarding committing
3677	* guest-state information into the VMCB assuming we assuredly execute the guest
3678	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
3679	* clearing the common-state (TRPM/forceflags), we must undo those changes so
3680	* that the recompiler can (and should) use them when it resumes guest
3681	* execution. Otherwise such operations must be done when we can no longer
3682	* exit to ring-3.
3683	*
3684	* @returns VBox status code (informational status codes included).
3685	* @retval VINF_SUCCESS if we can proceed with running the guest.
3686	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3687	*
3688	* @param pVM The cross context VM structure.
3689	* @param pVCpu The cross context virtual CPU structure.
3690	* @param pCtx Pointer to the guest-CPU context.
3691	* @param pSvmTransient Pointer to the SVM transient structure.
3692	*/
3693	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3694	{
3695	HMSVM_ASSERT_PREEMPT_SAFE();
3696	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
3697
3698	#if defined(VBOX_WITH_NESTED_HWVIRT) && defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM)
3699
3700	/* IEM only for executing nested guest, we shouldn't get here. */
3701	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3702	{
3703	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3704	return VINF_EM_RESCHEDULE_REM;
3705	}
3706	#endif
3707
3708	/* Check force flag actions that might require us to go back to ring-3. */
3709	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3710	if (rc != VINF_SUCCESS)
3711	return rc;
3712
3713	if (TRPMHasTrap(pVCpu))
3714	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3715	else if (!pVCpu->hm.s.Event.fPending)
3716	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
3717
3718	/*
3719	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3720	* Just do it in software, see @bugref{8411}.
3721	* NB: If we could continue a task switch exit we wouldn't need to do this.
3722	*/
3723	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
3724	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
3725	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3726
3727	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
3728	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3729	#endif
3730
3731	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3732	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3733	AssertRCReturn(rc, rc);
3734	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3735
3736	/*
3737	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3738	* so we can update it on the way back if the guest changed the TPR.
3739	*/
3740	if (pVCpu->hm.s.svm.fSyncVTpr)
3741	{
3742	if (pVM->hm.s.fTPRPatchingActive)
3743	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3744	else
3745	{
3746	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3747	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3748	}
3749	}
3750
3751	/*
3752	* No longjmps to ring-3 from this point on!!!
3753	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3754	* This also disables flushing of the R0-logger instance (if any).
3755	*/
3756	VMMRZCallRing3Disable(pVCpu);
3757
3758	/*
3759	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3760	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3761	*
3762	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3763	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3764	*
3765	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3766	* executing guest code.
3767	*/
3768	pSvmTransient->fEFlags = ASMIntDisableFlags();
3769	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3770	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3771	{
3772	ASMSetFlags(pSvmTransient->fEFlags);
3773	VMMRZCallRing3Enable(pVCpu);
3774	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3775	return VINF_EM_RAW_TO_R3;
3776	}
3777	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3778	{
3779	ASMSetFlags(pSvmTransient->fEFlags);
3780	VMMRZCallRing3Enable(pVCpu);
3781	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3782	return VINF_EM_RAW_INTERRUPT;
3783	}
3784
3785	/*
3786	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3787	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3788	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3789	*
3790	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3791	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3792	*/
3793	if (pVCpu->hm.s.Event.fPending)
3794	{
3795	SVMEVENT Event;
3796	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3797	if ( Event.n.u1Valid
3798	&& Event.n.u3Type == SVM_EVENT_NMI
3799	&& Event.n.u8Vector == X86_XCPT_NMI
3800	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3801	{
3802	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3803	}
3804	}
3805
3806	return VINF_SUCCESS;
3807	}
3808
3809
3810	#ifdef VBOX_WITH_NESTED_HWVIRT
3811	/**
3812	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
3813	* means there is no backing out to ring-3 or anywhere else at this point.
3814	*
3815	* @param pVM The cross context VM structure.
3816	* @param pVCpu The cross context virtual CPU structure.
3817	* @param pCtx Pointer to the guest-CPU context.
3818	* @param pSvmTransient Pointer to the SVM transient structure.
3819	*
3820	* @remarks Called with preemption disabled.
3821	* @remarks No-long-jump zone!!!
3822	*/
3823	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3824	{
3825	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3826	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3827	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3828
3829	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3830	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3831
3832	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3833	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
3834
3835	if ( pVCpu->hm.s.fPreloadGuestFpu
3836	&& !CPUMIsGuestFPUStateActive(pVCpu))
3837	{
3838	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3839	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3840	}
3841
3842	/* Load the state shared between host and nested-guest (FPU, debug). */
3843	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3844	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
3845
3846	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3847	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3848
3849	/* Setup TSC offsetting. */
3850	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3851	if ( pSvmTransient->fUpdateTscOffsetting
3852	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3853	{
3854	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcbNstGst);
3855	pSvmTransient->fUpdateTscOffsetting = false;
3856	}
3857
3858	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3859	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3860	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
3861
3862	/* Store status of the shared guest-host state at the time of VMRUN. */
3863	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3864	if (CPUMIsGuestInLongModeEx(pCtx))
3865	{
3866	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3867	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3868	}
3869	else
3870	#endif
3871	{
3872	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3873	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3874	}
3875	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3876
3877	/* The TLB flushing would've already been setup by the nested-hypervisor. */
3878	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3879	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
3880	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3881
3882	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3883
3884	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3885	to start executing. */
3886
3887	/*
3888	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3889	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3890	*
3891	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3892	*/
3893	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
3894	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3895	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
3896	{
3897	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3898	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3899	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3900	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3901	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3902	pSvmTransient->fRestoreTscAuxMsr = true;
3903	}
3904	else
3905	{
3906	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3907	pSvmTransient->fRestoreTscAuxMsr = false;
3908	}
3909
3910	/*
3911	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
3912	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
3913	*/
3914	if ( !(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
3915	\|\| !(pVM->cpum.ro.GuestFeatures.fSvmVmcbClean))
3916	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
3917	}
3918	#endif
3919
3920
3921	/**
3922	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3923	* means there is no backing out to ring-3 or anywhere else at this
3924	* point.
3925	*
3926	* @param pVM The cross context VM structure.
3927	* @param pVCpu The cross context virtual CPU structure.
3928	* @param pCtx Pointer to the guest-CPU context.
3929	* @param pSvmTransient Pointer to the SVM transient structure.
3930	*
3931	* @remarks Called with preemption disabled.
3932	* @remarks No-long-jump zone!!!
3933	*/
3934	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3935	{
3936	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3937	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3938	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3939
3940	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3941	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3942
3943	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3944	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
3945
3946	if ( pVCpu->hm.s.fPreloadGuestFpu
3947	&& !CPUMIsGuestFPUStateActive(pVCpu))
3948	{
3949	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3950	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3951	}
3952
3953	/* Load the state shared between host and guest (FPU, debug). */
3954	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3955	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3956
3957	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3958	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3959
3960	/* Setup TSC offsetting. */
3961	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3962	if ( pSvmTransient->fUpdateTscOffsetting
3963	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3964	{
3965	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
3966	pSvmTransient->fUpdateTscOffsetting = false;
3967	}
3968
3969	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3970	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3971	pVmcb->ctrl.u64VmcbCleanBits = 0;
3972
3973	/* Store status of the shared guest-host state at the time of VMRUN. */
3974	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3975	if (CPUMIsGuestInLongModeEx(pCtx))
3976	{
3977	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3978	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3979	}
3980	else
3981	#endif
3982	{
3983	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3984	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3985	}
3986	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3987
3988	/* Flush the appropriate tagged-TLB entries. */
3989	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3990	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
3991	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3992
3993	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3994
3995	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3996	to start executing. */
3997
3998	/*
3999	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4000	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4001	*
4002	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4003	*/
4004	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4005	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4006	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4007	{
4008	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4009	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4010	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4011	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4012	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4013	pSvmTransient->fRestoreTscAuxMsr = true;
4014	}
4015	else
4016	{
4017	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4018	pSvmTransient->fRestoreTscAuxMsr = false;
4019	}
4020
4021	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4022	if (!(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
4023	pVmcb->ctrl.u64VmcbCleanBits = 0;
4024	}
4025
4026
4027	/**
4028	* Wrapper for running the guest code in AMD-V.
4029	*
4030	* @returns VBox strict status code.
4031	* @param pVM The cross context VM structure.
4032	* @param pVCpu The cross context virtual CPU structure.
4033	* @param pCtx Pointer to the guest-CPU context.
4034	*
4035	* @remarks No-long-jump zone!!!
4036	*/
4037	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4038	{
4039	/*
4040	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4041	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4042	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4043	*/
4044	#ifdef VBOX_WITH_KERNEL_USING_XMM
4045	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4046	pVCpu->hm.s.svm.pfnVMRun);
4047	#else
4048	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4049	#endif
4050	}
4051
4052
4053	#ifdef VBOX_WITH_NESTED_HWVIRT
4054	/**
4055	* Wrapper for running the nested-guest code in AMD-V.
4056	*
4057	* @returns VBox strict status code.
4058	* @param pVM The cross context VM structure.
4059	* @param pVCpu The cross context virtual CPU structure.
4060	* @param pCtx Pointer to the guest-CPU context.
4061	*
4062	* @remarks No-long-jump zone!!!
4063	*/
4064	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4065	{
4066	/*
4067	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4068	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4069	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4070	*/
4071	#ifdef VBOX_WITH_KERNEL_USING_XMM
4072	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4073	pVCpu->hm.s.svm.pfnVMRun);
4074	#else
4075	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4076	#endif
4077	}
4078
4079
4080	/**
4081	* Performs some essential restoration of state after running nested-guest code in
4082	* AMD-V.
4083	*
4084	* @param pVM The cross context VM structure.
4085	* @param pVCpu The cross context virtual CPU structure.
4086	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4087	* out-of-sync. Make sure to update the required fields
4088	* before using them.
4089	* @param pSvmTransient Pointer to the SVM transient structure.
4090	* @param rcVMRun Return code of VMRUN.
4091	*
4092	* @remarks Called with interrupts disabled.
4093	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4094	* unconditionally when it is safe to do so.
4095	*/
4096	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4097	{
4098	RT_NOREF(pVM);
4099	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4100
4101	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4102	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4103
4104	/* TSC read must be done early for maximum accuracy. */
4105	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4106	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4107	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4108	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset);
4109
4110	if (pSvmTransient->fRestoreTscAuxMsr)
4111	{
4112	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4113	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4114	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4115	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4116	}
4117
4118	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4119	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4120	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4121
4122	Assert(!(ASMGetFlags() & X86_EFL_IF));
4123	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4124	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4125
4126	/* Mark the VMCB-state cache as unmodified by VMM. */
4127	pVmcbNstGstCtrl->u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4128
4129	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4130	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4131	{
4132	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4133	return;
4134	}
4135
4136	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4137	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4138	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4139	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4140
4141	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4142	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4143	guest-CPU context. */
4144
4145	/*
4146	* Currently, reload the entire nested-guest VMCB due to code that directly inspects
4147	* the nested-guest VMCB instead of the cache, e.g. hmR0SvmEvaluatePendingEventNested.
4148	*/
4149	HMSvmNstGstVmExitNotify(pVCpu, pVmcbNstGst);
4150	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4151	}
4152	#endif
4153
4154	/**
4155	* Performs some essential restoration of state after running guest code in
4156	* AMD-V.
4157	*
4158	* @param pVM The cross context VM structure.
4159	* @param pVCpu The cross context virtual CPU structure.
4160	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4161	* out-of-sync. Make sure to update the required fields
4162	* before using them.
4163	* @param pSvmTransient Pointer to the SVM transient structure.
4164	* @param rcVMRun Return code of VMRUN.
4165	*
4166	* @remarks Called with interrupts disabled.
4167	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4168	* unconditionally when it is safe to do so.
4169	*/
4170	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4171	{
4172	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4173
4174	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4175	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4176
4177	PSVMVMCB pVmcb =pVCpu->hm.s.svm.pVmcb;
4178	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4179
4180	/* TSC read must be done early for maximum accuracy. */
4181	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4182	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4183
4184	if (pSvmTransient->fRestoreTscAuxMsr)
4185	{
4186	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4187	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4188	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4189	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4190	}
4191
4192	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4193	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4194	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4195
4196	Assert(!(ASMGetFlags() & X86_EFL_IF));
4197	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4198	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4199
4200	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4201	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4202	{
4203	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4204	return;
4205	}
4206
4207	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4208	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4209	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4210	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4211
4212	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4213
4214	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4215	{
4216	if (pVCpu->hm.s.svm.fSyncVTpr)
4217	{
4218	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4219	if ( pVM->hm.s.fTPRPatchingActive
4220	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4221	{
4222	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4223	AssertRC(rc);
4224	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4225	}
4226	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4227	{
4228	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4229	AssertRC(rc);
4230	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4231	}
4232	}
4233	}
4234	}
4235
4236
4237	/**
4238	* Runs the guest code using AMD-V.
4239	*
4240	* @returns VBox status code.
4241	* @param pVM The cross context VM structure.
4242	* @param pVCpu The cross context virtual CPU structure.
4243	* @param pCtx Pointer to the guest-CPU context.
4244	* @param pcLoops Pointer to the number of executed loops.
4245	*/
4246	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4247	{
4248	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4249	Assert(pcLoops);
4250	Assert(*pcLoops <= cMaxResumeLoops);
4251
4252	SVMTRANSIENT SvmTransient;
4253	SvmTransient.fUpdateTscOffsetting = true;
4254
4255	int rc = VERR_INTERNAL_ERROR_5;
4256	for (;;)
4257	{
4258	Assert(!HMR0SuspendPending());
4259	HMSVM_ASSERT_CPU_SAFE();
4260
4261	/* Preparatory work for running guest code, this may force us to return
4262	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4263	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4264	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4265	if (rc != VINF_SUCCESS)
4266	break;
4267
4268	/*
4269	* No longjmps to ring-3 from this point on!!!
4270	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4271	* This also disables flushing of the R0-logger instance (if any).
4272	*/
4273	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4274	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4275
4276	/* Restore any residual host-state and save any bits shared between host
4277	and guest into the guest-CPU state. Re-enables interrupts! */
4278	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4279
4280	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4281	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4282	{
4283	if (rc == VINF_SUCCESS)
4284	rc = VERR_SVM_INVALID_GUEST_STATE;
4285	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4286	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4287	break;
4288	}
4289
4290	/* Handle the #VMEXIT. */
4291	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4292	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4293	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4294	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4295	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4296	if (rc != VINF_SUCCESS)
4297	break;
4298	if (++(*pcLoops) >= cMaxResumeLoops)
4299	{
4300	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4301	rc = VINF_EM_RAW_INTERRUPT;
4302	break;
4303	}
4304	}
4305
4306	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4307	return rc;
4308	}
4309
4310
4311	/**
4312	* Runs the guest code using AMD-V in single step mode.
4313	*
4314	* @returns VBox status code.
4315	* @param pVM The cross context VM structure.
4316	* @param pVCpu The cross context virtual CPU structure.
4317	* @param pCtx Pointer to the guest-CPU context.
4318	* @param pcLoops Pointer to the number of executed loops.
4319	*/
4320	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4321	{
4322	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4323	Assert(pcLoops);
4324	Assert(*pcLoops <= cMaxResumeLoops);
4325
4326	SVMTRANSIENT SvmTransient;
4327	SvmTransient.fUpdateTscOffsetting = true;
4328
4329	uint16_t uCsStart = pCtx->cs.Sel;
4330	uint64_t uRipStart = pCtx->rip;
4331
4332	int rc = VERR_INTERNAL_ERROR_5;
4333	for (;;)
4334	{
4335	Assert(!HMR0SuspendPending());
4336	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4337	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4338	(unsigned)RTMpCpuId(), *pcLoops));
4339
4340	/* Preparatory work for running guest code, this may force us to return
4341	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4342	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4343	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4344	if (rc != VINF_SUCCESS)
4345	break;
4346
4347	/*
4348	* No longjmps to ring-3 from this point on!!!
4349	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4350	* This also disables flushing of the R0-logger instance (if any).
4351	*/
4352	VMMRZCallRing3Disable(pVCpu);
4353	VMMRZCallRing3RemoveNotification(pVCpu);
4354	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4355
4356	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4357
4358	/*
4359	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4360	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4361	*/
4362	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4363	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4364	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4365	{
4366	if (rc == VINF_SUCCESS)
4367	rc = VERR_SVM_INVALID_GUEST_STATE;
4368	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4369	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4370	return rc;
4371	}
4372
4373	/* Handle the #VMEXIT. */
4374	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4375	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4376	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4377	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4378	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4379	if (rc != VINF_SUCCESS)
4380	break;
4381	if (++(*pcLoops) >= cMaxResumeLoops)
4382	{
4383	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4384	rc = VINF_EM_RAW_INTERRUPT;
4385	break;
4386	}
4387
4388	/*
4389	* Did the RIP change, if so, consider it a single step.
4390	* Otherwise, make sure one of the TFs gets set.
4391	*/
4392	if ( pCtx->rip != uRipStart
4393	\|\| pCtx->cs.Sel != uCsStart)
4394	{
4395	rc = VINF_EM_DBG_STEPPED;
4396	break;
4397	}
4398	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4399	}
4400
4401	/*
4402	* Clear the X86_EFL_TF if necessary.
4403	*/
4404	if (pVCpu->hm.s.fClearTrapFlag)
4405	{
4406	pVCpu->hm.s.fClearTrapFlag = false;
4407	pCtx->eflags.Bits.u1TF = 0;
4408	}
4409
4410	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4411	return rc;
4412	}
4413
4414	#ifdef VBOX_WITH_NESTED_HWVIRT
4415	/**
4416	* Runs the nested-guest code using AMD-V.
4417	*
4418	* @returns VBox status code.
4419	* @param pVM The cross context VM structure.
4420	* @param pVCpu The cross context virtual CPU structure.
4421	* @param pCtx Pointer to the guest-CPU context.
4422	* @param pcLoops Pointer to the number of executed loops. If we're switching
4423	* from the guest-code execution loop to this nested-guest
4424	* execution loop pass the remainder value, else pass 0.
4425	*/
4426	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4427	{
4428	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4429	Assert(pcLoops);
4430	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4431
4432	SVMTRANSIENT SvmTransient;
4433	SvmTransient.fUpdateTscOffsetting = true;
4434
4435	int rc = VERR_INTERNAL_ERROR_4;
4436	for (;;)
4437	{
4438	Assert(!HMR0SuspendPending());
4439	HMSVM_ASSERT_CPU_SAFE();
4440
4441	/* Preparatory work for running nested-guest code, this may force us to return
4442	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4443	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4444	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4445	if (rc != VINF_SUCCESS)
4446	break;
4447
4448	/*
4449	* No longjmps to ring-3 from this point on!!!
4450	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4451	* This also disables flushing of the R0-logger instance (if any).
4452	*/
4453	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4454
4455	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4456
4457	/* Restore any residual host-state and save any bits shared between host
4458	and guest into the guest-CPU state. Re-enables interrupts! */
4459	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4460
4461	/** @todo This needs some work... we probably should cause a \#VMEXIT on
4462	* SVM_EXIT_INVALID and handle rc != VINF_SUCCESS differently. */
4463	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4464	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4465	{
4466	if (rc == VINF_SUCCESS)
4467	rc = VERR_SVM_INVALID_GUEST_STATE;
4468	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4469	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4470	break;
4471	}
4472
4473	/* Handle the #VMEXIT. */
4474	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4475	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4476	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4477	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4478	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4479	if (rc != VINF_SUCCESS)
4480	break;
4481	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4482	{
4483	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4484	rc = VINF_EM_RAW_INTERRUPT;
4485	break;
4486	}
4487
4488	/** @todo handle single-stepping */
4489	}
4490
4491	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4492	return rc;
4493	}
4494	#endif
4495
4496
4497	/**
4498	* Runs the guest code using AMD-V.
4499	*
4500	* @returns Strict VBox status code.
4501	* @param pVM The cross context VM structure.
4502	* @param pVCpu The cross context virtual CPU structure.
4503	* @param pCtx Pointer to the guest-CPU context.
4504	*/
4505	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4506	{
4507	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4508	HMSVM_ASSERT_PREEMPT_SAFE();
4509	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4510
4511	uint32_t cLoops = 0;
4512	int rc;
4513	#ifdef VBOX_WITH_NESTED_HWVIRT
4514	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4515	#endif
4516	{
4517	if (!pVCpu->hm.s.fSingleInstruction)
4518	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4519	else
4520	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4521	}
4522	#ifdef VBOX_WITH_NESTED_HWVIRT
4523	else
4524	{
4525	rc = VINF_SVM_VMRUN;
4526	}
4527
4528	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4529	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4530	if (rc == VINF_SVM_VMRUN)
4531	{
4532	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4533	if (rc == VINF_SVM_VMEXIT)
4534	rc = VINF_SUCCESS;
4535	}
4536	#endif
4537
4538	/* Fixup error codes. */
4539	if (rc == VERR_EM_INTERPRETER)
4540	rc = VINF_EM_RAW_EMULATE_INSTR;
4541	else if (rc == VINF_EM_RESET)
4542	rc = VINF_EM_TRIPLE_FAULT;
4543
4544	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4545	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4546	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4547	return rc;
4548	}
4549
4550
4551	#ifdef VBOX_WITH_NESTED_HWVIRT
4552	/**
4553	* Determines whether an IOIO intercept is active for the nested-guest or not.
4554	*
4555	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4556	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4557	*/
4558	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4559	{
4560	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4561	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4562	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4563	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4564	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4565	const bool fRep = pIoExitInfo->n.u1REP;
4566	const bool fStrIo = pIoExitInfo->n.u1STR;
4567
4568	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4569	NULL /* pIoExitInfo */);
4570	}
4571
4572
4573	/**
4574	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4575	* SVM_EXIT_INVALID).
4576	*
4577	* @returns VBox status code (informational status codes included).
4578	* @param pVCpu The cross context virtual CPU structure.
4579	* @param pCtx Pointer to the guest-CPU context.
4580	* @param pSvmTransient Pointer to the SVM transient structure.
4581	*/
4582	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4583	{
4584	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4585	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4586
4587	#define HM_SVM_RET_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4588	do \
4589	{ \
4590	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2)); \
4591	} while (0) \
4592
4593	/*
4594	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4595	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
4596	*/
4597	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4598	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4599	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4600	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4601	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4602	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4603
4604	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4605	switch (uExitCode)
4606	{
4607	case SVM_EXIT_CPUID:
4608	{
4609	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_CPUID)
4610	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4611	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
4612	}
4613
4614	case SVM_EXIT_RDTSC:
4615	{
4616	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC)
4617	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4618	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
4619	}
4620
4621	case SVM_EXIT_RDTSCP:
4622	{
4623	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP)
4624	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4625	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
4626	}
4627
4628
4629	case SVM_EXIT_MONITOR:
4630	{
4631	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MONITOR)
4632	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4633	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
4634	}
4635
4636	case SVM_EXIT_MWAIT:
4637	{
4638	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MWAIT)
4639	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4640	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
4641	}
4642
4643	case SVM_EXIT_HLT:
4644	{
4645	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_HLT)
4646	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4647	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
4648	}
4649
4650	case SVM_EXIT_MSR:
4651	{
4652	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MSR_PROT)
4653	{
4654	uint32_t const idMsr = pCtx->ecx;
4655	uint16_t offMsrpm;
4656	uint32_t uMsrpmBit;
4657	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4658	if (RT_SUCCESS(rc))
4659	{
4660	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4661	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
4662	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
4663
4664	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4665	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4666	{
4667	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4668	}
4669	}
4670	else
4671	{
4672	/*
4673	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4674	* See AMD-V spec. "15.11 MSR Intercepts".
4675	*/
4676	Assert(rc == VERR_OUT_OF_RANGE);
4677	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4678	}
4679	}
4680	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
4681	}
4682
4683	case SVM_EXIT_IOIO:
4684	{
4685	/*
4686	* Figure out if the IO port access is intercepted by the nested-guest.
4687	*/
4688	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_IOIO_PROT)
4689	{
4690	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
4691	SVMIOIOEXITINFO IoExitInfo;
4692	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4693	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
4694	if (fIntercept)
4695	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4696	}
4697	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
4698	}
4699
4700	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
4701	{
4702	PVM pVM = pVCpu->CTX_SUFF(pVM);
4703	if (pVM->hm.s.fNestedPaging)
4704	{
4705	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4706	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4707
4708	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4709	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_PF))
4710	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4711
4712	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
4713	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4714	return VINF_SUCCESS;
4715	}
4716	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
4717	}
4718
4719	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
4720	{
4721	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_NM))
4722	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4723	hmR0SvmSetPendingXcptNM(pVCpu);
4724	return VINF_SUCCESS;
4725	}
4726
4727	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
4728	{
4729	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_UD))
4730	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4731	hmR0SvmSetPendingXcptUD(pVCpu);
4732	return VINF_SUCCESS;
4733	}
4734
4735	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
4736	{
4737	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_MF))
4738	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4739	hmR0SvmSetPendingXcptMF(pVCpu);
4740	return VINF_SUCCESS;
4741	}
4742
4743	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
4744	{
4745	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_DB))
4746	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4747	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
4748	}
4749
4750	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
4751	{
4752	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_AC))
4753	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4754	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
4755	}
4756
4757	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
4758	{
4759	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_BP))
4760	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4761	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
4762	}
4763
4764	case SVM_EXIT_READ_CR0:
4765	case SVM_EXIT_READ_CR3:
4766	case SVM_EXIT_READ_CR4:
4767	{
4768	if (pVmcbNstGstCache->u16InterceptRdCRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0)))
4769	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4770	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
4771	}
4772
4773	case SVM_EXIT_WRITE_CR0:
4774	case SVM_EXIT_WRITE_CR3:
4775	case SVM_EXIT_WRITE_CR4:
4776	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
4777	{
4778	Log4(("hmR0SvmHandleExitNested: Write CRx: u16InterceptWrCRx=%#x u64ExitCode=%#RX64 %#x\n",
4779	pVmcbNstGstCache->u16InterceptWrCRx, pSvmTransient->u64ExitCode,
4780	(1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0))));
4781	if (pVmcbNstGstCache->u16InterceptWrCRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)))
4782	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4783	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
4784	}
4785
4786	case SVM_EXIT_PAUSE:
4787	{
4788	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_PAUSE)
4789	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4790	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
4791	}
4792
4793	case SVM_EXIT_VINTR:
4794	{
4795	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
4796	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4797	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4798	}
4799
4800	case SVM_EXIT_INTR:
4801	{
4802	/* We shouldn't direct physical interrupts to the nested-guest. */
4803	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4804	}
4805
4806	case SVM_EXIT_FERR_FREEZE:
4807	{
4808	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_FERR_FREEZE)
4809	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4810	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4811	}
4812
4813	case SVM_EXIT_NMI:
4814	{
4815	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_NMI)
4816	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4817	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4818	}
4819
4820	case SVM_EXIT_INVLPG:
4821	{
4822	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVLPG)
4823	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4824	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
4825	}
4826
4827	case SVM_EXIT_WBINVD:
4828	{
4829	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_WBINVD)
4830	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4831	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
4832	}
4833
4834	case SVM_EXIT_INVD:
4835	{
4836	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVD)
4837	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4838	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
4839	}
4840
4841	case SVM_EXIT_RDPMC:
4842	{
4843	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDPMC)
4844	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4845	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
4846	}
4847
4848	default:
4849	{
4850	switch (pSvmTransient->u64ExitCode)
4851	{
4852	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
4853	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
4854	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
4855	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
4856	{
4857	if (pVmcbNstGstCache->u16InterceptRdDRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_DR0)))
4858	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4859	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4860	}
4861
4862	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
4863	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
4864	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
4865	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
4866	{
4867	if (pVmcbNstGstCache->u16InterceptWrDRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_DR0)))
4868	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4869	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
4870	}
4871
4872	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
4873	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
4874	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
4875	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
4876	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
4877	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
4878	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
4879	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
4880	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
4881	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
4882	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
4883	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
4884	{
4885	if (pVmcbNstGstCache->u32InterceptXcpt & (1U << (uint32_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0)))
4886	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4887	/** @todo Write hmR0SvmExitXcptGeneric! */
4888	return VERR_NOT_IMPLEMENTED;
4889	}
4890
4891	case SVM_EXIT_XSETBV:
4892	{
4893	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_XSETBV)
4894	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4895	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
4896	}
4897
4898	case SVM_EXIT_TASK_SWITCH:
4899	{
4900	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_TASK_SWITCH)
4901	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4902	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
4903	}
4904
4905	case SVM_EXIT_IRET:
4906	{
4907	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
4908	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4909	return hmR0SvmNestedExitIret(pVCpu, pCtx, pSvmTransient);
4910	}
4911
4912	case SVM_EXIT_SHUTDOWN:
4913	{
4914	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SHUTDOWN)
4915	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4916	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
4917	}
4918
4919	case SVM_EXIT_SMI:
4920	{
4921	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SMI)
4922	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4923	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4924	}
4925
4926	case SVM_EXIT_INIT:
4927	{
4928	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INIT)
4929	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4930	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4931	}
4932
4933	case SVM_EXIT_VMMCALL:
4934	{
4935	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMMCALL)
4936	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4937	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
4938	}
4939
4940	case SVM_EXIT_CLGI:
4941	{
4942	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_CLGI)
4943	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4944	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
4945	}
4946
4947	case SVM_EXIT_STGI:
4948	{
4949	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_STGI)
4950	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4951	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
4952	}
4953
4954	case SVM_EXIT_VMLOAD:
4955	{
4956	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMLOAD)
4957	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4958	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
4959	}
4960
4961	case SVM_EXIT_VMSAVE:
4962	{
4963	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMSAVE)
4964	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4965	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
4966	}
4967
4968	case SVM_EXIT_INVLPGA:
4969	{
4970	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVLPGA)
4971	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4972	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
4973	}
4974
4975	case SVM_EXIT_VMRUN:
4976	{
4977	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN)
4978	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4979	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
4980	}
4981
4982	case SVM_EXIT_RSM:
4983	{
4984	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RSM)
4985	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4986	hmR0SvmSetPendingXcptUD(pVCpu);
4987	return VINF_SUCCESS;
4988	}
4989
4990	case SVM_EXIT_SKINIT:
4991	{
4992	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SKINIT)
4993	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4994	hmR0SvmSetPendingXcptUD(pVCpu);
4995	return VINF_SUCCESS;
4996	}
4997
4998	case SVM_EXIT_NPF:
4999	{
5000	/* We don't yet support nested-paging for nested-guests, so this should never really happen. */
5001	Assert(!pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging);
5002	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5003	}
5004
5005	default:
5006	{
5007	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5008	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5009	return VERR_SVM_UNKNOWN_EXIT;
5010	}
5011	}
5012	}
5013	}
5014	/* not reached */
5015
5016	#undef HM_SVM_RET_VMEXIT_NESTED
5017	}
5018	#endif
5019
5020
5021	/**
5022	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5023	*
5024	* @returns VBox status code (informational status codes included).
5025	* @param pVCpu The cross context virtual CPU structure.
5026	* @param pCtx Pointer to the guest-CPU context.
5027	* @param pSvmTransient Pointer to the SVM transient structure.
5028	*/
5029	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5030	{
5031	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5032	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5033
5034	/*
5035	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5036	* normal workloads (for some definition of "normal").
5037	*/
5038	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
5039	switch (pSvmTransient->u64ExitCode)
5040	{
5041	case SVM_EXIT_NPF:
5042	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5043
5044	case SVM_EXIT_IOIO:
5045	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5046
5047	case SVM_EXIT_RDTSC:
5048	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5049
5050	case SVM_EXIT_RDTSCP:
5051	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5052
5053	case SVM_EXIT_CPUID:
5054	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5055
5056	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5057	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5058
5059	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5060	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5061
5062	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5063	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5064
5065	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5066	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5067
5068	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5069	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5070
5071	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5072	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5073
5074	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5075	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5076
5077	case SVM_EXIT_MONITOR:
5078	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5079
5080	case SVM_EXIT_MWAIT:
5081	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5082
5083	case SVM_EXIT_HLT:
5084	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5085
5086	case SVM_EXIT_READ_CR0:
5087	case SVM_EXIT_READ_CR3:
5088	case SVM_EXIT_READ_CR4:
5089	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5090
5091	case SVM_EXIT_WRITE_CR0:
5092	case SVM_EXIT_WRITE_CR3:
5093	case SVM_EXIT_WRITE_CR4:
5094	case SVM_EXIT_WRITE_CR8:
5095	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5096
5097	case SVM_EXIT_PAUSE:
5098	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5099
5100	case SVM_EXIT_VMMCALL:
5101	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5102
5103	case SVM_EXIT_VINTR:
5104	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5105
5106	case SVM_EXIT_INTR:
5107	case SVM_EXIT_FERR_FREEZE:
5108	case SVM_EXIT_NMI:
5109	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5110
5111	case SVM_EXIT_MSR:
5112	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5113
5114	case SVM_EXIT_INVLPG:
5115	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5116
5117	case SVM_EXIT_WBINVD:
5118	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5119
5120	case SVM_EXIT_INVD:
5121	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5122
5123	case SVM_EXIT_RDPMC:
5124	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5125
5126	default:
5127	{
5128	switch (pSvmTransient->u64ExitCode)
5129	{
5130	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5131	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5132	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5133	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5134	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5135
5136	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5137	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5138	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5139	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5140	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5141
5142	case SVM_EXIT_XSETBV:
5143	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5144
5145	case SVM_EXIT_TASK_SWITCH:
5146	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5147
5148	case SVM_EXIT_IRET:
5149	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5150
5151	case SVM_EXIT_SHUTDOWN:
5152	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5153
5154	case SVM_EXIT_SMI:
5155	case SVM_EXIT_INIT:
5156	{
5157	/*
5158	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5159	* If it ever does, we want to know about it so log the exit code and bail.
5160	*/
5161	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5162	}
5163
5164	#ifdef VBOX_WITH_NESTED_HWVIRT
5165	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5166	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5167	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5168	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5169	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5170	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5171	#else
5172	case SVM_EXIT_CLGI:
5173	case SVM_EXIT_STGI:
5174	case SVM_EXIT_VMLOAD:
5175	case SVM_EXIT_VMSAVE:
5176	case SVM_EXIT_INVLPGA:
5177	case SVM_EXIT_VMRUN:
5178	#endif
5179	case SVM_EXIT_RSM:
5180	case SVM_EXIT_SKINIT:
5181	{
5182	hmR0SvmSetPendingXcptUD(pVCpu);
5183	return VINF_SUCCESS;
5184	}
5185
5186	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5187	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5188	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5189	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5190	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5191	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5192	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5193	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5194	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5195	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5196	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5197	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5198	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5199	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5200	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5201	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5202	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5203	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5204	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5205	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5206	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5207	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5208	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5209	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5210	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5211	{
5212	/** @todo r=ramshankar; We should be doing
5213	* HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY here! */
5214
5215	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5216	SVMEVENT Event;
5217	Event.u = 0;
5218	Event.n.u1Valid = 1;
5219	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5220	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5221
5222	switch (Event.n.u8Vector)
5223	{
5224	case X86_XCPT_DE:
5225	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
5226	break;
5227
5228	case X86_XCPT_NP:
5229	Event.n.u1ErrorCodeValid = 1;
5230	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5231	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
5232	break;
5233
5234	case X86_XCPT_SS:
5235	Event.n.u1ErrorCodeValid = 1;
5236	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5237	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
5238	break;
5239
5240	case X86_XCPT_GP:
5241	Event.n.u1ErrorCodeValid = 1;
5242	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5243	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
5244	break;
5245
5246	default:
5247	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
5248	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
5249	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
5250	}
5251
5252	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
5253	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5254	return VINF_SUCCESS;
5255	}
5256	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5257
5258	default:
5259	{
5260	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
5261	pVCpu->hm.s.u32HMError = u32ExitCode;
5262	return VERR_SVM_UNKNOWN_EXIT;
5263	}
5264	}
5265	}
5266	}
5267	/* not reached */
5268	}
5269
5270
5271	#ifdef DEBUG
5272	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5273	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5274	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5275
5276	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5277	do \
5278	{ \
5279	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5280	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5281	} while (0)
5282
5283	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5284	do { \
5285	AssertPtr(pVCpu); \
5286	AssertPtr(pCtx); \
5287	AssertPtr(pSvmTransient); \
5288	Assert(ASMIntAreEnabled()); \
5289	HMSVM_ASSERT_PREEMPT_SAFE(); \
5290	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5291	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5292	HMSVM_ASSERT_PREEMPT_SAFE(); \
5293	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5294	HMSVM_ASSERT_PREEMPT_CPUID(); \
5295	} while (0)
5296	#else /* Release builds */
5297	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5298	#endif
5299
5300
5301	/**
5302	* Worker for hmR0SvmInterpretInvlpg().
5303	*
5304	* @return VBox status code.
5305	* @param pVCpu The cross context virtual CPU structure.
5306	* @param pCpu Pointer to the disassembler state.
5307	* @param pCtx The guest CPU context.
5308	*/
5309	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5310	{
5311	DISQPVPARAMVAL Param1;
5312	RTGCPTR GCPtrPage;
5313
5314	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5315	if (RT_FAILURE(rc))
5316	return VERR_EM_INTERPRETER;
5317
5318	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5319	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5320	{
5321	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5322	return VERR_EM_INTERPRETER;
5323
5324	GCPtrPage = Param1.val.val64;
5325	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5326	rc = VBOXSTRICTRC_VAL(rc2);
5327	}
5328	else
5329	{
5330	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5331	rc = VERR_EM_INTERPRETER;
5332	}
5333
5334	return rc;
5335	}
5336
5337
5338	/**
5339	* Interprets INVLPG.
5340	*
5341	* @returns VBox status code.
5342	* @retval VINF_* Scheduling instructions.
5343	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5344	* @retval VERR_* Fatal errors.
5345	*
5346	* @param pVM The cross context VM structure.
5347	* @param pVCpu The cross context virtual CPU structure.
5348	* @param pCtx The guest CPU context.
5349	*
5350	* @remarks Updates the RIP if the instruction was executed successfully.
5351	*/
5352	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5353	{
5354	/* Only allow 32 & 64 bit code. */
5355	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5356	{
5357	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5358	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5359	if ( RT_SUCCESS(rc)
5360	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5361	{
5362	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5363	if (RT_SUCCESS(rc))
5364	pCtx->rip += pDis->cbInstr;
5365	return rc;
5366	}
5367	else
5368	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5369	}
5370	return VERR_EM_INTERPRETER;
5371	}
5372
5373
5374	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5375	/**
5376	* Gets the IEM exception flags for the specified SVM event.
5377	*
5378	* @returns The IEM exception flags.
5379	* @param pEvent Pointer to the SVM event.
5380	*
5381	* @remarks This function currently only constructs flags required for
5382	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5383	* and CR2 aspects of an exception are not included).
5384	*/
5385	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5386	{
5387	uint8_t const uEventType = pEvent->n.u3Type;
5388	uint32_t fIemXcptFlags;
5389	switch (uEventType)
5390	{
5391	case SVM_EVENT_EXCEPTION:
5392	/*
5393	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5394	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5395	*/
5396	if (pEvent->n.u8Vector == X86_XCPT_BP)
5397	{
5398	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5399	break;
5400	}
5401	if (pEvent->n.u8Vector == X86_XCPT_OF)
5402	{
5403	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5404	break;
5405	}
5406	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5407	RT_FALL_THRU();
5408	case SVM_EVENT_NMI:
5409	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5410	break;
5411
5412	case SVM_EVENT_EXTERNAL_IRQ:
5413	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5414	break;
5415
5416	case SVM_EVENT_SOFTWARE_INT:
5417	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5418	break;
5419
5420	default:
5421	fIemXcptFlags = 0;
5422	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5423	break;
5424	}
5425	return fIemXcptFlags;
5426	}
5427
5428	#else
5429	/**
5430	* Determines if an exception is a contributory exception.
5431	*
5432	* Contributory exceptions are ones which can cause double-faults unless the
5433	* original exception was a benign exception. Page-fault is intentionally not
5434	* included here as it's a conditional contributory exception.
5435	*
5436	* @returns true if the exception is contributory, false otherwise.
5437	* @param uVector The exception vector.
5438	*/
5439	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5440	{
5441	switch (uVector)
5442	{
5443	case X86_XCPT_GP:
5444	case X86_XCPT_SS:
5445	case X86_XCPT_NP:
5446	case X86_XCPT_TS:
5447	case X86_XCPT_DE:
5448	return true;
5449	default:
5450	break;
5451	}
5452	return false;
5453	}
5454	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5455
5456
5457	/**
5458	* Handle a condition that occurred while delivering an event through the guest
5459	* IDT.
5460	*
5461	* @returns VBox status code (informational error codes included).
5462	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5463	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5464	* continue execution of the guest which will delivery the \#DF.
5465	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5466	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5467	*
5468	* @param pVCpu The cross context virtual CPU structure.
5469	* @param pCtx Pointer to the guest-CPU context.
5470	* @param pSvmTransient Pointer to the SVM transient structure.
5471	*
5472	* @remarks No-long-jump zone!!!
5473	*/
5474	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5475	{
5476	int rc = VINF_SUCCESS;
5477	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5478
5479	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5480	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5481	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5482
5483	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5484	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5485	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5486	{
5487	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5488	IEMXCPTRAISE enmRaise;
5489	IEMXCPTRAISEINFO fRaiseInfo;
5490	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5491	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5492	if (fExitIsHwXcpt)
5493	{
5494	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5495	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5496	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5497	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5498	}
5499	else
5500	{
5501	/*
5502	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5503	* end up here.
5504	*
5505	* If the event was:
5506	* - a software interrupt, we can re-execute the instruction which will regenerate
5507	* the event.
5508	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5509	* - a hardware exception or external interrupt, we re-inject it.
5510	*/
5511	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5512	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5513	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5514	else
5515	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5516	}
5517
5518	switch (enmRaise)
5519	{
5520	case IEMXCPTRAISE_CURRENT_XCPT:
5521	case IEMXCPTRAISE_PREV_EVENT:
5522	{
5523	/* For software interrupts, we shall re-execute the instruction. */
5524	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5525	{
5526	RTGCUINTPTR GCPtrFaultAddress = 0;
5527
5528	/* If we are re-injecting an NMI, clear NMI blocking. */
5529	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5530	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5531
5532	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5533	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5534	pSvmTransient->fVectoringPF = true;
5535	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5536	&& uIdtVector == X86_XCPT_PF)
5537	{
5538	/*
5539	* If the previous exception was a #PF, we need to recover the CR2 value.
5540	* This can't happen with shadow paging.
5541	*/
5542	GCPtrFaultAddress = pCtx->cr2;
5543	}
5544
5545	/*
5546	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5547	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5548	*/
5549	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5550	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5551	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5552
5553	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5554	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5555	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5556	}
5557	break;
5558	}
5559
5560	case IEMXCPTRAISE_REEXEC_INSTR:
5561	{
5562	Assert(rc == VINF_SUCCESS);
5563	break;
5564	}
5565
5566	case IEMXCPTRAISE_DOUBLE_FAULT:
5567	{
5568	/*
5569	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5570	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5571	*/
5572	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5573	{
5574	pSvmTransient->fVectoringDoublePF = true;
5575	Assert(rc == VINF_SUCCESS);
5576	}
5577	else
5578	{
5579	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5580	hmR0SvmSetPendingXcptDF(pVCpu);
5581	rc = VINF_HM_DOUBLE_FAULT;
5582	}
5583	break;
5584	}
5585
5586	case IEMXCPTRAISE_TRIPLE_FAULT:
5587	{
5588	rc = VINF_EM_RESET;
5589	break;
5590	}
5591
5592	case IEMXCPTRAISE_CPU_HANG:
5593	{
5594	rc = VERR_EM_GUEST_CPU_HANG;
5595	break;
5596	}
5597
5598	default:
5599	{
5600	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5601	rc = VERR_SVM_IPE_2;
5602	break;
5603	}
5604	}
5605	#else
5606	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5607
5608	typedef enum
5609	{
5610	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5611	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5612	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5613	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5614	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5615	} SVMREFLECTXCPT;
5616
5617	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5618	bool fReflectingNmi = false;
5619	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5620	{
5621	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5622	{
5623	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5624
5625	#ifdef VBOX_STRICT
5626	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5627	&& uExitVector == X86_XCPT_PF)
5628	{
5629	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5630	}
5631	#endif
5632
5633	if ( uIdtVector == X86_XCPT_BP
5634	\|\| uIdtVector == X86_XCPT_OF)
5635	{
5636	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5637	}
5638	else if ( uExitVector == X86_XCPT_PF
5639	&& uIdtVector == X86_XCPT_PF)
5640	{
5641	pSvmTransient->fVectoringDoublePF = true;
5642	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
5643	}
5644	else if ( uExitVector == X86_XCPT_AC
5645	&& uIdtVector == X86_XCPT_AC)
5646	{
5647	enmReflect = SVMREFLECTXCPT_HANG;
5648	Log4(("IDT: Nested #AC - Bad guest\n"));
5649	}
5650	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
5651	&& hmR0SvmIsContributoryXcpt(uExitVector)
5652	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
5653	\|\| uIdtVector == X86_XCPT_PF))
5654	{
5655	enmReflect = SVMREFLECTXCPT_DF;
5656	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
5657	uIdtVector, uExitVector));
5658	}
5659	else if (uIdtVector == X86_XCPT_DF)
5660	{
5661	enmReflect = SVMREFLECTXCPT_TF;
5662	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
5663	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
5664	}
5665	else
5666	enmReflect = SVMREFLECTXCPT_XCPT;
5667	}
5668	else
5669	{
5670	/*
5671	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
5672	* exception to the guest after handling the #VMEXIT.
5673	*/
5674	enmReflect = SVMREFLECTXCPT_XCPT;
5675	}
5676	}
5677	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
5678	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5679	{
5680	enmReflect = SVMREFLECTXCPT_XCPT;
5681	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
5682
5683	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5684	{
5685	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5686	if (uExitVector == X86_XCPT_PF)
5687	{
5688	pSvmTransient->fVectoringPF = true;
5689	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
5690	}
5691	}
5692	}
5693	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
5694
5695	switch (enmReflect)
5696	{
5697	case SVMREFLECTXCPT_XCPT:
5698	{
5699	/* If we are re-injecting the NMI, clear NMI blocking. */
5700	if (fReflectingNmi)
5701	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5702
5703	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5704	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5705	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
5706
5707	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
5708	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
5709	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
5710	break;
5711	}
5712
5713	case SVMREFLECTXCPT_DF:
5714	{
5715	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5716	hmR0SvmSetPendingXcptDF(pVCpu);
5717	rc = VINF_HM_DOUBLE_FAULT;
5718	break;
5719	}
5720
5721	case SVMREFLECTXCPT_TF:
5722	{
5723	rc = VINF_EM_RESET;
5724	break;
5725	}
5726
5727	case SVMREFLECTXCPT_HANG:
5728	{
5729	rc = VERR_EM_GUEST_CPU_HANG;
5730	break;
5731	}
5732
5733	default:
5734	Assert(rc == VINF_SUCCESS);
5735	break;
5736	}
5737	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5738	}
5739	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5740	NOREF(pCtx);
5741	return rc;
5742	}
5743
5744
5745	/**
5746	* Updates interrupt shadow for the current RIP.
5747	*/
5748	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
5749	do { \
5750	/* Update interrupt shadow. */ \
5751	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
5752	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
5753	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
5754	} while (0)
5755
5756
5757	/**
5758	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
5759	* supported, otherwise advances the RIP by the number of bytes specified in
5760	* @a cb.
5761	*
5762	* @param pVCpu The cross context virtual CPU structure.
5763	* @param pCtx Pointer to the guest-CPU context.
5764	* @param cb RIP increment value in bytes.
5765	*
5766	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
5767	* when NRIP_SAVE is supported by the CPU, otherwise use
5768	* hmR0SvmAdvanceRipDumb!
5769	*/
5770	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5771	{
5772	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
5773	{
5774	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5775	Assert(pVmcb->ctrl.u64NextRIP);
5776	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
5777	pCtx->rip = pVmcb->ctrl.u64NextRIP;
5778	}
5779	else
5780	pCtx->rip += cb;
5781
5782	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5783	}
5784
5785
5786	#ifdef VBOX_WITH_NESTED_HWVIRT
5787	/**
5788	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
5789	* feature. Otherwise, returns the value in @a cbLikely.
5790	*
5791	* @param pVCpu The cross context virtual CPU structure.
5792	* @param pCtx Pointer to the guest-CPU context.
5793	* @param cbLikely The likely instruction length.
5794	*/
5795	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
5796	{
5797	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
5798	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
5799	{
5800	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5801	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
5802	Assert(cbInstr == cbLikely);
5803	return cbInstr;
5804	}
5805	return cbLikely;
5806	}
5807	#endif
5808
5809
5810	/**
5811	* Advances the guest RIP by the number of bytes specified in @a cb. This does
5812	* not make use of any hardware features to determine the instruction length.
5813	*
5814	* @param pVCpu The cross context virtual CPU structure.
5815	* @param pCtx Pointer to the guest-CPU context.
5816	* @param cb RIP increment value in bytes.
5817	*/
5818	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5819	{
5820	pCtx->rip += cb;
5821	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5822	}
5823	#undef HMSVM_UPDATE_INTR_SHADOW
5824
5825
5826	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5827	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5828	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5829
5830	/** @name \#VMEXIT handlers.
5831	* @{
5832	*/
5833
5834	/**
5835	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5836	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5837	*/
5838	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5839	{
5840	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5841
5842	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5843	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5844	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5845	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5846
5847	/*
5848	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
5849	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
5850	* interrupt it is until the host actually take the interrupt.
5851	*
5852	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
5853	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5854	*/
5855	return VINF_EM_RAW_INTERRUPT;
5856	}
5857
5858
5859	/**
5860	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5861	*/
5862	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5863	{
5864	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5865
5866	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5867	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
5868	int rc = VINF_SUCCESS;
5869	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5870	return rc;
5871	}
5872
5873
5874	/**
5875	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5876	*/
5877	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5878	{
5879	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5880
5881	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5882	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
5883	int rc = VINF_SUCCESS;
5884	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5885	return rc;
5886	}
5887
5888
5889	/**
5890	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5891	*/
5892	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5893	{
5894	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5895	PVM pVM = pVCpu->CTX_SUFF(pVM);
5896	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
5897	if (RT_LIKELY(rc == VINF_SUCCESS))
5898	{
5899	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5900	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5901	}
5902	else
5903	{
5904	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5905	rc = VERR_EM_INTERPRETER;
5906	}
5907	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
5908	return rc;
5909	}
5910
5911
5912	/**
5913	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5914	*/
5915	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5916	{
5917	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5918	PVM pVM = pVCpu->CTX_SUFF(pVM);
5919	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
5920	if (RT_LIKELY(rc == VINF_SUCCESS))
5921	{
5922	pSvmTransient->fUpdateTscOffsetting = true;
5923	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5924	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5925	}
5926	else
5927	{
5928	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
5929	rc = VERR_EM_INTERPRETER;
5930	}
5931	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
5932	return rc;
5933	}
5934
5935
5936	/**
5937	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5938	*/
5939	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5940	{
5941	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5942	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5943	if (RT_LIKELY(rc == VINF_SUCCESS))
5944	{
5945	pSvmTransient->fUpdateTscOffsetting = true;
5946	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
5947	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5948	}
5949	else
5950	{
5951	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
5952	rc = VERR_EM_INTERPRETER;
5953	}
5954	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
5955	return rc;
5956	}
5957
5958
5959	/**
5960	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5961	*/
5962	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5963	{
5964	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5965	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
5966	if (RT_LIKELY(rc == VINF_SUCCESS))
5967	{
5968	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5969	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5970	}
5971	else
5972	{
5973	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
5974	rc = VERR_EM_INTERPRETER;
5975	}
5976	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
5977	return rc;
5978	}
5979
5980
5981	/**
5982	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5983	*/
5984	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5985	{
5986	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5987	PVM pVM = pVCpu->CTX_SUFF(pVM);
5988	Assert(!pVM->hm.s.fNestedPaging);
5989	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
5990
5991	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
5992	{
5993	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
5994	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5995	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
5996	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
5997	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
5998	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5999	return VBOXSTRICTRC_VAL(rcStrict);
6000	}
6001
6002	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6003	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6004	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6005	return rc;
6006	}
6007
6008
6009	/**
6010	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6011	*/
6012	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6013	{
6014	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6015
6016	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6017	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6018	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6019	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6020	if (rc != VINF_SUCCESS)
6021	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6022	return rc;
6023	}
6024
6025
6026	/**
6027	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6028	*/
6029	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6030	{
6031	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6032	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6033	if (RT_LIKELY(rc == VINF_SUCCESS))
6034	{
6035	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6036	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6037	}
6038	else
6039	{
6040	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6041	rc = VERR_EM_INTERPRETER;
6042	}
6043	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6044	return rc;
6045	}
6046
6047
6048	/**
6049	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6050	*/
6051	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6052	{
6053	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6054	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6055	int rc = VBOXSTRICTRC_VAL(rc2);
6056	if ( rc == VINF_EM_HALT
6057	\|\| rc == VINF_SUCCESS)
6058	{
6059	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6060
6061	if ( rc == VINF_EM_HALT
6062	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6063	{
6064	rc = VINF_SUCCESS;
6065	}
6066	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6067	}
6068	else
6069	{
6070	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6071	rc = VERR_EM_INTERPRETER;
6072	}
6073	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6074	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6075	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6076	return rc;
6077	}
6078
6079
6080	/**
6081	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6082	* \#VMEXIT.
6083	*/
6084	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6085	{
6086	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6087	return VINF_EM_RESET;
6088	}
6089
6090
6091	/**
6092	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6093	*/
6094	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6095	{
6096	RT_NOREF(pCtx);
6097	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64\n", pSvmTransient->u64ExitCode));
6098	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6099	return VERR_SVM_UNEXPECTED_EXIT;
6100	}
6101
6102
6103	/**
6104	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6105	*/
6106	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6107	{
6108	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6109
6110	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6111	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6112
6113	PVM pVM = pVCpu->CTX_SUFF(pVM);
6114	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
6115	{
6116	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
6117	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6118	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6119	if (fMovCRx)
6120	{
6121	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6122	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6123	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6124	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6125	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6126	return VBOXSTRICTRC_VAL(rcStrict);
6127	}
6128	/* else: SMSW instruction, fall back below to IEM for this. */
6129	}
6130
6131	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6132	int rc = VBOXSTRICTRC_VAL(rc2);
6133	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6134	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6135	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6136	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6137	return rc;
6138	}
6139
6140
6141	/**
6142	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6143	*/
6144	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6145	{
6146	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6147
6148	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6149	Assert(iCrReg <= 15);
6150
6151	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6152	PVM pVM = pVCpu->CTX_SUFF(pVM);
6153	bool fDecodedInstr = false;
6154	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
6155	{
6156	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
6157	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6158	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6159	if (fMovCRx)
6160	{
6161	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6162	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6163	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6164	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6165	fDecodedInstr = true;
6166	}
6167	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6168	}
6169
6170	if (!fDecodedInstr)
6171	{
6172	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6173	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6174	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6175	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6176	rcStrict = VERR_EM_INTERPRETER;
6177	}
6178
6179	if (rcStrict == VINF_SUCCESS)
6180	{
6181	switch (iCrReg)
6182	{
6183	case 0: /* CR0. */
6184	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6185	break;
6186
6187	case 3: /* CR3. */
6188	Assert(!pVM->hm.s.fNestedPaging);
6189	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6190	break;
6191
6192	case 4: /* CR4. */
6193	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6194	break;
6195
6196	case 8: /* CR8 (TPR). */
6197	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6198	break;
6199
6200	default:
6201	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6202	pSvmTransient->u64ExitCode, iCrReg));
6203	break;
6204	}
6205	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6206	}
6207	else
6208	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6209	return VBOXSTRICTRC_TODO(rcStrict);
6210	}
6211
6212
6213	/**
6214	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6215	* \#VMEXIT.
6216	*/
6217	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6218	{
6219	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6220	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6221	PVM pVM = pVCpu->CTX_SUFF(pVM);
6222
6223	int rc;
6224	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6225	{
6226	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6227	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6228
6229	/* Handle TPR patching; intercepted LSTAR write. */
6230	if ( pVM->hm.s.fTPRPatchingActive
6231	&& pCtx->ecx == MSR_K8_LSTAR)
6232	{
6233	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6234	{
6235	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6236	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6237	AssertRC(rc2);
6238	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6239	}
6240	rc = VINF_SUCCESS;
6241	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6242	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6243	return rc;
6244	}
6245
6246	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6247	{
6248	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6249	if (RT_LIKELY(rc == VINF_SUCCESS))
6250	{
6251	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6252	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6253	}
6254	else
6255	AssertMsg( rc == VERR_EM_INTERPRETER
6256	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6257	}
6258	else
6259	{
6260	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6261	if (RT_LIKELY(rc == VINF_SUCCESS))
6262	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6263	else
6264	AssertMsg( rc == VERR_EM_INTERPRETER
6265	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6266	}
6267
6268	if (rc == VINF_SUCCESS)
6269	{
6270	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6271	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6272	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6273	{
6274	/*
6275	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6276	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6277	* EMInterpretWrmsr() changes it.
6278	*/
6279	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6280	}
6281	else if (pCtx->ecx == MSR_K6_EFER)
6282	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
6283	else if (pCtx->ecx == MSR_IA32_TSC)
6284	pSvmTransient->fUpdateTscOffsetting = true;
6285	}
6286	}
6287	else
6288	{
6289	/* MSR Read access. */
6290	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6291	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6292	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6293
6294	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6295	{
6296	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6297	if (RT_LIKELY(rc == VINF_SUCCESS))
6298	{
6299	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6300	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6301	}
6302	else
6303	AssertMsg( rc == VERR_EM_INTERPRETER
6304	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6305	}
6306	else
6307	{
6308	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6309	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6310	{
6311	AssertMsg( rc == VERR_EM_INTERPRETER
6312	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6313	}
6314	/* RIP updated by EMInterpretInstruction(). */
6315	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6316	}
6317	}
6318
6319	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
6320	return rc;
6321	}
6322
6323
6324	/**
6325	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6326	*/
6327	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6328	{
6329	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6330	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6331
6332	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6333	if (pSvmTransient->fWasGuestDebugStateActive)
6334	{
6335	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6336	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6337	return VERR_SVM_UNEXPECTED_EXIT;
6338	}
6339
6340	/*
6341	* Lazy DR0-3 loading.
6342	*/
6343	if (!pSvmTransient->fWasHyperDebugStateActive)
6344	{
6345	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6346	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6347
6348	/* Don't intercept DRx read and writes. */
6349	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6350	pVmcb->ctrl.u16InterceptRdDRx = 0;
6351	pVmcb->ctrl.u16InterceptWrDRx = 0;
6352	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6353
6354	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6355	VMMRZCallRing3Disable(pVCpu);
6356	HM_DISABLE_PREEMPT();
6357
6358	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6359	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6360	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6361
6362	HM_RESTORE_PREEMPT();
6363	VMMRZCallRing3Enable(pVCpu);
6364
6365	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6366	return VINF_SUCCESS;
6367	}
6368
6369	/*
6370	* Interpret the read/writing of DRx.
6371	*/
6372	/** @todo Decode assist. */
6373	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6374	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6375	if (RT_LIKELY(rc == VINF_SUCCESS))
6376	{
6377	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6378	/** @todo CPUM should set this flag! */
6379	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6380	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6381	}
6382	else
6383	Assert(rc == VERR_EM_INTERPRETER);
6384	return VBOXSTRICTRC_TODO(rc);
6385	}
6386
6387
6388	/**
6389	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6390	*/
6391	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6392	{
6393	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6394	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6395	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6396	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6397	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6398	return rc;
6399	}
6400
6401
6402	/**
6403	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6404	*/
6405	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6406	{
6407	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6408
6409	/** @todo decode assists... */
6410	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6411	if (rcStrict == VINF_IEM_RAISED_XCPT)
6412	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6413
6414	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6415	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6416	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6417
6418	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6419	return VBOXSTRICTRC_TODO(rcStrict);
6420	}
6421
6422
6423	/**
6424	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6425	*/
6426	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6427	{
6428	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6429
6430	/* I/O operation lookup arrays. */
6431	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6432	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6433	the result (in AL/AX/EAX). */
6434	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6435
6436	PVM pVM = pVCpu->CTX_SUFF(pVM);
6437	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6438
6439	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6440	SVMIOIOEXITINFO IoExitInfo;
6441	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6442	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6443	uint32_t cbValue = s_aIOSize[uIOWidth];
6444	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6445
6446	if (RT_UNLIKELY(!cbValue))
6447	{
6448	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6449	return VERR_EM_INTERPRETER;
6450	}
6451
6452	VBOXSTRICTRC rcStrict;
6453	bool fUpdateRipAlready = false;
6454	if (IoExitInfo.n.u1STR)
6455	{
6456	#ifdef VBOX_WITH_2ND_IEM_STEP
6457	/* INS/OUTS - I/O String instruction. */
6458	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6459	* in EXITINFO1? Investigate once this thing is up and running. */
6460	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6461	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6462	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6463	static IEMMODE const s_aenmAddrMode[8] =
6464	{
6465	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6466	};
6467	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6468	if (enmAddrMode != (IEMMODE)-1)
6469	{
6470	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6471	if (cbInstr <= 15 && cbInstr >= 1)
6472	{
6473	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6474	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6475	{
6476	/* Don't know exactly how to detect whether u3SEG is valid, currently
6477	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6478	2384 Opterons when only checking NRIP. */
6479	if ( (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6480	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6481	{
6482	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6483	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6484	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6485	IoExitInfo.n.u3SEG, true /fIoChecked/);
6486	}
6487	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6488	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6489	X86_SREG_DS, true /fIoChecked/);
6490	else
6491	rcStrict = IEMExecOne(pVCpu);
6492	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6493	}
6494	else
6495	{
6496	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6497	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6498	true /fIoChecked/);
6499	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6500	}
6501	}
6502	else
6503	{
6504	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6505	rcStrict = IEMExecOne(pVCpu);
6506	}
6507	}
6508	else
6509	{
6510	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6511	rcStrict = IEMExecOne(pVCpu);
6512	}
6513	fUpdateRipAlready = true;
6514
6515	#else
6516	/* INS/OUTS - I/O String instruction. */
6517	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6518
6519	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6520	* in EXITINFO1? Investigate once this thing is up and running. */
6521
6522	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6523	if (rcStrict == VINF_SUCCESS)
6524	{
6525	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6526	{
6527	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6528	(DISCPUMODE)pDis->uAddrMode, cbValue);
6529	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6530	}
6531	else
6532	{
6533	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6534	(DISCPUMODE)pDis->uAddrMode, cbValue);
6535	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6536	}
6537	}
6538	else
6539	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6540	#endif
6541	}
6542	else
6543	{
6544	/* IN/OUT - I/O instruction. */
6545	Assert(!IoExitInfo.n.u1REP);
6546
6547	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6548	{
6549	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6550	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6551	}
6552	else
6553	{
6554	uint32_t u32Val = 0;
6555	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6556	if (IOM_SUCCESS(rcStrict))
6557	{
6558	/* Save result of I/O IN instr. in AL/AX/EAX. */
6559	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6560	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6561	}
6562	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6563	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6564
6565	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6566	}
6567	}
6568
6569	if (IOM_SUCCESS(rcStrict))
6570	{
6571	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6572	if (!fUpdateRipAlready)
6573	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6574
6575	/*
6576	* If any I/O breakpoints are armed, we need to check if one triggered
6577	* and take appropriate action.
6578	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6579	*/
6580	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6581	* execution engines about whether hyper BPs and such are pending. */
6582	uint32_t const uDr7 = pCtx->dr[7];
6583	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6584	&& X86_DR7_ANY_RW_IO(uDr7)
6585	&& (pCtx->cr4 & X86_CR4_DE))
6586	\|\| DBGFBpIsHwIoArmed(pVM)))
6587	{
6588	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6589	VMMRZCallRing3Disable(pVCpu);
6590	HM_DISABLE_PREEMPT();
6591
6592	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6593	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6594
6595	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6596	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6597	{
6598	/* Raise #DB. */
6599	pVmcb->guest.u64DR6 = pCtx->dr[6];
6600	pVmcb->guest.u64DR7 = pCtx->dr[7];
6601	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6602	hmR0SvmSetPendingXcptDB(pVCpu);
6603	}
6604	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6605	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6606	else if ( rcStrict2 != VINF_SUCCESS
6607	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6608	rcStrict = rcStrict2;
6609	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6610
6611	HM_RESTORE_PREEMPT();
6612	VMMRZCallRing3Enable(pVCpu);
6613	}
6614
6615	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6616	}
6617
6618	#ifdef VBOX_STRICT
6619	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6620	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6621	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6622	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6623	else
6624	{
6625	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6626	* statuses, that the VMM device and some others may return. See
6627	* IOM_SUCCESS() for guidance. */
6628	AssertMsg( RT_FAILURE(rcStrict)
6629	\|\| rcStrict == VINF_SUCCESS
6630	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6631	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6632	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6633	\|\| rcStrict == VINF_EM_RAW_TO_R3
6634	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6635	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6636	}
6637	#endif
6638	return VBOXSTRICTRC_TODO(rcStrict);
6639	}
6640
6641
6642	/**
6643	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6644	*/
6645	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6646	{
6647	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6648	PVM pVM = pVCpu->CTX_SUFF(pVM);
6649	Assert(pVM->hm.s.fNestedPaging);
6650
6651	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6652
6653	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6654	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6655	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6656	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6657
6658	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
6659
6660	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6661	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
6662	if ( pVM->hm.s.fTprPatchingAllowed
6663	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6664	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6665	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6666	&& !CPUMIsGuestInLongModeEx(pCtx)
6667	&& !CPUMGetGuestCPL(pVCpu)
6668	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6669	{
6670	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6671	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6672
6673	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6674	{
6675	/* Only attempt to patch the instruction once. */
6676	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6677	if (!pPatch)
6678	return VINF_EM_HM_PATCH_TPR_INSTR;
6679	}
6680	}
6681	#endif
6682
6683	/*
6684	* Determine the nested paging mode.
6685	*/
6686	PGMMODE enmNestedPagingMode;
6687	#if HC_ARCH_BITS == 32
6688	if (CPUMIsGuestInLongModeEx(pCtx))
6689	enmNestedPagingMode = PGMMODE_AMD64_NX;
6690	else
6691	#endif
6692	enmNestedPagingMode = PGMGetHostMode(pVM);
6693
6694	/*
6695	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6696	*/
6697	int rc;
6698	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6699	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6700	{
6701	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
6702	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
6703	if (pVCpu->hm.s.Event.fPending)
6704	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6705
6706	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6707	u32ErrCode);
6708	rc = VBOXSTRICTRC_VAL(rc2);
6709
6710	/*
6711	* If we succeed, resume guest execution.
6712	* If we fail in interpreting the instruction because we couldn't get the guest physical address
6713	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
6714	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
6715	* weird case. See @bugref{6043}.
6716	*/
6717	if ( rc == VINF_SUCCESS
6718	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6719	\|\| rc == VERR_PAGE_NOT_PRESENT)
6720	{
6721	/* Successfully handled MMIO operation. */
6722	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6723	rc = VINF_SUCCESS;
6724	}
6725	return rc;
6726	}
6727
6728	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6729	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6730	TRPMResetTrap(pVCpu);
6731
6732	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6733
6734	/*
6735	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6736	*/
6737	if ( rc == VINF_SUCCESS
6738	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6739	\|\| rc == VERR_PAGE_NOT_PRESENT)
6740	{
6741	/* We've successfully synced our shadow page tables. */
6742	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6743	rc = VINF_SUCCESS;
6744	}
6745
6746	return rc;
6747	}
6748
6749
6750	/**
6751	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6752	* \#VMEXIT.
6753	*/
6754	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6755	{
6756	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6757
6758	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6759	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
6760	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;
6761
6762	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
6763	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
6764	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
6765
6766	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6767	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6768	return VINF_SUCCESS;
6769	}
6770
6771
6772	/**
6773	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6774	* \#VMEXIT.
6775	*/
6776	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6777	{
6778	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6779
6780	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6781
6782	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6783	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6784	#endif
6785
6786	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6787	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6788	{
6789	/*
6790	* AMD-V provides us with the exception which caused the TS; we collect
6791	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
6792	*/
6793	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
6794	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6795	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6796	}
6797
6798	/** @todo Emulate task switch someday, currently just going back to ring-3 for
6799	* emulation. */
6800	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6801	return VERR_EM_INTERPRETER;
6802	}
6803
6804
6805	/**
6806	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6807	*/
6808	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6809	{
6810	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6811	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
6812
6813	bool fRipUpdated;
6814	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
6815	if (RT_SUCCESS(rcStrict))
6816	{
6817	/* Only update the RIP if we're continuing guest execution and not
6818	in the case of say VINF_GIM_R3_HYPERCALL. */
6819	if ( rcStrict == VINF_SUCCESS
6820	&& !fRipUpdated)
6821	{
6822	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
6823	}
6824
6825	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
6826	we would need to reload the guest changed bits here before VM-entry. */
6827	return VBOXSTRICTRC_VAL(rcStrict);
6828	}
6829
6830	hmR0SvmSetPendingXcptUD(pVCpu);
6831	return VINF_SUCCESS;
6832	}
6833
6834
6835	/**
6836	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6837	*/
6838	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6839	{
6840	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6841	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
6842	return VINF_EM_RAW_INTERRUPT;
6843	}
6844
6845
6846	/**
6847	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
6848	*/
6849	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6850	{
6851	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6852
6853	/* Clear NMI blocking. */
6854	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6855
6856	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6857	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6858	hmR0SvmClearIretIntercept(pVmcb);
6859
6860	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6861	return VINF_SUCCESS;
6862	}
6863
6864
6865	/**
6866	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
6867	* Conditional \#VMEXIT.
6868	*/
6869	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6870	{
6871	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6872
6873	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6874
6875	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
6876	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6877	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6878	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
6879	PVM pVM = pVCpu->CTX_SUFF(pVM);
6880
6881	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
6882	if (pVM->hm.s.fNestedPaging)
6883	{
6884	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
6885	if (!pSvmTransient->fVectoringDoublePF)
6886	{
6887	/* A genuine guest #PF, reflect it to the guest. */
6888	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
6889	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
6890	uFaultAddress, u32ErrCode));
6891	}
6892	else
6893	{
6894	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
6895	hmR0SvmSetPendingXcptDF(pVCpu);
6896	Log4(("Pending #DF due to vectoring #PF. NP\n"));
6897	}
6898	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
6899	return VINF_SUCCESS;
6900	}
6901	#endif
6902
6903	Assert(!pVM->hm.s.fNestedPaging);
6904
6905	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6906	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
6907	if ( pVM->hm.s.fTprPatchingAllowed
6908	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
6909	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
6910	&& !CPUMIsGuestInLongModeEx(pCtx)
6911	&& !CPUMGetGuestCPL(pVCpu)
6912	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6913	{
6914	RTGCPHYS GCPhysApicBase;
6915	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6916	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6917
6918	/* Check if the page at the fault-address is the APIC base. */
6919	RTGCPHYS GCPhysPage;
6920	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
6921	if ( rc2 == VINF_SUCCESS
6922	&& GCPhysPage == GCPhysApicBase)
6923	{
6924	/* Only attempt to patch the instruction once. */
6925	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6926	if (!pPatch)
6927	return VINF_EM_HM_PATCH_TPR_INSTR;
6928	}
6929	}
6930	#endif
6931
6932	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
6933	pCtx->rip, u32ErrCode, pCtx->cr3));
6934
6935	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
6936	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
6937	if (pSvmTransient->fVectoringPF)
6938	{
6939	Assert(pVCpu->hm.s.Event.fPending);
6940	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6941	}
6942
6943	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
6944	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
6945
6946	Log4(("#PF rc=%Rrc\n", rc));
6947
6948	if (rc == VINF_SUCCESS)
6949	{
6950	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
6951	TRPMResetTrap(pVCpu);
6952	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6953	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6954	return rc;
6955	}
6956	else if (rc == VINF_EM_RAW_GUEST_TRAP)
6957	{
6958	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
6959
6960	if (!pSvmTransient->fVectoringDoublePF)
6961	{
6962	/* It's a guest page fault and needs to be reflected to the guest. */
6963	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
6964	TRPMResetTrap(pVCpu);
6965	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
6966	}
6967	else
6968	{
6969	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
6970	TRPMResetTrap(pVCpu);
6971	hmR0SvmSetPendingXcptDF(pVCpu);
6972	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
6973	}
6974
6975	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
6976	return VINF_SUCCESS;
6977	}
6978
6979	TRPMResetTrap(pVCpu);
6980	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
6981	return rc;
6982	}
6983
6984
6985	/**
6986	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
6987	* Conditional \#VMEXIT.
6988	*/
6989	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6990	{
6991	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6992
6993	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
6994	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6995	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
6996
6997	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6998	VMMRZCallRing3Disable(pVCpu);
6999	HM_DISABLE_PREEMPT();
7000
7001	int rc;
7002	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7003	if (pSvmTransient->fWasGuestFPUStateActive)
7004	{
7005	rc = VINF_EM_RAW_GUEST_TRAP;
7006	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7007	}
7008	else
7009	{
7010	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7011	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7012	#endif
7013	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7014	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7015	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7016	}
7017
7018	HM_RESTORE_PREEMPT();
7019	VMMRZCallRing3Enable(pVCpu);
7020
7021	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7022	{
7023	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7024	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7025	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7026	pVCpu->hm.s.fPreloadGuestFpu = true;
7027	}
7028	else
7029	{
7030	/* Forward #NM to the guest. */
7031	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7032	hmR0SvmSetPendingXcptNM(pVCpu);
7033	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7034	}
7035	return VINF_SUCCESS;
7036	}
7037
7038
7039	/**
7040	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7041	* Conditional \#VMEXIT.
7042	*/
7043	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7044	{
7045	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7046
7047	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7048	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7049	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7050
7051	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7052	if (pVCpu->hm.s.fGIMTrapXcptUD)
7053	{
7054	uint8_t cbInstr = 0;
7055	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7056	if (rcStrict == VINF_SUCCESS)
7057	{
7058	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7059	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7060	rc = VINF_SUCCESS;
7061	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7062	}
7063	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7064	rc = VINF_SUCCESS;
7065	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7066	rc = VINF_GIM_R3_HYPERCALL;
7067	else
7068	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7069	}
7070
7071	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7072	if (RT_FAILURE(rc))
7073	{
7074	hmR0SvmSetPendingXcptUD(pVCpu);
7075	rc = VINF_SUCCESS;
7076	}
7077
7078	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7079	return rc;
7080	}
7081
7082
7083	/**
7084	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7085	* Conditional \#VMEXIT.
7086	*/
7087	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7088	{
7089	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7090
7091	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7092	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7093	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7094
7095	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7096
7097	if (!(pCtx->cr0 & X86_CR0_NE))
7098	{
7099	PVM pVM = pVCpu->CTX_SUFF(pVM);
7100	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7101	unsigned cbOp;
7102	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7103	if (RT_SUCCESS(rc))
7104	{
7105	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7106	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7107	if (RT_SUCCESS(rc))
7108	pCtx->rip += cbOp;
7109	}
7110	else
7111	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7112	return rc;
7113	}
7114
7115	hmR0SvmSetPendingXcptMF(pVCpu);
7116	return VINF_SUCCESS;
7117	}
7118
7119
7120	/**
7121	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7122	* \#VMEXIT.
7123	*/
7124	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7125	{
7126	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7127
7128	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7129	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7130	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7131	{
7132	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7133	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7134	}
7135
7136	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7137
7138	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7139	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7140	PVM pVM = pVCpu->CTX_SUFF(pVM);
7141	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7142	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7143	if (rc == VINF_EM_RAW_GUEST_TRAP)
7144	{
7145	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7146	if (CPUMIsHyperDebugStateActive(pVCpu))
7147	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7148
7149	/* Reflect the exception back to the guest. */
7150	hmR0SvmSetPendingXcptDB(pVCpu);
7151	rc = VINF_SUCCESS;
7152	}
7153
7154	/*
7155	* Update DR6.
7156	*/
7157	if (CPUMIsHyperDebugStateActive(pVCpu))
7158	{
7159	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7160	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7161	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7162	}
7163	else
7164	{
7165	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7166	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7167	}
7168
7169	return rc;
7170	}
7171
7172
7173	/**
7174	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7175	* Conditional \#VMEXIT.
7176	*/
7177	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7178	{
7179	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7180
7181	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7182	* shutdown VMEXIT. */
7183	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7184
7185	SVMEVENT Event;
7186	Event.u = 0;
7187	Event.n.u1Valid = 1;
7188	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7189	Event.n.u8Vector = X86_XCPT_AC;
7190	Event.n.u1ErrorCodeValid = 1;
7191	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7192	return VINF_SUCCESS;
7193	}
7194
7195
7196	/**
7197	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7198	* Conditional \#VMEXIT.
7199	*/
7200	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7201	{
7202	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7203
7204	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7205
7206	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7207	if (rc == VINF_EM_RAW_GUEST_TRAP)
7208	{
7209	SVMEVENT Event;
7210	Event.u = 0;
7211	Event.n.u1Valid = 1;
7212	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7213	Event.n.u8Vector = X86_XCPT_BP;
7214	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7215	}
7216
7217	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7218	return rc;
7219	}
7220
7221
7222	#ifdef VBOX_WITH_NESTED_HWVIRT
7223	/**
7224	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7225	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7226	*/
7227	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7228	{
7229	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7230
7231	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7232
7233	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7234	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7235	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7236	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7237
7238	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7239	pCtx->rip, u32ErrCode, pCtx->cr3));
7240
7241	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7242	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7243	if (pSvmTransient->fVectoringPF)
7244	{
7245	Assert(pVCpu->hm.s.Event.fPending);
7246	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7247	}
7248
7249	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7250
7251	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7252	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7253
7254	Log4(("#PFNested: rc=%Rrc\n", rc));
7255
7256	if (rc == VINF_SUCCESS)
7257	{
7258	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7259	TRPMResetTrap(pVCpu);
7260	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7261	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7262	return rc;
7263	}
7264
7265	if (rc == VINF_EM_RAW_GUEST_TRAP)
7266	{
7267	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7268
7269	if (!pSvmTransient->fVectoringDoublePF)
7270	{
7271	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7272	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7273	TRPMResetTrap(pVCpu);
7274	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7275	}
7276	else
7277	{
7278	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7279	TRPMResetTrap(pVCpu);
7280	hmR0SvmSetPendingXcptDF(pVCpu);
7281	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7282	}
7283
7284	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7285	return VINF_SUCCESS;
7286	}
7287
7288	TRPMResetTrap(pVCpu);
7289	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7290	return rc;
7291	}
7292
7293
7294	/**
7295	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7296	*/
7297	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7298	{
7299	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7300
7301	/** @todo Stat. */
7302	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7303	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7304	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7305	return VBOXSTRICTRC_VAL(rcStrict);
7306	}
7307
7308
7309	/**
7310	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7311	*/
7312	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7313	{
7314	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7315
7316	/** @todo Stat. */
7317	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7318	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7319	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7320	return VBOXSTRICTRC_VAL(rcStrict);
7321	}
7322
7323
7324	/**
7325	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7326	*/
7327	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7328	{
7329	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7330
7331	/** @todo Stat. */
7332	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7333	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7334	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7335	return VBOXSTRICTRC_VAL(rcStrict);
7336	}
7337
7338
7339	/**
7340	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7341	*/
7342	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7343	{
7344	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7345
7346	/** @todo Stat. */
7347	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7348	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7349	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7350	return VBOXSTRICTRC_VAL(rcStrict);
7351	}
7352
7353
7354	/**
7355	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7356	*/
7357	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7358	{
7359	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7360	/** @todo Stat. */
7361	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7362	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7363	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7364	return VBOXSTRICTRC_VAL(rcStrict);
7365	}
7366
7367
7368	/**
7369	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7370	*/
7371	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7372	{
7373	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7374	/** @todo Stat. */
7375	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7376	#if 0
7377	VBOXSTRICTRC rcStrict;
7378	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7379	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7380	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7381	if (rcStrict == VINF_SUCCESS)
7382	{
7383	rcStrict = VINF_SVM_VMRUN;
7384	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7385	}
7386	return VBOXSTRICTRC_VAL(rcStrict);
7387	#endif
7388	return VERR_EM_INTERPRETER;
7389	}
7390
7391
7392	/**
7393	* Nested-guest \#VMEXIT handler for IRET (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7394	*/
7395	HMSVM_EXIT_DECL hmR0SvmNestedExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7396	{
7397	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7398
7399	/* Clear NMI blocking. */
7400	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7401
7402	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7403	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
7404	hmR0SvmClearIretIntercept(pVmcbNstGst);
7405
7406	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEventNested() and resume guest execution. */
7407	return VINF_SUCCESS;
7408	}
7409
7410
7411	/**
7412	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7413	* Unconditional \#VMEXIT.
7414	*/
7415	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7416	{
7417	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7418
7419	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7420	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7421	* shutdown VMEXIT. */
7422	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7423	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7424	{
7425	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7426	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7427	}
7428
7429	hmR0SvmSetPendingXcptDB(pVCpu);
7430	return VINF_SUCCESS;
7431	}
7432
7433
7434	/**
7435	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7436	* Conditional \#VMEXIT.
7437	*/
7438	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7439	{
7440	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7441
7442	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7443	* shutdown VMEXIT. */
7444	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7445
7446	SVMEVENT Event;
7447	Event.u = 0;
7448	Event.n.u1Valid = 1;
7449	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7450	Event.n.u8Vector = X86_XCPT_BP;
7451	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7452	return VINF_SUCCESS;
7453	}
7454
7455	#endif /* VBOX_WITH_NESTED_HWVIRT */
7456
7457
7458	/** @} */
7459

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 69474

Download in other formats: