HMSVMR0.cpp@ 69713

Last change on this file since 69713 was 69713, checked in by vboxsync, 7 years ago
VMM/HMSVMR0: comment on nCR3 during VMRUN/VMEXIT.
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1	/* $Id: HMSVMR0.cpp 69713 2017-11-16 12:32:33Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/thread.h>
25
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#include <VBox/vmm/apic.h>
33	#include "HMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include "HMSVMR0.h"
36	#include "dtrace/VBoxVMM.h"
37
38	#define HMSVM_USE_IEM_EVENT_REFLECTION
39	#ifdef DEBUG_ramshankar
40	# define HMSVM_SYNC_FULL_GUEST_STATE
41	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
42	# define HMSVM_ALWAYS_TRAP_PF
43	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
44	#endif
45
46
47	/*********************************************************************************************************************************
48	* Defined Constants And Macros *
49	*********************************************************************************************************************************/
50	#ifdef VBOX_WITH_STATISTICS
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
52	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
53	if ((u64ExitCode) == SVM_EXIT_NPF) \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
55	else \
56	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
57	} while (0)
58	#else
59	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
60	#endif
61
62	/** If we decide to use a function table approach this can be useful to
63	* switch to a "static DECLCALLBACK(int)". */
64	#define HMSVM_EXIT_DECL static int
65
66	/** Macro for checking and returning from the using function for
67	* \#VMEXIT intercepts that maybe caused during delivering of another
68	* event in the guest. */
69	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
70	do \
71	{ \
72	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
73	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
74	else if (rc == VINF_HM_DOUBLE_FAULT) \
75	return VINF_SUCCESS; \
76	else \
77	return rc; \
78	} while (0)
79
80	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
81	* instruction that exited. */
82	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
83	do { \
84	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
85	(a_rc) = VINF_EM_DBG_STEPPED; \
86	} while (0)
87
88	/** Assert that preemption is disabled or covered by thread-context hooks. */
89	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
90	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
91
92	/** Assert that we haven't migrated CPUs when thread-context hooks are not
93	* used. */
94	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
95	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
96	("Illegal migration! Entered on CPU %u Current %u\n", \
97	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
98
99	/**
100	* Exception bitmap mask for all contributory exceptions.
101	*
102	* Page fault is deliberately excluded here as it's conditional as to whether
103	* it's contributory or benign. Page faults are handled separately.
104	*/
105	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
106	\| RT_BIT(X86_XCPT_DE))
107
108	/**
109	* Mandatory/unconditional guest control intercepts.
110	*/
111	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
112	\| SVM_CTRL_INTERCEPT_NMI \
113	\| SVM_CTRL_INTERCEPT_INIT \
114	\| SVM_CTRL_INTERCEPT_RDPMC \
115	\| SVM_CTRL_INTERCEPT_CPUID \
116	\| SVM_CTRL_INTERCEPT_RSM \
117	\| SVM_CTRL_INTERCEPT_HLT \
118	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
119	\| SVM_CTRL_INTERCEPT_MSR_PROT \
120	\| SVM_CTRL_INTERCEPT_INVLPGA \
121	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
122	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
123	\| SVM_CTRL_INTERCEPT_VMRUN \
124	\| SVM_CTRL_INTERCEPT_VMMCALL \
125	\| SVM_CTRL_INTERCEPT_VMLOAD \
126	\| SVM_CTRL_INTERCEPT_VMSAVE \
127	\| SVM_CTRL_INTERCEPT_STGI \
128	\| SVM_CTRL_INTERCEPT_CLGI \
129	\| SVM_CTRL_INTERCEPT_SKINIT \
130	\| SVM_CTRL_INTERCEPT_WBINVD \
131	\| SVM_CTRL_INTERCEPT_MONITOR \
132	\| SVM_CTRL_INTERCEPT_MWAIT \
133	\| SVM_CTRL_INTERCEPT_XSETBV)
134
135	/**
136	* Mandatory/unconditional nested-guest control intercepts.
137	*/
138	#define HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS ( HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS \
139	\| SVM_CTRL_INTERCEPT_SMI)
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/\#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG fEFlags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
211	bool fWasGuestFPUStateActive;
212	/** Whether the guest debug state was active at the time of \#VMEXIT. */
213	bool fWasGuestDebugStateActive;
214	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
215	bool fWasHyperDebugStateActive;
216	/** Whether the TSC offset mode needs to be updated. */
217	bool fUpdateTscOffsetting;
218	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
219	bool fRestoreTscAuxMsr;
220	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
221	* contributary exception or a page-fault. */
222	bool fVectoringDoublePF;
223	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
224	* external interrupt or NMI. */
225	bool fVectoringPF;
226	} SVMTRANSIENT, *PSVMTRANSIENT;
227	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
228	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
229	/** @} */
230
231	/**
232	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
233	*/
234	typedef enum SVMMSREXITREAD
235	{
236	/** Reading this MSR causes a \#VMEXIT. */
237	SVMMSREXIT_INTERCEPT_READ = 0xb,
238	/** Reading this MSR does not cause a \#VMEXIT. */
239	SVMMSREXIT_PASSTHRU_READ
240	} SVMMSREXITREAD;
241
242	/**
243	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
244	*/
245	typedef enum SVMMSREXITWRITE
246	{
247	/** Writing to this MSR causes a \#VMEXIT. */
248	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
249	/** Writing to this MSR does not cause a \#VMEXIT. */
250	SVMMSREXIT_PASSTHRU_WRITE
251	} SVMMSREXITWRITE;
252
253	/**
254	* SVM \#VMEXIT handler.
255	*
256	* @returns VBox status code.
257	* @param pVCpu The cross context virtual CPU structure.
258	* @param pMixedCtx Pointer to the guest-CPU context.
259	* @param pSvmTransient Pointer to the SVM-transient structure.
260	*/
261	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262
263
264	/*********************************************************************************************************************************
265	* Internal Functions *
266	*********************************************************************************************************************************/
267	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
268	SVMMSREXITWRITE enmWrite);
269	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
270	static void hmR0SvmLeave(PVMCPU pVCpu);
271
272	/** @name \#VMEXIT handlers.
273	* @{
274	*/
275	static FNSVMEXITHANDLER hmR0SvmExitIntr;
276	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
277	static FNSVMEXITHANDLER hmR0SvmExitInvd;
278	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
279	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
280	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
281	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
282	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
283	static FNSVMEXITHANDLER hmR0SvmExitHlt;
284	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
285	static FNSVMEXITHANDLER hmR0SvmExitMwait;
286	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
287	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
288	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
289	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
290	static FNSVMEXITHANDLER hmR0SvmExitMsr;
291	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
292	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
293	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
294	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
295	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
296	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
297	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
298	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
299	static FNSVMEXITHANDLER hmR0SvmExitPause;
300	static FNSVMEXITHANDLER hmR0SvmExitIret;
301	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
302	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
303	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
304	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
305	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
306	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
307	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
308	#ifdef VBOX_WITH_NESTED_HWVIRT
309	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
310	static FNSVMEXITHANDLER hmR0SvmExitClgi;
311	static FNSVMEXITHANDLER hmR0SvmExitStgi;
312	static FNSVMEXITHANDLER hmR0SvmExitVmload;
313	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
314	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
315	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
316	static FNSVMEXITHANDLER hmR0SvmNestedExitIret;
317	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
318	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
319	#endif
320	/** @} */
321
322	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
323	#ifdef VBOX_WITH_NESTED_HWVIRT
324	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
325	#endif
326
327
328	/*********************************************************************************************************************************
329	* Global Variables *
330	*********************************************************************************************************************************/
331	/** Ring-0 memory object for the IO bitmap. */
332	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
333	/** Physical address of the IO bitmap. */
334	RTHCPHYS g_HCPhysIOBitmap = 0;
335	/** Pointer to the IO bitmap. */
336	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
337
338	#ifdef VBOX_WITH_NESTED_HWVIRT
339	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
340	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
341	/** Physical address of the nested-guest MSRPM bitmap. */
342	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
343	/** Pointer to the nested-guest MSRPM bitmap. */
344	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
345	#endif
346
347	/**
348	* Sets up and activates AMD-V on the current CPU.
349	*
350	* @returns VBox status code.
351	* @param pCpu Pointer to the CPU info struct.
352	* @param pVM The cross context VM structure. Can be
353	* NULL after a resume!
354	* @param pvCpuPage Pointer to the global CPU page.
355	* @param HCPhysCpuPage Physical address of the global CPU page.
356	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
357	* @param pvArg Unused on AMD-V.
358	*/
359	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
360	void *pvArg)
361	{
362	Assert(!fEnabledByHost);
363	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
364	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
365	Assert(pvCpuPage); NOREF(pvCpuPage);
366	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
367
368	NOREF(pvArg);
369	NOREF(fEnabledByHost);
370
371	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
372	RTCCUINTREG fEFlags = ASMIntDisableFlags();
373
374	/*
375	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
376	*/
377	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
378	if (u64HostEfer & MSR_K6_EFER_SVME)
379	{
380	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
381	if ( pVM
382	&& pVM->hm.s.svm.fIgnoreInUseError)
383	{
384	pCpu->fIgnoreAMDVInUseError = true;
385	}
386
387	if (!pCpu->fIgnoreAMDVInUseError)
388	{
389	ASMSetFlags(fEFlags);
390	return VERR_SVM_IN_USE;
391	}
392	}
393
394	/* Turn on AMD-V in the EFER MSR. */
395	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
396
397	/* Write the physical page address where the CPU will store the host state while executing the VM. */
398	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
399
400	/* Restore interrupts. */
401	ASMSetFlags(fEFlags);
402
403	/*
404	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
405	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
406	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
407	* guest code.
408	*/
409	pCpu->fFlushAsidBeforeUse = true;
410
411	/*
412	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
413	*/
414	++pCpu->cTlbFlushes;
415
416	return VINF_SUCCESS;
417	}
418
419
420	/**
421	* Deactivates AMD-V on the current CPU.
422	*
423	* @returns VBox status code.
424	* @param pCpu Pointer to the CPU info struct.
425	* @param pvCpuPage Pointer to the global CPU page.
426	* @param HCPhysCpuPage Physical address of the global CPU page.
427	*/
428	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
429	{
430	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
431	AssertReturn( HCPhysCpuPage
432	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
433	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
434	NOREF(pCpu);
435
436	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
437	RTCCUINTREG fEFlags = ASMIntDisableFlags();
438
439	/* Turn off AMD-V in the EFER MSR. */
440	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
441	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
442
443	/* Invalidate host state physical address. */
444	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
445
446	/* Restore interrupts. */
447	ASMSetFlags(fEFlags);
448
449	return VINF_SUCCESS;
450	}
451
452
453	/**
454	* Does global AMD-V initialization (called during module initialization).
455	*
456	* @returns VBox status code.
457	*/
458	VMMR0DECL(int) SVMR0GlobalInit(void)
459	{
460	/*
461	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
462	* once globally here instead of per-VM.
463	*/
464	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
465	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
466	if (RT_FAILURE(rc))
467	return rc;
468
469	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
470	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
471
472	/* Set all bits to intercept all IO accesses. */
473	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
474
475	#ifdef VBOX_WITH_NESTED_HWVIRT
476	/*
477	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
478	*/
479	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
480	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
481	if (RT_FAILURE(rc))
482	return rc;
483
484	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
485	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
486
487	/* Set all bits to intercept all MSR accesses. */
488	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
489	#endif
490
491	return VINF_SUCCESS;
492	}
493
494
495	/**
496	* Does global AMD-V termination (called during module termination).
497	*/
498	VMMR0DECL(void) SVMR0GlobalTerm(void)
499	{
500	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
501	{
502	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
503	g_pvIOBitmap = NULL;
504	g_HCPhysIOBitmap = 0;
505	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
506	}
507
508	#ifdef VBOX_WITH_NESTED_HWVIRT
509	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
510	{
511	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
512	g_pvNstGstMsrBitmap = NULL;
513	g_HCPhysNstGstMsrBitmap = 0;
514	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
515	}
516	#endif
517	}
518
519
520	/**
521	* Frees any allocated per-VCPU structures for a VM.
522	*
523	* @param pVM The cross context VM structure.
524	*/
525	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
526	{
527	for (uint32_t i = 0; i < pVM->cCpus; i++)
528	{
529	PVMCPU pVCpu = &pVM->aCpus[i];
530	AssertPtr(pVCpu);
531
532	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
533	{
534	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
535	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
536	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
537	}
538
539	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
540	{
541	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
542	pVCpu->hm.s.svm.pVmcb = NULL;
543	pVCpu->hm.s.svm.HCPhysVmcb = 0;
544	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
545	}
546
547	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
548	{
549	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
550	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
551	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
552	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
553	}
554	}
555	}
556
557
558	/**
559	* Does per-VM AMD-V initialization.
560	*
561	* @returns VBox status code.
562	* @param pVM The cross context VM structure.
563	*/
564	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
565	{
566	int rc = VERR_INTERNAL_ERROR_5;
567
568	/*
569	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
570	*/
571	uint32_t u32Family;
572	uint32_t u32Model;
573	uint32_t u32Stepping;
574	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
575	{
576	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
577	pVM->hm.s.svm.fAlwaysFlushTLB = true;
578	}
579
580	/*
581	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
582	*/
583	for (VMCPUID i = 0; i < pVM->cCpus; i++)
584	{
585	PVMCPU pVCpu = &pVM->aCpus[i];
586	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
587	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
588	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
589	}
590
591	for (VMCPUID i = 0; i < pVM->cCpus; i++)
592	{
593	PVMCPU pVCpu = &pVM->aCpus[i];
594
595	/*
596	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
597	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
598	*/
599	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
600	if (RT_FAILURE(rc))
601	goto failure_cleanup;
602
603	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
604	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
605	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
606	ASMMemZeroPage(pvVmcbHost);
607
608	/*
609	* Allocate one page for the guest-state VMCB.
610	*/
611	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
612	if (RT_FAILURE(rc))
613	goto failure_cleanup;
614
615	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
616	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
617	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
618	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
619
620	/*
621	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
622	* SVM to not require one.
623	*/
624	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
625	false /* fExecutable */);
626	if (RT_FAILURE(rc))
627	goto failure_cleanup;
628
629	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
630	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
631	/* Set all bits to intercept all MSR accesses (changed later on). */
632	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
633	}
634
635	return VINF_SUCCESS;
636
637	failure_cleanup:
638	hmR0SvmFreeStructs(pVM);
639	return rc;
640	}
641
642
643	/**
644	* Does per-VM AMD-V termination.
645	*
646	* @returns VBox status code.
647	* @param pVM The cross context VM structure.
648	*/
649	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
650	{
651	hmR0SvmFreeStructs(pVM);
652	return VINF_SUCCESS;
653	}
654
655
656	/**
657	* Sets the permission bits for the specified MSR in the MSRPM.
658	*
659	* @param pVmcb Pointer to the VM control block.
660	* @param pbMsrBitmap Pointer to the MSR bitmap.
661	* @param uMsr The MSR for which the access permissions are being set.
662	* @param enmRead MSR read permissions.
663	* @param enmWrite MSR write permissions.
664	*/
665	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
666	SVMMSREXITWRITE enmWrite)
667	{
668	uint16_t offMsrpm;
669	uint32_t uMsrpmBit;
670	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
671	AssertRC(rc);
672
673	Assert(uMsrpmBit < 0x3fff);
674	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
675
676	pbMsrBitmap += offMsrpm;
677	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
678	ASMBitSet(pbMsrBitmap, uMsrpmBit);
679	else
680	ASMBitClear(pbMsrBitmap, uMsrpmBit);
681
682	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
683	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
684	else
685	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
686
687	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
688	}
689
690
691	/**
692	* Sets up AMD-V for the specified VM.
693	* This function is only called once per-VM during initalization.
694	*
695	* @returns VBox status code.
696	* @param pVM The cross context VM structure.
697	*/
698	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
699	{
700	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
701	AssertReturn(pVM, VERR_INVALID_PARAMETER);
702	Assert(pVM->hm.s.svm.fSupported);
703
704	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
705	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
706	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
707
708	for (VMCPUID i = 0; i < pVM->cCpus; i++)
709	{
710	PVMCPU pVCpu = &pVM->aCpus[i];
711	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
712
713	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
714
715	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
716	Assert(!pVCpu->hm.s.idxExitHistoryFree);
717	HMCPU_EXIT_HISTORY_RESET(pVCpu);
718
719	/* Always trap #AC for reasons of security. */
720	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
721
722	/* Always trap #DB for reasons of security. */
723	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
724
725	/* Trap exceptions unconditionally (debug purposes). */
726	#ifdef HMSVM_ALWAYS_TRAP_PF
727	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
728	#endif
729	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
730	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
731	pVmcb->ctrl.u32InterceptXcpt \|= 0
732	\| RT_BIT(X86_XCPT_BP)
733	\| RT_BIT(X86_XCPT_DE)
734	\| RT_BIT(X86_XCPT_NM)
735	\| RT_BIT(X86_XCPT_UD)
736	\| RT_BIT(X86_XCPT_NP)
737	\| RT_BIT(X86_XCPT_SS)
738	\| RT_BIT(X86_XCPT_GP)
739	\| RT_BIT(X86_XCPT_PF)
740	\| RT_BIT(X86_XCPT_MF)
741	;
742	#endif
743
744	/* Set up unconditional intercepts and conditions. */
745	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
746
747	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
748	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
749
750	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
751	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
752
753	/* Intercept all DRx reads and writes by default. Changed later on. */
754	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
755	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
756
757	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
758	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
759
760	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
761	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
762	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
763
764	/* Set IO and MSR bitmap permission bitmap physical addresses. */
765	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
766	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
767
768	/* No LBR virtualization. */
769	pVmcb->ctrl.u64LBRVirt = 0;
770
771	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
772	pVmcb->ctrl.u64VmcbCleanBits = 0;
773
774	/* The host ASID MBZ, for the guest start with 1. */
775	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
776
777	/*
778	* Setup the PAT MSR (applicable for Nested Paging only).
779	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
780	* so choose type 6 for all PAT slots.
781	*/
782	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
783
784	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
785	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
786
787	/* Without Nested Paging, we need additionally intercepts. */
788	if (!pVM->hm.s.fNestedPaging)
789	{
790	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
791	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
792	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
793
794	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
795	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
796	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
797
798	/* Page faults must be intercepted to implement shadow paging. */
799	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
800	}
801
802	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
803	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
804	#endif
805
806	/* Apply the exceptions intercepts needed by the GIM provider. */
807	if (pVCpu->hm.s.fGIMTrapXcptUD)
808	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
809
810	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
811	if (fUsePauseFilter)
812	{
813	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
814	if (fPauseFilterThreshold)
815	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
816	}
817
818	/*
819	* The following MSRs are saved/restored automatically during the world-switch.
820	* Don't intercept guest read/write accesses to these MSRs.
821	*/
822	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
823	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
824	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
825	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
826	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
827	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
828	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
829	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
830	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
831	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
832	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
833	}
834
835	return VINF_SUCCESS;
836	}
837
838
839	/**
840	* Invalidates a guest page by guest virtual address.
841	*
842	* @returns VBox status code.
843	* @param pVM The cross context VM structure.
844	* @param pVCpu The cross context virtual CPU structure.
845	* @param GCVirt Guest virtual address of the page to invalidate.
846	*/
847	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
848	{
849	AssertReturn(pVM, VERR_INVALID_PARAMETER);
850	Assert(pVM->hm.s.svm.fSupported);
851
852	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
853
854	/* Skip it if a TLB flush is already pending. */
855	if (!fFlushPending)
856	{
857	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
858
859	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
860	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
861
862	#if HC_ARCH_BITS == 32
863	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
864	if (CPUMIsGuestInLongMode(pVCpu))
865	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
866	else
867	#endif
868	{
869	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
870	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
871	}
872	}
873	return VINF_SUCCESS;
874	}
875
876
877	/**
878	* Flushes the appropriate tagged-TLB entries.
879	*
880	* @param pVCpu The cross context virtual CPU structure.
881	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
882	* @param pVmcb Pointer to the VM control block.
883	*/
884	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
885	{
886	PVM pVM = pVCpu->CTX_SUFF(pVM);
887	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
888
889	/*
890	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
891	* This can happen both for start & resume due to long jumps back to ring-3.
892	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
893	* so we cannot reuse the ASIDs without flushing.
894	*/
895	bool fNewAsid = false;
896	Assert(pCpu->idCpu != NIL_RTCPUID);
897	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
898	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
899	{
900	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
901	pVCpu->hm.s.fForceTLBFlush = true;
902	fNewAsid = true;
903	}
904
905	/* Set TLB flush state as checked until we return from the world switch. */
906	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
907
908	/* Check for explicit TLB flushes. */
909	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
910	{
911	pVCpu->hm.s.fForceTLBFlush = true;
912	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
913	}
914
915	/*
916	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
917	* This Host CPU requirement takes precedence.
918	*/
919	if (pVM->hm.s.svm.fAlwaysFlushTLB)
920	{
921	pCpu->uCurrentAsid = 1;
922	pVCpu->hm.s.uCurrentAsid = 1;
923	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
924	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
925
926	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
927	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
928
929	/* Keep track of last CPU ID even when flushing all the time. */
930	if (fNewAsid)
931	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
932	}
933	else
934	{
935	#ifdef VBOX_WITH_NESTED_HWVIRT
936	/*
937	* Only if the nested hypervisor says it does not need to flush anything in the TLB,
938	* can we possibly apply it on the host. Otherwise, the nested-guest TLB flush setting
939	* should be used and then the host settings be added on top.
940	*/
941	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
942	{
943	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
944	if (pVmcbNstGstCache->TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
945	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
946	else
947	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = pVmcbNstGstCache->TLBCtrl.n.u8TLBFlush;
948	}
949	#else
950	RT_NOREF(pCtx);
951	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
952	#endif
953	if (pVCpu->hm.s.fForceTLBFlush)
954	{
955	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
956	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
957
958	if (fNewAsid)
959	{
960	++pCpu->uCurrentAsid;
961
962	bool fHitASIDLimit = false;
963	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
964	{
965	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
966	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
967	fHitASIDLimit = true;
968	}
969
970	if ( fHitASIDLimit
971	\|\| pCpu->fFlushAsidBeforeUse)
972	{
973	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
974	pCpu->fFlushAsidBeforeUse = false;
975	}
976
977	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
978	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
979	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
980	}
981	else
982	{
983	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
984	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
985	else
986	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
987	}
988
989	pVCpu->hm.s.fForceTLBFlush = false;
990	}
991	}
992
993	/* Update VMCB with the ASID. */
994	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
995	{
996	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
997	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
998	}
999
1000	#ifdef VBOX_WITH_NESTED_HWVIRT
1001	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx) \|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush != SVM_TLB_FLUSH_NOTHING);
1002	#endif
1003
1004	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
1005	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1006	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1007	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1008	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1009	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1010	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1011	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1012
1013	#ifdef VBOX_WITH_STATISTICS
1014	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1015	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1016	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1017	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1018	{
1019	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1020	}
1021	else
1022	{
1023	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1024	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1025	}
1026	#endif
1027	}
1028
1029
1030	/** @name 64-bit guest on 32-bit host OS helper functions.
1031	*
1032	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1033	* mode (code segment, paging). These wrappers/helpers perform the necessary
1034	* bits for the 32->64 switcher.
1035	*
1036	* @{ */
1037	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1038	/**
1039	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1040	*
1041	* @returns VBox status code.
1042	* @param HCPhysVmcbHost Physical address of host VMCB.
1043	* @param HCPhysVmcb Physical address of the VMCB.
1044	* @param pCtx Pointer to the guest-CPU context.
1045	* @param pVM The cross context VM structure.
1046	* @param pVCpu The cross context virtual CPU structure.
1047	*/
1048	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1049	{
1050	uint32_t aParam[8];
1051	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1052	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1053	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1054	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1055	aParam[4] = VM_RC_ADDR(pVM, pVM);
1056	aParam[5] = 0;
1057	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1058	aParam[7] = 0;
1059
1060	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1061	}
1062
1063
1064	/**
1065	* Executes the specified VMRUN handler in 64-bit mode.
1066	*
1067	* @returns VBox status code.
1068	* @param pVM The cross context VM structure.
1069	* @param pVCpu The cross context virtual CPU structure.
1070	* @param pCtx Pointer to the guest-CPU context.
1071	* @param enmOp The operation to perform.
1072	* @param cParams Number of parameters.
1073	* @param paParam Array of 32-bit parameters.
1074	*/
1075	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1076	uint32_t cParams, uint32_t *paParam)
1077	{
1078	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1079	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1080
1081	NOREF(pCtx);
1082
1083	/* Disable interrupts. */
1084	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1085
1086	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1087	RTCPUID idHostCpu = RTMpCpuId();
1088	CPUMR0SetLApic(pVCpu, idHostCpu);
1089	#endif
1090
1091	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1092	CPUMSetHyperEIP(pVCpu, enmOp);
1093	for (int i = (int)cParams - 1; i >= 0; i--)
1094	CPUMPushHyper(pVCpu, paParam[i]);
1095
1096	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1097	/* Call the switcher. */
1098	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1099	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1100
1101	/* Restore interrupts. */
1102	ASMSetFlags(uOldEFlags);
1103	return rc;
1104	}
1105
1106	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1107	/** @} */
1108
1109
1110	/**
1111	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1112	* the corresponding VMCB Clean bit.
1113	*
1114	* @param pVmcb Pointer to the VM control block.
1115	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1116	*/
1117	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1118	{
1119	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1120	{
1121	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1122	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1123	}
1124	}
1125
1126
1127	/**
1128	* Removes an exception from the intercept-exception bitmap in the VMCB and
1129	* updates the corresponding VMCB Clean bit.
1130	*
1131	* @param pVmcb Pointer to the VM control block.
1132	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1133	*/
1134	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1135	{
1136	Assert(u32Xcpt != X86_XCPT_DB);
1137	Assert(u32Xcpt != X86_XCPT_AC);
1138	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1139	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1140	{
1141	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1142	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1143	}
1144	#endif
1145	}
1146
1147
1148	/**
1149	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1150	* Although the guest CR0 is a separate field in the VMCB we have to consider
1151	* the FPU state itself which is shared between the host and the guest.
1152	*
1153	* @returns VBox status code.
1154	* @param pVCpu The cross context virtual CPU structure.
1155	* @param pVmcb Pointer to the VM control block.
1156	* @param pCtx Pointer to the guest-CPU context.
1157	*
1158	* @remarks No-long-jump zone!!!
1159	*/
1160	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1161	{
1162	uint64_t u64GuestCR0 = pCtx->cr0;
1163
1164	/* Always enable caching. */
1165	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1166
1167	/*
1168	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1169	*/
1170	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1171	{
1172	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1173	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1174	}
1175
1176	/*
1177	* Guest FPU bits.
1178	*/
1179	bool fInterceptNM = false;
1180	bool fInterceptMF = false;
1181	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1182	if (CPUMIsGuestFPUStateActive(pVCpu))
1183	{
1184	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1185	if (!(pCtx->cr0 & X86_CR0_NE))
1186	{
1187	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1188	fInterceptMF = true;
1189	}
1190	}
1191	else
1192	{
1193	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1194	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1195	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1196	}
1197
1198	/*
1199	* Update the exception intercept bitmap.
1200	*/
1201	if (fInterceptNM)
1202	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1203	else
1204	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1205
1206	if (fInterceptMF)
1207	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1208	else
1209	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1210
1211	pVmcb->guest.u64CR0 = u64GuestCR0;
1212	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1213	}
1214
1215
1216	/**
1217	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1218	*
1219	* @returns VBox status code.
1220	* @param pVCpu The cross context virtual CPU structure.
1221	* @param pVmcb Pointer to the VM control block.
1222	* @param pCtx Pointer to the guest-CPU context.
1223	*
1224	* @remarks No-long-jump zone!!!
1225	*/
1226	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1227	{
1228	PVM pVM = pVCpu->CTX_SUFF(pVM);
1229
1230	/*
1231	* Guest CR2.
1232	*/
1233	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1234	{
1235	pVmcb->guest.u64CR2 = pCtx->cr2;
1236	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1237	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1238	}
1239
1240	/*
1241	* Guest CR3.
1242	*/
1243	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1244	{
1245	if (pVM->hm.s.fNestedPaging)
1246	{
1247	PGMMODE enmShwPagingMode;
1248	#if HC_ARCH_BITS == 32
1249	if (CPUMIsGuestInLongModeEx(pCtx))
1250	enmShwPagingMode = PGMMODE_AMD64_NX;
1251	else
1252	#endif
1253	enmShwPagingMode = PGMGetHostMode(pVM);
1254
1255	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1256	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1257	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1258	pVmcb->guest.u64CR3 = pCtx->cr3;
1259	}
1260	else
1261	{
1262	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1263	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1264	}
1265
1266	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1267	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1268	}
1269
1270	/*
1271	* Guest CR4.
1272	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1273	*/
1274	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1275	{
1276	uint64_t u64GuestCR4 = pCtx->cr4;
1277	Assert(RT_HI_U32(u64GuestCR4) == 0);
1278	if (!pVM->hm.s.fNestedPaging)
1279	{
1280	switch (pVCpu->hm.s.enmShadowMode)
1281	{
1282	case PGMMODE_REAL:
1283	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1284	AssertFailed();
1285	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1286
1287	case PGMMODE_32_BIT: /* 32-bit paging. */
1288	u64GuestCR4 &= ~X86_CR4_PAE;
1289	break;
1290
1291	case PGMMODE_PAE: /* PAE paging. */
1292	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1293	/** Must use PAE paging as we could use physical memory > 4 GB */
1294	u64GuestCR4 \|= X86_CR4_PAE;
1295	break;
1296
1297	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1298	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1299	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1300	break;
1301	#else
1302	AssertFailed();
1303	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1304	#endif
1305
1306	default: /* shut up gcc */
1307	AssertFailed();
1308	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1309	}
1310	}
1311
1312	pVmcb->guest.u64CR4 = u64GuestCR4;
1313	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1314
1315	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1316	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1317
1318	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1319	}
1320
1321	return VINF_SUCCESS;
1322	}
1323
1324
1325	#ifdef VBOX_WITH_NESTED_HWVIRT
1326	/**
1327	* Loads the nested-guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1328	*
1329	* @returns VBox status code.
1330	* @param pVCpu The cross context virtual CPU structure.
1331	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1332	* @param pCtx Pointer to the guest-CPU context.
1333	*
1334	* @remarks No-long-jump zone!!!
1335	*/
1336	static int hmR0SvmLoadGuestControlRegsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1337	{
1338	/*
1339	* Guest CR0.
1340	*/
1341	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1342	{
1343	pVmcbNstGst->guest.u64CR0 = pCtx->cr0;
1344	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1345	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1346	}
1347
1348	return hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
1349	}
1350	#endif
1351
1352
1353	/**
1354	* Loads the guest segment registers into the VMCB.
1355	*
1356	* @returns VBox status code.
1357	* @param pVCpu The cross context virtual CPU structure.
1358	* @param pVmcb Pointer to the VM control block.
1359	* @param pCtx Pointer to the guest-CPU context.
1360	*
1361	* @remarks No-long-jump zone!!!
1362	*/
1363	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1364	{
1365	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1366	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1367	{
1368	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1369	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1370	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1371	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1372	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1373	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1374
1375	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1376	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1377	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1378	}
1379
1380	/* Guest TR. */
1381	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1382	{
1383	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1384	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1385	}
1386
1387	/* Guest LDTR. */
1388	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1389	{
1390	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1391	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1392	}
1393
1394	/* Guest GDTR. */
1395	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1396	{
1397	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1398	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1399	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1400	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1401	}
1402
1403	/* Guest IDTR. */
1404	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1405	{
1406	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1407	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1408	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1409	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1410	}
1411	}
1412
1413
1414	/**
1415	* Loads the guest MSRs into the VMCB.
1416	*
1417	* @param pVCpu The cross context virtual CPU structure.
1418	* @param pVmcb Pointer to the VM control block.
1419	* @param pCtx Pointer to the guest-CPU context.
1420	*
1421	* @remarks No-long-jump zone!!!
1422	*/
1423	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1424	{
1425	/* Guest Sysenter MSRs. */
1426	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1427	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1428	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1429
1430	/*
1431	* Guest EFER MSR.
1432	* AMD-V requires guest EFER.SVME to be set. Weird.
1433	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1434	*/
1435	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1436	{
1437	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1438	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1439	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1440	}
1441
1442	/* 64-bit MSRs. */
1443	if (CPUMIsGuestInLongModeEx(pCtx))
1444	{
1445	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1446	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1447	}
1448	else
1449	{
1450	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1451	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1452	{
1453	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1454	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1455	}
1456	}
1457
1458	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1459	* be writable in 32-bit mode. Clarify with AMD spec. */
1460	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1461	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1462	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1463	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1464	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1465	}
1466
1467
1468	/**
1469	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1470	* necessary intercepts accordingly.
1471	*
1472	* @param pVCpu The cross context virtual CPU structure.
1473	* @param pVmcb Pointer to the VM control block.
1474	* @param pCtx Pointer to the guest-CPU context.
1475	*
1476	* @remarks No-long-jump zone!!!
1477	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1478	*/
1479	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1480	{
1481	bool fInterceptMovDRx = false;
1482
1483	/*
1484	* Anyone single stepping on the host side? If so, we'll have to use the
1485	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1486	* the VMM level like the VT-x implementations does.
1487	*/
1488	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1489	if (fStepping)
1490	{
1491	pVCpu->hm.s.fClearTrapFlag = true;
1492	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1493	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1494	}
1495	else
1496	Assert(!DBGFIsStepping(pVCpu));
1497
1498	if ( fStepping
1499	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1500	{
1501	/*
1502	* Use the combined guest and host DRx values found in the hypervisor
1503	* register set because the debugger has breakpoints active or someone
1504	* is single stepping on the host side.
1505	*
1506	* Note! DBGF expects a clean DR6 state before executing guest code.
1507	*/
1508	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1509	if ( CPUMIsGuestInLongModeEx(pCtx)
1510	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1511	{
1512	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1513	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1514	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1515	}
1516	else
1517	#endif
1518	if (!CPUMIsHyperDebugStateActive(pVCpu))
1519	{
1520	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1521	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1522	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1523	}
1524
1525	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1526	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1527	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1528	{
1529	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1530	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1531	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1532	pVCpu->hm.s.fUsingHyperDR7 = true;
1533	}
1534
1535	/** @todo If we cared, we could optimize to allow the guest to read registers
1536	* with the same values. */
1537	fInterceptMovDRx = true;
1538	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1539	}
1540	else
1541	{
1542	/*
1543	* Update DR6, DR7 with the guest values if necessary.
1544	*/
1545	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1546	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1547	{
1548	pVmcb->guest.u64DR7 = pCtx->dr[7];
1549	pVmcb->guest.u64DR6 = pCtx->dr[6];
1550	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1551	pVCpu->hm.s.fUsingHyperDR7 = false;
1552	}
1553
1554	/*
1555	* If the guest has enabled debug registers, we need to load them prior to
1556	* executing guest code so they'll trigger at the right time.
1557	*/
1558	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1559	{
1560	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1561	if ( CPUMIsGuestInLongModeEx(pCtx)
1562	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1563	{
1564	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1565	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1566	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1567	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1568	}
1569	else
1570	#endif
1571	if (!CPUMIsGuestDebugStateActive(pVCpu))
1572	{
1573	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1574	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1575	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1576	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1577	}
1578	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1579	}
1580	/*
1581	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1582	* intercept #DB as DR6 is updated in the VMCB.
1583	*
1584	* Note! If we cared and dared, we could skip intercepting \#DB here.
1585	* However, \#DB shouldn't be performance critical, so we'll play safe
1586	* and keep the code similar to the VT-x code and always intercept it.
1587	*/
1588	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1589	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1590	&& !CPUMIsGuestDebugStateActive(pVCpu))
1591	#else
1592	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1593	#endif
1594	{
1595	fInterceptMovDRx = true;
1596	}
1597	}
1598
1599	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1600	if (fInterceptMovDRx)
1601	{
1602	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1603	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1604	{
1605	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1606	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1607	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1608	}
1609	}
1610	else
1611	{
1612	if ( pVmcb->ctrl.u16InterceptRdDRx
1613	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1614	{
1615	pVmcb->ctrl.u16InterceptRdDRx = 0;
1616	pVmcb->ctrl.u16InterceptWrDRx = 0;
1617	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1618	}
1619	}
1620	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1621	}
1622
1623
1624	#ifdef VBOX_WITH_NESTED_HWVIRT
1625	/**
1626	* Loads the nested-guest APIC state (currently just the TPR).
1627	*
1628	* @param pVCpu The cross context virtual CPU structure.
1629	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1630	*/
1631	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1632	{
1633	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1634	{
1635	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1636	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1637	pVCpu->hm.s.svm.fSyncVTpr = false;
1638	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1639
1640	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1641	}
1642	}
1643	#endif
1644
1645	/**
1646	* Loads the guest APIC state (currently just the TPR).
1647	*
1648	* @returns VBox status code.
1649	* @param pVCpu The cross context virtual CPU structure.
1650	* @param pVmcb Pointer to the VM control block.
1651	* @param pCtx Pointer to the guest-CPU context.
1652	*/
1653	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1654	{
1655	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1656	return VINF_SUCCESS;
1657
1658	int rc = VINF_SUCCESS;
1659	PVM pVM = pVCpu->CTX_SUFF(pVM);
1660	if ( PDMHasApic(pVM)
1661	&& APICIsEnabled(pVCpu))
1662	{
1663	bool fPendingIntr;
1664	uint8_t u8Tpr;
1665	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1666	AssertRCReturn(rc, rc);
1667
1668	/* Assume that we need to trap all TPR accesses and thus need not check on
1669	every #VMEXIT if we should update the TPR. */
1670	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1671	pVCpu->hm.s.svm.fSyncVTpr = false;
1672
1673	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1674	if (pVM->hm.s.fTPRPatchingActive)
1675	{
1676	pCtx->msrLSTAR = u8Tpr;
1677	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1678
1679	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1680	if (fPendingIntr)
1681	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1682	else
1683	{
1684	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1685	pVCpu->hm.s.svm.fSyncVTpr = true;
1686	}
1687	}
1688	else
1689	{
1690	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1691	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1692
1693	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1694	if (fPendingIntr)
1695	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1696	else
1697	{
1698	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1699	pVCpu->hm.s.svm.fSyncVTpr = true;
1700	}
1701
1702	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1703	}
1704	}
1705
1706	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1707	return rc;
1708	}
1709
1710
1711	/**
1712	* Loads the exception interrupts required for guest (or nested-guest) execution in
1713	* the VMCB.
1714	*
1715	* @param pVCpu The cross context virtual CPU structure.
1716	* @param pVmcb Pointer to the VM control block.
1717	*/
1718	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb)
1719	{
1720	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1721	{
1722	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1723	if (pVCpu->hm.s.fGIMTrapXcptUD)
1724	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1725	else
1726	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1727
1728	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1729	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1730	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1731	else
1732	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_BP);
1733
1734	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1735	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1736	}
1737	}
1738
1739
1740	#ifdef VBOX_WITH_NESTED_HWVIRT
1741	/**
1742	* Loads the intercepts required for nested-guest execution in the VMCB.
1743	*
1744	* This merges the guest and nested-guest intercepts in a way that if the outer
1745	* guest intercepts an exception we need to intercept it in the nested-guest as
1746	* well and handle it accordingly.
1747	*
1748	* @param pVCpu The cross context virtual CPU structure.
1749	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1750	*/
1751	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1752	{
1753	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1754	{
1755	/* First, load the guest intercepts into the guest VMCB. */
1756	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1757	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb);
1758
1759	/* Next, merge the intercepts into the nested-guest VMCB. */
1760	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1761	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1762
1763	/*
1764	* CR3, CR4 reads and writes are intercepted as we modify them before
1765	* hardware-assisted SVM execution. In addition, PGM needs to be up to date
1766	* on paging mode changes in the nested-guest.
1767	*
1768	* CR0 writes are intercepted in case of paging mode changes. CR0 reads are not
1769	* intercepted as we currently don't modify CR0 while executing the nested-guest.
1770	*/
1771	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(4) \| RT_BIT(3);
1772	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(0);
1773
1774	/** @todo Figure out debugging with nested-guests, till then just intercept
1775	* all DR[0-15] accesses. */
1776	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
1777	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
1778
1779	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
1780	pVmcbNstGst->ctrl.u64InterceptCtrl \|= pVmcb->ctrl.u64InterceptCtrl
1781	\| HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS;
1782	/*
1783	* Remove control intercepts that we don't need while executing the nested-guest.
1784	*
1785	* VMMCALL when not intercepted raises a \#UD exception in the guest. However,
1786	* other SVM instructions like VMSAVE when not intercept can cause havoc on the
1787	* host as they can write to any location in physical memory, hence they always
1788	* need to be intercepted (they are included in HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS).
1789	*/
1790	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
1791	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
1792	pVmcbNstGst->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VMMCALL;
1793
1794	/* Remove exception intercepts that we don't need while executing the nested-guest. */
1795	pVmcbNstGst->ctrl.u32InterceptXcpt &= ~RT_BIT(X86_XCPT_UD);
1796
1797	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
1798	}
1799	}
1800	#endif
1801
1802
1803	/**
1804	* Sets up the appropriate function to run guest code.
1805	*
1806	* @returns VBox status code.
1807	* @param pVCpu The cross context virtual CPU structure.
1808	*
1809	* @remarks No-long-jump zone!!!
1810	*/
1811	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
1812	{
1813	if (CPUMIsGuestInLongMode(pVCpu))
1814	{
1815	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1816	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1817	#endif
1818	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1819	#if HC_ARCH_BITS == 32
1820	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1821	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1822	#else
1823	/* 64-bit host or hybrid host. */
1824	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1825	#endif
1826	}
1827	else
1828	{
1829	/* Guest is not in long mode, use the 32-bit handler. */
1830	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1831	}
1832	return VINF_SUCCESS;
1833	}
1834
1835
1836	/**
1837	* Enters the AMD-V session.
1838	*
1839	* @returns VBox status code.
1840	* @param pVM The cross context VM structure.
1841	* @param pVCpu The cross context virtual CPU structure.
1842	* @param pCpu Pointer to the CPU info struct.
1843	*/
1844	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1845	{
1846	AssertPtr(pVM);
1847	AssertPtr(pVCpu);
1848	Assert(pVM->hm.s.svm.fSupported);
1849	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1850	NOREF(pVM); NOREF(pCpu);
1851
1852	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1853	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1854
1855	pVCpu->hm.s.fLeaveDone = false;
1856	return VINF_SUCCESS;
1857	}
1858
1859
1860	/**
1861	* Thread-context callback for AMD-V.
1862	*
1863	* @param enmEvent The thread-context event.
1864	* @param pVCpu The cross context virtual CPU structure.
1865	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1866	* @thread EMT(pVCpu)
1867	*/
1868	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1869	{
1870	NOREF(fGlobalInit);
1871
1872	switch (enmEvent)
1873	{
1874	case RTTHREADCTXEVENT_OUT:
1875	{
1876	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1877	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1878	VMCPU_ASSERT_EMT(pVCpu);
1879
1880	/* No longjmps (log-flush, locks) in this fragile context. */
1881	VMMRZCallRing3Disable(pVCpu);
1882
1883	if (!pVCpu->hm.s.fLeaveDone)
1884	{
1885	hmR0SvmLeave(pVCpu);
1886	pVCpu->hm.s.fLeaveDone = true;
1887	}
1888
1889	/* Leave HM context, takes care of local init (term). */
1890	int rc = HMR0LeaveCpu(pVCpu);
1891	AssertRC(rc); NOREF(rc);
1892
1893	/* Restore longjmp state. */
1894	VMMRZCallRing3Enable(pVCpu);
1895	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
1896	break;
1897	}
1898
1899	case RTTHREADCTXEVENT_IN:
1900	{
1901	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1902	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1903	VMCPU_ASSERT_EMT(pVCpu);
1904
1905	/* No longjmps (log-flush, locks) in this fragile context. */
1906	VMMRZCallRing3Disable(pVCpu);
1907
1908	/*
1909	* Initialize the bare minimum state required for HM. This takes care of
1910	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1911	*/
1912	int rc = HMR0EnterCpu(pVCpu);
1913	AssertRC(rc); NOREF(rc);
1914	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1915
1916	pVCpu->hm.s.fLeaveDone = false;
1917
1918	/* Restore longjmp state. */
1919	VMMRZCallRing3Enable(pVCpu);
1920	break;
1921	}
1922
1923	default:
1924	break;
1925	}
1926	}
1927
1928
1929	/**
1930	* Saves the host state.
1931	*
1932	* @returns VBox status code.
1933	* @param pVM The cross context VM structure.
1934	* @param pVCpu The cross context virtual CPU structure.
1935	*
1936	* @remarks No-long-jump zone!!!
1937	*/
1938	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1939	{
1940	NOREF(pVM);
1941	NOREF(pVCpu);
1942	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1943	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1944	return VINF_SUCCESS;
1945	}
1946
1947
1948	/**
1949	* Loads the guest state into the VMCB.
1950	*
1951	* The CPU state will be loaded from these fields on every successful VM-entry.
1952	* Also sets up the appropriate VMRUN function to execute guest code based on
1953	* the guest CPU mode.
1954	*
1955	* @returns VBox status code.
1956	* @param pVM The cross context VM structure.
1957	* @param pVCpu The cross context virtual CPU structure.
1958	* @param pCtx Pointer to the guest-CPU context.
1959	*
1960	* @remarks No-long-jump zone!!!
1961	*/
1962	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1963	{
1964	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1965	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1966
1967	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1968
1969	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1970	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1971
1972	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1973	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1974
1975	pVmcb->guest.u64RIP = pCtx->rip;
1976	pVmcb->guest.u64RSP = pCtx->rsp;
1977	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1978	pVmcb->guest.u64RAX = pCtx->rax;
1979
1980	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1981	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1982
1983	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb);
1984
1985	rc = hmR0SvmSetupVMRunHandler(pVCpu);
1986	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1987
1988	/* Clear any unused and reserved bits. */
1989	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1990	\| HM_CHANGED_GUEST_RSP
1991	\| HM_CHANGED_GUEST_RFLAGS
1992	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1993	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1994	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1995	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1996	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1997	\| HM_CHANGED_SVM_RESERVED2
1998	\| HM_CHANGED_SVM_RESERVED3
1999	\| HM_CHANGED_SVM_RESERVED4);
2000
2001	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2002	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2003	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2004	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2005
2006	Log4(("hmR0SvmLoadGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32\n", pCtx->cs.Sel, pCtx->rip,
2007	pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
2008	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2009	return rc;
2010	}
2011
2012
2013	#ifdef VBOX_WITH_NESTED_HWVIRT
2014	/**
2015	* Caches the nested-guest VMCB fields before we modify them for execution using
2016	* hardware-assisted SVM.
2017	*
2018	* @param pCtx Pointer to the guest-CPU context.
2019	*
2020	* @sa HMSvmNstGstVmExitNotify.
2021	*/
2022	static void hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2023	{
2024	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2025	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2026	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2027	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2028
2029	/*
2030	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2031	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2032	*
2033	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2034	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2035	*/
2036	if (!pNstGstVmcbCache->fValid)
2037	{
2038	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2039	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2040	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2041	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2042	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2043	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2044	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2045	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2046	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2047	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2048	pNstGstVmcbCache->u64VmcbCleanBits = pVmcbNstGstCtrl->u64VmcbCleanBits;
2049	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2050	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2051	pNstGstVmcbCache->NestedPagingCtrl = pVmcbNstGstCtrl->NestedPaging;
2052	pNstGstVmcbCache->fValid = true;
2053	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2054	}
2055	}
2056
2057
2058	/**
2059	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2060	*
2061	* @param pVCpu The cross context virtual CPU structure.
2062	* @param pCtx Pointer to the guest-CPU context.
2063	*/
2064	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2065	{
2066	RT_NOREF(pVCpu);
2067	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2068	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2069
2070	/*
2071	* First cache the nested-guest VMCB fields we may potentially modify.
2072	*/
2073	hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2074
2075	/*
2076	* The IOPM of the nested-guest can be ignored because the the guest always
2077	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2078	* into the nested-guest one and swap it back on the #VMEXIT.
2079	*/
2080	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2081
2082	/*
2083	* Load the host-physical address into the MSRPM rather than the nested-guest
2084	* physical address (currently we trap all MSRs in the nested-guest).
2085	*/
2086	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2087
2088	/*
2089	* Use the same nested-paging as the "outer" guest. We can't dynamically
2090	* switch off nested-paging suddenly while executing a VM (see assertion at the
2091	* end of Trap0eHandler in PGMAllBth.h).
2092	*/
2093	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2094	}
2095
2096
2097	/**
2098	* Loads the nested-guest state into the VMCB.
2099	*
2100	* @returns VBox status code.
2101	* @param pVCpu The cross context virtual CPU structure.
2102	* @param pCtx Pointer to the guest-CPU context.
2103	*
2104	* @remarks No-long-jump zone!!!
2105	*/
2106	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2107	{
2108	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2109
2110	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2111	Assert(pVmcbNstGst);
2112
2113	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2114
2115	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2116	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2117
2118	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2119	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2120	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2121	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2122
2123	int rc = hmR0SvmLoadGuestControlRegsNested(pVCpu, pVmcbNstGst, pCtx);
2124	AssertRCReturn(rc, rc);
2125
2126	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2127	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst);
2128
2129	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2130	AssertRCReturn(rc, rc);
2131
2132	/* Clear any unused and reserved bits. */
2133	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2134	\| HM_CHANGED_GUEST_RSP
2135	\| HM_CHANGED_GUEST_RFLAGS
2136	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2137	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2138	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2139	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2140	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2141	\| HM_CHANGED_SVM_RESERVED2
2142	\| HM_CHANGED_SVM_RESERVED3
2143	\| HM_CHANGED_SVM_RESERVED4);
2144
2145	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2146	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2147	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2148	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2149
2150	Log4(("hmR0SvmLoadGuestStateNested: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 (HyperCR3=%#RX64) CR4=%#RX32 rc=%d\n",
2151	pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pVmcbNstGst->guest.u64CR3, pCtx->cr4, rc));
2152	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2153	return rc;
2154	}
2155	#endif
2156
2157
2158	/**
2159	* Loads the state shared between the host and guest or nested-guest into the
2160	* VMCB.
2161	*
2162	* @param pVCpu The cross context virtual CPU structure.
2163	* @param pVmcb Pointer to the VM control block.
2164	* @param pCtx Pointer to the guest-CPU context.
2165	*
2166	* @remarks No-long-jump zone!!!
2167	*/
2168	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2169	{
2170	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2171	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2172
2173	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2174	{
2175	#ifdef VBOX_WITH_NESTED_HWVIRT
2176	/* We use nested-guest CR0 unmodified, hence nothing to do here. */
2177	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2178	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2179	else
2180	Assert(pVmcb->guest.u64CR0 == pCtx->cr0);
2181	#else
2182	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2183	#endif
2184	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2185	}
2186
2187	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2188	{
2189	/* We use nested-guest CR0 unmodified, hence nothing to do here. */
2190	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2191	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2192	else
2193	{
2194	pVmcb->guest.u64DR6 = pCtx->dr[6];
2195	pVmcb->guest.u64DR7 = pCtx->dr[7];
2196	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2197	}
2198
2199	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2200	}
2201
2202	/* Unused on AMD-V. */
2203	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2204
2205	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2206	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2207	}
2208
2209
2210	/**
2211	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU context.
2212	*
2213	* Currently there is no residual state left in the CPU that is not updated in the
2214	* VMCB.
2215	*
2216	* @returns VBox status code.
2217	* @param pVCpu The cross context virtual CPU structure.
2218	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2219	* out-of-sync. Make sure to update the required fields
2220	* before using them.
2221	* @param pVmcb Pointer to the VM control block.
2222	*/
2223	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2224	{
2225	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2226
2227	pMixedCtx->rip = pVmcb->guest.u64RIP;
2228	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2229	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2230	pMixedCtx->rax = pVmcb->guest.u64RAX;
2231
2232	/*
2233	* Guest interrupt shadow.
2234	*/
2235	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
2236	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2237	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2238	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2239
2240	/*
2241	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2242	*/
2243	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2244
2245	#ifdef VBOX_WITH_NESTED_GUEST
2246	/*
2247	* The nested hypervisor might not be intercepting these control registers,
2248	*/
2249	if (CPUMIsGuestInNestedHwVirtMode(pMixedCtx))
2250	{
2251	pMixedCtx->cr4 = pVmcb->guest.u64CR4;
2252	pMixedCtx->cr0 = pVmcb->guest.u64CR0;
2253	}
2254	#endif
2255
2256	/*
2257	* Guest MSRs.
2258	*/
2259	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2260	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2261	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2262	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2263	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2264	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2265	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2266	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2267
2268	/*
2269	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2270	*/
2271	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2272	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2273	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2274	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2275	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2276	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2277
2278	/*
2279	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2280	* register (yet).
2281	*/
2282	/** @todo SELM might need to be fixed as it too should not care about the
2283	* granularity bit. See @bugref{6785}. */
2284	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2285	&& pMixedCtx->cs.Attr.n.u1Present
2286	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2287	{
2288	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2289	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2290	}
2291
2292	#ifdef VBOX_STRICT
2293	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
2294	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
2295	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
2296	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
2297	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
2298	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
2299	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
2300
2301	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2302	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2303	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2304	HMSVM_ASSERT_SEG_GRANULARITY(es);
2305	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2306	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2307
2308	# undef HMSVM_ASSERT_SEL_GRANULARITY
2309	#endif
2310
2311	/*
2312	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2313	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2314	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2315	* See AMD spec. 15.5.1 "Basic operation".
2316	*/
2317	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2318	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2319
2320	/*
2321	* Guest TR.
2322	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2323	* between Intel and AMD. See @bugref{6208#c39}.
2324	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2325	*/
2326	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2327	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2328	{
2329	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2330	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2331	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2332	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2333	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2334	}
2335
2336	/*
2337	* Guest Descriptor-Table registers.
2338	*/
2339	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2340	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2341	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2342
2343	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2344	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2345
2346	/*
2347	* Guest Debug registers.
2348	*/
2349	if (!pVCpu->hm.s.fUsingHyperDR7)
2350	{
2351	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2352	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2353	}
2354	else
2355	{
2356	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2357	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2358	}
2359
2360	/*
2361	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2362	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2363	*/
2364	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2365	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2366	{
2367	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2368	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2369	}
2370	}
2371
2372
2373	/**
2374	* Does the necessary state syncing before returning to ring-3 for any reason
2375	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2376	*
2377	* @param pVCpu The cross context virtual CPU structure.
2378	*
2379	* @remarks No-long-jmp zone!!!
2380	*/
2381	static void hmR0SvmLeave(PVMCPU pVCpu)
2382	{
2383	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2384	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2385	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2386
2387	/*
2388	* !!! IMPORTANT !!!
2389	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2390	*/
2391
2392	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2393	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2394	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2395
2396	/*
2397	* Restore host debug registers if necessary and resync on next R0 reentry.
2398	*/
2399	#ifdef VBOX_STRICT
2400	if (CPUMIsHyperDebugStateActive(pVCpu))
2401	{
2402	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2403	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2404	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2405	}
2406	#endif
2407	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2408	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2409
2410	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2411	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2412
2413	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2414	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2415	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2416	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2417	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2418
2419	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2420	}
2421
2422
2423	/**
2424	* Leaves the AMD-V session.
2425	*
2426	* @returns VBox status code.
2427	* @param pVCpu The cross context virtual CPU structure.
2428	*/
2429	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2430	{
2431	HM_DISABLE_PREEMPT();
2432	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2433	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2434
2435	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2436	and done this from the SVMR0ThreadCtxCallback(). */
2437	if (!pVCpu->hm.s.fLeaveDone)
2438	{
2439	hmR0SvmLeave(pVCpu);
2440	pVCpu->hm.s.fLeaveDone = true;
2441	}
2442
2443	/*
2444	* !!! IMPORTANT !!!
2445	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2446	*/
2447
2448	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2449	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2450	VMMR0ThreadCtxHookDisable(pVCpu);
2451
2452	/* Leave HM context. This takes care of local init (term). */
2453	int rc = HMR0LeaveCpu(pVCpu);
2454
2455	HM_RESTORE_PREEMPT();
2456	return rc;
2457	}
2458
2459
2460	/**
2461	* Does the necessary state syncing before doing a longjmp to ring-3.
2462	*
2463	* @returns VBox status code.
2464	* @param pVCpu The cross context virtual CPU structure.
2465	*
2466	* @remarks No-long-jmp zone!!!
2467	*/
2468	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2469	{
2470	return hmR0SvmLeaveSession(pVCpu);
2471	}
2472
2473
2474	/**
2475	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2476	* any remaining host state) before we longjump to ring-3 and possibly get
2477	* preempted.
2478	*
2479	* @param pVCpu The cross context virtual CPU structure.
2480	* @param enmOperation The operation causing the ring-3 longjump.
2481	* @param pvUser The user argument (pointer to the possibly
2482	* out-of-date guest-CPU context).
2483	*/
2484	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2485	{
2486	RT_NOREF_PV(pvUser);
2487
2488	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2489	{
2490	/*
2491	* !!! IMPORTANT !!!
2492	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2493	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2494	*/
2495	VMMRZCallRing3RemoveNotification(pVCpu);
2496	VMMRZCallRing3Disable(pVCpu);
2497	HM_DISABLE_PREEMPT();
2498
2499	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2500	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2501
2502	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2503	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2504
2505	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2506	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2507	VMMR0ThreadCtxHookDisable(pVCpu);
2508
2509	/* Leave HM context. This takes care of local init (term). */
2510	HMR0LeaveCpu(pVCpu);
2511
2512	HM_RESTORE_PREEMPT();
2513	return VINF_SUCCESS;
2514	}
2515
2516	Assert(pVCpu);
2517	Assert(pvUser);
2518	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2519	HMSVM_ASSERT_PREEMPT_SAFE();
2520
2521	VMMRZCallRing3Disable(pVCpu);
2522	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2523
2524	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2525	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2526	AssertRCReturn(rc, rc);
2527
2528	VMMRZCallRing3Enable(pVCpu);
2529	return VINF_SUCCESS;
2530	}
2531
2532
2533	/**
2534	* Take necessary actions before going back to ring-3.
2535	*
2536	* An action requires us to go back to ring-3. This function does the necessary
2537	* steps before we can safely return to ring-3. This is not the same as longjmps
2538	* to ring-3, this is voluntary.
2539	*
2540	* @returns VBox status code.
2541	* @param pVM The cross context VM structure.
2542	* @param pVCpu The cross context virtual CPU structure.
2543	* @param pCtx Pointer to the guest-CPU context.
2544	* @param rcExit The reason for exiting to ring-3. Can be
2545	* VINF_VMM_UNKNOWN_RING3_CALL.
2546	*/
2547	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2548	{
2549	Assert(pVM);
2550	Assert(pVCpu);
2551	Assert(pCtx);
2552	HMSVM_ASSERT_PREEMPT_SAFE();
2553
2554	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2555	VMMRZCallRing3Disable(pVCpu);
2556	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2557
2558	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2559	if (pVCpu->hm.s.Event.fPending)
2560	{
2561	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2562	Assert(!pVCpu->hm.s.Event.fPending);
2563	}
2564
2565	/* Sync. the necessary state for going back to ring-3. */
2566	hmR0SvmLeaveSession(pVCpu);
2567	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2568
2569	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2570	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2571	\| CPUM_CHANGED_LDTR
2572	\| CPUM_CHANGED_GDTR
2573	\| CPUM_CHANGED_IDTR
2574	\| CPUM_CHANGED_TR
2575	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2576	if ( pVM->hm.s.fNestedPaging
2577	&& CPUMIsGuestPagingEnabledEx(pCtx))
2578	{
2579	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2580	}
2581
2582	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2583	if (rcExit != VINF_EM_RAW_INTERRUPT)
2584	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2585
2586	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2587
2588	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2589	VMMRZCallRing3RemoveNotification(pVCpu);
2590	VMMRZCallRing3Enable(pVCpu);
2591
2592	/*
2593	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2594	* and if we're injecting an event we should have a TRPM trap pending.
2595	*/
2596	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2597	pVCpu->hm.s.u32HMError = rcExit,
2598	VERR_SVM_IPE_5);
2599	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2600	pVCpu->hm.s.u32HMError = rcExit,
2601	VERR_SVM_IPE_4);
2602
2603	return rcExit;
2604	}
2605
2606
2607	/**
2608	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2609	* intercepts.
2610	*
2611	* @param pVM The cross context VM structure.
2612	* @param pVCpu The cross context virtual CPU structure.
2613	* @param pVmcb Pointer to the VM control block.
2614	*
2615	* @remarks No-long-jump zone!!!
2616	*/
2617	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2618	{
2619	bool fParavirtTsc;
2620	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2621	if (fCanUseRealTsc)
2622	{
2623	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2624	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2625	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2626	}
2627	else
2628	{
2629	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2630	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2631	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2632	}
2633	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2634
2635	/** @todo later optimize this to be done elsewhere and not before every
2636	* VM-entry. */
2637	if (fParavirtTsc)
2638	{
2639	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2640	information before every VM-entry, hence disable it for performance sake. */
2641	#if 0
2642	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2643	AssertRC(rc);
2644	#endif
2645	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2646	}
2647	}
2648
2649
2650	/**
2651	* Sets an event as a pending event to be injected into the guest.
2652	*
2653	* @param pVCpu The cross context virtual CPU structure.
2654	* @param pEvent Pointer to the SVM event.
2655	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2656	* page-fault.
2657	*
2658	* @remarks Statistics counter assumes this is a guest event being reflected to
2659	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2660	*/
2661	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2662	{
2663	Assert(!pVCpu->hm.s.Event.fPending);
2664	Assert(pEvent->n.u1Valid);
2665
2666	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2667	pVCpu->hm.s.Event.fPending = true;
2668	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2669
2670	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2671	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2672	}
2673
2674
2675	/**
2676	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
2677	*
2678	* @param pVCpu The cross context virtual CPU structure.
2679	*/
2680	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
2681	{
2682	SVMEVENT Event;
2683	Event.u = 0;
2684	Event.n.u1Valid = 1;
2685	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2686	Event.n.u8Vector = X86_XCPT_UD;
2687	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2688	}
2689
2690
2691	/**
2692	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
2693	*
2694	* @param pVCpu The cross context virtual CPU structure.
2695	*/
2696	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
2697	{
2698	SVMEVENT Event;
2699	Event.u = 0;
2700	Event.n.u1Valid = 1;
2701	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2702	Event.n.u8Vector = X86_XCPT_DB;
2703	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2704	}
2705
2706
2707	/**
2708	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
2709	*
2710	* @param pVCpu The cross context virtual CPU structure.
2711	* @param pCtx Pointer to the guest-CPU context.
2712	* @param u32ErrCode The error-code for the page-fault.
2713	* @param uFaultAddress The page fault address (CR2).
2714	*
2715	* @remarks This updates the guest CR2 with @a uFaultAddress!
2716	*/
2717	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
2718	{
2719	SVMEVENT Event;
2720	Event.u = 0;
2721	Event.n.u1Valid = 1;
2722	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2723	Event.n.u8Vector = X86_XCPT_PF;
2724	Event.n.u1ErrorCodeValid = 1;
2725	Event.n.u32ErrorCode = u32ErrCode;
2726
2727	/* Update CR2 of the guest. */
2728	if (pCtx->cr2 != uFaultAddress)
2729	{
2730	pCtx->cr2 = uFaultAddress;
2731	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
2732	}
2733
2734	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
2735	}
2736
2737
2738	/**
2739	* Sets a device-not-available (\#NM) exception as pending-for-injection into
2740	* the VM.
2741	*
2742	* @param pVCpu The cross context virtual CPU structure.
2743	*/
2744	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
2745	{
2746	SVMEVENT Event;
2747	Event.u = 0;
2748	Event.n.u1Valid = 1;
2749	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2750	Event.n.u8Vector = X86_XCPT_NM;
2751	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2752	}
2753
2754
2755	/**
2756	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
2757	*
2758	* @param pVCpu The cross context virtual CPU structure.
2759	*/
2760	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
2761	{
2762	SVMEVENT Event;
2763	Event.u = 0;
2764	Event.n.u1Valid = 1;
2765	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2766	Event.n.u8Vector = X86_XCPT_MF;
2767	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2768	}
2769
2770
2771	/**
2772	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
2773	*
2774	* @param pVCpu The cross context virtual CPU structure.
2775	*/
2776	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
2777	{
2778	SVMEVENT Event;
2779	Event.u = 0;
2780	Event.n.u1Valid = 1;
2781	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2782	Event.n.u8Vector = X86_XCPT_DF;
2783	Event.n.u1ErrorCodeValid = 1;
2784	Event.n.u32ErrorCode = 0;
2785	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2786	}
2787
2788
2789	/**
2790	* Injects an event into the guest upon VMRUN by updating the relevant field
2791	* in the VMCB.
2792	*
2793	* @param pVCpu The cross context virtual CPU structure.
2794	* @param pVmcb Pointer to the guest VM control block.
2795	* @param pCtx Pointer to the guest-CPU context.
2796	* @param pEvent Pointer to the event.
2797	*
2798	* @remarks No-long-jump zone!!!
2799	* @remarks Requires CR0!
2800	*/
2801	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2802	{
2803	NOREF(pVCpu); NOREF(pCtx);
2804
2805	pVmcb->ctrl.EventInject.u = pEvent->u;
2806	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2807
2808	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2809	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2810	}
2811
2812
2813
2814	/**
2815	* Converts any TRPM trap into a pending HM event. This is typically used when
2816	* entering from ring-3 (not longjmp returns).
2817	*
2818	* @param pVCpu The cross context virtual CPU structure.
2819	*/
2820	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2821	{
2822	Assert(TRPMHasTrap(pVCpu));
2823	Assert(!pVCpu->hm.s.Event.fPending);
2824
2825	uint8_t uVector;
2826	TRPMEVENT enmTrpmEvent;
2827	RTGCUINT uErrCode;
2828	RTGCUINTPTR GCPtrFaultAddress;
2829	uint8_t cbInstr;
2830
2831	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2832	AssertRC(rc);
2833
2834	SVMEVENT Event;
2835	Event.u = 0;
2836	Event.n.u1Valid = 1;
2837	Event.n.u8Vector = uVector;
2838
2839	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2840	if (enmTrpmEvent == TRPM_TRAP)
2841	{
2842	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2843	switch (uVector)
2844	{
2845	case X86_XCPT_NMI:
2846	{
2847	Event.n.u3Type = SVM_EVENT_NMI;
2848	break;
2849	}
2850
2851	case X86_XCPT_PF:
2852	case X86_XCPT_DF:
2853	case X86_XCPT_TS:
2854	case X86_XCPT_NP:
2855	case X86_XCPT_SS:
2856	case X86_XCPT_GP:
2857	case X86_XCPT_AC:
2858	{
2859	Event.n.u1ErrorCodeValid = 1;
2860	Event.n.u32ErrorCode = uErrCode;
2861	break;
2862	}
2863	}
2864	}
2865	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2866	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2867	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2868	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2869	else
2870	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2871
2872	rc = TRPMResetTrap(pVCpu);
2873	AssertRC(rc);
2874
2875	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2876	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2877
2878	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2879	}
2880
2881
2882	/**
2883	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2884	* AMD-V to execute any instruction.
2885	*
2886	* @param pVCpu The cross context virtual CPU structure.
2887	*/
2888	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2889	{
2890	Assert(pVCpu->hm.s.Event.fPending);
2891	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2892
2893	SVMEVENT Event;
2894	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2895
2896	uint8_t uVector = Event.n.u8Vector;
2897	uint8_t uVectorType = Event.n.u3Type;
2898	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
2899
2900	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2901
2902	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2903	AssertRC(rc);
2904
2905	if (Event.n.u1ErrorCodeValid)
2906	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2907
2908	if ( uVectorType == SVM_EVENT_EXCEPTION
2909	&& uVector == X86_XCPT_PF)
2910	{
2911	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2912	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2913	}
2914	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2915	{
2916	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2917	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2918	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2919	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2920	}
2921	pVCpu->hm.s.Event.fPending = false;
2922	}
2923
2924
2925	/**
2926	* Checks if the guest (or nested-guest) has an interrupt shadow active right
2927	* now.
2928	*
2929	* @returns true if the interrupt shadow is active, false otherwise.
2930	* @param pVCpu The cross context virtual CPU structure.
2931	* @param pCtx Pointer to the guest-CPU context.
2932	*
2933	* @remarks No-long-jump zone!!!
2934	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2935	*/
2936	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
2937	{
2938	/*
2939	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2940	* inhibit interrupts or clear any existing interrupt-inhibition.
2941	*/
2942	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2943	{
2944	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2945	{
2946	/*
2947	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2948	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2949	*/
2950	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2951	return false;
2952	}
2953	return true;
2954	}
2955	return false;
2956	}
2957
2958
2959	/**
2960	* Sets the virtual interrupt intercept control in the VMCB which
2961	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
2962	* receive interrupts.
2963	*
2964	* @param pVmcb Pointer to the VM control block.
2965	*/
2966	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2967	{
2968	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
2969	{
2970	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1; /* A virtual interrupt is pending. */
2971	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0; /* Vector not necessary as we #VMEXIT for delivering the interrupt. */
2972	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
2973	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2974
2975	Log4(("Setting VINTR intercept\n"));
2976	}
2977	}
2978
2979
2980	#if 0
2981	/**
2982	* Clears the virtual interrupt intercept control in the VMCB as
2983	* we are figured the guest is unable process any interrupts
2984	* at this point of time.
2985	*
2986	* @param pVmcb Pointer to the VM control block.
2987	*/
2988	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
2989	{
2990	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
2991	{
2992	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
2993	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2994	Log4(("Clearing VINTR intercept\n"));
2995	}
2996	}
2997	#endif
2998
2999
3000	/**
3001	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3002	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3003	* virtual NMIs.
3004	*
3005	* @param pVmcb Pointer to the VM control block.
3006	*/
3007	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3008	{
3009	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3010	{
3011	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3012	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3013
3014	Log4(("Setting IRET intercept\n"));
3015	}
3016	}
3017
3018
3019	/**
3020	* Clears the IRET intercept control in the VMCB.
3021	*
3022	* @param pVmcb Pointer to the VM control block.
3023	*/
3024	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3025	{
3026	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3027	{
3028	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3029	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3030
3031	Log4(("Clearing IRET intercept\n"));
3032	}
3033	}
3034
3035	#ifdef VBOX_WITH_NESTED_HWVIRT
3036	/**
3037	* Evaluates the event to be delivered to the nested-guest and sets it as the
3038	* pending event.
3039	*
3040	* @returns VBox strict status code.
3041	* @param pVCpu The cross context virtual CPU structure.
3042	* @param pCtx Pointer to the guest-CPU context.
3043	*/
3044	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3045	{
3046	Log4Func(("\n"));
3047
3048	Assert(!pVCpu->hm.s.Event.fPending);
3049
3050	bool const fGif = pCtx->hwvirt.svm.fGif;
3051	if (fGif)
3052	{
3053	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3054
3055	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3056
3057	/*
3058	* Check if the nested-guest can receive NMIs.
3059	* NMIs are higher priority than regular interrupts.
3060	*/
3061	/** @todo SMI. SMIs take priority over NMIs. */
3062	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3063	{
3064	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3065	if (fBlockNmi)
3066	hmR0SvmSetIretIntercept(pVmcbNstGst);
3067	else if (fIntShadow)
3068	{
3069	/** @todo Figure this out, how we shall manage virt. intercept if the
3070	* nested-guest already has one set and/or if we really need it? */
3071	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3072	}
3073	else
3074	{
3075	Log4(("Pending NMI\n"));
3076
3077	SVMEVENT Event;
3078	Event.u = 0;
3079	Event.n.u1Valid = 1;
3080	Event.n.u8Vector = X86_XCPT_NMI;
3081	Event.n.u3Type = SVM_EVENT_NMI;
3082
3083	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3084	hmR0SvmSetIretIntercept(pVmcbNstGst);
3085	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3086	return VINF_SUCCESS;
3087	}
3088	}
3089
3090	/*
3091	* Check if the nested-guest can receive external interrupts (generated by
3092	* the guest's PIC/APIC).
3093	*
3094	* External intercepts from the physical CPU are -always- intercepted when
3095	* executing using hardware-assisted SVM, see HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS.
3096	*
3097	* External interrupts that are generated for the outer guest may be intercepted
3098	* depending on how the nested-guest VMCB was programmed by guest software.
3099	*
3100	* Physical interrupts always take priority over virtual interrupts,
3101	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3102	*/
3103	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3104	&& !fIntShadow
3105	&& !pVCpu->hm.s.fSingleInstruction
3106	&& CPUMCanSvmNstGstTakePhysIntr(pCtx))
3107	{
3108	if (CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_INTR))
3109	{
3110	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3111	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3112	}
3113
3114	uint8_t u8Interrupt;
3115	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3116	if (RT_SUCCESS(rc))
3117	{
3118	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3119
3120	SVMEVENT Event;
3121	Event.u = 0;
3122	Event.n.u1Valid = 1;
3123	Event.n.u8Vector = u8Interrupt;
3124	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3125
3126	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3127	}
3128	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3129	{
3130	/*
3131	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3132	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3133	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3134	*/
3135	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3136	}
3137	else
3138	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3139	}
3140
3141	/*
3142	* Check if the nested-guest can receive virtual (injected by VMRUN) interrupts.
3143	* We can call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any
3144	* nested-guest VMCB interrupt control fields besides V_INTR_MASKING, see hmR0SvmVmRunCacheVmcb.
3145	*/
3146	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3147	&& CPUMCanSvmNstGstTakeVirtIntr(pCtx)
3148	&& CPUMIsGuestSvmCtrlInterceptSet(pCtx, SVM_CTRL_INTERCEPT_VINTR))
3149	{
3150	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3151	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3152	}
3153	}
3154
3155	return VINF_SUCCESS;
3156	}
3157	#endif
3158
3159	/**
3160	* Evaluates the event to be delivered to the guest and sets it as the pending
3161	* event.
3162	*
3163	* @param pVCpu The cross context virtual CPU structure.
3164	* @param pCtx Pointer to the guest-CPU context.
3165	*/
3166	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3167	{
3168	Assert(!pVCpu->hm.s.Event.fPending);
3169
3170	#ifdef VBOX_WITH_NESTED_HWVIRT
3171	bool const fGif = pCtx->hwvirt.svm.fGif;
3172	#else
3173	bool const fGif = true;
3174	#endif
3175	Log4Func(("fGif=%RTbool\n", fGif));
3176
3177	/*
3178	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3179	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3180	*/
3181	if (fGif)
3182	{
3183	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3184	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3185	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3186	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3187
3188	Log4Func(("fGif=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fGif, fBlockInt, fIntShadow,
3189	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3190
3191	/** @todo SMI. SMIs take priority over NMIs. */
3192	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3193	{
3194	if (fBlockNmi)
3195	hmR0SvmSetIretIntercept(pVmcb);
3196	else if (fIntShadow)
3197	hmR0SvmSetVirtIntrIntercept(pVmcb);
3198	else
3199	{
3200	Log4(("Pending NMI\n"));
3201
3202	SVMEVENT Event;
3203	Event.u = 0;
3204	Event.n.u1Valid = 1;
3205	Event.n.u8Vector = X86_XCPT_NMI;
3206	Event.n.u3Type = SVM_EVENT_NMI;
3207
3208	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3209	hmR0SvmSetIretIntercept(pVmcb);
3210	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3211	return;
3212	}
3213	}
3214	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3215	&& !pVCpu->hm.s.fSingleInstruction)
3216	{
3217	/*
3218	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3219	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3220	*/
3221	if ( !fBlockInt
3222	&& !fIntShadow)
3223	{
3224	uint8_t u8Interrupt;
3225	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3226	if (RT_SUCCESS(rc))
3227	{
3228	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3229
3230	SVMEVENT Event;
3231	Event.u = 0;
3232	Event.n.u1Valid = 1;
3233	Event.n.u8Vector = u8Interrupt;
3234	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3235
3236	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3237	}
3238	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3239	{
3240	/*
3241	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3242	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3243	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3244	*/
3245	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3246	}
3247	else
3248	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3249	}
3250	else
3251	hmR0SvmSetVirtIntrIntercept(pVmcb);
3252	}
3253	}
3254	}
3255
3256
3257	/**
3258	* Injects any pending events into the guest or nested-guest.
3259	*
3260	* @param pVCpu The cross context virtual CPU structure.
3261	* @param pCtx Pointer to the guest-CPU context.
3262	* @param pVmcb Pointer to the VM control block.
3263	*/
3264	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3265	{
3266	Assert(!TRPMHasTrap(pVCpu));
3267	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3268
3269	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3270
3271	/*
3272	* When executing the nested-guest, we avoid assertions on whether the
3273	* event injection is valid purely based on EFLAGS, as V_INTR_MASKING
3274	* affects the interpretation of interruptibility (see CPUMCanSvmNstGstTakePhysIntr).
3275	*/
3276	#ifndef VBOX_WITH_NESTED_HWVIRT
3277	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3278	#endif
3279
3280	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
3281	{
3282	SVMEVENT Event;
3283	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3284	Assert(Event.n.u1Valid);
3285
3286	#ifndef VBOX_WITH_NESTED_HWVIRT
3287	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3288	{
3289	Assert(!fBlockInt);
3290	Assert(!fIntShadow);
3291	}
3292	else if (Event.n.u3Type == SVM_EVENT_NMI)
3293	Assert(!fIntShadow);
3294	NOREF(fBlockInt);
3295	#else
3296	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3297	#endif
3298
3299	Log4(("Injecting pending HM event\n"));
3300	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3301	pVCpu->hm.s.Event.fPending = false;
3302
3303	#ifdef VBOX_WITH_STATISTICS
3304	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3305	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3306	else
3307	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3308	#endif
3309	}
3310
3311	/*
3312	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3313	*
3314	* For nested-guests: We need to update it too for the scenario where IEM executes
3315	* the nested-guest but execution later continues here with an interrupt shadow active.
3316	*/
3317	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
3318	}
3319
3320
3321	/**
3322	* Reports world-switch error and dumps some useful debug info.
3323	*
3324	* @param pVM The cross context VM structure.
3325	* @param pVCpu The cross context virtual CPU structure.
3326	* @param rcVMRun The return code from VMRUN (or
3327	* VERR_SVM_INVALID_GUEST_STATE for invalid
3328	* guest-state).
3329	* @param pCtx Pointer to the guest-CPU context.
3330	*/
3331	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3332	{
3333	NOREF(pCtx);
3334	HMSVM_ASSERT_PREEMPT_SAFE();
3335	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3336
3337	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3338	{
3339	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3340	#ifdef VBOX_STRICT
3341	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
3342	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3343	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3344	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3345	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3346	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3347	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3348	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3349	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3350	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3351
3352	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3353	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3354	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3355
3356	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3357	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3358	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
3359	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3360	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3361	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3362	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3363	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3364	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3365	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3366
3367	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
3368	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3369	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3370	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3371	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3372	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3373	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3374	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3375	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3376	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3377	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
3378	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3379	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3380	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3381	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3382	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3383	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3384
3385	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3386	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
3387
3388	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3389	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3390	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3391	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3392	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3393	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3394	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3395	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3396	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3397	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3398	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3399	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3400	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3401	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3402	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3403	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3404	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3405	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3406	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3407	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3408
3409	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3410	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3411
3412	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3413	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3414	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3415	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3416
3417	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3418	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3419
3420	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3421	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3422	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3423	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3424
3425	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3426	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3427	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3428	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3429	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3430	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3431	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3432
3433	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3434	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3435	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3436	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3437
3438	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3439	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3440	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3441
3442	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3443	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3444	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3445	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3446	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3447	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3448	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3449	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3450	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3451	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3452	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3453	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3454	#endif /* VBOX_STRICT */
3455	}
3456	else
3457	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3458
3459	NOREF(pVmcb);
3460	}
3461
3462
3463	/**
3464	* Check per-VM and per-VCPU force flag actions that require us to go back to
3465	* ring-3 for one reason or another.
3466	*
3467	* @returns VBox status code (information status code included).
3468	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3469	* ring-3.
3470	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3471	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3472	* interrupts)
3473	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3474	* all EMTs to be in ring-3.
3475	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3476	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3477	* to the EM loop.
3478	*
3479	* @param pVM The cross context VM structure.
3480	* @param pVCpu The cross context virtual CPU structure.
3481	* @param pCtx Pointer to the guest-CPU context.
3482	*/
3483	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3484	{
3485	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3486
3487	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3488	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3489	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3490
3491	/* Update pending interrupts into the APIC's IRR. */
3492	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3493	APICUpdatePendingInterrupts(pVCpu);
3494
3495	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3496	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3497	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3498	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3499	{
3500	/* Pending PGM C3 sync. */
3501	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3502	{
3503	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3504	if (rc != VINF_SUCCESS)
3505	{
3506	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3507	return rc;
3508	}
3509	}
3510
3511	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3512	/* -XXX- what was that about single stepping? */
3513	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3514	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3515	{
3516	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3517	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3518	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3519	return rc;
3520	}
3521
3522	/* Pending VM request packets, such as hardware interrupts. */
3523	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3524	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3525	{
3526	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3527	return VINF_EM_PENDING_REQUEST;
3528	}
3529
3530	/* Pending PGM pool flushes. */
3531	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3532	{
3533	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3534	return VINF_PGM_POOL_FLUSH_PENDING;
3535	}
3536
3537	/* Pending DMA requests. */
3538	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3539	{
3540	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3541	return VINF_EM_RAW_TO_R3;
3542	}
3543	}
3544
3545	return VINF_SUCCESS;
3546	}
3547
3548
3549	#ifdef VBOX_WITH_NESTED_HWVIRT
3550	/**
3551	* Does the preparations before executing nested-guest code in AMD-V.
3552	*
3553	* @returns VBox status code (informational status codes included).
3554	* @retval VINF_SUCCESS if we can proceed with running the guest.
3555	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3556	*
3557	* @param pVM The cross context VM structure.
3558	* @param pVCpu The cross context virtual CPU structure.
3559	* @param pCtx Pointer to the guest-CPU context.
3560	* @param pSvmTransient Pointer to the SVM transient structure.
3561	*
3562	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3563	* @sa hmR0SvmPreRunGuest.
3564	*/
3565	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3566	{
3567	HMSVM_ASSERT_PREEMPT_SAFE();
3568
3569	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3570	{
3571	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3572	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3573	return VINF_EM_RESCHEDULE_REM;
3574	#endif
3575	}
3576	else
3577	return VINF_SVM_VMEXIT;
3578
3579	/* Check force flag actions that might require us to go back to ring-3. */
3580	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3581	if (rc != VINF_SUCCESS)
3582	return rc;
3583
3584	if (TRPMHasTrap(pVCpu))
3585	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3586	else if (!pVCpu->hm.s.Event.fPending)
3587	{
3588	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3589	if (rcStrict != VINF_SUCCESS)
3590	return VBOXSTRICTRC_VAL(rcStrict);
3591	}
3592
3593	/*
3594	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3595	* Just do it in software, see @bugref{8411}.
3596	* NB: If we could continue a task switch exit we wouldn't need to do this.
3597	*/
3598	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3599	&& pVCpu->hm.s.Event.fPending
3600	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
3601	{
3602	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3603	}
3604
3605	/*
3606	* Load the nested-guest state.
3607	*/
3608	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
3609	AssertRCReturn(rc, rc);
3610	/** @todo Get new STAM counter for this? */
3611	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3612
3613	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fValid);
3614
3615	/*
3616	* No longjmps to ring-3 from this point on!!!
3617	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3618	* This also disables flushing of the R0-logger instance (if any).
3619	*/
3620	VMMRZCallRing3Disable(pVCpu);
3621
3622	/*
3623	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3624	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3625	*
3626	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3627	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3628	*
3629	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3630	* executing guest code.
3631	*/
3632	pSvmTransient->fEFlags = ASMIntDisableFlags();
3633	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3634	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3635	{
3636	ASMSetFlags(pSvmTransient->fEFlags);
3637	VMMRZCallRing3Enable(pVCpu);
3638	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3639	return VINF_EM_RAW_TO_R3;
3640	}
3641	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3642	{
3643	ASMSetFlags(pSvmTransient->fEFlags);
3644	VMMRZCallRing3Enable(pVCpu);
3645	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3646	return VINF_EM_RAW_INTERRUPT;
3647	}
3648
3649	/*
3650	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3651	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3652	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3653	*
3654	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3655	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3656	*/
3657	if (pVCpu->hm.s.Event.fPending)
3658	{
3659	SVMEVENT Event;
3660	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3661	if ( Event.n.u1Valid
3662	&& Event.n.u3Type == SVM_EVENT_NMI
3663	&& Event.n.u8Vector == X86_XCPT_NMI
3664	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3665	{
3666	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3667	}
3668	}
3669
3670	return VINF_SUCCESS;
3671	}
3672	#endif
3673
3674
3675	/**
3676	* Does the preparations before executing guest code in AMD-V.
3677	*
3678	* This may cause longjmps to ring-3 and may even result in rescheduling to the
3679	* recompiler. We must be cautious what we do here regarding committing
3680	* guest-state information into the VMCB assuming we assuredly execute the guest
3681	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
3682	* clearing the common-state (TRPM/forceflags), we must undo those changes so
3683	* that the recompiler can (and should) use them when it resumes guest
3684	* execution. Otherwise such operations must be done when we can no longer
3685	* exit to ring-3.
3686	*
3687	* @returns VBox status code (informational status codes included).
3688	* @retval VINF_SUCCESS if we can proceed with running the guest.
3689	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3690	*
3691	* @param pVM The cross context VM structure.
3692	* @param pVCpu The cross context virtual CPU structure.
3693	* @param pCtx Pointer to the guest-CPU context.
3694	* @param pSvmTransient Pointer to the SVM transient structure.
3695	*/
3696	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3697	{
3698	HMSVM_ASSERT_PREEMPT_SAFE();
3699	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
3700
3701	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3702	/* IEM only for executing nested guest, we shouldn't get here. */
3703	/** @todo Make this into an assertion since HMR3CanExecuteGuest already checks
3704	* for it? */
3705	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3706	{
3707	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3708	return VINF_EM_RESCHEDULE_REM;
3709	}
3710	#endif
3711
3712	/* Check force flag actions that might require us to go back to ring-3. */
3713	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3714	if (rc != VINF_SUCCESS)
3715	return rc;
3716
3717	if (TRPMHasTrap(pVCpu))
3718	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3719	else if (!pVCpu->hm.s.Event.fPending)
3720	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
3721
3722	/*
3723	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3724	* Just do it in software, see @bugref{8411}.
3725	* NB: If we could continue a task switch exit we wouldn't need to do this.
3726	*/
3727	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
3728	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
3729	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3730
3731	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
3732	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3733	#endif
3734
3735	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3736	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3737	AssertRCReturn(rc, rc);
3738	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3739
3740	/*
3741	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3742	* so we can update it on the way back if the guest changed the TPR.
3743	*/
3744	if (pVCpu->hm.s.svm.fSyncVTpr)
3745	{
3746	if (pVM->hm.s.fTPRPatchingActive)
3747	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3748	else
3749	{
3750	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3751	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3752	}
3753	}
3754
3755	/*
3756	* No longjmps to ring-3 from this point on!!!
3757	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3758	* This also disables flushing of the R0-logger instance (if any).
3759	*/
3760	VMMRZCallRing3Disable(pVCpu);
3761
3762	/*
3763	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3764	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3765	*
3766	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3767	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3768	*
3769	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3770	* executing guest code.
3771	*/
3772	pSvmTransient->fEFlags = ASMIntDisableFlags();
3773	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3774	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3775	{
3776	ASMSetFlags(pSvmTransient->fEFlags);
3777	VMMRZCallRing3Enable(pVCpu);
3778	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3779	return VINF_EM_RAW_TO_R3;
3780	}
3781	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3782	{
3783	ASMSetFlags(pSvmTransient->fEFlags);
3784	VMMRZCallRing3Enable(pVCpu);
3785	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3786	return VINF_EM_RAW_INTERRUPT;
3787	}
3788
3789	/*
3790	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3791	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3792	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3793	*
3794	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3795	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3796	*/
3797	if (pVCpu->hm.s.Event.fPending)
3798	{
3799	SVMEVENT Event;
3800	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3801	if ( Event.n.u1Valid
3802	&& Event.n.u3Type == SVM_EVENT_NMI
3803	&& Event.n.u8Vector == X86_XCPT_NMI
3804	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3805	{
3806	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3807	}
3808	}
3809
3810	return VINF_SUCCESS;
3811	}
3812
3813
3814	#ifdef VBOX_WITH_NESTED_HWVIRT
3815	/**
3816	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
3817	* means there is no backing out to ring-3 or anywhere else at this point.
3818	*
3819	* @param pVM The cross context VM structure.
3820	* @param pVCpu The cross context virtual CPU structure.
3821	* @param pCtx Pointer to the guest-CPU context.
3822	* @param pSvmTransient Pointer to the SVM transient structure.
3823	*
3824	* @remarks Called with preemption disabled.
3825	* @remarks No-long-jump zone!!!
3826	*/
3827	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3828	{
3829	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3830	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3831	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3832
3833	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3834	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3835
3836	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3837	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
3838
3839	if ( pVCpu->hm.s.fPreloadGuestFpu
3840	&& !CPUMIsGuestFPUStateActive(pVCpu))
3841	{
3842	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3843	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3844	}
3845
3846	/* Load the state shared between host and nested-guest (FPU, debug). */
3847	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3848	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
3849
3850	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3851	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3852
3853	/* Setup TSC offsetting. */
3854	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3855	if ( pSvmTransient->fUpdateTscOffsetting
3856	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3857	{
3858	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcbNstGst);
3859	pSvmTransient->fUpdateTscOffsetting = false;
3860	}
3861
3862	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3863	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3864	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
3865
3866	/* Store status of the shared guest-host state at the time of VMRUN. */
3867	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3868	if (CPUMIsGuestInLongModeEx(pCtx))
3869	{
3870	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3871	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3872	}
3873	else
3874	#endif
3875	{
3876	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3877	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3878	}
3879	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3880
3881	/* The TLB flushing would've already been setup by the nested-hypervisor. */
3882	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3883	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
3884	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3885
3886	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3887
3888	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3889	to start executing. */
3890
3891	/*
3892	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3893	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3894	*
3895	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3896	*/
3897	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
3898	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3899	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
3900	{
3901	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3902	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3903	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3904	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3905	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3906	pSvmTransient->fRestoreTscAuxMsr = true;
3907	}
3908	else
3909	{
3910	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3911	pSvmTransient->fRestoreTscAuxMsr = false;
3912	}
3913
3914	/*
3915	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
3916	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
3917	*/
3918	if ( !(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
3919	\|\| !(pVM->cpum.ro.GuestFeatures.fSvmVmcbClean))
3920	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
3921	}
3922	#endif
3923
3924
3925	/**
3926	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3927	* means there is no backing out to ring-3 or anywhere else at this
3928	* point.
3929	*
3930	* @param pVM The cross context VM structure.
3931	* @param pVCpu The cross context virtual CPU structure.
3932	* @param pCtx Pointer to the guest-CPU context.
3933	* @param pSvmTransient Pointer to the SVM transient structure.
3934	*
3935	* @remarks Called with preemption disabled.
3936	* @remarks No-long-jump zone!!!
3937	*/
3938	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3939	{
3940	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3941	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3942	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3943
3944	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3945	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3946
3947	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3948	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
3949
3950	if ( pVCpu->hm.s.fPreloadGuestFpu
3951	&& !CPUMIsGuestFPUStateActive(pVCpu))
3952	{
3953	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3954	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3955	}
3956
3957	/* Load the state shared between host and guest (FPU, debug). */
3958	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3959	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3960
3961	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3962	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3963
3964	/* Setup TSC offsetting. */
3965	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3966	if ( pSvmTransient->fUpdateTscOffsetting
3967	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3968	{
3969	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
3970	pSvmTransient->fUpdateTscOffsetting = false;
3971	}
3972
3973	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3974	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3975	pVmcb->ctrl.u64VmcbCleanBits = 0;
3976
3977	/* Store status of the shared guest-host state at the time of VMRUN. */
3978	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3979	if (CPUMIsGuestInLongModeEx(pCtx))
3980	{
3981	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3982	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3983	}
3984	else
3985	#endif
3986	{
3987	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3988	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3989	}
3990	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3991
3992	/* Flush the appropriate tagged-TLB entries. */
3993	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3994	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
3995	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3996
3997	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3998
3999	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4000	to start executing. */
4001
4002	/*
4003	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4004	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4005	*
4006	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4007	*/
4008	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4009	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4010	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4011	{
4012	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4013	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4014	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4015	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4016	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4017	pSvmTransient->fRestoreTscAuxMsr = true;
4018	}
4019	else
4020	{
4021	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4022	pSvmTransient->fRestoreTscAuxMsr = false;
4023	}
4024
4025	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4026	if (!(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
4027	pVmcb->ctrl.u64VmcbCleanBits = 0;
4028	}
4029
4030
4031	/**
4032	* Wrapper for running the guest code in AMD-V.
4033	*
4034	* @returns VBox strict status code.
4035	* @param pVM The cross context VM structure.
4036	* @param pVCpu The cross context virtual CPU structure.
4037	* @param pCtx Pointer to the guest-CPU context.
4038	*
4039	* @remarks No-long-jump zone!!!
4040	*/
4041	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4042	{
4043	/*
4044	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4045	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4046	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4047	*/
4048	#ifdef VBOX_WITH_KERNEL_USING_XMM
4049	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4050	pVCpu->hm.s.svm.pfnVMRun);
4051	#else
4052	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4053	#endif
4054	}
4055
4056
4057	#ifdef VBOX_WITH_NESTED_HWVIRT
4058	/**
4059	* Wrapper for running the nested-guest code in AMD-V.
4060	*
4061	* @returns VBox strict status code.
4062	* @param pVM The cross context VM structure.
4063	* @param pVCpu The cross context virtual CPU structure.
4064	* @param pCtx Pointer to the guest-CPU context.
4065	*
4066	* @remarks No-long-jump zone!!!
4067	*/
4068	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4069	{
4070	/*
4071	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4072	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4073	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4074	*/
4075	#ifdef VBOX_WITH_KERNEL_USING_XMM
4076	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4077	pVCpu->hm.s.svm.pfnVMRun);
4078	#else
4079	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4080	#endif
4081	}
4082
4083
4084	/**
4085	* Performs some essential restoration of state after running nested-guest code in
4086	* AMD-V.
4087	*
4088	* @param pVM The cross context VM structure.
4089	* @param pVCpu The cross context virtual CPU structure.
4090	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4091	* out-of-sync. Make sure to update the required fields
4092	* before using them.
4093	* @param pSvmTransient Pointer to the SVM transient structure.
4094	* @param rcVMRun Return code of VMRUN.
4095	*
4096	* @remarks Called with interrupts disabled.
4097	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4098	* unconditionally when it is safe to do so.
4099	*/
4100	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4101	{
4102	RT_NOREF(pVM);
4103	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4104
4105	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4106	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4107
4108	/* TSC read must be done early for maximum accuracy. */
4109	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4110	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4111	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4112	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset);
4113
4114	if (pSvmTransient->fRestoreTscAuxMsr)
4115	{
4116	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4117	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4118	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4119	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4120	}
4121
4122	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4123	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4124	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4125
4126	Assert(!(ASMGetFlags() & X86_EFL_IF));
4127	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4128	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4129
4130	/* Mark the VMCB-state cache as unmodified by VMM. */
4131	pVmcbNstGstCtrl->u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4132
4133	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4134	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4135	{
4136	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4137	return;
4138	}
4139
4140	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4141	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4142	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4143	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4144
4145	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4146	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4147	guest-CPU context. */
4148
4149	/*
4150	* Currently, reload the entire nested-guest VMCB due to code that directly inspects
4151	* the nested-guest VMCB instead of the cache, e.g. hmR0SvmEvaluatePendingEventNested.
4152	*/
4153	HMSvmNstGstVmExitNotify(pVCpu, pVmcbNstGst);
4154	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4155	}
4156	#endif
4157
4158	/**
4159	* Performs some essential restoration of state after running guest code in
4160	* AMD-V.
4161	*
4162	* @param pVM The cross context VM structure.
4163	* @param pVCpu The cross context virtual CPU structure.
4164	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4165	* out-of-sync. Make sure to update the required fields
4166	* before using them.
4167	* @param pSvmTransient Pointer to the SVM transient structure.
4168	* @param rcVMRun Return code of VMRUN.
4169	*
4170	* @remarks Called with interrupts disabled.
4171	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4172	* unconditionally when it is safe to do so.
4173	*/
4174	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4175	{
4176	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4177
4178	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4179	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4180
4181	PSVMVMCB pVmcb =pVCpu->hm.s.svm.pVmcb;
4182	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4183
4184	/* TSC read must be done early for maximum accuracy. */
4185	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4186	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4187
4188	if (pSvmTransient->fRestoreTscAuxMsr)
4189	{
4190	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4191	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4192	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4193	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4194	}
4195
4196	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4197	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4198	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4199
4200	Assert(!(ASMGetFlags() & X86_EFL_IF));
4201	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4202	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4203
4204	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4205	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4206	{
4207	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4208	return;
4209	}
4210
4211	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4212	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4213	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4214	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4215
4216	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4217
4218	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4219	{
4220	if (pVCpu->hm.s.svm.fSyncVTpr)
4221	{
4222	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4223	if ( pVM->hm.s.fTPRPatchingActive
4224	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4225	{
4226	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4227	AssertRC(rc);
4228	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4229	}
4230	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4231	{
4232	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4233	AssertRC(rc);
4234	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4235	}
4236	}
4237	}
4238	}
4239
4240
4241	/**
4242	* Runs the guest code using AMD-V.
4243	*
4244	* @returns VBox status code.
4245	* @param pVM The cross context VM structure.
4246	* @param pVCpu The cross context virtual CPU structure.
4247	* @param pCtx Pointer to the guest-CPU context.
4248	* @param pcLoops Pointer to the number of executed loops.
4249	*/
4250	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4251	{
4252	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4253	Assert(pcLoops);
4254	Assert(*pcLoops <= cMaxResumeLoops);
4255
4256	SVMTRANSIENT SvmTransient;
4257	SvmTransient.fUpdateTscOffsetting = true;
4258
4259	int rc = VERR_INTERNAL_ERROR_5;
4260	for (;;)
4261	{
4262	Assert(!HMR0SuspendPending());
4263	HMSVM_ASSERT_CPU_SAFE();
4264
4265	/* Preparatory work for running guest code, this may force us to return
4266	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4267	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4268	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4269	if (rc != VINF_SUCCESS)
4270	break;
4271
4272	/*
4273	* No longjmps to ring-3 from this point on!!!
4274	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4275	* This also disables flushing of the R0-logger instance (if any).
4276	*/
4277	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4278	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4279
4280	/* Restore any residual host-state and save any bits shared between host
4281	and guest into the guest-CPU state. Re-enables interrupts! */
4282	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4283
4284	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4285	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4286	{
4287	if (rc == VINF_SUCCESS)
4288	rc = VERR_SVM_INVALID_GUEST_STATE;
4289	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4290	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4291	break;
4292	}
4293
4294	/* Handle the #VMEXIT. */
4295	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4296	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4297	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4298	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4299	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4300	if (rc != VINF_SUCCESS)
4301	break;
4302	if (++(*pcLoops) >= cMaxResumeLoops)
4303	{
4304	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4305	rc = VINF_EM_RAW_INTERRUPT;
4306	break;
4307	}
4308	}
4309
4310	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4311	return rc;
4312	}
4313
4314
4315	/**
4316	* Runs the guest code using AMD-V in single step mode.
4317	*
4318	* @returns VBox status code.
4319	* @param pVM The cross context VM structure.
4320	* @param pVCpu The cross context virtual CPU structure.
4321	* @param pCtx Pointer to the guest-CPU context.
4322	* @param pcLoops Pointer to the number of executed loops.
4323	*/
4324	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4325	{
4326	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4327	Assert(pcLoops);
4328	Assert(*pcLoops <= cMaxResumeLoops);
4329
4330	SVMTRANSIENT SvmTransient;
4331	SvmTransient.fUpdateTscOffsetting = true;
4332
4333	uint16_t uCsStart = pCtx->cs.Sel;
4334	uint64_t uRipStart = pCtx->rip;
4335
4336	int rc = VERR_INTERNAL_ERROR_5;
4337	for (;;)
4338	{
4339	Assert(!HMR0SuspendPending());
4340	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4341	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4342	(unsigned)RTMpCpuId(), *pcLoops));
4343
4344	/* Preparatory work for running guest code, this may force us to return
4345	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4346	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4347	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4348	if (rc != VINF_SUCCESS)
4349	break;
4350
4351	/*
4352	* No longjmps to ring-3 from this point on!!!
4353	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4354	* This also disables flushing of the R0-logger instance (if any).
4355	*/
4356	VMMRZCallRing3Disable(pVCpu);
4357	VMMRZCallRing3RemoveNotification(pVCpu);
4358	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4359
4360	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4361
4362	/*
4363	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4364	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4365	*/
4366	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4367	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4368	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4369	{
4370	if (rc == VINF_SUCCESS)
4371	rc = VERR_SVM_INVALID_GUEST_STATE;
4372	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4373	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4374	return rc;
4375	}
4376
4377	/* Handle the #VMEXIT. */
4378	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4379	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4380	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4381	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4382	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4383	if (rc != VINF_SUCCESS)
4384	break;
4385	if (++(*pcLoops) >= cMaxResumeLoops)
4386	{
4387	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4388	rc = VINF_EM_RAW_INTERRUPT;
4389	break;
4390	}
4391
4392	/*
4393	* Did the RIP change, if so, consider it a single step.
4394	* Otherwise, make sure one of the TFs gets set.
4395	*/
4396	if ( pCtx->rip != uRipStart
4397	\|\| pCtx->cs.Sel != uCsStart)
4398	{
4399	rc = VINF_EM_DBG_STEPPED;
4400	break;
4401	}
4402	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4403	}
4404
4405	/*
4406	* Clear the X86_EFL_TF if necessary.
4407	*/
4408	if (pVCpu->hm.s.fClearTrapFlag)
4409	{
4410	pVCpu->hm.s.fClearTrapFlag = false;
4411	pCtx->eflags.Bits.u1TF = 0;
4412	}
4413
4414	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4415	return rc;
4416	}
4417
4418	#ifdef VBOX_WITH_NESTED_HWVIRT
4419	/**
4420	* Runs the nested-guest code using AMD-V.
4421	*
4422	* @returns VBox status code.
4423	* @param pVM The cross context VM structure.
4424	* @param pVCpu The cross context virtual CPU structure.
4425	* @param pCtx Pointer to the guest-CPU context.
4426	* @param pcLoops Pointer to the number of executed loops. If we're switching
4427	* from the guest-code execution loop to this nested-guest
4428	* execution loop pass the remainder value, else pass 0.
4429	*/
4430	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4431	{
4432	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4433	Assert(pcLoops);
4434	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4435
4436	SVMTRANSIENT SvmTransient;
4437	SvmTransient.fUpdateTscOffsetting = true;
4438
4439	int rc = VERR_INTERNAL_ERROR_4;
4440	for (;;)
4441	{
4442	Assert(!HMR0SuspendPending());
4443	HMSVM_ASSERT_CPU_SAFE();
4444
4445	/* Preparatory work for running nested-guest code, this may force us to return
4446	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4447	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4448	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4449	if (rc != VINF_SUCCESS)
4450	break;
4451
4452	/*
4453	* No longjmps to ring-3 from this point on!!!
4454	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4455	* This also disables flushing of the R0-logger instance (if any).
4456	*/
4457	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4458
4459	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4460
4461	/* Restore any residual host-state and save any bits shared between host
4462	and guest into the guest-CPU state. Re-enables interrupts! */
4463	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4464
4465	/** @todo This needs some work... we probably should cause a \#VMEXIT on
4466	* SVM_EXIT_INVALID and handle rc != VINF_SUCCESS differently. */
4467	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4468	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4469	{
4470	if (rc == VINF_SUCCESS)
4471	rc = VERR_SVM_INVALID_GUEST_STATE;
4472	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4473	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4474	break;
4475	}
4476
4477	/* Handle the #VMEXIT. */
4478	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4479	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4480	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4481	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4482	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4483	if (rc != VINF_SUCCESS)
4484	break;
4485	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4486	{
4487	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4488	rc = VINF_EM_RAW_INTERRUPT;
4489	break;
4490	}
4491
4492	/** @todo handle single-stepping */
4493	}
4494
4495	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4496	return rc;
4497	}
4498	#endif
4499
4500
4501	/**
4502	* Runs the guest code using AMD-V.
4503	*
4504	* @returns Strict VBox status code.
4505	* @param pVM The cross context VM structure.
4506	* @param pVCpu The cross context virtual CPU structure.
4507	* @param pCtx Pointer to the guest-CPU context.
4508	*/
4509	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4510	{
4511	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4512	HMSVM_ASSERT_PREEMPT_SAFE();
4513	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4514
4515	uint32_t cLoops = 0;
4516	int rc;
4517	#ifdef VBOX_WITH_NESTED_HWVIRT
4518	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4519	#endif
4520	{
4521	if (!pVCpu->hm.s.fSingleInstruction)
4522	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4523	else
4524	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4525	}
4526	#ifdef VBOX_WITH_NESTED_HWVIRT
4527	else
4528	{
4529	rc = VINF_SVM_VMRUN;
4530	}
4531
4532	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4533	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4534	if (rc == VINF_SVM_VMRUN)
4535	{
4536	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4537	if (rc == VINF_SVM_VMEXIT)
4538	rc = VINF_SUCCESS;
4539	}
4540	#endif
4541
4542	/* Fixup error codes. */
4543	if (rc == VERR_EM_INTERPRETER)
4544	rc = VINF_EM_RAW_EMULATE_INSTR;
4545	else if (rc == VINF_EM_RESET)
4546	rc = VINF_EM_TRIPLE_FAULT;
4547
4548	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4549	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4550	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4551	return rc;
4552	}
4553
4554
4555	#ifdef VBOX_WITH_NESTED_HWVIRT
4556	/**
4557	* Determines whether an IOIO intercept is active for the nested-guest or not.
4558	*
4559	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4560	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4561	*/
4562	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4563	{
4564	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4565	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4566	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4567	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4568	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4569	const bool fRep = pIoExitInfo->n.u1REP;
4570	const bool fStrIo = pIoExitInfo->n.u1STR;
4571
4572	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4573	NULL /* pIoExitInfo */);
4574	}
4575
4576
4577	/**
4578	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4579	* SVM_EXIT_INVALID).
4580	*
4581	* @returns VBox status code (informational status codes included).
4582	* @param pVCpu The cross context virtual CPU structure.
4583	* @param pCtx Pointer to the guest-CPU context.
4584	* @param pSvmTransient Pointer to the SVM transient structure.
4585	*/
4586	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4587	{
4588	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4589	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4590
4591	#define HM_SVM_RET_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4592	do \
4593	{ \
4594	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2)); \
4595	} while (0) \
4596
4597	/*
4598	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4599	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
4600	*/
4601	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4602	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4603	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4604	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4605	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4606	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4607
4608	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4609	switch (uExitCode)
4610	{
4611	case SVM_EXIT_CPUID:
4612	{
4613	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_CPUID)
4614	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4615	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
4616	}
4617
4618	case SVM_EXIT_RDTSC:
4619	{
4620	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC)
4621	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4622	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
4623	}
4624
4625	case SVM_EXIT_RDTSCP:
4626	{
4627	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP)
4628	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4629	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
4630	}
4631
4632
4633	case SVM_EXIT_MONITOR:
4634	{
4635	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MONITOR)
4636	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4637	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
4638	}
4639
4640	case SVM_EXIT_MWAIT:
4641	{
4642	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MWAIT)
4643	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4644	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
4645	}
4646
4647	case SVM_EXIT_HLT:
4648	{
4649	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_HLT)
4650	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4651	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
4652	}
4653
4654	case SVM_EXIT_MSR:
4655	{
4656	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MSR_PROT)
4657	{
4658	uint32_t const idMsr = pCtx->ecx;
4659	uint16_t offMsrpm;
4660	uint32_t uMsrpmBit;
4661	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4662	if (RT_SUCCESS(rc))
4663	{
4664	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4665	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
4666	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
4667
4668	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4669	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4670	{
4671	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4672	}
4673	}
4674	else
4675	{
4676	/*
4677	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4678	* See AMD-V spec. "15.11 MSR Intercepts".
4679	*/
4680	Assert(rc == VERR_OUT_OF_RANGE);
4681	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4682	}
4683	}
4684	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
4685	}
4686
4687	case SVM_EXIT_IOIO:
4688	{
4689	/*
4690	* Figure out if the IO port access is intercepted by the nested-guest.
4691	*/
4692	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_IOIO_PROT)
4693	{
4694	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
4695	SVMIOIOEXITINFO IoExitInfo;
4696	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4697	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
4698	if (fIntercept)
4699	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4700	}
4701	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
4702	}
4703
4704	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
4705	{
4706	PVM pVM = pVCpu->CTX_SUFF(pVM);
4707	if (pVM->hm.s.fNestedPaging)
4708	{
4709	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4710	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4711
4712	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4713	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_PF))
4714	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4715
4716	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
4717	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4718	return VINF_SUCCESS;
4719	}
4720	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
4721	}
4722
4723	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
4724	{
4725	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_NM))
4726	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4727	hmR0SvmSetPendingXcptNM(pVCpu);
4728	return VINF_SUCCESS;
4729	}
4730
4731	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
4732	{
4733	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_UD))
4734	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4735	hmR0SvmSetPendingXcptUD(pVCpu);
4736	return VINF_SUCCESS;
4737	}
4738
4739	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
4740	{
4741	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_MF))
4742	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4743	hmR0SvmSetPendingXcptMF(pVCpu);
4744	return VINF_SUCCESS;
4745	}
4746
4747	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
4748	{
4749	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_DB))
4750	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4751	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
4752	}
4753
4754	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
4755	{
4756	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_AC))
4757	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4758	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
4759	}
4760
4761	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
4762	{
4763	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_BP))
4764	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4765	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
4766	}
4767
4768	case SVM_EXIT_READ_CR0:
4769	case SVM_EXIT_READ_CR3:
4770	case SVM_EXIT_READ_CR4:
4771	{
4772	if (pVmcbNstGstCache->u16InterceptRdCRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0)))
4773	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4774	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
4775	}
4776
4777	case SVM_EXIT_WRITE_CR0:
4778	case SVM_EXIT_WRITE_CR3:
4779	case SVM_EXIT_WRITE_CR4:
4780	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
4781	{
4782	Log4(("hmR0SvmHandleExitNested: Write CRx: u16InterceptWrCRx=%#x u64ExitCode=%#RX64 %#x\n",
4783	pVmcbNstGstCache->u16InterceptWrCRx, pSvmTransient->u64ExitCode,
4784	(1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0))));
4785	if (pVmcbNstGstCache->u16InterceptWrCRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)))
4786	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4787	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
4788	}
4789
4790	case SVM_EXIT_PAUSE:
4791	{
4792	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_PAUSE)
4793	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4794	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
4795	}
4796
4797	case SVM_EXIT_VINTR:
4798	{
4799	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
4800	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4801	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4802	}
4803
4804	case SVM_EXIT_INTR:
4805	{
4806	/* We shouldn't direct physical interrupts to the nested-guest. */
4807	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4808	}
4809
4810	case SVM_EXIT_FERR_FREEZE:
4811	{
4812	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_FERR_FREEZE)
4813	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4814	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4815	}
4816
4817	case SVM_EXIT_NMI:
4818	{
4819	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_NMI)
4820	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4821	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4822	}
4823
4824	case SVM_EXIT_INVLPG:
4825	{
4826	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVLPG)
4827	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4828	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
4829	}
4830
4831	case SVM_EXIT_WBINVD:
4832	{
4833	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_WBINVD)
4834	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4835	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
4836	}
4837
4838	case SVM_EXIT_INVD:
4839	{
4840	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVD)
4841	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4842	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
4843	}
4844
4845	case SVM_EXIT_RDPMC:
4846	{
4847	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDPMC)
4848	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4849	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
4850	}
4851
4852	default:
4853	{
4854	switch (pSvmTransient->u64ExitCode)
4855	{
4856	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
4857	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
4858	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
4859	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
4860	{
4861	if (pVmcbNstGstCache->u16InterceptRdDRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_DR0)))
4862	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4863	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4864	}
4865
4866	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
4867	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
4868	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
4869	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
4870	{
4871	if (pVmcbNstGstCache->u16InterceptWrDRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_DR0)))
4872	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4873	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
4874	}
4875
4876	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
4877	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
4878	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
4879	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
4880	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
4881	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
4882	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
4883	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
4884	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
4885	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
4886	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
4887	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
4888	{
4889	if (pVmcbNstGstCache->u32InterceptXcpt & (1U << (uint32_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0)))
4890	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4891	/** @todo Write hmR0SvmExitXcptGeneric! */
4892	return VERR_NOT_IMPLEMENTED;
4893	}
4894
4895	case SVM_EXIT_XSETBV:
4896	{
4897	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_XSETBV)
4898	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4899	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
4900	}
4901
4902	case SVM_EXIT_TASK_SWITCH:
4903	{
4904	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_TASK_SWITCH)
4905	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4906	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
4907	}
4908
4909	case SVM_EXIT_IRET:
4910	{
4911	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
4912	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4913	return hmR0SvmNestedExitIret(pVCpu, pCtx, pSvmTransient);
4914	}
4915
4916	case SVM_EXIT_SHUTDOWN:
4917	{
4918	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SHUTDOWN)
4919	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4920	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
4921	}
4922
4923	case SVM_EXIT_SMI:
4924	{
4925	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SMI)
4926	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4927	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4928	}
4929
4930	case SVM_EXIT_INIT:
4931	{
4932	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INIT)
4933	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4934	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4935	}
4936
4937	case SVM_EXIT_VMMCALL:
4938	{
4939	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMMCALL)
4940	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4941	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
4942	}
4943
4944	case SVM_EXIT_CLGI:
4945	{
4946	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_CLGI)
4947	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4948	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
4949	}
4950
4951	case SVM_EXIT_STGI:
4952	{
4953	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_STGI)
4954	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4955	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
4956	}
4957
4958	case SVM_EXIT_VMLOAD:
4959	{
4960	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMLOAD)
4961	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4962	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
4963	}
4964
4965	case SVM_EXIT_VMSAVE:
4966	{
4967	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMSAVE)
4968	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4969	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
4970	}
4971
4972	case SVM_EXIT_INVLPGA:
4973	{
4974	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVLPGA)
4975	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4976	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
4977	}
4978
4979	case SVM_EXIT_VMRUN:
4980	{
4981	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN)
4982	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4983	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
4984	}
4985
4986	case SVM_EXIT_RSM:
4987	{
4988	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RSM)
4989	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4990	hmR0SvmSetPendingXcptUD(pVCpu);
4991	return VINF_SUCCESS;
4992	}
4993
4994	case SVM_EXIT_SKINIT:
4995	{
4996	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SKINIT)
4997	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4998	hmR0SvmSetPendingXcptUD(pVCpu);
4999	return VINF_SUCCESS;
5000	}
5001
5002	case SVM_EXIT_NPF:
5003	{
5004	/* We don't yet support nested-paging for nested-guests, so this should never really happen. */
5005	Assert(!pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging);
5006	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5007	}
5008
5009	default:
5010	{
5011	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5012	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5013	return VERR_SVM_UNKNOWN_EXIT;
5014	}
5015	}
5016	}
5017	}
5018	/* not reached */
5019
5020	#undef HM_SVM_RET_VMEXIT_NESTED
5021	}
5022	#endif
5023
5024
5025	/**
5026	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5027	*
5028	* @returns VBox status code (informational status codes included).
5029	* @param pVCpu The cross context virtual CPU structure.
5030	* @param pCtx Pointer to the guest-CPU context.
5031	* @param pSvmTransient Pointer to the SVM transient structure.
5032	*/
5033	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5034	{
5035	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5036	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5037
5038	/*
5039	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5040	* normal workloads (for some definition of "normal").
5041	*/
5042	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
5043	switch (pSvmTransient->u64ExitCode)
5044	{
5045	case SVM_EXIT_NPF:
5046	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5047
5048	case SVM_EXIT_IOIO:
5049	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5050
5051	case SVM_EXIT_RDTSC:
5052	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5053
5054	case SVM_EXIT_RDTSCP:
5055	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5056
5057	case SVM_EXIT_CPUID:
5058	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5059
5060	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5061	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5062
5063	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5064	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5065
5066	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5067	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5068
5069	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5070	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5071
5072	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5073	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5074
5075	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5076	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5077
5078	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5079	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5080
5081	case SVM_EXIT_MONITOR:
5082	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5083
5084	case SVM_EXIT_MWAIT:
5085	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5086
5087	case SVM_EXIT_HLT:
5088	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5089
5090	case SVM_EXIT_READ_CR0:
5091	case SVM_EXIT_READ_CR3:
5092	case SVM_EXIT_READ_CR4:
5093	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5094
5095	case SVM_EXIT_WRITE_CR0:
5096	case SVM_EXIT_WRITE_CR3:
5097	case SVM_EXIT_WRITE_CR4:
5098	case SVM_EXIT_WRITE_CR8:
5099	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5100
5101	case SVM_EXIT_PAUSE:
5102	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5103
5104	case SVM_EXIT_VMMCALL:
5105	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5106
5107	case SVM_EXIT_VINTR:
5108	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5109
5110	case SVM_EXIT_INTR:
5111	case SVM_EXIT_FERR_FREEZE:
5112	case SVM_EXIT_NMI:
5113	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5114
5115	case SVM_EXIT_MSR:
5116	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5117
5118	case SVM_EXIT_INVLPG:
5119	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5120
5121	case SVM_EXIT_WBINVD:
5122	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5123
5124	case SVM_EXIT_INVD:
5125	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5126
5127	case SVM_EXIT_RDPMC:
5128	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5129
5130	default:
5131	{
5132	switch (pSvmTransient->u64ExitCode)
5133	{
5134	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5135	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5136	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5137	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5138	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5139
5140	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5141	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5142	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5143	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5144	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5145
5146	case SVM_EXIT_XSETBV:
5147	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5148
5149	case SVM_EXIT_TASK_SWITCH:
5150	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5151
5152	case SVM_EXIT_IRET:
5153	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5154
5155	case SVM_EXIT_SHUTDOWN:
5156	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5157
5158	case SVM_EXIT_SMI:
5159	case SVM_EXIT_INIT:
5160	{
5161	/*
5162	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5163	* If it ever does, we want to know about it so log the exit code and bail.
5164	*/
5165	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5166	}
5167
5168	#ifdef VBOX_WITH_NESTED_HWVIRT
5169	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5170	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5171	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5172	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5173	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5174	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5175	#else
5176	case SVM_EXIT_CLGI:
5177	case SVM_EXIT_STGI:
5178	case SVM_EXIT_VMLOAD:
5179	case SVM_EXIT_VMSAVE:
5180	case SVM_EXIT_INVLPGA:
5181	case SVM_EXIT_VMRUN:
5182	#endif
5183	case SVM_EXIT_RSM:
5184	case SVM_EXIT_SKINIT:
5185	{
5186	hmR0SvmSetPendingXcptUD(pVCpu);
5187	return VINF_SUCCESS;
5188	}
5189
5190	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5191	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5192	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5193	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5194	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5195	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5196	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5197	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5198	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5199	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5200	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5201	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5202	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5203	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5204	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5205	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5206	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5207	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5208	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5209	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5210	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5211	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5212	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5213	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5214	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5215	{
5216	/** @todo r=ramshankar; We should be doing
5217	* HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY here! */
5218
5219	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5220	SVMEVENT Event;
5221	Event.u = 0;
5222	Event.n.u1Valid = 1;
5223	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5224	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5225
5226	switch (Event.n.u8Vector)
5227	{
5228	case X86_XCPT_DE:
5229	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
5230	break;
5231
5232	case X86_XCPT_NP:
5233	Event.n.u1ErrorCodeValid = 1;
5234	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5235	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
5236	break;
5237
5238	case X86_XCPT_SS:
5239	Event.n.u1ErrorCodeValid = 1;
5240	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5241	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
5242	break;
5243
5244	case X86_XCPT_GP:
5245	Event.n.u1ErrorCodeValid = 1;
5246	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5247	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
5248	break;
5249
5250	default:
5251	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
5252	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
5253	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
5254	}
5255
5256	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
5257	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5258	return VINF_SUCCESS;
5259	}
5260	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5261
5262	default:
5263	{
5264	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
5265	pVCpu->hm.s.u32HMError = u32ExitCode;
5266	return VERR_SVM_UNKNOWN_EXIT;
5267	}
5268	}
5269	}
5270	}
5271	/* not reached */
5272	}
5273
5274
5275	#ifdef DEBUG
5276	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5277	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5278	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5279
5280	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5281	do \
5282	{ \
5283	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5284	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5285	} while (0)
5286
5287	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5288	do { \
5289	AssertPtr(pVCpu); \
5290	AssertPtr(pCtx); \
5291	AssertPtr(pSvmTransient); \
5292	Assert(ASMIntAreEnabled()); \
5293	HMSVM_ASSERT_PREEMPT_SAFE(); \
5294	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5295	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5296	HMSVM_ASSERT_PREEMPT_SAFE(); \
5297	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5298	HMSVM_ASSERT_PREEMPT_CPUID(); \
5299	} while (0)
5300	#else /* Release builds */
5301	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5302	#endif
5303
5304
5305	/**
5306	* Worker for hmR0SvmInterpretInvlpg().
5307	*
5308	* @return VBox status code.
5309	* @param pVCpu The cross context virtual CPU structure.
5310	* @param pCpu Pointer to the disassembler state.
5311	* @param pCtx The guest CPU context.
5312	*/
5313	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5314	{
5315	DISQPVPARAMVAL Param1;
5316	RTGCPTR GCPtrPage;
5317
5318	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5319	if (RT_FAILURE(rc))
5320	return VERR_EM_INTERPRETER;
5321
5322	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5323	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5324	{
5325	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5326	return VERR_EM_INTERPRETER;
5327
5328	GCPtrPage = Param1.val.val64;
5329	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5330	rc = VBOXSTRICTRC_VAL(rc2);
5331	}
5332	else
5333	{
5334	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5335	rc = VERR_EM_INTERPRETER;
5336	}
5337
5338	return rc;
5339	}
5340
5341
5342	/**
5343	* Interprets INVLPG.
5344	*
5345	* @returns VBox status code.
5346	* @retval VINF_* Scheduling instructions.
5347	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5348	* @retval VERR_* Fatal errors.
5349	*
5350	* @param pVM The cross context VM structure.
5351	* @param pVCpu The cross context virtual CPU structure.
5352	* @param pCtx The guest CPU context.
5353	*
5354	* @remarks Updates the RIP if the instruction was executed successfully.
5355	*/
5356	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5357	{
5358	/* Only allow 32 & 64 bit code. */
5359	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5360	{
5361	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5362	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5363	if ( RT_SUCCESS(rc)
5364	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5365	{
5366	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5367	if (RT_SUCCESS(rc))
5368	pCtx->rip += pDis->cbInstr;
5369	return rc;
5370	}
5371	else
5372	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5373	}
5374	return VERR_EM_INTERPRETER;
5375	}
5376
5377
5378	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5379	/**
5380	* Gets the IEM exception flags for the specified SVM event.
5381	*
5382	* @returns The IEM exception flags.
5383	* @param pEvent Pointer to the SVM event.
5384	*
5385	* @remarks This function currently only constructs flags required for
5386	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5387	* and CR2 aspects of an exception are not included).
5388	*/
5389	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5390	{
5391	uint8_t const uEventType = pEvent->n.u3Type;
5392	uint32_t fIemXcptFlags;
5393	switch (uEventType)
5394	{
5395	case SVM_EVENT_EXCEPTION:
5396	/*
5397	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5398	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5399	*/
5400	if (pEvent->n.u8Vector == X86_XCPT_BP)
5401	{
5402	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5403	break;
5404	}
5405	if (pEvent->n.u8Vector == X86_XCPT_OF)
5406	{
5407	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5408	break;
5409	}
5410	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5411	RT_FALL_THRU();
5412	case SVM_EVENT_NMI:
5413	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5414	break;
5415
5416	case SVM_EVENT_EXTERNAL_IRQ:
5417	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5418	break;
5419
5420	case SVM_EVENT_SOFTWARE_INT:
5421	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5422	break;
5423
5424	default:
5425	fIemXcptFlags = 0;
5426	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5427	break;
5428	}
5429	return fIemXcptFlags;
5430	}
5431
5432	#else
5433	/**
5434	* Determines if an exception is a contributory exception.
5435	*
5436	* Contributory exceptions are ones which can cause double-faults unless the
5437	* original exception was a benign exception. Page-fault is intentionally not
5438	* included here as it's a conditional contributory exception.
5439	*
5440	* @returns true if the exception is contributory, false otherwise.
5441	* @param uVector The exception vector.
5442	*/
5443	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5444	{
5445	switch (uVector)
5446	{
5447	case X86_XCPT_GP:
5448	case X86_XCPT_SS:
5449	case X86_XCPT_NP:
5450	case X86_XCPT_TS:
5451	case X86_XCPT_DE:
5452	return true;
5453	default:
5454	break;
5455	}
5456	return false;
5457	}
5458	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5459
5460
5461	/**
5462	* Handle a condition that occurred while delivering an event through the guest
5463	* IDT.
5464	*
5465	* @returns VBox status code (informational error codes included).
5466	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5467	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5468	* continue execution of the guest which will delivery the \#DF.
5469	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5470	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5471	*
5472	* @param pVCpu The cross context virtual CPU structure.
5473	* @param pCtx Pointer to the guest-CPU context.
5474	* @param pSvmTransient Pointer to the SVM transient structure.
5475	*
5476	* @remarks No-long-jump zone!!!
5477	*/
5478	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5479	{
5480	int rc = VINF_SUCCESS;
5481	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5482
5483	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5484	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5485	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5486
5487	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5488	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5489	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5490	{
5491	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5492	IEMXCPTRAISE enmRaise;
5493	IEMXCPTRAISEINFO fRaiseInfo;
5494	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5495	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5496	if (fExitIsHwXcpt)
5497	{
5498	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5499	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5500	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5501	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5502	}
5503	else
5504	{
5505	/*
5506	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5507	* end up here.
5508	*
5509	* If the event was:
5510	* - a software interrupt, we can re-execute the instruction which will regenerate
5511	* the event.
5512	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5513	* - a hardware exception or external interrupt, we re-inject it.
5514	*/
5515	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5516	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5517	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5518	else
5519	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5520	}
5521
5522	switch (enmRaise)
5523	{
5524	case IEMXCPTRAISE_CURRENT_XCPT:
5525	case IEMXCPTRAISE_PREV_EVENT:
5526	{
5527	/* For software interrupts, we shall re-execute the instruction. */
5528	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5529	{
5530	RTGCUINTPTR GCPtrFaultAddress = 0;
5531
5532	/* If we are re-injecting an NMI, clear NMI blocking. */
5533	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5534	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5535
5536	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5537	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5538	pSvmTransient->fVectoringPF = true;
5539	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5540	&& uIdtVector == X86_XCPT_PF)
5541	{
5542	/*
5543	* If the previous exception was a #PF, we need to recover the CR2 value.
5544	* This can't happen with shadow paging.
5545	*/
5546	GCPtrFaultAddress = pCtx->cr2;
5547	}
5548
5549	/*
5550	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5551	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5552	*/
5553	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5554	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5555	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5556
5557	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5558	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5559	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5560	}
5561	break;
5562	}
5563
5564	case IEMXCPTRAISE_REEXEC_INSTR:
5565	{
5566	Assert(rc == VINF_SUCCESS);
5567	break;
5568	}
5569
5570	case IEMXCPTRAISE_DOUBLE_FAULT:
5571	{
5572	/*
5573	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5574	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5575	*/
5576	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5577	{
5578	pSvmTransient->fVectoringDoublePF = true;
5579	Assert(rc == VINF_SUCCESS);
5580	}
5581	else
5582	{
5583	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5584	hmR0SvmSetPendingXcptDF(pVCpu);
5585	rc = VINF_HM_DOUBLE_FAULT;
5586	}
5587	break;
5588	}
5589
5590	case IEMXCPTRAISE_TRIPLE_FAULT:
5591	{
5592	rc = VINF_EM_RESET;
5593	break;
5594	}
5595
5596	case IEMXCPTRAISE_CPU_HANG:
5597	{
5598	rc = VERR_EM_GUEST_CPU_HANG;
5599	break;
5600	}
5601
5602	default:
5603	{
5604	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5605	rc = VERR_SVM_IPE_2;
5606	break;
5607	}
5608	}
5609	#else
5610	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5611
5612	typedef enum
5613	{
5614	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5615	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5616	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5617	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5618	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5619	} SVMREFLECTXCPT;
5620
5621	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5622	bool fReflectingNmi = false;
5623	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5624	{
5625	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5626	{
5627	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5628
5629	#ifdef VBOX_STRICT
5630	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5631	&& uExitVector == X86_XCPT_PF)
5632	{
5633	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5634	}
5635	#endif
5636
5637	if ( uIdtVector == X86_XCPT_BP
5638	\|\| uIdtVector == X86_XCPT_OF)
5639	{
5640	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5641	}
5642	else if ( uExitVector == X86_XCPT_PF
5643	&& uIdtVector == X86_XCPT_PF)
5644	{
5645	pSvmTransient->fVectoringDoublePF = true;
5646	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
5647	}
5648	else if ( uExitVector == X86_XCPT_AC
5649	&& uIdtVector == X86_XCPT_AC)
5650	{
5651	enmReflect = SVMREFLECTXCPT_HANG;
5652	Log4(("IDT: Nested #AC - Bad guest\n"));
5653	}
5654	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
5655	&& hmR0SvmIsContributoryXcpt(uExitVector)
5656	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
5657	\|\| uIdtVector == X86_XCPT_PF))
5658	{
5659	enmReflect = SVMREFLECTXCPT_DF;
5660	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
5661	uIdtVector, uExitVector));
5662	}
5663	else if (uIdtVector == X86_XCPT_DF)
5664	{
5665	enmReflect = SVMREFLECTXCPT_TF;
5666	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
5667	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
5668	}
5669	else
5670	enmReflect = SVMREFLECTXCPT_XCPT;
5671	}
5672	else
5673	{
5674	/*
5675	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
5676	* exception to the guest after handling the #VMEXIT.
5677	*/
5678	enmReflect = SVMREFLECTXCPT_XCPT;
5679	}
5680	}
5681	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
5682	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5683	{
5684	enmReflect = SVMREFLECTXCPT_XCPT;
5685	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
5686
5687	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5688	{
5689	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5690	if (uExitVector == X86_XCPT_PF)
5691	{
5692	pSvmTransient->fVectoringPF = true;
5693	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
5694	}
5695	}
5696	}
5697	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
5698
5699	switch (enmReflect)
5700	{
5701	case SVMREFLECTXCPT_XCPT:
5702	{
5703	/* If we are re-injecting the NMI, clear NMI blocking. */
5704	if (fReflectingNmi)
5705	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5706
5707	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5708	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5709	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
5710
5711	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
5712	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
5713	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
5714	break;
5715	}
5716
5717	case SVMREFLECTXCPT_DF:
5718	{
5719	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5720	hmR0SvmSetPendingXcptDF(pVCpu);
5721	rc = VINF_HM_DOUBLE_FAULT;
5722	break;
5723	}
5724
5725	case SVMREFLECTXCPT_TF:
5726	{
5727	rc = VINF_EM_RESET;
5728	break;
5729	}
5730
5731	case SVMREFLECTXCPT_HANG:
5732	{
5733	rc = VERR_EM_GUEST_CPU_HANG;
5734	break;
5735	}
5736
5737	default:
5738	Assert(rc == VINF_SUCCESS);
5739	break;
5740	}
5741	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5742	}
5743	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5744	NOREF(pCtx);
5745	return rc;
5746	}
5747
5748
5749	/**
5750	* Updates interrupt shadow for the current RIP.
5751	*/
5752	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
5753	do { \
5754	/* Update interrupt shadow. */ \
5755	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
5756	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
5757	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
5758	} while (0)
5759
5760
5761	/**
5762	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
5763	* supported, otherwise advances the RIP by the number of bytes specified in
5764	* @a cb.
5765	*
5766	* @param pVCpu The cross context virtual CPU structure.
5767	* @param pCtx Pointer to the guest-CPU context.
5768	* @param cb RIP increment value in bytes.
5769	*
5770	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
5771	* when NRIP_SAVE is supported by the CPU, otherwise use
5772	* hmR0SvmAdvanceRipDumb!
5773	*/
5774	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5775	{
5776	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
5777	{
5778	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5779	Assert(pVmcb->ctrl.u64NextRIP);
5780	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
5781	pCtx->rip = pVmcb->ctrl.u64NextRIP;
5782	}
5783	else
5784	pCtx->rip += cb;
5785
5786	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5787	}
5788
5789
5790	#ifdef VBOX_WITH_NESTED_HWVIRT
5791	/**
5792	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
5793	* feature. Otherwise, returns the value in @a cbLikely.
5794	*
5795	* @param pVCpu The cross context virtual CPU structure.
5796	* @param pCtx Pointer to the guest-CPU context.
5797	* @param cbLikely The likely instruction length.
5798	*/
5799	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
5800	{
5801	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
5802	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
5803	{
5804	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5805	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
5806	Assert(cbInstr == cbLikely);
5807	return cbInstr;
5808	}
5809	return cbLikely;
5810	}
5811	#endif
5812
5813
5814	/**
5815	* Advances the guest RIP by the number of bytes specified in @a cb. This does
5816	* not make use of any hardware features to determine the instruction length.
5817	*
5818	* @param pVCpu The cross context virtual CPU structure.
5819	* @param pCtx Pointer to the guest-CPU context.
5820	* @param cb RIP increment value in bytes.
5821	*/
5822	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5823	{
5824	pCtx->rip += cb;
5825	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5826	}
5827	#undef HMSVM_UPDATE_INTR_SHADOW
5828
5829
5830	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5831	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5832	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5833
5834	/** @name \#VMEXIT handlers.
5835	* @{
5836	*/
5837
5838	/**
5839	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5840	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5841	*/
5842	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5843	{
5844	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5845
5846	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5847	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5848	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5849	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5850
5851	/*
5852	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
5853	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
5854	* interrupt it is until the host actually take the interrupt.
5855	*
5856	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
5857	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5858	*/
5859	return VINF_EM_RAW_INTERRUPT;
5860	}
5861
5862
5863	/**
5864	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5865	*/
5866	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5867	{
5868	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5869
5870	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5871	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
5872	int rc = VINF_SUCCESS;
5873	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5874	return rc;
5875	}
5876
5877
5878	/**
5879	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5880	*/
5881	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5882	{
5883	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5884
5885	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5886	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
5887	int rc = VINF_SUCCESS;
5888	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5889	return rc;
5890	}
5891
5892
5893	/**
5894	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5895	*/
5896	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5897	{
5898	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5899	PVM pVM = pVCpu->CTX_SUFF(pVM);
5900	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
5901	if (RT_LIKELY(rc == VINF_SUCCESS))
5902	{
5903	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5904	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5905	}
5906	else
5907	{
5908	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5909	rc = VERR_EM_INTERPRETER;
5910	}
5911	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
5912	return rc;
5913	}
5914
5915
5916	/**
5917	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5918	*/
5919	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5920	{
5921	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5922	PVM pVM = pVCpu->CTX_SUFF(pVM);
5923	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
5924	if (RT_LIKELY(rc == VINF_SUCCESS))
5925	{
5926	pSvmTransient->fUpdateTscOffsetting = true;
5927	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5928	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5929	}
5930	else
5931	{
5932	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
5933	rc = VERR_EM_INTERPRETER;
5934	}
5935	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
5936	return rc;
5937	}
5938
5939
5940	/**
5941	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5942	*/
5943	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5944	{
5945	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5946	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5947	if (RT_LIKELY(rc == VINF_SUCCESS))
5948	{
5949	pSvmTransient->fUpdateTscOffsetting = true;
5950	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
5951	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5952	}
5953	else
5954	{
5955	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
5956	rc = VERR_EM_INTERPRETER;
5957	}
5958	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
5959	return rc;
5960	}
5961
5962
5963	/**
5964	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5965	*/
5966	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5967	{
5968	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5969	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
5970	if (RT_LIKELY(rc == VINF_SUCCESS))
5971	{
5972	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5973	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5974	}
5975	else
5976	{
5977	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
5978	rc = VERR_EM_INTERPRETER;
5979	}
5980	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
5981	return rc;
5982	}
5983
5984
5985	/**
5986	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5987	*/
5988	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5989	{
5990	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5991	PVM pVM = pVCpu->CTX_SUFF(pVM);
5992	Assert(!pVM->hm.s.fNestedPaging);
5993	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
5994
5995	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
5996	{
5997	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
5998	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5999	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6000	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6001	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6002	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6003	return VBOXSTRICTRC_VAL(rcStrict);
6004	}
6005
6006	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6007	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6008	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6009	return rc;
6010	}
6011
6012
6013	/**
6014	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6015	*/
6016	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6017	{
6018	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6019
6020	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6021	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6022	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6023	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6024	if (rc != VINF_SUCCESS)
6025	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6026	return rc;
6027	}
6028
6029
6030	/**
6031	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6032	*/
6033	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6034	{
6035	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6036	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6037	if (RT_LIKELY(rc == VINF_SUCCESS))
6038	{
6039	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6040	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6041	}
6042	else
6043	{
6044	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6045	rc = VERR_EM_INTERPRETER;
6046	}
6047	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6048	return rc;
6049	}
6050
6051
6052	/**
6053	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6054	*/
6055	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6056	{
6057	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6058	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6059	int rc = VBOXSTRICTRC_VAL(rc2);
6060	if ( rc == VINF_EM_HALT
6061	\|\| rc == VINF_SUCCESS)
6062	{
6063	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6064
6065	if ( rc == VINF_EM_HALT
6066	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6067	{
6068	rc = VINF_SUCCESS;
6069	}
6070	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6071	}
6072	else
6073	{
6074	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6075	rc = VERR_EM_INTERPRETER;
6076	}
6077	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6078	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6079	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6080	return rc;
6081	}
6082
6083
6084	/**
6085	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6086	* \#VMEXIT.
6087	*/
6088	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6089	{
6090	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6091	return VINF_EM_RESET;
6092	}
6093
6094
6095	/**
6096	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6097	*/
6098	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6099	{
6100	RT_NOREF(pCtx);
6101	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64\n", pSvmTransient->u64ExitCode));
6102	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6103	return VERR_SVM_UNEXPECTED_EXIT;
6104	}
6105
6106
6107	/**
6108	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6109	*/
6110	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6111	{
6112	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6113
6114	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6115	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6116
6117	PVM pVM = pVCpu->CTX_SUFF(pVM);
6118	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
6119	{
6120	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
6121	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6122	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6123	if (fMovCRx)
6124	{
6125	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6126	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6127	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6128	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6129	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6130	return VBOXSTRICTRC_VAL(rcStrict);
6131	}
6132	/* else: SMSW instruction, fall back below to IEM for this. */
6133	}
6134
6135	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6136	int rc = VBOXSTRICTRC_VAL(rc2);
6137	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6138	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6139	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6140	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6141	return rc;
6142	}
6143
6144
6145	/**
6146	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6147	*/
6148	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6149	{
6150	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6151
6152	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6153	Assert(iCrReg <= 15);
6154
6155	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6156	PVM pVM = pVCpu->CTX_SUFF(pVM);
6157	bool fDecodedInstr = false;
6158	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
6159	{
6160	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
6161	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6162	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6163	if (fMovCRx)
6164	{
6165	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6166	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6167	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6168	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6169	fDecodedInstr = true;
6170	}
6171	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6172	}
6173
6174	if (!fDecodedInstr)
6175	{
6176	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6177	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6178	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6179	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6180	rcStrict = VERR_EM_INTERPRETER;
6181	}
6182
6183	if (rcStrict == VINF_SUCCESS)
6184	{
6185	switch (iCrReg)
6186	{
6187	case 0: /* CR0. */
6188	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6189	break;
6190
6191	case 3: /* CR3. */
6192	Assert(!pVM->hm.s.fNestedPaging);
6193	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6194	break;
6195
6196	case 4: /* CR4. */
6197	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6198	break;
6199
6200	case 8: /* CR8 (TPR). */
6201	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6202	break;
6203
6204	default:
6205	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6206	pSvmTransient->u64ExitCode, iCrReg));
6207	break;
6208	}
6209	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6210	}
6211	else
6212	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6213	return VBOXSTRICTRC_TODO(rcStrict);
6214	}
6215
6216
6217	/**
6218	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6219	* \#VMEXIT.
6220	*/
6221	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6222	{
6223	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6224	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6225	PVM pVM = pVCpu->CTX_SUFF(pVM);
6226
6227	int rc;
6228	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6229	{
6230	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6231	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6232
6233	/* Handle TPR patching; intercepted LSTAR write. */
6234	if ( pVM->hm.s.fTPRPatchingActive
6235	&& pCtx->ecx == MSR_K8_LSTAR)
6236	{
6237	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6238	{
6239	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6240	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6241	AssertRC(rc2);
6242	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6243	}
6244	rc = VINF_SUCCESS;
6245	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6246	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6247	return rc;
6248	}
6249
6250	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6251	{
6252	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6253	if (RT_LIKELY(rc == VINF_SUCCESS))
6254	{
6255	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6256	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6257	}
6258	else
6259	AssertMsg( rc == VERR_EM_INTERPRETER
6260	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6261	}
6262	else
6263	{
6264	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6265	if (RT_LIKELY(rc == VINF_SUCCESS))
6266	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6267	else
6268	AssertMsg( rc == VERR_EM_INTERPRETER
6269	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6270	}
6271
6272	if (rc == VINF_SUCCESS)
6273	{
6274	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6275	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6276	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6277	{
6278	/*
6279	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6280	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6281	* EMInterpretWrmsr() changes it.
6282	*/
6283	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6284	}
6285	else if (pCtx->ecx == MSR_K6_EFER)
6286	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
6287	else if (pCtx->ecx == MSR_IA32_TSC)
6288	pSvmTransient->fUpdateTscOffsetting = true;
6289	}
6290	}
6291	else
6292	{
6293	/* MSR Read access. */
6294	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6295	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6296	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6297
6298	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6299	{
6300	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6301	if (RT_LIKELY(rc == VINF_SUCCESS))
6302	{
6303	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6304	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6305	}
6306	else
6307	AssertMsg( rc == VERR_EM_INTERPRETER
6308	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6309	}
6310	else
6311	{
6312	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6313	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6314	{
6315	AssertMsg( rc == VERR_EM_INTERPRETER
6316	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6317	}
6318	/* RIP updated by EMInterpretInstruction(). */
6319	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6320	}
6321	}
6322
6323	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
6324	return rc;
6325	}
6326
6327
6328	/**
6329	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6330	*/
6331	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6332	{
6333	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6334	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6335
6336	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6337	if (pSvmTransient->fWasGuestDebugStateActive)
6338	{
6339	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6340	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6341	return VERR_SVM_UNEXPECTED_EXIT;
6342	}
6343
6344	/*
6345	* Lazy DR0-3 loading.
6346	*/
6347	if (!pSvmTransient->fWasHyperDebugStateActive)
6348	{
6349	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6350	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6351
6352	/* Don't intercept DRx read and writes. */
6353	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6354	pVmcb->ctrl.u16InterceptRdDRx = 0;
6355	pVmcb->ctrl.u16InterceptWrDRx = 0;
6356	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6357
6358	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6359	VMMRZCallRing3Disable(pVCpu);
6360	HM_DISABLE_PREEMPT();
6361
6362	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6363	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6364	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6365
6366	HM_RESTORE_PREEMPT();
6367	VMMRZCallRing3Enable(pVCpu);
6368
6369	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6370	return VINF_SUCCESS;
6371	}
6372
6373	/*
6374	* Interpret the read/writing of DRx.
6375	*/
6376	/** @todo Decode assist. */
6377	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6378	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6379	if (RT_LIKELY(rc == VINF_SUCCESS))
6380	{
6381	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6382	/** @todo CPUM should set this flag! */
6383	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6384	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6385	}
6386	else
6387	Assert(rc == VERR_EM_INTERPRETER);
6388	return VBOXSTRICTRC_TODO(rc);
6389	}
6390
6391
6392	/**
6393	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6394	*/
6395	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6396	{
6397	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6398	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6399	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6400	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6401	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6402	return rc;
6403	}
6404
6405
6406	/**
6407	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6408	*/
6409	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6410	{
6411	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6412
6413	/** @todo decode assists... */
6414	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6415	if (rcStrict == VINF_IEM_RAISED_XCPT)
6416	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6417
6418	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6419	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6420	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6421
6422	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6423	return VBOXSTRICTRC_TODO(rcStrict);
6424	}
6425
6426
6427	/**
6428	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6429	*/
6430	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6431	{
6432	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6433
6434	/* I/O operation lookup arrays. */
6435	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6436	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6437	the result (in AL/AX/EAX). */
6438	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6439
6440	PVM pVM = pVCpu->CTX_SUFF(pVM);
6441	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6442
6443	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6444	SVMIOIOEXITINFO IoExitInfo;
6445	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6446	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6447	uint32_t cbValue = s_aIOSize[uIOWidth];
6448	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6449
6450	if (RT_UNLIKELY(!cbValue))
6451	{
6452	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6453	return VERR_EM_INTERPRETER;
6454	}
6455
6456	VBOXSTRICTRC rcStrict;
6457	bool fUpdateRipAlready = false;
6458	if (IoExitInfo.n.u1STR)
6459	{
6460	#ifdef VBOX_WITH_2ND_IEM_STEP
6461	/* INS/OUTS - I/O String instruction. */
6462	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6463	* in EXITINFO1? Investigate once this thing is up and running. */
6464	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6465	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6466	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6467	static IEMMODE const s_aenmAddrMode[8] =
6468	{
6469	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6470	};
6471	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6472	if (enmAddrMode != (IEMMODE)-1)
6473	{
6474	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6475	if (cbInstr <= 15 && cbInstr >= 1)
6476	{
6477	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6478	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6479	{
6480	/* Don't know exactly how to detect whether u3SEG is valid, currently
6481	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6482	2384 Opterons when only checking NRIP. */
6483	if ( (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6484	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6485	{
6486	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6487	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6488	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6489	IoExitInfo.n.u3SEG, true /fIoChecked/);
6490	}
6491	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6492	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6493	X86_SREG_DS, true /fIoChecked/);
6494	else
6495	rcStrict = IEMExecOne(pVCpu);
6496	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6497	}
6498	else
6499	{
6500	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6501	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6502	true /fIoChecked/);
6503	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6504	}
6505	}
6506	else
6507	{
6508	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6509	rcStrict = IEMExecOne(pVCpu);
6510	}
6511	}
6512	else
6513	{
6514	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6515	rcStrict = IEMExecOne(pVCpu);
6516	}
6517	fUpdateRipAlready = true;
6518
6519	#else
6520	/* INS/OUTS - I/O String instruction. */
6521	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6522
6523	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6524	* in EXITINFO1? Investigate once this thing is up and running. */
6525
6526	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6527	if (rcStrict == VINF_SUCCESS)
6528	{
6529	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6530	{
6531	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6532	(DISCPUMODE)pDis->uAddrMode, cbValue);
6533	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6534	}
6535	else
6536	{
6537	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6538	(DISCPUMODE)pDis->uAddrMode, cbValue);
6539	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6540	}
6541	}
6542	else
6543	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6544	#endif
6545	}
6546	else
6547	{
6548	/* IN/OUT - I/O instruction. */
6549	Assert(!IoExitInfo.n.u1REP);
6550
6551	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6552	{
6553	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6554	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6555	}
6556	else
6557	{
6558	uint32_t u32Val = 0;
6559	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6560	if (IOM_SUCCESS(rcStrict))
6561	{
6562	/* Save result of I/O IN instr. in AL/AX/EAX. */
6563	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6564	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6565	}
6566	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6567	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6568
6569	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6570	}
6571	}
6572
6573	if (IOM_SUCCESS(rcStrict))
6574	{
6575	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6576	if (!fUpdateRipAlready)
6577	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6578
6579	/*
6580	* If any I/O breakpoints are armed, we need to check if one triggered
6581	* and take appropriate action.
6582	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6583	*/
6584	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6585	* execution engines about whether hyper BPs and such are pending. */
6586	uint32_t const uDr7 = pCtx->dr[7];
6587	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6588	&& X86_DR7_ANY_RW_IO(uDr7)
6589	&& (pCtx->cr4 & X86_CR4_DE))
6590	\|\| DBGFBpIsHwIoArmed(pVM)))
6591	{
6592	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6593	VMMRZCallRing3Disable(pVCpu);
6594	HM_DISABLE_PREEMPT();
6595
6596	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6597	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6598
6599	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6600	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6601	{
6602	/* Raise #DB. */
6603	pVmcb->guest.u64DR6 = pCtx->dr[6];
6604	pVmcb->guest.u64DR7 = pCtx->dr[7];
6605	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6606	hmR0SvmSetPendingXcptDB(pVCpu);
6607	}
6608	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6609	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6610	else if ( rcStrict2 != VINF_SUCCESS
6611	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6612	rcStrict = rcStrict2;
6613	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6614
6615	HM_RESTORE_PREEMPT();
6616	VMMRZCallRing3Enable(pVCpu);
6617	}
6618
6619	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6620	}
6621
6622	#ifdef VBOX_STRICT
6623	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6624	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6625	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6626	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6627	else
6628	{
6629	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6630	* statuses, that the VMM device and some others may return. See
6631	* IOM_SUCCESS() for guidance. */
6632	AssertMsg( RT_FAILURE(rcStrict)
6633	\|\| rcStrict == VINF_SUCCESS
6634	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6635	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6636	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6637	\|\| rcStrict == VINF_EM_RAW_TO_R3
6638	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6639	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6640	}
6641	#endif
6642	return VBOXSTRICTRC_TODO(rcStrict);
6643	}
6644
6645
6646	/**
6647	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6648	*/
6649	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6650	{
6651	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6652	PVM pVM = pVCpu->CTX_SUFF(pVM);
6653	Assert(pVM->hm.s.fNestedPaging);
6654
6655	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6656
6657	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6658	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6659	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6660	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6661
6662	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
6663
6664	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6665	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
6666	if ( pVM->hm.s.fTprPatchingAllowed
6667	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6668	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6669	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6670	&& !CPUMIsGuestInLongModeEx(pCtx)
6671	&& !CPUMGetGuestCPL(pVCpu)
6672	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6673	{
6674	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6675	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6676
6677	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6678	{
6679	/* Only attempt to patch the instruction once. */
6680	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6681	if (!pPatch)
6682	return VINF_EM_HM_PATCH_TPR_INSTR;
6683	}
6684	}
6685	#endif
6686
6687	/*
6688	* Determine the nested paging mode.
6689	*/
6690	PGMMODE enmNestedPagingMode;
6691	#if HC_ARCH_BITS == 32
6692	if (CPUMIsGuestInLongModeEx(pCtx))
6693	enmNestedPagingMode = PGMMODE_AMD64_NX;
6694	else
6695	#endif
6696	enmNestedPagingMode = PGMGetHostMode(pVM);
6697
6698	/*
6699	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6700	*/
6701	int rc;
6702	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6703	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6704	{
6705	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
6706	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
6707	if (pVCpu->hm.s.Event.fPending)
6708	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6709
6710	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6711	u32ErrCode);
6712	rc = VBOXSTRICTRC_VAL(rc2);
6713
6714	/*
6715	* If we succeed, resume guest execution.
6716	* If we fail in interpreting the instruction because we couldn't get the guest physical address
6717	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
6718	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
6719	* weird case. See @bugref{6043}.
6720	*/
6721	if ( rc == VINF_SUCCESS
6722	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6723	\|\| rc == VERR_PAGE_NOT_PRESENT)
6724	{
6725	/* Successfully handled MMIO operation. */
6726	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6727	rc = VINF_SUCCESS;
6728	}
6729	return rc;
6730	}
6731
6732	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6733	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6734	TRPMResetTrap(pVCpu);
6735
6736	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6737
6738	/*
6739	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6740	*/
6741	if ( rc == VINF_SUCCESS
6742	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6743	\|\| rc == VERR_PAGE_NOT_PRESENT)
6744	{
6745	/* We've successfully synced our shadow page tables. */
6746	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6747	rc = VINF_SUCCESS;
6748	}
6749
6750	return rc;
6751	}
6752
6753
6754	/**
6755	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6756	* \#VMEXIT.
6757	*/
6758	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6759	{
6760	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6761
6762	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6763	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
6764	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;
6765
6766	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
6767	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
6768	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
6769
6770	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6771	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6772	return VINF_SUCCESS;
6773	}
6774
6775
6776	/**
6777	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6778	* \#VMEXIT.
6779	*/
6780	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6781	{
6782	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6783
6784	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6785
6786	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6787	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6788	#endif
6789
6790	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6791	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6792	{
6793	/*
6794	* AMD-V provides us with the exception which caused the TS; we collect
6795	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
6796	*/
6797	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
6798	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6799	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6800	}
6801
6802	/** @todo Emulate task switch someday, currently just going back to ring-3 for
6803	* emulation. */
6804	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6805	return VERR_EM_INTERPRETER;
6806	}
6807
6808
6809	/**
6810	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6811	*/
6812	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6813	{
6814	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6815	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
6816
6817	bool fRipUpdated;
6818	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
6819	if (RT_SUCCESS(rcStrict))
6820	{
6821	/* Only update the RIP if we're continuing guest execution and not
6822	in the case of say VINF_GIM_R3_HYPERCALL. */
6823	if ( rcStrict == VINF_SUCCESS
6824	&& !fRipUpdated)
6825	{
6826	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
6827	}
6828
6829	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
6830	we would need to reload the guest changed bits here before VM-entry. */
6831	return VBOXSTRICTRC_VAL(rcStrict);
6832	}
6833
6834	hmR0SvmSetPendingXcptUD(pVCpu);
6835	return VINF_SUCCESS;
6836	}
6837
6838
6839	/**
6840	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6841	*/
6842	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6843	{
6844	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6845	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
6846	return VINF_EM_RAW_INTERRUPT;
6847	}
6848
6849
6850	/**
6851	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
6852	*/
6853	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6854	{
6855	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6856
6857	/* Clear NMI blocking. */
6858	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6859
6860	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6861	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6862	hmR0SvmClearIretIntercept(pVmcb);
6863
6864	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6865	return VINF_SUCCESS;
6866	}
6867
6868
6869	/**
6870	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
6871	* Conditional \#VMEXIT.
6872	*/
6873	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6874	{
6875	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6876
6877	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6878
6879	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
6880	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6881	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6882	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
6883	PVM pVM = pVCpu->CTX_SUFF(pVM);
6884
6885	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
6886	if (pVM->hm.s.fNestedPaging)
6887	{
6888	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
6889	if (!pSvmTransient->fVectoringDoublePF)
6890	{
6891	/* A genuine guest #PF, reflect it to the guest. */
6892	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
6893	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
6894	uFaultAddress, u32ErrCode));
6895	}
6896	else
6897	{
6898	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
6899	hmR0SvmSetPendingXcptDF(pVCpu);
6900	Log4(("Pending #DF due to vectoring #PF. NP\n"));
6901	}
6902	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
6903	return VINF_SUCCESS;
6904	}
6905	#endif
6906
6907	Assert(!pVM->hm.s.fNestedPaging);
6908
6909	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6910	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
6911	if ( pVM->hm.s.fTprPatchingAllowed
6912	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
6913	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
6914	&& !CPUMIsGuestInLongModeEx(pCtx)
6915	&& !CPUMGetGuestCPL(pVCpu)
6916	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6917	{
6918	RTGCPHYS GCPhysApicBase;
6919	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6920	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6921
6922	/* Check if the page at the fault-address is the APIC base. */
6923	RTGCPHYS GCPhysPage;
6924	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
6925	if ( rc2 == VINF_SUCCESS
6926	&& GCPhysPage == GCPhysApicBase)
6927	{
6928	/* Only attempt to patch the instruction once. */
6929	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6930	if (!pPatch)
6931	return VINF_EM_HM_PATCH_TPR_INSTR;
6932	}
6933	}
6934	#endif
6935
6936	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
6937	pCtx->rip, u32ErrCode, pCtx->cr3));
6938
6939	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
6940	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
6941	if (pSvmTransient->fVectoringPF)
6942	{
6943	Assert(pVCpu->hm.s.Event.fPending);
6944	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6945	}
6946
6947	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
6948	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
6949
6950	Log4(("#PF rc=%Rrc\n", rc));
6951
6952	if (rc == VINF_SUCCESS)
6953	{
6954	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
6955	TRPMResetTrap(pVCpu);
6956	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6957	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6958	return rc;
6959	}
6960	else if (rc == VINF_EM_RAW_GUEST_TRAP)
6961	{
6962	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
6963
6964	if (!pSvmTransient->fVectoringDoublePF)
6965	{
6966	/* It's a guest page fault and needs to be reflected to the guest. */
6967	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
6968	TRPMResetTrap(pVCpu);
6969	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
6970	}
6971	else
6972	{
6973	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
6974	TRPMResetTrap(pVCpu);
6975	hmR0SvmSetPendingXcptDF(pVCpu);
6976	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
6977	}
6978
6979	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
6980	return VINF_SUCCESS;
6981	}
6982
6983	TRPMResetTrap(pVCpu);
6984	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
6985	return rc;
6986	}
6987
6988
6989	/**
6990	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
6991	* Conditional \#VMEXIT.
6992	*/
6993	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6994	{
6995	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6996
6997	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
6998	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6999	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7000
7001	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7002	VMMRZCallRing3Disable(pVCpu);
7003	HM_DISABLE_PREEMPT();
7004
7005	int rc;
7006	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7007	if (pSvmTransient->fWasGuestFPUStateActive)
7008	{
7009	rc = VINF_EM_RAW_GUEST_TRAP;
7010	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7011	}
7012	else
7013	{
7014	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7015	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7016	#endif
7017	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7018	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7019	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7020	}
7021
7022	HM_RESTORE_PREEMPT();
7023	VMMRZCallRing3Enable(pVCpu);
7024
7025	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7026	{
7027	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7028	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7029	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7030	pVCpu->hm.s.fPreloadGuestFpu = true;
7031	}
7032	else
7033	{
7034	/* Forward #NM to the guest. */
7035	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7036	hmR0SvmSetPendingXcptNM(pVCpu);
7037	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7038	}
7039	return VINF_SUCCESS;
7040	}
7041
7042
7043	/**
7044	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7045	* Conditional \#VMEXIT.
7046	*/
7047	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7048	{
7049	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7050
7051	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7052	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7053	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7054
7055	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7056	if (pVCpu->hm.s.fGIMTrapXcptUD)
7057	{
7058	uint8_t cbInstr = 0;
7059	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7060	if (rcStrict == VINF_SUCCESS)
7061	{
7062	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7063	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7064	rc = VINF_SUCCESS;
7065	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7066	}
7067	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7068	rc = VINF_SUCCESS;
7069	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7070	rc = VINF_GIM_R3_HYPERCALL;
7071	else
7072	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7073	}
7074
7075	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7076	if (RT_FAILURE(rc))
7077	{
7078	hmR0SvmSetPendingXcptUD(pVCpu);
7079	rc = VINF_SUCCESS;
7080	}
7081
7082	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7083	return rc;
7084	}
7085
7086
7087	/**
7088	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7089	* Conditional \#VMEXIT.
7090	*/
7091	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7092	{
7093	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7094
7095	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7096	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7097	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7098
7099	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7100
7101	if (!(pCtx->cr0 & X86_CR0_NE))
7102	{
7103	PVM pVM = pVCpu->CTX_SUFF(pVM);
7104	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7105	unsigned cbOp;
7106	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7107	if (RT_SUCCESS(rc))
7108	{
7109	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7110	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7111	if (RT_SUCCESS(rc))
7112	pCtx->rip += cbOp;
7113	}
7114	else
7115	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7116	return rc;
7117	}
7118
7119	hmR0SvmSetPendingXcptMF(pVCpu);
7120	return VINF_SUCCESS;
7121	}
7122
7123
7124	/**
7125	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7126	* \#VMEXIT.
7127	*/
7128	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7129	{
7130	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7131
7132	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7133	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7134	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7135	{
7136	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7137	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7138	}
7139
7140	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7141
7142	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7143	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7144	PVM pVM = pVCpu->CTX_SUFF(pVM);
7145	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7146	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7147	if (rc == VINF_EM_RAW_GUEST_TRAP)
7148	{
7149	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7150	if (CPUMIsHyperDebugStateActive(pVCpu))
7151	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7152
7153	/* Reflect the exception back to the guest. */
7154	hmR0SvmSetPendingXcptDB(pVCpu);
7155	rc = VINF_SUCCESS;
7156	}
7157
7158	/*
7159	* Update DR6.
7160	*/
7161	if (CPUMIsHyperDebugStateActive(pVCpu))
7162	{
7163	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7164	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7165	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7166	}
7167	else
7168	{
7169	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7170	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7171	}
7172
7173	return rc;
7174	}
7175
7176
7177	/**
7178	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7179	* Conditional \#VMEXIT.
7180	*/
7181	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7182	{
7183	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7184
7185	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7186	* shutdown VMEXIT. */
7187	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7188
7189	SVMEVENT Event;
7190	Event.u = 0;
7191	Event.n.u1Valid = 1;
7192	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7193	Event.n.u8Vector = X86_XCPT_AC;
7194	Event.n.u1ErrorCodeValid = 1;
7195	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7196	return VINF_SUCCESS;
7197	}
7198
7199
7200	/**
7201	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7202	* Conditional \#VMEXIT.
7203	*/
7204	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7205	{
7206	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7207
7208	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7209
7210	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7211	if (rc == VINF_EM_RAW_GUEST_TRAP)
7212	{
7213	SVMEVENT Event;
7214	Event.u = 0;
7215	Event.n.u1Valid = 1;
7216	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7217	Event.n.u8Vector = X86_XCPT_BP;
7218	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7219	}
7220
7221	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7222	return rc;
7223	}
7224
7225
7226	#ifdef VBOX_WITH_NESTED_HWVIRT
7227	/**
7228	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7229	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7230	*/
7231	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7232	{
7233	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7234
7235	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7236
7237	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7238	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7239	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7240	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7241
7242	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7243	pCtx->rip, u32ErrCode, pCtx->cr3));
7244
7245	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7246	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7247	if (pSvmTransient->fVectoringPF)
7248	{
7249	Assert(pVCpu->hm.s.Event.fPending);
7250	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7251	}
7252
7253	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7254
7255	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7256	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7257
7258	Log4(("#PFNested: rc=%Rrc\n", rc));
7259
7260	if (rc == VINF_SUCCESS)
7261	{
7262	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7263	TRPMResetTrap(pVCpu);
7264	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7265	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7266	return rc;
7267	}
7268
7269	if (rc == VINF_EM_RAW_GUEST_TRAP)
7270	{
7271	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7272
7273	if (!pSvmTransient->fVectoringDoublePF)
7274	{
7275	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7276	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7277	TRPMResetTrap(pVCpu);
7278	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7279	}
7280	else
7281	{
7282	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7283	TRPMResetTrap(pVCpu);
7284	hmR0SvmSetPendingXcptDF(pVCpu);
7285	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7286	}
7287
7288	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7289	return VINF_SUCCESS;
7290	}
7291
7292	TRPMResetTrap(pVCpu);
7293	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7294	return rc;
7295	}
7296
7297
7298	/**
7299	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7300	*/
7301	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7302	{
7303	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7304
7305	/** @todo Stat. */
7306	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7307	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7308	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7309	return VBOXSTRICTRC_VAL(rcStrict);
7310	}
7311
7312
7313	/**
7314	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7315	*/
7316	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7317	{
7318	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7319
7320	/** @todo Stat. */
7321	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7322	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7323	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7324	return VBOXSTRICTRC_VAL(rcStrict);
7325	}
7326
7327
7328	/**
7329	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7330	*/
7331	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7332	{
7333	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7334
7335	/** @todo Stat. */
7336	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7337	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7338	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7339	if (rcStrict == VINF_SUCCESS)
7340	{
7341	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7342	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7343	\| HM_CHANGED_GUEST_TR
7344	\| HM_CHANGED_GUEST_LDTR);
7345	}
7346	return VBOXSTRICTRC_VAL(rcStrict);
7347	}
7348
7349
7350	/**
7351	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7352	*/
7353	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7354	{
7355	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7356
7357	/** @todo Stat. */
7358	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7359	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7360	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7361	return VBOXSTRICTRC_VAL(rcStrict);
7362	}
7363
7364
7365	/**
7366	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7367	*/
7368	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7369	{
7370	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7371	/** @todo Stat. */
7372	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7373	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7374	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7375	return VBOXSTRICTRC_VAL(rcStrict);
7376	}
7377
7378
7379	/**
7380	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7381	*/
7382	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7383	{
7384	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7385	/** @todo Stat. */
7386	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7387	#if 0
7388	VBOXSTRICTRC rcStrict;
7389	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7390	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7391	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7392	if (rcStrict == VINF_SUCCESS)
7393	{
7394	rcStrict = VINF_SVM_VMRUN;
7395	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7396	}
7397	return VBOXSTRICTRC_VAL(rcStrict);
7398	#endif
7399	return VERR_EM_INTERPRETER;
7400	}
7401
7402
7403	/**
7404	* Nested-guest \#VMEXIT handler for IRET (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7405	*/
7406	HMSVM_EXIT_DECL hmR0SvmNestedExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7407	{
7408	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7409
7410	/* Clear NMI blocking. */
7411	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7412
7413	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7414	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
7415	hmR0SvmClearIretIntercept(pVmcbNstGst);
7416
7417	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEventNested() and resume guest execution. */
7418	return VINF_SUCCESS;
7419	}
7420
7421
7422	/**
7423	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7424	* Unconditional \#VMEXIT.
7425	*/
7426	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7427	{
7428	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7429
7430	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7431	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7432	* shutdown VMEXIT. */
7433	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7434	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7435	{
7436	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7437	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7438	}
7439
7440	hmR0SvmSetPendingXcptDB(pVCpu);
7441	return VINF_SUCCESS;
7442	}
7443
7444
7445	/**
7446	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7447	* Conditional \#VMEXIT.
7448	*/
7449	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7450	{
7451	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7452
7453	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7454	* shutdown VMEXIT. */
7455	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7456
7457	SVMEVENT Event;
7458	Event.u = 0;
7459	Event.n.u1Valid = 1;
7460	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7461	Event.n.u8Vector = X86_XCPT_BP;
7462	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7463	return VINF_SUCCESS;
7464	}
7465
7466	#endif /* VBOX_WITH_NESTED_HWVIRT */
7467
7468
7469	/** @} */
7470

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 69713

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