HMSVMR0.cpp@ 69786

Last change on this file since 69786 was 69786, checked in by vboxsync, 7 years ago
VMM/HMSVMR0: Nested Hw.virt: Fix lazy loading debug registers unintentionally while executing the nested-guest.
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1	/* $Id: HMSVMR0.cpp 69786 2017-11-21 06:49:59Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/thread.h>
25
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#include <VBox/vmm/apic.h>
33	#include "HMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include "HMSVMR0.h"
36	#include "dtrace/VBoxVMM.h"
37
38	#define HMSVM_USE_IEM_EVENT_REFLECTION
39	#ifdef DEBUG_ramshankar
40	# define HMSVM_SYNC_FULL_GUEST_STATE
41	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
42	# define HMSVM_ALWAYS_TRAP_PF
43	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
44	#endif
45
46
47	/*********************************************************************************************************************************
48	* Defined Constants And Macros *
49	*********************************************************************************************************************************/
50	#ifdef VBOX_WITH_STATISTICS
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
52	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
53	if ((u64ExitCode) == SVM_EXIT_NPF) \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
55	else \
56	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
57	} while (0)
58	#else
59	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
60	#endif
61
62	/** If we decide to use a function table approach this can be useful to
63	* switch to a "static DECLCALLBACK(int)". */
64	#define HMSVM_EXIT_DECL static int
65
66	/** Macro for checking and returning from the using function for
67	* \#VMEXIT intercepts that maybe caused during delivering of another
68	* event in the guest. */
69	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
70	do \
71	{ \
72	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
73	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
74	else if (rc == VINF_HM_DOUBLE_FAULT) \
75	return VINF_SUCCESS; \
76	else \
77	return rc; \
78	} while (0)
79
80	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
81	* instruction that exited. */
82	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
83	do { \
84	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
85	(a_rc) = VINF_EM_DBG_STEPPED; \
86	} while (0)
87
88	/** Assert that preemption is disabled or covered by thread-context hooks. */
89	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
90	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
91
92	/** Assert that we haven't migrated CPUs when thread-context hooks are not
93	* used. */
94	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
95	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
96	("Illegal migration! Entered on CPU %u Current %u\n", \
97	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
98
99	/**
100	* Exception bitmap mask for all contributory exceptions.
101	*
102	* Page fault is deliberately excluded here as it's conditional as to whether
103	* it's contributory or benign. Page faults are handled separately.
104	*/
105	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
106	\| RT_BIT(X86_XCPT_DE))
107
108	/**
109	* Mandatory/unconditional guest control intercepts.
110	*/
111	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
112	\| SVM_CTRL_INTERCEPT_NMI \
113	\| SVM_CTRL_INTERCEPT_INIT \
114	\| SVM_CTRL_INTERCEPT_RDPMC \
115	\| SVM_CTRL_INTERCEPT_CPUID \
116	\| SVM_CTRL_INTERCEPT_RSM \
117	\| SVM_CTRL_INTERCEPT_HLT \
118	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
119	\| SVM_CTRL_INTERCEPT_MSR_PROT \
120	\| SVM_CTRL_INTERCEPT_INVLPGA \
121	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
122	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
123	\| SVM_CTRL_INTERCEPT_VMRUN \
124	\| SVM_CTRL_INTERCEPT_VMMCALL \
125	\| SVM_CTRL_INTERCEPT_VMLOAD \
126	\| SVM_CTRL_INTERCEPT_VMSAVE \
127	\| SVM_CTRL_INTERCEPT_STGI \
128	\| SVM_CTRL_INTERCEPT_CLGI \
129	\| SVM_CTRL_INTERCEPT_SKINIT \
130	\| SVM_CTRL_INTERCEPT_WBINVD \
131	\| SVM_CTRL_INTERCEPT_MONITOR \
132	\| SVM_CTRL_INTERCEPT_MWAIT \
133	\| SVM_CTRL_INTERCEPT_XSETBV)
134
135	/**
136	* Mandatory/unconditional nested-guest control intercepts.
137	*/
138	#define HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS ( HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS \
139	\| SVM_CTRL_INTERCEPT_SMI)
140
141	/** @name VMCB Clean Bits.
142	*
143	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
144	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
145	* memory.
146	*
147	* @{ */
148	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
149	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
150	/** I/O permission bitmap, MSR permission bitmap. */
151	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
152	/** ASID. */
153	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
154	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
155	V_INTR_VECTOR. */
156	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
157	/** Nested Paging: Nested CR3 (nCR3), PAT. */
158	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
159	/** Control registers (CR0, CR3, CR4, EFER). */
160	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
161	/** Debug registers (DR6, DR7). */
162	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
163	/** GDT, IDT limit and base. */
164	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
165	/** Segment register: CS, SS, DS, ES limit and base. */
166	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
167	/** CR2.*/
168	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
169	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
170	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
171	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
172	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
173	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
174	/** Mask of all valid VMCB Clean bits. */
175	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
176	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
177	\| HMSVM_VMCB_CLEAN_ASID \
178	\| HMSVM_VMCB_CLEAN_TPR \
179	\| HMSVM_VMCB_CLEAN_NP \
180	\| HMSVM_VMCB_CLEAN_CRX_EFER \
181	\| HMSVM_VMCB_CLEAN_DRX \
182	\| HMSVM_VMCB_CLEAN_DT \
183	\| HMSVM_VMCB_CLEAN_SEG \
184	\| HMSVM_VMCB_CLEAN_CR2 \
185	\| HMSVM_VMCB_CLEAN_LBR \
186	\| HMSVM_VMCB_CLEAN_AVIC)
187	/** @} */
188
189	/** @name SVM transient.
190	*
191	* A state structure for holding miscellaneous information across AMD-V
192	* VMRUN/\#VMEXIT operation, restored after the transition.
193	*
194	* @{ */
195	typedef struct SVMTRANSIENT
196	{
197	/** The host's rflags/eflags. */
198	RTCCUINTREG fEFlags;
199	#if HC_ARCH_BITS == 32
200	uint32_t u32Alignment0;
201	#endif
202
203	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
204	uint64_t u64ExitCode;
205	/** The guest's TPR value used for TPR shadowing. */
206	uint8_t u8GuestTpr;
207	/** Alignment. */
208	uint8_t abAlignment0[7];
209
210	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
211	bool fWasGuestFPUStateActive;
212	/** Whether the guest debug state was active at the time of \#VMEXIT. */
213	bool fWasGuestDebugStateActive;
214	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
215	bool fWasHyperDebugStateActive;
216	/** Whether the TSC offset mode needs to be updated. */
217	bool fUpdateTscOffsetting;
218	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
219	bool fRestoreTscAuxMsr;
220	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
221	* contributary exception or a page-fault. */
222	bool fVectoringDoublePF;
223	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
224	* external interrupt or NMI. */
225	bool fVectoringPF;
226	} SVMTRANSIENT, *PSVMTRANSIENT;
227	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
228	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
229	/** @} */
230
231	/**
232	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
233	*/
234	typedef enum SVMMSREXITREAD
235	{
236	/** Reading this MSR causes a \#VMEXIT. */
237	SVMMSREXIT_INTERCEPT_READ = 0xb,
238	/** Reading this MSR does not cause a \#VMEXIT. */
239	SVMMSREXIT_PASSTHRU_READ
240	} SVMMSREXITREAD;
241
242	/**
243	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
244	*/
245	typedef enum SVMMSREXITWRITE
246	{
247	/** Writing to this MSR causes a \#VMEXIT. */
248	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
249	/** Writing to this MSR does not cause a \#VMEXIT. */
250	SVMMSREXIT_PASSTHRU_WRITE
251	} SVMMSREXITWRITE;
252
253	/**
254	* SVM \#VMEXIT handler.
255	*
256	* @returns VBox status code.
257	* @param pVCpu The cross context virtual CPU structure.
258	* @param pMixedCtx Pointer to the guest-CPU context.
259	* @param pSvmTransient Pointer to the SVM-transient structure.
260	*/
261	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
262
263
264	/*********************************************************************************************************************************
265	* Internal Functions *
266	*********************************************************************************************************************************/
267	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
268	SVMMSREXITWRITE enmWrite);
269	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
270	static void hmR0SvmLeave(PVMCPU pVCpu);
271
272	/** @name \#VMEXIT handlers.
273	* @{
274	*/
275	static FNSVMEXITHANDLER hmR0SvmExitIntr;
276	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
277	static FNSVMEXITHANDLER hmR0SvmExitInvd;
278	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
279	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
280	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
281	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
282	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
283	static FNSVMEXITHANDLER hmR0SvmExitHlt;
284	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
285	static FNSVMEXITHANDLER hmR0SvmExitMwait;
286	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
287	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
288	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
289	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
290	static FNSVMEXITHANDLER hmR0SvmExitMsr;
291	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
292	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
293	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
294	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
295	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
296	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
297	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
298	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
299	static FNSVMEXITHANDLER hmR0SvmExitPause;
300	static FNSVMEXITHANDLER hmR0SvmExitIret;
301	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
302	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
303	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
304	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
305	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
306	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
307	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
308	#ifdef VBOX_WITH_NESTED_HWVIRT
309	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
310	static FNSVMEXITHANDLER hmR0SvmExitClgi;
311	static FNSVMEXITHANDLER hmR0SvmExitStgi;
312	static FNSVMEXITHANDLER hmR0SvmExitVmload;
313	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
314	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
315	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
316	static FNSVMEXITHANDLER hmR0SvmNestedExitIret;
317	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
318	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
319	#endif
320	/** @} */
321
322	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
323	#ifdef VBOX_WITH_NESTED_HWVIRT
324	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
325	#endif
326
327
328	/*********************************************************************************************************************************
329	* Global Variables *
330	*********************************************************************************************************************************/
331	/** Ring-0 memory object for the IO bitmap. */
332	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
333	/** Physical address of the IO bitmap. */
334	RTHCPHYS g_HCPhysIOBitmap = 0;
335	/** Pointer to the IO bitmap. */
336	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
337
338	#ifdef VBOX_WITH_NESTED_HWVIRT
339	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
340	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
341	/** Physical address of the nested-guest MSRPM bitmap. */
342	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
343	/** Pointer to the nested-guest MSRPM bitmap. */
344	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
345	#endif
346
347	/**
348	* Sets up and activates AMD-V on the current CPU.
349	*
350	* @returns VBox status code.
351	* @param pCpu Pointer to the CPU info struct.
352	* @param pVM The cross context VM structure. Can be
353	* NULL after a resume!
354	* @param pvCpuPage Pointer to the global CPU page.
355	* @param HCPhysCpuPage Physical address of the global CPU page.
356	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
357	* @param pvArg Unused on AMD-V.
358	*/
359	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
360	void *pvArg)
361	{
362	Assert(!fEnabledByHost);
363	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
364	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
365	Assert(pvCpuPage); NOREF(pvCpuPage);
366	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
367
368	NOREF(pvArg);
369	NOREF(fEnabledByHost);
370
371	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
372	RTCCUINTREG fEFlags = ASMIntDisableFlags();
373
374	/*
375	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
376	*/
377	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
378	if (u64HostEfer & MSR_K6_EFER_SVME)
379	{
380	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
381	if ( pVM
382	&& pVM->hm.s.svm.fIgnoreInUseError)
383	{
384	pCpu->fIgnoreAMDVInUseError = true;
385	}
386
387	if (!pCpu->fIgnoreAMDVInUseError)
388	{
389	ASMSetFlags(fEFlags);
390	return VERR_SVM_IN_USE;
391	}
392	}
393
394	/* Turn on AMD-V in the EFER MSR. */
395	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
396
397	/* Write the physical page address where the CPU will store the host state while executing the VM. */
398	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
399
400	/* Restore interrupts. */
401	ASMSetFlags(fEFlags);
402
403	/*
404	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
405	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
406	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
407	* guest code.
408	*/
409	pCpu->fFlushAsidBeforeUse = true;
410
411	/*
412	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
413	*/
414	++pCpu->cTlbFlushes;
415
416	return VINF_SUCCESS;
417	}
418
419
420	/**
421	* Deactivates AMD-V on the current CPU.
422	*
423	* @returns VBox status code.
424	* @param pCpu Pointer to the CPU info struct.
425	* @param pvCpuPage Pointer to the global CPU page.
426	* @param HCPhysCpuPage Physical address of the global CPU page.
427	*/
428	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
429	{
430	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
431	AssertReturn( HCPhysCpuPage
432	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
433	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
434	NOREF(pCpu);
435
436	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
437	RTCCUINTREG fEFlags = ASMIntDisableFlags();
438
439	/* Turn off AMD-V in the EFER MSR. */
440	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
441	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
442
443	/* Invalidate host state physical address. */
444	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
445
446	/* Restore interrupts. */
447	ASMSetFlags(fEFlags);
448
449	return VINF_SUCCESS;
450	}
451
452
453	/**
454	* Does global AMD-V initialization (called during module initialization).
455	*
456	* @returns VBox status code.
457	*/
458	VMMR0DECL(int) SVMR0GlobalInit(void)
459	{
460	/*
461	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
462	* once globally here instead of per-VM.
463	*/
464	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
465	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
466	if (RT_FAILURE(rc))
467	return rc;
468
469	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
470	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
471
472	/* Set all bits to intercept all IO accesses. */
473	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
474
475	#ifdef VBOX_WITH_NESTED_HWVIRT
476	/*
477	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
478	*/
479	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
480	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
481	if (RT_FAILURE(rc))
482	return rc;
483
484	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
485	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
486
487	/* Set all bits to intercept all MSR accesses. */
488	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
489	#endif
490
491	return VINF_SUCCESS;
492	}
493
494
495	/**
496	* Does global AMD-V termination (called during module termination).
497	*/
498	VMMR0DECL(void) SVMR0GlobalTerm(void)
499	{
500	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
501	{
502	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
503	g_pvIOBitmap = NULL;
504	g_HCPhysIOBitmap = 0;
505	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
506	}
507
508	#ifdef VBOX_WITH_NESTED_HWVIRT
509	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
510	{
511	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
512	g_pvNstGstMsrBitmap = NULL;
513	g_HCPhysNstGstMsrBitmap = 0;
514	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
515	}
516	#endif
517	}
518
519
520	/**
521	* Frees any allocated per-VCPU structures for a VM.
522	*
523	* @param pVM The cross context VM structure.
524	*/
525	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
526	{
527	for (uint32_t i = 0; i < pVM->cCpus; i++)
528	{
529	PVMCPU pVCpu = &pVM->aCpus[i];
530	AssertPtr(pVCpu);
531
532	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
533	{
534	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
535	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
536	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
537	}
538
539	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
540	{
541	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
542	pVCpu->hm.s.svm.pVmcb = NULL;
543	pVCpu->hm.s.svm.HCPhysVmcb = 0;
544	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
545	}
546
547	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
548	{
549	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
550	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
551	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
552	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
553	}
554	}
555	}
556
557
558	/**
559	* Does per-VM AMD-V initialization.
560	*
561	* @returns VBox status code.
562	* @param pVM The cross context VM structure.
563	*/
564	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
565	{
566	int rc = VERR_INTERNAL_ERROR_5;
567
568	/*
569	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
570	*/
571	uint32_t u32Family;
572	uint32_t u32Model;
573	uint32_t u32Stepping;
574	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
575	{
576	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
577	pVM->hm.s.svm.fAlwaysFlushTLB = true;
578	}
579
580	/*
581	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
582	*/
583	for (VMCPUID i = 0; i < pVM->cCpus; i++)
584	{
585	PVMCPU pVCpu = &pVM->aCpus[i];
586	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
587	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
588	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
589	}
590
591	for (VMCPUID i = 0; i < pVM->cCpus; i++)
592	{
593	PVMCPU pVCpu = &pVM->aCpus[i];
594
595	/*
596	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
597	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
598	*/
599	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
600	if (RT_FAILURE(rc))
601	goto failure_cleanup;
602
603	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
604	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
605	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
606	ASMMemZeroPage(pvVmcbHost);
607
608	/*
609	* Allocate one page for the guest-state VMCB.
610	*/
611	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
612	if (RT_FAILURE(rc))
613	goto failure_cleanup;
614
615	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
616	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
617	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
618	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
619
620	/*
621	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
622	* SVM to not require one.
623	*/
624	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
625	false /* fExecutable */);
626	if (RT_FAILURE(rc))
627	goto failure_cleanup;
628
629	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
630	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
631	/* Set all bits to intercept all MSR accesses (changed later on). */
632	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
633	}
634
635	return VINF_SUCCESS;
636
637	failure_cleanup:
638	hmR0SvmFreeStructs(pVM);
639	return rc;
640	}
641
642
643	/**
644	* Does per-VM AMD-V termination.
645	*
646	* @returns VBox status code.
647	* @param pVM The cross context VM structure.
648	*/
649	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
650	{
651	hmR0SvmFreeStructs(pVM);
652	return VINF_SUCCESS;
653	}
654
655
656	/**
657	* Sets the permission bits for the specified MSR in the MSRPM.
658	*
659	* @param pVmcb Pointer to the VM control block.
660	* @param pbMsrBitmap Pointer to the MSR bitmap.
661	* @param uMsr The MSR for which the access permissions are being set.
662	* @param enmRead MSR read permissions.
663	* @param enmWrite MSR write permissions.
664	*/
665	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
666	SVMMSREXITWRITE enmWrite)
667	{
668	uint16_t offMsrpm;
669	uint32_t uMsrpmBit;
670	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
671	AssertRC(rc);
672
673	Assert(uMsrpmBit < 0x3fff);
674	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
675
676	pbMsrBitmap += offMsrpm;
677	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
678	ASMBitSet(pbMsrBitmap, uMsrpmBit);
679	else
680	ASMBitClear(pbMsrBitmap, uMsrpmBit);
681
682	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
683	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
684	else
685	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
686
687	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
688	}
689
690
691	/**
692	* Sets up AMD-V for the specified VM.
693	* This function is only called once per-VM during initalization.
694	*
695	* @returns VBox status code.
696	* @param pVM The cross context VM structure.
697	*/
698	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
699	{
700	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
701	AssertReturn(pVM, VERR_INVALID_PARAMETER);
702	Assert(pVM->hm.s.svm.fSupported);
703
704	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
705	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
706	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
707
708	for (VMCPUID i = 0; i < pVM->cCpus; i++)
709	{
710	PVMCPU pVCpu = &pVM->aCpus[i];
711	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
712
713	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
714
715	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
716	Assert(!pVCpu->hm.s.idxExitHistoryFree);
717	HMCPU_EXIT_HISTORY_RESET(pVCpu);
718
719	/* Always trap #AC for reasons of security. */
720	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
721
722	/* Always trap #DB for reasons of security. */
723	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
724
725	/* Trap exceptions unconditionally (debug purposes). */
726	#ifdef HMSVM_ALWAYS_TRAP_PF
727	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
728	#endif
729	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
730	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
731	pVmcb->ctrl.u32InterceptXcpt \|= 0
732	\| RT_BIT(X86_XCPT_BP)
733	\| RT_BIT(X86_XCPT_DE)
734	\| RT_BIT(X86_XCPT_NM)
735	\| RT_BIT(X86_XCPT_UD)
736	\| RT_BIT(X86_XCPT_NP)
737	\| RT_BIT(X86_XCPT_SS)
738	\| RT_BIT(X86_XCPT_GP)
739	\| RT_BIT(X86_XCPT_PF)
740	\| RT_BIT(X86_XCPT_MF)
741	;
742	#endif
743
744	/* Set up unconditional intercepts and conditions. */
745	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
746
747	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
748	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
749
750	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
751	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
752
753	/* Intercept all DRx reads and writes by default. Changed later on. */
754	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
755	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
756
757	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
758	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
759
760	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
761	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
762	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
763
764	/* Set IO and MSR bitmap permission bitmap physical addresses. */
765	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
766	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
767
768	/* No LBR virtualization. */
769	pVmcb->ctrl.u64LBRVirt = 0;
770
771	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
772	pVmcb->ctrl.u64VmcbCleanBits = 0;
773
774	/* The host ASID MBZ, for the guest start with 1. */
775	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
776
777	/*
778	* Setup the PAT MSR (applicable for Nested Paging only).
779	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
780	* so choose type 6 for all PAT slots.
781	*/
782	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
783
784	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
785	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
786
787	/* Without Nested Paging, we need additionally intercepts. */
788	if (!pVM->hm.s.fNestedPaging)
789	{
790	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
791	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
792	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
793
794	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
795	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
796	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
797
798	/* Page faults must be intercepted to implement shadow paging. */
799	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
800	}
801
802	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
803	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
804	#endif
805
806	/* Apply the exceptions intercepts needed by the GIM provider. */
807	if (pVCpu->hm.s.fGIMTrapXcptUD)
808	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
809
810	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
811	if (fUsePauseFilter)
812	{
813	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
814	if (fPauseFilterThreshold)
815	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
816	}
817
818	/*
819	* The following MSRs are saved/restored automatically during the world-switch.
820	* Don't intercept guest read/write accesses to these MSRs.
821	*/
822	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
823	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
824	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
825	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
826	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
827	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
828	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
829	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
830	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
831	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
832	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
833	}
834
835	return VINF_SUCCESS;
836	}
837
838
839	/**
840	* Invalidates a guest page by guest virtual address.
841	*
842	* @returns VBox status code.
843	* @param pVM The cross context VM structure.
844	* @param pVCpu The cross context virtual CPU structure.
845	* @param GCVirt Guest virtual address of the page to invalidate.
846	*/
847	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
848	{
849	AssertReturn(pVM, VERR_INVALID_PARAMETER);
850	Assert(pVM->hm.s.svm.fSupported);
851
852	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
853
854	/* Skip it if a TLB flush is already pending. */
855	if (!fFlushPending)
856	{
857	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
858
859	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
860	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
861
862	#if HC_ARCH_BITS == 32
863	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
864	if (CPUMIsGuestInLongMode(pVCpu))
865	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
866	else
867	#endif
868	{
869	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
870	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
871	}
872	}
873	return VINF_SUCCESS;
874	}
875
876
877	/**
878	* Flushes the appropriate tagged-TLB entries.
879	*
880	* @param pVCpu The cross context virtual CPU structure.
881	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
882	* @param pVmcb Pointer to the VM control block.
883	*/
884	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
885	{
886	PVM pVM = pVCpu->CTX_SUFF(pVM);
887	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
888
889	/*
890	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
891	* This can happen both for start & resume due to long jumps back to ring-3.
892	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
893	* so we cannot reuse the ASIDs without flushing.
894	*/
895	bool fNewAsid = false;
896	Assert(pCpu->idCpu != NIL_RTCPUID);
897	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
898	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
899	{
900	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
901	pVCpu->hm.s.fForceTLBFlush = true;
902	fNewAsid = true;
903	}
904
905	#ifdef VBOX_WITH_NESTED_HWVIRT
906	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
907	fNewAsid = true;
908	#else
909	RT_NOREF(pCtx);
910	#endif
911
912	/* Set TLB flush state as checked until we return from the world switch. */
913	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
914
915	/* Check for explicit TLB flushes. */
916	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
917	{
918	pVCpu->hm.s.fForceTLBFlush = true;
919	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
920	}
921
922	/*
923	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
924	* This Host CPU requirement takes precedence.
925	*/
926	if (pVM->hm.s.svm.fAlwaysFlushTLB)
927	{
928	pCpu->uCurrentAsid = 1;
929	pVCpu->hm.s.uCurrentAsid = 1;
930	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
931	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
932
933	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
934	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
935
936	/* Keep track of last CPU ID even when flushing all the time. */
937	if (fNewAsid)
938	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
939	}
940	else
941	{
942	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
943	if (pVCpu->hm.s.fForceTLBFlush)
944	{
945	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
946	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
947
948	if (fNewAsid)
949	{
950	++pCpu->uCurrentAsid;
951
952	bool fHitASIDLimit = false;
953	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
954	{
955	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
956	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
957	fHitASIDLimit = true;
958	}
959
960	if ( fHitASIDLimit
961	\|\| pCpu->fFlushAsidBeforeUse)
962	{
963	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
964	pCpu->fFlushAsidBeforeUse = false;
965	}
966
967	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
968	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
969	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
970	}
971	else
972	{
973	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
974	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
975	else
976	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
977	}
978
979	pVCpu->hm.s.fForceTLBFlush = false;
980	}
981	}
982
983	/* Update VMCB with the ASID. */
984	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
985	{
986	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
987	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
988	}
989
990	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
991	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
992	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
993	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
994	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
995	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
996	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
997	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
998
999	#ifdef VBOX_WITH_STATISTICS
1000	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1001	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1002	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1003	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1004	{
1005	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1006	}
1007	else
1008	{
1009	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1010	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1011	}
1012	#endif
1013	}
1014
1015
1016	/** @name 64-bit guest on 32-bit host OS helper functions.
1017	*
1018	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1019	* mode (code segment, paging). These wrappers/helpers perform the necessary
1020	* bits for the 32->64 switcher.
1021	*
1022	* @{ */
1023	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1024	/**
1025	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1026	*
1027	* @returns VBox status code.
1028	* @param HCPhysVmcbHost Physical address of host VMCB.
1029	* @param HCPhysVmcb Physical address of the VMCB.
1030	* @param pCtx Pointer to the guest-CPU context.
1031	* @param pVM The cross context VM structure.
1032	* @param pVCpu The cross context virtual CPU structure.
1033	*/
1034	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1035	{
1036	uint32_t aParam[8];
1037	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1038	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1039	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1040	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1041	aParam[4] = VM_RC_ADDR(pVM, pVM);
1042	aParam[5] = 0;
1043	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1044	aParam[7] = 0;
1045
1046	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1047	}
1048
1049
1050	/**
1051	* Executes the specified VMRUN handler in 64-bit mode.
1052	*
1053	* @returns VBox status code.
1054	* @param pVM The cross context VM structure.
1055	* @param pVCpu The cross context virtual CPU structure.
1056	* @param pCtx Pointer to the guest-CPU context.
1057	* @param enmOp The operation to perform.
1058	* @param cParams Number of parameters.
1059	* @param paParam Array of 32-bit parameters.
1060	*/
1061	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1062	uint32_t cParams, uint32_t *paParam)
1063	{
1064	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1065	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1066
1067	NOREF(pCtx);
1068
1069	/* Disable interrupts. */
1070	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1071
1072	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1073	RTCPUID idHostCpu = RTMpCpuId();
1074	CPUMR0SetLApic(pVCpu, idHostCpu);
1075	#endif
1076
1077	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1078	CPUMSetHyperEIP(pVCpu, enmOp);
1079	for (int i = (int)cParams - 1; i >= 0; i--)
1080	CPUMPushHyper(pVCpu, paParam[i]);
1081
1082	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1083	/* Call the switcher. */
1084	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1085	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1086
1087	/* Restore interrupts. */
1088	ASMSetFlags(uOldEFlags);
1089	return rc;
1090	}
1091
1092	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1093	/** @} */
1094
1095
1096	/**
1097	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1098	* the corresponding VMCB Clean bit.
1099	*
1100	* @param pVmcb Pointer to the VM control block.
1101	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1102	*/
1103	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1104	{
1105	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1106	{
1107	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1108	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1109	}
1110	}
1111
1112
1113	/**
1114	* Removes an exception from the intercept-exception bitmap in the VMCB and
1115	* updates the corresponding VMCB Clean bit.
1116	*
1117	* @param pVmcb Pointer to the VM control block.
1118	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1119	*/
1120	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1121	{
1122	Assert(u32Xcpt != X86_XCPT_DB);
1123	Assert(u32Xcpt != X86_XCPT_AC);
1124	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1125	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1126	{
1127	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1128	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1129	}
1130	#endif
1131	}
1132
1133
1134	/**
1135	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1136	* Although the guest CR0 is a separate field in the VMCB we have to consider
1137	* the FPU state itself which is shared between the host and the guest.
1138	*
1139	* @returns VBox status code.
1140	* @param pVCpu The cross context virtual CPU structure.
1141	* @param pVmcb Pointer to the VM control block.
1142	* @param pCtx Pointer to the guest-CPU context.
1143	*
1144	* @remarks No-long-jump zone!!!
1145	*/
1146	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1147	{
1148	uint64_t u64GuestCR0 = pCtx->cr0;
1149
1150	/* Always enable caching. */
1151	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1152
1153	/*
1154	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1155	*/
1156	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1157	{
1158	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1159	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1160	}
1161
1162	/*
1163	* Guest FPU bits.
1164	*/
1165	bool fInterceptNM = false;
1166	bool fInterceptMF = false;
1167	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1168	if (CPUMIsGuestFPUStateActive(pVCpu))
1169	{
1170	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1171	if (!(pCtx->cr0 & X86_CR0_NE))
1172	{
1173	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1174	fInterceptMF = true;
1175	}
1176	}
1177	else
1178	{
1179	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1180	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1181	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1182	}
1183
1184	/*
1185	* Update the exception intercept bitmap.
1186	*/
1187	if (fInterceptNM)
1188	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1189	else
1190	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1191
1192	if (fInterceptMF)
1193	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1194	else
1195	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1196
1197	pVmcb->guest.u64CR0 = u64GuestCR0;
1198	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1199	}
1200
1201
1202	/**
1203	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1204	*
1205	* @returns VBox status code.
1206	* @param pVCpu The cross context virtual CPU structure.
1207	* @param pVmcb Pointer to the VM control block.
1208	* @param pCtx Pointer to the guest-CPU context.
1209	*
1210	* @remarks No-long-jump zone!!!
1211	*/
1212	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1213	{
1214	PVM pVM = pVCpu->CTX_SUFF(pVM);
1215
1216	/*
1217	* Guest CR2.
1218	*/
1219	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1220	{
1221	pVmcb->guest.u64CR2 = pCtx->cr2;
1222	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1223	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1224	}
1225
1226	/*
1227	* Guest CR3.
1228	*/
1229	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1230	{
1231	if (pVM->hm.s.fNestedPaging)
1232	{
1233	PGMMODE enmShwPagingMode;
1234	#if HC_ARCH_BITS == 32
1235	if (CPUMIsGuestInLongModeEx(pCtx))
1236	enmShwPagingMode = PGMMODE_AMD64_NX;
1237	else
1238	#endif
1239	enmShwPagingMode = PGMGetHostMode(pVM);
1240
1241	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1242	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1243	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1244	pVmcb->guest.u64CR3 = pCtx->cr3;
1245	}
1246	else
1247	{
1248	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1249	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1250	}
1251
1252	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1253	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1254	}
1255
1256	/*
1257	* Guest CR4.
1258	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1259	*/
1260	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1261	{
1262	uint64_t u64GuestCR4 = pCtx->cr4;
1263	Assert(RT_HI_U32(u64GuestCR4) == 0);
1264	if (!pVM->hm.s.fNestedPaging)
1265	{
1266	switch (pVCpu->hm.s.enmShadowMode)
1267	{
1268	case PGMMODE_REAL:
1269	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1270	AssertFailed();
1271	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1272
1273	case PGMMODE_32_BIT: /* 32-bit paging. */
1274	u64GuestCR4 &= ~X86_CR4_PAE;
1275	break;
1276
1277	case PGMMODE_PAE: /* PAE paging. */
1278	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1279	/** Must use PAE paging as we could use physical memory > 4 GB */
1280	u64GuestCR4 \|= X86_CR4_PAE;
1281	break;
1282
1283	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1284	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1285	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1286	break;
1287	#else
1288	AssertFailed();
1289	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1290	#endif
1291
1292	default: /* shut up gcc */
1293	AssertFailed();
1294	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1295	}
1296	}
1297
1298	pVmcb->guest.u64CR4 = u64GuestCR4;
1299	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1300
1301	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1302	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1303
1304	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1305	}
1306
1307	return VINF_SUCCESS;
1308	}
1309
1310
1311	#ifdef VBOX_WITH_NESTED_HWVIRT
1312	/**
1313	* Loads the nested-guest control registers (CR0, CR2, CR3, CR4) into the VMCB.
1314	*
1315	* @returns VBox status code.
1316	* @param pVCpu The cross context virtual CPU structure.
1317	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1318	* @param pCtx Pointer to the guest-CPU context.
1319	*
1320	* @remarks No-long-jump zone!!!
1321	*/
1322	static int hmR0SvmLoadGuestControlRegsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1323	{
1324	/*
1325	* Guest CR0.
1326	*/
1327	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1328	{
1329	pVmcbNstGst->guest.u64CR0 = pCtx->cr0;
1330	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1331	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1332	}
1333
1334	return hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
1335	}
1336	#endif
1337
1338
1339	/**
1340	* Loads the guest segment registers into the VMCB.
1341	*
1342	* @returns VBox status code.
1343	* @param pVCpu The cross context virtual CPU structure.
1344	* @param pVmcb Pointer to the VM control block.
1345	* @param pCtx Pointer to the guest-CPU context.
1346	*
1347	* @remarks No-long-jump zone!!!
1348	*/
1349	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1350	{
1351	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1352	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1353	{
1354	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1355	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1356	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1357	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1358	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1359	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1360
1361	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1362	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1363	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1364	}
1365
1366	/* Guest TR. */
1367	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1368	{
1369	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1370	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1371	}
1372
1373	/* Guest LDTR. */
1374	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1375	{
1376	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1377	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1378	}
1379
1380	/* Guest GDTR. */
1381	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1382	{
1383	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1384	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1385	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1386	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1387	}
1388
1389	/* Guest IDTR. */
1390	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1391	{
1392	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1393	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1394	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1395	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1396	}
1397	}
1398
1399
1400	/**
1401	* Loads the guest MSRs into the VMCB.
1402	*
1403	* @param pVCpu The cross context virtual CPU structure.
1404	* @param pVmcb Pointer to the VM control block.
1405	* @param pCtx Pointer to the guest-CPU context.
1406	*
1407	* @remarks No-long-jump zone!!!
1408	*/
1409	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1410	{
1411	/* Guest Sysenter MSRs. */
1412	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1413	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1414	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1415
1416	/*
1417	* Guest EFER MSR.
1418	* AMD-V requires guest EFER.SVME to be set. Weird.
1419	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1420	*/
1421	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1422	{
1423	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1424	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1425	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1426	}
1427
1428	/* 64-bit MSRs. */
1429	if (CPUMIsGuestInLongModeEx(pCtx))
1430	{
1431	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1432	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1433	}
1434	else
1435	{
1436	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1437	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1438	{
1439	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1440	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1441	}
1442	}
1443
1444	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1445	* be writable in 32-bit mode. Clarify with AMD spec. */
1446	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1447	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1448	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1449	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1450	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1451	}
1452
1453
1454	/**
1455	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1456	* necessary intercepts accordingly.
1457	*
1458	* @param pVCpu The cross context virtual CPU structure.
1459	* @param pVmcb Pointer to the VM control block.
1460	* @param pCtx Pointer to the guest-CPU context.
1461	*
1462	* @remarks No-long-jump zone!!!
1463	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1464	*/
1465	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1466	{
1467	bool fInterceptMovDRx = false;
1468
1469	/*
1470	* Anyone single stepping on the host side? If so, we'll have to use the
1471	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1472	* the VMM level like the VT-x implementations does.
1473	*/
1474	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1475	if (fStepping)
1476	{
1477	pVCpu->hm.s.fClearTrapFlag = true;
1478	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1479	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1480	}
1481	else
1482	Assert(!DBGFIsStepping(pVCpu));
1483
1484	if ( fStepping
1485	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1486	{
1487	/*
1488	* Use the combined guest and host DRx values found in the hypervisor
1489	* register set because the debugger has breakpoints active or someone
1490	* is single stepping on the host side.
1491	*
1492	* Note! DBGF expects a clean DR6 state before executing guest code.
1493	*/
1494	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1495	if ( CPUMIsGuestInLongModeEx(pCtx)
1496	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1497	{
1498	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1499	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1500	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1501	}
1502	else
1503	#endif
1504	if (!CPUMIsHyperDebugStateActive(pVCpu))
1505	{
1506	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1507	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1508	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1509	}
1510
1511	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1512	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1513	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1514	{
1515	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1516	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1517	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1518	pVCpu->hm.s.fUsingHyperDR7 = true;
1519	}
1520
1521	/** @todo If we cared, we could optimize to allow the guest to read registers
1522	* with the same values. */
1523	fInterceptMovDRx = true;
1524	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1525	}
1526	else
1527	{
1528	/*
1529	* Update DR6, DR7 with the guest values if necessary.
1530	*/
1531	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1532	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1533	{
1534	pVmcb->guest.u64DR7 = pCtx->dr[7];
1535	pVmcb->guest.u64DR6 = pCtx->dr[6];
1536	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1537	pVCpu->hm.s.fUsingHyperDR7 = false;
1538	}
1539
1540	/*
1541	* If the guest has enabled debug registers, we need to load them prior to
1542	* executing guest code so they'll trigger at the right time.
1543	*/
1544	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1545	{
1546	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1547	if ( CPUMIsGuestInLongModeEx(pCtx)
1548	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1549	{
1550	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1551	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1552	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1553	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1554	}
1555	else
1556	#endif
1557	if (!CPUMIsGuestDebugStateActive(pVCpu))
1558	{
1559	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1560	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1561	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1562	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1563	}
1564	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1565	}
1566	/*
1567	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1568	* intercept #DB as DR6 is updated in the VMCB.
1569	*
1570	* Note! If we cared and dared, we could skip intercepting \#DB here.
1571	* However, \#DB shouldn't be performance critical, so we'll play safe
1572	* and keep the code similar to the VT-x code and always intercept it.
1573	*/
1574	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1575	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1576	&& !CPUMIsGuestDebugStateActive(pVCpu))
1577	#else
1578	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1579	#endif
1580	{
1581	fInterceptMovDRx = true;
1582	}
1583	}
1584
1585	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1586	if (fInterceptMovDRx)
1587	{
1588	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1589	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1590	{
1591	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1592	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1593	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1594	}
1595	}
1596	else
1597	{
1598	if ( pVmcb->ctrl.u16InterceptRdDRx
1599	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1600	{
1601	pVmcb->ctrl.u16InterceptRdDRx = 0;
1602	pVmcb->ctrl.u16InterceptWrDRx = 0;
1603	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1604	}
1605	}
1606	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1607	}
1608
1609
1610	#ifdef VBOX_WITH_NESTED_HWVIRT
1611	/**
1612	* Loads the nested-guest APIC state (currently just the TPR).
1613	*
1614	* @param pVCpu The cross context virtual CPU structure.
1615	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1616	*/
1617	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1618	{
1619	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1620	{
1621	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1622	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1623	pVCpu->hm.s.svm.fSyncVTpr = false;
1624	pVmcbNstGst->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1625
1626	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1627	}
1628	}
1629	#endif
1630
1631	/**
1632	* Loads the guest APIC state (currently just the TPR).
1633	*
1634	* @returns VBox status code.
1635	* @param pVCpu The cross context virtual CPU structure.
1636	* @param pVmcb Pointer to the VM control block.
1637	* @param pCtx Pointer to the guest-CPU context.
1638	*/
1639	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1640	{
1641	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1642	return VINF_SUCCESS;
1643
1644	int rc = VINF_SUCCESS;
1645	PVM pVM = pVCpu->CTX_SUFF(pVM);
1646	if ( PDMHasApic(pVM)
1647	&& APICIsEnabled(pVCpu))
1648	{
1649	bool fPendingIntr;
1650	uint8_t u8Tpr;
1651	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1652	AssertRCReturn(rc, rc);
1653
1654	/* Assume that we need to trap all TPR accesses and thus need not check on
1655	every #VMEXIT if we should update the TPR. */
1656	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1657	pVCpu->hm.s.svm.fSyncVTpr = false;
1658
1659	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1660	if (pVM->hm.s.fTPRPatchingActive)
1661	{
1662	pCtx->msrLSTAR = u8Tpr;
1663	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1664
1665	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1666	if (fPendingIntr)
1667	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1668	else
1669	{
1670	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1671	pVCpu->hm.s.svm.fSyncVTpr = true;
1672	}
1673	}
1674	else
1675	{
1676	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1677	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1678
1679	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1680	if (fPendingIntr)
1681	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1682	else
1683	{
1684	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1685	pVCpu->hm.s.svm.fSyncVTpr = true;
1686	}
1687
1688	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1689	}
1690	}
1691
1692	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1693	return rc;
1694	}
1695
1696
1697	/**
1698	* Loads the exception interrupts required for guest (or nested-guest) execution in
1699	* the VMCB.
1700	*
1701	* @param pVCpu The cross context virtual CPU structure.
1702	* @param pVmcb Pointer to the VM control block.
1703	*/
1704	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb)
1705	{
1706	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1707	{
1708	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1709	if (pVCpu->hm.s.fGIMTrapXcptUD)
1710	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1711	else
1712	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1713
1714	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1715	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1716	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1717	else
1718	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_BP);
1719
1720	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1721	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1722	}
1723	}
1724
1725
1726	#ifdef VBOX_WITH_NESTED_HWVIRT
1727	/**
1728	* Loads the intercepts required for nested-guest execution in the VMCB.
1729	*
1730	* This merges the guest and nested-guest intercepts in a way that if the outer
1731	* guest intercepts an exception we need to intercept it in the nested-guest as
1732	* well and handle it accordingly.
1733	*
1734	* @param pVCpu The cross context virtual CPU structure.
1735	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1736	*/
1737	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1738	{
1739	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1740	{
1741	/* First, load the guest intercepts into the guest VMCB. */
1742	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1743	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb);
1744
1745	/* Next, merge the intercepts into the nested-guest VMCB. */
1746	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1747	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1748
1749	/*
1750	* CR3, CR4 reads and writes are intercepted as we modify them before
1751	* hardware-assisted SVM execution. In addition, PGM needs to be up to date
1752	* on paging mode changes in the nested-guest.
1753	*
1754	* CR0 writes are intercepted in case of paging mode changes. CR0 reads are not
1755	* intercepted as we currently don't modify CR0 while executing the nested-guest.
1756	*/
1757	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(4) \| RT_BIT(3);
1758	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(4) \| RT_BIT(3) \| RT_BIT(0);
1759
1760	/** @todo Figure out debugging with nested-guests, till then just intercept
1761	* all DR[0-15] accesses. */
1762	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
1763	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
1764
1765	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
1766	pVmcbNstGst->ctrl.u64InterceptCtrl \|= pVmcb->ctrl.u64InterceptCtrl
1767	\| HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS;
1768	/*
1769	* Remove control intercepts that we don't need while executing the nested-guest.
1770	*
1771	* VMMCALL when not intercepted raises a \#UD exception in the guest. However,
1772	* other SVM instructions like VMSAVE when not intercept can cause havoc on the
1773	* host as they can write to any location in physical memory, hence they always
1774	* need to be intercepted (they are included in HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS).
1775	*/
1776	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
1777	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
1778	pVmcbNstGst->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VMMCALL;
1779
1780	/* Remove exception intercepts that we don't need while executing the nested-guest. */
1781	pVmcbNstGst->ctrl.u32InterceptXcpt &= ~RT_BIT(X86_XCPT_UD);
1782
1783	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
1784	}
1785	}
1786	#endif
1787
1788
1789	/**
1790	* Sets up the appropriate function to run guest code.
1791	*
1792	* @returns VBox status code.
1793	* @param pVCpu The cross context virtual CPU structure.
1794	*
1795	* @remarks No-long-jump zone!!!
1796	*/
1797	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
1798	{
1799	if (CPUMIsGuestInLongMode(pVCpu))
1800	{
1801	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1802	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1803	#endif
1804	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1805	#if HC_ARCH_BITS == 32
1806	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1807	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1808	#else
1809	/* 64-bit host or hybrid host. */
1810	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1811	#endif
1812	}
1813	else
1814	{
1815	/* Guest is not in long mode, use the 32-bit handler. */
1816	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1817	}
1818	return VINF_SUCCESS;
1819	}
1820
1821
1822	/**
1823	* Enters the AMD-V session.
1824	*
1825	* @returns VBox status code.
1826	* @param pVM The cross context VM structure.
1827	* @param pVCpu The cross context virtual CPU structure.
1828	* @param pCpu Pointer to the CPU info struct.
1829	*/
1830	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1831	{
1832	AssertPtr(pVM);
1833	AssertPtr(pVCpu);
1834	Assert(pVM->hm.s.svm.fSupported);
1835	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1836	NOREF(pVM); NOREF(pCpu);
1837
1838	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1839	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1840
1841	pVCpu->hm.s.fLeaveDone = false;
1842	return VINF_SUCCESS;
1843	}
1844
1845
1846	/**
1847	* Thread-context callback for AMD-V.
1848	*
1849	* @param enmEvent The thread-context event.
1850	* @param pVCpu The cross context virtual CPU structure.
1851	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1852	* @thread EMT(pVCpu)
1853	*/
1854	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1855	{
1856	NOREF(fGlobalInit);
1857
1858	switch (enmEvent)
1859	{
1860	case RTTHREADCTXEVENT_OUT:
1861	{
1862	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1863	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1864	VMCPU_ASSERT_EMT(pVCpu);
1865
1866	/* No longjmps (log-flush, locks) in this fragile context. */
1867	VMMRZCallRing3Disable(pVCpu);
1868
1869	if (!pVCpu->hm.s.fLeaveDone)
1870	{
1871	hmR0SvmLeave(pVCpu);
1872	pVCpu->hm.s.fLeaveDone = true;
1873	}
1874
1875	/* Leave HM context, takes care of local init (term). */
1876	int rc = HMR0LeaveCpu(pVCpu);
1877	AssertRC(rc); NOREF(rc);
1878
1879	/* Restore longjmp state. */
1880	VMMRZCallRing3Enable(pVCpu);
1881	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
1882	break;
1883	}
1884
1885	case RTTHREADCTXEVENT_IN:
1886	{
1887	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1888	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1889	VMCPU_ASSERT_EMT(pVCpu);
1890
1891	/* No longjmps (log-flush, locks) in this fragile context. */
1892	VMMRZCallRing3Disable(pVCpu);
1893
1894	/*
1895	* Initialize the bare minimum state required for HM. This takes care of
1896	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1897	*/
1898	int rc = HMR0EnterCpu(pVCpu);
1899	AssertRC(rc); NOREF(rc);
1900	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1901
1902	pVCpu->hm.s.fLeaveDone = false;
1903
1904	/* Restore longjmp state. */
1905	VMMRZCallRing3Enable(pVCpu);
1906	break;
1907	}
1908
1909	default:
1910	break;
1911	}
1912	}
1913
1914
1915	/**
1916	* Saves the host state.
1917	*
1918	* @returns VBox status code.
1919	* @param pVM The cross context VM structure.
1920	* @param pVCpu The cross context virtual CPU structure.
1921	*
1922	* @remarks No-long-jump zone!!!
1923	*/
1924	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1925	{
1926	NOREF(pVM);
1927	NOREF(pVCpu);
1928	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1929	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1930	return VINF_SUCCESS;
1931	}
1932
1933
1934	/**
1935	* Loads the guest state into the VMCB.
1936	*
1937	* The CPU state will be loaded from these fields on every successful VM-entry.
1938	* Also sets up the appropriate VMRUN function to execute guest code based on
1939	* the guest CPU mode.
1940	*
1941	* @returns VBox status code.
1942	* @param pVM The cross context VM structure.
1943	* @param pVCpu The cross context virtual CPU structure.
1944	* @param pCtx Pointer to the guest-CPU context.
1945	*
1946	* @remarks No-long-jump zone!!!
1947	*/
1948	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1949	{
1950	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1951	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1952
1953	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1954
1955	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1956	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1957
1958	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1959	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1960
1961	pVmcb->guest.u64RIP = pCtx->rip;
1962	pVmcb->guest.u64RSP = pCtx->rsp;
1963	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1964	pVmcb->guest.u64RAX = pCtx->rax;
1965
1966	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1967	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1968
1969	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb);
1970
1971	rc = hmR0SvmSetupVMRunHandler(pVCpu);
1972	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1973
1974	/* Clear any unused and reserved bits. */
1975	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1976	\| HM_CHANGED_GUEST_RSP
1977	\| HM_CHANGED_GUEST_RFLAGS
1978	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1979	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1980	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1981	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1982	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1983	\| HM_CHANGED_SVM_RESERVED2
1984	\| HM_CHANGED_SVM_RESERVED3
1985	\| HM_CHANGED_SVM_RESERVED4);
1986
1987	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1988	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1989	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1990	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1991
1992	Log4(("hmR0SvmLoadGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32\n", pCtx->cs.Sel, pCtx->rip,
1993	pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
1994	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1995	return rc;
1996	}
1997
1998
1999	#ifdef VBOX_WITH_NESTED_HWVIRT
2000	/**
2001	* Caches the nested-guest VMCB fields before we modify them for execution using
2002	* hardware-assisted SVM.
2003	*
2004	* @returns true if the VMCB was previously already cached, false otherwise.
2005	* @param pCtx Pointer to the guest-CPU context.
2006	*
2007	* @sa HMSvmNstGstVmExitNotify.
2008	*/
2009	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2010	{
2011	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2012	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2013	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2014	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2015
2016	/*
2017	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2018	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2019	*
2020	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2021	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2022	*/
2023	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2024	if (!fWasCached)
2025	{
2026	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2027	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2028	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2029	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2030	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2031	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2032	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2033	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2034	pNstGstVmcbCache->u64EFER = pVmcbNstGstState->u64EFER;
2035	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2036	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2037	pNstGstVmcbCache->u64VmcbCleanBits = pVmcbNstGstCtrl->u64VmcbCleanBits;
2038	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2039	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2040	pNstGstVmcbCache->NestedPagingCtrl = pVmcbNstGstCtrl->NestedPaging;
2041	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2042	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2043	}
2044
2045	return fWasCached;
2046	}
2047
2048
2049	/**
2050	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2051	*
2052	* @param pVCpu The cross context virtual CPU structure.
2053	* @param pCtx Pointer to the guest-CPU context.
2054	*/
2055	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2056	{
2057	RT_NOREF(pVCpu);
2058	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2059	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2060
2061	/*
2062	* First cache the nested-guest VMCB fields we may potentially modify.
2063	*/
2064	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2065	if (!fVmcbCached)
2066	{
2067	/*
2068	* The IOPM of the nested-guest can be ignored because the the guest always
2069	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2070	* into the nested-guest one and swap it back on the #VMEXIT.
2071	*/
2072	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2073
2074	/*
2075	* Load the host-physical address into the MSRPM rather than the nested-guest
2076	* physical address (currently we trap all MSRs in the nested-guest).
2077	*/
2078	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2079
2080	/*
2081	* Use the same nested-paging as the "outer" guest. We can't dynamically
2082	* switch off nested-paging suddenly while executing a VM (see assertion at the
2083	* end of Trap0eHandler in PGMAllBth.h).
2084	*/
2085	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2086	}
2087	else
2088	{
2089	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2090	Assert(pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap);
2091	Assert(pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2092	}
2093	}
2094
2095
2096	/**
2097	* Loads the nested-guest state into the VMCB.
2098	*
2099	* @returns VBox status code.
2100	* @param pVCpu The cross context virtual CPU structure.
2101	* @param pCtx Pointer to the guest-CPU context.
2102	*
2103	* @remarks No-long-jump zone!!!
2104	*/
2105	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2106	{
2107	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2108
2109	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2110	Assert(pVmcbNstGst);
2111
2112	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2113	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2114
2115	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2116	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2117	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2118	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2119
2120	int rc = hmR0SvmLoadGuestControlRegsNested(pVCpu, pVmcbNstGst, pCtx);
2121	AssertRCReturn(rc, rc);
2122
2123	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2124	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst);
2125
2126	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2127	AssertRCReturn(rc, rc);
2128
2129	/* Clear any unused and reserved bits. */
2130	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2131	\| HM_CHANGED_GUEST_RSP
2132	\| HM_CHANGED_GUEST_RFLAGS
2133	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2134	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2135	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2136	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2137	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2138	\| HM_CHANGED_SVM_RESERVED2
2139	\| HM_CHANGED_SVM_RESERVED3
2140	\| HM_CHANGED_SVM_RESERVED4);
2141
2142	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2143	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2144	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2145	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2146
2147	Log4(("hmR0SvmLoadGuestStateNested: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 (HyperCR3=%#RX64) CR4=%#RX32 rc=%d\n",
2148	pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pVmcbNstGst->guest.u64CR3, pCtx->cr4, rc));
2149	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2150	return rc;
2151	}
2152	#endif
2153
2154
2155	/**
2156	* Loads the state shared between the host and guest or nested-guest into the
2157	* VMCB.
2158	*
2159	* @param pVCpu The cross context virtual CPU structure.
2160	* @param pVmcb Pointer to the VM control block.
2161	* @param pCtx Pointer to the guest-CPU context.
2162	*
2163	* @remarks No-long-jump zone!!!
2164	*/
2165	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2166	{
2167	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2168	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2169
2170	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2171	{
2172	#ifdef VBOX_WITH_NESTED_HWVIRT
2173	/* We use nested-guest CR0 unmodified, hence nothing to do here. */
2174	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2175	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2176	else
2177	Assert(pVmcb->guest.u64CR0 == pCtx->cr0);
2178	#else
2179	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2180	#endif
2181	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2182	}
2183
2184	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2185	{
2186	/* We use nested-guest CR0 unmodified, hence nothing to do here. */
2187	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2188	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2189	else
2190	{
2191	pVmcb->guest.u64DR6 = pCtx->dr[6];
2192	pVmcb->guest.u64DR7 = pCtx->dr[7];
2193	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2194	}
2195
2196	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2197	}
2198
2199	/* Unused on AMD-V. */
2200	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2201
2202	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2203	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2204	}
2205
2206
2207	/**
2208	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU context.
2209	*
2210	* Currently there is no residual state left in the CPU that is not updated in the
2211	* VMCB.
2212	*
2213	* @returns VBox status code.
2214	* @param pVCpu The cross context virtual CPU structure.
2215	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2216	* out-of-sync. Make sure to update the required fields
2217	* before using them.
2218	* @param pVmcb Pointer to the VM control block.
2219	*/
2220	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2221	{
2222	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2223
2224	pMixedCtx->rip = pVmcb->guest.u64RIP;
2225	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2226	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2227	pMixedCtx->rax = pVmcb->guest.u64RAX;
2228
2229	/*
2230	* Guest interrupt shadow.
2231	*/
2232	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
2233	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2234	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2235	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2236
2237	/*
2238	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2239	*/
2240	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2241
2242	#ifdef VBOX_WITH_NESTED_GUEST
2243	/*
2244	* The nested hypervisor might not be intercepting these control registers,
2245	*/
2246	if (CPUMIsGuestInNestedHwVirtMode(pMixedCtx))
2247	{
2248	pMixedCtx->cr4 = pVmcb->guest.u64CR4;
2249	pMixedCtx->cr0 = pVmcb->guest.u64CR0;
2250	}
2251	#endif
2252
2253	/*
2254	* Guest MSRs.
2255	*/
2256	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2257	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2258	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2259	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2260	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2261	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2262	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2263	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2264
2265	/*
2266	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2267	*/
2268	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2269	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2270	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2271	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2272	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2273	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2274
2275	/*
2276	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2277	* register (yet).
2278	*/
2279	/** @todo SELM might need to be fixed as it too should not care about the
2280	* granularity bit. See @bugref{6785}. */
2281	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2282	&& pMixedCtx->cs.Attr.n.u1Present
2283	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2284	{
2285	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2286	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2287	}
2288
2289	#ifdef VBOX_STRICT
2290	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
2291	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
2292	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
2293	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
2294	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
2295	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
2296	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
2297
2298	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2299	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2300	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2301	HMSVM_ASSERT_SEG_GRANULARITY(es);
2302	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2303	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2304
2305	# undef HMSVM_ASSERT_SEL_GRANULARITY
2306	#endif
2307
2308	/*
2309	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2310	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2311	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2312	* See AMD spec. 15.5.1 "Basic operation".
2313	*/
2314	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2315	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2316
2317	/*
2318	* Guest TR.
2319	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2320	* between Intel and AMD. See @bugref{6208#c39}.
2321	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2322	*/
2323	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2324	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2325	{
2326	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2327	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2328	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2329	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2330	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2331	}
2332
2333	/*
2334	* Guest Descriptor-Table registers.
2335	*/
2336	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2337	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2338	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2339
2340	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2341	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2342
2343	/*
2344	* Guest Debug registers.
2345	*/
2346	if (!pVCpu->hm.s.fUsingHyperDR7)
2347	{
2348	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2349	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2350	}
2351	else
2352	{
2353	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2354	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2355	}
2356
2357	/*
2358	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2359	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2360	*/
2361	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2362	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2363	{
2364	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2365	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2366	}
2367	}
2368
2369
2370	/**
2371	* Does the necessary state syncing before returning to ring-3 for any reason
2372	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2373	*
2374	* @param pVCpu The cross context virtual CPU structure.
2375	*
2376	* @remarks No-long-jmp zone!!!
2377	*/
2378	static void hmR0SvmLeave(PVMCPU pVCpu)
2379	{
2380	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2381	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2382	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2383
2384	/*
2385	* !!! IMPORTANT !!!
2386	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2387	*/
2388
2389	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2390	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2391	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2392
2393	/*
2394	* Restore host debug registers if necessary and resync on next R0 reentry.
2395	*/
2396	#ifdef VBOX_STRICT
2397	if (CPUMIsHyperDebugStateActive(pVCpu))
2398	{
2399	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2400	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2401	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2402	}
2403	#endif
2404	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2405	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2406
2407	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2408	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2409
2410	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2411	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2412	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2413	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2414	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2415
2416	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2417	}
2418
2419
2420	/**
2421	* Leaves the AMD-V session.
2422	*
2423	* @returns VBox status code.
2424	* @param pVCpu The cross context virtual CPU structure.
2425	*/
2426	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2427	{
2428	HM_DISABLE_PREEMPT();
2429	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2430	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2431
2432	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2433	and done this from the SVMR0ThreadCtxCallback(). */
2434	if (!pVCpu->hm.s.fLeaveDone)
2435	{
2436	hmR0SvmLeave(pVCpu);
2437	pVCpu->hm.s.fLeaveDone = true;
2438	}
2439
2440	/*
2441	* !!! IMPORTANT !!!
2442	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2443	*/
2444
2445	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2446	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2447	VMMR0ThreadCtxHookDisable(pVCpu);
2448
2449	/* Leave HM context. This takes care of local init (term). */
2450	int rc = HMR0LeaveCpu(pVCpu);
2451
2452	HM_RESTORE_PREEMPT();
2453	return rc;
2454	}
2455
2456
2457	/**
2458	* Does the necessary state syncing before doing a longjmp to ring-3.
2459	*
2460	* @returns VBox status code.
2461	* @param pVCpu The cross context virtual CPU structure.
2462	*
2463	* @remarks No-long-jmp zone!!!
2464	*/
2465	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2466	{
2467	return hmR0SvmLeaveSession(pVCpu);
2468	}
2469
2470
2471	/**
2472	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2473	* any remaining host state) before we longjump to ring-3 and possibly get
2474	* preempted.
2475	*
2476	* @param pVCpu The cross context virtual CPU structure.
2477	* @param enmOperation The operation causing the ring-3 longjump.
2478	* @param pvUser The user argument (pointer to the possibly
2479	* out-of-date guest-CPU context).
2480	*/
2481	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2482	{
2483	RT_NOREF_PV(pvUser);
2484
2485	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2486	{
2487	/*
2488	* !!! IMPORTANT !!!
2489	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2490	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2491	*/
2492	VMMRZCallRing3RemoveNotification(pVCpu);
2493	VMMRZCallRing3Disable(pVCpu);
2494	HM_DISABLE_PREEMPT();
2495
2496	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2497	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2498
2499	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2500	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2501
2502	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2503	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2504	VMMR0ThreadCtxHookDisable(pVCpu);
2505
2506	/* Leave HM context. This takes care of local init (term). */
2507	HMR0LeaveCpu(pVCpu);
2508
2509	HM_RESTORE_PREEMPT();
2510	return VINF_SUCCESS;
2511	}
2512
2513	Assert(pVCpu);
2514	Assert(pvUser);
2515	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2516	HMSVM_ASSERT_PREEMPT_SAFE();
2517
2518	VMMRZCallRing3Disable(pVCpu);
2519	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2520
2521	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2522	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2523	AssertRCReturn(rc, rc);
2524
2525	VMMRZCallRing3Enable(pVCpu);
2526	return VINF_SUCCESS;
2527	}
2528
2529
2530	/**
2531	* Take necessary actions before going back to ring-3.
2532	*
2533	* An action requires us to go back to ring-3. This function does the necessary
2534	* steps before we can safely return to ring-3. This is not the same as longjmps
2535	* to ring-3, this is voluntary.
2536	*
2537	* @returns VBox status code.
2538	* @param pVM The cross context VM structure.
2539	* @param pVCpu The cross context virtual CPU structure.
2540	* @param pCtx Pointer to the guest-CPU context.
2541	* @param rcExit The reason for exiting to ring-3. Can be
2542	* VINF_VMM_UNKNOWN_RING3_CALL.
2543	*/
2544	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2545	{
2546	Assert(pVM);
2547	Assert(pVCpu);
2548	Assert(pCtx);
2549	HMSVM_ASSERT_PREEMPT_SAFE();
2550
2551	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2552	VMMRZCallRing3Disable(pVCpu);
2553	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
2554	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
2555
2556	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2557	if (pVCpu->hm.s.Event.fPending)
2558	{
2559	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2560	Assert(!pVCpu->hm.s.Event.fPending);
2561	}
2562
2563	/* Sync. the necessary state for going back to ring-3. */
2564	hmR0SvmLeaveSession(pVCpu);
2565	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2566
2567	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2568	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2569	\| CPUM_CHANGED_LDTR
2570	\| CPUM_CHANGED_GDTR
2571	\| CPUM_CHANGED_IDTR
2572	\| CPUM_CHANGED_TR
2573	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2574	if ( pVM->hm.s.fNestedPaging
2575	&& CPUMIsGuestPagingEnabledEx(pCtx))
2576	{
2577	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2578	}
2579
2580	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2581	if (rcExit != VINF_EM_RAW_INTERRUPT)
2582	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2583
2584	#ifdef VBOX_WITH_NESTED_HWVIRT
2585	/*
2586	* We may inspect the nested-guest VMCB state in ring-3 (e.g. for injecting interrupts)
2587	* and thus we need to restore any modifications we may have made to it here if we're
2588	* still executing the nested-guest.
2589	*/
2590	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2591	HMSvmNstGstVmExitNotify(pVCpu, pCtx);
2592	#endif
2593
2594	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2595
2596	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2597	VMMRZCallRing3RemoveNotification(pVCpu);
2598	VMMRZCallRing3Enable(pVCpu);
2599
2600	/*
2601	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2602	* and if we're injecting an event we should have a TRPM trap pending.
2603	*/
2604	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2605	pVCpu->hm.s.u32HMError = rcExit,
2606	VERR_SVM_IPE_5);
2607	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2608	pVCpu->hm.s.u32HMError = rcExit,
2609	VERR_SVM_IPE_4);
2610
2611	return rcExit;
2612	}
2613
2614
2615	/**
2616	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2617	* intercepts.
2618	*
2619	* @param pVM The cross context VM structure.
2620	* @param pVCpu The cross context virtual CPU structure.
2621	* @param pVmcb Pointer to the VM control block.
2622	*
2623	* @remarks No-long-jump zone!!!
2624	*/
2625	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2626	{
2627	bool fParavirtTsc;
2628	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2629	if (fCanUseRealTsc)
2630	{
2631	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2632	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2633	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2634	}
2635	else
2636	{
2637	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2638	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2639	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2640	}
2641	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2642
2643	/** @todo later optimize this to be done elsewhere and not before every
2644	* VM-entry. */
2645	if (fParavirtTsc)
2646	{
2647	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2648	information before every VM-entry, hence disable it for performance sake. */
2649	#if 0
2650	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2651	AssertRC(rc);
2652	#endif
2653	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2654	}
2655	}
2656
2657
2658	/**
2659	* Sets an event as a pending event to be injected into the guest.
2660	*
2661	* @param pVCpu The cross context virtual CPU structure.
2662	* @param pEvent Pointer to the SVM event.
2663	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2664	* page-fault.
2665	*
2666	* @remarks Statistics counter assumes this is a guest event being reflected to
2667	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2668	*/
2669	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2670	{
2671	Assert(!pVCpu->hm.s.Event.fPending);
2672	Assert(pEvent->n.u1Valid);
2673
2674	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2675	pVCpu->hm.s.Event.fPending = true;
2676	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2677
2678	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2679	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2680	}
2681
2682
2683	/**
2684	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
2685	*
2686	* @param pVCpu The cross context virtual CPU structure.
2687	*/
2688	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
2689	{
2690	SVMEVENT Event;
2691	Event.u = 0;
2692	Event.n.u1Valid = 1;
2693	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2694	Event.n.u8Vector = X86_XCPT_UD;
2695	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2696	}
2697
2698
2699	/**
2700	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
2701	*
2702	* @param pVCpu The cross context virtual CPU structure.
2703	*/
2704	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
2705	{
2706	SVMEVENT Event;
2707	Event.u = 0;
2708	Event.n.u1Valid = 1;
2709	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2710	Event.n.u8Vector = X86_XCPT_DB;
2711	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2712	}
2713
2714
2715	/**
2716	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
2717	*
2718	* @param pVCpu The cross context virtual CPU structure.
2719	* @param pCtx Pointer to the guest-CPU context.
2720	* @param u32ErrCode The error-code for the page-fault.
2721	* @param uFaultAddress The page fault address (CR2).
2722	*
2723	* @remarks This updates the guest CR2 with @a uFaultAddress!
2724	*/
2725	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
2726	{
2727	SVMEVENT Event;
2728	Event.u = 0;
2729	Event.n.u1Valid = 1;
2730	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2731	Event.n.u8Vector = X86_XCPT_PF;
2732	Event.n.u1ErrorCodeValid = 1;
2733	Event.n.u32ErrorCode = u32ErrCode;
2734
2735	/* Update CR2 of the guest. */
2736	if (pCtx->cr2 != uFaultAddress)
2737	{
2738	pCtx->cr2 = uFaultAddress;
2739	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
2740	}
2741
2742	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
2743	}
2744
2745
2746	/**
2747	* Sets a device-not-available (\#NM) exception as pending-for-injection into
2748	* the VM.
2749	*
2750	* @param pVCpu The cross context virtual CPU structure.
2751	*/
2752	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
2753	{
2754	SVMEVENT Event;
2755	Event.u = 0;
2756	Event.n.u1Valid = 1;
2757	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2758	Event.n.u8Vector = X86_XCPT_NM;
2759	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2760	}
2761
2762
2763	/**
2764	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
2765	*
2766	* @param pVCpu The cross context virtual CPU structure.
2767	*/
2768	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
2769	{
2770	SVMEVENT Event;
2771	Event.u = 0;
2772	Event.n.u1Valid = 1;
2773	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2774	Event.n.u8Vector = X86_XCPT_MF;
2775	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2776	}
2777
2778
2779	/**
2780	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
2781	*
2782	* @param pVCpu The cross context virtual CPU structure.
2783	*/
2784	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
2785	{
2786	SVMEVENT Event;
2787	Event.u = 0;
2788	Event.n.u1Valid = 1;
2789	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2790	Event.n.u8Vector = X86_XCPT_DF;
2791	Event.n.u1ErrorCodeValid = 1;
2792	Event.n.u32ErrorCode = 0;
2793	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2794	}
2795
2796
2797	/**
2798	* Injects an event into the guest upon VMRUN by updating the relevant field
2799	* in the VMCB.
2800	*
2801	* @param pVCpu The cross context virtual CPU structure.
2802	* @param pVmcb Pointer to the guest VM control block.
2803	* @param pCtx Pointer to the guest-CPU context.
2804	* @param pEvent Pointer to the event.
2805	*
2806	* @remarks No-long-jump zone!!!
2807	* @remarks Requires CR0!
2808	*/
2809	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2810	{
2811	NOREF(pVCpu); NOREF(pCtx);
2812
2813	pVmcb->ctrl.EventInject.u = pEvent->u;
2814	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2815
2816	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2817	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2818	}
2819
2820
2821
2822	/**
2823	* Converts any TRPM trap into a pending HM event. This is typically used when
2824	* entering from ring-3 (not longjmp returns).
2825	*
2826	* @param pVCpu The cross context virtual CPU structure.
2827	*/
2828	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2829	{
2830	Assert(TRPMHasTrap(pVCpu));
2831	Assert(!pVCpu->hm.s.Event.fPending);
2832
2833	uint8_t uVector;
2834	TRPMEVENT enmTrpmEvent;
2835	RTGCUINT uErrCode;
2836	RTGCUINTPTR GCPtrFaultAddress;
2837	uint8_t cbInstr;
2838
2839	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2840	AssertRC(rc);
2841
2842	SVMEVENT Event;
2843	Event.u = 0;
2844	Event.n.u1Valid = 1;
2845	Event.n.u8Vector = uVector;
2846
2847	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2848	if (enmTrpmEvent == TRPM_TRAP)
2849	{
2850	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2851	switch (uVector)
2852	{
2853	case X86_XCPT_NMI:
2854	{
2855	Event.n.u3Type = SVM_EVENT_NMI;
2856	break;
2857	}
2858
2859	case X86_XCPT_PF:
2860	case X86_XCPT_DF:
2861	case X86_XCPT_TS:
2862	case X86_XCPT_NP:
2863	case X86_XCPT_SS:
2864	case X86_XCPT_GP:
2865	case X86_XCPT_AC:
2866	{
2867	Event.n.u1ErrorCodeValid = 1;
2868	Event.n.u32ErrorCode = uErrCode;
2869	break;
2870	}
2871	}
2872	}
2873	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2874	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2875	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2876	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2877	else
2878	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2879
2880	rc = TRPMResetTrap(pVCpu);
2881	AssertRC(rc);
2882
2883	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2884	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2885
2886	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2887	}
2888
2889
2890	/**
2891	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2892	* AMD-V to execute any instruction.
2893	*
2894	* @param pVCpu The cross context virtual CPU structure.
2895	*/
2896	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2897	{
2898	Assert(pVCpu->hm.s.Event.fPending);
2899	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2900
2901	SVMEVENT Event;
2902	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2903
2904	uint8_t uVector = Event.n.u8Vector;
2905	uint8_t uVectorType = Event.n.u3Type;
2906	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
2907
2908	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2909
2910	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2911	AssertRC(rc);
2912
2913	if (Event.n.u1ErrorCodeValid)
2914	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2915
2916	if ( uVectorType == SVM_EVENT_EXCEPTION
2917	&& uVector == X86_XCPT_PF)
2918	{
2919	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2920	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2921	}
2922	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2923	{
2924	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2925	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2926	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2927	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2928	}
2929	pVCpu->hm.s.Event.fPending = false;
2930	}
2931
2932
2933	/**
2934	* Checks if the guest (or nested-guest) has an interrupt shadow active right
2935	* now.
2936	*
2937	* @returns true if the interrupt shadow is active, false otherwise.
2938	* @param pVCpu The cross context virtual CPU structure.
2939	* @param pCtx Pointer to the guest-CPU context.
2940	*
2941	* @remarks No-long-jump zone!!!
2942	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2943	*/
2944	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
2945	{
2946	/*
2947	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2948	* inhibit interrupts or clear any existing interrupt-inhibition.
2949	*/
2950	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2951	{
2952	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2953	{
2954	/*
2955	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2956	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2957	*/
2958	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2959	return false;
2960	}
2961	return true;
2962	}
2963	return false;
2964	}
2965
2966
2967	/**
2968	* Sets the virtual interrupt intercept control in the VMCB which
2969	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
2970	* receive interrupts.
2971	*
2972	* @param pVmcb Pointer to the VM control block.
2973	*/
2974	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2975	{
2976	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
2977	{
2978	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1; /* A virtual interrupt is pending. */
2979	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0; /* Vector not necessary as we #VMEXIT for delivering the interrupt. */
2980	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
2981	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2982
2983	Log4(("Setting VINTR intercept\n"));
2984	}
2985	}
2986
2987
2988	#if 0
2989	/**
2990	* Clears the virtual interrupt intercept control in the VMCB as
2991	* we are figured the guest is unable process any interrupts
2992	* at this point of time.
2993	*
2994	* @param pVmcb Pointer to the VM control block.
2995	*/
2996	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
2997	{
2998	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
2999	{
3000	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3001	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3002	Log4(("Clearing VINTR intercept\n"));
3003	}
3004	}
3005	#endif
3006
3007
3008	/**
3009	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3010	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3011	* virtual NMIs.
3012	*
3013	* @param pVmcb Pointer to the VM control block.
3014	*/
3015	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3016	{
3017	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3018	{
3019	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3020	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3021
3022	Log4(("Setting IRET intercept\n"));
3023	}
3024	}
3025
3026
3027	/**
3028	* Clears the IRET intercept control in the VMCB.
3029	*
3030	* @param pVmcb Pointer to the VM control block.
3031	*/
3032	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3033	{
3034	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3035	{
3036	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3037	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3038
3039	Log4(("Clearing IRET intercept\n"));
3040	}
3041	}
3042
3043	#ifdef VBOX_WITH_NESTED_HWVIRT
3044	/**
3045	* Checks whether the SVM nested-guest is in a state to receive physical (APIC)
3046	* interrupts.
3047	*
3048	* @returns true if it's ready, false otherwise.
3049	* @param pCtx The guest-CPU context.
3050	*
3051	* @remarks This function looks at the VMCB cache rather than directly at the
3052	* nested-guest VMCB which may have been suitably modified for executing
3053	* using hardware-assisted SVM.
3054	*/
3055	static bool hmR0SvmCanNstGstTakePhysIntr(PVMCPU pVCpu, PCCPUMCTX pCtx)
3056	{
3057	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
3058	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3059	X86EFLAGS fEFlags;
3060	if (pVmcbNstGstCache->fVIntrMasking)
3061	fEFlags.u = pCtx->hwvirt.svm.HostState.rflags.u;
3062	else
3063	fEFlags.u = pCtx->eflags.u;
3064
3065	return fEFlags.Bits.u1IF;
3066	}
3067
3068
3069	/**
3070	* Evaluates the event to be delivered to the nested-guest and sets it as the
3071	* pending event.
3072	*
3073	* @returns VBox strict status code.
3074	* @param pVCpu The cross context virtual CPU structure.
3075	* @param pCtx Pointer to the guest-CPU context.
3076	*/
3077	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3078	{
3079	Log4Func(("\n"));
3080
3081	Assert(!pVCpu->hm.s.Event.fPending);
3082
3083	bool const fGif = pCtx->hwvirt.svm.fGif;
3084	if (fGif)
3085	{
3086	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3087
3088	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3089
3090	/*
3091	* Check if the nested-guest can receive NMIs.
3092	* NMIs are higher priority than regular interrupts.
3093	*/
3094	/** @todo SMI. SMIs take priority over NMIs. */
3095	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3096	{
3097	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3098	if (fBlockNmi)
3099	hmR0SvmSetIretIntercept(pVmcbNstGst);
3100	else if (fIntShadow)
3101	{
3102	/** @todo Figure this out, how we shall manage virt. intercept if the
3103	* nested-guest already has one set and/or if we really need it? */
3104	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3105	}
3106	else
3107	{
3108	Log4(("Pending NMI\n"));
3109
3110	SVMEVENT Event;
3111	Event.u = 0;
3112	Event.n.u1Valid = 1;
3113	Event.n.u8Vector = X86_XCPT_NMI;
3114	Event.n.u3Type = SVM_EVENT_NMI;
3115
3116	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3117	hmR0SvmSetIretIntercept(pVmcbNstGst);
3118	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3119	return VINF_SUCCESS;
3120	}
3121	}
3122
3123	/*
3124	* Check if the nested-guest can receive external interrupts (generated by
3125	* the guest's PIC/APIC).
3126	*
3127	* External intercepts from the physical CPU are -always- intercepted when
3128	* executing using hardware-assisted SVM, see HMSVM_MANDATORY_NESTED_GUEST_CTRL_INTERCEPTS.
3129	*
3130	* External interrupts that are generated for the outer guest may be intercepted
3131	* depending on how the nested-guest VMCB was programmed by guest software.
3132	*
3133	* Physical interrupts always take priority over virtual interrupts,
3134	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3135	*/
3136	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3137	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
3138	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3139	&& !fIntShadow
3140	&& !pVCpu->hm.s.fSingleInstruction
3141	&& hmR0SvmCanNstGstTakePhysIntr(pVCpu, pCtx))
3142	{
3143	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR)
3144	{
3145	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3146	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3147	}
3148
3149	uint8_t u8Interrupt;
3150	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3151	if (RT_SUCCESS(rc))
3152	{
3153	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3154
3155	SVMEVENT Event;
3156	Event.u = 0;
3157	Event.n.u1Valid = 1;
3158	Event.n.u8Vector = u8Interrupt;
3159	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3160
3161	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3162	}
3163	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3164	{
3165	/*
3166	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3167	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3168	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3169	*/
3170	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3171	}
3172	else
3173	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3174	}
3175
3176	/*
3177	* Check if the nested-guest can receive virtual (injected by VMRUN) interrupts.
3178	* We can safely call CPUMCanSvmNstGstTakeVirtIntr here as we don't cache/modify any
3179	* nested-guest VMCB interrupt control fields besides V_INTR_MASKING, see hmR0SvmVmRunCacheVmcb.
3180	*/
3181	if ( (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3182	&& VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3183	&& CPUMCanSvmNstGstTakeVirtIntr(pCtx))
3184	{
3185	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3186	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3187	}
3188	}
3189
3190	return VINF_SUCCESS;
3191	}
3192	#endif
3193
3194	/**
3195	* Evaluates the event to be delivered to the guest and sets it as the pending
3196	* event.
3197	*
3198	* @param pVCpu The cross context virtual CPU structure.
3199	* @param pCtx Pointer to the guest-CPU context.
3200	*/
3201	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3202	{
3203	Assert(!pVCpu->hm.s.Event.fPending);
3204
3205	#ifdef VBOX_WITH_NESTED_HWVIRT
3206	bool const fGif = pCtx->hwvirt.svm.fGif;
3207	#else
3208	bool const fGif = true;
3209	#endif
3210	Log4Func(("fGif=%RTbool\n", fGif));
3211
3212	/*
3213	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3214	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3215	*/
3216	if (fGif)
3217	{
3218	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3219	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3220	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3221	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3222
3223	Log4Func(("fGif=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fGif, fBlockInt, fIntShadow,
3224	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3225
3226	/** @todo SMI. SMIs take priority over NMIs. */
3227	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3228	{
3229	if (fBlockNmi)
3230	hmR0SvmSetIretIntercept(pVmcb);
3231	else if (fIntShadow)
3232	hmR0SvmSetVirtIntrIntercept(pVmcb);
3233	else
3234	{
3235	Log4(("Pending NMI\n"));
3236
3237	SVMEVENT Event;
3238	Event.u = 0;
3239	Event.n.u1Valid = 1;
3240	Event.n.u8Vector = X86_XCPT_NMI;
3241	Event.n.u3Type = SVM_EVENT_NMI;
3242
3243	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3244	hmR0SvmSetIretIntercept(pVmcb);
3245	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3246	return;
3247	}
3248	}
3249	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3250	&& !pVCpu->hm.s.fSingleInstruction)
3251	{
3252	/*
3253	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3254	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3255	*/
3256	if ( !fBlockInt
3257	&& !fIntShadow)
3258	{
3259	uint8_t u8Interrupt;
3260	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3261	if (RT_SUCCESS(rc))
3262	{
3263	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3264
3265	SVMEVENT Event;
3266	Event.u = 0;
3267	Event.n.u1Valid = 1;
3268	Event.n.u8Vector = u8Interrupt;
3269	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3270
3271	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3272	}
3273	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3274	{
3275	/*
3276	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
3277	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
3278	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
3279	*/
3280	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3281	}
3282	else
3283	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3284	}
3285	else
3286	hmR0SvmSetVirtIntrIntercept(pVmcb);
3287	}
3288	}
3289	}
3290
3291
3292	/**
3293	* Injects any pending events into the guest or nested-guest.
3294	*
3295	* @param pVCpu The cross context virtual CPU structure.
3296	* @param pCtx Pointer to the guest-CPU context.
3297	* @param pVmcb Pointer to the VM control block.
3298	*/
3299	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3300	{
3301	Assert(!TRPMHasTrap(pVCpu));
3302	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3303
3304	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3305
3306	/*
3307	* When executing the nested-guest, we avoid assertions on whether the
3308	* event injection is valid purely based on EFLAGS, as V_INTR_MASKING
3309	* affects the interpretation of interruptibility (see CPUMCanSvmNstGstTakePhysIntr).
3310	*/
3311	#ifndef VBOX_WITH_NESTED_HWVIRT
3312	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3313	#endif
3314
3315	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
3316	{
3317	SVMEVENT Event;
3318	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3319	Assert(Event.n.u1Valid);
3320
3321	#ifndef VBOX_WITH_NESTED_HWVIRT
3322	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3323	{
3324	Assert(!fBlockInt);
3325	Assert(!fIntShadow);
3326	}
3327	else if (Event.n.u3Type == SVM_EVENT_NMI)
3328	Assert(!fIntShadow);
3329	NOREF(fBlockInt);
3330	#else
3331	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3332	#endif
3333
3334	Log4(("Injecting pending HM event\n"));
3335	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3336	pVCpu->hm.s.Event.fPending = false;
3337
3338	#ifdef VBOX_WITH_STATISTICS
3339	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3340	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3341	else
3342	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3343	#endif
3344	}
3345
3346	/*
3347	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3348	*
3349	* For nested-guests: We need to update it too for the scenario where IEM executes
3350	* the nested-guest but execution later continues here with an interrupt shadow active.
3351	*/
3352	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
3353	}
3354
3355
3356	/**
3357	* Reports world-switch error and dumps some useful debug info.
3358	*
3359	* @param pVM The cross context VM structure.
3360	* @param pVCpu The cross context virtual CPU structure.
3361	* @param rcVMRun The return code from VMRUN (or
3362	* VERR_SVM_INVALID_GUEST_STATE for invalid
3363	* guest-state).
3364	* @param pCtx Pointer to the guest-CPU context.
3365	*/
3366	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3367	{
3368	NOREF(pCtx);
3369	HMSVM_ASSERT_PREEMPT_SAFE();
3370	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3371
3372	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3373	{
3374	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3375	#ifdef VBOX_STRICT
3376	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
3377	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3378	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3379	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3380	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3381	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3382	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3383	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3384	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3385	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3386
3387	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3388	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3389	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3390
3391	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3392	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3393	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
3394	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3395	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3396	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3397	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3398	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3399	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3400	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3401
3402	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
3403	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3404	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3405	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3406	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3407	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3408	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3409	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3410	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3411	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3412	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
3413	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3414	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3415	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3416	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3417	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3418	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3419
3420	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3421	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
3422
3423	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3424	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3425	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3426	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3427	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3428	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3429	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3430	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3431	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3432	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3433	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3434	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3435	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3436	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3437	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3438	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3439	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3440	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3441	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3442	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3443
3444	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3445	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3446
3447	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3448	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3449	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3450	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3451
3452	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3453	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3454
3455	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3456	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3457	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3458	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3459
3460	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3461	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3462	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3463	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3464	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3465	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3466	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3467
3468	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3469	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3470	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3471	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3472
3473	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3474	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3475	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3476
3477	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3478	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3479	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3480	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3481	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3482	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3483	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3484	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3485	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3486	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3487	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3488	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3489	#endif /* VBOX_STRICT */
3490	}
3491	else
3492	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3493
3494	NOREF(pVmcb);
3495	}
3496
3497
3498	/**
3499	* Check per-VM and per-VCPU force flag actions that require us to go back to
3500	* ring-3 for one reason or another.
3501	*
3502	* @returns VBox status code (information status code included).
3503	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3504	* ring-3.
3505	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3506	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3507	* interrupts)
3508	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3509	* all EMTs to be in ring-3.
3510	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3511	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3512	* to the EM loop.
3513	*
3514	* @param pVM The cross context VM structure.
3515	* @param pVCpu The cross context virtual CPU structure.
3516	* @param pCtx Pointer to the guest-CPU context.
3517	*/
3518	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3519	{
3520	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3521
3522	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3523	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3524	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3525
3526	/* Update pending interrupts into the APIC's IRR. */
3527	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3528	APICUpdatePendingInterrupts(pVCpu);
3529
3530	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3531	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3532	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3533	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3534	{
3535	/* Pending PGM C3 sync. */
3536	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3537	{
3538	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3539	if (rc != VINF_SUCCESS)
3540	{
3541	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3542	return rc;
3543	}
3544	}
3545
3546	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3547	/* -XXX- what was that about single stepping? */
3548	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3549	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3550	{
3551	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3552	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3553	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3554	return rc;
3555	}
3556
3557	/* Pending VM request packets, such as hardware interrupts. */
3558	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3559	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3560	{
3561	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3562	return VINF_EM_PENDING_REQUEST;
3563	}
3564
3565	/* Pending PGM pool flushes. */
3566	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3567	{
3568	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3569	return VINF_PGM_POOL_FLUSH_PENDING;
3570	}
3571
3572	/* Pending DMA requests. */
3573	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3574	{
3575	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3576	return VINF_EM_RAW_TO_R3;
3577	}
3578	}
3579
3580	return VINF_SUCCESS;
3581	}
3582
3583
3584	#ifdef VBOX_WITH_NESTED_HWVIRT
3585	/**
3586	* Does the preparations before executing nested-guest code in AMD-V.
3587	*
3588	* @returns VBox status code (informational status codes included).
3589	* @retval VINF_SUCCESS if we can proceed with running the guest.
3590	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3591	*
3592	* @param pVM The cross context VM structure.
3593	* @param pVCpu The cross context virtual CPU structure.
3594	* @param pCtx Pointer to the guest-CPU context.
3595	* @param pSvmTransient Pointer to the SVM transient structure.
3596	*
3597	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3598	* @sa hmR0SvmPreRunGuest.
3599	*/
3600	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3601	{
3602	HMSVM_ASSERT_PREEMPT_SAFE();
3603
3604	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3605	{
3606	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3607	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3608	return VINF_EM_RESCHEDULE_REM;
3609	#endif
3610	}
3611	else
3612	return VINF_SVM_VMEXIT;
3613
3614	/* Check force flag actions that might require us to go back to ring-3. */
3615	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3616	if (rc != VINF_SUCCESS)
3617	return rc;
3618
3619	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
3620
3621	if (TRPMHasTrap(pVCpu))
3622	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3623	else if (!pVCpu->hm.s.Event.fPending)
3624	{
3625	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3626	if (rcStrict != VINF_SUCCESS)
3627	return VBOXSTRICTRC_VAL(rcStrict);
3628	}
3629
3630	/*
3631	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3632	* Just do it in software, see @bugref{8411}.
3633	* NB: If we could continue a task switch exit we wouldn't need to do this.
3634	*/
3635	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3636	&& pVCpu->hm.s.Event.fPending
3637	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
3638	{
3639	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3640	}
3641
3642	/*
3643	* Load the nested-guest state.
3644	*/
3645	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
3646	AssertRCReturn(rc, rc);
3647	/** @todo Get new STAM counter for this? */
3648	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3649
3650	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
3651
3652	/*
3653	* No longjmps to ring-3 from this point on!!!
3654	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3655	* This also disables flushing of the R0-logger instance (if any).
3656	*/
3657	VMMRZCallRing3Disable(pVCpu);
3658
3659	/*
3660	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3661	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3662	*
3663	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3664	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3665	*
3666	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3667	* executing guest code.
3668	*/
3669	pSvmTransient->fEFlags = ASMIntDisableFlags();
3670	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3671	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3672	{
3673	ASMSetFlags(pSvmTransient->fEFlags);
3674	VMMRZCallRing3Enable(pVCpu);
3675	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3676	return VINF_EM_RAW_TO_R3;
3677	}
3678	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3679	{
3680	ASMSetFlags(pSvmTransient->fEFlags);
3681	VMMRZCallRing3Enable(pVCpu);
3682	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3683	return VINF_EM_RAW_INTERRUPT;
3684	}
3685
3686	/*
3687	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3688	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3689	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3690	*
3691	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3692	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3693	*/
3694	if (pVCpu->hm.s.Event.fPending)
3695	{
3696	SVMEVENT Event;
3697	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3698	if ( Event.n.u1Valid
3699	&& Event.n.u3Type == SVM_EVENT_NMI
3700	&& Event.n.u8Vector == X86_XCPT_NMI
3701	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3702	{
3703	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3704	}
3705	}
3706
3707	return VINF_SUCCESS;
3708	}
3709	#endif
3710
3711
3712	/**
3713	* Does the preparations before executing guest code in AMD-V.
3714	*
3715	* This may cause longjmps to ring-3 and may even result in rescheduling to the
3716	* recompiler. We must be cautious what we do here regarding committing
3717	* guest-state information into the VMCB assuming we assuredly execute the guest
3718	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
3719	* clearing the common-state (TRPM/forceflags), we must undo those changes so
3720	* that the recompiler can (and should) use them when it resumes guest
3721	* execution. Otherwise such operations must be done when we can no longer
3722	* exit to ring-3.
3723	*
3724	* @returns VBox status code (informational status codes included).
3725	* @retval VINF_SUCCESS if we can proceed with running the guest.
3726	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3727	*
3728	* @param pVM The cross context VM structure.
3729	* @param pVCpu The cross context virtual CPU structure.
3730	* @param pCtx Pointer to the guest-CPU context.
3731	* @param pSvmTransient Pointer to the SVM transient structure.
3732	*/
3733	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3734	{
3735	HMSVM_ASSERT_PREEMPT_SAFE();
3736	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
3737
3738	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3739	/* IEM only for executing nested guest, we shouldn't get here. */
3740	/** @todo Make this into an assertion since HMR3CanExecuteGuest already checks
3741	* for it? */
3742	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3743	{
3744	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3745	return VINF_EM_RESCHEDULE_REM;
3746	}
3747	#endif
3748
3749	/* Check force flag actions that might require us to go back to ring-3. */
3750	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3751	if (rc != VINF_SUCCESS)
3752	return rc;
3753
3754	if (TRPMHasTrap(pVCpu))
3755	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3756	else if (!pVCpu->hm.s.Event.fPending)
3757	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
3758
3759	/*
3760	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3761	* Just do it in software, see @bugref{8411}.
3762	* NB: If we could continue a task switch exit we wouldn't need to do this.
3763	*/
3764	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
3765	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
3766	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3767
3768	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
3769	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3770	#endif
3771
3772	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3773	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3774	AssertRCReturn(rc, rc);
3775	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3776
3777	/*
3778	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3779	* so we can update it on the way back if the guest changed the TPR.
3780	*/
3781	if (pVCpu->hm.s.svm.fSyncVTpr)
3782	{
3783	if (pVM->hm.s.fTPRPatchingActive)
3784	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3785	else
3786	{
3787	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3788	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3789	}
3790	}
3791
3792	/*
3793	* No longjmps to ring-3 from this point on!!!
3794	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3795	* This also disables flushing of the R0-logger instance (if any).
3796	*/
3797	VMMRZCallRing3Disable(pVCpu);
3798
3799	/*
3800	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3801	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3802	*
3803	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3804	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3805	*
3806	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3807	* executing guest code.
3808	*/
3809	pSvmTransient->fEFlags = ASMIntDisableFlags();
3810	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3811	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3812	{
3813	ASMSetFlags(pSvmTransient->fEFlags);
3814	VMMRZCallRing3Enable(pVCpu);
3815	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3816	return VINF_EM_RAW_TO_R3;
3817	}
3818	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3819	{
3820	ASMSetFlags(pSvmTransient->fEFlags);
3821	VMMRZCallRing3Enable(pVCpu);
3822	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3823	return VINF_EM_RAW_INTERRUPT;
3824	}
3825
3826	/*
3827	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3828	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3829	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3830	*
3831	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3832	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3833	*/
3834	if (pVCpu->hm.s.Event.fPending)
3835	{
3836	SVMEVENT Event;
3837	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3838	if ( Event.n.u1Valid
3839	&& Event.n.u3Type == SVM_EVENT_NMI
3840	&& Event.n.u8Vector == X86_XCPT_NMI
3841	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3842	{
3843	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3844	}
3845	}
3846
3847	return VINF_SUCCESS;
3848	}
3849
3850
3851	#ifdef VBOX_WITH_NESTED_HWVIRT
3852	/**
3853	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
3854	* means there is no backing out to ring-3 or anywhere else at this point.
3855	*
3856	* @param pVM The cross context VM structure.
3857	* @param pVCpu The cross context virtual CPU structure.
3858	* @param pCtx Pointer to the guest-CPU context.
3859	* @param pSvmTransient Pointer to the SVM transient structure.
3860	*
3861	* @remarks Called with preemption disabled.
3862	* @remarks No-long-jump zone!!!
3863	*/
3864	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3865	{
3866	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3867	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3868	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3869
3870	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3871	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3872
3873	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3874	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
3875
3876	if ( pVCpu->hm.s.fPreloadGuestFpu
3877	&& !CPUMIsGuestFPUStateActive(pVCpu))
3878	{
3879	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3880	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3881	}
3882
3883	/* Load the state shared between host and nested-guest (FPU, debug). */
3884	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3885	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
3886
3887	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3888	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3889
3890	/* Setup TSC offsetting. */
3891	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3892	if ( pSvmTransient->fUpdateTscOffsetting
3893	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3894	{
3895	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcbNstGst);
3896	pSvmTransient->fUpdateTscOffsetting = false;
3897	}
3898
3899	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3900	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3901	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
3902
3903	/* Store status of the shared guest-host state at the time of VMRUN. */
3904	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3905	if (CPUMIsGuestInLongModeEx(pCtx))
3906	{
3907	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3908	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3909	}
3910	else
3911	#endif
3912	{
3913	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3914	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3915	}
3916	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3917
3918	/* The TLB flushing would've already been setup by the nested-hypervisor. */
3919	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3920	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
3921	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3922
3923	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3924
3925	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3926	to start executing. */
3927
3928	/*
3929	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3930	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3931	*
3932	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3933	*/
3934	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
3935	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3936	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
3937	{
3938	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3939	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3940	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3941	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3942	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3943	pSvmTransient->fRestoreTscAuxMsr = true;
3944	}
3945	else
3946	{
3947	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3948	pSvmTransient->fRestoreTscAuxMsr = false;
3949	}
3950
3951	/*
3952	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
3953	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
3954	*/
3955	if ( !(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
3956	\|\| !(pVM->cpum.ro.GuestFeatures.fSvmVmcbClean))
3957	pVmcbNstGst->ctrl.u64VmcbCleanBits = 0;
3958	}
3959	#endif
3960
3961
3962	/**
3963	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3964	* means there is no backing out to ring-3 or anywhere else at this
3965	* point.
3966	*
3967	* @param pVM The cross context VM structure.
3968	* @param pVCpu The cross context virtual CPU structure.
3969	* @param pCtx Pointer to the guest-CPU context.
3970	* @param pSvmTransient Pointer to the SVM transient structure.
3971	*
3972	* @remarks Called with preemption disabled.
3973	* @remarks No-long-jump zone!!!
3974	*/
3975	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3976	{
3977	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3978	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3979	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3980
3981	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3982	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3983
3984	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3985	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
3986
3987	if ( pVCpu->hm.s.fPreloadGuestFpu
3988	&& !CPUMIsGuestFPUStateActive(pVCpu))
3989	{
3990	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3991	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3992	}
3993
3994	/* Load the state shared between host and guest (FPU, debug). */
3995	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3996	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3997
3998	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3999	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4000
4001	/* Setup TSC offsetting. */
4002	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4003	if ( pSvmTransient->fUpdateTscOffsetting
4004	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4005	{
4006	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
4007	pSvmTransient->fUpdateTscOffsetting = false;
4008	}
4009
4010	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4011	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4012	pVmcb->ctrl.u64VmcbCleanBits = 0;
4013
4014	/* Store status of the shared guest-host state at the time of VMRUN. */
4015	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4016	if (CPUMIsGuestInLongModeEx(pCtx))
4017	{
4018	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4019	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4020	}
4021	else
4022	#endif
4023	{
4024	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4025	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4026	}
4027	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4028
4029	/* Flush the appropriate tagged-TLB entries. */
4030	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4031	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
4032	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4033
4034	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4035
4036	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4037	to start executing. */
4038
4039	/*
4040	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4041	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4042	*
4043	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4044	*/
4045	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4046	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4047	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4048	{
4049	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4050	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4051	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4052	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4053	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4054	pSvmTransient->fRestoreTscAuxMsr = true;
4055	}
4056	else
4057	{
4058	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4059	pSvmTransient->fRestoreTscAuxMsr = false;
4060	}
4061
4062	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4063	if (!(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
4064	pVmcb->ctrl.u64VmcbCleanBits = 0;
4065	}
4066
4067
4068	/**
4069	* Wrapper for running the guest code in AMD-V.
4070	*
4071	* @returns VBox strict status code.
4072	* @param pVM The cross context VM structure.
4073	* @param pVCpu The cross context virtual CPU structure.
4074	* @param pCtx Pointer to the guest-CPU context.
4075	*
4076	* @remarks No-long-jump zone!!!
4077	*/
4078	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4079	{
4080	/*
4081	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4082	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4083	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4084	*/
4085	#ifdef VBOX_WITH_KERNEL_USING_XMM
4086	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4087	pVCpu->hm.s.svm.pfnVMRun);
4088	#else
4089	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4090	#endif
4091	}
4092
4093
4094	#ifdef VBOX_WITH_NESTED_HWVIRT
4095	/**
4096	* Wrapper for running the nested-guest code in AMD-V.
4097	*
4098	* @returns VBox strict status code.
4099	* @param pVM The cross context VM structure.
4100	* @param pVCpu The cross context virtual CPU structure.
4101	* @param pCtx Pointer to the guest-CPU context.
4102	*
4103	* @remarks No-long-jump zone!!!
4104	*/
4105	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4106	{
4107	/*
4108	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4109	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4110	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4111	*/
4112	#ifdef VBOX_WITH_KERNEL_USING_XMM
4113	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4114	pVCpu->hm.s.svm.pfnVMRun);
4115	#else
4116	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4117	#endif
4118	}
4119
4120
4121	/**
4122	* Performs some essential restoration of state after running nested-guest code in
4123	* AMD-V.
4124	*
4125	* @param pVM The cross context VM structure.
4126	* @param pVCpu The cross context virtual CPU structure.
4127	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4128	* out-of-sync. Make sure to update the required fields
4129	* before using them.
4130	* @param pSvmTransient Pointer to the SVM transient structure.
4131	* @param rcVMRun Return code of VMRUN.
4132	*
4133	* @remarks Called with interrupts disabled.
4134	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4135	* unconditionally when it is safe to do so.
4136	*/
4137	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4138	{
4139	RT_NOREF(pVM);
4140	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4141
4142	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4143	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4144
4145	/* TSC read must be done early for maximum accuracy. */
4146	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4147	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4148	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4149	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset);
4150
4151	if (pSvmTransient->fRestoreTscAuxMsr)
4152	{
4153	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4154	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4155	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4156	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4157	}
4158
4159	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4160	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4161	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4162
4163	Assert(!(ASMGetFlags() & X86_EFL_IF));
4164	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4165	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4166
4167	/* Mark the VMCB-state cache as unmodified by VMM. */
4168	pVmcbNstGstCtrl->u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4169
4170	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4171	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4172	{
4173	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4174	return;
4175	}
4176
4177	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4178	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4179	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4180	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4181
4182	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4183	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4184	guest-CPU context. */
4185
4186	HMSvmNstGstVmExitNotify(pVCpu, pMixedCtx); /* Restore modified VMCB fields for now, see @bugref{7243#c52} .*/
4187	}
4188	#endif
4189
4190	/**
4191	* Performs some essential restoration of state after running guest code in
4192	* AMD-V.
4193	*
4194	* @param pVM The cross context VM structure.
4195	* @param pVCpu The cross context virtual CPU structure.
4196	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4197	* out-of-sync. Make sure to update the required fields
4198	* before using them.
4199	* @param pSvmTransient Pointer to the SVM transient structure.
4200	* @param rcVMRun Return code of VMRUN.
4201	*
4202	* @remarks Called with interrupts disabled.
4203	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4204	* unconditionally when it is safe to do so.
4205	*/
4206	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4207	{
4208	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4209
4210	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4211	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4212
4213	PSVMVMCB pVmcb =pVCpu->hm.s.svm.pVmcb;
4214	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4215
4216	/* TSC read must be done early for maximum accuracy. */
4217	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4218	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4219
4220	if (pSvmTransient->fRestoreTscAuxMsr)
4221	{
4222	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4223	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4224	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4225	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4226	}
4227
4228	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4229	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4230	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4231
4232	Assert(!(ASMGetFlags() & X86_EFL_IF));
4233	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4234	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4235
4236	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4237	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4238	{
4239	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4240	return;
4241	}
4242
4243	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4244	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4245	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4246	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4247
4248	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4249
4250	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4251	{
4252	if (pVCpu->hm.s.svm.fSyncVTpr)
4253	{
4254	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4255	if ( pVM->hm.s.fTPRPatchingActive
4256	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4257	{
4258	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4259	AssertRC(rc);
4260	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4261	}
4262	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4263	{
4264	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4265	AssertRC(rc);
4266	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4267	}
4268	}
4269	}
4270	}
4271
4272
4273	/**
4274	* Runs the guest code using AMD-V.
4275	*
4276	* @returns VBox status code.
4277	* @param pVM The cross context VM structure.
4278	* @param pVCpu The cross context virtual CPU structure.
4279	* @param pCtx Pointer to the guest-CPU context.
4280	* @param pcLoops Pointer to the number of executed loops.
4281	*/
4282	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4283	{
4284	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4285	Assert(pcLoops);
4286	Assert(*pcLoops <= cMaxResumeLoops);
4287
4288	SVMTRANSIENT SvmTransient;
4289	SvmTransient.fUpdateTscOffsetting = true;
4290
4291	int rc = VERR_INTERNAL_ERROR_5;
4292	for (;;)
4293	{
4294	Assert(!HMR0SuspendPending());
4295	HMSVM_ASSERT_CPU_SAFE();
4296
4297	/* Preparatory work for running guest code, this may force us to return
4298	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4299	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4300	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4301	if (rc != VINF_SUCCESS)
4302	break;
4303
4304	/*
4305	* No longjmps to ring-3 from this point on!!!
4306	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4307	* This also disables flushing of the R0-logger instance (if any).
4308	*/
4309	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4310	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4311
4312	/* Restore any residual host-state and save any bits shared between host
4313	and guest into the guest-CPU state. Re-enables interrupts! */
4314	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4315
4316	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4317	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4318	{
4319	if (rc == VINF_SUCCESS)
4320	rc = VERR_SVM_INVALID_GUEST_STATE;
4321	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4322	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4323	break;
4324	}
4325
4326	/* Handle the #VMEXIT. */
4327	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4328	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4329	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4330	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4331	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4332	if (rc != VINF_SUCCESS)
4333	break;
4334	if (++(*pcLoops) >= cMaxResumeLoops)
4335	{
4336	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4337	rc = VINF_EM_RAW_INTERRUPT;
4338	break;
4339	}
4340	}
4341
4342	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4343	return rc;
4344	}
4345
4346
4347	/**
4348	* Runs the guest code using AMD-V in single step mode.
4349	*
4350	* @returns VBox status code.
4351	* @param pVM The cross context VM structure.
4352	* @param pVCpu The cross context virtual CPU structure.
4353	* @param pCtx Pointer to the guest-CPU context.
4354	* @param pcLoops Pointer to the number of executed loops.
4355	*/
4356	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4357	{
4358	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4359	Assert(pcLoops);
4360	Assert(*pcLoops <= cMaxResumeLoops);
4361
4362	SVMTRANSIENT SvmTransient;
4363	SvmTransient.fUpdateTscOffsetting = true;
4364
4365	uint16_t uCsStart = pCtx->cs.Sel;
4366	uint64_t uRipStart = pCtx->rip;
4367
4368	int rc = VERR_INTERNAL_ERROR_5;
4369	for (;;)
4370	{
4371	Assert(!HMR0SuspendPending());
4372	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4373	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4374	(unsigned)RTMpCpuId(), *pcLoops));
4375
4376	/* Preparatory work for running guest code, this may force us to return
4377	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4378	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4379	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4380	if (rc != VINF_SUCCESS)
4381	break;
4382
4383	/*
4384	* No longjmps to ring-3 from this point on!!!
4385	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4386	* This also disables flushing of the R0-logger instance (if any).
4387	*/
4388	VMMRZCallRing3Disable(pVCpu);
4389	VMMRZCallRing3RemoveNotification(pVCpu);
4390	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4391
4392	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4393
4394	/*
4395	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4396	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4397	*/
4398	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4399	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4400	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4401	{
4402	if (rc == VINF_SUCCESS)
4403	rc = VERR_SVM_INVALID_GUEST_STATE;
4404	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4405	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4406	return rc;
4407	}
4408
4409	/* Handle the #VMEXIT. */
4410	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4411	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4412	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4413	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4414	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4415	if (rc != VINF_SUCCESS)
4416	break;
4417	if (++(*pcLoops) >= cMaxResumeLoops)
4418	{
4419	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4420	rc = VINF_EM_RAW_INTERRUPT;
4421	break;
4422	}
4423
4424	/*
4425	* Did the RIP change, if so, consider it a single step.
4426	* Otherwise, make sure one of the TFs gets set.
4427	*/
4428	if ( pCtx->rip != uRipStart
4429	\|\| pCtx->cs.Sel != uCsStart)
4430	{
4431	rc = VINF_EM_DBG_STEPPED;
4432	break;
4433	}
4434	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4435	}
4436
4437	/*
4438	* Clear the X86_EFL_TF if necessary.
4439	*/
4440	if (pVCpu->hm.s.fClearTrapFlag)
4441	{
4442	pVCpu->hm.s.fClearTrapFlag = false;
4443	pCtx->eflags.Bits.u1TF = 0;
4444	}
4445
4446	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4447	return rc;
4448	}
4449
4450	#ifdef VBOX_WITH_NESTED_HWVIRT
4451	/**
4452	* Runs the nested-guest code using AMD-V.
4453	*
4454	* @returns VBox status code.
4455	* @param pVM The cross context VM structure.
4456	* @param pVCpu The cross context virtual CPU structure.
4457	* @param pCtx Pointer to the guest-CPU context.
4458	* @param pcLoops Pointer to the number of executed loops. If we're switching
4459	* from the guest-code execution loop to this nested-guest
4460	* execution loop pass the remainder value, else pass 0.
4461	*/
4462	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4463	{
4464	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4465	Assert(pcLoops);
4466	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4467
4468	SVMTRANSIENT SvmTransient;
4469	SvmTransient.fUpdateTscOffsetting = true;
4470
4471	int rc = VERR_INTERNAL_ERROR_4;
4472	for (;;)
4473	{
4474	Assert(!HMR0SuspendPending());
4475	HMSVM_ASSERT_CPU_SAFE();
4476
4477	/* Preparatory work for running nested-guest code, this may force us to return
4478	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4479	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4480	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4481	if (rc != VINF_SUCCESS)
4482	break;
4483
4484	/*
4485	* No longjmps to ring-3 from this point on!!!
4486	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4487	* This also disables flushing of the R0-logger instance (if any).
4488	*/
4489	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4490
4491	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4492
4493	/* Restore any residual host-state and save any bits shared between host
4494	and guest into the guest-CPU state. Re-enables interrupts! */
4495	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4496
4497	/** @todo This needs some work... we probably should cause a \#VMEXIT on
4498	* SVM_EXIT_INVALID and handle rc != VINF_SUCCESS differently. */
4499	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4500	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4501	{
4502	if (rc == VINF_SUCCESS)
4503	rc = VERR_SVM_INVALID_GUEST_STATE;
4504	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4505	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4506	break;
4507	}
4508
4509	/* Handle the #VMEXIT. */
4510	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4511	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4512	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4513	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4514	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4515	if (rc != VINF_SUCCESS)
4516	break;
4517	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4518	{
4519	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4520	rc = VINF_EM_RAW_INTERRUPT;
4521	break;
4522	}
4523
4524	/** @todo handle single-stepping */
4525	}
4526
4527	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4528	return rc;
4529	}
4530	#endif
4531
4532
4533	/**
4534	* Runs the guest code using AMD-V.
4535	*
4536	* @returns Strict VBox status code.
4537	* @param pVM The cross context VM structure.
4538	* @param pVCpu The cross context virtual CPU structure.
4539	* @param pCtx Pointer to the guest-CPU context.
4540	*/
4541	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4542	{
4543	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4544	HMSVM_ASSERT_PREEMPT_SAFE();
4545	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4546
4547	uint32_t cLoops = 0;
4548	int rc;
4549	#ifdef VBOX_WITH_NESTED_HWVIRT
4550	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4551	#endif
4552	{
4553	if (!pVCpu->hm.s.fSingleInstruction)
4554	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4555	else
4556	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4557	}
4558	#ifdef VBOX_WITH_NESTED_HWVIRT
4559	else
4560	{
4561	rc = VINF_SVM_VMRUN;
4562	}
4563
4564	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4565	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4566	if (rc == VINF_SVM_VMRUN)
4567	{
4568	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4569	if (rc == VINF_SVM_VMEXIT)
4570	rc = VINF_SUCCESS;
4571	}
4572	#endif
4573
4574	/* Fixup error codes. */
4575	if (rc == VERR_EM_INTERPRETER)
4576	rc = VINF_EM_RAW_EMULATE_INSTR;
4577	else if (rc == VINF_EM_RESET)
4578	rc = VINF_EM_TRIPLE_FAULT;
4579
4580	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4581	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4582	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4583	return rc;
4584	}
4585
4586
4587	#ifdef VBOX_WITH_NESTED_HWVIRT
4588	/**
4589	* Determines whether an IOIO intercept is active for the nested-guest or not.
4590	*
4591	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4592	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4593	*/
4594	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4595	{
4596	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4597	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4598	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4599	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4600	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4601	const bool fRep = pIoExitInfo->n.u1REP;
4602	const bool fStrIo = pIoExitInfo->n.u1STR;
4603
4604	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4605	NULL /* pIoExitInfo */);
4606	}
4607
4608
4609	/**
4610	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4611	* SVM_EXIT_INVALID).
4612	*
4613	* @returns VBox status code (informational status codes included).
4614	* @param pVCpu The cross context virtual CPU structure.
4615	* @param pCtx Pointer to the guest-CPU context.
4616	* @param pSvmTransient Pointer to the SVM transient structure.
4617	*/
4618	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4619	{
4620	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4621	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4622
4623	#define HM_SVM_RET_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4624	do \
4625	{ \
4626	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2)); \
4627	} while (0) \
4628
4629	/*
4630	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4631	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
4632	*/
4633	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4634	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4635	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4636	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4637	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4638	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4639
4640	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4641	switch (uExitCode)
4642	{
4643	case SVM_EXIT_CPUID:
4644	{
4645	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_CPUID)
4646	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4647	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
4648	}
4649
4650	case SVM_EXIT_RDTSC:
4651	{
4652	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC)
4653	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4654	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
4655	}
4656
4657	case SVM_EXIT_RDTSCP:
4658	{
4659	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP)
4660	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4661	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
4662	}
4663
4664
4665	case SVM_EXIT_MONITOR:
4666	{
4667	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MONITOR)
4668	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4669	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
4670	}
4671
4672	case SVM_EXIT_MWAIT:
4673	{
4674	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MWAIT)
4675	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4676	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
4677	}
4678
4679	case SVM_EXIT_HLT:
4680	{
4681	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_HLT)
4682	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4683	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
4684	}
4685
4686	case SVM_EXIT_MSR:
4687	{
4688	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_MSR_PROT)
4689	{
4690	uint32_t const idMsr = pCtx->ecx;
4691	uint16_t offMsrpm;
4692	uint32_t uMsrpmBit;
4693	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4694	if (RT_SUCCESS(rc))
4695	{
4696	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4697	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
4698	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
4699
4700	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4701	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4702	{
4703	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4704	}
4705	}
4706	else
4707	{
4708	/*
4709	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4710	* See AMD-V spec. "15.11 MSR Intercepts".
4711	*/
4712	Assert(rc == VERR_OUT_OF_RANGE);
4713	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4714	}
4715	}
4716	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
4717	}
4718
4719	case SVM_EXIT_IOIO:
4720	{
4721	/*
4722	* Figure out if the IO port access is intercepted by the nested-guest.
4723	*/
4724	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_IOIO_PROT)
4725	{
4726	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
4727	SVMIOIOEXITINFO IoExitInfo;
4728	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4729	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
4730	if (fIntercept)
4731	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4732	}
4733	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
4734	}
4735
4736	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
4737	{
4738	PVM pVM = pVCpu->CTX_SUFF(pVM);
4739	if (pVM->hm.s.fNestedPaging)
4740	{
4741	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4742	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4743
4744	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4745	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_PF))
4746	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4747
4748	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
4749	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4750	return VINF_SUCCESS;
4751	}
4752	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
4753	}
4754
4755	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
4756	{
4757	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_NM))
4758	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4759	hmR0SvmSetPendingXcptNM(pVCpu);
4760	return VINF_SUCCESS;
4761	}
4762
4763	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
4764	{
4765	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_UD))
4766	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4767	hmR0SvmSetPendingXcptUD(pVCpu);
4768	return VINF_SUCCESS;
4769	}
4770
4771	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
4772	{
4773	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_MF))
4774	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4775	hmR0SvmSetPendingXcptMF(pVCpu);
4776	return VINF_SUCCESS;
4777	}
4778
4779	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
4780	{
4781	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_DB))
4782	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4783	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
4784	}
4785
4786	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
4787	{
4788	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_AC))
4789	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4790	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
4791	}
4792
4793	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
4794	{
4795	if (pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(X86_XCPT_BP))
4796	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4797	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
4798	}
4799
4800	case SVM_EXIT_READ_CR0:
4801	case SVM_EXIT_READ_CR3:
4802	case SVM_EXIT_READ_CR4:
4803	{
4804	if (pVmcbNstGstCache->u16InterceptRdCRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0)))
4805	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4806	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
4807	}
4808
4809	case SVM_EXIT_WRITE_CR0:
4810	case SVM_EXIT_WRITE_CR3:
4811	case SVM_EXIT_WRITE_CR4:
4812	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
4813	{
4814	Log4(("hmR0SvmHandleExitNested: Write CRx: u16InterceptWrCRx=%#x u64ExitCode=%#RX64 %#x\n",
4815	pVmcbNstGstCache->u16InterceptWrCRx, pSvmTransient->u64ExitCode,
4816	(1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0))));
4817	if (pVmcbNstGstCache->u16InterceptWrCRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)))
4818	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4819	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
4820	}
4821
4822	case SVM_EXIT_PAUSE:
4823	{
4824	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_PAUSE)
4825	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4826	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
4827	}
4828
4829	case SVM_EXIT_VINTR:
4830	{
4831	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
4832	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4833	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4834	}
4835
4836	case SVM_EXIT_INTR:
4837	{
4838	/* We shouldn't direct physical interrupts to the nested-guest. */
4839	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4840	}
4841
4842	case SVM_EXIT_FERR_FREEZE:
4843	{
4844	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_FERR_FREEZE)
4845	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4846	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4847	}
4848
4849	case SVM_EXIT_NMI:
4850	{
4851	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_NMI)
4852	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4853	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
4854	}
4855
4856	case SVM_EXIT_INVLPG:
4857	{
4858	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVLPG)
4859	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4860	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
4861	}
4862
4863	case SVM_EXIT_WBINVD:
4864	{
4865	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_WBINVD)
4866	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4867	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
4868	}
4869
4870	case SVM_EXIT_INVD:
4871	{
4872	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVD)
4873	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4874	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
4875	}
4876
4877	case SVM_EXIT_RDPMC:
4878	{
4879	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDPMC)
4880	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4881	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
4882	}
4883
4884	default:
4885	{
4886	switch (pSvmTransient->u64ExitCode)
4887	{
4888	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
4889	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
4890	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
4891	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
4892	{
4893	if (pVmcbNstGstCache->u16InterceptRdDRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_READ_DR0)))
4894	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4895	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4896	}
4897
4898	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
4899	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
4900	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
4901	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
4902	{
4903	if (pVmcbNstGstCache->u16InterceptWrDRx & (1U << (uint16_t)(pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_DR0)))
4904	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4905	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
4906	}
4907
4908	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
4909	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
4910	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
4911	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
4912	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
4913	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
4914	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
4915	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
4916	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
4917	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
4918	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
4919	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
4920	{
4921	if (pVmcbNstGstCache->u32InterceptXcpt & (1U << (uint32_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0)))
4922	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4923	/** @todo Write hmR0SvmExitXcptGeneric! */
4924	return VERR_NOT_IMPLEMENTED;
4925	}
4926
4927	case SVM_EXIT_XSETBV:
4928	{
4929	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_XSETBV)
4930	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4931	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
4932	}
4933
4934	case SVM_EXIT_TASK_SWITCH:
4935	{
4936	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_TASK_SWITCH)
4937	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4938	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
4939	}
4940
4941	case SVM_EXIT_IRET:
4942	{
4943	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
4944	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4945	return hmR0SvmNestedExitIret(pVCpu, pCtx, pSvmTransient);
4946	}
4947
4948	case SVM_EXIT_SHUTDOWN:
4949	{
4950	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SHUTDOWN)
4951	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4952	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
4953	}
4954
4955	case SVM_EXIT_SMI:
4956	{
4957	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SMI)
4958	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4959	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4960	}
4961
4962	case SVM_EXIT_INIT:
4963	{
4964	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INIT)
4965	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4966	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
4967	}
4968
4969	case SVM_EXIT_VMMCALL:
4970	{
4971	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMMCALL)
4972	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4973	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
4974	}
4975
4976	case SVM_EXIT_CLGI:
4977	{
4978	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_CLGI)
4979	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4980	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
4981	}
4982
4983	case SVM_EXIT_STGI:
4984	{
4985	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_STGI)
4986	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4987	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
4988	}
4989
4990	case SVM_EXIT_VMLOAD:
4991	{
4992	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMLOAD)
4993	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4994	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
4995	}
4996
4997	case SVM_EXIT_VMSAVE:
4998	{
4999	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMSAVE)
5000	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5001	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5002	}
5003
5004	case SVM_EXIT_INVLPGA:
5005	{
5006	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INVLPGA)
5007	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5008	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5009	}
5010
5011	case SVM_EXIT_VMRUN:
5012	{
5013	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VMRUN)
5014	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5015	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5016	}
5017
5018	case SVM_EXIT_RSM:
5019	{
5020	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RSM)
5021	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5022	hmR0SvmSetPendingXcptUD(pVCpu);
5023	return VINF_SUCCESS;
5024	}
5025
5026	case SVM_EXIT_SKINIT:
5027	{
5028	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_SKINIT)
5029	HM_SVM_RET_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5030	hmR0SvmSetPendingXcptUD(pVCpu);
5031	return VINF_SUCCESS;
5032	}
5033
5034	case SVM_EXIT_NPF:
5035	{
5036	/* We don't yet support nested-paging for nested-guests, so this should never really happen. */
5037	Assert(!pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging);
5038	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5039	}
5040
5041	default:
5042	{
5043	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5044	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5045	return VERR_SVM_UNKNOWN_EXIT;
5046	}
5047	}
5048	}
5049	}
5050	/* not reached */
5051
5052	#undef HM_SVM_RET_VMEXIT_NESTED
5053	}
5054	#endif
5055
5056
5057	/**
5058	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5059	*
5060	* @returns VBox status code (informational status codes included).
5061	* @param pVCpu The cross context virtual CPU structure.
5062	* @param pCtx Pointer to the guest-CPU context.
5063	* @param pSvmTransient Pointer to the SVM transient structure.
5064	*/
5065	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5066	{
5067	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5068	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5069
5070	/*
5071	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5072	* normal workloads (for some definition of "normal").
5073	*/
5074	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
5075	switch (pSvmTransient->u64ExitCode)
5076	{
5077	case SVM_EXIT_NPF:
5078	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5079
5080	case SVM_EXIT_IOIO:
5081	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5082
5083	case SVM_EXIT_RDTSC:
5084	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5085
5086	case SVM_EXIT_RDTSCP:
5087	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5088
5089	case SVM_EXIT_CPUID:
5090	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5091
5092	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5093	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5094
5095	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5096	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5097
5098	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5099	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5100
5101	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5102	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5103
5104	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5105	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5106
5107	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5108	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5109
5110	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5111	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5112
5113	case SVM_EXIT_MONITOR:
5114	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5115
5116	case SVM_EXIT_MWAIT:
5117	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5118
5119	case SVM_EXIT_HLT:
5120	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5121
5122	case SVM_EXIT_READ_CR0:
5123	case SVM_EXIT_READ_CR3:
5124	case SVM_EXIT_READ_CR4:
5125	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5126
5127	case SVM_EXIT_WRITE_CR0:
5128	case SVM_EXIT_WRITE_CR3:
5129	case SVM_EXIT_WRITE_CR4:
5130	case SVM_EXIT_WRITE_CR8:
5131	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5132
5133	case SVM_EXIT_PAUSE:
5134	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5135
5136	case SVM_EXIT_VMMCALL:
5137	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5138
5139	case SVM_EXIT_VINTR:
5140	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5141
5142	case SVM_EXIT_INTR:
5143	case SVM_EXIT_FERR_FREEZE:
5144	case SVM_EXIT_NMI:
5145	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5146
5147	case SVM_EXIT_MSR:
5148	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5149
5150	case SVM_EXIT_INVLPG:
5151	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5152
5153	case SVM_EXIT_WBINVD:
5154	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5155
5156	case SVM_EXIT_INVD:
5157	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5158
5159	case SVM_EXIT_RDPMC:
5160	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5161
5162	default:
5163	{
5164	switch (pSvmTransient->u64ExitCode)
5165	{
5166	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5167	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5168	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5169	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5170	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5171
5172	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5173	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5174	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5175	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5176	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5177
5178	case SVM_EXIT_XSETBV:
5179	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5180
5181	case SVM_EXIT_TASK_SWITCH:
5182	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5183
5184	case SVM_EXIT_IRET:
5185	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5186
5187	case SVM_EXIT_SHUTDOWN:
5188	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5189
5190	case SVM_EXIT_SMI:
5191	case SVM_EXIT_INIT:
5192	{
5193	/*
5194	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5195	* If it ever does, we want to know about it so log the exit code and bail.
5196	*/
5197	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5198	}
5199
5200	#ifdef VBOX_WITH_NESTED_HWVIRT
5201	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5202	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5203	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5204	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5205	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5206	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5207	#else
5208	case SVM_EXIT_CLGI:
5209	case SVM_EXIT_STGI:
5210	case SVM_EXIT_VMLOAD:
5211	case SVM_EXIT_VMSAVE:
5212	case SVM_EXIT_INVLPGA:
5213	case SVM_EXIT_VMRUN:
5214	#endif
5215	case SVM_EXIT_RSM:
5216	case SVM_EXIT_SKINIT:
5217	{
5218	hmR0SvmSetPendingXcptUD(pVCpu);
5219	return VINF_SUCCESS;
5220	}
5221
5222	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5223	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5224	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5225	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5226	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5227	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5228	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5229	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5230	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5231	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5232	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5233	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5234	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5235	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5236	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5237	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5238	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5239	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5240	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5241	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5242	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5243	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5244	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5245	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5246	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5247	{
5248	/** @todo r=ramshankar; We should be doing
5249	* HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY here! */
5250
5251	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5252	SVMEVENT Event;
5253	Event.u = 0;
5254	Event.n.u1Valid = 1;
5255	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5256	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5257
5258	switch (Event.n.u8Vector)
5259	{
5260	case X86_XCPT_DE:
5261	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
5262	break;
5263
5264	case X86_XCPT_NP:
5265	Event.n.u1ErrorCodeValid = 1;
5266	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5267	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
5268	break;
5269
5270	case X86_XCPT_SS:
5271	Event.n.u1ErrorCodeValid = 1;
5272	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5273	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
5274	break;
5275
5276	case X86_XCPT_GP:
5277	Event.n.u1ErrorCodeValid = 1;
5278	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
5279	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
5280	break;
5281
5282	default:
5283	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
5284	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
5285	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
5286	}
5287
5288	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
5289	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5290	return VINF_SUCCESS;
5291	}
5292	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5293
5294	default:
5295	{
5296	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
5297	pVCpu->hm.s.u32HMError = u32ExitCode;
5298	return VERR_SVM_UNKNOWN_EXIT;
5299	}
5300	}
5301	}
5302	}
5303	/* not reached */
5304	}
5305
5306
5307	#ifdef DEBUG
5308	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5309	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5310	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5311
5312	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5313	do \
5314	{ \
5315	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5316	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5317	} while (0)
5318
5319	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5320	do { \
5321	AssertPtr(pVCpu); \
5322	AssertPtr(pCtx); \
5323	AssertPtr(pSvmTransient); \
5324	Assert(ASMIntAreEnabled()); \
5325	HMSVM_ASSERT_PREEMPT_SAFE(); \
5326	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5327	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5328	HMSVM_ASSERT_PREEMPT_SAFE(); \
5329	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5330	HMSVM_ASSERT_PREEMPT_CPUID(); \
5331	} while (0)
5332	#else /* Release builds */
5333	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5334	#endif
5335
5336
5337	/**
5338	* Worker for hmR0SvmInterpretInvlpg().
5339	*
5340	* @return VBox status code.
5341	* @param pVCpu The cross context virtual CPU structure.
5342	* @param pCpu Pointer to the disassembler state.
5343	* @param pCtx The guest CPU context.
5344	*/
5345	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5346	{
5347	DISQPVPARAMVAL Param1;
5348	RTGCPTR GCPtrPage;
5349
5350	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5351	if (RT_FAILURE(rc))
5352	return VERR_EM_INTERPRETER;
5353
5354	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5355	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5356	{
5357	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5358	return VERR_EM_INTERPRETER;
5359
5360	GCPtrPage = Param1.val.val64;
5361	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5362	rc = VBOXSTRICTRC_VAL(rc2);
5363	}
5364	else
5365	{
5366	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5367	rc = VERR_EM_INTERPRETER;
5368	}
5369
5370	return rc;
5371	}
5372
5373
5374	/**
5375	* Interprets INVLPG.
5376	*
5377	* @returns VBox status code.
5378	* @retval VINF_* Scheduling instructions.
5379	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5380	* @retval VERR_* Fatal errors.
5381	*
5382	* @param pVM The cross context VM structure.
5383	* @param pVCpu The cross context virtual CPU structure.
5384	* @param pCtx The guest CPU context.
5385	*
5386	* @remarks Updates the RIP if the instruction was executed successfully.
5387	*/
5388	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5389	{
5390	/* Only allow 32 & 64 bit code. */
5391	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5392	{
5393	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5394	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5395	if ( RT_SUCCESS(rc)
5396	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5397	{
5398	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5399	if (RT_SUCCESS(rc))
5400	pCtx->rip += pDis->cbInstr;
5401	return rc;
5402	}
5403	else
5404	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5405	}
5406	return VERR_EM_INTERPRETER;
5407	}
5408
5409
5410	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5411	/**
5412	* Gets the IEM exception flags for the specified SVM event.
5413	*
5414	* @returns The IEM exception flags.
5415	* @param pEvent Pointer to the SVM event.
5416	*
5417	* @remarks This function currently only constructs flags required for
5418	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5419	* and CR2 aspects of an exception are not included).
5420	*/
5421	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5422	{
5423	uint8_t const uEventType = pEvent->n.u3Type;
5424	uint32_t fIemXcptFlags;
5425	switch (uEventType)
5426	{
5427	case SVM_EVENT_EXCEPTION:
5428	/*
5429	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5430	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5431	*/
5432	if (pEvent->n.u8Vector == X86_XCPT_BP)
5433	{
5434	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5435	break;
5436	}
5437	if (pEvent->n.u8Vector == X86_XCPT_OF)
5438	{
5439	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5440	break;
5441	}
5442	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5443	RT_FALL_THRU();
5444	case SVM_EVENT_NMI:
5445	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5446	break;
5447
5448	case SVM_EVENT_EXTERNAL_IRQ:
5449	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5450	break;
5451
5452	case SVM_EVENT_SOFTWARE_INT:
5453	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5454	break;
5455
5456	default:
5457	fIemXcptFlags = 0;
5458	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5459	break;
5460	}
5461	return fIemXcptFlags;
5462	}
5463
5464	#else
5465	/**
5466	* Determines if an exception is a contributory exception.
5467	*
5468	* Contributory exceptions are ones which can cause double-faults unless the
5469	* original exception was a benign exception. Page-fault is intentionally not
5470	* included here as it's a conditional contributory exception.
5471	*
5472	* @returns true if the exception is contributory, false otherwise.
5473	* @param uVector The exception vector.
5474	*/
5475	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5476	{
5477	switch (uVector)
5478	{
5479	case X86_XCPT_GP:
5480	case X86_XCPT_SS:
5481	case X86_XCPT_NP:
5482	case X86_XCPT_TS:
5483	case X86_XCPT_DE:
5484	return true;
5485	default:
5486	break;
5487	}
5488	return false;
5489	}
5490	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5491
5492
5493	/**
5494	* Handle a condition that occurred while delivering an event through the guest
5495	* IDT.
5496	*
5497	* @returns VBox status code (informational error codes included).
5498	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5499	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5500	* continue execution of the guest which will delivery the \#DF.
5501	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5502	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5503	*
5504	* @param pVCpu The cross context virtual CPU structure.
5505	* @param pCtx Pointer to the guest-CPU context.
5506	* @param pSvmTransient Pointer to the SVM transient structure.
5507	*
5508	* @remarks No-long-jump zone!!!
5509	*/
5510	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5511	{
5512	int rc = VINF_SUCCESS;
5513	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5514
5515	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5516	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5517	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5518
5519	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5520	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5521	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5522	{
5523	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5524	IEMXCPTRAISE enmRaise;
5525	IEMXCPTRAISEINFO fRaiseInfo;
5526	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5527	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5528	if (fExitIsHwXcpt)
5529	{
5530	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5531	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5532	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5533	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5534	}
5535	else
5536	{
5537	/*
5538	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5539	* end up here.
5540	*
5541	* If the event was:
5542	* - a software interrupt, we can re-execute the instruction which will regenerate
5543	* the event.
5544	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5545	* - a hardware exception or external interrupt, we re-inject it.
5546	*/
5547	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5548	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5549	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5550	else
5551	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5552	}
5553
5554	switch (enmRaise)
5555	{
5556	case IEMXCPTRAISE_CURRENT_XCPT:
5557	case IEMXCPTRAISE_PREV_EVENT:
5558	{
5559	/* For software interrupts, we shall re-execute the instruction. */
5560	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5561	{
5562	RTGCUINTPTR GCPtrFaultAddress = 0;
5563
5564	/* If we are re-injecting an NMI, clear NMI blocking. */
5565	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5566	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5567
5568	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5569	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5570	pSvmTransient->fVectoringPF = true;
5571	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5572	&& uIdtVector == X86_XCPT_PF)
5573	{
5574	/*
5575	* If the previous exception was a #PF, we need to recover the CR2 value.
5576	* This can't happen with shadow paging.
5577	*/
5578	GCPtrFaultAddress = pCtx->cr2;
5579	}
5580
5581	/*
5582	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5583	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5584	*/
5585	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5586	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5587	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5588
5589	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5590	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5591	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5592	}
5593	break;
5594	}
5595
5596	case IEMXCPTRAISE_REEXEC_INSTR:
5597	{
5598	Assert(rc == VINF_SUCCESS);
5599	break;
5600	}
5601
5602	case IEMXCPTRAISE_DOUBLE_FAULT:
5603	{
5604	/*
5605	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5606	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5607	*/
5608	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5609	{
5610	pSvmTransient->fVectoringDoublePF = true;
5611	Assert(rc == VINF_SUCCESS);
5612	}
5613	else
5614	{
5615	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5616	hmR0SvmSetPendingXcptDF(pVCpu);
5617	rc = VINF_HM_DOUBLE_FAULT;
5618	}
5619	break;
5620	}
5621
5622	case IEMXCPTRAISE_TRIPLE_FAULT:
5623	{
5624	rc = VINF_EM_RESET;
5625	break;
5626	}
5627
5628	case IEMXCPTRAISE_CPU_HANG:
5629	{
5630	rc = VERR_EM_GUEST_CPU_HANG;
5631	break;
5632	}
5633
5634	default:
5635	{
5636	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5637	rc = VERR_SVM_IPE_2;
5638	break;
5639	}
5640	}
5641	#else
5642	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5643
5644	typedef enum
5645	{
5646	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5647	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5648	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5649	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5650	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5651	} SVMREFLECTXCPT;
5652
5653	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5654	bool fReflectingNmi = false;
5655	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5656	{
5657	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5658	{
5659	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5660
5661	#ifdef VBOX_STRICT
5662	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5663	&& uExitVector == X86_XCPT_PF)
5664	{
5665	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5666	}
5667	#endif
5668
5669	if ( uIdtVector == X86_XCPT_BP
5670	\|\| uIdtVector == X86_XCPT_OF)
5671	{
5672	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5673	}
5674	else if ( uExitVector == X86_XCPT_PF
5675	&& uIdtVector == X86_XCPT_PF)
5676	{
5677	pSvmTransient->fVectoringDoublePF = true;
5678	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
5679	}
5680	else if ( uExitVector == X86_XCPT_AC
5681	&& uIdtVector == X86_XCPT_AC)
5682	{
5683	enmReflect = SVMREFLECTXCPT_HANG;
5684	Log4(("IDT: Nested #AC - Bad guest\n"));
5685	}
5686	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
5687	&& hmR0SvmIsContributoryXcpt(uExitVector)
5688	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
5689	\|\| uIdtVector == X86_XCPT_PF))
5690	{
5691	enmReflect = SVMREFLECTXCPT_DF;
5692	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
5693	uIdtVector, uExitVector));
5694	}
5695	else if (uIdtVector == X86_XCPT_DF)
5696	{
5697	enmReflect = SVMREFLECTXCPT_TF;
5698	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
5699	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
5700	}
5701	else
5702	enmReflect = SVMREFLECTXCPT_XCPT;
5703	}
5704	else
5705	{
5706	/*
5707	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
5708	* exception to the guest after handling the #VMEXIT.
5709	*/
5710	enmReflect = SVMREFLECTXCPT_XCPT;
5711	}
5712	}
5713	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
5714	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5715	{
5716	enmReflect = SVMREFLECTXCPT_XCPT;
5717	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
5718
5719	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5720	{
5721	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5722	if (uExitVector == X86_XCPT_PF)
5723	{
5724	pSvmTransient->fVectoringPF = true;
5725	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
5726	}
5727	}
5728	}
5729	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
5730
5731	switch (enmReflect)
5732	{
5733	case SVMREFLECTXCPT_XCPT:
5734	{
5735	/* If we are re-injecting the NMI, clear NMI blocking. */
5736	if (fReflectingNmi)
5737	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5738
5739	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5740	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5741	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
5742
5743	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
5744	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
5745	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
5746	break;
5747	}
5748
5749	case SVMREFLECTXCPT_DF:
5750	{
5751	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5752	hmR0SvmSetPendingXcptDF(pVCpu);
5753	rc = VINF_HM_DOUBLE_FAULT;
5754	break;
5755	}
5756
5757	case SVMREFLECTXCPT_TF:
5758	{
5759	rc = VINF_EM_RESET;
5760	break;
5761	}
5762
5763	case SVMREFLECTXCPT_HANG:
5764	{
5765	rc = VERR_EM_GUEST_CPU_HANG;
5766	break;
5767	}
5768
5769	default:
5770	Assert(rc == VINF_SUCCESS);
5771	break;
5772	}
5773	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5774	}
5775	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5776	NOREF(pCtx);
5777	return rc;
5778	}
5779
5780
5781	/**
5782	* Updates interrupt shadow for the current RIP.
5783	*/
5784	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
5785	do { \
5786	/* Update interrupt shadow. */ \
5787	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
5788	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
5789	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
5790	} while (0)
5791
5792
5793	/**
5794	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
5795	* supported, otherwise advances the RIP by the number of bytes specified in
5796	* @a cb.
5797	*
5798	* @param pVCpu The cross context virtual CPU structure.
5799	* @param pCtx Pointer to the guest-CPU context.
5800	* @param cb RIP increment value in bytes.
5801	*
5802	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
5803	* when NRIP_SAVE is supported by the CPU, otherwise use
5804	* hmR0SvmAdvanceRipDumb!
5805	*/
5806	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5807	{
5808	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
5809	{
5810	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5811	Assert(pVmcb->ctrl.u64NextRIP);
5812	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
5813	pCtx->rip = pVmcb->ctrl.u64NextRIP;
5814	}
5815	else
5816	pCtx->rip += cb;
5817
5818	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5819	}
5820
5821
5822	#ifdef VBOX_WITH_NESTED_HWVIRT
5823	/**
5824	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
5825	* feature. Otherwise, returns the value in @a cbLikely.
5826	*
5827	* @param pVCpu The cross context virtual CPU structure.
5828	* @param pCtx Pointer to the guest-CPU context.
5829	* @param cbLikely The likely instruction length.
5830	*/
5831	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
5832	{
5833	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
5834	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
5835	{
5836	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
5837	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
5838	Assert(cbInstr == cbLikely);
5839	return cbInstr;
5840	}
5841	return cbLikely;
5842	}
5843	#endif
5844
5845
5846	/**
5847	* Advances the guest RIP by the number of bytes specified in @a cb. This does
5848	* not make use of any hardware features to determine the instruction length.
5849	*
5850	* @param pVCpu The cross context virtual CPU structure.
5851	* @param pCtx Pointer to the guest-CPU context.
5852	* @param cb RIP increment value in bytes.
5853	*/
5854	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5855	{
5856	pCtx->rip += cb;
5857	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5858	}
5859	#undef HMSVM_UPDATE_INTR_SHADOW
5860
5861
5862	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5863	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5864	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5865
5866	/** @name \#VMEXIT handlers.
5867	* @{
5868	*/
5869
5870	/**
5871	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5872	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5873	*/
5874	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5875	{
5876	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5877
5878	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5879	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5880	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5881	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5882
5883	/*
5884	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
5885	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
5886	* interrupt it is until the host actually take the interrupt.
5887	*
5888	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
5889	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5890	*/
5891	return VINF_EM_RAW_INTERRUPT;
5892	}
5893
5894
5895	/**
5896	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5897	*/
5898	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5899	{
5900	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5901
5902	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5903	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
5904	int rc = VINF_SUCCESS;
5905	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5906	return rc;
5907	}
5908
5909
5910	/**
5911	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5912	*/
5913	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5914	{
5915	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5916
5917	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5918	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
5919	int rc = VINF_SUCCESS;
5920	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5921	return rc;
5922	}
5923
5924
5925	/**
5926	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5927	*/
5928	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5929	{
5930	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5931	PVM pVM = pVCpu->CTX_SUFF(pVM);
5932	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
5933	if (RT_LIKELY(rc == VINF_SUCCESS))
5934	{
5935	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5936	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5937	}
5938	else
5939	{
5940	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5941	rc = VERR_EM_INTERPRETER;
5942	}
5943	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
5944	return rc;
5945	}
5946
5947
5948	/**
5949	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5950	*/
5951	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5952	{
5953	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5954	PVM pVM = pVCpu->CTX_SUFF(pVM);
5955	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
5956	if (RT_LIKELY(rc == VINF_SUCCESS))
5957	{
5958	pSvmTransient->fUpdateTscOffsetting = true;
5959	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
5960	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5961	}
5962	else
5963	{
5964	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
5965	rc = VERR_EM_INTERPRETER;
5966	}
5967	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
5968	return rc;
5969	}
5970
5971
5972	/**
5973	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5974	*/
5975	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5976	{
5977	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5978	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5979	if (RT_LIKELY(rc == VINF_SUCCESS))
5980	{
5981	pSvmTransient->fUpdateTscOffsetting = true;
5982	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
5983	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5984	}
5985	else
5986	{
5987	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
5988	rc = VERR_EM_INTERPRETER;
5989	}
5990	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
5991	return rc;
5992	}
5993
5994
5995	/**
5996	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5997	*/
5998	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5999	{
6000	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6001	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6002	if (RT_LIKELY(rc == VINF_SUCCESS))
6003	{
6004	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6005	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6006	}
6007	else
6008	{
6009	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6010	rc = VERR_EM_INTERPRETER;
6011	}
6012	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6013	return rc;
6014	}
6015
6016
6017	/**
6018	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6019	*/
6020	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6021	{
6022	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6023	PVM pVM = pVCpu->CTX_SUFF(pVM);
6024	Assert(!pVM->hm.s.fNestedPaging);
6025	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6026
6027	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
6028	{
6029	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
6030	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6031	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6032	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6033	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6034	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6035	return VBOXSTRICTRC_VAL(rcStrict);
6036	}
6037
6038	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6039	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6040	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6041	return rc;
6042	}
6043
6044
6045	/**
6046	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6047	*/
6048	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6049	{
6050	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6051
6052	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6053	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6054	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6055	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6056	if (rc != VINF_SUCCESS)
6057	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6058	return rc;
6059	}
6060
6061
6062	/**
6063	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6064	*/
6065	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6066	{
6067	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6068	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6069	if (RT_LIKELY(rc == VINF_SUCCESS))
6070	{
6071	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6072	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6073	}
6074	else
6075	{
6076	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6077	rc = VERR_EM_INTERPRETER;
6078	}
6079	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6080	return rc;
6081	}
6082
6083
6084	/**
6085	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6086	*/
6087	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6088	{
6089	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6090	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6091	int rc = VBOXSTRICTRC_VAL(rc2);
6092	if ( rc == VINF_EM_HALT
6093	\|\| rc == VINF_SUCCESS)
6094	{
6095	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6096
6097	if ( rc == VINF_EM_HALT
6098	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6099	{
6100	rc = VINF_SUCCESS;
6101	}
6102	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6103	}
6104	else
6105	{
6106	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6107	rc = VERR_EM_INTERPRETER;
6108	}
6109	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6110	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6111	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6112	return rc;
6113	}
6114
6115
6116	/**
6117	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6118	* \#VMEXIT.
6119	*/
6120	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6121	{
6122	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6123	return VINF_EM_RESET;
6124	}
6125
6126
6127	/**
6128	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6129	*/
6130	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6131	{
6132	RT_NOREF(pCtx);
6133	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64\n", pSvmTransient->u64ExitCode));
6134	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6135	return VERR_SVM_UNEXPECTED_EXIT;
6136	}
6137
6138
6139	/**
6140	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6141	*/
6142	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6143	{
6144	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6145
6146	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6147	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6148
6149	PVM pVM = pVCpu->CTX_SUFF(pVM);
6150	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
6151	{
6152	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
6153	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6154	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6155	if (fMovCRx)
6156	{
6157	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6158	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6159	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6160	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6161	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6162	return VBOXSTRICTRC_VAL(rcStrict);
6163	}
6164	/* else: SMSW instruction, fall back below to IEM for this. */
6165	}
6166
6167	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6168	int rc = VBOXSTRICTRC_VAL(rc2);
6169	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6170	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6171	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6172	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6173	return rc;
6174	}
6175
6176
6177	/**
6178	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6179	*/
6180	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6181	{
6182	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6183
6184	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6185	Assert(iCrReg <= 15);
6186
6187	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6188	PVM pVM = pVCpu->CTX_SUFF(pVM);
6189	bool fDecodedInstr = false;
6190	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
6191	{
6192	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
6193	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6194	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6195	if (fMovCRx)
6196	{
6197	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6198	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6199	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6200	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6201	fDecodedInstr = true;
6202	}
6203	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6204	}
6205
6206	if (!fDecodedInstr)
6207	{
6208	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6209	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6210	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6211	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6212	rcStrict = VERR_EM_INTERPRETER;
6213	}
6214
6215	if (rcStrict == VINF_SUCCESS)
6216	{
6217	switch (iCrReg)
6218	{
6219	case 0: /* CR0. */
6220	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6221	break;
6222
6223	case 3: /* CR3. */
6224	Assert(!pVM->hm.s.fNestedPaging);
6225	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6226	break;
6227
6228	case 4: /* CR4. */
6229	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6230	break;
6231
6232	case 8: /* CR8 (TPR). */
6233	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6234	break;
6235
6236	default:
6237	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6238	pSvmTransient->u64ExitCode, iCrReg));
6239	break;
6240	}
6241	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6242	}
6243	else
6244	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6245	return VBOXSTRICTRC_TODO(rcStrict);
6246	}
6247
6248
6249	/**
6250	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6251	* \#VMEXIT.
6252	*/
6253	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6254	{
6255	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6256	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6257	PVM pVM = pVCpu->CTX_SUFF(pVM);
6258
6259	int rc;
6260	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6261	{
6262	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6263	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6264
6265	/* Handle TPR patching; intercepted LSTAR write. */
6266	if ( pVM->hm.s.fTPRPatchingActive
6267	&& pCtx->ecx == MSR_K8_LSTAR)
6268	{
6269	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6270	{
6271	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6272	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6273	AssertRC(rc2);
6274	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6275	}
6276	rc = VINF_SUCCESS;
6277	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6278	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6279	return rc;
6280	}
6281
6282	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6283	{
6284	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6285	if (RT_LIKELY(rc == VINF_SUCCESS))
6286	{
6287	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6288	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6289	}
6290	else
6291	AssertMsg( rc == VERR_EM_INTERPRETER
6292	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6293	}
6294	else
6295	{
6296	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6297	if (RT_LIKELY(rc == VINF_SUCCESS))
6298	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6299	else
6300	AssertMsg( rc == VERR_EM_INTERPRETER
6301	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6302	}
6303
6304	if (rc == VINF_SUCCESS)
6305	{
6306	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6307	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6308	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6309	{
6310	/*
6311	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6312	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6313	* EMInterpretWrmsr() changes it.
6314	*/
6315	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6316	}
6317	else if (pCtx->ecx == MSR_K6_EFER)
6318	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
6319	else if (pCtx->ecx == MSR_IA32_TSC)
6320	pSvmTransient->fUpdateTscOffsetting = true;
6321	}
6322	}
6323	else
6324	{
6325	/* MSR Read access. */
6326	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6327	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6328	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6329
6330	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6331	{
6332	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6333	if (RT_LIKELY(rc == VINF_SUCCESS))
6334	{
6335	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6336	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6337	}
6338	else
6339	AssertMsg( rc == VERR_EM_INTERPRETER
6340	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6341	}
6342	else
6343	{
6344	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6345	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6346	{
6347	AssertMsg( rc == VERR_EM_INTERPRETER
6348	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6349	}
6350	/* RIP updated by EMInterpretInstruction(). */
6351	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6352	}
6353	}
6354
6355	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
6356	return rc;
6357	}
6358
6359
6360	/**
6361	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6362	*/
6363	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6364	{
6365	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6366	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6367
6368	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6369	if (pSvmTransient->fWasGuestDebugStateActive)
6370	{
6371	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6372	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6373	return VERR_SVM_UNEXPECTED_EXIT;
6374	}
6375
6376	/*
6377	* Lazy DR0-3 loading.
6378	*/
6379	if ( !pSvmTransient->fWasHyperDebugStateActive
6380	#ifdef VBOX_WITH_NESTED_HWVIRT
6381	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)) /** @todo implement single-stepping when executing a nested-guest. */
6382	#endif
6383	{
6384	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6385	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6386
6387	/* Don't intercept DRx read and writes. */
6388	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6389	pVmcb->ctrl.u16InterceptRdDRx = 0;
6390	pVmcb->ctrl.u16InterceptWrDRx = 0;
6391	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6392
6393	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6394	VMMRZCallRing3Disable(pVCpu);
6395	HM_DISABLE_PREEMPT();
6396
6397	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6398	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6399	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6400
6401	HM_RESTORE_PREEMPT();
6402	VMMRZCallRing3Enable(pVCpu);
6403
6404	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6405	return VINF_SUCCESS;
6406	}
6407
6408	/*
6409	* Interpret the read/writing of DRx.
6410	*/
6411	/** @todo Decode assist. */
6412	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6413	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6414	if (RT_LIKELY(rc == VINF_SUCCESS))
6415	{
6416	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6417	/** @todo CPUM should set this flag! */
6418	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6419	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6420	}
6421	else
6422	Assert(rc == VERR_EM_INTERPRETER);
6423	return VBOXSTRICTRC_TODO(rc);
6424	}
6425
6426
6427	/**
6428	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6429	*/
6430	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6431	{
6432	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6433	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6434	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6435	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6436	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6437	return rc;
6438	}
6439
6440
6441	/**
6442	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6443	*/
6444	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6445	{
6446	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6447
6448	/** @todo decode assists... */
6449	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6450	if (rcStrict == VINF_IEM_RAISED_XCPT)
6451	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6452
6453	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6454	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6455	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6456
6457	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6458	return VBOXSTRICTRC_TODO(rcStrict);
6459	}
6460
6461
6462	/**
6463	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6464	*/
6465	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6466	{
6467	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6468
6469	/* I/O operation lookup arrays. */
6470	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6471	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6472	the result (in AL/AX/EAX). */
6473	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6474
6475	PVM pVM = pVCpu->CTX_SUFF(pVM);
6476	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6477
6478	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6479	SVMIOIOEXITINFO IoExitInfo;
6480	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6481	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6482	uint32_t cbValue = s_aIOSize[uIOWidth];
6483	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6484
6485	if (RT_UNLIKELY(!cbValue))
6486	{
6487	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6488	return VERR_EM_INTERPRETER;
6489	}
6490
6491	VBOXSTRICTRC rcStrict;
6492	bool fUpdateRipAlready = false;
6493	if (IoExitInfo.n.u1STR)
6494	{
6495	#ifdef VBOX_WITH_2ND_IEM_STEP
6496	/* INS/OUTS - I/O String instruction. */
6497	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6498	* in EXITINFO1? Investigate once this thing is up and running. */
6499	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6500	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6501	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6502	static IEMMODE const s_aenmAddrMode[8] =
6503	{
6504	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6505	};
6506	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6507	if (enmAddrMode != (IEMMODE)-1)
6508	{
6509	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6510	if (cbInstr <= 15 && cbInstr >= 1)
6511	{
6512	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6513	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6514	{
6515	/* Don't know exactly how to detect whether u3SEG is valid, currently
6516	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6517	2384 Opterons when only checking NRIP. */
6518	if ( (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
6519	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6520	{
6521	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6522	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6523	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6524	IoExitInfo.n.u3SEG, true /fIoChecked/);
6525	}
6526	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6527	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6528	X86_SREG_DS, true /fIoChecked/);
6529	else
6530	rcStrict = IEMExecOne(pVCpu);
6531	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6532	}
6533	else
6534	{
6535	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6536	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6537	true /fIoChecked/);
6538	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6539	}
6540	}
6541	else
6542	{
6543	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6544	rcStrict = IEMExecOne(pVCpu);
6545	}
6546	}
6547	else
6548	{
6549	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6550	rcStrict = IEMExecOne(pVCpu);
6551	}
6552	fUpdateRipAlready = true;
6553
6554	#else
6555	/* INS/OUTS - I/O String instruction. */
6556	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6557
6558	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6559	* in EXITINFO1? Investigate once this thing is up and running. */
6560
6561	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6562	if (rcStrict == VINF_SUCCESS)
6563	{
6564	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6565	{
6566	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6567	(DISCPUMODE)pDis->uAddrMode, cbValue);
6568	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6569	}
6570	else
6571	{
6572	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6573	(DISCPUMODE)pDis->uAddrMode, cbValue);
6574	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6575	}
6576	}
6577	else
6578	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6579	#endif
6580	}
6581	else
6582	{
6583	/* IN/OUT - I/O instruction. */
6584	Assert(!IoExitInfo.n.u1REP);
6585
6586	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6587	{
6588	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6589	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6590	}
6591	else
6592	{
6593	uint32_t u32Val = 0;
6594	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6595	if (IOM_SUCCESS(rcStrict))
6596	{
6597	/* Save result of I/O IN instr. in AL/AX/EAX. */
6598	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6599	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6600	}
6601	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6602	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6603
6604	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6605	}
6606	}
6607
6608	if (IOM_SUCCESS(rcStrict))
6609	{
6610	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6611	if (!fUpdateRipAlready)
6612	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6613
6614	/*
6615	* If any I/O breakpoints are armed, we need to check if one triggered
6616	* and take appropriate action.
6617	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6618	*/
6619	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6620	* execution engines about whether hyper BPs and such are pending. */
6621	uint32_t const uDr7 = pCtx->dr[7];
6622	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6623	&& X86_DR7_ANY_RW_IO(uDr7)
6624	&& (pCtx->cr4 & X86_CR4_DE))
6625	\|\| DBGFBpIsHwIoArmed(pVM)))
6626	{
6627	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6628	VMMRZCallRing3Disable(pVCpu);
6629	HM_DISABLE_PREEMPT();
6630
6631	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6632	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6633
6634	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6635	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6636	{
6637	/* Raise #DB. */
6638	pVmcb->guest.u64DR6 = pCtx->dr[6];
6639	pVmcb->guest.u64DR7 = pCtx->dr[7];
6640	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6641	hmR0SvmSetPendingXcptDB(pVCpu);
6642	}
6643	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6644	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6645	else if ( rcStrict2 != VINF_SUCCESS
6646	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6647	rcStrict = rcStrict2;
6648	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6649
6650	HM_RESTORE_PREEMPT();
6651	VMMRZCallRing3Enable(pVCpu);
6652	}
6653
6654	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6655	}
6656
6657	#ifdef VBOX_STRICT
6658	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6659	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6660	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6661	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6662	else
6663	{
6664	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6665	* statuses, that the VMM device and some others may return. See
6666	* IOM_SUCCESS() for guidance. */
6667	AssertMsg( RT_FAILURE(rcStrict)
6668	\|\| rcStrict == VINF_SUCCESS
6669	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6670	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6671	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6672	\|\| rcStrict == VINF_EM_RAW_TO_R3
6673	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6674	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6675	}
6676	#endif
6677	return VBOXSTRICTRC_TODO(rcStrict);
6678	}
6679
6680
6681	/**
6682	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6683	*/
6684	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6685	{
6686	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6687	PVM pVM = pVCpu->CTX_SUFF(pVM);
6688	Assert(pVM->hm.s.fNestedPaging);
6689
6690	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6691
6692	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6693	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6694	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6695	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6696
6697	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
6698
6699	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6700	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
6701	if ( pVM->hm.s.fTprPatchingAllowed
6702	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6703	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6704	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6705	&& !CPUMIsGuestInLongModeEx(pCtx)
6706	&& !CPUMGetGuestCPL(pVCpu)
6707	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6708	{
6709	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6710	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6711
6712	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6713	{
6714	/* Only attempt to patch the instruction once. */
6715	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6716	if (!pPatch)
6717	return VINF_EM_HM_PATCH_TPR_INSTR;
6718	}
6719	}
6720	#endif
6721
6722	/*
6723	* Determine the nested paging mode.
6724	*/
6725	PGMMODE enmNestedPagingMode;
6726	#if HC_ARCH_BITS == 32
6727	if (CPUMIsGuestInLongModeEx(pCtx))
6728	enmNestedPagingMode = PGMMODE_AMD64_NX;
6729	else
6730	#endif
6731	enmNestedPagingMode = PGMGetHostMode(pVM);
6732
6733	/*
6734	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6735	*/
6736	int rc;
6737	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6738	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6739	{
6740	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
6741	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
6742	if (pVCpu->hm.s.Event.fPending)
6743	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6744
6745	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6746	u32ErrCode);
6747	rc = VBOXSTRICTRC_VAL(rc2);
6748
6749	/*
6750	* If we succeed, resume guest execution.
6751	* If we fail in interpreting the instruction because we couldn't get the guest physical address
6752	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
6753	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
6754	* weird case. See @bugref{6043}.
6755	*/
6756	if ( rc == VINF_SUCCESS
6757	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6758	\|\| rc == VERR_PAGE_NOT_PRESENT)
6759	{
6760	/* Successfully handled MMIO operation. */
6761	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6762	rc = VINF_SUCCESS;
6763	}
6764	return rc;
6765	}
6766
6767	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6768	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6769	TRPMResetTrap(pVCpu);
6770
6771	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6772
6773	/*
6774	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6775	*/
6776	if ( rc == VINF_SUCCESS
6777	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6778	\|\| rc == VERR_PAGE_NOT_PRESENT)
6779	{
6780	/* We've successfully synced our shadow page tables. */
6781	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6782	rc = VINF_SUCCESS;
6783	}
6784
6785	return rc;
6786	}
6787
6788
6789	/**
6790	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6791	* \#VMEXIT.
6792	*/
6793	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6794	{
6795	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6796
6797	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6798	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
6799	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;
6800
6801	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
6802	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
6803	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
6804
6805	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6806	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6807	return VINF_SUCCESS;
6808	}
6809
6810
6811	/**
6812	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6813	* \#VMEXIT.
6814	*/
6815	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6816	{
6817	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6818
6819	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6820
6821	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6822	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6823	#endif
6824
6825	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6826	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6827	{
6828	/*
6829	* AMD-V provides us with the exception which caused the TS; we collect
6830	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
6831	*/
6832	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
6833	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6834	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6835	}
6836
6837	/** @todo Emulate task switch someday, currently just going back to ring-3 for
6838	* emulation. */
6839	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6840	return VERR_EM_INTERPRETER;
6841	}
6842
6843
6844	/**
6845	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6846	*/
6847	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6848	{
6849	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6850	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
6851
6852	bool fRipUpdated;
6853	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
6854	if (RT_SUCCESS(rcStrict))
6855	{
6856	/* Only update the RIP if we're continuing guest execution and not
6857	in the case of say VINF_GIM_R3_HYPERCALL. */
6858	if ( rcStrict == VINF_SUCCESS
6859	&& !fRipUpdated)
6860	{
6861	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
6862	}
6863
6864	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
6865	we would need to reload the guest changed bits here before VM-entry. */
6866	return VBOXSTRICTRC_VAL(rcStrict);
6867	}
6868
6869	hmR0SvmSetPendingXcptUD(pVCpu);
6870	return VINF_SUCCESS;
6871	}
6872
6873
6874	/**
6875	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6876	*/
6877	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6878	{
6879	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6880	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
6881	return VINF_EM_RAW_INTERRUPT;
6882	}
6883
6884
6885	/**
6886	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
6887	*/
6888	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6889	{
6890	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6891
6892	/* Clear NMI blocking. */
6893	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6894
6895	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6896	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6897	hmR0SvmClearIretIntercept(pVmcb);
6898
6899	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6900	return VINF_SUCCESS;
6901	}
6902
6903
6904	/**
6905	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
6906	* Conditional \#VMEXIT.
6907	*/
6908	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6909	{
6910	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6911
6912	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6913
6914	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
6915	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6916	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6917	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
6918	PVM pVM = pVCpu->CTX_SUFF(pVM);
6919
6920	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
6921	if (pVM->hm.s.fNestedPaging)
6922	{
6923	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
6924	if (!pSvmTransient->fVectoringDoublePF)
6925	{
6926	/* A genuine guest #PF, reflect it to the guest. */
6927	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
6928	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
6929	uFaultAddress, u32ErrCode));
6930	}
6931	else
6932	{
6933	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
6934	hmR0SvmSetPendingXcptDF(pVCpu);
6935	Log4(("Pending #DF due to vectoring #PF. NP\n"));
6936	}
6937	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
6938	return VINF_SUCCESS;
6939	}
6940	#endif
6941
6942	Assert(!pVM->hm.s.fNestedPaging);
6943
6944	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6945	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
6946	if ( pVM->hm.s.fTprPatchingAllowed
6947	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
6948	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
6949	&& !CPUMIsGuestInLongModeEx(pCtx)
6950	&& !CPUMGetGuestCPL(pVCpu)
6951	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6952	{
6953	RTGCPHYS GCPhysApicBase;
6954	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6955	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6956
6957	/* Check if the page at the fault-address is the APIC base. */
6958	RTGCPHYS GCPhysPage;
6959	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
6960	if ( rc2 == VINF_SUCCESS
6961	&& GCPhysPage == GCPhysApicBase)
6962	{
6963	/* Only attempt to patch the instruction once. */
6964	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6965	if (!pPatch)
6966	return VINF_EM_HM_PATCH_TPR_INSTR;
6967	}
6968	}
6969	#endif
6970
6971	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
6972	pCtx->rip, u32ErrCode, pCtx->cr3));
6973
6974	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
6975	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
6976	if (pSvmTransient->fVectoringPF)
6977	{
6978	Assert(pVCpu->hm.s.Event.fPending);
6979	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6980	}
6981
6982	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
6983	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
6984
6985	Log4(("#PF rc=%Rrc\n", rc));
6986
6987	if (rc == VINF_SUCCESS)
6988	{
6989	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
6990	TRPMResetTrap(pVCpu);
6991	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6992	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6993	return rc;
6994	}
6995	else if (rc == VINF_EM_RAW_GUEST_TRAP)
6996	{
6997	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
6998
6999	if (!pSvmTransient->fVectoringDoublePF)
7000	{
7001	/* It's a guest page fault and needs to be reflected to the guest. */
7002	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7003	TRPMResetTrap(pVCpu);
7004	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7005	}
7006	else
7007	{
7008	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7009	TRPMResetTrap(pVCpu);
7010	hmR0SvmSetPendingXcptDF(pVCpu);
7011	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7012	}
7013
7014	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7015	return VINF_SUCCESS;
7016	}
7017
7018	TRPMResetTrap(pVCpu);
7019	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7020	return rc;
7021	}
7022
7023
7024	/**
7025	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
7026	* Conditional \#VMEXIT.
7027	*/
7028	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7029	{
7030	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7031
7032	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7033	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7034	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7035
7036	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7037	VMMRZCallRing3Disable(pVCpu);
7038	HM_DISABLE_PREEMPT();
7039
7040	int rc;
7041	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7042	if (pSvmTransient->fWasGuestFPUStateActive)
7043	{
7044	rc = VINF_EM_RAW_GUEST_TRAP;
7045	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7046	}
7047	else
7048	{
7049	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7050	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7051	#endif
7052	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7053	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7054	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7055	}
7056
7057	HM_RESTORE_PREEMPT();
7058	VMMRZCallRing3Enable(pVCpu);
7059
7060	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7061	{
7062	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7063	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7064	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7065	pVCpu->hm.s.fPreloadGuestFpu = true;
7066	}
7067	else
7068	{
7069	/* Forward #NM to the guest. */
7070	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7071	hmR0SvmSetPendingXcptNM(pVCpu);
7072	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7073	}
7074	return VINF_SUCCESS;
7075	}
7076
7077
7078	/**
7079	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7080	* Conditional \#VMEXIT.
7081	*/
7082	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7083	{
7084	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7085
7086	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7087	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7088	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7089
7090	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7091	if (pVCpu->hm.s.fGIMTrapXcptUD)
7092	{
7093	uint8_t cbInstr = 0;
7094	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7095	if (rcStrict == VINF_SUCCESS)
7096	{
7097	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7098	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7099	rc = VINF_SUCCESS;
7100	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7101	}
7102	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7103	rc = VINF_SUCCESS;
7104	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7105	rc = VINF_GIM_R3_HYPERCALL;
7106	else
7107	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7108	}
7109
7110	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7111	if (RT_FAILURE(rc))
7112	{
7113	hmR0SvmSetPendingXcptUD(pVCpu);
7114	rc = VINF_SUCCESS;
7115	}
7116
7117	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7118	return rc;
7119	}
7120
7121
7122	/**
7123	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7124	* Conditional \#VMEXIT.
7125	*/
7126	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7127	{
7128	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7129
7130	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7131	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7132	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7133
7134	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7135
7136	if (!(pCtx->cr0 & X86_CR0_NE))
7137	{
7138	PVM pVM = pVCpu->CTX_SUFF(pVM);
7139	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7140	unsigned cbOp;
7141	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7142	if (RT_SUCCESS(rc))
7143	{
7144	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7145	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7146	if (RT_SUCCESS(rc))
7147	pCtx->rip += cbOp;
7148	}
7149	else
7150	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7151	return rc;
7152	}
7153
7154	hmR0SvmSetPendingXcptMF(pVCpu);
7155	return VINF_SUCCESS;
7156	}
7157
7158
7159	/**
7160	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7161	* \#VMEXIT.
7162	*/
7163	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7164	{
7165	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7166
7167	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7168	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7169	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7170	{
7171	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7172	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7173	}
7174
7175	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7176
7177	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7178	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7179	PVM pVM = pVCpu->CTX_SUFF(pVM);
7180	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7181	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7182	if (rc == VINF_EM_RAW_GUEST_TRAP)
7183	{
7184	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7185	if (CPUMIsHyperDebugStateActive(pVCpu))
7186	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7187
7188	/* Reflect the exception back to the guest. */
7189	hmR0SvmSetPendingXcptDB(pVCpu);
7190	rc = VINF_SUCCESS;
7191	}
7192
7193	/*
7194	* Update DR6.
7195	*/
7196	if (CPUMIsHyperDebugStateActive(pVCpu))
7197	{
7198	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7199	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7200	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7201	}
7202	else
7203	{
7204	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7205	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7206	}
7207
7208	return rc;
7209	}
7210
7211
7212	/**
7213	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7214	* Conditional \#VMEXIT.
7215	*/
7216	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7217	{
7218	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7219
7220	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7221	* shutdown VMEXIT. */
7222	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7223
7224	SVMEVENT Event;
7225	Event.u = 0;
7226	Event.n.u1Valid = 1;
7227	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7228	Event.n.u8Vector = X86_XCPT_AC;
7229	Event.n.u1ErrorCodeValid = 1;
7230	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7231	return VINF_SUCCESS;
7232	}
7233
7234
7235	/**
7236	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7237	* Conditional \#VMEXIT.
7238	*/
7239	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7240	{
7241	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7242
7243	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7244
7245	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7246	if (rc == VINF_EM_RAW_GUEST_TRAP)
7247	{
7248	SVMEVENT Event;
7249	Event.u = 0;
7250	Event.n.u1Valid = 1;
7251	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7252	Event.n.u8Vector = X86_XCPT_BP;
7253	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7254	}
7255
7256	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7257	return rc;
7258	}
7259
7260
7261	#ifdef VBOX_WITH_NESTED_HWVIRT
7262	/**
7263	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7264	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7265	*/
7266	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7267	{
7268	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7269
7270	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7271
7272	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7273	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7274	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7275	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7276
7277	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7278	pCtx->rip, u32ErrCode, pCtx->cr3));
7279
7280	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7281	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7282	if (pSvmTransient->fVectoringPF)
7283	{
7284	Assert(pVCpu->hm.s.Event.fPending);
7285	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7286	}
7287
7288	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7289
7290	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7291	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7292
7293	Log4(("#PFNested: rc=%Rrc\n", rc));
7294
7295	if (rc == VINF_SUCCESS)
7296	{
7297	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7298	TRPMResetTrap(pVCpu);
7299	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7300	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7301	return rc;
7302	}
7303
7304	if (rc == VINF_EM_RAW_GUEST_TRAP)
7305	{
7306	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7307
7308	if (!pSvmTransient->fVectoringDoublePF)
7309	{
7310	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7311	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7312	TRPMResetTrap(pVCpu);
7313	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7314	}
7315	else
7316	{
7317	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7318	TRPMResetTrap(pVCpu);
7319	hmR0SvmSetPendingXcptDF(pVCpu);
7320	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7321	}
7322
7323	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7324	return VINF_SUCCESS;
7325	}
7326
7327	TRPMResetTrap(pVCpu);
7328	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7329	return rc;
7330	}
7331
7332
7333	/**
7334	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7335	*/
7336	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7337	{
7338	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7339
7340	/** @todo Stat. */
7341	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7342	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7343	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7344	return VBOXSTRICTRC_VAL(rcStrict);
7345	}
7346
7347
7348	/**
7349	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7350	*/
7351	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7352	{
7353	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7354
7355	/** @todo Stat. */
7356	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7357	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7358	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7359	return VBOXSTRICTRC_VAL(rcStrict);
7360	}
7361
7362
7363	/**
7364	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7365	*/
7366	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7367	{
7368	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7369
7370	/** @todo Stat. */
7371	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7372	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7373	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7374	if (rcStrict == VINF_SUCCESS)
7375	{
7376	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7377	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7378	\| HM_CHANGED_GUEST_TR
7379	\| HM_CHANGED_GUEST_LDTR);
7380	}
7381	return VBOXSTRICTRC_VAL(rcStrict);
7382	}
7383
7384
7385	/**
7386	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7387	*/
7388	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7389	{
7390	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7391
7392	/** @todo Stat. */
7393	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7394	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7395	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7396	return VBOXSTRICTRC_VAL(rcStrict);
7397	}
7398
7399
7400	/**
7401	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7402	*/
7403	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7404	{
7405	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7406	/** @todo Stat. */
7407	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7408	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7409	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7410	return VBOXSTRICTRC_VAL(rcStrict);
7411	}
7412
7413
7414	/**
7415	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7416	*/
7417	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7418	{
7419	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7420	/** @todo Stat. */
7421	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7422	#if 0
7423	VBOXSTRICTRC rcStrict;
7424	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7425	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7426	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7427	if (rcStrict == VINF_SUCCESS)
7428	{
7429	rcStrict = VINF_SVM_VMRUN;
7430	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7431	}
7432	return VBOXSTRICTRC_VAL(rcStrict);
7433	#endif
7434	return VERR_EM_INTERPRETER;
7435	}
7436
7437
7438	/**
7439	* Nested-guest \#VMEXIT handler for IRET (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7440	*/
7441	HMSVM_EXIT_DECL hmR0SvmNestedExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7442	{
7443	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7444
7445	/* Clear NMI blocking. */
7446	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7447
7448	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7449	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
7450	hmR0SvmClearIretIntercept(pVmcbNstGst);
7451
7452	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEventNested() and resume guest execution. */
7453	return VINF_SUCCESS;
7454	}
7455
7456
7457	/**
7458	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7459	* Unconditional \#VMEXIT.
7460	*/
7461	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7462	{
7463	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7464
7465	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7466	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7467	* shutdown VMEXIT. */
7468	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7469	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7470	{
7471	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7472	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7473	}
7474
7475	hmR0SvmSetPendingXcptDB(pVCpu);
7476	return VINF_SUCCESS;
7477	}
7478
7479
7480	/**
7481	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7482	* Conditional \#VMEXIT.
7483	*/
7484	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7485	{
7486	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7487
7488	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7489	* shutdown VMEXIT. */
7490	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7491
7492	SVMEVENT Event;
7493	Event.u = 0;
7494	Event.n.u1Valid = 1;
7495	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7496	Event.n.u8Vector = X86_XCPT_BP;
7497	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7498	return VINF_SUCCESS;
7499	}
7500
7501	#endif /* VBOX_WITH_NESTED_HWVIRT */
7502
7503
7504	/** @} */
7505

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 69786

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