HMSVMR0.cpp@ 70408

Last change on this file since 70408 was 70408, checked in by vboxsync, 7 years ago
VMM/HMSVMR0: Clean up.
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1	/* $Id: HMSVMR0.cpp 70408 2018-01-02 04:56:56Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#define HMSVM_USE_IEM_EVENT_REFLECTION
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
43	# define HMSVM_ALWAYS_TRAP_PF
44	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
45	#endif
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	#ifdef VBOX_WITH_STATISTICS
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
53	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
54	if ((u64ExitCode) == SVM_EXIT_NPF) \
55	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
56	else \
57	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
58	} while (0)
59	#else
60	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
61	#endif
62
63	/** If we decide to use a function table approach this can be useful to
64	* switch to a "static DECLCALLBACK(int)". */
65	#define HMSVM_EXIT_DECL static int
66
67	/** Macro for checking and returning from the using function for
68	* \#VMEXIT intercepts that maybe caused during delivering of another
69	* event in the guest. */
70	#ifdef VBOX_WITH_NESTED_HWVIRT
71	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
72	do \
73	{ \
74	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
75	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
76	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
77	else if ( rc == VINF_EM_RESET \
78	&& CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
79	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_SHUTDOWN, 0, 0)); \
80	else \
81	return rc; \
82	} while (0)
83	#else
84	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
85	do \
86	{ \
87	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
88	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
89	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
90	else \
91	return rc; \
92	} while (0)
93	#endif
94
95	/**
96	* Updates interrupt shadow for the current RIP.
97	*/
98	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
99	do { \
100	/* Update interrupt shadow. */ \
101	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
102	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
103	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
104	} while (0)
105
106	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
107	* instruction that exited. */
108	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
109	do { \
110	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
111	(a_rc) = VINF_EM_DBG_STEPPED; \
112	} while (0)
113
114	/** Assert that preemption is disabled or covered by thread-context hooks. */
115	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
116	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
117
118	/** Assert that we haven't migrated CPUs when thread-context hooks are not
119	* used. */
120	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
121	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
122	("Illegal migration! Entered on CPU %u Current %u\n", \
123	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
124
125	/** Assert that we're not executing a nested-guest. */
126	#ifdef VBOX_WITH_NESTED_HWVIRT
127	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
128	#else
129	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
130	#endif
131
132	/** Assert that we're executing a nested-guest. */
133	#ifdef VBOX_WITH_NESTED_HWVIRT
134	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
135	#else
136	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
137	#endif
138
139	/**
140	* Exception bitmap mask for all contributory exceptions.
141	*
142	* Page fault is deliberately excluded here as it's conditional as to whether
143	* it's contributory or benign. Page faults are handled separately.
144	*/
145	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
146	\| RT_BIT(X86_XCPT_DE))
147
148	/**
149	* Mandatory/unconditional guest control intercepts.
150	*
151	* SMIs can and do happen in normal operation. We need not intercept them
152	* while executing the guest or nested-guest.
153	*/
154	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
155	\| SVM_CTRL_INTERCEPT_NMI \
156	\| SVM_CTRL_INTERCEPT_INIT \
157	\| SVM_CTRL_INTERCEPT_RDPMC \
158	\| SVM_CTRL_INTERCEPT_CPUID \
159	\| SVM_CTRL_INTERCEPT_RSM \
160	\| SVM_CTRL_INTERCEPT_HLT \
161	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
162	\| SVM_CTRL_INTERCEPT_MSR_PROT \
163	\| SVM_CTRL_INTERCEPT_INVLPGA \
164	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
165	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
166	\| SVM_CTRL_INTERCEPT_VMRUN \
167	\| SVM_CTRL_INTERCEPT_VMMCALL \
168	\| SVM_CTRL_INTERCEPT_VMLOAD \
169	\| SVM_CTRL_INTERCEPT_VMSAVE \
170	\| SVM_CTRL_INTERCEPT_STGI \
171	\| SVM_CTRL_INTERCEPT_CLGI \
172	\| SVM_CTRL_INTERCEPT_SKINIT \
173	\| SVM_CTRL_INTERCEPT_WBINVD \
174	\| SVM_CTRL_INTERCEPT_MONITOR \
175	\| SVM_CTRL_INTERCEPT_MWAIT \
176	\| SVM_CTRL_INTERCEPT_XSETBV)
177
178	/** @name VMCB Clean Bits.
179	*
180	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
181	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
182	* memory.
183	*
184	* @{ */
185	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
186	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
187	/** I/O permission bitmap, MSR permission bitmap. */
188	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
189	/** ASID. */
190	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
191	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
192	V_INTR_VECTOR. */
193	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
194	/** Nested Paging: Nested CR3 (nCR3), PAT. */
195	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
196	/** Control registers (CR0, CR3, CR4, EFER). */
197	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
198	/** Debug registers (DR6, DR7). */
199	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
200	/** GDT, IDT limit and base. */
201	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
202	/** Segment register: CS, SS, DS, ES limit and base. */
203	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
204	/** CR2.*/
205	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
206	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
207	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
208	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
209	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
210	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
211	/** Mask of all valid VMCB Clean bits. */
212	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
213	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
214	\| HMSVM_VMCB_CLEAN_ASID \
215	\| HMSVM_VMCB_CLEAN_TPR \
216	\| HMSVM_VMCB_CLEAN_NP \
217	\| HMSVM_VMCB_CLEAN_CRX_EFER \
218	\| HMSVM_VMCB_CLEAN_DRX \
219	\| HMSVM_VMCB_CLEAN_DT \
220	\| HMSVM_VMCB_CLEAN_SEG \
221	\| HMSVM_VMCB_CLEAN_CR2 \
222	\| HMSVM_VMCB_CLEAN_LBR \
223	\| HMSVM_VMCB_CLEAN_AVIC)
224	/** @} */
225
226	/** @name SVM transient.
227	*
228	* A state structure for holding miscellaneous information across AMD-V
229	* VMRUN/\#VMEXIT operation, restored after the transition.
230	*
231	* @{ */
232	typedef struct SVMTRANSIENT
233	{
234	/** The host's rflags/eflags. */
235	RTCCUINTREG fEFlags;
236	#if HC_ARCH_BITS == 32
237	uint32_t u32Alignment0;
238	#endif
239
240	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
241	uint64_t u64ExitCode;
242	/** The guest's TPR value used for TPR shadowing. */
243	uint8_t u8GuestTpr;
244	/** Alignment. */
245	uint8_t abAlignment0[7];
246
247	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
248	bool fWasGuestFPUStateActive;
249	/** Whether the guest debug state was active at the time of \#VMEXIT. */
250	bool fWasGuestDebugStateActive;
251	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
252	bool fWasHyperDebugStateActive;
253	/** Whether the TSC offset mode needs to be updated. */
254	bool fUpdateTscOffsetting;
255	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
256	bool fRestoreTscAuxMsr;
257	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
258	* contributary exception or a page-fault. */
259	bool fVectoringDoublePF;
260	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
261	* external interrupt or NMI. */
262	bool fVectoringPF;
263	} SVMTRANSIENT, *PSVMTRANSIENT;
264	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
265	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
266	/** @} */
267
268	/**
269	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
270	*/
271	typedef enum SVMMSREXITREAD
272	{
273	/** Reading this MSR causes a \#VMEXIT. */
274	SVMMSREXIT_INTERCEPT_READ = 0xb,
275	/** Reading this MSR does not cause a \#VMEXIT. */
276	SVMMSREXIT_PASSTHRU_READ
277	} SVMMSREXITREAD;
278
279	/**
280	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
281	*/
282	typedef enum SVMMSREXITWRITE
283	{
284	/** Writing to this MSR causes a \#VMEXIT. */
285	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
286	/** Writing to this MSR does not cause a \#VMEXIT. */
287	SVMMSREXIT_PASSTHRU_WRITE
288	} SVMMSREXITWRITE;
289
290	/**
291	* SVM \#VMEXIT handler.
292	*
293	* @returns VBox status code.
294	* @param pVCpu The cross context virtual CPU structure.
295	* @param pMixedCtx Pointer to the guest-CPU context.
296	* @param pSvmTransient Pointer to the SVM-transient structure.
297	*/
298	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
299
300
301	/*********************************************************************************************************************************
302	* Internal Functions *
303	*********************************************************************************************************************************/
304	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
305	SVMMSREXITWRITE enmWrite);
306	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
307	static void hmR0SvmLeave(PVMCPU pVCpu);
308
309	/** @name \#VMEXIT handlers.
310	* @{
311	*/
312	static FNSVMEXITHANDLER hmR0SvmExitIntr;
313	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
314	static FNSVMEXITHANDLER hmR0SvmExitInvd;
315	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
316	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
317	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
318	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
319	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
320	static FNSVMEXITHANDLER hmR0SvmExitHlt;
321	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
322	static FNSVMEXITHANDLER hmR0SvmExitMwait;
323	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
324	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
325	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
326	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
327	static FNSVMEXITHANDLER hmR0SvmExitMsr;
328	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
329	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
330	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
331	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
332	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
333	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
334	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
335	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
336	static FNSVMEXITHANDLER hmR0SvmExitPause;
337	static FNSVMEXITHANDLER hmR0SvmExitIret;
338	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
339	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
340	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
341	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
342	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
343	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
344	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
345	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
346	#ifdef VBOX_WITH_NESTED_HWVIRT
347	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
348	static FNSVMEXITHANDLER hmR0SvmExitClgi;
349	static FNSVMEXITHANDLER hmR0SvmExitStgi;
350	static FNSVMEXITHANDLER hmR0SvmExitVmload;
351	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
352	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
353	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
354	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
355	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
356	#endif
357	/** @} */
358
359	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
360	#ifdef VBOX_WITH_NESTED_HWVIRT
361	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
362	#endif
363
364
365	/*********************************************************************************************************************************
366	* Global Variables *
367	*********************************************************************************************************************************/
368	/** Ring-0 memory object for the IO bitmap. */
369	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
370	/** Physical address of the IO bitmap. */
371	RTHCPHYS g_HCPhysIOBitmap = 0;
372	/** Pointer to the IO bitmap. */
373	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
374
375	#ifdef VBOX_WITH_NESTED_HWVIRT
376	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
377	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
378	/** Physical address of the nested-guest MSRPM bitmap. */
379	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
380	/** Pointer to the nested-guest MSRPM bitmap. */
381	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
382	#endif
383
384	/**
385	* Sets up and activates AMD-V on the current CPU.
386	*
387	* @returns VBox status code.
388	* @param pCpu Pointer to the CPU info struct.
389	* @param pVM The cross context VM structure. Can be
390	* NULL after a resume!
391	* @param pvCpuPage Pointer to the global CPU page.
392	* @param HCPhysCpuPage Physical address of the global CPU page.
393	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
394	* @param pvArg Unused on AMD-V.
395	*/
396	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
397	void *pvArg)
398	{
399	Assert(!fEnabledByHost);
400	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
401	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
402	Assert(pvCpuPage); NOREF(pvCpuPage);
403	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
404
405	NOREF(pvArg);
406	NOREF(fEnabledByHost);
407
408	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
409	RTCCUINTREG fEFlags = ASMIntDisableFlags();
410
411	/*
412	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
413	*/
414	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
415	if (u64HostEfer & MSR_K6_EFER_SVME)
416	{
417	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
418	if ( pVM
419	&& pVM->hm.s.svm.fIgnoreInUseError)
420	{
421	pCpu->fIgnoreAMDVInUseError = true;
422	}
423
424	if (!pCpu->fIgnoreAMDVInUseError)
425	{
426	ASMSetFlags(fEFlags);
427	return VERR_SVM_IN_USE;
428	}
429	}
430
431	/* Turn on AMD-V in the EFER MSR. */
432	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
433
434	/* Write the physical page address where the CPU will store the host state while executing the VM. */
435	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
436
437	/* Restore interrupts. */
438	ASMSetFlags(fEFlags);
439
440	/*
441	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
442	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
443	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
444	* guest code.
445	*/
446	pCpu->fFlushAsidBeforeUse = true;
447
448	/*
449	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
450	*/
451	++pCpu->cTlbFlushes;
452
453	return VINF_SUCCESS;
454	}
455
456
457	/**
458	* Deactivates AMD-V on the current CPU.
459	*
460	* @returns VBox status code.
461	* @param pCpu Pointer to the CPU info struct.
462	* @param pvCpuPage Pointer to the global CPU page.
463	* @param HCPhysCpuPage Physical address of the global CPU page.
464	*/
465	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
466	{
467	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
468	AssertReturn( HCPhysCpuPage
469	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
470	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
471	NOREF(pCpu);
472
473	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
474	RTCCUINTREG fEFlags = ASMIntDisableFlags();
475
476	/* Turn off AMD-V in the EFER MSR. */
477	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
478	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
479
480	/* Invalidate host state physical address. */
481	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
482
483	/* Restore interrupts. */
484	ASMSetFlags(fEFlags);
485
486	return VINF_SUCCESS;
487	}
488
489
490	/**
491	* Does global AMD-V initialization (called during module initialization).
492	*
493	* @returns VBox status code.
494	*/
495	VMMR0DECL(int) SVMR0GlobalInit(void)
496	{
497	/*
498	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
499	* once globally here instead of per-VM.
500	*/
501	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
502	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
503	if (RT_FAILURE(rc))
504	return rc;
505
506	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
507	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
508
509	/* Set all bits to intercept all IO accesses. */
510	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
511
512	#ifdef VBOX_WITH_NESTED_HWVIRT
513	/*
514	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
515	*/
516	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
517	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
518	if (RT_FAILURE(rc))
519	return rc;
520
521	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
522	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
523
524	/* Set all bits to intercept all MSR accesses. */
525	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
526	#endif
527
528	return VINF_SUCCESS;
529	}
530
531
532	/**
533	* Does global AMD-V termination (called during module termination).
534	*/
535	VMMR0DECL(void) SVMR0GlobalTerm(void)
536	{
537	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
538	{
539	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
540	g_pvIOBitmap = NULL;
541	g_HCPhysIOBitmap = 0;
542	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
543	}
544
545	#ifdef VBOX_WITH_NESTED_HWVIRT
546	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
547	{
548	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
549	g_pvNstGstMsrBitmap = NULL;
550	g_HCPhysNstGstMsrBitmap = 0;
551	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
552	}
553	#endif
554	}
555
556
557	/**
558	* Frees any allocated per-VCPU structures for a VM.
559	*
560	* @param pVM The cross context VM structure.
561	*/
562	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
563	{
564	for (uint32_t i = 0; i < pVM->cCpus; i++)
565	{
566	PVMCPU pVCpu = &pVM->aCpus[i];
567	AssertPtr(pVCpu);
568
569	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
570	{
571	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
572	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
573	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
574	}
575
576	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
577	{
578	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
579	pVCpu->hm.s.svm.pVmcb = NULL;
580	pVCpu->hm.s.svm.HCPhysVmcb = 0;
581	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
582	}
583
584	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
585	{
586	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
587	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
588	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
589	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
590	}
591	}
592	}
593
594
595	/**
596	* Does per-VM AMD-V initialization.
597	*
598	* @returns VBox status code.
599	* @param pVM The cross context VM structure.
600	*/
601	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
602	{
603	int rc = VERR_INTERNAL_ERROR_5;
604
605	/*
606	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
607	*/
608	uint32_t u32Family;
609	uint32_t u32Model;
610	uint32_t u32Stepping;
611	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
612	{
613	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
614	pVM->hm.s.svm.fAlwaysFlushTLB = true;
615	}
616
617	/*
618	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
619	*/
620	for (VMCPUID i = 0; i < pVM->cCpus; i++)
621	{
622	PVMCPU pVCpu = &pVM->aCpus[i];
623	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
624	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
625	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
626	}
627
628	for (VMCPUID i = 0; i < pVM->cCpus; i++)
629	{
630	PVMCPU pVCpu = &pVM->aCpus[i];
631
632	/*
633	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
634	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
635	*/
636	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
637	if (RT_FAILURE(rc))
638	goto failure_cleanup;
639
640	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
641	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
642	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
643	ASMMemZeroPage(pvVmcbHost);
644
645	/*
646	* Allocate one page for the guest-state VMCB.
647	*/
648	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
649	if (RT_FAILURE(rc))
650	goto failure_cleanup;
651
652	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
653	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
654	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
655	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
656
657	/*
658	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
659	* SVM to not require one.
660	*/
661	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
662	false /* fExecutable */);
663	if (RT_FAILURE(rc))
664	goto failure_cleanup;
665
666	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
667	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
668	/* Set all bits to intercept all MSR accesses (changed later on). */
669	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
670	}
671
672	return VINF_SUCCESS;
673
674	failure_cleanup:
675	hmR0SvmFreeStructs(pVM);
676	return rc;
677	}
678
679
680	/**
681	* Does per-VM AMD-V termination.
682	*
683	* @returns VBox status code.
684	* @param pVM The cross context VM structure.
685	*/
686	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
687	{
688	hmR0SvmFreeStructs(pVM);
689	return VINF_SUCCESS;
690	}
691
692
693	/**
694	* Returns whether the VMCB Clean Bits feature is supported.
695	*
696	* @return @c true if supported, @c false otherwise.
697	* @param pVCpu The cross context virtual CPU structure.
698	* @param pCtx Pointer to the guest-CPU context.
699	*/
700	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu, PCPUMCTX pCtx)
701	{
702	PVM pVM = pVCpu->CTX_SUFF(pVM);
703	#ifdef VBOX_WITH_NESTED_HWVIRT
704	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
705	{
706	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
707	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
708	}
709	#else
710	RT_NOREF(pCtx);
711	#endif
712	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
713	}
714
715
716	/**
717	* Returns whether the decode assists feature is supported.
718	*
719	* @return @c true if supported, @c false otherwise.
720	* @param pVCpu The cross context virtual CPU structure.
721	* @param pCtx Pointer to the guest-CPU context.
722	*/
723	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu, PCPUMCTX pCtx)
724	{
725	PVM pVM = pVCpu->CTX_SUFF(pVM);
726	#ifdef VBOX_WITH_NESTED_HWVIRT
727	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
728	{
729	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
730	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
731	}
732	#else
733	RT_NOREF(pCtx);
734	#endif
735	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
736	}
737
738
739	/**
740	* Returns whether the NRIP_SAVE feature is supported.
741	*
742	* @return @c true if supported, @c false otherwise.
743	* @param pVCpu The cross context virtual CPU structure.
744	* @param pCtx Pointer to the guest-CPU context.
745	*/
746	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu, PCPUMCTX pCtx)
747	{
748	PVM pVM = pVCpu->CTX_SUFF(pVM);
749	#ifdef VBOX_WITH_NESTED_HWVIRT
750	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
751	{
752	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
753	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
754	}
755	#else
756	RT_NOREF(pCtx);
757	#endif
758	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
759	}
760
761
762	/**
763	* Sets the permission bits for the specified MSR in the MSRPM.
764	*
765	* @param pVmcb Pointer to the VM control block.
766	* @param pbMsrBitmap Pointer to the MSR bitmap.
767	* @param uMsr The MSR for which the access permissions are being set.
768	* @param enmRead MSR read permissions.
769	* @param enmWrite MSR write permissions.
770	*/
771	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
772	SVMMSREXITWRITE enmWrite)
773	{
774	uint16_t offMsrpm;
775	uint32_t uMsrpmBit;
776	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
777	AssertRC(rc);
778
779	Assert(uMsrpmBit < 0x3fff);
780	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
781
782	pbMsrBitmap += offMsrpm;
783	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
784	ASMBitSet(pbMsrBitmap, uMsrpmBit);
785	else
786	ASMBitClear(pbMsrBitmap, uMsrpmBit);
787
788	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
789	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
790	else
791	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
792
793	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
794	}
795
796
797	/**
798	* Sets up AMD-V for the specified VM.
799	* This function is only called once per-VM during initalization.
800	*
801	* @returns VBox status code.
802	* @param pVM The cross context VM structure.
803	*/
804	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
805	{
806	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
807	AssertReturn(pVM, VERR_INVALID_PARAMETER);
808	Assert(pVM->hm.s.svm.fSupported);
809
810	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
811	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
812	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
813
814	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
815	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM etc. */
816
817	for (VMCPUID i = 0; i < pVM->cCpus; i++)
818	{
819	PVMCPU pVCpu = &pVM->aCpus[i];
820	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
821
822	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
823
824	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
825	Assert(!pVCpu->hm.s.idxExitHistoryFree);
826	HMCPU_EXIT_HISTORY_RESET(pVCpu);
827
828	/* Always trap #AC for reasons of security. */
829	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
830
831	/* Always trap #DB for reasons of security. */
832	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
833
834	/* Trap exceptions unconditionally (debug purposes). */
835	#ifdef HMSVM_ALWAYS_TRAP_PF
836	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
837	#endif
838	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
839	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
840	pVmcb->ctrl.u32InterceptXcpt \|= 0
841	\| RT_BIT(X86_XCPT_BP)
842	\| RT_BIT(X86_XCPT_DE)
843	\| RT_BIT(X86_XCPT_NM)
844	\| RT_BIT(X86_XCPT_UD)
845	\| RT_BIT(X86_XCPT_NP)
846	\| RT_BIT(X86_XCPT_SS)
847	\| RT_BIT(X86_XCPT_GP)
848	\| RT_BIT(X86_XCPT_PF)
849	\| RT_BIT(X86_XCPT_MF)
850	;
851	#endif
852
853	/* Set up unconditional intercepts and conditions. */
854	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
855
856	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
857	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
858
859	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
860	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
861
862	/* Intercept all DRx reads and writes by default. Changed later on. */
863	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
864	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
865
866	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
867	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
868
869	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
870	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
871	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
872
873	/* Set IO and MSR bitmap permission bitmap physical addresses. */
874	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
875	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
876
877	/* LBR virtualization. */
878	if (fUseLbrVirt)
879	{
880	pVmcb->ctrl.LbrVirt.n.u1LbrVirt = fUseLbrVirt;
881	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
882	}
883	else
884	Assert(pVmcb->ctrl.LbrVirt.n.u1LbrVirt == 0);
885
886	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
887	Assert(pVmcb->ctrl.u32VmcbCleanBits == 0);
888
889	/* The host ASID MBZ, for the guest start with 1. */
890	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
891
892	/*
893	* Setup the PAT MSR (applicable for Nested Paging only).
894	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
895	* so choose type 6 for all PAT slots.
896	*/
897	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
898
899	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
900	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
901
902	/* Without Nested Paging, we need additionally intercepts. */
903	if (!pVM->hm.s.fNestedPaging)
904	{
905	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
906	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
907	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
908
909	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
910	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
911	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
912
913	/* Page faults must be intercepted to implement shadow paging. */
914	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
915	}
916
917	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
918	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
919	#endif
920
921	/* Apply the exceptions intercepts needed by the GIM provider. */
922	if (pVCpu->hm.s.fGIMTrapXcptUD)
923	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
924
925	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
926	if (fUsePauseFilter)
927	{
928	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
929	if (fPauseFilterThreshold)
930	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
931	}
932
933	/*
934	* The following MSRs are saved/restored automatically during the world-switch.
935	* Don't intercept guest read/write accesses to these MSRs.
936	*/
937	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
938	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
939	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
940	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
941	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
942	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
943	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
944	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
945	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
946	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
947	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
948	}
949
950	return VINF_SUCCESS;
951	}
952
953
954	/**
955	* Gets a pointer to the currently active guest or nested-guest VMCB.
956	*
957	* @returns Pointer to the current context VMCB.
958	* @param pVCpu The cross context virtual CPU structure.
959	* @param pCtx Pointer to the guest-CPU context.
960	*/
961	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
962	{
963	#ifdef VBOX_WITH_NESTED_HWVIRT
964	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
965	return pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
966	#else
967	RT_NOREF(pCtx);
968	#endif
969	return pVCpu->hm.s.svm.pVmcb;
970	}
971
972
973	/**
974	* Invalidates a guest page by guest virtual address.
975	*
976	* @returns VBox status code.
977	* @param pVM The cross context VM structure.
978	* @param pVCpu The cross context virtual CPU structure.
979	* @param GCVirt Guest virtual address of the page to invalidate.
980	*/
981	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
982	{
983	AssertReturn(pVM, VERR_INVALID_PARAMETER);
984	Assert(pVM->hm.s.svm.fSupported);
985
986	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
987
988	/* Skip it if a TLB flush is already pending. */
989	if (!fFlushPending)
990	{
991	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
992
993	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
994	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
995	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
996
997	#if HC_ARCH_BITS == 32
998	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
999	if (CPUMIsGuestInLongMode(pVCpu))
1000	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1001	else
1002	#endif
1003	{
1004	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1005	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1006	}
1007	}
1008	return VINF_SUCCESS;
1009	}
1010
1011
1012	/**
1013	* Flushes the appropriate tagged-TLB entries.
1014	*
1015	* @param pVCpu The cross context virtual CPU structure.
1016	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
1017	* @param pVmcb Pointer to the VM control block.
1018	*/
1019	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
1020	{
1021	#ifndef VBOX_WITH_NESTED_HWVIRT
1022	RT_NOREF(pCtx);
1023	#endif
1024
1025	PVM pVM = pVCpu->CTX_SUFF(pVM);
1026	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
1027
1028	/*
1029	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1030	* This can happen both for start & resume due to long jumps back to ring-3.
1031	*
1032	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no correlation
1033	* between it and the physical CPU.
1034	*
1035	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1036	* so we cannot reuse the ASIDs without flushing.
1037	*/
1038	bool fNewAsid = false;
1039	Assert(pCpu->idCpu != NIL_RTCPUID);
1040	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1041	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes
1042	#ifdef VBOX_WITH_NESTED_HWVIRT
1043	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1044	#endif
1045	)
1046	{
1047	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1048	pVCpu->hm.s.fForceTLBFlush = true;
1049	fNewAsid = true;
1050	}
1051
1052	/* Set TLB flush state as checked until we return from the world switch. */
1053	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1054
1055	/* Check for explicit TLB flushes. */
1056	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1057	{
1058	pVCpu->hm.s.fForceTLBFlush = true;
1059	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1060	}
1061
1062	/*
1063	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1064	* This Host CPU requirement takes precedence.
1065	*/
1066	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1067	{
1068	pCpu->uCurrentAsid = 1;
1069	pVCpu->hm.s.uCurrentAsid = 1;
1070	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1071	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1072
1073	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1074	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1075
1076	/* Keep track of last CPU ID even when flushing all the time. */
1077	if (fNewAsid)
1078	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1079	}
1080	else
1081	{
1082	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1083	if (pVCpu->hm.s.fForceTLBFlush)
1084	{
1085	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1086	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1087
1088	if (fNewAsid)
1089	{
1090	++pCpu->uCurrentAsid;
1091
1092	bool fHitASIDLimit = false;
1093	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1094	{
1095	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1096	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1097	fHitASIDLimit = true;
1098	}
1099
1100	if ( fHitASIDLimit
1101	\|\| pCpu->fFlushAsidBeforeUse)
1102	{
1103	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1104	pCpu->fFlushAsidBeforeUse = false;
1105	}
1106
1107	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1108	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1109	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1110	}
1111	else
1112	{
1113	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1114	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1115	else
1116	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1117	}
1118
1119	pVCpu->hm.s.fForceTLBFlush = false;
1120	}
1121	}
1122
1123	/* Update VMCB with the ASID. */
1124	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1125	{
1126	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1127	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1128	}
1129
1130	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
1131	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1132	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1133	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1134	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1135	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1136	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1137	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1138
1139	#ifdef VBOX_WITH_STATISTICS
1140	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1141	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1142	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1143	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1144	{
1145	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1146	}
1147	else
1148	{
1149	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1150	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1151	}
1152	#endif
1153	}
1154
1155
1156	/** @name 64-bit guest on 32-bit host OS helper functions.
1157	*
1158	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1159	* mode (code segment, paging). These wrappers/helpers perform the necessary
1160	* bits for the 32->64 switcher.
1161	*
1162	* @{ */
1163	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1164	/**
1165	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1166	*
1167	* @returns VBox status code.
1168	* @param HCPhysVmcbHost Physical address of host VMCB.
1169	* @param HCPhysVmcb Physical address of the VMCB.
1170	* @param pCtx Pointer to the guest-CPU context.
1171	* @param pVM The cross context VM structure.
1172	* @param pVCpu The cross context virtual CPU structure.
1173	*/
1174	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1175	{
1176	uint32_t aParam[8];
1177	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1178	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1179	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1180	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1181	aParam[4] = VM_RC_ADDR(pVM, pVM);
1182	aParam[5] = 0;
1183	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1184	aParam[7] = 0;
1185
1186	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1187	}
1188
1189
1190	/**
1191	* Executes the specified VMRUN handler in 64-bit mode.
1192	*
1193	* @returns VBox status code.
1194	* @param pVM The cross context VM structure.
1195	* @param pVCpu The cross context virtual CPU structure.
1196	* @param pCtx Pointer to the guest-CPU context.
1197	* @param enmOp The operation to perform.
1198	* @param cParams Number of parameters.
1199	* @param paParam Array of 32-bit parameters.
1200	*/
1201	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1202	uint32_t cParams, uint32_t *paParam)
1203	{
1204	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1205	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1206
1207	NOREF(pCtx);
1208
1209	/* Disable interrupts. */
1210	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1211
1212	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1213	RTCPUID idHostCpu = RTMpCpuId();
1214	CPUMR0SetLApic(pVCpu, idHostCpu);
1215	#endif
1216
1217	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1218	CPUMSetHyperEIP(pVCpu, enmOp);
1219	for (int i = (int)cParams - 1; i >= 0; i--)
1220	CPUMPushHyper(pVCpu, paParam[i]);
1221
1222	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1223	/* Call the switcher. */
1224	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1225	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1226
1227	/* Restore interrupts. */
1228	ASMSetFlags(uOldEFlags);
1229	return rc;
1230	}
1231
1232	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1233	/** @} */
1234
1235
1236	/**
1237	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1238	* the corresponding VMCB Clean bit.
1239	*
1240	* @param pVmcb Pointer to the VM control block.
1241	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1242	*/
1243	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1244	{
1245	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1246	{
1247	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1248	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1249	}
1250	}
1251
1252
1253	/**
1254	* Removes an exception from the intercept-exception bitmap in the VMCB and
1255	* updates the corresponding VMCB Clean bit.
1256	*
1257	* @param pVCpu The cross context virtual CPU structure.
1258	* @param pCtx Pointer to the guest-CPU context.
1259	* @param pVmcb Pointer to the VM control block.
1260	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1261	*
1262	* @remarks This takes into account if we're executing a nested-guest and only
1263	* removes the exception intercept if both the guest -and- nested-guest
1264	* are not intercepting it.
1265	*/
1266	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint32_t u32Xcpt)
1267	{
1268	Assert(u32Xcpt != X86_XCPT_DB);
1269	Assert(u32Xcpt != X86_XCPT_AC);
1270	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1271	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1272	{
1273	bool fRemoveXcpt = true;
1274	#ifdef VBOX_WITH_NESTED_HWVIRT
1275	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1276	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1277	{
1278	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
1279	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
1280	fRemoveXcpt = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(u32Xcpt));
1281	}
1282	#else
1283	RT_NOREF2(pVCpu, pCtx);
1284	#endif
1285	if (fRemoveXcpt)
1286	{
1287	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1288	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1289	}
1290	}
1291	#else
1292	RT_NOREF3(pVCpu, pCtx, pVmcb);
1293	#endif
1294	}
1295
1296
1297	/**
1298	* Loads the guest (or nested-guest) CR0 control register into the guest-state
1299	* area in the VMCB.
1300	*
1301	* Although the guest CR0 is a separate field in the VMCB we have to consider
1302	* the FPU state itself which is shared between the host and the guest.
1303	*
1304	* @returns VBox status code.
1305	* @param pVCpu The cross context virtual CPU structure.
1306	* @param pVmcb Pointer to the VM control block.
1307	* @param pCtx Pointer to the guest-CPU context.
1308	*
1309	* @remarks No-long-jump zone!!!
1310	*/
1311	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1312	{
1313	uint64_t u64GuestCR0 = pCtx->cr0;
1314
1315	/* Always enable caching. */
1316	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1317
1318	/*
1319	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1320	*/
1321	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1322	{
1323	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1324	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1325	}
1326
1327	/*
1328	* Guest FPU bits.
1329	*/
1330	bool fInterceptNM = false;
1331	bool fInterceptMF = false;
1332	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1333	if (CPUMIsGuestFPUStateActive(pVCpu))
1334	{
1335	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1336	if (!(pCtx->cr0 & X86_CR0_NE))
1337	{
1338	Log4(("hmR0SvmLoadSharedCR0: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1339	fInterceptMF = true;
1340	}
1341	}
1342	else
1343	{
1344	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1345	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1346	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1347	}
1348
1349	/*
1350	* Update the exception intercept bitmap.
1351	*/
1352	if (fInterceptNM)
1353	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1354	else
1355	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_NM);
1356
1357	if (fInterceptMF)
1358	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1359	else
1360	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_MF);
1361
1362	pVmcb->guest.u64CR0 = u64GuestCR0;
1363	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1364	}
1365
1366
1367	/**
1368	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1369	*
1370	* @returns VBox status code.
1371	* @param pVCpu The cross context virtual CPU structure.
1372	* @param pVmcb Pointer to the VM control block.
1373	* @param pCtx Pointer to the guest-CPU context.
1374	*
1375	* @remarks No-long-jump zone!!!
1376	*/
1377	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1378	{
1379	PVM pVM = pVCpu->CTX_SUFF(pVM);
1380
1381	/*
1382	* Guest CR2.
1383	*/
1384	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1385	{
1386	pVmcb->guest.u64CR2 = pCtx->cr2;
1387	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1388	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1389	}
1390
1391	/*
1392	* Guest CR3.
1393	*/
1394	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1395	{
1396	if (pVM->hm.s.fNestedPaging)
1397	{
1398	PGMMODE enmShwPagingMode;
1399	#if HC_ARCH_BITS == 32
1400	if (CPUMIsGuestInLongModeEx(pCtx))
1401	enmShwPagingMode = PGMMODE_AMD64_NX;
1402	else
1403	#endif
1404	enmShwPagingMode = PGMGetHostMode(pVM);
1405
1406	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1407	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1408	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1409	pVmcb->guest.u64CR3 = pCtx->cr3;
1410	}
1411	else
1412	{
1413	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1414	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1415	}
1416
1417	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1418	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1419	}
1420
1421	/*
1422	* Guest CR4.
1423	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1424	*/
1425	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1426	{
1427	uint64_t u64GuestCR4 = pCtx->cr4;
1428	Assert(RT_HI_U32(u64GuestCR4) == 0);
1429	if (!pVM->hm.s.fNestedPaging)
1430	{
1431	switch (pVCpu->hm.s.enmShadowMode)
1432	{
1433	case PGMMODE_REAL:
1434	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1435	AssertFailed();
1436	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1437
1438	case PGMMODE_32_BIT: /* 32-bit paging. */
1439	u64GuestCR4 &= ~X86_CR4_PAE;
1440	break;
1441
1442	case PGMMODE_PAE: /* PAE paging. */
1443	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1444	/** Must use PAE paging as we could use physical memory > 4 GB */
1445	u64GuestCR4 \|= X86_CR4_PAE;
1446	break;
1447
1448	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1449	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1450	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1451	break;
1452	#else
1453	AssertFailed();
1454	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1455	#endif
1456
1457	default: /* shut up gcc */
1458	AssertFailed();
1459	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1460	}
1461	}
1462
1463	pVmcb->guest.u64CR4 = u64GuestCR4;
1464	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1465
1466	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1467	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1468
1469	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1470	}
1471
1472	return VINF_SUCCESS;
1473	}
1474
1475
1476	/**
1477	* Loads the guest segment registers into the VMCB.
1478	*
1479	* @returns VBox status code.
1480	* @param pVCpu The cross context virtual CPU structure.
1481	* @param pVmcb Pointer to the VM control block.
1482	* @param pCtx Pointer to the guest-CPU context.
1483	*
1484	* @remarks No-long-jump zone!!!
1485	*/
1486	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1487	{
1488	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1489	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1490	{
1491	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1492	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1493	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1494	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1495	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1496	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1497
1498	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1499	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1500	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1501	}
1502
1503	/* Guest TR. */
1504	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1505	{
1506	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1507	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1508	}
1509
1510	/* Guest LDTR. */
1511	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1512	{
1513	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1514	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1515	}
1516
1517	/* Guest GDTR. */
1518	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1519	{
1520	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1521	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1522	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1523	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1524	}
1525
1526	/* Guest IDTR. */
1527	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1528	{
1529	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1530	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1531	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1532	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1533	}
1534	}
1535
1536
1537	/**
1538	* Loads the guest MSRs into the VMCB.
1539	*
1540	* @param pVCpu The cross context virtual CPU structure.
1541	* @param pVmcb Pointer to the VM control block.
1542	* @param pCtx Pointer to the guest-CPU context.
1543	*
1544	* @remarks No-long-jump zone!!!
1545	*/
1546	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1547	{
1548	/* Guest Sysenter MSRs. */
1549	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1550	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1551	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1552
1553	/*
1554	* Guest EFER MSR.
1555	* AMD-V requires guest EFER.SVME to be set. Weird.
1556	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1557	*/
1558	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1559	{
1560	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1561	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1562	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1563	}
1564
1565	/* 64-bit MSRs. */
1566	if (CPUMIsGuestInLongModeEx(pCtx))
1567	{
1568	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1569	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1570	}
1571	else
1572	{
1573	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1574	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1575	{
1576	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1577	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1578	}
1579	}
1580
1581	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1582	* be writable in 32-bit mode. Clarify with AMD spec. */
1583	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1584	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1585	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1586	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1587	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1588	}
1589
1590
1591	/**
1592	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1593	* necessary intercepts accordingly.
1594	*
1595	* @param pVCpu The cross context virtual CPU structure.
1596	* @param pVmcb Pointer to the VM control block.
1597	* @param pCtx Pointer to the guest-CPU context.
1598	*
1599	* @remarks No-long-jump zone!!!
1600	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1601	*/
1602	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1603	{
1604	bool fInterceptMovDRx = false;
1605
1606	/*
1607	* Anyone single stepping on the host side? If so, we'll have to use the
1608	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1609	* the VMM level like the VT-x implementations does.
1610	*/
1611	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1612	if (fStepping)
1613	{
1614	pVCpu->hm.s.fClearTrapFlag = true;
1615	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1616	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1617	}
1618
1619	if ( fStepping
1620	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1621	{
1622	/*
1623	* Use the combined guest and host DRx values found in the hypervisor
1624	* register set because the debugger has breakpoints active or someone
1625	* is single stepping on the host side.
1626	*
1627	* Note! DBGF expects a clean DR6 state before executing guest code.
1628	*/
1629	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1630	if ( CPUMIsGuestInLongModeEx(pCtx)
1631	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1632	{
1633	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1634	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1635	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1636	}
1637	else
1638	#endif
1639	if (!CPUMIsHyperDebugStateActive(pVCpu))
1640	{
1641	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1642	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1643	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1644	}
1645
1646	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1647	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1648	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1649	{
1650	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1651	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1652	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1653	pVCpu->hm.s.fUsingHyperDR7 = true;
1654	}
1655
1656	/** @todo If we cared, we could optimize to allow the guest to read registers
1657	* with the same values. */
1658	fInterceptMovDRx = true;
1659	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1660	}
1661	else
1662	{
1663	/*
1664	* Update DR6, DR7 with the guest values if necessary.
1665	*/
1666	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1667	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1668	{
1669	pVmcb->guest.u64DR7 = pCtx->dr[7];
1670	pVmcb->guest.u64DR6 = pCtx->dr[6];
1671	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1672	pVCpu->hm.s.fUsingHyperDR7 = false;
1673	}
1674
1675	/*
1676	* If the guest has enabled debug registers, we need to load them prior to
1677	* executing guest code so they'll trigger at the right time.
1678	*/
1679	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1680	{
1681	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1682	if ( CPUMIsGuestInLongModeEx(pCtx)
1683	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1684	{
1685	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1686	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1687	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1688	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1689	}
1690	else
1691	#endif
1692	if (!CPUMIsGuestDebugStateActive(pVCpu))
1693	{
1694	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1695	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1696	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1697	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1698	}
1699	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1700	}
1701	/*
1702	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1703	* intercept #DB as DR6 is updated in the VMCB.
1704	*
1705	* Note! If we cared and dared, we could skip intercepting \#DB here.
1706	* However, \#DB shouldn't be performance critical, so we'll play safe
1707	* and keep the code similar to the VT-x code and always intercept it.
1708	*/
1709	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1710	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1711	&& !CPUMIsGuestDebugStateActive(pVCpu))
1712	#else
1713	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1714	#endif
1715	{
1716	fInterceptMovDRx = true;
1717	}
1718	}
1719
1720	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1721	if (fInterceptMovDRx)
1722	{
1723	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1724	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1725	{
1726	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1727	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1728	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1729	}
1730	}
1731	else
1732	{
1733	if ( pVmcb->ctrl.u16InterceptRdDRx
1734	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1735	{
1736	pVmcb->ctrl.u16InterceptRdDRx = 0;
1737	pVmcb->ctrl.u16InterceptWrDRx = 0;
1738	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1739	}
1740	}
1741	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1742	}
1743
1744
1745	#ifdef VBOX_WITH_NESTED_HWVIRT
1746	/**
1747	* Loads the nested-guest APIC state (currently just the TPR).
1748	*
1749	* @param pVCpu The cross context virtual CPU structure.
1750	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1751	*/
1752	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1753	{
1754	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1755	{
1756	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1757	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1758	pVCpu->hm.s.svm.fSyncVTpr = false;
1759	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1760
1761	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1762	}
1763	}
1764	#endif
1765
1766	/**
1767	* Loads the guest APIC state (currently just the TPR).
1768	*
1769	* @returns VBox status code.
1770	* @param pVCpu The cross context virtual CPU structure.
1771	* @param pVmcb Pointer to the VM control block.
1772	* @param pCtx Pointer to the guest-CPU context.
1773	*/
1774	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1775	{
1776	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1777	return VINF_SUCCESS;
1778
1779	int rc = VINF_SUCCESS;
1780	PVM pVM = pVCpu->CTX_SUFF(pVM);
1781	if ( PDMHasApic(pVM)
1782	&& APICIsEnabled(pVCpu))
1783	{
1784	bool fPendingIntr;
1785	uint8_t u8Tpr;
1786	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1787	AssertRCReturn(rc, rc);
1788
1789	/* Assume that we need to trap all TPR accesses and thus need not check on
1790	every #VMEXIT if we should update the TPR. */
1791	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1792	pVCpu->hm.s.svm.fSyncVTpr = false;
1793
1794	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1795	if (pVM->hm.s.fTPRPatchingActive)
1796	{
1797	pCtx->msrLSTAR = u8Tpr;
1798	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1799
1800	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1801	if (fPendingIntr)
1802	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1803	else
1804	{
1805	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1806	pVCpu->hm.s.svm.fSyncVTpr = true;
1807	}
1808	}
1809	else
1810	{
1811	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1812	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1813
1814	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1815	if (fPendingIntr)
1816	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1817	else
1818	{
1819	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1820	pVCpu->hm.s.svm.fSyncVTpr = true;
1821	}
1822
1823	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1824	}
1825	}
1826
1827	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1828	return rc;
1829	}
1830
1831
1832	/**
1833	* Loads the exception interrupts required for guest (or nested-guest) execution in
1834	* the VMCB.
1835	*
1836	* @param pVCpu The cross context virtual CPU structure.
1837	* @param pVmcb Pointer to the VM control block.
1838	* @param pCtx Pointer to the guest-CPU context.
1839	*/
1840	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1841	{
1842	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1843	{
1844	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1845	if (pVCpu->hm.s.fGIMTrapXcptUD)
1846	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1847	else
1848	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_UD);
1849
1850	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1851	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1852	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1853	else
1854	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_BP);
1855
1856	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1857	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1858	}
1859	}
1860
1861
1862	#ifdef VBOX_WITH_NESTED_HWVIRT
1863	/**
1864	* Loads the intercepts required for nested-guest execution in the VMCB.
1865	*
1866	* This merges the guest and nested-guest intercepts in a way that if the outer
1867	* guest intercepts an exception we need to intercept it in the nested-guest as
1868	* well and handle it accordingly.
1869	*
1870	* @param pVCpu The cross context virtual CPU structure.
1871	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1872	* @param pCtx Pointer to the guest-CPU context.
1873	*/
1874	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1875	{
1876	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1877	{
1878	/* First, load the guest intercepts into the guest VMCB. */
1879	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1880	Assert(!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR));
1881	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1882
1883	/* Next, merge the intercepts into the nested-guest VMCB. */
1884	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1885	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1886
1887	/* Always intercept CR0, CR4 reads and writes as we alter them. */
1888	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(0) \| RT_BIT(4);
1889	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(0) \| RT_BIT(4);
1890
1891	/* Always intercept CR3 reads and writes without nested-paging as we load shadow page tables. */
1892	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1893	{
1894	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1895	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1896	}
1897
1898	/** @todo Figure out debugging with nested-guests, till then just intercept
1899	* all DR[0-15] accesses. */
1900	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
1901	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
1902
1903	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
1904	pVmcbNstGst->ctrl.u64InterceptCtrl \|= pVmcb->ctrl.u64InterceptCtrl
1905	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
1906
1907	/*
1908	* Remove control intercepts that we don't need while executing the nested-guest.
1909	*
1910	* VMMCALL when not intercepted raises a \#UD exception in the guest. However,
1911	* other SVM instructions like VMSAVE when not intercept can cause havoc on the
1912	* host as they can write to any location in physical memory, hence they always
1913	* need to be intercepted (they are included in HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS).
1914	*/
1915	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
1916	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
1917	pVmcbNstGst->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VMMCALL;
1918
1919	/* Finally, update the VMCB clean bits. */
1920	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1921
1922	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
1923	}
1924	}
1925	#endif
1926
1927
1928	/**
1929	* Sets up the appropriate function to run guest code.
1930	*
1931	* @returns VBox status code.
1932	* @param pVCpu The cross context virtual CPU structure.
1933	*
1934	* @remarks No-long-jump zone!!!
1935	*/
1936	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
1937	{
1938	if (CPUMIsGuestInLongMode(pVCpu))
1939	{
1940	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1941	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1942	#endif
1943	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1944	#if HC_ARCH_BITS == 32
1945	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1946	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1947	#else
1948	/* 64-bit host or hybrid host. */
1949	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1950	#endif
1951	}
1952	else
1953	{
1954	/* Guest is not in long mode, use the 32-bit handler. */
1955	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1956	}
1957	return VINF_SUCCESS;
1958	}
1959
1960
1961	/**
1962	* Enters the AMD-V session.
1963	*
1964	* @returns VBox status code.
1965	* @param pVM The cross context VM structure.
1966	* @param pVCpu The cross context virtual CPU structure.
1967	* @param pCpu Pointer to the CPU info struct.
1968	*/
1969	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1970	{
1971	AssertPtr(pVM);
1972	AssertPtr(pVCpu);
1973	Assert(pVM->hm.s.svm.fSupported);
1974	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1975	NOREF(pVM); NOREF(pCpu);
1976
1977	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1978	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1979
1980	pVCpu->hm.s.fLeaveDone = false;
1981	return VINF_SUCCESS;
1982	}
1983
1984
1985	/**
1986	* Thread-context callback for AMD-V.
1987	*
1988	* @param enmEvent The thread-context event.
1989	* @param pVCpu The cross context virtual CPU structure.
1990	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1991	* @thread EMT(pVCpu)
1992	*/
1993	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1994	{
1995	NOREF(fGlobalInit);
1996
1997	switch (enmEvent)
1998	{
1999	case RTTHREADCTXEVENT_OUT:
2000	{
2001	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2002	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2003	VMCPU_ASSERT_EMT(pVCpu);
2004
2005	/* No longjmps (log-flush, locks) in this fragile context. */
2006	VMMRZCallRing3Disable(pVCpu);
2007
2008	if (!pVCpu->hm.s.fLeaveDone)
2009	{
2010	hmR0SvmLeave(pVCpu);
2011	pVCpu->hm.s.fLeaveDone = true;
2012	}
2013
2014	/* Leave HM context, takes care of local init (term). */
2015	int rc = HMR0LeaveCpu(pVCpu);
2016	AssertRC(rc); NOREF(rc);
2017
2018	/* Restore longjmp state. */
2019	VMMRZCallRing3Enable(pVCpu);
2020	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2021	break;
2022	}
2023
2024	case RTTHREADCTXEVENT_IN:
2025	{
2026	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2027	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2028	VMCPU_ASSERT_EMT(pVCpu);
2029
2030	/* No longjmps (log-flush, locks) in this fragile context. */
2031	VMMRZCallRing3Disable(pVCpu);
2032
2033	/*
2034	* Initialize the bare minimum state required for HM. This takes care of
2035	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2036	*/
2037	int rc = HMR0EnterCpu(pVCpu);
2038	AssertRC(rc); NOREF(rc);
2039	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2040
2041	pVCpu->hm.s.fLeaveDone = false;
2042
2043	/* Restore longjmp state. */
2044	VMMRZCallRing3Enable(pVCpu);
2045	break;
2046	}
2047
2048	default:
2049	break;
2050	}
2051	}
2052
2053
2054	/**
2055	* Saves the host state.
2056	*
2057	* @returns VBox status code.
2058	* @param pVM The cross context VM structure.
2059	* @param pVCpu The cross context virtual CPU structure.
2060	*
2061	* @remarks No-long-jump zone!!!
2062	*/
2063	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
2064	{
2065	NOREF(pVM);
2066	NOREF(pVCpu);
2067	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2068	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
2069	return VINF_SUCCESS;
2070	}
2071
2072
2073	/**
2074	* Loads the guest state into the VMCB.
2075	*
2076	* The CPU state will be loaded from these fields on every successful VM-entry.
2077	* Also sets up the appropriate VMRUN function to execute guest code based on
2078	* the guest CPU mode.
2079	*
2080	* @returns VBox status code.
2081	* @param pVM The cross context VM structure.
2082	* @param pVCpu The cross context virtual CPU structure.
2083	* @param pCtx Pointer to the guest-CPU context.
2084	*
2085	* @remarks No-long-jump zone!!!
2086	*/
2087	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2088	{
2089	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2090
2091	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2092	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2093
2094	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2095
2096	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
2097	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2098
2099	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
2100	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
2101
2102	pVmcb->guest.u64RIP = pCtx->rip;
2103	pVmcb->guest.u64RSP = pCtx->rsp;
2104	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2105	pVmcb->guest.u64RAX = pCtx->rax;
2106
2107	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
2108	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2109
2110	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
2111
2112	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2113	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2114
2115	/* Clear any unused and reserved bits. */
2116	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2117	\| HM_CHANGED_GUEST_RSP
2118	\| HM_CHANGED_GUEST_RFLAGS
2119	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2120	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2121	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2122	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2123	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2124	\| HM_CHANGED_SVM_RESERVED2
2125	\| HM_CHANGED_SVM_RESERVED3
2126	\| HM_CHANGED_SVM_RESERVED4);
2127
2128	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2129	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2130	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2131	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2132
2133	Log4(("hmR0SvmLoadGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32 ESP=%#RX32 EBP=%#RX32\n",
2134	pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4, pCtx->esp, pCtx->ebp));
2135	Log4(("hmR0SvmLoadGuestState: SS={%04x base=%016RX64 limit=%08x flags=%08x}\n", pCtx->ss.Sel, pCtx->ss.u64Base,
2136	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
2137	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2138	return rc;
2139	}
2140
2141
2142	#ifdef VBOX_WITH_NESTED_HWVIRT
2143	/**
2144	* Caches the nested-guest VMCB fields before we modify them for execution using
2145	* hardware-assisted SVM.
2146	*
2147	* @returns true if the VMCB was previously already cached, false otherwise.
2148	* @param pCtx Pointer to the guest-CPU context.
2149	*
2150	* @sa HMSvmNstGstVmExitNotify.
2151	*/
2152	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2153	{
2154	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2155	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2156	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2157	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2158
2159	/*
2160	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2161	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2162	*
2163	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2164	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2165	*/
2166	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2167	if (!fWasCached)
2168	{
2169	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2170	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2171	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2172	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2173	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2174	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2175	pNstGstVmcbCache->u64CR0 = pVmcbNstGstState->u64CR0;
2176	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2177	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2178	pNstGstVmcbCache->u64EFER = pVmcbNstGstState->u64EFER;
2179	pNstGstVmcbCache->u64DBGCTL = pVmcbNstGstState->u64DBGCTL;
2180	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2181	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2182	pNstGstVmcbCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2183	pNstGstVmcbCache->u32VmcbCleanBits = pVmcbNstGstCtrl->u32VmcbCleanBits;
2184	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2185	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2186	pNstGstVmcbCache->u1NestedPaging = pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging;
2187	pNstGstVmcbCache->u1LbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2188	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2189	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2190	}
2191
2192	return fWasCached;
2193	}
2194
2195
2196	/**
2197	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2198	*
2199	* @param pVCpu The cross context virtual CPU structure.
2200	* @param pCtx Pointer to the guest-CPU context.
2201	*/
2202	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2203	{
2204	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2205	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2206
2207	/*
2208	* First cache the nested-guest VMCB fields we may potentially modify.
2209	*/
2210	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2211	if (!fVmcbCached)
2212	{
2213	/*
2214	* The IOPM of the nested-guest can be ignored because the the guest always
2215	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2216	* into the nested-guest one and swap it back on the #VMEXIT.
2217	*/
2218	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2219
2220	/*
2221	* Load the host-physical address into the MSRPM rather than the nested-guest
2222	* physical address (currently we trap all MSRs in the nested-guest).
2223	*/
2224	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2225
2226	/*
2227	* Use the same nested-paging as the "outer" guest. We can't dynamically
2228	* switch off nested-paging suddenly while executing a VM (see assertion at the
2229	* end of Trap0eHandler in PGMAllBth.h).
2230	*/
2231	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2232
2233	/* For now copy the LBR info. from outer guest VMCB. */
2234	/** @todo fix this later. */
2235	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2236	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2237	pVmcbNstGst->guest.u64DBGCTL = pVmcb->guest.u64DBGCTL;
2238	}
2239	else
2240	{
2241	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2242	Assert(pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap);
2243	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2244	}
2245	}
2246
2247
2248	/**
2249	* Loads the nested-guest state into the VMCB.
2250	*
2251	* @returns VBox status code.
2252	* @param pVCpu The cross context virtual CPU structure.
2253	* @param pCtx Pointer to the guest-CPU context.
2254	*
2255	* @remarks No-long-jump zone!!!
2256	*/
2257	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2258	{
2259	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2260
2261	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2262	Assert(pVmcbNstGst);
2263
2264	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2265
2266	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
2267	AssertRCReturn(rc, rc);
2268
2269	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2270	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2271	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2272
2273	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2274	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2275	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2276	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2277
2278	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst, pCtx);
2279
2280	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2281	AssertRCReturn(rc, rc);
2282
2283	/* Clear any unused and reserved bits. */
2284	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2285	\| HM_CHANGED_GUEST_RSP
2286	\| HM_CHANGED_GUEST_RFLAGS
2287	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2288	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2289	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2290	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2291	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2292	\| HM_CHANGED_SVM_RESERVED2
2293	\| HM_CHANGED_SVM_RESERVED3
2294	\| HM_CHANGED_SVM_RESERVED4);
2295
2296	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2297	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2298	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2299	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2300
2301	Log4(("hmR0SvmLoadGuestStateNested: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 (HyperCR3=%#RX64) CR4=%#RX32 "
2302	"ESP=%#RX32 EBP=%#RX32 rc=%d\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3,
2303	pVmcbNstGst->guest.u64CR3, pCtx->cr4, pCtx->esp, pCtx->ebp, rc));
2304	Log4(("hmR0SvmLoadGuestStateNested: SS={%04x base=%016RX64 limit=%08x flags=%08x}\n", pCtx->ss.Sel, pCtx->ss.u64Base,
2305	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
2306	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2307
2308	return rc;
2309	}
2310	#endif
2311
2312
2313	/**
2314	* Loads the state shared between the host and guest or nested-guest into the
2315	* VMCB.
2316	*
2317	* @param pVCpu The cross context virtual CPU structure.
2318	* @param pVmcb Pointer to the VM control block.
2319	* @param pCtx Pointer to the guest-CPU context.
2320	*
2321	* @remarks No-long-jump zone!!!
2322	*/
2323	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2324	{
2325	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2326	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2327
2328	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2329	{
2330	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2331	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2332	}
2333
2334	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2335	{
2336	/** @todo Figure out stepping with nested-guest. */
2337	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2338	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2339	else
2340	{
2341	pVmcb->guest.u64DR6 = pCtx->dr[6];
2342	pVmcb->guest.u64DR7 = pCtx->dr[7];
2343	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2344	}
2345
2346	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2347	}
2348
2349	/* Unused on AMD-V. */
2350	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2351
2352	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2353	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2354	}
2355
2356
2357	/**
2358	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU context.
2359	*
2360	* Currently there is no residual state left in the CPU that is not updated in the
2361	* VMCB.
2362	*
2363	* @returns VBox status code.
2364	* @param pVCpu The cross context virtual CPU structure.
2365	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2366	* out-of-sync. Make sure to update the required fields
2367	* before using them.
2368	* @param pVmcb Pointer to the VM control block.
2369	*/
2370	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2371	{
2372	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2373
2374	pMixedCtx->rip = pVmcb->guest.u64RIP;
2375	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2376	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2377	pMixedCtx->rax = pVmcb->guest.u64RAX;
2378
2379	/*
2380	* Guest interrupt shadow.
2381	*/
2382	if (pVmcb->ctrl.IntShadow.n.u1IntShadow)
2383	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2384	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2385	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2386
2387	/*
2388	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2389	*/
2390	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2391
2392	/*
2393	* Guest MSRs.
2394	*/
2395	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2396	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2397	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2398	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2399	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2400	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2401	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2402	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2403
2404	/*
2405	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2406	*/
2407	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2408	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2409	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2410	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2411	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2412	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2413
2414	/*
2415	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2416	* register (yet).
2417	*/
2418	/** @todo SELM might need to be fixed as it too should not care about the
2419	* granularity bit. See @bugref{6785}. */
2420	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2421	&& pMixedCtx->cs.Attr.n.u1Present
2422	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2423	{
2424	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2425	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2426	}
2427
2428	#ifdef VBOX_STRICT
2429	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
2430	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
2431	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
2432	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
2433	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
2434	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
2435	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
2436
2437	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2438	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2439	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2440	HMSVM_ASSERT_SEG_GRANULARITY(es);
2441	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2442	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2443
2444	# undef HMSVM_ASSERT_SEL_GRANULARITY
2445	#endif
2446
2447	/*
2448	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2449	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2450	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2451	* See AMD spec. 15.5.1 "Basic operation".
2452	*/
2453	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2454	uint8_t const uCpl = pVmcb->guest.u8CPL;
2455	if (pMixedCtx->ss.Attr.n.u2Dpl != uCpl)
2456	{
2457	Log4(("hmR0SvmSaveGuestState: CPL differs. SS.DPL=%u, CPL=%u, overwriting SS.DPL!\n", pMixedCtx->ss.Attr.n.u2Dpl, uCpl));
2458	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2459	}
2460
2461	/*
2462	* Guest TR.
2463	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2464	* between Intel and AMD. See @bugref{6208#c39}.
2465	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2466	*/
2467	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2468	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2469	{
2470	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2471	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2472	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2473	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2474	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2475	}
2476
2477	/*
2478	* Guest Descriptor-Table registers.
2479	*/
2480	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2481	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2482	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2483
2484	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2485	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2486
2487	/*
2488	* Guest Debug registers.
2489	*/
2490	if (!pVCpu->hm.s.fUsingHyperDR7)
2491	{
2492	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2493	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2494	}
2495	else
2496	{
2497	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2498	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2499	}
2500
2501	/*
2502	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2503	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2504	*/
2505	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2506	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2507	{
2508	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2509	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2510	}
2511
2512	if (CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2513	{
2514	Log4(("hmR0SvmSaveGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32 ESP=%#RX32 EBP=%#RX32\n",
2515	pMixedCtx->cs.Sel, pMixedCtx->rip, pMixedCtx->eflags.u, pMixedCtx->cr0, pMixedCtx->cr3, pMixedCtx->cr4,
2516	pMixedCtx->esp, pMixedCtx->ebp));
2517	Log4(("hmR0SvmSaveGuestState: SS={%04x base=%016RX64 limit=%08x flags=%08x}\n", pMixedCtx->ss.Sel, pMixedCtx->ss.u64Base,
2518	pMixedCtx->ss.u32Limit, pMixedCtx->ss.Attr.u));
2519	Log4(("hmR0SvmSaveGuestState: DBGCTL BR_FROM=%#RX64 BR_TO=%#RX64 XcptFrom=%#RX64 XcptTo=%#RX64\n",
2520	pVmcb->guest.u64BR_FROM, pVmcb->guest.u64BR_TO,pVmcb->guest.u64LASTEXCPFROM, pVmcb->guest.u64LASTEXCPTO));
2521	}
2522	}
2523
2524
2525	/**
2526	* Does the necessary state syncing before returning to ring-3 for any reason
2527	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2528	*
2529	* @param pVCpu The cross context virtual CPU structure.
2530	*
2531	* @remarks No-long-jmp zone!!!
2532	*/
2533	static void hmR0SvmLeave(PVMCPU pVCpu)
2534	{
2535	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2536	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2537	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2538
2539	/*
2540	* !!! IMPORTANT !!!
2541	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2542	*/
2543
2544	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2545	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2546	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); /** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2547
2548	/*
2549	* Restore host debug registers if necessary and resync on next R0 reentry.
2550	*/
2551	#ifdef VBOX_STRICT
2552	if (CPUMIsHyperDebugStateActive(pVCpu))
2553	{
2554	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2555	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2556	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2557	}
2558	#endif
2559	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2560	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);/** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2561
2562	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2563	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2564
2565	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2566	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2567	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2568	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2569	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2570
2571	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2572	}
2573
2574
2575	/**
2576	* Leaves the AMD-V session.
2577	*
2578	* @returns VBox status code.
2579	* @param pVCpu The cross context virtual CPU structure.
2580	*/
2581	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2582	{
2583	HM_DISABLE_PREEMPT();
2584	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2585	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2586
2587	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2588	and done this from the SVMR0ThreadCtxCallback(). */
2589	if (!pVCpu->hm.s.fLeaveDone)
2590	{
2591	hmR0SvmLeave(pVCpu);
2592	pVCpu->hm.s.fLeaveDone = true;
2593	}
2594
2595	/*
2596	* !!! IMPORTANT !!!
2597	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2598	*/
2599
2600	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2601	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2602	VMMR0ThreadCtxHookDisable(pVCpu);
2603
2604	/* Leave HM context. This takes care of local init (term). */
2605	int rc = HMR0LeaveCpu(pVCpu);
2606
2607	HM_RESTORE_PREEMPT();
2608	return rc;
2609	}
2610
2611
2612	/**
2613	* Does the necessary state syncing before doing a longjmp to ring-3.
2614	*
2615	* @returns VBox status code.
2616	* @param pVCpu The cross context virtual CPU structure.
2617	*
2618	* @remarks No-long-jmp zone!!!
2619	*/
2620	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2621	{
2622	return hmR0SvmLeaveSession(pVCpu);
2623	}
2624
2625
2626	/**
2627	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2628	* any remaining host state) before we longjump to ring-3 and possibly get
2629	* preempted.
2630	*
2631	* @param pVCpu The cross context virtual CPU structure.
2632	* @param enmOperation The operation causing the ring-3 longjump.
2633	* @param pvUser The user argument (pointer to the possibly
2634	* out-of-date guest-CPU context).
2635	*/
2636	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2637	{
2638	RT_NOREF_PV(pvUser);
2639
2640	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2641	{
2642	/*
2643	* !!! IMPORTANT !!!
2644	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2645	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2646	*/
2647	VMMRZCallRing3RemoveNotification(pVCpu);
2648	VMMRZCallRing3Disable(pVCpu);
2649	HM_DISABLE_PREEMPT();
2650
2651	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2652	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2653
2654	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2655	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2656
2657	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2658	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2659	VMMR0ThreadCtxHookDisable(pVCpu);
2660
2661	/* Leave HM context. This takes care of local init (term). */
2662	HMR0LeaveCpu(pVCpu);
2663
2664	HM_RESTORE_PREEMPT();
2665	return VINF_SUCCESS;
2666	}
2667
2668	Assert(pVCpu);
2669	Assert(pvUser);
2670	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2671	HMSVM_ASSERT_PREEMPT_SAFE();
2672
2673	VMMRZCallRing3Disable(pVCpu);
2674	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2675
2676	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2677	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2678	AssertRCReturn(rc, rc);
2679
2680	VMMRZCallRing3Enable(pVCpu);
2681	return VINF_SUCCESS;
2682	}
2683
2684
2685	/**
2686	* Take necessary actions before going back to ring-3.
2687	*
2688	* An action requires us to go back to ring-3. This function does the necessary
2689	* steps before we can safely return to ring-3. This is not the same as longjmps
2690	* to ring-3, this is voluntary.
2691	*
2692	* @returns VBox status code.
2693	* @param pVM The cross context VM structure.
2694	* @param pVCpu The cross context virtual CPU structure.
2695	* @param pCtx Pointer to the guest-CPU context.
2696	* @param rcExit The reason for exiting to ring-3. Can be
2697	* VINF_VMM_UNKNOWN_RING3_CALL.
2698	*/
2699	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2700	{
2701	Assert(pVM);
2702	Assert(pVCpu);
2703	Assert(pCtx);
2704	HMSVM_ASSERT_PREEMPT_SAFE();
2705
2706	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2707	VMMRZCallRing3Disable(pVCpu);
2708	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
2709	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
2710
2711	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2712	if (pVCpu->hm.s.Event.fPending)
2713	{
2714	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2715	Assert(!pVCpu->hm.s.Event.fPending);
2716	}
2717
2718	/* Sync. the necessary state for going back to ring-3. */
2719	hmR0SvmLeaveSession(pVCpu);
2720	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2721
2722	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2723	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2724	\| CPUM_CHANGED_LDTR
2725	\| CPUM_CHANGED_GDTR
2726	\| CPUM_CHANGED_IDTR
2727	\| CPUM_CHANGED_TR
2728	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2729	if ( pVM->hm.s.fNestedPaging
2730	&& CPUMIsGuestPagingEnabledEx(pCtx))
2731	{
2732	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2733	}
2734
2735	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2736	if (rcExit != VINF_EM_RAW_INTERRUPT)
2737	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2738
2739	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2740
2741	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2742	VMMRZCallRing3RemoveNotification(pVCpu);
2743	VMMRZCallRing3Enable(pVCpu);
2744
2745	/*
2746	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2747	* and if we're injecting an event we should have a TRPM trap pending.
2748	*/
2749	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2750	pVCpu->hm.s.u32HMError = rcExit,
2751	VERR_SVM_IPE_5);
2752	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2753	pVCpu->hm.s.u32HMError = rcExit,
2754	VERR_SVM_IPE_4);
2755
2756	return rcExit;
2757	}
2758
2759
2760	#ifdef VBOX_WITH_NESTED_HWVIRT
2761	/**
2762	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2763	* intercepts for the nested-guest.
2764	*
2765	* @param pVM The cross context VM structure.
2766	* @param pVCpu The cross context virtual CPU structure.
2767	* @param pCtx Pointer to the nested guest-CPU context.
2768	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2769	*
2770	* @remarks No-long-jump zone!!!
2771	*/
2772	static void hmR0SvmUpdateTscOffsettingNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcbNstGst)
2773	{
2774	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2775
2776	bool fParavirtTsc;
2777	uint64_t uTscOffset;
2778	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
2779
2780	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2781	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2782
2783	/*
2784	* Only avoid intercepting if we determined the host TSC (++) is stable enough
2785	* to not intercept -and- the nested-hypervisor itself does not want to intercept it.
2786	*/
2787	if ( fCanUseRealTsc
2788	&& !(pVmcbNstGstCache->u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
2789	{
2790	pVmcbNstGstCtrl->u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2791	pVmcbNstGstCtrl->u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2792	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2793	}
2794	else
2795	{
2796	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2797	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2798	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2799	}
2800
2801	/* Apply the nested-guest VMCB's TSC offset over the guest one. */
2802	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
2803
2804	/* Update the nested-guest VMCB with the combined TSC offset (of guest and nested-guest). */
2805	pVmcbNstGstCtrl->u64TSCOffset = uTscOffset;
2806
2807	/* Finally update the VMCB clean bits since we touched the intercepts as well as the TSC offset. */
2808	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2809
2810	if (fParavirtTsc)
2811	{
2812	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2813	information before every VM-entry, hence disable it for performance sake. */
2814	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2815	}
2816	}
2817	#endif
2818
2819
2820	/**
2821	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2822	* intercepts.
2823	*
2824	* @param pVM The cross context VM structure.
2825	* @param pVCpu The cross context virtual CPU structure.
2826	* @param pVmcb Pointer to the VM control block.
2827	*
2828	* @remarks No-long-jump zone!!!
2829	*/
2830	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2831	{
2832	bool fParavirtTsc;
2833	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2834	if (fCanUseRealTsc)
2835	{
2836	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2837	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2838	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2839	}
2840	else
2841	{
2842	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2843	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2844	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2845	}
2846	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2847
2848	/** @todo later optimize this to be done elsewhere and not before every
2849	* VM-entry. */
2850	if (fParavirtTsc)
2851	{
2852	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2853	information before every VM-entry, hence disable it for performance sake. */
2854	#if 0
2855	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2856	AssertRC(rc);
2857	#endif
2858	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2859	}
2860	}
2861
2862
2863	/**
2864	* Sets an event as a pending event to be injected into the guest.
2865	*
2866	* @param pVCpu The cross context virtual CPU structure.
2867	* @param pEvent Pointer to the SVM event.
2868	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2869	* page-fault.
2870	*
2871	* @remarks Statistics counter assumes this is a guest event being reflected to
2872	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2873	*/
2874	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2875	{
2876	Assert(!pVCpu->hm.s.Event.fPending);
2877	Assert(pEvent->n.u1Valid);
2878
2879	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2880	pVCpu->hm.s.Event.fPending = true;
2881	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2882
2883	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2884	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2885	}
2886
2887
2888	/**
2889	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
2890	*
2891	* @param pVCpu The cross context virtual CPU structure.
2892	*/
2893	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
2894	{
2895	SVMEVENT Event;
2896	Event.u = 0;
2897	Event.n.u1Valid = 1;
2898	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2899	Event.n.u8Vector = X86_XCPT_UD;
2900	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2901	}
2902
2903
2904	/**
2905	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
2906	*
2907	* @param pVCpu The cross context virtual CPU structure.
2908	*/
2909	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
2910	{
2911	SVMEVENT Event;
2912	Event.u = 0;
2913	Event.n.u1Valid = 1;
2914	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2915	Event.n.u8Vector = X86_XCPT_DB;
2916	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2917	}
2918
2919
2920	/**
2921	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
2922	*
2923	* @param pVCpu The cross context virtual CPU structure.
2924	* @param pCtx Pointer to the guest-CPU context.
2925	* @param u32ErrCode The error-code for the page-fault.
2926	* @param uFaultAddress The page fault address (CR2).
2927	*
2928	* @remarks This updates the guest CR2 with @a uFaultAddress!
2929	*/
2930	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
2931	{
2932	SVMEVENT Event;
2933	Event.u = 0;
2934	Event.n.u1Valid = 1;
2935	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2936	Event.n.u8Vector = X86_XCPT_PF;
2937	Event.n.u1ErrorCodeValid = 1;
2938	Event.n.u32ErrorCode = u32ErrCode;
2939
2940	/* Update CR2 of the guest. */
2941	if (pCtx->cr2 != uFaultAddress)
2942	{
2943	pCtx->cr2 = uFaultAddress;
2944	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
2945	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
2946	}
2947
2948	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
2949	}
2950
2951
2952	/**
2953	* Sets a device-not-available (\#NM) exception as pending-for-injection into
2954	* the VM.
2955	*
2956	* @param pVCpu The cross context virtual CPU structure.
2957	*/
2958	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
2959	{
2960	SVMEVENT Event;
2961	Event.u = 0;
2962	Event.n.u1Valid = 1;
2963	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2964	Event.n.u8Vector = X86_XCPT_NM;
2965	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2966	}
2967
2968
2969	/**
2970	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
2971	*
2972	* @param pVCpu The cross context virtual CPU structure.
2973	*/
2974	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
2975	{
2976	SVMEVENT Event;
2977	Event.u = 0;
2978	Event.n.u1Valid = 1;
2979	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2980	Event.n.u8Vector = X86_XCPT_MF;
2981	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2982	}
2983
2984
2985	/**
2986	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
2987	*
2988	* @param pVCpu The cross context virtual CPU structure.
2989	*/
2990	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
2991	{
2992	SVMEVENT Event;
2993	Event.u = 0;
2994	Event.n.u1Valid = 1;
2995	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2996	Event.n.u8Vector = X86_XCPT_DF;
2997	Event.n.u1ErrorCodeValid = 1;
2998	Event.n.u32ErrorCode = 0;
2999	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3000	}
3001
3002
3003	/**
3004	* Injects an event into the guest upon VMRUN by updating the relevant field
3005	* in the VMCB.
3006	*
3007	* @param pVCpu The cross context virtual CPU structure.
3008	* @param pVmcb Pointer to the guest VM control block.
3009	* @param pCtx Pointer to the guest-CPU context.
3010	* @param pEvent Pointer to the event.
3011	*
3012	* @remarks No-long-jump zone!!!
3013	* @remarks Requires CR0!
3014	*/
3015	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
3016	{
3017	NOREF(pVCpu); NOREF(pCtx);
3018
3019	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3020	pVmcb->ctrl.EventInject.u = pEvent->u;
3021	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3022
3023	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3024	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3025	}
3026
3027
3028
3029	/**
3030	* Converts any TRPM trap into a pending HM event. This is typically used when
3031	* entering from ring-3 (not longjmp returns).
3032	*
3033	* @param pVCpu The cross context virtual CPU structure.
3034	*/
3035	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3036	{
3037	Assert(TRPMHasTrap(pVCpu));
3038	Assert(!pVCpu->hm.s.Event.fPending);
3039
3040	uint8_t uVector;
3041	TRPMEVENT enmTrpmEvent;
3042	RTGCUINT uErrCode;
3043	RTGCUINTPTR GCPtrFaultAddress;
3044	uint8_t cbInstr;
3045
3046	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3047	AssertRC(rc);
3048
3049	SVMEVENT Event;
3050	Event.u = 0;
3051	Event.n.u1Valid = 1;
3052	Event.n.u8Vector = uVector;
3053
3054	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3055	if (enmTrpmEvent == TRPM_TRAP)
3056	{
3057	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3058	switch (uVector)
3059	{
3060	case X86_XCPT_NMI:
3061	{
3062	Event.n.u3Type = SVM_EVENT_NMI;
3063	break;
3064	}
3065
3066	case X86_XCPT_PF:
3067	case X86_XCPT_DF:
3068	case X86_XCPT_TS:
3069	case X86_XCPT_NP:
3070	case X86_XCPT_SS:
3071	case X86_XCPT_GP:
3072	case X86_XCPT_AC:
3073	{
3074	Event.n.u1ErrorCodeValid = 1;
3075	Event.n.u32ErrorCode = uErrCode;
3076	break;
3077	}
3078	}
3079	}
3080	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3081	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3082	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3083	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3084	else
3085	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3086
3087	rc = TRPMResetTrap(pVCpu);
3088	AssertRC(rc);
3089
3090	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3091	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3092
3093	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3094	}
3095
3096
3097	/**
3098	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3099	* AMD-V to execute any instruction.
3100	*
3101	* @param pVCpu The cross context virtual CPU structure.
3102	*/
3103	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3104	{
3105	Assert(pVCpu->hm.s.Event.fPending);
3106	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3107
3108	SVMEVENT Event;
3109	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3110
3111	uint8_t uVector = Event.n.u8Vector;
3112	uint8_t uVectorType = Event.n.u3Type;
3113	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3114
3115	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3116
3117	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3118	AssertRC(rc);
3119
3120	if (Event.n.u1ErrorCodeValid)
3121	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3122
3123	if ( uVectorType == SVM_EVENT_EXCEPTION
3124	&& uVector == X86_XCPT_PF)
3125	{
3126	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3127	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3128	}
3129	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3130	{
3131	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3132	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3133	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3134	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3135	}
3136	pVCpu->hm.s.Event.fPending = false;
3137	}
3138
3139
3140	/**
3141	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3142	* now.
3143	*
3144	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3145	* @param pVCpu The cross context virtual CPU structure.
3146	* @param pCtx Pointer to the guest-CPU context.
3147	*
3148	* @remarks No-long-jump zone!!!
3149	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3150	*/
3151	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
3152	{
3153	/*
3154	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
3155	* inhibit interrupts or clear any existing interrupt-inhibition.
3156	*/
3157	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3158	{
3159	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
3160	{
3161	/*
3162	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3163	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
3164	*/
3165	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3166	return false;
3167	}
3168	return true;
3169	}
3170	return false;
3171	}
3172
3173
3174	/**
3175	* Sets the virtual interrupt intercept control in the VMCB.
3176	*
3177	* @param pVmcb Pointer to the VM control block.
3178	*/
3179	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
3180	{
3181	/*
3182	* When AVIC isn't supported, indicate that a virtual interrupt is pending and to
3183	* cause a #VMEXIT when the guest is ready to accept interrupts. At #VMEXIT, we
3184	* then get the interrupt from the APIC (updating ISR at the right time) and
3185	* inject the interrupt.
3186	*
3187	* With AVIC is supported, we could make use of the asynchronously delivery without
3188	* #VMEXIT and we would be passing the AVIC page to SVM.
3189	*/
3190	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3191	{
3192	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 0);
3193	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3194	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
3195	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3196	Log4(("Set VINTR intercept\n"));
3197	}
3198	}
3199
3200
3201	/**
3202	* Clears the virtual interrupt intercept control in the VMCB as
3203	* we are figured the guest is unable process any interrupts
3204	* at this point of time.
3205	*
3206	* @param pVmcb Pointer to the VM control block.
3207	*/
3208	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
3209	{
3210	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3211	{
3212	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 1);
3213	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
3214	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3215	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3216	Log4(("Cleared VINTR intercept\n"));
3217	}
3218	}
3219
3220
3221	/**
3222	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3223	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3224	* virtual NMIs.
3225	*
3226	* @param pVmcb Pointer to the VM control block.
3227	*/
3228	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3229	{
3230	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3231	{
3232	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3233	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3234
3235	Log4(("Setting IRET intercept\n"));
3236	}
3237	}
3238
3239
3240	/**
3241	* Clears the IRET intercept control in the VMCB.
3242	*
3243	* @param pVmcb Pointer to the VM control block.
3244	*/
3245	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3246	{
3247	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3248	{
3249	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3250	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3251
3252	Log4(("Clearing IRET intercept\n"));
3253	}
3254	}
3255
3256	#ifdef VBOX_WITH_NESTED_HWVIRT
3257
3258
3259	/**
3260	* Evaluates the event to be delivered to the nested-guest and sets it as the
3261	* pending event.
3262	*
3263	* @returns VBox strict status code.
3264	* @param pVCpu The cross context virtual CPU structure.
3265	* @param pCtx Pointer to the guest-CPU context.
3266	*/
3267	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3268	{
3269	Log4Func(("\n"));
3270
3271	Assert(!pVCpu->hm.s.Event.fPending);
3272
3273	bool const fGif = pCtx->hwvirt.svm.fGif;
3274	if (fGif)
3275	{
3276	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3277
3278	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3279
3280	/*
3281	* Check if the nested-guest can receive NMIs.
3282	* NMIs are higher priority than regular interrupts.
3283	*/
3284	/** @todo SMI. SMIs take priority over NMIs. */
3285	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3286	{
3287	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3288	if (fBlockNmi)
3289	hmR0SvmSetIretIntercept(pVmcbNstGst);
3290	else if (fIntShadow)
3291	{
3292	/** @todo Figure this out, how we shall manage virt. intercept if the
3293	* nested-guest already has one set and/or if we really need it? */
3294	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3295	}
3296	else
3297	{
3298	Log4(("Pending NMI\n"));
3299
3300	SVMEVENT Event;
3301	Event.u = 0;
3302	Event.n.u1Valid = 1;
3303	Event.n.u8Vector = X86_XCPT_NMI;
3304	Event.n.u3Type = SVM_EVENT_NMI;
3305
3306	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3307	hmR0SvmSetIretIntercept(pVmcbNstGst);
3308	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3309	return VINF_SUCCESS;
3310	}
3311	}
3312
3313	/*
3314	* Check if the nested-guest can receive external interrupts (generated by
3315	* the guest's PIC/APIC).
3316	*
3317	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3318	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3319	*
3320	* External interrupts that are generated for the outer guest may be intercepted
3321	* depending on how the nested-guest VMCB was programmed by guest software.
3322	*
3323	* Physical interrupts always take priority over virtual interrupts,
3324	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3325	*/
3326	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3327	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3328	&& !fIntShadow
3329	&& !pVCpu->hm.s.fSingleInstruction
3330	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3331	{
3332	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR)
3333	{
3334	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3335	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3336	}
3337
3338	uint8_t u8Interrupt;
3339	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3340	if (RT_SUCCESS(rc))
3341	{
3342	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3343
3344	SVMEVENT Event;
3345	Event.u = 0;
3346	Event.n.u1Valid = 1;
3347	Event.n.u8Vector = u8Interrupt;
3348	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3349
3350	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3351	}
3352	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3353	{
3354	/*
3355	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3356	* updated eventually when the TPR is written by the guest.
3357	*/
3358	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3359	}
3360	else
3361	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3362	}
3363
3364	/*
3365	* Check if the nested-guest is intercepting virtual (using V_IRQ and related fields)
3366	* interrupt injection. The virtual interrupt injection itself, if any, will be done
3367	* by the physical CPU.
3368	*/
3369	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3370	&& (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3371	&& CPUMCanSvmNstGstTakeVirtIntr(pCtx))
3372	{
3373	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3374	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3375	}
3376	}
3377
3378	return VINF_SUCCESS;
3379	}
3380	#endif
3381
3382
3383	/**
3384	* Evaluates the event to be delivered to the guest and sets it as the pending
3385	* event.
3386	*
3387	* @param pVCpu The cross context virtual CPU structure.
3388	* @param pCtx Pointer to the guest-CPU context.
3389	*
3390	* @remarks Don't use this function when we are actively executing a
3391	* nested-guest, use hmR0SvmEvaluatePendingEventNested instead.
3392	*/
3393	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3394	{
3395	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3396	Assert(!pVCpu->hm.s.Event.fPending);
3397
3398	#ifdef VBOX_WITH_NESTED_HWVIRT
3399	bool const fGif = pCtx->hwvirt.svm.fGif;
3400	#else
3401	bool const fGif = true;
3402	#endif
3403	Log4Func(("fGif=%RTbool\n", fGif));
3404
3405	/*
3406	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3407	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3408	*/
3409	if (fGif)
3410	{
3411	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3412	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3413	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3414	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3415
3416	Log4Func(("fGif=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fGif, fBlockInt, fIntShadow,
3417	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3418
3419	/** @todo SMI. SMIs take priority over NMIs. */
3420	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3421	{
3422	if (fBlockNmi)
3423	hmR0SvmSetIretIntercept(pVmcb);
3424	else if (fIntShadow)
3425	hmR0SvmSetVirtIntrIntercept(pVmcb);
3426	else
3427	{
3428	Log4(("Pending NMI\n"));
3429
3430	SVMEVENT Event;
3431	Event.u = 0;
3432	Event.n.u1Valid = 1;
3433	Event.n.u8Vector = X86_XCPT_NMI;
3434	Event.n.u3Type = SVM_EVENT_NMI;
3435
3436	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3437	hmR0SvmSetIretIntercept(pVmcb);
3438	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3439	return;
3440	}
3441	}
3442	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3443	&& !pVCpu->hm.s.fSingleInstruction)
3444	{
3445	/*
3446	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3447	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3448	*/
3449	if ( !fBlockInt
3450	&& !fIntShadow)
3451	{
3452	uint8_t u8Interrupt;
3453	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3454	if (RT_SUCCESS(rc))
3455	{
3456	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3457
3458	SVMEVENT Event;
3459	Event.u = 0;
3460	Event.n.u1Valid = 1;
3461	Event.n.u8Vector = u8Interrupt;
3462	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3463
3464	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3465	}
3466	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3467	{
3468	/*
3469	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3470	* updated eventually when the TPR is written by the guest.
3471	*/
3472	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3473	}
3474	else
3475	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3476	}
3477	else
3478	hmR0SvmSetVirtIntrIntercept(pVmcb);
3479	}
3480	}
3481	}
3482
3483
3484	/**
3485	* Injects any pending events into the guest or nested-guest.
3486	*
3487	* @param pVCpu The cross context virtual CPU structure.
3488	* @param pCtx Pointer to the guest-CPU context.
3489	* @param pVmcb Pointer to the VM control block.
3490	*/
3491	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3492	{
3493	Assert(!TRPMHasTrap(pVCpu));
3494	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3495
3496	bool const fIsNestedGuest = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
3497	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3498	bool const fBlockInt = !fIsNestedGuest ? !(pCtx->eflags.u32 & X86_EFL_IF) : CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx);
3499
3500	if (pVCpu->hm.s.Event.fPending)
3501	{
3502	SVMEVENT Event;
3503	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3504	Assert(Event.n.u1Valid);
3505
3506	/*
3507	* Validate event injection pre-conditions.
3508	*/
3509	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3510	{
3511	Assert(!fBlockInt);
3512	Assert(!fIntShadow);
3513	}
3514	else if (Event.n.u3Type == SVM_EVENT_NMI)
3515	Assert(!fIntShadow);
3516	NOREF(fBlockInt);
3517
3518	/*
3519	* Inject it (update VMCB for injection by the hardware).
3520	*/
3521	Log4(("Injecting pending HM event\n"));
3522	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3523	pVCpu->hm.s.Event.fPending = false;
3524
3525	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3526	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3527	else
3528	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3529	}
3530	else
3531	{
3532	#ifdef VBOX_WITH_NESTED_HWVIRT
3533	/*
3534	* If IEM emulated VMRUN and injected an event, it would not clear the EVENTINJ::Valid bit
3535	* as a physical CPU clears it in the VMCB as part of the #VMEXIT (if the AMD spec. is to
3536	* believed, real behavior might differ). Regardless, IEM does it only on #VMEXIT for now
3537	* and since we are continuing nested-guest execution using hardware-assisted SVM, we need
3538	* to clear this field otherwise we will inject the event twice, see @bugref{7243#78}.
3539	*/
3540	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3541	pVmcb->ctrl.EventInject.n.u1Valid = 0;
3542	#endif
3543	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3544	}
3545
3546	/*
3547	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3548	*
3549	* For nested-guests: We need to update it too for the scenario where IEM executes
3550	* the nested-guest but execution later continues here with an interrupt shadow active.
3551	*/
3552	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3553	}
3554
3555
3556	/**
3557	* Reports world-switch error and dumps some useful debug info.
3558	*
3559	* @param pVM The cross context VM structure.
3560	* @param pVCpu The cross context virtual CPU structure.
3561	* @param rcVMRun The return code from VMRUN (or
3562	* VERR_SVM_INVALID_GUEST_STATE for invalid
3563	* guest-state).
3564	* @param pCtx Pointer to the guest-CPU context.
3565	*/
3566	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3567	{
3568	NOREF(pCtx);
3569	HMSVM_ASSERT_PREEMPT_SAFE();
3570	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3571	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3572
3573	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3574	{
3575	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3576	#ifdef VBOX_STRICT
3577	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3578	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3579	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3580	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3581	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3582	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3583	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3584	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3585	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3586	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3587
3588	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3589	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3590	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3591
3592	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3593	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3594	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3595	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved0));
3596	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3597	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3598	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3599	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3600	Log4(("ctrl.IntCtrl.u6Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved1));
3601	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3602	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3603
3604	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3605	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3606	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3607	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3608	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3609	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3610	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3611	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3612	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3613	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3614	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3615	Log4(("ctrl.NestedPaging.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPaging.n.u1NestedPaging));
3616	Log4(("ctrl.NestedPaging.u1Sev %#x\n", pVmcb->ctrl.NestedPaging.n.u1Sev));
3617	Log4(("ctrl.NestedPaging.u1SevEs %#x\n", pVmcb->ctrl.NestedPaging.n.u1SevEs));
3618	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3619	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3620	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3621	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3622	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3623	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3624
3625	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3626
3627	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3628	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3629
3630	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3631	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3632	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3633	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3634	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3635	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3636	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3637	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3638	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3639	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3640	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3641	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3642	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3643	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3644	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3645	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3646	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3647	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3648	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3649	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3650
3651	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3652	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3653
3654	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3655	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3656	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3657	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3658
3659	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3660	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3661
3662	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3663	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3664	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3665	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3666
3667	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3668	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3669	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3670	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3671	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3672	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3673	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3674
3675	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3676	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3677	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3678	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3679
3680	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3681	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3682	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3683
3684	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3685	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3686	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3687	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3688	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3689	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3690	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3691	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3692	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3693	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3694	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3695	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3696	#endif /* VBOX_STRICT */
3697	}
3698	else
3699	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3700
3701	NOREF(pVmcb);
3702	}
3703
3704
3705	/**
3706	* Check per-VM and per-VCPU force flag actions that require us to go back to
3707	* ring-3 for one reason or another.
3708	*
3709	* @returns VBox status code (information status code included).
3710	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3711	* ring-3.
3712	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3713	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3714	* interrupts)
3715	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3716	* all EMTs to be in ring-3.
3717	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3718	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3719	* to the EM loop.
3720	*
3721	* @param pVM The cross context VM structure.
3722	* @param pVCpu The cross context virtual CPU structure.
3723	* @param pCtx Pointer to the guest-CPU context.
3724	*/
3725	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3726	{
3727	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3728
3729	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3730	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3731	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3732
3733	/* Update pending interrupts into the APIC's IRR. */
3734	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3735	APICUpdatePendingInterrupts(pVCpu);
3736
3737	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3738	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3739	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3740	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3741	{
3742	/* Pending PGM C3 sync. */
3743	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3744	{
3745	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3746	if (rc != VINF_SUCCESS)
3747	{
3748	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3749	return rc;
3750	}
3751	}
3752
3753	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3754	/* -XXX- what was that about single stepping? */
3755	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3756	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3757	{
3758	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3759	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3760	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3761	return rc;
3762	}
3763
3764	/* Pending VM request packets, such as hardware interrupts. */
3765	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3766	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3767	{
3768	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3769	return VINF_EM_PENDING_REQUEST;
3770	}
3771
3772	/* Pending PGM pool flushes. */
3773	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3774	{
3775	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3776	return VINF_PGM_POOL_FLUSH_PENDING;
3777	}
3778
3779	/* Pending DMA requests. */
3780	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3781	{
3782	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3783	return VINF_EM_RAW_TO_R3;
3784	}
3785	}
3786
3787	return VINF_SUCCESS;
3788	}
3789
3790
3791	#ifdef VBOX_WITH_NESTED_HWVIRT
3792	/**
3793	* Does the preparations before executing nested-guest code in AMD-V.
3794	*
3795	* @returns VBox status code (informational status codes included).
3796	* @retval VINF_SUCCESS if we can proceed with running the guest.
3797	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3798	*
3799	* @param pVM The cross context VM structure.
3800	* @param pVCpu The cross context virtual CPU structure.
3801	* @param pCtx Pointer to the guest-CPU context.
3802	* @param pSvmTransient Pointer to the SVM transient structure.
3803	*
3804	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3805	* @sa hmR0SvmPreRunGuest.
3806	*/
3807	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3808	{
3809	HMSVM_ASSERT_PREEMPT_SAFE();
3810
3811	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3812	{
3813	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3814	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3815	return VINF_EM_RESCHEDULE_REM;
3816	#endif
3817	}
3818	else
3819	return VINF_SVM_VMEXIT;
3820
3821	/* Check force flag actions that might require us to go back to ring-3. */
3822	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3823	if (rc != VINF_SUCCESS)
3824	return rc;
3825
3826	if (TRPMHasTrap(pVCpu))
3827	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3828	else if (!pVCpu->hm.s.Event.fPending)
3829	{
3830	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3831	if (rcStrict != VINF_SUCCESS)
3832	return VBOXSTRICTRC_VAL(rcStrict);
3833	}
3834
3835	/*
3836	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3837	* Just do it in software, see @bugref{8411}.
3838	* NB: If we could continue a task switch exit we wouldn't need to do this.
3839	*/
3840	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3841	&& pVCpu->hm.s.Event.fPending
3842	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
3843	{
3844	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3845	}
3846
3847	/*
3848	* Load the nested-guest state.
3849	*/
3850	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
3851	AssertRCReturn(rc, rc);
3852	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */
3853
3854	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */
3855	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
3856
3857	/*
3858	* No longjmps to ring-3 from this point on!!!
3859	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3860	* This also disables flushing of the R0-logger instance (if any).
3861	*/
3862	VMMRZCallRing3Disable(pVCpu);
3863
3864	/*
3865	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3866	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3867	*
3868	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3869	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3870	*
3871	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3872	* executing guest code.
3873	*/
3874	pSvmTransient->fEFlags = ASMIntDisableFlags();
3875	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3876	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3877	{
3878	ASMSetFlags(pSvmTransient->fEFlags);
3879	VMMRZCallRing3Enable(pVCpu);
3880	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3881	return VINF_EM_RAW_TO_R3;
3882	}
3883	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3884	{
3885	ASMSetFlags(pSvmTransient->fEFlags);
3886	VMMRZCallRing3Enable(pVCpu);
3887	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3888	return VINF_EM_RAW_INTERRUPT;
3889	}
3890
3891	/*
3892	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3893	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3894	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3895	*
3896	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3897	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3898	*/
3899	if (pVCpu->hm.s.Event.fPending)
3900	{
3901	SVMEVENT Event;
3902	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3903	if ( Event.n.u1Valid
3904	&& Event.n.u3Type == SVM_EVENT_NMI
3905	&& Event.n.u8Vector == X86_XCPT_NMI
3906	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3907	{
3908	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3909	}
3910	}
3911
3912	return VINF_SUCCESS;
3913	}
3914	#endif
3915
3916
3917	/**
3918	* Does the preparations before executing guest code in AMD-V.
3919	*
3920	* This may cause longjmps to ring-3 and may even result in rescheduling to the
3921	* recompiler. We must be cautious what we do here regarding committing
3922	* guest-state information into the VMCB assuming we assuredly execute the guest
3923	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
3924	* clearing the common-state (TRPM/forceflags), we must undo those changes so
3925	* that the recompiler can (and should) use them when it resumes guest
3926	* execution. Otherwise such operations must be done when we can no longer
3927	* exit to ring-3.
3928	*
3929	* @returns VBox status code (informational status codes included).
3930	* @retval VINF_SUCCESS if we can proceed with running the guest.
3931	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3932	*
3933	* @param pVM The cross context VM structure.
3934	* @param pVCpu The cross context virtual CPU structure.
3935	* @param pCtx Pointer to the guest-CPU context.
3936	* @param pSvmTransient Pointer to the SVM transient structure.
3937	*/
3938	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3939	{
3940	HMSVM_ASSERT_PREEMPT_SAFE();
3941	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3942
3943	/* Check force flag actions that might require us to go back to ring-3. */
3944	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3945	if (rc != VINF_SUCCESS)
3946	return rc;
3947
3948	if (TRPMHasTrap(pVCpu))
3949	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3950	else if (!pVCpu->hm.s.Event.fPending)
3951	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
3952
3953	/*
3954	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3955	* Just do it in software, see @bugref{8411}.
3956	* NB: If we could continue a task switch exit we wouldn't need to do this.
3957	*/
3958	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
3959	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
3960	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3961
3962	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
3963	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3964	#endif
3965
3966	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3967	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3968	AssertRCReturn(rc, rc);
3969	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3970
3971	/*
3972	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3973	* so we can update it on the way back if the guest changed the TPR.
3974	*/
3975	if (pVCpu->hm.s.svm.fSyncVTpr)
3976	{
3977	if (pVM->hm.s.fTPRPatchingActive)
3978	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3979	else
3980	{
3981	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3982	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3983	}
3984	}
3985
3986	/*
3987	* No longjmps to ring-3 from this point on!!!
3988	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3989	* This also disables flushing of the R0-logger instance (if any).
3990	*/
3991	VMMRZCallRing3Disable(pVCpu);
3992
3993	/*
3994	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3995	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3996	*
3997	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3998	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3999	*
4000	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4001	* executing guest code.
4002	*/
4003	pSvmTransient->fEFlags = ASMIntDisableFlags();
4004	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4005	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4006	{
4007	ASMSetFlags(pSvmTransient->fEFlags);
4008	VMMRZCallRing3Enable(pVCpu);
4009	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4010	return VINF_EM_RAW_TO_R3;
4011	}
4012	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4013	{
4014	ASMSetFlags(pSvmTransient->fEFlags);
4015	VMMRZCallRing3Enable(pVCpu);
4016	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4017	return VINF_EM_RAW_INTERRUPT;
4018	}
4019
4020	/*
4021	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4022	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4023	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4024	*
4025	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4026	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4027	*/
4028	if (pVCpu->hm.s.Event.fPending)
4029	{
4030	SVMEVENT Event;
4031	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4032	if ( Event.n.u1Valid
4033	&& Event.n.u3Type == SVM_EVENT_NMI
4034	&& Event.n.u8Vector == X86_XCPT_NMI
4035	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4036	{
4037	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4038	}
4039	}
4040
4041	return VINF_SUCCESS;
4042	}
4043
4044
4045	#ifdef VBOX_WITH_NESTED_HWVIRT
4046	/**
4047	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
4048	* means there is no backing out to ring-3 or anywhere else at this point.
4049	*
4050	* @param pVM The cross context VM structure.
4051	* @param pVCpu The cross context virtual CPU structure.
4052	* @param pCtx Pointer to the guest-CPU context.
4053	* @param pSvmTransient Pointer to the SVM transient structure.
4054	*
4055	* @remarks Called with preemption disabled.
4056	* @remarks No-long-jump zone!!!
4057	*/
4058	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4059	{
4060	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4061	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4062	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4063	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4064
4065	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4066	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4067
4068	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4069	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
4070
4071	if ( pVCpu->hm.s.fPreloadGuestFpu
4072	&& !CPUMIsGuestFPUStateActive(pVCpu))
4073	{
4074	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4075	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4076	}
4077
4078	/* Load the state shared between host and nested-guest (FPU, debug). */
4079	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4080	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
4081
4082	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4083	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4084
4085	/* Setup TSC offsetting. */
4086	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4087	if ( pSvmTransient->fUpdateTscOffsetting
4088	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4089	{
4090	hmR0SvmUpdateTscOffsettingNested(pVM, pVCpu, pCtx, pVmcbNstGst);
4091	pSvmTransient->fUpdateTscOffsetting = false;
4092	}
4093
4094	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4095	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4096	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4097
4098	/* Store status of the shared guest-host state at the time of VMRUN. */
4099	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4100	if (CPUMIsGuestInLongModeEx(pCtx))
4101	{
4102	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4103	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4104	}
4105	else
4106	#endif
4107	{
4108	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4109	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4110	}
4111	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4112
4113	/* The TLB flushing would've already been setup by the nested-hypervisor. */
4114	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4115	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
4116	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4117
4118	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4119
4120	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4121	to start executing. */
4122
4123	/*
4124	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4125	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4126	*
4127	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4128	*/
4129	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4130	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4131	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4132	{
4133	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4134	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4135	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4136	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4137	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4138	pSvmTransient->fRestoreTscAuxMsr = true;
4139	}
4140	else
4141	{
4142	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4143	pSvmTransient->fRestoreTscAuxMsr = false;
4144	}
4145
4146	/*
4147	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
4148	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
4149	*/
4150	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4151	if (!fSupportsVmcbCleanBits)
4152	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4153	}
4154	#endif
4155
4156
4157	/**
4158	* Prepares to run guest code in AMD-V and we've committed to doing so. This
4159	* means there is no backing out to ring-3 or anywhere else at this
4160	* point.
4161	*
4162	* @param pVM The cross context VM structure.
4163	* @param pVCpu The cross context virtual CPU structure.
4164	* @param pCtx Pointer to the guest-CPU context.
4165	* @param pSvmTransient Pointer to the SVM transient structure.
4166	*
4167	* @remarks Called with preemption disabled.
4168	* @remarks No-long-jump zone!!!
4169	*/
4170	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4171	{
4172	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4173	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4174	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4175	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4176
4177	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4178	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4179
4180	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4181	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
4182
4183	if ( pVCpu->hm.s.fPreloadGuestFpu
4184	&& !CPUMIsGuestFPUStateActive(pVCpu))
4185	{
4186	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4187	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4188	}
4189
4190	/* Load the state shared between host and guest (FPU, debug). */
4191	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4192	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
4193
4194	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4195	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4196
4197	/* Setup TSC offsetting. */
4198	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4199	if ( pSvmTransient->fUpdateTscOffsetting
4200	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4201	{
4202	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
4203	pSvmTransient->fUpdateTscOffsetting = false;
4204	}
4205
4206	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4207	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4208	pVmcb->ctrl.u32VmcbCleanBits = 0;
4209
4210	/* Store status of the shared guest-host state at the time of VMRUN. */
4211	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4212	if (CPUMIsGuestInLongModeEx(pCtx))
4213	{
4214	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4215	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4216	}
4217	else
4218	#endif
4219	{
4220	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4221	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4222	}
4223	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4224
4225	/* Flush the appropriate tagged-TLB entries. */
4226	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4227	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
4228	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4229
4230	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4231
4232	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4233	to start executing. */
4234
4235	/*
4236	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4237	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4238	*
4239	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4240	*/
4241	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4242	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4243	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4244	{
4245	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4246	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4247	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4248	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4249	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4250	pSvmTransient->fRestoreTscAuxMsr = true;
4251	}
4252	else
4253	{
4254	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4255	pSvmTransient->fRestoreTscAuxMsr = false;
4256	}
4257
4258	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4259	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4260	if (!fSupportsVmcbCleanBits)
4261	pVmcb->ctrl.u32VmcbCleanBits = 0;
4262	}
4263
4264
4265	/**
4266	* Wrapper for running the guest code in AMD-V.
4267	*
4268	* @returns VBox strict status code.
4269	* @param pVM The cross context VM structure.
4270	* @param pVCpu The cross context virtual CPU structure.
4271	* @param pCtx Pointer to the guest-CPU context.
4272	*
4273	* @remarks No-long-jump zone!!!
4274	*/
4275	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4276	{
4277	/*
4278	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4279	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4280	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4281	*/
4282	#ifdef VBOX_WITH_KERNEL_USING_XMM
4283	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4284	pVCpu->hm.s.svm.pfnVMRun);
4285	#else
4286	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4287	#endif
4288	}
4289
4290
4291	#ifdef VBOX_WITH_NESTED_HWVIRT
4292	/**
4293	* Wrapper for running the nested-guest code in AMD-V.
4294	*
4295	* @returns VBox strict status code.
4296	* @param pVM The cross context VM structure.
4297	* @param pVCpu The cross context virtual CPU structure.
4298	* @param pCtx Pointer to the guest-CPU context.
4299	*
4300	* @remarks No-long-jump zone!!!
4301	*/
4302	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4303	{
4304	/*
4305	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4306	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4307	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4308	*/
4309	#ifdef VBOX_WITH_KERNEL_USING_XMM
4310	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4311	pVCpu->hm.s.svm.pfnVMRun);
4312	#else
4313	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4314	#endif
4315	}
4316
4317
4318	/**
4319	* Performs some essential restoration of state after running nested-guest code in
4320	* AMD-V.
4321	*
4322	* @param pVM The cross context VM structure.
4323	* @param pVCpu The cross context virtual CPU structure.
4324	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4325	* out-of-sync. Make sure to update the required fields
4326	* before using them.
4327	* @param pSvmTransient Pointer to the SVM transient structure.
4328	* @param rcVMRun Return code of VMRUN.
4329	*
4330	* @remarks Called with interrupts disabled.
4331	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4332	* unconditionally when it is safe to do so.
4333	*/
4334	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4335	{
4336	RT_NOREF(pVM);
4337	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4338
4339	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4340	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4341
4342	/* TSC read must be done early for maximum accuracy. */
4343	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4344	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4345	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4346	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4347	{
4348	/*
4349	* Undo what we did in hmR0SvmUpdateTscOffsettingNested() but don't restore the
4350	* nested-guest VMCB TSC offset here. It shall eventually be restored on #VMEXIT
4351	* later by HMSvmNstGstVmExitNotify().
4352	*/
4353	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset - pVmcbNstGstCache->u64TSCOffset);
4354	}
4355
4356	if (pSvmTransient->fRestoreTscAuxMsr)
4357	{
4358	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4359	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4360	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4361	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4362	}
4363
4364	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4365	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4366	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4367
4368	Assert(!(ASMGetFlags() & X86_EFL_IF));
4369	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4370	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4371
4372	/* Mark the VMCB-state cache as unmodified by VMM. */
4373	pVmcbNstGstCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4374
4375	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4376	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4377	{
4378	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4379	return;
4380	}
4381
4382	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4383	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4384	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4385	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4386
4387	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4388	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4389	guest-CPU context. */
4390	}
4391	#endif
4392
4393	/**
4394	* Performs some essential restoration of state after running guest code in
4395	* AMD-V.
4396	*
4397	* @param pVM The cross context VM structure.
4398	* @param pVCpu The cross context virtual CPU structure.
4399	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4400	* out-of-sync. Make sure to update the required fields
4401	* before using them.
4402	* @param pSvmTransient Pointer to the SVM transient structure.
4403	* @param rcVMRun Return code of VMRUN.
4404	*
4405	* @remarks Called with interrupts disabled.
4406	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4407	* unconditionally when it is safe to do so.
4408	*/
4409	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4410	{
4411	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4412
4413	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4414	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4415
4416	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4417	pVmcb->ctrl.u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4418
4419	/* TSC read must be done early for maximum accuracy. */
4420	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4421	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4422
4423	if (pSvmTransient->fRestoreTscAuxMsr)
4424	{
4425	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4426	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4427	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4428	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4429	}
4430
4431	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4432	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4433	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4434
4435	Assert(!(ASMGetFlags() & X86_EFL_IF));
4436	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4437	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4438
4439	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4440	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4441	{
4442	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4443	return;
4444	}
4445
4446	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4447	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4448	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4449	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4450
4451	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4452
4453	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4454	{
4455	if (pVCpu->hm.s.svm.fSyncVTpr)
4456	{
4457	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4458	if ( pVM->hm.s.fTPRPatchingActive
4459	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4460	{
4461	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4462	AssertRC(rc);
4463	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4464	}
4465	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4466	{
4467	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4468	AssertRC(rc);
4469	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4470	}
4471	}
4472	}
4473	}
4474
4475
4476	/**
4477	* Runs the guest code using AMD-V.
4478	*
4479	* @returns VBox status code.
4480	* @param pVM The cross context VM structure.
4481	* @param pVCpu The cross context virtual CPU structure.
4482	* @param pCtx Pointer to the guest-CPU context.
4483	* @param pcLoops Pointer to the number of executed loops.
4484	*/
4485	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4486	{
4487	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4488	Assert(pcLoops);
4489	Assert(*pcLoops <= cMaxResumeLoops);
4490
4491	SVMTRANSIENT SvmTransient;
4492	SvmTransient.fUpdateTscOffsetting = true;
4493
4494	int rc = VERR_INTERNAL_ERROR_5;
4495	for (;;)
4496	{
4497	Assert(!HMR0SuspendPending());
4498	HMSVM_ASSERT_CPU_SAFE();
4499
4500	/* Preparatory work for running guest code, this may force us to return
4501	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4502	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4503	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4504	if (rc != VINF_SUCCESS)
4505	break;
4506
4507	/*
4508	* No longjmps to ring-3 from this point on!!!
4509	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4510	* This also disables flushing of the R0-logger instance (if any).
4511	*/
4512	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4513	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4514
4515	/* Restore any residual host-state and save any bits shared between host
4516	and guest into the guest-CPU state. Re-enables interrupts! */
4517	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4518
4519	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4520	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4521	{
4522	if (rc == VINF_SUCCESS)
4523	rc = VERR_SVM_INVALID_GUEST_STATE;
4524	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4525	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4526	break;
4527	}
4528
4529	/* Handle the #VMEXIT. */
4530	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4531	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4532	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4533	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4534	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4535	if (rc != VINF_SUCCESS)
4536	break;
4537	if (++(*pcLoops) >= cMaxResumeLoops)
4538	{
4539	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4540	rc = VINF_EM_RAW_INTERRUPT;
4541	break;
4542	}
4543	}
4544
4545	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4546	return rc;
4547	}
4548
4549
4550	/**
4551	* Runs the guest code using AMD-V in single step mode.
4552	*
4553	* @returns VBox status code.
4554	* @param pVM The cross context VM structure.
4555	* @param pVCpu The cross context virtual CPU structure.
4556	* @param pCtx Pointer to the guest-CPU context.
4557	* @param pcLoops Pointer to the number of executed loops.
4558	*/
4559	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4560	{
4561	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4562	Assert(pcLoops);
4563	Assert(*pcLoops <= cMaxResumeLoops);
4564
4565	SVMTRANSIENT SvmTransient;
4566	SvmTransient.fUpdateTscOffsetting = true;
4567
4568	uint16_t uCsStart = pCtx->cs.Sel;
4569	uint64_t uRipStart = pCtx->rip;
4570
4571	int rc = VERR_INTERNAL_ERROR_5;
4572	for (;;)
4573	{
4574	Assert(!HMR0SuspendPending());
4575	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4576	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4577	(unsigned)RTMpCpuId(), *pcLoops));
4578
4579	/* Preparatory work for running guest code, this may force us to return
4580	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4581	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4582	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4583	if (rc != VINF_SUCCESS)
4584	break;
4585
4586	/*
4587	* No longjmps to ring-3 from this point on!!!
4588	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4589	* This also disables flushing of the R0-logger instance (if any).
4590	*/
4591	VMMRZCallRing3Disable(pVCpu);
4592	VMMRZCallRing3RemoveNotification(pVCpu);
4593	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4594
4595	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4596
4597	/*
4598	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4599	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4600	*/
4601	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4602	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4603	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4604	{
4605	if (rc == VINF_SUCCESS)
4606	rc = VERR_SVM_INVALID_GUEST_STATE;
4607	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4608	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4609	return rc;
4610	}
4611
4612	/* Handle the #VMEXIT. */
4613	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4614	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4615	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4616	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4617	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4618	if (rc != VINF_SUCCESS)
4619	break;
4620	if (++(*pcLoops) >= cMaxResumeLoops)
4621	{
4622	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4623	rc = VINF_EM_RAW_INTERRUPT;
4624	break;
4625	}
4626
4627	/*
4628	* Did the RIP change, if so, consider it a single step.
4629	* Otherwise, make sure one of the TFs gets set.
4630	*/
4631	if ( pCtx->rip != uRipStart
4632	\|\| pCtx->cs.Sel != uCsStart)
4633	{
4634	rc = VINF_EM_DBG_STEPPED;
4635	break;
4636	}
4637	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4638	}
4639
4640	/*
4641	* Clear the X86_EFL_TF if necessary.
4642	*/
4643	if (pVCpu->hm.s.fClearTrapFlag)
4644	{
4645	pVCpu->hm.s.fClearTrapFlag = false;
4646	pCtx->eflags.Bits.u1TF = 0;
4647	}
4648
4649	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4650	return rc;
4651	}
4652
4653	#ifdef VBOX_WITH_NESTED_HWVIRT
4654	/**
4655	* Runs the nested-guest code using AMD-V.
4656	*
4657	* @returns VBox status code.
4658	* @param pVM The cross context VM structure.
4659	* @param pVCpu The cross context virtual CPU structure.
4660	* @param pCtx Pointer to the guest-CPU context.
4661	* @param pcLoops Pointer to the number of executed loops. If we're switching
4662	* from the guest-code execution loop to this nested-guest
4663	* execution loop pass the remainder value, else pass 0.
4664	*/
4665	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4666	{
4667	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4668	Assert(pcLoops);
4669	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4670
4671	SVMTRANSIENT SvmTransient;
4672	SvmTransient.fUpdateTscOffsetting = true;
4673
4674	int rc = VERR_INTERNAL_ERROR_4;
4675	for (;;)
4676	{
4677	Assert(!HMR0SuspendPending());
4678	HMSVM_ASSERT_CPU_SAFE();
4679
4680	/* Preparatory work for running nested-guest code, this may force us to return
4681	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4682	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4683	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4684	if (rc != VINF_SUCCESS)
4685	break;
4686
4687	/*
4688	* No longjmps to ring-3 from this point on!!!
4689	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4690	* This also disables flushing of the R0-logger instance (if any).
4691	*/
4692	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4693
4694	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4695
4696	/* Restore any residual host-state and save any bits shared between host
4697	and guest into the guest-CPU state. Re-enables interrupts! */
4698	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4699
4700	/** @todo This needs some work... we probably should cause a \#VMEXIT on
4701	* SVM_EXIT_INVALID and handle rc != VINF_SUCCESS differently. */
4702	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4703	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4704	{
4705	if (rc == VINF_SUCCESS)
4706	rc = VERR_SVM_INVALID_GUEST_STATE;
4707	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4708	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4709	break;
4710	}
4711
4712	/* Handle the #VMEXIT. */
4713	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4714	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4715	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4716	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4717	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4718	if (rc != VINF_SUCCESS)
4719	break;
4720	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4721	{
4722	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4723	rc = VINF_EM_RAW_INTERRUPT;
4724	break;
4725	}
4726
4727	/** @todo handle single-stepping */
4728	}
4729
4730	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4731	return rc;
4732	}
4733	#endif
4734
4735
4736	/**
4737	* Runs the guest code using AMD-V.
4738	*
4739	* @returns Strict VBox status code.
4740	* @param pVM The cross context VM structure.
4741	* @param pVCpu The cross context virtual CPU structure.
4742	* @param pCtx Pointer to the guest-CPU context.
4743	*/
4744	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4745	{
4746	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4747	HMSVM_ASSERT_PREEMPT_SAFE();
4748	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4749
4750	uint32_t cLoops = 0;
4751	int rc;
4752	#ifdef VBOX_WITH_NESTED_HWVIRT
4753	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4754	#endif
4755	{
4756	if (!pVCpu->hm.s.fSingleInstruction)
4757	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4758	else
4759	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4760	}
4761	#ifdef VBOX_WITH_NESTED_HWVIRT
4762	else
4763	{
4764	rc = VINF_SVM_VMRUN;
4765	}
4766
4767	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4768	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4769	if (rc == VINF_SVM_VMRUN)
4770	{
4771	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4772	if (rc == VINF_SVM_VMEXIT)
4773	rc = VINF_SUCCESS;
4774	}
4775	#endif
4776
4777	/* Fixup error codes. */
4778	if (rc == VERR_EM_INTERPRETER)
4779	rc = VINF_EM_RAW_EMULATE_INSTR;
4780	else if (rc == VINF_EM_RESET)
4781	rc = VINF_EM_TRIPLE_FAULT;
4782
4783	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4784	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4785	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4786	return rc;
4787	}
4788
4789
4790	#ifdef VBOX_WITH_NESTED_HWVIRT
4791	/**
4792	* Determines whether an IOIO intercept is active for the nested-guest or not.
4793	*
4794	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4795	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4796	*/
4797	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4798	{
4799	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4800	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4801	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4802	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4803	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4804	const bool fRep = pIoExitInfo->n.u1REP;
4805	const bool fStrIo = pIoExitInfo->n.u1STR;
4806
4807	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4808	NULL /* pIoExitInfo */);
4809	}
4810
4811
4812	/**
4813	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4814	* SVM_EXIT_INVALID).
4815	*
4816	* @returns VBox status code (informational status codes included).
4817	* @param pVCpu The cross context virtual CPU structure.
4818	* @param pCtx Pointer to the guest-CPU context.
4819	* @param pSvmTransient Pointer to the SVM transient structure.
4820	*/
4821	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4822	{
4823	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4824	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4825	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4826
4827	#define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4828	VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
4829
4830	/*
4831	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4832	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
4833	*/
4834	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4835	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4836	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4837	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4838	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4839
4840	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4841	switch (uExitCode)
4842	{
4843	case SVM_EXIT_CPUID:
4844	{
4845	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4846	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4847	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
4848	}
4849
4850	case SVM_EXIT_RDTSC:
4851	{
4852	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4853	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4854	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
4855	}
4856
4857	case SVM_EXIT_RDTSCP:
4858	{
4859	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4860	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4861	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
4862	}
4863
4864
4865	case SVM_EXIT_MONITOR:
4866	{
4867	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4868	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4869	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
4870	}
4871
4872	case SVM_EXIT_MWAIT:
4873	{
4874	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4875	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4876	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
4877	}
4878
4879	case SVM_EXIT_HLT:
4880	{
4881	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4882	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4883	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
4884	}
4885
4886	case SVM_EXIT_MSR:
4887	{
4888	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4889	{
4890	uint32_t const idMsr = pCtx->ecx;
4891	uint16_t offMsrpm;
4892	uint32_t uMsrpmBit;
4893	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4894	if (RT_SUCCESS(rc))
4895	{
4896	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4897	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
4898	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
4899
4900	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4901	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4902	{
4903	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4904	}
4905	}
4906	else
4907	{
4908	/*
4909	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4910	* See AMD-V spec. "15.11 MSR Intercepts".
4911	*/
4912	Assert(rc == VERR_OUT_OF_RANGE);
4913	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4914	}
4915	}
4916	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
4917	}
4918
4919	case SVM_EXIT_IOIO:
4920	{
4921	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4922	{
4923	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
4924	SVMIOIOEXITINFO IoExitInfo;
4925	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4926	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
4927	if (fIntercept)
4928	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4929	}
4930	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
4931	}
4932
4933	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
4934	{
4935	PVM pVM = pVCpu->CTX_SUFF(pVM);
4936	if (pVM->hm.s.fNestedPaging)
4937	{
4938	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4939	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4940
4941	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4942	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4943	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4944
4945	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
4946	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
4947	return VINF_SUCCESS;
4948	}
4949	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
4950	}
4951
4952	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
4953	{
4954	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_NM))
4955	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4956	hmR0SvmSetPendingXcptNM(pVCpu);
4957	return VINF_SUCCESS;
4958	}
4959
4960	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
4961	{
4962	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
4963	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4964	hmR0SvmSetPendingXcptUD(pVCpu);
4965	return VINF_SUCCESS;
4966	}
4967
4968	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
4969	{
4970	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
4971	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4972	hmR0SvmSetPendingXcptMF(pVCpu);
4973	return VINF_SUCCESS;
4974	}
4975
4976	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
4977	{
4978	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
4979	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4980	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
4981	}
4982
4983	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
4984	{
4985	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
4986	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4987	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
4988	}
4989
4990	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
4991	{
4992	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
4993	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4994	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
4995	}
4996
4997	case SVM_EXIT_READ_CR0:
4998	case SVM_EXIT_READ_CR3:
4999	case SVM_EXIT_READ_CR4:
5000	{
5001	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5002	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5003	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5004	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5005	}
5006
5007	case SVM_EXIT_WRITE_CR0:
5008	case SVM_EXIT_WRITE_CR3:
5009	case SVM_EXIT_WRITE_CR4:
5010	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
5011	{
5012	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5013	Log4(("hmR0SvmHandleExitNested: Write CRx: u16InterceptWrCRx=%#x u64ExitCode=%#RX64 %#x\n",
5014	pVmcbNstGstCtrl->u16InterceptWrCRx, pSvmTransient->u64ExitCode, uCr));
5015
5016	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5017	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5018	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5019	}
5020
5021	case SVM_EXIT_PAUSE:
5022	{
5023	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5024	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5025	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5026	}
5027
5028	case SVM_EXIT_VINTR:
5029	{
5030	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5031	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5032	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5033	}
5034
5035	case SVM_EXIT_INTR:
5036	case SVM_EXIT_NMI:
5037	case SVM_EXIT_SMI:
5038	{
5039	/*
5040	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5041	*
5042	* Although we don't intercept SMIs, the nested-guest might. Therefore, we
5043	* might get an SMI #VMEXIT here so simply ignore rather than causing a
5044	* corresponding nested-guest #VMEXIT.
5045	*/
5046	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5047	}
5048
5049	case SVM_EXIT_FERR_FREEZE:
5050	{
5051	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5052	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5053	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5054	}
5055
5056	case SVM_EXIT_INVLPG:
5057	{
5058	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5059	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5060	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5061	}
5062
5063	case SVM_EXIT_WBINVD:
5064	{
5065	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5066	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5067	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5068	}
5069
5070	case SVM_EXIT_INVD:
5071	{
5072	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5073	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5074	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5075	}
5076
5077	case SVM_EXIT_RDPMC:
5078	{
5079	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5080	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5081	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5082	}
5083
5084	default:
5085	{
5086	switch (uExitCode)
5087	{
5088	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5089	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5090	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5091	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5092	{
5093	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5094	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5095	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5096	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5097	}
5098
5099	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5100	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5101	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5102	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5103	{
5104	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5105	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5106	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5107	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5108	}
5109
5110	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
5111	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
5112	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
5113	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
5114	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
5115	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
5116	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
5117	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
5118	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
5119	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
5120	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
5121	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5122	{
5123	uint8_t const uVector = uExitCode - SVM_EXIT_EXCEPTION_0;
5124	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5125	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5126	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5127	}
5128
5129	case SVM_EXIT_XSETBV:
5130	{
5131	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5132	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5133	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5134	}
5135
5136	case SVM_EXIT_TASK_SWITCH:
5137	{
5138	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5139	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5140	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5141	}
5142
5143	case SVM_EXIT_IRET:
5144	{
5145	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5146	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5147	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5148	}
5149
5150	case SVM_EXIT_SHUTDOWN:
5151	{
5152	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5153	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5154	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5155	}
5156
5157	case SVM_EXIT_VMMCALL:
5158	{
5159	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5160	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5161	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5162	}
5163
5164	case SVM_EXIT_CLGI:
5165	{
5166	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5167	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5168	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5169	}
5170
5171	case SVM_EXIT_STGI:
5172	{
5173	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5174	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5175	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5176	}
5177
5178	case SVM_EXIT_VMLOAD:
5179	{
5180	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5181	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5182	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5183	}
5184
5185	case SVM_EXIT_VMSAVE:
5186	{
5187	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5188	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5189	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5190	}
5191
5192	case SVM_EXIT_INVLPGA:
5193	{
5194	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5195	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5196	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5197	}
5198
5199	case SVM_EXIT_VMRUN:
5200	{
5201	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5202	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5203	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5204	}
5205
5206	case SVM_EXIT_RSM:
5207	{
5208	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5209	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5210	hmR0SvmSetPendingXcptUD(pVCpu);
5211	return VINF_SUCCESS;
5212	}
5213
5214	case SVM_EXIT_SKINIT:
5215	{
5216	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5217	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5218	hmR0SvmSetPendingXcptUD(pVCpu);
5219	return VINF_SUCCESS;
5220	}
5221
5222	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5223	case SVM_EXIT_NPF: /* We don't yet support nested-paging for nested-guests, so this should never happen. */
5224	{
5225	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5226	}
5227
5228	default:
5229	{
5230	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5231	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5232	return VERR_SVM_UNKNOWN_EXIT;
5233	}
5234	}
5235	}
5236	}
5237	/* not reached */
5238
5239	#undef HM_SVM_VMEXIT_NESTED
5240	}
5241	#endif
5242
5243
5244	/**
5245	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5246	*
5247	* @returns VBox status code (informational status codes included).
5248	* @param pVCpu The cross context virtual CPU structure.
5249	* @param pCtx Pointer to the guest-CPU context.
5250	* @param pSvmTransient Pointer to the SVM transient structure.
5251	*/
5252	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5253	{
5254	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5255	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5256
5257	/*
5258	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5259	* normal workloads (for some definition of "normal").
5260	*/
5261	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5262	switch (uExitCode)
5263	{
5264	case SVM_EXIT_NPF:
5265	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5266
5267	case SVM_EXIT_IOIO:
5268	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5269
5270	case SVM_EXIT_RDTSC:
5271	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5272
5273	case SVM_EXIT_RDTSCP:
5274	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5275
5276	case SVM_EXIT_CPUID:
5277	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5278
5279	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5280	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5281
5282	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5283	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5284
5285	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5286	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5287
5288	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5289	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5290
5291	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5292	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5293
5294	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5295	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5296
5297	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5298	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5299
5300	case SVM_EXIT_MONITOR:
5301	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5302
5303	case SVM_EXIT_MWAIT:
5304	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5305
5306	case SVM_EXIT_HLT:
5307	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5308
5309	case SVM_EXIT_READ_CR0:
5310	case SVM_EXIT_READ_CR3:
5311	case SVM_EXIT_READ_CR4:
5312	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5313
5314	case SVM_EXIT_WRITE_CR0:
5315	case SVM_EXIT_WRITE_CR3:
5316	case SVM_EXIT_WRITE_CR4:
5317	case SVM_EXIT_WRITE_CR8:
5318	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5319
5320	case SVM_EXIT_PAUSE:
5321	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5322
5323	case SVM_EXIT_VMMCALL:
5324	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5325
5326	case SVM_EXIT_VINTR:
5327	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5328
5329	case SVM_EXIT_INTR:
5330	case SVM_EXIT_FERR_FREEZE:
5331	case SVM_EXIT_NMI:
5332	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5333
5334	case SVM_EXIT_MSR:
5335	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5336
5337	case SVM_EXIT_INVLPG:
5338	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5339
5340	case SVM_EXIT_WBINVD:
5341	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5342
5343	case SVM_EXIT_INVD:
5344	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5345
5346	case SVM_EXIT_RDPMC:
5347	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5348
5349	default:
5350	{
5351	switch (pSvmTransient->u64ExitCode)
5352	{
5353	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5354	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5355	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5356	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5357	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5358
5359	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5360	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5361	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5362	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5363	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5364
5365	case SVM_EXIT_XSETBV:
5366	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5367
5368	case SVM_EXIT_TASK_SWITCH:
5369	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5370
5371	case SVM_EXIT_IRET:
5372	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5373
5374	case SVM_EXIT_SHUTDOWN:
5375	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5376
5377	case SVM_EXIT_SMI:
5378	case SVM_EXIT_INIT:
5379	{
5380	/*
5381	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5382	* If it ever does, we want to know about it so log the exit code and bail.
5383	*/
5384	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5385	}
5386
5387	#ifdef VBOX_WITH_NESTED_HWVIRT
5388	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5389	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5390	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5391	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5392	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5393	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5394	#else
5395	case SVM_EXIT_CLGI:
5396	case SVM_EXIT_STGI:
5397	case SVM_EXIT_VMLOAD:
5398	case SVM_EXIT_VMSAVE:
5399	case SVM_EXIT_INVLPGA:
5400	case SVM_EXIT_VMRUN:
5401	#endif
5402	case SVM_EXIT_RSM:
5403	case SVM_EXIT_SKINIT:
5404	{
5405	hmR0SvmSetPendingXcptUD(pVCpu);
5406	return VINF_SUCCESS;
5407	}
5408
5409	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5410	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5411	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5412	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5413	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5414	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5415	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5416	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5417	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5418	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5419	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5420	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5421	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5422	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5423	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5424	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5425	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5426	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5427	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5428	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5429	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5430	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5431	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5432	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5433	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5434	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5435	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5436
5437	default:
5438	{
5439	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5440	pVCpu->hm.s.u32HMError = uExitCode;
5441	return VERR_SVM_UNKNOWN_EXIT;
5442	}
5443	}
5444	}
5445	}
5446	/* not reached */
5447	}
5448
5449
5450	#ifdef DEBUG
5451	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5452	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5453	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5454
5455	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5456	do \
5457	{ \
5458	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5459	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5460	} while (0)
5461
5462	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5463	do { \
5464	AssertPtr(pVCpu); \
5465	AssertPtr(pCtx); \
5466	AssertPtr(pSvmTransient); \
5467	Assert(ASMIntAreEnabled()); \
5468	HMSVM_ASSERT_PREEMPT_SAFE(); \
5469	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5470	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5471	HMSVM_ASSERT_PREEMPT_SAFE(); \
5472	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5473	HMSVM_ASSERT_PREEMPT_CPUID(); \
5474	} while (0)
5475	#else /* Release builds */
5476	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5477	#endif
5478
5479
5480	/**
5481	* Worker for hmR0SvmInterpretInvlpg().
5482	*
5483	* @return VBox status code.
5484	* @param pVCpu The cross context virtual CPU structure.
5485	* @param pCpu Pointer to the disassembler state.
5486	* @param pCtx The guest CPU context.
5487	*/
5488	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5489	{
5490	DISQPVPARAMVAL Param1;
5491	RTGCPTR GCPtrPage;
5492
5493	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5494	if (RT_FAILURE(rc))
5495	return VERR_EM_INTERPRETER;
5496
5497	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5498	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5499	{
5500	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5501	return VERR_EM_INTERPRETER;
5502
5503	GCPtrPage = Param1.val.val64;
5504	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5505	rc = VBOXSTRICTRC_VAL(rc2);
5506	}
5507	else
5508	{
5509	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5510	rc = VERR_EM_INTERPRETER;
5511	}
5512
5513	return rc;
5514	}
5515
5516
5517	/**
5518	* Interprets INVLPG.
5519	*
5520	* @returns VBox status code.
5521	* @retval VINF_* Scheduling instructions.
5522	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5523	* @retval VERR_* Fatal errors.
5524	*
5525	* @param pVM The cross context VM structure.
5526	* @param pVCpu The cross context virtual CPU structure.
5527	* @param pCtx The guest CPU context.
5528	*
5529	* @remarks Updates the RIP if the instruction was executed successfully.
5530	*/
5531	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5532	{
5533	/* Only allow 32 & 64 bit code. */
5534	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5535	{
5536	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5537	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5538	if ( RT_SUCCESS(rc)
5539	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5540	{
5541	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5542	if (RT_SUCCESS(rc))
5543	pCtx->rip += pDis->cbInstr;
5544	return rc;
5545	}
5546	else
5547	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5548	}
5549	return VERR_EM_INTERPRETER;
5550	}
5551
5552
5553	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5554	/**
5555	* Gets the IEM exception flags for the specified SVM event.
5556	*
5557	* @returns The IEM exception flags.
5558	* @param pEvent Pointer to the SVM event.
5559	*
5560	* @remarks This function currently only constructs flags required for
5561	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5562	* and CR2 aspects of an exception are not included).
5563	*/
5564	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5565	{
5566	uint8_t const uEventType = pEvent->n.u3Type;
5567	uint32_t fIemXcptFlags;
5568	switch (uEventType)
5569	{
5570	case SVM_EVENT_EXCEPTION:
5571	/*
5572	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5573	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5574	*/
5575	if (pEvent->n.u8Vector == X86_XCPT_BP)
5576	{
5577	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5578	break;
5579	}
5580	if (pEvent->n.u8Vector == X86_XCPT_OF)
5581	{
5582	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5583	break;
5584	}
5585	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5586	RT_FALL_THRU();
5587	case SVM_EVENT_NMI:
5588	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5589	break;
5590
5591	case SVM_EVENT_EXTERNAL_IRQ:
5592	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5593	break;
5594
5595	case SVM_EVENT_SOFTWARE_INT:
5596	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5597	break;
5598
5599	default:
5600	fIemXcptFlags = 0;
5601	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5602	break;
5603	}
5604	return fIemXcptFlags;
5605	}
5606
5607	#else
5608	/**
5609	* Determines if an exception is a contributory exception.
5610	*
5611	* Contributory exceptions are ones which can cause double-faults unless the
5612	* original exception was a benign exception. Page-fault is intentionally not
5613	* included here as it's a conditional contributory exception.
5614	*
5615	* @returns @c true if the exception is contributory, @c false otherwise.
5616	* @param uVector The exception vector.
5617	*/
5618	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5619	{
5620	switch (uVector)
5621	{
5622	case X86_XCPT_GP:
5623	case X86_XCPT_SS:
5624	case X86_XCPT_NP:
5625	case X86_XCPT_TS:
5626	case X86_XCPT_DE:
5627	return true;
5628	default:
5629	break;
5630	}
5631	return false;
5632	}
5633	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5634
5635
5636	/**
5637	* Handle a condition that occurred while delivering an event through the guest
5638	* IDT.
5639	*
5640	* @returns VBox status code (informational error codes included).
5641	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5642	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5643	* continue execution of the guest which will delivery the \#DF.
5644	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5645	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5646	*
5647	* @param pVCpu The cross context virtual CPU structure.
5648	* @param pCtx Pointer to the guest-CPU context.
5649	* @param pSvmTransient Pointer to the SVM transient structure.
5650	*
5651	* @remarks No-long-jump zone!!!
5652	*/
5653	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5654	{
5655	int rc = VINF_SUCCESS;
5656	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5657
5658	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5659	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5660	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5661
5662	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5663	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5664	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5665	{
5666	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5667	IEMXCPTRAISE enmRaise;
5668	IEMXCPTRAISEINFO fRaiseInfo;
5669	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5670	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5671	if (fExitIsHwXcpt)
5672	{
5673	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5674	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5675	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5676	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5677	}
5678	else
5679	{
5680	/*
5681	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5682	* end up here.
5683	*
5684	* If the event was:
5685	* - a software interrupt, we can re-execute the instruction which will regenerate
5686	* the event.
5687	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5688	* - a hardware exception or external interrupt, we re-inject it.
5689	*/
5690	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5691	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5692	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5693	else
5694	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5695	}
5696
5697	switch (enmRaise)
5698	{
5699	case IEMXCPTRAISE_CURRENT_XCPT:
5700	case IEMXCPTRAISE_PREV_EVENT:
5701	{
5702	/* For software interrupts, we shall re-execute the instruction. */
5703	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5704	{
5705	RTGCUINTPTR GCPtrFaultAddress = 0;
5706
5707	/* If we are re-injecting an NMI, clear NMI blocking. */
5708	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5709	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5710
5711	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5712	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5713	pSvmTransient->fVectoringPF = true;
5714	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5715	&& uIdtVector == X86_XCPT_PF)
5716	{
5717	/*
5718	* If the previous exception was a #PF, we need to recover the CR2 value.
5719	* This can't happen with shadow paging.
5720	*/
5721	GCPtrFaultAddress = pCtx->cr2;
5722	}
5723
5724	/*
5725	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5726	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5727	*/
5728	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5729	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5730	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5731
5732	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5733	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5734	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5735	}
5736	break;
5737	}
5738
5739	case IEMXCPTRAISE_REEXEC_INSTR:
5740	{
5741	Assert(rc == VINF_SUCCESS);
5742	break;
5743	}
5744
5745	case IEMXCPTRAISE_DOUBLE_FAULT:
5746	{
5747	/*
5748	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5749	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5750	*/
5751	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5752	{
5753	pSvmTransient->fVectoringDoublePF = true;
5754	Assert(rc == VINF_SUCCESS);
5755	}
5756	else
5757	{
5758	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5759	hmR0SvmSetPendingXcptDF(pVCpu);
5760	rc = VINF_HM_DOUBLE_FAULT;
5761	}
5762	break;
5763	}
5764
5765	case IEMXCPTRAISE_TRIPLE_FAULT:
5766	{
5767	rc = VINF_EM_RESET;
5768	break;
5769	}
5770
5771	case IEMXCPTRAISE_CPU_HANG:
5772	{
5773	rc = VERR_EM_GUEST_CPU_HANG;
5774	break;
5775	}
5776
5777	default:
5778	{
5779	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5780	rc = VERR_SVM_IPE_2;
5781	break;
5782	}
5783	}
5784	#else
5785	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5786
5787	typedef enum
5788	{
5789	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5790	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5791	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5792	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5793	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5794	} SVMREFLECTXCPT;
5795
5796	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5797	bool fReflectingNmi = false;
5798	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5799	{
5800	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5801	{
5802	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5803
5804	#ifdef VBOX_STRICT
5805	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5806	&& uExitVector == X86_XCPT_PF)
5807	{
5808	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5809	}
5810	#endif
5811
5812	if ( uIdtVector == X86_XCPT_BP
5813	\|\| uIdtVector == X86_XCPT_OF)
5814	{
5815	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5816	}
5817	else if ( uExitVector == X86_XCPT_PF
5818	&& uIdtVector == X86_XCPT_PF)
5819	{
5820	pSvmTransient->fVectoringDoublePF = true;
5821	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
5822	}
5823	else if ( uExitVector == X86_XCPT_AC
5824	&& uIdtVector == X86_XCPT_AC)
5825	{
5826	enmReflect = SVMREFLECTXCPT_HANG;
5827	Log4(("IDT: Nested #AC - Bad guest\n"));
5828	}
5829	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
5830	&& hmR0SvmIsContributoryXcpt(uExitVector)
5831	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
5832	\|\| uIdtVector == X86_XCPT_PF))
5833	{
5834	enmReflect = SVMREFLECTXCPT_DF;
5835	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
5836	uIdtVector, uExitVector));
5837	}
5838	else if (uIdtVector == X86_XCPT_DF)
5839	{
5840	enmReflect = SVMREFLECTXCPT_TF;
5841	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
5842	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
5843	}
5844	else
5845	enmReflect = SVMREFLECTXCPT_XCPT;
5846	}
5847	else
5848	{
5849	/*
5850	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
5851	* exception to the guest after handling the #VMEXIT.
5852	*/
5853	enmReflect = SVMREFLECTXCPT_XCPT;
5854	}
5855	}
5856	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
5857	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5858	{
5859	enmReflect = SVMREFLECTXCPT_XCPT;
5860	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
5861
5862	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5863	{
5864	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5865	if (uExitVector == X86_XCPT_PF)
5866	{
5867	pSvmTransient->fVectoringPF = true;
5868	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
5869	}
5870	}
5871	}
5872	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
5873
5874	switch (enmReflect)
5875	{
5876	case SVMREFLECTXCPT_XCPT:
5877	{
5878	/* If we are re-injecting the NMI, clear NMI blocking. */
5879	if (fReflectingNmi)
5880	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5881
5882	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5883	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5884	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
5885
5886	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
5887	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
5888	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
5889	break;
5890	}
5891
5892	case SVMREFLECTXCPT_DF:
5893	{
5894	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5895	hmR0SvmSetPendingXcptDF(pVCpu);
5896	rc = VINF_HM_DOUBLE_FAULT;
5897	break;
5898	}
5899
5900	case SVMREFLECTXCPT_TF:
5901	{
5902	rc = VINF_EM_RESET;
5903	break;
5904	}
5905
5906	case SVMREFLECTXCPT_HANG:
5907	{
5908	rc = VERR_EM_GUEST_CPU_HANG;
5909	break;
5910	}
5911
5912	default:
5913	Assert(rc == VINF_SUCCESS);
5914	break;
5915	}
5916	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5917	}
5918	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5919	NOREF(pCtx);
5920	return rc;
5921	}
5922
5923
5924	/**
5925	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
5926	* supported, otherwise advances the RIP by the number of bytes specified in
5927	* @a cb.
5928	*
5929	* @param pVCpu The cross context virtual CPU structure.
5930	* @param pCtx Pointer to the guest-CPU context.
5931	* @param cb RIP increment value in bytes.
5932	*
5933	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
5934	* when NRIP_SAVE is supported by the CPU, otherwise use
5935	* hmR0SvmAdvanceRipDumb!
5936	*/
5937	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5938	{
5939	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
5940	if (fSupportsNextRipSave)
5941	{
5942	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5943	Assert(pVmcb->ctrl.u64NextRIP);
5944	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
5945	pCtx->rip = pVmcb->ctrl.u64NextRIP;
5946	}
5947	else
5948	pCtx->rip += cb;
5949
5950	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5951	}
5952
5953
5954	#ifdef VBOX_WITH_NESTED_HWVIRT
5955	/**
5956	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
5957	* feature. Otherwise, returns the value in @a cbLikely.
5958	*
5959	* @param pVCpu The cross context virtual CPU structure.
5960	* @param pCtx Pointer to the guest-CPU context.
5961	* @param cbLikely The likely instruction length.
5962	*/
5963	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
5964	{
5965	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
5966	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
5967	if (fSupportsNextRipSave)
5968	{
5969	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5970	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
5971	Assert(cbInstr == cbLikely);
5972	return cbInstr;
5973	}
5974	return cbLikely;
5975	}
5976	#endif
5977
5978
5979	/**
5980	* Advances the guest RIP by the number of bytes specified in @a cb. This does
5981	* not make use of any hardware features to determine the instruction length.
5982	*
5983	* @param pVCpu The cross context virtual CPU structure.
5984	* @param pCtx Pointer to the guest-CPU context.
5985	* @param cb RIP increment value in bytes.
5986	*/
5987	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
5988	{
5989	pCtx->rip += cb;
5990	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
5991	}
5992	#undef HMSVM_UPDATE_INTR_SHADOW
5993
5994
5995	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5996	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5997	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5998
5999	/** @name \#VMEXIT handlers.
6000	* @{
6001	*/
6002
6003	/**
6004	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6005	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6006	*/
6007	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6008	{
6009	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6010
6011	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6012	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6013	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6014	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6015
6016	/*
6017	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
6018	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
6019	* interrupt it is until the host actually take the interrupt.
6020	*
6021	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
6022	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6023	*/
6024	return VINF_EM_RAW_INTERRUPT;
6025	}
6026
6027
6028	/**
6029	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6030	*/
6031	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6032	{
6033	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6034
6035	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6036	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
6037	int rc = VINF_SUCCESS;
6038	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6039	return rc;
6040	}
6041
6042
6043	/**
6044	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6045	*/
6046	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6047	{
6048	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6049
6050	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6051	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
6052	int rc = VINF_SUCCESS;
6053	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6054	return rc;
6055	}
6056
6057
6058	/**
6059	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6060	*/
6061	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6062	{
6063	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6064	PVM pVM = pVCpu->CTX_SUFF(pVM);
6065	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6066	if (RT_LIKELY(rc == VINF_SUCCESS))
6067	{
6068	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6069	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6070	}
6071	else
6072	{
6073	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6074	rc = VERR_EM_INTERPRETER;
6075	}
6076	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
6077	return rc;
6078	}
6079
6080
6081	/**
6082	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6083	*/
6084	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6085	{
6086	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6087	PVM pVM = pVCpu->CTX_SUFF(pVM);
6088	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6089	if (RT_LIKELY(rc == VINF_SUCCESS))
6090	{
6091	pSvmTransient->fUpdateTscOffsetting = true;
6092	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6093	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6094	}
6095	else
6096	{
6097	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
6098	rc = VERR_EM_INTERPRETER;
6099	}
6100	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
6101	return rc;
6102	}
6103
6104
6105	/**
6106	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6107	*/
6108	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6109	{
6110	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6111	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
6112	if (RT_LIKELY(rc == VINF_SUCCESS))
6113	{
6114	pSvmTransient->fUpdateTscOffsetting = true;
6115	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6116	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6117	}
6118	else
6119	{
6120	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
6121	rc = VERR_EM_INTERPRETER;
6122	}
6123	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
6124	return rc;
6125	}
6126
6127
6128	/**
6129	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6130	*/
6131	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6132	{
6133	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6134	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6135	if (RT_LIKELY(rc == VINF_SUCCESS))
6136	{
6137	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6138	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6139	}
6140	else
6141	{
6142	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6143	rc = VERR_EM_INTERPRETER;
6144	}
6145	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6146	return rc;
6147	}
6148
6149
6150	/**
6151	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6152	*/
6153	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6154	{
6155	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6156	PVM pVM = pVCpu->CTX_SUFF(pVM);
6157	Assert(!pVM->hm.s.fNestedPaging);
6158	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6159
6160	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6161	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6162	if ( fSupportsDecodeAssists
6163	&& fSupportsNextRipSave)
6164	{
6165	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6166	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6167	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6168	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6169	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6170	return VBOXSTRICTRC_VAL(rcStrict);
6171	}
6172
6173	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6174	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6175	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6176	return rc;
6177	}
6178
6179
6180	/**
6181	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6182	*/
6183	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6184	{
6185	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6186
6187	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6188	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6189	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6190	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6191	if (rc != VINF_SUCCESS)
6192	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6193	return rc;
6194	}
6195
6196
6197	/**
6198	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6199	*/
6200	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6201	{
6202	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6203	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6204	if (RT_LIKELY(rc == VINF_SUCCESS))
6205	{
6206	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6207	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6208	}
6209	else
6210	{
6211	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6212	rc = VERR_EM_INTERPRETER;
6213	}
6214	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6215	return rc;
6216	}
6217
6218
6219	/**
6220	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6221	*/
6222	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6223	{
6224	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6225	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6226	int rc = VBOXSTRICTRC_VAL(rc2);
6227	if ( rc == VINF_EM_HALT
6228	\|\| rc == VINF_SUCCESS)
6229	{
6230	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6231
6232	if ( rc == VINF_EM_HALT
6233	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6234	{
6235	rc = VINF_SUCCESS;
6236	}
6237	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6238	}
6239	else
6240	{
6241	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6242	rc = VERR_EM_INTERPRETER;
6243	}
6244	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6245	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6246	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6247	return rc;
6248	}
6249
6250
6251	/**
6252	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6253	* \#VMEXIT.
6254	*/
6255	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6256	{
6257	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6258	return VINF_EM_RESET;
6259	}
6260
6261
6262	/**
6263	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6264	*/
6265	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6266	{
6267	RT_NOREF(pCtx);
6268	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64\n", pSvmTransient->u64ExitCode));
6269	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6270	return VERR_SVM_UNEXPECTED_EXIT;
6271	}
6272
6273
6274	/**
6275	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6276	*/
6277	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6278	{
6279	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6280
6281	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6282	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6283
6284	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6285	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6286	if ( fSupportsDecodeAssists
6287	&& fSupportsNextRipSave)
6288	{
6289	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6290	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6291	if (fMovCRx)
6292	{
6293	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6294	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6295	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6296	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6297	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6298	return VBOXSTRICTRC_VAL(rcStrict);
6299	}
6300	/* else: SMSW instruction, fall back below to IEM for this. */
6301	}
6302
6303	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6304	int rc = VBOXSTRICTRC_VAL(rc2);
6305	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6306	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6307	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6308	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6309	return rc;
6310	}
6311
6312
6313	/**
6314	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6315	*/
6316	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6317	{
6318	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6319
6320	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6321	Assert(iCrReg <= 15);
6322
6323	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6324	bool fDecodedInstr = false;
6325	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6326	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6327	if ( fSupportsDecodeAssists
6328	&& fSupportsNextRipSave)
6329	{
6330	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6331	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6332	if (fMovCRx)
6333	{
6334	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6335	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6336	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6337	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6338	fDecodedInstr = true;
6339	}
6340	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6341	}
6342
6343	if (!fDecodedInstr)
6344	{
6345	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6346	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6347	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6348	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6349	rcStrict = VERR_EM_INTERPRETER;
6350	}
6351
6352	if (rcStrict == VINF_SUCCESS)
6353	{
6354	switch (iCrReg)
6355	{
6356	case 0: /* CR0. */
6357	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6358	break;
6359
6360	case 3: /* CR3. */
6361	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6362	break;
6363
6364	case 4: /* CR4. */
6365	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6366	break;
6367
6368	case 8: /* CR8 (TPR). */
6369	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6370	break;
6371
6372	default:
6373	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6374	pSvmTransient->u64ExitCode, iCrReg));
6375	break;
6376	}
6377	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6378	}
6379	else
6380	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6381	return VBOXSTRICTRC_TODO(rcStrict);
6382	}
6383
6384
6385	/**
6386	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6387	* \#VMEXIT.
6388	*/
6389	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6390	{
6391	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6392	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6393	PVM pVM = pVCpu->CTX_SUFF(pVM);
6394
6395	int rc;
6396	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6397	{
6398	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6399	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6400
6401	/* Handle TPR patching; intercepted LSTAR write. */
6402	if ( pVM->hm.s.fTPRPatchingActive
6403	&& pCtx->ecx == MSR_K8_LSTAR)
6404	{
6405	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6406	{
6407	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6408	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6409	AssertRC(rc2);
6410	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6411	}
6412	rc = VINF_SUCCESS;
6413	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6414	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6415	return rc;
6416	}
6417
6418	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6419	if (fSupportsNextRipSave)
6420	{
6421	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6422	if (RT_LIKELY(rc == VINF_SUCCESS))
6423	{
6424	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6425	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6426	}
6427	else
6428	AssertMsg( rc == VERR_EM_INTERPRETER
6429	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6430	}
6431	else
6432	{
6433	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6434	if (RT_LIKELY(rc == VINF_SUCCESS))
6435	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6436	else
6437	AssertMsg( rc == VERR_EM_INTERPRETER
6438	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6439	}
6440
6441	if (rc == VINF_SUCCESS)
6442	{
6443	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6444	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6445	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6446	{
6447	/*
6448	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6449	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6450	* EMInterpretWrmsr() changes it.
6451	*/
6452	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6453	}
6454	else if (pCtx->ecx == MSR_K6_EFER)
6455	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
6456	else if (pCtx->ecx == MSR_IA32_TSC)
6457	pSvmTransient->fUpdateTscOffsetting = true;
6458	}
6459	}
6460	else
6461	{
6462	/* MSR Read access. */
6463	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6464	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6465	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6466
6467	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6468	if (fSupportsNextRipSave)
6469	{
6470	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6471	if (RT_LIKELY(rc == VINF_SUCCESS))
6472	{
6473	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6474	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6475	}
6476	else
6477	AssertMsg( rc == VERR_EM_INTERPRETER
6478	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6479	}
6480	else
6481	{
6482	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6483	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6484	{
6485	AssertMsg( rc == VERR_EM_INTERPRETER
6486	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6487	}
6488	/* RIP updated by EMInterpretInstruction(). */
6489	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6490	}
6491	}
6492
6493	/* RIP has been updated by EMInterpret[Rd\|Wr]msr() or EMInterpretInstruction(). */
6494	return rc;
6495	}
6496
6497
6498	/**
6499	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6500	*/
6501	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6502	{
6503	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6504	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6505
6506	/** @todo Stepping with nested-guest. */
6507	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6508	{
6509	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6510	if (pSvmTransient->fWasGuestDebugStateActive)
6511	{
6512	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6513	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6514	return VERR_SVM_UNEXPECTED_EXIT;
6515	}
6516
6517	/*
6518	* Lazy DR0-3 loading.
6519	*/
6520	if (!pSvmTransient->fWasHyperDebugStateActive)
6521	{
6522	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6523	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6524
6525	/* Don't intercept DRx read and writes. */
6526	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6527	pVmcb->ctrl.u16InterceptRdDRx = 0;
6528	pVmcb->ctrl.u16InterceptWrDRx = 0;
6529	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6530
6531	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6532	VMMRZCallRing3Disable(pVCpu);
6533	HM_DISABLE_PREEMPT();
6534
6535	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6536	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6537	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6538
6539	HM_RESTORE_PREEMPT();
6540	VMMRZCallRing3Enable(pVCpu);
6541
6542	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6543	return VINF_SUCCESS;
6544	}
6545	}
6546
6547	/*
6548	* Interpret the read/writing of DRx.
6549	*/
6550	/** @todo Decode assist. */
6551	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6552	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6553	if (RT_LIKELY(rc == VINF_SUCCESS))
6554	{
6555	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6556	/** @todo CPUM should set this flag! */
6557	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6558	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6559	}
6560	else
6561	Assert(rc == VERR_EM_INTERPRETER);
6562	return VBOXSTRICTRC_TODO(rc);
6563	}
6564
6565
6566	/**
6567	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6568	*/
6569	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6570	{
6571	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6572	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6573	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6574	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6575	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6576	return rc;
6577	}
6578
6579
6580	/**
6581	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6582	*/
6583	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6584	{
6585	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6586
6587	/** @todo decode assists... */
6588	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6589	if (rcStrict == VINF_IEM_RAISED_XCPT)
6590	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6591
6592	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6593	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6594	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6595
6596	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6597	return VBOXSTRICTRC_TODO(rcStrict);
6598	}
6599
6600
6601	/**
6602	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6603	*/
6604	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6605	{
6606	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6607
6608	/* I/O operation lookup arrays. */
6609	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6610	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6611	the result (in AL/AX/EAX). */
6612	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6613
6614	PVM pVM = pVCpu->CTX_SUFF(pVM);
6615	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6616
6617	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6618	SVMIOIOEXITINFO IoExitInfo;
6619	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6620	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6621	uint32_t cbValue = s_aIOSize[uIOWidth];
6622	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6623
6624	if (RT_UNLIKELY(!cbValue))
6625	{
6626	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6627	return VERR_EM_INTERPRETER;
6628	}
6629
6630	VBOXSTRICTRC rcStrict;
6631	bool fUpdateRipAlready = false;
6632	if (IoExitInfo.n.u1STR)
6633	{
6634	#ifdef VBOX_WITH_2ND_IEM_STEP
6635	/* INS/OUTS - I/O String instruction. */
6636	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6637	* in EXITINFO1? Investigate once this thing is up and running. */
6638	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6639	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6640	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6641	static IEMMODE const s_aenmAddrMode[8] =
6642	{
6643	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6644	};
6645	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6646	if (enmAddrMode != (IEMMODE)-1)
6647	{
6648	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6649	if (cbInstr <= 15 && cbInstr >= 1)
6650	{
6651	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6652	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6653	{
6654	/* Don't know exactly how to detect whether u3SEG is valid, currently
6655	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6656	2384 Opterons when only checking NRIP. */
6657	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6658	if ( fSupportsNextRipSave
6659	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6660	{
6661	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6662	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6663	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6664	IoExitInfo.n.u3SEG, true /fIoChecked/);
6665	}
6666	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6667	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6668	X86_SREG_DS, true /fIoChecked/);
6669	else
6670	rcStrict = IEMExecOne(pVCpu);
6671	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6672	}
6673	else
6674	{
6675	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6676	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6677	true /fIoChecked/);
6678	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6679	}
6680	}
6681	else
6682	{
6683	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6684	rcStrict = IEMExecOne(pVCpu);
6685	}
6686	}
6687	else
6688	{
6689	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6690	rcStrict = IEMExecOne(pVCpu);
6691	}
6692	fUpdateRipAlready = true;
6693
6694	#else
6695	/* INS/OUTS - I/O String instruction. */
6696	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6697
6698	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6699	* in EXITINFO1? Investigate once this thing is up and running. */
6700
6701	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6702	if (rcStrict == VINF_SUCCESS)
6703	{
6704	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6705	{
6706	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6707	(DISCPUMODE)pDis->uAddrMode, cbValue);
6708	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6709	}
6710	else
6711	{
6712	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6713	(DISCPUMODE)pDis->uAddrMode, cbValue);
6714	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6715	}
6716	}
6717	else
6718	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6719	#endif
6720	}
6721	else
6722	{
6723	/* IN/OUT - I/O instruction. */
6724	Assert(!IoExitInfo.n.u1REP);
6725
6726	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6727	{
6728	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6729	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6730	}
6731	else
6732	{
6733	uint32_t u32Val = 0;
6734	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6735	if (IOM_SUCCESS(rcStrict))
6736	{
6737	/* Save result of I/O IN instr. in AL/AX/EAX. */
6738	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6739	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6740	}
6741	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6742	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6743
6744	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6745	}
6746	}
6747
6748	if (IOM_SUCCESS(rcStrict))
6749	{
6750	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6751	if (!fUpdateRipAlready)
6752	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6753
6754	/*
6755	* If any I/O breakpoints are armed, we need to check if one triggered
6756	* and take appropriate action.
6757	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6758	*/
6759	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6760	* execution engines about whether hyper BPs and such are pending. */
6761	uint32_t const uDr7 = pCtx->dr[7];
6762	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6763	&& X86_DR7_ANY_RW_IO(uDr7)
6764	&& (pCtx->cr4 & X86_CR4_DE))
6765	\|\| DBGFBpIsHwIoArmed(pVM)))
6766	{
6767	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6768	VMMRZCallRing3Disable(pVCpu);
6769	HM_DISABLE_PREEMPT();
6770
6771	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6772	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6773
6774	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6775	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6776	{
6777	/* Raise #DB. */
6778	pVmcb->guest.u64DR6 = pCtx->dr[6];
6779	pVmcb->guest.u64DR7 = pCtx->dr[7];
6780	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6781	hmR0SvmSetPendingXcptDB(pVCpu);
6782	}
6783	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6784	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6785	else if ( rcStrict2 != VINF_SUCCESS
6786	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6787	rcStrict = rcStrict2;
6788	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6789
6790	HM_RESTORE_PREEMPT();
6791	VMMRZCallRing3Enable(pVCpu);
6792	}
6793
6794	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6795	}
6796
6797	#ifdef VBOX_STRICT
6798	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6799	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6800	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6801	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6802	else
6803	{
6804	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6805	* statuses, that the VMM device and some others may return. See
6806	* IOM_SUCCESS() for guidance. */
6807	AssertMsg( RT_FAILURE(rcStrict)
6808	\|\| rcStrict == VINF_SUCCESS
6809	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6810	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6811	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6812	\|\| rcStrict == VINF_EM_RAW_TO_R3
6813	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6814	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6815	}
6816	#endif
6817	return VBOXSTRICTRC_TODO(rcStrict);
6818	}
6819
6820
6821	/**
6822	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6823	*/
6824	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6825	{
6826	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6827	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
6828
6829	PVM pVM = pVCpu->CTX_SUFF(pVM);
6830	Assert(pVM->hm.s.fNestedPaging);
6831
6832	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6833
6834	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6835	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6836	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
6837	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6838
6839	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
6840
6841	#ifdef VBOX_HM_WITH_GUEST_PATCHING
6842	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
6843	if ( pVM->hm.s.fTprPatchingAllowed
6844	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6845	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6846	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6847	&& !CPUMIsGuestInLongModeEx(pCtx)
6848	&& !CPUMGetGuestCPL(pVCpu)
6849	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6850	{
6851	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6852	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6853
6854	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6855	{
6856	/* Only attempt to patch the instruction once. */
6857	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6858	if (!pPatch)
6859	return VINF_EM_HM_PATCH_TPR_INSTR;
6860	}
6861	}
6862	#endif
6863
6864	/*
6865	* Determine the nested paging mode.
6866	*/
6867	PGMMODE enmNestedPagingMode;
6868	#if HC_ARCH_BITS == 32
6869	if (CPUMIsGuestInLongModeEx(pCtx))
6870	enmNestedPagingMode = PGMMODE_AMD64_NX;
6871	else
6872	#endif
6873	enmNestedPagingMode = PGMGetHostMode(pVM);
6874
6875	/*
6876	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6877	*/
6878	int rc;
6879	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6880	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6881	{
6882	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
6883	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
6884	if (pVCpu->hm.s.Event.fPending)
6885	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6886
6887	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6888	u32ErrCode);
6889	rc = VBOXSTRICTRC_VAL(rc2);
6890
6891	/*
6892	* If we succeed, resume guest execution.
6893	* If we fail in interpreting the instruction because we couldn't get the guest physical address
6894	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
6895	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
6896	* weird case. See @bugref{6043}.
6897	*/
6898	if ( rc == VINF_SUCCESS
6899	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6900	\|\| rc == VERR_PAGE_NOT_PRESENT)
6901	{
6902	/* Successfully handled MMIO operation. */
6903	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6904	rc = VINF_SUCCESS;
6905	}
6906	return rc;
6907	}
6908
6909	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6910	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6911	TRPMResetTrap(pVCpu);
6912
6913	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6914
6915	/*
6916	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6917	*/
6918	if ( rc == VINF_SUCCESS
6919	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6920	\|\| rc == VERR_PAGE_NOT_PRESENT)
6921	{
6922	/* We've successfully synced our shadow page tables. */
6923	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6924	rc = VINF_SUCCESS;
6925	}
6926
6927	return rc;
6928	}
6929
6930
6931	/**
6932	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6933	* \#VMEXIT.
6934	*/
6935	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6936	{
6937	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6938	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
6939
6940	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6941	hmR0SvmClearVirtIntrIntercept(pVmcb);
6942
6943	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6944	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6945	return VINF_SUCCESS;
6946	}
6947
6948
6949	/**
6950	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6951	* \#VMEXIT.
6952	*/
6953	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6954	{
6955	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6956
6957	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
6958
6959	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6960	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6961	#endif
6962
6963	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6964	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6965	{
6966	/*
6967	* AMD-V provides us with the exception which caused the TS; we collect
6968	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
6969	*/
6970	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
6971	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6972	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6973	}
6974
6975	/** @todo Emulate task switch someday, currently just going back to ring-3 for
6976	* emulation. */
6977	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6978	return VERR_EM_INTERPRETER;
6979	}
6980
6981
6982	/**
6983	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6984	*/
6985	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6986	{
6987	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6988	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
6989
6990	bool fRipUpdated;
6991	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
6992	if (RT_SUCCESS(rcStrict))
6993	{
6994	/* Only update the RIP if we're continuing guest execution and not
6995	in the case of say VINF_GIM_R3_HYPERCALL. */
6996	if ( rcStrict == VINF_SUCCESS
6997	&& !fRipUpdated)
6998	{
6999	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
7000	}
7001
7002	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
7003	we would need to reload the guest changed bits here before VM-entry. */
7004	return VBOXSTRICTRC_VAL(rcStrict);
7005	}
7006
7007	hmR0SvmSetPendingXcptUD(pVCpu);
7008	return VINF_SUCCESS;
7009	}
7010
7011
7012	/**
7013	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7014	*/
7015	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7016	{
7017	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7018	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
7019	return VINF_EM_RAW_INTERRUPT;
7020	}
7021
7022
7023	/**
7024	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7025	*/
7026	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7027	{
7028	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7029
7030	/* Clear NMI blocking. */
7031	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7032
7033	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7034	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7035	hmR0SvmClearIretIntercept(pVmcb);
7036
7037	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7038	return VINF_SUCCESS;
7039	}
7040
7041
7042	/**
7043	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
7044	* Conditional \#VMEXIT.
7045	*/
7046	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7047	{
7048	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7049	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7050
7051	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7052
7053	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7054	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7055	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7056	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7057	PVM pVM = pVCpu->CTX_SUFF(pVM);
7058
7059	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7060	if (pVM->hm.s.fNestedPaging)
7061	{
7062	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7063	if (!pSvmTransient->fVectoringDoublePF)
7064	{
7065	/* A genuine guest #PF, reflect it to the guest. */
7066	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7067	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7068	uFaultAddress, u32ErrCode));
7069	}
7070	else
7071	{
7072	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7073	hmR0SvmSetPendingXcptDF(pVCpu);
7074	Log4(("Pending #DF due to vectoring #PF. NP\n"));
7075	}
7076	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7077	return VINF_SUCCESS;
7078	}
7079	#endif
7080
7081	Assert(!pVM->hm.s.fNestedPaging);
7082
7083	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7084	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
7085	if ( pVM->hm.s.fTprPatchingAllowed
7086	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7087	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
7088	&& !CPUMIsGuestInLongModeEx(pCtx)
7089	&& !CPUMGetGuestCPL(pVCpu)
7090	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7091	{
7092	RTGCPHYS GCPhysApicBase;
7093	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7094	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7095
7096	/* Check if the page at the fault-address is the APIC base. */
7097	RTGCPHYS GCPhysPage;
7098	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7099	if ( rc2 == VINF_SUCCESS
7100	&& GCPhysPage == GCPhysApicBase)
7101	{
7102	/* Only attempt to patch the instruction once. */
7103	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7104	if (!pPatch)
7105	return VINF_EM_HM_PATCH_TPR_INSTR;
7106	}
7107	}
7108	#endif
7109
7110	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7111	pCtx->rip, u32ErrCode, pCtx->cr3));
7112
7113	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7114	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7115	if (pSvmTransient->fVectoringPF)
7116	{
7117	Assert(pVCpu->hm.s.Event.fPending);
7118	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7119	}
7120
7121	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7122	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7123
7124	Log4(("#PF rc=%Rrc\n", rc));
7125
7126	if (rc == VINF_SUCCESS)
7127	{
7128	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7129	TRPMResetTrap(pVCpu);
7130	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7131	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7132	return rc;
7133	}
7134	else if (rc == VINF_EM_RAW_GUEST_TRAP)
7135	{
7136	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7137
7138	if (!pSvmTransient->fVectoringDoublePF)
7139	{
7140	/* It's a guest page fault and needs to be reflected to the guest. */
7141	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7142	TRPMResetTrap(pVCpu);
7143	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7144	}
7145	else
7146	{
7147	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7148	TRPMResetTrap(pVCpu);
7149	hmR0SvmSetPendingXcptDF(pVCpu);
7150	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7151	}
7152
7153	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7154	return VINF_SUCCESS;
7155	}
7156
7157	TRPMResetTrap(pVCpu);
7158	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7159	return rc;
7160	}
7161
7162
7163	/**
7164	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
7165	* Conditional \#VMEXIT.
7166	*/
7167	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7168	{
7169	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7170
7171	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7172	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7173	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7174
7175	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7176	VMMRZCallRing3Disable(pVCpu);
7177	HM_DISABLE_PREEMPT();
7178
7179	int rc;
7180	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7181	if (pSvmTransient->fWasGuestFPUStateActive)
7182	{
7183	rc = VINF_EM_RAW_GUEST_TRAP;
7184	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7185	}
7186	else
7187	{
7188	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7189	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7190	#endif
7191	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7192	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7193	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7194	}
7195
7196	HM_RESTORE_PREEMPT();
7197	VMMRZCallRing3Enable(pVCpu);
7198
7199	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7200	{
7201	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7202	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7203	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7204	pVCpu->hm.s.fPreloadGuestFpu = true;
7205	}
7206	else
7207	{
7208	/* Forward #NM to the guest. */
7209	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7210	hmR0SvmSetPendingXcptNM(pVCpu);
7211	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7212	}
7213	return VINF_SUCCESS;
7214	}
7215
7216
7217	/**
7218	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7219	* Conditional \#VMEXIT.
7220	*/
7221	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7222	{
7223	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7224
7225	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7226	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7227	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7228
7229	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7230	if (pVCpu->hm.s.fGIMTrapXcptUD)
7231	{
7232	uint8_t cbInstr = 0;
7233	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7234	if (rcStrict == VINF_SUCCESS)
7235	{
7236	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7237	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7238	rc = VINF_SUCCESS;
7239	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7240	}
7241	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7242	rc = VINF_SUCCESS;
7243	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7244	rc = VINF_GIM_R3_HYPERCALL;
7245	else
7246	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7247	}
7248
7249	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7250	if (RT_FAILURE(rc))
7251	{
7252	hmR0SvmSetPendingXcptUD(pVCpu);
7253	rc = VINF_SUCCESS;
7254	}
7255
7256	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7257	return rc;
7258	}
7259
7260
7261	/**
7262	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7263	* Conditional \#VMEXIT.
7264	*/
7265	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7266	{
7267	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7268
7269	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7270	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7271	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7272
7273	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7274
7275	if (!(pCtx->cr0 & X86_CR0_NE))
7276	{
7277	PVM pVM = pVCpu->CTX_SUFF(pVM);
7278	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7279	unsigned cbOp;
7280	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7281	if (RT_SUCCESS(rc))
7282	{
7283	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7284	/** @todo FERR intercept when in nested-guest mode? */
7285	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7286	if (RT_SUCCESS(rc))
7287	pCtx->rip += cbOp;
7288	}
7289	else
7290	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7291	return rc;
7292	}
7293
7294	hmR0SvmSetPendingXcptMF(pVCpu);
7295	return VINF_SUCCESS;
7296	}
7297
7298
7299	/**
7300	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7301	* \#VMEXIT.
7302	*/
7303	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7304	{
7305	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7306
7307	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7308	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7309	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7310	{
7311	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7312	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7313	}
7314
7315	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7316
7317	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7318	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7319	PVM pVM = pVCpu->CTX_SUFF(pVM);
7320	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7321	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7322	if (rc == VINF_EM_RAW_GUEST_TRAP)
7323	{
7324	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7325	if (CPUMIsHyperDebugStateActive(pVCpu))
7326	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7327
7328	/* Reflect the exception back to the guest. */
7329	hmR0SvmSetPendingXcptDB(pVCpu);
7330	rc = VINF_SUCCESS;
7331	}
7332
7333	/*
7334	* Update DR6.
7335	*/
7336	if (CPUMIsHyperDebugStateActive(pVCpu))
7337	{
7338	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7339	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7340	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7341	}
7342	else
7343	{
7344	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7345	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7346	}
7347
7348	return rc;
7349	}
7350
7351
7352	/**
7353	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7354	* Conditional \#VMEXIT.
7355	*/
7356	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7357	{
7358	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7359
7360	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7361	* shutdown VMEXIT. */
7362	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7363
7364	SVMEVENT Event;
7365	Event.u = 0;
7366	Event.n.u1Valid = 1;
7367	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7368	Event.n.u8Vector = X86_XCPT_AC;
7369	Event.n.u1ErrorCodeValid = 1;
7370	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7371	return VINF_SUCCESS;
7372	}
7373
7374
7375	/**
7376	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7377	* Conditional \#VMEXIT.
7378	*/
7379	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7380	{
7381	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7382
7383	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7384
7385	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7386	if (rc == VINF_EM_RAW_GUEST_TRAP)
7387	{
7388	SVMEVENT Event;
7389	Event.u = 0;
7390	Event.n.u1Valid = 1;
7391	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7392	Event.n.u8Vector = X86_XCPT_BP;
7393	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7394	}
7395
7396	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7397	return rc;
7398	}
7399
7400
7401	/**
7402	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7403	*/
7404	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7405	{
7406	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7407
7408	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7409
7410	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7411	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_EXCEPTION_0;
7412	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7413	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7414	Assert(uVector <= X86_XCPT_LAST);
7415	Log4(("hmR0SvmExitXcptGeneric: uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7416
7417
7418	SVMEVENT Event;
7419	Event.u = 0;
7420	Event.n.u1Valid = 1;
7421	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7422	Event.n.u8Vector = uVector;
7423	switch (uVector)
7424	{
7425	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7426	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7427	case X86_XCPT_DF:
7428	case X86_XCPT_TS:
7429	case X86_XCPT_NP:
7430	case X86_XCPT_SS:
7431	case X86_XCPT_GP:
7432	case X86_XCPT_AC:
7433	{
7434	Event.n.u1ErrorCodeValid = 1;
7435	Event.n.u32ErrorCode = uErrCode;
7436	break;
7437	}
7438	}
7439
7440	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7441	return VINF_SUCCESS;
7442	}
7443
7444
7445	#ifdef VBOX_WITH_NESTED_HWVIRT
7446	/**
7447	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7448	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7449	*/
7450	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7451	{
7452	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7453
7454	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7455
7456	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7457	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7458	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7459	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7460
7461	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7462	pCtx->rip, u32ErrCode, pCtx->cr3));
7463
7464	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7465	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7466	if (pSvmTransient->fVectoringPF)
7467	{
7468	Assert(pVCpu->hm.s.Event.fPending);
7469	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7470	}
7471
7472	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7473
7474	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7475	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7476
7477	Log4(("#PFNested: rc=%Rrc\n", rc));
7478
7479	if (rc == VINF_SUCCESS)
7480	{
7481	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7482	TRPMResetTrap(pVCpu);
7483	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7484	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7485	return rc;
7486	}
7487
7488	if (rc == VINF_EM_RAW_GUEST_TRAP)
7489	{
7490	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7491
7492	if (!pSvmTransient->fVectoringDoublePF)
7493	{
7494	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7495	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7496	TRPMResetTrap(pVCpu);
7497	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7498	}
7499	else
7500	{
7501	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7502	TRPMResetTrap(pVCpu);
7503	hmR0SvmSetPendingXcptDF(pVCpu);
7504	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7505	}
7506
7507	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7508	return VINF_SUCCESS;
7509	}
7510
7511	TRPMResetTrap(pVCpu);
7512	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7513	return rc;
7514	}
7515
7516
7517	/**
7518	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7519	*/
7520	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7521	{
7522	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7523
7524	/** @todo Stat. */
7525	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7526	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7527	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7528
7529	/*
7530	* The guest should no longer receive interrupts. Until VGIF is supported,
7531	* clear virtual interrupt intercepts here.
7532	*/
7533	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7534	hmR0SvmClearVirtIntrIntercept(pVmcb);
7535
7536	return VBOXSTRICTRC_VAL(rcStrict);
7537	}
7538
7539
7540	/**
7541	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7542	*/
7543	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7544	{
7545	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7546
7547	/** @todo Stat. */
7548	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7549	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7550	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7551	return VBOXSTRICTRC_VAL(rcStrict);
7552	}
7553
7554
7555	/**
7556	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7557	*/
7558	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7559	{
7560	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7561
7562	/** @todo Stat. */
7563	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7564	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7565	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7566	if (rcStrict == VINF_SUCCESS)
7567	{
7568	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7569	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7570	\| HM_CHANGED_GUEST_TR
7571	\| HM_CHANGED_GUEST_LDTR);
7572	}
7573	return VBOXSTRICTRC_VAL(rcStrict);
7574	}
7575
7576
7577	/**
7578	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7579	*/
7580	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7581	{
7582	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7583
7584	/** @todo Stat. */
7585	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7586	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7587	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7588	return VBOXSTRICTRC_VAL(rcStrict);
7589	}
7590
7591
7592	/**
7593	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7594	*/
7595	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7596	{
7597	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7598	/** @todo Stat. */
7599	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7600	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7601	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7602	return VBOXSTRICTRC_VAL(rcStrict);
7603	}
7604
7605
7606	/**
7607	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7608	*/
7609	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7610	{
7611	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7612	/** @todo Stat. */
7613	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7614	#if 0
7615	VBOXSTRICTRC rcStrict;
7616	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7617	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7618	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7619	if (rcStrict == VINF_SUCCESS)
7620	{
7621	rcStrict = VINF_SVM_VMRUN;
7622	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7623	}
7624	return VBOXSTRICTRC_VAL(rcStrict);
7625	#endif
7626	return VERR_EM_INTERPRETER;
7627	}
7628
7629
7630	/**
7631	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7632	* Unconditional \#VMEXIT.
7633	*/
7634	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7635	{
7636	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7637
7638	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7639	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7640	* shutdown VMEXIT. */
7641	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7642	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7643	{
7644	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7645	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7646	}
7647
7648	hmR0SvmSetPendingXcptDB(pVCpu);
7649	return VINF_SUCCESS;
7650	}
7651
7652
7653	/**
7654	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7655	* Conditional \#VMEXIT.
7656	*/
7657	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7658	{
7659	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7660
7661	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7662	* shutdown VMEXIT. */
7663	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7664
7665	SVMEVENT Event;
7666	Event.u = 0;
7667	Event.n.u1Valid = 1;
7668	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7669	Event.n.u8Vector = X86_XCPT_BP;
7670	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7671	return VINF_SUCCESS;
7672	}
7673
7674	#endif /* VBOX_WITH_NESTED_HWVIRT */
7675
7676
7677	/** @} */
7678

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 70408

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