HMSVMR0.cpp@ 70703

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1	/* $Id: HMSVMR0.cpp 70703 2018-01-23 11:19:47Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#define HMSVM_USE_IEM_EVENT_REFLECTION
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_SYNC_FULL_NESTED_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60	#else
61	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
62	#endif
63
64	/** If we decide to use a function table approach this can be useful to
65	* switch to a "static DECLCALLBACK(int)". */
66	#define HMSVM_EXIT_DECL static int
67
68	/** Macro for checking and returning from the using function for
69	* \#VMEXIT intercepts that maybe caused during delivering of another
70	* event in the guest. */
71	#ifdef VBOX_WITH_NESTED_HWVIRT
72	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
73	do \
74	{ \
75	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
76	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
77	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
78	else if ( rc == VINF_EM_RESET \
79	&& HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
80	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_SHUTDOWN, 0, 0)); \
81	else \
82	return rc; \
83	} while (0)
84	#else
85	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
86	do \
87	{ \
88	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
89	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
90	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
91	else \
92	return rc; \
93	} while (0)
94	#endif
95
96	/**
97	* Updates interrupt shadow for the current RIP.
98	*/
99	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
100	do { \
101	/* Update interrupt shadow. */ \
102	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
103	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
104	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
105	} while (0)
106
107	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
108	* instruction that exited. */
109	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
110	do { \
111	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
112	(a_rc) = VINF_EM_DBG_STEPPED; \
113	} while (0)
114
115	/** Assert that preemption is disabled or covered by thread-context hooks. */
116	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
117	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
118
119	/** Assert that we haven't migrated CPUs when thread-context hooks are not
120	* used. */
121	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
122	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
123	("Illegal migration! Entered on CPU %u Current %u\n", \
124	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
125
126	/** Assert that we're not executing a nested-guest. */
127	#ifdef VBOX_WITH_NESTED_HWVIRT
128	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
129	#else
130	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
131	#endif
132
133	/** Assert that we're executing a nested-guest. */
134	#ifdef VBOX_WITH_NESTED_HWVIRT
135	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
136	#else
137	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
138	#endif
139
140	/** Validate segment descriptor granularity bit. */
141	#ifdef VBOX_STRICT
142	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
143	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
144	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
145	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
146	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
147	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
148	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
149	#else
150	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) do { } while (0)
151	#endif
152
153	/**
154	* Exception bitmap mask for all contributory exceptions.
155	*
156	* Page fault is deliberately excluded here as it's conditional as to whether
157	* it's contributory or benign. Page faults are handled separately.
158	*/
159	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
160	\| RT_BIT(X86_XCPT_DE))
161
162	/**
163	* Mandatory/unconditional guest control intercepts.
164	*
165	* SMIs can and do happen in normal operation. We need not intercept them
166	* while executing the guest or nested-guest.
167	*/
168	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
169	\| SVM_CTRL_INTERCEPT_NMI \
170	\| SVM_CTRL_INTERCEPT_INIT \
171	\| SVM_CTRL_INTERCEPT_RDPMC \
172	\| SVM_CTRL_INTERCEPT_CPUID \
173	\| SVM_CTRL_INTERCEPT_RSM \
174	\| SVM_CTRL_INTERCEPT_HLT \
175	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
176	\| SVM_CTRL_INTERCEPT_MSR_PROT \
177	\| SVM_CTRL_INTERCEPT_INVLPGA \
178	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
179	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
180	\| SVM_CTRL_INTERCEPT_VMRUN \
181	\| SVM_CTRL_INTERCEPT_VMMCALL \
182	\| SVM_CTRL_INTERCEPT_SKINIT \
183	\| SVM_CTRL_INTERCEPT_WBINVD \
184	\| SVM_CTRL_INTERCEPT_MONITOR \
185	\| SVM_CTRL_INTERCEPT_MWAIT \
186	\| SVM_CTRL_INTERCEPT_XSETBV)
187
188	/** @name VMCB Clean Bits.
189	*
190	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
191	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
192	* memory.
193	*
194	* @{ */
195	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
196	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
197	/** I/O permission bitmap, MSR permission bitmap. */
198	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
199	/** ASID. */
200	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
201	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
202	V_INTR_VECTOR. */
203	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
204	/** Nested Paging: Nested CR3 (nCR3), PAT. */
205	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
206	/** Control registers (CR0, CR3, CR4, EFER). */
207	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
208	/** Debug registers (DR6, DR7). */
209	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
210	/** GDT, IDT limit and base. */
211	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
212	/** Segment register: CS, SS, DS, ES limit and base. */
213	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
214	/** CR2.*/
215	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
216	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
217	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
218	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
219	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
220	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
221	/** Mask of all valid VMCB Clean bits. */
222	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
223	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
224	\| HMSVM_VMCB_CLEAN_ASID \
225	\| HMSVM_VMCB_CLEAN_TPR \
226	\| HMSVM_VMCB_CLEAN_NP \
227	\| HMSVM_VMCB_CLEAN_CRX_EFER \
228	\| HMSVM_VMCB_CLEAN_DRX \
229	\| HMSVM_VMCB_CLEAN_DT \
230	\| HMSVM_VMCB_CLEAN_SEG \
231	\| HMSVM_VMCB_CLEAN_CR2 \
232	\| HMSVM_VMCB_CLEAN_LBR \
233	\| HMSVM_VMCB_CLEAN_AVIC)
234	/** @} */
235
236	/** @name SVM transient.
237	*
238	* A state structure for holding miscellaneous information across AMD-V
239	* VMRUN/\#VMEXIT operation, restored after the transition.
240	*
241	* @{ */
242	typedef struct SVMTRANSIENT
243	{
244	/** The host's rflags/eflags. */
245	RTCCUINTREG fEFlags;
246	#if HC_ARCH_BITS == 32
247	uint32_t u32Alignment0;
248	#endif
249
250	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
251	uint64_t u64ExitCode;
252	/** The guest's TPR value used for TPR shadowing. */
253	uint8_t u8GuestTpr;
254	/** Alignment. */
255	uint8_t abAlignment0[7];
256
257	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
258	bool fWasGuestFPUStateActive;
259	/** Whether the guest debug state was active at the time of \#VMEXIT. */
260	bool fWasGuestDebugStateActive;
261	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
262	bool fWasHyperDebugStateActive;
263	/** Whether the TSC offset mode needs to be updated. */
264	bool fUpdateTscOffsetting;
265	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
266	bool fRestoreTscAuxMsr;
267	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
268	* contributary exception or a page-fault. */
269	bool fVectoringDoublePF;
270	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
271	* external interrupt or NMI. */
272	bool fVectoringPF;
273	} SVMTRANSIENT, *PSVMTRANSIENT;
274	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
275	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
276	/** @} */
277
278	/**
279	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
280	*/
281	typedef enum SVMMSREXITREAD
282	{
283	/** Reading this MSR causes a \#VMEXIT. */
284	SVMMSREXIT_INTERCEPT_READ = 0xb,
285	/** Reading this MSR does not cause a \#VMEXIT. */
286	SVMMSREXIT_PASSTHRU_READ
287	} SVMMSREXITREAD;
288
289	/**
290	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
291	*/
292	typedef enum SVMMSREXITWRITE
293	{
294	/** Writing to this MSR causes a \#VMEXIT. */
295	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
296	/** Writing to this MSR does not cause a \#VMEXIT. */
297	SVMMSREXIT_PASSTHRU_WRITE
298	} SVMMSREXITWRITE;
299
300	/**
301	* SVM \#VMEXIT handler.
302	*
303	* @returns VBox status code.
304	* @param pVCpu The cross context virtual CPU structure.
305	* @param pMixedCtx Pointer to the guest-CPU context.
306	* @param pSvmTransient Pointer to the SVM-transient structure.
307	*/
308	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
309
310
311	/*********************************************************************************************************************************
312	* Internal Functions *
313	*********************************************************************************************************************************/
314	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
315	SVMMSREXITWRITE enmWrite);
316	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
317	static void hmR0SvmLeave(PVMCPU pVCpu);
318
319	/** @name \#VMEXIT handlers.
320	* @{
321	*/
322	static FNSVMEXITHANDLER hmR0SvmExitIntr;
323	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
324	static FNSVMEXITHANDLER hmR0SvmExitInvd;
325	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
326	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
327	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
328	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
329	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
330	static FNSVMEXITHANDLER hmR0SvmExitHlt;
331	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
332	static FNSVMEXITHANDLER hmR0SvmExitMwait;
333	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
334	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
335	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
336	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
337	static FNSVMEXITHANDLER hmR0SvmExitMsr;
338	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
339	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
340	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
341	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
342	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
343	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
344	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
345	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
346	static FNSVMEXITHANDLER hmR0SvmExitPause;
347	static FNSVMEXITHANDLER hmR0SvmExitIret;
348	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
349	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
350	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
351	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
352	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
353	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
354	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
355	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
356	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
357	#endif
358	#ifdef VBOX_WITH_NESTED_HWVIRT
359	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
360	static FNSVMEXITHANDLER hmR0SvmExitClgi;
361	static FNSVMEXITHANDLER hmR0SvmExitStgi;
362	static FNSVMEXITHANDLER hmR0SvmExitVmload;
363	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
364	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
365	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
366	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
367	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
368	#endif
369	/** @} */
370
371	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
372	#ifdef VBOX_WITH_NESTED_HWVIRT
373	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
374	#endif
375
376
377	/*********************************************************************************************************************************
378	* Global Variables *
379	*********************************************************************************************************************************/
380	/** Ring-0 memory object for the IO bitmap. */
381	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
382	/** Physical address of the IO bitmap. */
383	RTHCPHYS g_HCPhysIOBitmap = 0;
384	/** Pointer to the IO bitmap. */
385	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
386
387	#ifdef VBOX_WITH_NESTED_HWVIRT
388	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
389	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
390	/** Physical address of the nested-guest MSRPM bitmap. */
391	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
392	/** Pointer to the nested-guest MSRPM bitmap. */
393	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
394	#endif
395
396
397	#ifdef VBOX_STRICT
398	# define HMSVM_LOG_CS RT_BIT_32(0)
399	# define HMSVM_LOG_SS RT_BIT_32(1)
400	# define HMSVM_LOG_FS RT_BIT_32(2)
401	# define HMSVM_LOG_GS RT_BIT_32(3)
402	# define HMSVM_LOG_LBR RT_BIT_32(4)
403	# define HMSVM_LOG_ALL ( HMSVM_LOG_CS \
404	\| HMSVM_LOG_SS \
405	\| HMSVM_LOG_FS \
406	\| HMSVM_LOG_GS \
407	\| HMSVM_LOG_LBR)
408
409	/**
410	* Dumps CPU state and additional info. to the logger for diagnostics.
411	*
412	* @param pVCpu The cross context virtual CPU structure.
413	* @param pVmcb Pointer to the VM control block.
414	* @param pCtx Pointer to the guest-CPU context.
415	* @param pszPrefix Log prefix.
416	* @param fFlags Log flags, see HMSVM_LOG_XXX.
417	* @param uVerbose The verbosity level, currently unused.
418	*/
419	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, PCPUMCTX pCtx, const char *pszPrefix, uint32_t fFlags,
420	uint8_t uVerbose)
421	{
422	RT_NOREF(uVerbose);
423
424	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX32 cr0=%#RX32 cr3=%#RX32 cr4=%#RX32\n", pszPrefix, pCtx->cs.Sel, pCtx->rip,
425	pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
426	Log4(("%s: rsp=%#RX64 rbp=%#RX64 rdi=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp, pCtx->rdi));
427	if (fFlags & HMSVM_LOG_CS)
428	{
429	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
430	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
431	}
432	if (fFlags & HMSVM_LOG_SS)
433	{
434	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
435	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
436	}
437	if (fFlags & HMSVM_LOG_FS)
438	{
439	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
440	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
441	}
442	if (fFlags & HMSVM_LOG_GS)
443	{
444	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
445	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
446	}
447
448	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
449	if (fFlags & HMSVM_LOG_LBR)
450	{
451	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
452	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
453	}
454	NOREF(pVmcbGuest);
455	}
456	#endif
457
458
459	/**
460	* Sets up and activates AMD-V on the current CPU.
461	*
462	* @returns VBox status code.
463	* @param pCpu Pointer to the CPU info struct.
464	* @param pVM The cross context VM structure. Can be
465	* NULL after a resume!
466	* @param pvCpuPage Pointer to the global CPU page.
467	* @param HCPhysCpuPage Physical address of the global CPU page.
468	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
469	* @param pvArg Unused on AMD-V.
470	*/
471	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
472	void *pvArg)
473	{
474	Assert(!fEnabledByHost);
475	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
476	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
477	Assert(pvCpuPage); NOREF(pvCpuPage);
478	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
479
480	NOREF(pvArg);
481	NOREF(fEnabledByHost);
482
483	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
484	RTCCUINTREG fEFlags = ASMIntDisableFlags();
485
486	/*
487	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
488	*/
489	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
490	if (u64HostEfer & MSR_K6_EFER_SVME)
491	{
492	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
493	if ( pVM
494	&& pVM->hm.s.svm.fIgnoreInUseError)
495	{
496	pCpu->fIgnoreAMDVInUseError = true;
497	}
498
499	if (!pCpu->fIgnoreAMDVInUseError)
500	{
501	ASMSetFlags(fEFlags);
502	return VERR_SVM_IN_USE;
503	}
504	}
505
506	/* Turn on AMD-V in the EFER MSR. */
507	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
508
509	/* Write the physical page address where the CPU will store the host state while executing the VM. */
510	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
511
512	/* Restore interrupts. */
513	ASMSetFlags(fEFlags);
514
515	/*
516	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
517	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
518	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
519	* guest code.
520	*/
521	pCpu->fFlushAsidBeforeUse = true;
522
523	/*
524	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
525	*/
526	++pCpu->cTlbFlushes;
527
528	return VINF_SUCCESS;
529	}
530
531
532	/**
533	* Deactivates AMD-V on the current CPU.
534	*
535	* @returns VBox status code.
536	* @param pCpu Pointer to the CPU info struct.
537	* @param pvCpuPage Pointer to the global CPU page.
538	* @param HCPhysCpuPage Physical address of the global CPU page.
539	*/
540	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
541	{
542	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
543	AssertReturn( HCPhysCpuPage
544	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
545	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
546	NOREF(pCpu);
547
548	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
549	RTCCUINTREG fEFlags = ASMIntDisableFlags();
550
551	/* Turn off AMD-V in the EFER MSR. */
552	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
553	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
554
555	/* Invalidate host state physical address. */
556	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
557
558	/* Restore interrupts. */
559	ASMSetFlags(fEFlags);
560
561	return VINF_SUCCESS;
562	}
563
564
565	/**
566	* Does global AMD-V initialization (called during module initialization).
567	*
568	* @returns VBox status code.
569	*/
570	VMMR0DECL(int) SVMR0GlobalInit(void)
571	{
572	/*
573	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
574	* once globally here instead of per-VM.
575	*/
576	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
577	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
578	if (RT_FAILURE(rc))
579	return rc;
580
581	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
582	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
583
584	/* Set all bits to intercept all IO accesses. */
585	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
586
587	#ifdef VBOX_WITH_NESTED_HWVIRT
588	/*
589	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
590	*/
591	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
592	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
593	if (RT_FAILURE(rc))
594	return rc;
595
596	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
597	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
598
599	/* Set all bits to intercept all MSR accesses. */
600	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
601	#endif
602
603	return VINF_SUCCESS;
604	}
605
606
607	/**
608	* Does global AMD-V termination (called during module termination).
609	*/
610	VMMR0DECL(void) SVMR0GlobalTerm(void)
611	{
612	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
613	{
614	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
615	g_pvIOBitmap = NULL;
616	g_HCPhysIOBitmap = 0;
617	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
618	}
619
620	#ifdef VBOX_WITH_NESTED_HWVIRT
621	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
622	{
623	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
624	g_pvNstGstMsrBitmap = NULL;
625	g_HCPhysNstGstMsrBitmap = 0;
626	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
627	}
628	#endif
629	}
630
631
632	/**
633	* Frees any allocated per-VCPU structures for a VM.
634	*
635	* @param pVM The cross context VM structure.
636	*/
637	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
638	{
639	for (uint32_t i = 0; i < pVM->cCpus; i++)
640	{
641	PVMCPU pVCpu = &pVM->aCpus[i];
642	AssertPtr(pVCpu);
643
644	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
645	{
646	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
647	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
648	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
649	}
650
651	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
652	{
653	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
654	pVCpu->hm.s.svm.pVmcb = NULL;
655	pVCpu->hm.s.svm.HCPhysVmcb = 0;
656	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
657	}
658
659	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
660	{
661	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
662	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
663	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
664	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
665	}
666	}
667	}
668
669
670	/**
671	* Does per-VM AMD-V initialization.
672	*
673	* @returns VBox status code.
674	* @param pVM The cross context VM structure.
675	*/
676	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
677	{
678	int rc = VERR_INTERNAL_ERROR_5;
679
680	/*
681	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
682	*/
683	uint32_t u32Family;
684	uint32_t u32Model;
685	uint32_t u32Stepping;
686	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
687	{
688	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
689	pVM->hm.s.svm.fAlwaysFlushTLB = true;
690	}
691
692	/*
693	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
694	*/
695	for (VMCPUID i = 0; i < pVM->cCpus; i++)
696	{
697	PVMCPU pVCpu = &pVM->aCpus[i];
698	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
699	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
700	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
701	}
702
703	for (VMCPUID i = 0; i < pVM->cCpus; i++)
704	{
705	PVMCPU pVCpu = &pVM->aCpus[i];
706
707	/*
708	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
709	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
710	*/
711	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
712	if (RT_FAILURE(rc))
713	goto failure_cleanup;
714
715	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
716	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
717	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
718	ASMMemZeroPage(pvVmcbHost);
719
720	/*
721	* Allocate one page for the guest-state VMCB.
722	*/
723	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
724	if (RT_FAILURE(rc))
725	goto failure_cleanup;
726
727	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
728	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
729	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
730	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
731
732	/*
733	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
734	* SVM to not require one.
735	*/
736	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
737	false /* fExecutable */);
738	if (RT_FAILURE(rc))
739	goto failure_cleanup;
740
741	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
742	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
743	/* Set all bits to intercept all MSR accesses (changed later on). */
744	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
745	}
746
747	return VINF_SUCCESS;
748
749	failure_cleanup:
750	hmR0SvmFreeStructs(pVM);
751	return rc;
752	}
753
754
755	/**
756	* Does per-VM AMD-V termination.
757	*
758	* @returns VBox status code.
759	* @param pVM The cross context VM structure.
760	*/
761	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
762	{
763	hmR0SvmFreeStructs(pVM);
764	return VINF_SUCCESS;
765	}
766
767
768	/**
769	* Returns whether the VMCB Clean Bits feature is supported.
770	*
771	* @return @c true if supported, @c false otherwise.
772	* @param pVCpu The cross context virtual CPU structure.
773	* @param pCtx Pointer to the guest-CPU context.
774	*/
775	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu, PCPUMCTX pCtx)
776	{
777	PVM pVM = pVCpu->CTX_SUFF(pVM);
778	#ifdef VBOX_WITH_NESTED_HWVIRT
779	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
780	{
781	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
782	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
783	}
784	#else
785	RT_NOREF(pCtx);
786	#endif
787	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
788	}
789
790
791	/**
792	* Returns whether the decode assists feature is supported.
793	*
794	* @return @c true if supported, @c false otherwise.
795	* @param pVCpu The cross context virtual CPU structure.
796	* @param pCtx Pointer to the guest-CPU context.
797	*/
798	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu, PCPUMCTX pCtx)
799	{
800	PVM pVM = pVCpu->CTX_SUFF(pVM);
801	#ifdef VBOX_WITH_NESTED_HWVIRT
802	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
803	{
804	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
805	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
806	}
807	#else
808	RT_NOREF(pCtx);
809	#endif
810	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
811	}
812
813
814	/**
815	* Returns whether the NRIP_SAVE feature is supported.
816	*
817	* @return @c true if supported, @c false otherwise.
818	* @param pVCpu The cross context virtual CPU structure.
819	* @param pCtx Pointer to the guest-CPU context.
820	*/
821	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu, PCPUMCTX pCtx)
822	{
823	PVM pVM = pVCpu->CTX_SUFF(pVM);
824	#ifdef VBOX_WITH_NESTED_HWVIRT
825	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
826	{
827	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
828	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
829	}
830	#else
831	RT_NOREF(pCtx);
832	#endif
833	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
834	}
835
836
837	/**
838	* Sets the permission bits for the specified MSR in the MSRPM.
839	*
840	* @param pVmcb Pointer to the VM control block.
841	* @param pbMsrBitmap Pointer to the MSR bitmap.
842	* @param uMsr The MSR for which the access permissions are being set.
843	* @param enmRead MSR read permissions.
844	* @param enmWrite MSR write permissions.
845	*/
846	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
847	SVMMSREXITWRITE enmWrite)
848	{
849	uint16_t offMsrpm;
850	uint32_t uMsrpmBit;
851	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
852	AssertRC(rc);
853
854	Assert(uMsrpmBit < 0x3fff);
855	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
856
857	pbMsrBitmap += offMsrpm;
858	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
859	ASMBitSet(pbMsrBitmap, uMsrpmBit);
860	else
861	ASMBitClear(pbMsrBitmap, uMsrpmBit);
862
863	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
864	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
865	else
866	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
867
868	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
869	}
870
871
872	/**
873	* Sets up AMD-V for the specified VM.
874	* This function is only called once per-VM during initalization.
875	*
876	* @returns VBox status code.
877	* @param pVM The cross context VM structure.
878	*/
879	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
880	{
881	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
882	AssertReturn(pVM, VERR_INVALID_PARAMETER);
883	Assert(pVM->hm.s.svm.fSupported);
884
885	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
886	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
887	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
888
889	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
890	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
891
892	#ifdef VBOX_WITH_NESTED_HWVIRT
893	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
894	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
895
896	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
897	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
898	#endif
899
900	for (VMCPUID i = 0; i < pVM->cCpus; i++)
901	{
902	PVMCPU pVCpu = &pVM->aCpus[i];
903	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
904
905	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
906
907	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
908	Assert(!pVCpu->hm.s.idxExitHistoryFree);
909	HMCPU_EXIT_HISTORY_RESET(pVCpu);
910
911	/* Always trap #AC for reasons of security. */
912	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
913
914	/* Always trap #DB for reasons of security. */
915	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
916
917	/* Trap exceptions unconditionally (debug purposes). */
918	#ifdef HMSVM_ALWAYS_TRAP_PF
919	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
920	#endif
921	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
922	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
923	pVmcb->ctrl.u32InterceptXcpt \|= 0
924	\| RT_BIT(X86_XCPT_BP)
925	\| RT_BIT(X86_XCPT_DE)
926	\| RT_BIT(X86_XCPT_NM)
927	\| RT_BIT(X86_XCPT_UD)
928	\| RT_BIT(X86_XCPT_NP)
929	\| RT_BIT(X86_XCPT_SS)
930	\| RT_BIT(X86_XCPT_GP)
931	\| RT_BIT(X86_XCPT_PF)
932	\| RT_BIT(X86_XCPT_MF)
933	;
934	#endif
935
936	/* Set up unconditional intercepts and conditions. */
937	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
938
939	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
940	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
941
942	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
943	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
944
945	/* Intercept all DRx reads and writes by default. Changed later on. */
946	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
947	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
948
949	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
950	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
951
952	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
953	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
954	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
955
956	/* Set IO and MSR bitmap permission bitmap physical addresses. */
957	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
958	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
959
960	/* LBR virtualization. */
961	if (fUseLbrVirt)
962	{
963	pVmcb->ctrl.LbrVirt.n.u1LbrVirt = fUseLbrVirt;
964	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
965	}
966	else
967	Assert(pVmcb->ctrl.LbrVirt.n.u1LbrVirt == 0);
968
969	#ifdef VBOX_WITH_NESTED_HWVIRT
970	/* Virtualized VMSAVE/VMLOAD. */
971	pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
972	if (!fUseVirtVmsaveVmload)
973	{
974	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
975	\| SVM_CTRL_INTERCEPT_VMLOAD;
976	}
977
978	/* Virtual GIF. */
979	pVmcb->ctrl.IntCtrl.n.u1VGifEnable = fUseVGif;
980	if (!fUseVGif)
981	{
982	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
983	\| SVM_CTRL_INTERCEPT_STGI;
984	}
985	#endif
986
987	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
988	Assert(pVmcb->ctrl.u32VmcbCleanBits == 0);
989
990	/* The host ASID MBZ, for the guest start with 1. */
991	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
992
993	/*
994	* Setup the PAT MSR (applicable for Nested Paging only).
995	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
996	* so choose type 6 for all PAT slots.
997	*/
998	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
999
1000	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1001	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1002
1003	/* Without Nested Paging, we need additionally intercepts. */
1004	if (!pVM->hm.s.fNestedPaging)
1005	{
1006	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1007	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1008	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1009
1010	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1011	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1012	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1013
1014	/* Page faults must be intercepted to implement shadow paging. */
1015	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1016	}
1017
1018	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1019	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1020	#endif
1021
1022	/* Apply the exceptions intercepts needed by the GIM provider. */
1023	if (pVCpu->hm.s.fGIMTrapXcptUD)
1024	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1025
1026	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1027	if (fUsePauseFilter)
1028	{
1029	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1030	if (fPauseFilterThreshold)
1031	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1032	}
1033
1034	/*
1035	* The following MSRs are saved/restored automatically during the world-switch.
1036	* Don't intercept guest read/write accesses to these MSRs.
1037	*/
1038	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1039	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1040	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1041	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1042	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1043	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1044	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1045	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1046	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1047	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1048	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1049	}
1050
1051	return VINF_SUCCESS;
1052	}
1053
1054
1055	/**
1056	* Gets a pointer to the currently active guest or nested-guest VMCB.
1057	*
1058	* @returns Pointer to the current context VMCB.
1059	* @param pVCpu The cross context virtual CPU structure.
1060	* @param pCtx Pointer to the guest-CPU context.
1061	*/
1062	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
1063	{
1064	#ifdef VBOX_WITH_NESTED_HWVIRT
1065	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1066	return pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1067	#else
1068	RT_NOREF(pCtx);
1069	#endif
1070	return pVCpu->hm.s.svm.pVmcb;
1071	}
1072
1073
1074	/**
1075	* Invalidates a guest page by guest virtual address.
1076	*
1077	* @returns VBox status code.
1078	* @param pVM The cross context VM structure.
1079	* @param pVCpu The cross context virtual CPU structure.
1080	* @param GCVirt Guest virtual address of the page to invalidate.
1081	*/
1082	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1083	{
1084	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1085	Assert(pVM->hm.s.svm.fSupported);
1086
1087	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1088
1089	/* Skip it if a TLB flush is already pending. */
1090	if (!fFlushPending)
1091	{
1092	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
1093
1094	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1095	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
1096	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1097
1098	#if HC_ARCH_BITS == 32
1099	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1100	if (CPUMIsGuestInLongMode(pVCpu))
1101	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1102	else
1103	#endif
1104	{
1105	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1106	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1107	}
1108	}
1109	return VINF_SUCCESS;
1110	}
1111
1112
1113	/**
1114	* Flushes the appropriate tagged-TLB entries.
1115	*
1116	* @param pVCpu The cross context virtual CPU structure.
1117	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
1118	* @param pVmcb Pointer to the VM control block.
1119	*/
1120	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
1121	{
1122	#ifndef VBOX_WITH_NESTED_HWVIRT
1123	RT_NOREF(pCtx);
1124	#endif
1125
1126	PVM pVM = pVCpu->CTX_SUFF(pVM);
1127	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
1128
1129	/*
1130	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1131	* This can happen both for start & resume due to long jumps back to ring-3.
1132	*
1133	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no correlation
1134	* between it and the physical CPU.
1135	*
1136	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1137	* so we cannot reuse the ASIDs without flushing.
1138	*/
1139	bool fNewAsid = false;
1140	Assert(pCpu->idCpu != NIL_RTCPUID);
1141	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1142	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes
1143	#ifdef VBOX_WITH_NESTED_HWVIRT
1144	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1145	#endif
1146	)
1147	{
1148	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1149	pVCpu->hm.s.fForceTLBFlush = true;
1150	fNewAsid = true;
1151	}
1152
1153	/* Set TLB flush state as checked until we return from the world switch. */
1154	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1155
1156	/* Check for explicit TLB flushes. */
1157	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1158	{
1159	pVCpu->hm.s.fForceTLBFlush = true;
1160	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1161	}
1162
1163	/*
1164	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1165	* This Host CPU requirement takes precedence.
1166	*/
1167	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1168	{
1169	pCpu->uCurrentAsid = 1;
1170	pVCpu->hm.s.uCurrentAsid = 1;
1171	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1172	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1173
1174	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1175	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1176
1177	/* Keep track of last CPU ID even when flushing all the time. */
1178	if (fNewAsid)
1179	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1180	}
1181	else
1182	{
1183	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1184	if (pVCpu->hm.s.fForceTLBFlush)
1185	{
1186	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1187	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1188
1189	if (fNewAsid)
1190	{
1191	++pCpu->uCurrentAsid;
1192
1193	bool fHitASIDLimit = false;
1194	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1195	{
1196	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1197	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1198	fHitASIDLimit = true;
1199	}
1200
1201	if ( fHitASIDLimit
1202	\|\| pCpu->fFlushAsidBeforeUse)
1203	{
1204	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1205	pCpu->fFlushAsidBeforeUse = false;
1206	}
1207
1208	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1209	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1210	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1211	}
1212	else
1213	{
1214	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1215	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1216	else
1217	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1218	}
1219
1220	pVCpu->hm.s.fForceTLBFlush = false;
1221	}
1222	}
1223
1224	/* Update VMCB with the ASID. */
1225	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1226	{
1227	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1228	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1229	}
1230
1231	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
1232	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1233	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1234	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1235	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1236	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1237	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1238	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1239
1240	#ifdef VBOX_WITH_STATISTICS
1241	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1242	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1243	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1244	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1245	{
1246	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1247	}
1248	else
1249	{
1250	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1251	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1252	}
1253	#endif
1254	}
1255
1256
1257	/** @name 64-bit guest on 32-bit host OS helper functions.
1258	*
1259	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1260	* mode (code segment, paging). These wrappers/helpers perform the necessary
1261	* bits for the 32->64 switcher.
1262	*
1263	* @{ */
1264	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1265	/**
1266	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1267	*
1268	* @returns VBox status code.
1269	* @param HCPhysVmcbHost Physical address of host VMCB.
1270	* @param HCPhysVmcb Physical address of the VMCB.
1271	* @param pCtx Pointer to the guest-CPU context.
1272	* @param pVM The cross context VM structure.
1273	* @param pVCpu The cross context virtual CPU structure.
1274	*/
1275	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1276	{
1277	uint32_t aParam[8];
1278	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1279	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1280	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1281	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1282	aParam[4] = VM_RC_ADDR(pVM, pVM);
1283	aParam[5] = 0;
1284	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1285	aParam[7] = 0;
1286
1287	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1288	}
1289
1290
1291	/**
1292	* Executes the specified VMRUN handler in 64-bit mode.
1293	*
1294	* @returns VBox status code.
1295	* @param pVM The cross context VM structure.
1296	* @param pVCpu The cross context virtual CPU structure.
1297	* @param pCtx Pointer to the guest-CPU context.
1298	* @param enmOp The operation to perform.
1299	* @param cParams Number of parameters.
1300	* @param paParam Array of 32-bit parameters.
1301	*/
1302	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1303	uint32_t cParams, uint32_t *paParam)
1304	{
1305	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1306	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1307
1308	NOREF(pCtx);
1309
1310	/* Disable interrupts. */
1311	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1312
1313	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1314	RTCPUID idHostCpu = RTMpCpuId();
1315	CPUMR0SetLApic(pVCpu, idHostCpu);
1316	#endif
1317
1318	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1319	CPUMSetHyperEIP(pVCpu, enmOp);
1320	for (int i = (int)cParams - 1; i >= 0; i--)
1321	CPUMPushHyper(pVCpu, paParam[i]);
1322
1323	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1324	/* Call the switcher. */
1325	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1326	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1327
1328	/* Restore interrupts. */
1329	ASMSetFlags(uOldEFlags);
1330	return rc;
1331	}
1332
1333	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1334	/** @} */
1335
1336
1337	/**
1338	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1339	* the corresponding VMCB Clean bit.
1340	*
1341	* @param pVmcb Pointer to the VM control block.
1342	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1343	*/
1344	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1345	{
1346	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1347	{
1348	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1349	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1350	}
1351	}
1352
1353
1354	/**
1355	* Removes an exception from the intercept-exception bitmap in the VMCB and
1356	* updates the corresponding VMCB Clean bit.
1357	*
1358	* @param pVCpu The cross context virtual CPU structure.
1359	* @param pCtx Pointer to the guest-CPU context.
1360	* @param pVmcb Pointer to the VM control block.
1361	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1362	*
1363	* @remarks This takes into account if we're executing a nested-guest and only
1364	* removes the exception intercept if both the guest -and- nested-guest
1365	* are not intercepting it.
1366	*/
1367	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint32_t u32Xcpt)
1368	{
1369	Assert(u32Xcpt != X86_XCPT_DB);
1370	Assert(u32Xcpt != X86_XCPT_AC);
1371	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1372	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1373	{
1374	bool fRemoveXcpt = true;
1375	#ifdef VBOX_WITH_NESTED_HWVIRT
1376	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1377	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1378	{
1379	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
1380	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
1381	fRemoveXcpt = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(u32Xcpt));
1382	}
1383	#else
1384	RT_NOREF2(pVCpu, pCtx);
1385	#endif
1386	if (fRemoveXcpt)
1387	{
1388	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1389	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1390	}
1391	}
1392	#else
1393	RT_NOREF3(pVCpu, pCtx, pVmcb);
1394	#endif
1395	}
1396
1397
1398	/**
1399	* Loads the guest (or nested-guest) CR0 control register into the guest-state
1400	* area in the VMCB.
1401	*
1402	* Although the guest CR0 is a separate field in the VMCB we have to consider
1403	* the FPU state itself which is shared between the host and the guest.
1404	*
1405	* @returns VBox status code.
1406	* @param pVCpu The cross context virtual CPU structure.
1407	* @param pVmcb Pointer to the VM control block.
1408	* @param pCtx Pointer to the guest-CPU context.
1409	*
1410	* @remarks No-long-jump zone!!!
1411	*/
1412	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1413	{
1414	uint64_t u64GuestCR0 = pCtx->cr0;
1415
1416	/* Always enable caching. */
1417	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1418
1419	/*
1420	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1421	*/
1422	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1423	{
1424	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1425	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1426	}
1427
1428	/*
1429	* Guest FPU bits.
1430	*/
1431	bool fInterceptNM = false;
1432	bool fInterceptMF = false;
1433	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1434	if (CPUMIsGuestFPUStateActive(pVCpu))
1435	{
1436	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1437	if (!(pCtx->cr0 & X86_CR0_NE))
1438	{
1439	Log4(("hmR0SvmLoadSharedCR0: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1440	fInterceptMF = true;
1441	}
1442	}
1443	else
1444	{
1445	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1446	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1447	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1448	}
1449
1450	/*
1451	* Update the exception intercept bitmap.
1452	*/
1453	if (fInterceptNM)
1454	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1455	else
1456	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_NM);
1457
1458	if (fInterceptMF)
1459	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1460	else
1461	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_MF);
1462
1463	pVmcb->guest.u64CR0 = u64GuestCR0;
1464	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1465	}
1466
1467
1468	/**
1469	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1470	*
1471	* @returns VBox status code.
1472	* @param pVCpu The cross context virtual CPU structure.
1473	* @param pVmcb Pointer to the VM control block.
1474	* @param pCtx Pointer to the guest-CPU context.
1475	*
1476	* @remarks No-long-jump zone!!!
1477	*/
1478	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1479	{
1480	PVM pVM = pVCpu->CTX_SUFF(pVM);
1481
1482	/*
1483	* Guest CR2.
1484	*/
1485	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1486	{
1487	pVmcb->guest.u64CR2 = pCtx->cr2;
1488	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1489	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1490	}
1491
1492	/*
1493	* Guest CR3.
1494	*/
1495	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1496	{
1497	if (pVM->hm.s.fNestedPaging)
1498	{
1499	PGMMODE enmShwPagingMode;
1500	#if HC_ARCH_BITS == 32
1501	if (CPUMIsGuestInLongModeEx(pCtx))
1502	enmShwPagingMode = PGMMODE_AMD64_NX;
1503	else
1504	#endif
1505	enmShwPagingMode = PGMGetHostMode(pVM);
1506
1507	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1508	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1509	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1510	pVmcb->guest.u64CR3 = pCtx->cr3;
1511	}
1512	else
1513	{
1514	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1515	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1516	}
1517
1518	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1519	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1520	}
1521
1522	/*
1523	* Guest CR4.
1524	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1525	*/
1526	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1527	{
1528	uint64_t u64GuestCR4 = pCtx->cr4;
1529	Assert(RT_HI_U32(u64GuestCR4) == 0);
1530	if (!pVM->hm.s.fNestedPaging)
1531	{
1532	switch (pVCpu->hm.s.enmShadowMode)
1533	{
1534	case PGMMODE_REAL:
1535	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1536	AssertFailed();
1537	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1538
1539	case PGMMODE_32_BIT: /* 32-bit paging. */
1540	u64GuestCR4 &= ~X86_CR4_PAE;
1541	break;
1542
1543	case PGMMODE_PAE: /* PAE paging. */
1544	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1545	/** Must use PAE paging as we could use physical memory > 4 GB */
1546	u64GuestCR4 \|= X86_CR4_PAE;
1547	break;
1548
1549	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1550	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1551	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1552	break;
1553	#else
1554	AssertFailed();
1555	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1556	#endif
1557
1558	default: /* shut up gcc */
1559	AssertFailed();
1560	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1561	}
1562	}
1563
1564	pVmcb->guest.u64CR4 = u64GuestCR4;
1565	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1566
1567	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1568	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1569
1570	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1571	}
1572
1573	return VINF_SUCCESS;
1574	}
1575
1576
1577	/**
1578	* Loads the guest (or nested-guest) segment registers into the VMCB.
1579	*
1580	* @returns VBox status code.
1581	* @param pVCpu The cross context virtual CPU structure.
1582	* @param pVmcb Pointer to the VM control block.
1583	* @param pCtx Pointer to the guest-CPU context.
1584	*
1585	* @remarks No-long-jump zone!!!
1586	*/
1587	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1588	{
1589	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1590	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1591	{
1592	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1593	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1594	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1595	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1596	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1597	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1598
1599	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1600	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1601	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1602	}
1603
1604	/* Guest TR. */
1605	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1606	{
1607	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1608	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1609	}
1610
1611	/* Guest LDTR. */
1612	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1613	{
1614	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1615	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1616	}
1617
1618	/* Guest GDTR. */
1619	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1620	{
1621	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1622	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1623	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1624	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1625	}
1626
1627	/* Guest IDTR. */
1628	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1629	{
1630	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1631	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1632	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1633	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1634	}
1635	}
1636
1637
1638	/**
1639	* Loads the guest (or nested-guest) MSRs into the VMCB.
1640	*
1641	* @param pVCpu The cross context virtual CPU structure.
1642	* @param pVmcb Pointer to the VM control block.
1643	* @param pCtx Pointer to the guest-CPU context.
1644	*
1645	* @remarks No-long-jump zone!!!
1646	*/
1647	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1648	{
1649	/* Guest Sysenter MSRs. */
1650	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1651	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1652	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1653
1654	/*
1655	* Guest EFER MSR.
1656	* AMD-V requires guest EFER.SVME to be set. Weird.
1657	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1658	*/
1659	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1660	{
1661	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1662	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1663	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1664	}
1665
1666	/* 64-bit MSRs. */
1667	if (CPUMIsGuestInLongModeEx(pCtx))
1668	{
1669	/* Load these always as the guest may modify FS/GS base using MSRs in 64-bit mode which we don't intercept. */
1670	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1671	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1672	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1673	}
1674	else
1675	{
1676	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1677	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1678	{
1679	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1680	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1681	}
1682	}
1683
1684	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1685	* be writable in 32-bit mode. Clarify with AMD spec. */
1686	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1687	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1688	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1689	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1690	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1691	}
1692
1693
1694	/**
1695	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1696	* necessary intercepts accordingly.
1697	*
1698	* @param pVCpu The cross context virtual CPU structure.
1699	* @param pVmcb Pointer to the VM control block.
1700	* @param pCtx Pointer to the guest-CPU context.
1701	*
1702	* @remarks No-long-jump zone!!!
1703	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1704	*/
1705	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1706	{
1707	bool fInterceptMovDRx = false;
1708
1709	/*
1710	* Anyone single stepping on the host side? If so, we'll have to use the
1711	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1712	* the VMM level like the VT-x implementations does.
1713	*/
1714	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1715	if (fStepping)
1716	{
1717	pVCpu->hm.s.fClearTrapFlag = true;
1718	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1719	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1720	}
1721
1722	if ( fStepping
1723	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1724	{
1725	/*
1726	* Use the combined guest and host DRx values found in the hypervisor
1727	* register set because the debugger has breakpoints active or someone
1728	* is single stepping on the host side.
1729	*
1730	* Note! DBGF expects a clean DR6 state before executing guest code.
1731	*/
1732	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1733	if ( CPUMIsGuestInLongModeEx(pCtx)
1734	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1735	{
1736	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1737	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1738	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1739	}
1740	else
1741	#endif
1742	if (!CPUMIsHyperDebugStateActive(pVCpu))
1743	{
1744	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1745	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1746	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1747	}
1748
1749	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1750	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1751	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1752	{
1753	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1754	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1755	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1756	pVCpu->hm.s.fUsingHyperDR7 = true;
1757	}
1758
1759	/** @todo If we cared, we could optimize to allow the guest to read registers
1760	* with the same values. */
1761	fInterceptMovDRx = true;
1762	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1763	}
1764	else
1765	{
1766	/*
1767	* Update DR6, DR7 with the guest values if necessary.
1768	*/
1769	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1770	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1771	{
1772	pVmcb->guest.u64DR7 = pCtx->dr[7];
1773	pVmcb->guest.u64DR6 = pCtx->dr[6];
1774	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1775	pVCpu->hm.s.fUsingHyperDR7 = false;
1776	}
1777
1778	/*
1779	* If the guest has enabled debug registers, we need to load them prior to
1780	* executing guest code so they'll trigger at the right time.
1781	*/
1782	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1783	{
1784	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1785	if ( CPUMIsGuestInLongModeEx(pCtx)
1786	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1787	{
1788	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1789	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1790	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1791	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1792	}
1793	else
1794	#endif
1795	if (!CPUMIsGuestDebugStateActive(pVCpu))
1796	{
1797	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1798	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1799	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1800	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1801	}
1802	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1803	}
1804	/*
1805	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1806	* intercept #DB as DR6 is updated in the VMCB.
1807	*
1808	* Note! If we cared and dared, we could skip intercepting \#DB here.
1809	* However, \#DB shouldn't be performance critical, so we'll play safe
1810	* and keep the code similar to the VT-x code and always intercept it.
1811	*/
1812	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1813	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1814	&& !CPUMIsGuestDebugStateActive(pVCpu))
1815	#else
1816	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1817	#endif
1818	{
1819	fInterceptMovDRx = true;
1820	}
1821	}
1822
1823	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1824	if (fInterceptMovDRx)
1825	{
1826	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1827	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1828	{
1829	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1830	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1831	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1832	}
1833	}
1834	else
1835	{
1836	if ( pVmcb->ctrl.u16InterceptRdDRx
1837	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1838	{
1839	pVmcb->ctrl.u16InterceptRdDRx = 0;
1840	pVmcb->ctrl.u16InterceptWrDRx = 0;
1841	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1842	}
1843	}
1844	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1845	}
1846
1847
1848	#ifdef VBOX_WITH_NESTED_HWVIRT
1849	/**
1850	* Loads the nested-guest APIC state (currently just the TPR).
1851	*
1852	* @param pVCpu The cross context virtual CPU structure.
1853	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1854	*/
1855	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1856	{
1857	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1858	{
1859	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1860	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1861	pVCpu->hm.s.svm.fSyncVTpr = false;
1862	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1863
1864	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1865	}
1866	}
1867	#endif
1868
1869	/**
1870	* Loads the guest APIC state (currently just the TPR).
1871	*
1872	* @returns VBox status code.
1873	* @param pVCpu The cross context virtual CPU structure.
1874	* @param pVmcb Pointer to the VM control block.
1875	* @param pCtx Pointer to the guest-CPU context.
1876	*/
1877	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1878	{
1879	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1880	return VINF_SUCCESS;
1881
1882	int rc = VINF_SUCCESS;
1883	PVM pVM = pVCpu->CTX_SUFF(pVM);
1884	if ( PDMHasApic(pVM)
1885	&& APICIsEnabled(pVCpu))
1886	{
1887	bool fPendingIntr;
1888	uint8_t u8Tpr;
1889	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1890	AssertRCReturn(rc, rc);
1891
1892	/* Assume that we need to trap all TPR accesses and thus need not check on
1893	every #VMEXIT if we should update the TPR. */
1894	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1895	pVCpu->hm.s.svm.fSyncVTpr = false;
1896
1897	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1898	if (pVM->hm.s.fTPRPatchingActive)
1899	{
1900	pCtx->msrLSTAR = u8Tpr;
1901	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1902
1903	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1904	if (fPendingIntr)
1905	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1906	else
1907	{
1908	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1909	pVCpu->hm.s.svm.fSyncVTpr = true;
1910	}
1911	}
1912	else
1913	{
1914	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1915	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1916
1917	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1918	if (fPendingIntr)
1919	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1920	else
1921	{
1922	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1923	pVCpu->hm.s.svm.fSyncVTpr = true;
1924	}
1925
1926	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1927	}
1928	}
1929
1930	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1931	return rc;
1932	}
1933
1934
1935	/**
1936	* Loads the exception interrupts required for guest (or nested-guest) execution in
1937	* the VMCB.
1938	*
1939	* @param pVCpu The cross context virtual CPU structure.
1940	* @param pVmcb Pointer to the VM control block.
1941	* @param pCtx Pointer to the guest-CPU context.
1942	*/
1943	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1944	{
1945	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1946	{
1947	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1948	if (pVCpu->hm.s.fGIMTrapXcptUD)
1949	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1950	else
1951	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_UD);
1952
1953	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1954	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1955	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1956	else
1957	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_BP);
1958
1959	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1960	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1961	}
1962	}
1963
1964
1965	#ifdef VBOX_WITH_NESTED_HWVIRT
1966	/**
1967	* Loads the intercepts required for nested-guest execution in the VMCB.
1968	*
1969	* This merges the guest and nested-guest intercepts in a way that if the outer
1970	* guest intercepts an exception we need to intercept it in the nested-guest as
1971	* well and handle it accordingly.
1972	*
1973	* @param pVCpu The cross context virtual CPU structure.
1974	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1975	* @param pCtx Pointer to the guest-CPU context.
1976	*/
1977	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1978	{
1979	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1980	{
1981	/* First, load the guest intercepts into the guest VMCB. */
1982	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1983	Assert(!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR));
1984	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1985
1986	/* Next, merge the intercepts into the nested-guest VMCB. */
1987	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1988	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1989
1990	/* Always intercept CR0, CR4 reads and writes as we alter them. */
1991	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(0) \| RT_BIT(4);
1992	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(0) \| RT_BIT(4);
1993
1994	/* Always intercept CR3 reads and writes without nested-paging as we load shadow page tables. */
1995	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1996	{
1997	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1998	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1999	}
2000
2001	/** @todo Figure out debugging with nested-guests, till then just intercept
2002	* all DR[0-15] accesses. */
2003	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
2004	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
2005
2006	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2007	pVmcbNstGst->ctrl.u64InterceptCtrl \|= pVmcb->ctrl.u64InterceptCtrl
2008	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2009
2010	/*
2011	* Adjust control intercepts while executing the nested-guest that differ
2012	* from the outer guest intercepts.
2013	*
2014	* VMMCALL when not intercepted raises a \#UD exception in the guest. However,
2015	* other SVM instructions like VMSAVE when not intercept can cause havoc on the
2016	* host as they can write to any location in physical memory, hence they always
2017	* need to be intercepted (see below).
2018	*/
2019	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2020	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2021	pVmcbNstGst->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VMMCALL;
2022
2023	/*
2024	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2025	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2026	*/
2027	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2028	{
2029	pVmcbNstGst->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2030	\| SVM_CTRL_INTERCEPT_VMLOAD;
2031	}
2032
2033	/*
2034	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2035	* CLGI/STGI instructions executed by the nested-guest.
2036	*/
2037	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2038	{
2039	pVmcbNstGst->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2040	\| SVM_CTRL_INTERCEPT_STGI;
2041	}
2042
2043	/* Finally, update the VMCB clean bits. */
2044	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2045
2046	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS));
2047	}
2048	}
2049	#endif
2050
2051
2052	/**
2053	* Sets up the appropriate function to run guest code.
2054	*
2055	* @returns VBox status code.
2056	* @param pVCpu The cross context virtual CPU structure.
2057	*
2058	* @remarks No-long-jump zone!!!
2059	*/
2060	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
2061	{
2062	if (CPUMIsGuestInLongMode(pVCpu))
2063	{
2064	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2065	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2066	#endif
2067	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2068	#if HC_ARCH_BITS == 32
2069	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2070	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2071	#else
2072	/* 64-bit host or hybrid host. */
2073	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2074	#endif
2075	}
2076	else
2077	{
2078	/* Guest is not in long mode, use the 32-bit handler. */
2079	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2080	}
2081	return VINF_SUCCESS;
2082	}
2083
2084
2085	/**
2086	* Enters the AMD-V session.
2087	*
2088	* @returns VBox status code.
2089	* @param pVM The cross context VM structure.
2090	* @param pVCpu The cross context virtual CPU structure.
2091	* @param pCpu Pointer to the CPU info struct.
2092	*/
2093	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2094	{
2095	AssertPtr(pVM);
2096	AssertPtr(pVCpu);
2097	Assert(pVM->hm.s.svm.fSupported);
2098	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2099	NOREF(pVM); NOREF(pCpu);
2100
2101	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2102	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2103
2104	pVCpu->hm.s.fLeaveDone = false;
2105	return VINF_SUCCESS;
2106	}
2107
2108
2109	/**
2110	* Thread-context callback for AMD-V.
2111	*
2112	* @param enmEvent The thread-context event.
2113	* @param pVCpu The cross context virtual CPU structure.
2114	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2115	* @thread EMT(pVCpu)
2116	*/
2117	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2118	{
2119	NOREF(fGlobalInit);
2120
2121	switch (enmEvent)
2122	{
2123	case RTTHREADCTXEVENT_OUT:
2124	{
2125	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2126	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2127	VMCPU_ASSERT_EMT(pVCpu);
2128
2129	/* No longjmps (log-flush, locks) in this fragile context. */
2130	VMMRZCallRing3Disable(pVCpu);
2131
2132	if (!pVCpu->hm.s.fLeaveDone)
2133	{
2134	hmR0SvmLeave(pVCpu);
2135	pVCpu->hm.s.fLeaveDone = true;
2136	}
2137
2138	/* Leave HM context, takes care of local init (term). */
2139	int rc = HMR0LeaveCpu(pVCpu);
2140	AssertRC(rc); NOREF(rc);
2141
2142	/* Restore longjmp state. */
2143	VMMRZCallRing3Enable(pVCpu);
2144	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2145	break;
2146	}
2147
2148	case RTTHREADCTXEVENT_IN:
2149	{
2150	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2151	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2152	VMCPU_ASSERT_EMT(pVCpu);
2153
2154	/* No longjmps (log-flush, locks) in this fragile context. */
2155	VMMRZCallRing3Disable(pVCpu);
2156
2157	/*
2158	* Initialize the bare minimum state required for HM. This takes care of
2159	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2160	*/
2161	int rc = HMR0EnterCpu(pVCpu);
2162	AssertRC(rc); NOREF(rc);
2163	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2164
2165	pVCpu->hm.s.fLeaveDone = false;
2166
2167	/* Restore longjmp state. */
2168	VMMRZCallRing3Enable(pVCpu);
2169	break;
2170	}
2171
2172	default:
2173	break;
2174	}
2175	}
2176
2177
2178	/**
2179	* Saves the host state.
2180	*
2181	* @returns VBox status code.
2182	* @param pVM The cross context VM structure.
2183	* @param pVCpu The cross context virtual CPU structure.
2184	*
2185	* @remarks No-long-jump zone!!!
2186	*/
2187	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
2188	{
2189	NOREF(pVM);
2190	NOREF(pVCpu);
2191	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2192	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
2193	return VINF_SUCCESS;
2194	}
2195
2196
2197	/**
2198	* Loads the guest state into the VMCB.
2199	*
2200	* The CPU state will be loaded from these fields on every successful VM-entry.
2201	* Also sets up the appropriate VMRUN function to execute guest code based on
2202	* the guest CPU mode.
2203	*
2204	* @returns VBox status code.
2205	* @param pVM The cross context VM structure.
2206	* @param pVCpu The cross context virtual CPU structure.
2207	* @param pCtx Pointer to the guest-CPU context.
2208	*
2209	* @remarks No-long-jump zone!!!
2210	*/
2211	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2212	{
2213	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2214
2215	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2216	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2217
2218	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2219
2220	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
2221	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2222
2223	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
2224	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
2225
2226	pVmcb->guest.u64RIP = pCtx->rip;
2227	pVmcb->guest.u64RSP = pCtx->rsp;
2228	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2229	pVmcb->guest.u64RAX = pCtx->rax;
2230
2231	#ifdef VBOX_WITH_NESTED_HWVIRT
2232	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1)
2233	{
2234	Assert(pVM->hm.s.svm.fVGif);
2235	pVmcb->ctrl.IntCtrl.n.u1VGif = pCtx->hwvirt.svm.fGif;
2236	}
2237	#endif
2238
2239	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
2240	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2241
2242	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
2243
2244	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2245	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2246
2247	/* Clear any unused and reserved bits. */
2248	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2249	\| HM_CHANGED_GUEST_RSP
2250	\| HM_CHANGED_GUEST_RFLAGS
2251	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2252	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2253	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2254	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2255	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2256	\| HM_CHANGED_SVM_RESERVED2
2257	\| HM_CHANGED_SVM_RESERVED3
2258	\| HM_CHANGED_SVM_RESERVED4);
2259
2260	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2261	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2262	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2263	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2264
2265	Log4(("hmR0SvmLoadGuestState: CS:RIP=%04x:%RX64 EFL=%#x CR0=%#RX32 CR3=%#RX32 CR4=%#RX32 ESP=%#RX32 EBP=%#RX32\n",
2266	pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4, pCtx->esp, pCtx->ebp));
2267	Log4(("hmR0SvmLoadGuestState: SS={%04x base=%016RX64 limit=%08x flags=%08x}\n", pCtx->ss.Sel, pCtx->ss.u64Base,
2268	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
2269	Log4(("hmR0SvmLoadGuestState: FS={%04x base=%016RX64 limit=%08x flags=%08x}\n", pCtx->fs.Sel, pCtx->fs.u64Base,
2270	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
2271	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2272	return rc;
2273	}
2274
2275
2276	#ifdef VBOX_WITH_NESTED_HWVIRT
2277	/**
2278	* Caches the nested-guest VMCB fields before we modify them for execution using
2279	* hardware-assisted SVM.
2280	*
2281	* @returns true if the VMCB was previously already cached, false otherwise.
2282	* @param pCtx Pointer to the guest-CPU context.
2283	*
2284	* @sa HMSvmNstGstVmExitNotify.
2285	*/
2286	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2287	{
2288	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2289	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2290	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2291	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2292
2293	/*
2294	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2295	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2296	*
2297	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2298	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2299	*/
2300	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2301	if (!fWasCached)
2302	{
2303	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2304	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2305	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2306	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2307	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2308	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2309	pNstGstVmcbCache->u64CR0 = pVmcbNstGstState->u64CR0;
2310	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2311	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2312	pNstGstVmcbCache->u64EFER = pVmcbNstGstState->u64EFER;
2313	pNstGstVmcbCache->u64DBGCTL = pVmcbNstGstState->u64DBGCTL;
2314	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2315	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2316	pNstGstVmcbCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2317	pNstGstVmcbCache->u32VmcbCleanBits = pVmcbNstGstCtrl->u32VmcbCleanBits;
2318	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2319	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2320	pNstGstVmcbCache->u1NestedPaging = pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging;
2321	pNstGstVmcbCache->u1LbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2322	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2323	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2324	}
2325
2326	return fWasCached;
2327	}
2328
2329
2330	/**
2331	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2332	*
2333	* @param pVCpu The cross context virtual CPU structure.
2334	* @param pCtx Pointer to the guest-CPU context.
2335	*/
2336	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2337	{
2338	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2339	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2340
2341	/*
2342	* First cache the nested-guest VMCB fields we may potentially modify.
2343	*/
2344	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2345	if (!fVmcbCached)
2346	{
2347	/*
2348	* The IOPM of the nested-guest can be ignored because the the guest always
2349	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2350	* into the nested-guest one and swap it back on the #VMEXIT.
2351	*/
2352	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2353
2354	/*
2355	* Load the host-physical address into the MSRPM rather than the nested-guest
2356	* physical address (currently we trap all MSRs in the nested-guest).
2357	*/
2358	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2359
2360	/*
2361	* Use the same nested-paging as the "outer" guest. We can't dynamically
2362	* switch off nested-paging suddenly while executing a VM (see assertion at the
2363	* end of Trap0eHandler in PGMAllBth.h).
2364	*/
2365	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2366
2367	/* For now copy the LBR info. from outer guest VMCB. */
2368	/** @todo fix this later. */
2369	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2370	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2371	pVmcbNstGst->guest.u64DBGCTL = pVmcb->guest.u64DBGCTL;
2372	}
2373	else
2374	{
2375	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2376	Assert(pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap);
2377	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2378	}
2379	}
2380
2381
2382	/**
2383	* Loads the nested-guest state into the VMCB.
2384	*
2385	* @returns VBox status code.
2386	* @param pVCpu The cross context virtual CPU structure.
2387	* @param pCtx Pointer to the guest-CPU context.
2388	*
2389	* @remarks No-long-jump zone!!!
2390	*/
2391	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2392	{
2393	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2394
2395	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2396	Assert(pVmcbNstGst);
2397
2398	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2399
2400	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
2401	AssertRCReturn(rc, rc);
2402
2403	/*
2404	* We need to load the entire state (including FS, GS etc.) as we could be continuing
2405	* to execute the nested-guest at any point (not just immediately after VMRUN) and thus
2406	* the VMCB can possibly be out-of-sync with the actual nested-guest state if it was
2407	* executed in IEM.
2408	*/
2409	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2410	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2411	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2412
2413	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2414	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2415	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2416	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2417
2418	#ifdef VBOX_WITH_NESTED_HWVIRT
2419	Assert(pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable == 0); /* Nested VGIF not supported yet. */
2420	#endif
2421
2422	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst, pCtx);
2423
2424	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2425	AssertRCReturn(rc, rc);
2426
2427	/* Clear any unused and reserved bits. */
2428	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2429	\| HM_CHANGED_GUEST_RSP
2430	\| HM_CHANGED_GUEST_RFLAGS
2431	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2432	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2433	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2434	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2435	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2436	\| HM_CHANGED_SVM_RESERVED2
2437	\| HM_CHANGED_SVM_RESERVED3
2438	\| HM_CHANGED_SVM_RESERVED4);
2439
2440	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2441	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2442	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2443	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2444
2445	#ifdef VBOX_STRICT
2446	hmR0SvmLogState(pVCpu, pVmcbNstGst, pCtx, "hmR0SvmLoadGuestStateNested", HMSVM_LOG_ALL, 0 /* uVerbose */);
2447	#endif
2448	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2449	return rc;
2450	}
2451	#endif
2452
2453
2454	/**
2455	* Loads the state shared between the host and guest or nested-guest into the
2456	* VMCB.
2457	*
2458	* @param pVCpu The cross context virtual CPU structure.
2459	* @param pVmcb Pointer to the VM control block.
2460	* @param pCtx Pointer to the guest-CPU context.
2461	*
2462	* @remarks No-long-jump zone!!!
2463	*/
2464	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2465	{
2466	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2467	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2468
2469	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2470	{
2471	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2472	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2473	}
2474
2475	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2476	{
2477	/** @todo Figure out stepping with nested-guest. */
2478	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2479	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2480	else
2481	{
2482	pVmcb->guest.u64DR6 = pCtx->dr[6];
2483	pVmcb->guest.u64DR7 = pCtx->dr[7];
2484	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2485	}
2486
2487	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2488	}
2489
2490	/* Unused on AMD-V. */
2491	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2492
2493	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2494	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2495	}
2496
2497
2498	/**
2499	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2500	* context.
2501	*
2502	* Currently there is no residual state left in the CPU that is not updated in the
2503	* VMCB.
2504	*
2505	* @returns VBox status code.
2506	* @param pVCpu The cross context virtual CPU structure.
2507	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2508	* out-of-sync. Make sure to update the required fields
2509	* before using them.
2510	* @param pVmcb Pointer to the VM control block.
2511	*/
2512	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2513	{
2514	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2515
2516	pMixedCtx->rip = pVmcb->guest.u64RIP;
2517	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2518	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2519	pMixedCtx->rax = pVmcb->guest.u64RAX;
2520
2521	#ifdef VBOX_WITH_NESTED_HWVIRT
2522	/*
2523	* Guest Virtual GIF (Global Interrupt Flag).
2524	*/
2525	if ( pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1
2526	&& !CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2527	{
2528	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fVGif);
2529	pMixedCtx->hwvirt.svm.fGif = pVmcb->ctrl.IntCtrl.n.u1VGif;
2530	}
2531	#endif
2532
2533	/*
2534	* Guest interrupt shadow.
2535	*/
2536	if (pVmcb->ctrl.IntShadow.n.u1IntShadow)
2537	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2538	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2539	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2540
2541	/*
2542	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2543	*/
2544	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2545
2546	/*
2547	* Guest MSRs.
2548	*/
2549	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2550	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2551	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2552	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2553	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2554	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2555	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2556	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2557
2558	/*
2559	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2560	*/
2561	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2562	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2563	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2564	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2565	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2566	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2567
2568	/*
2569	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2570	* register (yet).
2571	*/
2572	/** @todo SELM might need to be fixed as it too should not care about the
2573	* granularity bit. See @bugref{6785}. */
2574	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2575	&& pMixedCtx->cs.Attr.n.u1Present
2576	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2577	{
2578	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2579	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2580	}
2581
2582	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2583	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2584	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2585	HMSVM_ASSERT_SEG_GRANULARITY(es);
2586	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2587	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2588
2589	/*
2590	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2591	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2592	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2593	* See AMD spec. 15.5.1 "Basic operation".
2594	*/
2595	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2596	uint8_t const uCpl = pVmcb->guest.u8CPL;
2597	if (pMixedCtx->ss.Attr.n.u2Dpl != uCpl)
2598	{
2599	Log4(("hmR0SvmSaveGuestState: CPL differs. SS.DPL=%u, CPL=%u, overwriting SS.DPL!\n", pMixedCtx->ss.Attr.n.u2Dpl, uCpl));
2600	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2601	}
2602
2603	/*
2604	* Guest TR.
2605	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2606	* between Intel and AMD. See @bugref{6208#c39}.
2607	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2608	*/
2609	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2610	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2611	{
2612	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2613	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2614	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2615	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2616	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2617	}
2618
2619	/*
2620	* Guest Descriptor-Table registers (GDTR, IDTR, LDTR).
2621	*/
2622	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2623	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2624	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2625
2626	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2627	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2628
2629	/*
2630	* Guest Debug registers.
2631	*/
2632	if (!pVCpu->hm.s.fUsingHyperDR7)
2633	{
2634	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2635	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2636	}
2637	else
2638	{
2639	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2640	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2641	}
2642
2643	/*
2644	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2645	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2646	*/
2647	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2648	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2649	{
2650	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2651	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2652	}
2653
2654	#ifdef VBOX_STRICT
2655	if (CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2656	hmR0SvmLogState(pVCpu, pVmcb, pMixedCtx, "hmR0SvmSaveGuestStateNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR, 0 /* uVerbose */);
2657	#endif
2658	}
2659
2660
2661	/**
2662	* Does the necessary state syncing before returning to ring-3 for any reason
2663	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2664	*
2665	* @param pVCpu The cross context virtual CPU structure.
2666	*
2667	* @remarks No-long-jmp zone!!!
2668	*/
2669	static void hmR0SvmLeave(PVMCPU pVCpu)
2670	{
2671	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2672	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2673	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2674
2675	/*
2676	* !!! IMPORTANT !!!
2677	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2678	*/
2679
2680	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2681	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2682	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); /** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2683
2684	/*
2685	* Restore host debug registers if necessary and resync on next R0 reentry.
2686	*/
2687	#ifdef VBOX_STRICT
2688	if (CPUMIsHyperDebugStateActive(pVCpu))
2689	{
2690	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2691	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2692	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2693	}
2694	#endif
2695	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2696	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);/** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2697
2698	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2699	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2700
2701	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2702	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2703	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2704	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2705	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2706
2707	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2708	}
2709
2710
2711	/**
2712	* Leaves the AMD-V session.
2713	*
2714	* @returns VBox status code.
2715	* @param pVCpu The cross context virtual CPU structure.
2716	*/
2717	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2718	{
2719	HM_DISABLE_PREEMPT();
2720	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2721	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2722
2723	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2724	and done this from the SVMR0ThreadCtxCallback(). */
2725	if (!pVCpu->hm.s.fLeaveDone)
2726	{
2727	hmR0SvmLeave(pVCpu);
2728	pVCpu->hm.s.fLeaveDone = true;
2729	}
2730
2731	/*
2732	* !!! IMPORTANT !!!
2733	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2734	*/
2735
2736	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2737	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2738	VMMR0ThreadCtxHookDisable(pVCpu);
2739
2740	/* Leave HM context. This takes care of local init (term). */
2741	int rc = HMR0LeaveCpu(pVCpu);
2742
2743	HM_RESTORE_PREEMPT();
2744	return rc;
2745	}
2746
2747
2748	/**
2749	* Does the necessary state syncing before doing a longjmp to ring-3.
2750	*
2751	* @returns VBox status code.
2752	* @param pVCpu The cross context virtual CPU structure.
2753	*
2754	* @remarks No-long-jmp zone!!!
2755	*/
2756	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2757	{
2758	return hmR0SvmLeaveSession(pVCpu);
2759	}
2760
2761
2762	/**
2763	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2764	* any remaining host state) before we longjump to ring-3 and possibly get
2765	* preempted.
2766	*
2767	* @param pVCpu The cross context virtual CPU structure.
2768	* @param enmOperation The operation causing the ring-3 longjump.
2769	* @param pvUser The user argument (pointer to the possibly
2770	* out-of-date guest-CPU context).
2771	*/
2772	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2773	{
2774	RT_NOREF_PV(pvUser);
2775
2776	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2777	{
2778	/*
2779	* !!! IMPORTANT !!!
2780	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2781	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2782	*/
2783	VMMRZCallRing3RemoveNotification(pVCpu);
2784	VMMRZCallRing3Disable(pVCpu);
2785	HM_DISABLE_PREEMPT();
2786
2787	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2788	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2789
2790	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2791	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2792
2793	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2794	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2795	VMMR0ThreadCtxHookDisable(pVCpu);
2796
2797	/* Leave HM context. This takes care of local init (term). */
2798	HMR0LeaveCpu(pVCpu);
2799
2800	HM_RESTORE_PREEMPT();
2801	return VINF_SUCCESS;
2802	}
2803
2804	Assert(pVCpu);
2805	Assert(pvUser);
2806	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2807	HMSVM_ASSERT_PREEMPT_SAFE();
2808
2809	VMMRZCallRing3Disable(pVCpu);
2810	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2811
2812	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2813	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2814	AssertRCReturn(rc, rc);
2815
2816	VMMRZCallRing3Enable(pVCpu);
2817	return VINF_SUCCESS;
2818	}
2819
2820
2821	/**
2822	* Take necessary actions before going back to ring-3.
2823	*
2824	* An action requires us to go back to ring-3. This function does the necessary
2825	* steps before we can safely return to ring-3. This is not the same as longjmps
2826	* to ring-3, this is voluntary.
2827	*
2828	* @returns VBox status code.
2829	* @param pVM The cross context VM structure.
2830	* @param pVCpu The cross context virtual CPU structure.
2831	* @param pCtx Pointer to the guest-CPU context.
2832	* @param rcExit The reason for exiting to ring-3. Can be
2833	* VINF_VMM_UNKNOWN_RING3_CALL.
2834	*/
2835	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2836	{
2837	Assert(pVM);
2838	Assert(pVCpu);
2839	Assert(pCtx);
2840	HMSVM_ASSERT_PREEMPT_SAFE();
2841
2842	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2843	VMMRZCallRing3Disable(pVCpu);
2844	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
2845	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
2846
2847	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2848	if (pVCpu->hm.s.Event.fPending)
2849	{
2850	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2851	Assert(!pVCpu->hm.s.Event.fPending);
2852	}
2853
2854	/* Sync. the necessary state for going back to ring-3. */
2855	hmR0SvmLeaveSession(pVCpu);
2856	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2857
2858	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2859	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2860	\| CPUM_CHANGED_LDTR
2861	\| CPUM_CHANGED_GDTR
2862	\| CPUM_CHANGED_IDTR
2863	\| CPUM_CHANGED_TR
2864	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2865	if ( pVM->hm.s.fNestedPaging
2866	&& CPUMIsGuestPagingEnabledEx(pCtx))
2867	{
2868	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2869	}
2870
2871	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2872	if (rcExit != VINF_EM_RAW_INTERRUPT)
2873	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2874
2875	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2876
2877	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2878	VMMRZCallRing3RemoveNotification(pVCpu);
2879	VMMRZCallRing3Enable(pVCpu);
2880
2881	/*
2882	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2883	* and if we're injecting an event we should have a TRPM trap pending.
2884	*/
2885	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2886	pVCpu->hm.s.u32HMError = rcExit,
2887	VERR_SVM_IPE_5);
2888	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2889	pVCpu->hm.s.u32HMError = rcExit,
2890	VERR_SVM_IPE_4);
2891
2892	return rcExit;
2893	}
2894
2895
2896	#ifdef VBOX_WITH_NESTED_HWVIRT
2897	/**
2898	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2899	* intercepts for the nested-guest.
2900	*
2901	* @param pVM The cross context VM structure.
2902	* @param pVCpu The cross context virtual CPU structure.
2903	* @param pCtx Pointer to the nested guest-CPU context.
2904	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2905	*
2906	* @remarks No-long-jump zone!!!
2907	*/
2908	static void hmR0SvmUpdateTscOffsettingNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcbNstGst)
2909	{
2910	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2911
2912	bool fParavirtTsc;
2913	uint64_t uTscOffset;
2914	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
2915
2916	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2917	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2918
2919	/*
2920	* Only avoid intercepting if we determined the host TSC (++) is stable enough
2921	* to not intercept -and- the nested-hypervisor itself does not want to intercept it.
2922	*/
2923	if ( fCanUseRealTsc
2924	&& !(pVmcbNstGstCache->u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
2925	{
2926	pVmcbNstGstCtrl->u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2927	pVmcbNstGstCtrl->u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2928	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2929	}
2930	else
2931	{
2932	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2933	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2934	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2935	}
2936
2937	/* Apply the nested-guest VMCB's TSC offset over the guest one. */
2938	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
2939
2940	/* Update the nested-guest VMCB with the combined TSC offset (of guest and nested-guest). */
2941	pVmcbNstGstCtrl->u64TSCOffset = uTscOffset;
2942
2943	/* Finally update the VMCB clean bits since we touched the intercepts as well as the TSC offset. */
2944	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2945
2946	if (fParavirtTsc)
2947	{
2948	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2949	information before every VM-entry, hence disable it for performance sake. */
2950	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2951	}
2952	}
2953	#endif
2954
2955
2956	/**
2957	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2958	* intercepts.
2959	*
2960	* @param pVM The cross context VM structure.
2961	* @param pVCpu The cross context virtual CPU structure.
2962	* @param pVmcb Pointer to the VM control block.
2963	*
2964	* @remarks No-long-jump zone!!!
2965	*/
2966	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2967	{
2968	bool fParavirtTsc;
2969	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2970	if (fCanUseRealTsc)
2971	{
2972	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2973	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2974	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2975	}
2976	else
2977	{
2978	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2979	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2980	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2981	}
2982	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2983
2984	/** @todo later optimize this to be done elsewhere and not before every
2985	* VM-entry. */
2986	if (fParavirtTsc)
2987	{
2988	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2989	information before every VM-entry, hence disable it for performance sake. */
2990	#if 0
2991	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2992	AssertRC(rc);
2993	#endif
2994	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2995	}
2996	}
2997
2998
2999	/**
3000	* Sets an event as a pending event to be injected into the guest.
3001	*
3002	* @param pVCpu The cross context virtual CPU structure.
3003	* @param pEvent Pointer to the SVM event.
3004	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3005	* page-fault.
3006	*
3007	* @remarks Statistics counter assumes this is a guest event being reflected to
3008	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3009	*/
3010	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3011	{
3012	Assert(!pVCpu->hm.s.Event.fPending);
3013	Assert(pEvent->n.u1Valid);
3014
3015	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3016	pVCpu->hm.s.Event.fPending = true;
3017	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3018
3019	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3020	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3021	}
3022
3023
3024	/**
3025	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3026	*
3027	* @param pVCpu The cross context virtual CPU structure.
3028	*/
3029	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3030	{
3031	SVMEVENT Event;
3032	Event.u = 0;
3033	Event.n.u1Valid = 1;
3034	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3035	Event.n.u8Vector = X86_XCPT_UD;
3036	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3037	}
3038
3039
3040	/**
3041	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3042	*
3043	* @param pVCpu The cross context virtual CPU structure.
3044	*/
3045	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3046	{
3047	SVMEVENT Event;
3048	Event.u = 0;
3049	Event.n.u1Valid = 1;
3050	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3051	Event.n.u8Vector = X86_XCPT_DB;
3052	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3053	}
3054
3055
3056	/**
3057	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3058	*
3059	* @param pVCpu The cross context virtual CPU structure.
3060	* @param pCtx Pointer to the guest-CPU context.
3061	* @param u32ErrCode The error-code for the page-fault.
3062	* @param uFaultAddress The page fault address (CR2).
3063	*
3064	* @remarks This updates the guest CR2 with @a uFaultAddress!
3065	*/
3066	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3067	{
3068	SVMEVENT Event;
3069	Event.u = 0;
3070	Event.n.u1Valid = 1;
3071	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3072	Event.n.u8Vector = X86_XCPT_PF;
3073	Event.n.u1ErrorCodeValid = 1;
3074	Event.n.u32ErrorCode = u32ErrCode;
3075
3076	/* Update CR2 of the guest. */
3077	if (pCtx->cr2 != uFaultAddress)
3078	{
3079	pCtx->cr2 = uFaultAddress;
3080	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3081	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3082	}
3083
3084	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3085	}
3086
3087
3088	/**
3089	* Sets a device-not-available (\#NM) exception as pending-for-injection into
3090	* the VM.
3091	*
3092	* @param pVCpu The cross context virtual CPU structure.
3093	*/
3094	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3095	{
3096	SVMEVENT Event;
3097	Event.u = 0;
3098	Event.n.u1Valid = 1;
3099	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3100	Event.n.u8Vector = X86_XCPT_NM;
3101	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3102	}
3103
3104
3105	/**
3106	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3107	*
3108	* @param pVCpu The cross context virtual CPU structure.
3109	*/
3110	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3111	{
3112	SVMEVENT Event;
3113	Event.u = 0;
3114	Event.n.u1Valid = 1;
3115	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3116	Event.n.u8Vector = X86_XCPT_MF;
3117	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3118	}
3119
3120
3121	/**
3122	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3123	*
3124	* @param pVCpu The cross context virtual CPU structure.
3125	*/
3126	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3127	{
3128	SVMEVENT Event;
3129	Event.u = 0;
3130	Event.n.u1Valid = 1;
3131	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3132	Event.n.u8Vector = X86_XCPT_DF;
3133	Event.n.u1ErrorCodeValid = 1;
3134	Event.n.u32ErrorCode = 0;
3135	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3136	}
3137
3138
3139	/**
3140	* Injects an event into the guest upon VMRUN by updating the relevant field
3141	* in the VMCB.
3142	*
3143	* @param pVCpu The cross context virtual CPU structure.
3144	* @param pVmcb Pointer to the guest VM control block.
3145	* @param pCtx Pointer to the guest-CPU context.
3146	* @param pEvent Pointer to the event.
3147	*
3148	* @remarks No-long-jump zone!!!
3149	* @remarks Requires CR0!
3150	*/
3151	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
3152	{
3153	NOREF(pVCpu); NOREF(pCtx);
3154
3155	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3156	pVmcb->ctrl.EventInject.u = pEvent->u;
3157	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3158
3159	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3160	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3161	}
3162
3163
3164
3165	/**
3166	* Converts any TRPM trap into a pending HM event. This is typically used when
3167	* entering from ring-3 (not longjmp returns).
3168	*
3169	* @param pVCpu The cross context virtual CPU structure.
3170	*/
3171	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3172	{
3173	Assert(TRPMHasTrap(pVCpu));
3174	Assert(!pVCpu->hm.s.Event.fPending);
3175
3176	uint8_t uVector;
3177	TRPMEVENT enmTrpmEvent;
3178	RTGCUINT uErrCode;
3179	RTGCUINTPTR GCPtrFaultAddress;
3180	uint8_t cbInstr;
3181
3182	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3183	AssertRC(rc);
3184
3185	SVMEVENT Event;
3186	Event.u = 0;
3187	Event.n.u1Valid = 1;
3188	Event.n.u8Vector = uVector;
3189
3190	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3191	if (enmTrpmEvent == TRPM_TRAP)
3192	{
3193	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3194	switch (uVector)
3195	{
3196	case X86_XCPT_NMI:
3197	{
3198	Event.n.u3Type = SVM_EVENT_NMI;
3199	break;
3200	}
3201
3202	case X86_XCPT_PF:
3203	case X86_XCPT_DF:
3204	case X86_XCPT_TS:
3205	case X86_XCPT_NP:
3206	case X86_XCPT_SS:
3207	case X86_XCPT_GP:
3208	case X86_XCPT_AC:
3209	{
3210	Event.n.u1ErrorCodeValid = 1;
3211	Event.n.u32ErrorCode = uErrCode;
3212	break;
3213	}
3214	}
3215	}
3216	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3217	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3218	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3219	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3220	else
3221	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3222
3223	rc = TRPMResetTrap(pVCpu);
3224	AssertRC(rc);
3225
3226	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3227	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3228
3229	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3230	}
3231
3232
3233	/**
3234	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3235	* AMD-V to execute any instruction.
3236	*
3237	* @param pVCpu The cross context virtual CPU structure.
3238	*/
3239	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3240	{
3241	Assert(pVCpu->hm.s.Event.fPending);
3242	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3243
3244	SVMEVENT Event;
3245	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3246
3247	uint8_t uVector = Event.n.u8Vector;
3248	uint8_t uVectorType = Event.n.u3Type;
3249	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3250
3251	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3252
3253	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3254	AssertRC(rc);
3255
3256	if (Event.n.u1ErrorCodeValid)
3257	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3258
3259	if ( uVectorType == SVM_EVENT_EXCEPTION
3260	&& uVector == X86_XCPT_PF)
3261	{
3262	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3263	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3264	}
3265	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3266	{
3267	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3268	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3269	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3270	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3271	}
3272	pVCpu->hm.s.Event.fPending = false;
3273	}
3274
3275
3276	/**
3277	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3278	* now.
3279	*
3280	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3281	* @param pVCpu The cross context virtual CPU structure.
3282	* @param pCtx Pointer to the guest-CPU context.
3283	*
3284	* @remarks No-long-jump zone!!!
3285	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3286	*/
3287	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
3288	{
3289	/*
3290	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
3291	* inhibit interrupts or clear any existing interrupt-inhibition.
3292	*/
3293	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3294	{
3295	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
3296	{
3297	/*
3298	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3299	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
3300	*/
3301	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3302	return false;
3303	}
3304	return true;
3305	}
3306	return false;
3307	}
3308
3309
3310	/**
3311	* Sets the virtual interrupt intercept control in the VMCB.
3312	*
3313	* @param pVmcb Pointer to the VM control block.
3314	*/
3315	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
3316	{
3317	/*
3318	* When AVIC isn't supported, indicate that a virtual interrupt is pending and to
3319	* cause a #VMEXIT when the guest is ready to accept interrupts. At #VMEXIT, we
3320	* then get the interrupt from the APIC (updating ISR at the right time) and
3321	* inject the interrupt.
3322	*
3323	* With AVIC is supported, we could make use of the asynchronously delivery without
3324	* #VMEXIT and we would be passing the AVIC page to SVM.
3325	*/
3326	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3327	{
3328	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 0);
3329	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3330	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
3331	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3332	Log4(("Set VINTR intercept\n"));
3333	}
3334	}
3335
3336
3337	/**
3338	* Clears the virtual interrupt intercept control in the VMCB as
3339	* we are figured the guest is unable process any interrupts
3340	* at this point of time.
3341	*
3342	* @param pVmcb Pointer to the VM control block.
3343	*/
3344	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
3345	{
3346	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3347	{
3348	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 1);
3349	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
3350	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3351	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3352	Log4(("Cleared VINTR intercept\n"));
3353	}
3354	}
3355
3356
3357	/**
3358	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3359	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3360	* virtual NMIs.
3361	*
3362	* @param pVmcb Pointer to the VM control block.
3363	*/
3364	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3365	{
3366	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3367	{
3368	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3369	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3370
3371	Log4(("Setting IRET intercept\n"));
3372	}
3373	}
3374
3375
3376	/**
3377	* Clears the IRET intercept control in the VMCB.
3378	*
3379	* @param pVmcb Pointer to the VM control block.
3380	*/
3381	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3382	{
3383	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3384	{
3385	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3386	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3387
3388	Log4(("Clearing IRET intercept\n"));
3389	}
3390	}
3391
3392	#ifdef VBOX_WITH_NESTED_HWVIRT
3393
3394
3395	/**
3396	* Evaluates the event to be delivered to the nested-guest and sets it as the
3397	* pending event.
3398	*
3399	* @returns VBox strict status code.
3400	* @param pVCpu The cross context virtual CPU structure.
3401	* @param pCtx Pointer to the guest-CPU context.
3402	*/
3403	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3404	{
3405	Log4Func(("\n"));
3406
3407	Assert(!pVCpu->hm.s.Event.fPending);
3408
3409	bool const fGif = pCtx->hwvirt.svm.fGif;
3410	if (fGif)
3411	{
3412	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3413
3414	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3415
3416	/*
3417	* Check if the nested-guest can receive NMIs.
3418	* NMIs are higher priority than regular interrupts.
3419	*/
3420	/** @todo SMI. SMIs take priority over NMIs. */
3421	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3422	{
3423	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3424	if (fBlockNmi)
3425	hmR0SvmSetIretIntercept(pVmcbNstGst);
3426	else if (fIntShadow)
3427	{
3428	/** @todo Figure this out, how we shall manage virt. intercept if the
3429	* nested-guest already has one set and/or if we really need it? */
3430	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3431	}
3432	else
3433	{
3434	Log4(("Pending NMI\n"));
3435
3436	SVMEVENT Event;
3437	Event.u = 0;
3438	Event.n.u1Valid = 1;
3439	Event.n.u8Vector = X86_XCPT_NMI;
3440	Event.n.u3Type = SVM_EVENT_NMI;
3441
3442	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3443	hmR0SvmSetIretIntercept(pVmcbNstGst);
3444	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3445	return VINF_SUCCESS;
3446	}
3447	}
3448
3449	/*
3450	* Check if the nested-guest can receive external interrupts (generated by
3451	* the guest's PIC/APIC).
3452	*
3453	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3454	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3455	*
3456	* External interrupts that are generated for the outer guest may be intercepted
3457	* depending on how the nested-guest VMCB was programmed by guest software.
3458	*
3459	* Physical interrupts always take priority over virtual interrupts,
3460	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3461	*/
3462	if (!fIntShadow)
3463	{
3464	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3465	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3466	&& !pVCpu->hm.s.fSingleInstruction
3467	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3468	{
3469	if (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_INTR)
3470	{
3471	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3472	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3473	}
3474
3475	uint8_t u8Interrupt;
3476	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3477	if (RT_SUCCESS(rc))
3478	{
3479	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3480
3481	SVMEVENT Event;
3482	Event.u = 0;
3483	Event.n.u1Valid = 1;
3484	Event.n.u8Vector = u8Interrupt;
3485	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3486
3487	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3488	}
3489	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3490	{
3491	/*
3492	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3493	* updated eventually when the TPR is written by the guest.
3494	*/
3495	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3496	}
3497	else
3498	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3499	}
3500
3501	/*
3502	* Check if the nested-guest is intercepting virtual (using V_IRQ and related fields)
3503	* interrupt injection. The virtual interrupt injection itself, if any, will be done
3504	* by the physical CPU.
3505	*/
3506	#if 0
3507	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3508	&& (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3509	&& CPUMCanSvmNstGstTakeVirtIntr(pCtx))
3510	{
3511	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3512	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3513	}
3514	#endif
3515	}
3516	}
3517
3518	return VINF_SUCCESS;
3519	}
3520	#endif
3521
3522
3523	/**
3524	* Evaluates the event to be delivered to the guest and sets it as the pending
3525	* event.
3526	*
3527	* @param pVCpu The cross context virtual CPU structure.
3528	* @param pCtx Pointer to the guest-CPU context.
3529	*
3530	* @remarks Don't use this function when we are actively executing a
3531	* nested-guest, use hmR0SvmEvaluatePendingEventNested instead.
3532	*/
3533	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3534	{
3535	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3536	Assert(!pVCpu->hm.s.Event.fPending);
3537
3538	#ifdef VBOX_WITH_NESTED_HWVIRT
3539	bool const fGif = pCtx->hwvirt.svm.fGif;
3540	#else
3541	bool const fGif = true;
3542	#endif
3543	Log4Func(("fGif=%RTbool\n", fGif));
3544
3545	/*
3546	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3547	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3548	*/
3549	if (fGif)
3550	{
3551	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3552	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3553	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3554	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3555
3556	Log4Func(("fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fBlockInt, fIntShadow,
3557	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3558
3559	/** @todo SMI. SMIs take priority over NMIs. */
3560	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3561	{
3562	if (fBlockNmi)
3563	hmR0SvmSetIretIntercept(pVmcb);
3564	else if (fIntShadow)
3565	hmR0SvmSetVirtIntrIntercept(pVmcb);
3566	else
3567	{
3568	Log4(("Pending NMI\n"));
3569
3570	SVMEVENT Event;
3571	Event.u = 0;
3572	Event.n.u1Valid = 1;
3573	Event.n.u8Vector = X86_XCPT_NMI;
3574	Event.n.u3Type = SVM_EVENT_NMI;
3575
3576	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3577	hmR0SvmSetIretIntercept(pVmcb);
3578	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3579	return;
3580	}
3581	}
3582	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3583	&& !pVCpu->hm.s.fSingleInstruction)
3584	{
3585	/*
3586	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3587	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3588	*/
3589	if ( !fBlockInt
3590	&& !fIntShadow)
3591	{
3592	uint8_t u8Interrupt;
3593	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3594	if (RT_SUCCESS(rc))
3595	{
3596	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3597
3598	SVMEVENT Event;
3599	Event.u = 0;
3600	Event.n.u1Valid = 1;
3601	Event.n.u8Vector = u8Interrupt;
3602	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3603
3604	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3605	}
3606	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3607	{
3608	/*
3609	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3610	* updated eventually when the TPR is written by the guest.
3611	*/
3612	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3613	}
3614	else
3615	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3616	}
3617	else
3618	hmR0SvmSetVirtIntrIntercept(pVmcb);
3619	}
3620	}
3621	}
3622
3623
3624	/**
3625	* Injects any pending events into the guest or nested-guest.
3626	*
3627	* @param pVCpu The cross context virtual CPU structure.
3628	* @param pCtx Pointer to the guest-CPU context.
3629	* @param pVmcb Pointer to the VM control block.
3630	*/
3631	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3632	{
3633	Assert(!TRPMHasTrap(pVCpu));
3634	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3635
3636	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3637	#ifdef VBOX_STRICT
3638	bool const fGif = pCtx->hwvirt.svm.fGif;
3639	bool fAllowInt = fGif;
3640	if (fGif)
3641	{
3642	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3643	fAllowInt = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx);
3644	else
3645	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3646	}
3647	#endif
3648
3649	if (pVCpu->hm.s.Event.fPending)
3650	{
3651	SVMEVENT Event;
3652	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3653	Assert(Event.n.u1Valid);
3654
3655	/*
3656	* Validate event injection pre-conditions.
3657	*/
3658	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3659	{
3660	Assert(fAllowInt);
3661	Assert(!fIntShadow);
3662	}
3663	else if (Event.n.u3Type == SVM_EVENT_NMI)
3664	{
3665	Assert(fGif);
3666	Assert(!fIntShadow);
3667	}
3668
3669	/*
3670	* Inject it (update VMCB for injection by the hardware).
3671	*/
3672	Log4(("Injecting pending HM event\n"));
3673	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3674	pVCpu->hm.s.Event.fPending = false;
3675
3676	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3677	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3678	else
3679	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3680	}
3681	else
3682	{
3683	#ifdef VBOX_WITH_NESTED_HWVIRT
3684	/*
3685	* If IEM emulated VMRUN and injected an event, it would not clear the EVENTINJ::Valid bit
3686	* as a physical CPU clears it in the VMCB as part of the #VMEXIT (if the AMD spec. is to
3687	* believed, real behavior might differ). Regardless, IEM does it only on #VMEXIT for now
3688	* and since we are continuing nested-guest execution using hardware-assisted SVM, we need
3689	* to clear this field otherwise we will inject the event twice, see @bugref{7243#78}.
3690	*/
3691	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3692	pVmcb->ctrl.EventInject.n.u1Valid = 0;
3693	#endif
3694	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3695	}
3696
3697	/*
3698	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3699	*
3700	* For nested-guests: We need to update it too for the scenario where IEM executes
3701	* the nested-guest but execution later continues here with an interrupt shadow active.
3702	*/
3703	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3704	}
3705
3706
3707	/**
3708	* Reports world-switch error and dumps some useful debug info.
3709	*
3710	* @param pVM The cross context VM structure.
3711	* @param pVCpu The cross context virtual CPU structure.
3712	* @param rcVMRun The return code from VMRUN (or
3713	* VERR_SVM_INVALID_GUEST_STATE for invalid
3714	* guest-state).
3715	* @param pCtx Pointer to the guest-CPU context.
3716	*/
3717	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3718	{
3719	NOREF(pCtx);
3720	HMSVM_ASSERT_PREEMPT_SAFE();
3721	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3722	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3723
3724	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3725	{
3726	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3727	#ifdef VBOX_STRICT
3728	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3729	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3730	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3731	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3732	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3733	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3734	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3735	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3736	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3737	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3738
3739	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3740	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3741	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3742
3743	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3744	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3745	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3746	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved0));
3747	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3748	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3749	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3750	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3751	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3752	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved1));
3753	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3754	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3755
3756	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3757	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3758	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3759	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3760	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3761	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3762	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3763	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3764	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3765	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3766	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3767	Log4(("ctrl.NestedPaging.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPaging.n.u1NestedPaging));
3768	Log4(("ctrl.NestedPaging.u1Sev %#x\n", pVmcb->ctrl.NestedPaging.n.u1Sev));
3769	Log4(("ctrl.NestedPaging.u1SevEs %#x\n", pVmcb->ctrl.NestedPaging.n.u1SevEs));
3770	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3771	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3772	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3773	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3774	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3775	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3776
3777	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3778
3779	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3780	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3781
3782	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3783	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3784	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3785	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3786	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3787	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3788	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3789	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3790	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3791	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3792	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3793	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3794	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3795	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3796	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3797	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3798	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3799	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3800	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3801	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3802
3803	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3804	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3805
3806	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3807	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3808	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3809	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3810
3811	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3812	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3813
3814	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3815	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3816	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3817	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3818
3819	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3820	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3821	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3822	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3823	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3824	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3825	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3826
3827	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3828	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3829	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3830	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3831
3832	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3833	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3834	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3835
3836	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3837	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3838	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3839	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3840	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3841	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3842	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3843	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3844	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3845	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3846	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3847	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3848	#endif /* VBOX_STRICT */
3849	}
3850	else
3851	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3852
3853	NOREF(pVmcb);
3854	}
3855
3856
3857	/**
3858	* Check per-VM and per-VCPU force flag actions that require us to go back to
3859	* ring-3 for one reason or another.
3860	*
3861	* @returns VBox status code (information status code included).
3862	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3863	* ring-3.
3864	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3865	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3866	* interrupts)
3867	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3868	* all EMTs to be in ring-3.
3869	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3870	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3871	* to the EM loop.
3872	*
3873	* @param pVM The cross context VM structure.
3874	* @param pVCpu The cross context virtual CPU structure.
3875	* @param pCtx Pointer to the guest-CPU context.
3876	*/
3877	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3878	{
3879	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3880
3881	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3882	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3883	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3884
3885	/* Update pending interrupts into the APIC's IRR. */
3886	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3887	APICUpdatePendingInterrupts(pVCpu);
3888
3889	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3890	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3891	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3892	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3893	{
3894	/* Pending PGM C3 sync. */
3895	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3896	{
3897	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3898	if (rc != VINF_SUCCESS)
3899	{
3900	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3901	return rc;
3902	}
3903	}
3904
3905	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3906	/* -XXX- what was that about single stepping? */
3907	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3908	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3909	{
3910	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3911	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3912	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3913	return rc;
3914	}
3915
3916	/* Pending VM request packets, such as hardware interrupts. */
3917	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3918	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3919	{
3920	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3921	return VINF_EM_PENDING_REQUEST;
3922	}
3923
3924	/* Pending PGM pool flushes. */
3925	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3926	{
3927	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3928	return VINF_PGM_POOL_FLUSH_PENDING;
3929	}
3930
3931	/* Pending DMA requests. */
3932	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3933	{
3934	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3935	return VINF_EM_RAW_TO_R3;
3936	}
3937	}
3938
3939	return VINF_SUCCESS;
3940	}
3941
3942
3943	#ifdef VBOX_WITH_NESTED_HWVIRT
3944	/**
3945	* Does the preparations before executing nested-guest code in AMD-V.
3946	*
3947	* @returns VBox status code (informational status codes included).
3948	* @retval VINF_SUCCESS if we can proceed with running the guest.
3949	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3950	*
3951	* @param pVM The cross context VM structure.
3952	* @param pVCpu The cross context virtual CPU structure.
3953	* @param pCtx Pointer to the guest-CPU context.
3954	* @param pSvmTransient Pointer to the SVM transient structure.
3955	*
3956	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3957	* @sa hmR0SvmPreRunGuest.
3958	*/
3959	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3960	{
3961	HMSVM_ASSERT_PREEMPT_SAFE();
3962
3963	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3964	{
3965	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3966	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3967	return VINF_EM_RESCHEDULE_REM;
3968	#endif
3969	}
3970	else
3971	return VINF_SVM_VMEXIT;
3972
3973	/* Check force flag actions that might require us to go back to ring-3. */
3974	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3975	if (rc != VINF_SUCCESS)
3976	return rc;
3977
3978	if (TRPMHasTrap(pVCpu))
3979	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3980	else if (!pVCpu->hm.s.Event.fPending)
3981	{
3982	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3983	if (rcStrict != VINF_SUCCESS)
3984	return VBOXSTRICTRC_VAL(rcStrict);
3985	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3986	return VINF_SVM_VMEXIT;
3987	}
3988
3989	/*
3990	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3991	* Just do it in software, see @bugref{8411}.
3992	* NB: If we could continue a task switch exit we wouldn't need to do this.
3993	*/
3994	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3995	&& pVCpu->hm.s.Event.fPending
3996	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
3997	{
3998	return VINF_EM_RAW_INJECT_TRPM_EVENT;
3999	}
4000
4001	#ifdef HMSVM_SYNC_FULL_NESTED_GUEST_STATE
4002	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4003	#endif
4004
4005	/*
4006	* Load the nested-guest state.
4007	*/
4008	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
4009	AssertRCReturn(rc, rc);
4010	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */
4011
4012	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */
4013	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
4014
4015	/*
4016	* No longjmps to ring-3 from this point on!!!
4017	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4018	* This also disables flushing of the R0-logger instance (if any).
4019	*/
4020	VMMRZCallRing3Disable(pVCpu);
4021
4022	/*
4023	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4024	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4025	*
4026	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4027	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4028	*
4029	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4030	* executing guest code.
4031	*/
4032	pSvmTransient->fEFlags = ASMIntDisableFlags();
4033	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4034	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4035	{
4036	ASMSetFlags(pSvmTransient->fEFlags);
4037	VMMRZCallRing3Enable(pVCpu);
4038	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4039	return VINF_EM_RAW_TO_R3;
4040	}
4041	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4042	{
4043	ASMSetFlags(pSvmTransient->fEFlags);
4044	VMMRZCallRing3Enable(pVCpu);
4045	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4046	return VINF_EM_RAW_INTERRUPT;
4047	}
4048
4049	/*
4050	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4051	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4052	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4053	*
4054	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4055	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4056	*/
4057	if (pVCpu->hm.s.Event.fPending)
4058	{
4059	SVMEVENT Event;
4060	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4061	if ( Event.n.u1Valid
4062	&& Event.n.u3Type == SVM_EVENT_NMI
4063	&& Event.n.u8Vector == X86_XCPT_NMI
4064	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4065	{
4066	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4067	}
4068	}
4069
4070	return VINF_SUCCESS;
4071	}
4072	#endif
4073
4074
4075	/**
4076	* Does the preparations before executing guest code in AMD-V.
4077	*
4078	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4079	* recompiler. We must be cautious what we do here regarding committing
4080	* guest-state information into the VMCB assuming we assuredly execute the guest
4081	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4082	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4083	* that the recompiler can (and should) use them when it resumes guest
4084	* execution. Otherwise such operations must be done when we can no longer
4085	* exit to ring-3.
4086	*
4087	* @returns VBox status code (informational status codes included).
4088	* @retval VINF_SUCCESS if we can proceed with running the guest.
4089	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4090	*
4091	* @param pVM The cross context VM structure.
4092	* @param pVCpu The cross context virtual CPU structure.
4093	* @param pCtx Pointer to the guest-CPU context.
4094	* @param pSvmTransient Pointer to the SVM transient structure.
4095	*/
4096	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4097	{
4098	HMSVM_ASSERT_PREEMPT_SAFE();
4099	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4100
4101	/* Check force flag actions that might require us to go back to ring-3. */
4102	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
4103	if (rc != VINF_SUCCESS)
4104	return rc;
4105
4106	if (TRPMHasTrap(pVCpu))
4107	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4108	else if (!pVCpu->hm.s.Event.fPending)
4109	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
4110
4111	/*
4112	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4113	* Just do it in software, see @bugref{8411}.
4114	* NB: If we could continue a task switch exit we wouldn't need to do this.
4115	*/
4116	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4117	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4118	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4119
4120	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4121	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4122	#endif
4123
4124	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
4125	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
4126	AssertRCReturn(rc, rc);
4127	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
4128
4129	/*
4130	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
4131	* so we can update it on the way back if the guest changed the TPR.
4132	*/
4133	if (pVCpu->hm.s.svm.fSyncVTpr)
4134	{
4135	if (pVM->hm.s.fTPRPatchingActive)
4136	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
4137	else
4138	{
4139	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4140	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4141	}
4142	}
4143
4144	/*
4145	* No longjmps to ring-3 from this point on!!!
4146	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4147	* This also disables flushing of the R0-logger instance (if any).
4148	*/
4149	VMMRZCallRing3Disable(pVCpu);
4150
4151	/*
4152	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4153	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4154	*
4155	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4156	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4157	*
4158	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4159	* executing guest code.
4160	*/
4161	pSvmTransient->fEFlags = ASMIntDisableFlags();
4162	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4163	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4164	{
4165	ASMSetFlags(pSvmTransient->fEFlags);
4166	VMMRZCallRing3Enable(pVCpu);
4167	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4168	return VINF_EM_RAW_TO_R3;
4169	}
4170	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4171	{
4172	ASMSetFlags(pSvmTransient->fEFlags);
4173	VMMRZCallRing3Enable(pVCpu);
4174	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4175	return VINF_EM_RAW_INTERRUPT;
4176	}
4177
4178	/*
4179	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4180	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4181	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4182	*
4183	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4184	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4185	*/
4186	if (pVCpu->hm.s.Event.fPending)
4187	{
4188	SVMEVENT Event;
4189	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4190	if ( Event.n.u1Valid
4191	&& Event.n.u3Type == SVM_EVENT_NMI
4192	&& Event.n.u8Vector == X86_XCPT_NMI
4193	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4194	{
4195	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4196	}
4197	}
4198
4199	return VINF_SUCCESS;
4200	}
4201
4202
4203	#ifdef VBOX_WITH_NESTED_HWVIRT
4204	/**
4205	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
4206	* means there is no backing out to ring-3 or anywhere else at this point.
4207	*
4208	* @param pVM The cross context VM structure.
4209	* @param pVCpu The cross context virtual CPU structure.
4210	* @param pCtx Pointer to the guest-CPU context.
4211	* @param pSvmTransient Pointer to the SVM transient structure.
4212	*
4213	* @remarks Called with preemption disabled.
4214	* @remarks No-long-jump zone!!!
4215	*/
4216	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4217	{
4218	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4219	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4220	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4221	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4222
4223	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4224	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4225
4226	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4227	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
4228
4229	if ( pVCpu->hm.s.fPreloadGuestFpu
4230	&& !CPUMIsGuestFPUStateActive(pVCpu))
4231	{
4232	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4233	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4234	}
4235
4236	/* Load the state shared between host and nested-guest (FPU, debug). */
4237	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4238	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
4239
4240	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4241	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4242
4243	/* Setup TSC offsetting. */
4244	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4245	if ( pSvmTransient->fUpdateTscOffsetting
4246	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4247	{
4248	hmR0SvmUpdateTscOffsettingNested(pVM, pVCpu, pCtx, pVmcbNstGst);
4249	pSvmTransient->fUpdateTscOffsetting = false;
4250	}
4251
4252	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4253	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4254	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4255
4256	/* Store status of the shared guest-host state at the time of VMRUN. */
4257	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4258	if (CPUMIsGuestInLongModeEx(pCtx))
4259	{
4260	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4261	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4262	}
4263	else
4264	#endif
4265	{
4266	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4267	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4268	}
4269	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4270
4271	/* The TLB flushing would've already been setup by the nested-hypervisor. */
4272	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4273	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
4274	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4275
4276	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4277
4278	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4279	to start executing. */
4280
4281	/*
4282	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4283	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4284	*
4285	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4286	*/
4287	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4288	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4289	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4290	{
4291	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4292	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4293	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4294	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4295	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4296	pSvmTransient->fRestoreTscAuxMsr = true;
4297	}
4298	else
4299	{
4300	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4301	pSvmTransient->fRestoreTscAuxMsr = false;
4302	}
4303
4304	/*
4305	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
4306	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
4307	*/
4308	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4309	if (!fSupportsVmcbCleanBits)
4310	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4311	}
4312	#endif
4313
4314
4315	/**
4316	* Prepares to run guest code in AMD-V and we've committed to doing so. This
4317	* means there is no backing out to ring-3 or anywhere else at this
4318	* point.
4319	*
4320	* @param pVM The cross context VM structure.
4321	* @param pVCpu The cross context virtual CPU structure.
4322	* @param pCtx Pointer to the guest-CPU context.
4323	* @param pSvmTransient Pointer to the SVM transient structure.
4324	*
4325	* @remarks Called with preemption disabled.
4326	* @remarks No-long-jump zone!!!
4327	*/
4328	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4329	{
4330	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4331	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4332	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4333	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4334
4335	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4336	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4337
4338	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4339	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
4340
4341	if ( pVCpu->hm.s.fPreloadGuestFpu
4342	&& !CPUMIsGuestFPUStateActive(pVCpu))
4343	{
4344	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4345	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4346	}
4347
4348	/* Load the state shared between host and guest (FPU, debug). */
4349	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4350	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
4351
4352	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4353	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4354
4355	/* Setup TSC offsetting. */
4356	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4357	if ( pSvmTransient->fUpdateTscOffsetting
4358	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4359	{
4360	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
4361	pSvmTransient->fUpdateTscOffsetting = false;
4362	}
4363
4364	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4365	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4366	pVmcb->ctrl.u32VmcbCleanBits = 0;
4367
4368	/* Store status of the shared guest-host state at the time of VMRUN. */
4369	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4370	if (CPUMIsGuestInLongModeEx(pCtx))
4371	{
4372	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4373	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4374	}
4375	else
4376	#endif
4377	{
4378	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4379	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4380	}
4381	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4382
4383	/* Flush the appropriate tagged-TLB entries. */
4384	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4385	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
4386	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4387
4388	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4389
4390	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4391	to start executing. */
4392
4393	/*
4394	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4395	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4396	*
4397	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4398	*/
4399	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4400	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4401	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4402	{
4403	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4404	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4405	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4406	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4407	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4408	pSvmTransient->fRestoreTscAuxMsr = true;
4409	}
4410	else
4411	{
4412	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4413	pSvmTransient->fRestoreTscAuxMsr = false;
4414	}
4415
4416	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4417	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4418	if (!fSupportsVmcbCleanBits)
4419	pVmcb->ctrl.u32VmcbCleanBits = 0;
4420	}
4421
4422
4423	/**
4424	* Wrapper for running the guest code in AMD-V.
4425	*
4426	* @returns VBox strict status code.
4427	* @param pVM The cross context VM structure.
4428	* @param pVCpu The cross context virtual CPU structure.
4429	* @param pCtx Pointer to the guest-CPU context.
4430	*
4431	* @remarks No-long-jump zone!!!
4432	*/
4433	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4434	{
4435	/*
4436	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4437	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4438	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4439	*/
4440	#ifdef VBOX_WITH_KERNEL_USING_XMM
4441	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4442	pVCpu->hm.s.svm.pfnVMRun);
4443	#else
4444	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4445	#endif
4446	}
4447
4448
4449	#ifdef VBOX_WITH_NESTED_HWVIRT
4450	/**
4451	* Wrapper for running the nested-guest code in AMD-V.
4452	*
4453	* @returns VBox strict status code.
4454	* @param pVM The cross context VM structure.
4455	* @param pVCpu The cross context virtual CPU structure.
4456	* @param pCtx Pointer to the guest-CPU context.
4457	*
4458	* @remarks No-long-jump zone!!!
4459	*/
4460	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4461	{
4462	/*
4463	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4464	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4465	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4466	*/
4467	#ifdef VBOX_WITH_KERNEL_USING_XMM
4468	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4469	pVCpu->hm.s.svm.pfnVMRun);
4470	#else
4471	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4472	#endif
4473	}
4474
4475
4476	/**
4477	* Performs some essential restoration of state after running nested-guest code in
4478	* AMD-V.
4479	*
4480	* @param pVM The cross context VM structure.
4481	* @param pVCpu The cross context virtual CPU structure.
4482	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4483	* out-of-sync. Make sure to update the required fields
4484	* before using them.
4485	* @param pSvmTransient Pointer to the SVM transient structure.
4486	* @param rcVMRun Return code of VMRUN.
4487	*
4488	* @remarks Called with interrupts disabled.
4489	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4490	* unconditionally when it is safe to do so.
4491	*/
4492	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4493	{
4494	RT_NOREF(pVM);
4495	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4496
4497	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4498	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4499
4500	/* TSC read must be done early for maximum accuracy. */
4501	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4502	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4503	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4504	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4505	{
4506	/*
4507	* Undo what we did in hmR0SvmUpdateTscOffsettingNested() but don't restore the
4508	* nested-guest VMCB TSC offset here. It shall eventually be restored on #VMEXIT
4509	* later by HMSvmNstGstVmExitNotify().
4510	*/
4511	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset - pVmcbNstGstCache->u64TSCOffset);
4512	}
4513
4514	if (pSvmTransient->fRestoreTscAuxMsr)
4515	{
4516	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4517	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4518	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4519	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4520	}
4521
4522	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4523	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4524	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4525
4526	Assert(!(ASMGetFlags() & X86_EFL_IF));
4527	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4528	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4529
4530	/* Mark the VMCB-state cache as unmodified by VMM. */
4531	pVmcbNstGstCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4532
4533	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4534	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4535	{
4536	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4537	return;
4538	}
4539
4540	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4541	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4542	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4543	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4544
4545	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4546	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4547	guest-CPU context. */
4548	}
4549	#endif
4550
4551	/**
4552	* Performs some essential restoration of state after running guest code in
4553	* AMD-V.
4554	*
4555	* @param pVM The cross context VM structure.
4556	* @param pVCpu The cross context virtual CPU structure.
4557	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4558	* out-of-sync. Make sure to update the required fields
4559	* before using them.
4560	* @param pSvmTransient Pointer to the SVM transient structure.
4561	* @param rcVMRun Return code of VMRUN.
4562	*
4563	* @remarks Called with interrupts disabled.
4564	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4565	* unconditionally when it is safe to do so.
4566	*/
4567	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4568	{
4569	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4570
4571	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4572	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4573
4574	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4575	pVmcb->ctrl.u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4576
4577	/* TSC read must be done early for maximum accuracy. */
4578	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4579	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4580
4581	if (pSvmTransient->fRestoreTscAuxMsr)
4582	{
4583	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4584	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4585	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4586	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4587	}
4588
4589	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4590	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4591	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4592
4593	Assert(!(ASMGetFlags() & X86_EFL_IF));
4594	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4595	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4596
4597	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4598	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4599	{
4600	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4601	return;
4602	}
4603
4604	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4605	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4606	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4607	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4608
4609	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4610
4611	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4612	{
4613	if (pVCpu->hm.s.svm.fSyncVTpr)
4614	{
4615	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4616	if ( pVM->hm.s.fTPRPatchingActive
4617	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4618	{
4619	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4620	AssertRC(rc);
4621	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4622	}
4623	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4624	{
4625	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4626	AssertRC(rc);
4627	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4628	}
4629	}
4630	}
4631	}
4632
4633
4634	/**
4635	* Runs the guest code using AMD-V.
4636	*
4637	* @returns VBox status code.
4638	* @param pVM The cross context VM structure.
4639	* @param pVCpu The cross context virtual CPU structure.
4640	* @param pCtx Pointer to the guest-CPU context.
4641	* @param pcLoops Pointer to the number of executed loops.
4642	*/
4643	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4644	{
4645	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4646	Assert(pcLoops);
4647	Assert(*pcLoops <= cMaxResumeLoops);
4648
4649	SVMTRANSIENT SvmTransient;
4650	SvmTransient.fUpdateTscOffsetting = true;
4651
4652	int rc = VERR_INTERNAL_ERROR_5;
4653	for (;;)
4654	{
4655	Assert(!HMR0SuspendPending());
4656	HMSVM_ASSERT_CPU_SAFE();
4657
4658	/* Preparatory work for running guest code, this may force us to return
4659	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4660	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4661	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4662	if (rc != VINF_SUCCESS)
4663	break;
4664
4665	/*
4666	* No longjmps to ring-3 from this point on!!!
4667	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4668	* This also disables flushing of the R0-logger instance (if any).
4669	*/
4670	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4671	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4672
4673	/* Restore any residual host-state and save any bits shared between host
4674	and guest into the guest-CPU state. Re-enables interrupts! */
4675	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4676
4677	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4678	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4679	{
4680	if (rc == VINF_SUCCESS)
4681	rc = VERR_SVM_INVALID_GUEST_STATE;
4682	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4683	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4684	break;
4685	}
4686
4687	/* Handle the #VMEXIT. */
4688	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4689	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4690	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4691	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4692	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4693	if (rc != VINF_SUCCESS)
4694	break;
4695	if (++(*pcLoops) >= cMaxResumeLoops)
4696	{
4697	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4698	rc = VINF_EM_RAW_INTERRUPT;
4699	break;
4700	}
4701	}
4702
4703	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4704	return rc;
4705	}
4706
4707
4708	/**
4709	* Runs the guest code using AMD-V in single step mode.
4710	*
4711	* @returns VBox status code.
4712	* @param pVM The cross context VM structure.
4713	* @param pVCpu The cross context virtual CPU structure.
4714	* @param pCtx Pointer to the guest-CPU context.
4715	* @param pcLoops Pointer to the number of executed loops.
4716	*/
4717	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4718	{
4719	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4720	Assert(pcLoops);
4721	Assert(*pcLoops <= cMaxResumeLoops);
4722
4723	SVMTRANSIENT SvmTransient;
4724	SvmTransient.fUpdateTscOffsetting = true;
4725
4726	uint16_t uCsStart = pCtx->cs.Sel;
4727	uint64_t uRipStart = pCtx->rip;
4728
4729	int rc = VERR_INTERNAL_ERROR_5;
4730	for (;;)
4731	{
4732	Assert(!HMR0SuspendPending());
4733	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4734	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4735	(unsigned)RTMpCpuId(), *pcLoops));
4736
4737	/* Preparatory work for running guest code, this may force us to return
4738	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4739	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4740	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4741	if (rc != VINF_SUCCESS)
4742	break;
4743
4744	/*
4745	* No longjmps to ring-3 from this point on!!!
4746	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4747	* This also disables flushing of the R0-logger instance (if any).
4748	*/
4749	VMMRZCallRing3Disable(pVCpu);
4750	VMMRZCallRing3RemoveNotification(pVCpu);
4751	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4752
4753	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4754
4755	/*
4756	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4757	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4758	*/
4759	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4760	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4761	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4762	{
4763	if (rc == VINF_SUCCESS)
4764	rc = VERR_SVM_INVALID_GUEST_STATE;
4765	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4766	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4767	return rc;
4768	}
4769
4770	/* Handle the #VMEXIT. */
4771	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4772	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4773	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4774	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4775	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4776	if (rc != VINF_SUCCESS)
4777	break;
4778	if (++(*pcLoops) >= cMaxResumeLoops)
4779	{
4780	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4781	rc = VINF_EM_RAW_INTERRUPT;
4782	break;
4783	}
4784
4785	/*
4786	* Did the RIP change, if so, consider it a single step.
4787	* Otherwise, make sure one of the TFs gets set.
4788	*/
4789	if ( pCtx->rip != uRipStart
4790	\|\| pCtx->cs.Sel != uCsStart)
4791	{
4792	rc = VINF_EM_DBG_STEPPED;
4793	break;
4794	}
4795	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4796	}
4797
4798	/*
4799	* Clear the X86_EFL_TF if necessary.
4800	*/
4801	if (pVCpu->hm.s.fClearTrapFlag)
4802	{
4803	pVCpu->hm.s.fClearTrapFlag = false;
4804	pCtx->eflags.Bits.u1TF = 0;
4805	}
4806
4807	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4808	return rc;
4809	}
4810
4811	#ifdef VBOX_WITH_NESTED_HWVIRT
4812	/**
4813	* Runs the nested-guest code using AMD-V.
4814	*
4815	* @returns VBox status code.
4816	* @param pVM The cross context VM structure.
4817	* @param pVCpu The cross context virtual CPU structure.
4818	* @param pCtx Pointer to the guest-CPU context.
4819	* @param pcLoops Pointer to the number of executed loops. If we're switching
4820	* from the guest-code execution loop to this nested-guest
4821	* execution loop pass the remainder value, else pass 0.
4822	*/
4823	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4824	{
4825	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4826	Assert(pcLoops);
4827	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4828
4829	SVMTRANSIENT SvmTransient;
4830	SvmTransient.fUpdateTscOffsetting = true;
4831
4832	int rc = VERR_INTERNAL_ERROR_4;
4833	for (;;)
4834	{
4835	Assert(!HMR0SuspendPending());
4836	HMSVM_ASSERT_CPU_SAFE();
4837
4838	/* Preparatory work for running nested-guest code, this may force us to return
4839	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4840	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4841	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4842	if ( rc != VINF_SUCCESS
4843	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4844	{
4845	break;
4846	}
4847
4848	/*
4849	* No longjmps to ring-3 from this point on!!!
4850	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4851	* This also disables flushing of the R0-logger instance (if any).
4852	*/
4853	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4854
4855	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4856
4857	/* Restore any residual host-state and save any bits shared between host
4858	and guest into the guest-CPU state. Re-enables interrupts! */
4859	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4860
4861	if (RT_LIKELY( rc == VINF_SUCCESS
4862	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4863	{ /* extremely likely */ }
4864	else
4865	{
4866	/* VMRUN failed, shouldn't really happen, Guru. */
4867	if (rc != VINF_SUCCESS)
4868	break;
4869
4870	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4871	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4872	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4873	break;
4874	}
4875
4876	/* Handle the #VMEXIT. */
4877	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4878	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4879	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4880	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4881	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4882	if (rc != VINF_SUCCESS)
4883	break;
4884	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4885	{
4886	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4887	rc = VINF_EM_RAW_INTERRUPT;
4888	break;
4889	}
4890
4891	/** @todo handle single-stepping */
4892	}
4893
4894	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4895	return rc;
4896	}
4897	#endif
4898
4899
4900	/**
4901	* Runs the guest code using AMD-V.
4902	*
4903	* @returns Strict VBox status code.
4904	* @param pVM The cross context VM structure.
4905	* @param pVCpu The cross context virtual CPU structure.
4906	* @param pCtx Pointer to the guest-CPU context.
4907	*/
4908	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4909	{
4910	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4911	HMSVM_ASSERT_PREEMPT_SAFE();
4912	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4913
4914	uint32_t cLoops = 0;
4915	int rc;
4916	#ifdef VBOX_WITH_NESTED_HWVIRT
4917	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4918	#endif
4919	{
4920	if (!pVCpu->hm.s.fSingleInstruction)
4921	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4922	else
4923	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4924	}
4925	#ifdef VBOX_WITH_NESTED_HWVIRT
4926	else
4927	{
4928	rc = VINF_SVM_VMRUN;
4929	}
4930
4931	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4932	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4933	if (rc == VINF_SVM_VMRUN)
4934	{
4935	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4936	if (rc == VINF_SVM_VMEXIT)
4937	rc = VINF_SUCCESS;
4938	}
4939	#endif
4940
4941	/* Fixup error codes. */
4942	if (rc == VERR_EM_INTERPRETER)
4943	rc = VINF_EM_RAW_EMULATE_INSTR;
4944	else if (rc == VINF_EM_RESET)
4945	rc = VINF_EM_TRIPLE_FAULT;
4946
4947	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4948	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4949	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4950	return rc;
4951	}
4952
4953
4954	#ifdef VBOX_WITH_NESTED_HWVIRT
4955	/**
4956	* Determines whether an IOIO intercept is active for the nested-guest or not.
4957	*
4958	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4959	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4960	*/
4961	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4962	{
4963	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4964	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4965	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4966	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4967	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4968	const bool fRep = pIoExitInfo->n.u1REP;
4969	const bool fStrIo = pIoExitInfo->n.u1STR;
4970
4971	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4972	NULL /* pIoExitInfo */);
4973	}
4974
4975
4976	/**
4977	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4978	* SVM_EXIT_INVALID).
4979	*
4980	* @returns VBox status code (informational status codes included).
4981	* @param pVCpu The cross context virtual CPU structure.
4982	* @param pCtx Pointer to the guest-CPU context.
4983	* @param pSvmTransient Pointer to the SVM transient structure.
4984	*/
4985	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4986	{
4987	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4988	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4989	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4990
4991	#define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4992	VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
4993
4994	/*
4995	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4996	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
4997	*/
4998	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4999	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5000	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5001	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5002	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5003
5004	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5005	switch (uExitCode)
5006	{
5007	case SVM_EXIT_CPUID:
5008	{
5009	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
5010	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5011	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5012	}
5013
5014	case SVM_EXIT_RDTSC:
5015	{
5016	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
5017	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5018	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5019	}
5020
5021	case SVM_EXIT_RDTSCP:
5022	{
5023	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
5024	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5025	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5026	}
5027
5028
5029	case SVM_EXIT_MONITOR:
5030	{
5031	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
5032	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5033	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5034	}
5035
5036	case SVM_EXIT_MWAIT:
5037	{
5038	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
5039	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5040	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5041	}
5042
5043	case SVM_EXIT_HLT:
5044	{
5045	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
5046	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5047	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5048	}
5049
5050	case SVM_EXIT_MSR:
5051	{
5052	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
5053	{
5054	uint32_t const idMsr = pCtx->ecx;
5055	uint16_t offMsrpm;
5056	uint32_t uMsrpmBit;
5057	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5058	if (RT_SUCCESS(rc))
5059	{
5060	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5061	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
5062	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
5063
5064	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5065	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5066	{
5067	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5068	}
5069	}
5070	else
5071	{
5072	/*
5073	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5074	* See AMD-V spec. "15.11 MSR Intercepts".
5075	*/
5076	Assert(rc == VERR_OUT_OF_RANGE);
5077	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5078	}
5079	}
5080	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5081	}
5082
5083	case SVM_EXIT_IOIO:
5084	{
5085	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
5086	{
5087	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
5088	SVMIOIOEXITINFO IoExitInfo;
5089	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5090	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
5091	if (fIntercept)
5092	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5093	}
5094	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5095	}
5096
5097	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5098	{
5099	PVM pVM = pVCpu->CTX_SUFF(pVM);
5100	if (pVM->hm.s.fNestedPaging)
5101	{
5102	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5103	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5104
5105	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5106	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5107	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5108
5109	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
5110	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5111	return VINF_SUCCESS;
5112	}
5113	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
5114	}
5115
5116	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5117	{
5118	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_NM))
5119	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5120	hmR0SvmSetPendingXcptNM(pVCpu);
5121	return VINF_SUCCESS;
5122	}
5123
5124	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5125	{
5126	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
5127	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5128	hmR0SvmSetPendingXcptUD(pVCpu);
5129	return VINF_SUCCESS;
5130	}
5131
5132	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5133	{
5134	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
5135	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5136	hmR0SvmSetPendingXcptMF(pVCpu);
5137	return VINF_SUCCESS;
5138	}
5139
5140	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5141	{
5142	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5143	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5144	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
5145	}
5146
5147	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5148	{
5149	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5150	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5151	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5152	}
5153
5154	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5155	{
5156	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5157	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5158	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
5159	}
5160
5161	case SVM_EXIT_READ_CR0:
5162	case SVM_EXIT_READ_CR3:
5163	case SVM_EXIT_READ_CR4:
5164	{
5165	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5166	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5167	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5168	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5169	}
5170
5171	case SVM_EXIT_WRITE_CR0:
5172	case SVM_EXIT_WRITE_CR3:
5173	case SVM_EXIT_WRITE_CR4:
5174	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
5175	{
5176	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5177	Log4(("hmR0SvmHandleExitNested: Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5178
5179	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5180	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5181	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5182	}
5183
5184	case SVM_EXIT_PAUSE:
5185	{
5186	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5187	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5188	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5189	}
5190
5191	case SVM_EXIT_VINTR:
5192	{
5193	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5194	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5195	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5196	}
5197
5198	case SVM_EXIT_INTR:
5199	case SVM_EXIT_NMI:
5200	case SVM_EXIT_SMI:
5201	{
5202	/*
5203	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5204	*
5205	* Although we don't intercept SMIs, the nested-guest might. Therefore, we
5206	* might get an SMI #VMEXIT here so simply ignore rather than causing a
5207	* corresponding nested-guest #VMEXIT.
5208	*/
5209	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5210	}
5211
5212	case SVM_EXIT_FERR_FREEZE:
5213	{
5214	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5215	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5216	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5217	}
5218
5219	case SVM_EXIT_INVLPG:
5220	{
5221	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5222	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5223	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5224	}
5225
5226	case SVM_EXIT_WBINVD:
5227	{
5228	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5229	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5230	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5231	}
5232
5233	case SVM_EXIT_INVD:
5234	{
5235	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5236	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5237	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5238	}
5239
5240	case SVM_EXIT_RDPMC:
5241	{
5242	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5243	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5244	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5245	}
5246
5247	default:
5248	{
5249	switch (uExitCode)
5250	{
5251	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5252	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5253	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5254	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5255	{
5256	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5257	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5258	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5259	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5260	}
5261
5262	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5263	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5264	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5265	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5266	{
5267	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5268	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5269	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5270	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5271	}
5272
5273	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
5274	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
5275	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
5276	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
5277	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
5278	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
5279	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
5280	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
5281	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
5282	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
5283	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
5284	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5285	{
5286	uint8_t const uVector = uExitCode - SVM_EXIT_EXCEPTION_0;
5287	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5288	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5289	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5290	}
5291
5292	case SVM_EXIT_XSETBV:
5293	{
5294	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5295	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5296	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5297	}
5298
5299	case SVM_EXIT_TASK_SWITCH:
5300	{
5301	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5302	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5303	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5304	}
5305
5306	case SVM_EXIT_IRET:
5307	{
5308	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5309	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5310	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5311	}
5312
5313	case SVM_EXIT_SHUTDOWN:
5314	{
5315	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5316	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5317	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5318	}
5319
5320	case SVM_EXIT_VMMCALL:
5321	{
5322	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5323	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5324	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5325	}
5326
5327	case SVM_EXIT_CLGI:
5328	{
5329	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5330	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5331	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5332	}
5333
5334	case SVM_EXIT_STGI:
5335	{
5336	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5337	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5338	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5339	}
5340
5341	case SVM_EXIT_VMLOAD:
5342	{
5343	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5344	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5345	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5346	}
5347
5348	case SVM_EXIT_VMSAVE:
5349	{
5350	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5351	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5352	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5353	}
5354
5355	case SVM_EXIT_INVLPGA:
5356	{
5357	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5358	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5359	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5360	}
5361
5362	case SVM_EXIT_VMRUN:
5363	{
5364	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5365	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5366	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5367	}
5368
5369	case SVM_EXIT_RSM:
5370	{
5371	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5372	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5373	hmR0SvmSetPendingXcptUD(pVCpu);
5374	return VINF_SUCCESS;
5375	}
5376
5377	case SVM_EXIT_SKINIT:
5378	{
5379	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5380	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5381	hmR0SvmSetPendingXcptUD(pVCpu);
5382	return VINF_SUCCESS;
5383	}
5384
5385	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5386	case SVM_EXIT_NPF: /* We don't yet support nested-paging for nested-guests, so this should never happen. */
5387	{
5388	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5389	}
5390
5391	default:
5392	{
5393	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5394	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5395	return VERR_SVM_UNKNOWN_EXIT;
5396	}
5397	}
5398	}
5399	}
5400	/* not reached */
5401
5402	#undef HM_SVM_VMEXIT_NESTED
5403	}
5404	#endif
5405
5406
5407	/**
5408	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5409	*
5410	* @returns VBox status code (informational status codes included).
5411	* @param pVCpu The cross context virtual CPU structure.
5412	* @param pCtx Pointer to the guest-CPU context.
5413	* @param pSvmTransient Pointer to the SVM transient structure.
5414	*/
5415	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5416	{
5417	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5418	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5419
5420	/*
5421	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5422	* normal workloads (for some definition of "normal").
5423	*/
5424	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5425	switch (uExitCode)
5426	{
5427	case SVM_EXIT_NPF:
5428	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5429
5430	case SVM_EXIT_IOIO:
5431	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5432
5433	case SVM_EXIT_RDTSC:
5434	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5435
5436	case SVM_EXIT_RDTSCP:
5437	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5438
5439	case SVM_EXIT_CPUID:
5440	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5441
5442	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5443	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5444
5445	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5446	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5447
5448	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5449	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5450
5451	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5452	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5453
5454	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5455	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5456
5457	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5458	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5459
5460	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5461	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5462
5463	case SVM_EXIT_MONITOR:
5464	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5465
5466	case SVM_EXIT_MWAIT:
5467	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5468
5469	case SVM_EXIT_HLT:
5470	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5471
5472	case SVM_EXIT_READ_CR0:
5473	case SVM_EXIT_READ_CR3:
5474	case SVM_EXIT_READ_CR4:
5475	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5476
5477	case SVM_EXIT_WRITE_CR0:
5478	case SVM_EXIT_WRITE_CR3:
5479	case SVM_EXIT_WRITE_CR4:
5480	case SVM_EXIT_WRITE_CR8:
5481	{
5482	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5483	Log4(("hmR0SvmHandleExitNested: Write CR%u\n", uCr)); NOREF(uCr);
5484	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5485	}
5486
5487	case SVM_EXIT_PAUSE:
5488	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5489
5490	case SVM_EXIT_VMMCALL:
5491	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5492
5493	case SVM_EXIT_VINTR:
5494	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5495
5496	case SVM_EXIT_INTR:
5497	case SVM_EXIT_FERR_FREEZE:
5498	case SVM_EXIT_NMI:
5499	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5500
5501	case SVM_EXIT_MSR:
5502	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5503
5504	case SVM_EXIT_INVLPG:
5505	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5506
5507	case SVM_EXIT_WBINVD:
5508	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5509
5510	case SVM_EXIT_INVD:
5511	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5512
5513	case SVM_EXIT_RDPMC:
5514	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5515
5516	default:
5517	{
5518	switch (pSvmTransient->u64ExitCode)
5519	{
5520	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5521	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5522	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5523	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5524	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5525
5526	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5527	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5528	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5529	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5530	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5531
5532	case SVM_EXIT_XSETBV:
5533	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5534
5535	case SVM_EXIT_TASK_SWITCH:
5536	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5537
5538	case SVM_EXIT_IRET:
5539	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5540
5541	case SVM_EXIT_SHUTDOWN:
5542	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5543
5544	case SVM_EXIT_SMI:
5545	case SVM_EXIT_INIT:
5546	{
5547	/*
5548	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5549	* If it ever does, we want to know about it so log the exit code and bail.
5550	*/
5551	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5552	}
5553
5554	#ifdef VBOX_WITH_NESTED_HWVIRT
5555	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5556	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5557	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5558	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5559	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5560	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5561	#else
5562	case SVM_EXIT_CLGI:
5563	case SVM_EXIT_STGI:
5564	case SVM_EXIT_VMLOAD:
5565	case SVM_EXIT_VMSAVE:
5566	case SVM_EXIT_INVLPGA:
5567	case SVM_EXIT_VMRUN:
5568	#endif
5569	case SVM_EXIT_RSM:
5570	case SVM_EXIT_SKINIT:
5571	{
5572	hmR0SvmSetPendingXcptUD(pVCpu);
5573	return VINF_SUCCESS;
5574	}
5575
5576	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5577	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5578	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5579	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5580	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5581	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5582	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5583	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5584	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5585	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5586	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5587	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5588	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5589	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5590	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5591	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5592	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5593	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5594	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5595	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5596	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5597	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5598	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5599	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5600	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5601	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5602	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5603
5604	default:
5605	{
5606	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5607	pVCpu->hm.s.u32HMError = uExitCode;
5608	return VERR_SVM_UNKNOWN_EXIT;
5609	}
5610	}
5611	}
5612	}
5613	/* not reached */
5614	}
5615
5616
5617	#ifdef DEBUG
5618	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5619	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5620	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5621
5622	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5623	do \
5624	{ \
5625	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5626	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5627	} while (0)
5628
5629	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5630	do { \
5631	AssertPtr(pVCpu); \
5632	AssertPtr(pCtx); \
5633	AssertPtr(pSvmTransient); \
5634	Assert(ASMIntAreEnabled()); \
5635	HMSVM_ASSERT_PREEMPT_SAFE(); \
5636	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5637	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5638	HMSVM_ASSERT_PREEMPT_SAFE(); \
5639	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5640	HMSVM_ASSERT_PREEMPT_CPUID(); \
5641	} while (0)
5642	#else /* Release builds */
5643	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5644	#endif
5645
5646
5647	/**
5648	* Worker for hmR0SvmInterpretInvlpg().
5649	*
5650	* @return VBox status code.
5651	* @param pVCpu The cross context virtual CPU structure.
5652	* @param pCpu Pointer to the disassembler state.
5653	* @param pCtx The guest CPU context.
5654	*/
5655	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5656	{
5657	DISQPVPARAMVAL Param1;
5658	RTGCPTR GCPtrPage;
5659
5660	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5661	if (RT_FAILURE(rc))
5662	return VERR_EM_INTERPRETER;
5663
5664	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5665	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5666	{
5667	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5668	return VERR_EM_INTERPRETER;
5669
5670	GCPtrPage = Param1.val.val64;
5671	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5672	rc = VBOXSTRICTRC_VAL(rc2);
5673	}
5674	else
5675	{
5676	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5677	rc = VERR_EM_INTERPRETER;
5678	}
5679
5680	return rc;
5681	}
5682
5683
5684	/**
5685	* Interprets INVLPG.
5686	*
5687	* @returns VBox status code.
5688	* @retval VINF_* Scheduling instructions.
5689	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5690	* @retval VERR_* Fatal errors.
5691	*
5692	* @param pVM The cross context VM structure.
5693	* @param pVCpu The cross context virtual CPU structure.
5694	* @param pCtx The guest CPU context.
5695	*
5696	* @remarks Updates the RIP if the instruction was executed successfully.
5697	*/
5698	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5699	{
5700	/* Only allow 32 & 64 bit code. */
5701	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5702	{
5703	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5704	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5705	if ( RT_SUCCESS(rc)
5706	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5707	{
5708	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5709	if (RT_SUCCESS(rc))
5710	pCtx->rip += pDis->cbInstr;
5711	return rc;
5712	}
5713	else
5714	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5715	}
5716	return VERR_EM_INTERPRETER;
5717	}
5718
5719
5720	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5721	/**
5722	* Gets the IEM exception flags for the specified SVM event.
5723	*
5724	* @returns The IEM exception flags.
5725	* @param pEvent Pointer to the SVM event.
5726	*
5727	* @remarks This function currently only constructs flags required for
5728	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5729	* and CR2 aspects of an exception are not included).
5730	*/
5731	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5732	{
5733	uint8_t const uEventType = pEvent->n.u3Type;
5734	uint32_t fIemXcptFlags;
5735	switch (uEventType)
5736	{
5737	case SVM_EVENT_EXCEPTION:
5738	/*
5739	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5740	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5741	*/
5742	if (pEvent->n.u8Vector == X86_XCPT_BP)
5743	{
5744	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5745	break;
5746	}
5747	if (pEvent->n.u8Vector == X86_XCPT_OF)
5748	{
5749	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5750	break;
5751	}
5752	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5753	RT_FALL_THRU();
5754	case SVM_EVENT_NMI:
5755	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5756	break;
5757
5758	case SVM_EVENT_EXTERNAL_IRQ:
5759	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5760	break;
5761
5762	case SVM_EVENT_SOFTWARE_INT:
5763	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5764	break;
5765
5766	default:
5767	fIemXcptFlags = 0;
5768	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5769	break;
5770	}
5771	return fIemXcptFlags;
5772	}
5773
5774	#else
5775	/**
5776	* Determines if an exception is a contributory exception.
5777	*
5778	* Contributory exceptions are ones which can cause double-faults unless the
5779	* original exception was a benign exception. Page-fault is intentionally not
5780	* included here as it's a conditional contributory exception.
5781	*
5782	* @returns @c true if the exception is contributory, @c false otherwise.
5783	* @param uVector The exception vector.
5784	*/
5785	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5786	{
5787	switch (uVector)
5788	{
5789	case X86_XCPT_GP:
5790	case X86_XCPT_SS:
5791	case X86_XCPT_NP:
5792	case X86_XCPT_TS:
5793	case X86_XCPT_DE:
5794	return true;
5795	default:
5796	break;
5797	}
5798	return false;
5799	}
5800	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5801
5802
5803	/**
5804	* Handle a condition that occurred while delivering an event through the guest
5805	* IDT.
5806	*
5807	* @returns VBox status code (informational error codes included).
5808	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5809	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5810	* continue execution of the guest which will delivery the \#DF.
5811	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5812	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5813	*
5814	* @param pVCpu The cross context virtual CPU structure.
5815	* @param pCtx Pointer to the guest-CPU context.
5816	* @param pSvmTransient Pointer to the SVM transient structure.
5817	*
5818	* @remarks No-long-jump zone!!!
5819	*/
5820	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5821	{
5822	int rc = VINF_SUCCESS;
5823	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5824
5825	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5826	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5827	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5828
5829	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5830	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5831	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5832	{
5833	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5834	IEMXCPTRAISE enmRaise;
5835	IEMXCPTRAISEINFO fRaiseInfo;
5836	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5837	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5838	if (fExitIsHwXcpt)
5839	{
5840	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5841	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5842	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5843	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5844	}
5845	else
5846	{
5847	/*
5848	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5849	* end up here.
5850	*
5851	* If the event was:
5852	* - a software interrupt, we can re-execute the instruction which will regenerate
5853	* the event.
5854	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5855	* - a hardware exception or external interrupt, we re-inject it.
5856	*/
5857	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5858	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5859	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5860	else
5861	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5862	}
5863
5864	switch (enmRaise)
5865	{
5866	case IEMXCPTRAISE_CURRENT_XCPT:
5867	case IEMXCPTRAISE_PREV_EVENT:
5868	{
5869	/* For software interrupts, we shall re-execute the instruction. */
5870	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5871	{
5872	RTGCUINTPTR GCPtrFaultAddress = 0;
5873
5874	/* If we are re-injecting an NMI, clear NMI blocking. */
5875	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5876	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5877
5878	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5879	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5880	pSvmTransient->fVectoringPF = true;
5881	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5882	&& uIdtVector == X86_XCPT_PF)
5883	{
5884	/*
5885	* If the previous exception was a #PF, we need to recover the CR2 value.
5886	* This can't happen with shadow paging.
5887	*/
5888	GCPtrFaultAddress = pCtx->cr2;
5889	}
5890
5891	/*
5892	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5893	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5894	*/
5895	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5896	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5897	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5898
5899	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5900	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5901	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5902	}
5903	break;
5904	}
5905
5906	case IEMXCPTRAISE_REEXEC_INSTR:
5907	{
5908	Assert(rc == VINF_SUCCESS);
5909	break;
5910	}
5911
5912	case IEMXCPTRAISE_DOUBLE_FAULT:
5913	{
5914	/*
5915	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5916	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5917	*/
5918	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5919	{
5920	pSvmTransient->fVectoringDoublePF = true;
5921	Assert(rc == VINF_SUCCESS);
5922	}
5923	else
5924	{
5925	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5926	hmR0SvmSetPendingXcptDF(pVCpu);
5927	rc = VINF_HM_DOUBLE_FAULT;
5928	}
5929	break;
5930	}
5931
5932	case IEMXCPTRAISE_TRIPLE_FAULT:
5933	{
5934	rc = VINF_EM_RESET;
5935	break;
5936	}
5937
5938	case IEMXCPTRAISE_CPU_HANG:
5939	{
5940	rc = VERR_EM_GUEST_CPU_HANG;
5941	break;
5942	}
5943
5944	default:
5945	{
5946	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5947	rc = VERR_SVM_IPE_2;
5948	break;
5949	}
5950	}
5951	#else
5952	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5953
5954	typedef enum
5955	{
5956	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5957	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5958	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5959	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5960	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5961	} SVMREFLECTXCPT;
5962
5963	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5964	bool fReflectingNmi = false;
5965	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5966	{
5967	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5968	{
5969	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5970
5971	#ifdef VBOX_STRICT
5972	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5973	&& uExitVector == X86_XCPT_PF)
5974	{
5975	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5976	}
5977	#endif
5978
5979	if ( uIdtVector == X86_XCPT_BP
5980	\|\| uIdtVector == X86_XCPT_OF)
5981	{
5982	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5983	}
5984	else if ( uExitVector == X86_XCPT_PF
5985	&& uIdtVector == X86_XCPT_PF)
5986	{
5987	pSvmTransient->fVectoringDoublePF = true;
5988	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
5989	}
5990	else if ( uExitVector == X86_XCPT_AC
5991	&& uIdtVector == X86_XCPT_AC)
5992	{
5993	enmReflect = SVMREFLECTXCPT_HANG;
5994	Log4(("IDT: Nested #AC - Bad guest\n"));
5995	}
5996	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
5997	&& hmR0SvmIsContributoryXcpt(uExitVector)
5998	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
5999	\|\| uIdtVector == X86_XCPT_PF))
6000	{
6001	enmReflect = SVMREFLECTXCPT_DF;
6002	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
6003	uIdtVector, uExitVector));
6004	}
6005	else if (uIdtVector == X86_XCPT_DF)
6006	{
6007	enmReflect = SVMREFLECTXCPT_TF;
6008	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
6009	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
6010	}
6011	else
6012	enmReflect = SVMREFLECTXCPT_XCPT;
6013	}
6014	else
6015	{
6016	/*
6017	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
6018	* exception to the guest after handling the #VMEXIT.
6019	*/
6020	enmReflect = SVMREFLECTXCPT_XCPT;
6021	}
6022	}
6023	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
6024	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
6025	{
6026	enmReflect = SVMREFLECTXCPT_XCPT;
6027	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
6028
6029	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
6030	{
6031	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
6032	if (uExitVector == X86_XCPT_PF)
6033	{
6034	pSvmTransient->fVectoringPF = true;
6035	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
6036	}
6037	}
6038	}
6039	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
6040
6041	switch (enmReflect)
6042	{
6043	case SVMREFLECTXCPT_XCPT:
6044	{
6045	/* If we are re-injecting the NMI, clear NMI blocking. */
6046	if (fReflectingNmi)
6047	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6048
6049	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
6050	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6051	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
6052
6053	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
6054	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
6055	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
6056	break;
6057	}
6058
6059	case SVMREFLECTXCPT_DF:
6060	{
6061	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6062	hmR0SvmSetPendingXcptDF(pVCpu);
6063	rc = VINF_HM_DOUBLE_FAULT;
6064	break;
6065	}
6066
6067	case SVMREFLECTXCPT_TF:
6068	{
6069	rc = VINF_EM_RESET;
6070	break;
6071	}
6072
6073	case SVMREFLECTXCPT_HANG:
6074	{
6075	rc = VERR_EM_GUEST_CPU_HANG;
6076	break;
6077	}
6078
6079	default:
6080	Assert(rc == VINF_SUCCESS);
6081	break;
6082	}
6083	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
6084	}
6085	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6086	NOREF(pCtx);
6087	return rc;
6088	}
6089
6090
6091	/**
6092	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
6093	* supported, otherwise advances the RIP by the number of bytes specified in
6094	* @a cb.
6095	*
6096	* @param pVCpu The cross context virtual CPU structure.
6097	* @param pCtx Pointer to the guest-CPU context.
6098	* @param cb RIP increment value in bytes.
6099	*
6100	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
6101	* when NRIP_SAVE is supported by the CPU, otherwise use
6102	* hmR0SvmAdvanceRipDumb!
6103	*/
6104	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6105	{
6106	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6107	if (fSupportsNextRipSave)
6108	{
6109	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6110	Assert(pVmcb->ctrl.u64NextRIP);
6111	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
6112	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6113	}
6114	else
6115	pCtx->rip += cb;
6116
6117	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6118	}
6119
6120
6121	#ifdef VBOX_WITH_NESTED_HWVIRT
6122	/**
6123	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
6124	* feature. Otherwise, returns the value in @a cbLikely.
6125	*
6126	* @param pVCpu The cross context virtual CPU structure.
6127	* @param pCtx Pointer to the guest-CPU context.
6128	* @param cbLikely The likely instruction length.
6129	*/
6130	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
6131	{
6132	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
6133	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6134	if (fSupportsNextRipSave)
6135	{
6136	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6137	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6138	Assert(cbInstr == cbLikely);
6139	return cbInstr;
6140	}
6141	return cbLikely;
6142	}
6143	#endif
6144
6145
6146	/**
6147	* Advances the guest RIP by the number of bytes specified in @a cb. This does
6148	* not make use of any hardware features to determine the instruction length.
6149	*
6150	* @param pVCpu The cross context virtual CPU structure.
6151	* @param pCtx Pointer to the guest-CPU context.
6152	* @param cb RIP increment value in bytes.
6153	*/
6154	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6155	{
6156	pCtx->rip += cb;
6157	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6158	}
6159	#undef HMSVM_UPDATE_INTR_SHADOW
6160
6161
6162	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6163	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6164	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6165
6166	/** @name \#VMEXIT handlers.
6167	* @{
6168	*/
6169
6170	/**
6171	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6172	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6173	*/
6174	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6175	{
6176	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6177
6178	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6179	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6180	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6181	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6182
6183	/*
6184	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
6185	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
6186	* interrupt it is until the host actually take the interrupt.
6187	*
6188	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
6189	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6190	*/
6191	return VINF_EM_RAW_INTERRUPT;
6192	}
6193
6194
6195	/**
6196	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6197	*/
6198	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6199	{
6200	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6201
6202	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6203	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
6204	int rc = VINF_SUCCESS;
6205	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6206	return rc;
6207	}
6208
6209
6210	/**
6211	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6212	*/
6213	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6214	{
6215	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6216
6217	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6218	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
6219	int rc = VINF_SUCCESS;
6220	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6221	return rc;
6222	}
6223
6224
6225	/**
6226	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6227	*/
6228	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6229	{
6230	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6231	PVM pVM = pVCpu->CTX_SUFF(pVM);
6232	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6233	if (RT_LIKELY(rc == VINF_SUCCESS))
6234	{
6235	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6236	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6237	}
6238	else
6239	{
6240	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6241	rc = VERR_EM_INTERPRETER;
6242	}
6243	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
6244	return rc;
6245	}
6246
6247
6248	/**
6249	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6250	*/
6251	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6252	{
6253	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6254	PVM pVM = pVCpu->CTX_SUFF(pVM);
6255	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6256	if (RT_LIKELY(rc == VINF_SUCCESS))
6257	{
6258	pSvmTransient->fUpdateTscOffsetting = true;
6259	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6260	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6261	}
6262	else
6263	{
6264	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
6265	rc = VERR_EM_INTERPRETER;
6266	}
6267	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
6268	return rc;
6269	}
6270
6271
6272	/**
6273	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6274	*/
6275	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6276	{
6277	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6278	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
6279	if (RT_LIKELY(rc == VINF_SUCCESS))
6280	{
6281	pSvmTransient->fUpdateTscOffsetting = true;
6282	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6283	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6284	}
6285	else
6286	{
6287	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
6288	rc = VERR_EM_INTERPRETER;
6289	}
6290	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
6291	return rc;
6292	}
6293
6294
6295	/**
6296	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6297	*/
6298	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6299	{
6300	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6301	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6302	if (RT_LIKELY(rc == VINF_SUCCESS))
6303	{
6304	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6305	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6306	}
6307	else
6308	{
6309	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6310	rc = VERR_EM_INTERPRETER;
6311	}
6312	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6313	return rc;
6314	}
6315
6316
6317	/**
6318	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6319	*/
6320	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6321	{
6322	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6323	PVM pVM = pVCpu->CTX_SUFF(pVM);
6324	Assert(!pVM->hm.s.fNestedPaging);
6325	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6326
6327	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6328	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6329	if ( fSupportsDecodeAssists
6330	&& fSupportsNextRipSave)
6331	{
6332	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6333	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6334	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6335	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6336	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6337	return VBOXSTRICTRC_VAL(rcStrict);
6338	}
6339
6340	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6341	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6342	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6343	return rc;
6344	}
6345
6346
6347	/**
6348	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6349	*/
6350	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6351	{
6352	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6353
6354	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6355	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6356	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6357	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6358	if (rc != VINF_SUCCESS)
6359	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6360	return rc;
6361	}
6362
6363
6364	/**
6365	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6366	*/
6367	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6368	{
6369	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6370	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6371	if (RT_LIKELY(rc == VINF_SUCCESS))
6372	{
6373	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6374	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6375	}
6376	else
6377	{
6378	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6379	rc = VERR_EM_INTERPRETER;
6380	}
6381	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6382	return rc;
6383	}
6384
6385
6386	/**
6387	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6388	*/
6389	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6390	{
6391	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6392	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6393	int rc = VBOXSTRICTRC_VAL(rc2);
6394	if ( rc == VINF_EM_HALT
6395	\|\| rc == VINF_SUCCESS)
6396	{
6397	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6398
6399	if ( rc == VINF_EM_HALT
6400	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6401	{
6402	rc = VINF_SUCCESS;
6403	}
6404	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6405	}
6406	else
6407	{
6408	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6409	rc = VERR_EM_INTERPRETER;
6410	}
6411	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6412	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6413	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6414	return rc;
6415	}
6416
6417
6418	/**
6419	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6420	* \#VMEXIT.
6421	*/
6422	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6423	{
6424	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6425	return VINF_EM_RESET;
6426	}
6427
6428
6429	/**
6430	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6431	*/
6432	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6433	{
6434	RT_NOREF(pCtx);
6435	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64\n", pSvmTransient->u64ExitCode));
6436	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6437	return VERR_SVM_UNEXPECTED_EXIT;
6438	}
6439
6440
6441	/**
6442	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6443	*/
6444	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6445	{
6446	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6447
6448	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6449	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6450
6451	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6452	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6453	if ( fSupportsDecodeAssists
6454	&& fSupportsNextRipSave)
6455	{
6456	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6457	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6458	if (fMovCRx)
6459	{
6460	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6461	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6462	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6463	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6464	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6465	return VBOXSTRICTRC_VAL(rcStrict);
6466	}
6467	/* else: SMSW instruction, fall back below to IEM for this. */
6468	}
6469
6470	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6471	int rc = VBOXSTRICTRC_VAL(rc2);
6472	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6473	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6474	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6475	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6476	return rc;
6477	}
6478
6479
6480	/**
6481	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6482	*/
6483	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6484	{
6485	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6486
6487	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6488	Assert(iCrReg <= 15);
6489
6490	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6491	bool fDecodedInstr = false;
6492	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6493	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6494	if ( fSupportsDecodeAssists
6495	&& fSupportsNextRipSave)
6496	{
6497	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6498	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6499	if (fMovCRx)
6500	{
6501	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6502	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6503	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6504	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6505	fDecodedInstr = true;
6506	}
6507	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6508	}
6509
6510	if (!fDecodedInstr)
6511	{
6512	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6513	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6514	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6515	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6516	rcStrict = VERR_EM_INTERPRETER;
6517	}
6518
6519	if (rcStrict == VINF_SUCCESS)
6520	{
6521	switch (iCrReg)
6522	{
6523	case 0: /* CR0. */
6524	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6525	break;
6526
6527	case 3: /* CR3. */
6528	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6529	break;
6530
6531	case 4: /* CR4. */
6532	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6533	break;
6534
6535	case 8: /* CR8 (TPR). */
6536	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6537	break;
6538
6539	default:
6540	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6541	pSvmTransient->u64ExitCode, iCrReg));
6542	break;
6543	}
6544	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6545	}
6546	else
6547	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6548	return VBOXSTRICTRC_TODO(rcStrict);
6549	}
6550
6551
6552	/**
6553	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6554	* \#VMEXIT.
6555	*/
6556	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6557	{
6558	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6559	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6560	PVM pVM = pVCpu->CTX_SUFF(pVM);
6561
6562	int rc;
6563	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6564	{
6565	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6566	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6567
6568	/* Handle TPR patching; intercepted LSTAR write. */
6569	if ( pVM->hm.s.fTPRPatchingActive
6570	&& pCtx->ecx == MSR_K8_LSTAR)
6571	{
6572	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6573	{
6574	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6575	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6576	AssertRC(rc2);
6577	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6578	}
6579	rc = VINF_SUCCESS;
6580	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6581	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6582	return rc;
6583	}
6584
6585	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6586	if (fSupportsNextRipSave)
6587	{
6588	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6589	if (RT_LIKELY(rc == VINF_SUCCESS))
6590	{
6591	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6592	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6593	}
6594	else
6595	AssertMsg( rc == VERR_EM_INTERPRETER
6596	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6597	}
6598	else
6599	{
6600	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6601	if (RT_LIKELY(rc == VINF_SUCCESS))
6602	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6603	else
6604	AssertMsg( rc == VERR_EM_INTERPRETER
6605	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6606	}
6607
6608	if (rc == VINF_SUCCESS)
6609	{
6610	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6611	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6612	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6613	{
6614	/*
6615	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6616	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6617	* EMInterpretWrmsr() changes it.
6618	*/
6619	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6620	}
6621	else
6622	{
6623	switch (pCtx->ecx)
6624	{
6625	case MSR_K6_EFER: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR); break;
6626	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6627	case MSR_K8_FS_BASE:
6628	case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
6629	case MSR_IA32_SYSENTER_CS: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6630	case MSR_IA32_SYSENTER_EIP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6631	case MSR_IA32_SYSENTER_ESP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6632	}
6633	}
6634	}
6635	}
6636	else
6637	{
6638	/* MSR Read access. */
6639	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6640	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6641	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6642
6643	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6644	if (fSupportsNextRipSave)
6645	{
6646	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6647	if (RT_LIKELY(rc == VINF_SUCCESS))
6648	{
6649	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6650	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6651	}
6652	else
6653	AssertMsg( rc == VERR_EM_INTERPRETER
6654	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6655	}
6656	else
6657	{
6658	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6659	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6660	{
6661	AssertMsg( rc == VERR_EM_INTERPRETER
6662	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6663	}
6664	/* RIP updated by EMInterpretInstruction(). */
6665	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6666	}
6667	}
6668
6669	/* RIP has been updated by EMInterpret[Rd\|Wr]msr() or EMInterpretInstruction(). */
6670	return rc;
6671	}
6672
6673
6674	/**
6675	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6676	*/
6677	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6678	{
6679	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6680	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6681
6682	/** @todo Stepping with nested-guest. */
6683	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6684	{
6685	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6686	if (pSvmTransient->fWasGuestDebugStateActive)
6687	{
6688	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6689	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6690	return VERR_SVM_UNEXPECTED_EXIT;
6691	}
6692
6693	/*
6694	* Lazy DR0-3 loading.
6695	*/
6696	if (!pSvmTransient->fWasHyperDebugStateActive)
6697	{
6698	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6699	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6700
6701	/* Don't intercept DRx read and writes. */
6702	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6703	pVmcb->ctrl.u16InterceptRdDRx = 0;
6704	pVmcb->ctrl.u16InterceptWrDRx = 0;
6705	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6706
6707	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6708	VMMRZCallRing3Disable(pVCpu);
6709	HM_DISABLE_PREEMPT();
6710
6711	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6712	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6713	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6714
6715	HM_RESTORE_PREEMPT();
6716	VMMRZCallRing3Enable(pVCpu);
6717
6718	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6719	return VINF_SUCCESS;
6720	}
6721	}
6722
6723	/*
6724	* Interpret the read/writing of DRx.
6725	*/
6726	/** @todo Decode assist. */
6727	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6728	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6729	if (RT_LIKELY(rc == VINF_SUCCESS))
6730	{
6731	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6732	/** @todo CPUM should set this flag! */
6733	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6734	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6735	}
6736	else
6737	Assert(rc == VERR_EM_INTERPRETER);
6738	return VBOXSTRICTRC_TODO(rc);
6739	}
6740
6741
6742	/**
6743	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6744	*/
6745	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6746	{
6747	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6748	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6749	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6750	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6751	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6752	return rc;
6753	}
6754
6755
6756	/**
6757	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6758	*/
6759	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6760	{
6761	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6762
6763	/** @todo decode assists... */
6764	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6765	if (rcStrict == VINF_IEM_RAISED_XCPT)
6766	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6767
6768	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6769	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6770	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6771
6772	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6773	return VBOXSTRICTRC_TODO(rcStrict);
6774	}
6775
6776
6777	/**
6778	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6779	*/
6780	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6781	{
6782	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6783
6784	/* I/O operation lookup arrays. */
6785	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6786	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6787	the result (in AL/AX/EAX). */
6788	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6789
6790	PVM pVM = pVCpu->CTX_SUFF(pVM);
6791	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6792
6793	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6794	SVMIOIOEXITINFO IoExitInfo;
6795	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6796	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6797	uint32_t cbValue = s_aIOSize[uIOWidth];
6798	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6799
6800	if (RT_UNLIKELY(!cbValue))
6801	{
6802	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6803	return VERR_EM_INTERPRETER;
6804	}
6805
6806	VBOXSTRICTRC rcStrict;
6807	bool fUpdateRipAlready = false;
6808	if (IoExitInfo.n.u1STR)
6809	{
6810	#ifdef VBOX_WITH_2ND_IEM_STEP
6811	/* INS/OUTS - I/O String instruction. */
6812	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6813	* in EXITINFO1? Investigate once this thing is up and running. */
6814	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6815	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6816	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6817	static IEMMODE const s_aenmAddrMode[8] =
6818	{
6819	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6820	};
6821	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6822	if (enmAddrMode != (IEMMODE)-1)
6823	{
6824	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6825	if (cbInstr <= 15 && cbInstr >= 1)
6826	{
6827	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6828	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6829	{
6830	/* Don't know exactly how to detect whether u3SEG is valid, currently
6831	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6832	2384 Opterons when only checking NRIP. */
6833	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6834	if ( fSupportsNextRipSave
6835	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6836	{
6837	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6838	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6839	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6840	IoExitInfo.n.u3SEG, true /fIoChecked/);
6841	}
6842	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6843	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6844	X86_SREG_DS, true /fIoChecked/);
6845	else
6846	rcStrict = IEMExecOne(pVCpu);
6847	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6848	}
6849	else
6850	{
6851	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6852	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6853	true /fIoChecked/);
6854	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6855	}
6856	}
6857	else
6858	{
6859	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6860	rcStrict = IEMExecOne(pVCpu);
6861	}
6862	}
6863	else
6864	{
6865	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6866	rcStrict = IEMExecOne(pVCpu);
6867	}
6868	fUpdateRipAlready = true;
6869
6870	#else
6871	/* INS/OUTS - I/O String instruction. */
6872	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6873
6874	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6875	* in EXITINFO1? Investigate once this thing is up and running. */
6876
6877	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6878	if (rcStrict == VINF_SUCCESS)
6879	{
6880	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6881	{
6882	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6883	(DISCPUMODE)pDis->uAddrMode, cbValue);
6884	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6885	}
6886	else
6887	{
6888	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6889	(DISCPUMODE)pDis->uAddrMode, cbValue);
6890	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6891	}
6892	}
6893	else
6894	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6895	#endif
6896	}
6897	else
6898	{
6899	/* IN/OUT - I/O instruction. */
6900	Assert(!IoExitInfo.n.u1REP);
6901
6902	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6903	{
6904	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6905	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6906	}
6907	else
6908	{
6909	uint32_t u32Val = 0;
6910	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6911	if (IOM_SUCCESS(rcStrict))
6912	{
6913	/* Save result of I/O IN instr. in AL/AX/EAX. */
6914	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6915	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6916	}
6917	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6918	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6919
6920	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6921	}
6922	}
6923
6924	if (IOM_SUCCESS(rcStrict))
6925	{
6926	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6927	if (!fUpdateRipAlready)
6928	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6929
6930	/*
6931	* If any I/O breakpoints are armed, we need to check if one triggered
6932	* and take appropriate action.
6933	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6934	*/
6935	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6936	* execution engines about whether hyper BPs and such are pending. */
6937	uint32_t const uDr7 = pCtx->dr[7];
6938	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6939	&& X86_DR7_ANY_RW_IO(uDr7)
6940	&& (pCtx->cr4 & X86_CR4_DE))
6941	\|\| DBGFBpIsHwIoArmed(pVM)))
6942	{
6943	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6944	VMMRZCallRing3Disable(pVCpu);
6945	HM_DISABLE_PREEMPT();
6946
6947	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6948	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6949
6950	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6951	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6952	{
6953	/* Raise #DB. */
6954	pVmcb->guest.u64DR6 = pCtx->dr[6];
6955	pVmcb->guest.u64DR7 = pCtx->dr[7];
6956	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6957	hmR0SvmSetPendingXcptDB(pVCpu);
6958	}
6959	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6960	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6961	else if ( rcStrict2 != VINF_SUCCESS
6962	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6963	rcStrict = rcStrict2;
6964	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6965
6966	HM_RESTORE_PREEMPT();
6967	VMMRZCallRing3Enable(pVCpu);
6968	}
6969
6970	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6971	}
6972
6973	#ifdef VBOX_STRICT
6974	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6975	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6976	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6977	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6978	else
6979	{
6980	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6981	* statuses, that the VMM device and some others may return. See
6982	* IOM_SUCCESS() for guidance. */
6983	AssertMsg( RT_FAILURE(rcStrict)
6984	\|\| rcStrict == VINF_SUCCESS
6985	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6986	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6987	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6988	\|\| rcStrict == VINF_EM_RAW_TO_R3
6989	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6990	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6991	}
6992	#endif
6993	return VBOXSTRICTRC_TODO(rcStrict);
6994	}
6995
6996
6997	/**
6998	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6999	*/
7000	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7001	{
7002	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7003	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7004
7005	PVM pVM = pVCpu->CTX_SUFF(pVM);
7006	Assert(pVM->hm.s.fNestedPaging);
7007
7008	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7009
7010	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7011	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7012	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7013	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7014
7015	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
7016
7017	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7018	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
7019	if ( pVM->hm.s.fTprPatchingAllowed
7020	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7021	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7022	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7023	&& !CPUMIsGuestInLongModeEx(pCtx)
7024	&& !CPUMGetGuestCPL(pVCpu)
7025	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7026	{
7027	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7028	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7029
7030	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7031	{
7032	/* Only attempt to patch the instruction once. */
7033	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7034	if (!pPatch)
7035	return VINF_EM_HM_PATCH_TPR_INSTR;
7036	}
7037	}
7038	#endif
7039
7040	/*
7041	* Determine the nested paging mode.
7042	*/
7043	PGMMODE enmNestedPagingMode;
7044	#if HC_ARCH_BITS == 32
7045	if (CPUMIsGuestInLongModeEx(pCtx))
7046	enmNestedPagingMode = PGMMODE_AMD64_NX;
7047	else
7048	#endif
7049	enmNestedPagingMode = PGMGetHostMode(pVM);
7050
7051	/*
7052	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7053	*/
7054	int rc;
7055	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7056	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7057	{
7058	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
7059	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
7060	if (pVCpu->hm.s.Event.fPending)
7061	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7062
7063	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7064	u32ErrCode);
7065	rc = VBOXSTRICTRC_VAL(rc2);
7066
7067	/*
7068	* If we succeed, resume guest execution.
7069	* If we fail in interpreting the instruction because we couldn't get the guest physical address
7070	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
7071	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
7072	* weird case. See @bugref{6043}.
7073	*/
7074	if ( rc == VINF_SUCCESS
7075	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7076	\|\| rc == VERR_PAGE_NOT_PRESENT)
7077	{
7078	/* Successfully handled MMIO operation. */
7079	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
7080	rc = VINF_SUCCESS;
7081	}
7082	return rc;
7083	}
7084
7085	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7086	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7087	TRPMResetTrap(pVCpu);
7088
7089	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7090
7091	/*
7092	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7093	*/
7094	if ( rc == VINF_SUCCESS
7095	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7096	\|\| rc == VERR_PAGE_NOT_PRESENT)
7097	{
7098	/* We've successfully synced our shadow page tables. */
7099	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7100	rc = VINF_SUCCESS;
7101	}
7102
7103	return rc;
7104	}
7105
7106
7107	/**
7108	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7109	* \#VMEXIT.
7110	*/
7111	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7112	{
7113	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7114	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7115
7116	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7117	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7118	hmR0SvmClearVirtIntrIntercept(pVmcb);
7119
7120	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7121	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7122	return VINF_SUCCESS;
7123	}
7124
7125
7126	/**
7127	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7128	* \#VMEXIT.
7129	*/
7130	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7131	{
7132	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7133
7134	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7135
7136	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7137	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7138	#endif
7139
7140	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7141	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7142	{
7143	/*
7144	* AMD-V provides us with the exception which caused the TS; we collect
7145	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
7146	*/
7147	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
7148	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7149	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7150	}
7151
7152	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7153	* emulation. */
7154	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7155	return VERR_EM_INTERPRETER;
7156	}
7157
7158
7159	/**
7160	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7161	*/
7162	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7163	{
7164	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7165	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
7166
7167	bool fRipUpdated;
7168	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
7169	if (RT_SUCCESS(rcStrict))
7170	{
7171	/* Only update the RIP if we're continuing guest execution and not
7172	in the case of say VINF_GIM_R3_HYPERCALL. */
7173	if ( rcStrict == VINF_SUCCESS
7174	&& !fRipUpdated)
7175	{
7176	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
7177	}
7178
7179	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
7180	we would need to reload the guest changed bits here before VM-entry. */
7181	return VBOXSTRICTRC_VAL(rcStrict);
7182	}
7183
7184	hmR0SvmSetPendingXcptUD(pVCpu);
7185	return VINF_SUCCESS;
7186	}
7187
7188
7189	/**
7190	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7191	*/
7192	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7193	{
7194	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7195	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
7196	return VINF_EM_RAW_INTERRUPT;
7197	}
7198
7199
7200	/**
7201	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7202	*/
7203	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7204	{
7205	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7206
7207	/* Clear NMI blocking. */
7208	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7209
7210	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7211	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7212	hmR0SvmClearIretIntercept(pVmcb);
7213
7214	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7215	return VINF_SUCCESS;
7216	}
7217
7218
7219	/**
7220	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
7221	* Conditional \#VMEXIT.
7222	*/
7223	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7224	{
7225	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7226	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7227
7228	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7229
7230	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7231	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7232	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7233	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7234	PVM pVM = pVCpu->CTX_SUFF(pVM);
7235
7236	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7237	if (pVM->hm.s.fNestedPaging)
7238	{
7239	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7240	if (!pSvmTransient->fVectoringDoublePF)
7241	{
7242	/* A genuine guest #PF, reflect it to the guest. */
7243	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7244	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7245	uFaultAddress, u32ErrCode));
7246	}
7247	else
7248	{
7249	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7250	hmR0SvmSetPendingXcptDF(pVCpu);
7251	Log4(("Pending #DF due to vectoring #PF. NP\n"));
7252	}
7253	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7254	return VINF_SUCCESS;
7255	}
7256	#endif
7257
7258	Assert(!pVM->hm.s.fNestedPaging);
7259
7260	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7261	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
7262	if ( pVM->hm.s.fTprPatchingAllowed
7263	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7264	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
7265	&& !CPUMIsGuestInLongModeEx(pCtx)
7266	&& !CPUMGetGuestCPL(pVCpu)
7267	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7268	{
7269	RTGCPHYS GCPhysApicBase;
7270	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7271	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7272
7273	/* Check if the page at the fault-address is the APIC base. */
7274	RTGCPHYS GCPhysPage;
7275	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7276	if ( rc2 == VINF_SUCCESS
7277	&& GCPhysPage == GCPhysApicBase)
7278	{
7279	/* Only attempt to patch the instruction once. */
7280	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7281	if (!pPatch)
7282	return VINF_EM_HM_PATCH_TPR_INSTR;
7283	}
7284	}
7285	#endif
7286
7287	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7288	pCtx->rip, u32ErrCode, pCtx->cr3));
7289
7290	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7291	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7292	if (pSvmTransient->fVectoringPF)
7293	{
7294	Assert(pVCpu->hm.s.Event.fPending);
7295	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7296	}
7297
7298	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7299	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7300
7301	Log4(("#PF rc=%Rrc\n", rc));
7302
7303	if (rc == VINF_SUCCESS)
7304	{
7305	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7306	TRPMResetTrap(pVCpu);
7307	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7308	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7309	return rc;
7310	}
7311	else if (rc == VINF_EM_RAW_GUEST_TRAP)
7312	{
7313	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7314
7315	if (!pSvmTransient->fVectoringDoublePF)
7316	{
7317	/* It's a guest page fault and needs to be reflected to the guest. */
7318	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7319	TRPMResetTrap(pVCpu);
7320	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7321	}
7322	else
7323	{
7324	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7325	TRPMResetTrap(pVCpu);
7326	hmR0SvmSetPendingXcptDF(pVCpu);
7327	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7328	}
7329
7330	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7331	return VINF_SUCCESS;
7332	}
7333
7334	TRPMResetTrap(pVCpu);
7335	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7336	return rc;
7337	}
7338
7339
7340	/**
7341	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
7342	* Conditional \#VMEXIT.
7343	*/
7344	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7345	{
7346	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7347
7348	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7349	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7350	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7351
7352	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7353	VMMRZCallRing3Disable(pVCpu);
7354	HM_DISABLE_PREEMPT();
7355
7356	int rc;
7357	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7358	if (pSvmTransient->fWasGuestFPUStateActive)
7359	{
7360	rc = VINF_EM_RAW_GUEST_TRAP;
7361	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7362	}
7363	else
7364	{
7365	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7366	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7367	#endif
7368	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7369	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7370	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7371	}
7372
7373	HM_RESTORE_PREEMPT();
7374	VMMRZCallRing3Enable(pVCpu);
7375
7376	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7377	{
7378	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7379	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7380	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7381	pVCpu->hm.s.fPreloadGuestFpu = true;
7382	}
7383	else
7384	{
7385	/* Forward #NM to the guest. */
7386	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7387	hmR0SvmSetPendingXcptNM(pVCpu);
7388	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7389	}
7390	return VINF_SUCCESS;
7391	}
7392
7393
7394	/**
7395	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7396	* Conditional \#VMEXIT.
7397	*/
7398	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7399	{
7400	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7401
7402	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7403	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7404	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7405
7406	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7407	if (pVCpu->hm.s.fGIMTrapXcptUD)
7408	{
7409	uint8_t cbInstr = 0;
7410	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7411	if (rcStrict == VINF_SUCCESS)
7412	{
7413	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7414	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7415	rc = VINF_SUCCESS;
7416	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7417	}
7418	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7419	rc = VINF_SUCCESS;
7420	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7421	rc = VINF_GIM_R3_HYPERCALL;
7422	else
7423	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7424	}
7425
7426	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7427	if (RT_FAILURE(rc))
7428	{
7429	hmR0SvmSetPendingXcptUD(pVCpu);
7430	rc = VINF_SUCCESS;
7431	}
7432
7433	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7434	return rc;
7435	}
7436
7437
7438	/**
7439	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7440	* Conditional \#VMEXIT.
7441	*/
7442	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7443	{
7444	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7445
7446	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7447	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7448	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7449
7450	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7451
7452	if (!(pCtx->cr0 & X86_CR0_NE))
7453	{
7454	PVM pVM = pVCpu->CTX_SUFF(pVM);
7455	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7456	unsigned cbOp;
7457	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7458	if (RT_SUCCESS(rc))
7459	{
7460	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7461	/** @todo FERR intercept when in nested-guest mode? */
7462	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7463	if (RT_SUCCESS(rc))
7464	pCtx->rip += cbOp;
7465	}
7466	else
7467	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7468	return rc;
7469	}
7470
7471	hmR0SvmSetPendingXcptMF(pVCpu);
7472	return VINF_SUCCESS;
7473	}
7474
7475
7476	/**
7477	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7478	* \#VMEXIT.
7479	*/
7480	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7481	{
7482	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7483
7484	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7485	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7486	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7487	{
7488	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7489	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7490	}
7491
7492	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7493
7494	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7495	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7496	PVM pVM = pVCpu->CTX_SUFF(pVM);
7497	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7498	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7499	if (rc == VINF_EM_RAW_GUEST_TRAP)
7500	{
7501	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7502	if (CPUMIsHyperDebugStateActive(pVCpu))
7503	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7504
7505	/* Reflect the exception back to the guest. */
7506	hmR0SvmSetPendingXcptDB(pVCpu);
7507	rc = VINF_SUCCESS;
7508	}
7509
7510	/*
7511	* Update DR6.
7512	*/
7513	if (CPUMIsHyperDebugStateActive(pVCpu))
7514	{
7515	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7516	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7517	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7518	}
7519	else
7520	{
7521	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7522	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7523	}
7524
7525	return rc;
7526	}
7527
7528
7529	/**
7530	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7531	* Conditional \#VMEXIT.
7532	*/
7533	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7534	{
7535	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7536
7537	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7538	* shutdown VMEXIT. */
7539	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7540
7541	SVMEVENT Event;
7542	Event.u = 0;
7543	Event.n.u1Valid = 1;
7544	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7545	Event.n.u8Vector = X86_XCPT_AC;
7546	Event.n.u1ErrorCodeValid = 1;
7547	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7548	return VINF_SUCCESS;
7549	}
7550
7551
7552	/**
7553	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7554	* Conditional \#VMEXIT.
7555	*/
7556	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7557	{
7558	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7559
7560	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7561
7562	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7563	if (rc == VINF_EM_RAW_GUEST_TRAP)
7564	{
7565	SVMEVENT Event;
7566	Event.u = 0;
7567	Event.n.u1Valid = 1;
7568	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7569	Event.n.u8Vector = X86_XCPT_BP;
7570	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7571	}
7572
7573	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7574	return rc;
7575	}
7576
7577
7578	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
7579	/**
7580	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7581	*/
7582	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7583	{
7584	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7585
7586	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7587
7588	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7589	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_EXCEPTION_0;
7590	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7591	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7592	Assert(uVector <= X86_XCPT_LAST);
7593	Log4(("hmR0SvmExitXcptGeneric: uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7594
7595	SVMEVENT Event;
7596	Event.u = 0;
7597	Event.n.u1Valid = 1;
7598	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7599	Event.n.u8Vector = uVector;
7600	switch (uVector)
7601	{
7602	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7603	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7604	case X86_XCPT_DF:
7605	case X86_XCPT_TS:
7606	case X86_XCPT_NP:
7607	case X86_XCPT_SS:
7608	case X86_XCPT_GP:
7609	case X86_XCPT_AC:
7610	{
7611	Event.n.u1ErrorCodeValid = 1;
7612	Event.n.u32ErrorCode = uErrCode;
7613	break;
7614	}
7615	}
7616
7617	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7618	return VINF_SUCCESS;
7619	}
7620	#endif
7621
7622	#ifdef VBOX_WITH_NESTED_HWVIRT
7623	/**
7624	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7625	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7626	*/
7627	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7628	{
7629	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7630
7631	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7632
7633	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7634	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7635	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7636	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7637
7638	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7639	pCtx->rip, u32ErrCode, pCtx->cr3));
7640
7641	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7642	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7643	if (pSvmTransient->fVectoringPF)
7644	{
7645	Assert(pVCpu->hm.s.Event.fPending);
7646	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7647	}
7648
7649	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7650
7651	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7652	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7653
7654	Log4(("#PFNested: rc=%Rrc\n", rc));
7655
7656	if (rc == VINF_SUCCESS)
7657	{
7658	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7659	TRPMResetTrap(pVCpu);
7660	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7661	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7662	return rc;
7663	}
7664
7665	if (rc == VINF_EM_RAW_GUEST_TRAP)
7666	{
7667	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7668
7669	if (!pSvmTransient->fVectoringDoublePF)
7670	{
7671	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7672	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7673	TRPMResetTrap(pVCpu);
7674	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7675	}
7676	else
7677	{
7678	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7679	TRPMResetTrap(pVCpu);
7680	hmR0SvmSetPendingXcptDF(pVCpu);
7681	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7682	}
7683
7684	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7685	return VINF_SUCCESS;
7686	}
7687
7688	TRPMResetTrap(pVCpu);
7689	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7690	return rc;
7691	}
7692
7693
7694	/**
7695	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7696	*/
7697	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7698	{
7699	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7700
7701	#ifdef VBOX_STRICT
7702	PCSVMVMCB pVmcbTmp = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7703	Assert(pVmcbTmp);
7704	Assert(!pVmcbTmp->ctrl.IntCtrl.n.u1VGifEnable);
7705	RT_NOREF(pVmcbTmp);
7706	#endif
7707
7708	/** @todo Stat. */
7709	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7710	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7711	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7712	return VBOXSTRICTRC_VAL(rcStrict);
7713	}
7714
7715
7716	/**
7717	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7718	*/
7719	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7720	{
7721	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7722
7723	#ifdef VBOX_STRICT
7724	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7725	Assert(pVmcb);
7726	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7727	RT_NOREF(pVmcb);
7728	#endif
7729
7730	/** @todo Stat. */
7731	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7732	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7733	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7734	return VBOXSTRICTRC_VAL(rcStrict);
7735	}
7736
7737
7738	/**
7739	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7740	*/
7741	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7742	{
7743	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7744
7745	#ifdef VBOX_STRICT
7746	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7747	Assert(pVmcb);
7748	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7749	RT_NOREF(pVmcb);
7750	#endif
7751
7752	/** @todo Stat. */
7753	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7754	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7755	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7756	if (rcStrict == VINF_SUCCESS)
7757	{
7758	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7759	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7760	\| HM_CHANGED_GUEST_TR
7761	\| HM_CHANGED_GUEST_LDTR);
7762	}
7763	return VBOXSTRICTRC_VAL(rcStrict);
7764	}
7765
7766
7767	/**
7768	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7769	*/
7770	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7771	{
7772	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7773
7774	#ifdef VBOX_STRICT
7775	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7776	Assert(pVmcb);
7777	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7778	RT_NOREF(pVmcb);
7779	#endif
7780
7781	/** @todo Stat. */
7782	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7783	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7784	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7785	return VBOXSTRICTRC_VAL(rcStrict);
7786	}
7787
7788
7789	/**
7790	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7791	*/
7792	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7793	{
7794	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7795	/** @todo Stat. */
7796	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7797	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7798	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7799	return VBOXSTRICTRC_VAL(rcStrict);
7800	}
7801
7802
7803	/**
7804	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7805	*/
7806	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7807	{
7808	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7809	/** @todo Stat. */
7810	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7811	#if 0
7812	VBOXSTRICTRC rcStrict;
7813	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7814	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7815	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7816	if (rcStrict == VINF_SUCCESS)
7817	{
7818	rcStrict = VINF_SVM_VMRUN;
7819	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7820	}
7821	return VBOXSTRICTRC_VAL(rcStrict);
7822	#endif
7823	return VERR_EM_INTERPRETER;
7824	}
7825
7826
7827	/**
7828	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7829	* Unconditional \#VMEXIT.
7830	*/
7831	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7832	{
7833	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7834
7835	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7836	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7837	* shutdown VMEXIT. */
7838	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7839	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7840	{
7841	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7842	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7843	}
7844
7845	hmR0SvmSetPendingXcptDB(pVCpu);
7846	return VINF_SUCCESS;
7847	}
7848
7849
7850	/**
7851	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7852	* Conditional \#VMEXIT.
7853	*/
7854	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7855	{
7856	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7857
7858	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7859	* shutdown VMEXIT. */
7860	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7861
7862	SVMEVENT Event;
7863	Event.u = 0;
7864	Event.n.u1Valid = 1;
7865	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7866	Event.n.u8Vector = X86_XCPT_BP;
7867	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7868	return VINF_SUCCESS;
7869	}
7870
7871	#endif /* VBOX_WITH_NESTED_HWVIRT */
7872
7873
7874	/** @} */
7875

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 70703

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