HMSVMR0.cpp@ 71927

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1	/* $Id: HMSVMR0.cpp 71927 2018-04-20 04:18:24Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#define HMSVM_USE_IEM_EVENT_REFLECTION
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_SYNC_FULL_NESTED_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	if ((u64ExitCode) == SVM_EXIT_NPF) \
65	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
66	else \
67	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
68	} while (0)
69	# endif
70	#else
71	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
72	# ifdef VBOX_WITH_NESTED_HWVIRT
73	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
74	# endif
75	#endif /* !VBOX_WITH_STATISTICS */
76
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static int
81
82	/** Macro for checking and returning from the using function for
83	* \#VMEXIT intercepts that maybe caused during delivering of another
84	* event in the guest. */
85	#ifdef VBOX_WITH_NESTED_HWVIRT
86	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
87	do \
88	{ \
89	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
90	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
91	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
92	else if ( rc == VINF_EM_RESET \
93	&& HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
94	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_SHUTDOWN, 0, 0)); \
95	else \
96	return rc; \
97	} while (0)
98	#else
99	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
100	do \
101	{ \
102	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
103	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
104	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
105	else \
106	return rc; \
107	} while (0)
108	#endif
109
110	/**
111	* Updates interrupt shadow for the current RIP.
112	*/
113	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
114	do { \
115	/* Update interrupt shadow. */ \
116	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
117	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
118	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
119	} while (0)
120
121	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
122	* instruction that exited. */
123	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
124	do { \
125	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
126	(a_rc) = VINF_EM_DBG_STEPPED; \
127	} while (0)
128
129	/** Assert that preemption is disabled or covered by thread-context hooks. */
130	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
131	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
132
133	/** Assert that we haven't migrated CPUs when thread-context hooks are not
134	* used. */
135	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
136	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
137	("Illegal migration! Entered on CPU %u Current %u\n", \
138	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
139
140	/** Assert that we're not executing a nested-guest. */
141	#ifdef VBOX_WITH_NESTED_HWVIRT
142	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
143	#else
144	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
145	#endif
146
147	/** Assert that we're executing a nested-guest. */
148	#ifdef VBOX_WITH_NESTED_HWVIRT
149	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
150	#else
151	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
152	#endif
153
154	/** Validate segment descriptor granularity bit. */
155	#ifdef VBOX_STRICT
156	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
157	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
158	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
159	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
160	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
161	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
162	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
163	#else
164	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) do { } while (0)
165	#endif
166
167	/**
168	* Exception bitmap mask for all contributory exceptions.
169	*
170	* Page fault is deliberately excluded here as it's conditional as to whether
171	* it's contributory or benign. Page faults are handled separately.
172	*/
173	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
174	\| RT_BIT(X86_XCPT_DE))
175
176	/**
177	* Mandatory/unconditional guest control intercepts.
178	*
179	* SMIs can and do happen in normal operation. We need not intercept them
180	* while executing the guest (or nested-guest).
181	*/
182	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
183	\| SVM_CTRL_INTERCEPT_NMI \
184	\| SVM_CTRL_INTERCEPT_INIT \
185	\| SVM_CTRL_INTERCEPT_RDPMC \
186	\| SVM_CTRL_INTERCEPT_CPUID \
187	\| SVM_CTRL_INTERCEPT_RSM \
188	\| SVM_CTRL_INTERCEPT_HLT \
189	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
190	\| SVM_CTRL_INTERCEPT_MSR_PROT \
191	\| SVM_CTRL_INTERCEPT_INVLPGA \
192	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
193	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
194	\| SVM_CTRL_INTERCEPT_VMRUN \
195	\| SVM_CTRL_INTERCEPT_SKINIT \
196	\| SVM_CTRL_INTERCEPT_WBINVD \
197	\| SVM_CTRL_INTERCEPT_MONITOR \
198	\| SVM_CTRL_INTERCEPT_MWAIT \
199	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
200	\| SVM_CTRL_INTERCEPT_XSETBV)
201
202	/** @name VMCB Clean Bits.
203	*
204	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
205	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
206	* memory.
207	*
208	* @{ */
209	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
210	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
211	/** I/O permission bitmap, MSR permission bitmap. */
212	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
213	/** ASID. */
214	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
215	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
216	V_INTR_VECTOR. */
217	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
218	/** Nested Paging: Nested CR3 (nCR3), PAT. */
219	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
220	/** Control registers (CR0, CR3, CR4, EFER). */
221	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
222	/** Debug registers (DR6, DR7). */
223	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
224	/** GDT, IDT limit and base. */
225	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
226	/** Segment register: CS, SS, DS, ES limit and base. */
227	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
228	/** CR2.*/
229	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
230	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
231	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
232	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
233	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
234	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
235	/** Mask of all valid VMCB Clean bits. */
236	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
237	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
238	\| HMSVM_VMCB_CLEAN_ASID \
239	\| HMSVM_VMCB_CLEAN_TPR \
240	\| HMSVM_VMCB_CLEAN_NP \
241	\| HMSVM_VMCB_CLEAN_CRX_EFER \
242	\| HMSVM_VMCB_CLEAN_DRX \
243	\| HMSVM_VMCB_CLEAN_DT \
244	\| HMSVM_VMCB_CLEAN_SEG \
245	\| HMSVM_VMCB_CLEAN_CR2 \
246	\| HMSVM_VMCB_CLEAN_LBR \
247	\| HMSVM_VMCB_CLEAN_AVIC)
248	/** @} */
249
250	/** @name SVM transient.
251	*
252	* A state structure for holding miscellaneous information across AMD-V
253	* VMRUN/\#VMEXIT operation, restored after the transition.
254	*
255	* @{ */
256	typedef struct SVMTRANSIENT
257	{
258	/** The host's rflags/eflags. */
259	RTCCUINTREG fEFlags;
260	#if HC_ARCH_BITS == 32
261	uint32_t u32Alignment0;
262	#endif
263
264	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
265	uint64_t u64ExitCode;
266	/** The guest's TPR value used for TPR shadowing. */
267	uint8_t u8GuestTpr;
268	/** Alignment. */
269	uint8_t abAlignment0[7];
270
271	/** Pointer to the currently executing VMCB. */
272	PSVMVMCB pVmcb;
273	/** Whether we are currently executing a nested-guest. */
274	bool fIsNestedGuest;
275
276	/** Whether the guest debug state was active at the time of \#VMEXIT. */
277	bool fWasGuestDebugStateActive;
278	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
279	bool fWasHyperDebugStateActive;
280	/** Whether the TSC offset mode needs to be updated. */
281	bool fUpdateTscOffsetting;
282	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
283	bool fRestoreTscAuxMsr;
284	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
285	* contributary exception or a page-fault. */
286	bool fVectoringDoublePF;
287	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
288	* external interrupt or NMI. */
289	bool fVectoringPF;
290	} SVMTRANSIENT, *PSVMTRANSIENT;
291	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
292	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
293	/** @} */
294
295	/**
296	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
297	*/
298	typedef enum SVMMSREXITREAD
299	{
300	/** Reading this MSR causes a \#VMEXIT. */
301	SVMMSREXIT_INTERCEPT_READ = 0xb,
302	/** Reading this MSR does not cause a \#VMEXIT. */
303	SVMMSREXIT_PASSTHRU_READ
304	} SVMMSREXITREAD;
305
306	/**
307	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
308	*/
309	typedef enum SVMMSREXITWRITE
310	{
311	/** Writing to this MSR causes a \#VMEXIT. */
312	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
313	/** Writing to this MSR does not cause a \#VMEXIT. */
314	SVMMSREXIT_PASSTHRU_WRITE
315	} SVMMSREXITWRITE;
316
317	/**
318	* SVM \#VMEXIT handler.
319	*
320	* @returns VBox status code.
321	* @param pVCpu The cross context virtual CPU structure.
322	* @param pMixedCtx Pointer to the guest-CPU context.
323	* @param pSvmTransient Pointer to the SVM-transient structure.
324	*/
325	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
326
327
328	/*********************************************************************************************************************************
329	* Internal Functions *
330	*********************************************************************************************************************************/
331	static void hmR0SvmSetMsrPermission(PCPUMCTX pCtx, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
332	SVMMSREXITWRITE enmWrite);
333	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
334	static void hmR0SvmLeave(PVMCPU pVCpu);
335
336	/** @name \#VMEXIT handlers.
337	* @{
338	*/
339	static FNSVMEXITHANDLER hmR0SvmExitIntr;
340	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
341	static FNSVMEXITHANDLER hmR0SvmExitInvd;
342	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
343	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
344	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
345	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
346	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
347	static FNSVMEXITHANDLER hmR0SvmExitHlt;
348	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
349	static FNSVMEXITHANDLER hmR0SvmExitMwait;
350	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
351	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
352	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
353	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
354	static FNSVMEXITHANDLER hmR0SvmExitMsr;
355	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
356	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
357	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
358	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
359	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
360	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
361	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
362	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
363	static FNSVMEXITHANDLER hmR0SvmExitPause;
364	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
365	static FNSVMEXITHANDLER hmR0SvmExitIret;
366	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
367	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
368	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
369	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
370	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
371	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
372	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
373	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
374	#endif
375	#ifdef VBOX_WITH_NESTED_HWVIRT
376	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
377	static FNSVMEXITHANDLER hmR0SvmExitClgi;
378	static FNSVMEXITHANDLER hmR0SvmExitStgi;
379	static FNSVMEXITHANDLER hmR0SvmExitVmload;
380	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
381	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
382	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
383	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
384	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
385	#endif
386	/** @} */
387
388	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
389	#ifdef VBOX_WITH_NESTED_HWVIRT
390	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
391	#endif
392
393
394	/*********************************************************************************************************************************
395	* Global Variables *
396	*********************************************************************************************************************************/
397	/** Ring-0 memory object for the IO bitmap. */
398	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
399	/** Physical address of the IO bitmap. */
400	static RTHCPHYS g_HCPhysIOBitmap;
401	/** Pointer to the IO bitmap. */
402	static R0PTRTYPE(void *) g_pvIOBitmap;
403
404	#ifdef VBOX_STRICT
405	# define HMSVM_LOG_CS RT_BIT_32(0)
406	# define HMSVM_LOG_SS RT_BIT_32(1)
407	# define HMSVM_LOG_FS RT_BIT_32(2)
408	# define HMSVM_LOG_GS RT_BIT_32(3)
409	# define HMSVM_LOG_LBR RT_BIT_32(4)
410	# define HMSVM_LOG_ALL ( HMSVM_LOG_CS \
411	\| HMSVM_LOG_SS \
412	\| HMSVM_LOG_FS \
413	\| HMSVM_LOG_GS \
414	\| HMSVM_LOG_LBR)
415
416	/**
417	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
418	*
419	* @param pVCpu The cross context virtual CPU structure.
420	* @param pVmcb Pointer to the VM control block.
421	* @param pCtx Pointer to the guest-CPU context.
422	* @param pszPrefix Log prefix.
423	* @param fFlags Log flags, see HMSVM_LOG_XXX.
424	* @param uVerbose The verbosity level, currently unused.
425	*/
426	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, PCPUMCTX pCtx, const char *pszPrefix, uint32_t fFlags,
427	uint8_t uVerbose)
428	{
429	RT_NOREF2(pVCpu, uVerbose);
430
431	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip,
432	pCtx->rflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
433	Log4(("%s: rsp=%#RX64 rbp=%#RX64 rdi=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp, pCtx->rdi));
434	if (fFlags & HMSVM_LOG_CS)
435	{
436	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
437	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
438	}
439	if (fFlags & HMSVM_LOG_SS)
440	{
441	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
442	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
443	}
444	if (fFlags & HMSVM_LOG_FS)
445	{
446	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
447	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
448	}
449	if (fFlags & HMSVM_LOG_GS)
450	{
451	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
452	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
453	}
454
455	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
456	if (fFlags & HMSVM_LOG_LBR)
457	{
458	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
459	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
460	}
461	NOREF(pVmcbGuest);
462	}
463	#endif /* VBOX_STRICT */
464
465
466	/**
467	* Sets up and activates AMD-V on the current CPU.
468	*
469	* @returns VBox status code.
470	* @param pCpu Pointer to the CPU info struct.
471	* @param pVM The cross context VM structure. Can be
472	* NULL after a resume!
473	* @param pvCpuPage Pointer to the global CPU page.
474	* @param HCPhysCpuPage Physical address of the global CPU page.
475	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
476	* @param pvArg Unused on AMD-V.
477	*/
478	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
479	void *pvArg)
480	{
481	Assert(!fEnabledByHost);
482	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
483	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
484	Assert(pvCpuPage); NOREF(pvCpuPage);
485	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
486
487	NOREF(pvArg);
488	NOREF(fEnabledByHost);
489
490	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
491	RTCCUINTREG fEFlags = ASMIntDisableFlags();
492
493	/*
494	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
495	*/
496	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
497	if (u64HostEfer & MSR_K6_EFER_SVME)
498	{
499	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
500	if ( pVM
501	&& pVM->hm.s.svm.fIgnoreInUseError)
502	{
503	pCpu->fIgnoreAMDVInUseError = true;
504	}
505
506	if (!pCpu->fIgnoreAMDVInUseError)
507	{
508	ASMSetFlags(fEFlags);
509	return VERR_SVM_IN_USE;
510	}
511	}
512
513	/* Turn on AMD-V in the EFER MSR. */
514	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
515
516	/* Write the physical page address where the CPU will store the host state while executing the VM. */
517	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
518
519	/* Restore interrupts. */
520	ASMSetFlags(fEFlags);
521
522	/*
523	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
524	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
525	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
526	* guest code.
527	*/
528	pCpu->fFlushAsidBeforeUse = true;
529
530	/*
531	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
532	*/
533	++pCpu->cTlbFlushes;
534
535	return VINF_SUCCESS;
536	}
537
538
539	/**
540	* Deactivates AMD-V on the current CPU.
541	*
542	* @returns VBox status code.
543	* @param pCpu Pointer to the CPU info struct.
544	* @param pvCpuPage Pointer to the global CPU page.
545	* @param HCPhysCpuPage Physical address of the global CPU page.
546	*/
547	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
548	{
549	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
550	AssertReturn( HCPhysCpuPage
551	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
552	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
553	NOREF(pCpu);
554
555	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
556	RTCCUINTREG fEFlags = ASMIntDisableFlags();
557
558	/* Turn off AMD-V in the EFER MSR. */
559	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
560	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
561
562	/* Invalidate host state physical address. */
563	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
564
565	/* Restore interrupts. */
566	ASMSetFlags(fEFlags);
567
568	return VINF_SUCCESS;
569	}
570
571
572	/**
573	* Does global AMD-V initialization (called during module initialization).
574	*
575	* @returns VBox status code.
576	*/
577	VMMR0DECL(int) SVMR0GlobalInit(void)
578	{
579	/*
580	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
581	* intercept all IO accesses, it's done once globally here instead of per-VM.
582	*/
583	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
584	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
585	if (RT_FAILURE(rc))
586	return rc;
587
588	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
589	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
590
591	/* Set all bits to intercept all IO accesses. */
592	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
593
594	return VINF_SUCCESS;
595	}
596
597
598	/**
599	* Does global AMD-V termination (called during module termination).
600	*/
601	VMMR0DECL(void) SVMR0GlobalTerm(void)
602	{
603	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
604	{
605	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
606	g_pvIOBitmap = NULL;
607	g_HCPhysIOBitmap = 0;
608	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
609	}
610	}
611
612
613	/**
614	* Frees any allocated per-VCPU structures for a VM.
615	*
616	* @param pVM The cross context VM structure.
617	*/
618	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
619	{
620	for (uint32_t i = 0; i < pVM->cCpus; i++)
621	{
622	PVMCPU pVCpu = &pVM->aCpus[i];
623	AssertPtr(pVCpu);
624
625	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
626	{
627	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
628	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
629	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
630	}
631
632	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
633	{
634	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
635	pVCpu->hm.s.svm.pVmcb = NULL;
636	pVCpu->hm.s.svm.HCPhysVmcb = 0;
637	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
638	}
639
640	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
641	{
642	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
643	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
644	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
645	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
646	}
647	}
648	}
649
650
651	/**
652	* Does per-VM AMD-V initialization.
653	*
654	* @returns VBox status code.
655	* @param pVM The cross context VM structure.
656	*/
657	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
658	{
659	int rc = VERR_INTERNAL_ERROR_5;
660
661	/*
662	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
663	*/
664	uint32_t u32Family;
665	uint32_t u32Model;
666	uint32_t u32Stepping;
667	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
668	{
669	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
670	pVM->hm.s.svm.fAlwaysFlushTLB = true;
671	}
672
673	/*
674	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
675	*/
676	for (VMCPUID i = 0; i < pVM->cCpus; i++)
677	{
678	PVMCPU pVCpu = &pVM->aCpus[i];
679	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
680	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
681	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
682	}
683
684	for (VMCPUID i = 0; i < pVM->cCpus; i++)
685	{
686	PVMCPU pVCpu = &pVM->aCpus[i];
687
688	/*
689	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
690	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
691	*/
692	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
693	if (RT_FAILURE(rc))
694	goto failure_cleanup;
695
696	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
697	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
698	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
699	ASMMemZeroPage(pvVmcbHost);
700
701	/*
702	* Allocate one page for the guest-state VMCB.
703	*/
704	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
705	if (RT_FAILURE(rc))
706	goto failure_cleanup;
707
708	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
709	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
710	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
711	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
712
713	/*
714	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
715	* SVM to not require one.
716	*/
717	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
718	false /* fExecutable */);
719	if (RT_FAILURE(rc))
720	goto failure_cleanup;
721
722	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
723	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
724	/* Set all bits to intercept all MSR accesses (changed later on). */
725	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
726	}
727
728	return VINF_SUCCESS;
729
730	failure_cleanup:
731	hmR0SvmFreeStructs(pVM);
732	return rc;
733	}
734
735
736	/**
737	* Does per-VM AMD-V termination.
738	*
739	* @returns VBox status code.
740	* @param pVM The cross context VM structure.
741	*/
742	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
743	{
744	hmR0SvmFreeStructs(pVM);
745	return VINF_SUCCESS;
746	}
747
748
749	/**
750	* Returns whether the VMCB Clean Bits feature is supported.
751	*
752	* @return @c true if supported, @c false otherwise.
753	* @param pVCpu The cross context virtual CPU structure.
754	* @param pCtx Pointer to the guest-CPU context.
755	*/
756	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu, PCPUMCTX pCtx)
757	{
758	PVM pVM = pVCpu->CTX_SUFF(pVM);
759	#ifdef VBOX_WITH_NESTED_HWVIRT
760	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
761	{
762	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
763	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
764	}
765	#else
766	RT_NOREF(pCtx);
767	#endif
768	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
769	}
770
771
772	/**
773	* Returns whether the decode assists feature is supported.
774	*
775	* @return @c true if supported, @c false otherwise.
776	* @param pVCpu The cross context virtual CPU structure.
777	* @param pCtx Pointer to the guest-CPU context.
778	*/
779	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu, PCPUMCTX pCtx)
780	{
781	PVM pVM = pVCpu->CTX_SUFF(pVM);
782	#ifdef VBOX_WITH_NESTED_HWVIRT
783	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
784	{
785	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
786	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
787	}
788	#else
789	RT_NOREF(pCtx);
790	#endif
791	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
792	}
793
794
795	/**
796	* Returns whether the NRIP_SAVE feature is supported.
797	*
798	* @return @c true if supported, @c false otherwise.
799	* @param pVCpu The cross context virtual CPU structure.
800	* @param pCtx Pointer to the guest-CPU context.
801	*/
802	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu, PCPUMCTX pCtx)
803	{
804	PVM pVM = pVCpu->CTX_SUFF(pVM);
805	#ifdef VBOX_WITH_NESTED_HWVIRT
806	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
807	{
808	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
809	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
810	}
811	#else
812	RT_NOREF(pCtx);
813	#endif
814	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
815	}
816
817
818	/**
819	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
820	*
821	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
822	* @param pbMsrBitmap Pointer to the MSR bitmap.
823	* @param idMsr The MSR for which the permissions are being set.
824	* @param enmRead MSR read permissions.
825	* @param enmWrite MSR write permissions.
826	*
827	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
828	* caller needs to take care of this.
829	*/
830	static void hmR0SvmSetMsrPermission(PCPUMCTX pCtx, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
831	SVMMSREXITWRITE enmWrite)
832	{
833	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
834	uint16_t offMsrpm;
835	uint8_t uMsrpmBit;
836	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
837	AssertRC(rc);
838
839	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
840	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
841
842	pbMsrBitmap += offMsrpm;
843	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
844	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
845	else
846	{
847	if (!fInNestedGuestMode)
848	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
849	#ifdef VBOX_WITH_NESTED_HWVIRT
850	else
851	{
852	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
853	uint8_t const pbNstGstMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
854	pbNstGstMsrBitmap += offMsrpm;
855	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
856	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
857	else
858	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
859	}
860	#endif
861	}
862
863	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
864	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
865	else
866	{
867	if (!fInNestedGuestMode)
868	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
869	#ifdef VBOX_WITH_NESTED_HWVIRT
870	else
871	{
872	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
873	uint8_t const pbNstGstMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
874	pbNstGstMsrBitmap += offMsrpm;
875	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
876	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
877	else
878	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
879	}
880	#endif
881	}
882	}
883
884
885	/**
886	* Sets up AMD-V for the specified VM.
887	* This function is only called once per-VM during initalization.
888	*
889	* @returns VBox status code.
890	* @param pVM The cross context VM structure.
891	*/
892	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
893	{
894	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
895	AssertReturn(pVM, VERR_INVALID_PARAMETER);
896	Assert(pVM->hm.s.svm.fSupported);
897
898	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
899	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
900	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
901
902	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
903	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
904
905	#ifdef VBOX_WITH_NESTED_HWVIRT
906	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
907	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
908
909	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
910	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
911	#endif
912
913	PVMCPU pVCpu = &pVM->aCpus[0];
914	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
915	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[0]\n"), VERR_SVM_INVALID_PVMCB);
916	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
917
918	/* Always trap #AC for reasons of security. */
919	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
920
921	/* Always trap #DB for reasons of security. */
922	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
923
924	/* Trap exceptions unconditionally (debug purposes). */
925	#ifdef HMSVM_ALWAYS_TRAP_PF
926	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
927	#endif
928	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
929	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
930	pVmcbCtrl->u32InterceptXcpt \|= 0
931	\| RT_BIT(X86_XCPT_BP)
932	\| RT_BIT(X86_XCPT_DE)
933	\| RT_BIT(X86_XCPT_NM)
934	\| RT_BIT(X86_XCPT_UD)
935	\| RT_BIT(X86_XCPT_NP)
936	\| RT_BIT(X86_XCPT_SS)
937	\| RT_BIT(X86_XCPT_GP)
938	\| RT_BIT(X86_XCPT_PF)
939	\| RT_BIT(X86_XCPT_MF)
940	;
941	#endif
942
943	/* Apply the exceptions intercepts needed by the GIM provider. */
944	if (pVCpu->hm.s.fGIMTrapXcptUD)
945	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
946
947	/* Set up unconditional intercepts and conditions. */
948	pVmcbCtrl->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
949	\| SVM_CTRL_INTERCEPT_VMMCALL;
950
951	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
952	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
953	#endif
954
955	#ifdef VBOX_WITH_NESTED_HWVIRT
956	/* Virtualized VMSAVE/VMLOAD. */
957	pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
958	if (!fUseVirtVmsaveVmload)
959	{
960	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
961	\| SVM_CTRL_INTERCEPT_VMLOAD;
962	}
963
964	/* Virtual GIF. */
965	pVmcbCtrl->IntCtrl.n.u1VGifEnable = fUseVGif;
966	if (!fUseVGif)
967	{
968	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
969	\| SVM_CTRL_INTERCEPT_STGI;
970	}
971	#endif
972
973	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
974	pVmcbCtrl->u16InterceptWrCRx = RT_BIT(4);
975
976	/* Intercept all DRx reads and writes by default. Changed later on. */
977	pVmcbCtrl->u16InterceptRdDRx = 0xffff;
978	pVmcbCtrl->u16InterceptWrDRx = 0xffff;
979
980	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
981	pVmcbCtrl->IntCtrl.n.u1VIntrMasking = 1;
982
983	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
984	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
985	pVmcbCtrl->IntCtrl.n.u1IgnoreTPR = 1;
986
987	/* Set the IO permission bitmap physical addresses. */
988	pVmcbCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
989
990	/* LBR virtualization. */
991	pVmcbCtrl->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
992
993	/* The host ASID MBZ, for the guest start with 1. */
994	pVmcbCtrl->TLBCtrl.n.u32ASID = 1;
995
996	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
997	pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
998
999	/* Without Nested Paging, we need additionally intercepts. */
1000	if (!pVM->hm.s.fNestedPaging)
1001	{
1002	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1003	pVmcbCtrl->u16InterceptRdCRx \|= RT_BIT(3);
1004	pVmcbCtrl->u16InterceptWrCRx \|= RT_BIT(3);
1005
1006	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1007	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1008	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1009
1010	/* Page faults must be intercepted to implement shadow paging. */
1011	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1012	}
1013
1014	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1015	if (fUsePauseFilter)
1016	{
1017	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1018	pVmcbCtrl->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1019	if (fPauseFilterThreshold)
1020	pVmcbCtrl->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1021	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1022	}
1023
1024	/*
1025	* Setup the MSR permission bitmap.
1026	* The following MSRs are saved/restored automatically during the world-switch.
1027	* Don't intercept guest read/write accesses to these MSRs.
1028	*/
1029	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1030	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1031	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1032	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1033	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1034	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1035	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1036	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1037	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1038	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1039	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1040	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1041	pVmcbCtrl->u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
1042
1043	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
1044	Assert(!pVCpu->hm.s.idxExitHistoryFree);
1045	HMCPU_EXIT_HISTORY_RESET(pVCpu);
1046
1047	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1048	Assert(pVmcbCtrl->u32VmcbCleanBits == 0);
1049
1050	for (VMCPUID i = 1; i < pVM->cCpus; i++)
1051	{
1052	PVMCPU pVCpuCur = &pVM->aCpus[i];
1053	PSVMVMCB pVmcbCur = pVM->aCpus[i].hm.s.svm.pVmcb;
1054	AssertMsgReturn(pVmcbCur, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
1055	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1056
1057	/* Copy the VMCB control area. */
1058	memcpy(pVmcbCtrlCur, pVmcbCtrl, sizeof(*pVmcbCtrlCur));
1059
1060	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1061	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hm.s.svm.pvMsrBitmap;
1062	memcpy(pbMsrBitmapCur, pbMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1063	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
1064
1065	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
1066	Assert(!pVCpuCur->hm.s.idxExitHistoryFree);
1067	HMCPU_EXIT_HISTORY_RESET(pVCpuCur);
1068
1069	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1070	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1071
1072	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs. */
1073	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu->hm.s.fGIMTrapXcptUD);
1074	}
1075
1076	return VINF_SUCCESS;
1077	}
1078
1079
1080	/**
1081	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1082	*
1083	* @returns Pointer to the current context VMCB.
1084	* @param pVCpu The cross context virtual CPU structure.
1085	* @param pCtx Pointer to the guest-CPU context.
1086	*/
1087	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
1088	{
1089	#ifdef VBOX_WITH_NESTED_HWVIRT
1090	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1091	return pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1092	#else
1093	RT_NOREF(pCtx);
1094	#endif
1095	return pVCpu->hm.s.svm.pVmcb;
1096	}
1097
1098
1099	/**
1100	* Gets a pointer to the nested-guest VMCB cache.
1101	*
1102	* @returns Pointer to the nested-guest VMCB cache.
1103	* @param pVCpu The cross context virtual CPU structure.
1104	* @param pCtx Pointer to the guest-CPU context.
1105	*/
1106	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPU pVCpu, PCPUMCTX pCtx)
1107	{
1108	#ifdef VBOX_WITH_NESTED_HWVIRT
1109	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); RT_NOREF(pCtx);
1110	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1111	#else
1112	RT_NOREF2(pVCpu, pCtx);
1113	return NULL;
1114	#endif
1115	}
1116
1117
1118	/**
1119	* Invalidates a guest page by guest virtual address.
1120	*
1121	* @returns VBox status code.
1122	* @param pVM The cross context VM structure.
1123	* @param pVCpu The cross context virtual CPU structure.
1124	* @param GCVirt Guest virtual address of the page to invalidate.
1125	*/
1126	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1127	{
1128	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1129	Assert(pVM->hm.s.svm.fSupported);
1130
1131	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1132
1133	/* Skip it if a TLB flush is already pending. */
1134	if (!fFlushPending)
1135	{
1136	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
1137
1138	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1139	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
1140	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1141
1142	#if HC_ARCH_BITS == 32
1143	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1144	if (CPUMIsGuestInLongMode(pVCpu))
1145	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1146	else
1147	#endif
1148	{
1149	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1150	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1151	}
1152	}
1153	return VINF_SUCCESS;
1154	}
1155
1156
1157	/**
1158	* Flushes the appropriate tagged-TLB entries.
1159	*
1160	* @param pVCpu The cross context virtual CPU structure.
1161	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
1162	* @param pVmcb Pointer to the VM control block.
1163	* @param pHostCpu Pointer to the HM host-CPU info.
1164	*/
1165	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, PHMGLOBALCPUINFO pHostCpu)
1166	{
1167	#ifndef VBOX_WITH_NESTED_HWVIRT
1168	RT_NOREF(pCtx);
1169	#endif
1170	PVM pVM = pVCpu->CTX_SUFF(pVM);
1171
1172	/*
1173	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1174	* This can happen both for start & resume due to long jumps back to ring-3.
1175	*
1176	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no correlation
1177	* between it and the physical CPU.
1178	*
1179	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1180	* so we cannot reuse the ASIDs without flushing.
1181	*/
1182	bool fNewAsid = false;
1183	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1184	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1185	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1186	#ifdef VBOX_WITH_NESTED_HWVIRT
1187	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1188	#endif
1189	)
1190	{
1191	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1192	pVCpu->hm.s.fForceTLBFlush = true;
1193	fNewAsid = true;
1194	}
1195
1196	/* Set TLB flush state as checked until we return from the world switch. */
1197	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1198
1199	/* Check for explicit TLB flushes. */
1200	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1201	{
1202	pVCpu->hm.s.fForceTLBFlush = true;
1203	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1204	}
1205
1206	/*
1207	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1208	* This Host CPU requirement takes precedence.
1209	*/
1210	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1211	{
1212	pHostCpu->uCurrentAsid = 1;
1213	pVCpu->hm.s.uCurrentAsid = 1;
1214	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1215	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1216	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1217
1218	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1219	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1220	}
1221	else
1222	{
1223	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1224	if (pVCpu->hm.s.fForceTLBFlush)
1225	{
1226	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1227	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1228
1229	if (fNewAsid)
1230	{
1231	++pHostCpu->uCurrentAsid;
1232
1233	bool fHitASIDLimit = false;
1234	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1235	{
1236	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1237	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1238	fHitASIDLimit = true;
1239	}
1240
1241	if ( fHitASIDLimit
1242	\|\| pHostCpu->fFlushAsidBeforeUse)
1243	{
1244	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1245	pHostCpu->fFlushAsidBeforeUse = false;
1246	}
1247
1248	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1249	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1250	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1251	}
1252	else
1253	{
1254	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1255	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1256	else
1257	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1258	}
1259
1260	pVCpu->hm.s.fForceTLBFlush = false;
1261	}
1262	}
1263
1264	/* Update VMCB with the ASID. */
1265	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1266	{
1267	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1268	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1269	}
1270
1271	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1272	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1273	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1274	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1275	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1276	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1277	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1278	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1279
1280	#ifdef VBOX_WITH_STATISTICS
1281	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1282	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1283	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1284	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1285	{
1286	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1287	}
1288	else
1289	{
1290	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1291	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1292	}
1293	#endif
1294	}
1295
1296
1297	/** @name 64-bit guest on 32-bit host OS helper functions.
1298	*
1299	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1300	* mode (code segment, paging). These wrappers/helpers perform the necessary
1301	* bits for the 32->64 switcher.
1302	*
1303	* @{ */
1304	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1305	/**
1306	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1307	*
1308	* @returns VBox status code.
1309	* @param HCPhysVmcbHost Physical address of host VMCB.
1310	* @param HCPhysVmcb Physical address of the VMCB.
1311	* @param pCtx Pointer to the guest-CPU context.
1312	* @param pVM The cross context VM structure.
1313	* @param pVCpu The cross context virtual CPU structure.
1314	*/
1315	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1316	{
1317	uint32_t aParam[8];
1318	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1319	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1320	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1321	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1322	aParam[4] = VM_RC_ADDR(pVM, pVM);
1323	aParam[5] = 0;
1324	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1325	aParam[7] = 0;
1326
1327	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1328	}
1329
1330
1331	/**
1332	* Executes the specified VMRUN handler in 64-bit mode.
1333	*
1334	* @returns VBox status code.
1335	* @param pVM The cross context VM structure.
1336	* @param pVCpu The cross context virtual CPU structure.
1337	* @param pCtx Pointer to the guest-CPU context.
1338	* @param enmOp The operation to perform.
1339	* @param cParams Number of parameters.
1340	* @param paParam Array of 32-bit parameters.
1341	*/
1342	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1343	uint32_t cParams, uint32_t *paParam)
1344	{
1345	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1346	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1347
1348	NOREF(pCtx);
1349
1350	/* Disable interrupts. */
1351	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1352
1353	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1354	RTCPUID idHostCpu = RTMpCpuId();
1355	CPUMR0SetLApic(pVCpu, idHostCpu);
1356	#endif
1357
1358	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1359	CPUMSetHyperEIP(pVCpu, enmOp);
1360	for (int i = (int)cParams - 1; i >= 0; i--)
1361	CPUMPushHyper(pVCpu, paParam[i]);
1362
1363	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1364	/* Call the switcher. */
1365	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1366	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1367
1368	/* Restore interrupts. */
1369	ASMSetFlags(uOldEFlags);
1370	return rc;
1371	}
1372
1373	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1374	/** @} */
1375
1376
1377	/**
1378	* Sets an exception intercept in the specified VMCB.
1379	*
1380	* @param pVmcb Pointer to the VM control block.
1381	* @param uXcpt The exception (X86_XCPT_*).
1382	*/
1383	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1384	{
1385	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1386	{
1387	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1388	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1389	}
1390	}
1391
1392
1393	/**
1394	* Clears an exception intercept in the specified VMCB.
1395	*
1396	* @param pVCpu The cross context virtual CPU structure.
1397	* @param pCtx Pointer to the guest-CPU context.
1398	* @param pVmcb Pointer to the VM control block.
1399	* @param uXcpt The exception (X86_XCPT_*).
1400	*
1401	* @remarks This takes into account if we're executing a nested-guest and only
1402	* removes the exception intercept if both the guest -and- nested-guest
1403	* are not intercepting it.
1404	*/
1405	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint8_t uXcpt)
1406	{
1407	Assert(uXcpt != X86_XCPT_DB);
1408	Assert(uXcpt != X86_XCPT_AC);
1409	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1410	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1411	{
1412	bool fRemove = true;
1413	#ifdef VBOX_WITH_NESTED_HWVIRT
1414	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1415	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1416	{
1417	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
1418	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1419	}
1420	#else
1421	RT_NOREF2(pVCpu, pCtx);
1422	#endif
1423	if (fRemove)
1424	{
1425	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1426	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1427	}
1428	}
1429	#else
1430	RT_NOREF3(pVCpu, pCtx, pVmcb);
1431	#endif
1432	}
1433
1434
1435	/**
1436	* Sets a control intercept in the specified VMCB.
1437	*
1438	* @param pVmcb Pointer to the VM control block.
1439	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1440	*/
1441	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1442	{
1443	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1444	{
1445	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1446	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1447	}
1448	}
1449
1450
1451	/**
1452	* Clears a control intercept in the specified VMCB.
1453	*
1454	* @returns @c true if the intercept is still set, @c false otherwise.
1455	* @param pVCpu The cross context virtual CPU structure.
1456	* @param pCtx Pointer to the guest-CPU context.
1457	* @param pVmcb Pointer to the VM control block.
1458	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1459	*
1460	* @remarks This takes into account if we're executing a nested-guest and only
1461	* removes the control intercept if both the guest -and- nested-guest
1462	* are not intercepting it.
1463	*/
1464	DECLINLINE(bool) hmR0SvmClearCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1465	{
1466	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1467	{
1468	bool fRemove = true;
1469	#ifdef VBOX_WITH_NESTED_HWVIRT
1470	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1471	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1472	{
1473	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
1474	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1475	}
1476	#else
1477	RT_NOREF2(pVCpu, pCtx);
1478	#endif
1479	if (fRemove)
1480	{
1481	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1482	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1483	}
1484	}
1485
1486	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1487	}
1488
1489
1490	/**
1491	* Loads the guest (or nested-guest) CR0 control register into the guest-state
1492	* area in the VMCB.
1493	*
1494	* Although the guest CR0 is a separate field in the VMCB we have to consider
1495	* the FPU state itself which is shared between the host and the guest.
1496	*
1497	* @returns VBox status code.
1498	* @param pVCpu The cross context virtual CPU structure.
1499	* @param pVmcb Pointer to the VM control block.
1500	* @param pCtx Pointer to the guest-CPU context.
1501	*
1502	* @remarks No-long-jump zone!!!
1503	*/
1504	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1505	{
1506	/* The guest FPU is now always pre-loaded before executing guest code, see @bugref{7243#c101}. */
1507	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1508
1509	uint64_t const uGuestCr0 = pCtx->cr0;
1510	uint64_t uShadowCr0 = uGuestCr0;
1511
1512	/* Always enable caching. */
1513	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1514
1515	/* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()). */
1516	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1517	{
1518	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1519	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1520	}
1521
1522	/*
1523	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that lets us
1524	* isolate the host from it, IEM/REM still needs work to emulate it properly. see @bugref{7243#c103}.
1525	*/
1526	if (!(uGuestCr0 & X86_CR0_NE))
1527	{
1528	uShadowCr0 \|= X86_CR0_NE;
1529	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1530	}
1531	else
1532	hmR0SvmClearXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_MF);
1533
1534	/*
1535	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1536	*
1537	* CR0 writes still needs interception as PGM requires tracking paging mode changes, see @bugref{6944}.
1538	* We also don't ever want to honor weird things like cache disable from the guest. However, we can
1539	* avoid intercepting changes to the TS & MP bits by clearing the CR0 write intercept below and keeping
1540	* SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1541	*/
1542	if (uShadowCr0 == uGuestCr0)
1543	{
1544	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1545	{
1546	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1547	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1548	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1549	}
1550	else
1551	{
1552	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1553	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
1554	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1555	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1556	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1557	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1558	}
1559	}
1560	else
1561	{
1562	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1563	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1564	}
1565	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1566
1567	Assert(RT_HI_U32(uShadowCr0) == 0);
1568	if (pVmcb->guest.u64CR0 != uShadowCr0)
1569	{
1570	pVmcb->guest.u64CR0 = uShadowCr0;
1571	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1572	}
1573	}
1574
1575
1576	/**
1577	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1578	*
1579	* @returns VBox status code.
1580	* @param pVCpu The cross context virtual CPU structure.
1581	* @param pVmcb Pointer to the VM control block.
1582	* @param pCtx Pointer to the guest-CPU context.
1583	*
1584	* @remarks No-long-jump zone!!!
1585	*/
1586	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1587	{
1588	PVM pVM = pVCpu->CTX_SUFF(pVM);
1589
1590	/*
1591	* Guest CR2.
1592	*/
1593	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1594	{
1595	pVmcb->guest.u64CR2 = pCtx->cr2;
1596	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1597	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1598	}
1599
1600	/*
1601	* Guest CR3.
1602	*/
1603	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1604	{
1605	if (pVM->hm.s.fNestedPaging)
1606	{
1607	PGMMODE enmShwPagingMode;
1608	#if HC_ARCH_BITS == 32
1609	if (CPUMIsGuestInLongModeEx(pCtx))
1610	enmShwPagingMode = PGMMODE_AMD64_NX;
1611	else
1612	#endif
1613	enmShwPagingMode = PGMGetHostMode(pVM);
1614
1615	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1616	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1617	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1618	pVmcb->guest.u64CR3 = pCtx->cr3;
1619	}
1620	else
1621	{
1622	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1623	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1624	}
1625
1626	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1627	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1628	}
1629
1630	/*
1631	* Guest CR4.
1632	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1633	*/
1634	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1635	{
1636	uint64_t uShadowCr4 = pCtx->cr4;
1637	if (!pVM->hm.s.fNestedPaging)
1638	{
1639	switch (pVCpu->hm.s.enmShadowMode)
1640	{
1641	case PGMMODE_REAL:
1642	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1643	AssertFailed();
1644	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1645
1646	case PGMMODE_32_BIT: /* 32-bit paging. */
1647	uShadowCr4 &= ~X86_CR4_PAE;
1648	break;
1649
1650	case PGMMODE_PAE: /* PAE paging. */
1651	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1652	/** Must use PAE paging as we could use physical memory > 4 GB */
1653	uShadowCr4 \|= X86_CR4_PAE;
1654	break;
1655
1656	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1657	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1658	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1659	break;
1660	#else
1661	AssertFailed();
1662	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1663	#endif
1664
1665	default: /* shut up gcc */
1666	AssertFailed();
1667	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1668	}
1669	}
1670
1671	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1672	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1673
1674	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1675	if (uShadowCr4 == pCtx->cr4)
1676	{
1677	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1678	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1679	else
1680	{
1681	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1682	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pCtx);
1683	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1684	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1685	}
1686	}
1687	else
1688	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1689
1690	/* CR4 writes are always intercepted (both guest, nested-guest) from tracking PGM mode changes. */
1691	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1692
1693	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1694	Assert(RT_HI_U32(uShadowCr4) == 0);
1695	pVmcb->guest.u64CR4 = uShadowCr4;
1696	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1697
1698	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1699	}
1700
1701	return VINF_SUCCESS;
1702	}
1703
1704
1705	/**
1706	* Loads the guest (or nested-guest) segment registers into the VMCB.
1707	*
1708	* @returns VBox status code.
1709	* @param pVCpu The cross context virtual CPU structure.
1710	* @param pVmcb Pointer to the VM control block.
1711	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
1712	*
1713	* @remarks No-long-jump zone!!!
1714	*/
1715	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1716	{
1717	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1718	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1719	{
1720	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1721	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1722	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1723	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1724	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1725	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1726
1727	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1728	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1729	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1730	}
1731
1732	/* Guest TR. */
1733	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1734	{
1735	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1736	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1737	}
1738
1739	/* Guest LDTR. */
1740	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1741	{
1742	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1743	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1744	}
1745
1746	/* Guest GDTR. */
1747	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1748	{
1749	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1750	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1751	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1752	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1753	}
1754
1755	/* Guest IDTR. */
1756	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1757	{
1758	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1759	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1760	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1761	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1762	}
1763	}
1764
1765
1766	/**
1767	* Loads the guest (or nested-guest) MSRs into the VMCB.
1768	*
1769	* @param pVCpu The cross context virtual CPU structure.
1770	* @param pVmcb Pointer to the VM control block.
1771	* @param pCtx Pointer to the guest-CPU context.
1772	*
1773	* @remarks No-long-jump zone!!!
1774	*/
1775	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1776	{
1777	/* Guest Sysenter MSRs. */
1778	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1779	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1780	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1781
1782	/*
1783	* Guest EFER MSR.
1784	* AMD-V requires guest EFER.SVME to be set. Weird.
1785	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1786	*/
1787	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1788	{
1789	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1790	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1791	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1792	}
1793
1794	/* 64-bit MSRs. */
1795	if (CPUMIsGuestInLongModeEx(pCtx))
1796	{
1797	/* Load these always as the guest may modify FS/GS base using MSRs in 64-bit mode which we don't intercept. */
1798	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1799	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1800	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1801	}
1802	else
1803	{
1804	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1805	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1806	{
1807	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1808	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1809	}
1810	}
1811
1812	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1813	* be writable in 32-bit mode. Clarify with AMD spec. */
1814	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1815	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1816	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1817	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1818	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1819
1820	/*
1821	* Setup the PAT MSR (applicable for Nested Paging only).
1822	*
1823	* While guests can modify and see the modified values throug the shadow values,
1824	* we shall not honor any guest modifications of this MSR to ensure caching is always
1825	* enabled similar to how we always run with CR0.CD and NW bits cleared.
1826	*
1827	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1828	*/
1829	pVmcb->guest.u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
1830
1831	/* Enable the last branch record bit if LBR virtualization is enabled. */
1832	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1833	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1834	}
1835
1836
1837	/**
1838	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1839	* necessary intercepts accordingly.
1840	*
1841	* @param pVCpu The cross context virtual CPU structure.
1842	* @param pVmcb Pointer to the VM control block.
1843	* @param pCtx Pointer to the guest-CPU context.
1844	*
1845	* @remarks No-long-jump zone!!!
1846	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1847	*/
1848	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1849	{
1850	bool fInterceptMovDRx = false;
1851
1852	/*
1853	* Anyone single stepping on the host side? If so, we'll have to use the
1854	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1855	* the VMM level like the VT-x implementations does.
1856	*/
1857	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1858	if (fStepping)
1859	{
1860	pVCpu->hm.s.fClearTrapFlag = true;
1861	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1862	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1863	}
1864
1865	if ( fStepping
1866	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1867	{
1868	/*
1869	* Use the combined guest and host DRx values found in the hypervisor
1870	* register set because the debugger has breakpoints active or someone
1871	* is single stepping on the host side.
1872	*
1873	* Note! DBGF expects a clean DR6 state before executing guest code.
1874	*/
1875	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1876	if ( CPUMIsGuestInLongModeEx(pCtx)
1877	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1878	{
1879	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1880	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1881	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1882	}
1883	else
1884	#endif
1885	if (!CPUMIsHyperDebugStateActive(pVCpu))
1886	{
1887	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1888	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1889	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1890	}
1891
1892	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1893	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1894	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1895	{
1896	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1897	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1898	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1899	pVCpu->hm.s.fUsingHyperDR7 = true;
1900	}
1901
1902	/** @todo If we cared, we could optimize to allow the guest to read registers
1903	* with the same values. */
1904	fInterceptMovDRx = true;
1905	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1906	}
1907	else
1908	{
1909	/*
1910	* Update DR6, DR7 with the guest values if necessary.
1911	*/
1912	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1913	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1914	{
1915	pVmcb->guest.u64DR7 = pCtx->dr[7];
1916	pVmcb->guest.u64DR6 = pCtx->dr[6];
1917	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1918	pVCpu->hm.s.fUsingHyperDR7 = false;
1919	}
1920
1921	/*
1922	* If the guest has enabled debug registers, we need to load them prior to
1923	* executing guest code so they'll trigger at the right time.
1924	*/
1925	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1926	{
1927	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1928	if ( CPUMIsGuestInLongModeEx(pCtx)
1929	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1930	{
1931	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1932	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1933	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1934	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1935	}
1936	else
1937	#endif
1938	if (!CPUMIsGuestDebugStateActive(pVCpu))
1939	{
1940	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1941	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1942	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1943	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1944	}
1945	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1946	}
1947	/*
1948	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1949	* intercept #DB as DR6 is updated in the VMCB.
1950	*
1951	* Note! If we cared and dared, we could skip intercepting \#DB here.
1952	* However, \#DB shouldn't be performance critical, so we'll play safe
1953	* and keep the code similar to the VT-x code and always intercept it.
1954	*/
1955	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1956	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1957	&& !CPUMIsGuestDebugStateActive(pVCpu))
1958	#else
1959	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1960	#endif
1961	{
1962	fInterceptMovDRx = true;
1963	}
1964	}
1965
1966	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1967	if (fInterceptMovDRx)
1968	{
1969	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1970	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1971	{
1972	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1973	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1974	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1975	}
1976	}
1977	else
1978	{
1979	if ( pVmcb->ctrl.u16InterceptRdDRx
1980	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1981	{
1982	pVmcb->ctrl.u16InterceptRdDRx = 0;
1983	pVmcb->ctrl.u16InterceptWrDRx = 0;
1984	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1985	}
1986	}
1987	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1988	}
1989
1990
1991	#ifdef VBOX_WITH_NESTED_HWVIRT
1992	/**
1993	* Loads the nested-guest APIC state (currently just the TPR).
1994	*
1995	* @param pVCpu The cross context virtual CPU structure.
1996	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1997	*/
1998	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1999	{
2000	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_APIC_STATE))
2001	{
2002	Assert(pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking == 1); RT_NOREF(pVmcbNstGst);
2003	pVCpu->hm.s.svm.fSyncVTpr = false;
2004	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
2005	}
2006	}
2007
2008
2009	/**
2010	* Loads the nested-guest hardware virtualization state.
2011	*
2012	* @param pVCpu The cross context virtual CPU structure.
2013	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2014	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
2015	*/
2016	static void hmR0SvmLoadGuestHwvirtStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
2017	{
2018	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_HWVIRT))
2019	{
2020	/*
2021	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2022	* since SVM doesn't have a preemption timer.
2023	*
2024	* We do this here rather than in hmR0SvmVmRunSetupVmcb() as we may have been executing the
2025	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2026	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2027	*/
2028	PVM pVM = pVCpu->CTX_SUFF(pVM);
2029	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2030	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2031	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2032	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
2033	{
2034	pVmcbNstGstCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2035	pVmcbNstGstCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2036	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2037	}
2038	else
2039	{
2040	pVmcbNstGstCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2041	pVmcbNstGstCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2042	}
2043
2044	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_HWVIRT);
2045	}
2046	}
2047	#endif
2048
2049	/**
2050	* Loads the guest APIC state (currently just the TPR).
2051	*
2052	* @returns VBox status code.
2053	* @param pVCpu The cross context virtual CPU structure.
2054	* @param pVmcb Pointer to the VM control block.
2055	* @param pCtx Pointer to the guest-CPU context.
2056	*/
2057	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2058	{
2059	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_APIC_STATE))
2060	return VINF_SUCCESS;
2061
2062	int rc = VINF_SUCCESS;
2063	PVM pVM = pVCpu->CTX_SUFF(pVM);
2064	if ( PDMHasApic(pVM)
2065	&& APICIsEnabled(pVCpu))
2066	{
2067	bool fPendingIntr;
2068	uint8_t u8Tpr;
2069	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2070	AssertRCReturn(rc, rc);
2071
2072	/* Assume that we need to trap all TPR accesses and thus need not check on
2073	every #VMEXIT if we should update the TPR. */
2074	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2075	pVCpu->hm.s.svm.fSyncVTpr = false;
2076
2077	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2078	if (pVM->hm.s.fTPRPatchingActive)
2079	{
2080	pCtx->msrLSTAR = u8Tpr;
2081	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
2082
2083	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2084	if (fPendingIntr)
2085	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2086	else
2087	{
2088	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2089	pVCpu->hm.s.svm.fSyncVTpr = true;
2090	}
2091	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2092	}
2093	else
2094	{
2095	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2096	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2097
2098	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
2099	if (fPendingIntr)
2100	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2101	else
2102	{
2103	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2104	pVCpu->hm.s.svm.fSyncVTpr = true;
2105	}
2106
2107	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2108	}
2109	}
2110
2111	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
2112	return rc;
2113	}
2114
2115
2116	/**
2117	* Loads the exception interrupts required for guest (or nested-guest) execution in
2118	* the VMCB.
2119	*
2120	* @param pVCpu The cross context virtual CPU structure.
2121	* @param pVmcb Pointer to the VM control block.
2122	* @param pCtx Pointer to the guest-CPU context.
2123	*/
2124	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2125	{
2126	/* If we modify intercepts from here, please check & adjust hmR0SvmLoadGuestXcptInterceptsNested()
2127	if required. */
2128	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMM_GUEST_XCPT_INTERCEPTS))
2129	{
2130	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2131	if (pVCpu->hm.s.fGIMTrapXcptUD)
2132	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2133	else
2134	hmR0SvmClearXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_UD);
2135
2136	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2137	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2138	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2139	else
2140	hmR0SvmClearXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_BP);
2141
2142	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
2143	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMM_GUEST_XCPT_INTERCEPTS);
2144	}
2145	}
2146
2147
2148	#ifdef VBOX_WITH_NESTED_HWVIRT
2149	/**
2150	* Merges guest and nested-guest intercepts for executing the nested-guest using
2151	* hardware-assisted SVM.
2152	*
2153	* This merges the guest and nested-guest intercepts in a way that if the outer
2154	* guest intercept is set we need to intercept it in the nested-guest as
2155	* well.
2156	*
2157	* @param pVCpu The cross context virtual CPU structure.
2158	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2159	* @param pCtx Pointer to the nested-guest-CPU context.
2160	*/
2161	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2162	{
2163	PVM pVM = pVCpu->CTX_SUFF(pVM);
2164	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2165	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2166	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2167
2168	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2169	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2170	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2171
2172	/* Always intercept CR4 writes for tracking PGM mode changes. */
2173	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2174
2175	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2176	if (!pVM->hm.s.fNestedPaging)
2177	{
2178	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2179	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2180	}
2181
2182	/** @todo Figure out debugging with nested-guests, till then just intercept
2183	* all DR[0-15] accesses. */
2184	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2185	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2186
2187	/*
2188	* Merge the guest's exception intercepts into the nested-guest VMCB.
2189	*
2190	* - \#UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2191	* while executing the nested-guest.
2192	*
2193	* - \#BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2194	* be tweaked later depending on how we wish to implement breakpoints.
2195	*
2196	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2197	* for VM debugger breakpoints, see hmR0SvmLoadGuestXcptIntercepts.
2198	*/
2199	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2200	pVmcbNstGstCtrl->u32InterceptXcpt \|= (pVmcb->ctrl.u32InterceptXcpt & ~( RT_BIT(X86_XCPT_UD)
2201	\| RT_BIT(X86_XCPT_BP)));
2202	#else
2203	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2204	#endif
2205
2206	/*
2207	* Adjust intercepts while executing the nested-guest that differ from the
2208	* outer guest intercepts.
2209	*
2210	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2211	* that belong to the nested-guest to the outer guest.
2212	*
2213	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2214	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2215	*/
2216	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2217	\| SVM_CTRL_INTERCEPT_VMMCALL))
2218	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2219
2220	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2221	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2222
2223	/* Finally, update the VMCB clean bits. */
2224	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2225	}
2226	#endif
2227
2228
2229	/**
2230	* Sets up the appropriate function to run guest code.
2231	*
2232	* @returns VBox status code.
2233	* @param pVCpu The cross context virtual CPU structure.
2234	*
2235	* @remarks No-long-jump zone!!!
2236	*/
2237	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
2238	{
2239	if (CPUMIsGuestInLongMode(pVCpu))
2240	{
2241	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2242	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2243	#endif
2244	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2245	#if HC_ARCH_BITS == 32
2246	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2247	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2248	#else
2249	/* 64-bit host or hybrid host. */
2250	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2251	#endif
2252	}
2253	else
2254	{
2255	/* Guest is not in long mode, use the 32-bit handler. */
2256	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2257	}
2258	return VINF_SUCCESS;
2259	}
2260
2261
2262	/**
2263	* Enters the AMD-V session.
2264	*
2265	* @returns VBox status code.
2266	* @param pVM The cross context VM structure.
2267	* @param pVCpu The cross context virtual CPU structure.
2268	* @param pCpu Pointer to the CPU info struct.
2269	*/
2270	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2271	{
2272	AssertPtr(pVM);
2273	AssertPtr(pVCpu);
2274	Assert(pVM->hm.s.svm.fSupported);
2275	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2276	NOREF(pVM); NOREF(pCpu);
2277
2278	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2279	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2280
2281	pVCpu->hm.s.fLeaveDone = false;
2282	return VINF_SUCCESS;
2283	}
2284
2285
2286	/**
2287	* Thread-context callback for AMD-V.
2288	*
2289	* @param enmEvent The thread-context event.
2290	* @param pVCpu The cross context virtual CPU structure.
2291	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2292	* @thread EMT(pVCpu)
2293	*/
2294	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2295	{
2296	NOREF(fGlobalInit);
2297
2298	switch (enmEvent)
2299	{
2300	case RTTHREADCTXEVENT_OUT:
2301	{
2302	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2303	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2304	VMCPU_ASSERT_EMT(pVCpu);
2305
2306	/* No longjmps (log-flush, locks) in this fragile context. */
2307	VMMRZCallRing3Disable(pVCpu);
2308
2309	if (!pVCpu->hm.s.fLeaveDone)
2310	{
2311	hmR0SvmLeave(pVCpu);
2312	pVCpu->hm.s.fLeaveDone = true;
2313	}
2314
2315	/* Leave HM context, takes care of local init (term). */
2316	int rc = HMR0LeaveCpu(pVCpu);
2317	AssertRC(rc); NOREF(rc);
2318
2319	/* Restore longjmp state. */
2320	VMMRZCallRing3Enable(pVCpu);
2321	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2322	break;
2323	}
2324
2325	case RTTHREADCTXEVENT_IN:
2326	{
2327	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2328	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2329	VMCPU_ASSERT_EMT(pVCpu);
2330
2331	/* No longjmps (log-flush, locks) in this fragile context. */
2332	VMMRZCallRing3Disable(pVCpu);
2333
2334	/*
2335	* Initialize the bare minimum state required for HM. This takes care of
2336	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2337	*/
2338	int rc = HMR0EnterCpu(pVCpu);
2339	AssertRC(rc); NOREF(rc);
2340	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2341
2342	pVCpu->hm.s.fLeaveDone = false;
2343
2344	/* Restore longjmp state. */
2345	VMMRZCallRing3Enable(pVCpu);
2346	break;
2347	}
2348
2349	default:
2350	break;
2351	}
2352	}
2353
2354
2355	/**
2356	* Saves the host state.
2357	*
2358	* @returns VBox status code.
2359	* @param pVM The cross context VM structure.
2360	* @param pVCpu The cross context virtual CPU structure.
2361	*
2362	* @remarks No-long-jump zone!!!
2363	*/
2364	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
2365	{
2366	NOREF(pVM);
2367	NOREF(pVCpu);
2368	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2369	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
2370	return VINF_SUCCESS;
2371	}
2372
2373
2374	/**
2375	* Loads the guest state into the VMCB.
2376	*
2377	* The CPU state will be loaded from these fields on every successful VM-entry.
2378	* Also sets up the appropriate VMRUN function to execute guest code based on
2379	* the guest CPU mode.
2380	*
2381	* @returns VBox status code.
2382	* @param pVM The cross context VM structure.
2383	* @param pVCpu The cross context virtual CPU structure.
2384	* @param pCtx Pointer to the guest-CPU context.
2385	*
2386	* @remarks No-long-jump zone!!!
2387	*/
2388	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2389	{
2390	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2391
2392	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2393	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2394
2395	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2396
2397	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
2398	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2399
2400	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
2401	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
2402
2403	pVmcb->guest.u64RIP = pCtx->rip;
2404	pVmcb->guest.u64RSP = pCtx->rsp;
2405	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2406	pVmcb->guest.u64RAX = pCtx->rax;
2407
2408	#ifdef VBOX_WITH_NESTED_HWVIRT
2409	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1)
2410	{
2411	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2412	pVmcb->ctrl.IntCtrl.n.u1VGif = pCtx->hwvirt.fGif;
2413	}
2414	#endif
2415
2416	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
2417	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2418
2419	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
2420
2421	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2422	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2423
2424	/* Clear any unused and reserved bits. */
2425	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2426	\| HM_CHANGED_GUEST_RSP
2427	\| HM_CHANGED_GUEST_RFLAGS
2428	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2429	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2430	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2431	\| HM_CHANGED_GUEST_HWVIRT /* Unused. */
2432	\| HM_CHANGED_VMM_GUEST_LAZY_MSRS
2433	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2434	\| HM_CHANGED_SVM_RESERVED2
2435	\| HM_CHANGED_SVM_RESERVED3
2436	\| HM_CHANGED_SVM_RESERVED4);
2437
2438	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2439	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2440	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2441	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2442
2443	#ifdef VBOX_STRICT
2444	hmR0SvmLogState(pVCpu, pVmcb, pCtx, "hmR0SvmLoadGuestState", 0 /* fFlags /, 0 / uVerbose */);
2445	#endif
2446	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2447	return rc;
2448	}
2449
2450
2451	#ifdef VBOX_WITH_NESTED_HWVIRT
2452	/**
2453	* Merges the guest and nested-guest MSR permission bitmap.
2454	*
2455	* If the guest is intercepting an MSR we need to intercept it regardless of
2456	* whether the nested-guest is intercepting it or not.
2457	*
2458	* @param pHostCpu Pointer to the physical CPU HM info. struct.
2459	* @param pVCpu The cross context virtual CPU structure.
2460	* @param pCtx Pointer to the nested-guest-CPU context.
2461	*/
2462	static void hmR0SvmMergeMsrpmNested(PHMGLOBALCPUINFO pHostCpu, PVMCPU pVCpu, PCPUMCTX pCtx)
2463	{
2464	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2465	uint64_t const pu64NstGstMsrpm = (uint64_t const )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2466	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2467
2468	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2469	uint32_t const offRsvdQwords = 0x1800 >> 3;
2470	for (uint32_t i = 0; i < offRsvdQwords; i++)
2471	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2472	}
2473
2474
2475	/**
2476	* Caches the nested-guest VMCB fields before we modify them for execution using
2477	* hardware-assisted SVM.
2478	*
2479	* @returns true if the VMCB was previously already cached, false otherwise.
2480	* @param pCtx Pointer to the guest-CPU context.
2481	*
2482	* @sa HMSvmNstGstVmExitNotify.
2483	*/
2484	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2485	{
2486	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2487	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2488	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2489	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2490
2491	/*
2492	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2493	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2494	*
2495	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2496	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2497	*/
2498	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2499	if (!fWasCached)
2500	{
2501	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2502	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2503	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2504	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2505	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2506	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2507	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2508	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2509	pVmcbNstGstCache->u64CR0 = pVmcbNstGstState->u64CR0;
2510	pVmcbNstGstCache->u64CR3 = pVmcbNstGstState->u64CR3;
2511	pVmcbNstGstCache->u64CR4 = pVmcbNstGstState->u64CR4;
2512	pVmcbNstGstCache->u64EFER = pVmcbNstGstState->u64EFER;
2513	pVmcbNstGstCache->u64PAT = pVmcbNstGstState->u64PAT;
2514	pVmcbNstGstCache->u64DBGCTL = pVmcbNstGstState->u64DBGCTL;
2515	pVmcbNstGstCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2516	pVmcbNstGstCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2517	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2518	pVmcbNstGstCache->u32VmcbCleanBits = pVmcbNstGstCtrl->u32VmcbCleanBits;
2519	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2520	pVmcbNstGstCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2521	pVmcbNstGstCache->u1NestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2522	pVmcbNstGstCache->u1LbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2523	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2524	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2525	}
2526
2527	return fWasCached;
2528	}
2529
2530
2531	/**
2532	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2533	*
2534	* This is done the first time we enter nested-guest execution using SVM R0
2535	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2536	* \#VMEXITs which may or may not cause the nested-guest \#VMEXIT).
2537	*
2538	* @param pVCpu The cross context virtual CPU structure.
2539	* @param pCtx Pointer to the nested-guest-CPU context.
2540	*/
2541	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2542	{
2543	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2544	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2545
2546	/*
2547	* First cache the nested-guest VMCB fields we may potentially modify.
2548	*/
2549	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2550	if (!fVmcbCached)
2551	{
2552	/*
2553	* The IOPM of the nested-guest can be ignored because the the guest always
2554	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2555	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2556	*/
2557	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2558
2559	/*
2560	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2561	* nested-paging suddenly while executing a VM (see assertion at the end of
2562	* Trap0eHandler() in PGMAllBth.h).
2563	*/
2564	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2565
2566	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2567	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2568
2569	#ifdef DEBUG_ramshankar
2570	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2571	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2572	#endif
2573
2574	/*
2575	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2576	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2577	*/
2578	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2579	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2580	\| SVM_CTRL_INTERCEPT_VMLOAD;
2581
2582	/*
2583	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2584	* CLGI/STGI instructions executed by the nested-guest.
2585	*/
2586	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2587	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2588	\| SVM_CTRL_INTERCEPT_STGI;
2589
2590	/* Merge the guest and nested-guest intercepts. */
2591	hmR0SvmMergeVmcbCtrlsNested(pVCpu, pCtx);
2592
2593	/* Update the VMCB clean bits. */
2594	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2595	}
2596	else
2597	{
2598	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2599	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2600	}
2601	}
2602
2603
2604	/**
2605	* Loads the nested-guest state into the VMCB.
2606	*
2607	* @returns VBox status code.
2608	* @param pVCpu The cross context virtual CPU structure.
2609	* @param pCtx Pointer to the guest-CPU context.
2610	*
2611	* @remarks No-long-jump zone!!!
2612	*/
2613	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2614	{
2615	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2616
2617	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb); Assert(pVmcbNstGst);
2618
2619	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
2620	AssertRCReturn(rc, rc);
2621
2622	/*
2623	* We need to load the entire state (including FS, GS etc.) as we could be continuing
2624	* to execute the nested-guest at any point (not just immediately after VMRUN) and thus
2625	* the VMCB can possibly be out-of-sync with the actual nested-guest state if it was
2626	* executed in IEM.
2627	*/
2628	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2629	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2630	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2631	hmR0SvmLoadGuestHwvirtStateNested(pVCpu, pVmcbNstGst, pCtx);
2632
2633	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2634	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2635	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2636	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2637
2638	#ifdef VBOX_WITH_NESTED_HWVIRT
2639	Assert(pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable == 0); /* Nested VGIF not supported yet. */
2640	#endif
2641
2642	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2643	AssertRCReturn(rc, rc);
2644
2645	/* Clear any unused and reserved bits. */
2646	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2647	\| HM_CHANGED_GUEST_RSP
2648	\| HM_CHANGED_GUEST_RFLAGS
2649	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2650	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2651	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2652	\| HM_CHANGED_VMM_GUEST_XCPT_INTERCEPTS /* Unused. */
2653	\| HM_CHANGED_VMM_GUEST_LAZY_MSRS
2654	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2655	\| HM_CHANGED_SVM_RESERVED2
2656	\| HM_CHANGED_SVM_RESERVED3
2657	\| HM_CHANGED_SVM_RESERVED4);
2658
2659	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2660	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2661	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2662	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2663
2664	#ifdef VBOX_STRICT
2665	hmR0SvmLogState(pVCpu, pVmcbNstGst, pCtx, "hmR0SvmLoadGuestStateNested", HMSVM_LOG_ALL, 0 /* uVerbose */);
2666	#endif
2667	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2668	return rc;
2669	}
2670	#endif /* VBOX_WITH_NESTED_HWVIRT */
2671
2672
2673	/**
2674	* Loads the state shared between the host and guest (or nested-guest) into the
2675	* VMCB.
2676	*
2677	* @param pVCpu The cross context virtual CPU structure.
2678	* @param pVmcb Pointer to the VM control block.
2679	* @param pCtx Pointer to the guest-CPU context.
2680	*
2681	* @remarks No-long-jump zone!!!
2682	*/
2683	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2684	{
2685	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2686	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2687
2688	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2689	{
2690	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2691	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2692	}
2693
2694	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2695	{
2696	/** @todo Figure out stepping with nested-guest. */
2697	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2698	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2699	else
2700	{
2701	pVmcb->guest.u64DR6 = pCtx->dr[6];
2702	pVmcb->guest.u64DR7 = pCtx->dr[7];
2703	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2704	}
2705
2706	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2707	}
2708
2709	/* Unused on AMD-V (no lazy MSRs). */
2710	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMM_GUEST_LAZY_MSRS);
2711
2712	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2713	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2714	}
2715
2716
2717	/**
2718	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2719	* context.
2720	*
2721	* Currently there is no residual state left in the CPU that is not updated in the
2722	* VMCB.
2723	*
2724	* @returns VBox status code.
2725	* @param pVCpu The cross context virtual CPU structure.
2726	* @param pMixedCtx Pointer to the guest-CPU or nested-guest-CPU
2727	* context. The data may be out-of-sync. Make sure to
2728	* update the required fields before using them.
2729	* @param pVmcb Pointer to the VM control block.
2730	*/
2731	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2732	{
2733	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2734
2735	pMixedCtx->rip = pVmcb->guest.u64RIP;
2736	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2737	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2738	pMixedCtx->rax = pVmcb->guest.u64RAX;
2739
2740	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2741	#ifdef VBOX_WITH_NESTED_HWVIRT
2742	if (!CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2743	{
2744	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2745	{
2746	/*
2747	* Guest Virtual GIF (Global Interrupt Flag).
2748	* We don't yet support passing VGIF feature to the guest.
2749	*/
2750	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fVGif);
2751	pMixedCtx->hwvirt.fGif = pVmcbCtrl->IntCtrl.n.u1VGif;
2752	}
2753	}
2754	else
2755	{
2756	/* Sync/verify nested-guest's V_IRQ pending and our force-flag. */
2757	if (!pVmcbCtrl->IntCtrl.n.u1VIrqPending)
2758	{
2759	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2760	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2761	}
2762	else
2763	Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST));
2764	}
2765	#endif
2766
2767	/*
2768	* Guest interrupt shadow.
2769	*/
2770	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2771	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2772	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2773	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2774
2775	/*
2776	* Guest control registers: CR0, CR2, CR3 (handled at the end).
2777	* Accesses to other control registers are always intercepted.
2778	*/
2779	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2780
2781	/* If we're not intercepting changes to CR0 TS & MP bits, sync those bits here. */
2782	if (!(pVmcbCtrl->u16InterceptWrCRx & RT_BIT(0)))
2783	{
2784	pMixedCtx->cr0 = (pMixedCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2785	\| (pVmcb->guest.u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2786	}
2787
2788	/*
2789	* Guest MSRs.
2790	*/
2791	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2792	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2793	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2794	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2795	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2796	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2797	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2798	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2799
2800	/*
2801	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2802	*/
2803	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2804	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2805	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2806	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2807	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2808	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2809
2810	/*
2811	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2812	* register (yet).
2813	*/
2814	/** @todo SELM might need to be fixed as it too should not care about the
2815	* granularity bit. See @bugref{6785}. */
2816	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2817	&& pMixedCtx->cs.Attr.n.u1Present
2818	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2819	{
2820	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2821	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2822	}
2823
2824	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2825	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2826	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2827	HMSVM_ASSERT_SEG_GRANULARITY(es);
2828	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2829	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2830
2831	/*
2832	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2833	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2834	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2835	* See AMD spec. 15.5.1 "Basic operation".
2836	*/
2837	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2838	uint8_t const uCpl = pVmcb->guest.u8CPL;
2839	if (pMixedCtx->ss.Attr.n.u2Dpl != uCpl)
2840	{
2841	Log4(("hmR0SvmSaveGuestState: CPL differs. SS.DPL=%u, CPL=%u, overwriting SS.DPL!\n", pMixedCtx->ss.Attr.n.u2Dpl, uCpl));
2842	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2843	}
2844
2845	/*
2846	* Guest TR.
2847	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2848	* between Intel and AMD. See @bugref{6208#c39}.
2849	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2850	*/
2851	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2852	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2853	{
2854	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2855	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2856	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2857	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2858	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2859	}
2860
2861	/*
2862	* Guest Descriptor-Table registers (GDTR, IDTR, LDTR).
2863	*/
2864	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2865	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2866	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2867
2868	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2869	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2870
2871	/*
2872	* Guest Debug registers.
2873	*/
2874	if (!pVCpu->hm.s.fUsingHyperDR7)
2875	{
2876	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2877	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2878	}
2879	else
2880	{
2881	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2882	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2883	}
2884
2885	/*
2886	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2887	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2888	*/
2889	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2890	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2891	{
2892	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2893	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2894	}
2895
2896	#ifdef VBOX_STRICT
2897	if (CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2898	hmR0SvmLogState(pVCpu, pVmcb, pMixedCtx, "hmR0SvmSaveGuestStateNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR, 0 /* uVerbose */);
2899	#endif
2900	}
2901
2902
2903	/**
2904	* Does the necessary state syncing before returning to ring-3 for any reason
2905	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2906	*
2907	* @param pVCpu The cross context virtual CPU structure.
2908	*
2909	* @remarks No-long-jmp zone!!!
2910	*/
2911	static void hmR0SvmLeave(PVMCPU pVCpu)
2912	{
2913	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2914	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2915	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2916
2917	/*
2918	* !!! IMPORTANT !!!
2919	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2920	*/
2921
2922	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2923	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2924	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); /** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2925
2926	/*
2927	* Restore host debug registers if necessary and resync on next R0 reentry.
2928	*/
2929	#ifdef VBOX_STRICT
2930	if (CPUMIsHyperDebugStateActive(pVCpu))
2931	{
2932	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2933	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2934	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2935	}
2936	#endif
2937	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2938	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);/** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2939
2940	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2941	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2942
2943	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2944	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2945	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2946	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2947	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2948
2949	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2950	}
2951
2952
2953	/**
2954	* Leaves the AMD-V session.
2955	*
2956	* @returns VBox status code.
2957	* @param pVCpu The cross context virtual CPU structure.
2958	*/
2959	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2960	{
2961	HM_DISABLE_PREEMPT();
2962	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2963	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2964
2965	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2966	and done this from the SVMR0ThreadCtxCallback(). */
2967	if (!pVCpu->hm.s.fLeaveDone)
2968	{
2969	hmR0SvmLeave(pVCpu);
2970	pVCpu->hm.s.fLeaveDone = true;
2971	}
2972
2973	/*
2974	* !!! IMPORTANT !!!
2975	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2976	*/
2977
2978	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2979	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2980	VMMR0ThreadCtxHookDisable(pVCpu);
2981
2982	/* Leave HM context. This takes care of local init (term). */
2983	int rc = HMR0LeaveCpu(pVCpu);
2984
2985	HM_RESTORE_PREEMPT();
2986	return rc;
2987	}
2988
2989
2990	/**
2991	* Does the necessary state syncing before doing a longjmp to ring-3.
2992	*
2993	* @returns VBox status code.
2994	* @param pVCpu The cross context virtual CPU structure.
2995	*
2996	* @remarks No-long-jmp zone!!!
2997	*/
2998	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2999	{
3000	return hmR0SvmLeaveSession(pVCpu);
3001	}
3002
3003
3004	/**
3005	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3006	* any remaining host state) before we longjump to ring-3 and possibly get
3007	* preempted.
3008	*
3009	* @param pVCpu The cross context virtual CPU structure.
3010	* @param enmOperation The operation causing the ring-3 longjump.
3011	* @param pvUser The user argument (pointer to the possibly
3012	* out-of-date guest-CPU context).
3013	*/
3014	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
3015	{
3016	RT_NOREF_PV(pvUser);
3017
3018	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3019	{
3020	/*
3021	* !!! IMPORTANT !!!
3022	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3023	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3024	*/
3025	VMMRZCallRing3RemoveNotification(pVCpu);
3026	VMMRZCallRing3Disable(pVCpu);
3027	HM_DISABLE_PREEMPT();
3028
3029	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3030	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3031
3032	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3033	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3034
3035	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3036	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3037	VMMR0ThreadCtxHookDisable(pVCpu);
3038
3039	/* Leave HM context. This takes care of local init (term). */
3040	HMR0LeaveCpu(pVCpu);
3041
3042	HM_RESTORE_PREEMPT();
3043	return VINF_SUCCESS;
3044	}
3045
3046	Assert(pVCpu);
3047	Assert(pvUser);
3048	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3049	HMSVM_ASSERT_PREEMPT_SAFE();
3050
3051	VMMRZCallRing3Disable(pVCpu);
3052	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3053
3054	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
3055	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3056	AssertRCReturn(rc, rc);
3057
3058	VMMRZCallRing3Enable(pVCpu);
3059	return VINF_SUCCESS;
3060	}
3061
3062
3063	/**
3064	* Take necessary actions before going back to ring-3.
3065	*
3066	* An action requires us to go back to ring-3. This function does the necessary
3067	* steps before we can safely return to ring-3. This is not the same as longjmps
3068	* to ring-3, this is voluntary.
3069	*
3070	* @returns VBox status code.
3071	* @param pVM The cross context VM structure.
3072	* @param pVCpu The cross context virtual CPU structure.
3073	* @param pCtx Pointer to the guest-CPU context.
3074	* @param rcExit The reason for exiting to ring-3. Can be
3075	* VINF_VMM_UNKNOWN_RING3_CALL.
3076	*/
3077	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
3078	{
3079	Assert(pVM);
3080	Assert(pVCpu);
3081	Assert(pCtx);
3082	HMSVM_ASSERT_PREEMPT_SAFE();
3083
3084	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3085	VMMRZCallRing3Disable(pVCpu);
3086	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
3087	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
3088
3089	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3090	if (pVCpu->hm.s.Event.fPending)
3091	{
3092	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3093	Assert(!pVCpu->hm.s.Event.fPending);
3094	}
3095
3096	/* Sync. the necessary state for going back to ring-3. */
3097	hmR0SvmLeaveSession(pVCpu);
3098	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3099
3100	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3101	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3102	\| CPUM_CHANGED_LDTR
3103	\| CPUM_CHANGED_GDTR
3104	\| CPUM_CHANGED_IDTR
3105	\| CPUM_CHANGED_TR
3106	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3107	if ( pVM->hm.s.fNestedPaging
3108	&& CPUMIsGuestPagingEnabledEx(pCtx))
3109	{
3110	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3111	}
3112
3113	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
3114	if (rcExit != VINF_EM_RAW_INTERRUPT)
3115	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3116
3117	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3118
3119	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
3120	VMMRZCallRing3RemoveNotification(pVCpu);
3121	VMMRZCallRing3Enable(pVCpu);
3122
3123	/*
3124	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3125	* and if we're injecting an event we should have a TRPM trap pending.
3126	*/
3127	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3128	pVCpu->hm.s.u32HMError = rcExit,
3129	VERR_SVM_IPE_5);
3130	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3131	pVCpu->hm.s.u32HMError = rcExit,
3132	VERR_SVM_IPE_4);
3133
3134	return rcExit;
3135	}
3136
3137
3138	/**
3139	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3140	* intercepts.
3141	*
3142	* @param pVM The cross context VM structure.
3143	* @param pVCpu The cross context virtual CPU structure.
3144	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
3145	* @param pVmcb Pointer to the VM control block.
3146	*
3147	* @remarks No-long-jump zone!!!
3148	*/
3149	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3150	{
3151	/*
3152	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3153	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3154	* RDTSC/RDTSCP as well.
3155	*/
3156	bool fParavirtTsc;
3157	uint64_t uTscOffset;
3158	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
3159
3160	bool fIntercept;
3161	if (fCanUseRealTsc)
3162	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pCtx, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3163	else
3164	{
3165	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3166	fIntercept = true;
3167	}
3168
3169	if (!fIntercept)
3170	{
3171	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3172	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3173	uTscOffset = HMSvmNstGstApplyTscOffset(pVCpu, uTscOffset);
3174
3175	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3176	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3177	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3178
3179	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
3180	}
3181	else
3182	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
3183
3184	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3185	information before every VM-entry, hence we have nothing to do here at the moment. */
3186	if (fParavirtTsc)
3187	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3188	}
3189
3190
3191	/**
3192	* Sets an event as a pending event to be injected into the guest.
3193	*
3194	* @param pVCpu The cross context virtual CPU structure.
3195	* @param pEvent Pointer to the SVM event.
3196	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3197	* page-fault.
3198	*
3199	* @remarks Statistics counter assumes this is a guest event being reflected to
3200	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3201	*/
3202	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3203	{
3204	Assert(!pVCpu->hm.s.Event.fPending);
3205	Assert(pEvent->n.u1Valid);
3206
3207	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3208	pVCpu->hm.s.Event.fPending = true;
3209	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3210
3211	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3212	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3213	}
3214
3215
3216	/**
3217	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3218	*
3219	* @param pVCpu The cross context virtual CPU structure.
3220	*/
3221	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3222	{
3223	SVMEVENT Event;
3224	Event.u = 0;
3225	Event.n.u1Valid = 1;
3226	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3227	Event.n.u8Vector = X86_XCPT_UD;
3228	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3229	}
3230
3231
3232	/**
3233	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3234	*
3235	* @param pVCpu The cross context virtual CPU structure.
3236	*/
3237	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3238	{
3239	SVMEVENT Event;
3240	Event.u = 0;
3241	Event.n.u1Valid = 1;
3242	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3243	Event.n.u8Vector = X86_XCPT_DB;
3244	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3245	}
3246
3247
3248	/**
3249	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3250	*
3251	* @param pVCpu The cross context virtual CPU structure.
3252	* @param pCtx Pointer to the guest-CPU context.
3253	* @param u32ErrCode The error-code for the page-fault.
3254	* @param uFaultAddress The page fault address (CR2).
3255	*
3256	* @remarks This updates the guest CR2 with @a uFaultAddress!
3257	*/
3258	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3259	{
3260	SVMEVENT Event;
3261	Event.u = 0;
3262	Event.n.u1Valid = 1;
3263	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3264	Event.n.u8Vector = X86_XCPT_PF;
3265	Event.n.u1ErrorCodeValid = 1;
3266	Event.n.u32ErrorCode = u32ErrCode;
3267
3268	/* Update CR2 of the guest. */
3269	if (pCtx->cr2 != uFaultAddress)
3270	{
3271	pCtx->cr2 = uFaultAddress;
3272	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3273	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3274	}
3275
3276	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3277	}
3278
3279
3280	/**
3281	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3282	*
3283	* @param pVCpu The cross context virtual CPU structure.
3284	*/
3285	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3286	{
3287	SVMEVENT Event;
3288	Event.u = 0;
3289	Event.n.u1Valid = 1;
3290	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3291	Event.n.u8Vector = X86_XCPT_MF;
3292	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3293	}
3294
3295
3296	/**
3297	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3298	*
3299	* @param pVCpu The cross context virtual CPU structure.
3300	*/
3301	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3302	{
3303	SVMEVENT Event;
3304	Event.u = 0;
3305	Event.n.u1Valid = 1;
3306	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3307	Event.n.u8Vector = X86_XCPT_DF;
3308	Event.n.u1ErrorCodeValid = 1;
3309	Event.n.u32ErrorCode = 0;
3310	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3311	}
3312
3313
3314	/**
3315	* Injects an event into the guest upon VMRUN by updating the relevant field
3316	* in the VMCB.
3317	*
3318	* @param pVCpu The cross context virtual CPU structure.
3319	* @param pVmcb Pointer to the guest VM control block.
3320	* @param pCtx Pointer to the guest-CPU context.
3321	* @param pEvent Pointer to the event.
3322	*
3323	* @remarks No-long-jump zone!!!
3324	* @remarks Requires CR0!
3325	*/
3326	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
3327	{
3328	NOREF(pVCpu); NOREF(pCtx);
3329
3330	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3331	pVmcb->ctrl.EventInject.u = pEvent->u;
3332	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3333
3334	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3335	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3336	}
3337
3338
3339
3340	/**
3341	* Converts any TRPM trap into a pending HM event. This is typically used when
3342	* entering from ring-3 (not longjmp returns).
3343	*
3344	* @param pVCpu The cross context virtual CPU structure.
3345	*/
3346	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3347	{
3348	Assert(TRPMHasTrap(pVCpu));
3349	Assert(!pVCpu->hm.s.Event.fPending);
3350
3351	uint8_t uVector;
3352	TRPMEVENT enmTrpmEvent;
3353	RTGCUINT uErrCode;
3354	RTGCUINTPTR GCPtrFaultAddress;
3355	uint8_t cbInstr;
3356
3357	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3358	AssertRC(rc);
3359
3360	SVMEVENT Event;
3361	Event.u = 0;
3362	Event.n.u1Valid = 1;
3363	Event.n.u8Vector = uVector;
3364
3365	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3366	if (enmTrpmEvent == TRPM_TRAP)
3367	{
3368	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3369	switch (uVector)
3370	{
3371	case X86_XCPT_NMI:
3372	{
3373	Event.n.u3Type = SVM_EVENT_NMI;
3374	break;
3375	}
3376
3377	case X86_XCPT_PF:
3378	case X86_XCPT_DF:
3379	case X86_XCPT_TS:
3380	case X86_XCPT_NP:
3381	case X86_XCPT_SS:
3382	case X86_XCPT_GP:
3383	case X86_XCPT_AC:
3384	{
3385	Event.n.u1ErrorCodeValid = 1;
3386	Event.n.u32ErrorCode = uErrCode;
3387	break;
3388	}
3389	}
3390	}
3391	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3392	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3393	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3394	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3395	else
3396	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3397
3398	rc = TRPMResetTrap(pVCpu);
3399	AssertRC(rc);
3400
3401	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3402	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3403
3404	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3405	}
3406
3407
3408	/**
3409	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3410	* AMD-V to execute any instruction.
3411	*
3412	* @param pVCpu The cross context virtual CPU structure.
3413	*/
3414	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3415	{
3416	Assert(pVCpu->hm.s.Event.fPending);
3417	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3418
3419	SVMEVENT Event;
3420	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3421
3422	uint8_t uVector = Event.n.u8Vector;
3423	uint8_t uVectorType = Event.n.u3Type;
3424	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3425
3426	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3427
3428	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3429	AssertRC(rc);
3430
3431	if (Event.n.u1ErrorCodeValid)
3432	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3433
3434	if ( uVectorType == SVM_EVENT_EXCEPTION
3435	&& uVector == X86_XCPT_PF)
3436	{
3437	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3438	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3439	}
3440	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3441	{
3442	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3443	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3444	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3445	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3446	}
3447	pVCpu->hm.s.Event.fPending = false;
3448	}
3449
3450
3451	/**
3452	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3453	* now.
3454	*
3455	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3456	* @param pVCpu The cross context virtual CPU structure.
3457	* @param pCtx Pointer to the guest-CPU context.
3458	*
3459	* @remarks No-long-jump zone!!!
3460	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3461	*/
3462	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
3463	{
3464	/*
3465	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
3466	* inhibit interrupts or clear any existing interrupt-inhibition.
3467	*/
3468	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3469	{
3470	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
3471	{
3472	/*
3473	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3474	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
3475	*/
3476	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3477	return false;
3478	}
3479	return true;
3480	}
3481	return false;
3482	}
3483
3484
3485	/**
3486	* Sets the virtual interrupt intercept control in the VMCB.
3487	*
3488	* @param pVmcb Pointer to the VM control block.
3489	*/
3490	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
3491	{
3492	/*
3493	* When AVIC isn't supported, indicate that a virtual interrupt is pending and to
3494	* cause a #VMEXIT when the guest is ready to accept interrupts. At #VMEXIT, we
3495	* then get the interrupt from the APIC (updating ISR at the right time) and
3496	* inject the interrupt.
3497	*
3498	* With AVIC is supported, we could make use of the asynchronously delivery without
3499	* #VMEXIT and we would be passing the AVIC page to SVM.
3500	*/
3501	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3502	{
3503	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 0);
3504	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3505	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
3506	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3507	Log4(("Set VINTR intercept\n"));
3508	}
3509	}
3510
3511
3512	/**
3513	* Clears the virtual interrupt intercept control in the VMCB as
3514	* we are figured the guest is unable process any interrupts
3515	* at this point of time.
3516	*
3517	* @param pVmcb Pointer to the VM control block.
3518	*/
3519	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
3520	{
3521	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3522	{
3523	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 1);
3524	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
3525	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3526	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3527	Log4(("Cleared VINTR intercept\n"));
3528	}
3529	}
3530
3531
3532	/**
3533	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3534	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3535	* virtual NMIs.
3536	*
3537	* @param pVmcb Pointer to the VM control block.
3538	*/
3539	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3540	{
3541	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3542	{
3543	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3544	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3545
3546	Log4(("Setting IRET intercept\n"));
3547	}
3548	}
3549
3550
3551	/**
3552	* Clears the IRET intercept control in the VMCB.
3553	*
3554	* @param pVmcb Pointer to the VM control block.
3555	*/
3556	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3557	{
3558	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3559	{
3560	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3561	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3562
3563	Log4(("Clearing IRET intercept\n"));
3564	}
3565	}
3566
3567	#ifdef VBOX_WITH_NESTED_HWVIRT
3568
3569
3570	/**
3571	* Evaluates the event to be delivered to the nested-guest and sets it as the
3572	* pending event.
3573	*
3574	* @returns VBox strict status code.
3575	* @param pVCpu The cross context virtual CPU structure.
3576	* @param pCtx Pointer to the guest-CPU context.
3577	*/
3578	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3579	{
3580	Log4Func(("\n"));
3581
3582	Assert(!pVCpu->hm.s.Event.fPending);
3583
3584	bool const fGif = pCtx->hwvirt.fGif;
3585	if (fGif)
3586	{
3587	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3588
3589	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3590
3591	/*
3592	* Check if the nested-guest can receive NMIs.
3593	* NMIs are higher priority than regular interrupts.
3594	*/
3595	/** @todo SMI. SMIs take priority over NMIs. */
3596	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3597	{
3598	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3599	if (fBlockNmi)
3600	hmR0SvmSetIretIntercept(pVmcbNstGst);
3601	else if (fIntShadow)
3602	{
3603	/** @todo Figure this out, how we shall manage virt. intercept if the
3604	* nested-guest already has one set and/or if we really need it? */
3605	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3606	}
3607	else
3608	{
3609	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3610	{
3611	Log4(("Intercepting NMI -> #VMEXIT\n"));
3612	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3613	}
3614
3615	Log4(("Pending NMI\n"));
3616	SVMEVENT Event;
3617	Event.u = 0;
3618	Event.n.u1Valid = 1;
3619	Event.n.u8Vector = X86_XCPT_NMI;
3620	Event.n.u3Type = SVM_EVENT_NMI;
3621	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3622	hmR0SvmSetIretIntercept(pVmcbNstGst);
3623	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3624	return VINF_SUCCESS;
3625	}
3626	}
3627
3628	/*
3629	* Check if the nested-guest can receive external interrupts (generated by
3630	* the guest's PIC/APIC).
3631	*
3632	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3633	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3634	*
3635	* External interrupts that are generated for the outer guest may be intercepted
3636	* depending on how the nested-guest VMCB was programmed by guest software.
3637	*
3638	* Physical interrupts always take priority over virtual interrupts,
3639	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3640	*/
3641	if (!fIntShadow)
3642	{
3643	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3644	&& !pVCpu->hm.s.fSingleInstruction
3645	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3646	{
3647	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3648	{
3649	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3650	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3651	}
3652
3653	uint8_t u8Interrupt;
3654	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3655	if (RT_SUCCESS(rc))
3656	{
3657	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3658	SVMEVENT Event;
3659	Event.u = 0;
3660	Event.n.u1Valid = 1;
3661	Event.n.u8Vector = u8Interrupt;
3662	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3663	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3664	}
3665	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3666	{
3667	/*
3668	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3669	* updated eventually when the TPR is written by the guest.
3670	*/
3671	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3672	}
3673	else
3674	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3675	}
3676
3677	/*
3678	* Check if the nested-guest is intercepting virtual (using V_IRQ and related fields)
3679	* interrupt injection. The virtual interrupt injection itself, if any, will be done
3680	* by the physical CPU.
3681	*/
3682	/** @todo later explore this for performance reasons. Right now the hardware
3683	* takes care of virtual interrupt injection for nested-guest. */
3684	#if 0
3685	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3686	&& CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR)
3687	&& CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx))
3688	{
3689	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3690	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3691	}
3692	#endif
3693	}
3694	}
3695
3696	return VINF_SUCCESS;
3697	}
3698	#endif
3699
3700
3701	/**
3702	* Evaluates the event to be delivered to the guest and sets it as the pending
3703	* event.
3704	*
3705	* @param pVCpu The cross context virtual CPU structure.
3706	* @param pCtx Pointer to the guest-CPU context.
3707	*
3708	* @remarks Don't use this function when we are actively executing a
3709	* nested-guest, use hmR0SvmEvaluatePendingEventNested instead.
3710	*/
3711	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3712	{
3713	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3714	Assert(!pVCpu->hm.s.Event.fPending);
3715
3716	#ifdef VBOX_WITH_NESTED_HWVIRT
3717	bool const fGif = pCtx->hwvirt.fGif;
3718	#else
3719	bool const fGif = true;
3720	#endif
3721	Log4Func(("fGif=%RTbool\n", fGif));
3722
3723	/*
3724	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3725	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3726	*/
3727	if (fGif)
3728	{
3729	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3730	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3731	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3732	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3733
3734	Log4Func(("fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fBlockInt, fIntShadow,
3735	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3736
3737	/** @todo SMI. SMIs take priority over NMIs. */
3738	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3739	{
3740	if (fBlockNmi)
3741	hmR0SvmSetIretIntercept(pVmcb);
3742	else if (fIntShadow)
3743	hmR0SvmSetVirtIntrIntercept(pVmcb);
3744	else
3745	{
3746	Log4(("Pending NMI\n"));
3747
3748	SVMEVENT Event;
3749	Event.u = 0;
3750	Event.n.u1Valid = 1;
3751	Event.n.u8Vector = X86_XCPT_NMI;
3752	Event.n.u3Type = SVM_EVENT_NMI;
3753
3754	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3755	hmR0SvmSetIretIntercept(pVmcb);
3756	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3757	return;
3758	}
3759	}
3760	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3761	&& !pVCpu->hm.s.fSingleInstruction)
3762	{
3763	/*
3764	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3765	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3766	*/
3767	if ( !fBlockInt
3768	&& !fIntShadow)
3769	{
3770	uint8_t u8Interrupt;
3771	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3772	if (RT_SUCCESS(rc))
3773	{
3774	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3775
3776	SVMEVENT Event;
3777	Event.u = 0;
3778	Event.n.u1Valid = 1;
3779	Event.n.u8Vector = u8Interrupt;
3780	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3781
3782	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3783	}
3784	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3785	{
3786	/*
3787	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3788	* updated eventually when the TPR is written by the guest.
3789	*/
3790	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3791	}
3792	else
3793	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3794	}
3795	else
3796	hmR0SvmSetVirtIntrIntercept(pVmcb);
3797	}
3798	}
3799	}
3800
3801
3802	/**
3803	* Injects any pending events into the guest (or nested-guest).
3804	*
3805	* @param pVCpu The cross context virtual CPU structure.
3806	* @param pCtx Pointer to the guest-CPU context.
3807	* @param pVmcb Pointer to the VM control block.
3808	*/
3809	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3810	{
3811	Assert(!TRPMHasTrap(pVCpu));
3812	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3813
3814	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3815	#ifdef VBOX_STRICT
3816	bool const fGif = pCtx->hwvirt.fGif;
3817	bool fAllowInt = fGif;
3818	if (fGif)
3819	{
3820	/*
3821	* For nested-guests we have no way to determine if we're injecting a physical or virtual
3822	* interrupt at this point. Hence the partial verification below.
3823	*/
3824	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3825	fAllowInt = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx) \|\| CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx);
3826	else
3827	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3828	}
3829	#endif
3830
3831	if (pVCpu->hm.s.Event.fPending)
3832	{
3833	SVMEVENT Event;
3834	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3835	Assert(Event.n.u1Valid);
3836
3837	/*
3838	* Validate event injection pre-conditions.
3839	*/
3840	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3841	{
3842	Assert(fAllowInt);
3843	Assert(!fIntShadow);
3844	}
3845	else if (Event.n.u3Type == SVM_EVENT_NMI)
3846	{
3847	Assert(fGif);
3848	Assert(!fIntShadow);
3849	}
3850
3851	/*
3852	* Inject it (update VMCB for injection by the hardware).
3853	*/
3854	Log4(("Injecting pending HM event\n"));
3855	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3856	pVCpu->hm.s.Event.fPending = false;
3857
3858	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3859	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3860	else
3861	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3862	}
3863	else
3864	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3865
3866	/*
3867	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3868	*
3869	* For nested-guests: We need to update it too for the scenario where IEM executes
3870	* the nested-guest but execution later continues here with an interrupt shadow active.
3871	*/
3872	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3873	}
3874
3875
3876	/**
3877	* Reports world-switch error and dumps some useful debug info.
3878	*
3879	* @param pVM The cross context VM structure.
3880	* @param pVCpu The cross context virtual CPU structure.
3881	* @param rcVMRun The return code from VMRUN (or
3882	* VERR_SVM_INVALID_GUEST_STATE for invalid
3883	* guest-state).
3884	* @param pCtx Pointer to the guest-CPU context.
3885	*/
3886	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3887	{
3888	NOREF(pCtx);
3889	HMSVM_ASSERT_PREEMPT_SAFE();
3890	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3891	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3892
3893	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3894	{
3895	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3896	#ifdef VBOX_STRICT
3897	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3898	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3899	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3900	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3901	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3902	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3903	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3904	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3905	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3906	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3907
3908	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3909	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3910	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3911
3912	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3913	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3914	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3915	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3916	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3917	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3918	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3919	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3920	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3921	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3922	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3923	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3924
3925	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3926	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3927	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3928	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3929	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3930	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3931	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3932	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3933	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3934	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3935	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3936	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3937	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3938	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3939	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3940	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3941	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3942	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3943	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3944	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3945
3946	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3947
3948	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3949	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3950
3951	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3952	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3953	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3954	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3955	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3956	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3957	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3958	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3959	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3960	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3961	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3962	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3963	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3964	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3965	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3966	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3967	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3968	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3969	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3970	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3971
3972	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3973	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3974
3975	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3976	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3977	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3978	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3979
3980	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3981	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3982
3983	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3984	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3985	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3986	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3987
3988	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3989	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3990	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3991	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3992	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3993	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3994	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3995
3996	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3997	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3998	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3999	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
4000
4001	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
4002	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
4003	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
4004
4005	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
4006	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
4007	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
4008	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
4009	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
4010	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
4011	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
4012	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
4013	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
4014	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
4015	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
4016	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
4017	#endif /* VBOX_STRICT */
4018	}
4019	else
4020	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
4021
4022	NOREF(pVmcb);
4023	}
4024
4025
4026	/**
4027	* Check per-VM and per-VCPU force flag actions that require us to go back to
4028	* ring-3 for one reason or another.
4029	*
4030	* @returns VBox status code (information status code included).
4031	* @retval VINF_SUCCESS if we don't have any actions that require going back to
4032	* ring-3.
4033	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
4034	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
4035	* interrupts)
4036	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
4037	* all EMTs to be in ring-3.
4038	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
4039	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
4040	* to the EM loop.
4041	*
4042	* @param pVM The cross context VM structure.
4043	* @param pVCpu The cross context virtual CPU structure.
4044	* @param pCtx Pointer to the guest-CPU context.
4045	*/
4046	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4047	{
4048	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4049
4050	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
4051	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
4052	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
4053
4054	/* Update pending interrupts into the APIC's IRR. */
4055	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
4056	APICUpdatePendingInterrupts(pVCpu);
4057
4058	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
4059	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
4060	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
4061	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
4062	{
4063	/* Pending PGM C3 sync. */
4064	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4065	{
4066	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4067	if (rc != VINF_SUCCESS)
4068	{
4069	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4070	return rc;
4071	}
4072	}
4073
4074	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4075	/* -XXX- what was that about single stepping? */
4076	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
4077	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4078	{
4079	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4080	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
4081	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4082	return rc;
4083	}
4084
4085	/* Pending VM request packets, such as hardware interrupts. */
4086	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
4087	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
4088	{
4089	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
4090	return VINF_EM_PENDING_REQUEST;
4091	}
4092
4093	/* Pending PGM pool flushes. */
4094	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4095	{
4096	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
4097	return VINF_PGM_POOL_FLUSH_PENDING;
4098	}
4099
4100	/* Pending DMA requests. */
4101	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
4102	{
4103	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
4104	return VINF_EM_RAW_TO_R3;
4105	}
4106	}
4107
4108	return VINF_SUCCESS;
4109	}
4110
4111
4112	#ifdef VBOX_WITH_NESTED_HWVIRT
4113	/**
4114	* Does the preparations before executing nested-guest code in AMD-V.
4115	*
4116	* @returns VBox status code (informational status codes included).
4117	* @retval VINF_SUCCESS if we can proceed with running the guest.
4118	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4119	*
4120	* @param pVM The cross context VM structure.
4121	* @param pVCpu The cross context virtual CPU structure.
4122	* @param pCtx Pointer to the nested-guest-CPU context.
4123	* @param pSvmTransient Pointer to the SVM transient structure.
4124	*
4125	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
4126	* @sa hmR0SvmPreRunGuest.
4127	*/
4128	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4129	{
4130	HMSVM_ASSERT_PREEMPT_SAFE();
4131
4132	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4133	{
4134	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4135	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4136	return VINF_EM_RESCHEDULE_REM;
4137	#endif
4138	}
4139	else
4140	return VINF_SVM_VMEXIT;
4141
4142	/* Check force flag actions that might require us to go back to ring-3. */
4143	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
4144	if (rc != VINF_SUCCESS)
4145	return rc;
4146
4147	if (TRPMHasTrap(pVCpu))
4148	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4149	else if (!pVCpu->hm.s.Event.fPending)
4150	{
4151	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
4152	if (rcStrict != VINF_SUCCESS)
4153	return VBOXSTRICTRC_VAL(rcStrict);
4154	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4155	return VINF_SVM_VMEXIT;
4156	}
4157
4158	/*
4159	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4160	* Just do it in software, see @bugref{8411}.
4161	* NB: If we could continue a task switch exit we wouldn't need to do this.
4162	*/
4163	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4164	&& pVCpu->hm.s.Event.fPending
4165	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4166	{
4167	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4168	}
4169
4170	#ifdef HMSVM_SYNC_FULL_NESTED_GUEST_STATE
4171	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4172	#endif
4173
4174	/*
4175	* Set up the nested-guest VMCB for execution using hardware-assisted SVM.
4176	*/
4177	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
4178
4179	/*
4180	* Load the nested-guest state.
4181	*/
4182	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
4183	AssertRCReturn(rc, rc);
4184	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */
4185
4186	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware-assisted SVM. */
4187	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
4188
4189	/*
4190	* No longjmps to ring-3 from this point on!!!
4191	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4192	* This also disables flushing of the R0-logger instance (if any).
4193	*/
4194	VMMRZCallRing3Disable(pVCpu);
4195
4196	/*
4197	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4198	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4199	*
4200	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4201	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4202	*
4203	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4204	* executing guest code.
4205	*/
4206	pSvmTransient->fEFlags = ASMIntDisableFlags();
4207	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4208	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4209	{
4210	ASMSetFlags(pSvmTransient->fEFlags);
4211	VMMRZCallRing3Enable(pVCpu);
4212	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4213	return VINF_EM_RAW_TO_R3;
4214	}
4215	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4216	{
4217	ASMSetFlags(pSvmTransient->fEFlags);
4218	VMMRZCallRing3Enable(pVCpu);
4219	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4220	return VINF_EM_RAW_INTERRUPT;
4221	}
4222
4223	/*
4224	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4225	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4226	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4227	*
4228	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4229	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4230	*/
4231	if (pVCpu->hm.s.Event.fPending)
4232	{
4233	SVMEVENT Event;
4234	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4235	if ( Event.n.u1Valid
4236	&& Event.n.u3Type == SVM_EVENT_NMI
4237	&& Event.n.u8Vector == X86_XCPT_NMI
4238	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4239	{
4240	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4241	}
4242	}
4243
4244	return VINF_SUCCESS;
4245	}
4246	#endif
4247
4248
4249	/**
4250	* Does the preparations before executing guest code in AMD-V.
4251	*
4252	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4253	* recompiler. We must be cautious what we do here regarding committing
4254	* guest-state information into the VMCB assuming we assuredly execute the guest
4255	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4256	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4257	* that the recompiler can (and should) use them when it resumes guest
4258	* execution. Otherwise such operations must be done when we can no longer
4259	* exit to ring-3.
4260	*
4261	* @returns VBox status code (informational status codes included).
4262	* @retval VINF_SUCCESS if we can proceed with running the guest.
4263	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4264	*
4265	* @param pVM The cross context VM structure.
4266	* @param pVCpu The cross context virtual CPU structure.
4267	* @param pCtx Pointer to the guest-CPU context.
4268	* @param pSvmTransient Pointer to the SVM transient structure.
4269	*/
4270	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4271	{
4272	HMSVM_ASSERT_PREEMPT_SAFE();
4273	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4274
4275	/* Check force flag actions that might require us to go back to ring-3. */
4276	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
4277	if (rc != VINF_SUCCESS)
4278	return rc;
4279
4280	if (TRPMHasTrap(pVCpu))
4281	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4282	else if (!pVCpu->hm.s.Event.fPending)
4283	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
4284
4285	/*
4286	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4287	* Just do it in software, see @bugref{8411}.
4288	* NB: If we could continue a task switch exit we wouldn't need to do this.
4289	*/
4290	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4291	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4292	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4293
4294	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4295	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4296	#endif
4297
4298	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
4299	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
4300	AssertRCReturn(rc, rc);
4301	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
4302
4303	/*
4304	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
4305	* so we can update it on the way back if the guest changed the TPR.
4306	*/
4307	if (pVCpu->hm.s.svm.fSyncVTpr)
4308	{
4309	if (pVM->hm.s.fTPRPatchingActive)
4310	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
4311	else
4312	{
4313	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4314	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4315	}
4316	}
4317
4318	/*
4319	* No longjmps to ring-3 from this point on!!!
4320	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4321	* This also disables flushing of the R0-logger instance (if any).
4322	*/
4323	VMMRZCallRing3Disable(pVCpu);
4324
4325	/*
4326	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4327	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4328	*
4329	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4330	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4331	*
4332	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4333	* executing guest code.
4334	*/
4335	pSvmTransient->fEFlags = ASMIntDisableFlags();
4336	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4337	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4338	{
4339	ASMSetFlags(pSvmTransient->fEFlags);
4340	VMMRZCallRing3Enable(pVCpu);
4341	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4342	return VINF_EM_RAW_TO_R3;
4343	}
4344	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4345	{
4346	ASMSetFlags(pSvmTransient->fEFlags);
4347	VMMRZCallRing3Enable(pVCpu);
4348	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4349	return VINF_EM_RAW_INTERRUPT;
4350	}
4351
4352	/*
4353	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4354	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4355	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4356	*
4357	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4358	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4359	*/
4360	if (pVCpu->hm.s.Event.fPending)
4361	{
4362	SVMEVENT Event;
4363	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4364	if ( Event.n.u1Valid
4365	&& Event.n.u3Type == SVM_EVENT_NMI
4366	&& Event.n.u8Vector == X86_XCPT_NMI
4367	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4368	{
4369	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4370	}
4371	}
4372
4373	return VINF_SUCCESS;
4374	}
4375
4376
4377	/**
4378	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4379	* doing so.
4380	*
4381	* This means there is no backing out to ring-3 or anywhere else at this point.
4382	*
4383	* @param pVCpu The cross context virtual CPU structure.
4384	* @param pCtx Pointer to the guest-CPU context.
4385	* @param pSvmTransient Pointer to the SVM transient structure.
4386	*
4387	* @remarks Called with preemption disabled.
4388	* @remarks No-long-jump zone!!!
4389	*/
4390	static void hmR0SvmPreRunGuestCommitted(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4391	{
4392	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4393	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4394	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4395
4396	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4397	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4398
4399	PVM pVM = pVCpu->CTX_SUFF(pVM);
4400	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4401	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
4402
4403	if (!CPUMIsGuestFPUStateActive(pVCpu))
4404	{
4405	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4406	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4407	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4408	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4409	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4410	}
4411
4412	/* Load the state shared between host and guest (FPU, debug). */
4413	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4414	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
4415
4416	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4417	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4418
4419	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
4420	RTCPUID const idHostCpu = pHostCpu->idCpu;
4421	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4422
4423	/* Setup TSC offsetting. */
4424	if ( pSvmTransient->fUpdateTscOffsetting
4425	\|\| fMigratedHostCpu)
4426	{
4427	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pCtx, pVmcb);
4428	pSvmTransient->fUpdateTscOffsetting = false;
4429	}
4430
4431	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4432	if (fMigratedHostCpu)
4433	pVmcb->ctrl.u32VmcbCleanBits = 0;
4434
4435	/* Store status of the shared guest-host state at the time of VMRUN. */
4436	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4437	if (CPUMIsGuestInLongModeEx(pCtx))
4438	{
4439	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4440	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4441	}
4442	else
4443	#endif
4444	{
4445	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4446	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4447	}
4448
4449	uint8_t *pbMsrBitmap;
4450	if (!pSvmTransient->fIsNestedGuest)
4451	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4452	else
4453	{
4454	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu, pCtx);
4455
4456	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4457	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4458	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4459	}
4460
4461	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4462	/* Flush the appropriate tagged-TLB entries. */
4463	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb, pHostCpu);
4464	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4465
4466	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4467
4468	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4469	to start executing. */
4470
4471	/*
4472	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4473	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4474	*
4475	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4476	*/
4477	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4478	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4479	{
4480	uint64_t const uGuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4481	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4482	if (uGuestTscAux != pVCpu->hm.s.u64HostTscAux)
4483	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4484	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4485	pSvmTransient->fRestoreTscAuxMsr = true;
4486	}
4487	else
4488	{
4489	hmR0SvmSetMsrPermission(pCtx, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4490	pSvmTransient->fRestoreTscAuxMsr = false;
4491	}
4492	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4493
4494	/*
4495	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the
4496	* nested virtualization case, mark all state-bits as dirty indicating to the
4497	* CPU to re-load from VMCB.
4498	*/
4499	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4500	if (!fSupportsVmcbCleanBits)
4501	pVmcb->ctrl.u32VmcbCleanBits = 0;
4502	}
4503
4504
4505	/**
4506	* Wrapper for running the guest code in AMD-V.
4507	*
4508	* @returns VBox strict status code.
4509	* @param pVM The cross context VM structure.
4510	* @param pVCpu The cross context virtual CPU structure.
4511	* @param pCtx Pointer to the guest-CPU context.
4512	*
4513	* @remarks No-long-jump zone!!!
4514	*/
4515	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4516	{
4517	/*
4518	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4519	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4520	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4521	*/
4522	#ifdef VBOX_WITH_KERNEL_USING_XMM
4523	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4524	pVCpu->hm.s.svm.pfnVMRun);
4525	#else
4526	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4527	#endif
4528	}
4529
4530	#ifdef VBOX_WITH_NESTED_HWVIRT
4531	/**
4532	* Wrapper for running the nested-guest code in AMD-V.
4533	*
4534	* @returns VBox strict status code.
4535	* @param pVM The cross context VM structure.
4536	* @param pVCpu The cross context virtual CPU structure.
4537	* @param pCtx Pointer to the guest-CPU context.
4538	*
4539	* @remarks No-long-jump zone!!!
4540	*/
4541	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4542	{
4543	/*
4544	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4545	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4546	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4547	*/
4548	#ifdef VBOX_WITH_KERNEL_USING_XMM
4549	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4550	pVCpu->hm.s.svm.pfnVMRun);
4551	#else
4552	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4553	#endif
4554	}
4555	#endif
4556
4557	/**
4558	* Performs some essential restoration of state after running guest (or
4559	* nested-guest) code in AMD-V.
4560	*
4561	* @param pVCpu The cross context virtual CPU structure.
4562	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4563	* out-of-sync. Make sure to update the required fields
4564	* before using them.
4565	* @param pSvmTransient Pointer to the SVM transient structure.
4566	* @param rcVMRun Return code of VMRUN.
4567	*
4568	* @remarks Called with interrupts disabled.
4569	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4570	* unconditionally when it is safe to do so.
4571	*/
4572	static void hmR0SvmPostRunGuest(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4573	{
4574	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4575
4576	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4577	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4578	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4579
4580	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4581	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4582
4583	/* TSC read must be done early for maximum accuracy. */
4584	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4585	{
4586	if (!pSvmTransient->fIsNestedGuest)
4587	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4588	else
4589	{
4590	/*
4591	* Undo what we did in hmR0SvmUpdateTscOffsetting() and HMSvmNstGstApplyTscOffset()
4592	* but don't restore the nested-guest VMCB TSC offset here. It shall eventually be
4593	* restored on #VMEXIT in HMSvmNstGstVmExitNotify().
4594	*/
4595	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu, pMixedCtx);
4596	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset - pVmcbNstGstCache->u64TSCOffset);
4597	}
4598	}
4599
4600	if (pSvmTransient->fRestoreTscAuxMsr)
4601	{
4602	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4603	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4604	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4605	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4606	}
4607
4608	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4609	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4610	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4611
4612	Assert(!(ASMGetFlags() & X86_EFL_IF));
4613	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4614	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4615
4616	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4617	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4618	{
4619	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4620	return;
4621	}
4622
4623	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4624	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbCtrl->u64ExitCode); /* Update the #VMEXIT history array. */
4625	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4626	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4627	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4628
4629	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4630
4631	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4632	&& pVCpu->hm.s.svm.fSyncVTpr)
4633	{
4634	Assert(!pSvmTransient->fIsNestedGuest);
4635	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4636	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
4637	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4638	{
4639	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4640	AssertRC(rc);
4641	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
4642	}
4643	/* Sync TPR when we aren't intercepting CR8 writes. */
4644	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4645	{
4646	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4647	AssertRC(rc);
4648	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
4649	}
4650	}
4651	}
4652
4653
4654	/**
4655	* Runs the guest code using AMD-V.
4656	*
4657	* @returns VBox status code.
4658	* @param pVM The cross context VM structure.
4659	* @param pVCpu The cross context virtual CPU structure.
4660	* @param pCtx Pointer to the guest-CPU context.
4661	* @param pcLoops Pointer to the number of executed loops.
4662	*/
4663	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4664	{
4665	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4666	Assert(pcLoops);
4667	Assert(*pcLoops <= cMaxResumeLoops);
4668
4669	SVMTRANSIENT SvmTransient;
4670	RT_ZERO(SvmTransient);
4671	SvmTransient.fUpdateTscOffsetting = true;
4672	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4673
4674	int rc = VERR_INTERNAL_ERROR_5;
4675	for (;;)
4676	{
4677	Assert(!HMR0SuspendPending());
4678	HMSVM_ASSERT_CPU_SAFE();
4679
4680	/* Preparatory work for running guest code, this may force us to return
4681	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4682	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4683	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4684	if (rc != VINF_SUCCESS)
4685	break;
4686
4687	/*
4688	* No longjmps to ring-3 from this point on!!!
4689	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4690	* This also disables flushing of the R0-logger instance (if any).
4691	*/
4692	hmR0SvmPreRunGuestCommitted(pVCpu, pCtx, &SvmTransient);
4693	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4694
4695	/* Restore any residual host-state and save any bits shared between host
4696	and guest into the guest-CPU state. Re-enables interrupts! */
4697	hmR0SvmPostRunGuest(pVCpu, pCtx, &SvmTransient, rc);
4698
4699	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4700	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4701	{
4702	if (rc == VINF_SUCCESS)
4703	rc = VERR_SVM_INVALID_GUEST_STATE;
4704	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4705	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4706	break;
4707	}
4708
4709	/* Handle the #VMEXIT. */
4710	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4711	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4712	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4713	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4714	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4715	if (rc != VINF_SUCCESS)
4716	break;
4717	if (++(*pcLoops) >= cMaxResumeLoops)
4718	{
4719	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4720	rc = VINF_EM_RAW_INTERRUPT;
4721	break;
4722	}
4723	}
4724
4725	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4726	return rc;
4727	}
4728
4729
4730	/**
4731	* Runs the guest code using AMD-V in single step mode.
4732	*
4733	* @returns VBox status code.
4734	* @param pVM The cross context VM structure.
4735	* @param pVCpu The cross context virtual CPU structure.
4736	* @param pCtx Pointer to the guest-CPU context.
4737	* @param pcLoops Pointer to the number of executed loops.
4738	*/
4739	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4740	{
4741	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4742	Assert(pcLoops);
4743	Assert(*pcLoops <= cMaxResumeLoops);
4744
4745	SVMTRANSIENT SvmTransient;
4746	RT_ZERO(SvmTransient);
4747	SvmTransient.fUpdateTscOffsetting = true;
4748	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4749
4750	uint16_t uCsStart = pCtx->cs.Sel;
4751	uint64_t uRipStart = pCtx->rip;
4752
4753	int rc = VERR_INTERNAL_ERROR_5;
4754	for (;;)
4755	{
4756	Assert(!HMR0SuspendPending());
4757	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4758	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4759	(unsigned)RTMpCpuId(), *pcLoops));
4760
4761	/* Preparatory work for running guest code, this may force us to return
4762	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4763	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4764	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4765	if (rc != VINF_SUCCESS)
4766	break;
4767
4768	/*
4769	* No longjmps to ring-3 from this point on!!!
4770	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4771	* This also disables flushing of the R0-logger instance (if any).
4772	*/
4773	VMMRZCallRing3Disable(pVCpu);
4774	VMMRZCallRing3RemoveNotification(pVCpu);
4775	hmR0SvmPreRunGuestCommitted(pVCpu, pCtx, &SvmTransient);
4776
4777	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4778
4779	/*
4780	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4781	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4782	*/
4783	hmR0SvmPostRunGuest(pVCpu, pCtx, &SvmTransient, rc);
4784	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4785	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4786	{
4787	if (rc == VINF_SUCCESS)
4788	rc = VERR_SVM_INVALID_GUEST_STATE;
4789	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4790	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4791	return rc;
4792	}
4793
4794	/* Handle the #VMEXIT. */
4795	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4796	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4797	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4798	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4799	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4800	if (rc != VINF_SUCCESS)
4801	break;
4802	if (++(*pcLoops) >= cMaxResumeLoops)
4803	{
4804	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4805	rc = VINF_EM_RAW_INTERRUPT;
4806	break;
4807	}
4808
4809	/*
4810	* Did the RIP change, if so, consider it a single step.
4811	* Otherwise, make sure one of the TFs gets set.
4812	*/
4813	if ( pCtx->rip != uRipStart
4814	\|\| pCtx->cs.Sel != uCsStart)
4815	{
4816	rc = VINF_EM_DBG_STEPPED;
4817	break;
4818	}
4819	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4820	}
4821
4822	/*
4823	* Clear the X86_EFL_TF if necessary.
4824	*/
4825	if (pVCpu->hm.s.fClearTrapFlag)
4826	{
4827	pVCpu->hm.s.fClearTrapFlag = false;
4828	pCtx->eflags.Bits.u1TF = 0;
4829	}
4830
4831	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4832	return rc;
4833	}
4834
4835	#ifdef VBOX_WITH_NESTED_HWVIRT
4836	/**
4837	* Runs the nested-guest code using AMD-V.
4838	*
4839	* @returns VBox status code.
4840	* @param pVM The cross context VM structure.
4841	* @param pVCpu The cross context virtual CPU structure.
4842	* @param pCtx Pointer to the guest-CPU context.
4843	* @param pcLoops Pointer to the number of executed loops. If we're switching
4844	* from the guest-code execution loop to this nested-guest
4845	* execution loop pass the remainder value, else pass 0.
4846	*/
4847	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4848	{
4849	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4850	Assert(pcLoops);
4851	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4852
4853	SVMTRANSIENT SvmTransient;
4854	RT_ZERO(SvmTransient);
4855	SvmTransient.fUpdateTscOffsetting = true;
4856	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4857	SvmTransient.fIsNestedGuest = true;
4858
4859	int rc = VERR_INTERNAL_ERROR_4;
4860	for (;;)
4861	{
4862	Assert(!HMR0SuspendPending());
4863	HMSVM_ASSERT_CPU_SAFE();
4864
4865	/* Preparatory work for running nested-guest code, this may force us to return
4866	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4867	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4868	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4869	if ( rc != VINF_SUCCESS
4870	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4871	{
4872	break;
4873	}
4874
4875	/*
4876	* No longjmps to ring-3 from this point on!!!
4877	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4878	* This also disables flushing of the R0-logger instance (if any).
4879	*/
4880	hmR0SvmPreRunGuestCommitted(pVCpu, pCtx, &SvmTransient);
4881
4882	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4883
4884	/* Restore any residual host-state and save any bits shared between host
4885	and guest into the guest-CPU state. Re-enables interrupts! */
4886	hmR0SvmPostRunGuest(pVCpu, pCtx, &SvmTransient, rc);
4887
4888	if (RT_LIKELY( rc == VINF_SUCCESS
4889	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4890	{ /* extremely likely */ }
4891	else
4892	{
4893	/* VMRUN failed, shouldn't really happen, Guru. */
4894	if (rc != VINF_SUCCESS)
4895	break;
4896
4897	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4898	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4899	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4900	break;
4901	}
4902
4903	/* Handle the #VMEXIT. */
4904	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4905	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4906	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4907	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4908	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4909	if (rc != VINF_SUCCESS)
4910	break;
4911	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4912	{
4913	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4914	rc = VINF_EM_RAW_INTERRUPT;
4915	break;
4916	}
4917
4918	/** @todo handle single-stepping */
4919	}
4920
4921	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4922	return rc;
4923	}
4924	#endif
4925
4926
4927	/**
4928	* Runs the guest code using AMD-V.
4929	*
4930	* @returns Strict VBox status code.
4931	* @param pVM The cross context VM structure.
4932	* @param pVCpu The cross context virtual CPU structure.
4933	* @param pCtx Pointer to the guest-CPU context.
4934	*/
4935	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4936	{
4937	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4938	HMSVM_ASSERT_PREEMPT_SAFE();
4939	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4940
4941	uint32_t cLoops = 0;
4942	int rc;
4943	#ifdef VBOX_WITH_NESTED_HWVIRT
4944	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4945	#endif
4946	{
4947	if (!pVCpu->hm.s.fSingleInstruction)
4948	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4949	else
4950	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4951	}
4952	#ifdef VBOX_WITH_NESTED_HWVIRT
4953	else
4954	{
4955	rc = VINF_SVM_VMRUN;
4956	}
4957
4958	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4959	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4960	if (rc == VINF_SVM_VMRUN)
4961	{
4962	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4963	if (rc == VINF_SVM_VMEXIT)
4964	rc = VINF_SUCCESS;
4965	}
4966	#endif
4967
4968	/* Fixup error codes. */
4969	if (rc == VERR_EM_INTERPRETER)
4970	rc = VINF_EM_RAW_EMULATE_INSTR;
4971	else if (rc == VINF_EM_RESET)
4972	rc = VINF_EM_TRIPLE_FAULT;
4973
4974	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4975	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4976	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4977	return rc;
4978	}
4979
4980
4981	#ifdef VBOX_WITH_NESTED_HWVIRT
4982	/**
4983	* Determines whether an IOIO intercept is active for the nested-guest or not.
4984	*
4985	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4986	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4987	*/
4988	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4989	{
4990	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4991	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4992	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4993	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4994	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
4995	const bool fRep = pIoExitInfo->n.u1Rep;
4996	const bool fStrIo = pIoExitInfo->n.u1Str;
4997
4998	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4999	NULL /* pIoExitInfo */);
5000	}
5001
5002
5003	/**
5004	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
5005	* SVM_EXIT_INVALID).
5006	*
5007	* @returns VBox status code (informational status codes included).
5008	* @param pVCpu The cross context virtual CPU structure.
5009	* @param pCtx Pointer to the guest-CPU context.
5010	* @param pSvmTransient Pointer to the SVM transient structure.
5011	*/
5012	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5013	{
5014	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
5015	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5016	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5017
5018	#define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5019	VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
5020
5021	/*
5022	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
5023	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
5024	*/
5025	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
5026	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5027	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5028	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5029	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5030
5031	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5032	switch (uExitCode)
5033	{
5034	case SVM_EXIT_CPUID:
5035	{
5036	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
5037	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5038	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5039	}
5040
5041	case SVM_EXIT_RDTSC:
5042	{
5043	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
5044	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5045	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5046	}
5047
5048	case SVM_EXIT_RDTSCP:
5049	{
5050	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
5051	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5052	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5053	}
5054
5055	case SVM_EXIT_MONITOR:
5056	{
5057	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
5058	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5059	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5060	}
5061
5062	case SVM_EXIT_MWAIT:
5063	{
5064	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
5065	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5066	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5067	}
5068
5069	case SVM_EXIT_HLT:
5070	{
5071	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
5072	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5073	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5074	}
5075
5076	case SVM_EXIT_MSR:
5077	{
5078	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
5079	{
5080	uint32_t const idMsr = pCtx->ecx;
5081	uint16_t offMsrpm;
5082	uint8_t uMsrpmBit;
5083	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5084	if (RT_SUCCESS(rc))
5085	{
5086	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
5087	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
5088
5089	uint8_t const pbMsrBitmap = (uint8_t const )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5090	pbMsrBitmap += offMsrpm;
5091	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
5092	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
5093
5094	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5095	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5096	{
5097	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5098	}
5099	}
5100	else
5101	{
5102	/*
5103	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5104	* See AMD-V spec. "15.11 MSR Intercepts".
5105	*/
5106	Assert(rc == VERR_OUT_OF_RANGE);
5107	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5108	}
5109	}
5110	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5111	}
5112
5113	case SVM_EXIT_IOIO:
5114	{
5115	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
5116	{
5117	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
5118	SVMIOIOEXITINFO IoExitInfo;
5119	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5120	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
5121	if (fIntercept)
5122	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5123	}
5124	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5125	}
5126
5127	case SVM_EXIT_XCPT_PF:
5128	{
5129	PVM pVM = pVCpu->CTX_SUFF(pVM);
5130	if (pVM->hm.s.fNestedPaging)
5131	{
5132	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5133	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5134
5135	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5136	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5137	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5138
5139	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
5140	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5141	return VINF_SUCCESS;
5142	}
5143	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
5144	}
5145
5146	case SVM_EXIT_XCPT_UD:
5147	{
5148	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
5149	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5150	hmR0SvmSetPendingXcptUD(pVCpu);
5151	return VINF_SUCCESS;
5152	}
5153
5154	case SVM_EXIT_XCPT_MF:
5155	{
5156	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
5157	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5158	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5159	}
5160
5161	case SVM_EXIT_XCPT_DB:
5162	{
5163	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5164	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5165	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
5166	}
5167
5168	case SVM_EXIT_XCPT_AC:
5169	{
5170	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5171	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5172	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5173	}
5174
5175	case SVM_EXIT_XCPT_BP:
5176	{
5177	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5178	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5179	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
5180	}
5181
5182	case SVM_EXIT_READ_CR0:
5183	case SVM_EXIT_READ_CR3:
5184	case SVM_EXIT_READ_CR4:
5185	{
5186	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5187	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5188	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5189	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5190	}
5191
5192	case SVM_EXIT_CR0_SEL_WRITE:
5193	{
5194	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5195	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5196	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5197	}
5198
5199	case SVM_EXIT_WRITE_CR0:
5200	case SVM_EXIT_WRITE_CR3:
5201	case SVM_EXIT_WRITE_CR4:
5202	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set? */
5203	{
5204	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5205	Log4(("hmR0SvmHandleExitNested: Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5206
5207	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5208	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5209	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5210	}
5211
5212	case SVM_EXIT_PAUSE:
5213	{
5214	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5215	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5216	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5217	}
5218
5219	case SVM_EXIT_VINTR:
5220	{
5221	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5222	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5223	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5224	}
5225
5226	case SVM_EXIT_INTR:
5227	case SVM_EXIT_NMI:
5228	case SVM_EXIT_XCPT_NMI: /* Shouldn't ever happen, SVM_EXIT_NMI is used instead. */
5229	case SVM_EXIT_SMI:
5230	{
5231	/*
5232	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5233	*
5234	* Although we don't intercept SMIs, the nested-guest might. Therefore, we
5235	* might get an SMI #VMEXIT here so simply ignore rather than causing a
5236	* corresponding nested-guest #VMEXIT.
5237	*/
5238	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5239	}
5240
5241	case SVM_EXIT_FERR_FREEZE:
5242	{
5243	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5244	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5245	return hmR0SvmExitFerrFreeze(pVCpu, pCtx, pSvmTransient);
5246	}
5247
5248	case SVM_EXIT_INVLPG:
5249	{
5250	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5251	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5252	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5253	}
5254
5255	case SVM_EXIT_WBINVD:
5256	{
5257	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5258	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5259	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5260	}
5261
5262	case SVM_EXIT_INVD:
5263	{
5264	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5265	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5266	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5267	}
5268
5269	case SVM_EXIT_RDPMC:
5270	{
5271	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5272	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5273	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5274	}
5275
5276	default:
5277	{
5278	switch (uExitCode)
5279	{
5280	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5281	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5282	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5283	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5284	{
5285	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5286	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5287	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5288	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5289	}
5290
5291	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5292	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5293	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5294	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5295	{
5296	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5297	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5298	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5299	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5300	}
5301
5302	case SVM_EXIT_XCPT_0: /* #DE */
5303	/* SVM_EXIT_XCPT_1: / / #DB - Handled above. */
5304	/* SVM_EXIT_XCPT_2: / / #NMI - Handled above. */
5305	/* SVM_EXIT_XCPT_3: / / #BP - Handled above. */
5306	case SVM_EXIT_XCPT_4: /* #OF */
5307	case SVM_EXIT_XCPT_5: /* #BR */
5308	/* SVM_EXIT_XCPT_6: / / #UD - Handled above. */
5309	case SVM_EXIT_XCPT_7: /* #NM */
5310	case SVM_EXIT_XCPT_8: /* #DF */
5311	case SVM_EXIT_XCPT_9: /* #CO_SEG_OVERRUN */
5312	case SVM_EXIT_XCPT_10: /* #TS */
5313	case SVM_EXIT_XCPT_11: /* #NP */
5314	case SVM_EXIT_XCPT_12: /* #SS */
5315	case SVM_EXIT_XCPT_13: /* #GP */
5316	/* SVM_EXIT_XCPT_14: / / #PF - Handled above. */
5317	case SVM_EXIT_XCPT_15: /* Reserved. */
5318	/* SVM_EXIT_XCPT_16: / / #MF - Handled above. */
5319	/* SVM_EXIT_XCPT_17: / / #AC - Handled above. */
5320	case SVM_EXIT_XCPT_18: /* #MC */
5321	case SVM_EXIT_XCPT_19: /* #XF */
5322	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5323	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5324	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5325	{
5326	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5327	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5328	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5329	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5330	}
5331
5332	case SVM_EXIT_XSETBV:
5333	{
5334	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5335	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5336	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5337	}
5338
5339	case SVM_EXIT_TASK_SWITCH:
5340	{
5341	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5342	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5343	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5344	}
5345
5346	case SVM_EXIT_IRET:
5347	{
5348	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5349	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5350	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5351	}
5352
5353	case SVM_EXIT_SHUTDOWN:
5354	{
5355	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5356	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5357	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5358	}
5359
5360	case SVM_EXIT_VMMCALL:
5361	{
5362	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5363	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5364	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5365	}
5366
5367	case SVM_EXIT_CLGI:
5368	{
5369	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5370	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5371	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5372	}
5373
5374	case SVM_EXIT_STGI:
5375	{
5376	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5377	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5378	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5379	}
5380
5381	case SVM_EXIT_VMLOAD:
5382	{
5383	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5384	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5385	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5386	}
5387
5388	case SVM_EXIT_VMSAVE:
5389	{
5390	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5391	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5392	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5393	}
5394
5395	case SVM_EXIT_INVLPGA:
5396	{
5397	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5398	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5399	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5400	}
5401
5402	case SVM_EXIT_VMRUN:
5403	{
5404	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5405	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5406	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5407	}
5408
5409	case SVM_EXIT_RSM:
5410	{
5411	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5412	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5413	hmR0SvmSetPendingXcptUD(pVCpu);
5414	return VINF_SUCCESS;
5415	}
5416
5417	case SVM_EXIT_SKINIT:
5418	{
5419	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5420	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5421	hmR0SvmSetPendingXcptUD(pVCpu);
5422	return VINF_SUCCESS;
5423	}
5424
5425	/** @todo Needed when restoring saved-state when saved state support wasn't yet
5426	* added. Perhaps it won't be required later. */
5427	#if 0
5428	case SVM_EXIT_NPF:
5429	{
5430	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5431	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5432	return HM_SVM_VMEXIT_NESTED(pVCpu, SVM_EXIT_XCPT_14, RT_LO_U32(uExitInfo1), uExitInfo2);
5433	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, RT_LO_U32(uExitInfo1), uExitInfo2);
5434	return VINF_SUCCESS;
5435	}
5436	#else
5437	case SVM_EXIT_NPF:
5438	#endif
5439	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5440	{
5441	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5442	}
5443
5444	default:
5445	{
5446	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5447	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5448	return VERR_SVM_UNKNOWN_EXIT;
5449	}
5450	}
5451	}
5452	}
5453	/* not reached */
5454
5455	#undef HM_SVM_VMEXIT_NESTED
5456	}
5457	#endif
5458
5459
5460	/**
5461	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5462	*
5463	* @returns VBox status code (informational status codes included).
5464	* @param pVCpu The cross context virtual CPU structure.
5465	* @param pCtx Pointer to the guest-CPU context.
5466	* @param pSvmTransient Pointer to the SVM transient structure.
5467	*/
5468	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5469	{
5470	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5471	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5472
5473	/*
5474	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5475	* normal workloads (for some definition of "normal").
5476	*/
5477	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5478	switch (uExitCode)
5479	{
5480	case SVM_EXIT_NPF:
5481	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5482
5483	case SVM_EXIT_IOIO:
5484	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5485
5486	case SVM_EXIT_RDTSC:
5487	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5488
5489	case SVM_EXIT_RDTSCP:
5490	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5491
5492	case SVM_EXIT_CPUID:
5493	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5494
5495	case SVM_EXIT_XCPT_14: /* X86_XCPT_PF */
5496	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5497
5498	case SVM_EXIT_XCPT_6: /* X86_XCPT_UD */
5499	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5500
5501	case SVM_EXIT_XCPT_16: /* X86_XCPT_MF */
5502	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5503
5504	case SVM_EXIT_XCPT_1: /* X86_XCPT_DB */
5505	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5506
5507	case SVM_EXIT_XCPT_17: /* X86_XCPT_AC */
5508	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5509
5510	case SVM_EXIT_XCPT_3: /* X86_XCPT_BP */
5511	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5512
5513	case SVM_EXIT_MONITOR:
5514	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5515
5516	case SVM_EXIT_MWAIT:
5517	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5518
5519	case SVM_EXIT_HLT:
5520	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5521
5522	case SVM_EXIT_READ_CR0:
5523	case SVM_EXIT_READ_CR3:
5524	case SVM_EXIT_READ_CR4:
5525	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5526
5527	case SVM_EXIT_CR0_SEL_WRITE:
5528	case SVM_EXIT_WRITE_CR0:
5529	case SVM_EXIT_WRITE_CR3:
5530	case SVM_EXIT_WRITE_CR4:
5531	case SVM_EXIT_WRITE_CR8:
5532	{
5533	uint8_t const uCr = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : uExitCode - SVM_EXIT_WRITE_CR0;
5534	Log4(("hmR0SvmHandleExit: Write CR%u\n", uCr)); NOREF(uCr);
5535	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5536	}
5537
5538	case SVM_EXIT_PAUSE:
5539	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5540
5541	case SVM_EXIT_VMMCALL:
5542	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5543
5544	case SVM_EXIT_VINTR:
5545	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5546
5547	case SVM_EXIT_FERR_FREEZE:
5548	return hmR0SvmExitFerrFreeze(pVCpu, pCtx, pSvmTransient);
5549
5550	case SVM_EXIT_INTR:
5551	case SVM_EXIT_NMI:
5552	case SVM_EXIT_XCPT_NMI: /* Shouldn't ever happen, SVM_EXIT_NMI is used instead. */
5553	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5554
5555	case SVM_EXIT_MSR:
5556	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5557
5558	case SVM_EXIT_INVLPG:
5559	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5560
5561	case SVM_EXIT_WBINVD:
5562	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5563
5564	case SVM_EXIT_INVD:
5565	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5566
5567	case SVM_EXIT_RDPMC:
5568	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5569
5570	default:
5571	{
5572	switch (pSvmTransient->u64ExitCode)
5573	{
5574	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5575	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5576	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5577	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5578	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5579
5580	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5581	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5582	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5583	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5584	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5585
5586	case SVM_EXIT_XSETBV:
5587	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5588
5589	case SVM_EXIT_TASK_SWITCH:
5590	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5591
5592	case SVM_EXIT_IRET:
5593	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5594
5595	case SVM_EXIT_SHUTDOWN:
5596	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5597
5598	case SVM_EXIT_SMI:
5599	case SVM_EXIT_INIT:
5600	{
5601	/*
5602	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5603	* If it ever does, we want to know about it so log the exit code and bail.
5604	*/
5605	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5606	}
5607
5608	#ifdef VBOX_WITH_NESTED_HWVIRT
5609	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5610	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5611	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5612	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5613	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5614	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5615	#else
5616	case SVM_EXIT_CLGI:
5617	case SVM_EXIT_STGI:
5618	case SVM_EXIT_VMLOAD:
5619	case SVM_EXIT_VMSAVE:
5620	case SVM_EXIT_INVLPGA:
5621	case SVM_EXIT_VMRUN:
5622	#endif
5623	case SVM_EXIT_RSM:
5624	case SVM_EXIT_SKINIT:
5625	{
5626	hmR0SvmSetPendingXcptUD(pVCpu);
5627	return VINF_SUCCESS;
5628	}
5629
5630	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5631	case SVM_EXIT_XCPT_0: /* #DE */
5632	/* SVM_EXIT_XCPT_1: / / #DB - Handled above. */
5633	/* SVM_EXIT_XCPT_2: / / #NMI - Handled above. */
5634	/* SVM_EXIT_XCPT_3: / / #BP - Handled above. */
5635	case SVM_EXIT_XCPT_4: /* #OF */
5636	case SVM_EXIT_XCPT_5: /* #BR */
5637	/* SVM_EXIT_XCPT_6: / / #UD - Handled above. */
5638	case SVM_EXIT_XCPT_7: /* #NM */
5639	case SVM_EXIT_XCPT_8: /* #DF */
5640	case SVM_EXIT_XCPT_9: /* #CO_SEG_OVERRUN */
5641	case SVM_EXIT_XCPT_10: /* #TS */
5642	case SVM_EXIT_XCPT_11: /* #NP */
5643	case SVM_EXIT_XCPT_12: /* #SS */
5644	case SVM_EXIT_XCPT_13: /* #GP */
5645	/* SVM_EXIT_XCPT_14: / / #PF - Handled above. */
5646	case SVM_EXIT_XCPT_15: /* Reserved. */
5647	/* SVM_EXIT_XCPT_16: / / #MF - Handled above. */
5648	/* SVM_EXIT_XCPT_17: / / #AC - Handled above. */
5649	case SVM_EXIT_XCPT_18: /* #MC */
5650	case SVM_EXIT_XCPT_19: /* #XF */
5651	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5652	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5653	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5654	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5655	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5656
5657	default:
5658	{
5659	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5660	pVCpu->hm.s.u32HMError = uExitCode;
5661	return VERR_SVM_UNKNOWN_EXIT;
5662	}
5663	}
5664	}
5665	}
5666	/* not reached */
5667	}
5668
5669
5670	#ifdef DEBUG
5671	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5672	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5673	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5674
5675	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5676	do \
5677	{ \
5678	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5679	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5680	} while (0)
5681
5682	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5683	do { \
5684	AssertPtr(pVCpu); \
5685	AssertPtr(pCtx); \
5686	AssertPtr(pSvmTransient); \
5687	Assert(ASMIntAreEnabled()); \
5688	HMSVM_ASSERT_PREEMPT_SAFE(); \
5689	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5690	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5691	HMSVM_ASSERT_PREEMPT_SAFE(); \
5692	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5693	HMSVM_ASSERT_PREEMPT_CPUID(); \
5694	} while (0)
5695	#else /* Release builds */
5696	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5697	#endif
5698
5699
5700	/**
5701	* Worker for hmR0SvmInterpretInvlpg().
5702	*
5703	* @return VBox status code.
5704	* @param pVCpu The cross context virtual CPU structure.
5705	* @param pCpu Pointer to the disassembler state.
5706	* @param pCtx The guest CPU context.
5707	*/
5708	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5709	{
5710	DISQPVPARAMVAL Param1;
5711	RTGCPTR GCPtrPage;
5712
5713	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5714	if (RT_FAILURE(rc))
5715	return VERR_EM_INTERPRETER;
5716
5717	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5718	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5719	{
5720	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5721	return VERR_EM_INTERPRETER;
5722
5723	GCPtrPage = Param1.val.val64;
5724	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5725	rc = VBOXSTRICTRC_VAL(rc2);
5726	}
5727	else
5728	{
5729	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5730	rc = VERR_EM_INTERPRETER;
5731	}
5732
5733	return rc;
5734	}
5735
5736
5737	/**
5738	* Interprets INVLPG.
5739	*
5740	* @returns VBox status code.
5741	* @retval VINF_* Scheduling instructions.
5742	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5743	* @retval VERR_* Fatal errors.
5744	*
5745	* @param pVM The cross context VM structure.
5746	* @param pVCpu The cross context virtual CPU structure.
5747	* @param pCtx The guest CPU context.
5748	*
5749	* @remarks Updates the RIP if the instruction was executed successfully.
5750	*/
5751	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5752	{
5753	/* Only allow 32 & 64 bit code. */
5754	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5755	{
5756	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5757	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5758	if ( RT_SUCCESS(rc)
5759	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5760	{
5761	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5762	if (RT_SUCCESS(rc))
5763	pCtx->rip += pDis->cbInstr;
5764	return rc;
5765	}
5766	else
5767	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5768	}
5769	return VERR_EM_INTERPRETER;
5770	}
5771
5772
5773	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5774	/**
5775	* Gets the IEM exception flags for the specified SVM event.
5776	*
5777	* @returns The IEM exception flags.
5778	* @param pEvent Pointer to the SVM event.
5779	*
5780	* @remarks This function currently only constructs flags required for
5781	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5782	* and CR2 aspects of an exception are not included).
5783	*/
5784	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5785	{
5786	uint8_t const uEventType = pEvent->n.u3Type;
5787	uint32_t fIemXcptFlags;
5788	switch (uEventType)
5789	{
5790	case SVM_EVENT_EXCEPTION:
5791	/*
5792	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5793	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5794	*/
5795	if (pEvent->n.u8Vector == X86_XCPT_BP)
5796	{
5797	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5798	break;
5799	}
5800	if (pEvent->n.u8Vector == X86_XCPT_OF)
5801	{
5802	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5803	break;
5804	}
5805	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5806	RT_FALL_THRU();
5807	case SVM_EVENT_NMI:
5808	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5809	break;
5810
5811	case SVM_EVENT_EXTERNAL_IRQ:
5812	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5813	break;
5814
5815	case SVM_EVENT_SOFTWARE_INT:
5816	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5817	break;
5818
5819	default:
5820	fIemXcptFlags = 0;
5821	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5822	break;
5823	}
5824	return fIemXcptFlags;
5825	}
5826
5827	#else
5828	/**
5829	* Determines if an exception is a contributory exception.
5830	*
5831	* Contributory exceptions are ones which can cause double-faults unless the
5832	* original exception was a benign exception. Page-fault is intentionally not
5833	* included here as it's a conditional contributory exception.
5834	*
5835	* @returns @c true if the exception is contributory, @c false otherwise.
5836	* @param uVector The exception vector.
5837	*/
5838	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5839	{
5840	switch (uVector)
5841	{
5842	case X86_XCPT_GP:
5843	case X86_XCPT_SS:
5844	case X86_XCPT_NP:
5845	case X86_XCPT_TS:
5846	case X86_XCPT_DE:
5847	return true;
5848	default:
5849	break;
5850	}
5851	return false;
5852	}
5853	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5854
5855
5856	/**
5857	* Handle a condition that occurred while delivering an event through the guest
5858	* IDT.
5859	*
5860	* @returns VBox status code (informational error codes included).
5861	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5862	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5863	* continue execution of the guest which will delivery the \#DF.
5864	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5865	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5866	*
5867	* @param pVCpu The cross context virtual CPU structure.
5868	* @param pCtx Pointer to the guest-CPU context.
5869	* @param pSvmTransient Pointer to the SVM transient structure.
5870	*
5871	* @remarks No-long-jump zone!!!
5872	*/
5873	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5874	{
5875	int rc = VINF_SUCCESS;
5876	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5877
5878	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5879	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5880	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5881
5882	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5883	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5884	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5885	{
5886	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5887	IEMXCPTRAISE enmRaise;
5888	IEMXCPTRAISEINFO fRaiseInfo;
5889	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5890	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5891	if (fExitIsHwXcpt)
5892	{
5893	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5894	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5895	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5896	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5897	}
5898	else
5899	{
5900	/*
5901	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5902	* end up here.
5903	*
5904	* If the event was:
5905	* - a software interrupt, we can re-execute the instruction which will regenerate
5906	* the event.
5907	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5908	* - a hardware exception or external interrupt, we re-inject it.
5909	*/
5910	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5911	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5912	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5913	else
5914	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5915	}
5916
5917	switch (enmRaise)
5918	{
5919	case IEMXCPTRAISE_CURRENT_XCPT:
5920	case IEMXCPTRAISE_PREV_EVENT:
5921	{
5922	/* For software interrupts, we shall re-execute the instruction. */
5923	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5924	{
5925	RTGCUINTPTR GCPtrFaultAddress = 0;
5926
5927	/* If we are re-injecting an NMI, clear NMI blocking. */
5928	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5929	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5930
5931	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5932	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5933	pSvmTransient->fVectoringPF = true;
5934	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5935	&& uIdtVector == X86_XCPT_PF)
5936	{
5937	/*
5938	* If the previous exception was a #PF, we need to recover the CR2 value.
5939	* This can't happen with shadow paging.
5940	*/
5941	GCPtrFaultAddress = pCtx->cr2;
5942	}
5943
5944	/*
5945	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5946	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5947	*/
5948	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5949	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5950	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5951
5952	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5953	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5954	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5955	}
5956	break;
5957	}
5958
5959	case IEMXCPTRAISE_REEXEC_INSTR:
5960	{
5961	Assert(rc == VINF_SUCCESS);
5962	break;
5963	}
5964
5965	case IEMXCPTRAISE_DOUBLE_FAULT:
5966	{
5967	/*
5968	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5969	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5970	*/
5971	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5972	{
5973	pSvmTransient->fVectoringDoublePF = true;
5974	Assert(rc == VINF_SUCCESS);
5975	}
5976	else
5977	{
5978	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5979	hmR0SvmSetPendingXcptDF(pVCpu);
5980	rc = VINF_HM_DOUBLE_FAULT;
5981	}
5982	break;
5983	}
5984
5985	case IEMXCPTRAISE_TRIPLE_FAULT:
5986	{
5987	rc = VINF_EM_RESET;
5988	break;
5989	}
5990
5991	case IEMXCPTRAISE_CPU_HANG:
5992	{
5993	rc = VERR_EM_GUEST_CPU_HANG;
5994	break;
5995	}
5996
5997	default:
5998	{
5999	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6000	rc = VERR_SVM_IPE_2;
6001	break;
6002	}
6003	}
6004	#else
6005	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
6006
6007	typedef enum
6008	{
6009	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
6010	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
6011	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
6012	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
6013	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
6014	} SVMREFLECTXCPT;
6015
6016	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
6017	bool fReflectingNmi = false;
6018	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
6019	{
6020	if (pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31)
6021	{
6022	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0);
6023
6024	#ifdef VBOX_STRICT
6025	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
6026	&& uExitVector == X86_XCPT_PF)
6027	{
6028	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
6029	}
6030	#endif
6031
6032	if ( uIdtVector == X86_XCPT_BP
6033	\|\| uIdtVector == X86_XCPT_OF)
6034	{
6035	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
6036	}
6037	else if ( uExitVector == X86_XCPT_PF
6038	&& uIdtVector == X86_XCPT_PF)
6039	{
6040	pSvmTransient->fVectoringDoublePF = true;
6041	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
6042	}
6043	else if ( uExitVector == X86_XCPT_AC
6044	&& uIdtVector == X86_XCPT_AC)
6045	{
6046	enmReflect = SVMREFLECTXCPT_HANG;
6047	Log4(("IDT: Nested #AC - Bad guest\n"));
6048	}
6049	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
6050	&& hmR0SvmIsContributoryXcpt(uExitVector)
6051	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
6052	\|\| uIdtVector == X86_XCPT_PF))
6053	{
6054	enmReflect = SVMREFLECTXCPT_DF;
6055	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
6056	uIdtVector, uExitVector));
6057	}
6058	else if (uIdtVector == X86_XCPT_DF)
6059	{
6060	enmReflect = SVMREFLECTXCPT_TF;
6061	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
6062	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
6063	}
6064	else
6065	enmReflect = SVMREFLECTXCPT_XCPT;
6066	}
6067	else
6068	{
6069	/*
6070	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
6071	* exception to the guest after handling the #VMEXIT.
6072	*/
6073	enmReflect = SVMREFLECTXCPT_XCPT;
6074	}
6075	}
6076	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
6077	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
6078	{
6079	enmReflect = SVMREFLECTXCPT_XCPT;
6080	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
6081
6082	if (pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31)
6083	{
6084	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0);
6085	if (uExitVector == X86_XCPT_PF)
6086	{
6087	pSvmTransient->fVectoringPF = true;
6088	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
6089	}
6090	}
6091	}
6092	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
6093
6094	switch (enmReflect)
6095	{
6096	case SVMREFLECTXCPT_XCPT:
6097	{
6098	/* If we are re-injecting the NMI, clear NMI blocking. */
6099	if (fReflectingNmi)
6100	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6101
6102	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
6103	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6104	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
6105
6106	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
6107	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
6108	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
6109	break;
6110	}
6111
6112	case SVMREFLECTXCPT_DF:
6113	{
6114	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6115	hmR0SvmSetPendingXcptDF(pVCpu);
6116	rc = VINF_HM_DOUBLE_FAULT;
6117	break;
6118	}
6119
6120	case SVMREFLECTXCPT_TF:
6121	{
6122	rc = VINF_EM_RESET;
6123	break;
6124	}
6125
6126	case SVMREFLECTXCPT_HANG:
6127	{
6128	rc = VERR_EM_GUEST_CPU_HANG;
6129	break;
6130	}
6131
6132	default:
6133	Assert(rc == VINF_SUCCESS);
6134	break;
6135	}
6136	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
6137	}
6138	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6139	NOREF(pCtx);
6140	return rc;
6141	}
6142
6143
6144	/**
6145	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
6146	* supported, otherwise advances the RIP by the number of bytes specified in
6147	* @a cb.
6148	*
6149	* @param pVCpu The cross context virtual CPU structure.
6150	* @param pCtx Pointer to the guest-CPU context.
6151	* @param cb RIP increment value in bytes.
6152	*
6153	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
6154	* when NRIP_SAVE is supported by the CPU, otherwise use
6155	* hmR0SvmAdvanceRipDumb!
6156	*/
6157	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6158	{
6159	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6160	if (fSupportsNextRipSave)
6161	{
6162	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6163	Assert(pVmcb->ctrl.u64NextRIP);
6164	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
6165	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6166	}
6167	else
6168	pCtx->rip += cb;
6169
6170	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6171	}
6172
6173
6174	#ifdef VBOX_WITH_NESTED_HWVIRT
6175	/**
6176	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
6177	* feature. Otherwise, returns the value in @a cbLikely.
6178	*
6179	* @param pVCpu The cross context virtual CPU structure.
6180	* @param pCtx Pointer to the guest-CPU context.
6181	* @param cbLikely The likely instruction length.
6182	*/
6183	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
6184	{
6185	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
6186	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6187	if (fSupportsNextRipSave)
6188	{
6189	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6190	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6191	Assert(cbInstr == cbLikely);
6192	return cbInstr;
6193	}
6194	return cbLikely;
6195	}
6196	#endif
6197
6198
6199	/**
6200	* Advances the guest RIP by the number of bytes specified in @a cb. This does
6201	* not make use of any hardware features to determine the instruction length.
6202	*
6203	* @param pVCpu The cross context virtual CPU structure.
6204	* @param pCtx Pointer to the guest-CPU context.
6205	* @param cb RIP increment value in bytes.
6206	*/
6207	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6208	{
6209	pCtx->rip += cb;
6210	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6211	}
6212	#undef HMSVM_UPDATE_INTR_SHADOW
6213
6214
6215	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6216	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6217	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6218
6219	/** @name \#VMEXIT handlers.
6220	* @{
6221	*/
6222
6223	/**
6224	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6225	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6226	*/
6227	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6228	{
6229	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6230
6231	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6232	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6233	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6234	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6235
6236	/*
6237	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
6238	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
6239	* interrupt it is until the host actually take the interrupt.
6240	*
6241	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
6242	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6243	*/
6244	return VINF_EM_RAW_INTERRUPT;
6245	}
6246
6247
6248	/**
6249	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6250	*/
6251	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6252	{
6253	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6254
6255	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6256	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
6257	int rc = VINF_SUCCESS;
6258	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6259	return rc;
6260	}
6261
6262
6263	/**
6264	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6265	*/
6266	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6267	{
6268	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6269
6270	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6271	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
6272	int rc = VINF_SUCCESS;
6273	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6274	return rc;
6275	}
6276
6277
6278	/**
6279	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6280	*/
6281	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6282	{
6283	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6284	PVM pVM = pVCpu->CTX_SUFF(pVM);
6285	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6286	if (RT_LIKELY(rc == VINF_SUCCESS))
6287	{
6288	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6289	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6290	}
6291	else
6292	{
6293	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6294	rc = VERR_EM_INTERPRETER;
6295	}
6296	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
6297	return rc;
6298	}
6299
6300
6301	/**
6302	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6303	*/
6304	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6305	{
6306	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6307	PVM pVM = pVCpu->CTX_SUFF(pVM);
6308	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6309	if (RT_LIKELY(rc == VINF_SUCCESS))
6310	{
6311	pSvmTransient->fUpdateTscOffsetting = true;
6312	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6313	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6314	}
6315	else
6316	{
6317	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
6318	rc = VERR_EM_INTERPRETER;
6319	}
6320	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
6321	return rc;
6322	}
6323
6324
6325	/**
6326	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6327	*/
6328	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6329	{
6330	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6331	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
6332	if (RT_LIKELY(rc == VINF_SUCCESS))
6333	{
6334	pSvmTransient->fUpdateTscOffsetting = true;
6335	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6336	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6337	}
6338	else
6339	{
6340	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
6341	rc = VERR_EM_INTERPRETER;
6342	}
6343	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
6344	return rc;
6345	}
6346
6347
6348	/**
6349	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6350	*/
6351	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6352	{
6353	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6354	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6355	if (RT_LIKELY(rc == VINF_SUCCESS))
6356	{
6357	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6358	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6359	}
6360	else
6361	{
6362	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6363	rc = VERR_EM_INTERPRETER;
6364	}
6365	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6366	return rc;
6367	}
6368
6369
6370	/**
6371	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6372	*/
6373	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6374	{
6375	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6376	PVM pVM = pVCpu->CTX_SUFF(pVM);
6377	Assert(!pVM->hm.s.fNestedPaging);
6378	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6379
6380	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6381	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6382	if ( fSupportsDecodeAssists
6383	&& fSupportsNextRipSave)
6384	{
6385	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6386	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6387	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6388	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6389	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6390	return VBOXSTRICTRC_VAL(rcStrict);
6391	}
6392
6393	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6394	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6395	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6396	return rc;
6397	}
6398
6399
6400	/**
6401	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6402	*/
6403	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6404	{
6405	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6406
6407	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6408	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6409	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6410	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6411	if (rc != VINF_SUCCESS)
6412	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6413	return rc;
6414	}
6415
6416
6417	/**
6418	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6419	*/
6420	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6421	{
6422	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6423	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6424	if (RT_LIKELY(rc == VINF_SUCCESS))
6425	{
6426	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6427	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6428	}
6429	else
6430	{
6431	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6432	rc = VERR_EM_INTERPRETER;
6433	}
6434	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6435	return rc;
6436	}
6437
6438
6439	/**
6440	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6441	*/
6442	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6443	{
6444	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6445	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6446	int rc = VBOXSTRICTRC_VAL(rc2);
6447	if ( rc == VINF_EM_HALT
6448	\|\| rc == VINF_SUCCESS)
6449	{
6450	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6451
6452	if ( rc == VINF_EM_HALT
6453	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6454	{
6455	rc = VINF_SUCCESS;
6456	}
6457	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6458	}
6459	else
6460	{
6461	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6462	rc = VERR_EM_INTERPRETER;
6463	}
6464	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6465	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6466	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6467	return rc;
6468	}
6469
6470
6471	/**
6472	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6473	* \#VMEXIT.
6474	*/
6475	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6476	{
6477	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6478	return VINF_EM_RESET;
6479	}
6480
6481
6482	/**
6483	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6484	*/
6485	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6486	{
6487	RT_NOREF(pCtx);
6488	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6489	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6490	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6491	RT_NOREF(pVmcb);
6492	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6493	return VERR_SVM_UNEXPECTED_EXIT;
6494	}
6495
6496
6497	/**
6498	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6499	*/
6500	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6501	{
6502	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6503
6504	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6505	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6506
6507	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6508	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6509	if ( fSupportsDecodeAssists
6510	&& fSupportsNextRipSave)
6511	{
6512	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6513	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6514	if (fMovCRx)
6515	{
6516	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6517	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6518	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6519	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6520	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6521	return VBOXSTRICTRC_VAL(rcStrict);
6522	}
6523	/* else: SMSW instruction, fall back below to IEM for this. */
6524	}
6525
6526	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6527	int rc = VBOXSTRICTRC_VAL(rc2);
6528	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6529	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6530	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6531	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6532	return rc;
6533	}
6534
6535
6536	/**
6537	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6538	*/
6539	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6540	{
6541	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6542
6543	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6544	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6545	Assert(iCrReg <= 15);
6546
6547	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6548	bool fDecodedInstr = false;
6549	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6550	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6551	if ( fSupportsDecodeAssists
6552	&& fSupportsNextRipSave)
6553	{
6554	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6555	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6556	if (fMovCRx)
6557	{
6558	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6559	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6560	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6561	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6562	fDecodedInstr = true;
6563	}
6564	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6565	}
6566
6567	if (!fDecodedInstr)
6568	{
6569	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6570	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6571	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6572	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6573	rcStrict = VERR_EM_INTERPRETER;
6574	}
6575
6576	if (rcStrict == VINF_SUCCESS)
6577	{
6578	switch (iCrReg)
6579	{
6580	case 0: /* CR0. */
6581	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6582	break;
6583
6584	case 3: /* CR3. */
6585	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6586	break;
6587
6588	case 4: /* CR4. */
6589	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6590	break;
6591
6592	case 8: /* CR8 (TPR). */
6593	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
6594	break;
6595
6596	default:
6597	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6598	pSvmTransient->u64ExitCode, iCrReg));
6599	break;
6600	}
6601	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6602	}
6603	else
6604	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6605	return VBOXSTRICTRC_TODO(rcStrict);
6606	}
6607
6608
6609	/**
6610	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6611	* \#VMEXIT.
6612	*/
6613	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6614	{
6615	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6616	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6617	PVM pVM = pVCpu->CTX_SUFF(pVM);
6618
6619	int rc;
6620	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6621	{
6622	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6623	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6624
6625	/* Handle TPR patching; intercepted LSTAR write. */
6626	if ( pVM->hm.s.fTPRPatchingActive
6627	&& pCtx->ecx == MSR_K8_LSTAR)
6628	{
6629	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6630	{
6631	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6632	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6633	AssertRC(rc2);
6634	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
6635	}
6636	rc = VINF_SUCCESS;
6637	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6638	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6639	return rc;
6640	}
6641
6642	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6643	if (fSupportsNextRipSave)
6644	{
6645	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6646	if (RT_LIKELY(rc == VINF_SUCCESS))
6647	{
6648	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6649	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6650	}
6651	else
6652	AssertMsg( rc == VERR_EM_INTERPRETER
6653	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6654	}
6655	else
6656	{
6657	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6658	if (RT_LIKELY(rc == VINF_SUCCESS))
6659	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6660	else
6661	AssertMsg( rc == VERR_EM_INTERPRETER
6662	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6663	}
6664
6665	if (rc == VINF_SUCCESS)
6666	{
6667	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6668	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6669	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6670	{
6671	/*
6672	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6673	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6674	* EMInterpretWrmsr() changes it.
6675	*/
6676	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
6677	}
6678	else
6679	{
6680	switch (pCtx->ecx)
6681	{
6682	case MSR_K6_EFER: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR); break;
6683	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6684	case MSR_K8_FS_BASE:
6685	case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
6686	case MSR_IA32_SYSENTER_CS: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6687	case MSR_IA32_SYSENTER_EIP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6688	case MSR_IA32_SYSENTER_ESP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6689	}
6690	}
6691	}
6692	}
6693	else
6694	{
6695	/* MSR Read access. */
6696	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6697	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6698	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6699
6700	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6701	if (fSupportsNextRipSave)
6702	{
6703	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6704	if (RT_LIKELY(rc == VINF_SUCCESS))
6705	{
6706	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6707	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6708	}
6709	else
6710	AssertMsg( rc == VERR_EM_INTERPRETER
6711	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6712	}
6713	else
6714	{
6715	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6716	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6717	{
6718	AssertMsg( rc == VERR_EM_INTERPRETER
6719	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6720	}
6721	/* RIP updated by EMInterpretInstruction(). */
6722	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6723	}
6724	}
6725
6726	/* RIP has been updated by EMInterpret[Rd\|Wr]msr() or EMInterpretInstruction(). */
6727	return rc;
6728	}
6729
6730
6731	/**
6732	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6733	*/
6734	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6735	{
6736	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6737	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6738
6739	/** @todo Stepping with nested-guest. */
6740	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6741	{
6742	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6743	if (pSvmTransient->fWasGuestDebugStateActive)
6744	{
6745	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6746	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6747	return VERR_SVM_UNEXPECTED_EXIT;
6748	}
6749
6750	/*
6751	* Lazy DR0-3 loading.
6752	*/
6753	if (!pSvmTransient->fWasHyperDebugStateActive)
6754	{
6755	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6756	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6757
6758	/* Don't intercept DRx read and writes. */
6759	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6760	pVmcb->ctrl.u16InterceptRdDRx = 0;
6761	pVmcb->ctrl.u16InterceptWrDRx = 0;
6762	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6763
6764	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6765	VMMRZCallRing3Disable(pVCpu);
6766	HM_DISABLE_PREEMPT();
6767
6768	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6769	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6770	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6771
6772	HM_RESTORE_PREEMPT();
6773	VMMRZCallRing3Enable(pVCpu);
6774
6775	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6776	return VINF_SUCCESS;
6777	}
6778	}
6779
6780	/*
6781	* Interpret the read/writing of DRx.
6782	*/
6783	/** @todo Decode assist. */
6784	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6785	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6786	if (RT_LIKELY(rc == VINF_SUCCESS))
6787	{
6788	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6789	/** @todo CPUM should set this flag! */
6790	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6791	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6792	}
6793	else
6794	Assert(rc == VERR_EM_INTERPRETER);
6795	return VBOXSTRICTRC_TODO(rc);
6796	}
6797
6798
6799	/**
6800	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6801	*/
6802	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6803	{
6804	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6805	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6806	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6807	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6808	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6809	return rc;
6810	}
6811
6812
6813	/**
6814	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6815	*/
6816	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6817	{
6818	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6819
6820	/** @todo decode assists... */
6821	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6822	if (rcStrict == VINF_IEM_RAISED_XCPT)
6823	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6824
6825	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6826	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6827	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6828
6829	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6830	return VBOXSTRICTRC_TODO(rcStrict);
6831	}
6832
6833
6834	/**
6835	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6836	*/
6837	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6838	{
6839	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6840
6841	/* I/O operation lookup arrays. */
6842	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6843	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6844	the result (in AL/AX/EAX). */
6845	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6846
6847	PVM pVM = pVCpu->CTX_SUFF(pVM);
6848	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6849
6850	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6851	SVMIOIOEXITINFO IoExitInfo;
6852	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6853	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6854	uint32_t cbValue = s_aIOSize[uIOWidth];
6855	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6856
6857	if (RT_UNLIKELY(!cbValue))
6858	{
6859	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6860	return VERR_EM_INTERPRETER;
6861	}
6862
6863	VBOXSTRICTRC rcStrict;
6864	bool fUpdateRipAlready = false;
6865	if (IoExitInfo.n.u1Str)
6866	{
6867	#ifdef VBOX_WITH_2ND_IEM_STEP
6868	/* INS/OUTS - I/O String instruction. */
6869	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6870	* in EXITINFO1? Investigate once this thing is up and running. */
6871	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6872	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6873	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6874	static IEMMODE const s_aenmAddrMode[8] =
6875	{
6876	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6877	};
6878	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6879	if (enmAddrMode != (IEMMODE)-1)
6880	{
6881	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6882	if (cbInstr <= 15 && cbInstr >= 1)
6883	{
6884	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6885	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6886	{
6887	/* Don't know exactly how to detect whether u3Seg is valid, currently
6888	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6889	2384 Opterons when only checking NRIP. */
6890	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6891	if ( fSupportsNextRipSave
6892	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6893	{
6894	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6895	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6896	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6897	IoExitInfo.n.u3Seg, true /fIoChecked/);
6898	}
6899	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6900	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6901	X86_SREG_DS, true /fIoChecked/);
6902	else
6903	rcStrict = IEMExecOne(pVCpu);
6904	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6905	}
6906	else
6907	{
6908	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6909	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6910	true /fIoChecked/);
6911	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6912	}
6913	}
6914	else
6915	{
6916	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6917	rcStrict = IEMExecOne(pVCpu);
6918	}
6919	}
6920	else
6921	{
6922	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6923	rcStrict = IEMExecOne(pVCpu);
6924	}
6925	fUpdateRipAlready = true;
6926
6927	#else
6928	/* INS/OUTS - I/O String instruction. */
6929	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6930
6931	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6932	* in EXITINFO1? Investigate once this thing is up and running. */
6933
6934	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6935	if (rcStrict == VINF_SUCCESS)
6936	{
6937	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6938	{
6939	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6940	(DISCPUMODE)pDis->uAddrMode, cbValue);
6941	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6942	}
6943	else
6944	{
6945	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6946	(DISCPUMODE)pDis->uAddrMode, cbValue);
6947	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6948	}
6949	}
6950	else
6951	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6952	#endif
6953	}
6954	else
6955	{
6956	/* IN/OUT - I/O instruction. */
6957	Assert(!IoExitInfo.n.u1Rep);
6958
6959	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6960	{
6961	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6962	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6963	}
6964	else
6965	{
6966	uint32_t u32Val = 0;
6967	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6968	if (IOM_SUCCESS(rcStrict))
6969	{
6970	/* Save result of I/O IN instr. in AL/AX/EAX. */
6971	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6972	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6973	}
6974	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6975	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6976
6977	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6978	}
6979	}
6980
6981	if (IOM_SUCCESS(rcStrict))
6982	{
6983	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6984	if (!fUpdateRipAlready)
6985	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6986
6987	/*
6988	* If any I/O breakpoints are armed, we need to check if one triggered
6989	* and take appropriate action.
6990	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6991	*/
6992	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6993	* execution engines about whether hyper BPs and such are pending. */
6994	uint32_t const uDr7 = pCtx->dr[7];
6995	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6996	&& X86_DR7_ANY_RW_IO(uDr7)
6997	&& (pCtx->cr4 & X86_CR4_DE))
6998	\|\| DBGFBpIsHwIoArmed(pVM)))
6999	{
7000	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7001	VMMRZCallRing3Disable(pVCpu);
7002	HM_DISABLE_PREEMPT();
7003
7004	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
7005	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
7006
7007	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
7008	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
7009	{
7010	/* Raise #DB. */
7011	pVmcb->guest.u64DR6 = pCtx->dr[6];
7012	pVmcb->guest.u64DR7 = pCtx->dr[7];
7013	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7014	hmR0SvmSetPendingXcptDB(pVCpu);
7015	}
7016	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
7017	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
7018	else if ( rcStrict2 != VINF_SUCCESS
7019	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
7020	rcStrict = rcStrict2;
7021	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
7022
7023	HM_RESTORE_PREEMPT();
7024	VMMRZCallRing3Enable(pVCpu);
7025	}
7026
7027	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7028	}
7029
7030	#ifdef VBOX_STRICT
7031	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
7032	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
7033	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
7034	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
7035	else
7036	{
7037	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
7038	* statuses, that the VMM device and some others may return. See
7039	* IOM_SUCCESS() for guidance. */
7040	AssertMsg( RT_FAILURE(rcStrict)
7041	\|\| rcStrict == VINF_SUCCESS
7042	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
7043	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
7044	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
7045	\|\| rcStrict == VINF_EM_RAW_TO_R3
7046	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
7047	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7048	}
7049	#endif
7050	return VBOXSTRICTRC_TODO(rcStrict);
7051	}
7052
7053
7054	/**
7055	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
7056	*/
7057	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7058	{
7059	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7060	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7061
7062	PVM pVM = pVCpu->CTX_SUFF(pVM);
7063	Assert(pVM->hm.s.fNestedPaging);
7064
7065	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7066
7067	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7068	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7069	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /** @todo Make it more explicit that high bits can be non-zero. */
7070	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7071
7072	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
7073
7074	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7075	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
7076	if ( pVM->hm.s.fTprPatchingAllowed
7077	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7078	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7079	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7080	&& !CPUMIsGuestInLongModeEx(pCtx)
7081	&& !CPUMGetGuestCPL(pVCpu)
7082	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7083	{
7084	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7085	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7086
7087	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7088	{
7089	/* Only attempt to patch the instruction once. */
7090	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7091	if (!pPatch)
7092	return VINF_EM_HM_PATCH_TPR_INSTR;
7093	}
7094	}
7095	#endif
7096
7097	/*
7098	* Determine the nested paging mode.
7099	*/
7100	PGMMODE enmNestedPagingMode;
7101	#if HC_ARCH_BITS == 32
7102	if (CPUMIsGuestInLongModeEx(pCtx))
7103	enmNestedPagingMode = PGMMODE_AMD64_NX;
7104	else
7105	#endif
7106	enmNestedPagingMode = PGMGetHostMode(pVM);
7107
7108	/*
7109	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7110	*/
7111	int rc;
7112	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7113	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7114	{
7115	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
7116	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
7117	if (pVCpu->hm.s.Event.fPending)
7118	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7119
7120	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7121	u32ErrCode);
7122	rc = VBOXSTRICTRC_VAL(rc2);
7123
7124	/*
7125	* If we succeed, resume guest execution.
7126	* If we fail in interpreting the instruction because we couldn't get the guest physical address
7127	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
7128	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
7129	* weird case. See @bugref{6043}.
7130	*/
7131	if ( rc == VINF_SUCCESS
7132	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7133	\|\| rc == VERR_PAGE_NOT_PRESENT)
7134	{
7135	/* Successfully handled MMIO operation. */
7136	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_APIC_STATE);
7137	rc = VINF_SUCCESS;
7138	}
7139	return rc;
7140	}
7141
7142	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7143	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7144	TRPMResetTrap(pVCpu);
7145
7146	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7147
7148	/*
7149	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7150	*/
7151	if ( rc == VINF_SUCCESS
7152	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7153	\|\| rc == VERR_PAGE_NOT_PRESENT)
7154	{
7155	/* We've successfully synced our shadow page tables. */
7156	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7157	rc = VINF_SUCCESS;
7158	}
7159
7160	return rc;
7161	}
7162
7163
7164	/**
7165	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7166	* \#VMEXIT.
7167	*/
7168	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7169	{
7170	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7171	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7172
7173	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7174	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7175	hmR0SvmClearVirtIntrIntercept(pVmcb);
7176
7177	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7178	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7179	return VINF_SUCCESS;
7180	}
7181
7182
7183	/**
7184	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7185	* \#VMEXIT.
7186	*/
7187	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7188	{
7189	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7190
7191	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7192
7193	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7194	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7195	#endif
7196
7197	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7198	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7199	{
7200	/*
7201	* AMD-V provides us with the exception which caused the TS; we collect
7202	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
7203	*/
7204	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
7205	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7206	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7207	}
7208
7209	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7210	* emulation. */
7211	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7212	return VERR_EM_INTERPRETER;
7213	}
7214
7215
7216	/**
7217	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7218	*/
7219	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7220	{
7221	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7222	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
7223
7224	bool fRipUpdated;
7225	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
7226	if (RT_SUCCESS(rcStrict))
7227	{
7228	/* Only update the RIP if we're continuing guest execution and not
7229	in the case of say VINF_GIM_R3_HYPERCALL. */
7230	if ( rcStrict == VINF_SUCCESS
7231	&& !fRipUpdated)
7232	{
7233	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
7234	}
7235
7236	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
7237	we would need to reload the guest changed bits here before VM-entry. */
7238	return VBOXSTRICTRC_VAL(rcStrict);
7239	}
7240
7241	hmR0SvmSetPendingXcptUD(pVCpu);
7242	return VINF_SUCCESS;
7243	}
7244
7245
7246	/**
7247	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7248	*/
7249	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7250	{
7251	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7252	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
7253	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
7254	/** @todo The guest has likely hit a contended spinlock. We might want to
7255	* poke a schedule different guest VCPU. */
7256	return VINF_EM_RAW_INTERRUPT;
7257	}
7258
7259
7260	/**
7261	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7262	* \#VMEXIT.
7263	*/
7264	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7265	{
7266	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7267	Assert(!(pCtx->cr0 & X86_CR0_NE));
7268
7269	Log4(("hmR0SvmExitFerrFreeze: Raising IRQ 13 in response to #FERR\n"));
7270	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7271	}
7272
7273
7274	/**
7275	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7276	*/
7277	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7278	{
7279	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7280
7281	/* Clear NMI blocking. */
7282	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7283
7284	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7285	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7286	hmR0SvmClearIretIntercept(pVmcb);
7287
7288	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7289	return VINF_SUCCESS;
7290	}
7291
7292
7293	/**
7294	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7295	* Conditional \#VMEXIT.
7296	*/
7297	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7298	{
7299	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7300	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7301
7302	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7303
7304	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7305	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7306	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7307	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7308	PVM pVM = pVCpu->CTX_SUFF(pVM);
7309
7310	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7311	if (pVM->hm.s.fNestedPaging)
7312	{
7313	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7314	if (!pSvmTransient->fVectoringDoublePF)
7315	{
7316	/* A genuine guest #PF, reflect it to the guest. */
7317	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7318	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7319	uFaultAddress, u32ErrCode));
7320	}
7321	else
7322	{
7323	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7324	hmR0SvmSetPendingXcptDF(pVCpu);
7325	Log4(("Pending #DF due to vectoring #PF. NP\n"));
7326	}
7327	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7328	return VINF_SUCCESS;
7329	}
7330	#endif
7331
7332	Assert(!pVM->hm.s.fNestedPaging);
7333
7334	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7335	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
7336	if ( pVM->hm.s.fTprPatchingAllowed
7337	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7338	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
7339	&& !CPUMIsGuestInLongModeEx(pCtx)
7340	&& !CPUMGetGuestCPL(pVCpu)
7341	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7342	{
7343	RTGCPHYS GCPhysApicBase;
7344	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7345	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7346
7347	/* Check if the page at the fault-address is the APIC base. */
7348	RTGCPHYS GCPhysPage;
7349	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7350	if ( rc2 == VINF_SUCCESS
7351	&& GCPhysPage == GCPhysApicBase)
7352	{
7353	/* Only attempt to patch the instruction once. */
7354	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7355	if (!pPatch)
7356	return VINF_EM_HM_PATCH_TPR_INSTR;
7357	}
7358	}
7359	#endif
7360
7361	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7362	pCtx->rip, u32ErrCode, pCtx->cr3));
7363
7364	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7365	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7366	if (pSvmTransient->fVectoringPF)
7367	{
7368	Assert(pVCpu->hm.s.Event.fPending);
7369	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7370	}
7371
7372	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7373	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7374
7375	Log4(("#PF rc=%Rrc\n", rc));
7376
7377	if (rc == VINF_SUCCESS)
7378	{
7379	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7380	TRPMResetTrap(pVCpu);
7381	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7382	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7383	return rc;
7384	}
7385	else if (rc == VINF_EM_RAW_GUEST_TRAP)
7386	{
7387	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7388
7389	if (!pSvmTransient->fVectoringDoublePF)
7390	{
7391	/* It's a guest page fault and needs to be reflected to the guest. */
7392	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7393	TRPMResetTrap(pVCpu);
7394	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7395	}
7396	else
7397	{
7398	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7399	TRPMResetTrap(pVCpu);
7400	hmR0SvmSetPendingXcptDF(pVCpu);
7401	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7402	}
7403
7404	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7405	return VINF_SUCCESS;
7406	}
7407
7408	TRPMResetTrap(pVCpu);
7409	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7410	return rc;
7411	}
7412
7413
7414	/**
7415	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7416	* Conditional \#VMEXIT.
7417	*/
7418	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7419	{
7420	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7421	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7422
7423	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7424	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7425	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7426
7427	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7428	if (pVCpu->hm.s.fGIMTrapXcptUD)
7429	{
7430	uint8_t cbInstr = 0;
7431	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7432	if (rcStrict == VINF_SUCCESS)
7433	{
7434	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7435	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7436	rc = VINF_SUCCESS;
7437	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7438	}
7439	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7440	rc = VINF_SUCCESS;
7441	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7442	rc = VINF_GIM_R3_HYPERCALL;
7443	else
7444	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7445	}
7446
7447	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7448	if (RT_FAILURE(rc))
7449	{
7450	hmR0SvmSetPendingXcptUD(pVCpu);
7451	rc = VINF_SUCCESS;
7452	}
7453
7454	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7455	return rc;
7456	}
7457
7458
7459	/**
7460	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7461	* Conditional \#VMEXIT.
7462	*/
7463	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7464	{
7465	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7466
7467	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7468	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7469	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7470
7471	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7472
7473	if (!(pCtx->cr0 & X86_CR0_NE))
7474	{
7475	PVM pVM = pVCpu->CTX_SUFF(pVM);
7476	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7477	unsigned cbOp;
7478	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7479	if (RT_SUCCESS(rc))
7480	{
7481	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7482	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7483	if (RT_SUCCESS(rc))
7484	pCtx->rip += cbOp;
7485	}
7486	else
7487	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7488	return rc;
7489	}
7490
7491	hmR0SvmSetPendingXcptMF(pVCpu);
7492	return VINF_SUCCESS;
7493	}
7494
7495
7496	/**
7497	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7498	* \#VMEXIT.
7499	*/
7500	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7501	{
7502	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7503
7504	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7505	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7506	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7507	{
7508	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7509	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7510	}
7511
7512	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7513
7514	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7515	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7516	PVM pVM = pVCpu->CTX_SUFF(pVM);
7517	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7518	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7519	if (rc == VINF_EM_RAW_GUEST_TRAP)
7520	{
7521	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7522	if (CPUMIsHyperDebugStateActive(pVCpu))
7523	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7524
7525	/* Reflect the exception back to the guest. */
7526	hmR0SvmSetPendingXcptDB(pVCpu);
7527	rc = VINF_SUCCESS;
7528	}
7529
7530	/*
7531	* Update DR6.
7532	*/
7533	if (CPUMIsHyperDebugStateActive(pVCpu))
7534	{
7535	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7536	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7537	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7538	}
7539	else
7540	{
7541	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7542	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7543	}
7544
7545	return rc;
7546	}
7547
7548
7549	/**
7550	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7551	* Conditional \#VMEXIT.
7552	*/
7553	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7554	{
7555	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7556
7557	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7558	* shutdown VMEXIT. */
7559	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7560
7561	SVMEVENT Event;
7562	Event.u = 0;
7563	Event.n.u1Valid = 1;
7564	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7565	Event.n.u8Vector = X86_XCPT_AC;
7566	Event.n.u1ErrorCodeValid = 1;
7567	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7568	return VINF_SUCCESS;
7569	}
7570
7571
7572	/**
7573	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7574	* Conditional \#VMEXIT.
7575	*/
7576	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7577	{
7578	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7579
7580	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7581
7582	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7583	if (rc == VINF_EM_RAW_GUEST_TRAP)
7584	{
7585	SVMEVENT Event;
7586	Event.u = 0;
7587	Event.n.u1Valid = 1;
7588	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7589	Event.n.u8Vector = X86_XCPT_BP;
7590	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7591	}
7592
7593	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7594	return rc;
7595	}
7596
7597
7598	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
7599	/**
7600	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7601	*/
7602	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7603	{
7604	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7605
7606	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7607
7608	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7609	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7610	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7611	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7612	Assert(uVector <= X86_XCPT_LAST);
7613	Log4(("hmR0SvmExitXcptGeneric: uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7614
7615	SVMEVENT Event;
7616	Event.u = 0;
7617	Event.n.u1Valid = 1;
7618	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7619	Event.n.u8Vector = uVector;
7620	switch (uVector)
7621	{
7622	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7623	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7624	case X86_XCPT_DF:
7625	case X86_XCPT_TS:
7626	case X86_XCPT_NP:
7627	case X86_XCPT_SS:
7628	case X86_XCPT_GP:
7629	case X86_XCPT_AC:
7630	{
7631	Event.n.u1ErrorCodeValid = 1;
7632	Event.n.u32ErrorCode = uErrCode;
7633	break;
7634	}
7635	}
7636
7637	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7638	return VINF_SUCCESS;
7639	}
7640	#endif
7641
7642	#ifdef VBOX_WITH_NESTED_HWVIRT
7643	/**
7644	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7645	* (SVM_EXIT_XCPT_14). Conditional \#VMEXIT.
7646	*/
7647	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7648	{
7649	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7650
7651	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7652
7653	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7654	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7655	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7656	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7657
7658	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7659	pCtx->rip, u32ErrCode, pCtx->cr3));
7660
7661	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7662	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7663	if (pSvmTransient->fVectoringPF)
7664	{
7665	Assert(pVCpu->hm.s.Event.fPending);
7666	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7667	}
7668
7669	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7670
7671	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7672	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7673
7674	Log4(("#PFNested: rc=%Rrc\n", rc));
7675
7676	if (rc == VINF_SUCCESS)
7677	{
7678	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7679	TRPMResetTrap(pVCpu);
7680	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7681	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7682	return rc;
7683	}
7684
7685	if (rc == VINF_EM_RAW_GUEST_TRAP)
7686	{
7687	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7688
7689	if (!pSvmTransient->fVectoringDoublePF)
7690	{
7691	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7692	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7693	TRPMResetTrap(pVCpu);
7694	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7695	}
7696	else
7697	{
7698	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7699	TRPMResetTrap(pVCpu);
7700	hmR0SvmSetPendingXcptDF(pVCpu);
7701	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7702	}
7703
7704	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7705	return VINF_SUCCESS;
7706	}
7707
7708	TRPMResetTrap(pVCpu);
7709	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7710	return rc;
7711	}
7712
7713
7714	/**
7715	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7716	*/
7717	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7718	{
7719	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7720
7721	#ifdef VBOX_STRICT
7722	PCSVMVMCB pVmcbTmp = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7723	Assert(pVmcbTmp);
7724	Assert(!pVmcbTmp->ctrl.IntCtrl.n.u1VGifEnable);
7725	RT_NOREF(pVmcbTmp);
7726	#endif
7727
7728	/** @todo Stat. */
7729	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7730	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7731	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7732	return VBOXSTRICTRC_VAL(rcStrict);
7733	}
7734
7735
7736	/**
7737	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7738	*/
7739	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7740	{
7741	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7742
7743	#ifdef VBOX_STRICT
7744	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7745	Assert(pVmcb);
7746	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7747	RT_NOREF(pVmcb);
7748	#endif
7749
7750	/** @todo Stat. */
7751	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7752	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7753	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7754	return VBOXSTRICTRC_VAL(rcStrict);
7755	}
7756
7757
7758	/**
7759	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7760	*/
7761	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7762	{
7763	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7764
7765	#ifdef VBOX_STRICT
7766	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7767	Assert(pVmcb);
7768	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7769	RT_NOREF(pVmcb);
7770	#endif
7771
7772	/** @todo Stat. */
7773	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7774	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7775	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7776	if (rcStrict == VINF_SUCCESS)
7777	{
7778	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7779	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7780	\| HM_CHANGED_GUEST_TR
7781	\| HM_CHANGED_GUEST_LDTR);
7782	}
7783	return VBOXSTRICTRC_VAL(rcStrict);
7784	}
7785
7786
7787	/**
7788	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7789	*/
7790	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7791	{
7792	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7793
7794	#ifdef VBOX_STRICT
7795	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7796	Assert(pVmcb);
7797	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7798	RT_NOREF(pVmcb);
7799	#endif
7800
7801	/** @todo Stat. */
7802	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7803	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7804	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7805	return VBOXSTRICTRC_VAL(rcStrict);
7806	}
7807
7808
7809	/**
7810	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7811	*/
7812	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7813	{
7814	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7815	/** @todo Stat. */
7816	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7817	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7818	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7819	return VBOXSTRICTRC_VAL(rcStrict);
7820	}
7821
7822
7823	/**
7824	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7825	*/
7826	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7827	{
7828	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7829	/** @todo Stat. */
7830	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7831	#if 0
7832	VBOXSTRICTRC rcStrict;
7833	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7834	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7835	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7836	if (rcStrict == VINF_SUCCESS)
7837	{
7838	rcStrict = VINF_SVM_VMRUN;
7839	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7840	}
7841	return VBOXSTRICTRC_VAL(rcStrict);
7842	#endif
7843	return VERR_EM_INTERPRETER;
7844	}
7845
7846
7847	/**
7848	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7849	* Unconditional \#VMEXIT.
7850	*/
7851	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7852	{
7853	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7854
7855	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7856	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7857	* shutdown VMEXIT. */
7858	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7859	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7860	{
7861	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7862	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7863	}
7864
7865	hmR0SvmSetPendingXcptDB(pVCpu);
7866	return VINF_SUCCESS;
7867	}
7868
7869
7870	/**
7871	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7872	* Conditional \#VMEXIT.
7873	*/
7874	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7875	{
7876	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7877
7878	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7879	* shutdown VMEXIT. */
7880	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7881
7882	SVMEVENT Event;
7883	Event.u = 0;
7884	Event.n.u1Valid = 1;
7885	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7886	Event.n.u8Vector = X86_XCPT_BP;
7887	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7888	return VINF_SUCCESS;
7889	}
7890
7891	#endif /* VBOX_WITH_NESTED_HWVIRT */
7892
7893
7894	/** @} */
7895

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 71927

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