HMSVMR0.cpp@ 75828

Last change on this file since 75828 was 75828, checked in by vboxsync, 6 years ago
HVMSVMR0: Fixes to mesa hack.
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1	/* $Id: HMSVMR0.cpp 75828 2018-11-30 08:26:15Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include "HMSVMR0.h"
38	#include "dtrace/VBoxVMM.h"
39
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
43	# define HMSVM_ALWAYS_TRAP_PF
44	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
45	#endif
46
47
48	/*********************************************************************************************************************************
49	* Defined Constants And Macros *
50	*********************************************************************************************************************************/
51	#ifdef VBOX_WITH_STATISTICS
52	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
53	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
54	if ((u64ExitCode) == SVM_EXIT_NPF) \
55	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
56	else \
57	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
58	} while (0)
59
60	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
61	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
62	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
63	if ((u64ExitCode) == SVM_EXIT_NPF) \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
65	else \
66	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
67	} while (0)
68	# endif
69	#else
70	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
71	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
72	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
73	# endif
74	#endif /* !VBOX_WITH_STATISTICS */
75
76	/** If we decide to use a function table approach this can be useful to
77	* switch to a "static DECLCALLBACK(int)". */
78	#define HMSVM_EXIT_DECL static int
79
80	/**
81	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
82	* guest using hardware-assisted SVM.
83	*
84	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
85	* are swapped and restored across the world-switch and also registers like
86	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
87	* \#VMEXIT.
88	*/
89	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
90	\| CPUMCTX_EXTRN_RFLAGS \
91	\| CPUMCTX_EXTRN_RAX \
92	\| CPUMCTX_EXTRN_RSP \
93	\| CPUMCTX_EXTRN_SREG_MASK \
94	\| CPUMCTX_EXTRN_CR0 \
95	\| CPUMCTX_EXTRN_CR2 \
96	\| CPUMCTX_EXTRN_CR3 \
97	\| CPUMCTX_EXTRN_TABLE_MASK \
98	\| CPUMCTX_EXTRN_DR6 \
99	\| CPUMCTX_EXTRN_DR7 \
100	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
101	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
102	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
103	\| CPUMCTX_EXTRN_HWVIRT \
104	\| CPUMCTX_EXTRN_HM_SVM_MASK)
105
106	/**
107	* Subset of the guest-CPU state that is shared between the guest and host.
108	*/
109	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
110
111	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
112	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
113	do { \
114	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
115	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
116	} while (0)
117
118	/** Assert that the required state bits are fetched. */
119	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
120	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
121	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
122
123	/** Assert that preemption is disabled or covered by thread-context hooks. */
124	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
125	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
126
127	/** Assert that we haven't migrated CPUs when thread-context hooks are not
128	* used. */
129	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
130	\|\| (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
131	("Illegal migration! Entered on CPU %u Current %u\n", \
132	(a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()));
133
134	/** Assert that we're not executing a nested-guest. */
135	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
136	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
137	#else
138	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
139	#endif
140
141	/** Assert that we're executing a nested-guest. */
142	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
143	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
144	#else
145	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
146	#endif
147
148	/** Macro for checking and returning from the using function for
149	* \#VMEXIT intercepts that maybe caused during delivering of another
150	* event in the guest. */
151	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
152	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
153	do \
154	{ \
155	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
156	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
157	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
158	else if ( rc == VINF_EM_RESET \
159	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
160	{ \
161	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
162	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0)); \
163	} \
164	else \
165	return rc; \
166	} while (0)
167	#else
168	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
169	do \
170	{ \
171	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
172	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
173	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
174	else \
175	return rc; \
176	} while (0)
177	#endif
178
179	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
180	* instruction that exited. */
181	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
182	do { \
183	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
184	(a_rc) = VINF_EM_DBG_STEPPED; \
185	} while (0)
186
187	/** Validate segment descriptor granularity bit. */
188	#ifdef VBOX_STRICT
189	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
190	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
191	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
192	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
193	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
194	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
195	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
196	#else
197	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
198	#endif
199
200	/**
201	* Exception bitmap mask for all contributory exceptions.
202	*
203	* Page fault is deliberately excluded here as it's conditional as to whether
204	* it's contributory or benign. Page faults are handled separately.
205	*/
206	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
207	\| RT_BIT(X86_XCPT_DE))
208
209	/**
210	* Mandatory/unconditional guest control intercepts.
211	*
212	* SMIs can and do happen in normal operation. We need not intercept them
213	* while executing the guest (or nested-guest).
214	*/
215	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
216	\| SVM_CTRL_INTERCEPT_NMI \
217	\| SVM_CTRL_INTERCEPT_INIT \
218	\| SVM_CTRL_INTERCEPT_RDPMC \
219	\| SVM_CTRL_INTERCEPT_CPUID \
220	\| SVM_CTRL_INTERCEPT_RSM \
221	\| SVM_CTRL_INTERCEPT_HLT \
222	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
223	\| SVM_CTRL_INTERCEPT_MSR_PROT \
224	\| SVM_CTRL_INTERCEPT_INVLPGA \
225	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
226	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
227	\| SVM_CTRL_INTERCEPT_VMRUN \
228	\| SVM_CTRL_INTERCEPT_SKINIT \
229	\| SVM_CTRL_INTERCEPT_WBINVD \
230	\| SVM_CTRL_INTERCEPT_MONITOR \
231	\| SVM_CTRL_INTERCEPT_MWAIT \
232	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
233	\| SVM_CTRL_INTERCEPT_XSETBV)
234
235	/** @name VMCB Clean Bits.
236	*
237	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
238	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
239	* memory.
240	*
241	* @{ */
242	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
243	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
244	/** I/O permission bitmap, MSR permission bitmap. */
245	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
246	/** ASID. */
247	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
248	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
249	V_INTR_VECTOR. */
250	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
251	/** Nested Paging: Nested CR3 (nCR3), PAT. */
252	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
253	/** Control registers (CR0, CR3, CR4, EFER). */
254	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
255	/** Debug registers (DR6, DR7). */
256	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
257	/** GDT, IDT limit and base. */
258	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
259	/** Segment register: CS, SS, DS, ES limit and base. */
260	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
261	/** CR2.*/
262	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
263	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
264	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
265	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
266	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
267	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
268	/** Mask of all valid VMCB Clean bits. */
269	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
270	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
271	\| HMSVM_VMCB_CLEAN_ASID \
272	\| HMSVM_VMCB_CLEAN_INT_CTRL \
273	\| HMSVM_VMCB_CLEAN_NP \
274	\| HMSVM_VMCB_CLEAN_CRX_EFER \
275	\| HMSVM_VMCB_CLEAN_DRX \
276	\| HMSVM_VMCB_CLEAN_DT \
277	\| HMSVM_VMCB_CLEAN_SEG \
278	\| HMSVM_VMCB_CLEAN_CR2 \
279	\| HMSVM_VMCB_CLEAN_LBR \
280	\| HMSVM_VMCB_CLEAN_AVIC)
281	/** @} */
282
283	/** @name SVM transient.
284	*
285	* A state structure for holding miscellaneous information across AMD-V
286	* VMRUN/\#VMEXIT operation, restored after the transition.
287	*
288	* @{ */
289	typedef struct SVMTRANSIENT
290	{
291	/** The host's rflags/eflags. */
292	RTCCUINTREG fEFlags;
293	#if HC_ARCH_BITS == 32
294	uint32_t u32Alignment0;
295	#endif
296
297	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
298	uint64_t u64ExitCode;
299	/** The guest's TPR value used for TPR shadowing. */
300	uint8_t u8GuestTpr;
301	/** Alignment. */
302	uint8_t abAlignment0[7];
303
304	/** Pointer to the currently executing VMCB. */
305	PSVMVMCB pVmcb;
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308
309	/** Whether the guest debug state was active at the time of \#VMEXIT. */
310	bool fWasGuestDebugStateActive;
311	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
312	bool fWasHyperDebugStateActive;
313	/** Whether the TSC offset mode needs to be updated. */
314	bool fUpdateTscOffsetting;
315	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
316	bool fRestoreTscAuxMsr;
317	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
318	* contributary exception or a page-fault. */
319	bool fVectoringDoublePF;
320	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
321	* external interrupt or NMI. */
322	bool fVectoringPF;
323	} SVMTRANSIENT, *PSVMTRANSIENT;
324	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
325	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
326	/** @} */
327
328	/**
329	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
330	*/
331	typedef enum SVMMSREXITREAD
332	{
333	/** Reading this MSR causes a \#VMEXIT. */
334	SVMMSREXIT_INTERCEPT_READ = 0xb,
335	/** Reading this MSR does not cause a \#VMEXIT. */
336	SVMMSREXIT_PASSTHRU_READ
337	} SVMMSREXITREAD;
338
339	/**
340	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
341	*/
342	typedef enum SVMMSREXITWRITE
343	{
344	/** Writing to this MSR causes a \#VMEXIT. */
345	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
346	/** Writing to this MSR does not cause a \#VMEXIT. */
347	SVMMSREXIT_PASSTHRU_WRITE
348	} SVMMSREXITWRITE;
349
350	/**
351	* SVM \#VMEXIT handler.
352	*
353	* @returns VBox status code.
354	* @param pVCpu The cross context virtual CPU structure.
355	* @param pSvmTransient Pointer to the SVM-transient structure.
356	*/
357	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
358
359
360	/*********************************************************************************************************************************
361	* Internal Functions *
362	*********************************************************************************************************************************/
363	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
364	static void hmR0SvmLeave(PVMCPU pVCpu, bool fImportState);
365
366
367	/** @name \#VMEXIT handlers.
368	* @{
369	*/
370	static FNSVMEXITHANDLER hmR0SvmExitIntr;
371	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
372	static FNSVMEXITHANDLER hmR0SvmExitInvd;
373	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
374	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
375	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
376	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
377	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
378	static FNSVMEXITHANDLER hmR0SvmExitHlt;
379	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
380	static FNSVMEXITHANDLER hmR0SvmExitMwait;
381	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
382	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
383	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
384	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
385	static FNSVMEXITHANDLER hmR0SvmExitMsr;
386	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
387	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
388	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
389	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
390	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
391	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
392	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
393	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
394	static FNSVMEXITHANDLER hmR0SvmExitPause;
395	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
396	static FNSVMEXITHANDLER hmR0SvmExitIret;
397	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
398	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
399	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
400	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
401	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
402	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
403	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
404	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
405	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
406	#endif
407	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
408	static FNSVMEXITHANDLER hmR0SvmExitClgi;
409	static FNSVMEXITHANDLER hmR0SvmExitStgi;
410	static FNSVMEXITHANDLER hmR0SvmExitVmload;
411	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
412	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
413	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
414	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
415	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
416	#endif
417	/** @} */
418
419	static int hmR0SvmHandleExit(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
420	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
421	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
422	#endif
423
424
425	/*********************************************************************************************************************************
426	* Global Variables *
427	*********************************************************************************************************************************/
428	/** Ring-0 memory object for the IO bitmap. */
429	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
430	/** Physical address of the IO bitmap. */
431	static RTHCPHYS g_HCPhysIOBitmap;
432	/** Pointer to the IO bitmap. */
433	static R0PTRTYPE(void *) g_pvIOBitmap;
434
435	#ifdef VBOX_STRICT
436	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
437	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
438	# define HMSVM_LOG_CS RT_BIT_32(2)
439	# define HMSVM_LOG_SS RT_BIT_32(3)
440	# define HMSVM_LOG_FS RT_BIT_32(4)
441	# define HMSVM_LOG_GS RT_BIT_32(5)
442	# define HMSVM_LOG_LBR RT_BIT_32(6)
443	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
444	\| HMSVM_LOG_CR_REGS \
445	\| HMSVM_LOG_CS \
446	\| HMSVM_LOG_SS \
447	\| HMSVM_LOG_FS \
448	\| HMSVM_LOG_GS \
449	\| HMSVM_LOG_LBR)
450
451	/**
452	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
453	*
454	* @param pVCpu The cross context virtual CPU structure.
455	* @param pVmcb Pointer to the VM control block.
456	* @param pszPrefix Log prefix.
457	* @param fFlags Log flags, see HMSVM_LOG_XXX.
458	* @param uVerbose The verbosity level, currently unused.
459	*/
460	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
461	{
462	RT_NOREF2(pVCpu, uVerbose);
463	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
464
465	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
466	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
467
468	if (fFlags & HMSVM_LOG_RBP_RSP)
469	{
470	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
471	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
472	}
473
474	if (fFlags & HMSVM_LOG_CR_REGS)
475	{
476	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
477	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
478	}
479
480	if (fFlags & HMSVM_LOG_CS)
481	{
482	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
483	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
484	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
485	}
486	if (fFlags & HMSVM_LOG_SS)
487	{
488	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
489	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
490	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
491	}
492	if (fFlags & HMSVM_LOG_FS)
493	{
494	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
495	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
496	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
497	}
498	if (fFlags & HMSVM_LOG_GS)
499	{
500	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
501	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
502	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
503	}
504
505	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
506	if (fFlags & HMSVM_LOG_LBR)
507	{
508	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
509	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
510	}
511	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
512	}
513	#endif /* VBOX_STRICT */
514
515
516	/**
517	* Sets up and activates AMD-V on the current CPU.
518	*
519	* @returns VBox status code.
520	* @param pHostCpu Pointer to the CPU info struct.
521	* @param pVM The cross context VM structure. Can be
522	* NULL after a resume!
523	* @param pvCpuPage Pointer to the global CPU page.
524	* @param HCPhysCpuPage Physical address of the global CPU page.
525	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
526	* @param pvArg Unused on AMD-V.
527	*/
528	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
529	void *pvArg)
530	{
531	Assert(!fEnabledByHost);
532	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
533	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
534	Assert(pvCpuPage); NOREF(pvCpuPage);
535	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
536
537	NOREF(pvArg);
538	NOREF(fEnabledByHost);
539
540	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
541	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
542
543	/*
544	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
545	*/
546	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
547	if (u64HostEfer & MSR_K6_EFER_SVME)
548	{
549	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
550	if ( pVM
551	&& pVM->hm.s.svm.fIgnoreInUseError)
552	pHostCpu->fIgnoreAMDVInUseError = true;
553
554	if (!pHostCpu->fIgnoreAMDVInUseError)
555	{
556	ASMSetFlags(fEFlags);
557	return VERR_SVM_IN_USE;
558	}
559	}
560
561	/* Turn on AMD-V in the EFER MSR. */
562	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
563
564	/* Write the physical page address where the CPU will store the host state while executing the VM. */
565	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
566
567	/* Restore interrupts. */
568	ASMSetFlags(fEFlags);
569
570	/*
571	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
572	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
573	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
574	* entirely with before executing any guest code.
575	*/
576	pHostCpu->fFlushAsidBeforeUse = true;
577
578	/*
579	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
580	*/
581	++pHostCpu->cTlbFlushes;
582
583	return VINF_SUCCESS;
584	}
585
586
587	/**
588	* Deactivates AMD-V on the current CPU.
589	*
590	* @returns VBox status code.
591	* @param pHostCpu Pointer to the CPU info struct.
592	* @param pvCpuPage Pointer to the global CPU page.
593	* @param HCPhysCpuPage Physical address of the global CPU page.
594	*/
595	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
596	{
597	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
598	AssertReturn( HCPhysCpuPage
599	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
600	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
601	RT_NOREF(pHostCpu);
602
603	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
604	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
605
606	/* Turn off AMD-V in the EFER MSR. */
607	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
608	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
609
610	/* Invalidate host state physical address. */
611	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
612
613	/* Restore interrupts. */
614	ASMSetFlags(fEFlags);
615
616	return VINF_SUCCESS;
617	}
618
619
620	/**
621	* Does global AMD-V initialization (called during module initialization).
622	*
623	* @returns VBox status code.
624	*/
625	VMMR0DECL(int) SVMR0GlobalInit(void)
626	{
627	/*
628	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
629	* intercept all IO accesses, it's done once globally here instead of per-VM.
630	*/
631	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
632	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
633	if (RT_FAILURE(rc))
634	return rc;
635
636	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
637	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
638
639	/* Set all bits to intercept all IO accesses. */
640	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
641
642	return VINF_SUCCESS;
643	}
644
645
646	/**
647	* Does global AMD-V termination (called during module termination).
648	*/
649	VMMR0DECL(void) SVMR0GlobalTerm(void)
650	{
651	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
652	{
653	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
654	g_pvIOBitmap = NULL;
655	g_HCPhysIOBitmap = 0;
656	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
657	}
658	}
659
660
661	/**
662	* Frees any allocated per-VCPU structures for a VM.
663	*
664	* @param pVM The cross context VM structure.
665	*/
666	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
667	{
668	for (uint32_t i = 0; i < pVM->cCpus; i++)
669	{
670	PVMCPU pVCpu = &pVM->aCpus[i];
671	AssertPtr(pVCpu);
672
673	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
674	{
675	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
676	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
677	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
678	}
679
680	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
681	{
682	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
683	pVCpu->hm.s.svm.pVmcb = NULL;
684	pVCpu->hm.s.svm.HCPhysVmcb = 0;
685	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
686	}
687
688	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
689	{
690	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
691	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
692	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
693	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
694	}
695	}
696	}
697
698
699	/**
700	* Does per-VM AMD-V initialization.
701	*
702	* @returns VBox status code.
703	* @param pVM The cross context VM structure.
704	*/
705	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
706	{
707	int rc = VERR_INTERNAL_ERROR_5;
708
709	/*
710	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
711	*/
712	uint32_t u32Family;
713	uint32_t u32Model;
714	uint32_t u32Stepping;
715	if (HMSvmIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
716	{
717	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
718	pVM->hm.s.svm.fAlwaysFlushTLB = true;
719	}
720
721	/*
722	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
723	*/
724	for (VMCPUID i = 0; i < pVM->cCpus; i++)
725	{
726	PVMCPU pVCpu = &pVM->aCpus[i];
727	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
728	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
729	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
730	}
731
732	for (VMCPUID i = 0; i < pVM->cCpus; i++)
733	{
734	PVMCPU pVCpu = &pVM->aCpus[i];
735
736	/*
737	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
738	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
739	*/
740	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
741	if (RT_FAILURE(rc))
742	goto failure_cleanup;
743
744	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
745	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
746	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
747	ASMMemZeroPage(pvVmcbHost);
748
749	/*
750	* Allocate one page for the guest-state VMCB.
751	*/
752	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
753	if (RT_FAILURE(rc))
754	goto failure_cleanup;
755
756	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
757	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
758	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
759	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
760
761	/*
762	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
763	* SVM to not require one.
764	*/
765	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
766	false /* fExecutable */);
767	if (RT_FAILURE(rc))
768	goto failure_cleanup;
769
770	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
771	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
772	/* Set all bits to intercept all MSR accesses (changed later on). */
773	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
774	}
775
776	return VINF_SUCCESS;
777
778	failure_cleanup:
779	hmR0SvmFreeStructs(pVM);
780	return rc;
781	}
782
783
784	/**
785	* Does per-VM AMD-V termination.
786	*
787	* @returns VBox status code.
788	* @param pVM The cross context VM structure.
789	*/
790	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
791	{
792	hmR0SvmFreeStructs(pVM);
793	return VINF_SUCCESS;
794	}
795
796
797	/**
798	* Returns whether the VMCB Clean Bits feature is supported.
799	*
800	* @return @c true if supported, @c false otherwise.
801	* @param pVCpu The cross context virtual CPU structure.
802	*/
803	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu)
804	{
805	PVM pVM = pVCpu->CTX_SUFF(pVM);
806	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
807	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
808	{
809	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
810	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
811	}
812	#endif
813	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
814	}
815
816
817	/**
818	* Returns whether the decode assists feature is supported.
819	*
820	* @return @c true if supported, @c false otherwise.
821	* @param pVCpu The cross context virtual CPU structure.
822	*/
823	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu)
824	{
825	PVM pVM = pVCpu->CTX_SUFF(pVM);
826	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
827	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
828	{
829	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
830	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
831	}
832	#endif
833	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
834	}
835
836
837	/**
838	* Returns whether the NRIP_SAVE feature is supported.
839	*
840	* @return @c true if supported, @c false otherwise.
841	* @param pVCpu The cross context virtual CPU structure.
842	*/
843	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu)
844	{
845	PVM pVM = pVCpu->CTX_SUFF(pVM);
846	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
847	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
848	{
849	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
850	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
851	}
852	#endif
853	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
854	}
855
856
857	/**
858	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
859	*
860	* @param pVCpu The cross context virtual CPU structure.
861	* @param pbMsrBitmap Pointer to the MSR bitmap.
862	* @param idMsr The MSR for which the permissions are being set.
863	* @param enmRead MSR read permissions.
864	* @param enmWrite MSR write permissions.
865	*
866	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
867	* caller needs to take care of this.
868	*/
869	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
870	SVMMSREXITWRITE enmWrite)
871	{
872	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
873	uint16_t offMsrpm;
874	uint8_t uMsrpmBit;
875	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
876	AssertRC(rc);
877
878	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
879	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
880
881	pbMsrBitmap += offMsrpm;
882	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
883	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
884	else
885	{
886	if (!fInNestedGuestMode)
887	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
888	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
889	else
890	{
891	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
892	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
893	pbNstGstMsrBitmap += offMsrpm;
894	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
895	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
896	else
897	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
898	}
899	#endif
900	}
901
902	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
903	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
904	else
905	{
906	if (!fInNestedGuestMode)
907	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
908	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
909	else
910	{
911	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
912	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
913	pbNstGstMsrBitmap += offMsrpm;
914	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
915	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
916	else
917	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
918	}
919	#endif
920	}
921	}
922
923
924	/**
925	* Sets up AMD-V for the specified VM.
926	* This function is only called once per-VM during initalization.
927	*
928	* @returns VBox status code.
929	* @param pVM The cross context VM structure.
930	*/
931	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
932	{
933	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
934	AssertReturn(pVM, VERR_INVALID_PARAMETER);
935	Assert(pVM->hm.s.svm.fSupported);
936
937	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
938	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
939	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
940
941	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
942	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
943
944	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
945	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
946	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
947
948	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
949	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
950	#endif
951
952	PVMCPU pVCpu = &pVM->aCpus[0];
953	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
954	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[0]\n"), VERR_SVM_INVALID_PVMCB);
955	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
956
957	/* Always trap #AC for reasons of security. */
958	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
959
960	/* Always trap #DB for reasons of security. */
961	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
962
963	/* Trap exceptions unconditionally (debug purposes). */
964	#ifdef HMSVM_ALWAYS_TRAP_PF
965	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
966	#endif
967	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
968	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
969	pVmcbCtrl->u32InterceptXcpt \|= 0
970	\| RT_BIT(X86_XCPT_BP)
971	\| RT_BIT(X86_XCPT_DE)
972	\| RT_BIT(X86_XCPT_NM)
973	\| RT_BIT(X86_XCPT_UD)
974	\| RT_BIT(X86_XCPT_NP)
975	\| RT_BIT(X86_XCPT_SS)
976	\| RT_BIT(X86_XCPT_GP)
977	\| RT_BIT(X86_XCPT_PF)
978	\| RT_BIT(X86_XCPT_MF)
979	;
980	#endif
981
982	/* Apply the exceptions intercepts needed by the GIM provider. */
983	if (pVCpu->hm.s.fGIMTrapXcptUD)
984	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
985
986	/* The mesa 3d driver hack needs #GP. */
987	if (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv)
988	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
989
990	/* Set up unconditional intercepts and conditions. */
991	pVmcbCtrl->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
992	\| SVM_CTRL_INTERCEPT_VMMCALL;
993
994	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
995	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
996	#endif
997
998	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
999	/* Virtualized VMSAVE/VMLOAD. */
1000	pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
1001	if (!fUseVirtVmsaveVmload)
1002	{
1003	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
1004	\| SVM_CTRL_INTERCEPT_VMLOAD;
1005	}
1006
1007	/* Virtual GIF. */
1008	pVmcbCtrl->IntCtrl.n.u1VGifEnable = fUseVGif;
1009	if (!fUseVGif)
1010	{
1011	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
1012	\| SVM_CTRL_INTERCEPT_STGI;
1013	}
1014	#endif
1015
1016	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1017	pVmcbCtrl->u16InterceptWrCRx = RT_BIT(4);
1018
1019	/* Intercept all DRx reads and writes by default. Changed later on. */
1020	pVmcbCtrl->u16InterceptRdDRx = 0xffff;
1021	pVmcbCtrl->u16InterceptWrDRx = 0xffff;
1022
1023	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1024	pVmcbCtrl->IntCtrl.n.u1VIntrMasking = 1;
1025
1026	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1027	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1028	pVmcbCtrl->IntCtrl.n.u1IgnoreTPR = 1;
1029
1030	/* Set the IO permission bitmap physical addresses. */
1031	pVmcbCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1032
1033	/* LBR virtualization. */
1034	pVmcbCtrl->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1035
1036	/* The host ASID MBZ, for the guest start with 1. */
1037	pVmcbCtrl->TLBCtrl.n.u32ASID = 1;
1038
1039	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1040	pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1041
1042	/* Without Nested Paging, we need additionally intercepts. */
1043	if (!pVM->hm.s.fNestedPaging)
1044	{
1045	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1046	pVmcbCtrl->u16InterceptRdCRx \|= RT_BIT(3);
1047	pVmcbCtrl->u16InterceptWrCRx \|= RT_BIT(3);
1048
1049	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1050	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1051	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1052
1053	/* Page faults must be intercepted to implement shadow paging. */
1054	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1055	}
1056
1057	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1058	if (fUsePauseFilter)
1059	{
1060	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1061	pVmcbCtrl->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1062	if (fPauseFilterThreshold)
1063	pVmcbCtrl->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1064	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1065	}
1066
1067	/*
1068	* Setup the MSR permission bitmap.
1069	* The following MSRs are saved/restored automatically during the world-switch.
1070	* Don't intercept guest read/write accesses to these MSRs.
1071	*/
1072	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1073	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1074	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1075	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1076	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1077	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1078	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1079	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1080	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1081	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1082	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1083	pVmcbCtrl->u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
1084
1085	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1086	Assert(pVmcbCtrl->u32VmcbCleanBits == 0);
1087
1088	for (VMCPUID i = 1; i < pVM->cCpus; i++)
1089	{
1090	PVMCPU pVCpuCur = &pVM->aCpus[i];
1091	PSVMVMCB pVmcbCur = pVM->aCpus[i].hm.s.svm.pVmcb;
1092	AssertMsgReturn(pVmcbCur, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
1093	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1094
1095	/* Copy the VMCB control area. */
1096	memcpy(pVmcbCtrlCur, pVmcbCtrl, sizeof(*pVmcbCtrlCur));
1097
1098	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1099	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hm.s.svm.pvMsrBitmap;
1100	memcpy(pbMsrBitmapCur, pbMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1101	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
1102
1103	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1104	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1105
1106	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1107	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu->hm.s.fGIMTrapXcptUD);
1108	}
1109
1110	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1111	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1112	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1113	#else
1114	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1115	#endif
1116	return VINF_SUCCESS;
1117	}
1118
1119
1120	/**
1121	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1122	*
1123	* @returns Pointer to the current context VMCB.
1124	* @param pVCpu The cross context virtual CPU structure.
1125	*/
1126	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu)
1127	{
1128	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1129	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1130	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1131	#endif
1132	return pVCpu->hm.s.svm.pVmcb;
1133	}
1134
1135
1136	/**
1137	* Gets a pointer to the nested-guest VMCB cache.
1138	*
1139	* @returns Pointer to the nested-guest VMCB cache.
1140	* @param pVCpu The cross context virtual CPU structure.
1141	*/
1142	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPU pVCpu)
1143	{
1144	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1145	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1146	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1147	#else
1148	RT_NOREF(pVCpu);
1149	return NULL;
1150	#endif
1151	}
1152
1153
1154	/**
1155	* Invalidates a guest page by guest virtual address.
1156	*
1157	* @returns VBox status code.
1158	* @param pVCpu The cross context virtual CPU structure.
1159	* @param GCVirt Guest virtual address of the page to invalidate.
1160	*/
1161	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1162	{
1163	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1164
1165	bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1166
1167	/* Skip it if a TLB flush is already pending. */
1168	if (!fFlushPending)
1169	{
1170	Log4Func(("%#RGv\n", GCVirt));
1171
1172	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1173	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1174
1175	#if HC_ARCH_BITS == 32
1176	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1177	if (CPUMIsGuestInLongMode(pVCpu))
1178	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1179	else
1180	#endif
1181	{
1182	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1183	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1184	}
1185	}
1186	return VINF_SUCCESS;
1187	}
1188
1189
1190	/**
1191	* Flushes the appropriate tagged-TLB entries.
1192	*
1193	* @param pVCpu The cross context virtual CPU structure.
1194	* @param pVmcb Pointer to the VM control block.
1195	* @param pHostCpu Pointer to the HM host-CPU info.
1196	*/
1197	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PSVMVMCB pVmcb, PHMGLOBALCPUINFO pHostCpu)
1198	{
1199	/*
1200	* Force a TLB flush for the first world switch if the current CPU differs from the one
1201	* we ran on last. This can happen both for start & resume due to long jumps back to
1202	* ring-3.
1203	*
1204	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1205	* correlation between it and the physical CPU.
1206	*
1207	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1208	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1209	*/
1210	bool fNewAsid = false;
1211	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1212	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1213	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1214	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1215	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1216	#endif
1217	)
1218	{
1219	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1220	pVCpu->hm.s.fForceTLBFlush = true;
1221	fNewAsid = true;
1222	}
1223
1224	/* Set TLB flush state as checked until we return from the world switch. */
1225	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1226
1227	/* Check for explicit TLB flushes. */
1228	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1229	{
1230	pVCpu->hm.s.fForceTLBFlush = true;
1231	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1232	}
1233
1234	/*
1235	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1236	* This Host CPU requirement takes precedence.
1237	*/
1238	PVM pVM = pVCpu->CTX_SUFF(pVM);
1239	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1240	{
1241	pHostCpu->uCurrentAsid = 1;
1242	pVCpu->hm.s.uCurrentAsid = 1;
1243	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1244	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1245	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1246
1247	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1248	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1249	}
1250	else
1251	{
1252	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1253	if (pVCpu->hm.s.fForceTLBFlush)
1254	{
1255	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1256	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1257
1258	if (fNewAsid)
1259	{
1260	++pHostCpu->uCurrentAsid;
1261
1262	bool fHitASIDLimit = false;
1263	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1264	{
1265	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1266	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1267	fHitASIDLimit = true;
1268	}
1269
1270	if ( fHitASIDLimit
1271	\|\| pHostCpu->fFlushAsidBeforeUse)
1272	{
1273	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1274	pHostCpu->fFlushAsidBeforeUse = false;
1275	}
1276
1277	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1278	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1279	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1280	}
1281	else
1282	{
1283	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1284	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1285	else
1286	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1287	}
1288
1289	pVCpu->hm.s.fForceTLBFlush = false;
1290	}
1291	}
1292
1293	/* Update VMCB with the ASID. */
1294	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1295	{
1296	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1297	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1298	}
1299
1300	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1301	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1302	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1303	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1304	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1305	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1306	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1307	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1308
1309	#ifdef VBOX_WITH_STATISTICS
1310	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1311	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1312	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1313	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1314	{
1315	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1316	}
1317	else
1318	{
1319	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1320	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1321	}
1322	#endif
1323	}
1324
1325
1326	/** @name 64-bit guest on 32-bit host OS helper functions.
1327	*
1328	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1329	* mode (code segment, paging). These wrappers/helpers perform the necessary
1330	* bits for the 32->64 switcher.
1331	*
1332	* @{ */
1333	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1334	/**
1335	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1336	*
1337	* @returns VBox status code.
1338	* @param HCPhysVmcbHost Physical address of host VMCB.
1339	* @param HCPhysVmcb Physical address of the VMCB.
1340	* @param pCtx Pointer to the guest-CPU context.
1341	* @param pVM The cross context VM structure.
1342	* @param pVCpu The cross context virtual CPU structure.
1343	*/
1344	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1345	{
1346	RT_NOREF2(pVM, pCtx);
1347	uint32_t aParam[8];
1348	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1349	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1350	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1351	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1352	aParam[4] = VM_RC_ADDR(pVM, pVM);
1353	aParam[5] = 0;
1354	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1355	aParam[7] = 0;
1356
1357	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1358	}
1359
1360
1361	/**
1362	* Executes the specified VMRUN handler in 64-bit mode.
1363	*
1364	* @returns VBox status code.
1365	* @param pVCpu The cross context virtual CPU structure.
1366	* @param enmOp The operation to perform.
1367	* @param cParams Number of parameters.
1368	* @param paParam Array of 32-bit parameters.
1369	*/
1370	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
1371	{
1372	PVM pVM = pVCpu->CTX_SUFF(pVM);
1373	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1374	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1375
1376	/* Disable interrupts. */
1377	RTHCUINTREG const fEFlags = ASMIntDisableFlags();
1378
1379	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1380	RTCPUID idHostCpu = RTMpCpuId();
1381	CPUMR0SetLApic(pVCpu, idHostCpu);
1382	#endif
1383
1384	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1385	CPUMSetHyperEIP(pVCpu, enmOp);
1386	for (int i = (int)cParams - 1; i >= 0; i--)
1387	CPUMPushHyper(pVCpu, paParam[i]);
1388
1389	/* Call the switcher. */
1390	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1391	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
1392	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1393
1394	/* Restore interrupts. */
1395	ASMSetFlags(fEFlags);
1396	return rc;
1397	}
1398
1399	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1400	/** @} */
1401
1402
1403	/**
1404	* Sets an exception intercept in the specified VMCB.
1405	*
1406	* @param pVmcb Pointer to the VM control block.
1407	* @param uXcpt The exception (X86_XCPT_*).
1408	*/
1409	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1410	{
1411	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1412	{
1413	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1414	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1415	}
1416	}
1417
1418
1419	/**
1420	* Clears an exception intercept in the specified VMCB.
1421	*
1422	* @param pVCpu The cross context virtual CPU structure.
1423	* @param pVmcb Pointer to the VM control block.
1424	* @param uXcpt The exception (X86_XCPT_*).
1425	*
1426	* @remarks This takes into account if we're executing a nested-guest and only
1427	* removes the exception intercept if both the guest -and- nested-guest
1428	* are not intercepting it.
1429	*/
1430	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPU pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1431	{
1432	Assert(uXcpt != X86_XCPT_DB);
1433	Assert(uXcpt != X86_XCPT_AC);
1434	Assert(uXcpt != X86_XCPT_GP);
1435	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1436	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1437	{
1438	bool fRemove = true;
1439	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1440	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1441	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1442	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1443	{
1444	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1445	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1446	}
1447	# else
1448	RT_NOREF(pVCpu);
1449	# endif
1450	if (fRemove)
1451	{
1452	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1453	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1454	}
1455	}
1456	#else
1457	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1458	#endif
1459	}
1460
1461
1462	/**
1463	* Sets a control intercept in the specified VMCB.
1464	*
1465	* @param pVmcb Pointer to the VM control block.
1466	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1467	*/
1468	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1469	{
1470	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1471	{
1472	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1473	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1474	}
1475	}
1476
1477
1478	/**
1479	* Clears a control intercept in the specified VMCB.
1480	*
1481	* @returns @c true if the intercept is still set, @c false otherwise.
1482	* @param pVCpu The cross context virtual CPU structure.
1483	* @param pVmcb Pointer to the VM control block.
1484	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1485	*
1486	* @remarks This takes into account if we're executing a nested-guest and only
1487	* removes the control intercept if both the guest -and- nested-guest
1488	* are not intercepting it.
1489	*/
1490	static bool hmR0SvmClearCtrlIntercept(PVMCPU pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1491	{
1492	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1493	{
1494	bool fRemove = true;
1495	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1496	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1497	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1498	{
1499	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1500	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1501	}
1502	#else
1503	RT_NOREF(pVCpu);
1504	#endif
1505	if (fRemove)
1506	{
1507	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1508	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1509	}
1510	}
1511
1512	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1513	}
1514
1515
1516	/**
1517	* Exports the guest (or nested-guest) CR0 into the VMCB.
1518	*
1519	* @param pVCpu The cross context virtual CPU structure.
1520	* @param pVmcb Pointer to the VM control block.
1521	*
1522	* @remarks This assumes we always pre-load the guest FPU.
1523	* @remarks No-long-jump zone!!!
1524	*/
1525	static void hmR0SvmExportGuestCR0(PVMCPU pVCpu, PSVMVMCB pVmcb)
1526	{
1527	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1528
1529	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1530	uint64_t const uGuestCr0 = pCtx->cr0;
1531	uint64_t uShadowCr0 = uGuestCr0;
1532
1533	/* Always enable caching. */
1534	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1535
1536	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1537	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1538	{
1539	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1540	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1541	}
1542
1543	/*
1544	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1545	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1546	* see @bugref{7243#c103}.
1547	*/
1548	if (!(uGuestCr0 & X86_CR0_NE))
1549	{
1550	uShadowCr0 \|= X86_CR0_NE;
1551	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1552	}
1553	else
1554	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1555
1556	/*
1557	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1558	*
1559	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1560	* see @bugref{6944}.
1561	*
1562	* We also don't ever want to honor weird things like cache disable from the guest.
1563	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1564	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1565	*/
1566	if (uShadowCr0 == uGuestCr0)
1567	{
1568	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1569	{
1570	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1571	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1572	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1573	}
1574	else
1575	{
1576	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1577	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1578	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1579	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1580	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1581	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1582	}
1583	}
1584	else
1585	{
1586	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1587	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1588	}
1589	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1590
1591	Assert(!RT_HI_U32(uShadowCr0));
1592	if (pVmcb->guest.u64CR0 != uShadowCr0)
1593	{
1594	pVmcb->guest.u64CR0 = uShadowCr0;
1595	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1596	}
1597	}
1598
1599
1600	/**
1601	* Exports the guest (or nested-guest) CR3 into the VMCB.
1602	*
1603	* @param pVCpu The cross context virtual CPU structure.
1604	* @param pVmcb Pointer to the VM control block.
1605	*
1606	* @remarks No-long-jump zone!!!
1607	*/
1608	static void hmR0SvmExportGuestCR3(PVMCPU pVCpu, PSVMVMCB pVmcb)
1609	{
1610	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1611
1612	PVM pVM = pVCpu->CTX_SUFF(pVM);
1613	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1614	if (pVM->hm.s.fNestedPaging)
1615	{
1616	PGMMODE enmShwPagingMode;
1617	#if HC_ARCH_BITS == 32
1618	if (CPUMIsGuestInLongModeEx(pCtx))
1619	enmShwPagingMode = PGMMODE_AMD64_NX;
1620	else
1621	#endif
1622	enmShwPagingMode = PGMGetHostMode(pVM);
1623
1624	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1625	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1626	pVmcb->guest.u64CR3 = pCtx->cr3;
1627	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1628	}
1629	else
1630	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1631
1632	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1633	}
1634
1635
1636	/**
1637	* Exports the guest (or nested-guest) CR4 into the VMCB.
1638	*
1639	* @param pVCpu The cross context virtual CPU structure.
1640	* @param pVmcb Pointer to the VM control block.
1641	*
1642	* @remarks No-long-jump zone!!!
1643	*/
1644	static int hmR0SvmExportGuestCR4(PVMCPU pVCpu, PSVMVMCB pVmcb)
1645	{
1646	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1647
1648	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1649	uint64_t uShadowCr4 = pCtx->cr4;
1650	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1651	{
1652	switch (pVCpu->hm.s.enmShadowMode)
1653	{
1654	case PGMMODE_REAL:
1655	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1656	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1657
1658	case PGMMODE_32_BIT: /* 32-bit paging. */
1659	uShadowCr4 &= ~X86_CR4_PAE;
1660	break;
1661
1662	case PGMMODE_PAE: /* PAE paging. */
1663	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1664	/** Must use PAE paging as we could use physical memory > 4 GB */
1665	uShadowCr4 \|= X86_CR4_PAE;
1666	break;
1667
1668	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1669	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1670	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1671	break;
1672	#else
1673	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1674	#endif
1675
1676	default: /* shut up gcc */
1677	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1678	}
1679	}
1680
1681	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1682	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1683
1684	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1685	if (uShadowCr4 == pCtx->cr4)
1686	{
1687	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1688	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1689	else
1690	{
1691	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1692	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1693	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1694	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1695	}
1696	}
1697	else
1698	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1699
1700	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1701	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1702
1703	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1704	Assert(!RT_HI_U32(uShadowCr4));
1705	pVmcb->guest.u64CR4 = uShadowCr4;
1706	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1707
1708	return VINF_SUCCESS;
1709	}
1710
1711
1712	/**
1713	* Exports the guest (or nested-guest) control registers into the VMCB.
1714	*
1715	* @returns VBox status code.
1716	* @param pVCpu The cross context virtual CPU structure.
1717	* @param pVmcb Pointer to the VM control block.
1718	*
1719	* @remarks No-long-jump zone!!!
1720	*/
1721	static int hmR0SvmExportGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1722	{
1723	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1724
1725	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1726	{
1727	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1728	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1729
1730	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1731	{
1732	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1733	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1734	}
1735
1736	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1737	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1738
1739	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1740	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1741	{
1742	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1743	if (RT_FAILURE(rc))
1744	return rc;
1745	}
1746
1747	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1748	}
1749	return VINF_SUCCESS;
1750	}
1751
1752
1753	/**
1754	* Exports the guest (or nested-guest) segment registers into the VMCB.
1755	*
1756	* @returns VBox status code.
1757	* @param pVCpu The cross context virtual CPU structure.
1758	* @param pVmcb Pointer to the VM control block.
1759	*
1760	* @remarks No-long-jump zone!!!
1761	*/
1762	static void hmR0SvmExportGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1763	{
1764	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1765	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1766
1767	/* Guest segment registers. */
1768	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1769	{
1770	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1771	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1772
1773	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1774	{
1775	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1776	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1777	}
1778
1779	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1780	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1781
1782	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1783	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1784
1785	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1786	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1787
1788	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1789	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1790
1791	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1792	}
1793
1794	/* Guest TR. */
1795	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1796	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1797
1798	/* Guest LDTR. */
1799	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1800	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1801
1802	/* Guest GDTR. */
1803	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1804	{
1805	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1806	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1807	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1808	}
1809
1810	/* Guest IDTR. */
1811	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1812	{
1813	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1814	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1815	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1816	}
1817
1818	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1819	\| HM_CHANGED_GUEST_TABLE_MASK);
1820	}
1821
1822
1823	/**
1824	* Exports the guest (or nested-guest) MSRs into the VMCB.
1825	*
1826	* @param pVCpu The cross context virtual CPU structure.
1827	* @param pVmcb Pointer to the VM control block.
1828	*
1829	* @remarks No-long-jump zone!!!
1830	*/
1831	static void hmR0SvmExportGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1832	{
1833	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1834	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1835
1836	/* Guest Sysenter MSRs. */
1837	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1838	{
1839	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1840	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1841
1842	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1843	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1844
1845	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1846	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1847	}
1848
1849	/*
1850	* Guest EFER MSR.
1851	* AMD-V requires guest EFER.SVME to be set. Weird.
1852	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1853	*/
1854	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1855	{
1856	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1857	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1858	}
1859
1860	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1861	if ( !CPUMIsGuestInLongModeEx(pCtx)
1862	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1863	{
1864	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1865	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1866	}
1867
1868	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1869	{
1870	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1871	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1872	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1873	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1874	}
1875
1876	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1877	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1878
1879	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1880	\| HM_CHANGED_GUEST_EFER_MSR
1881	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1882	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1883
1884	/*
1885	* Setup the PAT MSR (applicable for Nested Paging only).
1886	*
1887	* While guests can modify and see the modified values through the shadow values,
1888	* we shall not honor any guest modifications of this MSR to ensure caching is always
1889	* enabled similar to how we clear CR0.CD and NW bits.
1890	*
1891	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1892	*/
1893	pVmcb->guest.u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
1894
1895	/* Enable the last branch record bit if LBR virtualization is enabled. */
1896	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1897	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1898	}
1899
1900
1901	/**
1902	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1903	* the necessary intercepts accordingly.
1904	*
1905	* @param pVCpu The cross context virtual CPU structure.
1906	* @param pVmcb Pointer to the VM control block.
1907	*
1908	* @remarks No-long-jump zone!!!
1909	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1910	*/
1911	static void hmR0SvmExportSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb)
1912	{
1913	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1914
1915	/*
1916	* Anyone single stepping on the host side? If so, we'll have to use the
1917	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1918	* the VMM level like the VT-x implementations does.
1919	*/
1920	bool fInterceptMovDRx = false;
1921	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1922	if (fStepping)
1923	{
1924	pVCpu->hm.s.fClearTrapFlag = true;
1925	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1926	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1927	}
1928
1929	if ( fStepping
1930	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1931	{
1932	/*
1933	* Use the combined guest and host DRx values found in the hypervisor
1934	* register set because the debugger has breakpoints active or someone
1935	* is single stepping on the host side.
1936	*
1937	* Note! DBGF expects a clean DR6 state before executing guest code.
1938	*/
1939	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1940	if ( CPUMIsGuestInLongModeEx(pCtx)
1941	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1942	{
1943	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1944	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1945	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1946	}
1947	else
1948	#endif
1949	if (!CPUMIsHyperDebugStateActive(pVCpu))
1950	{
1951	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1952	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1953	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1954	}
1955
1956	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1957	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1958	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1959	{
1960	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1961	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1962	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1963	}
1964
1965	/** @todo If we cared, we could optimize to allow the guest to read registers
1966	* with the same values. */
1967	fInterceptMovDRx = true;
1968	pVCpu->hm.s.fUsingHyperDR7 = true;
1969	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1970	}
1971	else
1972	{
1973	/*
1974	* Update DR6, DR7 with the guest values if necessary.
1975	*/
1976	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1977	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1978	{
1979	pVmcb->guest.u64DR7 = pCtx->dr[7];
1980	pVmcb->guest.u64DR6 = pCtx->dr[6];
1981	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1982	}
1983	pVCpu->hm.s.fUsingHyperDR7 = false;
1984
1985	/*
1986	* If the guest has enabled debug registers, we need to load them prior to
1987	* executing guest code so they'll trigger at the right time.
1988	*/
1989	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1990	{
1991	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1992	if ( CPUMIsGuestInLongModeEx(pCtx)
1993	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1994	{
1995	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1996	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1997	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1998	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1999	}
2000	else
2001	#endif
2002	if (!CPUMIsGuestDebugStateActive(pVCpu))
2003	{
2004	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
2005	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
2006	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2007	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2008	}
2009	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
2010	}
2011	/*
2012	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
2013	* intercept #DB as DR6 is updated in the VMCB.
2014	*
2015	* Note! If we cared and dared, we could skip intercepting \#DB here.
2016	* However, \#DB shouldn't be performance critical, so we'll play safe
2017	* and keep the code similar to the VT-x code and always intercept it.
2018	*/
2019	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
2020	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
2021	&& !CPUMIsGuestDebugStateActive(pVCpu))
2022	#else
2023	else if (!CPUMIsGuestDebugStateActive(pVCpu))
2024	#endif
2025	{
2026	fInterceptMovDRx = true;
2027	}
2028	}
2029
2030	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
2031	if (fInterceptMovDRx)
2032	{
2033	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
2034	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
2035	{
2036	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
2037	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
2038	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2039	}
2040	}
2041	else
2042	{
2043	if ( pVmcb->ctrl.u16InterceptRdDRx
2044	\|\| pVmcb->ctrl.u16InterceptWrDRx)
2045	{
2046	pVmcb->ctrl.u16InterceptRdDRx = 0;
2047	pVmcb->ctrl.u16InterceptWrDRx = 0;
2048	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2049	}
2050	}
2051	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2052	}
2053
2054	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2055	/**
2056	* Exports the nested-guest hardware virtualization state into the nested-guest
2057	* VMCB.
2058	*
2059	* @param pVCpu The cross context virtual CPU structure.
2060	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2061	*
2062	* @remarks No-long-jump zone!!!
2063	*/
2064	static void hmR0SvmExportGuestHwvirtStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
2065	{
2066	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2067
2068	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
2069	{
2070	/*
2071	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2072	* since SVM doesn't have a preemption timer.
2073	*
2074	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
2075	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2076	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2077	*/
2078	PVM pVM = pVCpu->CTX_SUFF(pVM);
2079	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2080	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2081	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2082	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_PAUSE))
2083	{
2084	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2085	pVmcbNstGstCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2086	pVmcbNstGstCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2087	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2088	}
2089	else
2090	{
2091	pVmcbNstGstCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2092	pVmcbNstGstCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2093	}
2094
2095	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
2096	}
2097	}
2098	#endif
2099
2100	/**
2101	* Exports the guest APIC TPR state into the VMCB.
2102	*
2103	* @returns VBox status code.
2104	* @param pVCpu The cross context virtual CPU structure.
2105	* @param pVmcb Pointer to the VM control block.
2106	*/
2107	static int hmR0SvmExportGuestApicTpr(PVMCPU pVCpu, PSVMVMCB pVmcb)
2108	{
2109	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2110	{
2111	PVM pVM = pVCpu->CTX_SUFF(pVM);
2112	if ( PDMHasApic(pVM)
2113	&& APICIsEnabled(pVCpu))
2114	{
2115	bool fPendingIntr;
2116	uint8_t u8Tpr;
2117	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2118	AssertRCReturn(rc, rc);
2119
2120	/* Assume that we need to trap all TPR accesses and thus need not check on
2121	every #VMEXIT if we should update the TPR. */
2122	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2123	pVCpu->hm.s.svm.fSyncVTpr = false;
2124
2125	if (!pVM->hm.s.fTPRPatchingActive)
2126	{
2127	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2128	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2129
2130	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2131	can deliver the interrupt to the guest. */
2132	if (fPendingIntr)
2133	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2134	else
2135	{
2136	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2137	pVCpu->hm.s.svm.fSyncVTpr = true;
2138	}
2139
2140	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2141	}
2142	else
2143	{
2144	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2145	pVmcb->guest.u64LSTAR = u8Tpr;
2146	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
2147
2148	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2149	if (fPendingIntr)
2150	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2151	else
2152	{
2153	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2154	pVCpu->hm.s.svm.fSyncVTpr = true;
2155	}
2156	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2157	}
2158	}
2159	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2160	}
2161	return VINF_SUCCESS;
2162	}
2163
2164
2165	/**
2166	* Sets up the exception interrupts required for guest (or nested-guest)
2167	* execution in the VMCB.
2168	*
2169	* @param pVCpu The cross context virtual CPU structure.
2170	* @param pVmcb Pointer to the VM control block.
2171	*
2172	* @remarks No-long-jump zone!!!
2173	*/
2174	static void hmR0SvmExportGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb)
2175	{
2176	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2177
2178	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2179	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS)
2180	{
2181	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2182	if (pVCpu->hm.s.fGIMTrapXcptUD)
2183	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2184	else
2185	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2186
2187	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2188	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2189	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2190	else
2191	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2192
2193	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2194	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS;
2195	}
2196	}
2197
2198
2199	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2200	/**
2201	* Merges guest and nested-guest intercepts for executing the nested-guest using
2202	* hardware-assisted SVM.
2203	*
2204	* This merges the guest and nested-guest intercepts in a way that if the outer
2205	* guest intercept is set we need to intercept it in the nested-guest as
2206	* well.
2207	*
2208	* @param pVCpu The cross context virtual CPU structure.
2209	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2210	*/
2211	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPU pVCpu)
2212	{
2213	PVM pVM = pVCpu->CTX_SUFF(pVM);
2214	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2215	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2216	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2217
2218	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2219	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2220	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2221
2222	/* Always intercept CR4 writes for tracking PGM mode changes. */
2223	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2224
2225	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2226	if (!pVM->hm.s.fNestedPaging)
2227	{
2228	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2229	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2230	}
2231
2232	/** @todo Figure out debugging with nested-guests, till then just intercept
2233	* all DR[0-15] accesses. */
2234	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2235	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2236
2237	/*
2238	* Merge the guest's exception intercepts into the nested-guest VMCB.
2239	*
2240	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2241	* while executing the nested-guest.
2242	*
2243	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2244	* be tweaked later depending on how we wish to implement breakpoints.
2245	*
2246	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2247	* loaded into their guests, not ours.
2248	*
2249	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2250	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2251	*/
2252	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2253	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2254	& ~( RT_BIT(X86_XCPT_UD)
2255	\| RT_BIT(X86_XCPT_BP)
2256	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2257	#else
2258	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2259	#endif
2260
2261	/*
2262	* Adjust intercepts while executing the nested-guest that differ from the
2263	* outer guest intercepts.
2264	*
2265	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2266	* that belong to the nested-guest to the outer guest.
2267	*
2268	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2269	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2270	*/
2271	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2272	\| SVM_CTRL_INTERCEPT_VMMCALL))
2273	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2274
2275	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2276	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2277
2278	/* Finally, update the VMCB clean bits. */
2279	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2280	}
2281	#endif
2282
2283
2284	/**
2285	* Selects the appropriate function to run guest code.
2286	*
2287	* @returns VBox status code.
2288	* @param pVCpu The cross context virtual CPU structure.
2289	*
2290	* @remarks No-long-jump zone!!!
2291	*/
2292	static int hmR0SvmSelectVMRunHandler(PVMCPU pVCpu)
2293	{
2294	if (CPUMIsGuestInLongMode(pVCpu))
2295	{
2296	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2297	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2298	#endif
2299	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2300	#if HC_ARCH_BITS == 32
2301	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2302	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2303	#else
2304	/* 64-bit host or hybrid host. */
2305	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2306	#endif
2307	}
2308	else
2309	{
2310	/* Guest is not in long mode, use the 32-bit handler. */
2311	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2312	}
2313	return VINF_SUCCESS;
2314	}
2315
2316
2317	/**
2318	* Enters the AMD-V session.
2319	*
2320	* @returns VBox status code.
2321	* @param pVCpu The cross context virtual CPU structure.
2322	* @param pHostCpu Pointer to the CPU info struct.
2323	*/
2324	VMMR0DECL(int) SVMR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
2325	{
2326	AssertPtr(pVCpu);
2327	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2328	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2329	RT_NOREF(pHostCpu);
2330
2331	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2332	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2333	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2334
2335	pVCpu->hm.s.fLeaveDone = false;
2336	return VINF_SUCCESS;
2337	}
2338
2339
2340	/**
2341	* Thread-context callback for AMD-V.
2342	*
2343	* @param enmEvent The thread-context event.
2344	* @param pVCpu The cross context virtual CPU structure.
2345	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2346	* @thread EMT(pVCpu)
2347	*/
2348	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2349	{
2350	NOREF(fGlobalInit);
2351
2352	switch (enmEvent)
2353	{
2354	case RTTHREADCTXEVENT_OUT:
2355	{
2356	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2357	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2358	VMCPU_ASSERT_EMT(pVCpu);
2359
2360	/* No longjmps (log-flush, locks) in this fragile context. */
2361	VMMRZCallRing3Disable(pVCpu);
2362
2363	if (!pVCpu->hm.s.fLeaveDone)
2364	{
2365	hmR0SvmLeave(pVCpu, false /* fImportState */);
2366	pVCpu->hm.s.fLeaveDone = true;
2367	}
2368
2369	/* Leave HM context, takes care of local init (term). */
2370	int rc = HMR0LeaveCpu(pVCpu);
2371	AssertRC(rc); NOREF(rc);
2372
2373	/* Restore longjmp state. */
2374	VMMRZCallRing3Enable(pVCpu);
2375	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2376	break;
2377	}
2378
2379	case RTTHREADCTXEVENT_IN:
2380	{
2381	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2382	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2383	VMCPU_ASSERT_EMT(pVCpu);
2384
2385	/* No longjmps (log-flush, locks) in this fragile context. */
2386	VMMRZCallRing3Disable(pVCpu);
2387
2388	/*
2389	* Initialize the bare minimum state required for HM. This takes care of
2390	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2391	*/
2392	int rc = hmR0EnterCpu(pVCpu);
2393	AssertRC(rc); NOREF(rc);
2394	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2395	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2396
2397	pVCpu->hm.s.fLeaveDone = false;
2398
2399	/* Restore longjmp state. */
2400	VMMRZCallRing3Enable(pVCpu);
2401	break;
2402	}
2403
2404	default:
2405	break;
2406	}
2407	}
2408
2409
2410	/**
2411	* Saves the host state.
2412	*
2413	* @returns VBox status code.
2414	* @param pVCpu The cross context virtual CPU structure.
2415	*
2416	* @remarks No-long-jump zone!!!
2417	*/
2418	VMMR0DECL(int) SVMR0ExportHostState(PVMCPU pVCpu)
2419	{
2420	NOREF(pVCpu);
2421
2422	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2423	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2424	return VINF_SUCCESS;
2425	}
2426
2427
2428	/**
2429	* Exports the guest state from the guest-CPU context into the VMCB.
2430	*
2431	* The CPU state will be loaded from these fields on every successful VM-entry.
2432	* Also sets up the appropriate VMRUN function to execute guest code based on
2433	* the guest CPU mode.
2434	*
2435	* @returns VBox status code.
2436	* @param pVCpu The cross context virtual CPU structure.
2437	*
2438	* @remarks No-long-jump zone!!!
2439	*/
2440	static int hmR0SvmExportGuestState(PVMCPU pVCpu)
2441	{
2442	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2443
2444	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2445	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2446
2447	Assert(pVmcb);
2448	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2449
2450	pVmcb->guest.u64RIP = pCtx->rip;
2451	pVmcb->guest.u64RSP = pCtx->rsp;
2452	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2453	pVmcb->guest.u64RAX = pCtx->rax;
2454	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2455	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2456	{
2457	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Hardware supports it. */
2458	Assert(HMSvmIsVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2459	pVmcb->ctrl.IntCtrl.n.u1VGif = pCtx->hwvirt.fGif;
2460	}
2461	#endif
2462
2463	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2464
2465	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2466	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2467
2468	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2469	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2470	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2471
2472	ASMSetFlags(fEFlags);
2473
2474	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2475	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2476	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2477
2478	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2479	AssertRCReturn(rc, rc);
2480
2481	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2482	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2483	\| HM_CHANGED_GUEST_RFLAGS
2484	\| HM_CHANGED_GUEST_GPRS_MASK
2485	\| HM_CHANGED_GUEST_X87
2486	\| HM_CHANGED_GUEST_SSE_AVX
2487	\| HM_CHANGED_GUEST_OTHER_XSAVE
2488	\| HM_CHANGED_GUEST_XCRx
2489	\| HM_CHANGED_GUEST_TSC_AUX
2490	\| HM_CHANGED_GUEST_OTHER_MSRS
2491	\| HM_CHANGED_GUEST_HWVIRT
2492	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS)));
2493
2494	#ifdef VBOX_STRICT
2495	/*
2496	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2497	* except for the host-context and/or shared host-guest context bits.
2498	*/
2499	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2500	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2501	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2502	("fCtxChanged=%#RX64\n", fCtxChanged));
2503
2504	/*
2505	* If we need to log state that isn't always imported, we'll need to import them here.
2506	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2507	*/
2508	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2509	#endif
2510
2511	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2512	return VINF_SUCCESS;
2513	}
2514
2515
2516	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2517	/**
2518	* Merges the guest and nested-guest MSR permission bitmap.
2519	*
2520	* If the guest is intercepting an MSR we need to intercept it regardless of
2521	* whether the nested-guest is intercepting it or not.
2522	*
2523	* @param pHostCpu Pointer to the physical CPU HM info. struct.
2524	* @param pVCpu The cross context virtual CPU structure.
2525	*
2526	* @remarks No-long-jmp zone!!!
2527	*/
2528	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMGLOBALCPUINFO pHostCpu, PVMCPU pVCpu)
2529	{
2530	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2531	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2532	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2533
2534	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2535	uint32_t const offRsvdQwords = 0x1800 >> 3;
2536	for (uint32_t i = 0; i < offRsvdQwords; i++)
2537	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2538	}
2539
2540
2541	/**
2542	* Caches the nested-guest VMCB fields before we modify them for execution using
2543	* hardware-assisted SVM.
2544	*
2545	* @returns true if the VMCB was previously already cached, false otherwise.
2546	* @param pVCpu The cross context virtual CPU structure.
2547	*
2548	* @sa HMSvmNstGstVmExitNotify.
2549	*/
2550	static bool hmR0SvmCacheVmcbNested(PVMCPU pVCpu)
2551	{
2552	/*
2553	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2554	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2555	*
2556	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2557	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2558	*/
2559	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2560	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2561	if (!fWasCached)
2562	{
2563	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2564	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2565	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2566	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2567	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2568	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2569	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2570	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2571	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2572	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2573	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2574	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2575	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2576	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2577	pVmcbNstGstCache->fCacheValid = true;
2578	Log4Func(("Cached VMCB fields\n"));
2579	}
2580
2581	return fWasCached;
2582	}
2583
2584
2585	/**
2586	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2587	*
2588	* This is done the first time we enter nested-guest execution using SVM R0
2589	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2590	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2591	*
2592	* @param pVCpu The cross context virtual CPU structure.
2593	*/
2594	static void hmR0SvmSetupVmcbNested(PVMCPU pVCpu)
2595	{
2596	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2597	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2598
2599	/*
2600	* First cache the nested-guest VMCB fields we may potentially modify.
2601	*/
2602	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2603	if (!fVmcbCached)
2604	{
2605	/*
2606	* The IOPM of the nested-guest can be ignored because the the guest always
2607	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2608	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2609	*/
2610	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2611
2612	/*
2613	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2614	* nested-paging suddenly while executing a VM (see assertion at the end of
2615	* Trap0eHandler() in PGMAllBth.h).
2616	*/
2617	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2618
2619	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2620	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2621
2622	/*
2623	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2624	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2625	*/
2626	pVCpu->hm.s.svm.fSyncVTpr = false;
2627
2628	#ifdef DEBUG_ramshankar
2629	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2630	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2631	#endif
2632
2633	/*
2634	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2635	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2636	*/
2637	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2638	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2639	\| SVM_CTRL_INTERCEPT_VMLOAD;
2640
2641	/*
2642	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2643	* CLGI/STGI instructions executed by the nested-guest.
2644	*/
2645	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2646	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2647	\| SVM_CTRL_INTERCEPT_STGI;
2648
2649	/* Merge the guest and nested-guest intercepts. */
2650	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2651
2652	/* Update the VMCB clean bits. */
2653	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2654	}
2655	else
2656	{
2657	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
2658	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2659	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2660	}
2661	}
2662
2663
2664	/**
2665	* Exports the nested-guest state into the VMCB.
2666	*
2667	* We need to export the entire state as we could be continuing nested-guest
2668	* execution at any point (not just immediately after VMRUN) and thus the VMCB
2669	* can be out-of-sync with the nested-guest state if it was executed in IEM.
2670	*
2671	* @returns VBox status code.
2672	* @param pVCpu The cross context virtual CPU structure.
2673	* @param pCtx Pointer to the guest-CPU context.
2674	*
2675	* @remarks No-long-jump zone!!!
2676	*/
2677	static int hmR0SvmExportGuestStateNested(PVMCPU pVCpu)
2678	{
2679	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2680
2681	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2682	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2683	Assert(pVmcbNstGst);
2684
2685	hmR0SvmSetupVmcbNested(pVCpu);
2686
2687	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2688	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2689	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2690	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2691
2692	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2693
2694	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcbNstGst);
2695	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2696
2697	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcbNstGst);
2698	hmR0SvmExportGuestMsrs(pVCpu, pVmcbNstGst);
2699	hmR0SvmExportGuestHwvirtStateNested(pVCpu, pVmcbNstGst);
2700
2701	ASMSetFlags(fEFlags);
2702
2703	/* Nested VGIF not supported yet. */
2704	Assert(!pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable);
2705
2706	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2707	AssertRCReturn(rc, rc);
2708
2709	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2710	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2711	\| HM_CHANGED_GUEST_RFLAGS
2712	\| HM_CHANGED_GUEST_GPRS_MASK
2713	\| HM_CHANGED_GUEST_APIC_TPR
2714	\| HM_CHANGED_GUEST_X87
2715	\| HM_CHANGED_GUEST_SSE_AVX
2716	\| HM_CHANGED_GUEST_OTHER_XSAVE
2717	\| HM_CHANGED_GUEST_XCRx
2718	\| HM_CHANGED_GUEST_TSC_AUX
2719	\| HM_CHANGED_GUEST_OTHER_MSRS
2720	\| HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS
2721	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2722
2723	#ifdef VBOX_STRICT
2724	/*
2725	* All of the guest-CPU state and SVM keeper bits should be exported here by now, except
2726	* for the host-context and/or shared host-guest context bits.
2727	*/
2728	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2729	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2730	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2731	("fCtxChanged=%#RX64\n", fCtxChanged));
2732
2733	/*
2734	* If we need to log state that isn't always imported, we'll need to import them here.
2735	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2736	*/
2737	hmR0SvmLogState(pVCpu, pVmcbNstGst, "hmR0SvmExportGuestStateNested", 0 /* fFlags /, 0 / uVerbose */);
2738	#endif
2739
2740	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2741	return rc;
2742	}
2743	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2744
2745
2746	/**
2747	* Exports the state shared between the host and guest (or nested-guest) into
2748	* the VMCB.
2749	*
2750	* @param pVCpu The cross context virtual CPU structure.
2751	* @param pVmcb Pointer to the VM control block.
2752	*
2753	* @remarks No-long-jump zone!!!
2754	*/
2755	static void hmR0SvmExportSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb)
2756	{
2757	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2758	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2759
2760	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2761	{
2762	/** @todo Figure out stepping with nested-guest. */
2763	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2764	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2765	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2766	else
2767	{
2768	pVmcb->guest.u64DR6 = pCtx->dr[6];
2769	pVmcb->guest.u64DR7 = pCtx->dr[7];
2770	}
2771	}
2772
2773	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2774	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2775	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2776	}
2777
2778
2779	/**
2780	* Worker for SVMR0ImportStateOnDemand.
2781	*
2782	* @param pVCpu The cross context virtual CPU structure.
2783	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2784	*/
2785	static void hmR0SvmImportGuestState(PVMCPU pVCpu, uint64_t fWhat)
2786	{
2787	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2788
2789	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2790	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2791	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2792	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2793
2794	Log4Func(("fExtrn=%#RX64 fWhat=%#RX64\n", pCtx->fExtrn, fWhat));
2795
2796	/*
2797	* We disable interrupts to make the updating of the state and in particular
2798	* the fExtrn modification atomic wrt to preemption hooks.
2799	*/
2800	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2801
2802	fWhat &= pCtx->fExtrn;
2803	if (fWhat)
2804	{
2805	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2806	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2807	{
2808	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2809	{
2810	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2811	Assert(HMSvmIsVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2812	pCtx->hwvirt.fGif = pVmcbCtrl->IntCtrl.n.u1VGif;
2813	}
2814	}
2815
2816	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2817	{
2818	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2819	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2820	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2821	}
2822	#endif
2823
2824	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2825	{
2826	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2827	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2828	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2829	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2830	}
2831
2832	if (fWhat & CPUMCTX_EXTRN_RIP)
2833	pCtx->rip = pVmcbGuest->u64RIP;
2834
2835	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2836	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2837
2838	if (fWhat & CPUMCTX_EXTRN_RSP)
2839	pCtx->rsp = pVmcbGuest->u64RSP;
2840
2841	if (fWhat & CPUMCTX_EXTRN_RAX)
2842	pCtx->rax = pVmcbGuest->u64RAX;
2843
2844	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2845	{
2846	if (fWhat & CPUMCTX_EXTRN_CS)
2847	{
2848	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2849	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2850	/** @todo SELM might need to be fixed as it too should not care about the
2851	* granularity bit. See @bugref{6785}. */
2852	if ( !pCtx->cs.Attr.n.u1Granularity
2853	&& pCtx->cs.Attr.n.u1Present
2854	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2855	{
2856	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2857	pCtx->cs.Attr.n.u1Granularity = 1;
2858	}
2859	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2860	}
2861	if (fWhat & CPUMCTX_EXTRN_SS)
2862	{
2863	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2864	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2865	/*
2866	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2867	* VMCB and uses that and thus it's possible that when the CPL changes during
2868	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2869	* AMD Fusion CPUs with 64-bit guests.
2870	*
2871	* See AMD spec. 15.5.1 "Basic operation".
2872	*/
2873	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2874	uint8_t const uCpl = pVmcbGuest->u8CPL;
2875	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2876	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2877	}
2878	if (fWhat & CPUMCTX_EXTRN_DS)
2879	{
2880	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2881	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2882	}
2883	if (fWhat & CPUMCTX_EXTRN_ES)
2884	{
2885	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2886	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2887	}
2888	if (fWhat & CPUMCTX_EXTRN_FS)
2889	{
2890	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2891	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2892	}
2893	if (fWhat & CPUMCTX_EXTRN_GS)
2894	{
2895	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2896	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2897	}
2898	}
2899
2900	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2901	{
2902	if (fWhat & CPUMCTX_EXTRN_TR)
2903	{
2904	/*
2905	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2906	* are used between Intel and AMD, see @bugref{6208#c39}.
2907	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2908	*/
2909	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2910	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2911	{
2912	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2913	\|\| CPUMIsGuestInLongModeEx(pCtx))
2914	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2915	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2916	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2917	}
2918	}
2919
2920	if (fWhat & CPUMCTX_EXTRN_LDTR)
2921	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2922
2923	if (fWhat & CPUMCTX_EXTRN_GDTR)
2924	{
2925	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2926	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2927	}
2928
2929	if (fWhat & CPUMCTX_EXTRN_IDTR)
2930	{
2931	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2932	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2933	}
2934	}
2935
2936	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2937	{
2938	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2939	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2940	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2941	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2942	}
2943
2944	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2945	{
2946	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2947	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2948	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2949	}
2950
2951	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2952	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2953
2954	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2955	{
2956	if (fWhat & CPUMCTX_EXTRN_DR6)
2957	{
2958	if (!pVCpu->hm.s.fUsingHyperDR7)
2959	pCtx->dr[6] = pVmcbGuest->u64DR6;
2960	else
2961	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2962	}
2963
2964	if (fWhat & CPUMCTX_EXTRN_DR7)
2965	{
2966	if (!pVCpu->hm.s.fUsingHyperDR7)
2967	pCtx->dr[7] = pVmcbGuest->u64DR7;
2968	else
2969	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2970	}
2971	}
2972
2973	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2974	{
2975	if (fWhat & CPUMCTX_EXTRN_CR0)
2976	{
2977	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2978	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2979	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2980	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2981	CPUMSetGuestCR0(pVCpu, uCr0);
2982	VMMRZCallRing3Enable(pVCpu);
2983	}
2984
2985	if (fWhat & CPUMCTX_EXTRN_CR2)
2986	pCtx->cr2 = pVmcbGuest->u64CR2;
2987
2988	if (fWhat & CPUMCTX_EXTRN_CR3)
2989	{
2990	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2991	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2992	{
2993	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2994	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2995	}
2996	}
2997
2998	/* Changes to CR4 are always intercepted. */
2999	}
3000
3001	/* Update fExtrn. */
3002	pCtx->fExtrn &= ~fWhat;
3003
3004	/* If everything has been imported, clear the HM keeper bit. */
3005	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
3006	{
3007	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
3008	Assert(!pCtx->fExtrn);
3009	}
3010	}
3011	else
3012	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3013
3014	ASMSetFlags(fEFlags);
3015
3016	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
3017
3018	/*
3019	* Honor any pending CR3 updates.
3020	*
3021	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
3022	* -> hmR0SvmCallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
3023	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
3024	* handling -> hmR0SvmImportGuestState() and here we are.
3025	*
3026	* The reason for such complicated handling is because VM-exits that call into PGM expect
3027	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
3028	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
3029	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
3030	*
3031	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
3032	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
3033	*/
3034	if ( VMMRZCallRing3IsEnabled(pVCpu)
3035	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3036	{
3037	Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
3038	PGMUpdateCR3(pVCpu, pCtx->cr3);
3039	}
3040	}
3041
3042
3043	/**
3044	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
3045	* context.
3046	*
3047	* Currently there is no residual state left in the CPU that is not updated in the
3048	* VMCB.
3049	*
3050	* @returns VBox status code.
3051	* @param pVCpu The cross context virtual CPU structure.
3052	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
3053	*/
3054	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
3055	{
3056	hmR0SvmImportGuestState(pVCpu, fWhat);
3057	return VINF_SUCCESS;
3058	}
3059
3060
3061	/**
3062	* Does the necessary state syncing before returning to ring-3 for any reason
3063	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
3064	*
3065	* @param pVCpu The cross context virtual CPU structure.
3066	* @param fImportState Whether to import the guest state from the VMCB back
3067	* to the guest-CPU context.
3068	*
3069	* @remarks No-long-jmp zone!!!
3070	*/
3071	static void hmR0SvmLeave(PVMCPU pVCpu, bool fImportState)
3072	{
3073	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3074	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3075	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3076
3077	/*
3078	* !!! IMPORTANT !!!
3079	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
3080	*/
3081
3082	/* Save the guest state if necessary. */
3083	if (fImportState)
3084	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3085
3086	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3087	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3088	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
3089
3090	/*
3091	* Restore host debug registers if necessary and resync on next R0 reentry.
3092	*/
3093	#ifdef VBOX_STRICT
3094	if (CPUMIsHyperDebugStateActive(pVCpu))
3095	{
3096	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
3097	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
3098	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
3099	}
3100	#endif
3101	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3102	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
3103	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
3104
3105	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
3106	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
3107	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
3108	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
3109	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
3110	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3111
3112	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
3113	}
3114
3115
3116	/**
3117	* Leaves the AMD-V session.
3118	*
3119	* Only used while returning to ring-3 either due to longjump or exits to
3120	* ring-3.
3121	*
3122	* @returns VBox status code.
3123	* @param pVCpu The cross context virtual CPU structure.
3124	*/
3125	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
3126	{
3127	HM_DISABLE_PREEMPT(pVCpu);
3128	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3129	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3130
3131	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3132	and done this from the SVMR0ThreadCtxCallback(). */
3133	if (!pVCpu->hm.s.fLeaveDone)
3134	{
3135	hmR0SvmLeave(pVCpu, true /* fImportState */);
3136	pVCpu->hm.s.fLeaveDone = true;
3137	}
3138
3139	/*
3140	* !!! IMPORTANT !!!
3141	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
3142	*/
3143
3144	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3145	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3146	VMMR0ThreadCtxHookDisable(pVCpu);
3147
3148	/* Leave HM context. This takes care of local init (term). */
3149	int rc = HMR0LeaveCpu(pVCpu);
3150
3151	HM_RESTORE_PREEMPT();
3152	return rc;
3153	}
3154
3155
3156	/**
3157	* Does the necessary state syncing before doing a longjmp to ring-3.
3158	*
3159	* @returns VBox status code.
3160	* @param pVCpu The cross context virtual CPU structure.
3161	*
3162	* @remarks No-long-jmp zone!!!
3163	*/
3164	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
3165	{
3166	return hmR0SvmLeaveSession(pVCpu);
3167	}
3168
3169
3170	/**
3171	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3172	* any remaining host state) before we longjump to ring-3 and possibly get
3173	* preempted.
3174	*
3175	* @param pVCpu The cross context virtual CPU structure.
3176	* @param enmOperation The operation causing the ring-3 longjump.
3177	* @param pvUser The user argument, NULL (currently unused).
3178	*/
3179	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
3180	{
3181	RT_NOREF_PV(pvUser);
3182
3183	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3184	{
3185	/*
3186	* !!! IMPORTANT !!!
3187	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3188	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3189	*/
3190	VMMRZCallRing3RemoveNotification(pVCpu);
3191	VMMRZCallRing3Disable(pVCpu);
3192	HM_DISABLE_PREEMPT(pVCpu);
3193
3194	/* Import the entire guest state. */
3195	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3196
3197	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3198	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3199
3200	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3201	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3202
3203	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3204	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3205	VMMR0ThreadCtxHookDisable(pVCpu);
3206
3207	/* Leave HM context. This takes care of local init (term). */
3208	HMR0LeaveCpu(pVCpu);
3209
3210	HM_RESTORE_PREEMPT();
3211	return VINF_SUCCESS;
3212	}
3213
3214	Assert(pVCpu);
3215	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3216	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3217
3218	VMMRZCallRing3Disable(pVCpu);
3219	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3220
3221	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3222	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3223	AssertRCReturn(rc, rc);
3224
3225	VMMRZCallRing3Enable(pVCpu);
3226	return VINF_SUCCESS;
3227	}
3228
3229
3230	/**
3231	* Take necessary actions before going back to ring-3.
3232	*
3233	* An action requires us to go back to ring-3. This function does the necessary
3234	* steps before we can safely return to ring-3. This is not the same as longjmps
3235	* to ring-3, this is voluntary.
3236	*
3237	* @returns VBox status code.
3238	* @param pVCpu The cross context virtual CPU structure.
3239	* @param rcExit The reason for exiting to ring-3. Can be
3240	* VINF_VMM_UNKNOWN_RING3_CALL.
3241	*/
3242	static int hmR0SvmExitToRing3(PVMCPU pVCpu, int rcExit)
3243	{
3244	Assert(pVCpu);
3245	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3246
3247	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3248	VMMRZCallRing3Disable(pVCpu);
3249	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", rcExit, (uint64_t)pVCpu->fLocalForcedActions,
3250	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3251
3252	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3253	if (pVCpu->hm.s.Event.fPending)
3254	{
3255	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3256	Assert(!pVCpu->hm.s.Event.fPending);
3257	}
3258
3259	/* Sync. the necessary state for going back to ring-3. */
3260	hmR0SvmLeaveSession(pVCpu);
3261	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3262
3263	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3264	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3265	\| CPUM_CHANGED_LDTR
3266	\| CPUM_CHANGED_GDTR
3267	\| CPUM_CHANGED_IDTR
3268	\| CPUM_CHANGED_TR
3269	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3270	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
3271	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3272	{
3273	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3274	}
3275
3276	/* Update the exit-to-ring 3 reason. */
3277	pVCpu->hm.s.rcLastExitToR3 = rcExit;
3278
3279	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3280	if ( rcExit != VINF_EM_RAW_INTERRUPT
3281	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3282	{
3283	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3284	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3285	}
3286
3287	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3288
3289	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
3290	VMMRZCallRing3RemoveNotification(pVCpu);
3291	VMMRZCallRing3Enable(pVCpu);
3292
3293	/*
3294	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3295	* and if we're injecting an event we should have a TRPM trap pending.
3296	*/
3297	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3298	pVCpu->hm.s.u32HMError = rcExit,
3299	VERR_SVM_IPE_5);
3300	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3301	pVCpu->hm.s.u32HMError = rcExit,
3302	VERR_SVM_IPE_4);
3303
3304	return rcExit;
3305	}
3306
3307
3308	/**
3309	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3310	* intercepts.
3311	*
3312	* @param pVCpu The cross context virtual CPU structure.
3313	* @param pVmcb Pointer to the VM control block.
3314	*
3315	* @remarks No-long-jump zone!!!
3316	*/
3317	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3318	{
3319	/*
3320	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3321	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3322	* RDTSC/RDTSCP as well.
3323	*/
3324	bool fParavirtTsc;
3325	uint64_t uTscOffset;
3326	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3327
3328	bool fIntercept;
3329	if (fCanUseRealTsc)
3330	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3331	else
3332	{
3333	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3334	fIntercept = true;
3335	}
3336
3337	if (!fIntercept)
3338	{
3339	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3340	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3341	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3342	uTscOffset = HMSvmNstGstApplyTscOffset(pVCpu, uTscOffset);
3343	#endif
3344
3345	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3346	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3347	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3348
3349	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
3350	}
3351	else
3352	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
3353
3354	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3355	information before every VM-entry, hence we have nothing to do here at the moment. */
3356	if (fParavirtTsc)
3357	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3358	}
3359
3360
3361	/**
3362	* Sets an event as a pending event to be injected into the guest.
3363	*
3364	* @param pVCpu The cross context virtual CPU structure.
3365	* @param pEvent Pointer to the SVM event.
3366	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3367	* page-fault.
3368	*
3369	* @remarks Statistics counter assumes this is a guest event being reflected to
3370	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3371	*/
3372	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3373	{
3374	Assert(!pVCpu->hm.s.Event.fPending);
3375	Assert(pEvent->n.u1Valid);
3376
3377	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3378	pVCpu->hm.s.Event.fPending = true;
3379	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3380
3381	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3382	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3383	}
3384
3385
3386	/**
3387	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3388	*
3389	* @param pVCpu The cross context virtual CPU structure.
3390	*/
3391	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3392	{
3393	SVMEVENT Event;
3394	Event.u = 0;
3395	Event.n.u1Valid = 1;
3396	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3397	Event.n.u8Vector = X86_XCPT_UD;
3398	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3399	}
3400
3401
3402	/**
3403	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3404	*
3405	* @param pVCpu The cross context virtual CPU structure.
3406	*/
3407	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3408	{
3409	SVMEVENT Event;
3410	Event.u = 0;
3411	Event.n.u1Valid = 1;
3412	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3413	Event.n.u8Vector = X86_XCPT_DB;
3414	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3415	}
3416
3417
3418	/**
3419	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3420	*
3421	* @param pVCpu The cross context virtual CPU structure.
3422	* @param u32ErrCode The error-code for the page-fault.
3423	* @param uFaultAddress The page fault address (CR2).
3424	*
3425	* @remarks This updates the guest CR2 with @a uFaultAddress!
3426	*/
3427	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3428	{
3429	SVMEVENT Event;
3430	Event.u = 0;
3431	Event.n.u1Valid = 1;
3432	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3433	Event.n.u8Vector = X86_XCPT_PF;
3434	Event.n.u1ErrorCodeValid = 1;
3435	Event.n.u32ErrorCode = u32ErrCode;
3436
3437	/* Update CR2 of the guest. */
3438	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3439	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3440	{
3441	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3442	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3443	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3444	}
3445
3446	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3447	}
3448
3449
3450	/**
3451	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3452	*
3453	* @param pVCpu The cross context virtual CPU structure.
3454	*/
3455	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3456	{
3457	SVMEVENT Event;
3458	Event.u = 0;
3459	Event.n.u1Valid = 1;
3460	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3461	Event.n.u8Vector = X86_XCPT_MF;
3462	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3463	}
3464
3465
3466	/**
3467	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3468	*
3469	* @param pVCpu The cross context virtual CPU structure.
3470	*/
3471	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3472	{
3473	SVMEVENT Event;
3474	Event.u = 0;
3475	Event.n.u1Valid = 1;
3476	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3477	Event.n.u8Vector = X86_XCPT_DF;
3478	Event.n.u1ErrorCodeValid = 1;
3479	Event.n.u32ErrorCode = 0;
3480	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3481	}
3482
3483
3484	/**
3485	* Injects an event into the guest upon VMRUN by updating the relevant field
3486	* in the VMCB.
3487	*
3488	* @param pVCpu The cross context virtual CPU structure.
3489	* @param pVmcb Pointer to the guest VM control block.
3490	* @param pEvent Pointer to the event.
3491	*
3492	* @remarks No-long-jump zone!!!
3493	* @remarks Requires CR0!
3494	*/
3495	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3496	{
3497	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3498	pVmcb->ctrl.EventInject.u = pEvent->u;
3499	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3500	RT_NOREF(pVCpu);
3501
3502	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3503	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3504	}
3505
3506
3507
3508	/**
3509	* Converts any TRPM trap into a pending HM event. This is typically used when
3510	* entering from ring-3 (not longjmp returns).
3511	*
3512	* @param pVCpu The cross context virtual CPU structure.
3513	*/
3514	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3515	{
3516	Assert(TRPMHasTrap(pVCpu));
3517	Assert(!pVCpu->hm.s.Event.fPending);
3518
3519	uint8_t uVector;
3520	TRPMEVENT enmTrpmEvent;
3521	RTGCUINT uErrCode;
3522	RTGCUINTPTR GCPtrFaultAddress;
3523	uint8_t cbInstr;
3524
3525	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3526	AssertRC(rc);
3527
3528	SVMEVENT Event;
3529	Event.u = 0;
3530	Event.n.u1Valid = 1;
3531	Event.n.u8Vector = uVector;
3532
3533	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3534	if (enmTrpmEvent == TRPM_TRAP)
3535	{
3536	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3537	switch (uVector)
3538	{
3539	case X86_XCPT_NMI:
3540	{
3541	Event.n.u3Type = SVM_EVENT_NMI;
3542	break;
3543	}
3544
3545	case X86_XCPT_PF:
3546	case X86_XCPT_DF:
3547	case X86_XCPT_TS:
3548	case X86_XCPT_NP:
3549	case X86_XCPT_SS:
3550	case X86_XCPT_GP:
3551	case X86_XCPT_AC:
3552	{
3553	Event.n.u1ErrorCodeValid = 1;
3554	Event.n.u32ErrorCode = uErrCode;
3555	break;
3556	}
3557	}
3558	}
3559	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3560	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3561	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3562	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3563	else
3564	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3565
3566	rc = TRPMResetTrap(pVCpu);
3567	AssertRC(rc);
3568
3569	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3570	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3571
3572	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3573	}
3574
3575
3576	/**
3577	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3578	* AMD-V to execute any instruction.
3579	*
3580	* @param pVCpu The cross context virtual CPU structure.
3581	*/
3582	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3583	{
3584	Assert(pVCpu->hm.s.Event.fPending);
3585	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3586
3587	SVMEVENT Event;
3588	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3589
3590	uint8_t uVector = Event.n.u8Vector;
3591	uint8_t uVectorType = Event.n.u3Type;
3592	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3593
3594	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3595
3596	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3597	AssertRC(rc);
3598
3599	if (Event.n.u1ErrorCodeValid)
3600	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3601
3602	if ( uVectorType == SVM_EVENT_EXCEPTION
3603	&& uVector == X86_XCPT_PF)
3604	{
3605	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3606	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3607	}
3608	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3609	{
3610	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3611	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3612	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3613	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3614	}
3615	pVCpu->hm.s.Event.fPending = false;
3616	}
3617
3618
3619	/**
3620	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3621	* now.
3622	*
3623	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3624	* @param pVCpu The cross context virtual CPU structure.
3625	*
3626	* @remarks No-long-jump zone!!!
3627	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3628	*/
3629	static bool hmR0SvmIsIntrShadowActive(PVMCPU pVCpu)
3630	{
3631	/*
3632	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3633	* completes. Check if we should inhibit interrupts or clear any existing
3634	* interrupt inhibition.
3635	*/
3636	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3637	{
3638	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3639	{
3640	/*
3641	* We can clear the inhibit force flag as even if we go back to the recompiler
3642	* without executing guest code in AMD-V, the flag's condition to be cleared is
3643	* met and thus the cleared state is correct.
3644	*/
3645	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3646	return false;
3647	}
3648	return true;
3649	}
3650	return false;
3651	}
3652
3653
3654	/**
3655	* Sets the virtual interrupt intercept control in the VMCB.
3656	*
3657	* @param pVCpu The cross context virtual CPU structure.
3658	* @param pVmcb Pointer to the VM control block.
3659	*/
3660	static void hmR0SvmSetIntWindowExiting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3661	{
3662	/*
3663	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3664	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3665	* (updating ISR at the right time) and inject the interrupt.
3666	*
3667	* With AVIC is supported, we could make use of the asynchronously delivery without
3668	* #VMEXIT and we would be passing the AVIC page to SVM.
3669	*
3670	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3671	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3672	*/
3673	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3674	/*
3675	* Currently we don't overlay interupt windows and if there's any V_IRQ pending in the
3676	* nested-guest VMCB, we avoid setting up any interrupt window on behalf of the outer
3677	* guest.
3678	*/
3679	/** @todo Does this mean we end up prioritizing virtual interrupt
3680	* delivery/window over a physical interrupt (from the outer guest)
3681	* might be pending? */
3682	bool const fEnableIntWindow = !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
3683	if (!fEnableIntWindow)
3684	{
3685	Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx));
3686	Log4(("Nested-guest V_IRQ already pending\n"));
3687	}
3688	#else
3689	bool const fEnableIntWindow = true;
3690	RT_NOREF(pVCpu);
3691	#endif
3692	if (fEnableIntWindow)
3693	{
3694	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3695	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3696	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3697	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3698	Log4(("Set VINTR intercept\n"));
3699	}
3700	}
3701
3702
3703	/**
3704	* Clears the virtual interrupt intercept control in the VMCB as
3705	* we are figured the guest is unable process any interrupts
3706	* at this point of time.
3707	*
3708	* @param pVCpu The cross context virtual CPU structure.
3709	* @param pVmcb Pointer to the VM control block.
3710	*/
3711	static void hmR0SvmClearIntWindowExiting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3712	{
3713	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3714	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3715	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3716	{
3717	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3718	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3719	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3720	Log4(("Cleared VINTR intercept\n"));
3721	}
3722	}
3723
3724	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3725	/**
3726	* Evaluates the event to be delivered to the nested-guest and sets it as the
3727	* pending event.
3728	*
3729	* @returns VBox strict status code.
3730	* @param pVCpu The cross context virtual CPU structure.
3731	*/
3732	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu)
3733	{
3734	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3735	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
3736	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3737	\| CPUMCTX_EXTRN_RFLAGS
3738	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3739	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3740
3741	Assert(!pVCpu->hm.s.Event.fPending);
3742	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3743	Assert(pVmcb);
3744
3745	bool const fGif = pCtx->hwvirt.fGif;
3746	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3747	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3748
3749	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3750	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3751	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3752
3753	/** @todo SMI. SMIs take priority over NMIs. */
3754
3755	/*
3756	* Check if the guest can receive NMIs.
3757	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3758	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3759	*/
3760	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3761	&& !fBlockNmi)
3762	{
3763	if ( fGif
3764	&& !fIntShadow)
3765	{
3766	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3767	{
3768	Log4(("Intercepting NMI -> #VMEXIT\n"));
3769	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3770	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3771	}
3772
3773	Log4(("Setting NMI pending for injection\n"));
3774	SVMEVENT Event;
3775	Event.u = 0;
3776	Event.n.u1Valid = 1;
3777	Event.n.u8Vector = X86_XCPT_NMI;
3778	Event.n.u3Type = SVM_EVENT_NMI;
3779	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3780	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3781	}
3782	else if (!fGif)
3783	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3784	else
3785	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3786	}
3787	/*
3788	* Check if the nested-guest can receive external interrupts (generated by the guest's
3789	* PIC/APIC).
3790	*
3791	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3792	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3793	*
3794	* External interrupts that are generated for the outer guest may be intercepted
3795	* depending on how the nested-guest VMCB was programmed by guest software.
3796	*
3797	* Physical interrupts always take priority over virtual interrupts,
3798	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3799	*/
3800	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3801	&& !pVCpu->hm.s.fSingleInstruction)
3802	{
3803	if ( fGif
3804	&& !fIntShadow
3805	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3806	{
3807	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3808	{
3809	Log4(("Intercepting INTR -> #VMEXIT\n"));
3810	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3811	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3812	}
3813
3814	uint8_t u8Interrupt;
3815	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3816	if (RT_SUCCESS(rc))
3817	{
3818	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3819	SVMEVENT Event;
3820	Event.u = 0;
3821	Event.n.u1Valid = 1;
3822	Event.n.u8Vector = u8Interrupt;
3823	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3824	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3825	}
3826	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3827	{
3828	/*
3829	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3830	* updated eventually when the TPR is written by the guest.
3831	*/
3832	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3833	}
3834	else
3835	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3836	}
3837	else if (!fGif)
3838	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3839	else
3840	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3841	}
3842
3843	return VINF_SUCCESS;
3844	}
3845	#endif
3846
3847	/**
3848	* Evaluates the event to be delivered to the guest and sets it as the pending
3849	* event.
3850	*
3851	* @param pVCpu The cross context virtual CPU structure.
3852	*/
3853	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu)
3854	{
3855	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3856	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3857	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3858	\| CPUMCTX_EXTRN_RFLAGS
3859	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW);
3860
3861	Assert(!pVCpu->hm.s.Event.fPending);
3862	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3863	Assert(pVmcb);
3864
3865	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3866	bool const fGif = pCtx->hwvirt.fGif;
3867	#else
3868	bool const fGif = true;
3869	#endif
3870	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3871	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3872	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3873
3874	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool fIntPending=%RTbool NMI pending=%RTbool\n",
3875	fGif, fBlockNmi, fBlockInt, fIntShadow,
3876	VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3877	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3878
3879	/** @todo SMI. SMIs take priority over NMIs. */
3880
3881	/*
3882	* Check if the guest can receive NMIs.
3883	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3884	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3885	*/
3886	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3887	&& !fBlockNmi)
3888	{
3889	if ( fGif
3890	&& !fIntShadow)
3891	{
3892	Log4(("Setting NMI pending for injection\n"));
3893	SVMEVENT Event;
3894	Event.u = 0;
3895	Event.n.u1Valid = 1;
3896	Event.n.u8Vector = X86_XCPT_NMI;
3897	Event.n.u3Type = SVM_EVENT_NMI;
3898	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3899	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3900	}
3901	else if (!fGif)
3902	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3903	else
3904	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3905	}
3906	/*
3907	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3908	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3909	* it from the APIC device.
3910	*/
3911	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3912	&& !pVCpu->hm.s.fSingleInstruction)
3913	{
3914	if ( fGif
3915	&& !fBlockInt
3916	&& !fIntShadow)
3917	{
3918	uint8_t u8Interrupt;
3919	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3920	if (RT_SUCCESS(rc))
3921	{
3922	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3923	SVMEVENT Event;
3924	Event.u = 0;
3925	Event.n.u1Valid = 1;
3926	Event.n.u8Vector = u8Interrupt;
3927	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3928	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3929	}
3930	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3931	{
3932	/*
3933	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3934	* updated eventually when the TPR is written by the guest.
3935	*/
3936	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3937	}
3938	else
3939	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3940	}
3941	else if (!fGif)
3942	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3943	else
3944	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3945	}
3946	}
3947
3948
3949	/**
3950	* Injects any pending events into the guest (or nested-guest).
3951	*
3952	* @param pVCpu The cross context virtual CPU structure.
3953	* @param pVmcb Pointer to the VM control block.
3954	*
3955	* @remarks Must only be called when we are guaranteed to enter
3956	* hardware-assisted SVM execution and not return to ring-3
3957	* prematurely.
3958	*/
3959	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PSVMVMCB pVmcb)
3960	{
3961	Assert(!TRPMHasTrap(pVCpu));
3962	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3963
3964	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3965	#ifdef VBOX_STRICT
3966	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3967	bool const fGif = pCtx->hwvirt.fGif;
3968	bool fAllowInt = fGif;
3969	if (fGif)
3970	{
3971	/*
3972	* For nested-guests we have no way to determine if we're injecting a physical or
3973	* virtual interrupt at this point. Hence the partial verification below.
3974	*/
3975	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3976	fAllowInt = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx) \|\| CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx);
3977	else
3978	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3979	}
3980	#endif
3981
3982	if (pVCpu->hm.s.Event.fPending)
3983	{
3984	SVMEVENT Event;
3985	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3986	Assert(Event.n.u1Valid);
3987
3988	/*
3989	* Validate event injection pre-conditions.
3990	*/
3991	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3992	{
3993	Assert(fAllowInt);
3994	Assert(!fIntShadow);
3995	}
3996	else if (Event.n.u3Type == SVM_EVENT_NMI)
3997	{
3998	Assert(fGif);
3999	Assert(!fIntShadow);
4000	}
4001
4002	/*
4003	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
4004	* do this only when we are surely going to inject the NMI as otherwise if we return
4005	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
4006	* SVM R0.
4007	*
4008	* With VT-x, this is handled by the Guest interruptibility information VMCS field
4009	* which will set the VMCS field after actually delivering the NMI which we read on
4010	* VM-exit to determine the state.
4011	*/
4012	if ( Event.n.u3Type == SVM_EVENT_NMI
4013	&& Event.n.u8Vector == X86_XCPT_NMI
4014	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
4015	{
4016	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4017	}
4018
4019	/*
4020	* Inject it (update VMCB for injection by the hardware).
4021	*/
4022	Log4(("Injecting pending HM event\n"));
4023	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
4024	pVCpu->hm.s.Event.fPending = false;
4025
4026	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
4027	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
4028	else
4029	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
4030	}
4031	else
4032	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
4033
4034	/*
4035	* We could have injected an NMI through IEM and continue guest execution using
4036	* hardware-assisted SVM. In which case, we would not have any events pending (above)
4037	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
4038	*/
4039	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
4040	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
4041
4042	/*
4043	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
4044	*
4045	* For nested-guests: We need to update it too for the scenario where IEM executes
4046	* the nested-guest but execution later continues here with an interrupt shadow active.
4047	*/
4048	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
4049	}
4050
4051
4052	/**
4053	* Reports world-switch error and dumps some useful debug info.
4054	*
4055	* @param pVCpu The cross context virtual CPU structure.
4056	* @param rcVMRun The return code from VMRUN (or
4057	* VERR_SVM_INVALID_GUEST_STATE for invalid
4058	* guest-state).
4059	*/
4060	static void hmR0SvmReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun)
4061	{
4062	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4063	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4064	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4065
4066	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
4067	{
4068	#ifdef VBOX_STRICT
4069	hmR0DumpRegs(pVCpu);
4070	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
4071	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
4072	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
4073	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
4074	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
4075	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
4076	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
4077	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
4078	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
4079	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
4080	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
4081
4082	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
4083	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
4084	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
4085
4086	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
4087	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
4088	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
4089	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
4090	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
4091	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
4092	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
4093	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
4094	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
4095	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
4096	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
4097	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
4098
4099	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
4100	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
4101	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
4102	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
4103	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
4104	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
4105	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
4106	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
4107	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
4108	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
4109	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4110	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
4111	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
4112	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
4113	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
4114	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
4115	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
4116	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
4117	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
4118	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
4119
4120	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
4121
4122	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
4123	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
4124
4125	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
4126	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
4127	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
4128	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
4129	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
4130	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
4131	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
4132	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
4133	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
4134	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
4135	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
4136	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
4137	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
4138	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
4139	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
4140	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
4141	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
4142	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
4143	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
4144	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
4145
4146	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
4147	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
4148
4149	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
4150	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
4151	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
4152	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
4153
4154	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
4155	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
4156
4157	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
4158	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
4159	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
4160	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
4161
4162	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
4163	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
4164	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
4165	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
4166	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
4167	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
4168	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
4169
4170	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
4171	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
4172	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
4173	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
4174
4175	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
4176	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
4177	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
4178
4179	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
4180	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
4181	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
4182	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
4183	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
4184	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
4185	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
4186	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
4187	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
4188	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
4189	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
4190	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
4191
4192	NOREF(pVmcb);
4193	#endif /* VBOX_STRICT */
4194	}
4195	else
4196	Log4Func(("rcVMRun=%d\n", rcVMRun));
4197	}
4198
4199
4200	/**
4201	* Check per-VM and per-VCPU force flag actions that require us to go back to
4202	* ring-3 for one reason or another.
4203	*
4204	* @returns VBox status code (information status code included).
4205	* @retval VINF_SUCCESS if we don't have any actions that require going back to
4206	* ring-3.
4207	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
4208	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
4209	* interrupts)
4210	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
4211	* all EMTs to be in ring-3.
4212	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
4213	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
4214	* to the EM loop.
4215	*
4216	* @param pVCpu The cross context virtual CPU structure.
4217	*/
4218	static int hmR0SvmCheckForceFlags(PVMCPU pVCpu)
4219	{
4220	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4221	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
4222
4223	/* Could happen as a result of longjump. */
4224	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
4225	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
4226
4227	/* Update pending interrupts into the APIC's IRR. */
4228	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
4229	APICUpdatePendingInterrupts(pVCpu);
4230
4231	PVM pVM = pVCpu->CTX_SUFF(pVM);
4232	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
4233	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
4234	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
4235	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
4236	{
4237	/* Pending PGM C3 sync. */
4238	if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4239	{
4240	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
4241	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4242	if (rc != VINF_SUCCESS)
4243	{
4244	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4245	return rc;
4246	}
4247	}
4248
4249	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4250	/* -XXX- what was that about single stepping? */
4251	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
4252	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4253	{
4254	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4255	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
4256	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4257	return rc;
4258	}
4259
4260	/* Pending VM request packets, such as hardware interrupts. */
4261	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
4262	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
4263	{
4264	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4265	return VINF_EM_PENDING_REQUEST;
4266	}
4267
4268	/* Pending PGM pool flushes. */
4269	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4270	{
4271	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4272	return VINF_PGM_POOL_FLUSH_PENDING;
4273	}
4274
4275	/* Pending DMA requests. */
4276	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
4277	{
4278	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4279	return VINF_EM_RAW_TO_R3;
4280	}
4281	}
4282
4283	return VINF_SUCCESS;
4284	}
4285
4286
4287	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4288	/**
4289	* Does the preparations before executing nested-guest code in AMD-V.
4290	*
4291	* @returns VBox status code (informational status codes included).
4292	* @retval VINF_SUCCESS if we can proceed with running the guest.
4293	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4294	*
4295	* @param pVCpu The cross context virtual CPU structure.
4296	* @param pSvmTransient Pointer to the SVM transient structure.
4297	*
4298	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
4299	* @sa hmR0SvmPreRunGuest.
4300	*/
4301	static int hmR0SvmPreRunGuestNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4302	{
4303	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4304	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4305	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4306
4307	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM_ONLY_IN_IEM
4308	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4309	return VINF_EM_RESCHEDULE_REM;
4310	#endif
4311
4312	/* Check force flag actions that might require us to go back to ring-3. */
4313	int rc = hmR0SvmCheckForceFlags(pVCpu);
4314	if (rc != VINF_SUCCESS)
4315	return rc;
4316
4317	if (TRPMHasTrap(pVCpu))
4318	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4319	else if (!pVCpu->hm.s.Event.fPending)
4320	{
4321	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu);
4322	if ( rcStrict != VINF_SUCCESS
4323	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4324	return VBOXSTRICTRC_VAL(rcStrict);
4325	}
4326
4327	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4328
4329	/*
4330	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4331	* Just do it in software, see @bugref{8411}.
4332	* NB: If we could continue a task switch exit we wouldn't need to do this.
4333	*/
4334	PVM pVM = pVCpu->CTX_SUFF(pVM);
4335	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4336	&& pVCpu->hm.s.Event.fPending
4337	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4338	{
4339	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4340	}
4341
4342	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4343	Assert(!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4344	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4345	#endif
4346
4347	/*
4348	* Export the nested-guest state bits that are not shared with the host in any way as we
4349	* can longjmp or get preempted in the midst of exporting some of the state.
4350	*/
4351	rc = hmR0SvmExportGuestStateNested(pVCpu);
4352	AssertRCReturn(rc, rc);
4353	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4354
4355	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware-assisted SVM. */
4356	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4357
4358	/*
4359	* No longjmps to ring-3 from this point on!!!
4360	*
4361	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4362	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4363	*/
4364	VMMRZCallRing3Disable(pVCpu);
4365
4366	/*
4367	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4368	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4369	* preemption disabled for a while. Since this is purly to aid the
4370	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4371	* disable interrupt on NT.
4372	*
4373	* We need to check for force-flags that could've possible been altered since we last
4374	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4375	* see @bugref{6398}).
4376	*
4377	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4378	* to ring-3 before executing guest code.
4379	*/
4380	pSvmTransient->fEFlags = ASMIntDisableFlags();
4381	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4382	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4383	{
4384	ASMSetFlags(pSvmTransient->fEFlags);
4385	VMMRZCallRing3Enable(pVCpu);
4386	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4387	return VINF_EM_RAW_TO_R3;
4388	}
4389	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4390	{
4391	ASMSetFlags(pSvmTransient->fEFlags);
4392	VMMRZCallRing3Enable(pVCpu);
4393	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4394	return VINF_EM_RAW_INTERRUPT;
4395	}
4396	return VINF_SUCCESS;
4397	}
4398	#endif
4399
4400
4401	/**
4402	* Does the preparations before executing guest code in AMD-V.
4403	*
4404	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4405	* recompiler. We must be cautious what we do here regarding committing
4406	* guest-state information into the VMCB assuming we assuredly execute the guest
4407	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4408	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4409	* that the recompiler can (and should) use them when it resumes guest
4410	* execution. Otherwise such operations must be done when we can no longer
4411	* exit to ring-3.
4412	*
4413	* @returns VBox status code (informational status codes included).
4414	* @retval VINF_SUCCESS if we can proceed with running the guest.
4415	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4416	*
4417	* @param pVCpu The cross context virtual CPU structure.
4418	* @param pSvmTransient Pointer to the SVM transient structure.
4419	*/
4420	static int hmR0SvmPreRunGuest(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4421	{
4422	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4423	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4424
4425	/* Check force flag actions that might require us to go back to ring-3. */
4426	int rc = hmR0SvmCheckForceFlags(pVCpu);
4427	if (rc != VINF_SUCCESS)
4428	return rc;
4429
4430	if (TRPMHasTrap(pVCpu))
4431	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4432	else if (!pVCpu->hm.s.Event.fPending)
4433	hmR0SvmEvaluatePendingEvent(pVCpu);
4434
4435	/*
4436	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4437	* Just do it in software, see @bugref{8411}.
4438	* NB: If we could continue a task switch exit we wouldn't need to do this.
4439	*/
4440	PVM pVM = pVCpu->CTX_SUFF(pVM);
4441	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4442	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4443	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4444
4445	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4446	Assert(!(pVCpu->cpum.GstCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4447	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4448	#endif
4449
4450	/*
4451	* Export the guest state bits that are not shared with the host in any way as we can
4452	* longjmp or get preempted in the midst of exporting some of the state.
4453	*/
4454	rc = hmR0SvmExportGuestState(pVCpu);
4455	AssertRCReturn(rc, rc);
4456	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4457
4458	/*
4459	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4460	* world-switch so we can update it on the way back if the guest changed the TPR.
4461	*/
4462	if (pVCpu->hm.s.svm.fSyncVTpr)
4463	{
4464	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4465	if (pVM->hm.s.fTPRPatchingActive)
4466	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4467	else
4468	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4469	}
4470
4471	/*
4472	* No longjmps to ring-3 from this point on!!!
4473	*
4474	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4475	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4476	*/
4477	VMMRZCallRing3Disable(pVCpu);
4478
4479	/*
4480	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4481	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4482	* preemption disabled for a while. Since this is purly to aid the
4483	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4484	* disable interrupt on NT.
4485	*
4486	* We need to check for force-flags that could've possible been altered since we last
4487	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4488	* see @bugref{6398}).
4489	*
4490	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4491	* to ring-3 before executing guest code.
4492	*/
4493	pSvmTransient->fEFlags = ASMIntDisableFlags();
4494	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4495	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4496	{
4497	ASMSetFlags(pSvmTransient->fEFlags);
4498	VMMRZCallRing3Enable(pVCpu);
4499	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4500	return VINF_EM_RAW_TO_R3;
4501	}
4502	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4503	{
4504	ASMSetFlags(pSvmTransient->fEFlags);
4505	VMMRZCallRing3Enable(pVCpu);
4506	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4507	return VINF_EM_RAW_INTERRUPT;
4508	}
4509
4510	return VINF_SUCCESS;
4511	}
4512
4513
4514	/**
4515	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4516	* doing so.
4517	*
4518	* This means there is no backing out to ring-3 or anywhere else at this point.
4519	*
4520	* @param pVCpu The cross context virtual CPU structure.
4521	* @param pSvmTransient Pointer to the SVM transient structure.
4522	*
4523	* @remarks Called with preemption disabled.
4524	* @remarks No-long-jump zone!!!
4525	*/
4526	static void hmR0SvmPreRunGuestCommitted(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4527	{
4528	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4529	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4530	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4531
4532	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4533	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4534
4535	PVM pVM = pVCpu->CTX_SUFF(pVM);
4536	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4537
4538	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4539
4540	if (!CPUMIsGuestFPUStateActive(pVCpu))
4541	{
4542	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4543	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4544	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4545	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4546	}
4547
4548	/* Load the state shared between host and guest (FPU, debug). */
4549	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4550	hmR0SvmExportSharedState(pVCpu, pVmcb);
4551
4552	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4553	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4554
4555	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
4556	RTCPUID const idHostCpu = pHostCpu->idCpu;
4557	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4558
4559	/* Setup TSC offsetting. */
4560	if ( pSvmTransient->fUpdateTscOffsetting
4561	\|\| fMigratedHostCpu)
4562	{
4563	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4564	pSvmTransient->fUpdateTscOffsetting = false;
4565	}
4566
4567	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4568	if (fMigratedHostCpu)
4569	pVmcb->ctrl.u32VmcbCleanBits = 0;
4570
4571	/* Store status of the shared guest-host state at the time of VMRUN. */
4572	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4573	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
4574	{
4575	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4576	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4577	}
4578	else
4579	#endif
4580	{
4581	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4582	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4583	}
4584
4585	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4586	uint8_t *pbMsrBitmap;
4587	if (!pSvmTransient->fIsNestedGuest)
4588	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4589	else
4590	{
4591	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4592
4593	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4594	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4595	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4596	}
4597	#else
4598	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4599	#endif
4600
4601	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4602	/* Flush the appropriate tagged-TLB entries. */
4603	hmR0SvmFlushTaggedTlb(pVCpu, pVmcb, pHostCpu);
4604	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4605
4606	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4607
4608	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4609	to start executing. */
4610
4611	/*
4612	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4613	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4614	*
4615	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4616	*/
4617	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4618	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4619	{
4620	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4621	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4622	if (uGuestTscAux != pVCpu->hm.s.u64HostTscAux)
4623	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4624	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4625	pSvmTransient->fRestoreTscAuxMsr = true;
4626	}
4627	else
4628	{
4629	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4630	pSvmTransient->fRestoreTscAuxMsr = false;
4631	}
4632	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4633
4634	/*
4635	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4636	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4637	* from the VMCB.
4638	*/
4639	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu);
4640	if (!fSupportsVmcbCleanBits)
4641	pVmcb->ctrl.u32VmcbCleanBits = 0;
4642	}
4643
4644
4645	/**
4646	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4647	*
4648	* @returns VBox strict status code.
4649	* @param pVCpu The cross context virtual CPU structure.
4650	* @param HCPhysVmcb The host physical address of the VMCB.
4651	*
4652	* @remarks No-long-jump zone!!!
4653	*/
4654	DECLINLINE(int) hmR0SvmRunGuest(PVMCPU pVCpu, RTHCPHYS HCPhysVmcb)
4655	{
4656	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4657	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4658	pCtx->fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4659
4660	/*
4661	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4662	* floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4663	* callee-saved and thus the need for this XMM wrapper.
4664	*
4665	* Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4666	*/
4667	PVM pVM = pVCpu->CTX_SUFF(pVM);
4668	#ifdef VBOX_WITH_KERNEL_USING_XMM
4669	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu, pVCpu->hm.s.svm.pfnVMRun);
4670	#else
4671	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu);
4672	#endif
4673	}
4674
4675
4676	/**
4677	* Undoes the TSC offset applied for an SVM nested-guest and returns the TSC
4678	* value for the guest.
4679	*
4680	* @returns The TSC offset after undoing any nested-guest TSC offset.
4681	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
4682	* @param uTicks The nested-guest TSC.
4683	*
4684	* @note If you make any changes to this function, please check if
4685	* hmR0SvmNstGstUndoTscOffset() needs adjusting.
4686	*
4687	* @sa HMSvmNstGstApplyTscOffset().
4688	*/
4689	DECLINLINE(uint64_t) hmR0SvmNstGstUndoTscOffset(PVMCPU pVCpu, uint64_t uTicks)
4690	{
4691	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4692	Assert(pVmcbNstGstCache->fCacheValid);
4693	return uTicks - pVmcbNstGstCache->u64TSCOffset;
4694	}
4695
4696
4697	/**
4698	* Performs some essential restoration of state after running guest (or
4699	* nested-guest) code in AMD-V.
4700	*
4701	* @param pVCpu The cross context virtual CPU structure.
4702	* @param pSvmTransient Pointer to the SVM transient structure.
4703	* @param rcVMRun Return code of VMRUN.
4704	*
4705	* @remarks Called with interrupts disabled.
4706	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4707	* unconditionally when it is safe to do so.
4708	*/
4709	static void hmR0SvmPostRunGuest(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4710	{
4711	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4712
4713	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4714	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4715	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4716
4717	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4718	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4719
4720	/* TSC read must be done early for maximum accuracy. */
4721	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4722	{
4723	if (!pSvmTransient->fIsNestedGuest)
4724	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4725	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4726	else
4727	{
4728	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMSvmNstGstVmExitNotify(). */
4729	uint64_t const uGstTsc = hmR0SvmNstGstUndoTscOffset(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4730	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4731	}
4732	#endif
4733	}
4734
4735	if (pSvmTransient->fRestoreTscAuxMsr)
4736	{
4737	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4738	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4739	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4740	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4741	}
4742
4743	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4744	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4745	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4746
4747	Assert(!(ASMGetFlags() & X86_EFL_IF));
4748	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4749	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4750
4751	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4752	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4753	{
4754	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4755	return;
4756	}
4757
4758	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4759	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4760	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4761	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4762
4763	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4764	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4765	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4766	#else
4767	/*
4768	* Always import the following:
4769	*
4770	* - RIP for exit optimizations and evaluating event injection on re-entry.
4771	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4772	* state on preemption.
4773	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4774	* - CS for exit optimizations.
4775	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4776	* assembly switcher code.
4777	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4778	*/
4779	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4780	\| CPUMCTX_EXTRN_RFLAGS
4781	\| CPUMCTX_EXTRN_RAX
4782	\| CPUMCTX_EXTRN_RSP
4783	\| CPUMCTX_EXTRN_CS
4784	\| CPUMCTX_EXTRN_HWVIRT
4785	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4786	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4787	\| HMSVM_CPUMCTX_SHARED_STATE);
4788	#endif
4789
4790	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4791	&& pVCpu->hm.s.svm.fSyncVTpr)
4792	{
4793	Assert(!pSvmTransient->fIsNestedGuest);
4794	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4795	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
4796	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4797	{
4798	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4799	AssertRC(rc);
4800	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4801	}
4802	/* Sync TPR when we aren't intercepting CR8 writes. */
4803	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4804	{
4805	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4806	AssertRC(rc);
4807	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4808	}
4809	}
4810
4811	#ifdef DEBUG_ramshankar
4812	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4813	{
4814	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4815	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4816	0 /* uVerbose */);
4817	}
4818	#endif
4819
4820	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4821	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4822	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, uHostTsc);
4823	}
4824
4825
4826	/**
4827	* Runs the guest code using AMD-V.
4828	*
4829	* @returns VBox status code.
4830	* @param pVCpu The cross context virtual CPU structure.
4831	* @param pcLoops Pointer to the number of executed loops.
4832	*/
4833	static int hmR0SvmRunGuestCodeNormal(PVMCPU pVCpu, uint32_t *pcLoops)
4834	{
4835	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4836	Assert(pcLoops);
4837	Assert(*pcLoops <= cMaxResumeLoops);
4838
4839	SVMTRANSIENT SvmTransient;
4840	RT_ZERO(SvmTransient);
4841	SvmTransient.fUpdateTscOffsetting = true;
4842	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4843
4844	int rc = VERR_INTERNAL_ERROR_5;
4845	for (;;)
4846	{
4847	Assert(!HMR0SuspendPending());
4848	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4849
4850	/* Preparatory work for running nested-guest code, this may force us to return to
4851	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4852	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4853	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4854	if (rc != VINF_SUCCESS)
4855	break;
4856
4857	/*
4858	* No longjmps to ring-3 from this point on!!!
4859	*
4860	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4861	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4862	*/
4863	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4864	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4865
4866	/* Restore any residual host-state and save any bits shared between host and guest
4867	into the guest-CPU state. Re-enables interrupts! */
4868	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4869
4870	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4871	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4872	{
4873	if (rc == VINF_SUCCESS)
4874	rc = VERR_SVM_INVALID_GUEST_STATE;
4875	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4876	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4877	break;
4878	}
4879
4880	/* Handle the #VMEXIT. */
4881	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4882	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4883	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4884	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4885	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4886	if (rc != VINF_SUCCESS)
4887	break;
4888	if (++(*pcLoops) >= cMaxResumeLoops)
4889	{
4890	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4891	rc = VINF_EM_RAW_INTERRUPT;
4892	break;
4893	}
4894	}
4895
4896	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4897	return rc;
4898	}
4899
4900
4901	/**
4902	* Runs the guest code using AMD-V in single step mode.
4903	*
4904	* @returns VBox status code.
4905	* @param pVCpu The cross context virtual CPU structure.
4906	* @param pcLoops Pointer to the number of executed loops.
4907	*/
4908	static int hmR0SvmRunGuestCodeStep(PVMCPU pVCpu, uint32_t *pcLoops)
4909	{
4910	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4911	Assert(pcLoops);
4912	Assert(*pcLoops <= cMaxResumeLoops);
4913
4914	SVMTRANSIENT SvmTransient;
4915	RT_ZERO(SvmTransient);
4916	SvmTransient.fUpdateTscOffsetting = true;
4917	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4918
4919	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4920	uint16_t uCsStart = pCtx->cs.Sel;
4921	uint64_t uRipStart = pCtx->rip;
4922
4923	int rc = VERR_INTERNAL_ERROR_5;
4924	for (;;)
4925	{
4926	Assert(!HMR0SuspendPending());
4927	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4928	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4929	(unsigned)RTMpCpuId(), *pcLoops));
4930
4931	/* Preparatory work for running nested-guest code, this may force us to return to
4932	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4933	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4934	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4935	if (rc != VINF_SUCCESS)
4936	break;
4937
4938	/*
4939	* No longjmps to ring-3 from this point on!!!
4940	*
4941	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4942	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4943	*/
4944	VMMRZCallRing3Disable(pVCpu);
4945	VMMRZCallRing3RemoveNotification(pVCpu);
4946	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4947
4948	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4949
4950	/* Restore any residual host-state and save any bits shared between host and guest
4951	into the guest-CPU state. Re-enables interrupts! */
4952	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4953
4954	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4955	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4956	{
4957	if (rc == VINF_SUCCESS)
4958	rc = VERR_SVM_INVALID_GUEST_STATE;
4959	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4960	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4961	return rc;
4962	}
4963
4964	/* Handle the #VMEXIT. */
4965	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4966	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4967	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4968	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4969	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4970	if (rc != VINF_SUCCESS)
4971	break;
4972	if (++(*pcLoops) >= cMaxResumeLoops)
4973	{
4974	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4975	rc = VINF_EM_RAW_INTERRUPT;
4976	break;
4977	}
4978
4979	/*
4980	* Did the RIP change, if so, consider it a single step.
4981	* Otherwise, make sure one of the TFs gets set.
4982	*/
4983	if ( pCtx->rip != uRipStart
4984	\|\| pCtx->cs.Sel != uCsStart)
4985	{
4986	rc = VINF_EM_DBG_STEPPED;
4987	break;
4988	}
4989	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4990	}
4991
4992	/*
4993	* Clear the X86_EFL_TF if necessary.
4994	*/
4995	if (pVCpu->hm.s.fClearTrapFlag)
4996	{
4997	pVCpu->hm.s.fClearTrapFlag = false;
4998	pCtx->eflags.Bits.u1TF = 0;
4999	}
5000
5001	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
5002	return rc;
5003	}
5004
5005	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5006	/**
5007	* Runs the nested-guest code using AMD-V.
5008	*
5009	* @returns VBox status code.
5010	* @param pVCpu The cross context virtual CPU structure.
5011	* @param pcLoops Pointer to the number of executed loops. If we're switching
5012	* from the guest-code execution loop to this nested-guest
5013	* execution loop pass the remainder value, else pass 0.
5014	*/
5015	static int hmR0SvmRunGuestCodeNested(PVMCPU pVCpu, uint32_t *pcLoops)
5016	{
5017	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5018	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
5019	Assert(pcLoops);
5020	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops);
5021
5022	SVMTRANSIENT SvmTransient;
5023	RT_ZERO(SvmTransient);
5024	SvmTransient.fUpdateTscOffsetting = true;
5025	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
5026	SvmTransient.fIsNestedGuest = true;
5027
5028	int rc = VERR_INTERNAL_ERROR_4;
5029	for (;;)
5030	{
5031	Assert(!HMR0SuspendPending());
5032	HMSVM_ASSERT_CPU_SAFE(pVCpu);
5033
5034	/* Preparatory work for running nested-guest code, this may force us to return to
5035	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
5036	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
5037	rc = hmR0SvmPreRunGuestNested(pVCpu, &SvmTransient);
5038	if ( rc != VINF_SUCCESS
5039	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
5040	{
5041	break;
5042	}
5043
5044	/*
5045	* No longjmps to ring-3 from this point on!!!
5046	*
5047	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
5048	* better than a kernel panic. This also disables flushing of the R0-logger instance.
5049	*/
5050	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
5051
5052	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
5053
5054	/* Restore any residual host-state and save any bits shared between host and guest
5055	into the guest-CPU state. Re-enables interrupts! */
5056	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
5057
5058	if (RT_LIKELY( rc == VINF_SUCCESS
5059	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
5060	{ /* extremely likely */ }
5061	else
5062	{
5063	/* VMRUN failed, shouldn't really happen, Guru. */
5064	if (rc != VINF_SUCCESS)
5065	break;
5066
5067	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
5068	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
5069	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
5070	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
5071	break;
5072	}
5073
5074	/* Handle the #VMEXIT. */
5075	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
5076	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
5077	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
5078	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
5079	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
5080	if ( rc != VINF_SUCCESS
5081	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
5082	break;
5083	if (++(*pcLoops) >= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
5084	{
5085	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
5086	rc = VINF_EM_RAW_INTERRUPT;
5087	break;
5088	}
5089
5090	/** @todo handle single-stepping */
5091	}
5092
5093	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
5094	return rc;
5095	}
5096	#endif
5097
5098
5099	/**
5100	* Runs the guest code using AMD-V.
5101	*
5102	* @returns Strict VBox status code.
5103	* @param pVCpu The cross context virtual CPU structure.
5104	*/
5105	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPU pVCpu)
5106	{
5107	Assert(VMMRZCallRing3IsEnabled(pVCpu));
5108	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
5109	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, NULL /* pvUser */);
5110
5111	uint32_t cLoops = 0;
5112	int rc;
5113	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5114	if (!CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
5115	#endif
5116	{
5117	if (!pVCpu->hm.s.fSingleInstruction)
5118	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
5119	else
5120	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
5121	}
5122	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5123	else
5124	{
5125	rc = VINF_SVM_VMRUN;
5126	}
5127
5128	/* Re-check the nested-guest condition here as we may be transitioning from the normal
5129	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
5130	if (rc == VINF_SVM_VMRUN)
5131	{
5132	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
5133	if (rc == VINF_SVM_VMEXIT)
5134	rc = VINF_SUCCESS;
5135	}
5136	#endif
5137
5138	/* Fixup error codes. */
5139	if (rc == VERR_EM_INTERPRETER)
5140	rc = VINF_EM_RAW_EMULATE_INSTR;
5141	else if (rc == VINF_EM_RESET)
5142	rc = VINF_EM_TRIPLE_FAULT;
5143
5144	/* Prepare to return to ring-3. This will remove longjmp notifications. */
5145	rc = hmR0SvmExitToRing3(pVCpu, rc);
5146	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
5147	return rc;
5148	}
5149
5150
5151	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5152	/**
5153	* Determines whether an IOIO intercept is active for the nested-guest or not.
5154	*
5155	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
5156	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
5157	*/
5158	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
5159	{
5160	const uint16_t u16Port = pIoExitInfo->n.u16Port;
5161	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
5162	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
5163	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
5164	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
5165	const bool fRep = pIoExitInfo->n.u1Rep;
5166	const bool fStrIo = pIoExitInfo->n.u1Str;
5167
5168	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
5169	NULL /* pIoExitInfo */);
5170	}
5171
5172
5173	/**
5174	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
5175	* SVM_EXIT_INVALID).
5176	*
5177	* @returns VBox status code (informational status codes included).
5178	* @param pVCpu The cross context virtual CPU structure.
5179	* @param pSvmTransient Pointer to the SVM transient structure.
5180	*/
5181	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5182	{
5183	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
5184	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5185	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5186
5187	/*
5188	* We import the complete state here because we use separate VMCBs for the guest and the
5189	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
5190	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
5191	*/
5192	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5193	do { \
5194	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5195	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2))); \
5196	} while (0)
5197
5198	/*
5199	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
5200	* nested-guest. If it isn't, it should be handled by the (outer) guest.
5201	*/
5202	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
5203	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5204	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5205	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5206	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5207
5208	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5209	switch (uExitCode)
5210	{
5211	case SVM_EXIT_CPUID:
5212	{
5213	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
5214	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5215	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
5216	}
5217
5218	case SVM_EXIT_RDTSC:
5219	{
5220	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
5221	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5222	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
5223	}
5224
5225	case SVM_EXIT_RDTSCP:
5226	{
5227	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
5228	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5229	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
5230	}
5231
5232	case SVM_EXIT_MONITOR:
5233	{
5234	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
5235	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5236	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
5237	}
5238
5239	case SVM_EXIT_MWAIT:
5240	{
5241	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
5242	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5243	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
5244	}
5245
5246	case SVM_EXIT_HLT:
5247	{
5248	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_HLT))
5249	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5250	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
5251	}
5252
5253	case SVM_EXIT_MSR:
5254	{
5255	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
5256	{
5257	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
5258	uint16_t offMsrpm;
5259	uint8_t uMsrpmBit;
5260	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5261	if (RT_SUCCESS(rc))
5262	{
5263	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
5264	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
5265
5266	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5267	pbMsrBitmap += offMsrpm;
5268	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
5269	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
5270
5271	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5272	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5273	{
5274	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5275	}
5276	}
5277	else
5278	{
5279	/*
5280	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5281	* See AMD-V spec. "15.11 MSR Intercepts".
5282	*/
5283	Assert(rc == VERR_OUT_OF_RANGE);
5284	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5285	}
5286	}
5287	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
5288	}
5289
5290	case SVM_EXIT_IOIO:
5291	{
5292	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
5293	{
5294	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
5295	SVMIOIOEXITINFO IoExitInfo;
5296	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5297	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
5298	if (fIntercept)
5299	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5300	}
5301	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
5302	}
5303
5304	case SVM_EXIT_XCPT_PF:
5305	{
5306	PVM pVM = pVCpu->CTX_SUFF(pVM);
5307	if (pVM->hm.s.fNestedPaging)
5308	{
5309	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5310	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5311
5312	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5313	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_PF))
5314	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5315
5316	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
5317	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5318	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
5319	return VINF_SUCCESS;
5320	}
5321	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
5322	}
5323
5324	case SVM_EXIT_XCPT_UD:
5325	{
5326	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_UD))
5327	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5328	hmR0SvmSetPendingXcptUD(pVCpu);
5329	return VINF_SUCCESS;
5330	}
5331
5332	case SVM_EXIT_XCPT_MF:
5333	{
5334	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_MF))
5335	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5336	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
5337	}
5338
5339	case SVM_EXIT_XCPT_DB:
5340	{
5341	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_DB))
5342	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5343	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
5344	}
5345
5346	case SVM_EXIT_XCPT_AC:
5347	{
5348	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_AC))
5349	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5350	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
5351	}
5352
5353	case SVM_EXIT_XCPT_BP:
5354	{
5355	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_BP))
5356	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5357	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
5358	}
5359
5360	case SVM_EXIT_READ_CR0:
5361	case SVM_EXIT_READ_CR3:
5362	case SVM_EXIT_READ_CR4:
5363	{
5364	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5365	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, uCr))
5366	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5367	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5368	}
5369
5370	case SVM_EXIT_CR0_SEL_WRITE:
5371	{
5372	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5373	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5374	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5375	}
5376
5377	case SVM_EXIT_WRITE_CR0:
5378	case SVM_EXIT_WRITE_CR3:
5379	case SVM_EXIT_WRITE_CR4:
5380	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5381	{
5382	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5383	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5384
5385	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, uCr))
5386	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5387	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5388	}
5389
5390	case SVM_EXIT_PAUSE:
5391	{
5392	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_PAUSE))
5393	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5394	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5395	}
5396
5397	case SVM_EXIT_VINTR:
5398	{
5399	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VINTR))
5400	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5401	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5402	}
5403
5404	case SVM_EXIT_INTR:
5405	case SVM_EXIT_NMI:
5406	case SVM_EXIT_SMI:
5407	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5408	{
5409	/*
5410	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5411	*
5412	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5413	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5414	* nested-guest #VMEXIT.
5415	*
5416	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5417	* while trying to inject interrupts, see comment at the top of this function.
5418	*/
5419	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5420	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5421	}
5422
5423	case SVM_EXIT_FERR_FREEZE:
5424	{
5425	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5426	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5427	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5428	}
5429
5430	case SVM_EXIT_INVLPG:
5431	{
5432	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
5433	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5434	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5435	}
5436
5437	case SVM_EXIT_WBINVD:
5438	{
5439	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_WBINVD))
5440	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5441	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5442	}
5443
5444	case SVM_EXIT_INVD:
5445	{
5446	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVD))
5447	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5448	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5449	}
5450
5451	case SVM_EXIT_RDPMC:
5452	{
5453	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
5454	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5455	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5456	}
5457
5458	default:
5459	{
5460	switch (uExitCode)
5461	{
5462	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5463	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5464	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5465	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5466	{
5467	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5468	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, uDr))
5469	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5470	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5471	}
5472
5473	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5474	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5475	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5476	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5477	{
5478	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5479	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, uDr))
5480	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5481	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5482	}
5483
5484	case SVM_EXIT_XCPT_DE:
5485	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5486	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5487	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5488	case SVM_EXIT_XCPT_OF:
5489	case SVM_EXIT_XCPT_BR:
5490	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5491	case SVM_EXIT_XCPT_NM:
5492	case SVM_EXIT_XCPT_DF:
5493	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5494	case SVM_EXIT_XCPT_TS:
5495	case SVM_EXIT_XCPT_NP:
5496	case SVM_EXIT_XCPT_SS:
5497	case SVM_EXIT_XCPT_GP:
5498	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5499	case SVM_EXIT_XCPT_15: /* Reserved. */
5500	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5501	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5502	case SVM_EXIT_XCPT_MC:
5503	case SVM_EXIT_XCPT_XF:
5504	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5505	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5506	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5507	{
5508	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5509	if (HMIsGuestSvmXcptInterceptSet(pVCpu, uVector))
5510	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5511	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5512	}
5513
5514	case SVM_EXIT_XSETBV:
5515	{
5516	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
5517	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5518	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5519	}
5520
5521	case SVM_EXIT_TASK_SWITCH:
5522	{
5523	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5524	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5525	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5526	}
5527
5528	case SVM_EXIT_IRET:
5529	{
5530	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_IRET))
5531	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5532	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5533	}
5534
5535	case SVM_EXIT_SHUTDOWN:
5536	{
5537	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_SHUTDOWN))
5538	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5539	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5540	}
5541
5542	case SVM_EXIT_VMMCALL:
5543	{
5544	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
5545	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5546	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5547	}
5548
5549	case SVM_EXIT_CLGI:
5550	{
5551	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
5552	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5553	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5554	}
5555
5556	case SVM_EXIT_STGI:
5557	{
5558	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_STGI))
5559	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5560	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5561	}
5562
5563	case SVM_EXIT_VMLOAD:
5564	{
5565	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
5566	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5567	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5568	}
5569
5570	case SVM_EXIT_VMSAVE:
5571	{
5572	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
5573	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5574	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5575	}
5576
5577	case SVM_EXIT_INVLPGA:
5578	{
5579	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
5580	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5581	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5582	}
5583
5584	case SVM_EXIT_VMRUN:
5585	{
5586	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
5587	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5588	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5589	}
5590
5591	case SVM_EXIT_RSM:
5592	{
5593	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RSM))
5594	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5595	hmR0SvmSetPendingXcptUD(pVCpu);
5596	return VINF_SUCCESS;
5597	}
5598
5599	case SVM_EXIT_SKINIT:
5600	{
5601	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
5602	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5603	hmR0SvmSetPendingXcptUD(pVCpu);
5604	return VINF_SUCCESS;
5605	}
5606
5607	case SVM_EXIT_NPF:
5608	{
5609	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5610	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5611	}
5612
5613	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5614	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5615
5616	default:
5617	{
5618	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5619	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5620	return VERR_SVM_UNKNOWN_EXIT;
5621	}
5622	}
5623	}
5624	}
5625	/* not reached */
5626
5627	#undef NST_GST_VMEXIT_CALL_RET
5628	}
5629	#endif
5630
5631
5632	/**
5633	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5634	*
5635	* @returns VBox status code (informational status codes included).
5636	* @param pVCpu The cross context virtual CPU structure.
5637	* @param pSvmTransient Pointer to the SVM transient structure.
5638	*/
5639	static int hmR0SvmHandleExit(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5640	{
5641	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5642	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5643
5644	#ifdef DEBUG_ramshankar
5645	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5646	do { \
5647	if ((a_fDbg) == 1) \
5648	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5649	int rc = a_CallExpr; \
5650	if ((a_fDbg) == 1) \
5651	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5652	return rc; \
5653	} while (0)
5654	#else
5655	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5656	#endif
5657
5658	/*
5659	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5660	* for most guests under normal workloads (for some definition of "normal").
5661	*/
5662	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5663	switch (uExitCode)
5664	{
5665	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5666	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5667	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5668	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5669	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5670	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5671	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5672	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5673	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5674	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5675
5676	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5677	case SVM_EXIT_INTR:
5678	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5679
5680	case SVM_EXIT_READ_CR0:
5681	case SVM_EXIT_READ_CR3:
5682	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5683
5684	case SVM_EXIT_CR0_SEL_WRITE:
5685	case SVM_EXIT_WRITE_CR0:
5686	case SVM_EXIT_WRITE_CR3:
5687	case SVM_EXIT_WRITE_CR4:
5688	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5689
5690	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5691	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5692	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5693	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5694	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5695	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5696	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5697	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5698	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5699	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5700	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5701	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5702	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5703	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5704	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5705	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5706
5707	default:
5708	{
5709	switch (pSvmTransient->u64ExitCode)
5710	{
5711	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5712	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5713	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5714	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5715	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5716
5717	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5718	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5719	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5720	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5721	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5722
5723	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5724	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5725
5726	case SVM_EXIT_SMI:
5727	case SVM_EXIT_INIT:
5728	{
5729	/*
5730	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5731	* If it ever does, we want to know about it so log the exit code and bail.
5732	*/
5733	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5734	}
5735
5736	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5737	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5738	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5739	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5740	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5741	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5742	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5743	#else
5744	case SVM_EXIT_CLGI:
5745	case SVM_EXIT_STGI:
5746	case SVM_EXIT_VMLOAD:
5747	case SVM_EXIT_VMSAVE:
5748	case SVM_EXIT_INVLPGA:
5749	case SVM_EXIT_VMRUN:
5750	#endif
5751	case SVM_EXIT_RSM:
5752	case SVM_EXIT_SKINIT:
5753	{
5754	hmR0SvmSetPendingXcptUD(pVCpu);
5755	return VINF_SUCCESS;
5756	}
5757
5758	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5759	case SVM_EXIT_XCPT_DE:
5760	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5761	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5762	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5763	case SVM_EXIT_XCPT_OF:
5764	case SVM_EXIT_XCPT_BR:
5765	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5766	case SVM_EXIT_XCPT_NM:
5767	case SVM_EXIT_XCPT_DF:
5768	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5769	case SVM_EXIT_XCPT_TS:
5770	case SVM_EXIT_XCPT_NP:
5771	case SVM_EXIT_XCPT_SS:
5772	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5773	/* SVM_EXIT_XCPT_PF: */
5774	case SVM_EXIT_XCPT_15: /* Reserved. */
5775	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5776	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5777	case SVM_EXIT_XCPT_MC:
5778	case SVM_EXIT_XCPT_XF:
5779	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5780	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5781	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5782	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5783	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5784
5785	default:
5786	{
5787	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5788	pVCpu->hm.s.u32HMError = uExitCode;
5789	return VERR_SVM_UNKNOWN_EXIT;
5790	}
5791	}
5792	}
5793	}
5794	/* not reached */
5795	#undef VMEXIT_CALL_RET
5796	}
5797
5798
5799	#ifdef VBOX_STRICT
5800	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5801	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5802	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5803
5804	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5805	do \
5806	{ \
5807	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5808	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5809	} while (0)
5810
5811	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5812	do { \
5813	AssertPtr((a_pVCpu)); \
5814	AssertPtr((a_pSvmTransient)); \
5815	Assert(ASMIntAreEnabled()); \
5816	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5817	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5818	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5819	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5820	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5821	HMSVM_ASSERT_PREEMPT_CPUID(); \
5822	} while (0)
5823	#else
5824	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5825	do { \
5826	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5827	} while (0)
5828	#endif
5829
5830
5831	/**
5832	* Gets the IEM exception flags for the specified SVM event.
5833	*
5834	* @returns The IEM exception flags.
5835	* @param pEvent Pointer to the SVM event.
5836	*
5837	* @remarks This function currently only constructs flags required for
5838	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5839	* and CR2 aspects of an exception are not included).
5840	*/
5841	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5842	{
5843	uint8_t const uEventType = pEvent->n.u3Type;
5844	uint32_t fIemXcptFlags;
5845	switch (uEventType)
5846	{
5847	case SVM_EVENT_EXCEPTION:
5848	/*
5849	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5850	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5851	*/
5852	if (pEvent->n.u8Vector == X86_XCPT_BP)
5853	{
5854	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5855	break;
5856	}
5857	if (pEvent->n.u8Vector == X86_XCPT_OF)
5858	{
5859	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5860	break;
5861	}
5862	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5863	RT_FALL_THRU();
5864	case SVM_EVENT_NMI:
5865	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5866	break;
5867
5868	case SVM_EVENT_EXTERNAL_IRQ:
5869	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5870	break;
5871
5872	case SVM_EVENT_SOFTWARE_INT:
5873	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5874	break;
5875
5876	default:
5877	fIemXcptFlags = 0;
5878	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5879	break;
5880	}
5881	return fIemXcptFlags;
5882	}
5883
5884
5885	/**
5886	* Handle a condition that occurred while delivering an event through the guest
5887	* IDT.
5888	*
5889	* @returns VBox status code (informational error codes included).
5890	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5891	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5892	* continue execution of the guest which will delivery the \#DF.
5893	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5894	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5895	*
5896	* @param pVCpu The cross context virtual CPU structure.
5897	* @param pSvmTransient Pointer to the SVM transient structure.
5898	*
5899	* @remarks No-long-jump zone!!!
5900	*/
5901	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5902	{
5903	int rc = VINF_SUCCESS;
5904	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5905	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5906
5907	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5908	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5909	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5910
5911	/*
5912	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5913	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5914	*
5915	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5916	*/
5917	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5918	{
5919	IEMXCPTRAISE enmRaise;
5920	IEMXCPTRAISEINFO fRaiseInfo;
5921	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5922	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5923	if (fExitIsHwXcpt)
5924	{
5925	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5926	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5927	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5928	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5929	}
5930	else
5931	{
5932	/*
5933	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5934	* then we end up here.
5935	*
5936	* If the event was:
5937	* - a software interrupt, we can re-execute the instruction which will
5938	* regenerate the event.
5939	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5940	* - a hardware exception or external interrupt, we re-inject it.
5941	*/
5942	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5943	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5944	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5945	else
5946	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5947	}
5948
5949	switch (enmRaise)
5950	{
5951	case IEMXCPTRAISE_CURRENT_XCPT:
5952	case IEMXCPTRAISE_PREV_EVENT:
5953	{
5954	/* For software interrupts, we shall re-execute the instruction. */
5955	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5956	{
5957	RTGCUINTPTR GCPtrFaultAddress = 0;
5958
5959	/* If we are re-injecting an NMI, clear NMI blocking. */
5960	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5961	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5962
5963	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5964	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5965	{
5966	pSvmTransient->fVectoringPF = true;
5967	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5968	pVCpu->cpum.GstCtx.cr2));
5969	}
5970	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5971	&& uIdtVector == X86_XCPT_PF)
5972	{
5973	/*
5974	* If the previous exception was a #PF, we need to recover the CR2 value.
5975	* This can't happen with shadow paging.
5976	*/
5977	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5978	}
5979
5980	/*
5981	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5982	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5983	*/
5984	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5985	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5986	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5987
5988	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5989	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5990	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5991	}
5992	break;
5993	}
5994
5995	case IEMXCPTRAISE_REEXEC_INSTR:
5996	{
5997	Assert(rc == VINF_SUCCESS);
5998	break;
5999	}
6000
6001	case IEMXCPTRAISE_DOUBLE_FAULT:
6002	{
6003	/*
6004	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
6005	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
6006	* converted into a #DF.
6007	*/
6008	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
6009	{
6010	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
6011	pSvmTransient->fVectoringDoublePF = true;
6012	Assert(rc == VINF_SUCCESS);
6013	}
6014	else
6015	{
6016	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6017	hmR0SvmSetPendingXcptDF(pVCpu);
6018	rc = VINF_HM_DOUBLE_FAULT;
6019	}
6020	break;
6021	}
6022
6023	case IEMXCPTRAISE_TRIPLE_FAULT:
6024	{
6025	rc = VINF_EM_RESET;
6026	break;
6027	}
6028
6029	case IEMXCPTRAISE_CPU_HANG:
6030	{
6031	rc = VERR_EM_GUEST_CPU_HANG;
6032	break;
6033	}
6034
6035	default:
6036	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
6037	}
6038	}
6039	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6040	return rc;
6041	}
6042
6043
6044	/**
6045	* Advances the guest RIP by the number of bytes specified in @a cb.
6046	*
6047	* @param pVCpu The cross context virtual CPU structure.
6048	* @param cb RIP increment value in bytes.
6049	*/
6050	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPU pVCpu, uint32_t cb)
6051	{
6052	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6053	pCtx->rip += cb;
6054
6055	/* Update interrupt shadow. */
6056	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
6057	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
6058	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6059	}
6060
6061
6062	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6063	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6064	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6065
6066	/** @name \#VMEXIT handlers.
6067	* @{
6068	*/
6069
6070	/**
6071	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6072	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6073	*/
6074	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6075	{
6076	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6077
6078	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6079	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6080	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6081	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6082
6083	/*
6084	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
6085	* signal -before- the timer fires if the current interrupt is our own timer or a some
6086	* other host interrupt. We also cannot examine what interrupt it is until the host
6087	* actually take the interrupt.
6088	*
6089	* Going back to executing guest code here unconditionally causes random scheduling
6090	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6091	*/
6092	return VINF_EM_RAW_INTERRUPT;
6093	}
6094
6095
6096	/**
6097	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6098	*/
6099	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6100	{
6101	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6102
6103	VBOXSTRICTRC rcStrict;
6104	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6105	if (fSupportsNextRipSave)
6106	{
6107	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6108	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6109	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6110	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
6111	}
6112	else
6113	{
6114	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6115	rcStrict = IEMExecOne(pVCpu);
6116	}
6117
6118	if (rcStrict == VINF_IEM_RAISED_XCPT)
6119	{
6120	rcStrict = VINF_SUCCESS;
6121	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6122	}
6123	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6124	return VBOXSTRICTRC_TODO(rcStrict);
6125	}
6126
6127
6128	/**
6129	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6130	*/
6131	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6132	{
6133	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6134
6135	VBOXSTRICTRC rcStrict;
6136	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6137	if (fSupportsNextRipSave)
6138	{
6139	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6140	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6141	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6142	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
6143	}
6144	else
6145	{
6146	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6147	rcStrict = IEMExecOne(pVCpu);
6148	}
6149
6150	if (rcStrict == VINF_IEM_RAISED_XCPT)
6151	{
6152	rcStrict = VINF_SUCCESS;
6153	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6154	}
6155	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6156	return VBOXSTRICTRC_TODO(rcStrict);
6157	}
6158
6159
6160	/**
6161	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6162	*/
6163	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6164	{
6165	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6166
6167	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
6168	VBOXSTRICTRC rcStrict;
6169	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6170	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
6171	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6172	if (!pExitRec)
6173	{
6174	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6175	if (fSupportsNextRipSave)
6176	{
6177	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6178	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6179	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
6180	}
6181	else
6182	{
6183	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6184	rcStrict = IEMExecOne(pVCpu);
6185	}
6186
6187	if (rcStrict == VINF_IEM_RAISED_XCPT)
6188	{
6189	rcStrict = VINF_SUCCESS;
6190	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6191	}
6192	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6193	}
6194	else
6195	{
6196	/*
6197	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6198	*/
6199	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6200
6201	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
6202	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
6203
6204	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6205
6206	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6207	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6208	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6209	}
6210	return VBOXSTRICTRC_TODO(rcStrict);
6211	}
6212
6213
6214	/**
6215	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6216	*/
6217	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6218	{
6219	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6220
6221	VBOXSTRICTRC rcStrict;
6222	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6223	if (fSupportsNextRipSave)
6224	{
6225	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6226	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6227	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6228	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
6229	}
6230	else
6231	{
6232	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6233	rcStrict = IEMExecOne(pVCpu);
6234	}
6235
6236	if (rcStrict == VINF_SUCCESS)
6237	pSvmTransient->fUpdateTscOffsetting = true;
6238	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6239	{
6240	rcStrict = VINF_SUCCESS;
6241	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6242	}
6243	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6244	return VBOXSTRICTRC_TODO(rcStrict);
6245	}
6246
6247
6248	/**
6249	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6250	*/
6251	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6252	{
6253	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6254
6255	VBOXSTRICTRC rcStrict;
6256	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6257	if (fSupportsNextRipSave)
6258	{
6259	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
6260	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6261	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6262	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
6263	}
6264	else
6265	{
6266	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6267	rcStrict = IEMExecOne(pVCpu);
6268	}
6269
6270	if (rcStrict == VINF_SUCCESS)
6271	pSvmTransient->fUpdateTscOffsetting = true;
6272	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6273	{
6274	rcStrict = VINF_SUCCESS;
6275	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6276	}
6277	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6278	return VBOXSTRICTRC_TODO(rcStrict);
6279	}
6280
6281
6282	/**
6283	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6284	*/
6285	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6286	{
6287	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6288
6289	VBOXSTRICTRC rcStrict;
6290	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6291	if (fSupportsNextRipSave)
6292	{
6293	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6294	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6295	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6296	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
6297	}
6298	else
6299	{
6300	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6301	rcStrict = IEMExecOne(pVCpu);
6302	}
6303
6304	if (rcStrict == VINF_IEM_RAISED_XCPT)
6305	{
6306	rcStrict = VINF_SUCCESS;
6307	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6308	}
6309	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6310	return VBOXSTRICTRC_TODO(rcStrict);
6311	}
6312
6313
6314	/**
6315	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6316	*/
6317	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6318	{
6319	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6320	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6321
6322	VBOXSTRICTRC rcStrict;
6323	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6324	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6325	if ( fSupportsDecodeAssists
6326	&& fSupportsNextRipSave)
6327	{
6328	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
6329	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6330	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6331	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6332	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6333	}
6334	else
6335	{
6336	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6337	rcStrict = IEMExecOne(pVCpu);
6338	}
6339
6340	if (rcStrict == VINF_IEM_RAISED_XCPT)
6341	{
6342	rcStrict = VINF_SUCCESS;
6343	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6344	}
6345	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6346	return VBOXSTRICTRC_VAL(rcStrict);
6347	}
6348
6349
6350	/**
6351	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6352	*/
6353	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6354	{
6355	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6356
6357	VBOXSTRICTRC rcStrict;
6358	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6359	if (fSupportsNextRipSave)
6360	{
6361	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6362	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6363	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6364	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6365	}
6366	else
6367	{
6368	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6369	rcStrict = IEMExecOne(pVCpu);
6370	}
6371
6372	if ( rcStrict == VINF_EM_HALT
6373	\|\| rcStrict == VINF_SUCCESS)
6374	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6375	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6376	{
6377	rcStrict = VINF_SUCCESS;
6378	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6379	}
6380	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6381	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6382	if (rcStrict != VINF_SUCCESS)
6383	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6384	return VBOXSTRICTRC_VAL(rcStrict);;
6385	}
6386
6387
6388	/**
6389	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6390	*/
6391	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6392	{
6393	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6394
6395	/*
6396	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6397	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6398	* segment override prefix or other prefixes might be used, in which case we fallback to
6399	* IEMExecOne() to figure out.
6400	*/
6401	VBOXSTRICTRC rcStrict;
6402	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6403	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6404	if (cbInstr)
6405	{
6406	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6407	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6408	}
6409	else
6410	{
6411	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6412	rcStrict = IEMExecOne(pVCpu);
6413	}
6414
6415	if (rcStrict == VINF_IEM_RAISED_XCPT)
6416	{
6417	rcStrict = VINF_SUCCESS;
6418	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6419	}
6420	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6421	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6422	return VBOXSTRICTRC_TODO(rcStrict);
6423	}
6424
6425
6426	/**
6427	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6428	*/
6429	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6430	{
6431	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6432
6433	VBOXSTRICTRC rcStrict;
6434	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6435	if (fSupportsNextRipSave)
6436	{
6437	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6438	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6439	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6440	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6441	}
6442	else
6443	{
6444	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6445	rcStrict = IEMExecOne(pVCpu);
6446	}
6447
6448	if ( rcStrict == VINF_EM_HALT
6449	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6450	rcStrict = VINF_SUCCESS;
6451	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6452	{
6453	rcStrict = VINF_SUCCESS;
6454	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6455	}
6456	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6457	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6458	return VBOXSTRICTRC_TODO(rcStrict);
6459	}
6460
6461
6462	/**
6463	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6464	* \#VMEXIT.
6465	*/
6466	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6467	{
6468	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6469	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6470	return VINF_EM_RESET;
6471	}
6472
6473
6474	/**
6475	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6476	*/
6477	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6478	{
6479	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6480	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6481	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6482	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6483	RT_NOREF(pVmcb);
6484	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6485	return VERR_SVM_UNEXPECTED_EXIT;
6486	}
6487
6488
6489	/**
6490	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6491	*/
6492	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6493	{
6494	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6495
6496	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6497	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6498	#ifdef VBOX_WITH_STATISTICS
6499	switch (pSvmTransient->u64ExitCode)
6500	{
6501	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6502	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6503	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6504	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6505	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6506	}
6507	#endif
6508
6509	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6510	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6511	if ( fSupportsDecodeAssists
6512	&& fSupportsNextRipSave)
6513	{
6514	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6515	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6516	if (fMovCRx)
6517	{
6518	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6519	\| CPUMCTX_EXTRN_APIC_TPR);
6520	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6521	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6522	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6523	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6524	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6525	return VBOXSTRICTRC_VAL(rcStrict);
6526	}
6527	/* else: SMSW instruction, fall back below to IEM for this. */
6528	}
6529
6530	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6531	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6532	AssertMsg( rcStrict == VINF_SUCCESS
6533	\|\| rcStrict == VINF_PGM_SYNC_CR3
6534	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6535	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6536	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6537	if (rcStrict == VINF_IEM_RAISED_XCPT)
6538	{
6539	rcStrict = VINF_SUCCESS;
6540	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6541	}
6542	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6543	return VBOXSTRICTRC_TODO(rcStrict);
6544	}
6545
6546
6547	/**
6548	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6549	*/
6550	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6551	{
6552	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6553
6554	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6555	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6556	Assert(iCrReg <= 15);
6557
6558	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6559	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6560	bool fDecodedInstr = false;
6561	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6562	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6563	if ( fSupportsDecodeAssists
6564	&& fSupportsNextRipSave)
6565	{
6566	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6567	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6568	if (fMovCRx)
6569	{
6570	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6571	\| CPUMCTX_EXTRN_APIC_TPR);
6572	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6573	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6574	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6575	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6576	fDecodedInstr = true;
6577	}
6578	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6579	}
6580
6581	if (!fDecodedInstr)
6582	{
6583	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6584	Log4Func(("iCrReg=%#x\n", iCrReg));
6585	rcStrict = IEMExecOne(pVCpu);
6586	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6587	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6588	rcStrict = VERR_EM_INTERPRETER;
6589	}
6590
6591	if (rcStrict == VINF_SUCCESS)
6592	{
6593	switch (iCrReg)
6594	{
6595	case 0:
6596	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6597	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6598	break;
6599
6600	case 2:
6601	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6602	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6603	break;
6604
6605	case 3:
6606	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6607	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6608	break;
6609
6610	case 4:
6611	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6612	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6613	break;
6614
6615	case 8:
6616	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6617	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6618	break;
6619
6620	default:
6621	{
6622	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6623	pSvmTransient->u64ExitCode, iCrReg));
6624	break;
6625	}
6626	}
6627	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6628	}
6629	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6630	{
6631	rcStrict = VINF_SUCCESS;
6632	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6633	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6634	}
6635	else
6636	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6637	return VBOXSTRICTRC_TODO(rcStrict);
6638	}
6639
6640
6641	/**
6642	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6643	*
6644	* @returns Strict VBox status code.
6645	* @param pVCpu The cross context virtual CPU structure.
6646	* @param pVmcb Pointer to the VM control block.
6647	*/
6648	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPU pVCpu, PSVMVMCB pVmcb)
6649	{
6650	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6651	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6652
6653	VBOXSTRICTRC rcStrict;
6654	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6655	if (fSupportsNextRipSave)
6656	{
6657	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6658	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6659	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6660	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6661	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6662	}
6663	else
6664	{
6665	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6666	rcStrict = IEMExecOne(pVCpu);
6667	}
6668
6669	AssertMsg( rcStrict == VINF_SUCCESS
6670	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6671	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6672	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6673
6674	if (rcStrict == VINF_IEM_RAISED_XCPT)
6675	{
6676	rcStrict = VINF_SUCCESS;
6677	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6678	}
6679	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6680	return rcStrict;
6681	}
6682
6683
6684	/**
6685	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6686	*
6687	* @returns Strict VBox status code.
6688	* @param pVCpu The cross context virtual CPU structure.
6689	* @param pVmcb Pointer to the VM control block.
6690	* @param pSvmTransient Pointer to the SVM-transient structure.
6691	*/
6692	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPU pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6693	{
6694	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6695	uint32_t const idMsr = pCtx->ecx;
6696	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6697	Log4Func(("idMsr=%#RX32\n", idMsr));
6698
6699	/*
6700	* Handle TPR patching MSR writes.
6701	* We utilitize the LSTAR MSR for patching.
6702	*/
6703	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6704	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
6705	&& idMsr == MSR_K8_LSTAR)
6706	{
6707	unsigned cbInstr;
6708	if (fSupportsNextRipSave)
6709	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6710	else
6711	{
6712	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6713	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6714	if ( rc == VINF_SUCCESS
6715	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6716	Assert(cbInstr > 0);
6717	else
6718	cbInstr = 0;
6719	}
6720
6721	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6722	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6723	{
6724	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6725	AssertRCReturn(rc, rc);
6726	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6727	}
6728
6729	int rc = VINF_SUCCESS;
6730	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6731	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6732	return rc;
6733	}
6734
6735	/*
6736	* Handle regular MSR writes.
6737	*/
6738	VBOXSTRICTRC rcStrict;
6739	if (fSupportsNextRipSave)
6740	{
6741	/** @todo Optimize this: We don't need to get much of the MSR state here
6742	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6743	* clear the applicable extern flags. */
6744	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6745	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6746	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6747	}
6748	else
6749	{
6750	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6751	rcStrict = IEMExecOne(pVCpu);
6752	}
6753
6754	AssertMsg( rcStrict == VINF_SUCCESS
6755	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6756	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6757	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6758
6759	if (rcStrict == VINF_SUCCESS)
6760	{
6761	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6762	if ( idMsr >= MSR_IA32_X2APIC_START
6763	&& idMsr <= MSR_IA32_X2APIC_END)
6764	{
6765	/*
6766	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6767	* When full APIC register virtualization is implemented we'll have to make sure
6768	* APIC state is saved from the VMCB before IEM changes it.
6769	*/
6770	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6771	}
6772	else
6773	{
6774	switch (idMsr)
6775	{
6776	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6777	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6778	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6779	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6780	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6781	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6782	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6783	}
6784	}
6785	}
6786	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6787	{
6788	rcStrict = VINF_SUCCESS;
6789	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6790	}
6791	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6792	return rcStrict;
6793	}
6794
6795
6796	/**
6797	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6798	* \#VMEXIT.
6799	*/
6800	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6801	{
6802	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6803
6804	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6805	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6806	return VBOXSTRICTRC_TODO(hmR0SvmExitReadMsr(pVCpu, pVmcb));
6807
6808	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6809	return VBOXSTRICTRC_TODO(hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient));
6810	}
6811
6812
6813	/**
6814	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6815	*/
6816	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6817	{
6818	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6819	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6820
6821	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6822
6823	/** @todo Stepping with nested-guest. */
6824	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6825	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6826	{
6827	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6828	if (pSvmTransient->fWasGuestDebugStateActive)
6829	{
6830	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6831	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6832	return VERR_SVM_UNEXPECTED_EXIT;
6833	}
6834
6835	/*
6836	* Lazy DR0-3 loading.
6837	*/
6838	if (!pSvmTransient->fWasHyperDebugStateActive)
6839	{
6840	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6841	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6842
6843	/* Don't intercept DRx read and writes. */
6844	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6845	pVmcb->ctrl.u16InterceptRdDRx = 0;
6846	pVmcb->ctrl.u16InterceptWrDRx = 0;
6847	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6848
6849	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6850	VMMRZCallRing3Disable(pVCpu);
6851	HM_DISABLE_PREEMPT(pVCpu);
6852
6853	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6854	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6855	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6856
6857	HM_RESTORE_PREEMPT();
6858	VMMRZCallRing3Enable(pVCpu);
6859
6860	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6861	return VINF_SUCCESS;
6862	}
6863	}
6864
6865	/*
6866	* Interpret the read/writing of DRx.
6867	*/
6868	/** @todo Decode assist. */
6869	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6870	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6871	if (RT_LIKELY(rc == VINF_SUCCESS))
6872	{
6873	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6874	/** @todo CPUM should set this flag! */
6875	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6876	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6877	}
6878	else
6879	Assert(rc == VERR_EM_INTERPRETER);
6880	return VBOXSTRICTRC_TODO(rc);
6881	}
6882
6883
6884	/**
6885	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6886	*/
6887	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6888	{
6889	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6890	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6891	int rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6892	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6893	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6894	return rc;
6895	}
6896
6897
6898	/**
6899	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6900	*/
6901	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6902	{
6903	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6904	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6905
6906	/** @todo decode assists... */
6907	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6908	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6909	{
6910	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6911	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6912	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0,
6913	pCtx->cr4));
6914	}
6915	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6916	{
6917	rcStrict = VINF_SUCCESS;
6918	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6919	}
6920	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6921	return VBOXSTRICTRC_TODO(rcStrict);
6922	}
6923
6924
6925	/**
6926	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6927	*/
6928	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6929	{
6930	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6931	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6932
6933	/* I/O operation lookup arrays. */
6934	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6935	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6936	the result (in AL/AX/EAX). */
6937	PVM pVM = pVCpu->CTX_SUFF(pVM);
6938	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6939	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6940
6941	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6942
6943	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6944	SVMIOIOEXITINFO IoExitInfo;
6945	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6946	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6947	uint32_t cbValue = s_aIOSize[uIOWidth];
6948	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6949
6950	if (RT_UNLIKELY(!cbValue))
6951	{
6952	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6953	return VERR_EM_INTERPRETER;
6954	}
6955
6956	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6957	VBOXSTRICTRC rcStrict;
6958	PCEMEXITREC pExitRec = NULL;
6959	if ( !pVCpu->hm.s.fSingleInstruction
6960	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6961	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6962	!IoExitInfo.n.u1Str
6963	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6964	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6965	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6966	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6967	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6968	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6969	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6970	if (!pExitRec)
6971	{
6972	bool fUpdateRipAlready = false;
6973	if (IoExitInfo.n.u1Str)
6974	{
6975	/* INS/OUTS - I/O String instruction. */
6976	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6977	* in EXITINFO1? Investigate once this thing is up and running. */
6978	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6979	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6980	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6981	static IEMMODE const s_aenmAddrMode[8] =
6982	{
6983	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6984	};
6985	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6986	if (enmAddrMode != (IEMMODE)-1)
6987	{
6988	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6989	if (cbInstr <= 15 && cbInstr >= 1)
6990	{
6991	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6992	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6993	{
6994	/* Don't know exactly how to detect whether u3Seg is valid, currently
6995	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6996	2384 Opterons when only checking NRIP. */
6997	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6998	if ( fSupportsNextRipSave
6999	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
7000	{
7001	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
7002	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
7003	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
7004	IoExitInfo.n.u3Seg, true /fIoChecked/);
7005	}
7006	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
7007	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
7008	X86_SREG_DS, true /fIoChecked/);
7009	else
7010	rcStrict = IEMExecOne(pVCpu);
7011	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
7012	}
7013	else
7014	{
7015	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
7016	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
7017	true /fIoChecked/);
7018	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
7019	}
7020	}
7021	else
7022	{
7023	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
7024	rcStrict = IEMExecOne(pVCpu);
7025	}
7026	}
7027	else
7028	{
7029	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
7030	rcStrict = IEMExecOne(pVCpu);
7031	}
7032	fUpdateRipAlready = true;
7033	}
7034	else
7035	{
7036	/* IN/OUT - I/O instruction. */
7037	Assert(!IoExitInfo.n.u1Rep);
7038
7039	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
7040	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
7041	{
7042	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
7043	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
7044	&& !pCtx->eflags.Bits.u1TF)
7045	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
7046	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
7047	}
7048	else
7049	{
7050	uint32_t u32Val = 0;
7051	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
7052	if (IOM_SUCCESS(rcStrict))
7053	{
7054	/* Save result of I/O IN instr. in AL/AX/EAX. */
7055	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
7056	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
7057	}
7058	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
7059	&& !pCtx->eflags.Bits.u1TF)
7060	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
7061
7062	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
7063	}
7064	}
7065
7066	if (IOM_SUCCESS(rcStrict))
7067	{
7068	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
7069	if (!fUpdateRipAlready)
7070	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
7071
7072	/*
7073	* If any I/O breakpoints are armed, we need to check if one triggered
7074	* and take appropriate action.
7075	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
7076	*/
7077	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
7078	* execution engines about whether hyper BPs and such are pending. */
7079	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
7080	uint32_t const uDr7 = pCtx->dr[7];
7081	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7082	&& X86_DR7_ANY_RW_IO(uDr7)
7083	&& (pCtx->cr4 & X86_CR4_DE))
7084	\|\| DBGFBpIsHwIoArmed(pVM)))
7085	{
7086	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7087	VMMRZCallRing3Disable(pVCpu);
7088	HM_DISABLE_PREEMPT(pVCpu);
7089
7090	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
7091	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
7092
7093	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
7094	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
7095	{
7096	/* Raise #DB. */
7097	pVmcb->guest.u64DR6 = pCtx->dr[6];
7098	pVmcb->guest.u64DR7 = pCtx->dr[7];
7099	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7100	hmR0SvmSetPendingXcptDB(pVCpu);
7101	}
7102	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
7103	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
7104	else if ( rcStrict2 != VINF_SUCCESS
7105	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
7106	rcStrict = rcStrict2;
7107	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
7108
7109	HM_RESTORE_PREEMPT();
7110	VMMRZCallRing3Enable(pVCpu);
7111	}
7112
7113	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7114	}
7115
7116	#ifdef VBOX_STRICT
7117	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
7118	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
7119	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
7120	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
7121	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
7122	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
7123	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
7124	else
7125	{
7126	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
7127	* statuses, that the VMM device and some others may return. See
7128	* IOM_SUCCESS() for guidance. */
7129	AssertMsg( RT_FAILURE(rcStrict)
7130	\|\| rcStrict == VINF_SUCCESS
7131	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
7132	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
7133	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
7134	\|\| rcStrict == VINF_EM_RAW_TO_R3
7135	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
7136	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7137	}
7138	#endif
7139	}
7140	else
7141	{
7142	/*
7143	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
7144	*/
7145	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7146	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
7147	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
7148	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
7149	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
7150	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
7151	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
7152
7153	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7154	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7155
7156	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7157	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7158	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7159	}
7160	return VBOXSTRICTRC_TODO(rcStrict);
7161	}
7162
7163
7164	/**
7165	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
7166	*/
7167	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7168	{
7169	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7170	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7171	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7172
7173	PVM pVM = pVCpu->CTX_SUFF(pVM);
7174	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7175	Assert(pVM->hm.s.fNestedPaging);
7176
7177	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7178	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7179	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7180	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
7181	thus intentionally not copied into u32ErrCode. */
7182
7183	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
7184	u32ErrCode));
7185
7186	/*
7187	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
7188	*/
7189	if ( pVM->hm.s.fTprPatchingAllowed
7190	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7191	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7192	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7193	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7194	&& !CPUMIsGuestInLongModeEx(pCtx)
7195	&& !CPUMGetGuestCPL(pVCpu)
7196	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7197	{
7198	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7199	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7200
7201	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7202	{
7203	/* Only attempt to patch the instruction once. */
7204	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7205	if (!pPatch)
7206	return VINF_EM_HM_PATCH_TPR_INSTR;
7207	}
7208	}
7209
7210	/*
7211	* Determine the nested paging mode.
7212	*/
7213	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
7214	PGMMODE enmNestedPagingMode;
7215	#if HC_ARCH_BITS == 32
7216	if (CPUMIsGuestInLongModeEx(pCtx))
7217	enmNestedPagingMode = PGMMODE_AMD64_NX;
7218	else
7219	#endif
7220	enmNestedPagingMode = PGMGetHostMode(pVM);
7221
7222	/*
7223	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7224	*/
7225	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7226	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7227	{
7228	/*
7229	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
7230	* injecting the original pending event would most likely cause the same MMIO #NPF.
7231	*/
7232	if (pVCpu->hm.s.Event.fPending)
7233	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7234
7235	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
7236	VBOXSTRICTRC rcStrict;
7237	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
7238	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
7239	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
7240	if (!pExitRec)
7241	{
7242
7243	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7244	u32ErrCode);
7245
7246	/*
7247	* If we succeed, resume guest execution.
7248	*
7249	* If we fail in interpreting the instruction because we couldn't get the guest
7250	* physical address of the page containing the instruction via the guest's page
7251	* tables (we would invalidate the guest page in the host TLB), resume execution
7252	* which would cause a guest page fault to let the guest handle this weird case.
7253	*
7254	* See @bugref{6043}.
7255	*/
7256	if ( rcStrict == VINF_SUCCESS
7257	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
7258	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
7259	{
7260	/* Successfully handled MMIO operation. */
7261	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
7262	rcStrict = VINF_SUCCESS;
7263	}
7264	}
7265	else
7266	{
7267	/*
7268	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
7269	*/
7270	Assert(pCtx == &pVCpu->cpum.GstCtx);
7271	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7272	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
7273	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
7274
7275	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7276	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7277
7278	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7279	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7280	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7281	}
7282	return VBOXSTRICTRC_TODO(rcStrict);
7283	}
7284
7285	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7286	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7287	TRPMResetTrap(pVCpu);
7288
7289	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7290
7291	/*
7292	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7293	*/
7294	if ( rc == VINF_SUCCESS
7295	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7296	\|\| rc == VERR_PAGE_NOT_PRESENT)
7297	{
7298	/* We've successfully synced our shadow page tables. */
7299	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7300	rc = VINF_SUCCESS;
7301	}
7302
7303	return rc;
7304	}
7305
7306
7307	/**
7308	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7309	* \#VMEXIT.
7310	*/
7311	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7312	{
7313	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7314	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7315
7316	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7317	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7318	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
7319
7320	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7321	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7322	return VINF_SUCCESS;
7323	}
7324
7325
7326	/**
7327	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7328	* \#VMEXIT.
7329	*/
7330	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7331	{
7332	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7333	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7334
7335	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7336	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7337	#endif
7338
7339	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7340	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7341	{
7342	/*
7343	* AMD-V provides us with the exception which caused the TS; we collect
7344	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7345	*/
7346	Log4Func(("TS occurred during event delivery\n"));
7347	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7348	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7349	}
7350
7351	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7352	* emulation. */
7353	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7354	return VERR_EM_INTERPRETER;
7355	}
7356
7357
7358	/**
7359	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7360	*/
7361	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7362	{
7363	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7364	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7365
7366	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTprPatchingAllowed)
7367	{
7368	int rc = hmSvmEmulateMovTpr(pVCpu);
7369	if (rc != VERR_NOT_FOUND)
7370	{
7371	Log4Func(("hmSvmEmulateMovTpr returns %Rrc\n", rc));
7372	return rc;
7373	}
7374	}
7375
7376	if (EMAreHypercallInstructionsEnabled(pVCpu))
7377	{
7378	unsigned cbInstr;
7379	if (hmR0SvmSupportsNextRipSave(pVCpu))
7380	{
7381	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7382	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7383	}
7384	else
7385	{
7386	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7387	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7388	if ( rc == VINF_SUCCESS
7389	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7390	Assert(cbInstr > 0);
7391	else
7392	cbInstr = 0;
7393	}
7394
7395	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7396	if (RT_SUCCESS(rcStrict))
7397	{
7398	/* Only update the RIP if we're continuing guest execution and not in the case
7399	of say VINF_GIM_R3_HYPERCALL. */
7400	if (rcStrict == VINF_SUCCESS)
7401	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7402
7403	return VBOXSTRICTRC_VAL(rcStrict);
7404	}
7405	else
7406	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7407	}
7408
7409	hmR0SvmSetPendingXcptUD(pVCpu);
7410	return VINF_SUCCESS;
7411	}
7412
7413
7414	/**
7415	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7416	*/
7417	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7418	{
7419	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7420
7421	unsigned cbInstr;
7422	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7423	if (fSupportsNextRipSave)
7424	{
7425	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7426	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7427	}
7428	else
7429	{
7430	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7431	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7432	if ( rc == VINF_SUCCESS
7433	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7434	Assert(cbInstr > 0);
7435	else
7436	cbInstr = 0;
7437	}
7438
7439	/** @todo The guest has likely hit a contended spinlock. We might want to
7440	* poke a schedule different guest VCPU. */
7441	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7442	return VINF_EM_RAW_INTERRUPT;
7443	}
7444
7445
7446	/**
7447	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7448	* \#VMEXIT.
7449	*/
7450	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7451	{
7452	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7453	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7454	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7455
7456	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7457	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7458	}
7459
7460
7461	/**
7462	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7463	*/
7464	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7465	{
7466	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7467
7468	/* Clear NMI blocking. */
7469	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7470	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7471
7472	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7473	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7474	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7475
7476	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7477	return VINF_SUCCESS;
7478	}
7479
7480
7481	/**
7482	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7483	* Conditional \#VMEXIT.
7484	*/
7485	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7486	{
7487	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7488	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7489	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7490
7491	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7492	PVM pVM = pVCpu->CTX_SUFF(pVM);
7493	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7494	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7495	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7496	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7497
7498	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7499	if (pVM->hm.s.fNestedPaging)
7500	{
7501	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7502	if ( !pSvmTransient->fVectoringDoublePF
7503	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7504	{
7505	/* A genuine guest #PF, reflect it to the guest. */
7506	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7507	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7508	uFaultAddress, uErrCode));
7509	}
7510	else
7511	{
7512	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7513	hmR0SvmSetPendingXcptDF(pVCpu);
7514	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7515	}
7516	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7517	return VINF_SUCCESS;
7518	}
7519	#endif
7520
7521	Assert(!pVM->hm.s.fNestedPaging);
7522
7523	/*
7524	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7525	*/
7526	if ( pVM->hm.s.fTprPatchingAllowed
7527	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7528	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7529	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7530	&& !CPUMIsGuestInLongModeEx(pCtx)
7531	&& !CPUMGetGuestCPL(pVCpu)
7532	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7533	{
7534	RTGCPHYS GCPhysApicBase;
7535	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7536	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7537
7538	/* Check if the page at the fault-address is the APIC base. */
7539	RTGCPHYS GCPhysPage;
7540	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7541	if ( rc2 == VINF_SUCCESS
7542	&& GCPhysPage == GCPhysApicBase)
7543	{
7544	/* Only attempt to patch the instruction once. */
7545	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7546	if (!pPatch)
7547	return VINF_EM_HM_PATCH_TPR_INSTR;
7548	}
7549	}
7550
7551	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7552	pCtx->rip, uErrCode, pCtx->cr3));
7553
7554	/*
7555	* If it's a vectoring #PF, emulate injecting the original event injection as
7556	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7557	* event injection that caused a #PF. See @bugref{6607}.
7558	*/
7559	if (pSvmTransient->fVectoringPF)
7560	{
7561	Assert(pVCpu->hm.s.Event.fPending);
7562	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7563	}
7564
7565	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7566	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7567
7568	Log4Func(("#PF: rc=%Rrc\n", rc));
7569
7570	if (rc == VINF_SUCCESS)
7571	{
7572	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7573	TRPMResetTrap(pVCpu);
7574	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7575	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7576	return rc;
7577	}
7578
7579	if (rc == VINF_EM_RAW_GUEST_TRAP)
7580	{
7581	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7582
7583	/*
7584	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7585	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7586	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7587	*/
7588	if ( !pSvmTransient->fVectoringDoublePF
7589	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7590	{
7591	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7592	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7593	TRPMResetTrap(pVCpu);
7594
7595	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7596	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7597	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7598	&& HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_PF))
7599	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress));
7600	#endif
7601
7602	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7603	}
7604	else
7605	{
7606	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7607	TRPMResetTrap(pVCpu);
7608	hmR0SvmSetPendingXcptDF(pVCpu);
7609	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7610	}
7611
7612	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7613	return VINF_SUCCESS;
7614	}
7615
7616	TRPMResetTrap(pVCpu);
7617	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7618	return rc;
7619	}
7620
7621
7622	/**
7623	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7624	* Conditional \#VMEXIT.
7625	*/
7626	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7627	{
7628	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7629	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7630
7631	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7632	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7633	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7634
7635	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7636	if (pVCpu->hm.s.fGIMTrapXcptUD)
7637	{
7638	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7639	uint8_t cbInstr = 0;
7640	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7641	if (rcStrict == VINF_SUCCESS)
7642	{
7643	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7644	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7645	rc = VINF_SUCCESS;
7646	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7647	}
7648	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7649	rc = VINF_SUCCESS;
7650	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7651	rc = VINF_GIM_R3_HYPERCALL;
7652	else
7653	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7654	}
7655
7656	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7657	if (RT_FAILURE(rc))
7658	{
7659	hmR0SvmSetPendingXcptUD(pVCpu);
7660	rc = VINF_SUCCESS;
7661	}
7662
7663	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7664	return rc;
7665	}
7666
7667
7668	/**
7669	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7670	* Conditional \#VMEXIT.
7671	*/
7672	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7673	{
7674	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7675	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7676
7677	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7678	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7679
7680	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7681	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7682
7683	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7684
7685	if (!(pCtx->cr0 & X86_CR0_NE))
7686	{
7687	PVM pVM = pVCpu->CTX_SUFF(pVM);
7688	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7689	unsigned cbInstr;
7690	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7691	if (RT_SUCCESS(rc))
7692	{
7693	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7694	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7695	if (RT_SUCCESS(rc))
7696	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7697	}
7698	else
7699	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7700	return rc;
7701	}
7702
7703	hmR0SvmSetPendingXcptMF(pVCpu);
7704	return VINF_SUCCESS;
7705	}
7706
7707
7708	/**
7709	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7710	* \#VMEXIT.
7711	*/
7712	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7713	{
7714	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7715	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7716	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7717
7718	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7719	{
7720	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7721	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7722	}
7723
7724	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7725
7726	/*
7727	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7728	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7729	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7730	*/
7731	PVM pVM = pVCpu->CTX_SUFF(pVM);
7732	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7733	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7734	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7735	if (rc == VINF_EM_RAW_GUEST_TRAP)
7736	{
7737	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7738	if (CPUMIsHyperDebugStateActive(pVCpu))
7739	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7740
7741	/* Reflect the exception back to the guest. */
7742	hmR0SvmSetPendingXcptDB(pVCpu);
7743	rc = VINF_SUCCESS;
7744	}
7745
7746	/*
7747	* Update DR6.
7748	*/
7749	if (CPUMIsHyperDebugStateActive(pVCpu))
7750	{
7751	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7752	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7753	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7754	}
7755	else
7756	{
7757	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7758	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7759	}
7760
7761	return rc;
7762	}
7763
7764
7765	/**
7766	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7767	* Conditional \#VMEXIT.
7768	*/
7769	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7770	{
7771	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7772	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7773
7774	SVMEVENT Event;
7775	Event.u = 0;
7776	Event.n.u1Valid = 1;
7777	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7778	Event.n.u8Vector = X86_XCPT_AC;
7779	Event.n.u1ErrorCodeValid = 1;
7780	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7781	return VINF_SUCCESS;
7782	}
7783
7784
7785	/**
7786	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7787	* Conditional \#VMEXIT.
7788	*/
7789	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7790	{
7791	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7792	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7793	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7794
7795	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7796	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7797	if (rc == VINF_EM_RAW_GUEST_TRAP)
7798	{
7799	SVMEVENT Event;
7800	Event.u = 0;
7801	Event.n.u1Valid = 1;
7802	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7803	Event.n.u8Vector = X86_XCPT_BP;
7804	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7805	}
7806
7807	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7808	return rc;
7809	}
7810
7811
7812	/**
7813	* Hacks its way around the lovely mesa driver's backdoor accesses.
7814	*
7815	* @sa hmR0VmxHandleMesaDrvGp
7816	*/
7817	static int hmR0SvmHandleMesaDrvGp(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7818	{
7819	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7820	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7821	RT_NOREF(pCtx, pSvmTransient, pVmcb);
7822
7823	/* For now we'll just skip the instruction. */
7824	hmR0SvmAdvanceRip(pVCpu, 1);
7825	return VINF_SUCCESS;
7826	}
7827
7828
7829	/**
7830	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7831	* backdoor logging w/o checking what it is running inside.
7832	*
7833	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7834	* backdoor port and magic numbers loaded in registers.
7835	*
7836	* @returns true if it is, false if it isn't.
7837	* @sa hmR0VmxIsMesaDrvGp
7838	*/
7839	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPU pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7840	{
7841	/* Check magic and port. */
7842	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7843	/Log(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pCtx->rax : pVmcb->guest.u64RAX, pCtx->rdx));/
7844	if (pCtx->dx != UINT32_C(0x5658))
7845	return false;
7846	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pCtx->rax : pVmcb->guest.u64RAX) != UINT32_C(0x564d5868))
7847	return false;
7848
7849	/* Check that it is #GP(0). */
7850	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7851	return false;
7852
7853	/* Flat ring-3 CS. */
7854	/Log(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%Rx64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.Sel));/
7855	if (pVmcb->guest.u8CPL != 3)
7856	return false;
7857	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.Sel) != 0)
7858	return false;
7859
7860	/* 0xed: IN eAX,dx */
7861	uint64_t const uRip = pCtx->fExtrn & CPUMCTX_EXTRN_RIP ? pCtx->rip : pVmcb->guest.u64RIP;
7862	uint8_t abInstr[1];
7863	if ( hmR0SvmSupportsNextRipSave(pVCpu)
7864	&& pVmcb->ctrl.u64NextRIP - uRip != sizeof(abInstr))
7865	return false;
7866	if (pVmcb->ctrl.cbInstrFetched >= 1)
7867	{
7868	/Log(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7869	if (pVmcb->ctrl.abInstr[0] != 0xed)
7870	return false;
7871	}
7872	else
7873	{
7874	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, uRip, sizeof(abInstr));
7875	/Log(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0]));/
7876	if (RT_FAILURE(rc))
7877	return false;
7878	if (abInstr[0] != 0xed)
7879	return false;
7880	}
7881
7882	return true;
7883	}
7884
7885
7886	/**
7887	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7888	* Conditional \#VMEXIT.
7889	*/
7890	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7891	{
7892	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7893	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7894
7895	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7896	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7897
7898	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7899	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7900	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7901	{
7902	SVMEVENT Event;
7903	Event.u = 0;
7904	Event.n.u1Valid = 1;
7905	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7906	Event.n.u8Vector = X86_XCPT_GP;
7907	Event.n.u1ErrorCodeValid = 1;
7908	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7909	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7910	return VINF_SUCCESS;
7911	}
7912	return hmR0SvmHandleMesaDrvGp(pVCpu, pSvmTransient, pCtx, pVmcb);
7913	}
7914
7915
7916	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7917	/**
7918	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7919	*/
7920	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7921	{
7922	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7923	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7924
7925	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7926	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7927	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7928	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7929	Assert(uVector <= X86_XCPT_LAST);
7930	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7931
7932	SVMEVENT Event;
7933	Event.u = 0;
7934	Event.n.u1Valid = 1;
7935	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7936	Event.n.u8Vector = uVector;
7937	switch (uVector)
7938	{
7939	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7940	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7941	case X86_XCPT_DF:
7942	case X86_XCPT_TS:
7943	case X86_XCPT_NP:
7944	case X86_XCPT_SS:
7945	case X86_XCPT_GP:
7946	case X86_XCPT_AC:
7947	{
7948	Event.n.u1ErrorCodeValid = 1;
7949	Event.n.u32ErrorCode = uErrCode;
7950	break;
7951	}
7952	}
7953
7954	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7955	return VINF_SUCCESS;
7956	}
7957	#endif
7958
7959	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7960	/**
7961	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7962	*/
7963	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7964	{
7965	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7966
7967	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7968	Assert(pVmcb);
7969	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7970
7971	VBOXSTRICTRC rcStrict;
7972	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7973	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7974	if (fSupportsNextRipSave)
7975	{
7976	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7977	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7978	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7979	}
7980	else
7981	{
7982	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7983	rcStrict = IEMExecOne(pVCpu);
7984	}
7985
7986	if (rcStrict == VINF_SUCCESS)
7987	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7988	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7989	{
7990	rcStrict = VINF_SUCCESS;
7991	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7992	}
7993	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7994	return VBOXSTRICTRC_TODO(rcStrict);
7995	}
7996
7997
7998	/**
7999	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
8000	*/
8001	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8002	{
8003	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8004
8005	/*
8006	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
8007	* we only intercept STGI when events are pending for GIF to become 1.
8008	*/
8009	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8010	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
8011	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
8012
8013	VBOXSTRICTRC rcStrict;
8014	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8015	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
8016	if (fSupportsNextRipSave)
8017	{
8018	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
8019	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8020	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
8021	}
8022	else
8023	{
8024	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
8025	rcStrict = IEMExecOne(pVCpu);
8026	}
8027
8028	if (rcStrict == VINF_SUCCESS)
8029	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
8030	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8031	{
8032	rcStrict = VINF_SUCCESS;
8033	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8034	}
8035	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8036	return VBOXSTRICTRC_TODO(rcStrict);
8037	}
8038
8039
8040	/**
8041	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
8042	*/
8043	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8044	{
8045	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8046
8047	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8048	Assert(pVmcb);
8049	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
8050
8051	VBOXSTRICTRC rcStrict;
8052	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8053	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
8054	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
8055	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
8056	if (fSupportsNextRipSave)
8057	{
8058	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
8059	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8060	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
8061	}
8062	else
8063	{
8064	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
8065	rcStrict = IEMExecOne(pVCpu);
8066	}
8067
8068	if (rcStrict == VINF_SUCCESS)
8069	{
8070	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
8071	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
8072	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
8073	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
8074	}
8075	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8076	{
8077	rcStrict = VINF_SUCCESS;
8078	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8079	}
8080	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8081	return VBOXSTRICTRC_TODO(rcStrict);
8082	}
8083
8084
8085	/**
8086	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
8087	*/
8088	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8089	{
8090	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8091
8092	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8093	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
8094
8095	VBOXSTRICTRC rcStrict;
8096	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8097	if (fSupportsNextRipSave)
8098	{
8099	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
8100	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8101	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
8102	}
8103	else
8104	{
8105	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
8106	rcStrict = IEMExecOne(pVCpu);
8107	}
8108
8109	if (rcStrict == VINF_IEM_RAISED_XCPT)
8110	{
8111	rcStrict = VINF_SUCCESS;
8112	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8113	}
8114	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8115	return VBOXSTRICTRC_TODO(rcStrict);
8116	}
8117
8118
8119	/**
8120	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
8121	*/
8122	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8123	{
8124	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8125
8126	VBOXSTRICTRC rcStrict;
8127	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8128	if (fSupportsNextRipSave)
8129	{
8130	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
8131	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8132	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8133	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
8134	}
8135	else
8136	{
8137	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
8138	rcStrict = IEMExecOne(pVCpu);
8139	}
8140
8141	if (rcStrict == VINF_IEM_RAISED_XCPT)
8142	{
8143	rcStrict = VINF_SUCCESS;
8144	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8145	}
8146	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8147	return VBOXSTRICTRC_TODO(rcStrict);
8148	}
8149
8150
8151	/**
8152	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
8153	*/
8154	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8155	{
8156	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8157	/* We shall import the entire state here, just in case we enter and continue execution of
8158	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
8159	could lose lose part of CPU state. */
8160	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
8161
8162	VBOXSTRICTRC rcStrict;
8163	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8164	if (fSupportsNextRipSave)
8165	{
8166	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8167	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8168	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
8169	}
8170	else
8171	{
8172	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
8173	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
8174	instruction itself, see @bugref{7243#c126} */
8175	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
8176	}
8177
8178	if (rcStrict == VINF_SUCCESS)
8179	{
8180	rcStrict = VINF_SVM_VMRUN;
8181	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
8182	}
8183	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8184	{
8185	rcStrict = VINF_SUCCESS;
8186	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8187	}
8188	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8189	return VBOXSTRICTRC_TODO(rcStrict);
8190	}
8191
8192
8193	/**
8194	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
8195	* Unconditional \#VMEXIT.
8196	*/
8197	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8198	{
8199	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8200	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8201
8202	if (pVCpu->hm.s.Event.fPending)
8203	{
8204	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
8205	return VINF_EM_RAW_INJECT_TRPM_EVENT;
8206	}
8207
8208	hmR0SvmSetPendingXcptDB(pVCpu);
8209	return VINF_SUCCESS;
8210	}
8211
8212
8213	/**
8214	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
8215	* Conditional \#VMEXIT.
8216	*/
8217	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8218	{
8219	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8220	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8221
8222	SVMEVENT Event;
8223	Event.u = 0;
8224	Event.n.u1Valid = 1;
8225	Event.n.u3Type = SVM_EVENT_EXCEPTION;
8226	Event.n.u8Vector = X86_XCPT_BP;
8227	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
8228	return VINF_SUCCESS;
8229	}
8230	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
8231
8232	/** @} */
8233

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 75828

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