HMSVMR0.cpp@ 78680

Last change on this file since 78680 was 78483, checked in by vboxsync, 6 years ago
VMM: Nested SVM: bugref:7243 Renamed a couple of functions and doxygen to be more consistent.
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1	/* $Id: HMSVMR0.cpp 78483 2019-05-13 10:52:16Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include <VBox/err.h>
38	#include "HMSVMR0.h"
39	#include "dtrace/VBoxVMM.h"
40
41	#ifdef DEBUG_ramshankar
42	# define HMSVM_SYNC_FULL_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	if ((u64ExitCode) == SVM_EXIT_NPF) \
65	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
66	else \
67	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
68	} while (0)
69	# endif
70	#else
71	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
72	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
73	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
74	# endif
75	#endif /* !VBOX_WITH_STATISTICS */
76
77	/** If we decide to use a function table approach this can be useful to
78	* switch to a "static DECLCALLBACK(int)". */
79	#define HMSVM_EXIT_DECL static int
80
81	/**
82	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
83	* guest using hardware-assisted SVM.
84	*
85	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
86	* are swapped and restored across the world-switch and also registers like
87	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
88	* \#VMEXIT.
89	*/
90	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
91	\| CPUMCTX_EXTRN_RFLAGS \
92	\| CPUMCTX_EXTRN_RAX \
93	\| CPUMCTX_EXTRN_RSP \
94	\| CPUMCTX_EXTRN_SREG_MASK \
95	\| CPUMCTX_EXTRN_CR0 \
96	\| CPUMCTX_EXTRN_CR2 \
97	\| CPUMCTX_EXTRN_CR3 \
98	\| CPUMCTX_EXTRN_TABLE_MASK \
99	\| CPUMCTX_EXTRN_DR6 \
100	\| CPUMCTX_EXTRN_DR7 \
101	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
102	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
103	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
104	\| CPUMCTX_EXTRN_HWVIRT \
105	\| CPUMCTX_EXTRN_HM_SVM_MASK)
106
107	/**
108	* Subset of the guest-CPU state that is shared between the guest and host.
109	*/
110	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
111
112	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
113	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
114	do { \
115	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
116	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
117	} while (0)
118
119	/** Assert that the required state bits are fetched. */
120	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
121	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
122	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
123
124	/** Assert that preemption is disabled or covered by thread-context hooks. */
125	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
126	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
127
128	/** Assert that we haven't migrated CPUs when thread-context hooks are not
129	* used. */
130	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
131	\|\| (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
132	("Illegal migration! Entered on CPU %u Current %u\n", \
133	(a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()));
134
135	/** Assert that we're not executing a nested-guest. */
136	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
137	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
138	#else
139	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
140	#endif
141
142	/** Assert that we're executing a nested-guest. */
143	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
144	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
145	#else
146	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
147	#endif
148
149	/** Macro for checking and returning from the using function for
150	* \#VMEXIT intercepts that maybe caused during delivering of another
151	* event in the guest. */
152	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
153	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
154	do \
155	{ \
156	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
157	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
158	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
159	else if ( rc == VINF_EM_RESET \
160	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
161	{ \
162	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
163	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0)); \
164	} \
165	else \
166	return rc; \
167	} while (0)
168	#else
169	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
170	do \
171	{ \
172	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
173	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
174	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
175	else \
176	return rc; \
177	} while (0)
178	#endif
179
180	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
181	* instruction that exited. */
182	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
183	do { \
184	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
185	(a_rc) = VINF_EM_DBG_STEPPED; \
186	} while (0)
187
188	/** Validate segment descriptor granularity bit. */
189	#ifdef VBOX_STRICT
190	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
191	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
192	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
193	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
194	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
195	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
196	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
197	#else
198	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
199	#endif
200
201	/**
202	* Exception bitmap mask for all contributory exceptions.
203	*
204	* Page fault is deliberately excluded here as it's conditional as to whether
205	* it's contributory or benign. Page faults are handled separately.
206	*/
207	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
208	\| RT_BIT(X86_XCPT_DE))
209
210	/**
211	* Mandatory/unconditional guest control intercepts.
212	*
213	* SMIs can and do happen in normal operation. We need not intercept them
214	* while executing the guest (or nested-guest).
215	*/
216	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
217	\| SVM_CTRL_INTERCEPT_NMI \
218	\| SVM_CTRL_INTERCEPT_INIT \
219	\| SVM_CTRL_INTERCEPT_RDPMC \
220	\| SVM_CTRL_INTERCEPT_CPUID \
221	\| SVM_CTRL_INTERCEPT_RSM \
222	\| SVM_CTRL_INTERCEPT_HLT \
223	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
224	\| SVM_CTRL_INTERCEPT_MSR_PROT \
225	\| SVM_CTRL_INTERCEPT_INVLPGA \
226	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
227	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
228	\| SVM_CTRL_INTERCEPT_VMRUN \
229	\| SVM_CTRL_INTERCEPT_SKINIT \
230	\| SVM_CTRL_INTERCEPT_WBINVD \
231	\| SVM_CTRL_INTERCEPT_MONITOR \
232	\| SVM_CTRL_INTERCEPT_MWAIT \
233	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
234	\| SVM_CTRL_INTERCEPT_XSETBV)
235
236	/** @name VMCB Clean Bits.
237	*
238	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
239	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
240	* memory.
241	*
242	* @{ */
243	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
244	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
245	/** I/O permission bitmap, MSR permission bitmap. */
246	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
247	/** ASID. */
248	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
249	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
250	V_INTR_VECTOR. */
251	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
252	/** Nested Paging: Nested CR3 (nCR3), PAT. */
253	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
254	/** Control registers (CR0, CR3, CR4, EFER). */
255	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
256	/** Debug registers (DR6, DR7). */
257	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
258	/** GDT, IDT limit and base. */
259	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
260	/** Segment register: CS, SS, DS, ES limit and base. */
261	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
262	/** CR2.*/
263	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
264	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
265	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
266	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
267	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
268	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
269	/** Mask of all valid VMCB Clean bits. */
270	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
271	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
272	\| HMSVM_VMCB_CLEAN_ASID \
273	\| HMSVM_VMCB_CLEAN_INT_CTRL \
274	\| HMSVM_VMCB_CLEAN_NP \
275	\| HMSVM_VMCB_CLEAN_CRX_EFER \
276	\| HMSVM_VMCB_CLEAN_DRX \
277	\| HMSVM_VMCB_CLEAN_DT \
278	\| HMSVM_VMCB_CLEAN_SEG \
279	\| HMSVM_VMCB_CLEAN_CR2 \
280	\| HMSVM_VMCB_CLEAN_LBR \
281	\| HMSVM_VMCB_CLEAN_AVIC)
282	/** @} */
283
284	/** @name SVM transient.
285	*
286	* A state structure for holding miscellaneous information across AMD-V
287	* VMRUN/\#VMEXIT operation, restored after the transition.
288	*
289	* @{ */
290	typedef struct SVMTRANSIENT
291	{
292	/** The host's rflags/eflags. */
293	RTCCUINTREG fEFlags;
294	#if HC_ARCH_BITS == 32
295	uint32_t u32Alignment0;
296	#endif
297
298	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
299	uint64_t u64ExitCode;
300	/** The guest's TPR value used for TPR shadowing. */
301	uint8_t u8GuestTpr;
302	/** Alignment. */
303	uint8_t abAlignment0[7];
304
305	/** Pointer to the currently executing VMCB. */
306	PSVMVMCB pVmcb;
307	/** Whether we are currently executing a nested-guest. */
308	bool fIsNestedGuest;
309
310	/** Whether the guest debug state was active at the time of \#VMEXIT. */
311	bool fWasGuestDebugStateActive;
312	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
313	bool fWasHyperDebugStateActive;
314	/** Whether the TSC offset mode needs to be updated. */
315	bool fUpdateTscOffsetting;
316	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
317	bool fRestoreTscAuxMsr;
318	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
319	* contributary exception or a page-fault. */
320	bool fVectoringDoublePF;
321	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
322	* external interrupt or NMI. */
323	bool fVectoringPF;
324	} SVMTRANSIENT, *PSVMTRANSIENT;
325	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
326	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
327	/** @} */
328
329	/**
330	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
331	*/
332	typedef enum SVMMSREXITREAD
333	{
334	/** Reading this MSR causes a \#VMEXIT. */
335	SVMMSREXIT_INTERCEPT_READ = 0xb,
336	/** Reading this MSR does not cause a \#VMEXIT. */
337	SVMMSREXIT_PASSTHRU_READ
338	} SVMMSREXITREAD;
339
340	/**
341	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
342	*/
343	typedef enum SVMMSREXITWRITE
344	{
345	/** Writing to this MSR causes a \#VMEXIT. */
346	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
347	/** Writing to this MSR does not cause a \#VMEXIT. */
348	SVMMSREXIT_PASSTHRU_WRITE
349	} SVMMSREXITWRITE;
350
351	/**
352	* SVM \#VMEXIT handler.
353	*
354	* @returns VBox status code.
355	* @param pVCpu The cross context virtual CPU structure.
356	* @param pSvmTransient Pointer to the SVM-transient structure.
357	*/
358	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
359
360
361	/*********************************************************************************************************************************
362	* Internal Functions *
363	*********************************************************************************************************************************/
364	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
365	static void hmR0SvmLeave(PVMCPU pVCpu, bool fImportState);
366
367
368	/** @name \#VMEXIT handlers.
369	* @{
370	*/
371	static FNSVMEXITHANDLER hmR0SvmExitIntr;
372	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
373	static FNSVMEXITHANDLER hmR0SvmExitInvd;
374	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
375	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
376	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
377	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
378	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
379	static FNSVMEXITHANDLER hmR0SvmExitHlt;
380	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
381	static FNSVMEXITHANDLER hmR0SvmExitMwait;
382	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
383	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
384	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
385	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
386	static FNSVMEXITHANDLER hmR0SvmExitMsr;
387	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
388	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
389	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
390	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
391	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
392	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
393	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
394	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
395	static FNSVMEXITHANDLER hmR0SvmExitPause;
396	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
397	static FNSVMEXITHANDLER hmR0SvmExitIret;
398	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
399	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
400	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
401	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
402	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
403	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
404	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
405	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
406	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
407	#endif
408	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
409	static FNSVMEXITHANDLER hmR0SvmExitClgi;
410	static FNSVMEXITHANDLER hmR0SvmExitStgi;
411	static FNSVMEXITHANDLER hmR0SvmExitVmload;
412	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
413	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
414	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
415	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
416	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
417	#endif
418	/** @} */
419
420	static int hmR0SvmHandleExit(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
421	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
422	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
423	#endif
424
425
426	/*********************************************************************************************************************************
427	* Global Variables *
428	*********************************************************************************************************************************/
429	/** Ring-0 memory object for the IO bitmap. */
430	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
431	/** Physical address of the IO bitmap. */
432	static RTHCPHYS g_HCPhysIOBitmap;
433	/** Pointer to the IO bitmap. */
434	static R0PTRTYPE(void *) g_pvIOBitmap;
435
436	#ifdef VBOX_STRICT
437	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
438	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
439	# define HMSVM_LOG_CS RT_BIT_32(2)
440	# define HMSVM_LOG_SS RT_BIT_32(3)
441	# define HMSVM_LOG_FS RT_BIT_32(4)
442	# define HMSVM_LOG_GS RT_BIT_32(5)
443	# define HMSVM_LOG_LBR RT_BIT_32(6)
444	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
445	\| HMSVM_LOG_CR_REGS \
446	\| HMSVM_LOG_CS \
447	\| HMSVM_LOG_SS \
448	\| HMSVM_LOG_FS \
449	\| HMSVM_LOG_GS \
450	\| HMSVM_LOG_LBR)
451
452	/**
453	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
454	*
455	* @param pVCpu The cross context virtual CPU structure.
456	* @param pVmcb Pointer to the VM control block.
457	* @param pszPrefix Log prefix.
458	* @param fFlags Log flags, see HMSVM_LOG_XXX.
459	* @param uVerbose The verbosity level, currently unused.
460	*/
461	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
462	{
463	RT_NOREF2(pVCpu, uVerbose);
464	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
465
466	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
467	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
468
469	if (fFlags & HMSVM_LOG_RBP_RSP)
470	{
471	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
472	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
473	}
474
475	if (fFlags & HMSVM_LOG_CR_REGS)
476	{
477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
478	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
479	}
480
481	if (fFlags & HMSVM_LOG_CS)
482	{
483	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
484	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
485	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
486	}
487	if (fFlags & HMSVM_LOG_SS)
488	{
489	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
490	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
491	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
492	}
493	if (fFlags & HMSVM_LOG_FS)
494	{
495	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
496	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
497	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
498	}
499	if (fFlags & HMSVM_LOG_GS)
500	{
501	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
502	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
503	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
504	}
505
506	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
507	if (fFlags & HMSVM_LOG_LBR)
508	{
509	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
510	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
511	}
512	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
513	}
514	#endif /* VBOX_STRICT */
515
516
517	/**
518	* Sets up and activates AMD-V on the current CPU.
519	*
520	* @returns VBox status code.
521	* @param pHostCpu The HM physical-CPU structure.
522	* @param pVM The cross context VM structure. Can be
523	* NULL after a resume!
524	* @param pvCpuPage Pointer to the global CPU page.
525	* @param HCPhysCpuPage Physical address of the global CPU page.
526	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
527	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
528	* unused).
529	*/
530	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
531	PCSUPHWVIRTMSRS pHwvirtMsrs)
532	{
533	Assert(!fEnabledByHost);
534	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
535	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
536	Assert(pvCpuPage); NOREF(pvCpuPage);
537	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
538
539	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
540
541	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
542	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
543
544	/*
545	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
546	*/
547	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
548	if (u64HostEfer & MSR_K6_EFER_SVME)
549	{
550	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
551	if ( pVM
552	&& pVM->hm.s.svm.fIgnoreInUseError)
553	pHostCpu->fIgnoreAMDVInUseError = true;
554
555	if (!pHostCpu->fIgnoreAMDVInUseError)
556	{
557	ASMSetFlags(fEFlags);
558	return VERR_SVM_IN_USE;
559	}
560	}
561
562	/* Turn on AMD-V in the EFER MSR. */
563	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
564
565	/* Write the physical page address where the CPU will store the host state while executing the VM. */
566	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
567
568	/* Restore interrupts. */
569	ASMSetFlags(fEFlags);
570
571	/*
572	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
573	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
574	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
575	* entirely with before executing any guest code.
576	*/
577	pHostCpu->fFlushAsidBeforeUse = true;
578
579	/*
580	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
581	*/
582	++pHostCpu->cTlbFlushes;
583
584	return VINF_SUCCESS;
585	}
586
587
588	/**
589	* Deactivates AMD-V on the current CPU.
590	*
591	* @returns VBox status code.
592	* @param pvCpuPage Pointer to the global CPU page.
593	* @param HCPhysCpuPage Physical address of the global CPU page.
594	*/
595	VMMR0DECL(int) SVMR0DisableCpu(void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
596	{
597	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
598	AssertReturn( HCPhysCpuPage
599	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
600	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
601
602	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
603	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
604
605	/* Turn off AMD-V in the EFER MSR. */
606	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
607	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
608
609	/* Invalidate host state physical address. */
610	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
611
612	/* Restore interrupts. */
613	ASMSetFlags(fEFlags);
614
615	return VINF_SUCCESS;
616	}
617
618
619	/**
620	* Does global AMD-V initialization (called during module initialization).
621	*
622	* @returns VBox status code.
623	*/
624	VMMR0DECL(int) SVMR0GlobalInit(void)
625	{
626	/*
627	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
628	* intercept all IO accesses, it's done once globally here instead of per-VM.
629	*/
630	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
631	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
632	if (RT_FAILURE(rc))
633	return rc;
634
635	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
636	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
637
638	/* Set all bits to intercept all IO accesses. */
639	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
640
641	return VINF_SUCCESS;
642	}
643
644
645	/**
646	* Does global AMD-V termination (called during module termination).
647	*/
648	VMMR0DECL(void) SVMR0GlobalTerm(void)
649	{
650	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
651	{
652	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
653	g_pvIOBitmap = NULL;
654	g_HCPhysIOBitmap = 0;
655	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
656	}
657	}
658
659
660	/**
661	* Frees any allocated per-VCPU structures for a VM.
662	*
663	* @param pVM The cross context VM structure.
664	*/
665	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
666	{
667	for (uint32_t i = 0; i < pVM->cCpus; i++)
668	{
669	PVMCPU pVCpu = &pVM->aCpus[i];
670	AssertPtr(pVCpu);
671
672	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
673	{
674	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
675	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
676	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
677	}
678
679	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
680	{
681	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
682	pVCpu->hm.s.svm.pVmcb = NULL;
683	pVCpu->hm.s.svm.HCPhysVmcb = 0;
684	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
685	}
686
687	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
688	{
689	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
690	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
691	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
692	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
693	}
694	}
695	}
696
697
698	/**
699	* Does per-VM AMD-V initialization.
700	*
701	* @returns VBox status code.
702	* @param pVM The cross context VM structure.
703	*/
704	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
705	{
706	int rc = VERR_INTERNAL_ERROR_5;
707
708	/*
709	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
710	*/
711	uint32_t u32Family;
712	uint32_t u32Model;
713	uint32_t u32Stepping;
714	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
715	{
716	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
717	pVM->hm.s.svm.fAlwaysFlushTLB = true;
718	}
719
720	/*
721	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
722	*/
723	for (VMCPUID i = 0; i < pVM->cCpus; i++)
724	{
725	PVMCPU pVCpu = &pVM->aCpus[i];
726	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
727	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
728	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
729	}
730
731	for (VMCPUID i = 0; i < pVM->cCpus; i++)
732	{
733	PVMCPU pVCpu = &pVM->aCpus[i];
734
735	/*
736	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
737	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
738	*/
739	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
740	if (RT_FAILURE(rc))
741	goto failure_cleanup;
742
743	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
744	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
745	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
746	ASMMemZeroPage(pvVmcbHost);
747
748	/*
749	* Allocate one page for the guest-state VMCB.
750	*/
751	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
752	if (RT_FAILURE(rc))
753	goto failure_cleanup;
754
755	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
756	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
757	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
758	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
759
760	/*
761	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
762	* SVM to not require one.
763	*/
764	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
765	false /* fExecutable */);
766	if (RT_FAILURE(rc))
767	goto failure_cleanup;
768
769	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
770	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
771	/* Set all bits to intercept all MSR accesses (changed later on). */
772	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
773	}
774
775	return VINF_SUCCESS;
776
777	failure_cleanup:
778	hmR0SvmFreeStructs(pVM);
779	return rc;
780	}
781
782
783	/**
784	* Does per-VM AMD-V termination.
785	*
786	* @returns VBox status code.
787	* @param pVM The cross context VM structure.
788	*/
789	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
790	{
791	hmR0SvmFreeStructs(pVM);
792	return VINF_SUCCESS;
793	}
794
795
796	/**
797	* Returns whether the VMCB Clean Bits feature is supported.
798	*
799	* @return @c true if supported, @c false otherwise.
800	* @param pVCpu The cross context virtual CPU structure.
801	*/
802	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu)
803	{
804	PVM pVM = pVCpu->CTX_SUFF(pVM);
805	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
806	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
807	{
808	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
809	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
810	}
811	#endif
812	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
813	}
814
815
816	/**
817	* Returns whether the decode assists feature is supported.
818	*
819	* @return @c true if supported, @c false otherwise.
820	* @param pVCpu The cross context virtual CPU structure.
821	*/
822	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu)
823	{
824	PVM pVM = pVCpu->CTX_SUFF(pVM);
825	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
826	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
827	{
828	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
829	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
830	}
831	#endif
832	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
833	}
834
835
836	/**
837	* Returns whether the NRIP_SAVE feature is supported.
838	*
839	* @return @c true if supported, @c false otherwise.
840	* @param pVCpu The cross context virtual CPU structure.
841	*/
842	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu)
843	{
844	PVM pVM = pVCpu->CTX_SUFF(pVM);
845	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
846	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
847	{
848	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
849	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
850	}
851	#endif
852	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
853	}
854
855
856	/**
857	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
858	*
859	* @param pVCpu The cross context virtual CPU structure.
860	* @param pbMsrBitmap Pointer to the MSR bitmap.
861	* @param idMsr The MSR for which the permissions are being set.
862	* @param enmRead MSR read permissions.
863	* @param enmWrite MSR write permissions.
864	*
865	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
866	* caller needs to take care of this.
867	*/
868	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
869	SVMMSREXITWRITE enmWrite)
870	{
871	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
872	uint16_t offMsrpm;
873	uint8_t uMsrpmBit;
874	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
875	AssertRC(rc);
876
877	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
878	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
879
880	pbMsrBitmap += offMsrpm;
881	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
882	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
883	else
884	{
885	if (!fInNestedGuestMode)
886	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
887	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
888	else
889	{
890	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
891	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
892	pbNstGstMsrBitmap += offMsrpm;
893	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
894	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
895	else
896	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
897	}
898	#endif
899	}
900
901	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
902	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
903	else
904	{
905	if (!fInNestedGuestMode)
906	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
907	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
908	else
909	{
910	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
911	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
912	pbNstGstMsrBitmap += offMsrpm;
913	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
914	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
915	else
916	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
917	}
918	#endif
919	}
920	}
921
922
923	/**
924	* Sets up AMD-V for the specified VM.
925	* This function is only called once per-VM during initalization.
926	*
927	* @returns VBox status code.
928	* @param pVM The cross context VM structure.
929	*/
930	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
931	{
932	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
933	AssertReturn(pVM, VERR_INVALID_PARAMETER);
934	Assert(pVM->hm.s.svm.fSupported);
935
936	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
937	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
938	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
939
940	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
941	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
942
943	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
944	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
945	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
946
947	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
948	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
949	#endif
950
951	PVMCPU pVCpu = &pVM->aCpus[0];
952	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
953	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[0]\n"), VERR_SVM_INVALID_PVMCB);
954	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
955
956	/* Always trap #AC for reasons of security. */
957	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
958
959	/* Always trap #DB for reasons of security. */
960	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
961
962	/* Trap exceptions unconditionally (debug purposes). */
963	#ifdef HMSVM_ALWAYS_TRAP_PF
964	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
965	#endif
966	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
967	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
968	pVmcbCtrl->u32InterceptXcpt \|= 0
969	\| RT_BIT(X86_XCPT_BP)
970	\| RT_BIT(X86_XCPT_DE)
971	\| RT_BIT(X86_XCPT_NM)
972	\| RT_BIT(X86_XCPT_UD)
973	\| RT_BIT(X86_XCPT_NP)
974	\| RT_BIT(X86_XCPT_SS)
975	\| RT_BIT(X86_XCPT_GP)
976	\| RT_BIT(X86_XCPT_PF)
977	\| RT_BIT(X86_XCPT_MF)
978	;
979	#endif
980
981	/* Apply the exceptions intercepts needed by the GIM provider. */
982	if (pVCpu->hm.s.fGIMTrapXcptUD)
983	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
984
985	/* The mesa 3d driver hack needs #GP. */
986	if (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv)
987	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
988
989	/* Set up unconditional intercepts and conditions. */
990	pVmcbCtrl->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
991	\| SVM_CTRL_INTERCEPT_VMMCALL;
992
993	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
994	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
995	#endif
996
997	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
998	/* Virtualized VMSAVE/VMLOAD. */
999	pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
1000	if (!fUseVirtVmsaveVmload)
1001	{
1002	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
1003	\| SVM_CTRL_INTERCEPT_VMLOAD;
1004	}
1005
1006	/* Virtual GIF. */
1007	pVmcbCtrl->IntCtrl.n.u1VGifEnable = fUseVGif;
1008	if (!fUseVGif)
1009	{
1010	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
1011	\| SVM_CTRL_INTERCEPT_STGI;
1012	}
1013	#endif
1014
1015	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1016	pVmcbCtrl->u16InterceptWrCRx = RT_BIT(4);
1017
1018	/* Intercept all DRx reads and writes by default. Changed later on. */
1019	pVmcbCtrl->u16InterceptRdDRx = 0xffff;
1020	pVmcbCtrl->u16InterceptWrDRx = 0xffff;
1021
1022	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1023	pVmcbCtrl->IntCtrl.n.u1VIntrMasking = 1;
1024
1025	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1026	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1027	pVmcbCtrl->IntCtrl.n.u1IgnoreTPR = 1;
1028
1029	/* Set the IO permission bitmap physical addresses. */
1030	pVmcbCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1031
1032	/* LBR virtualization. */
1033	pVmcbCtrl->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1034
1035	/* The host ASID MBZ, for the guest start with 1. */
1036	pVmcbCtrl->TLBCtrl.n.u32ASID = 1;
1037
1038	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1039	pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1040
1041	/* Without Nested Paging, we need additionally intercepts. */
1042	if (!pVM->hm.s.fNestedPaging)
1043	{
1044	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1045	pVmcbCtrl->u16InterceptRdCRx \|= RT_BIT(3);
1046	pVmcbCtrl->u16InterceptWrCRx \|= RT_BIT(3);
1047
1048	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1049	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1050	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1051
1052	/* Page faults must be intercepted to implement shadow paging. */
1053	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1054	}
1055
1056	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1057	if (fUsePauseFilter)
1058	{
1059	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1060	pVmcbCtrl->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1061	if (fPauseFilterThreshold)
1062	pVmcbCtrl->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1063	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1064	}
1065
1066	/*
1067	* Setup the MSR permission bitmap.
1068	* The following MSRs are saved/restored automatically during the world-switch.
1069	* Don't intercept guest read/write accesses to these MSRs.
1070	*/
1071	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1072	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1073	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1074	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1075	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1076	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1077	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1078	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1079	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1080	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1081	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1082	pVmcbCtrl->u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
1083
1084	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1085	Assert(pVmcbCtrl->u32VmcbCleanBits == 0);
1086
1087	for (VMCPUID i = 1; i < pVM->cCpus; i++)
1088	{
1089	PVMCPU pVCpuCur = &pVM->aCpus[i];
1090	PSVMVMCB pVmcbCur = pVM->aCpus[i].hm.s.svm.pVmcb;
1091	AssertMsgReturn(pVmcbCur, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
1092	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1093
1094	/* Copy the VMCB control area. */
1095	memcpy(pVmcbCtrlCur, pVmcbCtrl, sizeof(*pVmcbCtrlCur));
1096
1097	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1098	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hm.s.svm.pvMsrBitmap;
1099	memcpy(pbMsrBitmapCur, pbMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1100	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
1101
1102	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1103	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1104
1105	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1106	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu->hm.s.fGIMTrapXcptUD);
1107	}
1108
1109	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1110	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1111	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1112	#else
1113	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1114	#endif
1115	return VINF_SUCCESS;
1116	}
1117
1118
1119	/**
1120	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1121	*
1122	* @returns Pointer to the current context VMCB.
1123	* @param pVCpu The cross context virtual CPU structure.
1124	*/
1125	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu)
1126	{
1127	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1128	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1129	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1130	#endif
1131	return pVCpu->hm.s.svm.pVmcb;
1132	}
1133
1134
1135	/**
1136	* Gets a pointer to the nested-guest VMCB cache.
1137	*
1138	* @returns Pointer to the nested-guest VMCB cache.
1139	* @param pVCpu The cross context virtual CPU structure.
1140	*/
1141	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPU pVCpu)
1142	{
1143	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1144	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1145	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1146	#else
1147	RT_NOREF(pVCpu);
1148	return NULL;
1149	#endif
1150	}
1151
1152
1153	/**
1154	* Invalidates a guest page by guest virtual address.
1155	*
1156	* @returns VBox status code.
1157	* @param pVCpu The cross context virtual CPU structure.
1158	* @param GCVirt Guest virtual address of the page to invalidate.
1159	*/
1160	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1161	{
1162	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1163
1164	bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1165
1166	/* Skip it if a TLB flush is already pending. */
1167	if (!fFlushPending)
1168	{
1169	Log4Func(("%#RGv\n", GCVirt));
1170
1171	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1172	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1173
1174	#if HC_ARCH_BITS == 32
1175	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1176	if (CPUMIsGuestInLongMode(pVCpu))
1177	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1178	else
1179	#endif
1180	{
1181	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1182	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1183	}
1184	}
1185	return VINF_SUCCESS;
1186	}
1187
1188
1189	/**
1190	* Flushes the appropriate tagged-TLB entries.
1191	*
1192	* @param pHostCpu The HM physical-CPU structure.
1193	* @param pVCpu The cross context virtual CPU structure.
1194	* @param pVmcb Pointer to the VM control block.
1195	*/
1196	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPU pVCpu, PSVMVMCB pVmcb)
1197	{
1198	/*
1199	* Force a TLB flush for the first world switch if the current CPU differs from the one
1200	* we ran on last. This can happen both for start & resume due to long jumps back to
1201	* ring-3.
1202	*
1203	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1204	* correlation between it and the physical CPU.
1205	*
1206	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1207	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1208	*/
1209	bool fNewAsid = false;
1210	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1211	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1212	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1213	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1214	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1215	#endif
1216	)
1217	{
1218	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1219	pVCpu->hm.s.fForceTLBFlush = true;
1220	fNewAsid = true;
1221	}
1222
1223	/* Set TLB flush state as checked until we return from the world switch. */
1224	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1225
1226	/* Check for explicit TLB flushes. */
1227	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1228	{
1229	pVCpu->hm.s.fForceTLBFlush = true;
1230	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1231	}
1232
1233	/*
1234	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1235	* This Host CPU requirement takes precedence.
1236	*/
1237	PVM pVM = pVCpu->CTX_SUFF(pVM);
1238	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1239	{
1240	pHostCpu->uCurrentAsid = 1;
1241	pVCpu->hm.s.uCurrentAsid = 1;
1242	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1243	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1244	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1245
1246	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1247	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1248	}
1249	else
1250	{
1251	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1252	if (pVCpu->hm.s.fForceTLBFlush)
1253	{
1254	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1255	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1256
1257	if (fNewAsid)
1258	{
1259	++pHostCpu->uCurrentAsid;
1260
1261	bool fHitASIDLimit = false;
1262	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1263	{
1264	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1265	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1266	fHitASIDLimit = true;
1267	}
1268
1269	if ( fHitASIDLimit
1270	\|\| pHostCpu->fFlushAsidBeforeUse)
1271	{
1272	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1273	pHostCpu->fFlushAsidBeforeUse = false;
1274	}
1275
1276	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1277	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1278	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1279	}
1280	else
1281	{
1282	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1283	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1284	else
1285	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1286	}
1287
1288	pVCpu->hm.s.fForceTLBFlush = false;
1289	}
1290	}
1291
1292	/* Update VMCB with the ASID. */
1293	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1294	{
1295	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1296	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1297	}
1298
1299	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1300	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1301	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1302	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1303	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1304	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1305	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1306	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1307
1308	#ifdef VBOX_WITH_STATISTICS
1309	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1310	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1311	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1312	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1313	{
1314	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1315	}
1316	else
1317	{
1318	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1319	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1320	}
1321	#endif
1322	}
1323
1324
1325	/** @name 64-bit guest on 32-bit host OS helper functions.
1326	*
1327	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1328	* mode (code segment, paging). These wrappers/helpers perform the necessary
1329	* bits for the 32->64 switcher.
1330	*
1331	* @{ */
1332	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1333	/**
1334	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1335	*
1336	* @returns VBox status code.
1337	* @param HCPhysVmcbHost Physical address of host VMCB.
1338	* @param HCPhysVmcb Physical address of the VMCB.
1339	* @param pCtx Pointer to the guest-CPU context.
1340	* @param pVM The cross context VM structure.
1341	* @param pVCpu The cross context virtual CPU structure.
1342	*/
1343	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1344	{
1345	RT_NOREF2(pVM, pCtx);
1346	uint32_t aParam[8];
1347	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1348	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1349	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1350	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1351	aParam[4] = VM_RC_ADDR(pVM, pVM);
1352	aParam[5] = 0;
1353	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1354	aParam[7] = 0;
1355
1356	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1357	}
1358
1359
1360	/**
1361	* Executes the specified VMRUN handler in 64-bit mode.
1362	*
1363	* @returns VBox status code.
1364	* @param pVCpu The cross context virtual CPU structure.
1365	* @param enmOp The operation to perform.
1366	* @param cParams Number of parameters.
1367	* @param paParam Array of 32-bit parameters.
1368	*/
1369	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
1370	{
1371	PVM pVM = pVCpu->CTX_SUFF(pVM);
1372	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1373	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1374
1375	/* Disable interrupts. */
1376	RTHCUINTREG const fEFlags = ASMIntDisableFlags();
1377
1378	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1379	RTCPUID idHostCpu = RTMpCpuId();
1380	CPUMR0SetLApic(pVCpu, idHostCpu);
1381	#endif
1382
1383	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1384	CPUMSetHyperEIP(pVCpu, enmOp);
1385	for (int i = (int)cParams - 1; i >= 0; i--)
1386	CPUMPushHyper(pVCpu, paParam[i]);
1387
1388	/* Call the switcher. */
1389	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1390	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
1391	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1392
1393	/* Restore interrupts. */
1394	ASMSetFlags(fEFlags);
1395	return rc;
1396	}
1397
1398	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1399	/** @} */
1400
1401
1402	/**
1403	* Sets an exception intercept in the specified VMCB.
1404	*
1405	* @param pVmcb Pointer to the VM control block.
1406	* @param uXcpt The exception (X86_XCPT_*).
1407	*/
1408	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1409	{
1410	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1411	{
1412	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1413	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1414	}
1415	}
1416
1417
1418	/**
1419	* Clears an exception intercept in the specified VMCB.
1420	*
1421	* @param pVCpu The cross context virtual CPU structure.
1422	* @param pVmcb Pointer to the VM control block.
1423	* @param uXcpt The exception (X86_XCPT_*).
1424	*
1425	* @remarks This takes into account if we're executing a nested-guest and only
1426	* removes the exception intercept if both the guest -and- nested-guest
1427	* are not intercepting it.
1428	*/
1429	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPU pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1430	{
1431	Assert(uXcpt != X86_XCPT_DB);
1432	Assert(uXcpt != X86_XCPT_AC);
1433	Assert(uXcpt != X86_XCPT_GP);
1434	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1435	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1436	{
1437	bool fRemove = true;
1438	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1439	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1440	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1441	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1442	{
1443	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1444	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1445	}
1446	# else
1447	RT_NOREF(pVCpu);
1448	# endif
1449	if (fRemove)
1450	{
1451	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1452	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1453	}
1454	}
1455	#else
1456	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1457	#endif
1458	}
1459
1460
1461	/**
1462	* Sets a control intercept in the specified VMCB.
1463	*
1464	* @param pVmcb Pointer to the VM control block.
1465	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1466	*/
1467	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1468	{
1469	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1470	{
1471	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1472	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1473	}
1474	}
1475
1476
1477	/**
1478	* Clears a control intercept in the specified VMCB.
1479	*
1480	* @returns @c true if the intercept is still set, @c false otherwise.
1481	* @param pVCpu The cross context virtual CPU structure.
1482	* @param pVmcb Pointer to the VM control block.
1483	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1484	*
1485	* @remarks This takes into account if we're executing a nested-guest and only
1486	* removes the control intercept if both the guest -and- nested-guest
1487	* are not intercepting it.
1488	*/
1489	static bool hmR0SvmClearCtrlIntercept(PVMCPU pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1490	{
1491	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1492	{
1493	bool fRemove = true;
1494	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1495	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1496	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1497	{
1498	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1499	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1500	}
1501	#else
1502	RT_NOREF(pVCpu);
1503	#endif
1504	if (fRemove)
1505	{
1506	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1507	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1508	}
1509	}
1510
1511	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1512	}
1513
1514
1515	/**
1516	* Exports the guest (or nested-guest) CR0 into the VMCB.
1517	*
1518	* @param pVCpu The cross context virtual CPU structure.
1519	* @param pVmcb Pointer to the VM control block.
1520	*
1521	* @remarks This assumes we always pre-load the guest FPU.
1522	* @remarks No-long-jump zone!!!
1523	*/
1524	static void hmR0SvmExportGuestCR0(PVMCPU pVCpu, PSVMVMCB pVmcb)
1525	{
1526	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1527
1528	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1529	uint64_t const uGuestCr0 = pCtx->cr0;
1530	uint64_t uShadowCr0 = uGuestCr0;
1531
1532	/* Always enable caching. */
1533	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1534
1535	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1536	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1537	{
1538	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1539	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1540	}
1541
1542	/*
1543	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1544	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1545	* see @bugref{7243#c103}.
1546	*/
1547	if (!(uGuestCr0 & X86_CR0_NE))
1548	{
1549	uShadowCr0 \|= X86_CR0_NE;
1550	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1551	}
1552	else
1553	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1554
1555	/*
1556	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1557	*
1558	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1559	* see @bugref{6944}.
1560	*
1561	* We also don't ever want to honor weird things like cache disable from the guest.
1562	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1563	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1564	*/
1565	if (uShadowCr0 == uGuestCr0)
1566	{
1567	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1568	{
1569	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1570	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1571	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1572	}
1573	else
1574	{
1575	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1576	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1577	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1578	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1579	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1580	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1581	}
1582	}
1583	else
1584	{
1585	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1586	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1587	}
1588	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1589
1590	Assert(!RT_HI_U32(uShadowCr0));
1591	if (pVmcb->guest.u64CR0 != uShadowCr0)
1592	{
1593	pVmcb->guest.u64CR0 = uShadowCr0;
1594	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1595	}
1596	}
1597
1598
1599	/**
1600	* Exports the guest (or nested-guest) CR3 into the VMCB.
1601	*
1602	* @param pVCpu The cross context virtual CPU structure.
1603	* @param pVmcb Pointer to the VM control block.
1604	*
1605	* @remarks No-long-jump zone!!!
1606	*/
1607	static void hmR0SvmExportGuestCR3(PVMCPU pVCpu, PSVMVMCB pVmcb)
1608	{
1609	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1610
1611	PVM pVM = pVCpu->CTX_SUFF(pVM);
1612	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1613	if (pVM->hm.s.fNestedPaging)
1614	{
1615	PGMMODE enmShwPagingMode;
1616	#if HC_ARCH_BITS == 32
1617	if (CPUMIsGuestInLongModeEx(pCtx))
1618	enmShwPagingMode = PGMMODE_AMD64_NX;
1619	else
1620	#endif
1621	enmShwPagingMode = PGMGetHostMode(pVM);
1622
1623	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1624	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1625	pVmcb->guest.u64CR3 = pCtx->cr3;
1626	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1627	}
1628	else
1629	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1630
1631	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1632	}
1633
1634
1635	/**
1636	* Exports the guest (or nested-guest) CR4 into the VMCB.
1637	*
1638	* @param pVCpu The cross context virtual CPU structure.
1639	* @param pVmcb Pointer to the VM control block.
1640	*
1641	* @remarks No-long-jump zone!!!
1642	*/
1643	static int hmR0SvmExportGuestCR4(PVMCPU pVCpu, PSVMVMCB pVmcb)
1644	{
1645	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1646
1647	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1648	uint64_t uShadowCr4 = pCtx->cr4;
1649	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1650	{
1651	switch (pVCpu->hm.s.enmShadowMode)
1652	{
1653	case PGMMODE_REAL:
1654	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1655	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1656
1657	case PGMMODE_32_BIT: /* 32-bit paging. */
1658	uShadowCr4 &= ~X86_CR4_PAE;
1659	break;
1660
1661	case PGMMODE_PAE: /* PAE paging. */
1662	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1663	/** Must use PAE paging as we could use physical memory > 4 GB */
1664	uShadowCr4 \|= X86_CR4_PAE;
1665	break;
1666
1667	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1668	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1669	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1670	break;
1671	#else
1672	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1673	#endif
1674
1675	default: /* shut up gcc */
1676	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1677	}
1678	}
1679
1680	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1681	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1682
1683	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1684	if (uShadowCr4 == pCtx->cr4)
1685	{
1686	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1687	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1688	else
1689	{
1690	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1691	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1692	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1693	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1694	}
1695	}
1696	else
1697	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1698
1699	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1700	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1701
1702	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1703	Assert(!RT_HI_U32(uShadowCr4));
1704	pVmcb->guest.u64CR4 = uShadowCr4;
1705	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1706
1707	return VINF_SUCCESS;
1708	}
1709
1710
1711	/**
1712	* Exports the guest (or nested-guest) control registers into the VMCB.
1713	*
1714	* @returns VBox status code.
1715	* @param pVCpu The cross context virtual CPU structure.
1716	* @param pVmcb Pointer to the VM control block.
1717	*
1718	* @remarks No-long-jump zone!!!
1719	*/
1720	static int hmR0SvmExportGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1721	{
1722	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1723
1724	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1725	{
1726	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1727	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1728
1729	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1730	{
1731	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1732	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1733	}
1734
1735	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1736	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1737
1738	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1739	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1740	{
1741	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1742	if (RT_FAILURE(rc))
1743	return rc;
1744	}
1745
1746	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1747	}
1748	return VINF_SUCCESS;
1749	}
1750
1751
1752	/**
1753	* Exports the guest (or nested-guest) segment registers into the VMCB.
1754	*
1755	* @returns VBox status code.
1756	* @param pVCpu The cross context virtual CPU structure.
1757	* @param pVmcb Pointer to the VM control block.
1758	*
1759	* @remarks No-long-jump zone!!!
1760	*/
1761	static void hmR0SvmExportGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1762	{
1763	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1764	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1765
1766	/* Guest segment registers. */
1767	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1768	{
1769	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1770	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1771
1772	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1773	{
1774	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1775	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1776	}
1777
1778	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1779	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1780
1781	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1782	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1783
1784	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1785	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1786
1787	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1788	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1789
1790	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1791	}
1792
1793	/* Guest TR. */
1794	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1795	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1796
1797	/* Guest LDTR. */
1798	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1799	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1800
1801	/* Guest GDTR. */
1802	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1803	{
1804	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1805	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1806	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1807	}
1808
1809	/* Guest IDTR. */
1810	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1811	{
1812	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1813	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1814	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1815	}
1816
1817	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1818	\| HM_CHANGED_GUEST_TABLE_MASK);
1819	}
1820
1821
1822	/**
1823	* Exports the guest (or nested-guest) MSRs into the VMCB.
1824	*
1825	* @param pVCpu The cross context virtual CPU structure.
1826	* @param pVmcb Pointer to the VM control block.
1827	*
1828	* @remarks No-long-jump zone!!!
1829	*/
1830	static void hmR0SvmExportGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1831	{
1832	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1833	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1834
1835	/* Guest Sysenter MSRs. */
1836	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1837	{
1838	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1839	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1840
1841	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1842	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1843
1844	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1845	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1846	}
1847
1848	/*
1849	* Guest EFER MSR.
1850	* AMD-V requires guest EFER.SVME to be set. Weird.
1851	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1852	*/
1853	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1854	{
1855	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1856	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1857	}
1858
1859	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1860	if ( !CPUMIsGuestInLongModeEx(pCtx)
1861	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1862	{
1863	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1864	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1865	}
1866
1867	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1868	{
1869	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1870	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1871	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1872	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1873	}
1874
1875	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1876	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1877
1878	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1879	\| HM_CHANGED_GUEST_EFER_MSR
1880	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1881	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1882
1883	/*
1884	* Setup the PAT MSR (applicable for Nested Paging only).
1885	*
1886	* While guests can modify and see the modified values through the shadow values,
1887	* we shall not honor any guest modifications of this MSR to ensure caching is always
1888	* enabled similar to how we clear CR0.CD and NW bits.
1889	*
1890	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1891	*/
1892	pVmcb->guest.u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
1893
1894	/* Enable the last branch record bit if LBR virtualization is enabled. */
1895	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1896	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1897	}
1898
1899
1900	/**
1901	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1902	* the necessary intercepts accordingly.
1903	*
1904	* @param pVCpu The cross context virtual CPU structure.
1905	* @param pVmcb Pointer to the VM control block.
1906	*
1907	* @remarks No-long-jump zone!!!
1908	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1909	*/
1910	static void hmR0SvmExportSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb)
1911	{
1912	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1913
1914	/*
1915	* Anyone single stepping on the host side? If so, we'll have to use the
1916	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1917	* the VMM level like the VT-x implementations does.
1918	*/
1919	bool fInterceptMovDRx = false;
1920	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1921	if (fStepping)
1922	{
1923	pVCpu->hm.s.fClearTrapFlag = true;
1924	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1925	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1926	}
1927
1928	if ( fStepping
1929	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1930	{
1931	/*
1932	* Use the combined guest and host DRx values found in the hypervisor
1933	* register set because the debugger has breakpoints active or someone
1934	* is single stepping on the host side.
1935	*
1936	* Note! DBGF expects a clean DR6 state before executing guest code.
1937	*/
1938	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1939	if ( CPUMIsGuestInLongModeEx(pCtx)
1940	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1941	{
1942	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1943	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1944	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1945	}
1946	else
1947	#endif
1948	if (!CPUMIsHyperDebugStateActive(pVCpu))
1949	{
1950	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1951	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1952	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1953	}
1954
1955	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1956	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1957	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1958	{
1959	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1960	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1961	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1962	}
1963
1964	/** @todo If we cared, we could optimize to allow the guest to read registers
1965	* with the same values. */
1966	fInterceptMovDRx = true;
1967	pVCpu->hm.s.fUsingHyperDR7 = true;
1968	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1969	}
1970	else
1971	{
1972	/*
1973	* Update DR6, DR7 with the guest values if necessary.
1974	*/
1975	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1976	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1977	{
1978	pVmcb->guest.u64DR7 = pCtx->dr[7];
1979	pVmcb->guest.u64DR6 = pCtx->dr[6];
1980	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1981	}
1982	pVCpu->hm.s.fUsingHyperDR7 = false;
1983
1984	/*
1985	* If the guest has enabled debug registers, we need to load them prior to
1986	* executing guest code so they'll trigger at the right time.
1987	*/
1988	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1989	{
1990	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1991	if ( CPUMIsGuestInLongModeEx(pCtx)
1992	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1993	{
1994	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1995	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1996	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1997	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1998	}
1999	else
2000	#endif
2001	if (!CPUMIsGuestDebugStateActive(pVCpu))
2002	{
2003	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
2004	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
2005	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2006	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2007	}
2008	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
2009	}
2010	/*
2011	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
2012	* intercept #DB as DR6 is updated in the VMCB.
2013	*
2014	* Note! If we cared and dared, we could skip intercepting \#DB here.
2015	* However, \#DB shouldn't be performance critical, so we'll play safe
2016	* and keep the code similar to the VT-x code and always intercept it.
2017	*/
2018	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
2019	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
2020	&& !CPUMIsGuestDebugStateActive(pVCpu))
2021	#else
2022	else if (!CPUMIsGuestDebugStateActive(pVCpu))
2023	#endif
2024	{
2025	fInterceptMovDRx = true;
2026	}
2027	}
2028
2029	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
2030	if (fInterceptMovDRx)
2031	{
2032	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
2033	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
2034	{
2035	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
2036	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
2037	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2038	}
2039	}
2040	else
2041	{
2042	if ( pVmcb->ctrl.u16InterceptRdDRx
2043	\|\| pVmcb->ctrl.u16InterceptWrDRx)
2044	{
2045	pVmcb->ctrl.u16InterceptRdDRx = 0;
2046	pVmcb->ctrl.u16InterceptWrDRx = 0;
2047	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2048	}
2049	}
2050	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2051	}
2052
2053	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2054	/**
2055	* Exports the nested-guest hardware virtualization state into the nested-guest
2056	* VMCB.
2057	*
2058	* @param pVCpu The cross context virtual CPU structure.
2059	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2060	*
2061	* @remarks No-long-jump zone!!!
2062	*/
2063	static void hmR0SvmExportGuestHwvirtStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
2064	{
2065	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2066
2067	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
2068	{
2069	/*
2070	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2071	* since SVM doesn't have a preemption timer.
2072	*
2073	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
2074	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2075	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2076	*/
2077	PVM pVM = pVCpu->CTX_SUFF(pVM);
2078	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2079	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2080	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2081	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_PAUSE))
2082	{
2083	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2084	pVmcbNstGstCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2085	pVmcbNstGstCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2086	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2087	}
2088	else
2089	{
2090	pVmcbNstGstCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2091	pVmcbNstGstCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2092	}
2093
2094	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
2095	}
2096	}
2097	#endif
2098
2099	/**
2100	* Exports the guest APIC TPR state into the VMCB.
2101	*
2102	* @returns VBox status code.
2103	* @param pVCpu The cross context virtual CPU structure.
2104	* @param pVmcb Pointer to the VM control block.
2105	*/
2106	static int hmR0SvmExportGuestApicTpr(PVMCPU pVCpu, PSVMVMCB pVmcb)
2107	{
2108	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2109	{
2110	PVM pVM = pVCpu->CTX_SUFF(pVM);
2111	if ( PDMHasApic(pVM)
2112	&& APICIsEnabled(pVCpu))
2113	{
2114	bool fPendingIntr;
2115	uint8_t u8Tpr;
2116	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2117	AssertRCReturn(rc, rc);
2118
2119	/* Assume that we need to trap all TPR accesses and thus need not check on
2120	every #VMEXIT if we should update the TPR. */
2121	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2122	pVCpu->hm.s.svm.fSyncVTpr = false;
2123
2124	if (!pVM->hm.s.fTPRPatchingActive)
2125	{
2126	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2127	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2128
2129	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2130	can deliver the interrupt to the guest. */
2131	if (fPendingIntr)
2132	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2133	else
2134	{
2135	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2136	pVCpu->hm.s.svm.fSyncVTpr = true;
2137	}
2138
2139	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2140	}
2141	else
2142	{
2143	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2144	pVmcb->guest.u64LSTAR = u8Tpr;
2145	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
2146
2147	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2148	if (fPendingIntr)
2149	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2150	else
2151	{
2152	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2153	pVCpu->hm.s.svm.fSyncVTpr = true;
2154	}
2155	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2156	}
2157	}
2158	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2159	}
2160	return VINF_SUCCESS;
2161	}
2162
2163
2164	/**
2165	* Sets up the exception interrupts required for guest (or nested-guest)
2166	* execution in the VMCB.
2167	*
2168	* @param pVCpu The cross context virtual CPU structure.
2169	* @param pVmcb Pointer to the VM control block.
2170	*
2171	* @remarks No-long-jump zone!!!
2172	*/
2173	static void hmR0SvmExportGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb)
2174	{
2175	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2176
2177	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2178	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS)
2179	{
2180	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2181	if (pVCpu->hm.s.fGIMTrapXcptUD)
2182	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2183	else
2184	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2185
2186	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2187	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2188	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2189	else
2190	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2191
2192	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2193	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS;
2194	}
2195	}
2196
2197
2198	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2199	/**
2200	* Merges guest and nested-guest intercepts for executing the nested-guest using
2201	* hardware-assisted SVM.
2202	*
2203	* This merges the guest and nested-guest intercepts in a way that if the outer
2204	* guest intercept is set we need to intercept it in the nested-guest as
2205	* well.
2206	*
2207	* @param pVCpu The cross context virtual CPU structure.
2208	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2209	*/
2210	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPU pVCpu)
2211	{
2212	PVM pVM = pVCpu->CTX_SUFF(pVM);
2213	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2214	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2215	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2216
2217	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2218	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2219	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2220
2221	/* Always intercept CR4 writes for tracking PGM mode changes. */
2222	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2223
2224	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2225	if (!pVM->hm.s.fNestedPaging)
2226	{
2227	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2228	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2229	}
2230
2231	/** @todo Figure out debugging with nested-guests, till then just intercept
2232	* all DR[0-15] accesses. */
2233	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2234	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2235
2236	/*
2237	* Merge the guest's exception intercepts into the nested-guest VMCB.
2238	*
2239	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2240	* while executing the nested-guest.
2241	*
2242	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2243	* be tweaked later depending on how we wish to implement breakpoints.
2244	*
2245	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2246	* loaded into their guests, not ours.
2247	*
2248	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2249	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2250	*/
2251	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2252	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2253	& ~( RT_BIT(X86_XCPT_UD)
2254	\| RT_BIT(X86_XCPT_BP)
2255	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2256	#else
2257	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2258	#endif
2259
2260	/*
2261	* Adjust intercepts while executing the nested-guest that differ from the
2262	* outer guest intercepts.
2263	*
2264	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2265	* that belong to the nested-guest to the outer guest.
2266	*
2267	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2268	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2269	*/
2270	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2271	\| SVM_CTRL_INTERCEPT_VMMCALL))
2272	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2273
2274	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2275	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2276
2277	/* Finally, update the VMCB clean bits. */
2278	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2279	}
2280	#endif
2281
2282
2283	/**
2284	* Selects the appropriate function to run guest code.
2285	*
2286	* @returns VBox status code.
2287	* @param pVCpu The cross context virtual CPU structure.
2288	*
2289	* @remarks No-long-jump zone!!!
2290	*/
2291	static int hmR0SvmSelectVMRunHandler(PVMCPU pVCpu)
2292	{
2293	if (CPUMIsGuestInLongMode(pVCpu))
2294	{
2295	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2296	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2297	#endif
2298	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2299	#if HC_ARCH_BITS == 32
2300	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2301	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2302	#else
2303	/* 64-bit host or hybrid host. */
2304	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2305	#endif
2306	}
2307	else
2308	{
2309	/* Guest is not in long mode, use the 32-bit handler. */
2310	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2311	}
2312	return VINF_SUCCESS;
2313	}
2314
2315
2316	/**
2317	* Enters the AMD-V session.
2318	*
2319	* @returns VBox status code.
2320	* @param pVCpu The cross context virtual CPU structure.
2321	*/
2322	VMMR0DECL(int) SVMR0Enter(PVMCPU pVCpu)
2323	{
2324	AssertPtr(pVCpu);
2325	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2326	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2327
2328	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2329	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2330	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2331
2332	pVCpu->hm.s.fLeaveDone = false;
2333	return VINF_SUCCESS;
2334	}
2335
2336
2337	/**
2338	* Thread-context callback for AMD-V.
2339	*
2340	* @param enmEvent The thread-context event.
2341	* @param pVCpu The cross context virtual CPU structure.
2342	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2343	* @thread EMT(pVCpu)
2344	*/
2345	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2346	{
2347	NOREF(fGlobalInit);
2348
2349	switch (enmEvent)
2350	{
2351	case RTTHREADCTXEVENT_OUT:
2352	{
2353	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2354	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2355	VMCPU_ASSERT_EMT(pVCpu);
2356
2357	/* No longjmps (log-flush, locks) in this fragile context. */
2358	VMMRZCallRing3Disable(pVCpu);
2359
2360	if (!pVCpu->hm.s.fLeaveDone)
2361	{
2362	hmR0SvmLeave(pVCpu, false /* fImportState */);
2363	pVCpu->hm.s.fLeaveDone = true;
2364	}
2365
2366	/* Leave HM context, takes care of local init (term). */
2367	int rc = HMR0LeaveCpu(pVCpu);
2368	AssertRC(rc); NOREF(rc);
2369
2370	/* Restore longjmp state. */
2371	VMMRZCallRing3Enable(pVCpu);
2372	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2373	break;
2374	}
2375
2376	case RTTHREADCTXEVENT_IN:
2377	{
2378	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2379	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2380	VMCPU_ASSERT_EMT(pVCpu);
2381
2382	/* No longjmps (log-flush, locks) in this fragile context. */
2383	VMMRZCallRing3Disable(pVCpu);
2384
2385	/*
2386	* Initialize the bare minimum state required for HM. This takes care of
2387	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2388	*/
2389	int rc = hmR0EnterCpu(pVCpu);
2390	AssertRC(rc); NOREF(rc);
2391	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2392	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2393
2394	pVCpu->hm.s.fLeaveDone = false;
2395
2396	/* Restore longjmp state. */
2397	VMMRZCallRing3Enable(pVCpu);
2398	break;
2399	}
2400
2401	default:
2402	break;
2403	}
2404	}
2405
2406
2407	/**
2408	* Saves the host state.
2409	*
2410	* @returns VBox status code.
2411	* @param pVCpu The cross context virtual CPU structure.
2412	*
2413	* @remarks No-long-jump zone!!!
2414	*/
2415	VMMR0DECL(int) SVMR0ExportHostState(PVMCPU pVCpu)
2416	{
2417	NOREF(pVCpu);
2418
2419	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2420	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2421	return VINF_SUCCESS;
2422	}
2423
2424
2425	/**
2426	* Exports the guest state from the guest-CPU context into the VMCB.
2427	*
2428	* The CPU state will be loaded from these fields on every successful VM-entry.
2429	* Also sets up the appropriate VMRUN function to execute guest code based on
2430	* the guest CPU mode.
2431	*
2432	* @returns VBox status code.
2433	* @param pVCpu The cross context virtual CPU structure.
2434	*
2435	* @remarks No-long-jump zone!!!
2436	*/
2437	static int hmR0SvmExportGuestState(PVMCPU pVCpu)
2438	{
2439	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2440
2441	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2442	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2443
2444	Assert(pVmcb);
2445	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2446
2447	pVmcb->guest.u64RIP = pCtx->rip;
2448	pVmcb->guest.u64RSP = pCtx->rsp;
2449	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2450	pVmcb->guest.u64RAX = pCtx->rax;
2451	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2452	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2453	{
2454	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Hardware supports it. */
2455	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2456	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
2457	}
2458	#endif
2459
2460	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2461
2462	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2463	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2464
2465	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2466	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2467	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2468
2469	ASMSetFlags(fEFlags);
2470
2471	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2472	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2473	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2474
2475	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2476	AssertRCReturn(rc, rc);
2477
2478	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2479	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2480	\| HM_CHANGED_GUEST_RFLAGS
2481	\| HM_CHANGED_GUEST_GPRS_MASK
2482	\| HM_CHANGED_GUEST_X87
2483	\| HM_CHANGED_GUEST_SSE_AVX
2484	\| HM_CHANGED_GUEST_OTHER_XSAVE
2485	\| HM_CHANGED_GUEST_XCRx
2486	\| HM_CHANGED_GUEST_TSC_AUX
2487	\| HM_CHANGED_GUEST_OTHER_MSRS
2488	\| HM_CHANGED_GUEST_HWVIRT
2489	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS)));
2490
2491	#ifdef VBOX_STRICT
2492	/*
2493	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2494	* except for the host-context and/or shared host-guest context bits.
2495	*/
2496	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2497	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2498	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2499	("fCtxChanged=%#RX64\n", fCtxChanged));
2500
2501	/*
2502	* If we need to log state that isn't always imported, we'll need to import them here.
2503	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2504	*/
2505	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2506	#endif
2507
2508	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2509	return VINF_SUCCESS;
2510	}
2511
2512
2513	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2514	/**
2515	* Merges the guest and nested-guest MSR permission bitmap.
2516	*
2517	* If the guest is intercepting an MSR we need to intercept it regardless of
2518	* whether the nested-guest is intercepting it or not.
2519	*
2520	* @param pHostCpu The HM physical-CPU structure.
2521	* @param pVCpu The cross context virtual CPU structure.
2522	*
2523	* @remarks No-long-jmp zone!!!
2524	*/
2525	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPU pVCpu)
2526	{
2527	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2528	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2529	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2530
2531	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2532	uint32_t const offRsvdQwords = 0x1800 >> 3;
2533	for (uint32_t i = 0; i < offRsvdQwords; i++)
2534	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2535	}
2536
2537
2538	/**
2539	* Caches the nested-guest VMCB fields before we modify them for execution using
2540	* hardware-assisted SVM.
2541	*
2542	* @returns true if the VMCB was previously already cached, false otherwise.
2543	* @param pVCpu The cross context virtual CPU structure.
2544	*
2545	* @sa HMNotifySvmNstGstVmexit.
2546	*/
2547	static bool hmR0SvmCacheVmcbNested(PVMCPU pVCpu)
2548	{
2549	/*
2550	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2551	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2552	*
2553	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2554	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2555	*/
2556	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2557	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2558	if (!fWasCached)
2559	{
2560	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2561	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2562	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2563	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2564	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2565	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2566	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2567	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2568	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2569	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2570	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2571	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2572	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2573	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2574	pVmcbNstGstCache->fCacheValid = true;
2575	Log4Func(("Cached VMCB fields\n"));
2576	}
2577
2578	return fWasCached;
2579	}
2580
2581
2582	/**
2583	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2584	*
2585	* This is done the first time we enter nested-guest execution using SVM R0
2586	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2587	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2588	*
2589	* @param pVCpu The cross context virtual CPU structure.
2590	*/
2591	static void hmR0SvmSetupVmcbNested(PVMCPU pVCpu)
2592	{
2593	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2594	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2595
2596	/*
2597	* First cache the nested-guest VMCB fields we may potentially modify.
2598	*/
2599	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2600	if (!fVmcbCached)
2601	{
2602	/*
2603	* The IOPM of the nested-guest can be ignored because the the guest always
2604	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2605	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2606	*/
2607	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2608
2609	/*
2610	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2611	* nested-paging suddenly while executing a VM (see assertion at the end of
2612	* Trap0eHandler() in PGMAllBth.h).
2613	*/
2614	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2615
2616	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2617	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2618
2619	/*
2620	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2621	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2622	*/
2623	pVCpu->hm.s.svm.fSyncVTpr = false;
2624
2625	#ifdef DEBUG_ramshankar
2626	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2627	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2628	#endif
2629
2630	/*
2631	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2632	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2633	*/
2634	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2635	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2636	\| SVM_CTRL_INTERCEPT_VMLOAD;
2637
2638	/*
2639	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2640	* CLGI/STGI instructions executed by the nested-guest.
2641	*/
2642	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2643	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2644	\| SVM_CTRL_INTERCEPT_STGI;
2645
2646	/* Merge the guest and nested-guest intercepts. */
2647	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2648
2649	/* Update the VMCB clean bits. */
2650	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2651	}
2652	else
2653	{
2654	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
2655	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2656	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2657	}
2658	}
2659
2660
2661	/**
2662	* Exports the nested-guest state into the VMCB.
2663	*
2664	* We need to export the entire state as we could be continuing nested-guest
2665	* execution at any point (not just immediately after VMRUN) and thus the VMCB
2666	* can be out-of-sync with the nested-guest state if it was executed in IEM.
2667	*
2668	* @returns VBox status code.
2669	* @param pVCpu The cross context virtual CPU structure.
2670	* @param pCtx Pointer to the guest-CPU context.
2671	*
2672	* @remarks No-long-jump zone!!!
2673	*/
2674	static int hmR0SvmExportGuestStateNested(PVMCPU pVCpu)
2675	{
2676	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2677
2678	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2679	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2680	Assert(pVmcbNstGst);
2681
2682	hmR0SvmSetupVmcbNested(pVCpu);
2683
2684	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2685	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2686	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2687	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2688
2689	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2690
2691	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcbNstGst);
2692	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2693
2694	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcbNstGst);
2695	hmR0SvmExportGuestMsrs(pVCpu, pVmcbNstGst);
2696	hmR0SvmExportGuestHwvirtStateNested(pVCpu, pVmcbNstGst);
2697
2698	ASMSetFlags(fEFlags);
2699
2700	/* Nested VGIF not supported yet. */
2701	Assert(!pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable);
2702
2703	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2704	AssertRCReturn(rc, rc);
2705
2706	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2707	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2708	\| HM_CHANGED_GUEST_RFLAGS
2709	\| HM_CHANGED_GUEST_GPRS_MASK
2710	\| HM_CHANGED_GUEST_APIC_TPR
2711	\| HM_CHANGED_GUEST_X87
2712	\| HM_CHANGED_GUEST_SSE_AVX
2713	\| HM_CHANGED_GUEST_OTHER_XSAVE
2714	\| HM_CHANGED_GUEST_XCRx
2715	\| HM_CHANGED_GUEST_TSC_AUX
2716	\| HM_CHANGED_GUEST_OTHER_MSRS
2717	\| HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS
2718	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2719
2720	#ifdef VBOX_STRICT
2721	/*
2722	* All of the guest-CPU state and SVM keeper bits should be exported here by now, except
2723	* for the host-context and/or shared host-guest context bits.
2724	*/
2725	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2726	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2727	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2728	("fCtxChanged=%#RX64\n", fCtxChanged));
2729
2730	/*
2731	* If we need to log state that isn't always imported, we'll need to import them here.
2732	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2733	*/
2734	hmR0SvmLogState(pVCpu, pVmcbNstGst, "hmR0SvmExportGuestStateNested", 0 /* fFlags /, 0 / uVerbose */);
2735	#endif
2736
2737	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2738	return rc;
2739	}
2740	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2741
2742
2743	/**
2744	* Exports the state shared between the host and guest (or nested-guest) into
2745	* the VMCB.
2746	*
2747	* @param pVCpu The cross context virtual CPU structure.
2748	* @param pVmcb Pointer to the VM control block.
2749	*
2750	* @remarks No-long-jump zone!!!
2751	*/
2752	static void hmR0SvmExportSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb)
2753	{
2754	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2755	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2756
2757	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2758	{
2759	/** @todo Figure out stepping with nested-guest. */
2760	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2761	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2762	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2763	else
2764	{
2765	pVmcb->guest.u64DR6 = pCtx->dr[6];
2766	pVmcb->guest.u64DR7 = pCtx->dr[7];
2767	}
2768	}
2769
2770	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2771	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2772	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2773	}
2774
2775
2776	/**
2777	* Worker for SVMR0ImportStateOnDemand.
2778	*
2779	* @param pVCpu The cross context virtual CPU structure.
2780	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2781	*/
2782	static void hmR0SvmImportGuestState(PVMCPU pVCpu, uint64_t fWhat)
2783	{
2784	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2785
2786	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2787	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2788	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2789	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2790
2791	Log4Func(("fExtrn=%#RX64 fWhat=%#RX64\n", pCtx->fExtrn, fWhat));
2792
2793	/*
2794	* We disable interrupts to make the updating of the state and in particular
2795	* the fExtrn modification atomic wrt to preemption hooks.
2796	*/
2797	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2798
2799	fWhat &= pCtx->fExtrn;
2800	if (fWhat)
2801	{
2802	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2803	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2804	{
2805	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2806	{
2807	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2808	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2809	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2810	}
2811	}
2812
2813	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2814	{
2815	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2816	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2817	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2818	}
2819	#endif
2820
2821	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2822	{
2823	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2824	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2825	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2826	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2827	}
2828
2829	if (fWhat & CPUMCTX_EXTRN_RIP)
2830	pCtx->rip = pVmcbGuest->u64RIP;
2831
2832	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2833	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2834
2835	if (fWhat & CPUMCTX_EXTRN_RSP)
2836	pCtx->rsp = pVmcbGuest->u64RSP;
2837
2838	if (fWhat & CPUMCTX_EXTRN_RAX)
2839	pCtx->rax = pVmcbGuest->u64RAX;
2840
2841	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2842	{
2843	if (fWhat & CPUMCTX_EXTRN_CS)
2844	{
2845	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2846	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2847	/** @todo SELM might need to be fixed as it too should not care about the
2848	* granularity bit. See @bugref{6785}. */
2849	if ( !pCtx->cs.Attr.n.u1Granularity
2850	&& pCtx->cs.Attr.n.u1Present
2851	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2852	{
2853	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2854	pCtx->cs.Attr.n.u1Granularity = 1;
2855	}
2856	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2857	}
2858	if (fWhat & CPUMCTX_EXTRN_SS)
2859	{
2860	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2861	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2862	/*
2863	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2864	* VMCB and uses that and thus it's possible that when the CPL changes during
2865	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2866	* AMD Fusion CPUs with 64-bit guests.
2867	*
2868	* See AMD spec. 15.5.1 "Basic operation".
2869	*/
2870	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2871	uint8_t const uCpl = pVmcbGuest->u8CPL;
2872	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2873	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2874	}
2875	if (fWhat & CPUMCTX_EXTRN_DS)
2876	{
2877	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2878	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2879	}
2880	if (fWhat & CPUMCTX_EXTRN_ES)
2881	{
2882	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2883	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2884	}
2885	if (fWhat & CPUMCTX_EXTRN_FS)
2886	{
2887	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2888	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2889	}
2890	if (fWhat & CPUMCTX_EXTRN_GS)
2891	{
2892	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2893	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2894	}
2895	}
2896
2897	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2898	{
2899	if (fWhat & CPUMCTX_EXTRN_TR)
2900	{
2901	/*
2902	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2903	* are used between Intel and AMD, see @bugref{6208#c39}.
2904	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2905	*/
2906	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2907	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2908	{
2909	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2910	\|\| CPUMIsGuestInLongModeEx(pCtx))
2911	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2912	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2913	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2914	}
2915	}
2916
2917	if (fWhat & CPUMCTX_EXTRN_LDTR)
2918	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2919
2920	if (fWhat & CPUMCTX_EXTRN_GDTR)
2921	{
2922	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2923	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2924	}
2925
2926	if (fWhat & CPUMCTX_EXTRN_IDTR)
2927	{
2928	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2929	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2930	}
2931	}
2932
2933	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2934	{
2935	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2936	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2937	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2938	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2939	}
2940
2941	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2942	{
2943	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2944	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2945	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2946	}
2947
2948	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2949	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2950
2951	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2952	{
2953	if (fWhat & CPUMCTX_EXTRN_DR6)
2954	{
2955	if (!pVCpu->hm.s.fUsingHyperDR7)
2956	pCtx->dr[6] = pVmcbGuest->u64DR6;
2957	else
2958	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2959	}
2960
2961	if (fWhat & CPUMCTX_EXTRN_DR7)
2962	{
2963	if (!pVCpu->hm.s.fUsingHyperDR7)
2964	pCtx->dr[7] = pVmcbGuest->u64DR7;
2965	else
2966	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2967	}
2968	}
2969
2970	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2971	{
2972	if (fWhat & CPUMCTX_EXTRN_CR0)
2973	{
2974	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2975	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2976	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2977	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2978	CPUMSetGuestCR0(pVCpu, uCr0);
2979	VMMRZCallRing3Enable(pVCpu);
2980	}
2981
2982	if (fWhat & CPUMCTX_EXTRN_CR2)
2983	pCtx->cr2 = pVmcbGuest->u64CR2;
2984
2985	if (fWhat & CPUMCTX_EXTRN_CR3)
2986	{
2987	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2988	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2989	{
2990	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2991	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2992	}
2993	}
2994
2995	/* Changes to CR4 are always intercepted. */
2996	}
2997
2998	/* Update fExtrn. */
2999	pCtx->fExtrn &= ~fWhat;
3000
3001	/* If everything has been imported, clear the HM keeper bit. */
3002	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
3003	{
3004	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
3005	Assert(!pCtx->fExtrn);
3006	}
3007	}
3008	else
3009	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3010
3011	ASMSetFlags(fEFlags);
3012
3013	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
3014
3015	/*
3016	* Honor any pending CR3 updates.
3017	*
3018	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
3019	* -> hmR0SvmCallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
3020	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
3021	* handling -> hmR0SvmImportGuestState() and here we are.
3022	*
3023	* The reason for such complicated handling is because VM-exits that call into PGM expect
3024	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
3025	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
3026	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
3027	*
3028	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
3029	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
3030	*/
3031	if ( VMMRZCallRing3IsEnabled(pVCpu)
3032	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3033	{
3034	Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
3035	PGMUpdateCR3(pVCpu, pCtx->cr3);
3036	}
3037	}
3038
3039
3040	/**
3041	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
3042	* context.
3043	*
3044	* Currently there is no residual state left in the CPU that is not updated in the
3045	* VMCB.
3046	*
3047	* @returns VBox status code.
3048	* @param pVCpu The cross context virtual CPU structure.
3049	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
3050	*/
3051	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
3052	{
3053	hmR0SvmImportGuestState(pVCpu, fWhat);
3054	return VINF_SUCCESS;
3055	}
3056
3057
3058	/**
3059	* Does the necessary state syncing before returning to ring-3 for any reason
3060	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
3061	*
3062	* @param pVCpu The cross context virtual CPU structure.
3063	* @param fImportState Whether to import the guest state from the VMCB back
3064	* to the guest-CPU context.
3065	*
3066	* @remarks No-long-jmp zone!!!
3067	*/
3068	static void hmR0SvmLeave(PVMCPU pVCpu, bool fImportState)
3069	{
3070	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3071	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3072	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3073
3074	/*
3075	* !!! IMPORTANT !!!
3076	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
3077	*/
3078
3079	/* Save the guest state if necessary. */
3080	if (fImportState)
3081	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3082
3083	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3084	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3085	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
3086
3087	/*
3088	* Restore host debug registers if necessary and resync on next R0 reentry.
3089	*/
3090	#ifdef VBOX_STRICT
3091	if (CPUMIsHyperDebugStateActive(pVCpu))
3092	{
3093	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
3094	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
3095	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
3096	}
3097	#endif
3098	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3099	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
3100	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
3101
3102	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
3103	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
3104	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
3105	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
3106	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
3107	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3108
3109	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
3110	}
3111
3112
3113	/**
3114	* Leaves the AMD-V session.
3115	*
3116	* Only used while returning to ring-3 either due to longjump or exits to
3117	* ring-3.
3118	*
3119	* @returns VBox status code.
3120	* @param pVCpu The cross context virtual CPU structure.
3121	*/
3122	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
3123	{
3124	HM_DISABLE_PREEMPT(pVCpu);
3125	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3126	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3127
3128	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3129	and done this from the SVMR0ThreadCtxCallback(). */
3130	if (!pVCpu->hm.s.fLeaveDone)
3131	{
3132	hmR0SvmLeave(pVCpu, true /* fImportState */);
3133	pVCpu->hm.s.fLeaveDone = true;
3134	}
3135
3136	/*
3137	* !!! IMPORTANT !!!
3138	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
3139	*/
3140
3141	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3142	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3143	VMMR0ThreadCtxHookDisable(pVCpu);
3144
3145	/* Leave HM context. This takes care of local init (term). */
3146	int rc = HMR0LeaveCpu(pVCpu);
3147
3148	HM_RESTORE_PREEMPT();
3149	return rc;
3150	}
3151
3152
3153	/**
3154	* Does the necessary state syncing before doing a longjmp to ring-3.
3155	*
3156	* @returns VBox status code.
3157	* @param pVCpu The cross context virtual CPU structure.
3158	*
3159	* @remarks No-long-jmp zone!!!
3160	*/
3161	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
3162	{
3163	return hmR0SvmLeaveSession(pVCpu);
3164	}
3165
3166
3167	/**
3168	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3169	* any remaining host state) before we longjump to ring-3 and possibly get
3170	* preempted.
3171	*
3172	* @param pVCpu The cross context virtual CPU structure.
3173	* @param enmOperation The operation causing the ring-3 longjump.
3174	* @param pvUser The user argument, NULL (currently unused).
3175	*/
3176	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
3177	{
3178	RT_NOREF_PV(pvUser);
3179
3180	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3181	{
3182	/*
3183	* !!! IMPORTANT !!!
3184	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3185	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3186	*/
3187	VMMRZCallRing3RemoveNotification(pVCpu);
3188	VMMRZCallRing3Disable(pVCpu);
3189	HM_DISABLE_PREEMPT(pVCpu);
3190
3191	/* Import the entire guest state. */
3192	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3193
3194	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3195	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3196
3197	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3198	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3199
3200	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3201	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3202	VMMR0ThreadCtxHookDisable(pVCpu);
3203
3204	/* Leave HM context. This takes care of local init (term). */
3205	HMR0LeaveCpu(pVCpu);
3206
3207	HM_RESTORE_PREEMPT();
3208	return VINF_SUCCESS;
3209	}
3210
3211	Assert(pVCpu);
3212	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3213	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3214
3215	VMMRZCallRing3Disable(pVCpu);
3216	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3217
3218	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3219	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3220	AssertRCReturn(rc, rc);
3221
3222	VMMRZCallRing3Enable(pVCpu);
3223	return VINF_SUCCESS;
3224	}
3225
3226
3227	/**
3228	* Take necessary actions before going back to ring-3.
3229	*
3230	* An action requires us to go back to ring-3. This function does the necessary
3231	* steps before we can safely return to ring-3. This is not the same as longjmps
3232	* to ring-3, this is voluntary.
3233	*
3234	* @returns VBox status code.
3235	* @param pVCpu The cross context virtual CPU structure.
3236	* @param rcExit The reason for exiting to ring-3. Can be
3237	* VINF_VMM_UNKNOWN_RING3_CALL.
3238	*/
3239	static int hmR0SvmExitToRing3(PVMCPU pVCpu, int rcExit)
3240	{
3241	Assert(pVCpu);
3242	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3243
3244	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3245	VMMRZCallRing3Disable(pVCpu);
3246	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", rcExit, (uint64_t)pVCpu->fLocalForcedActions,
3247	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3248
3249	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3250	if (pVCpu->hm.s.Event.fPending)
3251	{
3252	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3253	Assert(!pVCpu->hm.s.Event.fPending);
3254	}
3255
3256	/* Sync. the necessary state for going back to ring-3. */
3257	hmR0SvmLeaveSession(pVCpu);
3258	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3259
3260	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3261	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3262	\| CPUM_CHANGED_LDTR
3263	\| CPUM_CHANGED_GDTR
3264	\| CPUM_CHANGED_IDTR
3265	\| CPUM_CHANGED_TR
3266	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3267	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
3268	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3269	{
3270	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3271	}
3272
3273	/* Update the exit-to-ring 3 reason. */
3274	pVCpu->hm.s.rcLastExitToR3 = rcExit;
3275
3276	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3277	if ( rcExit != VINF_EM_RAW_INTERRUPT
3278	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3279	{
3280	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3281	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3282	}
3283
3284	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3285
3286	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
3287	VMMRZCallRing3RemoveNotification(pVCpu);
3288	VMMRZCallRing3Enable(pVCpu);
3289
3290	/*
3291	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3292	* and if we're injecting an event we should have a TRPM trap pending.
3293	*/
3294	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3295	pVCpu->hm.s.u32HMError = rcExit,
3296	VERR_SVM_IPE_5);
3297	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3298	pVCpu->hm.s.u32HMError = rcExit,
3299	VERR_SVM_IPE_4);
3300
3301	return rcExit;
3302	}
3303
3304
3305	/**
3306	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3307	* intercepts.
3308	*
3309	* @param pVCpu The cross context virtual CPU structure.
3310	* @param pVmcb Pointer to the VM control block.
3311	*
3312	* @remarks No-long-jump zone!!!
3313	*/
3314	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3315	{
3316	/*
3317	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3318	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3319	* RDTSC/RDTSCP as well.
3320	*/
3321	bool fParavirtTsc;
3322	uint64_t uTscOffset;
3323	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3324
3325	bool fIntercept;
3326	if (fCanUseRealTsc)
3327	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3328	else
3329	{
3330	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3331	fIntercept = true;
3332	}
3333
3334	if (!fIntercept)
3335	{
3336	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3337	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3338	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3339	uTscOffset = HMApplySvmNstGstTscOffset(pVCpu, uTscOffset);
3340	#endif
3341
3342	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3343	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3344	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3345
3346	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
3347	}
3348	else
3349	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
3350
3351	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3352	information before every VM-entry, hence we have nothing to do here at the moment. */
3353	if (fParavirtTsc)
3354	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3355	}
3356
3357
3358	/**
3359	* Sets an event as a pending event to be injected into the guest.
3360	*
3361	* @param pVCpu The cross context virtual CPU structure.
3362	* @param pEvent Pointer to the SVM event.
3363	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3364	* page-fault.
3365	*
3366	* @remarks Statistics counter assumes this is a guest event being reflected to
3367	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3368	*/
3369	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3370	{
3371	Assert(!pVCpu->hm.s.Event.fPending);
3372	Assert(pEvent->n.u1Valid);
3373
3374	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3375	pVCpu->hm.s.Event.fPending = true;
3376	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3377
3378	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3379	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3380	}
3381
3382
3383	/**
3384	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3385	*
3386	* @param pVCpu The cross context virtual CPU structure.
3387	*/
3388	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3389	{
3390	SVMEVENT Event;
3391	Event.u = 0;
3392	Event.n.u1Valid = 1;
3393	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3394	Event.n.u8Vector = X86_XCPT_UD;
3395	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3396	}
3397
3398
3399	/**
3400	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3401	*
3402	* @param pVCpu The cross context virtual CPU structure.
3403	*/
3404	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3405	{
3406	SVMEVENT Event;
3407	Event.u = 0;
3408	Event.n.u1Valid = 1;
3409	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3410	Event.n.u8Vector = X86_XCPT_DB;
3411	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3412	}
3413
3414
3415	/**
3416	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3417	*
3418	* @param pVCpu The cross context virtual CPU structure.
3419	* @param u32ErrCode The error-code for the page-fault.
3420	* @param uFaultAddress The page fault address (CR2).
3421	*
3422	* @remarks This updates the guest CR2 with @a uFaultAddress!
3423	*/
3424	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3425	{
3426	SVMEVENT Event;
3427	Event.u = 0;
3428	Event.n.u1Valid = 1;
3429	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3430	Event.n.u8Vector = X86_XCPT_PF;
3431	Event.n.u1ErrorCodeValid = 1;
3432	Event.n.u32ErrorCode = u32ErrCode;
3433
3434	/* Update CR2 of the guest. */
3435	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3436	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3437	{
3438	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3439	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3440	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3441	}
3442
3443	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3444	}
3445
3446
3447	/**
3448	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3449	*
3450	* @param pVCpu The cross context virtual CPU structure.
3451	*/
3452	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3453	{
3454	SVMEVENT Event;
3455	Event.u = 0;
3456	Event.n.u1Valid = 1;
3457	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3458	Event.n.u8Vector = X86_XCPT_MF;
3459	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3460	}
3461
3462
3463	/**
3464	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3465	*
3466	* @param pVCpu The cross context virtual CPU structure.
3467	*/
3468	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3469	{
3470	SVMEVENT Event;
3471	Event.u = 0;
3472	Event.n.u1Valid = 1;
3473	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3474	Event.n.u8Vector = X86_XCPT_DF;
3475	Event.n.u1ErrorCodeValid = 1;
3476	Event.n.u32ErrorCode = 0;
3477	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3478	}
3479
3480
3481	/**
3482	* Injects an event into the guest upon VMRUN by updating the relevant field
3483	* in the VMCB.
3484	*
3485	* @param pVCpu The cross context virtual CPU structure.
3486	* @param pVmcb Pointer to the guest VM control block.
3487	* @param pEvent Pointer to the event.
3488	*
3489	* @remarks No-long-jump zone!!!
3490	* @remarks Requires CR0!
3491	*/
3492	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3493	{
3494	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3495	pVmcb->ctrl.EventInject.u = pEvent->u;
3496	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3497	RT_NOREF(pVCpu);
3498
3499	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3500	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3501	}
3502
3503
3504
3505	/**
3506	* Converts any TRPM trap into a pending HM event. This is typically used when
3507	* entering from ring-3 (not longjmp returns).
3508	*
3509	* @param pVCpu The cross context virtual CPU structure.
3510	*/
3511	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3512	{
3513	Assert(TRPMHasTrap(pVCpu));
3514	Assert(!pVCpu->hm.s.Event.fPending);
3515
3516	uint8_t uVector;
3517	TRPMEVENT enmTrpmEvent;
3518	RTGCUINT uErrCode;
3519	RTGCUINTPTR GCPtrFaultAddress;
3520	uint8_t cbInstr;
3521
3522	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3523	AssertRC(rc);
3524
3525	SVMEVENT Event;
3526	Event.u = 0;
3527	Event.n.u1Valid = 1;
3528	Event.n.u8Vector = uVector;
3529
3530	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3531	if (enmTrpmEvent == TRPM_TRAP)
3532	{
3533	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3534	switch (uVector)
3535	{
3536	case X86_XCPT_NMI:
3537	{
3538	Event.n.u3Type = SVM_EVENT_NMI;
3539	break;
3540	}
3541
3542	case X86_XCPT_BP:
3543	case X86_XCPT_OF:
3544	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3545	RT_FALL_THRU();
3546
3547	case X86_XCPT_PF:
3548	case X86_XCPT_DF:
3549	case X86_XCPT_TS:
3550	case X86_XCPT_NP:
3551	case X86_XCPT_SS:
3552	case X86_XCPT_GP:
3553	case X86_XCPT_AC:
3554	{
3555	Event.n.u1ErrorCodeValid = 1;
3556	Event.n.u32ErrorCode = uErrCode;
3557	break;
3558	}
3559	}
3560	}
3561	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3562	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3563	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3564	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3565	else
3566	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3567
3568	rc = TRPMResetTrap(pVCpu);
3569	AssertRC(rc);
3570
3571	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3572	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3573
3574	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3575	}
3576
3577
3578	/**
3579	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3580	* AMD-V to execute any instruction.
3581	*
3582	* @param pVCpu The cross context virtual CPU structure.
3583	*/
3584	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3585	{
3586	Assert(pVCpu->hm.s.Event.fPending);
3587	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3588
3589	SVMEVENT Event;
3590	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3591
3592	uint8_t uVector = Event.n.u8Vector;
3593	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3594
3595	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3596
3597	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3598	AssertRC(rc);
3599
3600	if (Event.n.u1ErrorCodeValid)
3601	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3602
3603	if ( enmTrapType == TRPM_TRAP
3604	&& uVector == X86_XCPT_PF)
3605	{
3606	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3607	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3608	}
3609	else if (enmTrapType == TRPM_SOFTWARE_INT)
3610	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3611	pVCpu->hm.s.Event.fPending = false;
3612	}
3613
3614
3615	/**
3616	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3617	* now.
3618	*
3619	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3620	* @param pVCpu The cross context virtual CPU structure.
3621	*
3622	* @remarks No-long-jump zone!!!
3623	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3624	*/
3625	static bool hmR0SvmIsIntrShadowActive(PVMCPU pVCpu)
3626	{
3627	/*
3628	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3629	* completes. Check if we should inhibit interrupts or clear any existing
3630	* interrupt inhibition.
3631	*/
3632	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3633	{
3634	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3635	{
3636	/*
3637	* We can clear the inhibit force flag as even if we go back to the recompiler
3638	* without executing guest code in AMD-V, the flag's condition to be cleared is
3639	* met and thus the cleared state is correct.
3640	*/
3641	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3642	return false;
3643	}
3644	return true;
3645	}
3646	return false;
3647	}
3648
3649
3650	/**
3651	* Sets the virtual interrupt intercept control in the VMCB.
3652	*
3653	* @param pVCpu The cross context virtual CPU structure.
3654	* @param pVmcb Pointer to the VM control block.
3655	*/
3656	static void hmR0SvmSetIntWindowExiting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3657	{
3658	/*
3659	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3660	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3661	* (updating ISR at the right time) and inject the interrupt.
3662	*
3663	* With AVIC is supported, we could make use of the asynchronously delivery without
3664	* #VMEXIT and we would be passing the AVIC page to SVM.
3665	*
3666	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3667	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3668	*/
3669	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3670	/*
3671	* Currently we don't overlay interupt windows and if there's any V_IRQ pending in the
3672	* nested-guest VMCB, we avoid setting up any interrupt window on behalf of the outer
3673	* guest.
3674	*/
3675	/** @todo Does this mean we end up prioritizing virtual interrupt
3676	* delivery/window over a physical interrupt (from the outer guest)
3677	* might be pending? */
3678	bool const fEnableIntWindow = !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
3679	if (!fEnableIntWindow)
3680	{
3681	Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx));
3682	Log4(("Nested-guest V_IRQ already pending\n"));
3683	}
3684	#else
3685	bool const fEnableIntWindow = true;
3686	RT_NOREF(pVCpu);
3687	#endif
3688	if (fEnableIntWindow)
3689	{
3690	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3691	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3692	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3693	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3694	Log4(("Set VINTR intercept\n"));
3695	}
3696	}
3697
3698
3699	/**
3700	* Clears the virtual interrupt intercept control in the VMCB as
3701	* we are figured the guest is unable process any interrupts
3702	* at this point of time.
3703	*
3704	* @param pVCpu The cross context virtual CPU structure.
3705	* @param pVmcb Pointer to the VM control block.
3706	*/
3707	static void hmR0SvmClearIntWindowExiting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3708	{
3709	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3710	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3711	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3712	{
3713	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3714	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3715	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3716	Log4(("Cleared VINTR intercept\n"));
3717	}
3718	}
3719
3720	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3721	/**
3722	* Evaluates the event to be delivered to the nested-guest and sets it as the
3723	* pending event.
3724	*
3725	* @returns VBox strict status code.
3726	* @param pVCpu The cross context virtual CPU structure.
3727	*/
3728	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu)
3729	{
3730	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3731	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
3732	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3733	\| CPUMCTX_EXTRN_RFLAGS
3734	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3735	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3736
3737	Assert(!pVCpu->hm.s.Event.fPending);
3738	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3739	Assert(pVmcb);
3740
3741	bool const fGif = CPUMGetGuestGif(pCtx);
3742	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3743	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3744
3745	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3746	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3747	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3748
3749	/** @todo SMI. SMIs take priority over NMIs. */
3750
3751	/*
3752	* Check if the guest can receive NMIs.
3753	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3754	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3755	*/
3756	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3757	&& !fBlockNmi)
3758	{
3759	if ( fGif
3760	&& !fIntShadow)
3761	{
3762	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3763	{
3764	Log4(("Intercepting NMI -> #VMEXIT\n"));
3765	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3766	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3767	}
3768
3769	Log4(("Setting NMI pending for injection\n"));
3770	SVMEVENT Event;
3771	Event.u = 0;
3772	Event.n.u1Valid = 1;
3773	Event.n.u8Vector = X86_XCPT_NMI;
3774	Event.n.u3Type = SVM_EVENT_NMI;
3775	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3776	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3777	}
3778	else if (!fGif)
3779	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3780	else
3781	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3782	}
3783	/*
3784	* Check if the nested-guest can receive external interrupts (generated by the guest's
3785	* PIC/APIC).
3786	*
3787	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3788	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3789	*
3790	* External interrupts that are generated for the outer guest may be intercepted
3791	* depending on how the nested-guest VMCB was programmed by guest software.
3792	*
3793	* Physical interrupts always take priority over virtual interrupts,
3794	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3795	*
3796	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3797	* do that work when we execute nested guest code esp. since all the required information
3798	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3799	* the virtual interrupt controller.
3800	*/
3801	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3802	&& !pVCpu->hm.s.fSingleInstruction)
3803	{
3804	if ( fGif
3805	&& !fIntShadow
3806	&& CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx))
3807	{
3808	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3809	{
3810	Log4(("Intercepting INTR -> #VMEXIT\n"));
3811	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3812	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3813	}
3814
3815	uint8_t u8Interrupt;
3816	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3817	if (RT_SUCCESS(rc))
3818	{
3819	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3820	SVMEVENT Event;
3821	Event.u = 0;
3822	Event.n.u1Valid = 1;
3823	Event.n.u8Vector = u8Interrupt;
3824	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3825	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3826	}
3827	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3828	{
3829	/*
3830	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3831	* updated eventually when the TPR is written by the guest.
3832	*/
3833	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3834	}
3835	else
3836	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3837	}
3838	else if (!fGif)
3839	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3840	else
3841	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3842	}
3843
3844	return VINF_SUCCESS;
3845	}
3846	#endif
3847
3848	/**
3849	* Evaluates the event to be delivered to the guest and sets it as the pending
3850	* event.
3851	*
3852	* @param pVCpu The cross context virtual CPU structure.
3853	*/
3854	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu)
3855	{
3856	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3857	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3858	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3859	\| CPUMCTX_EXTRN_RFLAGS
3860	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW);
3861
3862	Assert(!pVCpu->hm.s.Event.fPending);
3863	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3864	Assert(pVmcb);
3865
3866	bool const fGif = CPUMGetGuestGif(pCtx);
3867	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3868	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3869	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3870
3871	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool fIntPending=%RTbool NMI pending=%RTbool\n",
3872	fGif, fBlockNmi, fBlockInt, fIntShadow,
3873	VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3874	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3875
3876	/** @todo SMI. SMIs take priority over NMIs. */
3877
3878	/*
3879	* Check if the guest can receive NMIs.
3880	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3881	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3882	*/
3883	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3884	&& !fBlockNmi)
3885	{
3886	if ( fGif
3887	&& !fIntShadow)
3888	{
3889	Log4(("Setting NMI pending for injection\n"));
3890	SVMEVENT Event;
3891	Event.u = 0;
3892	Event.n.u1Valid = 1;
3893	Event.n.u8Vector = X86_XCPT_NMI;
3894	Event.n.u3Type = SVM_EVENT_NMI;
3895	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3896	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3897	}
3898	else if (!fGif)
3899	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3900	else
3901	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3902	}
3903	/*
3904	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3905	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3906	* it from the APIC device.
3907	*/
3908	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3909	&& !pVCpu->hm.s.fSingleInstruction)
3910	{
3911	if ( fGif
3912	&& !fBlockInt
3913	&& !fIntShadow)
3914	{
3915	uint8_t u8Interrupt;
3916	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3917	if (RT_SUCCESS(rc))
3918	{
3919	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3920	SVMEVENT Event;
3921	Event.u = 0;
3922	Event.n.u1Valid = 1;
3923	Event.n.u8Vector = u8Interrupt;
3924	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3925	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3926	}
3927	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3928	{
3929	/*
3930	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3931	* updated eventually when the TPR is written by the guest.
3932	*/
3933	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3934	}
3935	else
3936	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3937	}
3938	else if (!fGif)
3939	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3940	else
3941	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3942	}
3943	}
3944
3945
3946	/**
3947	* Injects any pending events into the guest (or nested-guest).
3948	*
3949	* @param pVCpu The cross context virtual CPU structure.
3950	* @param pVmcb Pointer to the VM control block.
3951	*
3952	* @remarks Must only be called when we are guaranteed to enter
3953	* hardware-assisted SVM execution and not return to ring-3
3954	* prematurely.
3955	*/
3956	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PSVMVMCB pVmcb)
3957	{
3958	Assert(!TRPMHasTrap(pVCpu));
3959	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3960
3961	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3962	#ifdef VBOX_STRICT
3963	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3964	bool const fGif = CPUMGetGuestGif(pCtx);
3965	bool fAllowInt = fGif;
3966	if (fGif)
3967	{
3968	/*
3969	* For nested-guests we have no way to determine if we're injecting a physical or
3970	* virtual interrupt at this point. Hence the partial verification below.
3971	*/
3972	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3973	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3974	else
3975	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3976	}
3977	#endif
3978
3979	if (pVCpu->hm.s.Event.fPending)
3980	{
3981	SVMEVENT Event;
3982	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3983	Assert(Event.n.u1Valid);
3984
3985	/*
3986	* Validate event injection pre-conditions.
3987	*/
3988	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3989	{
3990	Assert(fAllowInt);
3991	Assert(!fIntShadow);
3992	}
3993	else if (Event.n.u3Type == SVM_EVENT_NMI)
3994	{
3995	Assert(fGif);
3996	Assert(!fIntShadow);
3997	}
3998
3999	/*
4000	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
4001	* do this only when we are surely going to inject the NMI as otherwise if we return
4002	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
4003	* SVM R0.
4004	*
4005	* With VT-x, this is handled by the Guest interruptibility information VMCS field
4006	* which will set the VMCS field after actually delivering the NMI which we read on
4007	* VM-exit to determine the state.
4008	*/
4009	if ( Event.n.u3Type == SVM_EVENT_NMI
4010	&& Event.n.u8Vector == X86_XCPT_NMI
4011	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
4012	{
4013	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4014	}
4015
4016	/*
4017	* Inject it (update VMCB for injection by the hardware).
4018	*/
4019	Log4(("Injecting pending HM event\n"));
4020	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
4021	pVCpu->hm.s.Event.fPending = false;
4022
4023	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
4024	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
4025	else
4026	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
4027	}
4028	else
4029	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
4030
4031	/*
4032	* We could have injected an NMI through IEM and continue guest execution using
4033	* hardware-assisted SVM. In which case, we would not have any events pending (above)
4034	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
4035	*/
4036	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
4037	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
4038
4039	/*
4040	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
4041	*
4042	* For nested-guests: We need to update it too for the scenario where IEM executes
4043	* the nested-guest but execution later continues here with an interrupt shadow active.
4044	*/
4045	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
4046	}
4047
4048
4049	/**
4050	* Reports world-switch error and dumps some useful debug info.
4051	*
4052	* @param pVCpu The cross context virtual CPU structure.
4053	* @param rcVMRun The return code from VMRUN (or
4054	* VERR_SVM_INVALID_GUEST_STATE for invalid
4055	* guest-state).
4056	*/
4057	static void hmR0SvmReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun)
4058	{
4059	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4060	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4061	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4062
4063	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
4064	{
4065	#ifdef VBOX_STRICT
4066	hmR0DumpRegs(pVCpu);
4067	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
4068	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
4069	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
4070	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
4071	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
4072	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
4073	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
4074	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
4075	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
4076	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
4077	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
4078
4079	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
4080	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
4081	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
4082
4083	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
4084	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
4085	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
4086	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
4087	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
4088	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
4089	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
4090	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
4091	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
4092	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
4093	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
4094	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
4095
4096	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
4097	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
4098	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
4099	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
4100	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
4101	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
4102	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
4103	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
4104	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
4105	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
4106	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4107	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
4108	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
4109	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
4110	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
4111	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
4112	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
4113	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
4114	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
4115	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
4116
4117	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
4118
4119	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
4120	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
4121
4122	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
4123	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
4124	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
4125	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
4126	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
4127	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
4128	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
4129	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
4130	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
4131	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
4132	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
4133	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
4134	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
4135	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
4136	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
4137	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
4138	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
4139	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
4140	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
4141	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
4142
4143	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
4144	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
4145
4146	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
4147	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
4148	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
4149	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
4150
4151	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
4152	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
4153
4154	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
4155	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
4156	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
4157	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
4158
4159	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
4160	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
4161	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
4162	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
4163	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
4164	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
4165	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
4166
4167	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
4168	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
4169	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
4170	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
4171
4172	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
4173	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
4174	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
4175
4176	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
4177	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
4178	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
4179	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
4180	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
4181	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
4182	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
4183	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
4184	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
4185	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
4186	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
4187	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
4188
4189	NOREF(pVmcb);
4190	#endif /* VBOX_STRICT */
4191	}
4192	else
4193	Log4Func(("rcVMRun=%d\n", rcVMRun));
4194	}
4195
4196
4197	/**
4198	* Check per-VM and per-VCPU force flag actions that require us to go back to
4199	* ring-3 for one reason or another.
4200	*
4201	* @returns VBox status code (information status code included).
4202	* @retval VINF_SUCCESS if we don't have any actions that require going back to
4203	* ring-3.
4204	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
4205	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
4206	* interrupts)
4207	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
4208	* all EMTs to be in ring-3.
4209	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
4210	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
4211	* to the EM loop.
4212	*
4213	* @param pVCpu The cross context virtual CPU structure.
4214	*/
4215	static int hmR0SvmCheckForceFlags(PVMCPU pVCpu)
4216	{
4217	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4218	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
4219
4220	/* Could happen as a result of longjump. */
4221	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
4222	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
4223
4224	/* Update pending interrupts into the APIC's IRR. */
4225	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
4226	APICUpdatePendingInterrupts(pVCpu);
4227
4228	PVM pVM = pVCpu->CTX_SUFF(pVM);
4229	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
4230	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
4231	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
4232	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
4233	{
4234	/* Pending PGM C3 sync. */
4235	if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4236	{
4237	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
4238	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4239	if (rc != VINF_SUCCESS)
4240	{
4241	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4242	return rc;
4243	}
4244	}
4245
4246	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4247	/* -XXX- what was that about single stepping? */
4248	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
4249	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4250	{
4251	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4252	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
4253	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4254	return rc;
4255	}
4256
4257	/* Pending VM request packets, such as hardware interrupts. */
4258	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
4259	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
4260	{
4261	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4262	return VINF_EM_PENDING_REQUEST;
4263	}
4264
4265	/* Pending PGM pool flushes. */
4266	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4267	{
4268	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4269	return VINF_PGM_POOL_FLUSH_PENDING;
4270	}
4271
4272	/* Pending DMA requests. */
4273	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
4274	{
4275	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4276	return VINF_EM_RAW_TO_R3;
4277	}
4278	}
4279
4280	return VINF_SUCCESS;
4281	}
4282
4283
4284	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4285	/**
4286	* Does the preparations before executing nested-guest code in AMD-V.
4287	*
4288	* @returns VBox status code (informational status codes included).
4289	* @retval VINF_SUCCESS if we can proceed with running the guest.
4290	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4291	*
4292	* @param pVCpu The cross context virtual CPU structure.
4293	* @param pSvmTransient Pointer to the SVM transient structure.
4294	*
4295	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
4296	* @sa hmR0SvmPreRunGuest.
4297	*/
4298	static int hmR0SvmPreRunGuestNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4299	{
4300	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4301	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4302	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4303
4304	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4305	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx)) /* Redundant check to avoid unreachable code warning. */
4306	{
4307	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4308	return VINF_EM_RESCHEDULE_REM;
4309	}
4310	#endif
4311
4312	/* Check force flag actions that might require us to go back to ring-3. */
4313	int rc = hmR0SvmCheckForceFlags(pVCpu);
4314	if (rc != VINF_SUCCESS)
4315	return rc;
4316
4317	if (TRPMHasTrap(pVCpu))
4318	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4319	else if (!pVCpu->hm.s.Event.fPending)
4320	{
4321	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu);
4322	if ( rcStrict != VINF_SUCCESS
4323	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4324	return VBOXSTRICTRC_VAL(rcStrict);
4325	}
4326
4327	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4328
4329	/*
4330	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4331	* Just do it in software, see @bugref{8411}.
4332	* NB: If we could continue a task switch exit we wouldn't need to do this.
4333	*/
4334	PVM pVM = pVCpu->CTX_SUFF(pVM);
4335	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4336	&& pVCpu->hm.s.Event.fPending
4337	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4338	{
4339	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4340	}
4341
4342	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4343	Assert(!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4344	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4345	#endif
4346
4347	/*
4348	* Export the nested-guest state bits that are not shared with the host in any way as we
4349	* can longjmp or get preempted in the midst of exporting some of the state.
4350	*/
4351	rc = hmR0SvmExportGuestStateNested(pVCpu);
4352	AssertRCReturn(rc, rc);
4353	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4354
4355	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware-assisted SVM. */
4356	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4357
4358	/*
4359	* No longjmps to ring-3 from this point on!!!
4360	*
4361	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4362	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4363	*/
4364	VMMRZCallRing3Disable(pVCpu);
4365
4366	/*
4367	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4368	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4369	* preemption disabled for a while. Since this is purly to aid the
4370	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4371	* disable interrupt on NT.
4372	*
4373	* We need to check for force-flags that could've possible been altered since we last
4374	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4375	* see @bugref{6398}).
4376	*
4377	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4378	* to ring-3 before executing guest code.
4379	*/
4380	pSvmTransient->fEFlags = ASMIntDisableFlags();
4381	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4382	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4383	{
4384	ASMSetFlags(pSvmTransient->fEFlags);
4385	VMMRZCallRing3Enable(pVCpu);
4386	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4387	return VINF_EM_RAW_TO_R3;
4388	}
4389	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4390	{
4391	ASMSetFlags(pSvmTransient->fEFlags);
4392	VMMRZCallRing3Enable(pVCpu);
4393	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4394	return VINF_EM_RAW_INTERRUPT;
4395	}
4396	return VINF_SUCCESS;
4397	}
4398	#endif
4399
4400
4401	/**
4402	* Does the preparations before executing guest code in AMD-V.
4403	*
4404	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4405	* recompiler. We must be cautious what we do here regarding committing
4406	* guest-state information into the VMCB assuming we assuredly execute the guest
4407	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4408	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4409	* that the recompiler can (and should) use them when it resumes guest
4410	* execution. Otherwise such operations must be done when we can no longer
4411	* exit to ring-3.
4412	*
4413	* @returns VBox status code (informational status codes included).
4414	* @retval VINF_SUCCESS if we can proceed with running the guest.
4415	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4416	*
4417	* @param pVCpu The cross context virtual CPU structure.
4418	* @param pSvmTransient Pointer to the SVM transient structure.
4419	*/
4420	static int hmR0SvmPreRunGuest(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4421	{
4422	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4423	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4424
4425	/* Check force flag actions that might require us to go back to ring-3. */
4426	int rc = hmR0SvmCheckForceFlags(pVCpu);
4427	if (rc != VINF_SUCCESS)
4428	return rc;
4429
4430	if (TRPMHasTrap(pVCpu))
4431	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4432	else if (!pVCpu->hm.s.Event.fPending)
4433	hmR0SvmEvaluatePendingEvent(pVCpu);
4434
4435	/*
4436	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4437	* Just do it in software, see @bugref{8411}.
4438	* NB: If we could continue a task switch exit we wouldn't need to do this.
4439	*/
4440	PVM pVM = pVCpu->CTX_SUFF(pVM);
4441	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4442	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4443	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4444
4445	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4446	Assert(!(pVCpu->cpum.GstCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4447	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4448	#endif
4449
4450	/*
4451	* Export the guest state bits that are not shared with the host in any way as we can
4452	* longjmp or get preempted in the midst of exporting some of the state.
4453	*/
4454	rc = hmR0SvmExportGuestState(pVCpu);
4455	AssertRCReturn(rc, rc);
4456	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4457
4458	/*
4459	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4460	* world-switch so we can update it on the way back if the guest changed the TPR.
4461	*/
4462	if (pVCpu->hm.s.svm.fSyncVTpr)
4463	{
4464	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4465	if (pVM->hm.s.fTPRPatchingActive)
4466	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4467	else
4468	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4469	}
4470
4471	/*
4472	* No longjmps to ring-3 from this point on!!!
4473	*
4474	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4475	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4476	*/
4477	VMMRZCallRing3Disable(pVCpu);
4478
4479	/*
4480	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4481	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4482	* preemption disabled for a while. Since this is purly to aid the
4483	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4484	* disable interrupt on NT.
4485	*
4486	* We need to check for force-flags that could've possible been altered since we last
4487	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4488	* see @bugref{6398}).
4489	*
4490	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4491	* to ring-3 before executing guest code.
4492	*/
4493	pSvmTransient->fEFlags = ASMIntDisableFlags();
4494	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4495	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4496	{
4497	ASMSetFlags(pSvmTransient->fEFlags);
4498	VMMRZCallRing3Enable(pVCpu);
4499	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4500	return VINF_EM_RAW_TO_R3;
4501	}
4502	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4503	{
4504	ASMSetFlags(pSvmTransient->fEFlags);
4505	VMMRZCallRing3Enable(pVCpu);
4506	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4507	return VINF_EM_RAW_INTERRUPT;
4508	}
4509
4510	return VINF_SUCCESS;
4511	}
4512
4513
4514	/**
4515	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4516	* doing so.
4517	*
4518	* This means there is no backing out to ring-3 or anywhere else at this point.
4519	*
4520	* @param pVCpu The cross context virtual CPU structure.
4521	* @param pSvmTransient Pointer to the SVM transient structure.
4522	*
4523	* @remarks Called with preemption disabled.
4524	* @remarks No-long-jump zone!!!
4525	*/
4526	static void hmR0SvmPreRunGuestCommitted(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4527	{
4528	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4529	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4530	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4531
4532	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4533	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4534
4535	PVM pVM = pVCpu->CTX_SUFF(pVM);
4536	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4537
4538	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4539
4540	if (!CPUMIsGuestFPUStateActive(pVCpu))
4541	{
4542	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4543	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4544	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4545	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4546	}
4547
4548	/* Load the state shared between host and guest (FPU, debug). */
4549	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4550	hmR0SvmExportSharedState(pVCpu, pVmcb);
4551
4552	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4553	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4554
4555	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4556	RTCPUID const idHostCpu = pHostCpu->idCpu;
4557	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4558
4559	/* Setup TSC offsetting. */
4560	if ( pSvmTransient->fUpdateTscOffsetting
4561	\|\| fMigratedHostCpu)
4562	{
4563	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4564	pSvmTransient->fUpdateTscOffsetting = false;
4565	}
4566
4567	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4568	if (fMigratedHostCpu)
4569	pVmcb->ctrl.u32VmcbCleanBits = 0;
4570
4571	/* Store status of the shared guest-host state at the time of VMRUN. */
4572	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4573	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
4574	{
4575	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4576	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4577	}
4578	else
4579	#endif
4580	{
4581	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4582	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4583	}
4584
4585	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4586	uint8_t *pbMsrBitmap;
4587	if (!pSvmTransient->fIsNestedGuest)
4588	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4589	else
4590	{
4591	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4592
4593	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4594	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4595	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4596	}
4597	#else
4598	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4599	#endif
4600
4601	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4602	/* Flush the appropriate tagged-TLB entries. */
4603	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4604	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4605
4606	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4607
4608	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4609	to start executing. */
4610
4611	/*
4612	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4613	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4614	*
4615	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4616	*/
4617	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4618	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4619	{
4620	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4621	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4622	if (uGuestTscAux != pVCpu->hm.s.u64HostTscAux)
4623	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4624	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4625	pSvmTransient->fRestoreTscAuxMsr = true;
4626	}
4627	else
4628	{
4629	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4630	pSvmTransient->fRestoreTscAuxMsr = false;
4631	}
4632	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4633
4634	/*
4635	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4636	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4637	* from the VMCB.
4638	*/
4639	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu);
4640	if (!fSupportsVmcbCleanBits)
4641	pVmcb->ctrl.u32VmcbCleanBits = 0;
4642	}
4643
4644
4645	/**
4646	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4647	*
4648	* @returns VBox strict status code.
4649	* @param pVCpu The cross context virtual CPU structure.
4650	* @param HCPhysVmcb The host physical address of the VMCB.
4651	*
4652	* @remarks No-long-jump zone!!!
4653	*/
4654	DECLINLINE(int) hmR0SvmRunGuest(PVMCPU pVCpu, RTHCPHYS HCPhysVmcb)
4655	{
4656	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4657	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4658	pCtx->fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4659
4660	/*
4661	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4662	* floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4663	* callee-saved and thus the need for this XMM wrapper.
4664	*
4665	* Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4666	*/
4667	PVM pVM = pVCpu->CTX_SUFF(pVM);
4668	#ifdef VBOX_WITH_KERNEL_USING_XMM
4669	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu, pVCpu->hm.s.svm.pfnVMRun);
4670	#else
4671	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu);
4672	#endif
4673	}
4674
4675
4676	/**
4677	* Performs some essential restoration of state after running guest (or
4678	* nested-guest) code in AMD-V.
4679	*
4680	* @param pVCpu The cross context virtual CPU structure.
4681	* @param pSvmTransient Pointer to the SVM transient structure.
4682	* @param rcVMRun Return code of VMRUN.
4683	*
4684	* @remarks Called with interrupts disabled.
4685	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4686	* unconditionally when it is safe to do so.
4687	*/
4688	static void hmR0SvmPostRunGuest(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4689	{
4690	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4691
4692	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4693	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4694	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4695
4696	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4697	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4698
4699	/* TSC read must be done early for maximum accuracy. */
4700	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4701	{
4702	if (!pSvmTransient->fIsNestedGuest)
4703	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4704	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4705	else
4706	{
4707	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4708	uint64_t const uGstTsc = HMRemoveSvmNstGstTscOffset(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4709	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4710	}
4711	#endif
4712	}
4713
4714	if (pSvmTransient->fRestoreTscAuxMsr)
4715	{
4716	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4717	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4718	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4719	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4720	}
4721
4722	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4723	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4724	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4725
4726	Assert(!(ASMGetFlags() & X86_EFL_IF));
4727	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4728	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4729
4730	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4731	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4732	{
4733	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4734	return;
4735	}
4736
4737	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4738	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4739	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4740	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4741
4742	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4743	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4744	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4745	#else
4746	/*
4747	* Always import the following:
4748	*
4749	* - RIP for exit optimizations and evaluating event injection on re-entry.
4750	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4751	* state on preemption.
4752	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4753	* - CS for exit optimizations.
4754	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4755	* assembly switcher code.
4756	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4757	*/
4758	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4759	\| CPUMCTX_EXTRN_RFLAGS
4760	\| CPUMCTX_EXTRN_RAX
4761	\| CPUMCTX_EXTRN_RSP
4762	\| CPUMCTX_EXTRN_CS
4763	\| CPUMCTX_EXTRN_HWVIRT
4764	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4765	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4766	\| HMSVM_CPUMCTX_SHARED_STATE);
4767	#endif
4768
4769	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4770	&& pVCpu->hm.s.svm.fSyncVTpr)
4771	{
4772	Assert(!pSvmTransient->fIsNestedGuest);
4773	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4774	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
4775	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4776	{
4777	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4778	AssertRC(rc);
4779	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4780	}
4781	/* Sync TPR when we aren't intercepting CR8 writes. */
4782	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4783	{
4784	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4785	AssertRC(rc);
4786	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4787	}
4788	}
4789
4790	#ifdef DEBUG_ramshankar
4791	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4792	{
4793	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4794	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4795	0 /* uVerbose */);
4796	}
4797	#endif
4798
4799	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4800	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4801	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, uHostTsc);
4802	}
4803
4804
4805	/**
4806	* Runs the guest code using AMD-V.
4807	*
4808	* @returns VBox status code.
4809	* @param pVCpu The cross context virtual CPU structure.
4810	* @param pcLoops Pointer to the number of executed loops.
4811	*/
4812	static int hmR0SvmRunGuestCodeNormal(PVMCPU pVCpu, uint32_t *pcLoops)
4813	{
4814	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4815	Assert(pcLoops);
4816	Assert(*pcLoops <= cMaxResumeLoops);
4817
4818	SVMTRANSIENT SvmTransient;
4819	RT_ZERO(SvmTransient);
4820	SvmTransient.fUpdateTscOffsetting = true;
4821	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4822
4823	int rc = VERR_INTERNAL_ERROR_5;
4824	for (;;)
4825	{
4826	Assert(!HMR0SuspendPending());
4827	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4828
4829	/* Preparatory work for running nested-guest code, this may force us to return to
4830	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4831	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4832	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4833	if (rc != VINF_SUCCESS)
4834	break;
4835
4836	/*
4837	* No longjmps to ring-3 from this point on!!!
4838	*
4839	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4840	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4841	*/
4842	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4843	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4844
4845	/* Restore any residual host-state and save any bits shared between host and guest
4846	into the guest-CPU state. Re-enables interrupts! */
4847	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4848
4849	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4850	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4851	{
4852	if (rc == VINF_SUCCESS)
4853	rc = VERR_SVM_INVALID_GUEST_STATE;
4854	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4855	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4856	break;
4857	}
4858
4859	/* Handle the #VMEXIT. */
4860	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4861	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4862	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4863	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4864	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4865	if (rc != VINF_SUCCESS)
4866	break;
4867	if (++(*pcLoops) >= cMaxResumeLoops)
4868	{
4869	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4870	rc = VINF_EM_RAW_INTERRUPT;
4871	break;
4872	}
4873	}
4874
4875	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4876	return rc;
4877	}
4878
4879
4880	/**
4881	* Runs the guest code using AMD-V in single step mode.
4882	*
4883	* @returns VBox status code.
4884	* @param pVCpu The cross context virtual CPU structure.
4885	* @param pcLoops Pointer to the number of executed loops.
4886	*/
4887	static int hmR0SvmRunGuestCodeStep(PVMCPU pVCpu, uint32_t *pcLoops)
4888	{
4889	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4890	Assert(pcLoops);
4891	Assert(*pcLoops <= cMaxResumeLoops);
4892
4893	SVMTRANSIENT SvmTransient;
4894	RT_ZERO(SvmTransient);
4895	SvmTransient.fUpdateTscOffsetting = true;
4896	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4897
4898	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4899	uint16_t uCsStart = pCtx->cs.Sel;
4900	uint64_t uRipStart = pCtx->rip;
4901
4902	int rc = VERR_INTERNAL_ERROR_5;
4903	for (;;)
4904	{
4905	Assert(!HMR0SuspendPending());
4906	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4907	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4908	(unsigned)RTMpCpuId(), *pcLoops));
4909
4910	/* Preparatory work for running nested-guest code, this may force us to return to
4911	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4912	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4913	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4914	if (rc != VINF_SUCCESS)
4915	break;
4916
4917	/*
4918	* No longjmps to ring-3 from this point on!!!
4919	*
4920	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4921	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4922	*/
4923	VMMRZCallRing3Disable(pVCpu);
4924	VMMRZCallRing3RemoveNotification(pVCpu);
4925	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4926
4927	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4928
4929	/* Restore any residual host-state and save any bits shared between host and guest
4930	into the guest-CPU state. Re-enables interrupts! */
4931	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4932
4933	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4934	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4935	{
4936	if (rc == VINF_SUCCESS)
4937	rc = VERR_SVM_INVALID_GUEST_STATE;
4938	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4939	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4940	return rc;
4941	}
4942
4943	/* Handle the #VMEXIT. */
4944	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4945	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4946	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4947	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4948	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4949	if (rc != VINF_SUCCESS)
4950	break;
4951	if (++(*pcLoops) >= cMaxResumeLoops)
4952	{
4953	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4954	rc = VINF_EM_RAW_INTERRUPT;
4955	break;
4956	}
4957
4958	/*
4959	* Did the RIP change, if so, consider it a single step.
4960	* Otherwise, make sure one of the TFs gets set.
4961	*/
4962	if ( pCtx->rip != uRipStart
4963	\|\| pCtx->cs.Sel != uCsStart)
4964	{
4965	rc = VINF_EM_DBG_STEPPED;
4966	break;
4967	}
4968	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4969	}
4970
4971	/*
4972	* Clear the X86_EFL_TF if necessary.
4973	*/
4974	if (pVCpu->hm.s.fClearTrapFlag)
4975	{
4976	pVCpu->hm.s.fClearTrapFlag = false;
4977	pCtx->eflags.Bits.u1TF = 0;
4978	}
4979
4980	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4981	return rc;
4982	}
4983
4984	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4985	/**
4986	* Runs the nested-guest code using AMD-V.
4987	*
4988	* @returns VBox status code.
4989	* @param pVCpu The cross context virtual CPU structure.
4990	* @param pcLoops Pointer to the number of executed loops. If we're switching
4991	* from the guest-code execution loop to this nested-guest
4992	* execution loop pass the remainder value, else pass 0.
4993	*/
4994	static int hmR0SvmRunGuestCodeNested(PVMCPU pVCpu, uint32_t *pcLoops)
4995	{
4996	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4997	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4998	Assert(pcLoops);
4999	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops);
5000
5001	SVMTRANSIENT SvmTransient;
5002	RT_ZERO(SvmTransient);
5003	SvmTransient.fUpdateTscOffsetting = true;
5004	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
5005	SvmTransient.fIsNestedGuest = true;
5006
5007	int rc = VERR_INTERNAL_ERROR_4;
5008	for (;;)
5009	{
5010	Assert(!HMR0SuspendPending());
5011	HMSVM_ASSERT_CPU_SAFE(pVCpu);
5012
5013	/* Preparatory work for running nested-guest code, this may force us to return to
5014	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
5015	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
5016	rc = hmR0SvmPreRunGuestNested(pVCpu, &SvmTransient);
5017	if ( rc != VINF_SUCCESS
5018	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
5019	{
5020	break;
5021	}
5022
5023	/*
5024	* No longjmps to ring-3 from this point on!!!
5025	*
5026	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
5027	* better than a kernel panic. This also disables flushing of the R0-logger instance.
5028	*/
5029	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
5030
5031	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
5032
5033	/* Restore any residual host-state and save any bits shared between host and guest
5034	into the guest-CPU state. Re-enables interrupts! */
5035	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
5036
5037	if (RT_LIKELY( rc == VINF_SUCCESS
5038	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
5039	{ /* extremely likely */ }
5040	else
5041	{
5042	/* VMRUN failed, shouldn't really happen, Guru. */
5043	if (rc != VINF_SUCCESS)
5044	break;
5045
5046	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
5047	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
5048	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
5049	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
5050	break;
5051	}
5052
5053	/* Handle the #VMEXIT. */
5054	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
5055	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
5056	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
5057	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
5058	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
5059	if ( rc != VINF_SUCCESS
5060	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
5061	break;
5062	if (++(*pcLoops) >= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
5063	{
5064	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
5065	rc = VINF_EM_RAW_INTERRUPT;
5066	break;
5067	}
5068
5069	/** @todo handle single-stepping */
5070	}
5071
5072	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
5073	return rc;
5074	}
5075	#endif
5076
5077
5078	/**
5079	* Runs the guest code using AMD-V.
5080	*
5081	* @returns Strict VBox status code.
5082	* @param pVCpu The cross context virtual CPU structure.
5083	*/
5084	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPU pVCpu)
5085	{
5086	Assert(VMMRZCallRing3IsEnabled(pVCpu));
5087	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
5088	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, NULL /* pvUser */);
5089
5090	uint32_t cLoops = 0;
5091	int rc;
5092	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5093	if (!CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
5094	#endif
5095	{
5096	if (!pVCpu->hm.s.fSingleInstruction)
5097	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
5098	else
5099	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
5100	}
5101	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5102	else
5103	{
5104	rc = VINF_SVM_VMRUN;
5105	}
5106
5107	/* Re-check the nested-guest condition here as we may be transitioning from the normal
5108	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
5109	if (rc == VINF_SVM_VMRUN)
5110	{
5111	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
5112	if (rc == VINF_SVM_VMEXIT)
5113	rc = VINF_SUCCESS;
5114	}
5115	#endif
5116
5117	/* Fixup error codes. */
5118	if (rc == VERR_EM_INTERPRETER)
5119	rc = VINF_EM_RAW_EMULATE_INSTR;
5120	else if (rc == VINF_EM_RESET)
5121	rc = VINF_EM_TRIPLE_FAULT;
5122
5123	/* Prepare to return to ring-3. This will remove longjmp notifications. */
5124	rc = hmR0SvmExitToRing3(pVCpu, rc);
5125	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
5126	return rc;
5127	}
5128
5129
5130	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5131	/**
5132	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
5133	*
5134	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
5135	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
5136	*/
5137	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
5138	{
5139	const uint16_t u16Port = pIoExitInfo->n.u16Port;
5140	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
5141	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
5142	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
5143	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
5144	const bool fRep = pIoExitInfo->n.u1Rep;
5145	const bool fStrIo = pIoExitInfo->n.u1Str;
5146
5147	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
5148	NULL /* pIoExitInfo */);
5149	}
5150
5151
5152	/**
5153	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
5154	* SVM_EXIT_INVALID).
5155	*
5156	* @returns VBox status code (informational status codes included).
5157	* @param pVCpu The cross context virtual CPU structure.
5158	* @param pSvmTransient Pointer to the SVM transient structure.
5159	*/
5160	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5161	{
5162	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
5163	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5164	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5165
5166	/*
5167	* We import the complete state here because we use separate VMCBs for the guest and the
5168	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
5169	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
5170	*/
5171	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5172	do { \
5173	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5174	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2))); \
5175	} while (0)
5176
5177	/*
5178	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
5179	* nested-guest. If it isn't, it should be handled by the (outer) guest.
5180	*/
5181	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
5182	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5183	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5184	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5185	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5186
5187	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5188	switch (uExitCode)
5189	{
5190	case SVM_EXIT_CPUID:
5191	{
5192	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
5193	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5194	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
5195	}
5196
5197	case SVM_EXIT_RDTSC:
5198	{
5199	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
5200	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5201	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
5202	}
5203
5204	case SVM_EXIT_RDTSCP:
5205	{
5206	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
5207	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5208	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
5209	}
5210
5211	case SVM_EXIT_MONITOR:
5212	{
5213	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
5214	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5215	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
5216	}
5217
5218	case SVM_EXIT_MWAIT:
5219	{
5220	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
5221	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5222	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
5223	}
5224
5225	case SVM_EXIT_HLT:
5226	{
5227	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_HLT))
5228	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5229	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
5230	}
5231
5232	case SVM_EXIT_MSR:
5233	{
5234	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
5235	{
5236	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
5237	uint16_t offMsrpm;
5238	uint8_t uMsrpmBit;
5239	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5240	if (RT_SUCCESS(rc))
5241	{
5242	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
5243	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
5244
5245	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5246	pbMsrBitmap += offMsrpm;
5247	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
5248	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
5249
5250	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5251	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5252	{
5253	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5254	}
5255	}
5256	else
5257	{
5258	/*
5259	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5260	* See AMD-V spec. "15.11 MSR Intercepts".
5261	*/
5262	Assert(rc == VERR_OUT_OF_RANGE);
5263	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5264	}
5265	}
5266	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
5267	}
5268
5269	case SVM_EXIT_IOIO:
5270	{
5271	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
5272	{
5273	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
5274	SVMIOIOEXITINFO IoExitInfo;
5275	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5276	bool const fIntercept = hmR0SvmIsIoInterceptSet(pvIoBitmap, &IoExitInfo);
5277	if (fIntercept)
5278	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5279	}
5280	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
5281	}
5282
5283	case SVM_EXIT_XCPT_PF:
5284	{
5285	PVM pVM = pVCpu->CTX_SUFF(pVM);
5286	if (pVM->hm.s.fNestedPaging)
5287	{
5288	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5289	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5290
5291	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5292	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_PF))
5293	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5294
5295	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
5296	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5297	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
5298	return VINF_SUCCESS;
5299	}
5300	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
5301	}
5302
5303	case SVM_EXIT_XCPT_UD:
5304	{
5305	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_UD))
5306	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5307	hmR0SvmSetPendingXcptUD(pVCpu);
5308	return VINF_SUCCESS;
5309	}
5310
5311	case SVM_EXIT_XCPT_MF:
5312	{
5313	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_MF))
5314	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5315	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
5316	}
5317
5318	case SVM_EXIT_XCPT_DB:
5319	{
5320	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_DB))
5321	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5322	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
5323	}
5324
5325	case SVM_EXIT_XCPT_AC:
5326	{
5327	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_AC))
5328	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5329	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
5330	}
5331
5332	case SVM_EXIT_XCPT_BP:
5333	{
5334	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_BP))
5335	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5336	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
5337	}
5338
5339	case SVM_EXIT_READ_CR0:
5340	case SVM_EXIT_READ_CR3:
5341	case SVM_EXIT_READ_CR4:
5342	{
5343	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5344	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, uCr))
5345	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5346	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5347	}
5348
5349	case SVM_EXIT_CR0_SEL_WRITE:
5350	{
5351	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5352	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5353	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5354	}
5355
5356	case SVM_EXIT_WRITE_CR0:
5357	case SVM_EXIT_WRITE_CR3:
5358	case SVM_EXIT_WRITE_CR4:
5359	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5360	{
5361	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5362	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5363
5364	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, uCr))
5365	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5366	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5367	}
5368
5369	case SVM_EXIT_PAUSE:
5370	{
5371	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_PAUSE))
5372	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5373	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5374	}
5375
5376	case SVM_EXIT_VINTR:
5377	{
5378	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VINTR))
5379	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5380	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5381	}
5382
5383	case SVM_EXIT_INTR:
5384	case SVM_EXIT_NMI:
5385	case SVM_EXIT_SMI:
5386	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5387	{
5388	/*
5389	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5390	*
5391	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5392	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5393	* nested-guest #VMEXIT.
5394	*
5395	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5396	* while trying to inject interrupts, see comment at the top of this function.
5397	*/
5398	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5399	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5400	}
5401
5402	case SVM_EXIT_FERR_FREEZE:
5403	{
5404	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5405	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5406	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5407	}
5408
5409	case SVM_EXIT_INVLPG:
5410	{
5411	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
5412	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5413	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5414	}
5415
5416	case SVM_EXIT_WBINVD:
5417	{
5418	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_WBINVD))
5419	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5420	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5421	}
5422
5423	case SVM_EXIT_INVD:
5424	{
5425	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVD))
5426	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5427	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5428	}
5429
5430	case SVM_EXIT_RDPMC:
5431	{
5432	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
5433	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5434	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5435	}
5436
5437	default:
5438	{
5439	switch (uExitCode)
5440	{
5441	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5442	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5443	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5444	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5445	{
5446	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5447	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, uDr))
5448	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5449	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5450	}
5451
5452	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5453	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5454	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5455	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5456	{
5457	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5458	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, uDr))
5459	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5460	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5461	}
5462
5463	case SVM_EXIT_XCPT_DE:
5464	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5465	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5466	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5467	case SVM_EXIT_XCPT_OF:
5468	case SVM_EXIT_XCPT_BR:
5469	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5470	case SVM_EXIT_XCPT_NM:
5471	case SVM_EXIT_XCPT_DF:
5472	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5473	case SVM_EXIT_XCPT_TS:
5474	case SVM_EXIT_XCPT_NP:
5475	case SVM_EXIT_XCPT_SS:
5476	case SVM_EXIT_XCPT_GP:
5477	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5478	case SVM_EXIT_XCPT_15: /* Reserved. */
5479	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5480	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5481	case SVM_EXIT_XCPT_MC:
5482	case SVM_EXIT_XCPT_XF:
5483	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5484	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5485	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5486	{
5487	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5488	if (HMIsGuestSvmXcptInterceptSet(pVCpu, uVector))
5489	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5490	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5491	}
5492
5493	case SVM_EXIT_XSETBV:
5494	{
5495	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
5496	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5497	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5498	}
5499
5500	case SVM_EXIT_TASK_SWITCH:
5501	{
5502	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5503	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5504	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5505	}
5506
5507	case SVM_EXIT_IRET:
5508	{
5509	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_IRET))
5510	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5511	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5512	}
5513
5514	case SVM_EXIT_SHUTDOWN:
5515	{
5516	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_SHUTDOWN))
5517	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5518	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5519	}
5520
5521	case SVM_EXIT_VMMCALL:
5522	{
5523	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
5524	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5525	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5526	}
5527
5528	case SVM_EXIT_CLGI:
5529	{
5530	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
5531	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5532	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5533	}
5534
5535	case SVM_EXIT_STGI:
5536	{
5537	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_STGI))
5538	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5539	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5540	}
5541
5542	case SVM_EXIT_VMLOAD:
5543	{
5544	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
5545	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5546	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5547	}
5548
5549	case SVM_EXIT_VMSAVE:
5550	{
5551	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
5552	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5553	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5554	}
5555
5556	case SVM_EXIT_INVLPGA:
5557	{
5558	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
5559	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5560	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5561	}
5562
5563	case SVM_EXIT_VMRUN:
5564	{
5565	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
5566	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5567	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5568	}
5569
5570	case SVM_EXIT_RSM:
5571	{
5572	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RSM))
5573	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5574	hmR0SvmSetPendingXcptUD(pVCpu);
5575	return VINF_SUCCESS;
5576	}
5577
5578	case SVM_EXIT_SKINIT:
5579	{
5580	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
5581	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5582	hmR0SvmSetPendingXcptUD(pVCpu);
5583	return VINF_SUCCESS;
5584	}
5585
5586	case SVM_EXIT_NPF:
5587	{
5588	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5589	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5590	}
5591
5592	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5593	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5594
5595	default:
5596	{
5597	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5598	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5599	return VERR_SVM_UNKNOWN_EXIT;
5600	}
5601	}
5602	}
5603	}
5604	/* not reached */
5605
5606	#undef NST_GST_VMEXIT_CALL_RET
5607	}
5608	#endif
5609
5610
5611	/**
5612	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5613	*
5614	* @returns VBox status code (informational status codes included).
5615	* @param pVCpu The cross context virtual CPU structure.
5616	* @param pSvmTransient Pointer to the SVM transient structure.
5617	*/
5618	static int hmR0SvmHandleExit(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5619	{
5620	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5621	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5622
5623	#ifdef DEBUG_ramshankar
5624	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5625	do { \
5626	if ((a_fDbg) == 1) \
5627	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5628	int rc = a_CallExpr; \
5629	if ((a_fDbg) == 1) \
5630	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5631	return rc; \
5632	} while (0)
5633	#else
5634	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5635	#endif
5636
5637	/*
5638	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5639	* for most guests under normal workloads (for some definition of "normal").
5640	*/
5641	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5642	switch (uExitCode)
5643	{
5644	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5645	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5646	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5647	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5648	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5649	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5650	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5651	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5652	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5653	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5654
5655	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5656	case SVM_EXIT_INTR:
5657	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5658
5659	case SVM_EXIT_READ_CR0:
5660	case SVM_EXIT_READ_CR3:
5661	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5662
5663	case SVM_EXIT_CR0_SEL_WRITE:
5664	case SVM_EXIT_WRITE_CR0:
5665	case SVM_EXIT_WRITE_CR3:
5666	case SVM_EXIT_WRITE_CR4:
5667	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5668
5669	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5670	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5671	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5672	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5673	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5674	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5675	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5676	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5677	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5678	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5679	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5680	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5681	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5682	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5683	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5684	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5685
5686	default:
5687	{
5688	switch (pSvmTransient->u64ExitCode)
5689	{
5690	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5691	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5692	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5693	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5694	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5695
5696	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5697	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5698	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5699	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5700	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5701
5702	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5703	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5704
5705	case SVM_EXIT_SMI:
5706	case SVM_EXIT_INIT:
5707	{
5708	/*
5709	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5710	* If it ever does, we want to know about it so log the exit code and bail.
5711	*/
5712	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5713	}
5714
5715	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5716	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5717	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5718	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5719	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5720	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5721	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5722	#else
5723	case SVM_EXIT_CLGI:
5724	case SVM_EXIT_STGI:
5725	case SVM_EXIT_VMLOAD:
5726	case SVM_EXIT_VMSAVE:
5727	case SVM_EXIT_INVLPGA:
5728	case SVM_EXIT_VMRUN:
5729	#endif
5730	case SVM_EXIT_RSM:
5731	case SVM_EXIT_SKINIT:
5732	{
5733	hmR0SvmSetPendingXcptUD(pVCpu);
5734	return VINF_SUCCESS;
5735	}
5736
5737	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5738	case SVM_EXIT_XCPT_DE:
5739	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5740	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5741	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5742	case SVM_EXIT_XCPT_OF:
5743	case SVM_EXIT_XCPT_BR:
5744	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5745	case SVM_EXIT_XCPT_NM:
5746	case SVM_EXIT_XCPT_DF:
5747	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5748	case SVM_EXIT_XCPT_TS:
5749	case SVM_EXIT_XCPT_NP:
5750	case SVM_EXIT_XCPT_SS:
5751	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5752	/* SVM_EXIT_XCPT_PF: */
5753	case SVM_EXIT_XCPT_15: /* Reserved. */
5754	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5755	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5756	case SVM_EXIT_XCPT_MC:
5757	case SVM_EXIT_XCPT_XF:
5758	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5759	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5760	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5761	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5762	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5763
5764	default:
5765	{
5766	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5767	pVCpu->hm.s.u32HMError = uExitCode;
5768	return VERR_SVM_UNKNOWN_EXIT;
5769	}
5770	}
5771	}
5772	}
5773	/* not reached */
5774	#undef VMEXIT_CALL_RET
5775	}
5776
5777
5778	#ifdef VBOX_STRICT
5779	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5780	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5781	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5782
5783	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5784	do \
5785	{ \
5786	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5787	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5788	} while (0)
5789
5790	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5791	do { \
5792	AssertPtr((a_pVCpu)); \
5793	AssertPtr((a_pSvmTransient)); \
5794	Assert(ASMIntAreEnabled()); \
5795	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5796	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5797	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5798	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5799	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5800	HMSVM_ASSERT_PREEMPT_CPUID(); \
5801	} while (0)
5802	#else
5803	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5804	do { \
5805	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5806	} while (0)
5807	#endif
5808
5809
5810	/**
5811	* Gets the IEM exception flags for the specified SVM event.
5812	*
5813	* @returns The IEM exception flags.
5814	* @param pEvent Pointer to the SVM event.
5815	*
5816	* @remarks This function currently only constructs flags required for
5817	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5818	* and CR2 aspects of an exception are not included).
5819	*/
5820	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5821	{
5822	uint8_t const uEventType = pEvent->n.u3Type;
5823	uint32_t fIemXcptFlags;
5824	switch (uEventType)
5825	{
5826	case SVM_EVENT_EXCEPTION:
5827	/*
5828	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5829	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5830	*/
5831	if (pEvent->n.u8Vector == X86_XCPT_BP)
5832	{
5833	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5834	break;
5835	}
5836	if (pEvent->n.u8Vector == X86_XCPT_OF)
5837	{
5838	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5839	break;
5840	}
5841	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5842	RT_FALL_THRU();
5843	case SVM_EVENT_NMI:
5844	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5845	break;
5846
5847	case SVM_EVENT_EXTERNAL_IRQ:
5848	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5849	break;
5850
5851	case SVM_EVENT_SOFTWARE_INT:
5852	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5853	break;
5854
5855	default:
5856	fIemXcptFlags = 0;
5857	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5858	break;
5859	}
5860	return fIemXcptFlags;
5861	}
5862
5863
5864	/**
5865	* Handle a condition that occurred while delivering an event through the guest
5866	* IDT.
5867	*
5868	* @returns VBox status code (informational error codes included).
5869	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5870	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5871	* continue execution of the guest which will delivery the \#DF.
5872	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5873	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5874	*
5875	* @param pVCpu The cross context virtual CPU structure.
5876	* @param pSvmTransient Pointer to the SVM transient structure.
5877	*
5878	* @remarks No-long-jump zone!!!
5879	*/
5880	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5881	{
5882	int rc = VINF_SUCCESS;
5883	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5884	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5885
5886	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5887	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5888	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5889
5890	/*
5891	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5892	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5893	*
5894	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5895	*/
5896	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5897	{
5898	IEMXCPTRAISE enmRaise;
5899	IEMXCPTRAISEINFO fRaiseInfo;
5900	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5901	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5902	if (fExitIsHwXcpt)
5903	{
5904	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5905	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5906	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5907	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5908	}
5909	else
5910	{
5911	/*
5912	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5913	* then we end up here.
5914	*
5915	* If the event was:
5916	* - a software interrupt, we can re-execute the instruction which will
5917	* regenerate the event.
5918	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5919	* - a hardware exception or external interrupt, we re-inject it.
5920	*/
5921	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5922	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5923	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5924	else
5925	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5926	}
5927
5928	switch (enmRaise)
5929	{
5930	case IEMXCPTRAISE_CURRENT_XCPT:
5931	case IEMXCPTRAISE_PREV_EVENT:
5932	{
5933	/* For software interrupts, we shall re-execute the instruction. */
5934	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5935	{
5936	RTGCUINTPTR GCPtrFaultAddress = 0;
5937
5938	/* If we are re-injecting an NMI, clear NMI blocking. */
5939	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5940	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5941
5942	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5943	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5944	{
5945	pSvmTransient->fVectoringPF = true;
5946	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5947	pVCpu->cpum.GstCtx.cr2));
5948	}
5949	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5950	&& uIdtVector == X86_XCPT_PF)
5951	{
5952	/*
5953	* If the previous exception was a #PF, we need to recover the CR2 value.
5954	* This can't happen with shadow paging.
5955	*/
5956	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5957	}
5958
5959	/*
5960	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5961	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5962	*/
5963	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5964	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5965	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5966
5967	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5968	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5969	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5970	}
5971	break;
5972	}
5973
5974	case IEMXCPTRAISE_REEXEC_INSTR:
5975	{
5976	Assert(rc == VINF_SUCCESS);
5977	break;
5978	}
5979
5980	case IEMXCPTRAISE_DOUBLE_FAULT:
5981	{
5982	/*
5983	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5984	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5985	* converted into a #DF.
5986	*/
5987	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5988	{
5989	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5990	pSvmTransient->fVectoringDoublePF = true;
5991	Assert(rc == VINF_SUCCESS);
5992	}
5993	else
5994	{
5995	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5996	hmR0SvmSetPendingXcptDF(pVCpu);
5997	rc = VINF_HM_DOUBLE_FAULT;
5998	}
5999	break;
6000	}
6001
6002	case IEMXCPTRAISE_TRIPLE_FAULT:
6003	{
6004	rc = VINF_EM_RESET;
6005	break;
6006	}
6007
6008	case IEMXCPTRAISE_CPU_HANG:
6009	{
6010	rc = VERR_EM_GUEST_CPU_HANG;
6011	break;
6012	}
6013
6014	default:
6015	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
6016	}
6017	}
6018	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6019	return rc;
6020	}
6021
6022
6023	/**
6024	* Advances the guest RIP by the number of bytes specified in @a cb.
6025	*
6026	* @param pVCpu The cross context virtual CPU structure.
6027	* @param cb RIP increment value in bytes.
6028	*/
6029	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPU pVCpu, uint32_t cb)
6030	{
6031	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6032	pCtx->rip += cb;
6033
6034	/* Update interrupt shadow. */
6035	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
6036	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
6037	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6038	}
6039
6040
6041	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6042	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6043	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6044
6045	/** @name \#VMEXIT handlers.
6046	* @{
6047	*/
6048
6049	/**
6050	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6051	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6052	*/
6053	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6054	{
6055	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6056
6057	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6058	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6059	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6060	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6061
6062	/*
6063	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
6064	* signal -before- the timer fires if the current interrupt is our own timer or a some
6065	* other host interrupt. We also cannot examine what interrupt it is until the host
6066	* actually take the interrupt.
6067	*
6068	* Going back to executing guest code here unconditionally causes random scheduling
6069	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6070	*/
6071	return VINF_EM_RAW_INTERRUPT;
6072	}
6073
6074
6075	/**
6076	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6077	*/
6078	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6079	{
6080	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6081
6082	VBOXSTRICTRC rcStrict;
6083	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6084	if (fSupportsNextRipSave)
6085	{
6086	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6087	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6088	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6089	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
6090	}
6091	else
6092	{
6093	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6094	rcStrict = IEMExecOne(pVCpu);
6095	}
6096
6097	if (rcStrict == VINF_IEM_RAISED_XCPT)
6098	{
6099	rcStrict = VINF_SUCCESS;
6100	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6101	}
6102	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6103	return VBOXSTRICTRC_TODO(rcStrict);
6104	}
6105
6106
6107	/**
6108	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6109	*/
6110	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6111	{
6112	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6113
6114	VBOXSTRICTRC rcStrict;
6115	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6116	if (fSupportsNextRipSave)
6117	{
6118	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6119	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6120	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6121	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
6122	}
6123	else
6124	{
6125	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6126	rcStrict = IEMExecOne(pVCpu);
6127	}
6128
6129	if (rcStrict == VINF_IEM_RAISED_XCPT)
6130	{
6131	rcStrict = VINF_SUCCESS;
6132	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6133	}
6134	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6135	return VBOXSTRICTRC_TODO(rcStrict);
6136	}
6137
6138
6139	/**
6140	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6141	*/
6142	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6143	{
6144	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6145
6146	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
6147	VBOXSTRICTRC rcStrict;
6148	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6149	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
6150	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6151	if (!pExitRec)
6152	{
6153	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6154	if (fSupportsNextRipSave)
6155	{
6156	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6157	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6158	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
6159	}
6160	else
6161	{
6162	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6163	rcStrict = IEMExecOne(pVCpu);
6164	}
6165
6166	if (rcStrict == VINF_IEM_RAISED_XCPT)
6167	{
6168	rcStrict = VINF_SUCCESS;
6169	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6170	}
6171	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6172	}
6173	else
6174	{
6175	/*
6176	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6177	*/
6178	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6179
6180	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
6181	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
6182
6183	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6184
6185	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6186	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6187	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6188	}
6189	return VBOXSTRICTRC_TODO(rcStrict);
6190	}
6191
6192
6193	/**
6194	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6195	*/
6196	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6197	{
6198	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6199
6200	VBOXSTRICTRC rcStrict;
6201	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6202	if (fSupportsNextRipSave)
6203	{
6204	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6205	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6206	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6207	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
6208	}
6209	else
6210	{
6211	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6212	rcStrict = IEMExecOne(pVCpu);
6213	}
6214
6215	if (rcStrict == VINF_SUCCESS)
6216	pSvmTransient->fUpdateTscOffsetting = true;
6217	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6218	{
6219	rcStrict = VINF_SUCCESS;
6220	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6221	}
6222	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6223	return VBOXSTRICTRC_TODO(rcStrict);
6224	}
6225
6226
6227	/**
6228	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6229	*/
6230	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6231	{
6232	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6233
6234	VBOXSTRICTRC rcStrict;
6235	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6236	if (fSupportsNextRipSave)
6237	{
6238	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
6239	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6240	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6241	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
6242	}
6243	else
6244	{
6245	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6246	rcStrict = IEMExecOne(pVCpu);
6247	}
6248
6249	if (rcStrict == VINF_SUCCESS)
6250	pSvmTransient->fUpdateTscOffsetting = true;
6251	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6252	{
6253	rcStrict = VINF_SUCCESS;
6254	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6255	}
6256	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6257	return VBOXSTRICTRC_TODO(rcStrict);
6258	}
6259
6260
6261	/**
6262	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6263	*/
6264	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6265	{
6266	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6267
6268	VBOXSTRICTRC rcStrict;
6269	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6270	if (fSupportsNextRipSave)
6271	{
6272	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6273	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6274	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6275	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
6276	}
6277	else
6278	{
6279	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6280	rcStrict = IEMExecOne(pVCpu);
6281	}
6282
6283	if (rcStrict == VINF_IEM_RAISED_XCPT)
6284	{
6285	rcStrict = VINF_SUCCESS;
6286	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6287	}
6288	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6289	return VBOXSTRICTRC_TODO(rcStrict);
6290	}
6291
6292
6293	/**
6294	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6295	*/
6296	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6297	{
6298	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6299	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6300
6301	VBOXSTRICTRC rcStrict;
6302	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6303	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6304	if ( fSupportsDecodeAssists
6305	&& fSupportsNextRipSave)
6306	{
6307	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
6308	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6309	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6310	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6311	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6312	}
6313	else
6314	{
6315	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6316	rcStrict = IEMExecOne(pVCpu);
6317	}
6318
6319	if (rcStrict == VINF_IEM_RAISED_XCPT)
6320	{
6321	rcStrict = VINF_SUCCESS;
6322	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6323	}
6324	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6325	return VBOXSTRICTRC_VAL(rcStrict);
6326	}
6327
6328
6329	/**
6330	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6331	*/
6332	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6333	{
6334	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6335
6336	VBOXSTRICTRC rcStrict;
6337	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6338	if (fSupportsNextRipSave)
6339	{
6340	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6341	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6342	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6343	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6344	}
6345	else
6346	{
6347	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6348	rcStrict = IEMExecOne(pVCpu);
6349	}
6350
6351	if ( rcStrict == VINF_EM_HALT
6352	\|\| rcStrict == VINF_SUCCESS)
6353	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6354	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6355	{
6356	rcStrict = VINF_SUCCESS;
6357	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6358	}
6359	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6360	if (rcStrict != VINF_SUCCESS)
6361	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6362	return VBOXSTRICTRC_VAL(rcStrict);;
6363	}
6364
6365
6366	/**
6367	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6368	*/
6369	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6370	{
6371	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6372
6373	/*
6374	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6375	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6376	* segment override prefix or other prefixes might be used, in which case we fallback to
6377	* IEMExecOne() to figure out.
6378	*/
6379	VBOXSTRICTRC rcStrict;
6380	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6381	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6382	if (cbInstr)
6383	{
6384	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6385	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6386	}
6387	else
6388	{
6389	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6390	rcStrict = IEMExecOne(pVCpu);
6391	}
6392
6393	if (rcStrict == VINF_IEM_RAISED_XCPT)
6394	{
6395	rcStrict = VINF_SUCCESS;
6396	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6397	}
6398	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6399	return VBOXSTRICTRC_TODO(rcStrict);
6400	}
6401
6402
6403	/**
6404	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6405	*/
6406	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6407	{
6408	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6409
6410	VBOXSTRICTRC rcStrict;
6411	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6412	if (fSupportsNextRipSave)
6413	{
6414	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6415	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6416	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6417	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6418	}
6419	else
6420	{
6421	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6422	rcStrict = IEMExecOne(pVCpu);
6423	}
6424
6425	if ( rcStrict == VINF_EM_HALT
6426	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6427	rcStrict = VINF_SUCCESS;
6428	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6429	{
6430	rcStrict = VINF_SUCCESS;
6431	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6432	}
6433	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6434	return VBOXSTRICTRC_TODO(rcStrict);
6435	}
6436
6437
6438	/**
6439	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6440	* \#VMEXIT.
6441	*/
6442	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6443	{
6444	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6445	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6446	return VINF_EM_RESET;
6447	}
6448
6449
6450	/**
6451	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6452	*/
6453	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6454	{
6455	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6456	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6457	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6458	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6459	RT_NOREF(pVmcb);
6460	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6461	return VERR_SVM_UNEXPECTED_EXIT;
6462	}
6463
6464
6465	/**
6466	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6467	*/
6468	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6469	{
6470	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6471
6472	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6473	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6474	#ifdef VBOX_WITH_STATISTICS
6475	switch (pSvmTransient->u64ExitCode)
6476	{
6477	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6478	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6479	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6480	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6481	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6482	}
6483	#endif
6484
6485	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6486	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6487	if ( fSupportsDecodeAssists
6488	&& fSupportsNextRipSave)
6489	{
6490	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6491	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6492	if (fMovCRx)
6493	{
6494	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6495	\| CPUMCTX_EXTRN_APIC_TPR);
6496	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6497	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6498	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6499	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6500	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6501	return VBOXSTRICTRC_VAL(rcStrict);
6502	}
6503	/* else: SMSW instruction, fall back below to IEM for this. */
6504	}
6505
6506	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6507	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6508	AssertMsg( rcStrict == VINF_SUCCESS
6509	\|\| rcStrict == VINF_PGM_SYNC_CR3
6510	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6511	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6512	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6513	if (rcStrict == VINF_IEM_RAISED_XCPT)
6514	{
6515	rcStrict = VINF_SUCCESS;
6516	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6517	}
6518	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6519	return VBOXSTRICTRC_TODO(rcStrict);
6520	}
6521
6522
6523	/**
6524	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6525	*/
6526	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6527	{
6528	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6529
6530	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6531	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6532	Assert(iCrReg <= 15);
6533
6534	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6535	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6536	bool fDecodedInstr = false;
6537	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6538	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6539	if ( fSupportsDecodeAssists
6540	&& fSupportsNextRipSave)
6541	{
6542	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6543	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6544	if (fMovCRx)
6545	{
6546	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6547	\| CPUMCTX_EXTRN_APIC_TPR);
6548	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6549	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6550	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6551	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6552	fDecodedInstr = true;
6553	}
6554	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6555	}
6556
6557	if (!fDecodedInstr)
6558	{
6559	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6560	Log4Func(("iCrReg=%#x\n", iCrReg));
6561	rcStrict = IEMExecOne(pVCpu);
6562	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6563	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6564	rcStrict = VERR_EM_INTERPRETER;
6565	}
6566
6567	if (rcStrict == VINF_SUCCESS)
6568	{
6569	switch (iCrReg)
6570	{
6571	case 0:
6572	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6573	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6574	break;
6575
6576	case 2:
6577	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6578	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6579	break;
6580
6581	case 3:
6582	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6583	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6584	break;
6585
6586	case 4:
6587	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6588	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6589	break;
6590
6591	case 8:
6592	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6593	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6594	break;
6595
6596	default:
6597	{
6598	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6599	pSvmTransient->u64ExitCode, iCrReg));
6600	break;
6601	}
6602	}
6603	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6604	}
6605	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6606	{
6607	rcStrict = VINF_SUCCESS;
6608	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6609	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6610	}
6611	else
6612	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6613	return VBOXSTRICTRC_TODO(rcStrict);
6614	}
6615
6616
6617	/**
6618	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6619	*
6620	* @returns Strict VBox status code.
6621	* @param pVCpu The cross context virtual CPU structure.
6622	* @param pVmcb Pointer to the VM control block.
6623	*/
6624	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPU pVCpu, PSVMVMCB pVmcb)
6625	{
6626	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6627	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6628
6629	VBOXSTRICTRC rcStrict;
6630	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6631	if (fSupportsNextRipSave)
6632	{
6633	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6634	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6635	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6636	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6637	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6638	}
6639	else
6640	{
6641	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6642	rcStrict = IEMExecOne(pVCpu);
6643	}
6644
6645	AssertMsg( rcStrict == VINF_SUCCESS
6646	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6647	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6648	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6649
6650	if (rcStrict == VINF_IEM_RAISED_XCPT)
6651	{
6652	rcStrict = VINF_SUCCESS;
6653	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6654	}
6655	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6656	return rcStrict;
6657	}
6658
6659
6660	/**
6661	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6662	*
6663	* @returns Strict VBox status code.
6664	* @param pVCpu The cross context virtual CPU structure.
6665	* @param pVmcb Pointer to the VM control block.
6666	* @param pSvmTransient Pointer to the SVM-transient structure.
6667	*/
6668	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPU pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6669	{
6670	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6671	uint32_t const idMsr = pCtx->ecx;
6672	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6673	Log4Func(("idMsr=%#RX32\n", idMsr));
6674
6675	/*
6676	* Handle TPR patching MSR writes.
6677	* We utilitize the LSTAR MSR for patching.
6678	*/
6679	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6680	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
6681	&& idMsr == MSR_K8_LSTAR)
6682	{
6683	unsigned cbInstr;
6684	if (fSupportsNextRipSave)
6685	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6686	else
6687	{
6688	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6689	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6690	if ( rc == VINF_SUCCESS
6691	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6692	Assert(cbInstr > 0);
6693	else
6694	cbInstr = 0;
6695	}
6696
6697	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6698	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6699	{
6700	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6701	AssertRCReturn(rc, rc);
6702	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6703	}
6704
6705	int rc = VINF_SUCCESS;
6706	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6707	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6708	return rc;
6709	}
6710
6711	/*
6712	* Handle regular MSR writes.
6713	*/
6714	VBOXSTRICTRC rcStrict;
6715	if (fSupportsNextRipSave)
6716	{
6717	/** @todo Optimize this: We don't need to get much of the MSR state here
6718	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6719	* clear the applicable extern flags. */
6720	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6721	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6722	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6723	}
6724	else
6725	{
6726	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6727	rcStrict = IEMExecOne(pVCpu);
6728	}
6729
6730	AssertMsg( rcStrict == VINF_SUCCESS
6731	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6732	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6733	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6734
6735	if (rcStrict == VINF_SUCCESS)
6736	{
6737	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6738	if ( idMsr >= MSR_IA32_X2APIC_START
6739	&& idMsr <= MSR_IA32_X2APIC_END)
6740	{
6741	/*
6742	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6743	* When full APIC register virtualization is implemented we'll have to make sure
6744	* APIC state is saved from the VMCB before IEM changes it.
6745	*/
6746	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6747	}
6748	else
6749	{
6750	switch (idMsr)
6751	{
6752	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6753	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6754	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6755	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6756	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6757	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6758	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6759	}
6760	}
6761	}
6762	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6763	{
6764	rcStrict = VINF_SUCCESS;
6765	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6766	}
6767	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6768	return rcStrict;
6769	}
6770
6771
6772	/**
6773	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6774	* \#VMEXIT.
6775	*/
6776	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6777	{
6778	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6779
6780	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6781	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6782	return VBOXSTRICTRC_TODO(hmR0SvmExitReadMsr(pVCpu, pVmcb));
6783
6784	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6785	return VBOXSTRICTRC_TODO(hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient));
6786	}
6787
6788
6789	/**
6790	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6791	*/
6792	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6793	{
6794	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6795	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6796
6797	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6798
6799	/** @todo Stepping with nested-guest. */
6800	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6801	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6802	{
6803	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6804	if (pSvmTransient->fWasGuestDebugStateActive)
6805	{
6806	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6807	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6808	return VERR_SVM_UNEXPECTED_EXIT;
6809	}
6810
6811	/*
6812	* Lazy DR0-3 loading.
6813	*/
6814	if (!pSvmTransient->fWasHyperDebugStateActive)
6815	{
6816	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6817	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6818
6819	/* Don't intercept DRx read and writes. */
6820	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6821	pVmcb->ctrl.u16InterceptRdDRx = 0;
6822	pVmcb->ctrl.u16InterceptWrDRx = 0;
6823	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6824
6825	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6826	VMMRZCallRing3Disable(pVCpu);
6827	HM_DISABLE_PREEMPT(pVCpu);
6828
6829	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6830	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6831	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6832
6833	HM_RESTORE_PREEMPT();
6834	VMMRZCallRing3Enable(pVCpu);
6835
6836	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6837	return VINF_SUCCESS;
6838	}
6839	}
6840
6841	/*
6842	* Interpret the read/writing of DRx.
6843	*/
6844	/** @todo Decode assist. */
6845	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6846	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6847	if (RT_LIKELY(rc == VINF_SUCCESS))
6848	{
6849	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6850	/** @todo CPUM should set this flag! */
6851	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6852	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6853	}
6854	else
6855	Assert(rc == VERR_EM_INTERPRETER);
6856	return VBOXSTRICTRC_TODO(rc);
6857	}
6858
6859
6860	/**
6861	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6862	*/
6863	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6864	{
6865	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6866	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6867	int rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6868	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6869	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6870	return rc;
6871	}
6872
6873
6874	/**
6875	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6876	*/
6877	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6878	{
6879	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6880	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6881
6882	/** @todo decode assists... */
6883	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6884	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6885	{
6886	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6887	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6888	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0,
6889	pCtx->cr4));
6890	}
6891	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6892	{
6893	rcStrict = VINF_SUCCESS;
6894	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6895	}
6896	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6897	return VBOXSTRICTRC_TODO(rcStrict);
6898	}
6899
6900
6901	/**
6902	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6903	*/
6904	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6905	{
6906	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6907	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6908
6909	/* I/O operation lookup arrays. */
6910	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6911	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6912	the result (in AL/AX/EAX). */
6913	PVM pVM = pVCpu->CTX_SUFF(pVM);
6914	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6915	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6916
6917	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6918
6919	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6920	SVMIOIOEXITINFO IoExitInfo;
6921	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6922	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6923	uint32_t cbValue = s_aIOSize[uIOWidth];
6924	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6925
6926	if (RT_UNLIKELY(!cbValue))
6927	{
6928	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6929	return VERR_EM_INTERPRETER;
6930	}
6931
6932	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6933	VBOXSTRICTRC rcStrict;
6934	PCEMEXITREC pExitRec = NULL;
6935	if ( !pVCpu->hm.s.fSingleInstruction
6936	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6937	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6938	!IoExitInfo.n.u1Str
6939	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6940	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6941	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6942	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6943	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6944	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6945	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6946	if (!pExitRec)
6947	{
6948	bool fUpdateRipAlready = false;
6949	if (IoExitInfo.n.u1Str)
6950	{
6951	/* INS/OUTS - I/O String instruction. */
6952	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6953	* in EXITINFO1? Investigate once this thing is up and running. */
6954	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6955	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6956	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6957	static IEMMODE const s_aenmAddrMode[8] =
6958	{
6959	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6960	};
6961	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6962	if (enmAddrMode != (IEMMODE)-1)
6963	{
6964	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6965	if (cbInstr <= 15 && cbInstr >= 1)
6966	{
6967	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6968	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6969	{
6970	/* Don't know exactly how to detect whether u3Seg is valid, currently
6971	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6972	2384 Opterons when only checking NRIP. */
6973	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6974	if ( fSupportsNextRipSave
6975	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6976	{
6977	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6978	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6979	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6980	IoExitInfo.n.u3Seg, true /fIoChecked/);
6981	}
6982	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6983	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6984	X86_SREG_DS, true /fIoChecked/);
6985	else
6986	rcStrict = IEMExecOne(pVCpu);
6987	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6988	}
6989	else
6990	{
6991	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6992	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6993	true /fIoChecked/);
6994	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6995	}
6996	}
6997	else
6998	{
6999	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
7000	rcStrict = IEMExecOne(pVCpu);
7001	}
7002	}
7003	else
7004	{
7005	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
7006	rcStrict = IEMExecOne(pVCpu);
7007	}
7008	fUpdateRipAlready = true;
7009	}
7010	else
7011	{
7012	/* IN/OUT - I/O instruction. */
7013	Assert(!IoExitInfo.n.u1Rep);
7014
7015	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
7016	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
7017	{
7018	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
7019	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
7020	&& !pCtx->eflags.Bits.u1TF)
7021	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
7022	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
7023	}
7024	else
7025	{
7026	uint32_t u32Val = 0;
7027	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
7028	if (IOM_SUCCESS(rcStrict))
7029	{
7030	/* Save result of I/O IN instr. in AL/AX/EAX. */
7031	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
7032	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
7033	}
7034	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
7035	&& !pCtx->eflags.Bits.u1TF)
7036	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
7037
7038	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
7039	}
7040	}
7041
7042	if (IOM_SUCCESS(rcStrict))
7043	{
7044	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
7045	if (!fUpdateRipAlready)
7046	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
7047
7048	/*
7049	* If any I/O breakpoints are armed, we need to check if one triggered
7050	* and take appropriate action.
7051	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
7052	*/
7053	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
7054	* execution engines about whether hyper BPs and such are pending. */
7055	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
7056	uint32_t const uDr7 = pCtx->dr[7];
7057	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7058	&& X86_DR7_ANY_RW_IO(uDr7)
7059	&& (pCtx->cr4 & X86_CR4_DE))
7060	\|\| DBGFBpIsHwIoArmed(pVM)))
7061	{
7062	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7063	VMMRZCallRing3Disable(pVCpu);
7064	HM_DISABLE_PREEMPT(pVCpu);
7065
7066	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
7067	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
7068
7069	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
7070	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
7071	{
7072	/* Raise #DB. */
7073	pVmcb->guest.u64DR6 = pCtx->dr[6];
7074	pVmcb->guest.u64DR7 = pCtx->dr[7];
7075	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7076	hmR0SvmSetPendingXcptDB(pVCpu);
7077	}
7078	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
7079	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
7080	else if ( rcStrict2 != VINF_SUCCESS
7081	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
7082	rcStrict = rcStrict2;
7083	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
7084
7085	HM_RESTORE_PREEMPT();
7086	VMMRZCallRing3Enable(pVCpu);
7087	}
7088
7089	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7090	}
7091
7092	#ifdef VBOX_STRICT
7093	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
7094	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
7095	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
7096	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
7097	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
7098	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
7099	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
7100	else
7101	{
7102	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
7103	* statuses, that the VMM device and some others may return. See
7104	* IOM_SUCCESS() for guidance. */
7105	AssertMsg( RT_FAILURE(rcStrict)
7106	\|\| rcStrict == VINF_SUCCESS
7107	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
7108	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
7109	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
7110	\|\| rcStrict == VINF_EM_RAW_TO_R3
7111	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
7112	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7113	}
7114	#endif
7115	}
7116	else
7117	{
7118	/*
7119	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
7120	*/
7121	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7122	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
7123	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
7124	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
7125	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
7126	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
7127	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
7128
7129	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7130	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7131
7132	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7133	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7134	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7135	}
7136	return VBOXSTRICTRC_TODO(rcStrict);
7137	}
7138
7139
7140	/**
7141	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
7142	*/
7143	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7144	{
7145	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7146	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7147	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7148
7149	PVM pVM = pVCpu->CTX_SUFF(pVM);
7150	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7151	Assert(pVM->hm.s.fNestedPaging);
7152
7153	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7154	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7155	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7156	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
7157	thus intentionally not copied into u32ErrCode. */
7158
7159	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
7160	u32ErrCode));
7161
7162	/*
7163	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
7164	*/
7165	if ( pVM->hm.s.fTprPatchingAllowed
7166	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7167	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7168	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7169	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7170	&& !CPUMIsGuestInLongModeEx(pCtx)
7171	&& !CPUMGetGuestCPL(pVCpu)
7172	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7173	{
7174	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7175	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7176
7177	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7178	{
7179	/* Only attempt to patch the instruction once. */
7180	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7181	if (!pPatch)
7182	return VINF_EM_HM_PATCH_TPR_INSTR;
7183	}
7184	}
7185
7186	/*
7187	* Determine the nested paging mode.
7188	*/
7189	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
7190	PGMMODE enmNestedPagingMode;
7191	#if HC_ARCH_BITS == 32
7192	if (CPUMIsGuestInLongModeEx(pCtx))
7193	enmNestedPagingMode = PGMMODE_AMD64_NX;
7194	else
7195	#endif
7196	enmNestedPagingMode = PGMGetHostMode(pVM);
7197
7198	/*
7199	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7200	*/
7201	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7202	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7203	{
7204	/*
7205	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
7206	* injecting the original pending event would most likely cause the same MMIO #NPF.
7207	*/
7208	if (pVCpu->hm.s.Event.fPending)
7209	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7210
7211	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
7212	VBOXSTRICTRC rcStrict;
7213	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
7214	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
7215	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
7216	if (!pExitRec)
7217	{
7218
7219	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7220	u32ErrCode);
7221
7222	/*
7223	* If we succeed, resume guest execution.
7224	*
7225	* If we fail in interpreting the instruction because we couldn't get the guest
7226	* physical address of the page containing the instruction via the guest's page
7227	* tables (we would invalidate the guest page in the host TLB), resume execution
7228	* which would cause a guest page fault to let the guest handle this weird case.
7229	*
7230	* See @bugref{6043}.
7231	*/
7232	if ( rcStrict == VINF_SUCCESS
7233	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
7234	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
7235	{
7236	/* Successfully handled MMIO operation. */
7237	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
7238	rcStrict = VINF_SUCCESS;
7239	}
7240	}
7241	else
7242	{
7243	/*
7244	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
7245	*/
7246	Assert(pCtx == &pVCpu->cpum.GstCtx);
7247	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7248	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
7249	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
7250
7251	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7252	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7253
7254	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7255	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7256	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7257	}
7258	return VBOXSTRICTRC_TODO(rcStrict);
7259	}
7260
7261	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7262	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7263	TRPMResetTrap(pVCpu);
7264
7265	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7266
7267	/*
7268	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7269	*/
7270	if ( rc == VINF_SUCCESS
7271	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7272	\|\| rc == VERR_PAGE_NOT_PRESENT)
7273	{
7274	/* We've successfully synced our shadow page tables. */
7275	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7276	rc = VINF_SUCCESS;
7277	}
7278
7279	return rc;
7280	}
7281
7282
7283	/**
7284	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7285	* \#VMEXIT.
7286	*/
7287	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7288	{
7289	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7290	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7291
7292	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7293	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7294	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
7295
7296	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7297	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7298	return VINF_SUCCESS;
7299	}
7300
7301
7302	/**
7303	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7304	* \#VMEXIT.
7305	*/
7306	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7307	{
7308	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7309	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7310
7311	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7312	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7313	#endif
7314
7315	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7316	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7317	{
7318	/*
7319	* AMD-V provides us with the exception which caused the TS; we collect
7320	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7321	*/
7322	Log4Func(("TS occurred during event delivery\n"));
7323	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7324	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7325	}
7326
7327	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7328	* emulation. */
7329	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7330	return VERR_EM_INTERPRETER;
7331	}
7332
7333
7334	/**
7335	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7336	*/
7337	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7338	{
7339	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7340	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7341
7342	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTprPatchingAllowed)
7343	{
7344	int rc = hmEmulateSvmMovTpr(pVCpu);
7345	if (rc != VERR_NOT_FOUND)
7346	{
7347	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
7348	return rc;
7349	}
7350	}
7351
7352	if (EMAreHypercallInstructionsEnabled(pVCpu))
7353	{
7354	unsigned cbInstr;
7355	if (hmR0SvmSupportsNextRipSave(pVCpu))
7356	{
7357	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7358	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7359	}
7360	else
7361	{
7362	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7363	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7364	if ( rc == VINF_SUCCESS
7365	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7366	Assert(cbInstr > 0);
7367	else
7368	cbInstr = 0;
7369	}
7370
7371	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7372	if (RT_SUCCESS(rcStrict))
7373	{
7374	/* Only update the RIP if we're continuing guest execution and not in the case
7375	of say VINF_GIM_R3_HYPERCALL. */
7376	if (rcStrict == VINF_SUCCESS)
7377	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7378
7379	return VBOXSTRICTRC_VAL(rcStrict);
7380	}
7381	else
7382	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7383	}
7384
7385	hmR0SvmSetPendingXcptUD(pVCpu);
7386	return VINF_SUCCESS;
7387	}
7388
7389
7390	/**
7391	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7392	*/
7393	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7394	{
7395	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7396
7397	unsigned cbInstr;
7398	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7399	if (fSupportsNextRipSave)
7400	{
7401	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7402	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7403	}
7404	else
7405	{
7406	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7407	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7408	if ( rc == VINF_SUCCESS
7409	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7410	Assert(cbInstr > 0);
7411	else
7412	cbInstr = 0;
7413	}
7414
7415	/** @todo The guest has likely hit a contended spinlock. We might want to
7416	* poke a schedule different guest VCPU. */
7417	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7418	return VINF_EM_RAW_INTERRUPT;
7419	}
7420
7421
7422	/**
7423	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7424	* \#VMEXIT.
7425	*/
7426	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7427	{
7428	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7429	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7430	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7431
7432	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7433	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7434	}
7435
7436
7437	/**
7438	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7439	*/
7440	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7441	{
7442	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7443
7444	/* Clear NMI blocking. */
7445	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7446	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7447
7448	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7449	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7450	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7451
7452	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7453	return VINF_SUCCESS;
7454	}
7455
7456
7457	/**
7458	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7459	* Conditional \#VMEXIT.
7460	*/
7461	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7462	{
7463	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7464	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7465	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7466
7467	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7468	PVM pVM = pVCpu->CTX_SUFF(pVM);
7469	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7470	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7471	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7472	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7473
7474	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7475	if (pVM->hm.s.fNestedPaging)
7476	{
7477	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7478	if ( !pSvmTransient->fVectoringDoublePF
7479	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7480	{
7481	/* A genuine guest #PF, reflect it to the guest. */
7482	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7483	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7484	uFaultAddress, uErrCode));
7485	}
7486	else
7487	{
7488	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7489	hmR0SvmSetPendingXcptDF(pVCpu);
7490	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7491	}
7492	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7493	return VINF_SUCCESS;
7494	}
7495	#endif
7496
7497	Assert(!pVM->hm.s.fNestedPaging);
7498
7499	/*
7500	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7501	*/
7502	if ( pVM->hm.s.fTprPatchingAllowed
7503	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7504	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7505	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7506	&& !CPUMIsGuestInLongModeEx(pCtx)
7507	&& !CPUMGetGuestCPL(pVCpu)
7508	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7509	{
7510	RTGCPHYS GCPhysApicBase;
7511	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7512	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7513
7514	/* Check if the page at the fault-address is the APIC base. */
7515	RTGCPHYS GCPhysPage;
7516	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7517	if ( rc2 == VINF_SUCCESS
7518	&& GCPhysPage == GCPhysApicBase)
7519	{
7520	/* Only attempt to patch the instruction once. */
7521	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7522	if (!pPatch)
7523	return VINF_EM_HM_PATCH_TPR_INSTR;
7524	}
7525	}
7526
7527	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7528	pCtx->rip, uErrCode, pCtx->cr3));
7529
7530	/*
7531	* If it's a vectoring #PF, emulate injecting the original event injection as
7532	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7533	* event injection that caused a #PF. See @bugref{6607}.
7534	*/
7535	if (pSvmTransient->fVectoringPF)
7536	{
7537	Assert(pVCpu->hm.s.Event.fPending);
7538	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7539	}
7540
7541	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7542	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7543
7544	Log4Func(("#PF: rc=%Rrc\n", rc));
7545
7546	if (rc == VINF_SUCCESS)
7547	{
7548	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7549	TRPMResetTrap(pVCpu);
7550	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7551	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7552	return rc;
7553	}
7554
7555	if (rc == VINF_EM_RAW_GUEST_TRAP)
7556	{
7557	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7558
7559	/*
7560	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7561	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7562	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7563	*/
7564	if ( !pSvmTransient->fVectoringDoublePF
7565	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7566	{
7567	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7568	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7569	TRPMResetTrap(pVCpu);
7570
7571	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7572	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7573	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7574	&& HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_PF))
7575	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress));
7576	#endif
7577
7578	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7579	}
7580	else
7581	{
7582	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7583	TRPMResetTrap(pVCpu);
7584	hmR0SvmSetPendingXcptDF(pVCpu);
7585	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7586	}
7587
7588	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7589	return VINF_SUCCESS;
7590	}
7591
7592	TRPMResetTrap(pVCpu);
7593	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7594	return rc;
7595	}
7596
7597
7598	/**
7599	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7600	* Conditional \#VMEXIT.
7601	*/
7602	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7603	{
7604	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7605	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7606
7607	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7608	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7609	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7610
7611	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7612	if (pVCpu->hm.s.fGIMTrapXcptUD)
7613	{
7614	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7615	uint8_t cbInstr = 0;
7616	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7617	if (rcStrict == VINF_SUCCESS)
7618	{
7619	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7620	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7621	rc = VINF_SUCCESS;
7622	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7623	}
7624	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7625	rc = VINF_SUCCESS;
7626	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7627	rc = VINF_GIM_R3_HYPERCALL;
7628	else
7629	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7630	}
7631
7632	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7633	if (RT_FAILURE(rc))
7634	{
7635	hmR0SvmSetPendingXcptUD(pVCpu);
7636	rc = VINF_SUCCESS;
7637	}
7638
7639	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7640	return rc;
7641	}
7642
7643
7644	/**
7645	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7646	* Conditional \#VMEXIT.
7647	*/
7648	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7649	{
7650	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7651	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7652
7653	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7654	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7655
7656	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7657	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7658
7659	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7660
7661	if (!(pCtx->cr0 & X86_CR0_NE))
7662	{
7663	PVM pVM = pVCpu->CTX_SUFF(pVM);
7664	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7665	unsigned cbInstr;
7666	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7667	if (RT_SUCCESS(rc))
7668	{
7669	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7670	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7671	if (RT_SUCCESS(rc))
7672	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7673	}
7674	else
7675	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7676	return rc;
7677	}
7678
7679	hmR0SvmSetPendingXcptMF(pVCpu);
7680	return VINF_SUCCESS;
7681	}
7682
7683
7684	/**
7685	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7686	* \#VMEXIT.
7687	*/
7688	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7689	{
7690	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7691	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7692	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7693
7694	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7695	{
7696	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7697	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7698	}
7699
7700	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7701
7702	/*
7703	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7704	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7705	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7706	*/
7707	PVM pVM = pVCpu->CTX_SUFF(pVM);
7708	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7709	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7710	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7711	if (rc == VINF_EM_RAW_GUEST_TRAP)
7712	{
7713	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7714	if (CPUMIsHyperDebugStateActive(pVCpu))
7715	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7716
7717	/* Reflect the exception back to the guest. */
7718	hmR0SvmSetPendingXcptDB(pVCpu);
7719	rc = VINF_SUCCESS;
7720	}
7721
7722	/*
7723	* Update DR6.
7724	*/
7725	if (CPUMIsHyperDebugStateActive(pVCpu))
7726	{
7727	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7728	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7729	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7730	}
7731	else
7732	{
7733	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7734	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7735	}
7736
7737	return rc;
7738	}
7739
7740
7741	/**
7742	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7743	* Conditional \#VMEXIT.
7744	*/
7745	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7746	{
7747	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7748	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7749
7750	SVMEVENT Event;
7751	Event.u = 0;
7752	Event.n.u1Valid = 1;
7753	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7754	Event.n.u8Vector = X86_XCPT_AC;
7755	Event.n.u1ErrorCodeValid = 1;
7756	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7757	return VINF_SUCCESS;
7758	}
7759
7760
7761	/**
7762	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7763	* Conditional \#VMEXIT.
7764	*/
7765	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7766	{
7767	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7768	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7769	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7770
7771	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7772	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7773	if (rc == VINF_EM_RAW_GUEST_TRAP)
7774	{
7775	SVMEVENT Event;
7776	Event.u = 0;
7777	Event.n.u1Valid = 1;
7778	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7779	Event.n.u8Vector = X86_XCPT_BP;
7780	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7781	}
7782
7783	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7784	return rc;
7785	}
7786
7787
7788	/**
7789	* Hacks its way around the lovely mesa driver's backdoor accesses.
7790	*
7791	* @sa hmR0VmxHandleMesaDrvGp
7792	*/
7793	static int hmR0SvmHandleMesaDrvGp(PVMCPU pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7794	{
7795	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7796	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7797	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7798	RT_NOREF(pCtx, pVmcb);
7799
7800	/* For now we'll just skip the instruction. */
7801	hmR0SvmAdvanceRip(pVCpu, 1);
7802	return VINF_SUCCESS;
7803	}
7804
7805
7806	/**
7807	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7808	* backdoor logging w/o checking what it is running inside.
7809	*
7810	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7811	* backdoor port and magic numbers loaded in registers.
7812	*
7813	* @returns true if it is, false if it isn't.
7814	* @sa hmR0VmxIsMesaDrvGp
7815	*/
7816	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPU pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7817	{
7818	/* Check magic and port. */
7819	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7820	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7821	if (pCtx->dx != UINT32_C(0x5658))
7822	return false;
7823	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7824	return false;
7825
7826	/* Check that it is #GP(0). */
7827	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7828	return false;
7829
7830	/* Flat ring-3 CS. */
7831	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7832	if (pVmcb->guest.u8CPL != 3)
7833	return false;
7834	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7835	return false;
7836
7837	/* 0xed: IN eAX,dx */
7838	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7839	{
7840	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7841	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7842	uint8_t abInstr[1];
7843	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7844	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7845	if (RT_FAILURE(rc))
7846	return false;
7847	if (abInstr[0] != 0xed)
7848	return false;
7849	}
7850	else
7851	{
7852	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7853	if (pVmcb->ctrl.abInstr[0] != 0xed)
7854	return false;
7855	}
7856	return true;
7857	}
7858
7859
7860	/**
7861	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7862	* Conditional \#VMEXIT.
7863	*/
7864	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7865	{
7866	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7867	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7868
7869	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7870	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7871
7872	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7873	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7874	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7875	{
7876	SVMEVENT Event;
7877	Event.u = 0;
7878	Event.n.u1Valid = 1;
7879	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7880	Event.n.u8Vector = X86_XCPT_GP;
7881	Event.n.u1ErrorCodeValid = 1;
7882	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7883	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7884	return VINF_SUCCESS;
7885	}
7886	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7887	}
7888
7889
7890	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7891	/**
7892	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7893	*/
7894	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7895	{
7896	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7897	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7898
7899	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7900	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7901	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7902	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7903	Assert(uVector <= X86_XCPT_LAST);
7904	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7905
7906	SVMEVENT Event;
7907	Event.u = 0;
7908	Event.n.u1Valid = 1;
7909	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7910	Event.n.u8Vector = uVector;
7911	switch (uVector)
7912	{
7913	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7914	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7915	case X86_XCPT_DF:
7916	case X86_XCPT_TS:
7917	case X86_XCPT_NP:
7918	case X86_XCPT_SS:
7919	case X86_XCPT_GP:
7920	case X86_XCPT_AC:
7921	{
7922	Event.n.u1ErrorCodeValid = 1;
7923	Event.n.u32ErrorCode = uErrCode;
7924	break;
7925	}
7926	}
7927
7928	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7929	return VINF_SUCCESS;
7930	}
7931	#endif
7932
7933	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7934	/**
7935	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7936	*/
7937	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7938	{
7939	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7940
7941	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7942	Assert(pVmcb);
7943	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7944
7945	VBOXSTRICTRC rcStrict;
7946	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7947	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7948	if (fSupportsNextRipSave)
7949	{
7950	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7951	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7952	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7953	}
7954	else
7955	{
7956	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7957	rcStrict = IEMExecOne(pVCpu);
7958	}
7959
7960	if (rcStrict == VINF_SUCCESS)
7961	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7962	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7963	{
7964	rcStrict = VINF_SUCCESS;
7965	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7966	}
7967	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7968	return VBOXSTRICTRC_TODO(rcStrict);
7969	}
7970
7971
7972	/**
7973	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7974	*/
7975	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7976	{
7977	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7978
7979	/*
7980	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7981	* we only intercept STGI when events are pending for GIF to become 1.
7982	*/
7983	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7984	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7985	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7986
7987	VBOXSTRICTRC rcStrict;
7988	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7989	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7990	if (fSupportsNextRipSave)
7991	{
7992	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7993	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7994	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7995	}
7996	else
7997	{
7998	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7999	rcStrict = IEMExecOne(pVCpu);
8000	}
8001
8002	if (rcStrict == VINF_SUCCESS)
8003	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
8004	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8005	{
8006	rcStrict = VINF_SUCCESS;
8007	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8008	}
8009	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8010	return VBOXSTRICTRC_TODO(rcStrict);
8011	}
8012
8013
8014	/**
8015	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
8016	*/
8017	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8018	{
8019	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8020
8021	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8022	Assert(pVmcb);
8023	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
8024
8025	VBOXSTRICTRC rcStrict;
8026	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8027	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
8028	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
8029	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
8030	if (fSupportsNextRipSave)
8031	{
8032	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
8033	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8034	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
8035	}
8036	else
8037	{
8038	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
8039	rcStrict = IEMExecOne(pVCpu);
8040	}
8041
8042	if (rcStrict == VINF_SUCCESS)
8043	{
8044	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
8045	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
8046	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
8047	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
8048	}
8049	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8050	{
8051	rcStrict = VINF_SUCCESS;
8052	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8053	}
8054	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8055	return VBOXSTRICTRC_TODO(rcStrict);
8056	}
8057
8058
8059	/**
8060	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
8061	*/
8062	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8063	{
8064	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8065
8066	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8067	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
8068
8069	VBOXSTRICTRC rcStrict;
8070	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8071	if (fSupportsNextRipSave)
8072	{
8073	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
8074	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8075	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
8076	}
8077	else
8078	{
8079	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
8080	rcStrict = IEMExecOne(pVCpu);
8081	}
8082
8083	if (rcStrict == VINF_IEM_RAISED_XCPT)
8084	{
8085	rcStrict = VINF_SUCCESS;
8086	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8087	}
8088	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8089	return VBOXSTRICTRC_TODO(rcStrict);
8090	}
8091
8092
8093	/**
8094	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
8095	*/
8096	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8097	{
8098	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8099
8100	VBOXSTRICTRC rcStrict;
8101	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8102	if (fSupportsNextRipSave)
8103	{
8104	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
8105	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8106	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8107	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
8108	}
8109	else
8110	{
8111	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
8112	rcStrict = IEMExecOne(pVCpu);
8113	}
8114
8115	if (rcStrict == VINF_IEM_RAISED_XCPT)
8116	{
8117	rcStrict = VINF_SUCCESS;
8118	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8119	}
8120	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8121	return VBOXSTRICTRC_TODO(rcStrict);
8122	}
8123
8124
8125	/**
8126	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
8127	*/
8128	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8129	{
8130	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8131	/* We shall import the entire state here, just in case we enter and continue execution of
8132	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
8133	could lose lose part of CPU state. */
8134	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
8135
8136	VBOXSTRICTRC rcStrict;
8137	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8138	if (fSupportsNextRipSave)
8139	{
8140	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8141	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8142	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
8143	}
8144	else
8145	{
8146	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
8147	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
8148	instruction itself, see @bugref{7243#c126} */
8149	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
8150	}
8151
8152	if (rcStrict == VINF_SUCCESS)
8153	{
8154	rcStrict = VINF_SVM_VMRUN;
8155	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
8156	}
8157	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8158	{
8159	rcStrict = VINF_SUCCESS;
8160	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8161	}
8162	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8163	return VBOXSTRICTRC_TODO(rcStrict);
8164	}
8165
8166
8167	/**
8168	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
8169	* Unconditional \#VMEXIT.
8170	*/
8171	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8172	{
8173	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8174	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8175
8176	if (pVCpu->hm.s.Event.fPending)
8177	{
8178	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
8179	return VINF_EM_RAW_INJECT_TRPM_EVENT;
8180	}
8181
8182	hmR0SvmSetPendingXcptDB(pVCpu);
8183	return VINF_SUCCESS;
8184	}
8185
8186
8187	/**
8188	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
8189	* Conditional \#VMEXIT.
8190	*/
8191	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8192	{
8193	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8194	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8195
8196	SVMEVENT Event;
8197	Event.u = 0;
8198	Event.n.u1Valid = 1;
8199	Event.n.u3Type = SVM_EVENT_EXCEPTION;
8200	Event.n.u8Vector = X86_XCPT_BP;
8201	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
8202	return VINF_SUCCESS;
8203	}
8204	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
8205
8206	/** @} */
8207

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 78680

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