HMSVMR0.cpp@ 82612

Last change on this file since 82612 was 82612, checked in by vboxsync, 5 years ago
VMM/HM: Disable LBR virtualization by default. Only enable when set via CFGM for now.
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1	/* $Id: HMSVMR0.cpp 82612 2019-12-18 10:47:57Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vmcc.h>
37	#include <VBox/err.h>
38	#include "HMSVMR0.h"
39	#include "dtrace/VBoxVMM.h"
40
41	#ifdef DEBUG_ramshankar
42	# define HMSVM_SYNC_FULL_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll); \
65	if ((u64ExitCode) == SVM_EXIT_NPF) \
66	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
67	else \
68	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
69	} while (0)
70	# endif
71	#else
72	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
73	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
74	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
75	# endif
76	#endif /* !VBOX_WITH_STATISTICS */
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static int
81
82	/**
83	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
84	* guest using hardware-assisted SVM.
85	*
86	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
87	* are swapped and restored across the world-switch and also registers like
88	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
89	* \#VMEXIT.
90	*/
91	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
92	\| CPUMCTX_EXTRN_RFLAGS \
93	\| CPUMCTX_EXTRN_RAX \
94	\| CPUMCTX_EXTRN_RSP \
95	\| CPUMCTX_EXTRN_SREG_MASK \
96	\| CPUMCTX_EXTRN_CR0 \
97	\| CPUMCTX_EXTRN_CR2 \
98	\| CPUMCTX_EXTRN_CR3 \
99	\| CPUMCTX_EXTRN_TABLE_MASK \
100	\| CPUMCTX_EXTRN_DR6 \
101	\| CPUMCTX_EXTRN_DR7 \
102	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
103	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
104	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
105	\| CPUMCTX_EXTRN_HWVIRT \
106	\| CPUMCTX_EXTRN_HM_SVM_MASK)
107
108	/**
109	* Subset of the guest-CPU state that is shared between the guest and host.
110	*/
111	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
112
113	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
114	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
115	do { \
116	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
117	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
118	} while (0)
119
120	/** Assert that the required state bits are fetched. */
121	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
122	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
123	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
124
125	/** Assert that preemption is disabled or covered by thread-context hooks. */
126	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
127	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
128
129	/** Assert that we haven't migrated CPUs when thread-context hooks are not
130	* used. */
131	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
132	\|\| (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
133	("Illegal migration! Entered on CPU %u Current %u\n", \
134	(a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()));
135
136	/** Assert that we're not executing a nested-guest. */
137	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
139	#else
140	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
141	#endif
142
143	/** Assert that we're executing a nested-guest. */
144	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
145	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
146	#else
147	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
148	#endif
149
150	/** Macro for checking and returning from the using function for
151	* \#VMEXIT intercepts that maybe caused during delivering of another
152	* event in the guest. */
153	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
154	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
155	do \
156	{ \
157	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
158	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
159	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
160	else if ( rc == VINF_EM_RESET \
161	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
162	{ \
163	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
164	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0)); \
165	} \
166	else \
167	return rc; \
168	} while (0)
169	#else
170	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
171	do \
172	{ \
173	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
174	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
175	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
176	else \
177	return rc; \
178	} while (0)
179	#endif
180
181	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
182	* instruction that exited. */
183	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
184	do { \
185	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
186	(a_rc) = VINF_EM_DBG_STEPPED; \
187	} while (0)
188
189	/** Validate segment descriptor granularity bit. */
190	#ifdef VBOX_STRICT
191	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
192	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
193	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
194	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
195	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
196	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
197	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
198	#else
199	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
200	#endif
201
202	/**
203	* Exception bitmap mask for all contributory exceptions.
204	*
205	* Page fault is deliberately excluded here as it's conditional as to whether
206	* it's contributory or benign. Page faults are handled separately.
207	*/
208	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
209	\| RT_BIT(X86_XCPT_DE))
210
211	/**
212	* Mandatory/unconditional guest control intercepts.
213	*
214	* SMIs can and do happen in normal operation. We need not intercept them
215	* while executing the guest (or nested-guest).
216	*/
217	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
218	\| SVM_CTRL_INTERCEPT_NMI \
219	\| SVM_CTRL_INTERCEPT_INIT \
220	\| SVM_CTRL_INTERCEPT_RDPMC \
221	\| SVM_CTRL_INTERCEPT_CPUID \
222	\| SVM_CTRL_INTERCEPT_RSM \
223	\| SVM_CTRL_INTERCEPT_HLT \
224	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
225	\| SVM_CTRL_INTERCEPT_MSR_PROT \
226	\| SVM_CTRL_INTERCEPT_INVLPGA \
227	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
228	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
229	\| SVM_CTRL_INTERCEPT_VMRUN \
230	\| SVM_CTRL_INTERCEPT_SKINIT \
231	\| SVM_CTRL_INTERCEPT_WBINVD \
232	\| SVM_CTRL_INTERCEPT_MONITOR \
233	\| SVM_CTRL_INTERCEPT_MWAIT \
234	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
235	\| SVM_CTRL_INTERCEPT_XSETBV)
236
237	/** @name VMCB Clean Bits.
238	*
239	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
240	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
241	* memory.
242	*
243	* @{ */
244	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
245	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
246	/** I/O permission bitmap, MSR permission bitmap. */
247	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
248	/** ASID. */
249	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
250	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
251	V_INTR_VECTOR. */
252	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
253	/** Nested Paging: Nested CR3 (nCR3), PAT. */
254	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
255	/** Control registers (CR0, CR3, CR4, EFER). */
256	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
257	/** Debug registers (DR6, DR7). */
258	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
259	/** GDT, IDT limit and base. */
260	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
261	/** Segment register: CS, SS, DS, ES limit and base. */
262	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
263	/** CR2.*/
264	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
265	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
266	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
267	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
268	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
269	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
270	/** Mask of all valid VMCB Clean bits. */
271	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
272	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
273	\| HMSVM_VMCB_CLEAN_ASID \
274	\| HMSVM_VMCB_CLEAN_INT_CTRL \
275	\| HMSVM_VMCB_CLEAN_NP \
276	\| HMSVM_VMCB_CLEAN_CRX_EFER \
277	\| HMSVM_VMCB_CLEAN_DRX \
278	\| HMSVM_VMCB_CLEAN_DT \
279	\| HMSVM_VMCB_CLEAN_SEG \
280	\| HMSVM_VMCB_CLEAN_CR2 \
281	\| HMSVM_VMCB_CLEAN_LBR \
282	\| HMSVM_VMCB_CLEAN_AVIC)
283	/** @} */
284
285	/** @name SVM transient.
286	*
287	* A state structure for holding miscellaneous information across AMD-V
288	* VMRUN/\#VMEXIT operation, restored after the transition.
289	*
290	* @{ */
291	typedef struct SVMTRANSIENT
292	{
293	/** The host's rflags/eflags. */
294	RTCCUINTREG fEFlags;
295	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
296	uint64_t u64ExitCode;
297
298	/** The guest's TPR value used for TPR shadowing. */
299	uint8_t u8GuestTpr;
300	/** Alignment. */
301	uint8_t abAlignment0[7];
302
303	/** Pointer to the currently executing VMCB. */
304	PSVMVMCB pVmcb;
305
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308	/** Whether the guest debug state was active at the time of \#VMEXIT. */
309	bool fWasGuestDebugStateActive;
310	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
311	bool fWasHyperDebugStateActive;
312	/** Whether the TSC offset mode needs to be updated. */
313	bool fUpdateTscOffsetting;
314	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
315	bool fRestoreTscAuxMsr;
316	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
317	* contributary exception or a page-fault. */
318	bool fVectoringDoublePF;
319	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
320	* external interrupt or NMI. */
321	bool fVectoringPF;
322	/** Padding. */
323	bool afPadding0;
324	} SVMTRANSIENT;
325	/** Pointer to SVM transient state. */
326	typedef SVMTRANSIENT *PSVMTRANSIENT;
327	/** Pointer to a const SVM transient state. */
328	typedef const SVMTRANSIENT *PCSVMTRANSIENT;
329
330	AssertCompileSizeAlignment(SVMTRANSIENT, sizeof(uint64_t));
331	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
332	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
333	/** @} */
334
335	/**
336	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
337	*/
338	typedef enum SVMMSREXITREAD
339	{
340	/** Reading this MSR causes a \#VMEXIT. */
341	SVMMSREXIT_INTERCEPT_READ = 0xb,
342	/** Reading this MSR does not cause a \#VMEXIT. */
343	SVMMSREXIT_PASSTHRU_READ
344	} SVMMSREXITREAD;
345
346	/**
347	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
348	*/
349	typedef enum SVMMSREXITWRITE
350	{
351	/** Writing to this MSR causes a \#VMEXIT. */
352	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
353	/** Writing to this MSR does not cause a \#VMEXIT. */
354	SVMMSREXIT_PASSTHRU_WRITE
355	} SVMMSREXITWRITE;
356
357	/**
358	* SVM \#VMEXIT handler.
359	*
360	* @returns VBox status code.
361	* @param pVCpu The cross context virtual CPU structure.
362	* @param pSvmTransient Pointer to the SVM-transient structure.
363	*/
364	typedef int FNSVMEXITHANDLER(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
365
366
367	/*********************************************************************************************************************************
368	* Internal Functions *
369	*********************************************************************************************************************************/
370	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu);
371	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState);
372
373
374	/** @name \#VMEXIT handlers.
375	* @{
376	*/
377	static FNSVMEXITHANDLER hmR0SvmExitIntr;
378	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
379	static FNSVMEXITHANDLER hmR0SvmExitInvd;
380	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
381	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
382	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
383	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
384	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
385	static FNSVMEXITHANDLER hmR0SvmExitHlt;
386	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
387	static FNSVMEXITHANDLER hmR0SvmExitMwait;
388	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
389	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
390	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
391	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
392	static FNSVMEXITHANDLER hmR0SvmExitMsr;
393	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
394	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
395	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
396	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
397	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
398	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
399	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
400	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
401	static FNSVMEXITHANDLER hmR0SvmExitPause;
402	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
403	static FNSVMEXITHANDLER hmR0SvmExitIret;
404	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
405	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
406	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
407	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
408	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
409	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
410	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
411	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
412	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
413	#endif
414	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
415	static FNSVMEXITHANDLER hmR0SvmExitClgi;
416	static FNSVMEXITHANDLER hmR0SvmExitStgi;
417	static FNSVMEXITHANDLER hmR0SvmExitVmload;
418	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
419	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
420	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
421	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
422	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
423	#endif
424	/** @} */
425
426	static int hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
427	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
428	static int hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
429	#endif
430
431
432	/*********************************************************************************************************************************
433	* Global Variables *
434	*********************************************************************************************************************************/
435	/** Ring-0 memory object for the IO bitmap. */
436	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
437	/** Physical address of the IO bitmap. */
438	static RTHCPHYS g_HCPhysIOBitmap;
439	/** Pointer to the IO bitmap. */
440	static R0PTRTYPE(void *) g_pvIOBitmap;
441
442	#ifdef VBOX_STRICT
443	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
444	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
445	# define HMSVM_LOG_CS RT_BIT_32(2)
446	# define HMSVM_LOG_SS RT_BIT_32(3)
447	# define HMSVM_LOG_FS RT_BIT_32(4)
448	# define HMSVM_LOG_GS RT_BIT_32(5)
449	# define HMSVM_LOG_LBR RT_BIT_32(6)
450	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
451	\| HMSVM_LOG_CR_REGS \
452	\| HMSVM_LOG_CS \
453	\| HMSVM_LOG_SS \
454	\| HMSVM_LOG_FS \
455	\| HMSVM_LOG_GS \
456	\| HMSVM_LOG_LBR)
457
458	/**
459	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
460	*
461	* @param pVCpu The cross context virtual CPU structure.
462	* @param pVmcb Pointer to the VM control block.
463	* @param pszPrefix Log prefix.
464	* @param fFlags Log flags, see HMSVM_LOG_XXX.
465	* @param uVerbose The verbosity level, currently unused.
466	*/
467	static void hmR0SvmLogState(PVMCPUCC pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
468	{
469	RT_NOREF2(pVCpu, uVerbose);
470	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
471
472	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
473	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
474
475	if (fFlags & HMSVM_LOG_RBP_RSP)
476	{
477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
478	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
479	}
480
481	if (fFlags & HMSVM_LOG_CR_REGS)
482	{
483	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
484	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
485	}
486
487	if (fFlags & HMSVM_LOG_CS)
488	{
489	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
490	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
491	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
492	}
493	if (fFlags & HMSVM_LOG_SS)
494	{
495	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
496	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
497	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
498	}
499	if (fFlags & HMSVM_LOG_FS)
500	{
501	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
502	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
503	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
504	}
505	if (fFlags & HMSVM_LOG_GS)
506	{
507	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
508	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
509	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
510	}
511
512	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
513	if (fFlags & HMSVM_LOG_LBR)
514	{
515	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
516	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
517	}
518	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
519	}
520	#endif /* VBOX_STRICT */
521
522
523	/**
524	* Sets up and activates AMD-V on the current CPU.
525	*
526	* @returns VBox status code.
527	* @param pHostCpu The HM physical-CPU structure.
528	* @param pVM The cross context VM structure. Can be
529	* NULL after a resume!
530	* @param pvCpuPage Pointer to the global CPU page.
531	* @param HCPhysCpuPage Physical address of the global CPU page.
532	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
533	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
534	* unused).
535	*/
536	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
537	PCSUPHWVIRTMSRS pHwvirtMsrs)
538	{
539	Assert(!fEnabledByHost);
540	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
541	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
542	Assert(pvCpuPage); NOREF(pvCpuPage);
543	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
544
545	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
546
547	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
549
550	/*
551	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
552	*/
553	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
554	if (u64HostEfer & MSR_K6_EFER_SVME)
555	{
556	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
557	if ( pVM
558	&& pVM->hm.s.svm.fIgnoreInUseError)
559	pHostCpu->fIgnoreAMDVInUseError = true;
560
561	if (!pHostCpu->fIgnoreAMDVInUseError)
562	{
563	ASMSetFlags(fEFlags);
564	return VERR_SVM_IN_USE;
565	}
566	}
567
568	/* Turn on AMD-V in the EFER MSR. */
569	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
570
571	/* Write the physical page address where the CPU will store the host state while executing the VM. */
572	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
573
574	/* Restore interrupts. */
575	ASMSetFlags(fEFlags);
576
577	/*
578	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
579	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
580	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
581	* entirely with before executing any guest code.
582	*/
583	pHostCpu->fFlushAsidBeforeUse = true;
584
585	/*
586	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
587	*/
588	++pHostCpu->cTlbFlushes;
589
590	return VINF_SUCCESS;
591	}
592
593
594	/**
595	* Deactivates AMD-V on the current CPU.
596	*
597	* @returns VBox status code.
598	* @param pHostCpu The HM physical-CPU structure.
599	* @param pvCpuPage Pointer to the global CPU page.
600	* @param HCPhysCpuPage Physical address of the global CPU page.
601	*/
602	VMMR0DECL(int) SVMR0DisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
603	{
604	RT_NOREF1(pHostCpu);
605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
606	AssertReturn( HCPhysCpuPage
607	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
608	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
609
610	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
611	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
612
613	/* Turn off AMD-V in the EFER MSR. */
614	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
615	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
616
617	/* Invalidate host state physical address. */
618	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
619
620	/* Restore interrupts. */
621	ASMSetFlags(fEFlags);
622
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* Does global AMD-V initialization (called during module initialization).
629	*
630	* @returns VBox status code.
631	*/
632	VMMR0DECL(int) SVMR0GlobalInit(void)
633	{
634	/*
635	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
636	* intercept all IO accesses, it's done once globally here instead of per-VM.
637	*/
638	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
639	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
640	if (RT_FAILURE(rc))
641	return rc;
642
643	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
644	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
645
646	/* Set all bits to intercept all IO accesses. */
647	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Does global AMD-V termination (called during module termination).
655	*/
656	VMMR0DECL(void) SVMR0GlobalTerm(void)
657	{
658	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
661	g_pvIOBitmap = NULL;
662	g_HCPhysIOBitmap = 0;
663	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666
667
668	/**
669	* Frees any allocated per-VCPU structures for a VM.
670	*
671	* @param pVM The cross context VM structure.
672	*/
673	DECLINLINE(void) hmR0SvmFreeStructs(PVMCC pVM)
674	{
675	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
676	{
677	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
678	AssertPtr(pVCpu);
679
680	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
681	{
682	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
683	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
684	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
685	}
686
687	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
688	{
689	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
690	pVCpu->hm.s.svm.pVmcb = NULL;
691	pVCpu->hm.s.svm.HCPhysVmcb = 0;
692	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
693	}
694
695	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
696	{
697	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
698	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
699	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
700	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
701	}
702	}
703	}
704
705
706	/**
707	* Does per-VM AMD-V initialization.
708	*
709	* @returns VBox status code.
710	* @param pVM The cross context VM structure.
711	*/
712	VMMR0DECL(int) SVMR0InitVM(PVMCC pVM)
713	{
714	int rc = VERR_INTERNAL_ERROR_5;
715
716	/*
717	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
718	*/
719	uint32_t u32Family;
720	uint32_t u32Model;
721	uint32_t u32Stepping;
722	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
723	{
724	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
725	pVM->hm.s.svm.fAlwaysFlushTLB = true;
726	}
727
728	/*
729	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
730	*/
731	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
732	{
733	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
734	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
735	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
736	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
737	}
738
739	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
740	{
741	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
742
743	/*
744	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
745	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
746	*/
747	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
748	if (RT_FAILURE(rc))
749	goto failure_cleanup;
750
751	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
752	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
753	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
754	ASMMemZeroPage(pvVmcbHost);
755
756	/*
757	* Allocate one page for the guest-state VMCB.
758	*/
759	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
760	if (RT_FAILURE(rc))
761	goto failure_cleanup;
762
763	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
764	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
765	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
766	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
767
768	/*
769	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
770	* SVM to not require one.
771	*/
772	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
773	false /* fExecutable */);
774	if (RT_FAILURE(rc))
775	goto failure_cleanup;
776
777	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
778	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
779	/* Set all bits to intercept all MSR accesses (changed later on). */
780	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
781	}
782
783	return VINF_SUCCESS;
784
785	failure_cleanup:
786	hmR0SvmFreeStructs(pVM);
787	return rc;
788	}
789
790
791	/**
792	* Does per-VM AMD-V termination.
793	*
794	* @returns VBox status code.
795	* @param pVM The cross context VM structure.
796	*/
797	VMMR0DECL(int) SVMR0TermVM(PVMCC pVM)
798	{
799	hmR0SvmFreeStructs(pVM);
800	return VINF_SUCCESS;
801	}
802
803
804	/**
805	* Returns whether the VMCB Clean Bits feature is supported.
806	*
807	* @returns @c true if supported, @c false otherwise.
808	* @param pVCpu The cross context virtual CPU structure.
809	* @param fIsNestedGuest Whether we are currently executing the nested-guest.
810	*/
811	DECL_FORCE_INLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPUCC pVCpu, bool fIsNestedGuest)
812	{
813	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
814	bool const fHostVmcbCleanBits = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
815	if (!fIsNestedGuest)
816	return fHostVmcbCleanBits;
817	return fHostVmcbCleanBits && pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
818	}
819
820
821	/**
822	* Returns whether the decode assists feature is supported.
823	*
824	* @returns @c true if supported, @c false otherwise.
825	* @param pVCpu The cross context virtual CPU structure.
826	*/
827	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPUCC pVCpu)
828	{
829	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
830	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
831	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
832	{
833	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
834	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
835	}
836	#endif
837	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
838	}
839
840
841	/**
842	* Returns whether the NRIP_SAVE feature is supported.
843	*
844	* @returns @c true if supported, @c false otherwise.
845	* @param pVCpu The cross context virtual CPU structure.
846	*/
847	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPUCC pVCpu)
848	{
849	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
850	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
851	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
852	{
853	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
854	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
855	}
856	#endif
857	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
858	}
859
860
861	/**
862	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
863	*
864	* @param pVCpu The cross context virtual CPU structure.
865	* @param pbMsrBitmap Pointer to the MSR bitmap.
866	* @param idMsr The MSR for which the permissions are being set.
867	* @param enmRead MSR read permissions.
868	* @param enmWrite MSR write permissions.
869	*
870	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
871	* caller needs to take care of this.
872	*/
873	static void hmR0SvmSetMsrPermission(PVMCPUCC pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
874	SVMMSREXITWRITE enmWrite)
875	{
876	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
877	uint16_t offMsrpm;
878	uint8_t uMsrpmBit;
879	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
880	AssertRC(rc);
881
882	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
883	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
884
885	pbMsrBitmap += offMsrpm;
886	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
887	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
888	else
889	{
890	if (!fInNestedGuestMode)
891	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
892	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
893	else
894	{
895	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
896	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
897	pbNstGstMsrBitmap += offMsrpm;
898	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
899	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
900	else
901	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
902	}
903	#endif
904	}
905
906	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
907	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
908	else
909	{
910	if (!fInNestedGuestMode)
911	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
912	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
913	else
914	{
915	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
916	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
917	pbNstGstMsrBitmap += offMsrpm;
918	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
919	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
920	else
921	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
922	}
923	#endif
924	}
925	}
926
927
928	/**
929	* Sets up AMD-V for the specified VM.
930	* This function is only called once per-VM during initalization.
931	*
932	* @returns VBox status code.
933	* @param pVM The cross context VM structure.
934	*/
935	VMMR0DECL(int) SVMR0SetupVM(PVMCC pVM)
936	{
937	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
938	AssertReturn(pVM, VERR_INVALID_PARAMETER);
939	Assert(pVM->hm.s.svm.fSupported);
940
941	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
942	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
943	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
944
945	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
946	bool const fUseLbrVirt = fLbrVirt && pVM->hm.s.svm.fLbrVirt; /** @todo IEM implementation etc. */
947
948	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
949	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
950	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
951
952	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
953	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
954	#endif
955
956	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
957	PSVMVMCB pVmcb0 = pVCpu0->hm.s.svm.pVmcb;
958	AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
959	PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
960
961	/* Always trap #AC for reasons of security. */
962	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
963
964	/* Always trap #DB for reasons of security. */
965	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
966
967	/* Trap exceptions unconditionally (debug purposes). */
968	#ifdef HMSVM_ALWAYS_TRAP_PF
969	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_PF);
970	#endif
971	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
972	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
973	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_BP)
974	\| RT_BIT_32(X86_XCPT_DE)
975	\| RT_BIT_32(X86_XCPT_NM)
976	\| RT_BIT_32(X86_XCPT_UD)
977	\| RT_BIT_32(X86_XCPT_NP)
978	\| RT_BIT_32(X86_XCPT_SS)
979	\| RT_BIT_32(X86_XCPT_GP)
980	\| RT_BIT_32(X86_XCPT_PF)
981	\| RT_BIT_32(X86_XCPT_MF)
982	;
983	#endif
984
985	/* Apply the exceptions intercepts needed by the GIM provider. */
986	if (pVCpu0->hm.s.fGIMTrapXcptUD)
987	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
988
989	/* The mesa 3d driver hack needs #GP. */
990	if (pVCpu0->hm.s.fTrapXcptGpForLovelyMesaDrv)
991	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
992
993	/* Set up unconditional intercepts and conditions. */
994	pVmcbCtrl0->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
995	\| SVM_CTRL_INTERCEPT_VMMCALL;
996
997	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
998	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
999	#endif
1000
1001	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1002	/* Virtualized VMSAVE/VMLOAD. */
1003	pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
1004	if (!fUseVirtVmsaveVmload)
1005	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
1006	\| SVM_CTRL_INTERCEPT_VMLOAD;
1007
1008	/* Virtual GIF. */
1009	pVmcbCtrl0->IntCtrl.n.u1VGifEnable = fUseVGif;
1010	if (!fUseVGif)
1011	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
1012	\| SVM_CTRL_INTERCEPT_STGI;
1013	#endif
1014
1015	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1016	pVmcbCtrl0->u16InterceptWrCRx = RT_BIT(4);
1017
1018	/* Intercept all DRx reads and writes by default. Changed later on. */
1019	pVmcbCtrl0->u16InterceptRdDRx = 0xffff;
1020	pVmcbCtrl0->u16InterceptWrDRx = 0xffff;
1021
1022	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1023	pVmcbCtrl0->IntCtrl.n.u1VIntrMasking = 1;
1024
1025	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1026	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1027	pVmcbCtrl0->IntCtrl.n.u1IgnoreTPR = 1;
1028
1029	/* Set the IO permission bitmap physical addresses. */
1030	pVmcbCtrl0->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1031
1032	/* LBR virtualization. */
1033	pVmcbCtrl0->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1034
1035	/* The host ASID MBZ, for the guest start with 1. */
1036	pVmcbCtrl0->TLBCtrl.n.u32ASID = 1;
1037
1038	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1039	pVmcbCtrl0->NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1040
1041	/* Without Nested Paging, we need additionally intercepts. */
1042	if (!pVM->hm.s.fNestedPaging)
1043	{
1044	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1045	pVmcbCtrl0->u16InterceptRdCRx \|= RT_BIT(3);
1046	pVmcbCtrl0->u16InterceptWrCRx \|= RT_BIT(3);
1047
1048	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1049	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1050	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1051
1052	/* Page faults must be intercepted to implement shadow paging. */
1053	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1054	}
1055
1056	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1057	if (fUsePauseFilter)
1058	{
1059	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1060	pVmcbCtrl0->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1061	if (fPauseFilterThreshold)
1062	pVmcbCtrl0->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1063	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1064	}
1065
1066	/*
1067	* Setup the MSR permission bitmap.
1068	* The following MSRs are saved/restored automatically during the world-switch.
1069	* Don't intercept guest read/write accesses to these MSRs.
1070	*/
1071	uint8_t pbMsrBitmap0 = (uint8_t )pVCpu0->hm.s.svm.pvMsrBitmap;
1072	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1073	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1074	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1075	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1076	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1077	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1078	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1079	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1080	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1081	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1082	pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hm.s.svm.HCPhysMsrBitmap;
1083
1084	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1085	Assert(pVmcbCtrl0->u32VmcbCleanBits == 0);
1086
1087	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1088	{
1089	PVMCPUCC pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
1090	PSVMVMCB pVmcbCur = pVCpuCur->hm.s.svm.pVmcb;
1091	AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
1092	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1093
1094	/* Copy the VMCB control area. */
1095	memcpy(pVmcbCtrlCur, pVmcbCtrl0, sizeof(*pVmcbCtrlCur));
1096
1097	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1098	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hm.s.svm.pvMsrBitmap;
1099	memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1100	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
1101
1102	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1103	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1104
1105	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1106	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu0->hm.s.fGIMTrapXcptUD);
1107	}
1108
1109	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1110	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1111	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1112	#else
1113	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1114	#endif
1115	return VINF_SUCCESS;
1116	}
1117
1118
1119	/**
1120	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1121	*
1122	* @returns Pointer to the current context VMCB.
1123	* @param pVCpu The cross context virtual CPU structure.
1124	*/
1125	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPUCC pVCpu)
1126	{
1127	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1128	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1129	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1130	#endif
1131	return pVCpu->hm.s.svm.pVmcb;
1132	}
1133
1134
1135	/**
1136	* Gets a pointer to the nested-guest VMCB cache.
1137	*
1138	* @returns Pointer to the nested-guest VMCB cache.
1139	* @param pVCpu The cross context virtual CPU structure.
1140	*/
1141	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPUCC pVCpu)
1142	{
1143	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1144	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1145	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1146	#else
1147	RT_NOREF(pVCpu);
1148	return NULL;
1149	#endif
1150	}
1151
1152
1153	/**
1154	* Invalidates a guest page by guest virtual address.
1155	*
1156	* @returns VBox status code.
1157	* @param pVCpu The cross context virtual CPU structure.
1158	* @param GCVirt Guest virtual address of the page to invalidate.
1159	*/
1160	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1161	{
1162	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1163
1164	bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1165
1166	/* Skip it if a TLB flush is already pending. */
1167	if (!fFlushPending)
1168	{
1169	Log4Func(("%#RGv\n", GCVirt));
1170
1171	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1172	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1173
1174	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1175	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1176	}
1177	return VINF_SUCCESS;
1178	}
1179
1180
1181	/**
1182	* Flushes the appropriate tagged-TLB entries.
1183	*
1184	* @param pHostCpu The HM physical-CPU structure.
1185	* @param pVCpu The cross context virtual CPU structure.
1186	* @param pVmcb Pointer to the VM control block.
1187	*/
1188	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1189	{
1190	/*
1191	* Force a TLB flush for the first world switch if the current CPU differs from the one
1192	* we ran on last. This can happen both for start & resume due to long jumps back to
1193	* ring-3.
1194	*
1195	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1196	* correlation between it and the physical CPU.
1197	*
1198	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1199	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1200	*/
1201	bool fNewAsid = false;
1202	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1203	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1204	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1205	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1206	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1207	#endif
1208	)
1209	{
1210	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1211	pVCpu->hm.s.fForceTLBFlush = true;
1212	fNewAsid = true;
1213	}
1214
1215	/* Set TLB flush state as checked until we return from the world switch. */
1216	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1217
1218	/* Check for explicit TLB flushes. */
1219	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1220	{
1221	pVCpu->hm.s.fForceTLBFlush = true;
1222	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1223	}
1224
1225	/*
1226	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1227	* This Host CPU requirement takes precedence.
1228	*/
1229	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1230	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1231	{
1232	pHostCpu->uCurrentAsid = 1;
1233	pVCpu->hm.s.uCurrentAsid = 1;
1234	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1235	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1236	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1237
1238	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1239	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1240	}
1241	else
1242	{
1243	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1244	if (pVCpu->hm.s.fForceTLBFlush)
1245	{
1246	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1247	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1248
1249	if (fNewAsid)
1250	{
1251	++pHostCpu->uCurrentAsid;
1252
1253	bool fHitASIDLimit = false;
1254	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1255	{
1256	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1257	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1258	fHitASIDLimit = true;
1259	}
1260
1261	if ( fHitASIDLimit
1262	\|\| pHostCpu->fFlushAsidBeforeUse)
1263	{
1264	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1265	pHostCpu->fFlushAsidBeforeUse = false;
1266	}
1267
1268	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1269	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1270	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1271	}
1272	else
1273	{
1274	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1275	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1276	else
1277	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1278	}
1279
1280	pVCpu->hm.s.fForceTLBFlush = false;
1281	}
1282	}
1283
1284	/* Update VMCB with the ASID. */
1285	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1286	{
1287	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1288	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1289	}
1290
1291	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1292	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1293	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1294	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1295	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1296	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1297	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1298	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1299
1300	#ifdef VBOX_WITH_STATISTICS
1301	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1302	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1303	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1304	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1305	{
1306	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1307	}
1308	else
1309	{
1310	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1311	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1312	}
1313	#endif
1314	}
1315
1316
1317	/**
1318	* Sets an exception intercept in the specified VMCB.
1319	*
1320	* @param pVmcb Pointer to the VM control block.
1321	* @param uXcpt The exception (X86_XCPT_*).
1322	*/
1323	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1324	{
1325	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1326	{
1327	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1328	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1329	}
1330	}
1331
1332
1333	/**
1334	* Clears an exception intercept in the specified VMCB.
1335	*
1336	* @param pVCpu The cross context virtual CPU structure.
1337	* @param pVmcb Pointer to the VM control block.
1338	* @param uXcpt The exception (X86_XCPT_*).
1339	*
1340	* @remarks This takes into account if we're executing a nested-guest and only
1341	* removes the exception intercept if both the guest -and- nested-guest
1342	* are not intercepting it.
1343	*/
1344	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1345	{
1346	Assert(uXcpt != X86_XCPT_DB);
1347	Assert(uXcpt != X86_XCPT_AC);
1348	Assert(uXcpt != X86_XCPT_GP);
1349	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1350	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1351	{
1352	bool fRemove = true;
1353	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1354	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1355	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1356	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1357	{
1358	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1359	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1360	}
1361	# else
1362	RT_NOREF(pVCpu);
1363	# endif
1364	if (fRemove)
1365	{
1366	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1367	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1368	}
1369	}
1370	#else
1371	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1372	#endif
1373	}
1374
1375
1376	/**
1377	* Sets a control intercept in the specified VMCB.
1378	*
1379	* @param pVmcb Pointer to the VM control block.
1380	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1381	*/
1382	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1383	{
1384	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1385	{
1386	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1387	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1388	}
1389	}
1390
1391
1392	/**
1393	* Clears a control intercept in the specified VMCB.
1394	*
1395	* @returns @c true if the intercept is still set, @c false otherwise.
1396	* @param pVCpu The cross context virtual CPU structure.
1397	* @param pVmcb Pointer to the VM control block.
1398	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1399	*
1400	* @remarks This takes into account if we're executing a nested-guest and only
1401	* removes the control intercept if both the guest -and- nested-guest
1402	* are not intercepting it.
1403	*/
1404	static bool hmR0SvmClearCtrlIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1405	{
1406	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1407	{
1408	bool fRemove = true;
1409	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1410	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1411	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1412	{
1413	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1414	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1415	}
1416	#else
1417	RT_NOREF(pVCpu);
1418	#endif
1419	if (fRemove)
1420	{
1421	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1422	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1423	}
1424	}
1425
1426	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1427	}
1428
1429
1430	/**
1431	* Exports the guest (or nested-guest) CR0 into the VMCB.
1432	*
1433	* @param pVCpu The cross context virtual CPU structure.
1434	* @param pVmcb Pointer to the VM control block.
1435	*
1436	* @remarks This assumes we always pre-load the guest FPU.
1437	* @remarks No-long-jump zone!!!
1438	*/
1439	static void hmR0SvmExportGuestCR0(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1440	{
1441	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1442
1443	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1444	uint64_t const uGuestCr0 = pCtx->cr0;
1445	uint64_t uShadowCr0 = uGuestCr0;
1446
1447	/* Always enable caching. */
1448	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1449
1450	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1451	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1452	{
1453	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1454	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1455	}
1456
1457	/*
1458	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1459	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1460	* see @bugref{7243#c103}.
1461	*/
1462	if (!(uGuestCr0 & X86_CR0_NE))
1463	{
1464	uShadowCr0 \|= X86_CR0_NE;
1465	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1466	}
1467	else
1468	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1469
1470	/*
1471	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1472	*
1473	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1474	* see @bugref{6944}.
1475	*
1476	* We also don't ever want to honor weird things like cache disable from the guest.
1477	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1478	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1479	*/
1480	if (uShadowCr0 == uGuestCr0)
1481	{
1482	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1483	{
1484	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1485	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1486	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1487	}
1488	else
1489	{
1490	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1491	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1492	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1493	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1494	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1495	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1496	}
1497	}
1498	else
1499	{
1500	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1501	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1502	}
1503	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1504
1505	Assert(!RT_HI_U32(uShadowCr0));
1506	if (pVmcb->guest.u64CR0 != uShadowCr0)
1507	{
1508	pVmcb->guest.u64CR0 = uShadowCr0;
1509	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1510	}
1511	}
1512
1513
1514	/**
1515	* Exports the guest (or nested-guest) CR3 into the VMCB.
1516	*
1517	* @param pVCpu The cross context virtual CPU structure.
1518	* @param pVmcb Pointer to the VM control block.
1519	*
1520	* @remarks No-long-jump zone!!!
1521	*/
1522	static void hmR0SvmExportGuestCR3(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1523	{
1524	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1525
1526	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1527	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1528	if (pVM->hm.s.fNestedPaging)
1529	{
1530	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetHyperCR3(pVCpu);
1531	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1532	pVmcb->guest.u64CR3 = pCtx->cr3;
1533	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1534	}
1535	else
1536	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1537
1538	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1539	}
1540
1541
1542	/**
1543	* Exports the guest (or nested-guest) CR4 into the VMCB.
1544	*
1545	* @param pVCpu The cross context virtual CPU structure.
1546	* @param pVmcb Pointer to the VM control block.
1547	*
1548	* @remarks No-long-jump zone!!!
1549	*/
1550	static int hmR0SvmExportGuestCR4(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1551	{
1552	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1553
1554	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1555	uint64_t uShadowCr4 = pCtx->cr4;
1556	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1557	{
1558	switch (pVCpu->hm.s.enmShadowMode)
1559	{
1560	case PGMMODE_REAL:
1561	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1562	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1563
1564	case PGMMODE_32_BIT: /* 32-bit paging. */
1565	uShadowCr4 &= ~X86_CR4_PAE;
1566	break;
1567
1568	case PGMMODE_PAE: /* PAE paging. */
1569	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1570	/** Must use PAE paging as we could use physical memory > 4 GB */
1571	uShadowCr4 \|= X86_CR4_PAE;
1572	break;
1573
1574	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1575	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1576	#ifdef VBOX_WITH_64_BITS_GUESTS
1577	break;
1578	#else
1579	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1580	#endif
1581
1582	default: /* shut up gcc */
1583	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1584	}
1585	}
1586
1587	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1588	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1589
1590	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1591	if (uShadowCr4 == pCtx->cr4)
1592	{
1593	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1594	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1595	else
1596	{
1597	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1598	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1599	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1600	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1601	}
1602	}
1603	else
1604	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1605
1606	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1607	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1608
1609	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1610	Assert(!RT_HI_U32(uShadowCr4));
1611	pVmcb->guest.u64CR4 = uShadowCr4;
1612	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1613
1614	return VINF_SUCCESS;
1615	}
1616
1617
1618	/**
1619	* Exports the guest (or nested-guest) control registers into the VMCB.
1620	*
1621	* @returns VBox status code.
1622	* @param pVCpu The cross context virtual CPU structure.
1623	* @param pVmcb Pointer to the VM control block.
1624	*
1625	* @remarks No-long-jump zone!!!
1626	*/
1627	static int hmR0SvmExportGuestControlRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1628	{
1629	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1630
1631	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1632	{
1633	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1634	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1635
1636	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1637	{
1638	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1639	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1640	}
1641
1642	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1643	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1644
1645	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1646	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1647	{
1648	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1649	if (RT_FAILURE(rc))
1650	return rc;
1651	}
1652
1653	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1654	}
1655	return VINF_SUCCESS;
1656	}
1657
1658
1659	/**
1660	* Exports the guest (or nested-guest) segment registers into the VMCB.
1661	*
1662	* @returns VBox status code.
1663	* @param pVCpu The cross context virtual CPU structure.
1664	* @param pVmcb Pointer to the VM control block.
1665	*
1666	* @remarks No-long-jump zone!!!
1667	*/
1668	static void hmR0SvmExportGuestSegmentRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1669	{
1670	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1671	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1672
1673	/* Guest segment registers. */
1674	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1675	{
1676	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1677	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1678
1679	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1680	{
1681	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1682	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1683	}
1684
1685	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1686	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1687
1688	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1689	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1690
1691	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1692	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1693
1694	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1695	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1696
1697	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1698	}
1699
1700	/* Guest TR. */
1701	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1702	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1703
1704	/* Guest LDTR. */
1705	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1706	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1707
1708	/* Guest GDTR. */
1709	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1710	{
1711	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1712	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1713	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1714	}
1715
1716	/* Guest IDTR. */
1717	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1718	{
1719	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1720	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1721	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1722	}
1723
1724	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1725	\| HM_CHANGED_GUEST_TABLE_MASK);
1726	}
1727
1728
1729	/**
1730	* Exports the guest (or nested-guest) MSRs into the VMCB.
1731	*
1732	* @param pVCpu The cross context virtual CPU structure.
1733	* @param pVmcb Pointer to the VM control block.
1734	*
1735	* @remarks No-long-jump zone!!!
1736	*/
1737	static void hmR0SvmExportGuestMsrs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1738	{
1739	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1740	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1741
1742	/* Guest Sysenter MSRs. */
1743	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1744	{
1745	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1746	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1747
1748	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1749	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1750
1751	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1752	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1753	}
1754
1755	/*
1756	* Guest EFER MSR.
1757	* AMD-V requires guest EFER.SVME to be set. Weird.
1758	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1759	*/
1760	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1761	{
1762	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1763	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1764	}
1765
1766	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1767	if ( !CPUMIsGuestInLongModeEx(pCtx)
1768	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1769	{
1770	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1771	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1772	}
1773
1774	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1775	{
1776	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1777	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1778	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1779	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1780	}
1781
1782	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1783	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1784
1785	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1786	\| HM_CHANGED_GUEST_EFER_MSR
1787	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1788	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1789
1790	/*
1791	* Setup the PAT MSR (applicable for Nested Paging only).
1792	*
1793	* While guests can modify and see the modified values through the shadow values,
1794	* we shall not honor any guest modifications of this MSR to ensure caching is always
1795	* enabled similar to how we clear CR0.CD and NW bits.
1796	*
1797	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1798	*/
1799	pVmcb->guest.u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
1800
1801	/* Enable the last branch record bit if LBR virtualization is enabled. */
1802	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1803	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1804	}
1805
1806
1807	/**
1808	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1809	* the necessary intercepts accordingly.
1810	*
1811	* @param pVCpu The cross context virtual CPU structure.
1812	* @param pVmcb Pointer to the VM control block.
1813	*
1814	* @remarks No-long-jump zone!!!
1815	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1816	*/
1817	static void hmR0SvmExportSharedDebugState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1818	{
1819	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1820
1821	/*
1822	* Anyone single stepping on the host side? If so, we'll have to use the
1823	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1824	* the VMM level like the VT-x implementations does.
1825	*/
1826	bool fInterceptMovDRx = false;
1827	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1828	if (fStepping)
1829	{
1830	pVCpu->hm.s.fClearTrapFlag = true;
1831	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1832	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1833	}
1834
1835	if ( fStepping
1836	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1837	{
1838	/*
1839	* Use the combined guest and host DRx values found in the hypervisor
1840	* register set because the debugger has breakpoints active or someone
1841	* is single stepping on the host side.
1842	*
1843	* Note! DBGF expects a clean DR6 state before executing guest code.
1844	*/
1845	if (!CPUMIsHyperDebugStateActive(pVCpu))
1846	{
1847	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1848	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1849	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1850	}
1851
1852	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1853	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1854	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1855	{
1856	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1857	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1858	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1859	}
1860
1861	/** @todo If we cared, we could optimize to allow the guest to read registers
1862	* with the same values. */
1863	fInterceptMovDRx = true;
1864	pVCpu->hm.s.fUsingHyperDR7 = true;
1865	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1866	}
1867	else
1868	{
1869	/*
1870	* Update DR6, DR7 with the guest values if necessary.
1871	*/
1872	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1873	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1874	{
1875	pVmcb->guest.u64DR7 = pCtx->dr[7];
1876	pVmcb->guest.u64DR6 = pCtx->dr[6];
1877	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1878	}
1879	pVCpu->hm.s.fUsingHyperDR7 = false;
1880
1881	/*
1882	* If the guest has enabled debug registers, we need to load them prior to
1883	* executing guest code so they'll trigger at the right time.
1884	*/
1885	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1886	{
1887	if (!CPUMIsGuestDebugStateActive(pVCpu))
1888	{
1889	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1890	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1891	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1892	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1893	}
1894	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
1895	}
1896	/*
1897	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1898	* intercept #DB as DR6 is updated in the VMCB.
1899	*
1900	* Note! If we cared and dared, we could skip intercepting \#DB here.
1901	* However, \#DB shouldn't be performance critical, so we'll play safe
1902	* and keep the code similar to the VT-x code and always intercept it.
1903	*/
1904	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1905	fInterceptMovDRx = true;
1906	}
1907
1908	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1909	if (fInterceptMovDRx)
1910	{
1911	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1912	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1913	{
1914	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1915	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1916	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1917	}
1918	}
1919	else
1920	{
1921	if ( pVmcb->ctrl.u16InterceptRdDRx
1922	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1923	{
1924	pVmcb->ctrl.u16InterceptRdDRx = 0;
1925	pVmcb->ctrl.u16InterceptWrDRx = 0;
1926	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1927	}
1928	}
1929	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1930	}
1931
1932	/**
1933	* Exports the hardware virtualization state into the nested-guest
1934	* VMCB.
1935	*
1936	* @param pVCpu The cross context virtual CPU structure.
1937	* @param pVmcb Pointer to the VM control block.
1938	*
1939	* @remarks No-long-jump zone!!!
1940	*/
1941	static void hmR0SvmExportGuestHwvirtState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1942	{
1943	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1944
1945	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
1946	{
1947	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
1948	{
1949	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1950	PCVM pVM = pVCpu->CTX_SUFF(pVM);
1951
1952	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx); /* Nested VGIF is not supported yet. */
1953	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Physical hardware supports VGIF. */
1954	Assert(HMIsSvmVGifActive(pVM)); /* Outer VM has enabled VGIF. */
1955	NOREF(pVM);
1956
1957	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
1958	}
1959
1960	/*
1961	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
1962	* since SVM doesn't have a preemption timer.
1963	*
1964	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
1965	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
1966	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
1967	*/
1968	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1969	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
1970	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1971	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1972	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_PAUSE))
1973	{
1974	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1975	pVmcbCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
1976	pVmcbCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
1977	}
1978	else
1979	{
1980	/** @todo r=ramshankar: We can turn these assignments into assertions. */
1981	pVmcbCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
1982	pVmcbCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
1983	}
1984	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1985
1986	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
1987	}
1988	}
1989
1990
1991	/**
1992	* Exports the guest APIC TPR state into the VMCB.
1993	*
1994	* @returns VBox status code.
1995	* @param pVCpu The cross context virtual CPU structure.
1996	* @param pVmcb Pointer to the VM control block.
1997	*/
1998	static int hmR0SvmExportGuestApicTpr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1999	{
2000	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2001
2002	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2003	{
2004	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2005	if ( PDMHasApic(pVM)
2006	&& APICIsEnabled(pVCpu))
2007	{
2008	bool fPendingIntr;
2009	uint8_t u8Tpr;
2010	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2011	AssertRCReturn(rc, rc);
2012
2013	/* Assume that we need to trap all TPR accesses and thus need not check on
2014	every #VMEXIT if we should update the TPR. */
2015	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2016	pVCpu->hm.s.svm.fSyncVTpr = false;
2017
2018	if (!pVM->hm.s.fTPRPatchingActive)
2019	{
2020	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2021	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2022
2023	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2024	can deliver the interrupt to the guest. */
2025	if (fPendingIntr)
2026	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2027	else
2028	{
2029	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2030	pVCpu->hm.s.svm.fSyncVTpr = true;
2031	}
2032
2033	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2034	}
2035	else
2036	{
2037	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2038	pVmcb->guest.u64LSTAR = u8Tpr;
2039	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
2040
2041	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2042	if (fPendingIntr)
2043	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2044	else
2045	{
2046	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2047	pVCpu->hm.s.svm.fSyncVTpr = true;
2048	}
2049	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2050	}
2051	}
2052	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2053	}
2054	return VINF_SUCCESS;
2055	}
2056
2057
2058	/**
2059	* Sets up the exception interrupts required for guest execution in the VMCB.
2060	*
2061	* @param pVCpu The cross context virtual CPU structure.
2062	* @param pVmcb Pointer to the VM control block.
2063	*
2064	* @remarks No-long-jump zone!!!
2065	*/
2066	static void hmR0SvmExportGuestXcptIntercepts(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2067	{
2068	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2069
2070	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2071	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_SVM_XCPT_INTERCEPTS)
2072	{
2073	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2074	if (pVCpu->hm.s.fGIMTrapXcptUD)
2075	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2076	else
2077	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2078
2079	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2080	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2081	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2082	else
2083	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2084
2085	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2086	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_SVM_XCPT_INTERCEPTS);
2087	}
2088	}
2089
2090
2091	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2092	/**
2093	* Merges guest and nested-guest intercepts for executing the nested-guest using
2094	* hardware-assisted SVM.
2095	*
2096	* This merges the guest and nested-guest intercepts in a way that if the outer
2097	* guest intercept is set we need to intercept it in the nested-guest as
2098	* well.
2099	*
2100	* @param pVCpu The cross context virtual CPU structure.
2101	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2102	*/
2103	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
2104	{
2105	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2106	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2107	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2108	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2109
2110	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2111	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2112	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2113
2114	/* Always intercept CR4 writes for tracking PGM mode changes. */
2115	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2116
2117	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2118	if (!pVM->hm.s.fNestedPaging)
2119	{
2120	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2121	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2122	}
2123
2124	/** @todo Figure out debugging with nested-guests, till then just intercept
2125	* all DR[0-15] accesses. */
2126	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2127	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2128
2129	/*
2130	* Merge the guest's exception intercepts into the nested-guest VMCB.
2131	*
2132	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2133	* while executing the nested-guest.
2134	*
2135	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2136	* be tweaked later depending on how we wish to implement breakpoints.
2137	*
2138	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2139	* loaded into their guests, not ours.
2140	*
2141	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2142	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2143	*/
2144	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2145	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2146	& ~( RT_BIT(X86_XCPT_UD)
2147	\| RT_BIT(X86_XCPT_BP)
2148	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2149	#else
2150	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2151	#endif
2152
2153	/*
2154	* Adjust intercepts while executing the nested-guest that differ from the
2155	* outer guest intercepts.
2156	*
2157	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2158	* that belong to the nested-guest to the outer guest.
2159	*
2160	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2161	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2162	*/
2163	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2164	\| SVM_CTRL_INTERCEPT_VMMCALL))
2165	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2166
2167	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2168	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2169
2170	/* Finally, update the VMCB clean bits. */
2171	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2172	}
2173	#endif
2174
2175
2176	/**
2177	* Selects the appropriate function to run guest code.
2178	*
2179	* @returns VBox status code.
2180	* @param pVCpu The cross context virtual CPU structure.
2181	*
2182	* @remarks No-long-jump zone!!!
2183	*/
2184	static int hmR0SvmSelectVMRunHandler(PVMCPUCC pVCpu)
2185	{
2186	if (CPUMIsGuestInLongMode(pVCpu))
2187	{
2188	#ifndef VBOX_WITH_64_BITS_GUESTS
2189	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2190	#else
2191	# if HC_ARCH_BITS != 64 \|\| ARCH_BITS != 64
2192	# error "Only 64-bit hosts are supported!"
2193	# endif
2194	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2195	/* Guest in long mode, use 64-bit handler (host is 64-bit). */
2196	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2197	#endif
2198	}
2199	else
2200	{
2201	/* Guest is not in long mode, use the 32-bit handler. */
2202	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2203	}
2204	return VINF_SUCCESS;
2205	}
2206
2207
2208	/**
2209	* Enters the AMD-V session.
2210	*
2211	* @returns VBox status code.
2212	* @param pVCpu The cross context virtual CPU structure.
2213	*/
2214	VMMR0DECL(int) SVMR0Enter(PVMCPUCC pVCpu)
2215	{
2216	AssertPtr(pVCpu);
2217	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2218	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2219
2220	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2221	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2222	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2223
2224	pVCpu->hm.s.fLeaveDone = false;
2225	return VINF_SUCCESS;
2226	}
2227
2228
2229	/**
2230	* Thread-context callback for AMD-V.
2231	*
2232	* @param enmEvent The thread-context event.
2233	* @param pVCpu The cross context virtual CPU structure.
2234	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2235	* @thread EMT(pVCpu)
2236	*/
2237	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
2238	{
2239	NOREF(fGlobalInit);
2240
2241	switch (enmEvent)
2242	{
2243	case RTTHREADCTXEVENT_OUT:
2244	{
2245	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2246	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2247	VMCPU_ASSERT_EMT(pVCpu);
2248
2249	/* No longjmps (log-flush, locks) in this fragile context. */
2250	VMMRZCallRing3Disable(pVCpu);
2251
2252	if (!pVCpu->hm.s.fLeaveDone)
2253	{
2254	hmR0SvmLeave(pVCpu, false /* fImportState */);
2255	pVCpu->hm.s.fLeaveDone = true;
2256	}
2257
2258	/* Leave HM context, takes care of local init (term). */
2259	int rc = HMR0LeaveCpu(pVCpu);
2260	AssertRC(rc); NOREF(rc);
2261
2262	/* Restore longjmp state. */
2263	VMMRZCallRing3Enable(pVCpu);
2264	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2265	break;
2266	}
2267
2268	case RTTHREADCTXEVENT_IN:
2269	{
2270	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2271	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2272	VMCPU_ASSERT_EMT(pVCpu);
2273
2274	/* No longjmps (log-flush, locks) in this fragile context. */
2275	VMMRZCallRing3Disable(pVCpu);
2276
2277	/*
2278	* Initialize the bare minimum state required for HM. This takes care of
2279	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2280	*/
2281	int rc = hmR0EnterCpu(pVCpu);
2282	AssertRC(rc); NOREF(rc);
2283	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2284	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2285
2286	pVCpu->hm.s.fLeaveDone = false;
2287
2288	/* Restore longjmp state. */
2289	VMMRZCallRing3Enable(pVCpu);
2290	break;
2291	}
2292
2293	default:
2294	break;
2295	}
2296	}
2297
2298
2299	/**
2300	* Saves the host state.
2301	*
2302	* @returns VBox status code.
2303	* @param pVCpu The cross context virtual CPU structure.
2304	*
2305	* @remarks No-long-jump zone!!!
2306	*/
2307	VMMR0DECL(int) SVMR0ExportHostState(PVMCPUCC pVCpu)
2308	{
2309	NOREF(pVCpu);
2310
2311	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2312	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2313	return VINF_SUCCESS;
2314	}
2315
2316
2317	/**
2318	* Exports the guest or nested-guest state from the virtual-CPU context into the
2319	* VMCB.
2320	*
2321	* Also sets up the appropriate VMRUN function to execute guest or nested-guest
2322	* code based on the virtual-CPU mode.
2323	*
2324	* @returns VBox status code.
2325	* @param pVCpu The cross context virtual CPU structure.
2326	* @param pSvmTransient Pointer to the SVM-transient structure.
2327	*
2328	* @remarks No-long-jump zone!!!
2329	*/
2330	static int hmR0SvmExportGuestState(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
2331	{
2332	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2333
2334	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2335	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2336	Assert(pVmcb);
2337
2338	pVmcb->guest.u64RIP = pCtx->rip;
2339	pVmcb->guest.u64RSP = pCtx->rsp;
2340	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2341	pVmcb->guest.u64RAX = pCtx->rax;
2342
2343	bool const fIsNestedGuest = pSvmTransient->fIsNestedGuest;
2344	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2345
2346	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2347	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2348	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2349	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2350	hmR0SvmExportGuestHwvirtState(pVCpu, pVmcb);
2351
2352	ASMSetFlags(fEFlags);
2353
2354	if (!fIsNestedGuest)
2355	{
2356	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2357	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2358	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2359	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2360	}
2361
2362	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2363	AssertRCReturn(rc, rc);
2364
2365	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2366	uint64_t fUnusedMask = HM_CHANGED_GUEST_RIP
2367	\| HM_CHANGED_GUEST_RFLAGS
2368	\| HM_CHANGED_GUEST_GPRS_MASK
2369	\| HM_CHANGED_GUEST_X87
2370	\| HM_CHANGED_GUEST_SSE_AVX
2371	\| HM_CHANGED_GUEST_OTHER_XSAVE
2372	\| HM_CHANGED_GUEST_XCRx
2373	\| HM_CHANGED_GUEST_TSC_AUX
2374	\| HM_CHANGED_GUEST_OTHER_MSRS;
2375	if (fIsNestedGuest)
2376	fUnusedMask \|= HM_CHANGED_SVM_XCPT_INTERCEPTS
2377	\| HM_CHANGED_GUEST_APIC_TPR;
2378
2379	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( fUnusedMask
2380	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2381
2382	#ifdef VBOX_STRICT
2383	/*
2384	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2385	* except for the host-context and/or shared host-guest context bits.
2386	*/
2387	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2388	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2389	("fCtxChanged=%#RX64\n", fCtxChanged));
2390
2391	/*
2392	* If we need to log state that isn't always imported, we'll need to import them here.
2393	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2394	*/
2395	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2396	#endif
2397
2398	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2399	return VINF_SUCCESS;
2400	}
2401
2402
2403	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2404	/**
2405	* Merges the guest and nested-guest MSR permission bitmap.
2406	*
2407	* If the guest is intercepting an MSR we need to intercept it regardless of
2408	* whether the nested-guest is intercepting it or not.
2409	*
2410	* @param pHostCpu The HM physical-CPU structure.
2411	* @param pVCpu The cross context virtual CPU structure.
2412	*
2413	* @remarks No-long-jmp zone!!!
2414	*/
2415	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2416	{
2417	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2418	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2419	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2420
2421	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2422	uint32_t const offRsvdQwords = 0x1800 >> 3;
2423	for (uint32_t i = 0; i < offRsvdQwords; i++)
2424	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2425	}
2426
2427
2428	/**
2429	* Caches the nested-guest VMCB fields before we modify them for execution using
2430	* hardware-assisted SVM.
2431	*
2432	* @returns true if the VMCB was previously already cached, false otherwise.
2433	* @param pVCpu The cross context virtual CPU structure.
2434	*
2435	* @sa HMNotifySvmNstGstVmexit.
2436	*/
2437	static bool hmR0SvmCacheVmcbNested(PVMCPUCC pVCpu)
2438	{
2439	/*
2440	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2441	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2442	*
2443	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2444	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2445	*/
2446	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2447	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2448	if (!fWasCached)
2449	{
2450	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2451	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2452	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2453	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2454	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2455	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2456	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2457	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2458	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2459	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2460	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2461	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2462	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2463	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2464	pVmcbNstGstCache->fCacheValid = true;
2465	Log4Func(("Cached VMCB fields\n"));
2466	}
2467
2468	return fWasCached;
2469	}
2470
2471
2472	/**
2473	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2474	*
2475	* This is done the first time we enter nested-guest execution using SVM R0
2476	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2477	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2478	*
2479	* @param pVCpu The cross context virtual CPU structure.
2480	*/
2481	static void hmR0SvmSetupVmcbNested(PVMCPUCC pVCpu)
2482	{
2483	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2484	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2485
2486	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2487
2488	/*
2489	* First cache the nested-guest VMCB fields we may potentially modify.
2490	*/
2491	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2492	if (!fVmcbCached)
2493	{
2494	/*
2495	* The IOPM of the nested-guest can be ignored because the the guest always
2496	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2497	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2498	*/
2499	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2500
2501	/*
2502	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2503	* nested-paging suddenly while executing a VM (see assertion at the end of
2504	* Trap0eHandler() in PGMAllBth.h).
2505	*/
2506	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2507
2508	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2509	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2510
2511	/*
2512	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2513	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2514	*/
2515	pVCpu->hm.s.svm.fSyncVTpr = false;
2516
2517	#ifdef DEBUG_ramshankar
2518	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2519	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2520	#endif
2521
2522	/*
2523	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2524	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2525	*/
2526	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2527	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2528	\| SVM_CTRL_INTERCEPT_VMLOAD;
2529
2530	/*
2531	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2532	* CLGI/STGI instructions executed by the nested-guest.
2533	*/
2534	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2535	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2536	\| SVM_CTRL_INTERCEPT_STGI;
2537
2538	/* Merge the guest and nested-guest intercepts. */
2539	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2540
2541	/* Update the VMCB clean bits. */
2542	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2543	}
2544	else
2545	{
2546	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
2547	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2548	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2549	}
2550	}
2551	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2552
2553
2554	/**
2555	* Exports the state shared between the host and guest (or nested-guest) into
2556	* the VMCB.
2557	*
2558	* @param pVCpu The cross context virtual CPU structure.
2559	* @param pVmcb Pointer to the VM control block.
2560	*
2561	* @remarks No-long-jump zone!!!
2562	*/
2563	static void hmR0SvmExportSharedState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2564	{
2565	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2566	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2567
2568	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2569	{
2570	/** @todo Figure out stepping with nested-guest. */
2571	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2572	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2573	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2574	else
2575	{
2576	pVmcb->guest.u64DR6 = pCtx->dr[6];
2577	pVmcb->guest.u64DR7 = pCtx->dr[7];
2578	}
2579	}
2580
2581	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2582	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2583	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2584	}
2585
2586
2587	/**
2588	* Worker for SVMR0ImportStateOnDemand.
2589	*
2590	* @param pVCpu The cross context virtual CPU structure.
2591	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2592	*/
2593	static void hmR0SvmImportGuestState(PVMCPUCC pVCpu, uint64_t fWhat)
2594	{
2595	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2596
2597	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2598	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2599	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2600	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2601
2602	/*
2603	* We disable interrupts to make the updating of the state and in particular
2604	* the fExtrn modification atomic wrt to preemption hooks.
2605	*/
2606	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2607
2608	fWhat &= pCtx->fExtrn;
2609	if (fWhat)
2610	{
2611	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2612	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2613	{
2614	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2615	{
2616	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2617	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2618	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2619	}
2620	}
2621
2622	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2623	{
2624	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2625	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2626	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2627	}
2628	#endif
2629
2630	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2631	{
2632	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2633	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2634	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2635	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2636	}
2637
2638	if (fWhat & CPUMCTX_EXTRN_RIP)
2639	pCtx->rip = pVmcbGuest->u64RIP;
2640
2641	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2642	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2643
2644	if (fWhat & CPUMCTX_EXTRN_RSP)
2645	pCtx->rsp = pVmcbGuest->u64RSP;
2646
2647	if (fWhat & CPUMCTX_EXTRN_RAX)
2648	pCtx->rax = pVmcbGuest->u64RAX;
2649
2650	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2651	{
2652	if (fWhat & CPUMCTX_EXTRN_CS)
2653	{
2654	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2655	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2656	/** @todo SELM might need to be fixed as it too should not care about the
2657	* granularity bit. See @bugref{6785}. */
2658	if ( !pCtx->cs.Attr.n.u1Granularity
2659	&& pCtx->cs.Attr.n.u1Present
2660	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2661	{
2662	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2663	pCtx->cs.Attr.n.u1Granularity = 1;
2664	}
2665	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2666	}
2667	if (fWhat & CPUMCTX_EXTRN_SS)
2668	{
2669	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2670	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2671	/*
2672	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2673	* VMCB and uses that and thus it's possible that when the CPL changes during
2674	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2675	* AMD Fusion CPUs with 64-bit guests.
2676	*
2677	* See AMD spec. 15.5.1 "Basic operation".
2678	*/
2679	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2680	uint8_t const uCpl = pVmcbGuest->u8CPL;
2681	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2682	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2683	}
2684	if (fWhat & CPUMCTX_EXTRN_DS)
2685	{
2686	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2687	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2688	}
2689	if (fWhat & CPUMCTX_EXTRN_ES)
2690	{
2691	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2692	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2693	}
2694	if (fWhat & CPUMCTX_EXTRN_FS)
2695	{
2696	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2697	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2698	}
2699	if (fWhat & CPUMCTX_EXTRN_GS)
2700	{
2701	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2702	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2703	}
2704	}
2705
2706	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2707	{
2708	if (fWhat & CPUMCTX_EXTRN_TR)
2709	{
2710	/*
2711	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2712	* are used between Intel and AMD, see @bugref{6208#c39}.
2713	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2714	*/
2715	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2716	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2717	{
2718	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2719	\|\| CPUMIsGuestInLongModeEx(pCtx))
2720	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2721	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2722	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2723	}
2724	}
2725
2726	if (fWhat & CPUMCTX_EXTRN_LDTR)
2727	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2728
2729	if (fWhat & CPUMCTX_EXTRN_GDTR)
2730	{
2731	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2732	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2733	}
2734
2735	if (fWhat & CPUMCTX_EXTRN_IDTR)
2736	{
2737	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2738	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2739	}
2740	}
2741
2742	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2743	{
2744	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2745	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2746	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2747	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2748	}
2749
2750	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2751	{
2752	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2753	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2754	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2755	}
2756
2757	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2758	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2759
2760	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2761	{
2762	if (fWhat & CPUMCTX_EXTRN_DR6)
2763	{
2764	if (!pVCpu->hm.s.fUsingHyperDR7)
2765	pCtx->dr[6] = pVmcbGuest->u64DR6;
2766	else
2767	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2768	}
2769
2770	if (fWhat & CPUMCTX_EXTRN_DR7)
2771	{
2772	if (!pVCpu->hm.s.fUsingHyperDR7)
2773	pCtx->dr[7] = pVmcbGuest->u64DR7;
2774	else
2775	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2776	}
2777	}
2778
2779	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2780	{
2781	if (fWhat & CPUMCTX_EXTRN_CR0)
2782	{
2783	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2784	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2785	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2786	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2787	CPUMSetGuestCR0(pVCpu, uCr0);
2788	VMMRZCallRing3Enable(pVCpu);
2789	}
2790
2791	if (fWhat & CPUMCTX_EXTRN_CR2)
2792	pCtx->cr2 = pVmcbGuest->u64CR2;
2793
2794	if (fWhat & CPUMCTX_EXTRN_CR3)
2795	{
2796	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2797	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2798	{
2799	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2800	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2801	}
2802	}
2803
2804	/* Changes to CR4 are always intercepted. */
2805	}
2806
2807	/* Update fExtrn. */
2808	pCtx->fExtrn &= ~fWhat;
2809
2810	/* If everything has been imported, clear the HM keeper bit. */
2811	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2812	{
2813	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2814	Assert(!pCtx->fExtrn);
2815	}
2816	}
2817	else
2818	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
2819
2820	ASMSetFlags(fEFlags);
2821
2822	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
2823
2824	/*
2825	* Honor any pending CR3 updates.
2826	*
2827	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
2828	* -> SVMR0CallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
2829	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
2830	* handling -> hmR0SvmImportGuestState() and here we are.
2831	*
2832	* The reason for such complicated handling is because VM-exits that call into PGM expect
2833	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
2834	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
2835	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
2836	*
2837	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
2838	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
2839	*/
2840	if ( VMMRZCallRing3IsEnabled(pVCpu)
2841	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2842	{
2843	Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
2844	PGMUpdateCR3(pVCpu, pCtx->cr3);
2845	}
2846	}
2847
2848
2849	/**
2850	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2851	* context.
2852	*
2853	* Currently there is no residual state left in the CPU that is not updated in the
2854	* VMCB.
2855	*
2856	* @returns VBox status code.
2857	* @param pVCpu The cross context virtual CPU structure.
2858	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2859	*/
2860	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2861	{
2862	hmR0SvmImportGuestState(pVCpu, fWhat);
2863	return VINF_SUCCESS;
2864	}
2865
2866
2867	/**
2868	* Does the necessary state syncing before returning to ring-3 for any reason
2869	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2870	*
2871	* @param pVCpu The cross context virtual CPU structure.
2872	* @param fImportState Whether to import the guest state from the VMCB back
2873	* to the guest-CPU context.
2874	*
2875	* @remarks No-long-jmp zone!!!
2876	*/
2877	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState)
2878	{
2879	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2880	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2881	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2882
2883	/*
2884	* !!! IMPORTANT !!!
2885	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2886	*/
2887
2888	/* Save the guest state if necessary. */
2889	if (fImportState)
2890	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2891
2892	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2893	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2894	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2895
2896	/*
2897	* Restore host debug registers if necessary and resync on next R0 reentry.
2898	*/
2899	#ifdef VBOX_STRICT
2900	if (CPUMIsHyperDebugStateActive(pVCpu))
2901	{
2902	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2903	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2904	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2905	}
2906	#endif
2907	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2908	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2909	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2910
2911	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2912	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
2913	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
2914	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
2915	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
2916	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
2917	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2918
2919	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2920	}
2921
2922
2923	/**
2924	* Leaves the AMD-V session.
2925	*
2926	* Only used while returning to ring-3 either due to longjump or exits to
2927	* ring-3.
2928	*
2929	* @returns VBox status code.
2930	* @param pVCpu The cross context virtual CPU structure.
2931	*/
2932	static int hmR0SvmLeaveSession(PVMCPUCC pVCpu)
2933	{
2934	HM_DISABLE_PREEMPT(pVCpu);
2935	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2936	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2937
2938	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2939	and done this from the SVMR0ThreadCtxCallback(). */
2940	if (!pVCpu->hm.s.fLeaveDone)
2941	{
2942	hmR0SvmLeave(pVCpu, true /* fImportState */);
2943	pVCpu->hm.s.fLeaveDone = true;
2944	}
2945
2946	/*
2947	* !!! IMPORTANT !!!
2948	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2949	*/
2950
2951	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2952	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2953	VMMR0ThreadCtxHookDisable(pVCpu);
2954
2955	/* Leave HM context. This takes care of local init (term). */
2956	int rc = HMR0LeaveCpu(pVCpu);
2957
2958	HM_RESTORE_PREEMPT();
2959	return rc;
2960	}
2961
2962
2963	/**
2964	* Does the necessary state syncing before doing a longjmp to ring-3.
2965	*
2966	* @returns VBox status code.
2967	* @param pVCpu The cross context virtual CPU structure.
2968	*
2969	* @remarks No-long-jmp zone!!!
2970	*/
2971	static int hmR0SvmLongJmpToRing3(PVMCPUCC pVCpu)
2972	{
2973	return hmR0SvmLeaveSession(pVCpu);
2974	}
2975
2976
2977	/**
2978	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2979	* any remaining host state) before we longjump to ring-3 and possibly get
2980	* preempted.
2981	*
2982	* @param pVCpu The cross context virtual CPU structure.
2983	* @param enmOperation The operation causing the ring-3 longjump.
2984	*/
2985	VMMR0DECL(int) SVMR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
2986	{
2987	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2988	{
2989	/*
2990	* !!! IMPORTANT !!!
2991	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2992	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2993	*/
2994	VMMRZCallRing3RemoveNotification(pVCpu);
2995	VMMRZCallRing3Disable(pVCpu);
2996	HM_DISABLE_PREEMPT(pVCpu);
2997
2998	/* Import the entire guest state. */
2999	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3000
3001	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3002	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3003
3004	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3005	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3006
3007	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3008	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3009	VMMR0ThreadCtxHookDisable(pVCpu);
3010
3011	/* Leave HM context. This takes care of local init (term). */
3012	HMR0LeaveCpu(pVCpu);
3013
3014	HM_RESTORE_PREEMPT();
3015	return VINF_SUCCESS;
3016	}
3017
3018	Assert(pVCpu);
3019	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3020	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3021
3022	VMMRZCallRing3Disable(pVCpu);
3023	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3024
3025	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3026	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3027	AssertRCReturn(rc, rc);
3028
3029	VMMRZCallRing3Enable(pVCpu);
3030	return VINF_SUCCESS;
3031	}
3032
3033
3034	/**
3035	* Take necessary actions before going back to ring-3.
3036	*
3037	* An action requires us to go back to ring-3. This function does the necessary
3038	* steps before we can safely return to ring-3. This is not the same as longjmps
3039	* to ring-3, this is voluntary.
3040	*
3041	* @returns VBox status code.
3042	* @param pVCpu The cross context virtual CPU structure.
3043	* @param rcExit The reason for exiting to ring-3. Can be
3044	* VINF_VMM_UNKNOWN_RING3_CALL.
3045	*/
3046	static int hmR0SvmExitToRing3(PVMCPUCC pVCpu, int rcExit)
3047	{
3048	Assert(pVCpu);
3049	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3050
3051	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3052	VMMRZCallRing3Disable(pVCpu);
3053	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", rcExit, (uint64_t)pVCpu->fLocalForcedActions,
3054	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3055
3056	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3057	if (pVCpu->hm.s.Event.fPending)
3058	{
3059	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3060	Assert(!pVCpu->hm.s.Event.fPending);
3061	}
3062
3063	/* Sync. the necessary state for going back to ring-3. */
3064	hmR0SvmLeaveSession(pVCpu);
3065	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3066
3067	/* Thread-context hooks are unregistered at this point!!! */
3068	/* Ring-3 callback notifications are unregistered at this point!!! */
3069
3070	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3071	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3072	\| CPUM_CHANGED_LDTR
3073	\| CPUM_CHANGED_GDTR
3074	\| CPUM_CHANGED_IDTR
3075	\| CPUM_CHANGED_TR
3076	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3077	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
3078	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3079	{
3080	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3081	}
3082
3083	/* Update the exit-to-ring 3 reason. */
3084	pVCpu->hm.s.rcLastExitToR3 = rcExit;
3085
3086	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3087	if ( rcExit != VINF_EM_RAW_INTERRUPT
3088	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3089	{
3090	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3091	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3092	}
3093
3094	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3095	VMMRZCallRing3Enable(pVCpu);
3096
3097	/*
3098	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3099	* and if we're injecting an event we should have a TRPM trap pending.
3100	*/
3101	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3102	pVCpu->hm.s.u32HMError = rcExit,
3103	VERR_SVM_IPE_5);
3104	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3105	pVCpu->hm.s.u32HMError = rcExit,
3106	VERR_SVM_IPE_4);
3107
3108	return rcExit;
3109	}
3110
3111
3112	/**
3113	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3114	* intercepts.
3115	*
3116	* @param pVCpu The cross context virtual CPU structure.
3117	* @param pVmcb Pointer to the VM control block.
3118	*
3119	* @remarks No-long-jump zone!!!
3120	*/
3121	static void hmR0SvmUpdateTscOffsetting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3122	{
3123	/*
3124	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3125	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3126	* RDTSC/RDTSCP as well.
3127	*/
3128	bool fParavirtTsc;
3129	uint64_t uTscOffset;
3130	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3131
3132	bool fIntercept;
3133	if (fCanUseRealTsc)
3134	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3135	else
3136	{
3137	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3138	fIntercept = true;
3139	}
3140
3141	if (!fIntercept)
3142	{
3143	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3144	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3145	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3146	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
3147	#endif
3148
3149	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3150	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3151	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3152	}
3153
3154	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3155	information before every VM-entry, hence we have nothing to do here at the moment. */
3156	if (fParavirtTsc)
3157	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3158	}
3159
3160
3161	/**
3162	* Sets an event as a pending event to be injected into the guest.
3163	*
3164	* @param pVCpu The cross context virtual CPU structure.
3165	* @param pEvent Pointer to the SVM event.
3166	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3167	* page-fault.
3168	*
3169	* @remarks Statistics counter assumes this is a guest event being reflected to
3170	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3171	*/
3172	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPUCC pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3173	{
3174	Assert(!pVCpu->hm.s.Event.fPending);
3175	Assert(pEvent->n.u1Valid);
3176
3177	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3178	pVCpu->hm.s.Event.fPending = true;
3179	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3180
3181	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3182	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3183	}
3184
3185
3186	/**
3187	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3188	*
3189	* @param pVCpu The cross context virtual CPU structure.
3190	*/
3191	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPUCC pVCpu)
3192	{
3193	SVMEVENT Event;
3194	Event.u = 0;
3195	Event.n.u1Valid = 1;
3196	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3197	Event.n.u8Vector = X86_XCPT_UD;
3198	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3199	}
3200
3201
3202	/**
3203	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3204	*
3205	* @param pVCpu The cross context virtual CPU structure.
3206	*/
3207	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPUCC pVCpu)
3208	{
3209	SVMEVENT Event;
3210	Event.u = 0;
3211	Event.n.u1Valid = 1;
3212	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3213	Event.n.u8Vector = X86_XCPT_DB;
3214	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3215	}
3216
3217
3218	/**
3219	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3220	*
3221	* @param pVCpu The cross context virtual CPU structure.
3222	* @param u32ErrCode The error-code for the page-fault.
3223	* @param uFaultAddress The page fault address (CR2).
3224	*
3225	* @remarks This updates the guest CR2 with @a uFaultAddress!
3226	*/
3227	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPUCC pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3228	{
3229	SVMEVENT Event;
3230	Event.u = 0;
3231	Event.n.u1Valid = 1;
3232	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3233	Event.n.u8Vector = X86_XCPT_PF;
3234	Event.n.u1ErrorCodeValid = 1;
3235	Event.n.u32ErrorCode = u32ErrCode;
3236
3237	/* Update CR2 of the guest. */
3238	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3239	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3240	{
3241	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3242	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3243	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3244	}
3245
3246	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3247	}
3248
3249
3250	/**
3251	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3252	*
3253	* @param pVCpu The cross context virtual CPU structure.
3254	*/
3255	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPUCC pVCpu)
3256	{
3257	SVMEVENT Event;
3258	Event.u = 0;
3259	Event.n.u1Valid = 1;
3260	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3261	Event.n.u8Vector = X86_XCPT_MF;
3262	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3263	}
3264
3265
3266	/**
3267	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3268	*
3269	* @param pVCpu The cross context virtual CPU structure.
3270	*/
3271	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPUCC pVCpu)
3272	{
3273	SVMEVENT Event;
3274	Event.u = 0;
3275	Event.n.u1Valid = 1;
3276	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3277	Event.n.u8Vector = X86_XCPT_DF;
3278	Event.n.u1ErrorCodeValid = 1;
3279	Event.n.u32ErrorCode = 0;
3280	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3281	}
3282
3283
3284	/**
3285	* Injects an event into the guest upon VMRUN by updating the relevant field
3286	* in the VMCB.
3287	*
3288	* @param pVCpu The cross context virtual CPU structure.
3289	* @param pVmcb Pointer to the guest VM control block.
3290	* @param pEvent Pointer to the event.
3291	*
3292	* @remarks No-long-jump zone!!!
3293	* @remarks Requires CR0!
3294	*/
3295	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3296	{
3297	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3298	pVmcb->ctrl.EventInject.u = pEvent->u;
3299	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3300	RT_NOREF(pVCpu);
3301
3302	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3303	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3304	}
3305
3306
3307
3308	/**
3309	* Converts any TRPM trap into a pending HM event. This is typically used when
3310	* entering from ring-3 (not longjmp returns).
3311	*
3312	* @param pVCpu The cross context virtual CPU structure.
3313	*/
3314	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
3315	{
3316	Assert(TRPMHasTrap(pVCpu));
3317	Assert(!pVCpu->hm.s.Event.fPending);
3318
3319	uint8_t uVector;
3320	TRPMEVENT enmTrpmEvent;
3321	uint32_t uErrCode;
3322	RTGCUINTPTR GCPtrFaultAddress;
3323	uint8_t cbInstr;
3324
3325	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, NULL /* pfIcebp */);
3326	AssertRC(rc);
3327
3328	SVMEVENT Event;
3329	Event.u = 0;
3330	Event.n.u1Valid = 1;
3331	Event.n.u8Vector = uVector;
3332
3333	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3334	if (enmTrpmEvent == TRPM_TRAP)
3335	{
3336	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3337	switch (uVector)
3338	{
3339	case X86_XCPT_NMI:
3340	{
3341	Event.n.u3Type = SVM_EVENT_NMI;
3342	break;
3343	}
3344
3345	case X86_XCPT_BP:
3346	case X86_XCPT_OF:
3347	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3348	RT_FALL_THRU();
3349
3350	case X86_XCPT_PF:
3351	case X86_XCPT_DF:
3352	case X86_XCPT_TS:
3353	case X86_XCPT_NP:
3354	case X86_XCPT_SS:
3355	case X86_XCPT_GP:
3356	case X86_XCPT_AC:
3357	{
3358	Event.n.u1ErrorCodeValid = 1;
3359	Event.n.u32ErrorCode = uErrCode;
3360	break;
3361	}
3362	}
3363	}
3364	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3365	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3366	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3367	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3368	else
3369	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3370
3371	rc = TRPMResetTrap(pVCpu);
3372	AssertRC(rc);
3373
3374	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3375	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3376
3377	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3378	}
3379
3380
3381	/**
3382	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3383	* AMD-V to execute any instruction.
3384	*
3385	* @param pVCpu The cross context virtual CPU structure.
3386	*/
3387	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu)
3388	{
3389	Assert(pVCpu->hm.s.Event.fPending);
3390	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3391
3392	SVMEVENT Event;
3393	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3394
3395	uint8_t uVector = Event.n.u8Vector;
3396	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3397
3398	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3399
3400	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3401	AssertRC(rc);
3402
3403	if (Event.n.u1ErrorCodeValid)
3404	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3405
3406	if ( enmTrapType == TRPM_TRAP
3407	&& uVector == X86_XCPT_PF)
3408	{
3409	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3410	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3411	}
3412	else if (enmTrapType == TRPM_SOFTWARE_INT)
3413	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3414	pVCpu->hm.s.Event.fPending = false;
3415	}
3416
3417
3418	/**
3419	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3420	* now.
3421	*
3422	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3423	* @param pVCpu The cross context virtual CPU structure.
3424	*
3425	* @remarks No-long-jump zone!!!
3426	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3427	*/
3428	static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
3429	{
3430	/*
3431	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3432	* completes. Check if we should inhibit interrupts or clear any existing
3433	* interrupt inhibition.
3434	*/
3435	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3436	{
3437	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3438	{
3439	/*
3440	* We can clear the inhibit force flag as even if we go back to the recompiler
3441	* without executing guest code in AMD-V, the flag's condition to be cleared is
3442	* met and thus the cleared state is correct.
3443	*/
3444	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3445	return false;
3446	}
3447	return true;
3448	}
3449	return false;
3450	}
3451
3452
3453	/**
3454	* Sets the virtual interrupt intercept control in the VMCB.
3455	*
3456	* @param pVCpu The cross context virtual CPU structure.
3457	* @param pVmcb Pointer to the VM control block.
3458	*/
3459	static void hmR0SvmSetIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3460	{
3461	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3462
3463	/*
3464	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3465	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3466	* (updating ISR at the right time) and inject the interrupt.
3467	*
3468	* With AVIC is supported, we could make use of the asynchronously delivery without
3469	* #VMEXIT and we would be passing the AVIC page to SVM.
3470	*
3471	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3472	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3473	*/
3474	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3475	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3476	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3477	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3478	Log4(("Set VINTR intercept\n"));
3479	}
3480
3481
3482	/**
3483	* Clears the virtual interrupt intercept control in the VMCB as
3484	* we are figured the guest is unable process any interrupts
3485	* at this point of time.
3486	*
3487	* @param pVCpu The cross context virtual CPU structure.
3488	* @param pVmcb Pointer to the VM control block.
3489	*/
3490	static void hmR0SvmClearIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3491	{
3492	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3493
3494	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3495	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3496	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3497	{
3498	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3499	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3500	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3501	Log4(("Cleared VINTR intercept\n"));
3502	}
3503	}
3504
3505
3506	/**
3507	* Evaluates the event to be delivered to the guest and sets it as the pending
3508	* event.
3509	*
3510	* @returns Strict VBox status code.
3511	* @param pVCpu The cross context virtual CPU structure.
3512	* @param pSvmTransient Pointer to the SVM transient structure.
3513	*/
3514	static VBOXSTRICTRC hmR0SvmEvaluatePendingEvent(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
3515	{
3516	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3517	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3518	\| CPUMCTX_EXTRN_RFLAGS
3519	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3520	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3521
3522	Assert(!pVCpu->hm.s.Event.fPending);
3523	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3524	Assert(pVmcb);
3525
3526	bool const fGif = CPUMGetGuestGif(pCtx);
3527	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3528	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3529
3530	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3531	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3532	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3533
3534	/** @todo SMI. SMIs take priority over NMIs. */
3535
3536	/*
3537	* Check if the guest or nested-guest can receive NMIs.
3538	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3539	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3540	*/
3541	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3542	&& !fBlockNmi)
3543	{
3544	if ( fGif
3545	&& !fIntShadow)
3546	{
3547	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3548	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3549	{
3550	Log4(("Intercepting NMI -> #VMEXIT\n"));
3551	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3552	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3553	}
3554	#endif
3555	Log4(("Setting NMI pending for injection\n"));
3556	SVMEVENT Event;
3557	Event.u = 0;
3558	Event.n.u1Valid = 1;
3559	Event.n.u8Vector = X86_XCPT_NMI;
3560	Event.n.u3Type = SVM_EVENT_NMI;
3561	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3562	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3563	}
3564	else if (!fGif)
3565	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3566	else if (!pSvmTransient->fIsNestedGuest)
3567	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3568	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3569	}
3570	/*
3571	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3572	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3573	* it from the APIC device.
3574	*
3575	* For nested-guests, physical interrupts always take priority over virtual interrupts.
3576	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3577	* do that work when we execute nested-guest code esp. since all the required information
3578	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3579	* the virtual interrupt controller.
3580	*
3581	* See AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3582	*/
3583	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3584	&& !pVCpu->hm.s.fSingleInstruction)
3585	{
3586	bool const fBlockInt = !pSvmTransient->fIsNestedGuest ? !(pCtx->eflags.u32 & X86_EFL_IF)
3587	: CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx);
3588	if ( fGif
3589	&& !fBlockInt
3590	&& !fIntShadow)
3591	{
3592	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3593	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3594	{
3595	Log4(("Intercepting INTR -> #VMEXIT\n"));
3596	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3597	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3598	}
3599	#endif
3600	uint8_t u8Interrupt;
3601	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3602	if (RT_SUCCESS(rc))
3603	{
3604	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3605	SVMEVENT Event;
3606	Event.u = 0;
3607	Event.n.u1Valid = 1;
3608	Event.n.u8Vector = u8Interrupt;
3609	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3610	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3611	}
3612	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3613	{
3614	/*
3615	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3616	* updated eventually when the TPR is written by the guest.
3617	*/
3618	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3619	}
3620	else
3621	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3622	}
3623	else if (!fGif)
3624	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3625	else if (!pSvmTransient->fIsNestedGuest)
3626	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3627	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3628	}
3629
3630	return VINF_SUCCESS;
3631	}
3632
3633
3634	/**
3635	* Injects any pending events into the guest (or nested-guest).
3636	*
3637	* @param pVCpu The cross context virtual CPU structure.
3638	* @param pVmcb Pointer to the VM control block.
3639	*
3640	* @remarks Must only be called when we are guaranteed to enter
3641	* hardware-assisted SVM execution and not return to ring-3
3642	* prematurely.
3643	*/
3644	static void hmR0SvmInjectPendingEvent(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3645	{
3646	Assert(!TRPMHasTrap(pVCpu));
3647	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3648
3649	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3650	#ifdef VBOX_STRICT
3651	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3652	bool const fGif = CPUMGetGuestGif(pCtx);
3653	bool fAllowInt = fGif;
3654	if (fGif)
3655	{
3656	/*
3657	* For nested-guests we have no way to determine if we're injecting a physical or
3658	* virtual interrupt at this point. Hence the partial verification below.
3659	*/
3660	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3661	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3662	else
3663	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3664	}
3665	#endif
3666
3667	if (pVCpu->hm.s.Event.fPending)
3668	{
3669	SVMEVENT Event;
3670	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3671	Assert(Event.n.u1Valid);
3672
3673	/*
3674	* Validate event injection pre-conditions.
3675	*/
3676	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3677	{
3678	Assert(fAllowInt);
3679	Assert(!fIntShadow);
3680	}
3681	else if (Event.n.u3Type == SVM_EVENT_NMI)
3682	{
3683	Assert(fGif);
3684	Assert(!fIntShadow);
3685	}
3686
3687	/*
3688	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3689	* do this only when we are surely going to inject the NMI as otherwise if we return
3690	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3691	* SVM R0.
3692	*
3693	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3694	* which will set the VMCS field after actually delivering the NMI which we read on
3695	* VM-exit to determine the state.
3696	*/
3697	if ( Event.n.u3Type == SVM_EVENT_NMI
3698	&& Event.n.u8Vector == X86_XCPT_NMI
3699	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3700	{
3701	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3702	}
3703
3704	/*
3705	* Inject it (update VMCB for injection by the hardware).
3706	*/
3707	Log4(("Injecting pending HM event\n"));
3708	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
3709	pVCpu->hm.s.Event.fPending = false;
3710
3711	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3712	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3713	else
3714	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3715	}
3716	else
3717	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3718
3719	/*
3720	* We could have injected an NMI through IEM and continue guest execution using
3721	* hardware-assisted SVM. In which case, we would not have any events pending (above)
3722	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
3723	*/
3724	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3725	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
3726
3727	/*
3728	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3729	*
3730	* For nested-guests: We need to update it too for the scenario where IEM executes
3731	* the nested-guest but execution later continues here with an interrupt shadow active.
3732	*/
3733	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3734	}
3735
3736
3737	/**
3738	* Reports world-switch error and dumps some useful debug info.
3739	*
3740	* @param pVCpu The cross context virtual CPU structure.
3741	* @param rcVMRun The return code from VMRUN (or
3742	* VERR_SVM_INVALID_GUEST_STATE for invalid
3743	* guest-state).
3744	*/
3745	static void hmR0SvmReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun)
3746	{
3747	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3748	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
3749	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3750
3751	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3752	{
3753	#ifdef VBOX_STRICT
3754	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
3755	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3756	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3757	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3758	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3759	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3760	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3761	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3762	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3763	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3764	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3765	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3766
3767	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3768	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3769	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3770
3771	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3772	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3773	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3774	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3775	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3776	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3777	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3778	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3779	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3780	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3781	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3782	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3783
3784	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3785	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3786	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3787	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3788	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3789	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3790	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3791	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3792	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3793	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3794	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3795	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3796	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3797	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3798	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3799	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3800	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3801	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3802	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3803	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3804
3805	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3806
3807	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3808	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3809
3810	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3811	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3812	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3813	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3814	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3815	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3816	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3817	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3818	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3819	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3820	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3821	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3822	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3823	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3824	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3825	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3826	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3827	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3828	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3829	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3830
3831	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3832	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3833
3834	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3835	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3836	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3837	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3838
3839	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3840	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3841
3842	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3843	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3844	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3845	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3846
3847	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3848	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3849	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3850	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3851	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3852	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3853	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3854
3855	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3856	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3857	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3858	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3859
3860	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3861	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3862	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3863
3864	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3865	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3866	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3867	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3868	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3869	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3870	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
3871	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3872	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3873	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3874	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3875	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3876
3877	NOREF(pVmcb);
3878	#endif /* VBOX_STRICT */
3879	}
3880	else
3881	Log4Func(("rcVMRun=%d\n", rcVMRun));
3882	}
3883
3884
3885	/**
3886	* Check per-VM and per-VCPU force flag actions that require us to go back to
3887	* ring-3 for one reason or another.
3888	*
3889	* @returns VBox status code (information status code included).
3890	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3891	* ring-3.
3892	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3893	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3894	* interrupts)
3895	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3896	* all EMTs to be in ring-3.
3897	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3898	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3899	* to the EM loop.
3900	*
3901	* @param pVCpu The cross context virtual CPU structure.
3902	*/
3903	static int hmR0SvmCheckForceFlags(PVMCPUCC pVCpu)
3904	{
3905	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3906	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3907
3908	/* Could happen as a result of longjump. */
3909	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3910	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
3911
3912	/* Update pending interrupts into the APIC's IRR. */
3913	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3914	APICUpdatePendingInterrupts(pVCpu);
3915
3916	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3917	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
3918	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3919	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
3920	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3921	{
3922	/* Pending PGM C3 sync. */
3923	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3924	{
3925	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
3926	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3927	if (rc != VINF_SUCCESS)
3928	{
3929	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3930	return rc;
3931	}
3932	}
3933
3934	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3935	/* -XXX- what was that about single stepping? */
3936	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
3937	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3938	{
3939	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3940	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
3941	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3942	return rc;
3943	}
3944
3945	/* Pending VM request packets, such as hardware interrupts. */
3946	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
3947	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
3948	{
3949	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
3950	Log4Func(("Pending VM request forcing us back to ring-3\n"));
3951	return VINF_EM_PENDING_REQUEST;
3952	}
3953
3954	/* Pending PGM pool flushes. */
3955	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3956	{
3957	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
3958	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
3959	return VINF_PGM_POOL_FLUSH_PENDING;
3960	}
3961
3962	/* Pending DMA requests. */
3963	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
3964	{
3965	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
3966	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
3967	return VINF_EM_RAW_TO_R3;
3968	}
3969	}
3970
3971	return VINF_SUCCESS;
3972	}
3973
3974
3975	/**
3976	* Does the preparations before executing guest code in AMD-V.
3977	*
3978	* This may cause longjmps to ring-3 and may even result in rescheduling to the
3979	* recompiler. We must be cautious what we do here regarding committing
3980	* guest-state information into the VMCB assuming we assuredly execute the guest
3981	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
3982	* clearing the common-state (TRPM/forceflags), we must undo those changes so
3983	* that the recompiler can (and should) use them when it resumes guest
3984	* execution. Otherwise such operations must be done when we can no longer
3985	* exit to ring-3.
3986	*
3987	* @returns VBox status code (informational status codes included).
3988	* @retval VINF_SUCCESS if we can proceed with running the guest.
3989	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3990	*
3991	* @param pVCpu The cross context virtual CPU structure.
3992	* @param pSvmTransient Pointer to the SVM transient structure.
3993	*/
3994	static int hmR0SvmPreRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
3995	{
3996	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3997
3998	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3999	if (pSvmTransient->fIsNestedGuest)
4000	{
4001	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4002	return VINF_EM_RESCHEDULE_REM;
4003	}
4004	#endif
4005
4006	/* Check force flag actions that might require us to go back to ring-3. */
4007	int rc = hmR0SvmCheckForceFlags(pVCpu);
4008	if (rc != VINF_SUCCESS)
4009	return rc;
4010
4011	if (TRPMHasTrap(pVCpu))
4012	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4013	else if (!pVCpu->hm.s.Event.fPending)
4014	{
4015	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEvent(pVCpu, pSvmTransient);
4016	if ( rcStrict != VINF_SUCCESS
4017	\|\| pSvmTransient->fIsNestedGuest != CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4018	{
4019	/* If a nested-guest VM-exit occurred, bail. */
4020	if (pSvmTransient->fIsNestedGuest)
4021	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4022	return VBOXSTRICTRC_VAL(rcStrict);
4023	}
4024	}
4025
4026	/*
4027	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4028	* Just do it in software, see @bugref{8411}.
4029	* NB: If we could continue a task switch exit we wouldn't need to do this.
4030	*/
4031	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4032	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4033	&& pVCpu->hm.s.Event.fPending
4034	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4035	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4036
4037	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4038	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4039	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4040	#endif
4041
4042	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4043	/*
4044	* Set up the nested-guest VMCB for execution using hardware-assisted SVM.
4045	*/
4046	if (pSvmTransient->fIsNestedGuest)
4047	hmR0SvmSetupVmcbNested(pVCpu);
4048	#endif
4049
4050	/*
4051	* Export the guest state bits that are not shared with the host in any way as we can
4052	* longjmp or get preempted in the midst of exporting some of the state.
4053	*/
4054	rc = hmR0SvmExportGuestState(pVCpu, pSvmTransient);
4055	AssertRCReturn(rc, rc);
4056	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4057
4058	/* Ensure we've cached (and hopefully modified) the nested-guest VMCB for execution using hardware-assisted SVM. */
4059	Assert(!pSvmTransient->fIsNestedGuest \|\| pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4060
4061	/*
4062	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4063	* world-switch so we can update it on the way back if the guest changed the TPR.
4064	*/
4065	if (pVCpu->hm.s.svm.fSyncVTpr)
4066	{
4067	Assert(!pSvmTransient->fIsNestedGuest);
4068	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4069	if (pVM->hm.s.fTPRPatchingActive)
4070	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4071	else
4072	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4073	}
4074
4075	/*
4076	* No longjmps to ring-3 from this point on!!!
4077	*
4078	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4079	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4080	*/
4081	VMMRZCallRing3Disable(pVCpu);
4082
4083	/*
4084	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4085	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4086	* preemption disabled for a while. Since this is purly to aid the
4087	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4088	* disable interrupt on NT.
4089	*
4090	* We need to check for force-flags that could've possible been altered since we last
4091	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4092	* see @bugref{6398}).
4093	*
4094	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4095	* to ring-3 before executing guest code.
4096	*/
4097	pSvmTransient->fEFlags = ASMIntDisableFlags();
4098	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4099	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4100	{
4101	ASMSetFlags(pSvmTransient->fEFlags);
4102	VMMRZCallRing3Enable(pVCpu);
4103	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4104	return VINF_EM_RAW_TO_R3;
4105	}
4106	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4107	{
4108	ASMSetFlags(pSvmTransient->fEFlags);
4109	VMMRZCallRing3Enable(pVCpu);
4110	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4111	return VINF_EM_RAW_INTERRUPT;
4112	}
4113
4114	return VINF_SUCCESS;
4115	}
4116
4117
4118	/**
4119	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4120	* doing so.
4121	*
4122	* This means there is no backing out to ring-3 or anywhere else at this point.
4123	*
4124	* @param pVCpu The cross context virtual CPU structure.
4125	* @param pSvmTransient Pointer to the SVM transient structure.
4126	*
4127	* @remarks Called with preemption disabled.
4128	* @remarks No-long-jump zone!!!
4129	*/
4130	static void hmR0SvmPreRunGuestCommitted(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4131	{
4132	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4133	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4134	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4135
4136	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4137	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4138
4139	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4140	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4141
4142	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4143
4144	if (!CPUMIsGuestFPUStateActive(pVCpu))
4145	{
4146	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4147	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4148	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4149	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4150	}
4151
4152	/* Load the state shared between host and guest (FPU, debug). */
4153	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4154	hmR0SvmExportSharedState(pVCpu, pVmcb);
4155
4156	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4157	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4158
4159	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4160	RTCPUID const idHostCpu = pHostCpu->idCpu;
4161	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4162
4163	/* Setup TSC offsetting. */
4164	if ( pSvmTransient->fUpdateTscOffsetting
4165	\|\| fMigratedHostCpu)
4166	{
4167	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4168	pSvmTransient->fUpdateTscOffsetting = false;
4169	}
4170
4171	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
4172	if (!(pVmcb->ctrl.u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
4173	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4174	else
4175	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4176
4177	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4178	if (fMigratedHostCpu)
4179	pVmcb->ctrl.u32VmcbCleanBits = 0;
4180
4181	/* Store status of the shared guest-host state at the time of VMRUN. */
4182	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4183	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4184
4185	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4186	uint8_t *pbMsrBitmap;
4187	if (!pSvmTransient->fIsNestedGuest)
4188	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4189	else
4190	{
4191	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4192
4193	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4194	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4195	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4196	}
4197	#else
4198	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4199	#endif
4200
4201	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4202	/* Flush the appropriate tagged-TLB entries. */
4203	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4204	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4205
4206	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4207
4208	TMNotifyStartOfExecution(pVM, pVCpu); /* Finally, notify TM to resume its clocks as we're about
4209	to start executing. */
4210
4211	/*
4212	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4213	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4214	*
4215	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4216	*/
4217	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4218	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4219	{
4220	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4221	pVCpu->hm.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4222	if (uGuestTscAux != pVCpu->hm.s.svm.u64HostTscAux)
4223	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4224	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4225	pSvmTransient->fRestoreTscAuxMsr = true;
4226	}
4227	else
4228	{
4229	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4230	pSvmTransient->fRestoreTscAuxMsr = false;
4231	}
4232	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4233
4234	/*
4235	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4236	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4237	* from the VMCB.
4238	*/
4239	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pSvmTransient->fIsNestedGuest);
4240	if (!fSupportsVmcbCleanBits)
4241	pVmcb->ctrl.u32VmcbCleanBits = 0;
4242	}
4243
4244
4245	/**
4246	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4247	*
4248	* @returns VBox strict status code.
4249	* @param pVCpu The cross context virtual CPU structure.
4250	* @param HCPhysVmcb The host physical address of the VMCB.
4251	*
4252	* @remarks No-long-jump zone!!!
4253	*/
4254	DECLINLINE(int) hmR0SvmRunGuest(PVMCPUCC pVCpu, RTHCPHYS HCPhysVmcb)
4255	{
4256	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4257	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4258	pCtx->fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4259
4260	/*
4261	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4262	* floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4263	* callee-saved and thus the need for this XMM wrapper.
4264	*
4265	* Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4266	*/
4267	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4268	#ifdef VBOX_WITH_KERNEL_USING_XMM
4269	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu, pVCpu->hm.s.svm.pfnVMRun);
4270	#else
4271	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu);
4272	#endif
4273	}
4274
4275
4276	/**
4277	* Performs some essential restoration of state after running guest (or
4278	* nested-guest) code in AMD-V.
4279	*
4280	* @param pVCpu The cross context virtual CPU structure.
4281	* @param pSvmTransient Pointer to the SVM transient structure.
4282	* @param rcVMRun Return code of VMRUN.
4283	*
4284	* @remarks Called with interrupts disabled.
4285	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4286	* unconditionally when it is safe to do so.
4287	*/
4288	static void hmR0SvmPostRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4289	{
4290	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4291
4292	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4293	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4294	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4295
4296	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4297	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4298
4299	/* TSC read must be done early for maximum accuracy. */
4300	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4301	{
4302	if (!pSvmTransient->fIsNestedGuest)
4303	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4304	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4305	else
4306	{
4307	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4308	uint64_t const uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4309	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4310	}
4311	#endif
4312	}
4313
4314	if (pSvmTransient->fRestoreTscAuxMsr)
4315	{
4316	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4317	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4318	if (u64GuestTscAuxMsr != pVCpu->hm.s.svm.u64HostTscAux)
4319	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.svm.u64HostTscAux);
4320	}
4321
4322	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4323	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4324	TMNotifyEndOfExecution(pVM, pVCpu); /* Notify TM that the guest is no longer running. */
4325	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4326
4327	Assert(!(ASMGetFlags() & X86_EFL_IF));
4328	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4329	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4330
4331	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4332	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4333	{
4334	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4335	return;
4336	}
4337
4338	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4339	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4340	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4341	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4342
4343	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4344	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4345	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4346	#else
4347	/*
4348	* Always import the following:
4349	*
4350	* - RIP for exit optimizations and evaluating event injection on re-entry.
4351	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4352	* state on preemption.
4353	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4354	* - CS for exit optimizations.
4355	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4356	* assembly switcher code.
4357	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4358	*/
4359	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4360	\| CPUMCTX_EXTRN_RFLAGS
4361	\| CPUMCTX_EXTRN_RAX
4362	\| CPUMCTX_EXTRN_RSP
4363	\| CPUMCTX_EXTRN_CS
4364	\| CPUMCTX_EXTRN_HWVIRT
4365	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4366	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4367	\| HMSVM_CPUMCTX_SHARED_STATE);
4368	#endif
4369
4370	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4371	&& pVCpu->hm.s.svm.fSyncVTpr)
4372	{
4373	Assert(!pSvmTransient->fIsNestedGuest);
4374	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4375	if ( pVM->hm.s.fTPRPatchingActive
4376	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4377	{
4378	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4379	AssertRC(rc);
4380	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4381	}
4382	/* Sync TPR when we aren't intercepting CR8 writes. */
4383	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4384	{
4385	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4386	AssertRC(rc);
4387	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4388	}
4389	}
4390
4391	#ifdef DEBUG_ramshankar
4392	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4393	{
4394	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4395	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4396	0 /* uVerbose */);
4397	}
4398	#endif
4399
4400	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4401	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4402	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, uHostTsc);
4403	}
4404
4405
4406	/**
4407	* Runs the guest code using AMD-V.
4408	*
4409	* @returns VBox status code.
4410	* @param pVCpu The cross context virtual CPU structure.
4411	* @param pcLoops Pointer to the number of executed loops.
4412	*/
4413	static int hmR0SvmRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
4414	{
4415	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4416	Assert(pcLoops);
4417	Assert(*pcLoops <= cMaxResumeLoops);
4418
4419	SVMTRANSIENT SvmTransient;
4420	RT_ZERO(SvmTransient);
4421	SvmTransient.fUpdateTscOffsetting = true;
4422	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4423
4424	int rc = VERR_INTERNAL_ERROR_5;
4425	for (;;)
4426	{
4427	Assert(!HMR0SuspendPending());
4428	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4429
4430	/* Preparatory work for running nested-guest code, this may force us to return to
4431	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4432	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4433	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4434	if (rc != VINF_SUCCESS)
4435	break;
4436
4437	/*
4438	* No longjmps to ring-3 from this point on!!!
4439	*
4440	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4441	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4442	*/
4443	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4444	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4445
4446	/* Restore any residual host-state and save any bits shared between host and guest
4447	into the guest-CPU state. Re-enables interrupts! */
4448	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4449
4450	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4451	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4452	{
4453	if (rc == VINF_SUCCESS)
4454	rc = VERR_SVM_INVALID_GUEST_STATE;
4455	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4456	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4457	break;
4458	}
4459
4460	/* Handle the #VMEXIT. */
4461	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4462	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4463	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4464	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4465	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4466	if (rc != VINF_SUCCESS)
4467	break;
4468	if (++(*pcLoops) >= cMaxResumeLoops)
4469	{
4470	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4471	rc = VINF_EM_RAW_INTERRUPT;
4472	break;
4473	}
4474	}
4475
4476	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4477	return rc;
4478	}
4479
4480
4481	/**
4482	* Runs the guest code using AMD-V in single step mode.
4483	*
4484	* @returns VBox status code.
4485	* @param pVCpu The cross context virtual CPU structure.
4486	* @param pcLoops Pointer to the number of executed loops.
4487	*/
4488	static int hmR0SvmRunGuestCodeStep(PVMCPUCC pVCpu, uint32_t *pcLoops)
4489	{
4490	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4491	Assert(pcLoops);
4492	Assert(*pcLoops <= cMaxResumeLoops);
4493
4494	SVMTRANSIENT SvmTransient;
4495	RT_ZERO(SvmTransient);
4496	SvmTransient.fUpdateTscOffsetting = true;
4497	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4498
4499	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4500	uint16_t uCsStart = pCtx->cs.Sel;
4501	uint64_t uRipStart = pCtx->rip;
4502
4503	int rc = VERR_INTERNAL_ERROR_5;
4504	for (;;)
4505	{
4506	Assert(!HMR0SuspendPending());
4507	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4508	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4509	(unsigned)RTMpCpuId(), *pcLoops));
4510
4511	/* Preparatory work for running nested-guest code, this may force us to return to
4512	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4513	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4514	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4515	if (rc != VINF_SUCCESS)
4516	break;
4517
4518	/*
4519	* No longjmps to ring-3 from this point on!!!
4520	*
4521	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4522	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4523	*/
4524	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4525
4526	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4527
4528	/* Restore any residual host-state and save any bits shared between host and guest
4529	into the guest-CPU state. Re-enables interrupts! */
4530	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4531
4532	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4533	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4534	{
4535	if (rc == VINF_SUCCESS)
4536	rc = VERR_SVM_INVALID_GUEST_STATE;
4537	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4538	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4539	return rc;
4540	}
4541
4542	/* Handle the #VMEXIT. */
4543	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4544	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4545	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4546	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4547	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4548	if (rc != VINF_SUCCESS)
4549	break;
4550	if (++(*pcLoops) >= cMaxResumeLoops)
4551	{
4552	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4553	rc = VINF_EM_RAW_INTERRUPT;
4554	break;
4555	}
4556
4557	/*
4558	* Did the RIP change, if so, consider it a single step.
4559	* Otherwise, make sure one of the TFs gets set.
4560	*/
4561	if ( pCtx->rip != uRipStart
4562	\|\| pCtx->cs.Sel != uCsStart)
4563	{
4564	rc = VINF_EM_DBG_STEPPED;
4565	break;
4566	}
4567	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4568	}
4569
4570	/*
4571	* Clear the X86_EFL_TF if necessary.
4572	*/
4573	if (pVCpu->hm.s.fClearTrapFlag)
4574	{
4575	pVCpu->hm.s.fClearTrapFlag = false;
4576	pCtx->eflags.Bits.u1TF = 0;
4577	}
4578
4579	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4580	return rc;
4581	}
4582
4583	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4584	/**
4585	* Runs the nested-guest code using AMD-V.
4586	*
4587	* @returns VBox status code.
4588	* @param pVCpu The cross context virtual CPU structure.
4589	* @param pcLoops Pointer to the number of executed loops. If we're switching
4590	* from the guest-code execution loop to this nested-guest
4591	* execution loop pass the remainder value, else pass 0.
4592	*/
4593	static int hmR0SvmRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
4594	{
4595	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4596	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4597	Assert(pcLoops);
4598	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops);
4599
4600	SVMTRANSIENT SvmTransient;
4601	RT_ZERO(SvmTransient);
4602	SvmTransient.fUpdateTscOffsetting = true;
4603	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4604	SvmTransient.fIsNestedGuest = true;
4605
4606	int rc = VERR_INTERNAL_ERROR_4;
4607	for (;;)
4608	{
4609	Assert(!HMR0SuspendPending());
4610	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4611
4612	/* Preparatory work for running nested-guest code, this may force us to return to
4613	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4614	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4615	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4616	if ( rc != VINF_SUCCESS
4617	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4618	break;
4619
4620	/*
4621	* No longjmps to ring-3 from this point on!!!
4622	*
4623	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4624	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4625	*/
4626	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4627
4628	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
4629
4630	/* Restore any residual host-state and save any bits shared between host and guest
4631	into the guest-CPU state. Re-enables interrupts! */
4632	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4633
4634	if (RT_LIKELY( rc == VINF_SUCCESS
4635	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4636	{ /* extremely likely */ }
4637	else
4638	{
4639	/* VMRUN failed, shouldn't really happen, Guru. */
4640	if (rc != VINF_SUCCESS)
4641	break;
4642
4643	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4644	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4645	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4646	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4647	break;
4648	}
4649
4650	/* Handle the #VMEXIT. */
4651	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4652	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4653	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4654	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
4655	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4656	if (rc == VINF_SUCCESS)
4657	{
4658	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4659	{
4660	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4661	rc = VINF_SVM_VMEXIT;
4662	}
4663	else
4664	{
4665	if (++(*pcLoops) <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
4666	continue;
4667	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4668	rc = VINF_EM_RAW_INTERRUPT;
4669	}
4670	}
4671	else
4672	Assert(rc != VINF_SVM_VMEXIT);
4673	break;
4674	/** @todo NSTSVM: handle single-stepping. */
4675	}
4676
4677	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4678	return rc;
4679	}
4680	#endif
4681
4682
4683	/**
4684	* Runs the guest code using AMD-V.
4685	*
4686	* @returns Strict VBox status code.
4687	* @param pVCpu The cross context virtual CPU structure.
4688	*/
4689	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPUCC pVCpu)
4690	{
4691	AssertPtr(pVCpu);
4692	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4693	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4694	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4695	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4696
4697	uint32_t cLoops = 0;
4698	int rc;
4699	for (;;)
4700	{
4701	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4702	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
4703	#else
4704	NOREF(pCtx);
4705	bool const fInNestedGuestMode = false;
4706	#endif
4707	if (!fInNestedGuestMode)
4708	{
4709	if (!pVCpu->hm.s.fSingleInstruction)
4710	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
4711	else
4712	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
4713	}
4714	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4715	else
4716	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
4717
4718	if (rc == VINF_SVM_VMRUN)
4719	{
4720	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4721	continue;
4722	}
4723	if (rc == VINF_SVM_VMEXIT)
4724	{
4725	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4726	continue;
4727	}
4728	#endif
4729	break;
4730	}
4731
4732	/* Fixup error codes. */
4733	if (rc == VERR_EM_INTERPRETER)
4734	rc = VINF_EM_RAW_EMULATE_INSTR;
4735	else if (rc == VINF_EM_RESET)
4736	rc = VINF_EM_TRIPLE_FAULT;
4737
4738	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4739	rc = hmR0SvmExitToRing3(pVCpu, rc);
4740	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4741	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4742	return rc;
4743	}
4744
4745
4746	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4747	/**
4748	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
4749	*
4750	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4751	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4752	*/
4753	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4754	{
4755	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4756	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4757	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4758	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4759	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
4760	const bool fRep = pIoExitInfo->n.u1Rep;
4761	const bool fStrIo = pIoExitInfo->n.u1Str;
4762
4763	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4764	NULL /* pIoExitInfo */);
4765	}
4766
4767
4768	/**
4769	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4770	* SVM_EXIT_INVALID).
4771	*
4772	* @returns VBox status code (informational status codes included).
4773	* @param pVCpu The cross context virtual CPU structure.
4774	* @param pSvmTransient Pointer to the SVM transient structure.
4775	*/
4776	static int hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4777	{
4778	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4779	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4780	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4781
4782	/*
4783	* We import the complete state here because we use separate VMCBs for the guest and the
4784	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
4785	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
4786	*/
4787	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4788	do { \
4789	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
4790	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2))); \
4791	} while (0)
4792
4793	/*
4794	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
4795	* nested-guest. If it isn't, it should be handled by the (outer) guest.
4796	*/
4797	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
4798	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4799	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4800	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4801	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4802	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4803
4804	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4805	switch (uExitCode)
4806	{
4807	case SVM_EXIT_CPUID:
4808	{
4809	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4810	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4811	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
4812	}
4813
4814	case SVM_EXIT_RDTSC:
4815	{
4816	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4817	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4818	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
4819	}
4820
4821	case SVM_EXIT_RDTSCP:
4822	{
4823	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4824	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4825	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
4826	}
4827
4828	case SVM_EXIT_MONITOR:
4829	{
4830	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4831	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4832	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
4833	}
4834
4835	case SVM_EXIT_MWAIT:
4836	{
4837	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4838	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4839	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
4840	}
4841
4842	case SVM_EXIT_HLT:
4843	{
4844	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4845	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4846	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
4847	}
4848
4849	case SVM_EXIT_MSR:
4850	{
4851	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4852	{
4853	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
4854	uint16_t offMsrpm;
4855	uint8_t uMsrpmBit;
4856	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4857	if (RT_SUCCESS(rc))
4858	{
4859	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
4860	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
4861
4862	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4863	pbMsrBitmap += offMsrpm;
4864	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
4865	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
4866
4867	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4868	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4869	{
4870	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4871	}
4872	}
4873	else
4874	{
4875	/*
4876	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4877	* See AMD-V spec. "15.11 MSR Intercepts".
4878	*/
4879	Assert(rc == VERR_OUT_OF_RANGE);
4880	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4881	}
4882	}
4883	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
4884	}
4885
4886	case SVM_EXIT_IOIO:
4887	{
4888	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4889	{
4890	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
4891	SVMIOIOEXITINFO IoExitInfo;
4892	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4893	bool const fIntercept = hmR0SvmIsIoInterceptSet(pvIoBitmap, &IoExitInfo);
4894	if (fIntercept)
4895	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4896	}
4897	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
4898	}
4899
4900	case SVM_EXIT_XCPT_PF:
4901	{
4902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4903	if (pVM->hm.s.fNestedPaging)
4904	{
4905	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4906	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4907
4908	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4909	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4910	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4911
4912	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
4913	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
4914	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
4915	return VINF_SUCCESS;
4916	}
4917	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
4918	}
4919
4920	case SVM_EXIT_XCPT_UD:
4921	{
4922	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
4923	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4924	hmR0SvmSetPendingXcptUD(pVCpu);
4925	return VINF_SUCCESS;
4926	}
4927
4928	case SVM_EXIT_XCPT_MF:
4929	{
4930	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
4931	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4932	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
4933	}
4934
4935	case SVM_EXIT_XCPT_DB:
4936	{
4937	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
4938	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4939	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
4940	}
4941
4942	case SVM_EXIT_XCPT_AC:
4943	{
4944	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
4945	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4946	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
4947	}
4948
4949	case SVM_EXIT_XCPT_BP:
4950	{
4951	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
4952	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4953	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
4954	}
4955
4956	case SVM_EXIT_READ_CR0:
4957	case SVM_EXIT_READ_CR3:
4958	case SVM_EXIT_READ_CR4:
4959	{
4960	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
4961	if (CPUMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
4962	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4963	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
4964	}
4965
4966	case SVM_EXIT_CR0_SEL_WRITE:
4967	{
4968	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
4969	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4970	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
4971	}
4972
4973	case SVM_EXIT_WRITE_CR0:
4974	case SVM_EXIT_WRITE_CR3:
4975	case SVM_EXIT_WRITE_CR4:
4976	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
4977	{
4978	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
4979	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
4980
4981	if (CPUMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
4982	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4983	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
4984	}
4985
4986	case SVM_EXIT_PAUSE:
4987	{
4988	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
4989	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4990	return hmR0SvmExitPause(pVCpu, pSvmTransient);
4991	}
4992
4993	case SVM_EXIT_VINTR:
4994	{
4995	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
4996	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4997	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
4998	}
4999
5000	case SVM_EXIT_INTR:
5001	case SVM_EXIT_NMI:
5002	case SVM_EXIT_SMI:
5003	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5004	{
5005	/*
5006	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5007	*
5008	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5009	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5010	* nested-guest #VMEXIT.
5011	*
5012	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5013	* while trying to inject interrupts, see comment at the top of this function.
5014	*/
5015	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5016	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5017	}
5018
5019	case SVM_EXIT_FERR_FREEZE:
5020	{
5021	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5022	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5023	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5024	}
5025
5026	case SVM_EXIT_INVLPG:
5027	{
5028	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5029	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5030	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5031	}
5032
5033	case SVM_EXIT_WBINVD:
5034	{
5035	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5036	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5037	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5038	}
5039
5040	case SVM_EXIT_INVD:
5041	{
5042	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5043	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5044	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5045	}
5046
5047	case SVM_EXIT_RDPMC:
5048	{
5049	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5050	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5051	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5052	}
5053
5054	default:
5055	{
5056	switch (uExitCode)
5057	{
5058	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5059	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5060	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5061	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5062	{
5063	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5064	if (CPUMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5065	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5066	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5067	}
5068
5069	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5070	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5071	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5072	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5073	{
5074	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5075	if (CPUMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5076	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5077	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5078	}
5079
5080	case SVM_EXIT_XCPT_DE:
5081	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5082	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5083	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5084	case SVM_EXIT_XCPT_OF:
5085	case SVM_EXIT_XCPT_BR:
5086	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5087	case SVM_EXIT_XCPT_NM:
5088	case SVM_EXIT_XCPT_DF:
5089	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5090	case SVM_EXIT_XCPT_TS:
5091	case SVM_EXIT_XCPT_NP:
5092	case SVM_EXIT_XCPT_SS:
5093	case SVM_EXIT_XCPT_GP:
5094	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5095	case SVM_EXIT_XCPT_15: /* Reserved. */
5096	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5097	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5098	case SVM_EXIT_XCPT_MC:
5099	case SVM_EXIT_XCPT_XF:
5100	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5101	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5102	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5103	{
5104	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5105	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5106	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5107	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5108	}
5109
5110	case SVM_EXIT_XSETBV:
5111	{
5112	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5113	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5114	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5115	}
5116
5117	case SVM_EXIT_TASK_SWITCH:
5118	{
5119	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5120	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5121	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5122	}
5123
5124	case SVM_EXIT_IRET:
5125	{
5126	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5127	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5128	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5129	}
5130
5131	case SVM_EXIT_SHUTDOWN:
5132	{
5133	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5134	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5135	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5136	}
5137
5138	case SVM_EXIT_VMMCALL:
5139	{
5140	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5141	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5142	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5143	}
5144
5145	case SVM_EXIT_CLGI:
5146	{
5147	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5148	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5149	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5150	}
5151
5152	case SVM_EXIT_STGI:
5153	{
5154	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5155	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5156	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5157	}
5158
5159	case SVM_EXIT_VMLOAD:
5160	{
5161	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5162	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5163	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5164	}
5165
5166	case SVM_EXIT_VMSAVE:
5167	{
5168	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5169	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5170	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5171	}
5172
5173	case SVM_EXIT_INVLPGA:
5174	{
5175	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5176	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5177	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5178	}
5179
5180	case SVM_EXIT_VMRUN:
5181	{
5182	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5183	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5184	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5185	}
5186
5187	case SVM_EXIT_RSM:
5188	{
5189	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5190	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5191	hmR0SvmSetPendingXcptUD(pVCpu);
5192	return VINF_SUCCESS;
5193	}
5194
5195	case SVM_EXIT_SKINIT:
5196	{
5197	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5198	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5199	hmR0SvmSetPendingXcptUD(pVCpu);
5200	return VINF_SUCCESS;
5201	}
5202
5203	case SVM_EXIT_NPF:
5204	{
5205	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5206	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5207	}
5208
5209	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5210	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5211
5212	default:
5213	{
5214	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5215	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5216	return VERR_SVM_UNKNOWN_EXIT;
5217	}
5218	}
5219	}
5220	}
5221	/* not reached */
5222
5223	#undef NST_GST_VMEXIT_CALL_RET
5224	}
5225	#endif
5226
5227
5228	/**
5229	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5230	*
5231	* @returns VBox status code (informational status codes included).
5232	* @param pVCpu The cross context virtual CPU structure.
5233	* @param pSvmTransient Pointer to the SVM transient structure.
5234	*/
5235	static int hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5236	{
5237	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5238	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5239
5240	#ifdef DEBUG_ramshankar
5241	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5242	do { \
5243	if ((a_fDbg) == 1) \
5244	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5245	int rc = a_CallExpr; \
5246	if ((a_fDbg) == 1) \
5247	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5248	return rc; \
5249	} while (0)
5250	#else
5251	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5252	#endif
5253
5254	/*
5255	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5256	* for most guests under normal workloads (for some definition of "normal").
5257	*/
5258	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5259	switch (uExitCode)
5260	{
5261	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5262	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5263	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5264	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5265	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5266	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5267	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5268	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5269	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5270	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5271
5272	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5273	case SVM_EXIT_INTR:
5274	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5275
5276	case SVM_EXIT_READ_CR0:
5277	case SVM_EXIT_READ_CR3:
5278	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5279
5280	case SVM_EXIT_CR0_SEL_WRITE:
5281	case SVM_EXIT_WRITE_CR0:
5282	case SVM_EXIT_WRITE_CR3:
5283	case SVM_EXIT_WRITE_CR4:
5284	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5285
5286	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5287	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5288	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5289	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5290	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5291	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5292	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5293	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5294	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5295	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5296	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5297	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5298	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5299	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5300	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5301	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5302
5303	default:
5304	{
5305	switch (pSvmTransient->u64ExitCode)
5306	{
5307	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5308	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5309	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5310	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5311	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5312
5313	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5314	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5315	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5316	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5317	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5318
5319	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5320	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5321
5322	case SVM_EXIT_SMI:
5323	case SVM_EXIT_INIT:
5324	{
5325	/*
5326	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5327	* If it ever does, we want to know about it so log the exit code and bail.
5328	*/
5329	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5330	}
5331
5332	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5333	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5334	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5335	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5336	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5337	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5338	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5339	#else
5340	case SVM_EXIT_CLGI:
5341	case SVM_EXIT_STGI:
5342	case SVM_EXIT_VMLOAD:
5343	case SVM_EXIT_VMSAVE:
5344	case SVM_EXIT_INVLPGA:
5345	case SVM_EXIT_VMRUN:
5346	#endif
5347	case SVM_EXIT_RSM:
5348	case SVM_EXIT_SKINIT:
5349	{
5350	hmR0SvmSetPendingXcptUD(pVCpu);
5351	return VINF_SUCCESS;
5352	}
5353
5354	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5355	case SVM_EXIT_XCPT_DE:
5356	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5357	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5358	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5359	case SVM_EXIT_XCPT_OF:
5360	case SVM_EXIT_XCPT_BR:
5361	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5362	case SVM_EXIT_XCPT_NM:
5363	case SVM_EXIT_XCPT_DF:
5364	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5365	case SVM_EXIT_XCPT_TS:
5366	case SVM_EXIT_XCPT_NP:
5367	case SVM_EXIT_XCPT_SS:
5368	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5369	/* SVM_EXIT_XCPT_PF: */
5370	case SVM_EXIT_XCPT_15: /* Reserved. */
5371	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5372	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5373	case SVM_EXIT_XCPT_MC:
5374	case SVM_EXIT_XCPT_XF:
5375	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5376	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5377	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5378	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5379	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5380
5381	default:
5382	{
5383	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5384	pVCpu->hm.s.u32HMError = uExitCode;
5385	return VERR_SVM_UNKNOWN_EXIT;
5386	}
5387	}
5388	}
5389	}
5390	/* not reached */
5391	#undef VMEXIT_CALL_RET
5392	}
5393
5394
5395	#ifdef VBOX_STRICT
5396	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5397	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5398	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5399
5400	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5401	do \
5402	{ \
5403	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5404	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5405	} while (0)
5406
5407	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5408	do { \
5409	AssertPtr((a_pVCpu)); \
5410	AssertPtr((a_pSvmTransient)); \
5411	Assert(ASMIntAreEnabled()); \
5412	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5413	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5414	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5415	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5416	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5417	HMSVM_ASSERT_PREEMPT_CPUID(); \
5418	} while (0)
5419	#else
5420	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5421	do { \
5422	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5423	} while (0)
5424	#endif
5425
5426
5427	/**
5428	* Gets the IEM exception flags for the specified SVM event.
5429	*
5430	* @returns The IEM exception flags.
5431	* @param pEvent Pointer to the SVM event.
5432	*
5433	* @remarks This function currently only constructs flags required for
5434	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5435	* and CR2 aspects of an exception are not included).
5436	*/
5437	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5438	{
5439	uint8_t const uEventType = pEvent->n.u3Type;
5440	uint32_t fIemXcptFlags;
5441	switch (uEventType)
5442	{
5443	case SVM_EVENT_EXCEPTION:
5444	/*
5445	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5446	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5447	*/
5448	if (pEvent->n.u8Vector == X86_XCPT_BP)
5449	{
5450	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5451	break;
5452	}
5453	if (pEvent->n.u8Vector == X86_XCPT_OF)
5454	{
5455	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5456	break;
5457	}
5458	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5459	RT_FALL_THRU();
5460	case SVM_EVENT_NMI:
5461	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5462	break;
5463
5464	case SVM_EVENT_EXTERNAL_IRQ:
5465	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5466	break;
5467
5468	case SVM_EVENT_SOFTWARE_INT:
5469	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5470	break;
5471
5472	default:
5473	fIemXcptFlags = 0;
5474	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5475	break;
5476	}
5477	return fIemXcptFlags;
5478	}
5479
5480
5481	/**
5482	* Handle a condition that occurred while delivering an event through the guest
5483	* IDT.
5484	*
5485	* @returns VBox status code (informational error codes included).
5486	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5487	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5488	* continue execution of the guest which will delivery the \#DF.
5489	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5490	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5491	*
5492	* @param pVCpu The cross context virtual CPU structure.
5493	* @param pSvmTransient Pointer to the SVM transient structure.
5494	*
5495	* @remarks No-long-jump zone!!!
5496	*/
5497	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5498	{
5499	int rc = VINF_SUCCESS;
5500	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5501	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5502
5503	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5504	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5505	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5506
5507	/*
5508	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5509	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5510	*
5511	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5512	*/
5513	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5514	{
5515	IEMXCPTRAISE enmRaise;
5516	IEMXCPTRAISEINFO fRaiseInfo;
5517	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5518	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5519	if (fExitIsHwXcpt)
5520	{
5521	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5522	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5523	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5524	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5525	}
5526	else
5527	{
5528	/*
5529	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5530	* then we end up here.
5531	*
5532	* If the event was:
5533	* - a software interrupt, we can re-execute the instruction which will
5534	* regenerate the event.
5535	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5536	* - a hardware exception or external interrupt, we re-inject it.
5537	*/
5538	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5539	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5540	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5541	else
5542	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5543	}
5544
5545	switch (enmRaise)
5546	{
5547	case IEMXCPTRAISE_CURRENT_XCPT:
5548	case IEMXCPTRAISE_PREV_EVENT:
5549	{
5550	/* For software interrupts, we shall re-execute the instruction. */
5551	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5552	{
5553	RTGCUINTPTR GCPtrFaultAddress = 0;
5554
5555	/* If we are re-injecting an NMI, clear NMI blocking. */
5556	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5557	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5558
5559	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5560	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5561	{
5562	pSvmTransient->fVectoringPF = true;
5563	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5564	pVCpu->cpum.GstCtx.cr2));
5565	}
5566	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5567	&& uIdtVector == X86_XCPT_PF)
5568	{
5569	/*
5570	* If the previous exception was a #PF, we need to recover the CR2 value.
5571	* This can't happen with shadow paging.
5572	*/
5573	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5574	}
5575
5576	/*
5577	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5578	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5579	*/
5580	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5581	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
5582	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5583
5584	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5585	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5586	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5587	}
5588	break;
5589	}
5590
5591	case IEMXCPTRAISE_REEXEC_INSTR:
5592	{
5593	Assert(rc == VINF_SUCCESS);
5594	break;
5595	}
5596
5597	case IEMXCPTRAISE_DOUBLE_FAULT:
5598	{
5599	/*
5600	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5601	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5602	* converted into a #DF.
5603	*/
5604	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5605	{
5606	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5607	pSvmTransient->fVectoringDoublePF = true;
5608	Assert(rc == VINF_SUCCESS);
5609	}
5610	else
5611	{
5612	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
5613	hmR0SvmSetPendingXcptDF(pVCpu);
5614	rc = VINF_HM_DOUBLE_FAULT;
5615	}
5616	break;
5617	}
5618
5619	case IEMXCPTRAISE_TRIPLE_FAULT:
5620	{
5621	rc = VINF_EM_RESET;
5622	break;
5623	}
5624
5625	case IEMXCPTRAISE_CPU_HANG:
5626	{
5627	rc = VERR_EM_GUEST_CPU_HANG;
5628	break;
5629	}
5630
5631	default:
5632	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
5633	}
5634	}
5635	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5636	return rc;
5637	}
5638
5639
5640	/**
5641	* Advances the guest RIP by the number of bytes specified in @a cb.
5642	*
5643	* @param pVCpu The cross context virtual CPU structure.
5644	* @param cb RIP increment value in bytes.
5645	*/
5646	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
5647	{
5648	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5649	pCtx->rip += cb;
5650
5651	/* Update interrupt shadow. */
5652	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5653	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
5654	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5655	}
5656
5657
5658	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5659	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5660	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5661
5662	/** @name \#VMEXIT handlers.
5663	* @{
5664	*/
5665
5666	/**
5667	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5668	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5669	*/
5670	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5671	{
5672	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5673
5674	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5675	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5676	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5677	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5678
5679	/*
5680	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
5681	* signal -before- the timer fires if the current interrupt is our own timer or a some
5682	* other host interrupt. We also cannot examine what interrupt it is until the host
5683	* actually take the interrupt.
5684	*
5685	* Going back to executing guest code here unconditionally causes random scheduling
5686	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5687	*/
5688	return VINF_EM_RAW_INTERRUPT;
5689	}
5690
5691
5692	/**
5693	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5694	*/
5695	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5696	{
5697	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5698
5699	VBOXSTRICTRC rcStrict;
5700	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5701	if (fSupportsNextRipSave)
5702	{
5703	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5704	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5705	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5706	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
5707	}
5708	else
5709	{
5710	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5711	rcStrict = IEMExecOne(pVCpu);
5712	}
5713
5714	if (rcStrict == VINF_IEM_RAISED_XCPT)
5715	{
5716	rcStrict = VINF_SUCCESS;
5717	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5718	}
5719	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5720	return VBOXSTRICTRC_TODO(rcStrict);
5721	}
5722
5723
5724	/**
5725	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5726	*/
5727	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5728	{
5729	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5730
5731	VBOXSTRICTRC rcStrict;
5732	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5733	if (fSupportsNextRipSave)
5734	{
5735	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5736	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5737	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5738	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
5739	}
5740	else
5741	{
5742	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5743	rcStrict = IEMExecOne(pVCpu);
5744	}
5745
5746	if (rcStrict == VINF_IEM_RAISED_XCPT)
5747	{
5748	rcStrict = VINF_SUCCESS;
5749	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5750	}
5751	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5752	return VBOXSTRICTRC_TODO(rcStrict);
5753	}
5754
5755
5756	/**
5757	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5758	*/
5759	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5760	{
5761	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5762
5763	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
5764	VBOXSTRICTRC rcStrict;
5765	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
5766	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
5767	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
5768	if (!pExitRec)
5769	{
5770	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5771	if (fSupportsNextRipSave)
5772	{
5773	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5774	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5775	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
5776	}
5777	else
5778	{
5779	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5780	rcStrict = IEMExecOne(pVCpu);
5781	}
5782
5783	if (rcStrict == VINF_IEM_RAISED_XCPT)
5784	{
5785	rcStrict = VINF_SUCCESS;
5786	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5787	}
5788	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5789	}
5790	else
5791	{
5792	/*
5793	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
5794	*/
5795	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5796
5797	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
5798	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
5799
5800	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
5801
5802	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
5803	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
5804	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
5805	}
5806	return VBOXSTRICTRC_TODO(rcStrict);
5807	}
5808
5809
5810	/**
5811	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5812	*/
5813	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5814	{
5815	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5816
5817	VBOXSTRICTRC rcStrict;
5818	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5819	if (fSupportsNextRipSave)
5820	{
5821	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5822	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5823	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5824	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
5825	}
5826	else
5827	{
5828	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5829	rcStrict = IEMExecOne(pVCpu);
5830	}
5831
5832	if (rcStrict == VINF_SUCCESS)
5833	pSvmTransient->fUpdateTscOffsetting = true;
5834	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5835	{
5836	rcStrict = VINF_SUCCESS;
5837	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5838	}
5839	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5840	return VBOXSTRICTRC_TODO(rcStrict);
5841	}
5842
5843
5844	/**
5845	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5846	*/
5847	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5848	{
5849	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5850
5851	VBOXSTRICTRC rcStrict;
5852	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5853	if (fSupportsNextRipSave)
5854	{
5855	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
5856	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5857	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5858	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
5859	}
5860	else
5861	{
5862	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5863	rcStrict = IEMExecOne(pVCpu);
5864	}
5865
5866	if (rcStrict == VINF_SUCCESS)
5867	pSvmTransient->fUpdateTscOffsetting = true;
5868	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5869	{
5870	rcStrict = VINF_SUCCESS;
5871	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5872	}
5873	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5874	return VBOXSTRICTRC_TODO(rcStrict);
5875	}
5876
5877
5878	/**
5879	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5880	*/
5881	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5882	{
5883	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5884
5885	VBOXSTRICTRC rcStrict;
5886	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5887	if (fSupportsNextRipSave)
5888	{
5889	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5890	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5891	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5892	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
5893	}
5894	else
5895	{
5896	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5897	rcStrict = IEMExecOne(pVCpu);
5898	}
5899
5900	if (rcStrict == VINF_IEM_RAISED_XCPT)
5901	{
5902	rcStrict = VINF_SUCCESS;
5903	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5904	}
5905	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5906	return VBOXSTRICTRC_TODO(rcStrict);
5907	}
5908
5909
5910	/**
5911	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5912	*/
5913	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5914	{
5915	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5916	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5917
5918	VBOXSTRICTRC rcStrict;
5919	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
5920	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5921	if ( fSupportsDecodeAssists
5922	&& fSupportsNextRipSave)
5923	{
5924	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
5925	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5926	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5927	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
5928	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
5929	}
5930	else
5931	{
5932	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5933	rcStrict = IEMExecOne(pVCpu);
5934	}
5935
5936	if (rcStrict == VINF_IEM_RAISED_XCPT)
5937	{
5938	rcStrict = VINF_SUCCESS;
5939	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5940	}
5941	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5942	return VBOXSTRICTRC_VAL(rcStrict);
5943	}
5944
5945
5946	/**
5947	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
5948	*/
5949	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5950	{
5951	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5952
5953	VBOXSTRICTRC rcStrict;
5954	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5955	if (fSupportsNextRipSave)
5956	{
5957	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5958	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5959	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5960	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
5961	}
5962	else
5963	{
5964	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5965	rcStrict = IEMExecOne(pVCpu);
5966	}
5967
5968	if ( rcStrict == VINF_EM_HALT
5969	\|\| rcStrict == VINF_SUCCESS)
5970	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
5971	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5972	{
5973	rcStrict = VINF_SUCCESS;
5974	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5975	}
5976	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5977	if (rcStrict != VINF_SUCCESS)
5978	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
5979	return VBOXSTRICTRC_VAL(rcStrict);;
5980	}
5981
5982
5983	/**
5984	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
5985	*/
5986	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5987	{
5988	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5989
5990	/*
5991	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
5992	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
5993	* segment override prefix or other prefixes might be used, in which case we fallback to
5994	* IEMExecOne() to figure out.
5995	*/
5996	VBOXSTRICTRC rcStrict;
5997	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5998	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
5999	if (cbInstr)
6000	{
6001	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6002	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6003	}
6004	else
6005	{
6006	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6007	rcStrict = IEMExecOne(pVCpu);
6008	}
6009
6010	if (rcStrict == VINF_IEM_RAISED_XCPT)
6011	{
6012	rcStrict = VINF_SUCCESS;
6013	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6014	}
6015	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6016	return VBOXSTRICTRC_TODO(rcStrict);
6017	}
6018
6019
6020	/**
6021	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6022	*/
6023	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6024	{
6025	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6026
6027	VBOXSTRICTRC rcStrict;
6028	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6029	if (fSupportsNextRipSave)
6030	{
6031	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6032	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6033	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6034	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6035	}
6036	else
6037	{
6038	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6039	rcStrict = IEMExecOne(pVCpu);
6040	}
6041
6042	if ( rcStrict == VINF_EM_HALT
6043	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6044	rcStrict = VINF_SUCCESS;
6045	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6046	{
6047	rcStrict = VINF_SUCCESS;
6048	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6049	}
6050	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6051	return VBOXSTRICTRC_TODO(rcStrict);
6052	}
6053
6054
6055	/**
6056	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6057	* \#VMEXIT.
6058	*/
6059	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6060	{
6061	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6062	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6063	return VINF_EM_RESET;
6064	}
6065
6066
6067	/**
6068	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6069	*/
6070	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6071	{
6072	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6073	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6074	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6075	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6076	RT_NOREF(pVmcb);
6077	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6078	return VERR_SVM_UNEXPECTED_EXIT;
6079	}
6080
6081
6082	/**
6083	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6084	*/
6085	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6086	{
6087	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6088
6089	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6090	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6091	#ifdef VBOX_WITH_STATISTICS
6092	switch (pSvmTransient->u64ExitCode)
6093	{
6094	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6095	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6096	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6097	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6098	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6099	}
6100	#endif
6101
6102	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6103	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6104	if ( fSupportsDecodeAssists
6105	&& fSupportsNextRipSave)
6106	{
6107	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6108	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6109	if (fMovCRx)
6110	{
6111	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6112	\| CPUMCTX_EXTRN_APIC_TPR);
6113	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6114	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6115	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6116	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6117	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6118	return VBOXSTRICTRC_VAL(rcStrict);
6119	}
6120	/* else: SMSW instruction, fall back below to IEM for this. */
6121	}
6122
6123	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6124	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6125	AssertMsg( rcStrict == VINF_SUCCESS
6126	\|\| rcStrict == VINF_PGM_SYNC_CR3
6127	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6128	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6129	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6130	if (rcStrict == VINF_IEM_RAISED_XCPT)
6131	{
6132	rcStrict = VINF_SUCCESS;
6133	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6134	}
6135	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6136	return VBOXSTRICTRC_TODO(rcStrict);
6137	}
6138
6139
6140	/**
6141	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6142	*/
6143	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6144	{
6145	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6146
6147	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6148	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6149	Assert(iCrReg <= 15);
6150
6151	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6152	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6153	bool fDecodedInstr = false;
6154	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6155	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6156	if ( fSupportsDecodeAssists
6157	&& fSupportsNextRipSave)
6158	{
6159	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6160	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6161	if (fMovCRx)
6162	{
6163	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6164	\| CPUMCTX_EXTRN_APIC_TPR);
6165	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6166	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6167	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6168	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6169	fDecodedInstr = true;
6170	}
6171	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6172	}
6173
6174	if (!fDecodedInstr)
6175	{
6176	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6177	Log4Func(("iCrReg=%#x\n", iCrReg));
6178	rcStrict = IEMExecOne(pVCpu);
6179	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6180	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6181	rcStrict = VERR_EM_INTERPRETER;
6182	}
6183
6184	if (rcStrict == VINF_SUCCESS)
6185	{
6186	switch (iCrReg)
6187	{
6188	case 0:
6189	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6190	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6191	break;
6192
6193	case 2:
6194	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6195	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6196	break;
6197
6198	case 3:
6199	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6200	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6201	break;
6202
6203	case 4:
6204	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6205	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6206	break;
6207
6208	case 8:
6209	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6210	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6211	break;
6212
6213	default:
6214	{
6215	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6216	pSvmTransient->u64ExitCode, iCrReg));
6217	break;
6218	}
6219	}
6220	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6221	}
6222	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6223	{
6224	rcStrict = VINF_SUCCESS;
6225	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6226	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6227	}
6228	else
6229	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6230	return VBOXSTRICTRC_TODO(rcStrict);
6231	}
6232
6233
6234	/**
6235	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6236	*
6237	* @returns Strict VBox status code.
6238	* @param pVCpu The cross context virtual CPU structure.
6239	* @param pVmcb Pointer to the VM control block.
6240	*/
6241	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
6242	{
6243	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6244	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6245
6246	VBOXSTRICTRC rcStrict;
6247	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6248	if (fSupportsNextRipSave)
6249	{
6250	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6251	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6252	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6253	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6254	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6255	}
6256	else
6257	{
6258	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6259	rcStrict = IEMExecOne(pVCpu);
6260	}
6261
6262	AssertMsg( rcStrict == VINF_SUCCESS
6263	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6264	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6265	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6266
6267	if (rcStrict == VINF_IEM_RAISED_XCPT)
6268	{
6269	rcStrict = VINF_SUCCESS;
6270	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6271	}
6272	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6273	return rcStrict;
6274	}
6275
6276
6277	/**
6278	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6279	*
6280	* @returns Strict VBox status code.
6281	* @param pVCpu The cross context virtual CPU structure.
6282	* @param pVmcb Pointer to the VM control block.
6283	* @param pSvmTransient Pointer to the SVM-transient structure.
6284	*/
6285	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6286	{
6287	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6288	uint32_t const idMsr = pCtx->ecx;
6289	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6290	Log4Func(("idMsr=%#RX32\n", idMsr));
6291
6292	/*
6293	* Handle TPR patching MSR writes.
6294	* We utilitize the LSTAR MSR for patching.
6295	*/
6296	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6297	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
6298	&& idMsr == MSR_K8_LSTAR)
6299	{
6300	unsigned cbInstr;
6301	if (fSupportsNextRipSave)
6302	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6303	else
6304	{
6305	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6306	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6307	if ( rc == VINF_SUCCESS
6308	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6309	Assert(cbInstr > 0);
6310	else
6311	cbInstr = 0;
6312	}
6313
6314	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6315	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6316	{
6317	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6318	AssertRCReturn(rc, rc);
6319	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6320	}
6321
6322	int rc = VINF_SUCCESS;
6323	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6324	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6325	return rc;
6326	}
6327
6328	/*
6329	* Handle regular MSR writes.
6330	*/
6331	VBOXSTRICTRC rcStrict;
6332	if (fSupportsNextRipSave)
6333	{
6334	/** @todo Optimize this: We don't need to get much of the MSR state here
6335	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6336	* clear the applicable extern flags. */
6337	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6338	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6339	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6340	}
6341	else
6342	{
6343	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6344	rcStrict = IEMExecOne(pVCpu);
6345	}
6346
6347	AssertMsg( rcStrict == VINF_SUCCESS
6348	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6349	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6350	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6351
6352	if (rcStrict == VINF_SUCCESS)
6353	{
6354	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6355	if ( idMsr >= MSR_IA32_X2APIC_START
6356	&& idMsr <= MSR_IA32_X2APIC_END)
6357	{
6358	/*
6359	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6360	* When full APIC register virtualization is implemented we'll have to make sure
6361	* APIC state is saved from the VMCB before IEM changes it.
6362	*/
6363	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6364	}
6365	else
6366	{
6367	switch (idMsr)
6368	{
6369	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6370	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6371	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6372	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6373	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6374	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6375	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6376	}
6377	}
6378	}
6379	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6380	{
6381	rcStrict = VINF_SUCCESS;
6382	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6383	}
6384	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6385	return rcStrict;
6386	}
6387
6388
6389	/**
6390	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6391	* \#VMEXIT.
6392	*/
6393	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6394	{
6395	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6396
6397	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6398	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6399	return VBOXSTRICTRC_TODO(hmR0SvmExitReadMsr(pVCpu, pVmcb));
6400
6401	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6402	return VBOXSTRICTRC_TODO(hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient));
6403	}
6404
6405
6406	/**
6407	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6408	*/
6409	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6410	{
6411	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6412	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6413
6414	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6415
6416	/** @todo Stepping with nested-guest. */
6417	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6418	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6419	{
6420	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6421	if (pSvmTransient->fWasGuestDebugStateActive)
6422	{
6423	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6424	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6425	return VERR_SVM_UNEXPECTED_EXIT;
6426	}
6427
6428	/*
6429	* Lazy DR0-3 loading.
6430	*/
6431	if (!pSvmTransient->fWasHyperDebugStateActive)
6432	{
6433	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6434	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6435
6436	/* Don't intercept DRx read and writes. */
6437	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6438	pVmcb->ctrl.u16InterceptRdDRx = 0;
6439	pVmcb->ctrl.u16InterceptWrDRx = 0;
6440	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6441
6442	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6443	VMMRZCallRing3Disable(pVCpu);
6444	HM_DISABLE_PREEMPT(pVCpu);
6445
6446	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6447	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6448	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6449
6450	HM_RESTORE_PREEMPT();
6451	VMMRZCallRing3Enable(pVCpu);
6452
6453	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6454	return VINF_SUCCESS;
6455	}
6456	}
6457
6458	/*
6459	* Interpret the read/writing of DRx.
6460	*/
6461	/** @todo Decode assist. */
6462	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6463	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6464	if (RT_LIKELY(rc == VINF_SUCCESS))
6465	{
6466	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6467	/** @todo CPUM should set this flag! */
6468	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6469	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6470	}
6471	else
6472	Assert(rc == VERR_EM_INTERPRETER);
6473	return VBOXSTRICTRC_TODO(rc);
6474	}
6475
6476
6477	/**
6478	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6479	*/
6480	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6481	{
6482	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6483	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6484	int rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6485	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6486	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6487	return rc;
6488	}
6489
6490
6491	/**
6492	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6493	*/
6494	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6495	{
6496	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6497	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6498
6499	/** @todo decode assists... */
6500	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6501	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6502	{
6503	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6504	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6505	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0,
6506	pCtx->cr4));
6507	}
6508	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6509	{
6510	rcStrict = VINF_SUCCESS;
6511	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6512	}
6513	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6514	return VBOXSTRICTRC_TODO(rcStrict);
6515	}
6516
6517
6518	/**
6519	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6520	*/
6521	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6522	{
6523	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6524	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6525
6526	/* I/O operation lookup arrays. */
6527	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6528	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6529	the result (in AL/AX/EAX). */
6530	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6531	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6532	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6533
6534	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6535
6536	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6537	SVMIOIOEXITINFO IoExitInfo;
6538	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6539	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6540	uint32_t cbValue = s_aIOSize[uIOWidth];
6541	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6542
6543	if (RT_UNLIKELY(!cbValue))
6544	{
6545	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6546	return VERR_EM_INTERPRETER;
6547	}
6548
6549	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6550	VBOXSTRICTRC rcStrict;
6551	PCEMEXITREC pExitRec = NULL;
6552	if ( !pVCpu->hm.s.fSingleInstruction
6553	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6554	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6555	!IoExitInfo.n.u1Str
6556	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6557	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6558	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6559	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6560	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6561	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6562	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6563	if (!pExitRec)
6564	{
6565	bool fUpdateRipAlready = false;
6566	if (IoExitInfo.n.u1Str)
6567	{
6568	/* INS/OUTS - I/O String instruction. */
6569	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6570	* in EXITINFO1? Investigate once this thing is up and running. */
6571	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6572	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6573	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6574	static IEMMODE const s_aenmAddrMode[8] =
6575	{
6576	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6577	};
6578	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6579	if (enmAddrMode != (IEMMODE)-1)
6580	{
6581	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6582	if (cbInstr <= 15 && cbInstr >= 1)
6583	{
6584	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6585	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6586	{
6587	/* Don't know exactly how to detect whether u3Seg is valid, currently
6588	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6589	2384 Opterons when only checking NRIP. */
6590	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6591	if ( fSupportsNextRipSave
6592	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6593	{
6594	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6595	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6596	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6597	IoExitInfo.n.u3Seg, true /fIoChecked/);
6598	}
6599	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6600	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6601	X86_SREG_DS, true /fIoChecked/);
6602	else
6603	rcStrict = IEMExecOne(pVCpu);
6604	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6605	}
6606	else
6607	{
6608	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6609	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6610	true /fIoChecked/);
6611	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6612	}
6613	}
6614	else
6615	{
6616	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6617	rcStrict = IEMExecOne(pVCpu);
6618	}
6619	}
6620	else
6621	{
6622	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6623	rcStrict = IEMExecOne(pVCpu);
6624	}
6625	fUpdateRipAlready = true;
6626	}
6627	else
6628	{
6629	/* IN/OUT - I/O instruction. */
6630	Assert(!IoExitInfo.n.u1Rep);
6631
6632	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6633	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6634	{
6635	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6636	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6637	&& !pCtx->eflags.Bits.u1TF)
6638	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
6639	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6640	}
6641	else
6642	{
6643	uint32_t u32Val = 0;
6644	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6645	if (IOM_SUCCESS(rcStrict))
6646	{
6647	/* Save result of I/O IN instr. in AL/AX/EAX. */
6648	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6649	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6650	}
6651	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6652	&& !pCtx->eflags.Bits.u1TF)
6653	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
6654
6655	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6656	}
6657	}
6658
6659	if (IOM_SUCCESS(rcStrict))
6660	{
6661	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6662	if (!fUpdateRipAlready)
6663	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6664
6665	/*
6666	* If any I/O breakpoints are armed, we need to check if one triggered
6667	* and take appropriate action.
6668	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6669	*/
6670	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6671	* execution engines about whether hyper BPs and such are pending. */
6672	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
6673	uint32_t const uDr7 = pCtx->dr[7];
6674	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6675	&& X86_DR7_ANY_RW_IO(uDr7)
6676	&& (pCtx->cr4 & X86_CR4_DE))
6677	\|\| DBGFBpIsHwIoArmed(pVM)))
6678	{
6679	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6680	VMMRZCallRing3Disable(pVCpu);
6681	HM_DISABLE_PREEMPT(pVCpu);
6682
6683	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6684	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6685
6686	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
6687	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6688	{
6689	/* Raise #DB. */
6690	pVmcb->guest.u64DR6 = pCtx->dr[6];
6691	pVmcb->guest.u64DR7 = pCtx->dr[7];
6692	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6693	hmR0SvmSetPendingXcptDB(pVCpu);
6694	}
6695	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6696	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6697	else if ( rcStrict2 != VINF_SUCCESS
6698	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6699	rcStrict = rcStrict2;
6700	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6701
6702	HM_RESTORE_PREEMPT();
6703	VMMRZCallRing3Enable(pVCpu);
6704	}
6705
6706	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6707	}
6708
6709	#ifdef VBOX_STRICT
6710	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6711	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
6712	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6713	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6714	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
6715	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
6716	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6717	else
6718	{
6719	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6720	* statuses, that the VMM device and some others may return. See
6721	* IOM_SUCCESS() for guidance. */
6722	AssertMsg( RT_FAILURE(rcStrict)
6723	\|\| rcStrict == VINF_SUCCESS
6724	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6725	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6726	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6727	\|\| rcStrict == VINF_EM_RAW_TO_R3
6728	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6729	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6730	}
6731	#endif
6732	}
6733	else
6734	{
6735	/*
6736	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6737	*/
6738	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6739	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
6740	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
6741	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
6742	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
6743	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
6744	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
6745
6746	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6747	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6748
6749	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6750	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6751	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6752	}
6753	return VBOXSTRICTRC_TODO(rcStrict);
6754	}
6755
6756
6757	/**
6758	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6759	*/
6760	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6761	{
6762	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6763	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6764	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6765
6766	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6767	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6768	Assert(pVM->hm.s.fNestedPaging);
6769
6770	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6771	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6772	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6773	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
6774	thus intentionally not copied into u32ErrCode. */
6775
6776	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
6777	u32ErrCode));
6778
6779	/*
6780	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
6781	*/
6782	if ( pVM->hm.s.fTprPatchingAllowed
6783	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6784	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6785	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6786	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
6787	&& !CPUMIsGuestInLongModeEx(pCtx)
6788	&& !CPUMGetGuestCPL(pVCpu)
6789	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6790	{
6791	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6792	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6793
6794	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6795	{
6796	/* Only attempt to patch the instruction once. */
6797	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6798	if (!pPatch)
6799	return VINF_EM_HM_PATCH_TPR_INSTR;
6800	}
6801	}
6802
6803	/*
6804	* Determine the nested paging mode.
6805	*/
6806	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
6807	PGMMODE const enmNestedPagingMode = PGMGetHostMode(pVM);
6808
6809	/*
6810	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6811	*/
6812	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6813	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6814	{
6815	/*
6816	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
6817	* injecting the original pending event would most likely cause the same MMIO #NPF.
6818	*/
6819	if (pVCpu->hm.s.Event.fPending)
6820	{
6821	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
6822	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6823	}
6824
6825	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
6826	VBOXSTRICTRC rcStrict;
6827	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6828	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
6829	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6830	if (!pExitRec)
6831	{
6832
6833	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6834	u32ErrCode);
6835
6836	/*
6837	* If we succeed, resume guest execution.
6838	*
6839	* If we fail in interpreting the instruction because we couldn't get the guest
6840	* physical address of the page containing the instruction via the guest's page
6841	* tables (we would invalidate the guest page in the host TLB), resume execution
6842	* which would cause a guest page fault to let the guest handle this weird case.
6843	*
6844	* See @bugref{6043}.
6845	*/
6846	if ( rcStrict == VINF_SUCCESS
6847	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
6848	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
6849	{
6850	/* Successfully handled MMIO operation. */
6851	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6852	rcStrict = VINF_SUCCESS;
6853	}
6854	}
6855	else
6856	{
6857	/*
6858	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6859	*/
6860	Assert(pCtx == &pVCpu->cpum.GstCtx);
6861	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6862	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
6863	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
6864
6865	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6866	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6867
6868	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6869	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6870	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6871	}
6872	return VBOXSTRICTRC_TODO(rcStrict);
6873	}
6874
6875	/*
6876	* Nested page-fault.
6877	*/
6878	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6879	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6880	TRPMResetTrap(pVCpu);
6881
6882	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6883
6884	/*
6885	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6886	*/
6887	if ( rc == VINF_SUCCESS
6888	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6889	\|\| rc == VERR_PAGE_NOT_PRESENT)
6890	{
6891	/* We've successfully synced our shadow page tables. */
6892	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6893	rc = VINF_SUCCESS;
6894	}
6895
6896	/*
6897	* If delivering an event causes an #NPF (and not MMIO), we shall resolve the fault and
6898	* re-inject the original event.
6899	*/
6900	if (pVCpu->hm.s.Event.fPending)
6901	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
6902
6903	return rc;
6904	}
6905
6906
6907	/**
6908	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6909	* \#VMEXIT.
6910	*/
6911	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6912	{
6913	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6914	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
6915
6916	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6917	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6918	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
6919
6920	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6921	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6922	return VINF_SUCCESS;
6923	}
6924
6925
6926	/**
6927	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6928	* \#VMEXIT.
6929	*/
6930	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6931	{
6932	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6933	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6934
6935	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6936	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6937	#endif
6938
6939	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6940	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6941	{
6942	/*
6943	* AMD-V provides us with the exception which caused the TS; we collect
6944	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
6945	*/
6946	Log4Func(("TS occurred during event delivery\n"));
6947	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6948	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6949	}
6950
6951	/** @todo Emulate task switch someday, currently just going back to ring-3 for
6952	* emulation. */
6953	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6954	return VERR_EM_INTERPRETER;
6955	}
6956
6957
6958	/**
6959	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6960	*/
6961	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6962	{
6963	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6964	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6965
6966	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6967	if (pVM->hm.s.fTprPatchingAllowed)
6968	{
6969	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
6970	if (rc != VERR_NOT_FOUND)
6971	{
6972	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
6973	return rc;
6974	}
6975	}
6976
6977	if (EMAreHypercallInstructionsEnabled(pVCpu))
6978	{
6979	unsigned cbInstr;
6980	if (hmR0SvmSupportsNextRipSave(pVCpu))
6981	{
6982	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6983	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6984	}
6985	else
6986	{
6987	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6988	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6989	if ( rc == VINF_SUCCESS
6990	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
6991	Assert(cbInstr > 0);
6992	else
6993	cbInstr = 0;
6994	}
6995
6996	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
6997	if (RT_SUCCESS(rcStrict))
6998	{
6999	/* Only update the RIP if we're continuing guest execution and not in the case
7000	of say VINF_GIM_R3_HYPERCALL. */
7001	if (rcStrict == VINF_SUCCESS)
7002	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7003
7004	return VBOXSTRICTRC_VAL(rcStrict);
7005	}
7006	else
7007	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7008	}
7009
7010	hmR0SvmSetPendingXcptUD(pVCpu);
7011	return VINF_SUCCESS;
7012	}
7013
7014
7015	/**
7016	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7017	*/
7018	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7019	{
7020	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7021
7022	unsigned cbInstr;
7023	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7024	if (fSupportsNextRipSave)
7025	{
7026	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7027	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7028	}
7029	else
7030	{
7031	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7032	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7033	if ( rc == VINF_SUCCESS
7034	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7035	Assert(cbInstr > 0);
7036	else
7037	cbInstr = 0;
7038	}
7039
7040	/** @todo The guest has likely hit a contended spinlock. We might want to
7041	* poke a schedule different guest VCPU. */
7042	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7043	return VINF_EM_RAW_INTERRUPT;
7044	}
7045
7046
7047	/**
7048	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7049	* \#VMEXIT.
7050	*/
7051	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7052	{
7053	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7054	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7055	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7056
7057	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7058	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7059	}
7060
7061
7062	/**
7063	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7064	*/
7065	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7066	{
7067	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7068
7069	/* Clear NMI blocking. */
7070	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7071	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7072
7073	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7074	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7075	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7076
7077	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7078	return VINF_SUCCESS;
7079	}
7080
7081
7082	/**
7083	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7084	* Conditional \#VMEXIT.
7085	*/
7086	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7087	{
7088	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7089	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7090	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7091
7092	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7093	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7094	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7095	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7096	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7097	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7098
7099	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7100	if (pVM->hm.s.fNestedPaging)
7101	{
7102	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7103	if ( !pSvmTransient->fVectoringDoublePF
7104	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7105	{
7106	/* A genuine guest #PF, reflect it to the guest. */
7107	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7108	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7109	uFaultAddress, uErrCode));
7110	}
7111	else
7112	{
7113	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7114	hmR0SvmSetPendingXcptDF(pVCpu);
7115	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7116	}
7117	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7118	return VINF_SUCCESS;
7119	}
7120	#endif
7121
7122	Assert(!pVM->hm.s.fNestedPaging);
7123
7124	/*
7125	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7126	*/
7127	if ( pVM->hm.s.fTprPatchingAllowed
7128	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7129	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7130	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7131	&& !CPUMIsGuestInLongModeEx(pCtx)
7132	&& !CPUMGetGuestCPL(pVCpu)
7133	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7134	{
7135	RTGCPHYS GCPhysApicBase;
7136	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7137	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7138
7139	/* Check if the page at the fault-address is the APIC base. */
7140	RTGCPHYS GCPhysPage;
7141	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7142	if ( rc2 == VINF_SUCCESS
7143	&& GCPhysPage == GCPhysApicBase)
7144	{
7145	/* Only attempt to patch the instruction once. */
7146	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7147	if (!pPatch)
7148	return VINF_EM_HM_PATCH_TPR_INSTR;
7149	}
7150	}
7151
7152	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7153	pCtx->rip, uErrCode, pCtx->cr3));
7154
7155	/*
7156	* If it's a vectoring #PF, emulate injecting the original event injection as
7157	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7158	* event injection that caused a #PF. See @bugref{6607}.
7159	*/
7160	if (pSvmTransient->fVectoringPF)
7161	{
7162	Assert(pVCpu->hm.s.Event.fPending);
7163	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7164	}
7165
7166	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7167	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7168
7169	Log4Func(("#PF: rc=%Rrc\n", rc));
7170
7171	if (rc == VINF_SUCCESS)
7172	{
7173	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7174	TRPMResetTrap(pVCpu);
7175	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7176	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7177	return rc;
7178	}
7179
7180	if (rc == VINF_EM_RAW_GUEST_TRAP)
7181	{
7182	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7183
7184	/*
7185	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7186	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7187	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7188	*/
7189	if ( !pSvmTransient->fVectoringDoublePF
7190	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7191	{
7192	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7193	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7194	TRPMResetTrap(pVCpu);
7195
7196	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7197	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7198	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7199	&& CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
7200	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress));
7201	#endif
7202
7203	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7204	}
7205	else
7206	{
7207	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7208	TRPMResetTrap(pVCpu);
7209	hmR0SvmSetPendingXcptDF(pVCpu);
7210	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7211	}
7212
7213	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7214	return VINF_SUCCESS;
7215	}
7216
7217	TRPMResetTrap(pVCpu);
7218	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7219	return rc;
7220	}
7221
7222
7223	/**
7224	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7225	* Conditional \#VMEXIT.
7226	*/
7227	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7228	{
7229	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7230	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7231	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7232
7233	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7234	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7235	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7236
7237	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7238	if (pVCpu->hm.s.fGIMTrapXcptUD)
7239	{
7240	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7241	uint8_t cbInstr = 0;
7242	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7243	if (rcStrict == VINF_SUCCESS)
7244	{
7245	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7246	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7247	rc = VINF_SUCCESS;
7248	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7249	}
7250	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7251	rc = VINF_SUCCESS;
7252	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7253	rc = VINF_GIM_R3_HYPERCALL;
7254	else
7255	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7256	}
7257
7258	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7259	if (RT_FAILURE(rc))
7260	{
7261	hmR0SvmSetPendingXcptUD(pVCpu);
7262	rc = VINF_SUCCESS;
7263	}
7264
7265	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7266	return rc;
7267	}
7268
7269
7270	/**
7271	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7272	* Conditional \#VMEXIT.
7273	*/
7274	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7275	{
7276	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7277	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7278	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7279
7280	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7281	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7282
7283	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7284	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7285
7286	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7287
7288	if (!(pCtx->cr0 & X86_CR0_NE))
7289	{
7290	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7291	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7292	unsigned cbInstr;
7293	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7294	if (RT_SUCCESS(rc))
7295	{
7296	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7297	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7298	if (RT_SUCCESS(rc))
7299	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7300	}
7301	else
7302	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7303	return rc;
7304	}
7305
7306	hmR0SvmSetPendingXcptMF(pVCpu);
7307	return VINF_SUCCESS;
7308	}
7309
7310
7311	/**
7312	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7313	* \#VMEXIT.
7314	*/
7315	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7316	{
7317	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7318	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7319	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7320	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7321
7322	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7323	{
7324	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7325	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7326	}
7327
7328	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7329
7330	/*
7331	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7332	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7333	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7334	*/
7335	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7336	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7337	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7338	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7339	if (rc == VINF_EM_RAW_GUEST_TRAP)
7340	{
7341	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7342	if (CPUMIsHyperDebugStateActive(pVCpu))
7343	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7344
7345	/* Reflect the exception back to the guest. */
7346	hmR0SvmSetPendingXcptDB(pVCpu);
7347	rc = VINF_SUCCESS;
7348	}
7349
7350	/*
7351	* Update DR6.
7352	*/
7353	if (CPUMIsHyperDebugStateActive(pVCpu))
7354	{
7355	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7356	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7357	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7358	}
7359	else
7360	{
7361	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7362	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7363	}
7364
7365	return rc;
7366	}
7367
7368
7369	/**
7370	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7371	* Conditional \#VMEXIT.
7372	*/
7373	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7374	{
7375	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7376	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7377	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
7378
7379	SVMEVENT Event;
7380	Event.u = 0;
7381	Event.n.u1Valid = 1;
7382	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7383	Event.n.u8Vector = X86_XCPT_AC;
7384	Event.n.u1ErrorCodeValid = 1;
7385	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7386	return VINF_SUCCESS;
7387	}
7388
7389
7390	/**
7391	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7392	* Conditional \#VMEXIT.
7393	*/
7394	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7395	{
7396	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7397	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7398	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7399	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
7400
7401	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7402	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7403	if (rc == VINF_EM_RAW_GUEST_TRAP)
7404	{
7405	SVMEVENT Event;
7406	Event.u = 0;
7407	Event.n.u1Valid = 1;
7408	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7409	Event.n.u8Vector = X86_XCPT_BP;
7410	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7411	rc = VINF_SUCCESS;
7412	}
7413
7414	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_DBG_BREAKPOINT);
7415	return rc;
7416	}
7417
7418
7419	/**
7420	* Hacks its way around the lovely mesa driver's backdoor accesses.
7421	*
7422	* @sa hmR0VmxHandleMesaDrvGp
7423	*/
7424	static int hmR0SvmHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7425	{
7426	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7427	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7428	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7429	RT_NOREF(pCtx, pVmcb);
7430
7431	/* For now we'll just skip the instruction. */
7432	hmR0SvmAdvanceRip(pVCpu, 1);
7433	return VINF_SUCCESS;
7434	}
7435
7436
7437	/**
7438	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7439	* backdoor logging w/o checking what it is running inside.
7440	*
7441	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7442	* backdoor port and magic numbers loaded in registers.
7443	*
7444	* @returns true if it is, false if it isn't.
7445	* @sa hmR0VmxIsMesaDrvGp
7446	*/
7447	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7448	{
7449	/* Check magic and port. */
7450	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7451	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7452	if (pCtx->dx != UINT32_C(0x5658))
7453	return false;
7454	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7455	return false;
7456
7457	/* Check that it is #GP(0). */
7458	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7459	return false;
7460
7461	/* Flat ring-3 CS. */
7462	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7463	if (pVmcb->guest.u8CPL != 3)
7464	return false;
7465	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7466	return false;
7467
7468	/* 0xed: IN eAX,dx */
7469	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7470	{
7471	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7472	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7473	uint8_t abInstr[1];
7474	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7475	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7476	if (RT_FAILURE(rc))
7477	return false;
7478	if (abInstr[0] != 0xed)
7479	return false;
7480	}
7481	else
7482	{
7483	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7484	if (pVmcb->ctrl.abInstr[0] != 0xed)
7485	return false;
7486	}
7487	return true;
7488	}
7489
7490
7491	/**
7492	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7493	* Conditional \#VMEXIT.
7494	*/
7495	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7496	{
7497	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7498	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7499	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
7500
7501	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7502	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7503
7504	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7505	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7506	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7507	{
7508	SVMEVENT Event;
7509	Event.u = 0;
7510	Event.n.u1Valid = 1;
7511	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7512	Event.n.u8Vector = X86_XCPT_GP;
7513	Event.n.u1ErrorCodeValid = 1;
7514	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7515	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7516	return VINF_SUCCESS;
7517	}
7518	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7519	}
7520
7521
7522	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7523	/**
7524	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7525	*/
7526	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7527	{
7528	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7529	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7530
7531	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7532	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7533	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7534	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7535	Assert(uVector <= X86_XCPT_LAST);
7536	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7537
7538	SVMEVENT Event;
7539	Event.u = 0;
7540	Event.n.u1Valid = 1;
7541	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7542	Event.n.u8Vector = uVector;
7543	switch (uVector)
7544	{
7545	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7546	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7547	case X86_XCPT_DF:
7548	case X86_XCPT_TS:
7549	case X86_XCPT_NP:
7550	case X86_XCPT_SS:
7551	case X86_XCPT_GP:
7552	case X86_XCPT_AC:
7553	{
7554	Event.n.u1ErrorCodeValid = 1;
7555	Event.n.u32ErrorCode = uErrCode;
7556	break;
7557	}
7558	}
7559
7560	#ifdef VBOX_WITH_STATISTICS
7561	switch (uVector)
7562	{
7563	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
7564	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
7565	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
7566	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7567	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
7568	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
7569	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7570	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
7571	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
7572	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
7573	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
7574	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
7575	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
7576	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
7577	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
7578	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
7579	default:
7580	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
7581	break;
7582	}
7583	#endif
7584
7585	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7586	return VINF_SUCCESS;
7587	}
7588	#endif
7589
7590	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7591	/**
7592	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7593	*/
7594	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7595	{
7596	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7597
7598	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7599	Assert(pVmcb);
7600	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7601
7602	VBOXSTRICTRC rcStrict;
7603	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7604	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7605	if (fSupportsNextRipSave)
7606	{
7607	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7608	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7609	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7610	}
7611	else
7612	{
7613	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7614	rcStrict = IEMExecOne(pVCpu);
7615	}
7616
7617	if (rcStrict == VINF_SUCCESS)
7618	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7619	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7620	{
7621	rcStrict = VINF_SUCCESS;
7622	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7623	}
7624	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7625	return VBOXSTRICTRC_TODO(rcStrict);
7626	}
7627
7628
7629	/**
7630	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7631	*/
7632	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7633	{
7634	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7635
7636	/*
7637	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7638	* we only intercept STGI when events are pending for GIF to become 1.
7639	*/
7640	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7641	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7642	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7643
7644	VBOXSTRICTRC rcStrict;
7645	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7646	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7647	if (fSupportsNextRipSave)
7648	{
7649	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7650	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7651	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7652	}
7653	else
7654	{
7655	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7656	rcStrict = IEMExecOne(pVCpu);
7657	}
7658
7659	if (rcStrict == VINF_SUCCESS)
7660	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7661	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7662	{
7663	rcStrict = VINF_SUCCESS;
7664	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7665	}
7666	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7667	return VBOXSTRICTRC_TODO(rcStrict);
7668	}
7669
7670
7671	/**
7672	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7673	*/
7674	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7675	{
7676	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7677
7678	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7679	Assert(pVmcb);
7680	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7681
7682	VBOXSTRICTRC rcStrict;
7683	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7684	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7685	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7686	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7687	if (fSupportsNextRipSave)
7688	{
7689	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7690	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7691	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7692	}
7693	else
7694	{
7695	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7696	rcStrict = IEMExecOne(pVCpu);
7697	}
7698
7699	if (rcStrict == VINF_SUCCESS)
7700	{
7701	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7702	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7703	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7704	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7705	}
7706	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7707	{
7708	rcStrict = VINF_SUCCESS;
7709	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7710	}
7711	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7712	return VBOXSTRICTRC_TODO(rcStrict);
7713	}
7714
7715
7716	/**
7717	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7718	*/
7719	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7720	{
7721	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7722
7723	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7724	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7725
7726	VBOXSTRICTRC rcStrict;
7727	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7728	if (fSupportsNextRipSave)
7729	{
7730	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7731	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7732	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7733	}
7734	else
7735	{
7736	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7737	rcStrict = IEMExecOne(pVCpu);
7738	}
7739
7740	if (rcStrict == VINF_IEM_RAISED_XCPT)
7741	{
7742	rcStrict = VINF_SUCCESS;
7743	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7744	}
7745	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7746	return VBOXSTRICTRC_TODO(rcStrict);
7747	}
7748
7749
7750	/**
7751	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7752	*/
7753	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7754	{
7755	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7756
7757	VBOXSTRICTRC rcStrict;
7758	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7759	if (fSupportsNextRipSave)
7760	{
7761	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7762	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7763	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7764	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7765	}
7766	else
7767	{
7768	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7769	rcStrict = IEMExecOne(pVCpu);
7770	}
7771
7772	if (rcStrict == VINF_IEM_RAISED_XCPT)
7773	{
7774	rcStrict = VINF_SUCCESS;
7775	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7776	}
7777	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7778	return VBOXSTRICTRC_TODO(rcStrict);
7779	}
7780
7781
7782	/**
7783	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7784	*/
7785	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7786	{
7787	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7788	/* We shall import the entire state here, just in case we enter and continue execution of
7789	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
7790	could lose lose part of CPU state. */
7791	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7792
7793	VBOXSTRICTRC rcStrict;
7794	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7795	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
7796	if (fSupportsNextRipSave)
7797	{
7798	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7799	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7800	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7801	}
7802	else
7803	{
7804	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
7805	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
7806	instruction itself, see @bugref{7243#c126} */
7807	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
7808	}
7809	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
7810
7811	if (rcStrict == VINF_SUCCESS)
7812	{
7813	rcStrict = VINF_SVM_VMRUN;
7814	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
7815	}
7816	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7817	{
7818	rcStrict = VINF_SUCCESS;
7819	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7820	}
7821	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7822	return VBOXSTRICTRC_TODO(rcStrict);
7823	}
7824
7825
7826	/**
7827	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7828	* Unconditional \#VMEXIT.
7829	*/
7830	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7831	{
7832	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7833	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7834
7835	if (pVCpu->hm.s.Event.fPending)
7836	{
7837	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7838	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7839	}
7840
7841	hmR0SvmSetPendingXcptDB(pVCpu);
7842	return VINF_SUCCESS;
7843	}
7844
7845
7846	/**
7847	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7848	* Conditional \#VMEXIT.
7849	*/
7850	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7851	{
7852	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7853	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7854
7855	SVMEVENT Event;
7856	Event.u = 0;
7857	Event.n.u1Valid = 1;
7858	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7859	Event.n.u8Vector = X86_XCPT_BP;
7860	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7861	return VINF_SUCCESS;
7862	}
7863	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
7864
7865	/** @} */
7866

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 82612

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