HMSVMR0.cpp@ 83029

Last change on this file since 83029 was 83029, checked in by vboxsync, 5 years ago
HM: Always use the 64-bit SVM context switcher for 64-bit capable VMs (see bugref:6208).
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1	/* $Id: HMSVMR0.cpp 83029 2020-02-10 09:18:24Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vmcc.h>
37	#include <VBox/err.h>
38	#include "HMSVMR0.h"
39	#include "dtrace/VBoxVMM.h"
40
41	#ifdef DEBUG_ramshankar
42	# define HMSVM_SYNC_FULL_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll); \
65	if ((u64ExitCode) == SVM_EXIT_NPF) \
66	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
67	else \
68	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
69	} while (0)
70	# endif
71	#else
72	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
73	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
74	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
75	# endif
76	#endif /* !VBOX_WITH_STATISTICS */
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static int
81
82	/**
83	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
84	* guest using hardware-assisted SVM.
85	*
86	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
87	* are swapped and restored across the world-switch and also registers like
88	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
89	* \#VMEXIT.
90	*/
91	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
92	\| CPUMCTX_EXTRN_RFLAGS \
93	\| CPUMCTX_EXTRN_RAX \
94	\| CPUMCTX_EXTRN_RSP \
95	\| CPUMCTX_EXTRN_SREG_MASK \
96	\| CPUMCTX_EXTRN_CR0 \
97	\| CPUMCTX_EXTRN_CR2 \
98	\| CPUMCTX_EXTRN_CR3 \
99	\| CPUMCTX_EXTRN_TABLE_MASK \
100	\| CPUMCTX_EXTRN_DR6 \
101	\| CPUMCTX_EXTRN_DR7 \
102	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
103	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
104	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
105	\| CPUMCTX_EXTRN_HWVIRT \
106	\| CPUMCTX_EXTRN_HM_SVM_MASK)
107
108	/**
109	* Subset of the guest-CPU state that is shared between the guest and host.
110	*/
111	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
112
113	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
114	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
115	do { \
116	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
117	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
118	} while (0)
119
120	/** Assert that the required state bits are fetched. */
121	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
122	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
123	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
124
125	/** Assert that preemption is disabled or covered by thread-context hooks. */
126	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
127	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
128
129	/** Assert that we haven't migrated CPUs when thread-context hooks are not
130	* used. */
131	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
132	\|\| (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
133	("Illegal migration! Entered on CPU %u Current %u\n", \
134	(a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()));
135
136	/** Assert that we're not executing a nested-guest. */
137	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
139	#else
140	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
141	#endif
142
143	/** Assert that we're executing a nested-guest. */
144	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
145	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
146	#else
147	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
148	#endif
149
150	/** Macro for checking and returning from the using function for
151	* \#VMEXIT intercepts that maybe caused during delivering of another
152	* event in the guest. */
153	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
154	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
155	do \
156	{ \
157	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
158	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
159	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
160	else if ( rc == VINF_EM_RESET \
161	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
162	{ \
163	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
164	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0)); \
165	} \
166	else \
167	return rc; \
168	} while (0)
169	#else
170	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
171	do \
172	{ \
173	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
174	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
175	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
176	else \
177	return rc; \
178	} while (0)
179	#endif
180
181	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
182	* instruction that exited. */
183	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
184	do { \
185	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
186	(a_rc) = VINF_EM_DBG_STEPPED; \
187	} while (0)
188
189	/** Validate segment descriptor granularity bit. */
190	#ifdef VBOX_STRICT
191	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
192	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
193	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
194	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
195	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
196	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
197	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
198	#else
199	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
200	#endif
201
202	/**
203	* Exception bitmap mask for all contributory exceptions.
204	*
205	* Page fault is deliberately excluded here as it's conditional as to whether
206	* it's contributory or benign. Page faults are handled separately.
207	*/
208	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
209	\| RT_BIT(X86_XCPT_DE))
210
211	/**
212	* Mandatory/unconditional guest control intercepts.
213	*
214	* SMIs can and do happen in normal operation. We need not intercept them
215	* while executing the guest (or nested-guest).
216	*/
217	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
218	\| SVM_CTRL_INTERCEPT_NMI \
219	\| SVM_CTRL_INTERCEPT_INIT \
220	\| SVM_CTRL_INTERCEPT_RDPMC \
221	\| SVM_CTRL_INTERCEPT_CPUID \
222	\| SVM_CTRL_INTERCEPT_RSM \
223	\| SVM_CTRL_INTERCEPT_HLT \
224	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
225	\| SVM_CTRL_INTERCEPT_MSR_PROT \
226	\| SVM_CTRL_INTERCEPT_INVLPGA \
227	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
228	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
229	\| SVM_CTRL_INTERCEPT_VMRUN \
230	\| SVM_CTRL_INTERCEPT_SKINIT \
231	\| SVM_CTRL_INTERCEPT_WBINVD \
232	\| SVM_CTRL_INTERCEPT_MONITOR \
233	\| SVM_CTRL_INTERCEPT_MWAIT \
234	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
235	\| SVM_CTRL_INTERCEPT_XSETBV)
236
237	/** @name VMCB Clean Bits.
238	*
239	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
240	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
241	* memory.
242	*
243	* @{ */
244	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
245	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
246	/** I/O permission bitmap, MSR permission bitmap. */
247	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
248	/** ASID. */
249	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
250	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
251	V_INTR_VECTOR. */
252	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
253	/** Nested Paging: Nested CR3 (nCR3), PAT. */
254	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
255	/** Control registers (CR0, CR3, CR4, EFER). */
256	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
257	/** Debug registers (DR6, DR7). */
258	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
259	/** GDT, IDT limit and base. */
260	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
261	/** Segment register: CS, SS, DS, ES limit and base. */
262	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
263	/** CR2.*/
264	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
265	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
266	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
267	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
268	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
269	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
270	/** Mask of all valid VMCB Clean bits. */
271	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
272	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
273	\| HMSVM_VMCB_CLEAN_ASID \
274	\| HMSVM_VMCB_CLEAN_INT_CTRL \
275	\| HMSVM_VMCB_CLEAN_NP \
276	\| HMSVM_VMCB_CLEAN_CRX_EFER \
277	\| HMSVM_VMCB_CLEAN_DRX \
278	\| HMSVM_VMCB_CLEAN_DT \
279	\| HMSVM_VMCB_CLEAN_SEG \
280	\| HMSVM_VMCB_CLEAN_CR2 \
281	\| HMSVM_VMCB_CLEAN_LBR \
282	\| HMSVM_VMCB_CLEAN_AVIC)
283	/** @} */
284
285	/** @name SVM transient.
286	*
287	* A state structure for holding miscellaneous information across AMD-V
288	* VMRUN/\#VMEXIT operation, restored after the transition.
289	*
290	* @{ */
291	typedef struct SVMTRANSIENT
292	{
293	/** The host's rflags/eflags. */
294	RTCCUINTREG fEFlags;
295	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
296	uint64_t u64ExitCode;
297
298	/** The guest's TPR value used for TPR shadowing. */
299	uint8_t u8GuestTpr;
300	/** Alignment. */
301	uint8_t abAlignment0[7];
302
303	/** Pointer to the currently executing VMCB. */
304	PSVMVMCB pVmcb;
305
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308	/** Whether the guest debug state was active at the time of \#VMEXIT. */
309	bool fWasGuestDebugStateActive;
310	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
311	bool fWasHyperDebugStateActive;
312	/** Whether the TSC offset mode needs to be updated. */
313	bool fUpdateTscOffsetting;
314	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
315	bool fRestoreTscAuxMsr;
316	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
317	* contributary exception or a page-fault. */
318	bool fVectoringDoublePF;
319	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
320	* external interrupt or NMI. */
321	bool fVectoringPF;
322	/** Padding. */
323	bool afPadding0;
324	} SVMTRANSIENT;
325	/** Pointer to SVM transient state. */
326	typedef SVMTRANSIENT *PSVMTRANSIENT;
327	/** Pointer to a const SVM transient state. */
328	typedef const SVMTRANSIENT *PCSVMTRANSIENT;
329
330	AssertCompileSizeAlignment(SVMTRANSIENT, sizeof(uint64_t));
331	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
332	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
333	/** @} */
334
335	/**
336	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
337	*/
338	typedef enum SVMMSREXITREAD
339	{
340	/** Reading this MSR causes a \#VMEXIT. */
341	SVMMSREXIT_INTERCEPT_READ = 0xb,
342	/** Reading this MSR does not cause a \#VMEXIT. */
343	SVMMSREXIT_PASSTHRU_READ
344	} SVMMSREXITREAD;
345
346	/**
347	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
348	*/
349	typedef enum SVMMSREXITWRITE
350	{
351	/** Writing to this MSR causes a \#VMEXIT. */
352	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
353	/** Writing to this MSR does not cause a \#VMEXIT. */
354	SVMMSREXIT_PASSTHRU_WRITE
355	} SVMMSREXITWRITE;
356
357	/**
358	* SVM \#VMEXIT handler.
359	*
360	* @returns VBox status code.
361	* @param pVCpu The cross context virtual CPU structure.
362	* @param pSvmTransient Pointer to the SVM-transient structure.
363	*/
364	typedef int FNSVMEXITHANDLER(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
365
366
367	/*********************************************************************************************************************************
368	* Internal Functions *
369	*********************************************************************************************************************************/
370	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu);
371	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState);
372
373
374	/** @name \#VMEXIT handlers.
375	* @{
376	*/
377	static FNSVMEXITHANDLER hmR0SvmExitIntr;
378	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
379	static FNSVMEXITHANDLER hmR0SvmExitInvd;
380	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
381	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
382	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
383	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
384	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
385	static FNSVMEXITHANDLER hmR0SvmExitHlt;
386	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
387	static FNSVMEXITHANDLER hmR0SvmExitMwait;
388	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
389	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
390	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
391	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
392	static FNSVMEXITHANDLER hmR0SvmExitMsr;
393	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
394	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
395	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
396	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
397	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
398	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
399	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
400	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
401	static FNSVMEXITHANDLER hmR0SvmExitPause;
402	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
403	static FNSVMEXITHANDLER hmR0SvmExitIret;
404	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
405	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
406	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
407	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
408	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
409	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
410	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
411	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
412	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
413	#endif
414	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
415	static FNSVMEXITHANDLER hmR0SvmExitClgi;
416	static FNSVMEXITHANDLER hmR0SvmExitStgi;
417	static FNSVMEXITHANDLER hmR0SvmExitVmload;
418	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
419	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
420	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
421	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
422	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
423	#endif
424	/** @} */
425
426	static int hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
427	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
428	static int hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
429	#endif
430
431
432	/*********************************************************************************************************************************
433	* Global Variables *
434	*********************************************************************************************************************************/
435	/** Ring-0 memory object for the IO bitmap. */
436	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
437	/** Physical address of the IO bitmap. */
438	static RTHCPHYS g_HCPhysIOBitmap;
439	/** Pointer to the IO bitmap. */
440	static R0PTRTYPE(void *) g_pvIOBitmap;
441
442	#ifdef VBOX_STRICT
443	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
444	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
445	# define HMSVM_LOG_CS RT_BIT_32(2)
446	# define HMSVM_LOG_SS RT_BIT_32(3)
447	# define HMSVM_LOG_FS RT_BIT_32(4)
448	# define HMSVM_LOG_GS RT_BIT_32(5)
449	# define HMSVM_LOG_LBR RT_BIT_32(6)
450	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
451	\| HMSVM_LOG_CR_REGS \
452	\| HMSVM_LOG_CS \
453	\| HMSVM_LOG_SS \
454	\| HMSVM_LOG_FS \
455	\| HMSVM_LOG_GS \
456	\| HMSVM_LOG_LBR)
457
458	/**
459	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
460	*
461	* @param pVCpu The cross context virtual CPU structure.
462	* @param pVmcb Pointer to the VM control block.
463	* @param pszPrefix Log prefix.
464	* @param fFlags Log flags, see HMSVM_LOG_XXX.
465	* @param uVerbose The verbosity level, currently unused.
466	*/
467	static void hmR0SvmLogState(PVMCPUCC pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
468	{
469	RT_NOREF2(pVCpu, uVerbose);
470	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
471
472	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
473	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
474
475	if (fFlags & HMSVM_LOG_RBP_RSP)
476	{
477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
478	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
479	}
480
481	if (fFlags & HMSVM_LOG_CR_REGS)
482	{
483	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
484	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
485	}
486
487	if (fFlags & HMSVM_LOG_CS)
488	{
489	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
490	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
491	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
492	}
493	if (fFlags & HMSVM_LOG_SS)
494	{
495	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
496	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
497	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
498	}
499	if (fFlags & HMSVM_LOG_FS)
500	{
501	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
502	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
503	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
504	}
505	if (fFlags & HMSVM_LOG_GS)
506	{
507	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
508	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
509	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
510	}
511
512	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
513	if (fFlags & HMSVM_LOG_LBR)
514	{
515	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
516	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
517	}
518	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
519	}
520	#endif /* VBOX_STRICT */
521
522
523	/**
524	* Sets up and activates AMD-V on the current CPU.
525	*
526	* @returns VBox status code.
527	* @param pHostCpu The HM physical-CPU structure.
528	* @param pVM The cross context VM structure. Can be
529	* NULL after a resume!
530	* @param pvCpuPage Pointer to the global CPU page.
531	* @param HCPhysCpuPage Physical address of the global CPU page.
532	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
533	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
534	* unused).
535	*/
536	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
537	PCSUPHWVIRTMSRS pHwvirtMsrs)
538	{
539	Assert(!fEnabledByHost);
540	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
541	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
542	Assert(pvCpuPage); NOREF(pvCpuPage);
543	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
544
545	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
546
547	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
549
550	/*
551	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
552	*/
553	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
554	if (u64HostEfer & MSR_K6_EFER_SVME)
555	{
556	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
557	if ( pVM
558	&& pVM->hm.s.svm.fIgnoreInUseError)
559	pHostCpu->fIgnoreAMDVInUseError = true;
560
561	if (!pHostCpu->fIgnoreAMDVInUseError)
562	{
563	ASMSetFlags(fEFlags);
564	return VERR_SVM_IN_USE;
565	}
566	}
567
568	/* Turn on AMD-V in the EFER MSR. */
569	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
570
571	/* Write the physical page address where the CPU will store the host state while executing the VM. */
572	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
573
574	/* Restore interrupts. */
575	ASMSetFlags(fEFlags);
576
577	/*
578	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
579	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
580	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
581	* entirely with before executing any guest code.
582	*/
583	pHostCpu->fFlushAsidBeforeUse = true;
584
585	/*
586	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
587	*/
588	++pHostCpu->cTlbFlushes;
589
590	return VINF_SUCCESS;
591	}
592
593
594	/**
595	* Deactivates AMD-V on the current CPU.
596	*
597	* @returns VBox status code.
598	* @param pHostCpu The HM physical-CPU structure.
599	* @param pvCpuPage Pointer to the global CPU page.
600	* @param HCPhysCpuPage Physical address of the global CPU page.
601	*/
602	VMMR0DECL(int) SVMR0DisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
603	{
604	RT_NOREF1(pHostCpu);
605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
606	AssertReturn( HCPhysCpuPage
607	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
608	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
609
610	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
611	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
612
613	/* Turn off AMD-V in the EFER MSR. */
614	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
615	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
616
617	/* Invalidate host state physical address. */
618	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
619
620	/* Restore interrupts. */
621	ASMSetFlags(fEFlags);
622
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* Does global AMD-V initialization (called during module initialization).
629	*
630	* @returns VBox status code.
631	*/
632	VMMR0DECL(int) SVMR0GlobalInit(void)
633	{
634	/*
635	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
636	* intercept all IO accesses, it's done once globally here instead of per-VM.
637	*/
638	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
639	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
640	if (RT_FAILURE(rc))
641	return rc;
642
643	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
644	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
645
646	/* Set all bits to intercept all IO accesses. */
647	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Does global AMD-V termination (called during module termination).
655	*/
656	VMMR0DECL(void) SVMR0GlobalTerm(void)
657	{
658	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
661	g_pvIOBitmap = NULL;
662	g_HCPhysIOBitmap = 0;
663	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666
667
668	/**
669	* Frees any allocated per-VCPU structures for a VM.
670	*
671	* @param pVM The cross context VM structure.
672	*/
673	DECLINLINE(void) hmR0SvmFreeStructs(PVMCC pVM)
674	{
675	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
676	{
677	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
678	AssertPtr(pVCpu);
679
680	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
681	{
682	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
683	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
684	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
685	}
686
687	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
688	{
689	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
690	pVCpu->hm.s.svm.pVmcb = NULL;
691	pVCpu->hm.s.svm.HCPhysVmcb = 0;
692	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
693	}
694
695	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
696	{
697	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
698	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
699	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
700	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
701	}
702	}
703	}
704
705
706	/**
707	* Does per-VM AMD-V initialization.
708	*
709	* @returns VBox status code.
710	* @param pVM The cross context VM structure.
711	*/
712	VMMR0DECL(int) SVMR0InitVM(PVMCC pVM)
713	{
714	int rc = VERR_INTERNAL_ERROR_5;
715
716	/*
717	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
718	*/
719	uint32_t u32Family;
720	uint32_t u32Model;
721	uint32_t u32Stepping;
722	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
723	{
724	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
725	pVM->hm.s.svm.fAlwaysFlushTLB = true;
726	}
727
728	/*
729	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
730	*/
731	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
732	{
733	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
734	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
735	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
736	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
737	}
738
739	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
740	{
741	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
742
743	/*
744	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
745	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
746	*/
747	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
748	if (RT_FAILURE(rc))
749	goto failure_cleanup;
750
751	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
752	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
753	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
754	ASMMemZeroPage(pvVmcbHost);
755
756	/*
757	* Allocate one page for the guest-state VMCB.
758	*/
759	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
760	if (RT_FAILURE(rc))
761	goto failure_cleanup;
762
763	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
764	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
765	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
766	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
767
768	/*
769	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
770	* SVM to not require one.
771	*/
772	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
773	false /* fExecutable */);
774	if (RT_FAILURE(rc))
775	goto failure_cleanup;
776
777	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
778	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
779	/* Set all bits to intercept all MSR accesses (changed later on). */
780	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
781	}
782
783	return VINF_SUCCESS;
784
785	failure_cleanup:
786	hmR0SvmFreeStructs(pVM);
787	return rc;
788	}
789
790
791	/**
792	* Does per-VM AMD-V termination.
793	*
794	* @returns VBox status code.
795	* @param pVM The cross context VM structure.
796	*/
797	VMMR0DECL(int) SVMR0TermVM(PVMCC pVM)
798	{
799	hmR0SvmFreeStructs(pVM);
800	return VINF_SUCCESS;
801	}
802
803
804	/**
805	* Returns whether the VMCB Clean Bits feature is supported.
806	*
807	* @returns @c true if supported, @c false otherwise.
808	* @param pVCpu The cross context virtual CPU structure.
809	* @param fIsNestedGuest Whether we are currently executing the nested-guest.
810	*/
811	DECL_FORCE_INLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPUCC pVCpu, bool fIsNestedGuest)
812	{
813	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
814	bool const fHostVmcbCleanBits = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
815	if (!fIsNestedGuest)
816	return fHostVmcbCleanBits;
817	return fHostVmcbCleanBits && pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
818	}
819
820
821	/**
822	* Returns whether the decode assists feature is supported.
823	*
824	* @returns @c true if supported, @c false otherwise.
825	* @param pVCpu The cross context virtual CPU structure.
826	*/
827	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPUCC pVCpu)
828	{
829	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
830	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
831	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
832	{
833	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
834	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
835	}
836	#endif
837	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
838	}
839
840
841	/**
842	* Returns whether the NRIP_SAVE feature is supported.
843	*
844	* @returns @c true if supported, @c false otherwise.
845	* @param pVCpu The cross context virtual CPU structure.
846	*/
847	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPUCC pVCpu)
848	{
849	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
850	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
851	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
852	{
853	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
854	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
855	}
856	#endif
857	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
858	}
859
860
861	/**
862	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
863	*
864	* @param pVCpu The cross context virtual CPU structure.
865	* @param pbMsrBitmap Pointer to the MSR bitmap.
866	* @param idMsr The MSR for which the permissions are being set.
867	* @param enmRead MSR read permissions.
868	* @param enmWrite MSR write permissions.
869	*
870	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
871	* caller needs to take care of this.
872	*/
873	static void hmR0SvmSetMsrPermission(PVMCPUCC pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
874	SVMMSREXITWRITE enmWrite)
875	{
876	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
877	uint16_t offMsrpm;
878	uint8_t uMsrpmBit;
879	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
880	AssertRC(rc);
881
882	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
883	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
884
885	pbMsrBitmap += offMsrpm;
886	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
887	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
888	else
889	{
890	if (!fInNestedGuestMode)
891	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
892	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
893	else
894	{
895	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
896	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
897	pbNstGstMsrBitmap += offMsrpm;
898	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
899	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
900	else
901	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
902	}
903	#endif
904	}
905
906	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
907	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
908	else
909	{
910	if (!fInNestedGuestMode)
911	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
912	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
913	else
914	{
915	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
916	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
917	pbNstGstMsrBitmap += offMsrpm;
918	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
919	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
920	else
921	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
922	}
923	#endif
924	}
925	}
926
927
928	/**
929	* Sets up AMD-V for the specified VM.
930	* This function is only called once per-VM during initalization.
931	*
932	* @returns VBox status code.
933	* @param pVM The cross context VM structure.
934	*/
935	VMMR0DECL(int) SVMR0SetupVM(PVMCC pVM)
936	{
937	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
938	AssertReturn(pVM, VERR_INVALID_PARAMETER);
939	Assert(pVM->hm.s.svm.fSupported);
940
941	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
942	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
943	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
944
945	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
946	bool const fUseLbrVirt = fLbrVirt && pVM->hm.s.svm.fLbrVirt; /** @todo IEM implementation etc. */
947
948	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
949	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
950	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
951
952	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
953	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
954	#endif
955
956	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
957	PSVMVMCB pVmcb0 = pVCpu0->hm.s.svm.pVmcb;
958	AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
959	PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
960
961	/* Always trap #AC for reasons of security. */
962	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
963
964	/* Always trap #DB for reasons of security. */
965	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
966
967	/* Trap exceptions unconditionally (debug purposes). */
968	#ifdef HMSVM_ALWAYS_TRAP_PF
969	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_PF);
970	#endif
971	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
972	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
973	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_BP)
974	\| RT_BIT_32(X86_XCPT_DE)
975	\| RT_BIT_32(X86_XCPT_NM)
976	\| RT_BIT_32(X86_XCPT_UD)
977	\| RT_BIT_32(X86_XCPT_NP)
978	\| RT_BIT_32(X86_XCPT_SS)
979	\| RT_BIT_32(X86_XCPT_GP)
980	\| RT_BIT_32(X86_XCPT_PF)
981	\| RT_BIT_32(X86_XCPT_MF)
982	;
983	#endif
984
985	/* Apply the exceptions intercepts needed by the GIM provider. */
986	if (pVCpu0->hm.s.fGIMTrapXcptUD)
987	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
988
989	/* The mesa 3d driver hack needs #GP. */
990	if (pVCpu0->hm.s.fTrapXcptGpForLovelyMesaDrv)
991	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
992
993	/* Set up unconditional intercepts and conditions. */
994	pVmcbCtrl0->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
995	\| SVM_CTRL_INTERCEPT_VMMCALL;
996
997	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
998	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
999	#endif
1000
1001	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1002	/* Virtualized VMSAVE/VMLOAD. */
1003	pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
1004	if (!fUseVirtVmsaveVmload)
1005	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
1006	\| SVM_CTRL_INTERCEPT_VMLOAD;
1007
1008	/* Virtual GIF. */
1009	pVmcbCtrl0->IntCtrl.n.u1VGifEnable = fUseVGif;
1010	if (!fUseVGif)
1011	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
1012	\| SVM_CTRL_INTERCEPT_STGI;
1013	#endif
1014
1015	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1016	pVmcbCtrl0->u16InterceptWrCRx = RT_BIT(4);
1017
1018	/* Intercept all DRx reads and writes by default. Changed later on. */
1019	pVmcbCtrl0->u16InterceptRdDRx = 0xffff;
1020	pVmcbCtrl0->u16InterceptWrDRx = 0xffff;
1021
1022	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1023	pVmcbCtrl0->IntCtrl.n.u1VIntrMasking = 1;
1024
1025	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1026	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1027	pVmcbCtrl0->IntCtrl.n.u1IgnoreTPR = 1;
1028
1029	/* Set the IO permission bitmap physical addresses. */
1030	pVmcbCtrl0->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1031
1032	/* LBR virtualization. */
1033	pVmcbCtrl0->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1034
1035	/* The host ASID MBZ, for the guest start with 1. */
1036	pVmcbCtrl0->TLBCtrl.n.u32ASID = 1;
1037
1038	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1039	pVmcbCtrl0->NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1040
1041	/* Without Nested Paging, we need additionally intercepts. */
1042	if (!pVM->hm.s.fNestedPaging)
1043	{
1044	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1045	pVmcbCtrl0->u16InterceptRdCRx \|= RT_BIT(3);
1046	pVmcbCtrl0->u16InterceptWrCRx \|= RT_BIT(3);
1047
1048	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1049	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1050	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1051
1052	/* Page faults must be intercepted to implement shadow paging. */
1053	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1054	}
1055
1056	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1057	if (fUsePauseFilter)
1058	{
1059	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1060	pVmcbCtrl0->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1061	if (fPauseFilterThreshold)
1062	pVmcbCtrl0->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1063	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1064	}
1065
1066	/*
1067	* Setup the MSR permission bitmap.
1068	* The following MSRs are saved/restored automatically during the world-switch.
1069	* Don't intercept guest read/write accesses to these MSRs.
1070	*/
1071	uint8_t pbMsrBitmap0 = (uint8_t )pVCpu0->hm.s.svm.pvMsrBitmap;
1072	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1073	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1074	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1075	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1076	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1077	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1078	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1079	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1080	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1081	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1082	pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hm.s.svm.HCPhysMsrBitmap;
1083
1084	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1085	Assert(pVmcbCtrl0->u32VmcbCleanBits == 0);
1086
1087	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1088	{
1089	PVMCPUCC pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
1090	PSVMVMCB pVmcbCur = pVCpuCur->hm.s.svm.pVmcb;
1091	AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
1092	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1093
1094	/* Copy the VMCB control area. */
1095	memcpy(pVmcbCtrlCur, pVmcbCtrl0, sizeof(*pVmcbCtrlCur));
1096
1097	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1098	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hm.s.svm.pvMsrBitmap;
1099	memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1100	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
1101
1102	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1103	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1104
1105	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1106	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu0->hm.s.fGIMTrapXcptUD);
1107	}
1108
1109	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1110	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1111	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1112	#else
1113	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1114	#endif
1115	return VINF_SUCCESS;
1116	}
1117
1118
1119	/**
1120	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1121	*
1122	* @returns Pointer to the current context VMCB.
1123	* @param pVCpu The cross context virtual CPU structure.
1124	*/
1125	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPUCC pVCpu)
1126	{
1127	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1128	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1129	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1130	#endif
1131	return pVCpu->hm.s.svm.pVmcb;
1132	}
1133
1134
1135	/**
1136	* Gets a pointer to the nested-guest VMCB cache.
1137	*
1138	* @returns Pointer to the nested-guest VMCB cache.
1139	* @param pVCpu The cross context virtual CPU structure.
1140	*/
1141	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPUCC pVCpu)
1142	{
1143	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1144	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1145	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1146	#else
1147	RT_NOREF(pVCpu);
1148	return NULL;
1149	#endif
1150	}
1151
1152
1153	/**
1154	* Invalidates a guest page by guest virtual address.
1155	*
1156	* @returns VBox status code.
1157	* @param pVCpu The cross context virtual CPU structure.
1158	* @param GCVirt Guest virtual address of the page to invalidate.
1159	*/
1160	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1161	{
1162	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1163
1164	bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1165
1166	/* Skip it if a TLB flush is already pending. */
1167	if (!fFlushPending)
1168	{
1169	Log4Func(("%#RGv\n", GCVirt));
1170
1171	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1172	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1173
1174	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1175	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1176	}
1177	return VINF_SUCCESS;
1178	}
1179
1180
1181	/**
1182	* Flushes the appropriate tagged-TLB entries.
1183	*
1184	* @param pHostCpu The HM physical-CPU structure.
1185	* @param pVCpu The cross context virtual CPU structure.
1186	* @param pVmcb Pointer to the VM control block.
1187	*/
1188	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1189	{
1190	/*
1191	* Force a TLB flush for the first world switch if the current CPU differs from the one
1192	* we ran on last. This can happen both for start & resume due to long jumps back to
1193	* ring-3.
1194	*
1195	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1196	* correlation between it and the physical CPU.
1197	*
1198	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1199	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1200	*/
1201	bool fNewAsid = false;
1202	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1203	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1204	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1205	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1206	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1207	#endif
1208	)
1209	{
1210	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1211	pVCpu->hm.s.fForceTLBFlush = true;
1212	fNewAsid = true;
1213	}
1214
1215	/* Set TLB flush state as checked until we return from the world switch. */
1216	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1217
1218	/* Check for explicit TLB flushes. */
1219	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1220	{
1221	pVCpu->hm.s.fForceTLBFlush = true;
1222	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1223	}
1224
1225	/*
1226	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1227	* This Host CPU requirement takes precedence.
1228	*/
1229	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1230	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1231	{
1232	pHostCpu->uCurrentAsid = 1;
1233	pVCpu->hm.s.uCurrentAsid = 1;
1234	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1235	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1236	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1237
1238	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1239	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1240	}
1241	else
1242	{
1243	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1244	if (pVCpu->hm.s.fForceTLBFlush)
1245	{
1246	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1247	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1248
1249	if (fNewAsid)
1250	{
1251	++pHostCpu->uCurrentAsid;
1252
1253	bool fHitASIDLimit = false;
1254	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1255	{
1256	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1257	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1258	fHitASIDLimit = true;
1259	}
1260
1261	if ( fHitASIDLimit
1262	\|\| pHostCpu->fFlushAsidBeforeUse)
1263	{
1264	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1265	pHostCpu->fFlushAsidBeforeUse = false;
1266	}
1267
1268	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1269	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1270	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1271	}
1272	else
1273	{
1274	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1275	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1276	else
1277	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1278	}
1279
1280	pVCpu->hm.s.fForceTLBFlush = false;
1281	}
1282	}
1283
1284	/* Update VMCB with the ASID. */
1285	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1286	{
1287	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1288	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1289	}
1290
1291	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1292	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1293	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1294	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1295	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1296	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1297	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1298	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1299
1300	#ifdef VBOX_WITH_STATISTICS
1301	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1302	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1303	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1304	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1305	{
1306	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1307	}
1308	else
1309	{
1310	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1311	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1312	}
1313	#endif
1314	}
1315
1316
1317	/**
1318	* Sets an exception intercept in the specified VMCB.
1319	*
1320	* @param pVmcb Pointer to the VM control block.
1321	* @param uXcpt The exception (X86_XCPT_*).
1322	*/
1323	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1324	{
1325	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1326	{
1327	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1328	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1329	}
1330	}
1331
1332
1333	/**
1334	* Clears an exception intercept in the specified VMCB.
1335	*
1336	* @param pVCpu The cross context virtual CPU structure.
1337	* @param pVmcb Pointer to the VM control block.
1338	* @param uXcpt The exception (X86_XCPT_*).
1339	*
1340	* @remarks This takes into account if we're executing a nested-guest and only
1341	* removes the exception intercept if both the guest -and- nested-guest
1342	* are not intercepting it.
1343	*/
1344	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1345	{
1346	Assert(uXcpt != X86_XCPT_DB);
1347	Assert(uXcpt != X86_XCPT_AC);
1348	Assert(uXcpt != X86_XCPT_GP);
1349	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1350	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1351	{
1352	bool fRemove = true;
1353	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1354	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1355	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1356	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1357	{
1358	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1359	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1360	}
1361	# else
1362	RT_NOREF(pVCpu);
1363	# endif
1364	if (fRemove)
1365	{
1366	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1367	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1368	}
1369	}
1370	#else
1371	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1372	#endif
1373	}
1374
1375
1376	/**
1377	* Sets a control intercept in the specified VMCB.
1378	*
1379	* @param pVmcb Pointer to the VM control block.
1380	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1381	*/
1382	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1383	{
1384	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1385	{
1386	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1387	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1388	}
1389	}
1390
1391
1392	/**
1393	* Clears a control intercept in the specified VMCB.
1394	*
1395	* @returns @c true if the intercept is still set, @c false otherwise.
1396	* @param pVCpu The cross context virtual CPU structure.
1397	* @param pVmcb Pointer to the VM control block.
1398	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1399	*
1400	* @remarks This takes into account if we're executing a nested-guest and only
1401	* removes the control intercept if both the guest -and- nested-guest
1402	* are not intercepting it.
1403	*/
1404	static bool hmR0SvmClearCtrlIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1405	{
1406	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1407	{
1408	bool fRemove = true;
1409	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1410	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1411	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1412	{
1413	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1414	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1415	}
1416	#else
1417	RT_NOREF(pVCpu);
1418	#endif
1419	if (fRemove)
1420	{
1421	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1422	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1423	}
1424	}
1425
1426	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1427	}
1428
1429
1430	/**
1431	* Exports the guest (or nested-guest) CR0 into the VMCB.
1432	*
1433	* @param pVCpu The cross context virtual CPU structure.
1434	* @param pVmcb Pointer to the VM control block.
1435	*
1436	* @remarks This assumes we always pre-load the guest FPU.
1437	* @remarks No-long-jump zone!!!
1438	*/
1439	static void hmR0SvmExportGuestCR0(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1440	{
1441	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1442
1443	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1444	uint64_t const uGuestCr0 = pCtx->cr0;
1445	uint64_t uShadowCr0 = uGuestCr0;
1446
1447	/* Always enable caching. */
1448	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1449
1450	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1451	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1452	{
1453	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1454	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1455	}
1456
1457	/*
1458	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1459	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1460	* see @bugref{7243#c103}.
1461	*/
1462	if (!(uGuestCr0 & X86_CR0_NE))
1463	{
1464	uShadowCr0 \|= X86_CR0_NE;
1465	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1466	}
1467	else
1468	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1469
1470	/*
1471	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1472	*
1473	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1474	* see @bugref{6944}.
1475	*
1476	* We also don't ever want to honor weird things like cache disable from the guest.
1477	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1478	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1479	*/
1480	if (uShadowCr0 == uGuestCr0)
1481	{
1482	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1483	{
1484	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1485	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1486	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1487	}
1488	else
1489	{
1490	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1491	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1492	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1493	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1494	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1495	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1496	}
1497	}
1498	else
1499	{
1500	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1501	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1502	}
1503	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1504
1505	Assert(!RT_HI_U32(uShadowCr0));
1506	if (pVmcb->guest.u64CR0 != uShadowCr0)
1507	{
1508	pVmcb->guest.u64CR0 = uShadowCr0;
1509	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1510	}
1511	}
1512
1513
1514	/**
1515	* Exports the guest (or nested-guest) CR3 into the VMCB.
1516	*
1517	* @param pVCpu The cross context virtual CPU structure.
1518	* @param pVmcb Pointer to the VM control block.
1519	*
1520	* @remarks No-long-jump zone!!!
1521	*/
1522	static void hmR0SvmExportGuestCR3(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1523	{
1524	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1525
1526	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1527	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1528	if (pVM->hm.s.fNestedPaging)
1529	{
1530	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetHyperCR3(pVCpu);
1531	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1532	pVmcb->guest.u64CR3 = pCtx->cr3;
1533	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1534	}
1535	else
1536	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1537
1538	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1539	}
1540
1541
1542	/**
1543	* Exports the guest (or nested-guest) CR4 into the VMCB.
1544	*
1545	* @param pVCpu The cross context virtual CPU structure.
1546	* @param pVmcb Pointer to the VM control block.
1547	*
1548	* @remarks No-long-jump zone!!!
1549	*/
1550	static int hmR0SvmExportGuestCR4(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1551	{
1552	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1553
1554	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1555	uint64_t uShadowCr4 = pCtx->cr4;
1556	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1557	{
1558	switch (pVCpu->hm.s.enmShadowMode)
1559	{
1560	case PGMMODE_REAL:
1561	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1562	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1563
1564	case PGMMODE_32_BIT: /* 32-bit paging. */
1565	uShadowCr4 &= ~X86_CR4_PAE;
1566	break;
1567
1568	case PGMMODE_PAE: /* PAE paging. */
1569	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1570	/** Must use PAE paging as we could use physical memory > 4 GB */
1571	uShadowCr4 \|= X86_CR4_PAE;
1572	break;
1573
1574	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1575	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1576	#ifdef VBOX_WITH_64_BITS_GUESTS
1577	break;
1578	#else
1579	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1580	#endif
1581
1582	default: /* shut up gcc */
1583	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1584	}
1585	}
1586
1587	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1588	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1589
1590	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1591	if (uShadowCr4 == pCtx->cr4)
1592	{
1593	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1594	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1595	else
1596	{
1597	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1598	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1599	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1600	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1601	}
1602	}
1603	else
1604	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1605
1606	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1607	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1608
1609	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1610	Assert(!RT_HI_U32(uShadowCr4));
1611	pVmcb->guest.u64CR4 = uShadowCr4;
1612	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1613
1614	return VINF_SUCCESS;
1615	}
1616
1617
1618	/**
1619	* Exports the guest (or nested-guest) control registers into the VMCB.
1620	*
1621	* @returns VBox status code.
1622	* @param pVCpu The cross context virtual CPU structure.
1623	* @param pVmcb Pointer to the VM control block.
1624	*
1625	* @remarks No-long-jump zone!!!
1626	*/
1627	static int hmR0SvmExportGuestControlRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1628	{
1629	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1630
1631	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1632	{
1633	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1634	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1635
1636	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1637	{
1638	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1639	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1640	}
1641
1642	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1643	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1644
1645	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1646	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1647	{
1648	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1649	if (RT_FAILURE(rc))
1650	return rc;
1651	}
1652
1653	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1654	}
1655	return VINF_SUCCESS;
1656	}
1657
1658
1659	/**
1660	* Exports the guest (or nested-guest) segment registers into the VMCB.
1661	*
1662	* @returns VBox status code.
1663	* @param pVCpu The cross context virtual CPU structure.
1664	* @param pVmcb Pointer to the VM control block.
1665	*
1666	* @remarks No-long-jump zone!!!
1667	*/
1668	static void hmR0SvmExportGuestSegmentRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1669	{
1670	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1671	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1672
1673	/* Guest segment registers. */
1674	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1675	{
1676	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1677	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1678
1679	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1680	{
1681	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1682	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1683	}
1684
1685	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1686	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1687
1688	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1689	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1690
1691	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1692	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1693
1694	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1695	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1696
1697	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1698	}
1699
1700	/* Guest TR. */
1701	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1702	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1703
1704	/* Guest LDTR. */
1705	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1706	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1707
1708	/* Guest GDTR. */
1709	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1710	{
1711	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1712	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1713	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1714	}
1715
1716	/* Guest IDTR. */
1717	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1718	{
1719	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1720	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1721	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1722	}
1723
1724	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1725	\| HM_CHANGED_GUEST_TABLE_MASK);
1726	}
1727
1728
1729	/**
1730	* Exports the guest (or nested-guest) MSRs into the VMCB.
1731	*
1732	* @param pVCpu The cross context virtual CPU structure.
1733	* @param pVmcb Pointer to the VM control block.
1734	*
1735	* @remarks No-long-jump zone!!!
1736	*/
1737	static void hmR0SvmExportGuestMsrs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1738	{
1739	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1740	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1741
1742	/* Guest Sysenter MSRs. */
1743	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1744	{
1745	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1746	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1747
1748	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1749	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1750
1751	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1752	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1753	}
1754
1755	/*
1756	* Guest EFER MSR.
1757	* AMD-V requires guest EFER.SVME to be set. Weird.
1758	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1759	*/
1760	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1761	{
1762	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1763	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1764	}
1765
1766	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1767	if ( !CPUMIsGuestInLongModeEx(pCtx)
1768	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1769	{
1770	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1771	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1772	}
1773
1774	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1775	{
1776	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1777	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1778	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1779	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1780	}
1781
1782	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1783	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1784
1785	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1786	\| HM_CHANGED_GUEST_EFER_MSR
1787	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1788	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1789
1790	/*
1791	* Setup the PAT MSR (applicable for Nested Paging only).
1792	*
1793	* The default value should be MSR_IA32_CR_PAT_INIT_VAL, but we treat all guest memory
1794	* as WB, so choose type 6 for all PAT slots, see @bugref{9634}.
1795	*
1796	* While guests can modify and see the modified values through the shadow values,
1797	* we shall not honor any guest modifications of this MSR to ensure caching is always
1798	* enabled similar to how we clear CR0.CD and NW bits.
1799	*
1800	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1801	*/
1802	pVmcb->guest.u64PAT = UINT64_C(0x0006060606060606);
1803
1804	/* Enable the last branch record bit if LBR virtualization is enabled. */
1805	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1806	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1807	}
1808
1809
1810	/**
1811	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1812	* the necessary intercepts accordingly.
1813	*
1814	* @param pVCpu The cross context virtual CPU structure.
1815	* @param pVmcb Pointer to the VM control block.
1816	*
1817	* @remarks No-long-jump zone!!!
1818	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1819	*/
1820	static void hmR0SvmExportSharedDebugState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1821	{
1822	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1823
1824	/*
1825	* Anyone single stepping on the host side? If so, we'll have to use the
1826	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1827	* the VMM level like the VT-x implementations does.
1828	*/
1829	bool fInterceptMovDRx = false;
1830	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1831	if (fStepping)
1832	{
1833	pVCpu->hm.s.fClearTrapFlag = true;
1834	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1835	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1836	}
1837
1838	if ( fStepping
1839	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1840	{
1841	/*
1842	* Use the combined guest and host DRx values found in the hypervisor
1843	* register set because the debugger has breakpoints active or someone
1844	* is single stepping on the host side.
1845	*
1846	* Note! DBGF expects a clean DR6 state before executing guest code.
1847	*/
1848	if (!CPUMIsHyperDebugStateActive(pVCpu))
1849	{
1850	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1851	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1852	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1853	}
1854
1855	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1856	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1857	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1858	{
1859	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1860	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1861	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1862	}
1863
1864	/** @todo If we cared, we could optimize to allow the guest to read registers
1865	* with the same values. */
1866	fInterceptMovDRx = true;
1867	pVCpu->hm.s.fUsingHyperDR7 = true;
1868	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1869	}
1870	else
1871	{
1872	/*
1873	* Update DR6, DR7 with the guest values if necessary.
1874	*/
1875	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1876	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1877	{
1878	pVmcb->guest.u64DR7 = pCtx->dr[7];
1879	pVmcb->guest.u64DR6 = pCtx->dr[6];
1880	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1881	}
1882	pVCpu->hm.s.fUsingHyperDR7 = false;
1883
1884	/*
1885	* If the guest has enabled debug registers, we need to load them prior to
1886	* executing guest code so they'll trigger at the right time.
1887	*/
1888	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1889	{
1890	if (!CPUMIsGuestDebugStateActive(pVCpu))
1891	{
1892	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1893	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1894	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1895	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1896	}
1897	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
1898	}
1899	/*
1900	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1901	* intercept #DB as DR6 is updated in the VMCB.
1902	*
1903	* Note! If we cared and dared, we could skip intercepting \#DB here.
1904	* However, \#DB shouldn't be performance critical, so we'll play safe
1905	* and keep the code similar to the VT-x code and always intercept it.
1906	*/
1907	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1908	fInterceptMovDRx = true;
1909	}
1910
1911	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1912	if (fInterceptMovDRx)
1913	{
1914	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1915	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1916	{
1917	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1918	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1919	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1920	}
1921	}
1922	else
1923	{
1924	if ( pVmcb->ctrl.u16InterceptRdDRx
1925	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1926	{
1927	pVmcb->ctrl.u16InterceptRdDRx = 0;
1928	pVmcb->ctrl.u16InterceptWrDRx = 0;
1929	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1930	}
1931	}
1932	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1933	}
1934
1935	/**
1936	* Exports the hardware virtualization state into the nested-guest
1937	* VMCB.
1938	*
1939	* @param pVCpu The cross context virtual CPU structure.
1940	* @param pVmcb Pointer to the VM control block.
1941	*
1942	* @remarks No-long-jump zone!!!
1943	*/
1944	static void hmR0SvmExportGuestHwvirtState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1945	{
1946	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1947
1948	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
1949	{
1950	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
1951	{
1952	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1953	PCVM pVM = pVCpu->CTX_SUFF(pVM);
1954
1955	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx); /* Nested VGIF is not supported yet. */
1956	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Physical hardware supports VGIF. */
1957	Assert(HMIsSvmVGifActive(pVM)); /* Outer VM has enabled VGIF. */
1958	NOREF(pVM);
1959
1960	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
1961	}
1962
1963	/*
1964	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
1965	* since SVM doesn't have a preemption timer.
1966	*
1967	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
1968	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
1969	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
1970	*/
1971	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1972	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
1973	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1974	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1975	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_PAUSE))
1976	{
1977	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1978	pVmcbCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
1979	pVmcbCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
1980	}
1981	else
1982	{
1983	/** @todo r=ramshankar: We can turn these assignments into assertions. */
1984	pVmcbCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
1985	pVmcbCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
1986	}
1987	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1988
1989	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
1990	}
1991	}
1992
1993
1994	/**
1995	* Exports the guest APIC TPR state into the VMCB.
1996	*
1997	* @returns VBox status code.
1998	* @param pVCpu The cross context virtual CPU structure.
1999	* @param pVmcb Pointer to the VM control block.
2000	*/
2001	static int hmR0SvmExportGuestApicTpr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2002	{
2003	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2004
2005	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2006	{
2007	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2008	if ( PDMHasApic(pVM)
2009	&& APICIsEnabled(pVCpu))
2010	{
2011	bool fPendingIntr;
2012	uint8_t u8Tpr;
2013	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2014	AssertRCReturn(rc, rc);
2015
2016	/* Assume that we need to trap all TPR accesses and thus need not check on
2017	every #VMEXIT if we should update the TPR. */
2018	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2019	pVCpu->hm.s.svm.fSyncVTpr = false;
2020
2021	if (!pVM->hm.s.fTPRPatchingActive)
2022	{
2023	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2024	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2025
2026	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2027	can deliver the interrupt to the guest. */
2028	if (fPendingIntr)
2029	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2030	else
2031	{
2032	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2033	pVCpu->hm.s.svm.fSyncVTpr = true;
2034	}
2035
2036	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2037	}
2038	else
2039	{
2040	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2041	pVmcb->guest.u64LSTAR = u8Tpr;
2042	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
2043
2044	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2045	if (fPendingIntr)
2046	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2047	else
2048	{
2049	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2050	pVCpu->hm.s.svm.fSyncVTpr = true;
2051	}
2052	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2053	}
2054	}
2055	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2056	}
2057	return VINF_SUCCESS;
2058	}
2059
2060
2061	/**
2062	* Sets up the exception interrupts required for guest execution in the VMCB.
2063	*
2064	* @param pVCpu The cross context virtual CPU structure.
2065	* @param pVmcb Pointer to the VM control block.
2066	*
2067	* @remarks No-long-jump zone!!!
2068	*/
2069	static void hmR0SvmExportGuestXcptIntercepts(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2070	{
2071	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2072
2073	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2074	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_SVM_XCPT_INTERCEPTS)
2075	{
2076	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2077	if (pVCpu->hm.s.fGIMTrapXcptUD)
2078	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2079	else
2080	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2081
2082	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2083	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2084	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2085	else
2086	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2087
2088	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2089	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_SVM_XCPT_INTERCEPTS);
2090	}
2091	}
2092
2093
2094	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2095	/**
2096	* Merges guest and nested-guest intercepts for executing the nested-guest using
2097	* hardware-assisted SVM.
2098	*
2099	* This merges the guest and nested-guest intercepts in a way that if the outer
2100	* guest intercept is set we need to intercept it in the nested-guest as
2101	* well.
2102	*
2103	* @param pVCpu The cross context virtual CPU structure.
2104	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2105	*/
2106	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
2107	{
2108	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2109	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2110	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2111	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2112
2113	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2114	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2115	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2116
2117	/* Always intercept CR4 writes for tracking PGM mode changes. */
2118	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2119
2120	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2121	if (!pVM->hm.s.fNestedPaging)
2122	{
2123	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2124	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2125	}
2126
2127	/** @todo Figure out debugging with nested-guests, till then just intercept
2128	* all DR[0-15] accesses. */
2129	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2130	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2131
2132	/*
2133	* Merge the guest's exception intercepts into the nested-guest VMCB.
2134	*
2135	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2136	* while executing the nested-guest.
2137	*
2138	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2139	* be tweaked later depending on how we wish to implement breakpoints.
2140	*
2141	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2142	* loaded into their guests, not ours.
2143	*
2144	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2145	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2146	*/
2147	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2148	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2149	& ~( RT_BIT(X86_XCPT_UD)
2150	\| RT_BIT(X86_XCPT_BP)
2151	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2152	#else
2153	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2154	#endif
2155
2156	/*
2157	* Adjust intercepts while executing the nested-guest that differ from the
2158	* outer guest intercepts.
2159	*
2160	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2161	* that belong to the nested-guest to the outer guest.
2162	*
2163	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2164	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2165	*/
2166	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2167	\| SVM_CTRL_INTERCEPT_VMMCALL))
2168	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2169
2170	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2171	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2172
2173	/* Finally, update the VMCB clean bits. */
2174	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2175	}
2176	#endif
2177
2178
2179	/**
2180	* Selects the appropriate function to run guest code.
2181	*
2182	* @param pVCpu The cross context virtual CPU structure.
2183	*
2184	* @remarks No-long-jump zone!!!
2185	*/
2186	DECLINLINE(void) hmR0SvmSelectVMRunHandler(PVMCPUCC pVCpu)
2187	{
2188	if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
2189	{
2190	# if HC_ARCH_BITS != 64 \|\| ARCH_BITS != 64
2191	# error "Only 64-bit hosts are supported!"
2192	# endif
2193	/* Guest may enter long mode, always use 64-bit handler. */
2194	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2195	}
2196	else
2197	{
2198	/* Guest is 32-bit only, use the 32-bit handler. */
2199	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun32;
2200	}
2201	}
2202
2203
2204	/**
2205	* Enters the AMD-V session.
2206	*
2207	* @returns VBox status code.
2208	* @param pVCpu The cross context virtual CPU structure.
2209	*/
2210	VMMR0DECL(int) SVMR0Enter(PVMCPUCC pVCpu)
2211	{
2212	AssertPtr(pVCpu);
2213	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2214	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2215
2216	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2217	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2218	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2219
2220	pVCpu->hm.s.fLeaveDone = false;
2221	return VINF_SUCCESS;
2222	}
2223
2224
2225	/**
2226	* Thread-context callback for AMD-V.
2227	*
2228	* @param enmEvent The thread-context event.
2229	* @param pVCpu The cross context virtual CPU structure.
2230	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2231	* @thread EMT(pVCpu)
2232	*/
2233	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
2234	{
2235	NOREF(fGlobalInit);
2236
2237	switch (enmEvent)
2238	{
2239	case RTTHREADCTXEVENT_OUT:
2240	{
2241	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2242	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2243	VMCPU_ASSERT_EMT(pVCpu);
2244
2245	/* No longjmps (log-flush, locks) in this fragile context. */
2246	VMMRZCallRing3Disable(pVCpu);
2247
2248	if (!pVCpu->hm.s.fLeaveDone)
2249	{
2250	hmR0SvmLeave(pVCpu, false /* fImportState */);
2251	pVCpu->hm.s.fLeaveDone = true;
2252	}
2253
2254	/* Leave HM context, takes care of local init (term). */
2255	int rc = HMR0LeaveCpu(pVCpu);
2256	AssertRC(rc); NOREF(rc);
2257
2258	/* Restore longjmp state. */
2259	VMMRZCallRing3Enable(pVCpu);
2260	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2261	break;
2262	}
2263
2264	case RTTHREADCTXEVENT_IN:
2265	{
2266	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2267	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2268	VMCPU_ASSERT_EMT(pVCpu);
2269
2270	/* No longjmps (log-flush, locks) in this fragile context. */
2271	VMMRZCallRing3Disable(pVCpu);
2272
2273	/*
2274	* Initialize the bare minimum state required for HM. This takes care of
2275	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2276	*/
2277	int rc = hmR0EnterCpu(pVCpu);
2278	AssertRC(rc); NOREF(rc);
2279	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2280	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2281
2282	pVCpu->hm.s.fLeaveDone = false;
2283
2284	/* Restore longjmp state. */
2285	VMMRZCallRing3Enable(pVCpu);
2286	break;
2287	}
2288
2289	default:
2290	break;
2291	}
2292	}
2293
2294
2295	/**
2296	* Saves the host state.
2297	*
2298	* @returns VBox status code.
2299	* @param pVCpu The cross context virtual CPU structure.
2300	*
2301	* @remarks No-long-jump zone!!!
2302	*/
2303	VMMR0DECL(int) SVMR0ExportHostState(PVMCPUCC pVCpu)
2304	{
2305	NOREF(pVCpu);
2306
2307	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2308	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2309	return VINF_SUCCESS;
2310	}
2311
2312
2313	/**
2314	* Exports the guest or nested-guest state from the virtual-CPU context into the
2315	* VMCB.
2316	*
2317	* Also sets up the appropriate VMRUN function to execute guest or nested-guest
2318	* code based on the virtual-CPU mode.
2319	*
2320	* @returns VBox status code.
2321	* @param pVCpu The cross context virtual CPU structure.
2322	* @param pSvmTransient Pointer to the SVM-transient structure.
2323	*
2324	* @remarks No-long-jump zone!!!
2325	*/
2326	static int hmR0SvmExportGuestState(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
2327	{
2328	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2329
2330	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2331	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2332	Assert(pVmcb);
2333
2334	pVmcb->guest.u64RIP = pCtx->rip;
2335	pVmcb->guest.u64RSP = pCtx->rsp;
2336	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2337	pVmcb->guest.u64RAX = pCtx->rax;
2338
2339	bool const fIsNestedGuest = pSvmTransient->fIsNestedGuest;
2340	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2341
2342	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2343	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2344	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2345	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2346	hmR0SvmExportGuestHwvirtState(pVCpu, pVmcb);
2347
2348	ASMSetFlags(fEFlags);
2349
2350	if (!fIsNestedGuest)
2351	{
2352	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2353	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2354	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2355	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2356	}
2357
2358	hmR0SvmSelectVMRunHandler(pVCpu);
2359
2360	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2361	uint64_t fUnusedMask = HM_CHANGED_GUEST_RIP
2362	\| HM_CHANGED_GUEST_RFLAGS
2363	\| HM_CHANGED_GUEST_GPRS_MASK
2364	\| HM_CHANGED_GUEST_X87
2365	\| HM_CHANGED_GUEST_SSE_AVX
2366	\| HM_CHANGED_GUEST_OTHER_XSAVE
2367	\| HM_CHANGED_GUEST_XCRx
2368	\| HM_CHANGED_GUEST_TSC_AUX
2369	\| HM_CHANGED_GUEST_OTHER_MSRS;
2370	if (fIsNestedGuest)
2371	fUnusedMask \|= HM_CHANGED_SVM_XCPT_INTERCEPTS
2372	\| HM_CHANGED_GUEST_APIC_TPR;
2373
2374	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( fUnusedMask
2375	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2376
2377	#ifdef VBOX_STRICT
2378	/*
2379	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2380	* except for the host-context and/or shared host-guest context bits.
2381	*/
2382	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2383	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2384	("fCtxChanged=%#RX64\n", fCtxChanged));
2385
2386	/*
2387	* If we need to log state that isn't always imported, we'll need to import them here.
2388	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2389	*/
2390	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2391	#endif
2392
2393	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2394	return VINF_SUCCESS;
2395	}
2396
2397
2398	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2399	/**
2400	* Merges the guest and nested-guest MSR permission bitmap.
2401	*
2402	* If the guest is intercepting an MSR we need to intercept it regardless of
2403	* whether the nested-guest is intercepting it or not.
2404	*
2405	* @param pHostCpu The HM physical-CPU structure.
2406	* @param pVCpu The cross context virtual CPU structure.
2407	*
2408	* @remarks No-long-jmp zone!!!
2409	*/
2410	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2411	{
2412	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2413	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2414	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2415
2416	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2417	uint32_t const offRsvdQwords = 0x1800 >> 3;
2418	for (uint32_t i = 0; i < offRsvdQwords; i++)
2419	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2420	}
2421
2422
2423	/**
2424	* Caches the nested-guest VMCB fields before we modify them for execution using
2425	* hardware-assisted SVM.
2426	*
2427	* @returns true if the VMCB was previously already cached, false otherwise.
2428	* @param pVCpu The cross context virtual CPU structure.
2429	*
2430	* @sa HMNotifySvmNstGstVmexit.
2431	*/
2432	static bool hmR0SvmCacheVmcbNested(PVMCPUCC pVCpu)
2433	{
2434	/*
2435	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2436	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2437	*
2438	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2439	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2440	*/
2441	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2442	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2443	if (!fWasCached)
2444	{
2445	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2446	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2447	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2448	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2449	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2450	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2451	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2452	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2453	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2454	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2455	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2456	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2457	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2458	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2459	pVmcbNstGstCache->fCacheValid = true;
2460	Log4Func(("Cached VMCB fields\n"));
2461	}
2462
2463	return fWasCached;
2464	}
2465
2466
2467	/**
2468	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2469	*
2470	* This is done the first time we enter nested-guest execution using SVM R0
2471	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2472	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2473	*
2474	* @param pVCpu The cross context virtual CPU structure.
2475	*/
2476	static void hmR0SvmSetupVmcbNested(PVMCPUCC pVCpu)
2477	{
2478	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2479	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2480
2481	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2482
2483	/*
2484	* First cache the nested-guest VMCB fields we may potentially modify.
2485	*/
2486	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2487	if (!fVmcbCached)
2488	{
2489	/*
2490	* The IOPM of the nested-guest can be ignored because the the guest always
2491	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2492	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2493	*/
2494	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2495
2496	/*
2497	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2498	* nested-paging suddenly while executing a VM (see assertion at the end of
2499	* Trap0eHandler() in PGMAllBth.h).
2500	*/
2501	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2502
2503	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2504	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2505
2506	/*
2507	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2508	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2509	*/
2510	pVCpu->hm.s.svm.fSyncVTpr = false;
2511
2512	#ifdef DEBUG_ramshankar
2513	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2514	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2515	#endif
2516
2517	/*
2518	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2519	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2520	*/
2521	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2522	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2523	\| SVM_CTRL_INTERCEPT_VMLOAD;
2524
2525	/*
2526	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2527	* CLGI/STGI instructions executed by the nested-guest.
2528	*/
2529	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2530	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2531	\| SVM_CTRL_INTERCEPT_STGI;
2532
2533	/* Merge the guest and nested-guest intercepts. */
2534	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2535
2536	/* Update the VMCB clean bits. */
2537	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2538	}
2539	else
2540	{
2541	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
2542	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2543	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2544	}
2545	}
2546	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2547
2548
2549	/**
2550	* Exports the state shared between the host and guest (or nested-guest) into
2551	* the VMCB.
2552	*
2553	* @param pVCpu The cross context virtual CPU structure.
2554	* @param pVmcb Pointer to the VM control block.
2555	*
2556	* @remarks No-long-jump zone!!!
2557	*/
2558	static void hmR0SvmExportSharedState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2559	{
2560	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2561	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2562
2563	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2564	{
2565	/** @todo Figure out stepping with nested-guest. */
2566	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2567	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2568	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2569	else
2570	{
2571	pVmcb->guest.u64DR6 = pCtx->dr[6];
2572	pVmcb->guest.u64DR7 = pCtx->dr[7];
2573	}
2574	}
2575
2576	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2577	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2578	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2579	}
2580
2581
2582	/**
2583	* Worker for SVMR0ImportStateOnDemand.
2584	*
2585	* @param pVCpu The cross context virtual CPU structure.
2586	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2587	*/
2588	static void hmR0SvmImportGuestState(PVMCPUCC pVCpu, uint64_t fWhat)
2589	{
2590	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2591
2592	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2593	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2594	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2595	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2596
2597	/*
2598	* We disable interrupts to make the updating of the state and in particular
2599	* the fExtrn modification atomic wrt to preemption hooks.
2600	*/
2601	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2602
2603	fWhat &= pCtx->fExtrn;
2604	if (fWhat)
2605	{
2606	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2607	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2608	{
2609	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2610	{
2611	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2612	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2613	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2614	}
2615	}
2616
2617	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2618	{
2619	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2620	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2621	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2622	}
2623	#endif
2624
2625	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2626	{
2627	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2628	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2629	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2630	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2631	}
2632
2633	if (fWhat & CPUMCTX_EXTRN_RIP)
2634	pCtx->rip = pVmcbGuest->u64RIP;
2635
2636	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2637	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2638
2639	if (fWhat & CPUMCTX_EXTRN_RSP)
2640	pCtx->rsp = pVmcbGuest->u64RSP;
2641
2642	if (fWhat & CPUMCTX_EXTRN_RAX)
2643	pCtx->rax = pVmcbGuest->u64RAX;
2644
2645	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2646	{
2647	if (fWhat & CPUMCTX_EXTRN_CS)
2648	{
2649	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2650	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2651	/** @todo SELM might need to be fixed as it too should not care about the
2652	* granularity bit. See @bugref{6785}. */
2653	if ( !pCtx->cs.Attr.n.u1Granularity
2654	&& pCtx->cs.Attr.n.u1Present
2655	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2656	{
2657	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2658	pCtx->cs.Attr.n.u1Granularity = 1;
2659	}
2660	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2661	}
2662	if (fWhat & CPUMCTX_EXTRN_SS)
2663	{
2664	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2665	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2666	/*
2667	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2668	* VMCB and uses that and thus it's possible that when the CPL changes during
2669	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2670	* AMD Fusion CPUs with 64-bit guests.
2671	*
2672	* See AMD spec. 15.5.1 "Basic operation".
2673	*/
2674	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2675	uint8_t const uCpl = pVmcbGuest->u8CPL;
2676	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2677	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2678	}
2679	if (fWhat & CPUMCTX_EXTRN_DS)
2680	{
2681	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2682	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2683	}
2684	if (fWhat & CPUMCTX_EXTRN_ES)
2685	{
2686	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2687	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2688	}
2689	if (fWhat & CPUMCTX_EXTRN_FS)
2690	{
2691	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2692	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2693	}
2694	if (fWhat & CPUMCTX_EXTRN_GS)
2695	{
2696	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2697	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2698	}
2699	}
2700
2701	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2702	{
2703	if (fWhat & CPUMCTX_EXTRN_TR)
2704	{
2705	/*
2706	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2707	* are used between Intel and AMD, see @bugref{6208#c39}.
2708	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2709	*/
2710	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2711	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2712	{
2713	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2714	\|\| CPUMIsGuestInLongModeEx(pCtx))
2715	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2716	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2717	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2718	}
2719	}
2720
2721	if (fWhat & CPUMCTX_EXTRN_LDTR)
2722	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2723
2724	if (fWhat & CPUMCTX_EXTRN_GDTR)
2725	{
2726	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2727	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2728	}
2729
2730	if (fWhat & CPUMCTX_EXTRN_IDTR)
2731	{
2732	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2733	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2734	}
2735	}
2736
2737	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2738	{
2739	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2740	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2741	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2742	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2743	}
2744
2745	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2746	{
2747	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2748	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2749	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2750	}
2751
2752	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2753	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2754
2755	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2756	{
2757	if (fWhat & CPUMCTX_EXTRN_DR6)
2758	{
2759	if (!pVCpu->hm.s.fUsingHyperDR7)
2760	pCtx->dr[6] = pVmcbGuest->u64DR6;
2761	else
2762	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2763	}
2764
2765	if (fWhat & CPUMCTX_EXTRN_DR7)
2766	{
2767	if (!pVCpu->hm.s.fUsingHyperDR7)
2768	pCtx->dr[7] = pVmcbGuest->u64DR7;
2769	else
2770	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2771	}
2772	}
2773
2774	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2775	{
2776	if (fWhat & CPUMCTX_EXTRN_CR0)
2777	{
2778	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2779	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2780	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2781	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2782	CPUMSetGuestCR0(pVCpu, uCr0);
2783	VMMRZCallRing3Enable(pVCpu);
2784	}
2785
2786	if (fWhat & CPUMCTX_EXTRN_CR2)
2787	pCtx->cr2 = pVmcbGuest->u64CR2;
2788
2789	if (fWhat & CPUMCTX_EXTRN_CR3)
2790	{
2791	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2792	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2793	{
2794	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2795	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2796	}
2797	}
2798
2799	/* Changes to CR4 are always intercepted. */
2800	}
2801
2802	/* Update fExtrn. */
2803	pCtx->fExtrn &= ~fWhat;
2804
2805	/* If everything has been imported, clear the HM keeper bit. */
2806	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2807	{
2808	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2809	Assert(!pCtx->fExtrn);
2810	}
2811	}
2812	else
2813	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
2814
2815	ASMSetFlags(fEFlags);
2816
2817	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
2818
2819	/*
2820	* Honor any pending CR3 updates.
2821	*
2822	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
2823	* -> SVMR0CallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
2824	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
2825	* handling -> hmR0SvmImportGuestState() and here we are.
2826	*
2827	* The reason for such complicated handling is because VM-exits that call into PGM expect
2828	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
2829	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
2830	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
2831	*
2832	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
2833	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
2834	*/
2835	if ( VMMRZCallRing3IsEnabled(pVCpu)
2836	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2837	{
2838	Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
2839	PGMUpdateCR3(pVCpu, pCtx->cr3);
2840	}
2841	}
2842
2843
2844	/**
2845	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2846	* context.
2847	*
2848	* Currently there is no residual state left in the CPU that is not updated in the
2849	* VMCB.
2850	*
2851	* @returns VBox status code.
2852	* @param pVCpu The cross context virtual CPU structure.
2853	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2854	*/
2855	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2856	{
2857	hmR0SvmImportGuestState(pVCpu, fWhat);
2858	return VINF_SUCCESS;
2859	}
2860
2861
2862	/**
2863	* Does the necessary state syncing before returning to ring-3 for any reason
2864	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2865	*
2866	* @param pVCpu The cross context virtual CPU structure.
2867	* @param fImportState Whether to import the guest state from the VMCB back
2868	* to the guest-CPU context.
2869	*
2870	* @remarks No-long-jmp zone!!!
2871	*/
2872	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState)
2873	{
2874	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2875	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2876	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2877
2878	/*
2879	* !!! IMPORTANT !!!
2880	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2881	*/
2882
2883	/* Save the guest state if necessary. */
2884	if (fImportState)
2885	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2886
2887	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2888	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2889	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2890
2891	/*
2892	* Restore host debug registers if necessary and resync on next R0 reentry.
2893	*/
2894	#ifdef VBOX_STRICT
2895	if (CPUMIsHyperDebugStateActive(pVCpu))
2896	{
2897	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2898	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2899	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2900	}
2901	#endif
2902	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2903	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2904	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2905
2906	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2907	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
2908	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
2909	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
2910	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
2911	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
2912	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2913
2914	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2915	}
2916
2917
2918	/**
2919	* Leaves the AMD-V session.
2920	*
2921	* Only used while returning to ring-3 either due to longjump or exits to
2922	* ring-3.
2923	*
2924	* @returns VBox status code.
2925	* @param pVCpu The cross context virtual CPU structure.
2926	*/
2927	static int hmR0SvmLeaveSession(PVMCPUCC pVCpu)
2928	{
2929	HM_DISABLE_PREEMPT(pVCpu);
2930	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2931	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2932
2933	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2934	and done this from the SVMR0ThreadCtxCallback(). */
2935	if (!pVCpu->hm.s.fLeaveDone)
2936	{
2937	hmR0SvmLeave(pVCpu, true /* fImportState */);
2938	pVCpu->hm.s.fLeaveDone = true;
2939	}
2940
2941	/*
2942	* !!! IMPORTANT !!!
2943	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2944	*/
2945
2946	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2947	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2948	VMMR0ThreadCtxHookDisable(pVCpu);
2949
2950	/* Leave HM context. This takes care of local init (term). */
2951	int rc = HMR0LeaveCpu(pVCpu);
2952
2953	HM_RESTORE_PREEMPT();
2954	return rc;
2955	}
2956
2957
2958	/**
2959	* Does the necessary state syncing before doing a longjmp to ring-3.
2960	*
2961	* @returns VBox status code.
2962	* @param pVCpu The cross context virtual CPU structure.
2963	*
2964	* @remarks No-long-jmp zone!!!
2965	*/
2966	static int hmR0SvmLongJmpToRing3(PVMCPUCC pVCpu)
2967	{
2968	return hmR0SvmLeaveSession(pVCpu);
2969	}
2970
2971
2972	/**
2973	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2974	* any remaining host state) before we longjump to ring-3 and possibly get
2975	* preempted.
2976	*
2977	* @param pVCpu The cross context virtual CPU structure.
2978	* @param enmOperation The operation causing the ring-3 longjump.
2979	*/
2980	VMMR0DECL(int) SVMR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
2981	{
2982	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2983	{
2984	/*
2985	* !!! IMPORTANT !!!
2986	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2987	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2988	*/
2989	VMMRZCallRing3RemoveNotification(pVCpu);
2990	VMMRZCallRing3Disable(pVCpu);
2991	HM_DISABLE_PREEMPT(pVCpu);
2992
2993	/* Import the entire guest state. */
2994	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2995
2996	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2997	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2998
2999	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3000	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3001
3002	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3003	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3004	VMMR0ThreadCtxHookDisable(pVCpu);
3005
3006	/* Leave HM context. This takes care of local init (term). */
3007	HMR0LeaveCpu(pVCpu);
3008
3009	HM_RESTORE_PREEMPT();
3010	return VINF_SUCCESS;
3011	}
3012
3013	Assert(pVCpu);
3014	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3015	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3016
3017	VMMRZCallRing3Disable(pVCpu);
3018	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3019
3020	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3021	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3022	AssertRCReturn(rc, rc);
3023
3024	VMMRZCallRing3Enable(pVCpu);
3025	return VINF_SUCCESS;
3026	}
3027
3028
3029	/**
3030	* Take necessary actions before going back to ring-3.
3031	*
3032	* An action requires us to go back to ring-3. This function does the necessary
3033	* steps before we can safely return to ring-3. This is not the same as longjmps
3034	* to ring-3, this is voluntary.
3035	*
3036	* @returns VBox status code.
3037	* @param pVCpu The cross context virtual CPU structure.
3038	* @param rcExit The reason for exiting to ring-3. Can be
3039	* VINF_VMM_UNKNOWN_RING3_CALL.
3040	*/
3041	static int hmR0SvmExitToRing3(PVMCPUCC pVCpu, int rcExit)
3042	{
3043	Assert(pVCpu);
3044	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3045
3046	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3047	VMMRZCallRing3Disable(pVCpu);
3048	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", rcExit, (uint64_t)pVCpu->fLocalForcedActions,
3049	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3050
3051	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3052	if (pVCpu->hm.s.Event.fPending)
3053	{
3054	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3055	Assert(!pVCpu->hm.s.Event.fPending);
3056	}
3057
3058	/* Sync. the necessary state for going back to ring-3. */
3059	hmR0SvmLeaveSession(pVCpu);
3060	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3061
3062	/* Thread-context hooks are unregistered at this point!!! */
3063	/* Ring-3 callback notifications are unregistered at this point!!! */
3064
3065	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3066	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3067	\| CPUM_CHANGED_LDTR
3068	\| CPUM_CHANGED_GDTR
3069	\| CPUM_CHANGED_IDTR
3070	\| CPUM_CHANGED_TR
3071	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3072	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
3073	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3074	{
3075	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3076	}
3077
3078	/* Update the exit-to-ring 3 reason. */
3079	pVCpu->hm.s.rcLastExitToR3 = rcExit;
3080
3081	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3082	if ( rcExit != VINF_EM_RAW_INTERRUPT
3083	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3084	{
3085	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3086	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3087	}
3088
3089	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3090	VMMRZCallRing3Enable(pVCpu);
3091
3092	/*
3093	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3094	* and if we're injecting an event we should have a TRPM trap pending.
3095	*/
3096	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3097	pVCpu->hm.s.u32HMError = rcExit,
3098	VERR_SVM_IPE_5);
3099	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3100	pVCpu->hm.s.u32HMError = rcExit,
3101	VERR_SVM_IPE_4);
3102
3103	return rcExit;
3104	}
3105
3106
3107	/**
3108	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3109	* intercepts.
3110	*
3111	* @param pVCpu The cross context virtual CPU structure.
3112	* @param pVmcb Pointer to the VM control block.
3113	*
3114	* @remarks No-long-jump zone!!!
3115	*/
3116	static void hmR0SvmUpdateTscOffsetting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3117	{
3118	/*
3119	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3120	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3121	* RDTSC/RDTSCP as well.
3122	*/
3123	bool fParavirtTsc;
3124	uint64_t uTscOffset;
3125	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3126
3127	bool fIntercept;
3128	if (fCanUseRealTsc)
3129	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3130	else
3131	{
3132	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3133	fIntercept = true;
3134	}
3135
3136	if (!fIntercept)
3137	{
3138	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3139	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3140	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3141	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
3142	#endif
3143
3144	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3145	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3146	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3147	}
3148
3149	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3150	information before every VM-entry, hence we have nothing to do here at the moment. */
3151	if (fParavirtTsc)
3152	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3153	}
3154
3155
3156	/**
3157	* Sets an event as a pending event to be injected into the guest.
3158	*
3159	* @param pVCpu The cross context virtual CPU structure.
3160	* @param pEvent Pointer to the SVM event.
3161	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3162	* page-fault.
3163	*
3164	* @remarks Statistics counter assumes this is a guest event being reflected to
3165	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3166	*/
3167	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPUCC pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3168	{
3169	Assert(!pVCpu->hm.s.Event.fPending);
3170	Assert(pEvent->n.u1Valid);
3171
3172	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3173	pVCpu->hm.s.Event.fPending = true;
3174	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3175
3176	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3177	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3178	}
3179
3180
3181	/**
3182	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3183	*
3184	* @param pVCpu The cross context virtual CPU structure.
3185	*/
3186	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPUCC pVCpu)
3187	{
3188	SVMEVENT Event;
3189	Event.u = 0;
3190	Event.n.u1Valid = 1;
3191	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3192	Event.n.u8Vector = X86_XCPT_UD;
3193	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3194	}
3195
3196
3197	/**
3198	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3199	*
3200	* @param pVCpu The cross context virtual CPU structure.
3201	*/
3202	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPUCC pVCpu)
3203	{
3204	SVMEVENT Event;
3205	Event.u = 0;
3206	Event.n.u1Valid = 1;
3207	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3208	Event.n.u8Vector = X86_XCPT_DB;
3209	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3210	}
3211
3212
3213	/**
3214	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3215	*
3216	* @param pVCpu The cross context virtual CPU structure.
3217	* @param u32ErrCode The error-code for the page-fault.
3218	* @param uFaultAddress The page fault address (CR2).
3219	*
3220	* @remarks This updates the guest CR2 with @a uFaultAddress!
3221	*/
3222	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPUCC pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3223	{
3224	SVMEVENT Event;
3225	Event.u = 0;
3226	Event.n.u1Valid = 1;
3227	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3228	Event.n.u8Vector = X86_XCPT_PF;
3229	Event.n.u1ErrorCodeValid = 1;
3230	Event.n.u32ErrorCode = u32ErrCode;
3231
3232	/* Update CR2 of the guest. */
3233	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3234	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3235	{
3236	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3237	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3238	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3239	}
3240
3241	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3242	}
3243
3244
3245	/**
3246	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3247	*
3248	* @param pVCpu The cross context virtual CPU structure.
3249	*/
3250	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPUCC pVCpu)
3251	{
3252	SVMEVENT Event;
3253	Event.u = 0;
3254	Event.n.u1Valid = 1;
3255	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3256	Event.n.u8Vector = X86_XCPT_MF;
3257	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3258	}
3259
3260
3261	/**
3262	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3263	*
3264	* @param pVCpu The cross context virtual CPU structure.
3265	*/
3266	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPUCC pVCpu)
3267	{
3268	SVMEVENT Event;
3269	Event.u = 0;
3270	Event.n.u1Valid = 1;
3271	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3272	Event.n.u8Vector = X86_XCPT_DF;
3273	Event.n.u1ErrorCodeValid = 1;
3274	Event.n.u32ErrorCode = 0;
3275	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3276	}
3277
3278
3279	/**
3280	* Injects an event into the guest upon VMRUN by updating the relevant field
3281	* in the VMCB.
3282	*
3283	* @param pVCpu The cross context virtual CPU structure.
3284	* @param pVmcb Pointer to the guest VM control block.
3285	* @param pEvent Pointer to the event.
3286	*
3287	* @remarks No-long-jump zone!!!
3288	* @remarks Requires CR0!
3289	*/
3290	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3291	{
3292	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3293	pVmcb->ctrl.EventInject.u = pEvent->u;
3294	if ( pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_EXCEPTION
3295	\|\| pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_NMI)
3296	{
3297	Assert(pEvent->n.u8Vector <= X86_XCPT_LAST);
3298	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedXcptsR0[pEvent->n.u8Vector]);
3299	}
3300	else
3301	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3302	RT_NOREF(pVCpu);
3303
3304	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3305	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3306	}
3307
3308
3309
3310	/**
3311	* Converts any TRPM trap into a pending HM event. This is typically used when
3312	* entering from ring-3 (not longjmp returns).
3313	*
3314	* @param pVCpu The cross context virtual CPU structure.
3315	*/
3316	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
3317	{
3318	Assert(TRPMHasTrap(pVCpu));
3319	Assert(!pVCpu->hm.s.Event.fPending);
3320
3321	uint8_t uVector;
3322	TRPMEVENT enmTrpmEvent;
3323	uint32_t uErrCode;
3324	RTGCUINTPTR GCPtrFaultAddress;
3325	uint8_t cbInstr;
3326
3327	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, NULL /* pfIcebp */);
3328	AssertRC(rc);
3329
3330	SVMEVENT Event;
3331	Event.u = 0;
3332	Event.n.u1Valid = 1;
3333	Event.n.u8Vector = uVector;
3334
3335	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3336	if (enmTrpmEvent == TRPM_TRAP)
3337	{
3338	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3339	switch (uVector)
3340	{
3341	case X86_XCPT_NMI:
3342	{
3343	Event.n.u3Type = SVM_EVENT_NMI;
3344	break;
3345	}
3346
3347	case X86_XCPT_BP:
3348	case X86_XCPT_OF:
3349	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3350	RT_FALL_THRU();
3351
3352	case X86_XCPT_PF:
3353	case X86_XCPT_DF:
3354	case X86_XCPT_TS:
3355	case X86_XCPT_NP:
3356	case X86_XCPT_SS:
3357	case X86_XCPT_GP:
3358	case X86_XCPT_AC:
3359	{
3360	Event.n.u1ErrorCodeValid = 1;
3361	Event.n.u32ErrorCode = uErrCode;
3362	break;
3363	}
3364	}
3365	}
3366	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3367	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3368	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3369	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3370	else
3371	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3372
3373	rc = TRPMResetTrap(pVCpu);
3374	AssertRC(rc);
3375
3376	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3377	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3378
3379	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3380	}
3381
3382
3383	/**
3384	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3385	* AMD-V to execute any instruction.
3386	*
3387	* @param pVCpu The cross context virtual CPU structure.
3388	*/
3389	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu)
3390	{
3391	Assert(pVCpu->hm.s.Event.fPending);
3392	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3393
3394	SVMEVENT Event;
3395	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3396
3397	uint8_t uVector = Event.n.u8Vector;
3398	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3399
3400	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3401
3402	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3403	AssertRC(rc);
3404
3405	if (Event.n.u1ErrorCodeValid)
3406	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3407
3408	if ( enmTrapType == TRPM_TRAP
3409	&& uVector == X86_XCPT_PF)
3410	{
3411	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3412	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3413	}
3414	else if (enmTrapType == TRPM_SOFTWARE_INT)
3415	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3416	pVCpu->hm.s.Event.fPending = false;
3417	}
3418
3419
3420	/**
3421	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3422	* now.
3423	*
3424	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3425	* @param pVCpu The cross context virtual CPU structure.
3426	*
3427	* @remarks No-long-jump zone!!!
3428	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3429	*/
3430	static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
3431	{
3432	/*
3433	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3434	* completes. Check if we should inhibit interrupts or clear any existing
3435	* interrupt inhibition.
3436	*/
3437	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3438	{
3439	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3440	{
3441	/*
3442	* We can clear the inhibit force flag as even if we go back to the recompiler
3443	* without executing guest code in AMD-V, the flag's condition to be cleared is
3444	* met and thus the cleared state is correct.
3445	*/
3446	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3447	return false;
3448	}
3449	return true;
3450	}
3451	return false;
3452	}
3453
3454
3455	/**
3456	* Sets the virtual interrupt intercept control in the VMCB.
3457	*
3458	* @param pVCpu The cross context virtual CPU structure.
3459	* @param pVmcb Pointer to the VM control block.
3460	*/
3461	static void hmR0SvmSetIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3462	{
3463	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3464
3465	/*
3466	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3467	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3468	* (updating ISR at the right time) and inject the interrupt.
3469	*
3470	* With AVIC is supported, we could make use of the asynchronously delivery without
3471	* #VMEXIT and we would be passing the AVIC page to SVM.
3472	*
3473	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3474	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3475	*/
3476	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3477	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3478	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3479	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3480	Log4(("Set VINTR intercept\n"));
3481	}
3482
3483
3484	/**
3485	* Clears the virtual interrupt intercept control in the VMCB as
3486	* we are figured the guest is unable process any interrupts
3487	* at this point of time.
3488	*
3489	* @param pVCpu The cross context virtual CPU structure.
3490	* @param pVmcb Pointer to the VM control block.
3491	*/
3492	static void hmR0SvmClearIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3493	{
3494	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3495
3496	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3497	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3498	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3499	{
3500	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3501	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3502	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3503	Log4(("Cleared VINTR intercept\n"));
3504	}
3505	}
3506
3507
3508	/**
3509	* Evaluates the event to be delivered to the guest and sets it as the pending
3510	* event.
3511	*
3512	* @returns Strict VBox status code.
3513	* @param pVCpu The cross context virtual CPU structure.
3514	* @param pSvmTransient Pointer to the SVM transient structure.
3515	*/
3516	static VBOXSTRICTRC hmR0SvmEvaluatePendingEvent(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
3517	{
3518	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3519	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3520	\| CPUMCTX_EXTRN_RFLAGS
3521	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3522	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3523
3524	Assert(!pVCpu->hm.s.Event.fPending);
3525	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3526	Assert(pVmcb);
3527
3528	bool const fGif = CPUMGetGuestGif(pCtx);
3529	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3530	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3531
3532	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3533	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3534	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3535
3536	/** @todo SMI. SMIs take priority over NMIs. */
3537
3538	/*
3539	* Check if the guest or nested-guest can receive NMIs.
3540	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3541	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3542	*/
3543	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3544	&& !fBlockNmi)
3545	{
3546	if ( fGif
3547	&& !fIntShadow)
3548	{
3549	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3550	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3551	{
3552	Log4(("Intercepting NMI -> #VMEXIT\n"));
3553	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3554	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3555	}
3556	#endif
3557	Log4(("Setting NMI pending for injection\n"));
3558	SVMEVENT Event;
3559	Event.u = 0;
3560	Event.n.u1Valid = 1;
3561	Event.n.u8Vector = X86_XCPT_NMI;
3562	Event.n.u3Type = SVM_EVENT_NMI;
3563	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3564	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3565	}
3566	else if (!fGif)
3567	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3568	else if (!pSvmTransient->fIsNestedGuest)
3569	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3570	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3571	}
3572	/*
3573	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3574	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3575	* it from the APIC device.
3576	*
3577	* For nested-guests, physical interrupts always take priority over virtual interrupts.
3578	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3579	* do that work when we execute nested-guest code esp. since all the required information
3580	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3581	* the virtual interrupt controller.
3582	*
3583	* See AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3584	*/
3585	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3586	&& !pVCpu->hm.s.fSingleInstruction)
3587	{
3588	bool const fBlockInt = !pSvmTransient->fIsNestedGuest ? !(pCtx->eflags.u32 & X86_EFL_IF)
3589	: CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx);
3590	if ( fGif
3591	&& !fBlockInt
3592	&& !fIntShadow)
3593	{
3594	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3595	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3596	{
3597	Log4(("Intercepting INTR -> #VMEXIT\n"));
3598	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3599	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3600	}
3601	#endif
3602	uint8_t u8Interrupt;
3603	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3604	if (RT_SUCCESS(rc))
3605	{
3606	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3607	SVMEVENT Event;
3608	Event.u = 0;
3609	Event.n.u1Valid = 1;
3610	Event.n.u8Vector = u8Interrupt;
3611	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3612	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3613	}
3614	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3615	{
3616	/*
3617	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3618	* updated eventually when the TPR is written by the guest.
3619	*/
3620	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3621	}
3622	else
3623	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3624	}
3625	else if (!fGif)
3626	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3627	else if (!pSvmTransient->fIsNestedGuest)
3628	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3629	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3630	}
3631
3632	return VINF_SUCCESS;
3633	}
3634
3635
3636	/**
3637	* Injects any pending events into the guest (or nested-guest).
3638	*
3639	* @param pVCpu The cross context virtual CPU structure.
3640	* @param pVmcb Pointer to the VM control block.
3641	*
3642	* @remarks Must only be called when we are guaranteed to enter
3643	* hardware-assisted SVM execution and not return to ring-3
3644	* prematurely.
3645	*/
3646	static void hmR0SvmInjectPendingEvent(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3647	{
3648	Assert(!TRPMHasTrap(pVCpu));
3649	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3650
3651	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3652	#ifdef VBOX_STRICT
3653	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3654	bool const fGif = CPUMGetGuestGif(pCtx);
3655	bool fAllowInt = fGif;
3656	if (fGif)
3657	{
3658	/*
3659	* For nested-guests we have no way to determine if we're injecting a physical or
3660	* virtual interrupt at this point. Hence the partial verification below.
3661	*/
3662	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3663	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3664	else
3665	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3666	}
3667	#endif
3668
3669	if (pVCpu->hm.s.Event.fPending)
3670	{
3671	SVMEVENT Event;
3672	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3673	Assert(Event.n.u1Valid);
3674
3675	/*
3676	* Validate event injection pre-conditions.
3677	*/
3678	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3679	{
3680	Assert(fAllowInt);
3681	Assert(!fIntShadow);
3682	}
3683	else if (Event.n.u3Type == SVM_EVENT_NMI)
3684	{
3685	Assert(fGif);
3686	Assert(!fIntShadow);
3687	}
3688
3689	/*
3690	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3691	* do this only when we are surely going to inject the NMI as otherwise if we return
3692	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3693	* SVM R0.
3694	*
3695	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3696	* which will set the VMCS field after actually delivering the NMI which we read on
3697	* VM-exit to determine the state.
3698	*/
3699	if ( Event.n.u3Type == SVM_EVENT_NMI
3700	&& Event.n.u8Vector == X86_XCPT_NMI
3701	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3702	{
3703	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3704	}
3705
3706	/*
3707	* Inject it (update VMCB for injection by the hardware).
3708	*/
3709	Log4(("Injecting pending HM event\n"));
3710	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
3711	pVCpu->hm.s.Event.fPending = false;
3712
3713	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3714	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3715	else
3716	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3717	}
3718	else
3719	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3720
3721	/*
3722	* We could have injected an NMI through IEM and continue guest execution using
3723	* hardware-assisted SVM. In which case, we would not have any events pending (above)
3724	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
3725	*/
3726	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3727	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
3728
3729	/*
3730	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3731	*
3732	* For nested-guests: We need to update it too for the scenario where IEM executes
3733	* the nested-guest but execution later continues here with an interrupt shadow active.
3734	*/
3735	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3736	}
3737
3738
3739	/**
3740	* Reports world-switch error and dumps some useful debug info.
3741	*
3742	* @param pVCpu The cross context virtual CPU structure.
3743	* @param rcVMRun The return code from VMRUN (or
3744	* VERR_SVM_INVALID_GUEST_STATE for invalid
3745	* guest-state).
3746	*/
3747	static void hmR0SvmReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun)
3748	{
3749	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3750	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
3751	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3752
3753	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3754	{
3755	#ifdef VBOX_STRICT
3756	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
3757	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3758	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3759	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3760	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3761	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3762	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3763	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3764	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3765	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3766	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3767	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3768
3769	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3770	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3771	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3772
3773	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3774	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3775	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3776	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3777	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3778	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3779	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3780	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3781	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3782	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3783	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3784	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3785
3786	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3787	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3788	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3789	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3790	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3791	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3792	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3793	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3794	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3795	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3796	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3797	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3798	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3799	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3800	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3801	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3802	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3803	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3804	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3805	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3806
3807	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3808
3809	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3810	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3811
3812	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3813	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3814	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3815	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3816	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3817	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3818	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3819	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3820	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3821	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3822	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3823	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3824	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3825	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3826	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3827	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3828	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3829	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3830	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3831	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3832
3833	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3834	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3835
3836	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3837	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3838	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3839	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3840
3841	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3842	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3843
3844	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3845	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3846	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3847	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3848
3849	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3850	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3851	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3852	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3853	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3854	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3855	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3856
3857	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3858	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3859	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3860	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3861
3862	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3863	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3864	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3865
3866	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3867	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3868	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3869	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3870	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3871	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3872	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
3873	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3874	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3875	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3876	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3877	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3878
3879	NOREF(pVmcb);
3880	#endif /* VBOX_STRICT */
3881	}
3882	else
3883	Log4Func(("rcVMRun=%d\n", rcVMRun));
3884	}
3885
3886
3887	/**
3888	* Check per-VM and per-VCPU force flag actions that require us to go back to
3889	* ring-3 for one reason or another.
3890	*
3891	* @returns VBox status code (information status code included).
3892	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3893	* ring-3.
3894	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3895	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3896	* interrupts)
3897	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3898	* all EMTs to be in ring-3.
3899	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3900	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3901	* to the EM loop.
3902	*
3903	* @param pVCpu The cross context virtual CPU structure.
3904	*/
3905	static int hmR0SvmCheckForceFlags(PVMCPUCC pVCpu)
3906	{
3907	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3908	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3909
3910	/* Could happen as a result of longjump. */
3911	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3912	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
3913
3914	/* Update pending interrupts into the APIC's IRR. */
3915	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3916	APICUpdatePendingInterrupts(pVCpu);
3917
3918	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3919	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
3920	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3921	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
3922	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3923	{
3924	/* Pending PGM C3 sync. */
3925	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3926	{
3927	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
3928	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3929	if (rc != VINF_SUCCESS)
3930	{
3931	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3932	return rc;
3933	}
3934	}
3935
3936	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3937	/* -XXX- what was that about single stepping? */
3938	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
3939	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3940	{
3941	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3942	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
3943	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3944	return rc;
3945	}
3946
3947	/* Pending VM request packets, such as hardware interrupts. */
3948	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
3949	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
3950	{
3951	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
3952	Log4Func(("Pending VM request forcing us back to ring-3\n"));
3953	return VINF_EM_PENDING_REQUEST;
3954	}
3955
3956	/* Pending PGM pool flushes. */
3957	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3958	{
3959	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
3960	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
3961	return VINF_PGM_POOL_FLUSH_PENDING;
3962	}
3963
3964	/* Pending DMA requests. */
3965	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
3966	{
3967	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
3968	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
3969	return VINF_EM_RAW_TO_R3;
3970	}
3971	}
3972
3973	return VINF_SUCCESS;
3974	}
3975
3976
3977	/**
3978	* Does the preparations before executing guest code in AMD-V.
3979	*
3980	* This may cause longjmps to ring-3 and may even result in rescheduling to the
3981	* recompiler. We must be cautious what we do here regarding committing
3982	* guest-state information into the VMCB assuming we assuredly execute the guest
3983	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
3984	* clearing the common-state (TRPM/forceflags), we must undo those changes so
3985	* that the recompiler can (and should) use them when it resumes guest
3986	* execution. Otherwise such operations must be done when we can no longer
3987	* exit to ring-3.
3988	*
3989	* @returns VBox status code (informational status codes included).
3990	* @retval VINF_SUCCESS if we can proceed with running the guest.
3991	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3992	*
3993	* @param pVCpu The cross context virtual CPU structure.
3994	* @param pSvmTransient Pointer to the SVM transient structure.
3995	*/
3996	static int hmR0SvmPreRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
3997	{
3998	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3999
4000	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4001	if (pSvmTransient->fIsNestedGuest)
4002	{
4003	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4004	return VINF_EM_RESCHEDULE_REM;
4005	}
4006	#endif
4007
4008	/* Check force flag actions that might require us to go back to ring-3. */
4009	int rc = hmR0SvmCheckForceFlags(pVCpu);
4010	if (rc != VINF_SUCCESS)
4011	return rc;
4012
4013	if (TRPMHasTrap(pVCpu))
4014	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4015	else if (!pVCpu->hm.s.Event.fPending)
4016	{
4017	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEvent(pVCpu, pSvmTransient);
4018	if ( rcStrict != VINF_SUCCESS
4019	\|\| pSvmTransient->fIsNestedGuest != CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4020	{
4021	/* If a nested-guest VM-exit occurred, bail. */
4022	if (pSvmTransient->fIsNestedGuest)
4023	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4024	return VBOXSTRICTRC_VAL(rcStrict);
4025	}
4026	}
4027
4028	/*
4029	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4030	* Just do it in software, see @bugref{8411}.
4031	* NB: If we could continue a task switch exit we wouldn't need to do this.
4032	*/
4033	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4034	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4035	&& pVCpu->hm.s.Event.fPending
4036	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4037	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4038
4039	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4040	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4041	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4042	#endif
4043
4044	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4045	/*
4046	* Set up the nested-guest VMCB for execution using hardware-assisted SVM.
4047	*/
4048	if (pSvmTransient->fIsNestedGuest)
4049	hmR0SvmSetupVmcbNested(pVCpu);
4050	#endif
4051
4052	/*
4053	* Export the guest state bits that are not shared with the host in any way as we can
4054	* longjmp or get preempted in the midst of exporting some of the state.
4055	*/
4056	rc = hmR0SvmExportGuestState(pVCpu, pSvmTransient);
4057	AssertRCReturn(rc, rc);
4058	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4059
4060	/* Ensure we've cached (and hopefully modified) the nested-guest VMCB for execution using hardware-assisted SVM. */
4061	Assert(!pSvmTransient->fIsNestedGuest \|\| pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4062
4063	/*
4064	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4065	* world-switch so we can update it on the way back if the guest changed the TPR.
4066	*/
4067	if (pVCpu->hm.s.svm.fSyncVTpr)
4068	{
4069	Assert(!pSvmTransient->fIsNestedGuest);
4070	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4071	if (pVM->hm.s.fTPRPatchingActive)
4072	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4073	else
4074	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4075	}
4076
4077	/*
4078	* No longjmps to ring-3 from this point on!!!
4079	*
4080	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4081	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4082	*/
4083	VMMRZCallRing3Disable(pVCpu);
4084
4085	/*
4086	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4087	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4088	* preemption disabled for a while. Since this is purly to aid the
4089	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4090	* disable interrupt on NT.
4091	*
4092	* We need to check for force-flags that could've possible been altered since we last
4093	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4094	* see @bugref{6398}).
4095	*
4096	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4097	* to ring-3 before executing guest code.
4098	*/
4099	pSvmTransient->fEFlags = ASMIntDisableFlags();
4100	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4101	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4102	{
4103	ASMSetFlags(pSvmTransient->fEFlags);
4104	VMMRZCallRing3Enable(pVCpu);
4105	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4106	return VINF_EM_RAW_TO_R3;
4107	}
4108	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4109	{
4110	ASMSetFlags(pSvmTransient->fEFlags);
4111	VMMRZCallRing3Enable(pVCpu);
4112	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4113	return VINF_EM_RAW_INTERRUPT;
4114	}
4115
4116	return VINF_SUCCESS;
4117	}
4118
4119
4120	/**
4121	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4122	* doing so.
4123	*
4124	* This means there is no backing out to ring-3 or anywhere else at this point.
4125	*
4126	* @param pVCpu The cross context virtual CPU structure.
4127	* @param pSvmTransient Pointer to the SVM transient structure.
4128	*
4129	* @remarks Called with preemption disabled.
4130	* @remarks No-long-jump zone!!!
4131	*/
4132	static void hmR0SvmPreRunGuestCommitted(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4133	{
4134	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4135	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4136	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4137
4138	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4139	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4140
4141	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4142	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4143
4144	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4145
4146	if (!CPUMIsGuestFPUStateActive(pVCpu))
4147	{
4148	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4149	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4150	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4151	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4152	}
4153
4154	/* Load the state shared between host and guest (FPU, debug). */
4155	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4156	hmR0SvmExportSharedState(pVCpu, pVmcb);
4157
4158	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4159	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4160
4161	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4162	RTCPUID const idHostCpu = pHostCpu->idCpu;
4163	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4164
4165	/* Setup TSC offsetting. */
4166	if ( pSvmTransient->fUpdateTscOffsetting
4167	\|\| fMigratedHostCpu)
4168	{
4169	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4170	pSvmTransient->fUpdateTscOffsetting = false;
4171	}
4172
4173	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
4174	if (!(pVmcb->ctrl.u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
4175	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4176	else
4177	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4178
4179	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4180	if (fMigratedHostCpu)
4181	pVmcb->ctrl.u32VmcbCleanBits = 0;
4182
4183	/* Store status of the shared guest-host state at the time of VMRUN. */
4184	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4185	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4186
4187	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4188	uint8_t *pbMsrBitmap;
4189	if (!pSvmTransient->fIsNestedGuest)
4190	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4191	else
4192	{
4193	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4194
4195	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4196	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4197	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4198	}
4199	#else
4200	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4201	#endif
4202
4203	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4204	/* Flush the appropriate tagged-TLB entries. */
4205	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4206	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4207
4208	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4209
4210	TMNotifyStartOfExecution(pVM, pVCpu); /* Finally, notify TM to resume its clocks as we're about
4211	to start executing. */
4212
4213	/*
4214	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4215	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4216	*
4217	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4218	*/
4219	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4220	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4221	{
4222	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4223	pVCpu->hm.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4224	if (uGuestTscAux != pVCpu->hm.s.svm.u64HostTscAux)
4225	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4226	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4227	pSvmTransient->fRestoreTscAuxMsr = true;
4228	}
4229	else
4230	{
4231	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4232	pSvmTransient->fRestoreTscAuxMsr = false;
4233	}
4234	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4235
4236	/*
4237	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4238	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4239	* from the VMCB.
4240	*/
4241	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pSvmTransient->fIsNestedGuest);
4242	if (!fSupportsVmcbCleanBits)
4243	pVmcb->ctrl.u32VmcbCleanBits = 0;
4244	}
4245
4246
4247	/**
4248	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4249	*
4250	* @returns VBox strict status code.
4251	* @param pVCpu The cross context virtual CPU structure.
4252	* @param HCPhysVmcb The host physical address of the VMCB.
4253	*
4254	* @remarks No-long-jump zone!!!
4255	*/
4256	DECLINLINE(int) hmR0SvmRunGuest(PVMCPUCC pVCpu, RTHCPHYS HCPhysVmcb)
4257	{
4258	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4259	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4260	pCtx->fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4261
4262	/*
4263	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4264	* floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4265	* callee-saved and thus the need for this XMM wrapper.
4266	*
4267	* Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4268	*/
4269	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4270	#ifdef VBOX_WITH_KERNEL_USING_XMM
4271	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu, pVCpu->hm.s.svm.pfnVMRun);
4272	#else
4273	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu);
4274	#endif
4275	}
4276
4277
4278	/**
4279	* Performs some essential restoration of state after running guest (or
4280	* nested-guest) code in AMD-V.
4281	*
4282	* @param pVCpu The cross context virtual CPU structure.
4283	* @param pSvmTransient Pointer to the SVM transient structure.
4284	* @param rcVMRun Return code of VMRUN.
4285	*
4286	* @remarks Called with interrupts disabled.
4287	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4288	* unconditionally when it is safe to do so.
4289	*/
4290	static void hmR0SvmPostRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4291	{
4292	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4293
4294	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4295	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4296	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4297
4298	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4299	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4300
4301	/* TSC read must be done early for maximum accuracy. */
4302	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4303	{
4304	if (!pSvmTransient->fIsNestedGuest)
4305	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4306	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4307	else
4308	{
4309	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4310	uint64_t const uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4311	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4312	}
4313	#endif
4314	}
4315
4316	if (pSvmTransient->fRestoreTscAuxMsr)
4317	{
4318	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4319	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4320	if (u64GuestTscAuxMsr != pVCpu->hm.s.svm.u64HostTscAux)
4321	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.svm.u64HostTscAux);
4322	}
4323
4324	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4325	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4326	TMNotifyEndOfExecution(pVM, pVCpu); /* Notify TM that the guest is no longer running. */
4327	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4328
4329	Assert(!(ASMGetFlags() & X86_EFL_IF));
4330	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4331	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4332
4333	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4334	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4335	{
4336	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4337	return;
4338	}
4339
4340	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4341	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4342	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4343	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4344
4345	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4346	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4347	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4348	#else
4349	/*
4350	* Always import the following:
4351	*
4352	* - RIP for exit optimizations and evaluating event injection on re-entry.
4353	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4354	* state on preemption.
4355	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4356	* - CS for exit optimizations.
4357	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4358	* assembly switcher code.
4359	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4360	*/
4361	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4362	\| CPUMCTX_EXTRN_RFLAGS
4363	\| CPUMCTX_EXTRN_RAX
4364	\| CPUMCTX_EXTRN_RSP
4365	\| CPUMCTX_EXTRN_CS
4366	\| CPUMCTX_EXTRN_HWVIRT
4367	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4368	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4369	\| HMSVM_CPUMCTX_SHARED_STATE);
4370	#endif
4371
4372	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4373	&& pVCpu->hm.s.svm.fSyncVTpr)
4374	{
4375	Assert(!pSvmTransient->fIsNestedGuest);
4376	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4377	if ( pVM->hm.s.fTPRPatchingActive
4378	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4379	{
4380	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4381	AssertRC(rc);
4382	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4383	}
4384	/* Sync TPR when we aren't intercepting CR8 writes. */
4385	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4386	{
4387	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4388	AssertRC(rc);
4389	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4390	}
4391	}
4392
4393	#ifdef DEBUG_ramshankar
4394	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4395	{
4396	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4397	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4398	0 /* uVerbose */);
4399	}
4400	#endif
4401
4402	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4403	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4404	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, uHostTsc);
4405	}
4406
4407
4408	/**
4409	* Runs the guest code using AMD-V.
4410	*
4411	* @returns VBox status code.
4412	* @param pVCpu The cross context virtual CPU structure.
4413	* @param pcLoops Pointer to the number of executed loops.
4414	*/
4415	static int hmR0SvmRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
4416	{
4417	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4418	Assert(pcLoops);
4419	Assert(*pcLoops <= cMaxResumeLoops);
4420
4421	SVMTRANSIENT SvmTransient;
4422	RT_ZERO(SvmTransient);
4423	SvmTransient.fUpdateTscOffsetting = true;
4424	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4425
4426	int rc = VERR_INTERNAL_ERROR_5;
4427	for (;;)
4428	{
4429	Assert(!HMR0SuspendPending());
4430	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4431
4432	/* Preparatory work for running nested-guest code, this may force us to return to
4433	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4434	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4435	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4436	if (rc != VINF_SUCCESS)
4437	break;
4438
4439	/*
4440	* No longjmps to ring-3 from this point on!!!
4441	*
4442	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4443	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4444	*/
4445	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4446	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4447
4448	/* Restore any residual host-state and save any bits shared between host and guest
4449	into the guest-CPU state. Re-enables interrupts! */
4450	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4451
4452	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4453	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4454	{
4455	if (rc == VINF_SUCCESS)
4456	rc = VERR_SVM_INVALID_GUEST_STATE;
4457	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4458	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4459	break;
4460	}
4461
4462	/* Handle the #VMEXIT. */
4463	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4464	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4465	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4466	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4467	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4468	if (rc != VINF_SUCCESS)
4469	break;
4470	if (++(*pcLoops) >= cMaxResumeLoops)
4471	{
4472	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4473	rc = VINF_EM_RAW_INTERRUPT;
4474	break;
4475	}
4476	}
4477
4478	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4479	return rc;
4480	}
4481
4482
4483	/**
4484	* Runs the guest code using AMD-V in single step mode.
4485	*
4486	* @returns VBox status code.
4487	* @param pVCpu The cross context virtual CPU structure.
4488	* @param pcLoops Pointer to the number of executed loops.
4489	*/
4490	static int hmR0SvmRunGuestCodeStep(PVMCPUCC pVCpu, uint32_t *pcLoops)
4491	{
4492	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4493	Assert(pcLoops);
4494	Assert(*pcLoops <= cMaxResumeLoops);
4495
4496	SVMTRANSIENT SvmTransient;
4497	RT_ZERO(SvmTransient);
4498	SvmTransient.fUpdateTscOffsetting = true;
4499	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4500
4501	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4502	uint16_t uCsStart = pCtx->cs.Sel;
4503	uint64_t uRipStart = pCtx->rip;
4504
4505	int rc = VERR_INTERNAL_ERROR_5;
4506	for (;;)
4507	{
4508	Assert(!HMR0SuspendPending());
4509	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4510	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4511	(unsigned)RTMpCpuId(), *pcLoops));
4512
4513	/* Preparatory work for running nested-guest code, this may force us to return to
4514	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4515	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4516	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4517	if (rc != VINF_SUCCESS)
4518	break;
4519
4520	/*
4521	* No longjmps to ring-3 from this point on!!!
4522	*
4523	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4524	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4525	*/
4526	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4527
4528	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4529
4530	/* Restore any residual host-state and save any bits shared between host and guest
4531	into the guest-CPU state. Re-enables interrupts! */
4532	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4533
4534	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4535	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4536	{
4537	if (rc == VINF_SUCCESS)
4538	rc = VERR_SVM_INVALID_GUEST_STATE;
4539	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4540	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4541	return rc;
4542	}
4543
4544	/* Handle the #VMEXIT. */
4545	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4546	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4547	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4548	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4549	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4550	if (rc != VINF_SUCCESS)
4551	break;
4552	if (++(*pcLoops) >= cMaxResumeLoops)
4553	{
4554	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4555	rc = VINF_EM_RAW_INTERRUPT;
4556	break;
4557	}
4558
4559	/*
4560	* Did the RIP change, if so, consider it a single step.
4561	* Otherwise, make sure one of the TFs gets set.
4562	*/
4563	if ( pCtx->rip != uRipStart
4564	\|\| pCtx->cs.Sel != uCsStart)
4565	{
4566	rc = VINF_EM_DBG_STEPPED;
4567	break;
4568	}
4569	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4570	}
4571
4572	/*
4573	* Clear the X86_EFL_TF if necessary.
4574	*/
4575	if (pVCpu->hm.s.fClearTrapFlag)
4576	{
4577	pVCpu->hm.s.fClearTrapFlag = false;
4578	pCtx->eflags.Bits.u1TF = 0;
4579	}
4580
4581	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4582	return rc;
4583	}
4584
4585	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4586	/**
4587	* Runs the nested-guest code using AMD-V.
4588	*
4589	* @returns VBox status code.
4590	* @param pVCpu The cross context virtual CPU structure.
4591	* @param pcLoops Pointer to the number of executed loops. If we're switching
4592	* from the guest-code execution loop to this nested-guest
4593	* execution loop pass the remainder value, else pass 0.
4594	*/
4595	static int hmR0SvmRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
4596	{
4597	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4598	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4599	Assert(pcLoops);
4600	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops);
4601
4602	SVMTRANSIENT SvmTransient;
4603	RT_ZERO(SvmTransient);
4604	SvmTransient.fUpdateTscOffsetting = true;
4605	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4606	SvmTransient.fIsNestedGuest = true;
4607
4608	int rc = VERR_INTERNAL_ERROR_4;
4609	for (;;)
4610	{
4611	Assert(!HMR0SuspendPending());
4612	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4613
4614	/* Preparatory work for running nested-guest code, this may force us to return to
4615	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4616	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4617	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4618	if ( rc != VINF_SUCCESS
4619	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4620	break;
4621
4622	/*
4623	* No longjmps to ring-3 from this point on!!!
4624	*
4625	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4626	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4627	*/
4628	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4629
4630	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
4631
4632	/* Restore any residual host-state and save any bits shared between host and guest
4633	into the guest-CPU state. Re-enables interrupts! */
4634	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4635
4636	if (RT_LIKELY( rc == VINF_SUCCESS
4637	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4638	{ /* extremely likely */ }
4639	else
4640	{
4641	/* VMRUN failed, shouldn't really happen, Guru. */
4642	if (rc != VINF_SUCCESS)
4643	break;
4644
4645	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4646	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4647	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4648	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4649	break;
4650	}
4651
4652	/* Handle the #VMEXIT. */
4653	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4654	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4655	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4656	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
4657	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4658	if (rc == VINF_SUCCESS)
4659	{
4660	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4661	{
4662	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4663	rc = VINF_SVM_VMEXIT;
4664	}
4665	else
4666	{
4667	if (++(*pcLoops) <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
4668	continue;
4669	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4670	rc = VINF_EM_RAW_INTERRUPT;
4671	}
4672	}
4673	else
4674	Assert(rc != VINF_SVM_VMEXIT);
4675	break;
4676	/** @todo NSTSVM: handle single-stepping. */
4677	}
4678
4679	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4680	return rc;
4681	}
4682	#endif
4683
4684
4685	/**
4686	* Runs the guest code using AMD-V.
4687	*
4688	* @returns Strict VBox status code.
4689	* @param pVCpu The cross context virtual CPU structure.
4690	*/
4691	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPUCC pVCpu)
4692	{
4693	AssertPtr(pVCpu);
4694	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4695	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4696	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4697	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4698
4699	uint32_t cLoops = 0;
4700	int rc;
4701	for (;;)
4702	{
4703	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4704	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
4705	#else
4706	NOREF(pCtx);
4707	bool const fInNestedGuestMode = false;
4708	#endif
4709	if (!fInNestedGuestMode)
4710	{
4711	if (!pVCpu->hm.s.fSingleInstruction)
4712	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
4713	else
4714	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
4715	}
4716	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4717	else
4718	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
4719
4720	if (rc == VINF_SVM_VMRUN)
4721	{
4722	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4723	continue;
4724	}
4725	if (rc == VINF_SVM_VMEXIT)
4726	{
4727	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4728	continue;
4729	}
4730	#endif
4731	break;
4732	}
4733
4734	/* Fixup error codes. */
4735	if (rc == VERR_EM_INTERPRETER)
4736	rc = VINF_EM_RAW_EMULATE_INSTR;
4737	else if (rc == VINF_EM_RESET)
4738	rc = VINF_EM_TRIPLE_FAULT;
4739
4740	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4741	rc = hmR0SvmExitToRing3(pVCpu, rc);
4742	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4743	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4744	return rc;
4745	}
4746
4747
4748	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4749	/**
4750	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
4751	*
4752	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4753	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4754	*/
4755	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4756	{
4757	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4758	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4759	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4760	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4761	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
4762	const bool fRep = pIoExitInfo->n.u1Rep;
4763	const bool fStrIo = pIoExitInfo->n.u1Str;
4764
4765	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4766	NULL /* pIoExitInfo */);
4767	}
4768
4769
4770	/**
4771	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4772	* SVM_EXIT_INVALID).
4773	*
4774	* @returns VBox status code (informational status codes included).
4775	* @param pVCpu The cross context virtual CPU structure.
4776	* @param pSvmTransient Pointer to the SVM transient structure.
4777	*/
4778	static int hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4779	{
4780	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4781	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4782	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4783
4784	/*
4785	* We import the complete state here because we use separate VMCBs for the guest and the
4786	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
4787	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
4788	*/
4789	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4790	do { \
4791	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
4792	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2))); \
4793	} while (0)
4794
4795	/*
4796	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
4797	* nested-guest. If it isn't, it should be handled by the (outer) guest.
4798	*/
4799	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
4800	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4801	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4802	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4803	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4804	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4805
4806	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4807	switch (uExitCode)
4808	{
4809	case SVM_EXIT_CPUID:
4810	{
4811	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4812	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4813	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
4814	}
4815
4816	case SVM_EXIT_RDTSC:
4817	{
4818	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4819	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4820	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
4821	}
4822
4823	case SVM_EXIT_RDTSCP:
4824	{
4825	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4826	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4827	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
4828	}
4829
4830	case SVM_EXIT_MONITOR:
4831	{
4832	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4833	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4834	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
4835	}
4836
4837	case SVM_EXIT_MWAIT:
4838	{
4839	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4840	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4841	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
4842	}
4843
4844	case SVM_EXIT_HLT:
4845	{
4846	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4847	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4848	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
4849	}
4850
4851	case SVM_EXIT_MSR:
4852	{
4853	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4854	{
4855	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
4856	uint16_t offMsrpm;
4857	uint8_t uMsrpmBit;
4858	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4859	if (RT_SUCCESS(rc))
4860	{
4861	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
4862	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
4863
4864	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4865	pbMsrBitmap += offMsrpm;
4866	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
4867	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
4868
4869	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4870	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4871	{
4872	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4873	}
4874	}
4875	else
4876	{
4877	/*
4878	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4879	* See AMD-V spec. "15.11 MSR Intercepts".
4880	*/
4881	Assert(rc == VERR_OUT_OF_RANGE);
4882	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4883	}
4884	}
4885	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
4886	}
4887
4888	case SVM_EXIT_IOIO:
4889	{
4890	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4891	{
4892	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
4893	SVMIOIOEXITINFO IoExitInfo;
4894	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4895	bool const fIntercept = hmR0SvmIsIoInterceptSet(pvIoBitmap, &IoExitInfo);
4896	if (fIntercept)
4897	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4898	}
4899	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
4900	}
4901
4902	case SVM_EXIT_XCPT_PF:
4903	{
4904	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4905	if (pVM->hm.s.fNestedPaging)
4906	{
4907	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4908	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4909
4910	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4911	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4912	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4913
4914	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
4915	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
4916	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
4917	return VINF_SUCCESS;
4918	}
4919	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
4920	}
4921
4922	case SVM_EXIT_XCPT_UD:
4923	{
4924	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
4925	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4926	hmR0SvmSetPendingXcptUD(pVCpu);
4927	return VINF_SUCCESS;
4928	}
4929
4930	case SVM_EXIT_XCPT_MF:
4931	{
4932	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
4933	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4934	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
4935	}
4936
4937	case SVM_EXIT_XCPT_DB:
4938	{
4939	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
4940	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4941	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
4942	}
4943
4944	case SVM_EXIT_XCPT_AC:
4945	{
4946	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
4947	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4948	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
4949	}
4950
4951	case SVM_EXIT_XCPT_BP:
4952	{
4953	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
4954	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4955	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
4956	}
4957
4958	case SVM_EXIT_READ_CR0:
4959	case SVM_EXIT_READ_CR3:
4960	case SVM_EXIT_READ_CR4:
4961	{
4962	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
4963	if (CPUMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
4964	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4965	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
4966	}
4967
4968	case SVM_EXIT_CR0_SEL_WRITE:
4969	{
4970	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
4971	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4972	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
4973	}
4974
4975	case SVM_EXIT_WRITE_CR0:
4976	case SVM_EXIT_WRITE_CR3:
4977	case SVM_EXIT_WRITE_CR4:
4978	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
4979	{
4980	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
4981	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
4982
4983	if (CPUMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
4984	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4985	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
4986	}
4987
4988	case SVM_EXIT_PAUSE:
4989	{
4990	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
4991	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4992	return hmR0SvmExitPause(pVCpu, pSvmTransient);
4993	}
4994
4995	case SVM_EXIT_VINTR:
4996	{
4997	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
4998	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4999	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5000	}
5001
5002	case SVM_EXIT_INTR:
5003	case SVM_EXIT_NMI:
5004	case SVM_EXIT_SMI:
5005	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5006	{
5007	/*
5008	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5009	*
5010	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5011	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5012	* nested-guest #VMEXIT.
5013	*
5014	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5015	* while trying to inject interrupts, see comment at the top of this function.
5016	*/
5017	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5018	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5019	}
5020
5021	case SVM_EXIT_FERR_FREEZE:
5022	{
5023	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5024	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5025	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5026	}
5027
5028	case SVM_EXIT_INVLPG:
5029	{
5030	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5031	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5032	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5033	}
5034
5035	case SVM_EXIT_WBINVD:
5036	{
5037	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5038	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5039	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5040	}
5041
5042	case SVM_EXIT_INVD:
5043	{
5044	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5045	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5046	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5047	}
5048
5049	case SVM_EXIT_RDPMC:
5050	{
5051	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5052	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5053	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5054	}
5055
5056	default:
5057	{
5058	switch (uExitCode)
5059	{
5060	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5061	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5062	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5063	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5064	{
5065	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5066	if (CPUMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5067	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5068	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5069	}
5070
5071	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5072	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5073	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5074	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5075	{
5076	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5077	if (CPUMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5078	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5079	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5080	}
5081
5082	case SVM_EXIT_XCPT_DE:
5083	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5084	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5085	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5086	case SVM_EXIT_XCPT_OF:
5087	case SVM_EXIT_XCPT_BR:
5088	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5089	case SVM_EXIT_XCPT_NM:
5090	case SVM_EXIT_XCPT_DF:
5091	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5092	case SVM_EXIT_XCPT_TS:
5093	case SVM_EXIT_XCPT_NP:
5094	case SVM_EXIT_XCPT_SS:
5095	case SVM_EXIT_XCPT_GP:
5096	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5097	case SVM_EXIT_XCPT_15: /* Reserved. */
5098	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5099	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5100	case SVM_EXIT_XCPT_MC:
5101	case SVM_EXIT_XCPT_XF:
5102	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5103	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5104	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5105	{
5106	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5107	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5108	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5109	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5110	}
5111
5112	case SVM_EXIT_XSETBV:
5113	{
5114	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5115	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5116	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5117	}
5118
5119	case SVM_EXIT_TASK_SWITCH:
5120	{
5121	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5122	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5123	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5124	}
5125
5126	case SVM_EXIT_IRET:
5127	{
5128	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5129	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5130	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5131	}
5132
5133	case SVM_EXIT_SHUTDOWN:
5134	{
5135	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5136	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5137	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5138	}
5139
5140	case SVM_EXIT_VMMCALL:
5141	{
5142	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5143	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5144	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5145	}
5146
5147	case SVM_EXIT_CLGI:
5148	{
5149	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5150	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5151	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5152	}
5153
5154	case SVM_EXIT_STGI:
5155	{
5156	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5157	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5158	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5159	}
5160
5161	case SVM_EXIT_VMLOAD:
5162	{
5163	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5164	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5165	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5166	}
5167
5168	case SVM_EXIT_VMSAVE:
5169	{
5170	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5171	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5172	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5173	}
5174
5175	case SVM_EXIT_INVLPGA:
5176	{
5177	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5178	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5179	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5180	}
5181
5182	case SVM_EXIT_VMRUN:
5183	{
5184	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5185	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5186	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5187	}
5188
5189	case SVM_EXIT_RSM:
5190	{
5191	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5192	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5193	hmR0SvmSetPendingXcptUD(pVCpu);
5194	return VINF_SUCCESS;
5195	}
5196
5197	case SVM_EXIT_SKINIT:
5198	{
5199	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5200	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5201	hmR0SvmSetPendingXcptUD(pVCpu);
5202	return VINF_SUCCESS;
5203	}
5204
5205	case SVM_EXIT_NPF:
5206	{
5207	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5208	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5209	}
5210
5211	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5212	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5213
5214	default:
5215	{
5216	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5217	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5218	return VERR_SVM_UNKNOWN_EXIT;
5219	}
5220	}
5221	}
5222	}
5223	/* not reached */
5224
5225	#undef NST_GST_VMEXIT_CALL_RET
5226	}
5227	#endif
5228
5229
5230	/**
5231	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5232	*
5233	* @returns VBox status code (informational status codes included).
5234	* @param pVCpu The cross context virtual CPU structure.
5235	* @param pSvmTransient Pointer to the SVM transient structure.
5236	*/
5237	static int hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5238	{
5239	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5240	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5241
5242	#ifdef DEBUG_ramshankar
5243	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5244	do { \
5245	if ((a_fDbg) == 1) \
5246	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5247	int rc = a_CallExpr; \
5248	if ((a_fDbg) == 1) \
5249	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5250	return rc; \
5251	} while (0)
5252	#else
5253	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5254	#endif
5255
5256	/*
5257	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5258	* for most guests under normal workloads (for some definition of "normal").
5259	*/
5260	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5261	switch (uExitCode)
5262	{
5263	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5264	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5265	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5266	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5267	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5268	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5269	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5270	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5271	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5272	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5273
5274	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5275	case SVM_EXIT_INTR:
5276	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5277
5278	case SVM_EXIT_READ_CR0:
5279	case SVM_EXIT_READ_CR3:
5280	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5281
5282	case SVM_EXIT_CR0_SEL_WRITE:
5283	case SVM_EXIT_WRITE_CR0:
5284	case SVM_EXIT_WRITE_CR3:
5285	case SVM_EXIT_WRITE_CR4:
5286	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5287
5288	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5289	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5290	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5291	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5292	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5293	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5294	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5295	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5296	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5297	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5298	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5299	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5300	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5301	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5302	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5303	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5304
5305	default:
5306	{
5307	switch (pSvmTransient->u64ExitCode)
5308	{
5309	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5310	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5311	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5312	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5313	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5314
5315	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5316	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5317	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5318	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5319	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5320
5321	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5322	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5323
5324	case SVM_EXIT_SMI:
5325	case SVM_EXIT_INIT:
5326	{
5327	/*
5328	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5329	* If it ever does, we want to know about it so log the exit code and bail.
5330	*/
5331	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5332	}
5333
5334	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5335	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5336	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5337	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5338	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5339	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5340	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5341	#else
5342	case SVM_EXIT_CLGI:
5343	case SVM_EXIT_STGI:
5344	case SVM_EXIT_VMLOAD:
5345	case SVM_EXIT_VMSAVE:
5346	case SVM_EXIT_INVLPGA:
5347	case SVM_EXIT_VMRUN:
5348	#endif
5349	case SVM_EXIT_RSM:
5350	case SVM_EXIT_SKINIT:
5351	{
5352	hmR0SvmSetPendingXcptUD(pVCpu);
5353	return VINF_SUCCESS;
5354	}
5355
5356	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5357	case SVM_EXIT_XCPT_DE:
5358	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5359	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5360	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5361	case SVM_EXIT_XCPT_OF:
5362	case SVM_EXIT_XCPT_BR:
5363	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5364	case SVM_EXIT_XCPT_NM:
5365	case SVM_EXIT_XCPT_DF:
5366	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5367	case SVM_EXIT_XCPT_TS:
5368	case SVM_EXIT_XCPT_NP:
5369	case SVM_EXIT_XCPT_SS:
5370	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5371	/* SVM_EXIT_XCPT_PF: */
5372	case SVM_EXIT_XCPT_15: /* Reserved. */
5373	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5374	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5375	case SVM_EXIT_XCPT_MC:
5376	case SVM_EXIT_XCPT_XF:
5377	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5378	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5379	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5380	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5381	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5382
5383	default:
5384	{
5385	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5386	pVCpu->hm.s.u32HMError = uExitCode;
5387	return VERR_SVM_UNKNOWN_EXIT;
5388	}
5389	}
5390	}
5391	}
5392	/* not reached */
5393	#undef VMEXIT_CALL_RET
5394	}
5395
5396
5397	#ifdef VBOX_STRICT
5398	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5399	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5400	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5401
5402	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5403	do \
5404	{ \
5405	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5406	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5407	} while (0)
5408
5409	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5410	do { \
5411	AssertPtr((a_pVCpu)); \
5412	AssertPtr((a_pSvmTransient)); \
5413	Assert(ASMIntAreEnabled()); \
5414	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5415	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5416	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5417	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5418	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5419	HMSVM_ASSERT_PREEMPT_CPUID(); \
5420	} while (0)
5421	#else
5422	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5423	do { \
5424	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5425	} while (0)
5426	#endif
5427
5428
5429	/**
5430	* Gets the IEM exception flags for the specified SVM event.
5431	*
5432	* @returns The IEM exception flags.
5433	* @param pEvent Pointer to the SVM event.
5434	*
5435	* @remarks This function currently only constructs flags required for
5436	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5437	* and CR2 aspects of an exception are not included).
5438	*/
5439	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5440	{
5441	uint8_t const uEventType = pEvent->n.u3Type;
5442	uint32_t fIemXcptFlags;
5443	switch (uEventType)
5444	{
5445	case SVM_EVENT_EXCEPTION:
5446	/*
5447	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5448	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5449	*/
5450	if (pEvent->n.u8Vector == X86_XCPT_BP)
5451	{
5452	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5453	break;
5454	}
5455	if (pEvent->n.u8Vector == X86_XCPT_OF)
5456	{
5457	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5458	break;
5459	}
5460	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5461	RT_FALL_THRU();
5462	case SVM_EVENT_NMI:
5463	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5464	break;
5465
5466	case SVM_EVENT_EXTERNAL_IRQ:
5467	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5468	break;
5469
5470	case SVM_EVENT_SOFTWARE_INT:
5471	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5472	break;
5473
5474	default:
5475	fIemXcptFlags = 0;
5476	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5477	break;
5478	}
5479	return fIemXcptFlags;
5480	}
5481
5482
5483	/**
5484	* Handle a condition that occurred while delivering an event through the guest
5485	* IDT.
5486	*
5487	* @returns VBox status code (informational error codes included).
5488	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5489	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5490	* continue execution of the guest which will delivery the \#DF.
5491	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5492	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5493	*
5494	* @param pVCpu The cross context virtual CPU structure.
5495	* @param pSvmTransient Pointer to the SVM transient structure.
5496	*
5497	* @remarks No-long-jump zone!!!
5498	*/
5499	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5500	{
5501	int rc = VINF_SUCCESS;
5502	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5503	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5504
5505	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5506	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5507	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5508
5509	/*
5510	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5511	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5512	*
5513	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5514	*/
5515	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5516	{
5517	IEMXCPTRAISE enmRaise;
5518	IEMXCPTRAISEINFO fRaiseInfo;
5519	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5520	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5521	if (fExitIsHwXcpt)
5522	{
5523	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5524	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5525	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5526	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5527	}
5528	else
5529	{
5530	/*
5531	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5532	* then we end up here.
5533	*
5534	* If the event was:
5535	* - a software interrupt, we can re-execute the instruction which will
5536	* regenerate the event.
5537	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5538	* - a hardware exception or external interrupt, we re-inject it.
5539	*/
5540	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5541	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5542	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5543	else
5544	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5545	}
5546
5547	switch (enmRaise)
5548	{
5549	case IEMXCPTRAISE_CURRENT_XCPT:
5550	case IEMXCPTRAISE_PREV_EVENT:
5551	{
5552	/* For software interrupts, we shall re-execute the instruction. */
5553	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5554	{
5555	RTGCUINTPTR GCPtrFaultAddress = 0;
5556
5557	/* If we are re-injecting an NMI, clear NMI blocking. */
5558	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5559	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5560
5561	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5562	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5563	{
5564	pSvmTransient->fVectoringPF = true;
5565	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5566	pVCpu->cpum.GstCtx.cr2));
5567	}
5568	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5569	&& uIdtVector == X86_XCPT_PF)
5570	{
5571	/*
5572	* If the previous exception was a #PF, we need to recover the CR2 value.
5573	* This can't happen with shadow paging.
5574	*/
5575	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5576	}
5577
5578	/*
5579	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5580	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5581	*/
5582	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5583	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
5584	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5585
5586	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5587	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5588	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5589	}
5590	break;
5591	}
5592
5593	case IEMXCPTRAISE_REEXEC_INSTR:
5594	{
5595	Assert(rc == VINF_SUCCESS);
5596	break;
5597	}
5598
5599	case IEMXCPTRAISE_DOUBLE_FAULT:
5600	{
5601	/*
5602	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5603	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5604	* converted into a #DF.
5605	*/
5606	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5607	{
5608	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5609	pSvmTransient->fVectoringDoublePF = true;
5610	Assert(rc == VINF_SUCCESS);
5611	}
5612	else
5613	{
5614	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
5615	hmR0SvmSetPendingXcptDF(pVCpu);
5616	rc = VINF_HM_DOUBLE_FAULT;
5617	}
5618	break;
5619	}
5620
5621	case IEMXCPTRAISE_TRIPLE_FAULT:
5622	{
5623	rc = VINF_EM_RESET;
5624	break;
5625	}
5626
5627	case IEMXCPTRAISE_CPU_HANG:
5628	{
5629	rc = VERR_EM_GUEST_CPU_HANG;
5630	break;
5631	}
5632
5633	default:
5634	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
5635	}
5636	}
5637	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5638	return rc;
5639	}
5640
5641
5642	/**
5643	* Advances the guest RIP by the number of bytes specified in @a cb.
5644	*
5645	* @param pVCpu The cross context virtual CPU structure.
5646	* @param cb RIP increment value in bytes.
5647	*/
5648	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
5649	{
5650	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5651	pCtx->rip += cb;
5652
5653	/* Update interrupt shadow. */
5654	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5655	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
5656	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5657	}
5658
5659
5660	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5661	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5662	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5663
5664	/** @name \#VMEXIT handlers.
5665	* @{
5666	*/
5667
5668	/**
5669	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5670	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5671	*/
5672	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5673	{
5674	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5675
5676	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5677	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5678	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5679	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5680
5681	/*
5682	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
5683	* signal -before- the timer fires if the current interrupt is our own timer or a some
5684	* other host interrupt. We also cannot examine what interrupt it is until the host
5685	* actually take the interrupt.
5686	*
5687	* Going back to executing guest code here unconditionally causes random scheduling
5688	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5689	*/
5690	return VINF_EM_RAW_INTERRUPT;
5691	}
5692
5693
5694	/**
5695	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5696	*/
5697	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5698	{
5699	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5700
5701	VBOXSTRICTRC rcStrict;
5702	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5703	if (fSupportsNextRipSave)
5704	{
5705	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5706	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5707	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5708	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
5709	}
5710	else
5711	{
5712	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5713	rcStrict = IEMExecOne(pVCpu);
5714	}
5715
5716	if (rcStrict == VINF_IEM_RAISED_XCPT)
5717	{
5718	rcStrict = VINF_SUCCESS;
5719	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5720	}
5721	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5722	return VBOXSTRICTRC_TODO(rcStrict);
5723	}
5724
5725
5726	/**
5727	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5728	*/
5729	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5730	{
5731	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5732
5733	VBOXSTRICTRC rcStrict;
5734	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5735	if (fSupportsNextRipSave)
5736	{
5737	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5738	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5739	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5740	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
5741	}
5742	else
5743	{
5744	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5745	rcStrict = IEMExecOne(pVCpu);
5746	}
5747
5748	if (rcStrict == VINF_IEM_RAISED_XCPT)
5749	{
5750	rcStrict = VINF_SUCCESS;
5751	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5752	}
5753	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5754	return VBOXSTRICTRC_TODO(rcStrict);
5755	}
5756
5757
5758	/**
5759	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5760	*/
5761	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5762	{
5763	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5764
5765	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
5766	VBOXSTRICTRC rcStrict;
5767	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
5768	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
5769	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
5770	if (!pExitRec)
5771	{
5772	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5773	if (fSupportsNextRipSave)
5774	{
5775	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5776	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5777	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
5778	}
5779	else
5780	{
5781	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5782	rcStrict = IEMExecOne(pVCpu);
5783	}
5784
5785	if (rcStrict == VINF_IEM_RAISED_XCPT)
5786	{
5787	rcStrict = VINF_SUCCESS;
5788	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5789	}
5790	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5791	}
5792	else
5793	{
5794	/*
5795	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
5796	*/
5797	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5798
5799	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
5800	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
5801
5802	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
5803
5804	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
5805	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
5806	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
5807	}
5808	return VBOXSTRICTRC_TODO(rcStrict);
5809	}
5810
5811
5812	/**
5813	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5814	*/
5815	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5816	{
5817	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5818
5819	VBOXSTRICTRC rcStrict;
5820	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5821	if (fSupportsNextRipSave)
5822	{
5823	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5824	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5825	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5826	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
5827	}
5828	else
5829	{
5830	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5831	rcStrict = IEMExecOne(pVCpu);
5832	}
5833
5834	if (rcStrict == VINF_SUCCESS)
5835	pSvmTransient->fUpdateTscOffsetting = true;
5836	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5837	{
5838	rcStrict = VINF_SUCCESS;
5839	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5840	}
5841	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5842	return VBOXSTRICTRC_TODO(rcStrict);
5843	}
5844
5845
5846	/**
5847	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5848	*/
5849	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5850	{
5851	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5852
5853	VBOXSTRICTRC rcStrict;
5854	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5855	if (fSupportsNextRipSave)
5856	{
5857	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
5858	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5859	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5860	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
5861	}
5862	else
5863	{
5864	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5865	rcStrict = IEMExecOne(pVCpu);
5866	}
5867
5868	if (rcStrict == VINF_SUCCESS)
5869	pSvmTransient->fUpdateTscOffsetting = true;
5870	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5871	{
5872	rcStrict = VINF_SUCCESS;
5873	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5874	}
5875	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5876	return VBOXSTRICTRC_TODO(rcStrict);
5877	}
5878
5879
5880	/**
5881	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5882	*/
5883	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5884	{
5885	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5886
5887	VBOXSTRICTRC rcStrict;
5888	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5889	if (fSupportsNextRipSave)
5890	{
5891	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5892	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5893	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5894	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
5895	}
5896	else
5897	{
5898	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5899	rcStrict = IEMExecOne(pVCpu);
5900	}
5901
5902	if (rcStrict == VINF_IEM_RAISED_XCPT)
5903	{
5904	rcStrict = VINF_SUCCESS;
5905	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5906	}
5907	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5908	return VBOXSTRICTRC_TODO(rcStrict);
5909	}
5910
5911
5912	/**
5913	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5914	*/
5915	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5916	{
5917	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5918	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5919
5920	VBOXSTRICTRC rcStrict;
5921	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
5922	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5923	if ( fSupportsDecodeAssists
5924	&& fSupportsNextRipSave)
5925	{
5926	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
5927	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5928	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5929	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
5930	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
5931	}
5932	else
5933	{
5934	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5935	rcStrict = IEMExecOne(pVCpu);
5936	}
5937
5938	if (rcStrict == VINF_IEM_RAISED_XCPT)
5939	{
5940	rcStrict = VINF_SUCCESS;
5941	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5942	}
5943	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5944	return VBOXSTRICTRC_VAL(rcStrict);
5945	}
5946
5947
5948	/**
5949	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
5950	*/
5951	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5952	{
5953	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5954
5955	VBOXSTRICTRC rcStrict;
5956	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5957	if (fSupportsNextRipSave)
5958	{
5959	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5960	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5961	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5962	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
5963	}
5964	else
5965	{
5966	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5967	rcStrict = IEMExecOne(pVCpu);
5968	}
5969
5970	if ( rcStrict == VINF_EM_HALT
5971	\|\| rcStrict == VINF_SUCCESS)
5972	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
5973	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5974	{
5975	rcStrict = VINF_SUCCESS;
5976	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5977	}
5978	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5979	if (rcStrict != VINF_SUCCESS)
5980	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
5981	return VBOXSTRICTRC_VAL(rcStrict);;
5982	}
5983
5984
5985	/**
5986	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
5987	*/
5988	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5989	{
5990	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5991
5992	/*
5993	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
5994	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
5995	* segment override prefix or other prefixes might be used, in which case we fallback to
5996	* IEMExecOne() to figure out.
5997	*/
5998	VBOXSTRICTRC rcStrict;
5999	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6000	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6001	if (cbInstr)
6002	{
6003	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6004	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6005	}
6006	else
6007	{
6008	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6009	rcStrict = IEMExecOne(pVCpu);
6010	}
6011
6012	if (rcStrict == VINF_IEM_RAISED_XCPT)
6013	{
6014	rcStrict = VINF_SUCCESS;
6015	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6016	}
6017	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6018	return VBOXSTRICTRC_TODO(rcStrict);
6019	}
6020
6021
6022	/**
6023	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6024	*/
6025	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6026	{
6027	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6028
6029	VBOXSTRICTRC rcStrict;
6030	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6031	if (fSupportsNextRipSave)
6032	{
6033	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6034	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6035	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6036	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6037	}
6038	else
6039	{
6040	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6041	rcStrict = IEMExecOne(pVCpu);
6042	}
6043
6044	if ( rcStrict == VINF_EM_HALT
6045	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6046	rcStrict = VINF_SUCCESS;
6047	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6048	{
6049	rcStrict = VINF_SUCCESS;
6050	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6051	}
6052	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6053	return VBOXSTRICTRC_TODO(rcStrict);
6054	}
6055
6056
6057	/**
6058	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6059	* \#VMEXIT.
6060	*/
6061	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6062	{
6063	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6064	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6065	return VINF_EM_RESET;
6066	}
6067
6068
6069	/**
6070	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6071	*/
6072	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6073	{
6074	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6075	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6076	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6077	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6078	RT_NOREF(pVmcb);
6079	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6080	return VERR_SVM_UNEXPECTED_EXIT;
6081	}
6082
6083
6084	/**
6085	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6086	*/
6087	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6088	{
6089	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6090
6091	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6092	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6093	#ifdef VBOX_WITH_STATISTICS
6094	switch (pSvmTransient->u64ExitCode)
6095	{
6096	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6097	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6098	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6099	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6100	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6101	}
6102	#endif
6103
6104	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6105	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6106	if ( fSupportsDecodeAssists
6107	&& fSupportsNextRipSave)
6108	{
6109	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6110	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6111	if (fMovCRx)
6112	{
6113	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6114	\| CPUMCTX_EXTRN_APIC_TPR);
6115	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6116	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6117	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6118	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6119	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6120	return VBOXSTRICTRC_VAL(rcStrict);
6121	}
6122	/* else: SMSW instruction, fall back below to IEM for this. */
6123	}
6124
6125	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6126	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6127	AssertMsg( rcStrict == VINF_SUCCESS
6128	\|\| rcStrict == VINF_PGM_SYNC_CR3
6129	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6130	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6131	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6132	if (rcStrict == VINF_IEM_RAISED_XCPT)
6133	{
6134	rcStrict = VINF_SUCCESS;
6135	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6136	}
6137	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6138	return VBOXSTRICTRC_TODO(rcStrict);
6139	}
6140
6141
6142	/**
6143	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6144	*/
6145	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6146	{
6147	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6148
6149	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6150	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6151	Assert(iCrReg <= 15);
6152
6153	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6154	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6155	bool fDecodedInstr = false;
6156	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6157	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6158	if ( fSupportsDecodeAssists
6159	&& fSupportsNextRipSave)
6160	{
6161	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6162	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6163	if (fMovCRx)
6164	{
6165	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6166	\| CPUMCTX_EXTRN_APIC_TPR);
6167	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6168	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6169	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6170	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6171	fDecodedInstr = true;
6172	}
6173	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6174	}
6175
6176	if (!fDecodedInstr)
6177	{
6178	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6179	Log4Func(("iCrReg=%#x\n", iCrReg));
6180	rcStrict = IEMExecOne(pVCpu);
6181	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6182	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6183	rcStrict = VERR_EM_INTERPRETER;
6184	}
6185
6186	if (rcStrict == VINF_SUCCESS)
6187	{
6188	switch (iCrReg)
6189	{
6190	case 0:
6191	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6192	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6193	break;
6194
6195	case 2:
6196	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6197	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6198	break;
6199
6200	case 3:
6201	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6202	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6203	break;
6204
6205	case 4:
6206	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6207	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6208	break;
6209
6210	case 8:
6211	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6212	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6213	break;
6214
6215	default:
6216	{
6217	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6218	pSvmTransient->u64ExitCode, iCrReg));
6219	break;
6220	}
6221	}
6222	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6223	}
6224	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6225	{
6226	rcStrict = VINF_SUCCESS;
6227	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6228	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6229	}
6230	else
6231	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6232	return VBOXSTRICTRC_TODO(rcStrict);
6233	}
6234
6235
6236	/**
6237	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6238	*
6239	* @returns Strict VBox status code.
6240	* @param pVCpu The cross context virtual CPU structure.
6241	* @param pVmcb Pointer to the VM control block.
6242	*/
6243	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
6244	{
6245	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6246	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6247
6248	VBOXSTRICTRC rcStrict;
6249	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6250	if (fSupportsNextRipSave)
6251	{
6252	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6253	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6254	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6255	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6256	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6257	}
6258	else
6259	{
6260	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6261	rcStrict = IEMExecOne(pVCpu);
6262	}
6263
6264	AssertMsg( rcStrict == VINF_SUCCESS
6265	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6266	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6267	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6268
6269	if (rcStrict == VINF_IEM_RAISED_XCPT)
6270	{
6271	rcStrict = VINF_SUCCESS;
6272	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6273	}
6274	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6275	return rcStrict;
6276	}
6277
6278
6279	/**
6280	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6281	*
6282	* @returns Strict VBox status code.
6283	* @param pVCpu The cross context virtual CPU structure.
6284	* @param pVmcb Pointer to the VM control block.
6285	* @param pSvmTransient Pointer to the SVM-transient structure.
6286	*/
6287	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6288	{
6289	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6290	uint32_t const idMsr = pCtx->ecx;
6291	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6292	Log4Func(("idMsr=%#RX32\n", idMsr));
6293
6294	/*
6295	* Handle TPR patching MSR writes.
6296	* We utilitize the LSTAR MSR for patching.
6297	*/
6298	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6299	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
6300	&& idMsr == MSR_K8_LSTAR)
6301	{
6302	unsigned cbInstr;
6303	if (fSupportsNextRipSave)
6304	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6305	else
6306	{
6307	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6308	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6309	if ( rc == VINF_SUCCESS
6310	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6311	Assert(cbInstr > 0);
6312	else
6313	cbInstr = 0;
6314	}
6315
6316	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6317	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6318	{
6319	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6320	AssertRCReturn(rc, rc);
6321	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6322	}
6323
6324	int rc = VINF_SUCCESS;
6325	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6326	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6327	return rc;
6328	}
6329
6330	/*
6331	* Handle regular MSR writes.
6332	*/
6333	VBOXSTRICTRC rcStrict;
6334	if (fSupportsNextRipSave)
6335	{
6336	/** @todo Optimize this: We don't need to get much of the MSR state here
6337	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6338	* clear the applicable extern flags. */
6339	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6340	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6341	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6342	}
6343	else
6344	{
6345	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6346	rcStrict = IEMExecOne(pVCpu);
6347	}
6348
6349	AssertMsg( rcStrict == VINF_SUCCESS
6350	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6351	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6352	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6353
6354	if (rcStrict == VINF_SUCCESS)
6355	{
6356	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6357	if ( idMsr >= MSR_IA32_X2APIC_START
6358	&& idMsr <= MSR_IA32_X2APIC_END)
6359	{
6360	/*
6361	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6362	* When full APIC register virtualization is implemented we'll have to make sure
6363	* APIC state is saved from the VMCB before IEM changes it.
6364	*/
6365	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6366	}
6367	else
6368	{
6369	switch (idMsr)
6370	{
6371	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6372	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6373	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6374	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6375	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6376	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6377	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6378	}
6379	}
6380	}
6381	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6382	{
6383	rcStrict = VINF_SUCCESS;
6384	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6385	}
6386	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6387	return rcStrict;
6388	}
6389
6390
6391	/**
6392	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6393	* \#VMEXIT.
6394	*/
6395	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6396	{
6397	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6398
6399	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6400	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6401	return VBOXSTRICTRC_TODO(hmR0SvmExitReadMsr(pVCpu, pVmcb));
6402
6403	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6404	return VBOXSTRICTRC_TODO(hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient));
6405	}
6406
6407
6408	/**
6409	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6410	*/
6411	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6412	{
6413	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6414	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6415
6416	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6417
6418	/** @todo Stepping with nested-guest. */
6419	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6420	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6421	{
6422	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6423	if (pSvmTransient->fWasGuestDebugStateActive)
6424	{
6425	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6426	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6427	return VERR_SVM_UNEXPECTED_EXIT;
6428	}
6429
6430	/*
6431	* Lazy DR0-3 loading.
6432	*/
6433	if (!pSvmTransient->fWasHyperDebugStateActive)
6434	{
6435	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6436	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6437
6438	/* Don't intercept DRx read and writes. */
6439	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6440	pVmcb->ctrl.u16InterceptRdDRx = 0;
6441	pVmcb->ctrl.u16InterceptWrDRx = 0;
6442	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6443
6444	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6445	VMMRZCallRing3Disable(pVCpu);
6446	HM_DISABLE_PREEMPT(pVCpu);
6447
6448	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6449	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6450	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6451
6452	HM_RESTORE_PREEMPT();
6453	VMMRZCallRing3Enable(pVCpu);
6454
6455	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6456	return VINF_SUCCESS;
6457	}
6458	}
6459
6460	/*
6461	* Interpret the read/writing of DRx.
6462	*/
6463	/** @todo Decode assist. */
6464	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6465	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6466	if (RT_LIKELY(rc == VINF_SUCCESS))
6467	{
6468	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6469	/** @todo CPUM should set this flag! */
6470	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6471	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6472	}
6473	else
6474	Assert(rc == VERR_EM_INTERPRETER);
6475	return VBOXSTRICTRC_TODO(rc);
6476	}
6477
6478
6479	/**
6480	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6481	*/
6482	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6483	{
6484	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6485	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6486	int rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6487	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6488	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6489	return rc;
6490	}
6491
6492
6493	/**
6494	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6495	*/
6496	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6497	{
6498	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6499	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6500
6501	/** @todo decode assists... */
6502	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6503	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6504	{
6505	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6506	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6507	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0,
6508	pCtx->cr4));
6509	}
6510	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6511	{
6512	rcStrict = VINF_SUCCESS;
6513	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6514	}
6515	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6516	return VBOXSTRICTRC_TODO(rcStrict);
6517	}
6518
6519
6520	/**
6521	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6522	*/
6523	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6524	{
6525	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6526	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6527
6528	/* I/O operation lookup arrays. */
6529	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6530	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6531	the result (in AL/AX/EAX). */
6532	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6533	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6534	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6535
6536	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6537
6538	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6539	SVMIOIOEXITINFO IoExitInfo;
6540	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6541	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6542	uint32_t cbValue = s_aIOSize[uIOWidth];
6543	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6544
6545	if (RT_UNLIKELY(!cbValue))
6546	{
6547	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6548	return VERR_EM_INTERPRETER;
6549	}
6550
6551	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6552	VBOXSTRICTRC rcStrict;
6553	PCEMEXITREC pExitRec = NULL;
6554	if ( !pVCpu->hm.s.fSingleInstruction
6555	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6556	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6557	!IoExitInfo.n.u1Str
6558	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6559	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6560	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6561	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6562	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6563	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6564	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6565	if (!pExitRec)
6566	{
6567	bool fUpdateRipAlready = false;
6568	if (IoExitInfo.n.u1Str)
6569	{
6570	/* INS/OUTS - I/O String instruction. */
6571	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6572	* in EXITINFO1? Investigate once this thing is up and running. */
6573	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6574	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6575	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6576	static IEMMODE const s_aenmAddrMode[8] =
6577	{
6578	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6579	};
6580	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6581	if (enmAddrMode != (IEMMODE)-1)
6582	{
6583	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6584	if (cbInstr <= 15 && cbInstr >= 1)
6585	{
6586	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6587	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6588	{
6589	/* Don't know exactly how to detect whether u3Seg is valid, currently
6590	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6591	2384 Opterons when only checking NRIP. */
6592	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6593	if ( fSupportsNextRipSave
6594	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6595	{
6596	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6597	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6598	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6599	IoExitInfo.n.u3Seg, true /fIoChecked/);
6600	}
6601	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6602	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6603	X86_SREG_DS, true /fIoChecked/);
6604	else
6605	rcStrict = IEMExecOne(pVCpu);
6606	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6607	}
6608	else
6609	{
6610	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6611	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6612	true /fIoChecked/);
6613	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6614	}
6615	}
6616	else
6617	{
6618	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6619	rcStrict = IEMExecOne(pVCpu);
6620	}
6621	}
6622	else
6623	{
6624	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6625	rcStrict = IEMExecOne(pVCpu);
6626	}
6627	fUpdateRipAlready = true;
6628	}
6629	else
6630	{
6631	/* IN/OUT - I/O instruction. */
6632	Assert(!IoExitInfo.n.u1Rep);
6633
6634	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6635	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6636	{
6637	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6638	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6639	&& !pCtx->eflags.Bits.u1TF)
6640	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
6641	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6642	}
6643	else
6644	{
6645	uint32_t u32Val = 0;
6646	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6647	if (IOM_SUCCESS(rcStrict))
6648	{
6649	/* Save result of I/O IN instr. in AL/AX/EAX. */
6650	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6651	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6652	}
6653	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6654	&& !pCtx->eflags.Bits.u1TF)
6655	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
6656
6657	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6658	}
6659	}
6660
6661	if (IOM_SUCCESS(rcStrict))
6662	{
6663	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6664	if (!fUpdateRipAlready)
6665	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6666
6667	/*
6668	* If any I/O breakpoints are armed, we need to check if one triggered
6669	* and take appropriate action.
6670	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6671	*/
6672	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6673	* execution engines about whether hyper BPs and such are pending. */
6674	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
6675	uint32_t const uDr7 = pCtx->dr[7];
6676	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6677	&& X86_DR7_ANY_RW_IO(uDr7)
6678	&& (pCtx->cr4 & X86_CR4_DE))
6679	\|\| DBGFBpIsHwIoArmed(pVM)))
6680	{
6681	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6682	VMMRZCallRing3Disable(pVCpu);
6683	HM_DISABLE_PREEMPT(pVCpu);
6684
6685	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6686	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6687
6688	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
6689	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6690	{
6691	/* Raise #DB. */
6692	pVmcb->guest.u64DR6 = pCtx->dr[6];
6693	pVmcb->guest.u64DR7 = pCtx->dr[7];
6694	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6695	hmR0SvmSetPendingXcptDB(pVCpu);
6696	}
6697	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6698	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6699	else if ( rcStrict2 != VINF_SUCCESS
6700	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6701	rcStrict = rcStrict2;
6702	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6703
6704	HM_RESTORE_PREEMPT();
6705	VMMRZCallRing3Enable(pVCpu);
6706	}
6707
6708	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6709	}
6710
6711	#ifdef VBOX_STRICT
6712	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6713	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
6714	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6715	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6716	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
6717	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
6718	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6719	else
6720	{
6721	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6722	* statuses, that the VMM device and some others may return. See
6723	* IOM_SUCCESS() for guidance. */
6724	AssertMsg( RT_FAILURE(rcStrict)
6725	\|\| rcStrict == VINF_SUCCESS
6726	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6727	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6728	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6729	\|\| rcStrict == VINF_EM_RAW_TO_R3
6730	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6731	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6732	}
6733	#endif
6734	}
6735	else
6736	{
6737	/*
6738	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6739	*/
6740	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6741	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
6742	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
6743	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
6744	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
6745	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
6746	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
6747
6748	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6749	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6750
6751	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6752	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6753	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6754	}
6755	return VBOXSTRICTRC_TODO(rcStrict);
6756	}
6757
6758
6759	/**
6760	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6761	*/
6762	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6763	{
6764	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6765	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6766	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6767
6768	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6769	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6770	Assert(pVM->hm.s.fNestedPaging);
6771
6772	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6773	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6774	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6775	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
6776	thus intentionally not copied into u32ErrCode. */
6777
6778	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
6779	u32ErrCode));
6780
6781	/*
6782	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
6783	*/
6784	if ( pVM->hm.s.fTprPatchingAllowed
6785	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6786	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6787	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6788	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
6789	&& !CPUMIsGuestInLongModeEx(pCtx)
6790	&& !CPUMGetGuestCPL(pVCpu)
6791	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6792	{
6793	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6794	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6795
6796	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6797	{
6798	/* Only attempt to patch the instruction once. */
6799	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6800	if (!pPatch)
6801	return VINF_EM_HM_PATCH_TPR_INSTR;
6802	}
6803	}
6804
6805	/*
6806	* Determine the nested paging mode.
6807	*/
6808	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
6809	PGMMODE const enmNestedPagingMode = PGMGetHostMode(pVM);
6810
6811	/*
6812	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6813	*/
6814	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6815	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6816	{
6817	/*
6818	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
6819	* injecting the original pending event would most likely cause the same MMIO #NPF.
6820	*/
6821	if (pVCpu->hm.s.Event.fPending)
6822	{
6823	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
6824	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6825	}
6826
6827	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
6828	VBOXSTRICTRC rcStrict;
6829	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6830	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
6831	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6832	if (!pExitRec)
6833	{
6834
6835	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6836	u32ErrCode);
6837
6838	/*
6839	* If we succeed, resume guest execution.
6840	*
6841	* If we fail in interpreting the instruction because we couldn't get the guest
6842	* physical address of the page containing the instruction via the guest's page
6843	* tables (we would invalidate the guest page in the host TLB), resume execution
6844	* which would cause a guest page fault to let the guest handle this weird case.
6845	*
6846	* See @bugref{6043}.
6847	*/
6848	if ( rcStrict == VINF_SUCCESS
6849	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
6850	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
6851	{
6852	/* Successfully handled MMIO operation. */
6853	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6854	rcStrict = VINF_SUCCESS;
6855	}
6856	}
6857	else
6858	{
6859	/*
6860	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6861	*/
6862	Assert(pCtx == &pVCpu->cpum.GstCtx);
6863	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6864	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
6865	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
6866
6867	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6868	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6869
6870	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6871	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6872	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6873	}
6874	return VBOXSTRICTRC_TODO(rcStrict);
6875	}
6876
6877	/*
6878	* Nested page-fault.
6879	*/
6880	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6881	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6882	TRPMResetTrap(pVCpu);
6883
6884	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6885
6886	/*
6887	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6888	*/
6889	if ( rc == VINF_SUCCESS
6890	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6891	\|\| rc == VERR_PAGE_NOT_PRESENT)
6892	{
6893	/* We've successfully synced our shadow page tables. */
6894	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6895	rc = VINF_SUCCESS;
6896	}
6897
6898	/*
6899	* If delivering an event causes an #NPF (and not MMIO), we shall resolve the fault and
6900	* re-inject the original event.
6901	*/
6902	if (pVCpu->hm.s.Event.fPending)
6903	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
6904
6905	return rc;
6906	}
6907
6908
6909	/**
6910	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6911	* \#VMEXIT.
6912	*/
6913	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6914	{
6915	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6916	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
6917
6918	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6919	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6920	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
6921
6922	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6923	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6924	return VINF_SUCCESS;
6925	}
6926
6927
6928	/**
6929	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6930	* \#VMEXIT.
6931	*/
6932	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6933	{
6934	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6935	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6936
6937	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6938	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6939	#endif
6940
6941	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6942	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6943	{
6944	/*
6945	* AMD-V provides us with the exception which caused the TS; we collect
6946	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
6947	*/
6948	Log4Func(("TS occurred during event delivery\n"));
6949	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6950	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6951	}
6952
6953	/** @todo Emulate task switch someday, currently just going back to ring-3 for
6954	* emulation. */
6955	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
6956	return VERR_EM_INTERPRETER;
6957	}
6958
6959
6960	/**
6961	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
6962	*/
6963	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6964	{
6965	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6966	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6967
6968	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6969	if (pVM->hm.s.fTprPatchingAllowed)
6970	{
6971	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
6972	if (rc != VERR_NOT_FOUND)
6973	{
6974	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
6975	return rc;
6976	}
6977	}
6978
6979	if (EMAreHypercallInstructionsEnabled(pVCpu))
6980	{
6981	unsigned cbInstr;
6982	if (hmR0SvmSupportsNextRipSave(pVCpu))
6983	{
6984	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6985	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6986	}
6987	else
6988	{
6989	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6990	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6991	if ( rc == VINF_SUCCESS
6992	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
6993	Assert(cbInstr > 0);
6994	else
6995	cbInstr = 0;
6996	}
6997
6998	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
6999	if (RT_SUCCESS(rcStrict))
7000	{
7001	/* Only update the RIP if we're continuing guest execution and not in the case
7002	of say VINF_GIM_R3_HYPERCALL. */
7003	if (rcStrict == VINF_SUCCESS)
7004	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7005
7006	return VBOXSTRICTRC_VAL(rcStrict);
7007	}
7008	else
7009	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7010	}
7011
7012	hmR0SvmSetPendingXcptUD(pVCpu);
7013	return VINF_SUCCESS;
7014	}
7015
7016
7017	/**
7018	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7019	*/
7020	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7021	{
7022	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7023
7024	unsigned cbInstr;
7025	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7026	if (fSupportsNextRipSave)
7027	{
7028	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7029	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7030	}
7031	else
7032	{
7033	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7034	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7035	if ( rc == VINF_SUCCESS
7036	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7037	Assert(cbInstr > 0);
7038	else
7039	cbInstr = 0;
7040	}
7041
7042	/** @todo The guest has likely hit a contended spinlock. We might want to
7043	* poke a schedule different guest VCPU. */
7044	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7045	return VINF_EM_RAW_INTERRUPT;
7046	}
7047
7048
7049	/**
7050	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7051	* \#VMEXIT.
7052	*/
7053	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7054	{
7055	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7056	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7057	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7058
7059	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7060	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7061	}
7062
7063
7064	/**
7065	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7066	*/
7067	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7068	{
7069	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7070
7071	/* Clear NMI blocking. */
7072	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
7073	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7074
7075	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7076	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7077	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7078
7079	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7080	return VINF_SUCCESS;
7081	}
7082
7083
7084	/**
7085	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7086	* Conditional \#VMEXIT.
7087	*/
7088	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7089	{
7090	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7091	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7092	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7093
7094	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7095	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7096	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7097	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7098	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7099	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7100
7101	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7102	if (pVM->hm.s.fNestedPaging)
7103	{
7104	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7105	if ( !pSvmTransient->fVectoringDoublePF
7106	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7107	{
7108	/* A genuine guest #PF, reflect it to the guest. */
7109	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7110	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7111	uFaultAddress, uErrCode));
7112	}
7113	else
7114	{
7115	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7116	hmR0SvmSetPendingXcptDF(pVCpu);
7117	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7118	}
7119	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7120	return VINF_SUCCESS;
7121	}
7122	#endif
7123
7124	Assert(!pVM->hm.s.fNestedPaging);
7125
7126	/*
7127	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7128	*/
7129	if ( pVM->hm.s.fTprPatchingAllowed
7130	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7131	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7132	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7133	&& !CPUMIsGuestInLongModeEx(pCtx)
7134	&& !CPUMGetGuestCPL(pVCpu)
7135	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7136	{
7137	RTGCPHYS GCPhysApicBase;
7138	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7139	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7140
7141	/* Check if the page at the fault-address is the APIC base. */
7142	RTGCPHYS GCPhysPage;
7143	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7144	if ( rc2 == VINF_SUCCESS
7145	&& GCPhysPage == GCPhysApicBase)
7146	{
7147	/* Only attempt to patch the instruction once. */
7148	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7149	if (!pPatch)
7150	return VINF_EM_HM_PATCH_TPR_INSTR;
7151	}
7152	}
7153
7154	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7155	pCtx->rip, uErrCode, pCtx->cr3));
7156
7157	/*
7158	* If it's a vectoring #PF, emulate injecting the original event injection as
7159	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7160	* event injection that caused a #PF. See @bugref{6607}.
7161	*/
7162	if (pSvmTransient->fVectoringPF)
7163	{
7164	Assert(pVCpu->hm.s.Event.fPending);
7165	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7166	}
7167
7168	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7169	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7170
7171	Log4Func(("#PF: rc=%Rrc\n", rc));
7172
7173	if (rc == VINF_SUCCESS)
7174	{
7175	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7176	TRPMResetTrap(pVCpu);
7177	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7178	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7179	return rc;
7180	}
7181
7182	if (rc == VINF_EM_RAW_GUEST_TRAP)
7183	{
7184	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7185
7186	/*
7187	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7188	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7189	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7190	*/
7191	if ( !pSvmTransient->fVectoringDoublePF
7192	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7193	{
7194	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7195	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7196	TRPMResetTrap(pVCpu);
7197
7198	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7199	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7200	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7201	&& CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
7202	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress));
7203	#endif
7204
7205	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7206	}
7207	else
7208	{
7209	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7210	TRPMResetTrap(pVCpu);
7211	hmR0SvmSetPendingXcptDF(pVCpu);
7212	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7213	}
7214
7215	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7216	return VINF_SUCCESS;
7217	}
7218
7219	TRPMResetTrap(pVCpu);
7220	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7221	return rc;
7222	}
7223
7224
7225	/**
7226	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7227	* Conditional \#VMEXIT.
7228	*/
7229	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7230	{
7231	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7232	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7233	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7234
7235	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7236	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7237	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7238
7239	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7240	if (pVCpu->hm.s.fGIMTrapXcptUD)
7241	{
7242	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7243	uint8_t cbInstr = 0;
7244	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7245	if (rcStrict == VINF_SUCCESS)
7246	{
7247	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7248	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7249	rc = VINF_SUCCESS;
7250	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7251	}
7252	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7253	rc = VINF_SUCCESS;
7254	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7255	rc = VINF_GIM_R3_HYPERCALL;
7256	else
7257	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7258	}
7259
7260	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7261	if (RT_FAILURE(rc))
7262	{
7263	hmR0SvmSetPendingXcptUD(pVCpu);
7264	rc = VINF_SUCCESS;
7265	}
7266
7267	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7268	return rc;
7269	}
7270
7271
7272	/**
7273	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7274	* Conditional \#VMEXIT.
7275	*/
7276	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7277	{
7278	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7279	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7280	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7281
7282	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7283	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7284
7285	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7286	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7287
7288	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7289
7290	if (!(pCtx->cr0 & X86_CR0_NE))
7291	{
7292	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7293	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7294	unsigned cbInstr;
7295	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7296	if (RT_SUCCESS(rc))
7297	{
7298	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7299	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7300	if (RT_SUCCESS(rc))
7301	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7302	}
7303	else
7304	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7305	return rc;
7306	}
7307
7308	hmR0SvmSetPendingXcptMF(pVCpu);
7309	return VINF_SUCCESS;
7310	}
7311
7312
7313	/**
7314	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7315	* \#VMEXIT.
7316	*/
7317	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7318	{
7319	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7320	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7321	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7322	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7323
7324	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7325	{
7326	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7327	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7328	}
7329
7330	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7331
7332	/*
7333	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7334	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7335	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7336	*/
7337	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7338	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7339	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7340	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7341	if (rc == VINF_EM_RAW_GUEST_TRAP)
7342	{
7343	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7344	if (CPUMIsHyperDebugStateActive(pVCpu))
7345	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7346
7347	/* Reflect the exception back to the guest. */
7348	hmR0SvmSetPendingXcptDB(pVCpu);
7349	rc = VINF_SUCCESS;
7350	}
7351
7352	/*
7353	* Update DR6.
7354	*/
7355	if (CPUMIsHyperDebugStateActive(pVCpu))
7356	{
7357	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7358	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7359	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7360	}
7361	else
7362	{
7363	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7364	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7365	}
7366
7367	return rc;
7368	}
7369
7370
7371	/**
7372	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7373	* Conditional \#VMEXIT.
7374	*/
7375	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7376	{
7377	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7378	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7379	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
7380
7381	SVMEVENT Event;
7382	Event.u = 0;
7383	Event.n.u1Valid = 1;
7384	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7385	Event.n.u8Vector = X86_XCPT_AC;
7386	Event.n.u1ErrorCodeValid = 1;
7387	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7388	return VINF_SUCCESS;
7389	}
7390
7391
7392	/**
7393	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7394	* Conditional \#VMEXIT.
7395	*/
7396	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7397	{
7398	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7399	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7400	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7401	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
7402
7403	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7404	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7405	if (rc == VINF_EM_RAW_GUEST_TRAP)
7406	{
7407	SVMEVENT Event;
7408	Event.u = 0;
7409	Event.n.u1Valid = 1;
7410	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7411	Event.n.u8Vector = X86_XCPT_BP;
7412	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7413	rc = VINF_SUCCESS;
7414	}
7415
7416	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_DBG_BREAKPOINT);
7417	return rc;
7418	}
7419
7420
7421	/**
7422	* Hacks its way around the lovely mesa driver's backdoor accesses.
7423	*
7424	* @sa hmR0VmxHandleMesaDrvGp
7425	*/
7426	static int hmR0SvmHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7427	{
7428	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7429	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7430	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7431	RT_NOREF(pCtx, pVmcb);
7432
7433	/* For now we'll just skip the instruction. */
7434	hmR0SvmAdvanceRip(pVCpu, 1);
7435	return VINF_SUCCESS;
7436	}
7437
7438
7439	/**
7440	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7441	* backdoor logging w/o checking what it is running inside.
7442	*
7443	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7444	* backdoor port and magic numbers loaded in registers.
7445	*
7446	* @returns true if it is, false if it isn't.
7447	* @sa hmR0VmxIsMesaDrvGp
7448	*/
7449	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7450	{
7451	/* Check magic and port. */
7452	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7453	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7454	if (pCtx->dx != UINT32_C(0x5658))
7455	return false;
7456	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7457	return false;
7458
7459	/* Check that it is #GP(0). */
7460	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7461	return false;
7462
7463	/* Flat ring-3 CS. */
7464	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7465	if (pVmcb->guest.u8CPL != 3)
7466	return false;
7467	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7468	return false;
7469
7470	/* 0xed: IN eAX,dx */
7471	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7472	{
7473	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7474	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7475	uint8_t abInstr[1];
7476	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7477	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7478	if (RT_FAILURE(rc))
7479	return false;
7480	if (abInstr[0] != 0xed)
7481	return false;
7482	}
7483	else
7484	{
7485	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7486	if (pVmcb->ctrl.abInstr[0] != 0xed)
7487	return false;
7488	}
7489	return true;
7490	}
7491
7492
7493	/**
7494	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7495	* Conditional \#VMEXIT.
7496	*/
7497	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7498	{
7499	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7500	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7501	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
7502
7503	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7504	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7505
7506	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7507	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7508	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7509	{
7510	SVMEVENT Event;
7511	Event.u = 0;
7512	Event.n.u1Valid = 1;
7513	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7514	Event.n.u8Vector = X86_XCPT_GP;
7515	Event.n.u1ErrorCodeValid = 1;
7516	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7517	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7518	return VINF_SUCCESS;
7519	}
7520	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7521	}
7522
7523
7524	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7525	/**
7526	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7527	*/
7528	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7529	{
7530	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7531	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7532
7533	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7534	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7535	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7536	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7537	Assert(uVector <= X86_XCPT_LAST);
7538	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7539
7540	SVMEVENT Event;
7541	Event.u = 0;
7542	Event.n.u1Valid = 1;
7543	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7544	Event.n.u8Vector = uVector;
7545	switch (uVector)
7546	{
7547	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7548	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7549	case X86_XCPT_DF:
7550	case X86_XCPT_TS:
7551	case X86_XCPT_NP:
7552	case X86_XCPT_SS:
7553	case X86_XCPT_GP:
7554	case X86_XCPT_AC:
7555	{
7556	Event.n.u1ErrorCodeValid = 1;
7557	Event.n.u32ErrorCode = uErrCode;
7558	break;
7559	}
7560	}
7561
7562	#ifdef VBOX_WITH_STATISTICS
7563	switch (uVector)
7564	{
7565	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
7566	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
7567	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
7568	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7569	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
7570	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
7571	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7572	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
7573	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
7574	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
7575	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
7576	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
7577	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
7578	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
7579	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
7580	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
7581	default:
7582	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
7583	break;
7584	}
7585	#endif
7586
7587	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7588	return VINF_SUCCESS;
7589	}
7590	#endif
7591
7592	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7593	/**
7594	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7595	*/
7596	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7597	{
7598	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7599
7600	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7601	Assert(pVmcb);
7602	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7603
7604	VBOXSTRICTRC rcStrict;
7605	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7606	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7607	if (fSupportsNextRipSave)
7608	{
7609	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7610	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7611	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7612	}
7613	else
7614	{
7615	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7616	rcStrict = IEMExecOne(pVCpu);
7617	}
7618
7619	if (rcStrict == VINF_SUCCESS)
7620	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7621	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7622	{
7623	rcStrict = VINF_SUCCESS;
7624	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7625	}
7626	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7627	return VBOXSTRICTRC_TODO(rcStrict);
7628	}
7629
7630
7631	/**
7632	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7633	*/
7634	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7635	{
7636	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7637
7638	/*
7639	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7640	* we only intercept STGI when events are pending for GIF to become 1.
7641	*/
7642	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7643	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7644	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7645
7646	VBOXSTRICTRC rcStrict;
7647	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7648	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7649	if (fSupportsNextRipSave)
7650	{
7651	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7652	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7653	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7654	}
7655	else
7656	{
7657	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7658	rcStrict = IEMExecOne(pVCpu);
7659	}
7660
7661	if (rcStrict == VINF_SUCCESS)
7662	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7663	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7664	{
7665	rcStrict = VINF_SUCCESS;
7666	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7667	}
7668	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7669	return VBOXSTRICTRC_TODO(rcStrict);
7670	}
7671
7672
7673	/**
7674	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7675	*/
7676	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7677	{
7678	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7679
7680	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7681	Assert(pVmcb);
7682	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7683
7684	VBOXSTRICTRC rcStrict;
7685	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7686	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7687	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7688	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7689	if (fSupportsNextRipSave)
7690	{
7691	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7692	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7693	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7694	}
7695	else
7696	{
7697	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7698	rcStrict = IEMExecOne(pVCpu);
7699	}
7700
7701	if (rcStrict == VINF_SUCCESS)
7702	{
7703	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7704	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7705	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7706	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7707	}
7708	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7709	{
7710	rcStrict = VINF_SUCCESS;
7711	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7712	}
7713	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7714	return VBOXSTRICTRC_TODO(rcStrict);
7715	}
7716
7717
7718	/**
7719	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7720	*/
7721	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7722	{
7723	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7724
7725	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7726	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7727
7728	VBOXSTRICTRC rcStrict;
7729	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7730	if (fSupportsNextRipSave)
7731	{
7732	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7733	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7734	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7735	}
7736	else
7737	{
7738	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7739	rcStrict = IEMExecOne(pVCpu);
7740	}
7741
7742	if (rcStrict == VINF_IEM_RAISED_XCPT)
7743	{
7744	rcStrict = VINF_SUCCESS;
7745	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7746	}
7747	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7748	return VBOXSTRICTRC_TODO(rcStrict);
7749	}
7750
7751
7752	/**
7753	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7754	*/
7755	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7756	{
7757	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7758
7759	VBOXSTRICTRC rcStrict;
7760	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7761	if (fSupportsNextRipSave)
7762	{
7763	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7764	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7765	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7766	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7767	}
7768	else
7769	{
7770	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7771	rcStrict = IEMExecOne(pVCpu);
7772	}
7773
7774	if (rcStrict == VINF_IEM_RAISED_XCPT)
7775	{
7776	rcStrict = VINF_SUCCESS;
7777	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7778	}
7779	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7780	return VBOXSTRICTRC_TODO(rcStrict);
7781	}
7782
7783
7784	/**
7785	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7786	*/
7787	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7788	{
7789	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7790	/* We shall import the entire state here, just in case we enter and continue execution of
7791	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
7792	could lose lose part of CPU state. */
7793	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7794
7795	VBOXSTRICTRC rcStrict;
7796	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7797	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
7798	if (fSupportsNextRipSave)
7799	{
7800	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7801	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7802	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7803	}
7804	else
7805	{
7806	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
7807	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
7808	instruction itself, see @bugref{7243#c126} */
7809	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
7810	}
7811	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
7812
7813	if (rcStrict == VINF_SUCCESS)
7814	{
7815	rcStrict = VINF_SVM_VMRUN;
7816	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
7817	}
7818	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7819	{
7820	rcStrict = VINF_SUCCESS;
7821	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7822	}
7823	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7824	return VBOXSTRICTRC_TODO(rcStrict);
7825	}
7826
7827
7828	/**
7829	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7830	* Unconditional \#VMEXIT.
7831	*/
7832	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7833	{
7834	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7835	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7836
7837	if (pVCpu->hm.s.Event.fPending)
7838	{
7839	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7840	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7841	}
7842
7843	hmR0SvmSetPendingXcptDB(pVCpu);
7844	return VINF_SUCCESS;
7845	}
7846
7847
7848	/**
7849	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7850	* Conditional \#VMEXIT.
7851	*/
7852	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7853	{
7854	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7855	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7856
7857	SVMEVENT Event;
7858	Event.u = 0;
7859	Event.n.u1Valid = 1;
7860	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7861	Event.n.u8Vector = X86_XCPT_BP;
7862	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7863	return VINF_SUCCESS;
7864	}
7865	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
7866
7867	/** @} */
7868

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 83029

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