HMSVMR0.cpp@ 87561

Last change on this file since 87561 was 87561, checked in by vboxsync, 4 years ago
VMM/HMVMX: Tidied up HM some more. bugref:9217
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1	/* $Id: HMSVMR0.cpp 87561 2021-02-03 11:43:51Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vmcc.h>
37	#include <VBox/err.h>
38	#include "HMSVMR0.h"
39	#include "dtrace/VBoxVMM.h"
40
41	#ifdef DEBUG_ramshankar
42	# define HMSVM_SYNC_FULL_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll); \
65	if ((u64ExitCode) == SVM_EXIT_NPF) \
66	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
67	else \
68	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
69	} while (0)
70	# endif
71	#else
72	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
73	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
74	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
75	# endif
76	#endif /* !VBOX_WITH_STATISTICS */
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static VBOXSTRICTRC
81
82	/**
83	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
84	* guest using hardware-assisted SVM.
85	*
86	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
87	* are swapped and restored across the world-switch and also registers like
88	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
89	* \#VMEXIT.
90	*/
91	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
92	\| CPUMCTX_EXTRN_RFLAGS \
93	\| CPUMCTX_EXTRN_RAX \
94	\| CPUMCTX_EXTRN_RSP \
95	\| CPUMCTX_EXTRN_SREG_MASK \
96	\| CPUMCTX_EXTRN_CR0 \
97	\| CPUMCTX_EXTRN_CR2 \
98	\| CPUMCTX_EXTRN_CR3 \
99	\| CPUMCTX_EXTRN_TABLE_MASK \
100	\| CPUMCTX_EXTRN_DR6 \
101	\| CPUMCTX_EXTRN_DR7 \
102	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
103	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
104	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
105	\| CPUMCTX_EXTRN_HWVIRT \
106	\| CPUMCTX_EXTRN_HM_SVM_MASK)
107
108	/**
109	* Subset of the guest-CPU state that is shared between the guest and host.
110	*/
111	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
112
113	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
114	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
115	do { \
116	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
117	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
118	} while (0)
119
120	/** Assert that the required state bits are fetched. */
121	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
122	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
123	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
124
125	/** Assert that preemption is disabled or covered by thread-context hooks. */
126	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
127	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
128
129	/** Assert that we haven't migrated CPUs when thread-context hooks are not
130	* used. */
131	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
132	\|\| (a_pVCpu)->hmr0.s.idEnteredCpu == RTMpCpuId(), \
133	("Illegal migration! Entered on CPU %u Current %u\n", \
134	(a_pVCpu)->hmr0.s.idEnteredCpu, RTMpCpuId()));
135
136	/** Assert that we're not executing a nested-guest. */
137	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
139	#else
140	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
141	#endif
142
143	/** Assert that we're executing a nested-guest. */
144	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
145	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
146	#else
147	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
148	#endif
149
150	/** Macro for checking and returning from the using function for
151	* \#VMEXIT intercepts that maybe caused during delivering of another
152	* event in the guest. */
153	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
154	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
155	do \
156	{ \
157	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
158	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
159	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
160	else if ( rc == VINF_EM_RESET \
161	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
162	{ \
163	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
164	return IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0); \
165	} \
166	else \
167	return rc; \
168	} while (0)
169	#else
170	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
171	do \
172	{ \
173	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
174	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
175	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
176	else \
177	return rc; \
178	} while (0)
179	#endif
180
181	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
182	* instruction that exited. */
183	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
184	do { \
185	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
186	(a_rc) = VINF_EM_DBG_STEPPED; \
187	} while (0)
188
189	/** Validate segment descriptor granularity bit. */
190	#ifdef VBOX_STRICT
191	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
192	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
193	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
194	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
195	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
196	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
197	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
198	#else
199	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
200	#endif
201
202	/**
203	* Exception bitmap mask for all contributory exceptions.
204	*
205	* Page fault is deliberately excluded here as it's conditional as to whether
206	* it's contributory or benign. Page faults are handled separately.
207	*/
208	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
209	\| RT_BIT(X86_XCPT_DE))
210
211	/**
212	* Mandatory/unconditional guest control intercepts.
213	*
214	* SMIs can and do happen in normal operation. We need not intercept them
215	* while executing the guest (or nested-guest).
216	*/
217	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
218	\| SVM_CTRL_INTERCEPT_NMI \
219	\| SVM_CTRL_INTERCEPT_INIT \
220	\| SVM_CTRL_INTERCEPT_RDPMC \
221	\| SVM_CTRL_INTERCEPT_CPUID \
222	\| SVM_CTRL_INTERCEPT_RSM \
223	\| SVM_CTRL_INTERCEPT_HLT \
224	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
225	\| SVM_CTRL_INTERCEPT_MSR_PROT \
226	\| SVM_CTRL_INTERCEPT_INVLPGA \
227	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
228	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
229	\| SVM_CTRL_INTERCEPT_VMRUN \
230	\| SVM_CTRL_INTERCEPT_SKINIT \
231	\| SVM_CTRL_INTERCEPT_WBINVD \
232	\| SVM_CTRL_INTERCEPT_MONITOR \
233	\| SVM_CTRL_INTERCEPT_MWAIT \
234	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
235	\| SVM_CTRL_INTERCEPT_XSETBV)
236
237	/** @name VMCB Clean Bits.
238	*
239	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
240	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
241	* memory.
242	*
243	* @{ */
244	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
245	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
246	/** I/O permission bitmap, MSR permission bitmap. */
247	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
248	/** ASID. */
249	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
250	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
251	V_INTR_VECTOR. */
252	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
253	/** Nested Paging: Nested CR3 (nCR3), PAT. */
254	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
255	/** Control registers (CR0, CR3, CR4, EFER). */
256	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
257	/** Debug registers (DR6, DR7). */
258	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
259	/** GDT, IDT limit and base. */
260	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
261	/** Segment register: CS, SS, DS, ES limit and base. */
262	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
263	/** CR2.*/
264	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
265	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
266	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
267	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
268	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
269	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
270	/** Mask of all valid VMCB Clean bits. */
271	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
272	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
273	\| HMSVM_VMCB_CLEAN_ASID \
274	\| HMSVM_VMCB_CLEAN_INT_CTRL \
275	\| HMSVM_VMCB_CLEAN_NP \
276	\| HMSVM_VMCB_CLEAN_CRX_EFER \
277	\| HMSVM_VMCB_CLEAN_DRX \
278	\| HMSVM_VMCB_CLEAN_DT \
279	\| HMSVM_VMCB_CLEAN_SEG \
280	\| HMSVM_VMCB_CLEAN_CR2 \
281	\| HMSVM_VMCB_CLEAN_LBR \
282	\| HMSVM_VMCB_CLEAN_AVIC)
283	/** @} */
284
285	/** @name SVM transient.
286	*
287	* A state structure for holding miscellaneous information across AMD-V
288	* VMRUN/\#VMEXIT operation, restored after the transition.
289	*
290	* @{ */
291	typedef struct SVMTRANSIENT
292	{
293	/** The host's rflags/eflags. */
294	RTCCUINTREG fEFlags;
295	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
296	uint64_t u64ExitCode;
297
298	/** The guest's TPR value used for TPR shadowing. */
299	uint8_t u8GuestTpr;
300	/** Alignment. */
301	uint8_t abAlignment0[7];
302
303	/** Pointer to the currently executing VMCB. */
304	PSVMVMCB pVmcb;
305
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308	/** Whether the guest debug state was active at the time of \#VMEXIT. */
309	bool fWasGuestDebugStateActive;
310	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
311	bool fWasHyperDebugStateActive;
312	/** Whether the TSC offset mode needs to be updated. */
313	bool fUpdateTscOffsetting;
314	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
315	bool fRestoreTscAuxMsr;
316	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
317	* contributary exception or a page-fault. */
318	bool fVectoringDoublePF;
319	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
320	* external interrupt or NMI. */
321	bool fVectoringPF;
322	/** Padding. */
323	bool afPadding0;
324	} SVMTRANSIENT;
325	/** Pointer to SVM transient state. */
326	typedef SVMTRANSIENT *PSVMTRANSIENT;
327	/** Pointer to a const SVM transient state. */
328	typedef const SVMTRANSIENT *PCSVMTRANSIENT;
329
330	AssertCompileSizeAlignment(SVMTRANSIENT, sizeof(uint64_t));
331	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
332	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
333	/** @} */
334
335	/**
336	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
337	*/
338	typedef enum SVMMSREXITREAD
339	{
340	/** Reading this MSR causes a \#VMEXIT. */
341	SVMMSREXIT_INTERCEPT_READ = 0xb,
342	/** Reading this MSR does not cause a \#VMEXIT. */
343	SVMMSREXIT_PASSTHRU_READ
344	} SVMMSREXITREAD;
345
346	/**
347	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
348	*/
349	typedef enum SVMMSREXITWRITE
350	{
351	/** Writing to this MSR causes a \#VMEXIT. */
352	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
353	/** Writing to this MSR does not cause a \#VMEXIT. */
354	SVMMSREXIT_PASSTHRU_WRITE
355	} SVMMSREXITWRITE;
356
357	/**
358	* SVM \#VMEXIT handler.
359	*
360	* @returns Strict VBox status code.
361	* @param pVCpu The cross context virtual CPU structure.
362	* @param pSvmTransient Pointer to the SVM-transient structure.
363	*/
364	typedef VBOXSTRICTRC FNSVMEXITHANDLER(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
365
366
367	/*********************************************************************************************************************************
368	* Internal Functions *
369	*********************************************************************************************************************************/
370	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu);
371	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState);
372
373
374	/** @name \#VMEXIT handlers.
375	* @{
376	*/
377	static FNSVMEXITHANDLER hmR0SvmExitIntr;
378	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
379	static FNSVMEXITHANDLER hmR0SvmExitInvd;
380	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
381	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
382	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
383	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
384	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
385	static FNSVMEXITHANDLER hmR0SvmExitHlt;
386	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
387	static FNSVMEXITHANDLER hmR0SvmExitMwait;
388	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
389	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
390	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
391	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
392	static FNSVMEXITHANDLER hmR0SvmExitMsr;
393	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
394	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
395	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
396	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
397	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
398	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
399	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
400	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
401	static FNSVMEXITHANDLER hmR0SvmExitPause;
402	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
403	static FNSVMEXITHANDLER hmR0SvmExitIret;
404	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
405	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
406	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
407	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
408	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
409	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
410	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
411	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
412	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
413	#endif
414	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
415	static FNSVMEXITHANDLER hmR0SvmExitClgi;
416	static FNSVMEXITHANDLER hmR0SvmExitStgi;
417	static FNSVMEXITHANDLER hmR0SvmExitVmload;
418	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
419	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
420	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
421	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
422	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
423	#endif
424	/** @} */
425
426	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
427	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
428	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
429	#endif
430
431
432	/*********************************************************************************************************************************
433	* Global Variables *
434	*********************************************************************************************************************************/
435	/** Ring-0 memory object for the IO bitmap. */
436	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
437	/** Physical address of the IO bitmap. */
438	static RTHCPHYS g_HCPhysIOBitmap;
439	/** Pointer to the IO bitmap. */
440	static R0PTRTYPE(void *) g_pvIOBitmap;
441
442	#ifdef VBOX_STRICT
443	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
444	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
445	# define HMSVM_LOG_CS RT_BIT_32(2)
446	# define HMSVM_LOG_SS RT_BIT_32(3)
447	# define HMSVM_LOG_FS RT_BIT_32(4)
448	# define HMSVM_LOG_GS RT_BIT_32(5)
449	# define HMSVM_LOG_LBR RT_BIT_32(6)
450	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
451	\| HMSVM_LOG_CR_REGS \
452	\| HMSVM_LOG_CS \
453	\| HMSVM_LOG_SS \
454	\| HMSVM_LOG_FS \
455	\| HMSVM_LOG_GS \
456	\| HMSVM_LOG_LBR)
457
458	/**
459	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
460	*
461	* @param pVCpu The cross context virtual CPU structure.
462	* @param pVmcb Pointer to the VM control block.
463	* @param pszPrefix Log prefix.
464	* @param fFlags Log flags, see HMSVM_LOG_XXX.
465	* @param uVerbose The verbosity level, currently unused.
466	*/
467	static void hmR0SvmLogState(PVMCPUCC pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
468	{
469	RT_NOREF2(pVCpu, uVerbose);
470	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
471
472	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
473	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
474
475	if (fFlags & HMSVM_LOG_RBP_RSP)
476	{
477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
478	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
479	}
480
481	if (fFlags & HMSVM_LOG_CR_REGS)
482	{
483	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
484	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
485	}
486
487	if (fFlags & HMSVM_LOG_CS)
488	{
489	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
490	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
491	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
492	}
493	if (fFlags & HMSVM_LOG_SS)
494	{
495	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
496	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
497	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
498	}
499	if (fFlags & HMSVM_LOG_FS)
500	{
501	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
502	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
503	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
504	}
505	if (fFlags & HMSVM_LOG_GS)
506	{
507	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
508	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
509	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
510	}
511
512	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
513	if (fFlags & HMSVM_LOG_LBR)
514	{
515	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
516	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
517	}
518	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
519	}
520	#endif /* VBOX_STRICT */
521
522
523	/**
524	* Sets up and activates AMD-V on the current CPU.
525	*
526	* @returns VBox status code.
527	* @param pHostCpu The HM physical-CPU structure.
528	* @param pVM The cross context VM structure. Can be
529	* NULL after a resume!
530	* @param pvCpuPage Pointer to the global CPU page.
531	* @param HCPhysCpuPage Physical address of the global CPU page.
532	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
533	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
534	* unused).
535	*/
536	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
537	PCSUPHWVIRTMSRS pHwvirtMsrs)
538	{
539	Assert(!fEnabledByHost);
540	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
541	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
542	Assert(pvCpuPage); NOREF(pvCpuPage);
543	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
544
545	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
546
547	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
549
550	/*
551	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
552	*/
553	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
554	if (u64HostEfer & MSR_K6_EFER_SVME)
555	{
556	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
557	if ( pVM
558	&& pVM->hm.s.svm.fIgnoreInUseError)
559	pHostCpu->fIgnoreAMDVInUseError = true;
560
561	if (!pHostCpu->fIgnoreAMDVInUseError)
562	{
563	ASMSetFlags(fEFlags);
564	return VERR_SVM_IN_USE;
565	}
566	}
567
568	/* Turn on AMD-V in the EFER MSR. */
569	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
570
571	/* Write the physical page address where the CPU will store the host state while executing the VM. */
572	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
573
574	/* Restore interrupts. */
575	ASMSetFlags(fEFlags);
576
577	/*
578	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
579	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
580	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
581	* entirely with before executing any guest code.
582	*/
583	pHostCpu->fFlushAsidBeforeUse = true;
584
585	/*
586	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
587	*/
588	++pHostCpu->cTlbFlushes;
589
590	return VINF_SUCCESS;
591	}
592
593
594	/**
595	* Deactivates AMD-V on the current CPU.
596	*
597	* @returns VBox status code.
598	* @param pHostCpu The HM physical-CPU structure.
599	* @param pvCpuPage Pointer to the global CPU page.
600	* @param HCPhysCpuPage Physical address of the global CPU page.
601	*/
602	VMMR0DECL(int) SVMR0DisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
603	{
604	RT_NOREF1(pHostCpu);
605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
606	AssertReturn( HCPhysCpuPage
607	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
608	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
609
610	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
611	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
612
613	/* Turn off AMD-V in the EFER MSR. */
614	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
615	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
616
617	/* Invalidate host state physical address. */
618	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
619
620	/* Restore interrupts. */
621	ASMSetFlags(fEFlags);
622
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* Does global AMD-V initialization (called during module initialization).
629	*
630	* @returns VBox status code.
631	*/
632	VMMR0DECL(int) SVMR0GlobalInit(void)
633	{
634	/*
635	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
636	* intercept all IO accesses, it's done once globally here instead of per-VM.
637	*/
638	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
639	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
640	if (RT_FAILURE(rc))
641	return rc;
642
643	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
644	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
645
646	/* Set all bits to intercept all IO accesses. */
647	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Does global AMD-V termination (called during module termination).
655	*/
656	VMMR0DECL(void) SVMR0GlobalTerm(void)
657	{
658	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
661	g_pvIOBitmap = NULL;
662	g_HCPhysIOBitmap = 0;
663	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666
667
668	/**
669	* Frees any allocated per-VCPU structures for a VM.
670	*
671	* @param pVM The cross context VM structure.
672	*/
673	DECLINLINE(void) hmR0SvmFreeStructs(PVMCC pVM)
674	{
675	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
676	{
677	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
678	AssertPtr(pVCpu);
679
680	if (pVCpu->hmr0.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
681	{
682	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcbHost, false);
683	pVCpu->hmr0.s.svm.HCPhysVmcbHost = 0;
684	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
685	}
686
687	if (pVCpu->hmr0.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
688	{
689	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcb, false);
690	pVCpu->hmr0.s.svm.pVmcb = NULL;
691	pVCpu->hmr0.s.svm.HCPhysVmcb = 0;
692	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
693	}
694
695	if (pVCpu->hmr0.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
696	{
697	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, false);
698	pVCpu->hmr0.s.svm.pvMsrBitmap = NULL;
699	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = 0;
700	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
701	}
702	}
703	}
704
705
706	/**
707	* Sets pfnVMRun to the best suited variant.
708	*
709	* This must be called whenever anything changes relative to the SVMR0VMRun
710	* variant selection:
711	* - pVCpu->hm.s.fLoadSaveGuestXcr0
712	* - CPUMCTX_WSF_IBPB_ENTRY in pVCpu->cpum.GstCtx.fWorldSwitcher
713	* - CPUMCTX_WSF_IBPB_EXIT in pVCpu->cpum.GstCtx.fWorldSwitcher
714	* - Perhaps: CPUMIsGuestFPUStateActive() (windows only)
715	* - Perhaps: CPUMCTX.fXStateMask (windows only)
716	*
717	* We currently ASSUME that neither CPUMCTX_WSF_IBPB_ENTRY nor
718	* CPUMCTX_WSF_IBPB_EXIT cannot be changed at runtime.
719	*/
720	static void hmR0SvmUpdateVmRunFunction(PVMCPUCC pVCpu)
721	{
722	static const struct CLANGWORKAROUND { PFNHMSVMVMRUN pfn; } s_aHmR0SvmVmRunFunctions[] =
723	{
724	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit },
725	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit },
726	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit },
727	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit },
728	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit },
729	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit },
730	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit },
731	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit },
732	};
733	uintptr_t const idx = (pVCpu->hmr0.s.fLoadSaveGuestXcr0 ? 1 : 0)
734	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_ENTRY ? 2 : 0)
735	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_EXIT ? 4 : 0);
736	PFNHMSVMVMRUN const pfnVMRun = s_aHmR0SvmVmRunFunctions[idx].pfn;
737	if (pVCpu->hmr0.s.svm.pfnVMRun != pfnVMRun)
738	pVCpu->hmr0.s.svm.pfnVMRun = pfnVMRun;
739	}
740
741
742	/**
743	* Selector FNHMSVMVMRUN implementation.
744	*/
745	static DECLCALLBACK(int) hmR0SvmVMRunSelector(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB)
746	{
747	hmR0SvmUpdateVmRunFunction(pVCpu);
748	return pVCpu->hmr0.s.svm.pfnVMRun(pVM, pVCpu, HCPhysVMCB);
749	}
750
751
752	/**
753	* Does per-VM AMD-V initialization.
754	*
755	* @returns VBox status code.
756	* @param pVM The cross context VM structure.
757	*/
758	VMMR0DECL(int) SVMR0InitVM(PVMCC pVM)
759	{
760	int rc = VERR_INTERNAL_ERROR_5;
761
762	/*
763	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
764	*/
765	uint32_t u32Family;
766	uint32_t u32Model;
767	uint32_t u32Stepping;
768	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
769	{
770	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
771	pVM->hmr0.s.svm.fAlwaysFlushTLB = true;
772	}
773
774	/*
775	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
776	*/
777	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
778	{
779	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
780	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
781	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
782	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
783	}
784
785	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
786	{
787	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
788
789	/*
790	* Initialize the hardware-assisted SVM guest-execution handler.
791	* We now use a single handler for both 32-bit and 64-bit guests, see @bugref{6208#c73}.
792	*/
793	pVCpu->hmr0.s.svm.pfnVMRun = hmR0SvmVMRunSelector;
794
795	/*
796	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
797	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
798	*/
799	/** @todo Does this need to be below 4G? */
800	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
801	if (RT_FAILURE(rc))
802	goto failure_cleanup;
803
804	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcbHost);
805	pVCpu->hmr0.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcbHost, 0 /* iPage */);
806	Assert(pVCpu->hmr0.s.svm.HCPhysVmcbHost < _4G);
807	ASMMemZeroPage(pvVmcbHost);
808
809	/*
810	* Allocate one page for the guest-state VMCB.
811	*/
812	/** @todo Does this need to be below 4G? */
813	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
814	if (RT_FAILURE(rc))
815	goto failure_cleanup;
816
817	pVCpu->hmr0.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcb);
818	pVCpu->hmr0.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcb, 0 /* iPage */);
819	Assert(pVCpu->hmr0.s.svm.HCPhysVmcb < _4G);
820	ASMMemZeroPage(pVCpu->hmr0.s.svm.pVmcb);
821
822	/*
823	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
824	* SVM to not require one.
825	*/
826	/** @todo Does this need to be below 4G? */
827	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
828	false /* fExecutable */);
829	if (RT_FAILURE(rc))
830	goto failure_cleanup;
831
832	pVCpu->hmr0.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjMsrBitmap);
833	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
834	/* Set all bits to intercept all MSR accesses (changed later on). */
835	ASMMemFill32(pVCpu->hmr0.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
836	}
837
838	return VINF_SUCCESS;
839
840	failure_cleanup:
841	hmR0SvmFreeStructs(pVM);
842	return rc;
843	}
844
845
846	/**
847	* Does per-VM AMD-V termination.
848	*
849	* @returns VBox status code.
850	* @param pVM The cross context VM structure.
851	*/
852	VMMR0DECL(int) SVMR0TermVM(PVMCC pVM)
853	{
854	hmR0SvmFreeStructs(pVM);
855	return VINF_SUCCESS;
856	}
857
858
859	/**
860	* Returns whether the VMCB Clean Bits feature is supported.
861	*
862	* @returns @c true if supported, @c false otherwise.
863	* @param pVCpu The cross context virtual CPU structure.
864	* @param fIsNestedGuest Whether we are currently executing the nested-guest.
865	*/
866	DECL_FORCE_INLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPUCC pVCpu, bool fIsNestedGuest)
867	{
868	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
869	bool const fHostVmcbCleanBits = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
870	if (!fIsNestedGuest)
871	return fHostVmcbCleanBits;
872	return fHostVmcbCleanBits && pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
873	}
874
875
876	/**
877	* Returns whether the decode assists feature is supported.
878	*
879	* @returns @c true if supported, @c false otherwise.
880	* @param pVCpu The cross context virtual CPU structure.
881	*/
882	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPUCC pVCpu)
883	{
884	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
885	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
886	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
887	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
888	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
889	#endif
890	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
891	}
892
893
894	/**
895	* Returns whether the NRIP_SAVE feature is supported.
896	*
897	* @returns @c true if supported, @c false otherwise.
898	* @param pVCpu The cross context virtual CPU structure.
899	*/
900	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPUCC pVCpu)
901	{
902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
903	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
904	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
905	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
906	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
907	#endif
908	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
909	}
910
911
912	/**
913	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
914	*
915	* @param pVCpu The cross context virtual CPU structure.
916	* @param pbMsrBitmap Pointer to the MSR bitmap.
917	* @param idMsr The MSR for which the permissions are being set.
918	* @param enmRead MSR read permissions.
919	* @param enmWrite MSR write permissions.
920	*
921	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
922	* caller needs to take care of this.
923	*/
924	static void hmR0SvmSetMsrPermission(PVMCPUCC pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
925	SVMMSREXITWRITE enmWrite)
926	{
927	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
928	uint16_t offMsrpm;
929	uint8_t uMsrpmBit;
930	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
931	AssertRC(rc);
932
933	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
934	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
935
936	pbMsrBitmap += offMsrpm;
937	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
938	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
939	else
940	{
941	if (!fInNestedGuestMode)
942	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
943	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
944	else
945	{
946	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
947	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
948	pbNstGstMsrBitmap += offMsrpm;
949	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
950	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
951	else
952	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
953	}
954	#endif
955	}
956
957	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
958	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
959	else
960	{
961	if (!fInNestedGuestMode)
962	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
963	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
964	else
965	{
966	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
967	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
968	pbNstGstMsrBitmap += offMsrpm;
969	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
970	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
971	else
972	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
973	}
974	#endif
975	}
976	}
977
978
979	/**
980	* Sets up AMD-V for the specified VM.
981	* This function is only called once per-VM during initalization.
982	*
983	* @returns VBox status code.
984	* @param pVM The cross context VM structure.
985	*/
986	VMMR0DECL(int) SVMR0SetupVM(PVMCC pVM)
987	{
988	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
989	AssertReturn(pVM, VERR_INVALID_PARAMETER);
990
991	/*
992	* Validate and copy over some parameters.
993	*/
994	AssertReturn(pVM->hm.s.svm.fSupported, VERR_INCOMPATIBLE_CONFIG);
995	bool const fNestedPaging = pVM->hm.s.fNestedPagingCfg;
996	AssertReturn( !fNestedPaging
997	\|\| (pVM->hm.s.svm.fFeaturesForRing3 & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
998	VERR_INCOMPATIBLE_CONFIG);
999	pVM->hmr0.s.fNestedPaging = fNestedPaging;
1000	pVM->hmr0.s.fAllow64BitGuests = pVM->hm.s.fAllow64BitGuestsCfg;
1001
1002	/*
1003	* Determin some configuration parameters.
1004	*/
1005	bool const fPauseFilter = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1006	bool const fPauseFilterThreshold = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1007	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
1008
1009	bool const fLbrVirt = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1010	bool const fUseLbrVirt = fLbrVirt && pVM->hm.s.svm.fLbrVirt; /** @todo IEM implementation etc. */
1011
1012	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1013	bool const fVirtVmsaveVmload = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1014	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && fNestedPaging;
1015
1016	bool const fVGif = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1017	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
1018	#endif
1019
1020	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
1021	PSVMVMCB pVmcb0 = pVCpu0->hmr0.s.svm.pVmcb;
1022	AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
1023	PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
1024
1025	/* Always trap #AC for reasons of security. */
1026	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
1027
1028	/* Always trap #DB for reasons of security. */
1029	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
1030
1031	/* Trap exceptions unconditionally (debug purposes). */
1032	#ifdef HMSVM_ALWAYS_TRAP_PF
1033	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_PF);
1034	#endif
1035	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1036	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
1037	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_BP)
1038	\| RT_BIT_32(X86_XCPT_DE)
1039	\| RT_BIT_32(X86_XCPT_NM)
1040	\| RT_BIT_32(X86_XCPT_UD)
1041	\| RT_BIT_32(X86_XCPT_NP)
1042	\| RT_BIT_32(X86_XCPT_SS)
1043	\| RT_BIT_32(X86_XCPT_GP)
1044	\| RT_BIT_32(X86_XCPT_PF)
1045	\| RT_BIT_32(X86_XCPT_MF)
1046	;
1047	#endif
1048
1049	/* Apply the exceptions intercepts needed by the GIM provider. */
1050	if (pVCpu0->hm.s.fGIMTrapXcptUD \|\| pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1051	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1052
1053	/* The mesa 3d driver hack needs #GP. */
1054	if (pVCpu0->hm.s.fTrapXcptGpForLovelyMesaDrv)
1055	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
1056
1057	/* Set up unconditional intercepts and conditions. */
1058	pVmcbCtrl0->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
1059	\| SVM_CTRL_INTERCEPT_VMMCALL
1060	\| SVM_CTRL_INTERCEPT_VMSAVE
1061	\| SVM_CTRL_INTERCEPT_VMLOAD
1062	\| SVM_CTRL_INTERCEPT_CLGI
1063	\| SVM_CTRL_INTERCEPT_STGI;
1064
1065	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1066	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1067	#endif
1068
1069	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1070	if (pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm)
1071	{
1072	/* Virtualized VMSAVE/VMLOAD. */
1073	if (fUseVirtVmsaveVmload)
1074	{
1075	pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload = 1;
1076	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_VMSAVE
1077	\| SVM_CTRL_INTERCEPT_VMLOAD);
1078	}
1079	else
1080	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1081
1082	/* Virtual GIF. */
1083	if (fUseVGif)
1084	{
1085	pVmcbCtrl0->IntCtrl.n.u1VGifEnable = 1;
1086	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_CLGI
1087	\| SVM_CTRL_INTERCEPT_STGI);
1088	}
1089	else
1090	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1091	}
1092	else
1093	#endif
1094	{
1095	Assert(!pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm);
1096	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1097	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1098	}
1099
1100	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1101	pVmcbCtrl0->u16InterceptWrCRx = RT_BIT(4);
1102
1103	/* Intercept all DRx reads and writes by default. Changed later on. */
1104	pVmcbCtrl0->u16InterceptRdDRx = 0xffff;
1105	pVmcbCtrl0->u16InterceptWrDRx = 0xffff;
1106
1107	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1108	pVmcbCtrl0->IntCtrl.n.u1VIntrMasking = 1;
1109
1110	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1111	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1112	pVmcbCtrl0->IntCtrl.n.u1IgnoreTPR = 1;
1113
1114	/* Set the IO permission bitmap physical addresses. */
1115	pVmcbCtrl0->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1116
1117	/* LBR virtualization. */
1118	pVmcbCtrl0->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1119
1120	/* The host ASID MBZ, for the guest start with 1. */
1121	pVmcbCtrl0->TLBCtrl.n.u32ASID = 1;
1122
1123	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1124	pVmcbCtrl0->NestedPagingCtrl.n.u1NestedPaging = fNestedPaging;
1125
1126	/* Without Nested Paging, we need additionally intercepts. */
1127	if (!fNestedPaging)
1128	{
1129	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1130	pVmcbCtrl0->u16InterceptRdCRx \|= RT_BIT(3);
1131	pVmcbCtrl0->u16InterceptWrCRx \|= RT_BIT(3);
1132
1133	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1134	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1135	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1136
1137	/* Page faults must be intercepted to implement shadow paging. */
1138	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1139	}
1140
1141	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1142	if (fUsePauseFilter)
1143	{
1144	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1145	pVmcbCtrl0->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1146	if (fPauseFilterThreshold)
1147	pVmcbCtrl0->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1148	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1149	}
1150
1151	/*
1152	* Setup the MSR permission bitmap.
1153	* The following MSRs are saved/restored automatically during the world-switch.
1154	* Don't intercept guest read/write accesses to these MSRs.
1155	*/
1156	uint8_t pbMsrBitmap0 = (uint8_t )pVCpu0->hmr0.s.svm.pvMsrBitmap;
1157	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1158	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1159	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1160	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1161	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1162	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1163	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1164	if (!pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1165	{
1166	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1167	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1168	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1169	}
1170	else
1171	{
1172	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1173	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1174	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1175	}
1176	pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hmr0.s.svm.HCPhysMsrBitmap;
1177
1178	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1179	Assert(pVmcbCtrl0->u32VmcbCleanBits == 0);
1180
1181	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1182	{
1183	PVMCPUCC pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
1184	PSVMVMCB pVmcbCur = pVCpuCur->hmr0.s.svm.pVmcb;
1185	AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
1186	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1187
1188	/* Copy the VMCB control area. */
1189	memcpy(pVmcbCtrlCur, pVmcbCtrl0, sizeof(*pVmcbCtrlCur));
1190
1191	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1192	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hmr0.s.svm.pvMsrBitmap;
1193	memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1194	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hmr0.s.svm.HCPhysMsrBitmap;
1195
1196	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1197	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1198
1199	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1200	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu0->hm.s.fGIMTrapXcptUD);
1201	}
1202
1203	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1204	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1205	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1206	#else
1207	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1208	#endif
1209	return VINF_SUCCESS;
1210	}
1211
1212
1213	/**
1214	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1215	*
1216	* @returns Pointer to the current context VMCB.
1217	* @param pVCpu The cross context virtual CPU structure.
1218	*/
1219	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPUCC pVCpu)
1220	{
1221	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1222	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1223	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1224	#endif
1225	return pVCpu->hmr0.s.svm.pVmcb;
1226	}
1227
1228
1229	/**
1230	* Gets a pointer to the nested-guest VMCB cache.
1231	*
1232	* @returns Pointer to the nested-guest VMCB cache.
1233	* @param pVCpu The cross context virtual CPU structure.
1234	*/
1235	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPUCC pVCpu)
1236	{
1237	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1238	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1239	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1240	#else
1241	RT_NOREF(pVCpu);
1242	return NULL;
1243	#endif
1244	}
1245
1246
1247	/**
1248	* Invalidates a guest page by guest virtual address.
1249	*
1250	* @returns VBox status code.
1251	* @param pVCpu The cross context virtual CPU structure.
1252	* @param GCVirt Guest virtual address of the page to invalidate.
1253	*/
1254	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1255	{
1256	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1257
1258	bool const fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH) \|\| pVCpu->CTX_SUFF(pVM)->hmr0.s.svm.fAlwaysFlushTLB;
1259
1260	/* Skip it if a TLB flush is already pending. */
1261	if (!fFlushPending)
1262	{
1263	Log4Func(("%#RGv\n", GCVirt));
1264
1265	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1266	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1267
1268	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1269	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1270	}
1271	return VINF_SUCCESS;
1272	}
1273
1274
1275	/**
1276	* Flushes the appropriate tagged-TLB entries.
1277	*
1278	* @param pHostCpu The HM physical-CPU structure.
1279	* @param pVCpu The cross context virtual CPU structure.
1280	* @param pVmcb Pointer to the VM control block.
1281	*/
1282	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1283	{
1284	/*
1285	* Force a TLB flush for the first world switch if the current CPU differs from the one
1286	* we ran on last. This can happen both for start & resume due to long jumps back to
1287	* ring-3.
1288	*
1289	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1290	* correlation between it and the physical CPU.
1291	*
1292	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1293	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1294	*/
1295	bool fNewAsid = false;
1296	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1297	if ( pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
1298	\|\| pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes
1299	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1300	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1301	#endif
1302	)
1303	{
1304	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1305	pVCpu->hmr0.s.fForceTLBFlush = true;
1306	fNewAsid = true;
1307	}
1308
1309	/* Set TLB flush state as checked until we return from the world switch. */
1310	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1311
1312	/* Check for explicit TLB flushes. */
1313	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1314	{
1315	pVCpu->hmr0.s.fForceTLBFlush = true;
1316	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1317	}
1318
1319	/*
1320	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1321	* This Host CPU requirement takes precedence.
1322	*/
1323	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1324	if (pVM->hmr0.s.svm.fAlwaysFlushTLB)
1325	{
1326	pHostCpu->uCurrentAsid = 1;
1327	pVCpu->hmr0.s.uCurrentAsid = 1;
1328	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1329	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1330	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1331
1332	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1333	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1334	}
1335	else
1336	{
1337	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1338	if (pVCpu->hmr0.s.fForceTLBFlush)
1339	{
1340	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1341	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1342
1343	if (fNewAsid)
1344	{
1345	++pHostCpu->uCurrentAsid;
1346
1347	bool fHitASIDLimit = false;
1348	if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid)
1349	{
1350	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1351	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1352	fHitASIDLimit = true;
1353	}
1354
1355	if ( fHitASIDLimit
1356	\|\| pHostCpu->fFlushAsidBeforeUse)
1357	{
1358	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1359	pHostCpu->fFlushAsidBeforeUse = false;
1360	}
1361
1362	pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1363	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1364	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1365	}
1366	else
1367	{
1368	if (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1369	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1370	else
1371	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1372	}
1373
1374	pVCpu->hmr0.s.fForceTLBFlush = false;
1375	}
1376	}
1377
1378	/* Update VMCB with the ASID. */
1379	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hmr0.s.uCurrentAsid)
1380	{
1381	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hmr0.s.uCurrentAsid;
1382	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1383	}
1384
1385	AssertMsg(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu,
1386	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hmr0.s.idLastCpu, pHostCpu->idCpu));
1387	AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1388	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1389	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid,
1390	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1391	AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid,
1392	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
1393
1394	#ifdef VBOX_WITH_STATISTICS
1395	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1396	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1397	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1398	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1399	{
1400	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1401	}
1402	else
1403	{
1404	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1405	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1406	}
1407	#endif
1408	}
1409
1410
1411	/**
1412	* Sets an exception intercept in the specified VMCB.
1413	*
1414	* @param pVmcb Pointer to the VM control block.
1415	* @param uXcpt The exception (X86_XCPT_*).
1416	*/
1417	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1418	{
1419	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1420	{
1421	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1422	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1423	}
1424	}
1425
1426
1427	/**
1428	* Clears an exception intercept in the specified VMCB.
1429	*
1430	* @param pVCpu The cross context virtual CPU structure.
1431	* @param pVmcb Pointer to the VM control block.
1432	* @param uXcpt The exception (X86_XCPT_*).
1433	*
1434	* @remarks This takes into account if we're executing a nested-guest and only
1435	* removes the exception intercept if both the guest -and- nested-guest
1436	* are not intercepting it.
1437	*/
1438	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1439	{
1440	Assert(uXcpt != X86_XCPT_DB);
1441	Assert(uXcpt != X86_XCPT_AC);
1442	Assert(uXcpt != X86_XCPT_GP);
1443	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1444	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1445	{
1446	bool fRemove = true;
1447	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1448	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1449	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1450	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1451	{
1452	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1453	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1454	}
1455	# else
1456	RT_NOREF(pVCpu);
1457	# endif
1458	if (fRemove)
1459	{
1460	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1461	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1462	}
1463	}
1464	#else
1465	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1466	#endif
1467	}
1468
1469
1470	/**
1471	* Sets a control intercept in the specified VMCB.
1472	*
1473	* @param pVmcb Pointer to the VM control block.
1474	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1475	*/
1476	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1477	{
1478	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1479	{
1480	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1481	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1482	}
1483	}
1484
1485
1486	/**
1487	* Clears a control intercept in the specified VMCB.
1488	*
1489	* @returns @c true if the intercept is still set, @c false otherwise.
1490	* @param pVCpu The cross context virtual CPU structure.
1491	* @param pVmcb Pointer to the VM control block.
1492	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1493	*
1494	* @remarks This takes into account if we're executing a nested-guest and only
1495	* removes the control intercept if both the guest -and- nested-guest
1496	* are not intercepting it.
1497	*/
1498	static bool hmR0SvmClearCtrlIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1499	{
1500	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1501	{
1502	bool fRemove = true;
1503	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1504	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1505	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1506	{
1507	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1508	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1509	}
1510	#else
1511	RT_NOREF(pVCpu);
1512	#endif
1513	if (fRemove)
1514	{
1515	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1516	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1517	}
1518	}
1519
1520	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1521	}
1522
1523
1524	/**
1525	* Exports the guest (or nested-guest) CR0 into the VMCB.
1526	*
1527	* @param pVCpu The cross context virtual CPU structure.
1528	* @param pVmcb Pointer to the VM control block.
1529	*
1530	* @remarks This assumes we always pre-load the guest FPU.
1531	* @remarks No-long-jump zone!!!
1532	*/
1533	static void hmR0SvmExportGuestCR0(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1534	{
1535	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1536
1537	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1538	uint64_t const uGuestCr0 = pCtx->cr0;
1539	uint64_t uShadowCr0 = uGuestCr0;
1540
1541	/* Always enable caching. */
1542	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1543
1544	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1545	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1546	{
1547	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1548	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1549	}
1550
1551	/*
1552	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1553	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1554	* see @bugref{7243#c103}.
1555	*/
1556	if (!(uGuestCr0 & X86_CR0_NE))
1557	{
1558	uShadowCr0 \|= X86_CR0_NE;
1559	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1560	}
1561	else
1562	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1563
1564	/*
1565	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1566	*
1567	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1568	* see @bugref{6944}.
1569	*
1570	* We also don't ever want to honor weird things like cache disable from the guest.
1571	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1572	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1573	*/
1574	if (uShadowCr0 == uGuestCr0)
1575	{
1576	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1577	{
1578	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1579	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1580	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1581	}
1582	else
1583	{
1584	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1585	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1586	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1587	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1588	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1589	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1590	}
1591	}
1592	else
1593	{
1594	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1595	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1596	}
1597	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1598
1599	Assert(!RT_HI_U32(uShadowCr0));
1600	if (pVmcb->guest.u64CR0 != uShadowCr0)
1601	{
1602	pVmcb->guest.u64CR0 = uShadowCr0;
1603	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1604	}
1605	}
1606
1607
1608	/**
1609	* Exports the guest (or nested-guest) CR3 into the VMCB.
1610	*
1611	* @param pVCpu The cross context virtual CPU structure.
1612	* @param pVmcb Pointer to the VM control block.
1613	*
1614	* @remarks No-long-jump zone!!!
1615	*/
1616	static void hmR0SvmExportGuestCR3(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1617	{
1618	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1619
1620	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1621	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1622	if (pVM->hmr0.s.fNestedPaging)
1623	{
1624	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetHyperCR3(pVCpu);
1625	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1626	pVmcb->guest.u64CR3 = pCtx->cr3;
1627	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1628	}
1629	else
1630	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1631
1632	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1633	}
1634
1635
1636	/**
1637	* Exports the guest (or nested-guest) CR4 into the VMCB.
1638	*
1639	* @param pVCpu The cross context virtual CPU structure.
1640	* @param pVmcb Pointer to the VM control block.
1641	*
1642	* @remarks No-long-jump zone!!!
1643	*/
1644	static int hmR0SvmExportGuestCR4(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1645	{
1646	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1647
1648	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1649	uint64_t uShadowCr4 = pCtx->cr4;
1650	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1651	{
1652	switch (pVCpu->hm.s.enmShadowMode)
1653	{
1654	case PGMMODE_REAL:
1655	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1656	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1657
1658	case PGMMODE_32_BIT: /* 32-bit paging. */
1659	uShadowCr4 &= ~X86_CR4_PAE;
1660	break;
1661
1662	case PGMMODE_PAE: /* PAE paging. */
1663	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1664	/** Must use PAE paging as we could use physical memory > 4 GB */
1665	uShadowCr4 \|= X86_CR4_PAE;
1666	break;
1667
1668	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1669	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1670	#ifdef VBOX_WITH_64_BITS_GUESTS
1671	break;
1672	#else
1673	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1674	#endif
1675
1676	default: /* shut up gcc */
1677	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1678	}
1679	}
1680
1681	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1682	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1683	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
1684	{
1685	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
1686	hmR0SvmUpdateVmRunFunction(pVCpu);
1687	}
1688
1689	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1690	if (uShadowCr4 == pCtx->cr4)
1691	{
1692	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1693	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1694	else
1695	{
1696	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1697	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1698	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1699	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1700	}
1701	}
1702	else
1703	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1704
1705	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1706	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1707
1708	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1709	Assert(!RT_HI_U32(uShadowCr4));
1710	pVmcb->guest.u64CR4 = uShadowCr4;
1711	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1712
1713	return VINF_SUCCESS;
1714	}
1715
1716
1717	/**
1718	* Exports the guest (or nested-guest) control registers into the VMCB.
1719	*
1720	* @returns VBox status code.
1721	* @param pVCpu The cross context virtual CPU structure.
1722	* @param pVmcb Pointer to the VM control block.
1723	*
1724	* @remarks No-long-jump zone!!!
1725	*/
1726	static int hmR0SvmExportGuestControlRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1727	{
1728	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1729
1730	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1731	{
1732	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1733	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1734
1735	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1736	{
1737	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1738	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1739	}
1740
1741	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1742	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1743
1744	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1745	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1746	{
1747	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1748	if (RT_FAILURE(rc))
1749	return rc;
1750	}
1751
1752	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1753	}
1754	return VINF_SUCCESS;
1755	}
1756
1757
1758	/**
1759	* Exports the guest (or nested-guest) segment registers into the VMCB.
1760	*
1761	* @returns VBox status code.
1762	* @param pVCpu The cross context virtual CPU structure.
1763	* @param pVmcb Pointer to the VM control block.
1764	*
1765	* @remarks No-long-jump zone!!!
1766	*/
1767	static void hmR0SvmExportGuestSegmentRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1768	{
1769	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1770	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1771
1772	/* Guest segment registers. */
1773	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1774	{
1775	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1776	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1777
1778	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1779	{
1780	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1781	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1782	}
1783
1784	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1785	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1786
1787	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1788	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1789
1790	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1791	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1792
1793	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1794	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1795
1796	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1797	}
1798
1799	/* Guest TR. */
1800	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1801	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1802
1803	/* Guest LDTR. */
1804	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1805	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1806
1807	/* Guest GDTR. */
1808	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1809	{
1810	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1811	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1812	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1813	}
1814
1815	/* Guest IDTR. */
1816	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1817	{
1818	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1819	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1820	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1821	}
1822
1823	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1824	\| HM_CHANGED_GUEST_TABLE_MASK);
1825	}
1826
1827
1828	/**
1829	* Exports the guest (or nested-guest) MSRs into the VMCB.
1830	*
1831	* @param pVCpu The cross context virtual CPU structure.
1832	* @param pVmcb Pointer to the VM control block.
1833	*
1834	* @remarks No-long-jump zone!!!
1835	*/
1836	static void hmR0SvmExportGuestMsrs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1837	{
1838	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1839	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1840
1841	/* Guest Sysenter MSRs. */
1842	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1843	{
1844	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1845	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1846
1847	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1848	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1849
1850	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1851	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1852	}
1853
1854	/*
1855	* Guest EFER MSR.
1856	* AMD-V requires guest EFER.SVME to be set. Weird.
1857	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1858	*/
1859	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1860	{
1861	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1862	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1863	}
1864
1865	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1866	if ( !CPUMIsGuestInLongModeEx(pCtx)
1867	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1868	{
1869	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1870	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1871	}
1872
1873	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1874	{
1875	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1876	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1877	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1878	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1879	}
1880
1881	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1882	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1883
1884	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1885	\| HM_CHANGED_GUEST_EFER_MSR
1886	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1887	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1888
1889	/*
1890	* Setup the PAT MSR (applicable for Nested Paging only).
1891	*
1892	* The default value should be MSR_IA32_CR_PAT_INIT_VAL, but we treat all guest memory
1893	* as WB, so choose type 6 for all PAT slots, see @bugref{9634}.
1894	*
1895	* While guests can modify and see the modified values through the shadow values,
1896	* we shall not honor any guest modifications of this MSR to ensure caching is always
1897	* enabled similar to how we clear CR0.CD and NW bits.
1898	*
1899	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1900	*/
1901	pVmcb->guest.u64PAT = UINT64_C(0x0006060606060606);
1902
1903	/* Enable the last branch record bit if LBR virtualization is enabled. */
1904	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1905	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1906	}
1907
1908
1909	/**
1910	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1911	* the necessary intercepts accordingly.
1912	*
1913	* @param pVCpu The cross context virtual CPU structure.
1914	* @param pVmcb Pointer to the VM control block.
1915	*
1916	* @remarks No-long-jump zone!!!
1917	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1918	*/
1919	static void hmR0SvmExportSharedDebugState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1920	{
1921	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1922
1923	/*
1924	* Anyone single stepping on the host side? If so, we'll have to use the
1925	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1926	* the VMM level like the VT-x implementations does.
1927	*/
1928	bool fInterceptMovDRx = false;
1929	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1930	if (fStepping)
1931	{
1932	pVCpu->hmr0.s.fClearTrapFlag = true;
1933	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1934	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1935	}
1936
1937	if ( fStepping
1938	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1939	{
1940	/*
1941	* Use the combined guest and host DRx values found in the hypervisor
1942	* register set because the debugger has breakpoints active or someone
1943	* is single stepping on the host side.
1944	*
1945	* Note! DBGF expects a clean DR6 state before executing guest code.
1946	*/
1947	if (!CPUMIsHyperDebugStateActive(pVCpu))
1948	{
1949	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1950	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1951	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1952	}
1953
1954	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1955	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1956	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1957	{
1958	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1959	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1960	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1961	}
1962
1963	/** @todo If we cared, we could optimize to allow the guest to read registers
1964	* with the same values. */
1965	fInterceptMovDRx = true;
1966	pVCpu->hmr0.s.fUsingHyperDR7 = true;
1967	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1968	}
1969	else
1970	{
1971	/*
1972	* Update DR6, DR7 with the guest values if necessary.
1973	*/
1974	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1975	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1976	{
1977	pVmcb->guest.u64DR7 = pCtx->dr[7];
1978	pVmcb->guest.u64DR6 = pCtx->dr[6];
1979	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1980	}
1981	pVCpu->hmr0.s.fUsingHyperDR7 = false;
1982
1983	/*
1984	* If the guest has enabled debug registers, we need to load them prior to
1985	* executing guest code so they'll trigger at the right time.
1986	*/
1987	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1988	{
1989	if (!CPUMIsGuestDebugStateActive(pVCpu))
1990	{
1991	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1992	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1993	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1994	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1995	}
1996	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
1997	}
1998	/*
1999	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
2000	* intercept #DB as DR6 is updated in the VMCB.
2001	*
2002	* Note! If we cared and dared, we could skip intercepting \#DB here.
2003	* However, \#DB shouldn't be performance critical, so we'll play safe
2004	* and keep the code similar to the VT-x code and always intercept it.
2005	*/
2006	else if (!CPUMIsGuestDebugStateActive(pVCpu))
2007	fInterceptMovDRx = true;
2008	}
2009
2010	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
2011	if (fInterceptMovDRx)
2012	{
2013	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
2014	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
2015	{
2016	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
2017	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
2018	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2019	}
2020	}
2021	else
2022	{
2023	if ( pVmcb->ctrl.u16InterceptRdDRx
2024	\|\| pVmcb->ctrl.u16InterceptWrDRx)
2025	{
2026	pVmcb->ctrl.u16InterceptRdDRx = 0;
2027	pVmcb->ctrl.u16InterceptWrDRx = 0;
2028	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2029	}
2030	}
2031	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2032	}
2033
2034	/**
2035	* Exports the hardware virtualization state into the nested-guest
2036	* VMCB.
2037	*
2038	* @param pVCpu The cross context virtual CPU structure.
2039	* @param pVmcb Pointer to the VM control block.
2040	*
2041	* @remarks No-long-jump zone!!!
2042	*/
2043	static void hmR0SvmExportGuestHwvirtState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2044	{
2045	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2046
2047	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
2048	{
2049	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2050	{
2051	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2052	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
2053
2054	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx); /* Nested VGIF is not supported yet. */
2055	Assert(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Physical hardware supports VGIF. */
2056	Assert(HMIsSvmVGifActive(pVM)); /* Outer VM has enabled VGIF. */
2057	NOREF(pVM);
2058
2059	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
2060	}
2061
2062	/*
2063	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2064	* since SVM doesn't have a preemption timer.
2065	*
2066	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
2067	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2068	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2069	*/
2070	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2071	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2072	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2073	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2074	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_PAUSE))
2075	{
2076	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2077	pVmcbCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2078	pVmcbCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2079	}
2080	else
2081	{
2082	/** @todo r=ramshankar: We can turn these assignments into assertions. */
2083	pVmcbCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2084	pVmcbCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2085	}
2086	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2087
2088	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
2089	}
2090	}
2091
2092
2093	/**
2094	* Exports the guest APIC TPR state into the VMCB.
2095	*
2096	* @returns VBox status code.
2097	* @param pVCpu The cross context virtual CPU structure.
2098	* @param pVmcb Pointer to the VM control block.
2099	*/
2100	static int hmR0SvmExportGuestApicTpr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2101	{
2102	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2103
2104	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2105	{
2106	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2107	if ( PDMHasApic(pVM)
2108	&& APICIsEnabled(pVCpu))
2109	{
2110	bool fPendingIntr;
2111	uint8_t u8Tpr;
2112	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2113	AssertRCReturn(rc, rc);
2114
2115	/* Assume that we need to trap all TPR accesses and thus need not check on
2116	every #VMEXIT if we should update the TPR. */
2117	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2118	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2119
2120	if (!pVM->hm.s.fTprPatchingActive)
2121	{
2122	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2123	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2124
2125	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2126	can deliver the interrupt to the guest. */
2127	if (fPendingIntr)
2128	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2129	else
2130	{
2131	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2132	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2133	}
2134
2135	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2136	}
2137	else
2138	{
2139	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2140	pVmcb->guest.u64LSTAR = u8Tpr;
2141	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hmr0.s.svm.pvMsrBitmap;
2142
2143	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2144	if (fPendingIntr)
2145	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2146	else
2147	{
2148	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2149	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2150	}
2151	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2152	}
2153	}
2154	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2155	}
2156	return VINF_SUCCESS;
2157	}
2158
2159
2160	/**
2161	* Sets up the exception interrupts required for guest execution in the VMCB.
2162	*
2163	* @param pVCpu The cross context virtual CPU structure.
2164	* @param pVmcb Pointer to the VM control block.
2165	*
2166	* @remarks No-long-jump zone!!!
2167	*/
2168	static void hmR0SvmExportGuestXcptIntercepts(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2169	{
2170	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2171
2172	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2173	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_SVM_XCPT_INTERCEPTS)
2174	{
2175	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2176	if (pVCpu->hm.s.fGIMTrapXcptUD \|\| pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
2177	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2178	else
2179	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2180
2181	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2182	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2183	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2184	else
2185	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2186
2187	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2188	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_SVM_XCPT_INTERCEPTS);
2189	}
2190	}
2191
2192
2193	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2194	/**
2195	* Merges guest and nested-guest intercepts for executing the nested-guest using
2196	* hardware-assisted SVM.
2197	*
2198	* This merges the guest and nested-guest intercepts in a way that if the outer
2199	* guest intercept is set we need to intercept it in the nested-guest as
2200	* well.
2201	*
2202	* @param pVCpu The cross context virtual CPU structure.
2203	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2204	*/
2205	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
2206	{
2207	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2208	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
2209	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2210	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2211
2212	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2213	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2214	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2215
2216	/* Always intercept CR4 writes for tracking PGM mode changes. */
2217	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2218
2219	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2220	if (!pVM->hmr0.s.fNestedPaging)
2221	{
2222	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2223	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2224	}
2225
2226	/** @todo Figure out debugging with nested-guests, till then just intercept
2227	* all DR[0-15] accesses. */
2228	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2229	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2230
2231	/*
2232	* Merge the guest's exception intercepts into the nested-guest VMCB.
2233	*
2234	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2235	* while executing the nested-guest.
2236	*
2237	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2238	* be tweaked later depending on how we wish to implement breakpoints.
2239	*
2240	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2241	* loaded into their guests, not ours.
2242	*
2243	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2244	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2245	*/
2246	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2247	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2248	& ~( RT_BIT(X86_XCPT_UD)
2249	\| RT_BIT(X86_XCPT_BP)
2250	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2251	#else
2252	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2253	#endif
2254
2255	/*
2256	* Adjust intercepts while executing the nested-guest that differ from the
2257	* outer guest intercepts.
2258	*
2259	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2260	* that belong to the nested-guest to the outer guest.
2261	*
2262	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2263	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2264	*/
2265	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2266	\| SVM_CTRL_INTERCEPT_VMMCALL))
2267	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2268
2269	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2270	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2271
2272	/* Finally, update the VMCB clean bits. */
2273	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2274	}
2275	#endif
2276
2277
2278	/**
2279	* Enters the AMD-V session.
2280	*
2281	* @returns VBox status code.
2282	* @param pVCpu The cross context virtual CPU structure.
2283	*/
2284	VMMR0DECL(int) SVMR0Enter(PVMCPUCC pVCpu)
2285	{
2286	AssertPtr(pVCpu);
2287	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2288	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2289
2290	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2291	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2292	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2293
2294	pVCpu->hmr0.s.fLeaveDone = false;
2295	return VINF_SUCCESS;
2296	}
2297
2298
2299	/**
2300	* Thread-context callback for AMD-V.
2301	*
2302	* @param enmEvent The thread-context event.
2303	* @param pVCpu The cross context virtual CPU structure.
2304	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2305	* @thread EMT(pVCpu)
2306	*/
2307	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
2308	{
2309	NOREF(fGlobalInit);
2310
2311	switch (enmEvent)
2312	{
2313	case RTTHREADCTXEVENT_OUT:
2314	{
2315	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2316	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2317	VMCPU_ASSERT_EMT(pVCpu);
2318
2319	/* No longjmps (log-flush, locks) in this fragile context. */
2320	VMMRZCallRing3Disable(pVCpu);
2321
2322	if (!pVCpu->hmr0.s.fLeaveDone)
2323	{
2324	hmR0SvmLeave(pVCpu, false /* fImportState */);
2325	pVCpu->hmr0.s.fLeaveDone = true;
2326	}
2327
2328	/* Leave HM context, takes care of local init (term). */
2329	int rc = HMR0LeaveCpu(pVCpu);
2330	AssertRC(rc); NOREF(rc);
2331
2332	/* Restore longjmp state. */
2333	VMMRZCallRing3Enable(pVCpu);
2334	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2335	break;
2336	}
2337
2338	case RTTHREADCTXEVENT_IN:
2339	{
2340	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2341	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2342	VMCPU_ASSERT_EMT(pVCpu);
2343
2344	/* No longjmps (log-flush, locks) in this fragile context. */
2345	VMMRZCallRing3Disable(pVCpu);
2346
2347	/*
2348	* Initialize the bare minimum state required for HM. This takes care of
2349	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2350	*/
2351	int rc = hmR0EnterCpu(pVCpu);
2352	AssertRC(rc); NOREF(rc);
2353	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2354	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2355
2356	pVCpu->hmr0.s.fLeaveDone = false;
2357
2358	/* Restore longjmp state. */
2359	VMMRZCallRing3Enable(pVCpu);
2360	break;
2361	}
2362
2363	default:
2364	break;
2365	}
2366	}
2367
2368
2369	/**
2370	* Saves the host state.
2371	*
2372	* @returns VBox status code.
2373	* @param pVCpu The cross context virtual CPU structure.
2374	*
2375	* @remarks No-long-jump zone!!!
2376	*/
2377	VMMR0DECL(int) SVMR0ExportHostState(PVMCPUCC pVCpu)
2378	{
2379	NOREF(pVCpu);
2380
2381	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2382	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2383	return VINF_SUCCESS;
2384	}
2385
2386
2387	/**
2388	* Exports the guest or nested-guest state from the virtual-CPU context into the
2389	* VMCB.
2390	*
2391	* Also sets up the appropriate VMRUN function to execute guest or nested-guest
2392	* code based on the virtual-CPU mode.
2393	*
2394	* @returns VBox status code.
2395	* @param pVCpu The cross context virtual CPU structure.
2396	* @param pSvmTransient Pointer to the SVM-transient structure.
2397	*
2398	* @remarks No-long-jump zone!!!
2399	*/
2400	static int hmR0SvmExportGuestState(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
2401	{
2402	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2403
2404	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2405	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2406	Assert(pVmcb);
2407
2408	pVmcb->guest.u64RIP = pCtx->rip;
2409	pVmcb->guest.u64RSP = pCtx->rsp;
2410	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2411	pVmcb->guest.u64RAX = pCtx->rax;
2412
2413	bool const fIsNestedGuest = pSvmTransient->fIsNestedGuest;
2414	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2415
2416	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2417	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2418	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2419	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2420	hmR0SvmExportGuestHwvirtState(pVCpu, pVmcb);
2421
2422	ASMSetFlags(fEFlags);
2423
2424	if (!fIsNestedGuest)
2425	{
2426	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2427	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2428	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2429	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2430	}
2431
2432	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2433	uint64_t fUnusedMask = HM_CHANGED_GUEST_RIP
2434	\| HM_CHANGED_GUEST_RFLAGS
2435	\| HM_CHANGED_GUEST_GPRS_MASK
2436	\| HM_CHANGED_GUEST_X87
2437	\| HM_CHANGED_GUEST_SSE_AVX
2438	\| HM_CHANGED_GUEST_OTHER_XSAVE
2439	\| HM_CHANGED_GUEST_XCRx
2440	\| HM_CHANGED_GUEST_TSC_AUX
2441	\| HM_CHANGED_GUEST_OTHER_MSRS;
2442	if (fIsNestedGuest)
2443	fUnusedMask \|= HM_CHANGED_SVM_XCPT_INTERCEPTS
2444	\| HM_CHANGED_GUEST_APIC_TPR;
2445
2446	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( fUnusedMask
2447	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2448
2449	#ifdef VBOX_STRICT
2450	/*
2451	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2452	* except for the host-context and/or shared host-guest context bits.
2453	*/
2454	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2455	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2456	("fCtxChanged=%#RX64\n", fCtxChanged));
2457
2458	/*
2459	* If we need to log state that isn't always imported, we'll need to import them here.
2460	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2461	*/
2462	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2463	#endif
2464
2465	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2466	return VINF_SUCCESS;
2467	}
2468
2469
2470	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2471	/**
2472	* Merges the guest and nested-guest MSR permission bitmap.
2473	*
2474	* If the guest is intercepting an MSR we need to intercept it regardless of
2475	* whether the nested-guest is intercepting it or not.
2476	*
2477	* @param pHostCpu The HM physical-CPU structure.
2478	* @param pVCpu The cross context virtual CPU structure.
2479	*
2480	* @remarks No-long-jmp zone!!!
2481	*/
2482	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2483	{
2484	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hmr0.s.svm.pvMsrBitmap;
2485	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2486	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2487
2488	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2489	uint32_t const offRsvdQwords = 0x1800 >> 3;
2490	for (uint32_t i = 0; i < offRsvdQwords; i++)
2491	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2492	}
2493
2494
2495	/**
2496	* Caches the nested-guest VMCB fields before we modify them for execution using
2497	* hardware-assisted SVM.
2498	*
2499	* @returns true if the VMCB was previously already cached, false otherwise.
2500	* @param pVCpu The cross context virtual CPU structure.
2501	*
2502	* @sa HMNotifySvmNstGstVmexit.
2503	*/
2504	static bool hmR0SvmCacheVmcbNested(PVMCPUCC pVCpu)
2505	{
2506	/*
2507	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2508	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2509	*
2510	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2511	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2512	*/
2513	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2514	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2515	if (!fWasCached)
2516	{
2517	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2518	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2519	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2520	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2521	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2522	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2523	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2524	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2525	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2526	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2527	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2528	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2529	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2530	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2531	pVmcbNstGstCache->fCacheValid = true;
2532	Log4Func(("Cached VMCB fields\n"));
2533	}
2534
2535	return fWasCached;
2536	}
2537
2538
2539	/**
2540	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2541	*
2542	* This is done the first time we enter nested-guest execution using SVM R0
2543	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2544	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2545	*
2546	* @param pVCpu The cross context virtual CPU structure.
2547	*/
2548	static void hmR0SvmSetupVmcbNested(PVMCPUCC pVCpu)
2549	{
2550	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2551	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2552
2553	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2554
2555	/*
2556	* First cache the nested-guest VMCB fields we may potentially modify.
2557	*/
2558	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2559	if (!fVmcbCached)
2560	{
2561	/*
2562	* The IOPM of the nested-guest can be ignored because the the guest always
2563	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2564	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2565	*/
2566	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2567
2568	/*
2569	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2570	* nested-paging suddenly while executing a VM (see assertion at the end of
2571	* Trap0eHandler() in PGMAllBth.h).
2572	*/
2573	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging;
2574
2575	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2576	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2577
2578	/*
2579	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2580	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2581	*/
2582	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2583
2584	#ifdef DEBUG_ramshankar
2585	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2586	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2587	#endif
2588
2589	/*
2590	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2591	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2592	*/
2593	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2594	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2595	\| SVM_CTRL_INTERCEPT_VMLOAD;
2596
2597	/*
2598	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2599	* CLGI/STGI instructions executed by the nested-guest.
2600	*/
2601	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2602	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2603	\| SVM_CTRL_INTERCEPT_STGI;
2604
2605	/* Merge the guest and nested-guest intercepts. */
2606	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2607
2608	/* Update the VMCB clean bits. */
2609	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2610	}
2611	else
2612	{
2613	Assert(!pVCpu->hmr0.s.svm.fSyncVTpr);
2614	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2615	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2616	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPagingCfg == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2617	}
2618	}
2619	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2620
2621
2622	/**
2623	* Exports the state shared between the host and guest (or nested-guest) into
2624	* the VMCB.
2625	*
2626	* @param pVCpu The cross context virtual CPU structure.
2627	* @param pVmcb Pointer to the VM control block.
2628	*
2629	* @remarks No-long-jump zone!!!
2630	*/
2631	static void hmR0SvmExportSharedState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2632	{
2633	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2634	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2635
2636	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2637	{
2638	/** @todo Figure out stepping with nested-guest. */
2639	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2640	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2641	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2642	else
2643	{
2644	pVmcb->guest.u64DR6 = pCtx->dr[6];
2645	pVmcb->guest.u64DR7 = pCtx->dr[7];
2646	}
2647	}
2648
2649	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2650	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2651	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2652	}
2653
2654
2655	/**
2656	* Worker for SVMR0ImportStateOnDemand.
2657	*
2658	* @param pVCpu The cross context virtual CPU structure.
2659	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2660	*/
2661	static void hmR0SvmImportGuestState(PVMCPUCC pVCpu, uint64_t fWhat)
2662	{
2663	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2664
2665	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2666	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2667	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2668	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2669
2670	/*
2671	* We disable interrupts to make the updating of the state and in particular
2672	* the fExtrn modification atomic wrt to preemption hooks.
2673	*/
2674	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2675
2676	fWhat &= pCtx->fExtrn;
2677	if (fWhat)
2678	{
2679	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2680	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2681	{
2682	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2683	{
2684	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2685	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2686	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2687	}
2688	}
2689
2690	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2691	{
2692	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2693	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2694	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2695	}
2696	#endif
2697
2698	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2699	{
2700	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2701	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2702	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2703	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2704	}
2705
2706	if (fWhat & CPUMCTX_EXTRN_RIP)
2707	pCtx->rip = pVmcbGuest->u64RIP;
2708
2709	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2710	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2711
2712	if (fWhat & CPUMCTX_EXTRN_RSP)
2713	pCtx->rsp = pVmcbGuest->u64RSP;
2714
2715	if (fWhat & CPUMCTX_EXTRN_RAX)
2716	pCtx->rax = pVmcbGuest->u64RAX;
2717
2718	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2719	{
2720	if (fWhat & CPUMCTX_EXTRN_CS)
2721	{
2722	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2723	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2724	/** @todo SELM might need to be fixed as it too should not care about the
2725	* granularity bit. See @bugref{6785}. */
2726	if ( !pCtx->cs.Attr.n.u1Granularity
2727	&& pCtx->cs.Attr.n.u1Present
2728	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2729	{
2730	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2731	pCtx->cs.Attr.n.u1Granularity = 1;
2732	}
2733	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2734	}
2735	if (fWhat & CPUMCTX_EXTRN_SS)
2736	{
2737	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2738	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2739	/*
2740	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2741	* VMCB and uses that and thus it's possible that when the CPL changes during
2742	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2743	* AMD Fusion CPUs with 64-bit guests.
2744	*
2745	* See AMD spec. 15.5.1 "Basic operation".
2746	*/
2747	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2748	uint8_t const uCpl = pVmcbGuest->u8CPL;
2749	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2750	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2751	}
2752	if (fWhat & CPUMCTX_EXTRN_DS)
2753	{
2754	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2755	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2756	}
2757	if (fWhat & CPUMCTX_EXTRN_ES)
2758	{
2759	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2760	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2761	}
2762	if (fWhat & CPUMCTX_EXTRN_FS)
2763	{
2764	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2765	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2766	}
2767	if (fWhat & CPUMCTX_EXTRN_GS)
2768	{
2769	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2770	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2771	}
2772	}
2773
2774	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2775	{
2776	if (fWhat & CPUMCTX_EXTRN_TR)
2777	{
2778	/*
2779	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2780	* are used between Intel and AMD, see @bugref{6208#c39}.
2781	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2782	*/
2783	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2784	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2785	{
2786	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2787	\|\| CPUMIsGuestInLongModeEx(pCtx))
2788	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2789	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2790	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2791	}
2792	}
2793
2794	if (fWhat & CPUMCTX_EXTRN_LDTR)
2795	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2796
2797	if (fWhat & CPUMCTX_EXTRN_GDTR)
2798	{
2799	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2800	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2801	}
2802
2803	if (fWhat & CPUMCTX_EXTRN_IDTR)
2804	{
2805	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2806	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2807	}
2808	}
2809
2810	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2811	{
2812	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2813	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2814	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2815	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2816	}
2817
2818	if ( (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2819	&& !pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit /* Intercepted. AMD-V would clear the high 32 bits of EIP & ESP. */)
2820	{
2821	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2822	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2823	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2824	}
2825
2826	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2827	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2828
2829	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2830	{
2831	if (fWhat & CPUMCTX_EXTRN_DR6)
2832	{
2833	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2834	pCtx->dr[6] = pVmcbGuest->u64DR6;
2835	else
2836	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2837	}
2838
2839	if (fWhat & CPUMCTX_EXTRN_DR7)
2840	{
2841	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2842	pCtx->dr[7] = pVmcbGuest->u64DR7;
2843	else
2844	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2845	}
2846	}
2847
2848	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2849	{
2850	if (fWhat & CPUMCTX_EXTRN_CR0)
2851	{
2852	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2853	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2854	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2855	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2856	CPUMSetGuestCR0(pVCpu, uCr0);
2857	VMMRZCallRing3Enable(pVCpu);
2858	}
2859
2860	if (fWhat & CPUMCTX_EXTRN_CR2)
2861	pCtx->cr2 = pVmcbGuest->u64CR2;
2862
2863	if (fWhat & CPUMCTX_EXTRN_CR3)
2864	{
2865	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2866	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2867	{
2868	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2869	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2870	}
2871	}
2872
2873	/* Changes to CR4 are always intercepted. */
2874	}
2875
2876	/* Update fExtrn. */
2877	pCtx->fExtrn &= ~fWhat;
2878
2879	/* If everything has been imported, clear the HM keeper bit. */
2880	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2881	{
2882	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2883	Assert(!pCtx->fExtrn);
2884	}
2885	}
2886	else
2887	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
2888
2889	ASMSetFlags(fEFlags);
2890
2891	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
2892
2893	/*
2894	* Honor any pending CR3 updates.
2895	*
2896	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
2897	* -> SVMR0CallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
2898	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
2899	* handling -> hmR0SvmImportGuestState() and here we are.
2900	*
2901	* The reason for such complicated handling is because VM-exits that call into PGM expect
2902	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
2903	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
2904	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
2905	*
2906	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
2907	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
2908	*/
2909	if ( VMMRZCallRing3IsEnabled(pVCpu)
2910	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2911	{
2912	Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
2913	PGMUpdateCR3(pVCpu, pCtx->cr3);
2914	}
2915	}
2916
2917
2918	/**
2919	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2920	* context.
2921	*
2922	* Currently there is no residual state left in the CPU that is not updated in the
2923	* VMCB.
2924	*
2925	* @returns VBox status code.
2926	* @param pVCpu The cross context virtual CPU structure.
2927	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2928	*/
2929	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2930	{
2931	hmR0SvmImportGuestState(pVCpu, fWhat);
2932	return VINF_SUCCESS;
2933	}
2934
2935
2936	/**
2937	* Does the necessary state syncing before returning to ring-3 for any reason
2938	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2939	*
2940	* @param pVCpu The cross context virtual CPU structure.
2941	* @param fImportState Whether to import the guest state from the VMCB back
2942	* to the guest-CPU context.
2943	*
2944	* @remarks No-long-jmp zone!!!
2945	*/
2946	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState)
2947	{
2948	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2949	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2950	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2951
2952	/*
2953	* !!! IMPORTANT !!!
2954	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2955	*/
2956
2957	/* Save the guest state if necessary. */
2958	if (fImportState)
2959	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2960
2961	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2962	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2963	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2964
2965	/*
2966	* Restore host debug registers if necessary and resync on next R0 reentry.
2967	*/
2968	#ifdef VBOX_STRICT
2969	if (CPUMIsHyperDebugStateActive(pVCpu))
2970	{
2971	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb; /** @todo nested-guest. */
2972	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2973	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2974	}
2975	#endif
2976	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2977	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2978	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2979
2980	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2981	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
2982	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
2983	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
2984	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
2985	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
2986	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2987
2988	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2989	}
2990
2991
2992	/**
2993	* Leaves the AMD-V session.
2994	*
2995	* Only used while returning to ring-3 either due to longjump or exits to
2996	* ring-3.
2997	*
2998	* @returns VBox status code.
2999	* @param pVCpu The cross context virtual CPU structure.
3000	*/
3001	static int hmR0SvmLeaveSession(PVMCPUCC pVCpu)
3002	{
3003	HM_DISABLE_PREEMPT(pVCpu);
3004	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3005	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3006
3007	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3008	and done this from the SVMR0ThreadCtxCallback(). */
3009	if (!pVCpu->hmr0.s.fLeaveDone)
3010	{
3011	hmR0SvmLeave(pVCpu, true /* fImportState */);
3012	pVCpu->hmr0.s.fLeaveDone = true;
3013	}
3014
3015	/*
3016	* !!! IMPORTANT !!!
3017	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
3018	*/
3019
3020	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3021	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3022	VMMR0ThreadCtxHookDisable(pVCpu);
3023
3024	/* Leave HM context. This takes care of local init (term). */
3025	int rc = HMR0LeaveCpu(pVCpu);
3026
3027	HM_RESTORE_PREEMPT();
3028	return rc;
3029	}
3030
3031
3032	/**
3033	* Does the necessary state syncing before doing a longjmp to ring-3.
3034	*
3035	* @returns VBox status code.
3036	* @param pVCpu The cross context virtual CPU structure.
3037	*
3038	* @remarks No-long-jmp zone!!!
3039	*/
3040	static int hmR0SvmLongJmpToRing3(PVMCPUCC pVCpu)
3041	{
3042	return hmR0SvmLeaveSession(pVCpu);
3043	}
3044
3045
3046	/**
3047	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3048	* any remaining host state) before we longjump to ring-3 and possibly get
3049	* preempted.
3050	*
3051	* @param pVCpu The cross context virtual CPU structure.
3052	* @param enmOperation The operation causing the ring-3 longjump.
3053	*/
3054	VMMR0DECL(int) SVMR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
3055	{
3056	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3057	{
3058	/*
3059	* !!! IMPORTANT !!!
3060	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3061	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3062	*/
3063	VMMRZCallRing3RemoveNotification(pVCpu);
3064	VMMRZCallRing3Disable(pVCpu);
3065	HM_DISABLE_PREEMPT(pVCpu);
3066
3067	/* Import the entire guest state. */
3068	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3069
3070	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3071	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3072
3073	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3074	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3075
3076	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3077	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3078	VMMR0ThreadCtxHookDisable(pVCpu);
3079
3080	/* Leave HM context. This takes care of local init (term). */
3081	HMR0LeaveCpu(pVCpu);
3082
3083	HM_RESTORE_PREEMPT();
3084	return VINF_SUCCESS;
3085	}
3086
3087	Assert(pVCpu);
3088	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3089	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3090
3091	VMMRZCallRing3Disable(pVCpu);
3092	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3093
3094	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3095	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3096	AssertRCReturn(rc, rc);
3097
3098	VMMRZCallRing3Enable(pVCpu);
3099	return VINF_SUCCESS;
3100	}
3101
3102
3103	/**
3104	* Take necessary actions before going back to ring-3.
3105	*
3106	* An action requires us to go back to ring-3. This function does the necessary
3107	* steps before we can safely return to ring-3. This is not the same as longjmps
3108	* to ring-3, this is voluntary.
3109	*
3110	* @returns Strict VBox status code.
3111	* @param pVCpu The cross context virtual CPU structure.
3112	* @param rcExit The reason for exiting to ring-3. Can be
3113	* VINF_VMM_UNKNOWN_RING3_CALL.
3114	*/
3115	static VBOXSTRICTRC hmR0SvmExitToRing3(PVMCPUCC pVCpu, VBOXSTRICTRC rcExit)
3116	{
3117	Assert(pVCpu);
3118	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3119
3120	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3121	VMMRZCallRing3Disable(pVCpu);
3122	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", VBOXSTRICTRC_VAL(rcExit), (uint64_t)pVCpu->fLocalForcedActions,
3123	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3124
3125	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3126	if (pVCpu->hm.s.Event.fPending)
3127	{
3128	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3129	Assert(!pVCpu->hm.s.Event.fPending);
3130	}
3131
3132	/* Sync. the necessary state for going back to ring-3. */
3133	hmR0SvmLeaveSession(pVCpu);
3134	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3135
3136	/* Thread-context hooks are unregistered at this point!!! */
3137	/* Ring-3 callback notifications are unregistered at this point!!! */
3138
3139	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3140	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3141	\| CPUM_CHANGED_LDTR
3142	\| CPUM_CHANGED_GDTR
3143	\| CPUM_CHANGED_IDTR
3144	\| CPUM_CHANGED_TR
3145	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3146	if ( pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging
3147	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3148	{
3149	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3150	}
3151
3152	/* Update the exit-to-ring 3 reason. */
3153	pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
3154
3155	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3156	if ( rcExit != VINF_EM_RAW_INTERRUPT
3157	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3158	{
3159	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3160	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3161	}
3162
3163	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3164	VMMRZCallRing3Enable(pVCpu);
3165
3166	/*
3167	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3168	* and if we're injecting an event we should have a TRPM trap pending.
3169	*/
3170	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3171	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3172	VERR_SVM_IPE_5);
3173	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3174	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3175	VERR_SVM_IPE_4);
3176
3177	return rcExit;
3178	}
3179
3180
3181	/**
3182	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3183	* intercepts.
3184	*
3185	* @param pVCpu The cross context virtual CPU structure.
3186	* @param pVmcb Pointer to the VM control block.
3187	*
3188	* @remarks No-long-jump zone!!!
3189	*/
3190	static void hmR0SvmUpdateTscOffsetting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3191	{
3192	/*
3193	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3194	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3195	* RDTSC/RDTSCP as well.
3196	*/
3197	bool fParavirtTsc;
3198	uint64_t uTscOffset;
3199	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3200
3201	bool fIntercept;
3202	if (fCanUseRealTsc)
3203	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3204	else
3205	{
3206	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3207	fIntercept = true;
3208	}
3209
3210	if (!fIntercept)
3211	{
3212	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3213	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3214	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3215	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
3216	#endif
3217
3218	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3219	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3220	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3221	}
3222
3223	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3224	information before every VM-entry, hence we have nothing to do here at the moment. */
3225	if (fParavirtTsc)
3226	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3227	}
3228
3229
3230	/**
3231	* Sets an event as a pending event to be injected into the guest.
3232	*
3233	* @param pVCpu The cross context virtual CPU structure.
3234	* @param pEvent Pointer to the SVM event.
3235	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3236	* page-fault.
3237	*
3238	* @remarks Statistics counter assumes this is a guest event being reflected to
3239	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3240	*/
3241	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPUCC pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3242	{
3243	Assert(!pVCpu->hm.s.Event.fPending);
3244	Assert(pEvent->n.u1Valid);
3245
3246	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3247	pVCpu->hm.s.Event.fPending = true;
3248	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3249
3250	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3251	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3252	}
3253
3254
3255	/**
3256	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3257	*
3258	* @param pVCpu The cross context virtual CPU structure.
3259	*/
3260	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPUCC pVCpu)
3261	{
3262	SVMEVENT Event;
3263	Event.u = 0;
3264	Event.n.u1Valid = 1;
3265	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3266	Event.n.u8Vector = X86_XCPT_UD;
3267	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3268	}
3269
3270
3271	/**
3272	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3273	*
3274	* @param pVCpu The cross context virtual CPU structure.
3275	*/
3276	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPUCC pVCpu)
3277	{
3278	SVMEVENT Event;
3279	Event.u = 0;
3280	Event.n.u1Valid = 1;
3281	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3282	Event.n.u8Vector = X86_XCPT_DB;
3283	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3284	}
3285
3286
3287	/**
3288	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3289	*
3290	* @param pVCpu The cross context virtual CPU structure.
3291	* @param u32ErrCode The error-code for the page-fault.
3292	* @param uFaultAddress The page fault address (CR2).
3293	*
3294	* @remarks This updates the guest CR2 with @a uFaultAddress!
3295	*/
3296	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPUCC pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3297	{
3298	SVMEVENT Event;
3299	Event.u = 0;
3300	Event.n.u1Valid = 1;
3301	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3302	Event.n.u8Vector = X86_XCPT_PF;
3303	Event.n.u1ErrorCodeValid = 1;
3304	Event.n.u32ErrorCode = u32ErrCode;
3305
3306	/* Update CR2 of the guest. */
3307	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3308	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3309	{
3310	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3311	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3312	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3313	}
3314
3315	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3316	}
3317
3318
3319	/**
3320	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3321	*
3322	* @param pVCpu The cross context virtual CPU structure.
3323	*/
3324	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPUCC pVCpu)
3325	{
3326	SVMEVENT Event;
3327	Event.u = 0;
3328	Event.n.u1Valid = 1;
3329	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3330	Event.n.u8Vector = X86_XCPT_MF;
3331	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3332	}
3333
3334
3335	/**
3336	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3337	*
3338	* @param pVCpu The cross context virtual CPU structure.
3339	*/
3340	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPUCC pVCpu)
3341	{
3342	SVMEVENT Event;
3343	Event.u = 0;
3344	Event.n.u1Valid = 1;
3345	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3346	Event.n.u8Vector = X86_XCPT_DF;
3347	Event.n.u1ErrorCodeValid = 1;
3348	Event.n.u32ErrorCode = 0;
3349	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3350	}
3351
3352
3353	/**
3354	* Injects an event into the guest upon VMRUN by updating the relevant field
3355	* in the VMCB.
3356	*
3357	* @param pVCpu The cross context virtual CPU structure.
3358	* @param pVmcb Pointer to the guest VM control block.
3359	* @param pEvent Pointer to the event.
3360	*
3361	* @remarks No-long-jump zone!!!
3362	* @remarks Requires CR0!
3363	*/
3364	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3365	{
3366	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3367	pVmcb->ctrl.EventInject.u = pEvent->u;
3368	if ( pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_EXCEPTION
3369	\|\| pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_NMI)
3370	{
3371	Assert(pEvent->n.u8Vector <= X86_XCPT_LAST);
3372	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedXcptsR0[pEvent->n.u8Vector]);
3373	}
3374	else
3375	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3376	RT_NOREF(pVCpu);
3377
3378	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3379	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3380	}
3381
3382
3383
3384	/**
3385	* Converts any TRPM trap into a pending HM event. This is typically used when
3386	* entering from ring-3 (not longjmp returns).
3387	*
3388	* @param pVCpu The cross context virtual CPU structure.
3389	*/
3390	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
3391	{
3392	Assert(TRPMHasTrap(pVCpu));
3393	Assert(!pVCpu->hm.s.Event.fPending);
3394
3395	uint8_t uVector;
3396	TRPMEVENT enmTrpmEvent;
3397	uint32_t uErrCode;
3398	RTGCUINTPTR GCPtrFaultAddress;
3399	uint8_t cbInstr;
3400
3401	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, NULL /* pfIcebp */);
3402	AssertRC(rc);
3403
3404	SVMEVENT Event;
3405	Event.u = 0;
3406	Event.n.u1Valid = 1;
3407	Event.n.u8Vector = uVector;
3408
3409	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3410	if (enmTrpmEvent == TRPM_TRAP)
3411	{
3412	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3413	switch (uVector)
3414	{
3415	case X86_XCPT_NMI:
3416	{
3417	Event.n.u3Type = SVM_EVENT_NMI;
3418	break;
3419	}
3420
3421	case X86_XCPT_BP:
3422	case X86_XCPT_OF:
3423	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3424	RT_FALL_THRU();
3425
3426	case X86_XCPT_PF:
3427	case X86_XCPT_DF:
3428	case X86_XCPT_TS:
3429	case X86_XCPT_NP:
3430	case X86_XCPT_SS:
3431	case X86_XCPT_GP:
3432	case X86_XCPT_AC:
3433	{
3434	Event.n.u1ErrorCodeValid = 1;
3435	Event.n.u32ErrorCode = uErrCode;
3436	break;
3437	}
3438	}
3439	}
3440	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3441	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3442	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3443	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3444	else
3445	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3446
3447	rc = TRPMResetTrap(pVCpu);
3448	AssertRC(rc);
3449
3450	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3451	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3452
3453	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3454	}
3455
3456
3457	/**
3458	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3459	* AMD-V to execute any instruction.
3460	*
3461	* @param pVCpu The cross context virtual CPU structure.
3462	*/
3463	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu)
3464	{
3465	Assert(pVCpu->hm.s.Event.fPending);
3466	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3467
3468	SVMEVENT Event;
3469	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3470
3471	uint8_t uVector = Event.n.u8Vector;
3472	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3473
3474	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3475
3476	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3477	AssertRC(rc);
3478
3479	if (Event.n.u1ErrorCodeValid)
3480	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3481
3482	if ( enmTrapType == TRPM_TRAP
3483	&& uVector == X86_XCPT_PF)
3484	{
3485	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3486	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3487	}
3488	else if (enmTrapType == TRPM_SOFTWARE_INT)
3489	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3490	pVCpu->hm.s.Event.fPending = false;
3491	}
3492
3493
3494	/**
3495	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3496	* now.
3497	*
3498	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3499	* @param pVCpu The cross context virtual CPU structure.
3500	*
3501	* @remarks No-long-jump zone!!!
3502	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3503	*/
3504	static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
3505	{
3506	/*
3507	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3508	* completes. Check if we should inhibit interrupts or clear any existing
3509	* interrupt inhibition.
3510	*/
3511	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3512	{
3513	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3514	{
3515	/*
3516	* We can clear the inhibit force flag as even if we go back to the recompiler
3517	* without executing guest code in AMD-V, the flag's condition to be cleared is
3518	* met and thus the cleared state is correct.
3519	*/
3520	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3521	return false;
3522	}
3523	return true;
3524	}
3525	return false;
3526	}
3527
3528
3529	/**
3530	* Sets the virtual interrupt intercept control in the VMCB.
3531	*
3532	* @param pVCpu The cross context virtual CPU structure.
3533	* @param pVmcb Pointer to the VM control block.
3534	*/
3535	static void hmR0SvmSetIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3536	{
3537	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3538
3539	/*
3540	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3541	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3542	* (updating ISR at the right time) and inject the interrupt.
3543	*
3544	* With AVIC is supported, we could make use of the asynchronously delivery without
3545	* #VMEXIT and we would be passing the AVIC page to SVM.
3546	*
3547	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3548	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3549	*/
3550	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3551	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3552	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3553	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3554	Log4(("Set VINTR intercept\n"));
3555	}
3556
3557
3558	/**
3559	* Clears the virtual interrupt intercept control in the VMCB as
3560	* we are figured the guest is unable process any interrupts
3561	* at this point of time.
3562	*
3563	* @param pVCpu The cross context virtual CPU structure.
3564	* @param pVmcb Pointer to the VM control block.
3565	*/
3566	static void hmR0SvmClearIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3567	{
3568	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3569
3570	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3571	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3572	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3573	{
3574	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3575	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3576	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3577	Log4(("Cleared VINTR intercept\n"));
3578	}
3579	}
3580
3581
3582	/**
3583	* Evaluates the event to be delivered to the guest and sets it as the pending
3584	* event.
3585	*
3586	* @returns Strict VBox status code.
3587	* @param pVCpu The cross context virtual CPU structure.
3588	* @param pSvmTransient Pointer to the SVM transient structure.
3589	*/
3590	static VBOXSTRICTRC hmR0SvmEvaluatePendingEvent(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
3591	{
3592	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3593	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3594	\| CPUMCTX_EXTRN_RFLAGS
3595	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3596	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3597
3598	Assert(!pVCpu->hm.s.Event.fPending);
3599	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3600	Assert(pVmcb);
3601
3602	bool const fGif = CPUMGetGuestGif(pCtx);
3603	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3604	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3605
3606	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3607	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3608	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3609
3610	/** @todo SMI. SMIs take priority over NMIs. */
3611
3612	/*
3613	* Check if the guest or nested-guest can receive NMIs.
3614	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3615	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3616	*/
3617	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3618	&& !fBlockNmi)
3619	{
3620	if ( fGif
3621	&& !fIntShadow)
3622	{
3623	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3624	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3625	{
3626	Log4(("Intercepting NMI -> #VMEXIT\n"));
3627	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3628	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3629	}
3630	#endif
3631	Log4(("Setting NMI pending for injection\n"));
3632	SVMEVENT Event;
3633	Event.u = 0;
3634	Event.n.u1Valid = 1;
3635	Event.n.u8Vector = X86_XCPT_NMI;
3636	Event.n.u3Type = SVM_EVENT_NMI;
3637	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3638	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3639	}
3640	else if (!fGif)
3641	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3642	else if (!pSvmTransient->fIsNestedGuest)
3643	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3644	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3645	}
3646	/*
3647	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3648	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3649	* it from the APIC device.
3650	*
3651	* For nested-guests, physical interrupts always take priority over virtual interrupts.
3652	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3653	* do that work when we execute nested-guest code esp. since all the required information
3654	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3655	* the virtual interrupt controller.
3656	*
3657	* See AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3658	*/
3659	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3660	&& !pVCpu->hm.s.fSingleInstruction)
3661	{
3662	bool const fBlockInt = !pSvmTransient->fIsNestedGuest ? !(pCtx->eflags.u32 & X86_EFL_IF)
3663	: CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx);
3664	if ( fGif
3665	&& !fBlockInt
3666	&& !fIntShadow)
3667	{
3668	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3669	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3670	{
3671	Log4(("Intercepting INTR -> #VMEXIT\n"));
3672	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3673	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3674	}
3675	#endif
3676	uint8_t u8Interrupt;
3677	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3678	if (RT_SUCCESS(rc))
3679	{
3680	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3681	SVMEVENT Event;
3682	Event.u = 0;
3683	Event.n.u1Valid = 1;
3684	Event.n.u8Vector = u8Interrupt;
3685	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3686	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3687	}
3688	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3689	{
3690	/*
3691	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3692	* updated eventually when the TPR is written by the guest.
3693	*/
3694	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3695	}
3696	else
3697	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3698	}
3699	else if (!fGif)
3700	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3701	else if (!pSvmTransient->fIsNestedGuest)
3702	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3703	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3704	}
3705
3706	return VINF_SUCCESS;
3707	}
3708
3709
3710	/**
3711	* Injects any pending events into the guest (or nested-guest).
3712	*
3713	* @param pVCpu The cross context virtual CPU structure.
3714	* @param pVmcb Pointer to the VM control block.
3715	*
3716	* @remarks Must only be called when we are guaranteed to enter
3717	* hardware-assisted SVM execution and not return to ring-3
3718	* prematurely.
3719	*/
3720	static void hmR0SvmInjectPendingEvent(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3721	{
3722	Assert(!TRPMHasTrap(pVCpu));
3723	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3724
3725	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3726	#ifdef VBOX_STRICT
3727	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3728	bool const fGif = CPUMGetGuestGif(pCtx);
3729	bool fAllowInt = fGif;
3730	if (fGif)
3731	{
3732	/*
3733	* For nested-guests we have no way to determine if we're injecting a physical or
3734	* virtual interrupt at this point. Hence the partial verification below.
3735	*/
3736	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3737	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3738	else
3739	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3740	}
3741	#endif
3742
3743	if (pVCpu->hm.s.Event.fPending)
3744	{
3745	SVMEVENT Event;
3746	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3747	Assert(Event.n.u1Valid);
3748
3749	/*
3750	* Validate event injection pre-conditions.
3751	*/
3752	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3753	{
3754	Assert(fAllowInt);
3755	Assert(!fIntShadow);
3756	}
3757	else if (Event.n.u3Type == SVM_EVENT_NMI)
3758	{
3759	Assert(fGif);
3760	Assert(!fIntShadow);
3761	}
3762
3763	/*
3764	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3765	* do this only when we are surely going to inject the NMI as otherwise if we return
3766	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3767	* SVM R0.
3768	*
3769	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3770	* which will set the VMCS field after actually delivering the NMI which we read on
3771	* VM-exit to determine the state.
3772	*/
3773	if ( Event.n.u3Type == SVM_EVENT_NMI
3774	&& Event.n.u8Vector == X86_XCPT_NMI
3775	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3776	{
3777	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3778	}
3779
3780	/*
3781	* Inject it (update VMCB for injection by the hardware).
3782	*/
3783	Log4(("Injecting pending HM event\n"));
3784	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
3785	pVCpu->hm.s.Event.fPending = false;
3786
3787	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3788	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3789	else
3790	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3791	}
3792	else
3793	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3794
3795	/*
3796	* We could have injected an NMI through IEM and continue guest execution using
3797	* hardware-assisted SVM. In which case, we would not have any events pending (above)
3798	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
3799	*/
3800	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3801	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
3802
3803	/*
3804	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3805	*
3806	* For nested-guests: We need to update it too for the scenario where IEM executes
3807	* the nested-guest but execution later continues here with an interrupt shadow active.
3808	*/
3809	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3810	}
3811
3812
3813	/**
3814	* Reports world-switch error and dumps some useful debug info.
3815	*
3816	* @param pVCpu The cross context virtual CPU structure.
3817	* @param rcVMRun The return code from VMRUN (or
3818	* VERR_SVM_INVALID_GUEST_STATE for invalid
3819	* guest-state).
3820	*/
3821	static void hmR0SvmReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun)
3822	{
3823	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3824	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
3825	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3826
3827	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3828	{
3829	#ifdef VBOX_STRICT
3830	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
3831	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3832	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3833	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3834	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3835	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3836	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3837	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3838	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3839	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3840	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3841	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3842
3843	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3844	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3845	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3846
3847	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3848	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3849	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3850	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3851	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3852	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3853	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3854	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3855	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3856	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3857	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3858	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3859
3860	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3861	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3862	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3863	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3864	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3865	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3866	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3867	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3868	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3869	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3870	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3871	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3872	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3873	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3874	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3875	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3876	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3877	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3878	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3879	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3880
3881	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3882
3883	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3884	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3885
3886	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3887	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3888	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3889	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3890	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3891	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3892	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3893	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3894	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3895	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3896	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3897	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3898	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3899	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3900	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3901	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3902	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3903	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3904	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3905	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3906
3907	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3908	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3909
3910	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3911	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3912	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3913	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3914
3915	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3916	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3917
3918	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3919	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3920	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3921	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3922
3923	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3924	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3925	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3926	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3927	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3928	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3929	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3930
3931	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3932	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3933	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3934	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3935
3936	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3937	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3938	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3939
3940	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3941	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3942	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3943	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3944	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3945	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3946	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
3947	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3948	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3949	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3950	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3951	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3952
3953	NOREF(pVmcb);
3954	#endif /* VBOX_STRICT */
3955	}
3956	else
3957	Log4Func(("rcVMRun=%d\n", rcVMRun));
3958	}
3959
3960
3961	/**
3962	* Check per-VM and per-VCPU force flag actions that require us to go back to
3963	* ring-3 for one reason or another.
3964	*
3965	* @returns Strict VBox status code (information status code included).
3966	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3967	* ring-3.
3968	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3969	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3970	* interrupts)
3971	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3972	* all EMTs to be in ring-3.
3973	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3974	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3975	* to the EM loop.
3976	*
3977	* @param pVCpu The cross context virtual CPU structure.
3978	*/
3979	static VBOXSTRICTRC hmR0SvmCheckForceFlags(PVMCPUCC pVCpu)
3980	{
3981	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3982	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3983
3984	/* Could happen as a result of longjump. */
3985	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3986	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
3987
3988	/* Update pending interrupts into the APIC's IRR. */
3989	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3990	APICUpdatePendingInterrupts(pVCpu);
3991
3992	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3993	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
3994	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3995	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
3996	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3997	{
3998	/* Pending PGM C3 sync. */
3999	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4000	{
4001	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
4002	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4003	if (rc != VINF_SUCCESS)
4004	{
4005	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4006	return rc;
4007	}
4008	}
4009
4010	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4011	/* -XXX- what was that about single stepping? */
4012	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
4013	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4014	{
4015	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4016	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
4017	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4018	return rc;
4019	}
4020
4021	/* Pending VM request packets, such as hardware interrupts. */
4022	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
4023	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
4024	{
4025	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
4026	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4027	return VINF_EM_PENDING_REQUEST;
4028	}
4029
4030	/* Pending PGM pool flushes. */
4031	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4032	{
4033	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
4034	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4035	return VINF_PGM_POOL_FLUSH_PENDING;
4036	}
4037
4038	/* Pending DMA requests. */
4039	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
4040	{
4041	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
4042	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4043	return VINF_EM_RAW_TO_R3;
4044	}
4045	}
4046
4047	return VINF_SUCCESS;
4048	}
4049
4050
4051	/**
4052	* Does the preparations before executing guest code in AMD-V.
4053	*
4054	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4055	* recompiler. We must be cautious what we do here regarding committing
4056	* guest-state information into the VMCB assuming we assuredly execute the guest
4057	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4058	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4059	* that the recompiler can (and should) use them when it resumes guest
4060	* execution. Otherwise such operations must be done when we can no longer
4061	* exit to ring-3.
4062	*
4063	* @returns Strict VBox status code (informational status codes included).
4064	* @retval VINF_SUCCESS if we can proceed with running the guest.
4065	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4066	*
4067	* @param pVCpu The cross context virtual CPU structure.
4068	* @param pSvmTransient Pointer to the SVM transient structure.
4069	*/
4070	static VBOXSTRICTRC hmR0SvmPreRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4071	{
4072	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4073
4074	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4075	if (pSvmTransient->fIsNestedGuest)
4076	{
4077	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4078	return VINF_EM_RESCHEDULE_REM;
4079	}
4080	#endif
4081
4082	/* Check force flag actions that might require us to go back to ring-3. */
4083	VBOXSTRICTRC rc = hmR0SvmCheckForceFlags(pVCpu);
4084	if (rc != VINF_SUCCESS)
4085	return rc;
4086
4087	if (TRPMHasTrap(pVCpu))
4088	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4089	else if (!pVCpu->hm.s.Event.fPending)
4090	{
4091	rc = hmR0SvmEvaluatePendingEvent(pVCpu, pSvmTransient);
4092	if ( rc != VINF_SUCCESS
4093	\|\| pSvmTransient->fIsNestedGuest != CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4094	{
4095	/* If a nested-guest VM-exit occurred, bail. */
4096	if (pSvmTransient->fIsNestedGuest)
4097	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4098	return rc;
4099	}
4100	}
4101
4102	/*
4103	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4104	* Just do it in software, see @bugref{8411}.
4105	* NB: If we could continue a task switch exit we wouldn't need to do this.
4106	*/
4107	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4108	if (RT_UNLIKELY( !g_fHmSvmFeatures
4109	&& pVCpu->hm.s.Event.fPending
4110	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4111	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4112
4113	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4114	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4115	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4116	#endif
4117
4118	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4119	/*
4120	* Set up the nested-guest VMCB for execution using hardware-assisted SVM.
4121	*/
4122	if (pSvmTransient->fIsNestedGuest)
4123	hmR0SvmSetupVmcbNested(pVCpu);
4124	#endif
4125
4126	/*
4127	* Export the guest state bits that are not shared with the host in any way as we can
4128	* longjmp or get preempted in the midst of exporting some of the state.
4129	*/
4130	rc = hmR0SvmExportGuestState(pVCpu, pSvmTransient);
4131	AssertRCReturn(rc, rc);
4132	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4133
4134	/* Ensure we've cached (and hopefully modified) the nested-guest VMCB for execution using hardware-assisted SVM. */
4135	Assert(!pSvmTransient->fIsNestedGuest \|\| pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4136
4137	/*
4138	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4139	* world-switch so we can update it on the way back if the guest changed the TPR.
4140	*/
4141	if (pVCpu->hmr0.s.svm.fSyncVTpr)
4142	{
4143	Assert(!pSvmTransient->fIsNestedGuest);
4144	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4145	if (pVM->hm.s.fTprPatchingActive)
4146	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4147	else
4148	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4149	}
4150
4151	/*
4152	* No longjmps to ring-3 from this point on!!!
4153	*
4154	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4155	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4156	*/
4157	VMMRZCallRing3Disable(pVCpu);
4158
4159	/*
4160	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4161	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4162	* preemption disabled for a while. Since this is purly to aid the
4163	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4164	* disable interrupt on NT.
4165	*
4166	* We need to check for force-flags that could've possible been altered since we last
4167	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4168	* see @bugref{6398}).
4169	*
4170	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4171	* to ring-3 before executing guest code.
4172	*/
4173	pSvmTransient->fEFlags = ASMIntDisableFlags();
4174	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4175	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4176	{
4177	ASMSetFlags(pSvmTransient->fEFlags);
4178	VMMRZCallRing3Enable(pVCpu);
4179	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4180	return VINF_EM_RAW_TO_R3;
4181	}
4182	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4183	{
4184	ASMSetFlags(pSvmTransient->fEFlags);
4185	VMMRZCallRing3Enable(pVCpu);
4186	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4187	return VINF_EM_RAW_INTERRUPT;
4188	}
4189
4190	return VINF_SUCCESS;
4191	}
4192
4193
4194	/**
4195	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4196	* doing so.
4197	*
4198	* This means there is no backing out to ring-3 or anywhere else at this point.
4199	*
4200	* @param pVCpu The cross context virtual CPU structure.
4201	* @param pSvmTransient Pointer to the SVM transient structure.
4202	*
4203	* @remarks Called with preemption disabled.
4204	* @remarks No-long-jump zone!!!
4205	*/
4206	static void hmR0SvmPreRunGuestCommitted(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4207	{
4208	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4209	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4210	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4211
4212	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4213	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4214
4215	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4216	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4217
4218	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4219
4220	if (!CPUMIsGuestFPUStateActive(pVCpu))
4221	{
4222	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4223	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4224	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4225	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4226	}
4227
4228	/* Load the state shared between host and guest (FPU, debug). */
4229	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4230	hmR0SvmExportSharedState(pVCpu, pVmcb);
4231
4232	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4233	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4234
4235	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4236	RTCPUID const idHostCpu = pHostCpu->idCpu;
4237	bool const fMigratedHostCpu = idHostCpu != pVCpu->hmr0.s.idLastCpu;
4238
4239	/* Setup TSC offsetting. */
4240	if ( pSvmTransient->fUpdateTscOffsetting
4241	\|\| fMigratedHostCpu)
4242	{
4243	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4244	pSvmTransient->fUpdateTscOffsetting = false;
4245	}
4246
4247	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
4248	if (!(pVmcb->ctrl.u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
4249	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4250	else
4251	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4252
4253	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4254	if (fMigratedHostCpu)
4255	pVmcb->ctrl.u32VmcbCleanBits = 0;
4256
4257	/* Store status of the shared guest-host state at the time of VMRUN. */
4258	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4259	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4260
4261	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4262	uint8_t *pbMsrBitmap;
4263	if (!pSvmTransient->fIsNestedGuest)
4264	pbMsrBitmap = (uint8_t *)pVCpu->hmr0.s.svm.pvMsrBitmap;
4265	else
4266	{
4267	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4268
4269	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4270	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4271	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4272	}
4273	#else
4274	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4275	#endif
4276
4277	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4278	/* Flush the appropriate tagged-TLB entries. */
4279	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4280	Assert(pVCpu->hmr0.s.idLastCpu == idHostCpu);
4281
4282	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4283
4284	TMNotifyStartOfExecution(pVM, pVCpu); /* Finally, notify TM to resume its clocks as we're about
4285	to start executing. */
4286
4287	/*
4288	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4289	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4290	*
4291	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4292	*/
4293	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4294	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4295	{
4296	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4297	pVCpu->hmr0.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4298	if (uGuestTscAux != pVCpu->hmr0.s.svm.u64HostTscAux)
4299	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4300	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4301	pSvmTransient->fRestoreTscAuxMsr = true;
4302	}
4303	else
4304	{
4305	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4306	pSvmTransient->fRestoreTscAuxMsr = false;
4307	}
4308	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4309
4310	/*
4311	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4312	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4313	* from the VMCB.
4314	*/
4315	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pSvmTransient->fIsNestedGuest);
4316	if (!fSupportsVmcbCleanBits)
4317	pVmcb->ctrl.u32VmcbCleanBits = 0;
4318	}
4319
4320
4321	/**
4322	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4323	*
4324	* @returns VBox strict status code.
4325	* @param pVCpu The cross context virtual CPU structure.
4326	* @param HCPhysVmcb The host physical address of the VMCB.
4327	*
4328	* @remarks No-long-jump zone!!!
4329	*/
4330	DECLINLINE(int) hmR0SvmRunGuest(PVMCPUCC pVCpu, RTHCPHYS HCPhysVmcb)
4331	{
4332	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4333	pVCpu->cpum.GstCtx.fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4334	return pVCpu->hmr0.s.svm.pfnVMRun(pVCpu->CTX_SUFF(pVM), pVCpu, HCPhysVmcb);
4335	}
4336
4337
4338	/**
4339	* Performs some essential restoration of state after running guest (or
4340	* nested-guest) code in AMD-V.
4341	*
4342	* @param pVCpu The cross context virtual CPU structure.
4343	* @param pSvmTransient Pointer to the SVM transient structure.
4344	* @param rcVMRun Return code of VMRUN.
4345	*
4346	* @remarks Called with interrupts disabled.
4347	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4348	* unconditionally when it is safe to do so.
4349	*/
4350	static void hmR0SvmPostRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient, VBOXSTRICTRC rcVMRun)
4351	{
4352	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4353
4354	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4355	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4356	ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4357
4358	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4359	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4360
4361	/* TSC read must be done early for maximum accuracy. */
4362	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4363	{
4364	if (!pSvmTransient->fIsNestedGuest)
4365	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4366	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4367	else
4368	{
4369	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4370	uint64_t const uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4371	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4372	}
4373	#endif
4374	}
4375
4376	if (pSvmTransient->fRestoreTscAuxMsr)
4377	{
4378	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4379	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4380	if (u64GuestTscAuxMsr != pVCpu->hmr0.s.svm.u64HostTscAux)
4381	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hmr0.s.svm.u64HostTscAux);
4382	}
4383
4384	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4385	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4386	TMNotifyEndOfExecution(pVM, pVCpu); /* Notify TM that the guest is no longer running. */
4387	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4388
4389	Assert(!(ASMGetFlags() & X86_EFL_IF));
4390	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4391	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4392
4393	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4394	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4395	{
4396	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", VBOXSTRICTRC_VAL(rcVMRun)));
4397	return;
4398	}
4399
4400	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4401	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4402	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4403	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4404
4405	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4406	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4407	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4408	#else
4409	/*
4410	* Always import the following:
4411	*
4412	* - RIP for exit optimizations and evaluating event injection on re-entry.
4413	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4414	* state on preemption.
4415	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4416	* - CS for exit optimizations.
4417	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4418	* assembly switcher code.
4419	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4420	*/
4421	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4422	\| CPUMCTX_EXTRN_RFLAGS
4423	\| CPUMCTX_EXTRN_RAX
4424	\| CPUMCTX_EXTRN_RSP
4425	\| CPUMCTX_EXTRN_CS
4426	\| CPUMCTX_EXTRN_HWVIRT
4427	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4428	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4429	\| HMSVM_CPUMCTX_SHARED_STATE);
4430	#endif
4431
4432	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4433	&& pVCpu->hmr0.s.svm.fSyncVTpr)
4434	{
4435	Assert(!pSvmTransient->fIsNestedGuest);
4436	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4437	if ( pVM->hm.s.fTprPatchingActive
4438	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4439	{
4440	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4441	AssertRC(rc);
4442	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4443	}
4444	/* Sync TPR when we aren't intercepting CR8 writes. */
4445	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4446	{
4447	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4448	AssertRC(rc);
4449	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4450	}
4451	}
4452
4453	#ifdef DEBUG_ramshankar
4454	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4455	{
4456	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4457	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4458	0 /* uVerbose */);
4459	}
4460	#endif
4461
4462	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4463	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4464	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, uHostTsc);
4465	}
4466
4467
4468	/**
4469	* Runs the guest code using AMD-V.
4470	*
4471	* @returns Strict VBox status code.
4472	* @param pVCpu The cross context virtual CPU structure.
4473	* @param pcLoops Pointer to the number of executed loops.
4474	*/
4475	static VBOXSTRICTRC hmR0SvmRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
4476	{
4477	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4478	Assert(pcLoops);
4479	Assert(*pcLoops <= cMaxResumeLoops);
4480
4481	SVMTRANSIENT SvmTransient;
4482	RT_ZERO(SvmTransient);
4483	SvmTransient.fUpdateTscOffsetting = true;
4484	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4485
4486	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4487	for (;;)
4488	{
4489	Assert(!HMR0SuspendPending());
4490	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4491
4492	/* Preparatory work for running nested-guest code, this may force us to return to
4493	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4494	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4495	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4496	if (rc != VINF_SUCCESS)
4497	break;
4498
4499	/*
4500	* No longjmps to ring-3 from this point on!!!
4501	*
4502	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4503	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4504	*/
4505	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4506	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4507
4508	/* Restore any residual host-state and save any bits shared between host and guest
4509	into the guest-CPU state. Re-enables interrupts! */
4510	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4511
4512	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4513	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4514	{
4515	if (rc == VINF_SUCCESS)
4516	rc = VERR_SVM_INVALID_GUEST_STATE;
4517	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4518	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4519	break;
4520	}
4521
4522	/* Handle the #VMEXIT. */
4523	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4524	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4525	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4526	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4527	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4528	if (rc != VINF_SUCCESS)
4529	break;
4530	if (++(*pcLoops) >= cMaxResumeLoops)
4531	{
4532	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4533	rc = VINF_EM_RAW_INTERRUPT;
4534	break;
4535	}
4536	}
4537
4538	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4539	return rc;
4540	}
4541
4542
4543	/**
4544	* Runs the guest code using AMD-V in single step mode.
4545	*
4546	* @returns Strict VBox status code.
4547	* @param pVCpu The cross context virtual CPU structure.
4548	* @param pcLoops Pointer to the number of executed loops.
4549	*/
4550	static VBOXSTRICTRC hmR0SvmRunGuestCodeStep(PVMCPUCC pVCpu, uint32_t *pcLoops)
4551	{
4552	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4553	Assert(pcLoops);
4554	Assert(*pcLoops <= cMaxResumeLoops);
4555
4556	SVMTRANSIENT SvmTransient;
4557	RT_ZERO(SvmTransient);
4558	SvmTransient.fUpdateTscOffsetting = true;
4559	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4560
4561	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4562	uint16_t uCsStart = pCtx->cs.Sel;
4563	uint64_t uRipStart = pCtx->rip;
4564
4565	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4566	for (;;)
4567	{
4568	Assert(!HMR0SuspendPending());
4569	AssertMsg(pVCpu->hmr0.s.idEnteredCpu == RTMpCpuId(),
4570	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hmr0.s.idEnteredCpu,
4571	(unsigned)RTMpCpuId(), *pcLoops));
4572
4573	/* Preparatory work for running nested-guest code, this may force us to return to
4574	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4575	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4576	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4577	if (rc != VINF_SUCCESS)
4578	break;
4579
4580	/*
4581	* No longjmps to ring-3 from this point on!!!
4582	*
4583	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4584	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4585	*/
4586	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4587
4588	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4589
4590	/* Restore any residual host-state and save any bits shared between host and guest
4591	into the guest-CPU state. Re-enables interrupts! */
4592	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4593
4594	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4595	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4596	{
4597	if (rc == VINF_SUCCESS)
4598	rc = VERR_SVM_INVALID_GUEST_STATE;
4599	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4600	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4601	return rc;
4602	}
4603
4604	/* Handle the #VMEXIT. */
4605	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4606	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4607	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4608	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4609	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4610	if (rc != VINF_SUCCESS)
4611	break;
4612	if (++(*pcLoops) >= cMaxResumeLoops)
4613	{
4614	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4615	rc = VINF_EM_RAW_INTERRUPT;
4616	break;
4617	}
4618
4619	/*
4620	* Did the RIP change, if so, consider it a single step.
4621	* Otherwise, make sure one of the TFs gets set.
4622	*/
4623	if ( pCtx->rip != uRipStart
4624	\|\| pCtx->cs.Sel != uCsStart)
4625	{
4626	rc = VINF_EM_DBG_STEPPED;
4627	break;
4628	}
4629	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4630	}
4631
4632	/*
4633	* Clear the X86_EFL_TF if necessary.
4634	*/
4635	if (pVCpu->hmr0.s.fClearTrapFlag)
4636	{
4637	pVCpu->hmr0.s.fClearTrapFlag = false;
4638	pCtx->eflags.Bits.u1TF = 0;
4639	}
4640
4641	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4642	return rc;
4643	}
4644
4645	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4646	/**
4647	* Runs the nested-guest code using AMD-V.
4648	*
4649	* @returns Strict VBox status code.
4650	* @param pVCpu The cross context virtual CPU structure.
4651	* @param pcLoops Pointer to the number of executed loops. If we're switching
4652	* from the guest-code execution loop to this nested-guest
4653	* execution loop pass the remainder value, else pass 0.
4654	*/
4655	static VBOXSTRICTRC hmR0SvmRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
4656	{
4657	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4658	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4659	Assert(pcLoops);
4660	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops);
4661
4662	SVMTRANSIENT SvmTransient;
4663	RT_ZERO(SvmTransient);
4664	SvmTransient.fUpdateTscOffsetting = true;
4665	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4666	SvmTransient.fIsNestedGuest = true;
4667
4668	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_4;
4669	for (;;)
4670	{
4671	Assert(!HMR0SuspendPending());
4672	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4673
4674	/* Preparatory work for running nested-guest code, this may force us to return to
4675	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4676	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4677	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4678	if ( rc != VINF_SUCCESS
4679	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4680	break;
4681
4682	/*
4683	* No longjmps to ring-3 from this point on!!!
4684	*
4685	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4686	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4687	*/
4688	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4689
4690	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
4691
4692	/* Restore any residual host-state and save any bits shared between host and guest
4693	into the guest-CPU state. Re-enables interrupts! */
4694	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4695
4696	if (RT_LIKELY( rc == VINF_SUCCESS
4697	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4698	{ /* extremely likely */ }
4699	else
4700	{
4701	/* VMRUN failed, shouldn't really happen, Guru. */
4702	if (rc != VINF_SUCCESS)
4703	break;
4704
4705	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4706	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4707	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4708	rc = IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0);
4709	break;
4710	}
4711
4712	/* Handle the #VMEXIT. */
4713	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4714	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4715	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4716	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
4717	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4718	if (rc == VINF_SUCCESS)
4719	{
4720	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4721	{
4722	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4723	rc = VINF_SVM_VMEXIT;
4724	}
4725	else
4726	{
4727	if (++(*pcLoops) <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops)
4728	continue;
4729	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4730	rc = VINF_EM_RAW_INTERRUPT;
4731	}
4732	}
4733	else
4734	Assert(rc != VINF_SVM_VMEXIT);
4735	break;
4736	/** @todo NSTSVM: handle single-stepping. */
4737	}
4738
4739	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4740	return rc;
4741	}
4742	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
4743
4744
4745	/**
4746	* Runs the guest code using AMD-V.
4747	*
4748	* @returns Strict VBox status code.
4749	* @param pVCpu The cross context virtual CPU structure.
4750	*/
4751	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPUCC pVCpu)
4752	{
4753	AssertPtr(pVCpu);
4754	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4755	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4756	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4757	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4758
4759	uint32_t cLoops = 0;
4760	VBOXSTRICTRC rc;
4761	for (;;)
4762	{
4763	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4764	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
4765	#else
4766	NOREF(pCtx);
4767	bool const fInNestedGuestMode = false;
4768	#endif
4769	if (!fInNestedGuestMode)
4770	{
4771	if (!pVCpu->hm.s.fSingleInstruction)
4772	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
4773	else
4774	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
4775	}
4776	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4777	else
4778	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
4779
4780	if (rc == VINF_SVM_VMRUN)
4781	{
4782	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4783	continue;
4784	}
4785	if (rc == VINF_SVM_VMEXIT)
4786	{
4787	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4788	continue;
4789	}
4790	#endif
4791	break;
4792	}
4793
4794	/* Fixup error codes. */
4795	if (rc == VERR_EM_INTERPRETER)
4796	rc = VINF_EM_RAW_EMULATE_INSTR;
4797	else if (rc == VINF_EM_RESET)
4798	rc = VINF_EM_TRIPLE_FAULT;
4799
4800	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4801	rc = hmR0SvmExitToRing3(pVCpu, rc);
4802	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4803	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4804	return rc;
4805	}
4806
4807
4808	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4809	/**
4810	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
4811	*
4812	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4813	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4814	*/
4815	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4816	{
4817	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4818	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4819	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4820	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4821	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
4822	const bool fRep = pIoExitInfo->n.u1Rep;
4823	const bool fStrIo = pIoExitInfo->n.u1Str;
4824
4825	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4826	NULL /* pIoExitInfo */);
4827	}
4828
4829
4830	/**
4831	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4832	* SVM_EXIT_INVALID).
4833	*
4834	* @returns VBox status code (informational status codes included).
4835	* @param pVCpu The cross context virtual CPU structure.
4836	* @param pSvmTransient Pointer to the SVM transient structure.
4837	*/
4838	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4839	{
4840	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4841	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4842	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4843
4844	/*
4845	* We import the complete state here because we use separate VMCBs for the guest and the
4846	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
4847	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
4848	*/
4849	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4850	do { \
4851	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
4852	return IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); \
4853	} while (0)
4854
4855	/*
4856	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
4857	* nested-guest. If it isn't, it should be handled by the (outer) guest.
4858	*/
4859	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
4860	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4861	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4862	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4863	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4864	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4865
4866	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4867	switch (uExitCode)
4868	{
4869	case SVM_EXIT_CPUID:
4870	{
4871	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4872	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4873	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
4874	}
4875
4876	case SVM_EXIT_RDTSC:
4877	{
4878	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4879	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4880	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
4881	}
4882
4883	case SVM_EXIT_RDTSCP:
4884	{
4885	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4886	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4887	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
4888	}
4889
4890	case SVM_EXIT_MONITOR:
4891	{
4892	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4893	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4894	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
4895	}
4896
4897	case SVM_EXIT_MWAIT:
4898	{
4899	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4900	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4901	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
4902	}
4903
4904	case SVM_EXIT_HLT:
4905	{
4906	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4907	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4908	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
4909	}
4910
4911	case SVM_EXIT_MSR:
4912	{
4913	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4914	{
4915	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
4916	uint16_t offMsrpm;
4917	uint8_t uMsrpmBit;
4918	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4919	if (RT_SUCCESS(rc))
4920	{
4921	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
4922	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
4923
4924	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4925	pbMsrBitmap += offMsrpm;
4926	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
4927	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
4928
4929	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4930	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4931	{
4932	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4933	}
4934	}
4935	else
4936	{
4937	/*
4938	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4939	* See AMD-V spec. "15.11 MSR Intercepts".
4940	*/
4941	Assert(rc == VERR_OUT_OF_RANGE);
4942	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4943	}
4944	}
4945	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
4946	}
4947
4948	case SVM_EXIT_IOIO:
4949	{
4950	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4951	{
4952	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
4953	SVMIOIOEXITINFO IoExitInfo;
4954	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4955	bool const fIntercept = hmR0SvmIsIoInterceptSet(pvIoBitmap, &IoExitInfo);
4956	if (fIntercept)
4957	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4958	}
4959	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
4960	}
4961
4962	case SVM_EXIT_XCPT_PF:
4963	{
4964	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4965	if (pVM->hmr0.s.fNestedPaging)
4966	{
4967	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4968	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4969
4970	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4971	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4972	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4973
4974	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
4975	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
4976	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
4977	return VINF_SUCCESS;
4978	}
4979	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
4980	}
4981
4982	case SVM_EXIT_XCPT_UD:
4983	{
4984	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
4985	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4986	hmR0SvmSetPendingXcptUD(pVCpu);
4987	return VINF_SUCCESS;
4988	}
4989
4990	case SVM_EXIT_XCPT_MF:
4991	{
4992	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
4993	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4994	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
4995	}
4996
4997	case SVM_EXIT_XCPT_DB:
4998	{
4999	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5000	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5001	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
5002	}
5003
5004	case SVM_EXIT_XCPT_AC:
5005	{
5006	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5007	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5008	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
5009	}
5010
5011	case SVM_EXIT_XCPT_BP:
5012	{
5013	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5014	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5015	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
5016	}
5017
5018	case SVM_EXIT_READ_CR0:
5019	case SVM_EXIT_READ_CR3:
5020	case SVM_EXIT_READ_CR4:
5021	{
5022	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5023	if (CPUMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5024	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5025	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5026	}
5027
5028	case SVM_EXIT_CR0_SEL_WRITE:
5029	{
5030	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5031	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5032	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5033	}
5034
5035	case SVM_EXIT_WRITE_CR0:
5036	case SVM_EXIT_WRITE_CR3:
5037	case SVM_EXIT_WRITE_CR4:
5038	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5039	{
5040	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5041	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5042
5043	if (CPUMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5044	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5045	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5046	}
5047
5048	case SVM_EXIT_PAUSE:
5049	{
5050	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5051	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5052	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5053	}
5054
5055	case SVM_EXIT_VINTR:
5056	{
5057	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5058	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5059	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5060	}
5061
5062	case SVM_EXIT_INTR:
5063	case SVM_EXIT_NMI:
5064	case SVM_EXIT_SMI:
5065	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5066	{
5067	/*
5068	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5069	*
5070	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5071	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5072	* nested-guest #VMEXIT.
5073	*
5074	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5075	* while trying to inject interrupts, see comment at the top of this function.
5076	*/
5077	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5078	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5079	}
5080
5081	case SVM_EXIT_FERR_FREEZE:
5082	{
5083	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5084	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5085	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5086	}
5087
5088	case SVM_EXIT_INVLPG:
5089	{
5090	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5091	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5092	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5093	}
5094
5095	case SVM_EXIT_WBINVD:
5096	{
5097	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5098	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5099	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5100	}
5101
5102	case SVM_EXIT_INVD:
5103	{
5104	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5105	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5106	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5107	}
5108
5109	case SVM_EXIT_RDPMC:
5110	{
5111	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5112	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5113	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5114	}
5115
5116	default:
5117	{
5118	switch (uExitCode)
5119	{
5120	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5121	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5122	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5123	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5124	{
5125	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5126	if (CPUMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5127	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5128	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5129	}
5130
5131	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5132	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5133	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5134	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5135	{
5136	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5137	if (CPUMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5138	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5139	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5140	}
5141
5142	case SVM_EXIT_XCPT_DE:
5143	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5144	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5145	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5146	case SVM_EXIT_XCPT_OF:
5147	case SVM_EXIT_XCPT_BR:
5148	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5149	case SVM_EXIT_XCPT_NM:
5150	case SVM_EXIT_XCPT_DF:
5151	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5152	case SVM_EXIT_XCPT_TS:
5153	case SVM_EXIT_XCPT_NP:
5154	case SVM_EXIT_XCPT_SS:
5155	case SVM_EXIT_XCPT_GP:
5156	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5157	case SVM_EXIT_XCPT_15: /* Reserved. */
5158	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5159	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5160	case SVM_EXIT_XCPT_MC:
5161	case SVM_EXIT_XCPT_XF:
5162	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5163	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5164	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5165	{
5166	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5167	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5168	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5169	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5170	}
5171
5172	case SVM_EXIT_XSETBV:
5173	{
5174	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5175	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5176	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5177	}
5178
5179	case SVM_EXIT_TASK_SWITCH:
5180	{
5181	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5182	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5183	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5184	}
5185
5186	case SVM_EXIT_IRET:
5187	{
5188	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5189	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5190	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5191	}
5192
5193	case SVM_EXIT_SHUTDOWN:
5194	{
5195	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5196	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5197	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5198	}
5199
5200	case SVM_EXIT_VMMCALL:
5201	{
5202	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5203	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5204	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5205	}
5206
5207	case SVM_EXIT_CLGI:
5208	{
5209	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5210	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5211	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5212	}
5213
5214	case SVM_EXIT_STGI:
5215	{
5216	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5217	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5218	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5219	}
5220
5221	case SVM_EXIT_VMLOAD:
5222	{
5223	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5224	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5225	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5226	}
5227
5228	case SVM_EXIT_VMSAVE:
5229	{
5230	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5231	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5232	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5233	}
5234
5235	case SVM_EXIT_INVLPGA:
5236	{
5237	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5238	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5239	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5240	}
5241
5242	case SVM_EXIT_VMRUN:
5243	{
5244	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5245	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5246	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5247	}
5248
5249	case SVM_EXIT_RSM:
5250	{
5251	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5252	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5253	hmR0SvmSetPendingXcptUD(pVCpu);
5254	return VINF_SUCCESS;
5255	}
5256
5257	case SVM_EXIT_SKINIT:
5258	{
5259	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5260	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5261	hmR0SvmSetPendingXcptUD(pVCpu);
5262	return VINF_SUCCESS;
5263	}
5264
5265	case SVM_EXIT_NPF:
5266	{
5267	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5268	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5269	}
5270
5271	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5272	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5273
5274	default:
5275	{
5276	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5277	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5278	return VERR_SVM_UNKNOWN_EXIT;
5279	}
5280	}
5281	}
5282	}
5283	/* not reached */
5284
5285	#undef NST_GST_VMEXIT_CALL_RET
5286	}
5287	#endif
5288
5289
5290	/**
5291	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5292	*
5293	* @returns Strict VBox status code (informational status codes included).
5294	* @param pVCpu The cross context virtual CPU structure.
5295	* @param pSvmTransient Pointer to the SVM transient structure.
5296	*/
5297	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5298	{
5299	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5300	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5301
5302	#ifdef DEBUG_ramshankar
5303	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5304	do { \
5305	if ((a_fDbg) == 1) \
5306	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5307	int rc = a_CallExpr; \
5308	if ((a_fDbg) == 1) \
5309	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5310	return rc; \
5311	} while (0)
5312	#else
5313	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5314	#endif
5315
5316	/*
5317	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5318	* for most guests under normal workloads (for some definition of "normal").
5319	*/
5320	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5321	switch (uExitCode)
5322	{
5323	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5324	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5325	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5326	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5327	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5328	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5329	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5330	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5331	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5332	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5333
5334	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5335	case SVM_EXIT_INTR:
5336	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5337
5338	case SVM_EXIT_READ_CR0:
5339	case SVM_EXIT_READ_CR3:
5340	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5341
5342	case SVM_EXIT_CR0_SEL_WRITE:
5343	case SVM_EXIT_WRITE_CR0:
5344	case SVM_EXIT_WRITE_CR3:
5345	case SVM_EXIT_WRITE_CR4:
5346	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5347
5348	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5349	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5350	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5351	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5352	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5353	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5354	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5355	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5356	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5357	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5358	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5359	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5360	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5361	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5362	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5363	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5364
5365	default:
5366	{
5367	switch (pSvmTransient->u64ExitCode)
5368	{
5369	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5370	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5371	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5372	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5373	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5374
5375	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5376	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5377	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5378	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5379	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5380
5381	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5382	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5383
5384	case SVM_EXIT_SMI:
5385	case SVM_EXIT_INIT:
5386	{
5387	/*
5388	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5389	* If it ever does, we want to know about it so log the exit code and bail.
5390	*/
5391	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5392	}
5393
5394	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5395	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5396	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5397	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5398	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5399	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5400	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5401	#else
5402	case SVM_EXIT_CLGI:
5403	case SVM_EXIT_STGI:
5404	case SVM_EXIT_VMLOAD:
5405	case SVM_EXIT_VMSAVE:
5406	case SVM_EXIT_INVLPGA:
5407	case SVM_EXIT_VMRUN:
5408	#endif
5409	case SVM_EXIT_RSM:
5410	case SVM_EXIT_SKINIT:
5411	{
5412	hmR0SvmSetPendingXcptUD(pVCpu);
5413	return VINF_SUCCESS;
5414	}
5415
5416	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5417	case SVM_EXIT_XCPT_DE:
5418	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5419	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5420	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5421	case SVM_EXIT_XCPT_OF:
5422	case SVM_EXIT_XCPT_BR:
5423	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5424	case SVM_EXIT_XCPT_NM:
5425	case SVM_EXIT_XCPT_DF:
5426	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5427	case SVM_EXIT_XCPT_TS:
5428	case SVM_EXIT_XCPT_NP:
5429	case SVM_EXIT_XCPT_SS:
5430	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5431	/* SVM_EXIT_XCPT_PF: */
5432	case SVM_EXIT_XCPT_15: /* Reserved. */
5433	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5434	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5435	case SVM_EXIT_XCPT_MC:
5436	case SVM_EXIT_XCPT_XF:
5437	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5438	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5439	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5440	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5441	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5442
5443	default:
5444	{
5445	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5446	pVCpu->hm.s.u32HMError = uExitCode;
5447	return VERR_SVM_UNKNOWN_EXIT;
5448	}
5449	}
5450	}
5451	}
5452	/* not reached */
5453	#undef VMEXIT_CALL_RET
5454	}
5455
5456
5457	#ifdef VBOX_STRICT
5458	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5459	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5460	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5461
5462	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5463	do \
5464	{ \
5465	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5466	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5467	} while (0)
5468
5469	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5470	do { \
5471	AssertPtr((a_pVCpu)); \
5472	AssertPtr((a_pSvmTransient)); \
5473	Assert(ASMIntAreEnabled()); \
5474	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5475	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5476	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5477	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5478	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5479	HMSVM_ASSERT_PREEMPT_CPUID(); \
5480	} while (0)
5481	#else
5482	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5483	do { \
5484	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5485	} while (0)
5486	#endif
5487
5488
5489	/**
5490	* Gets the IEM exception flags for the specified SVM event.
5491	*
5492	* @returns The IEM exception flags.
5493	* @param pEvent Pointer to the SVM event.
5494	*
5495	* @remarks This function currently only constructs flags required for
5496	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5497	* and CR2 aspects of an exception are not included).
5498	*/
5499	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5500	{
5501	uint8_t const uEventType = pEvent->n.u3Type;
5502	uint32_t fIemXcptFlags;
5503	switch (uEventType)
5504	{
5505	case SVM_EVENT_EXCEPTION:
5506	/*
5507	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5508	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5509	*/
5510	if (pEvent->n.u8Vector == X86_XCPT_BP)
5511	{
5512	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5513	break;
5514	}
5515	if (pEvent->n.u8Vector == X86_XCPT_OF)
5516	{
5517	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5518	break;
5519	}
5520	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5521	RT_FALL_THRU();
5522	case SVM_EVENT_NMI:
5523	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5524	break;
5525
5526	case SVM_EVENT_EXTERNAL_IRQ:
5527	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5528	break;
5529
5530	case SVM_EVENT_SOFTWARE_INT:
5531	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5532	break;
5533
5534	default:
5535	fIemXcptFlags = 0;
5536	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5537	break;
5538	}
5539	return fIemXcptFlags;
5540	}
5541
5542
5543	/**
5544	* Handle a condition that occurred while delivering an event through the guest
5545	* IDT.
5546	*
5547	* @returns VBox status code (informational error codes included).
5548	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5549	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5550	* continue execution of the guest which will delivery the \#DF.
5551	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5552	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5553	*
5554	* @param pVCpu The cross context virtual CPU structure.
5555	* @param pSvmTransient Pointer to the SVM transient structure.
5556	*
5557	* @remarks No-long-jump zone!!!
5558	*/
5559	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5560	{
5561	int rc = VINF_SUCCESS;
5562	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5563	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5564
5565	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5566	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5567	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5568
5569	/*
5570	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5571	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5572	*
5573	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5574	*/
5575	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5576	{
5577	IEMXCPTRAISE enmRaise;
5578	IEMXCPTRAISEINFO fRaiseInfo;
5579	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5580	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5581	if (fExitIsHwXcpt)
5582	{
5583	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5584	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5585	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5586	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5587	}
5588	else
5589	{
5590	/*
5591	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5592	* then we end up here.
5593	*
5594	* If the event was:
5595	* - a software interrupt, we can re-execute the instruction which will
5596	* regenerate the event.
5597	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5598	* - a hardware exception or external interrupt, we re-inject it.
5599	*/
5600	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5601	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5602	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5603	else
5604	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5605	}
5606
5607	switch (enmRaise)
5608	{
5609	case IEMXCPTRAISE_CURRENT_XCPT:
5610	case IEMXCPTRAISE_PREV_EVENT:
5611	{
5612	/* For software interrupts, we shall re-execute the instruction. */
5613	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5614	{
5615	RTGCUINTPTR GCPtrFaultAddress = 0;
5616
5617	/* If we are re-injecting an NMI, clear NMI blocking. */
5618	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5619	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5620
5621	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5622	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5623	{
5624	pSvmTransient->fVectoringPF = true;
5625	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5626	pVCpu->cpum.GstCtx.cr2));
5627	}
5628	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5629	&& uIdtVector == X86_XCPT_PF)
5630	{
5631	/*
5632	* If the previous exception was a #PF, we need to recover the CR2 value.
5633	* This can't happen with shadow paging.
5634	*/
5635	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5636	}
5637
5638	/*
5639	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5640	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5641	*/
5642	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5643	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
5644	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5645
5646	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5647	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5648	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5649	}
5650	break;
5651	}
5652
5653	case IEMXCPTRAISE_REEXEC_INSTR:
5654	{
5655	Assert(rc == VINF_SUCCESS);
5656	break;
5657	}
5658
5659	case IEMXCPTRAISE_DOUBLE_FAULT:
5660	{
5661	/*
5662	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5663	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5664	* converted into a #DF.
5665	*/
5666	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5667	{
5668	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5669	pSvmTransient->fVectoringDoublePF = true;
5670	Assert(rc == VINF_SUCCESS);
5671	}
5672	else
5673	{
5674	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
5675	hmR0SvmSetPendingXcptDF(pVCpu);
5676	rc = VINF_HM_DOUBLE_FAULT;
5677	}
5678	break;
5679	}
5680
5681	case IEMXCPTRAISE_TRIPLE_FAULT:
5682	{
5683	rc = VINF_EM_RESET;
5684	break;
5685	}
5686
5687	case IEMXCPTRAISE_CPU_HANG:
5688	{
5689	rc = VERR_EM_GUEST_CPU_HANG;
5690	break;
5691	}
5692
5693	default:
5694	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
5695	}
5696	}
5697	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5698	return rc;
5699	}
5700
5701
5702	/**
5703	* Advances the guest RIP by the number of bytes specified in @a cb.
5704	*
5705	* @param pVCpu The cross context virtual CPU structure.
5706	* @param cb RIP increment value in bytes.
5707	*/
5708	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
5709	{
5710	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5711	pCtx->rip += cb;
5712
5713	/* Update interrupt shadow. */
5714	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5715	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
5716	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5717	}
5718
5719
5720	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5721	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5722	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5723
5724	/** @name \#VMEXIT handlers.
5725	* @{
5726	*/
5727
5728	/**
5729	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5730	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5731	*/
5732	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5733	{
5734	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5735
5736	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5737	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5738	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5739	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5740
5741	/*
5742	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
5743	* signal -before- the timer fires if the current interrupt is our own timer or a some
5744	* other host interrupt. We also cannot examine what interrupt it is until the host
5745	* actually take the interrupt.
5746	*
5747	* Going back to executing guest code here unconditionally causes random scheduling
5748	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5749	*/
5750	return VINF_EM_RAW_INTERRUPT;
5751	}
5752
5753
5754	/**
5755	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5756	*/
5757	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5758	{
5759	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5760
5761	VBOXSTRICTRC rcStrict;
5762	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5763	if (fSupportsNextRipSave)
5764	{
5765	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5766	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5767	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5768	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
5769	}
5770	else
5771	{
5772	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5773	rcStrict = IEMExecOne(pVCpu);
5774	}
5775
5776	if (rcStrict == VINF_IEM_RAISED_XCPT)
5777	{
5778	rcStrict = VINF_SUCCESS;
5779	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5780	}
5781	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5782	return rcStrict;
5783	}
5784
5785
5786	/**
5787	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5788	*/
5789	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5790	{
5791	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5792
5793	VBOXSTRICTRC rcStrict;
5794	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5795	if (fSupportsNextRipSave)
5796	{
5797	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5798	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5799	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5800	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
5801	}
5802	else
5803	{
5804	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5805	rcStrict = IEMExecOne(pVCpu);
5806	}
5807
5808	if (rcStrict == VINF_IEM_RAISED_XCPT)
5809	{
5810	rcStrict = VINF_SUCCESS;
5811	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5812	}
5813	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5814	return rcStrict;
5815	}
5816
5817
5818	/**
5819	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5820	*/
5821	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5822	{
5823	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5824
5825	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
5826	VBOXSTRICTRC rcStrict;
5827	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
5828	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
5829	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
5830	if (!pExitRec)
5831	{
5832	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5833	if (fSupportsNextRipSave)
5834	{
5835	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5836	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5837	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
5838	}
5839	else
5840	{
5841	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5842	rcStrict = IEMExecOne(pVCpu);
5843	}
5844
5845	if (rcStrict == VINF_IEM_RAISED_XCPT)
5846	{
5847	rcStrict = VINF_SUCCESS;
5848	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5849	}
5850	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5851	}
5852	else
5853	{
5854	/*
5855	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
5856	*/
5857	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5858
5859	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
5860	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
5861
5862	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
5863
5864	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
5865	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
5866	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
5867	}
5868	return rcStrict;
5869	}
5870
5871
5872	/**
5873	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5874	*/
5875	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5876	{
5877	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5878
5879	VBOXSTRICTRC rcStrict;
5880	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5881	if (fSupportsNextRipSave)
5882	{
5883	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5884	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5885	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5886	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
5887	}
5888	else
5889	{
5890	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5891	rcStrict = IEMExecOne(pVCpu);
5892	}
5893
5894	if (rcStrict == VINF_SUCCESS)
5895	pSvmTransient->fUpdateTscOffsetting = true;
5896	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5897	{
5898	rcStrict = VINF_SUCCESS;
5899	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5900	}
5901	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5902	return rcStrict;
5903	}
5904
5905
5906	/**
5907	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5908	*/
5909	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5910	{
5911	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5912
5913	VBOXSTRICTRC rcStrict;
5914	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5915	if (fSupportsNextRipSave)
5916	{
5917	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
5918	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5919	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5920	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
5921	}
5922	else
5923	{
5924	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5925	rcStrict = IEMExecOne(pVCpu);
5926	}
5927
5928	if (rcStrict == VINF_SUCCESS)
5929	pSvmTransient->fUpdateTscOffsetting = true;
5930	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5931	{
5932	rcStrict = VINF_SUCCESS;
5933	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5934	}
5935	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5936	return rcStrict;
5937	}
5938
5939
5940	/**
5941	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5942	*/
5943	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5944	{
5945	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5946
5947	VBOXSTRICTRC rcStrict;
5948	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5949	if (fSupportsNextRipSave)
5950	{
5951	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5952	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5953	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5954	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
5955	}
5956	else
5957	{
5958	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5959	rcStrict = IEMExecOne(pVCpu);
5960	}
5961
5962	if (rcStrict == VINF_IEM_RAISED_XCPT)
5963	{
5964	rcStrict = VINF_SUCCESS;
5965	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5966	}
5967	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5968	return rcStrict;
5969	}
5970
5971
5972	/**
5973	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5974	*/
5975	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5976	{
5977	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5978	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5979
5980	VBOXSTRICTRC rcStrict;
5981	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
5982	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5983	if ( fSupportsDecodeAssists
5984	&& fSupportsNextRipSave)
5985	{
5986	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
5987	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5988	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5989	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
5990	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
5991	}
5992	else
5993	{
5994	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5995	rcStrict = IEMExecOne(pVCpu);
5996	}
5997
5998	if (rcStrict == VINF_IEM_RAISED_XCPT)
5999	{
6000	rcStrict = VINF_SUCCESS;
6001	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6002	}
6003	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6004	return VBOXSTRICTRC_VAL(rcStrict);
6005	}
6006
6007
6008	/**
6009	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6010	*/
6011	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6012	{
6013	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6014
6015	VBOXSTRICTRC rcStrict;
6016	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6017	if (fSupportsNextRipSave)
6018	{
6019	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6020	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6021	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6022	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6023	}
6024	else
6025	{
6026	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6027	rcStrict = IEMExecOne(pVCpu);
6028	}
6029
6030	if ( rcStrict == VINF_EM_HALT
6031	\|\| rcStrict == VINF_SUCCESS)
6032	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6033	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6034	{
6035	rcStrict = VINF_SUCCESS;
6036	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6037	}
6038	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6039	if (rcStrict != VINF_SUCCESS)
6040	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6041	return VBOXSTRICTRC_VAL(rcStrict);;
6042	}
6043
6044
6045	/**
6046	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6047	*/
6048	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6049	{
6050	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6051
6052	/*
6053	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6054	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6055	* segment override prefix or other prefixes might be used, in which case we fallback to
6056	* IEMExecOne() to figure out.
6057	*/
6058	VBOXSTRICTRC rcStrict;
6059	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6060	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6061	if (cbInstr)
6062	{
6063	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6064	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6065	}
6066	else
6067	{
6068	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6069	rcStrict = IEMExecOne(pVCpu);
6070	}
6071
6072	if (rcStrict == VINF_IEM_RAISED_XCPT)
6073	{
6074	rcStrict = VINF_SUCCESS;
6075	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6076	}
6077	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6078	return rcStrict;
6079	}
6080
6081
6082	/**
6083	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6084	*/
6085	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6086	{
6087	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6088
6089	VBOXSTRICTRC rcStrict;
6090	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6091	if (fSupportsNextRipSave)
6092	{
6093	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6094	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6095	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6096	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6097	}
6098	else
6099	{
6100	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6101	rcStrict = IEMExecOne(pVCpu);
6102	}
6103
6104	if ( rcStrict == VINF_EM_HALT
6105	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6106	rcStrict = VINF_SUCCESS;
6107	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6108	{
6109	rcStrict = VINF_SUCCESS;
6110	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6111	}
6112	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6113	return rcStrict;
6114	}
6115
6116
6117	/**
6118	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6119	* \#VMEXIT.
6120	*/
6121	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6122	{
6123	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6124	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6125	return VINF_EM_RESET;
6126	}
6127
6128
6129	/**
6130	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6131	*/
6132	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6133	{
6134	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6135	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6136	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6137	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6138	RT_NOREF(pVmcb);
6139	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6140	return VERR_SVM_UNEXPECTED_EXIT;
6141	}
6142
6143
6144	/**
6145	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6146	*/
6147	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6148	{
6149	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6150
6151	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6152	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6153	#ifdef VBOX_WITH_STATISTICS
6154	switch (pSvmTransient->u64ExitCode)
6155	{
6156	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6157	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6158	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6159	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6160	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6161	}
6162	#endif
6163
6164	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6165	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6166	if ( fSupportsDecodeAssists
6167	&& fSupportsNextRipSave)
6168	{
6169	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6170	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6171	if (fMovCRx)
6172	{
6173	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6174	\| CPUMCTX_EXTRN_APIC_TPR);
6175	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6176	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6177	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6178	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6179	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6180	return VBOXSTRICTRC_VAL(rcStrict);
6181	}
6182	/* else: SMSW instruction, fall back below to IEM for this. */
6183	}
6184
6185	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6186	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6187	AssertMsg( rcStrict == VINF_SUCCESS
6188	\|\| rcStrict == VINF_PGM_SYNC_CR3
6189	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6190	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6191	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6192	if (rcStrict == VINF_IEM_RAISED_XCPT)
6193	{
6194	rcStrict = VINF_SUCCESS;
6195	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6196	}
6197	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6198	return rcStrict;
6199	}
6200
6201
6202	/**
6203	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6204	*/
6205	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6206	{
6207	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6208
6209	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6210	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6211	Assert(iCrReg <= 15);
6212
6213	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6214	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6215	bool fDecodedInstr = false;
6216	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6217	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6218	if ( fSupportsDecodeAssists
6219	&& fSupportsNextRipSave)
6220	{
6221	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6222	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6223	if (fMovCRx)
6224	{
6225	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6226	\| CPUMCTX_EXTRN_APIC_TPR);
6227	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6228	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6229	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6230	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6231	fDecodedInstr = true;
6232	}
6233	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6234	}
6235
6236	if (!fDecodedInstr)
6237	{
6238	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6239	Log4Func(("iCrReg=%#x\n", iCrReg));
6240	rcStrict = IEMExecOne(pVCpu);
6241	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6242	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6243	rcStrict = VERR_EM_INTERPRETER;
6244	}
6245
6246	if (rcStrict == VINF_SUCCESS)
6247	{
6248	switch (iCrReg)
6249	{
6250	case 0:
6251	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6252	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6253	break;
6254
6255	case 2:
6256	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6257	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6258	break;
6259
6260	case 3:
6261	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6262	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6263	break;
6264
6265	case 4:
6266	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6267	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6268	break;
6269
6270	case 8:
6271	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6272	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6273	break;
6274
6275	default:
6276	{
6277	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6278	pSvmTransient->u64ExitCode, iCrReg));
6279	break;
6280	}
6281	}
6282	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6283	}
6284	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6285	{
6286	rcStrict = VINF_SUCCESS;
6287	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6288	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6289	}
6290	else
6291	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6292	return rcStrict;
6293	}
6294
6295
6296	/**
6297	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6298	*
6299	* @returns Strict VBox status code.
6300	* @param pVCpu The cross context virtual CPU structure.
6301	* @param pVmcb Pointer to the VM control block.
6302	*/
6303	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
6304	{
6305	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6306	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6307
6308	VBOXSTRICTRC rcStrict;
6309	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6310	if (fSupportsNextRipSave)
6311	{
6312	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6313	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6314	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6315	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6316	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6317	}
6318	else
6319	{
6320	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6321	rcStrict = IEMExecOne(pVCpu);
6322	}
6323
6324	AssertMsg( rcStrict == VINF_SUCCESS
6325	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6326	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6327	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6328
6329	if (rcStrict == VINF_IEM_RAISED_XCPT)
6330	{
6331	rcStrict = VINF_SUCCESS;
6332	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6333	}
6334	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6335	return rcStrict;
6336	}
6337
6338
6339	/**
6340	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6341	*
6342	* @returns Strict VBox status code.
6343	* @param pVCpu The cross context virtual CPU structure.
6344	* @param pVmcb Pointer to the VM control block.
6345	* @param pSvmTransient Pointer to the SVM-transient structure.
6346	*/
6347	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6348	{
6349	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6350	uint32_t const idMsr = pCtx->ecx;
6351	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6352	Log4Func(("idMsr=%#RX32\n", idMsr));
6353
6354	/*
6355	* Handle TPR patching MSR writes.
6356	* We utilitize the LSTAR MSR for patching.
6357	*/
6358	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6359	if ( idMsr == MSR_K8_LSTAR
6360	&& pVCpu->CTX_SUFF(pVM)->hm.s.fTprPatchingActive)
6361	{
6362	unsigned cbInstr;
6363	if (fSupportsNextRipSave)
6364	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6365	else
6366	{
6367	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
6368	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6369	if ( rc == VINF_SUCCESS
6370	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6371	Assert(cbInstr > 0);
6372	else
6373	cbInstr = 0;
6374	}
6375
6376	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6377	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6378	{
6379	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6380	AssertRCReturn(rc, rc);
6381	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6382	}
6383
6384	int rc = VINF_SUCCESS;
6385	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6386	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6387	return rc;
6388	}
6389
6390	/*
6391	* Handle regular MSR writes.
6392	*/
6393	VBOXSTRICTRC rcStrict;
6394	if (fSupportsNextRipSave)
6395	{
6396	/** @todo Optimize this: We don't need to get much of the MSR state here
6397	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6398	* clear the applicable extern flags. */
6399	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6400	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6401	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6402	}
6403	else
6404	{
6405	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6406	rcStrict = IEMExecOne(pVCpu);
6407	}
6408
6409	AssertMsg( rcStrict == VINF_SUCCESS
6410	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6411	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6412	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6413
6414	if (rcStrict == VINF_SUCCESS)
6415	{
6416	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6417	if ( idMsr >= MSR_IA32_X2APIC_START
6418	&& idMsr <= MSR_IA32_X2APIC_END)
6419	{
6420	/*
6421	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6422	* When full APIC register virtualization is implemented we'll have to make sure
6423	* APIC state is saved from the VMCB before IEM changes it.
6424	*/
6425	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6426	}
6427	else
6428	{
6429	switch (idMsr)
6430	{
6431	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6432	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6433	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6434	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6435	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6436	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6437	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6438	}
6439	}
6440	}
6441	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6442	{
6443	rcStrict = VINF_SUCCESS;
6444	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6445	}
6446	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6447	return rcStrict;
6448	}
6449
6450
6451	/**
6452	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6453	* \#VMEXIT.
6454	*/
6455	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6456	{
6457	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6458
6459	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6460	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6461	return hmR0SvmExitReadMsr(pVCpu, pVmcb);
6462
6463	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6464	return hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient);
6465	}
6466
6467
6468	/**
6469	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6470	*/
6471	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6472	{
6473	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6474	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6475
6476	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6477
6478	/** @todo Stepping with nested-guest. */
6479	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6480	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6481	{
6482	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6483	if (pSvmTransient->fWasGuestDebugStateActive)
6484	{
6485	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6486	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6487	return VERR_SVM_UNEXPECTED_EXIT;
6488	}
6489
6490	/*
6491	* Lazy DR0-3 loading.
6492	*/
6493	if (!pSvmTransient->fWasHyperDebugStateActive)
6494	{
6495	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6496	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6497
6498	/* Don't intercept DRx read and writes. */
6499	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
6500	pVmcb->ctrl.u16InterceptRdDRx = 0;
6501	pVmcb->ctrl.u16InterceptWrDRx = 0;
6502	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6503
6504	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6505	VMMRZCallRing3Disable(pVCpu);
6506	HM_DISABLE_PREEMPT(pVCpu);
6507
6508	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6509	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6510	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6511
6512	HM_RESTORE_PREEMPT();
6513	VMMRZCallRing3Enable(pVCpu);
6514
6515	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6516	return VINF_SUCCESS;
6517	}
6518	}
6519
6520	/*
6521	* Interpret the read/writing of DRx.
6522	*/
6523	/** @todo Decode assist. */
6524	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6525	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6526	if (RT_LIKELY(rc == VINF_SUCCESS))
6527	{
6528	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6529	/** @todo CPUM should set this flag! */
6530	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6531	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6532	}
6533	else
6534	Assert(rc == VERR_EM_INTERPRETER);
6535	return rc;
6536	}
6537
6538
6539	/**
6540	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6541	*/
6542	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6543	{
6544	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6545	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6546	VBOXSTRICTRC rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6547	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6548	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6549	return rc;
6550	}
6551
6552
6553	/**
6554	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6555	*/
6556	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6557	{
6558	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6559	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6560
6561	/** @todo decode assists... */
6562	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6563	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6564	{
6565	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6566	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6567	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], fLoadSaveGuestXcr0, pCtx->cr4));
6568	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
6569	{
6570	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
6571	hmR0SvmUpdateVmRunFunction(pVCpu);
6572	}
6573	}
6574	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6575	{
6576	rcStrict = VINF_SUCCESS;
6577	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6578	}
6579	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6580	return rcStrict;
6581	}
6582
6583
6584	/**
6585	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6586	*/
6587	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6588	{
6589	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6590	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6591
6592	/* I/O operation lookup arrays. */
6593	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6594	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6595	the result (in AL/AX/EAX). */
6596	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6597	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6598	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6599
6600	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6601
6602	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6603	SVMIOIOEXITINFO IoExitInfo;
6604	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6605	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6606	uint32_t cbValue = s_aIOSize[uIOWidth];
6607	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6608
6609	if (RT_UNLIKELY(!cbValue))
6610	{
6611	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6612	return VERR_EM_INTERPRETER;
6613	}
6614
6615	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6616	VBOXSTRICTRC rcStrict;
6617	PCEMEXITREC pExitRec = NULL;
6618	if ( !pVCpu->hm.s.fSingleInstruction
6619	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6620	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6621	!IoExitInfo.n.u1Str
6622	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6623	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6624	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6625	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6626	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6627	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6628	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6629	if (!pExitRec)
6630	{
6631	bool fUpdateRipAlready = false;
6632	if (IoExitInfo.n.u1Str)
6633	{
6634	/* INS/OUTS - I/O String instruction. */
6635	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6636	* in EXITINFO1? Investigate once this thing is up and running. */
6637	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6638	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6639	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6640	static IEMMODE const s_aenmAddrMode[8] =
6641	{
6642	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6643	};
6644	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6645	if (enmAddrMode != (IEMMODE)-1)
6646	{
6647	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6648	if (cbInstr <= 15 && cbInstr >= 1)
6649	{
6650	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6651	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6652	{
6653	/* Don't know exactly how to detect whether u3Seg is valid, currently
6654	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6655	2384 Opterons when only checking NRIP. */
6656	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6657	if ( fSupportsNextRipSave
6658	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6659	{
6660	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6661	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6662	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6663	IoExitInfo.n.u3Seg, true /fIoChecked/);
6664	}
6665	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6666	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6667	X86_SREG_DS, true /fIoChecked/);
6668	else
6669	rcStrict = IEMExecOne(pVCpu);
6670	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6671	}
6672	else
6673	{
6674	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6675	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6676	true /fIoChecked/);
6677	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6678	}
6679	}
6680	else
6681	{
6682	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6683	rcStrict = IEMExecOne(pVCpu);
6684	}
6685	}
6686	else
6687	{
6688	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6689	rcStrict = IEMExecOne(pVCpu);
6690	}
6691	fUpdateRipAlready = true;
6692	}
6693	else
6694	{
6695	/* IN/OUT - I/O instruction. */
6696	Assert(!IoExitInfo.n.u1Rep);
6697
6698	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6699	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6700	{
6701	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6702	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6703	&& !pCtx->eflags.Bits.u1TF)
6704	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
6705	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6706	}
6707	else
6708	{
6709	uint32_t u32Val = 0;
6710	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6711	if (IOM_SUCCESS(rcStrict))
6712	{
6713	/* Save result of I/O IN instr. in AL/AX/EAX. */
6714	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6715	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6716	}
6717	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6718	&& !pCtx->eflags.Bits.u1TF)
6719	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
6720
6721	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6722	}
6723	}
6724
6725	if (IOM_SUCCESS(rcStrict))
6726	{
6727	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6728	if (!fUpdateRipAlready)
6729	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6730
6731	/*
6732	* If any I/O breakpoints are armed, we need to check if one triggered
6733	* and take appropriate action.
6734	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6735	*/
6736	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6737	* execution engines about whether hyper BPs and such are pending. */
6738	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
6739	uint32_t const uDr7 = pCtx->dr[7];
6740	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6741	&& X86_DR7_ANY_RW_IO(uDr7)
6742	&& (pCtx->cr4 & X86_CR4_DE))
6743	\|\| DBGFBpIsHwIoArmed(pVM)))
6744	{
6745	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6746	VMMRZCallRing3Disable(pVCpu);
6747	HM_DISABLE_PREEMPT(pVCpu);
6748
6749	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6750	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6751
6752	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
6753	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6754	{
6755	/* Raise #DB. */
6756	pVmcb->guest.u64DR6 = pCtx->dr[6];
6757	pVmcb->guest.u64DR7 = pCtx->dr[7];
6758	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6759	hmR0SvmSetPendingXcptDB(pVCpu);
6760	}
6761	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6762	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6763	else if ( rcStrict2 != VINF_SUCCESS
6764	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6765	rcStrict = rcStrict2;
6766	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6767
6768	HM_RESTORE_PREEMPT();
6769	VMMRZCallRing3Enable(pVCpu);
6770	}
6771
6772	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6773	}
6774
6775	#ifdef VBOX_STRICT
6776	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6777	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
6778	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6779	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6780	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
6781	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
6782	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6783	else
6784	{
6785	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6786	* statuses, that the VMM device and some others may return. See
6787	* IOM_SUCCESS() for guidance. */
6788	AssertMsg( RT_FAILURE(rcStrict)
6789	\|\| rcStrict == VINF_SUCCESS
6790	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6791	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6792	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6793	\|\| rcStrict == VINF_EM_DBG_STEPPED
6794	\|\| rcStrict == VINF_EM_RAW_TO_R3
6795	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6796	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6797	}
6798	#endif
6799	}
6800	else
6801	{
6802	/*
6803	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6804	*/
6805	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6806	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
6807	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
6808	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
6809	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
6810	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
6811	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
6812
6813	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6814	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6815
6816	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6817	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6818	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6819	}
6820	return rcStrict;
6821	}
6822
6823
6824	/**
6825	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6826	*/
6827	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6828	{
6829	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6830	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6831	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6832
6833	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6834	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6835	Assert(pVM->hmr0.s.fNestedPaging);
6836
6837	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6838	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6839	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6840	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
6841	thus intentionally not copied into u32ErrCode. */
6842
6843	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x cbInstrFetched=%u %.15Rhxs\n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
6844	u32ErrCode, pVmcb->ctrl.cbInstrFetched, pVmcb->ctrl.abInstr));
6845
6846	/*
6847	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
6848	*/
6849	if ( pVM->hm.s.fTprPatchingAllowed
6850	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6851	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6852	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6853	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
6854	&& !CPUMIsGuestInLongModeEx(pCtx)
6855	&& !CPUMGetGuestCPL(pVCpu)
6856	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6857	{
6858	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6859	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6860
6861	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6862	{
6863	/* Only attempt to patch the instruction once. */
6864	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6865	if (!pPatch)
6866	return VINF_EM_HM_PATCH_TPR_INSTR;
6867	}
6868	}
6869
6870	/*
6871	* Determine the nested paging mode.
6872	*/
6873	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
6874	PGMMODE const enmNestedPagingMode = PGMGetHostMode(pVM);
6875
6876	/*
6877	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6878	*/
6879	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6880	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6881	{
6882	/*
6883	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
6884	* injecting the original pending event would most likely cause the same MMIO #NPF.
6885	*/
6886	if (pVCpu->hm.s.Event.fPending)
6887	{
6888	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
6889	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6890	}
6891
6892	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
6893	VBOXSTRICTRC rcStrict;
6894	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6895	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
6896	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6897	if (!pExitRec)
6898	{
6899
6900	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6901	u32ErrCode);
6902
6903	/*
6904	* If we succeed, resume guest execution.
6905	*
6906	* If we fail in interpreting the instruction because we couldn't get the guest
6907	* physical address of the page containing the instruction via the guest's page
6908	* tables (we would invalidate the guest page in the host TLB), resume execution
6909	* which would cause a guest page fault to let the guest handle this weird case.
6910	*
6911	* See @bugref{6043}.
6912	*/
6913	if ( rcStrict == VINF_SUCCESS
6914	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
6915	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
6916	{
6917	/* Successfully handled MMIO operation. */
6918	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6919	rcStrict = VINF_SUCCESS;
6920	}
6921	}
6922	else
6923	{
6924	/*
6925	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6926	*/
6927	Assert(pCtx == &pVCpu->cpum.GstCtx);
6928	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6929	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
6930	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
6931
6932	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6933	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6934
6935	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6936	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6937	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6938	}
6939	return rcStrict;
6940	}
6941
6942	/*
6943	* Nested page-fault.
6944	*/
6945	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6946	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6947	TRPMResetTrap(pVCpu);
6948
6949	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6950
6951	/*
6952	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6953	*/
6954	if ( rc == VINF_SUCCESS
6955	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6956	\|\| rc == VERR_PAGE_NOT_PRESENT)
6957	{
6958	/* We've successfully synced our shadow page tables. */
6959	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6960	rc = VINF_SUCCESS;
6961	}
6962
6963	/*
6964	* If delivering an event causes an #NPF (and not MMIO), we shall resolve the fault and
6965	* re-inject the original event.
6966	*/
6967	if (pVCpu->hm.s.Event.fPending)
6968	{
6969	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
6970
6971	/*
6972	* If the #NPF handler requested emulation of the instruction, ignore it.
6973	* We need to re-inject the original event so as to not lose it.
6974	* Reproducible when booting ReactOS 0.4.12 with BTRFS (installed using BootCD,
6975	* LiveCD is broken for other reasons).
6976	*/
6977	if (rc == VINF_EM_RAW_EMULATE_INSTR)
6978	rc = VINF_EM_RAW_INJECT_TRPM_EVENT;
6979	}
6980
6981	return rc;
6982	}
6983
6984
6985	/**
6986	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6987	* \#VMEXIT.
6988	*/
6989	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6990	{
6991	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6992	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
6993
6994	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6995	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6996	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
6997
6998	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6999	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7000	return VINF_SUCCESS;
7001	}
7002
7003
7004	/**
7005	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7006	* \#VMEXIT.
7007	*/
7008	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7009	{
7010	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7011	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7012
7013	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7014	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
7015	#endif
7016
7017	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7018	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7019	{
7020	/*
7021	* AMD-V provides us with the exception which caused the TS; we collect
7022	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7023	*/
7024	Log4Func(("TS occurred during event delivery\n"));
7025	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7026	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7027	}
7028
7029	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7030	* emulation. */
7031	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7032	return VERR_EM_INTERPRETER;
7033	}
7034
7035
7036	/**
7037	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7038	*/
7039	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7040	{
7041	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7042	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7043
7044	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7045	if (pVM->hm.s.fTprPatchingAllowed)
7046	{
7047	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
7048	if (rc != VERR_NOT_FOUND)
7049	{
7050	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
7051	return rc;
7052	}
7053	}
7054
7055	if (EMAreHypercallInstructionsEnabled(pVCpu))
7056	{
7057	unsigned cbInstr;
7058	if (hmR0SvmSupportsNextRipSave(pVCpu))
7059	{
7060	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7061	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7062	}
7063	else
7064	{
7065	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7066	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7067	if ( rc == VINF_SUCCESS
7068	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7069	Assert(cbInstr > 0);
7070	else
7071	cbInstr = 0;
7072	}
7073
7074	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7075	if (RT_SUCCESS(rcStrict))
7076	{
7077	/* Only update the RIP if we're continuing guest execution and not in the case
7078	of say VINF_GIM_R3_HYPERCALL. */
7079	if (rcStrict == VINF_SUCCESS)
7080	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7081
7082	return VBOXSTRICTRC_VAL(rcStrict);
7083	}
7084	else
7085	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7086	}
7087
7088	hmR0SvmSetPendingXcptUD(pVCpu);
7089	return VINF_SUCCESS;
7090	}
7091
7092
7093	/**
7094	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7095	*/
7096	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7097	{
7098	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7099
7100	unsigned cbInstr;
7101	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7102	if (fSupportsNextRipSave)
7103	{
7104	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7105	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7106	}
7107	else
7108	{
7109	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7110	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7111	if ( rc == VINF_SUCCESS
7112	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7113	Assert(cbInstr > 0);
7114	else
7115	cbInstr = 0;
7116	}
7117
7118	/** @todo The guest has likely hit a contended spinlock. We might want to
7119	* poke a schedule different guest VCPU. */
7120	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7121	return VINF_EM_RAW_INTERRUPT;
7122	}
7123
7124
7125	/**
7126	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7127	* \#VMEXIT.
7128	*/
7129	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7130	{
7131	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7132	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7133	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7134
7135	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7136	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7137	}
7138
7139
7140	/**
7141	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7142	*/
7143	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7144	{
7145	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7146
7147	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now (almost) ready. */
7148	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7149	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7150
7151	/* Emulate the IRET. We have to execute the IRET before an NMI, but must potentially
7152	* deliver a pending NMI right after. If the IRET faults, an NMI can come before the
7153	* handler executes. Yes, x86 is ugly.
7154	*/
7155	return VINF_EM_RAW_EMULATE_INSTR;
7156	}
7157
7158
7159	/**
7160	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7161	* Conditional \#VMEXIT.
7162	*/
7163	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7164	{
7165	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7166	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7167	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7168
7169	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7170	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7171	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7172	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7173	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7174	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7175
7176	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7177	if (pVM->hmr0.s.fNestedPaging)
7178	{
7179	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7180	if ( !pSvmTransient->fVectoringDoublePF
7181	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7182	{
7183	/* A genuine guest #PF, reflect it to the guest. */
7184	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7185	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7186	uFaultAddress, uErrCode));
7187	}
7188	else
7189	{
7190	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7191	hmR0SvmSetPendingXcptDF(pVCpu);
7192	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7193	}
7194	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7195	return VINF_SUCCESS;
7196	}
7197	#endif
7198
7199	Assert(!pVM->hmr0.s.fNestedPaging);
7200
7201	/*
7202	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7203	*/
7204	if ( pVM->hm.s.fTprPatchingAllowed
7205	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7206	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7207	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7208	&& !CPUMIsGuestInLongModeEx(pCtx)
7209	&& !CPUMGetGuestCPL(pVCpu)
7210	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7211	{
7212	RTGCPHYS GCPhysApicBase;
7213	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7214	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7215
7216	/* Check if the page at the fault-address is the APIC base. */
7217	RTGCPHYS GCPhysPage;
7218	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7219	if ( rc2 == VINF_SUCCESS
7220	&& GCPhysPage == GCPhysApicBase)
7221	{
7222	/* Only attempt to patch the instruction once. */
7223	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7224	if (!pPatch)
7225	return VINF_EM_HM_PATCH_TPR_INSTR;
7226	}
7227	}
7228
7229	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7230	pCtx->rip, uErrCode, pCtx->cr3));
7231
7232	/*
7233	* If it's a vectoring #PF, emulate injecting the original event injection as
7234	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7235	* event injection that caused a #PF. See @bugref{6607}.
7236	*/
7237	if (pSvmTransient->fVectoringPF)
7238	{
7239	Assert(pVCpu->hm.s.Event.fPending);
7240	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7241	}
7242
7243	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7244	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7245
7246	Log4Func(("#PF: rc=%Rrc\n", rc));
7247
7248	if (rc == VINF_SUCCESS)
7249	{
7250	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7251	TRPMResetTrap(pVCpu);
7252	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7253	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7254	return rc;
7255	}
7256
7257	if (rc == VINF_EM_RAW_GUEST_TRAP)
7258	{
7259	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7260
7261	/*
7262	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7263	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7264	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7265	*/
7266	if ( !pSvmTransient->fVectoringDoublePF
7267	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7268	{
7269	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7270	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7271	TRPMResetTrap(pVCpu);
7272
7273	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7274	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7275	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7276	&& CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
7277	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress);
7278	#endif
7279
7280	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7281	}
7282	else
7283	{
7284	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7285	TRPMResetTrap(pVCpu);
7286	hmR0SvmSetPendingXcptDF(pVCpu);
7287	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7288	}
7289
7290	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7291	return VINF_SUCCESS;
7292	}
7293
7294	TRPMResetTrap(pVCpu);
7295	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7296	return rc;
7297	}
7298
7299
7300	/**
7301	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7302	* Conditional \#VMEXIT.
7303	*/
7304	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7305	{
7306	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7307	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7308	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7309
7310	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7311	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7312	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7313
7314	/** @todo if we accumulate more optional stuff here, we ought to combine the
7315	* reading of opcode bytes to avoid doing more than once. */
7316
7317	VBOXSTRICTRC rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7318	if (pVCpu->hm.s.fGIMTrapXcptUD)
7319	{
7320	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7321	uint8_t cbInstr = 0;
7322	rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7323	if (rcStrict == VINF_SUCCESS)
7324	{
7325	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7326	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7327	rcStrict = VINF_SUCCESS;
7328	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7329	}
7330	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7331	rcStrict = VINF_SUCCESS;
7332	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7333	rcStrict = VINF_GIM_R3_HYPERCALL;
7334	else
7335	{
7336	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7337	rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7338	}
7339	}
7340
7341	if (pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
7342	{
7343	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_SS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS
7344	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7345	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
7346	{
7347	/* Ideally, IEM should just handle all these special #UD situations, but
7348	we don't quite trust things to behave optimially when doing that. So,
7349	for now we'll restrict ourselves to a handful of possible sysenter and
7350	sysexit encodings that we filter right here. */
7351	uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
7352	uint8_t cbInstr = pVmcb->ctrl.cbInstrFetched;
7353	uint32_t const uCpl = CPUMGetGuestCPL(pVCpu);
7354	uint8_t const cbMin = uCpl != 0 ? 2 : 1 + 2;
7355	RTGCPTR const GCPtrInstr = pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base;
7356	if (cbInstr < cbMin \|\| cbInstr > SVM_CTRL_GUEST_INSTR_BYTES_MAX)
7357	{
7358	cbInstr = cbMin;
7359	int rc2 = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, GCPtrInstr, cbInstr);
7360	AssertRCStmt(rc2, cbInstr = 0);
7361	}
7362	else
7363	memcpy(abInstr, pVmcb->ctrl.abInstr, cbInstr); /* unlikely */
7364	if ( cbInstr == 0 /* read error */
7365	\|\| (cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x34) /* sysenter */
7366	\|\| ( uCpl == 0
7367	&& ( ( cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x35) /* sysexit */
7368	\|\| ( cbInstr >= 3 && abInstr[1] == 0x0f && abInstr[2] == 0x35 /* rex.w sysexit */
7369	&& (abInstr[0] & (X86_OP_REX_W \| 0xf0)) == X86_OP_REX_W))))
7370	{
7371	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK
7372	\| CPUMCTX_EXTRN_SREG_MASK /* without ES+DS+GS the app will #GP later - go figure */);
7373	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7374	rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), GCPtrInstr, abInstr, cbInstr);
7375	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: rcStrict=%Rrc %04x:%08RX64 %08RX64 %04x:%08RX64\n",
7376	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u,
7377	pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.rsp));
7378	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7379	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK); /** @todo Lazy bird. */
7380	if (rcStrict == VINF_IEM_RAISED_XCPT)
7381	rcStrict = VINF_SUCCESS;
7382	return rcStrict;
7383	}
7384	Log6(("hmR0SvmExitXcptUD: not sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7385	}
7386	else
7387	Log6(("hmR0SvmExitXcptUD: not in long mode at %04x:%llx\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7388	}
7389
7390	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7391	if (RT_FAILURE(rcStrict))
7392	{
7393	hmR0SvmSetPendingXcptUD(pVCpu);
7394	rcStrict = VINF_SUCCESS;
7395	}
7396
7397	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7398	return rcStrict;
7399	}
7400
7401
7402	/**
7403	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7404	* Conditional \#VMEXIT.
7405	*/
7406	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7407	{
7408	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7409	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7410	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7411
7412	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7413	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7414
7415	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7416	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7417
7418	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7419
7420	if (!(pCtx->cr0 & X86_CR0_NE))
7421	{
7422	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7423	PDISSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7424	unsigned cbInstr;
7425	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7426	if (RT_SUCCESS(rc))
7427	{
7428	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7429	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7430	if (RT_SUCCESS(rc))
7431	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7432	}
7433	else
7434	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7435	return rc;
7436	}
7437
7438	hmR0SvmSetPendingXcptMF(pVCpu);
7439	return VINF_SUCCESS;
7440	}
7441
7442
7443	/**
7444	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7445	* \#VMEXIT.
7446	*/
7447	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7448	{
7449	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7450	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7451	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7452	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7453
7454	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7455	{
7456	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7457	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7458	}
7459
7460	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7461
7462	/*
7463	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7464	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7465	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7466	*/
7467	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7468	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7469	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7470	int rc = DBGFTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7471	if (rc == VINF_EM_RAW_GUEST_TRAP)
7472	{
7473	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7474	if (CPUMIsHyperDebugStateActive(pVCpu))
7475	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7476
7477	/* Reflect the exception back to the guest. */
7478	hmR0SvmSetPendingXcptDB(pVCpu);
7479	rc = VINF_SUCCESS;
7480	}
7481
7482	/*
7483	* Update DR6.
7484	*/
7485	if (CPUMIsHyperDebugStateActive(pVCpu))
7486	{
7487	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7488	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7489	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7490	}
7491	else
7492	{
7493	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7494	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7495	}
7496
7497	return rc;
7498	}
7499
7500
7501	/**
7502	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7503	* Conditional \#VMEXIT.
7504	*/
7505	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7506	{
7507	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7508	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7509	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
7510
7511	SVMEVENT Event;
7512	Event.u = 0;
7513	Event.n.u1Valid = 1;
7514	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7515	Event.n.u8Vector = X86_XCPT_AC;
7516	Event.n.u1ErrorCodeValid = 1;
7517	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7518	return VINF_SUCCESS;
7519	}
7520
7521
7522	/**
7523	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7524	* Conditional \#VMEXIT.
7525	*/
7526	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7527	{
7528	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7529	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7530	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7531	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
7532
7533	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7534	int rc = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7535	if (rc == VINF_EM_RAW_GUEST_TRAP)
7536	{
7537	SVMEVENT Event;
7538	Event.u = 0;
7539	Event.n.u1Valid = 1;
7540	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7541	Event.n.u8Vector = X86_XCPT_BP;
7542	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7543	rc = VINF_SUCCESS;
7544	}
7545
7546	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_DBG_BREAKPOINT);
7547	return rc;
7548	}
7549
7550
7551	/**
7552	* Hacks its way around the lovely mesa driver's backdoor accesses.
7553	*
7554	* @sa hmR0VmxHandleMesaDrvGp
7555	*/
7556	static int hmR0SvmHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7557	{
7558	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7559	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7560	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7561	RT_NOREF(pCtx, pVmcb);
7562
7563	/* For now we'll just skip the instruction. */
7564	hmR0SvmAdvanceRip(pVCpu, 1);
7565	return VINF_SUCCESS;
7566	}
7567
7568
7569	/**
7570	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7571	* backdoor logging w/o checking what it is running inside.
7572	*
7573	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7574	* backdoor port and magic numbers loaded in registers.
7575	*
7576	* @returns true if it is, false if it isn't.
7577	* @sa hmR0VmxIsMesaDrvGp
7578	*/
7579	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7580	{
7581	/* Check magic and port. */
7582	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7583	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7584	if (pCtx->dx != UINT32_C(0x5658))
7585	return false;
7586	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7587	return false;
7588
7589	/* Check that it is #GP(0). */
7590	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7591	return false;
7592
7593	/* Flat ring-3 CS. */
7594	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7595	if (pVmcb->guest.u8CPL != 3)
7596	return false;
7597	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7598	return false;
7599
7600	/* 0xed: IN eAX,dx */
7601	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7602	{
7603	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7604	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7605	uint8_t abInstr[1];
7606	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7607	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7608	if (RT_FAILURE(rc))
7609	return false;
7610	if (abInstr[0] != 0xed)
7611	return false;
7612	}
7613	else
7614	{
7615	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7616	if (pVmcb->ctrl.abInstr[0] != 0xed)
7617	return false;
7618	}
7619	return true;
7620	}
7621
7622
7623	/**
7624	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7625	* Conditional \#VMEXIT.
7626	*/
7627	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7628	{
7629	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7630	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7631	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
7632
7633	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7634	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7635
7636	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7637	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7638	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7639	{
7640	SVMEVENT Event;
7641	Event.u = 0;
7642	Event.n.u1Valid = 1;
7643	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7644	Event.n.u8Vector = X86_XCPT_GP;
7645	Event.n.u1ErrorCodeValid = 1;
7646	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7647	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7648	return VINF_SUCCESS;
7649	}
7650	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7651	}
7652
7653
7654	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7655	/**
7656	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7657	*/
7658	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7659	{
7660	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7661	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7662
7663	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7664	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7665	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7666	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7667	Assert(uVector <= X86_XCPT_LAST);
7668	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7669
7670	SVMEVENT Event;
7671	Event.u = 0;
7672	Event.n.u1Valid = 1;
7673	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7674	Event.n.u8Vector = uVector;
7675	switch (uVector)
7676	{
7677	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7678	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7679	case X86_XCPT_DF:
7680	case X86_XCPT_TS:
7681	case X86_XCPT_NP:
7682	case X86_XCPT_SS:
7683	case X86_XCPT_GP:
7684	case X86_XCPT_AC:
7685	{
7686	Event.n.u1ErrorCodeValid = 1;
7687	Event.n.u32ErrorCode = uErrCode;
7688	break;
7689	}
7690	}
7691
7692	#ifdef VBOX_WITH_STATISTICS
7693	switch (uVector)
7694	{
7695	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
7696	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
7697	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
7698	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7699	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
7700	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
7701	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7702	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
7703	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
7704	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
7705	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
7706	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
7707	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
7708	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
7709	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
7710	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
7711	default:
7712	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
7713	break;
7714	}
7715	#endif
7716
7717	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7718	return VINF_SUCCESS;
7719	}
7720	#endif
7721
7722	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7723	/**
7724	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7725	*/
7726	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7727	{
7728	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7729
7730	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7731	Assert(pVmcb);
7732	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7733
7734	VBOXSTRICTRC rcStrict;
7735	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7736	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7737	if (fSupportsNextRipSave)
7738	{
7739	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7740	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7741	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7742	}
7743	else
7744	{
7745	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7746	rcStrict = IEMExecOne(pVCpu);
7747	}
7748
7749	if (rcStrict == VINF_SUCCESS)
7750	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7751	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7752	{
7753	rcStrict = VINF_SUCCESS;
7754	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7755	}
7756	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7757	return rcStrict;
7758	}
7759
7760
7761	/**
7762	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7763	*/
7764	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7765	{
7766	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7767
7768	/*
7769	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7770	* we only intercept STGI when events are pending for GIF to become 1.
7771	*/
7772	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7773	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7774	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7775
7776	VBOXSTRICTRC rcStrict;
7777	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7778	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7779	if (fSupportsNextRipSave)
7780	{
7781	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7782	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7783	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7784	}
7785	else
7786	{
7787	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7788	rcStrict = IEMExecOne(pVCpu);
7789	}
7790
7791	if (rcStrict == VINF_SUCCESS)
7792	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7793	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7794	{
7795	rcStrict = VINF_SUCCESS;
7796	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7797	}
7798	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7799	return rcStrict;
7800	}
7801
7802
7803	/**
7804	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7805	*/
7806	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7807	{
7808	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7809
7810	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7811	Assert(pVmcb);
7812	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7813
7814	VBOXSTRICTRC rcStrict;
7815	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7816	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7817	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7818	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7819	if (fSupportsNextRipSave)
7820	{
7821	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7822	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7823	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7824	}
7825	else
7826	{
7827	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7828	rcStrict = IEMExecOne(pVCpu);
7829	}
7830
7831	if (rcStrict == VINF_SUCCESS)
7832	{
7833	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7834	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7835	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7836	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7837	}
7838	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7839	{
7840	rcStrict = VINF_SUCCESS;
7841	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7842	}
7843	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7844	return rcStrict;
7845	}
7846
7847
7848	/**
7849	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7850	*/
7851	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7852	{
7853	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7854
7855	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7856	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7857
7858	VBOXSTRICTRC rcStrict;
7859	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7860	if (fSupportsNextRipSave)
7861	{
7862	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7863	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7864	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7865	}
7866	else
7867	{
7868	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7869	rcStrict = IEMExecOne(pVCpu);
7870	}
7871
7872	if (rcStrict == VINF_IEM_RAISED_XCPT)
7873	{
7874	rcStrict = VINF_SUCCESS;
7875	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7876	}
7877	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7878	return rcStrict;
7879	}
7880
7881
7882	/**
7883	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7884	*/
7885	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7886	{
7887	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7888
7889	VBOXSTRICTRC rcStrict;
7890	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7891	if (fSupportsNextRipSave)
7892	{
7893	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7894	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7895	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7896	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7897	}
7898	else
7899	{
7900	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7901	rcStrict = IEMExecOne(pVCpu);
7902	}
7903
7904	if (rcStrict == VINF_IEM_RAISED_XCPT)
7905	{
7906	rcStrict = VINF_SUCCESS;
7907	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7908	}
7909	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7910	return rcStrict;
7911	}
7912
7913
7914	/**
7915	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7916	*/
7917	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7918	{
7919	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7920	/* We shall import the entire state here, just in case we enter and continue execution of
7921	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
7922	could lose lose part of CPU state. */
7923	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7924
7925	VBOXSTRICTRC rcStrict;
7926	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7927	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
7928	if (fSupportsNextRipSave)
7929	{
7930	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7931	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7932	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7933	}
7934	else
7935	{
7936	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
7937	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
7938	instruction itself, see @bugref{7243#c126} */
7939	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
7940	}
7941	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
7942
7943	if (rcStrict == VINF_SUCCESS)
7944	{
7945	rcStrict = VINF_SVM_VMRUN;
7946	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
7947	}
7948	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7949	{
7950	rcStrict = VINF_SUCCESS;
7951	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7952	}
7953	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7954	return rcStrict;
7955	}
7956
7957
7958	/**
7959	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7960	* Unconditional \#VMEXIT.
7961	*/
7962	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7963	{
7964	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7965	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7966
7967	if (pVCpu->hm.s.Event.fPending)
7968	{
7969	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7970	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7971	}
7972
7973	hmR0SvmSetPendingXcptDB(pVCpu);
7974	return VINF_SUCCESS;
7975	}
7976
7977
7978	/**
7979	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7980	* Conditional \#VMEXIT.
7981	*/
7982	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7983	{
7984	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7985	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7986
7987	SVMEVENT Event;
7988	Event.u = 0;
7989	Event.n.u1Valid = 1;
7990	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7991	Event.n.u8Vector = X86_XCPT_BP;
7992	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7993	return VINF_SUCCESS;
7994	}
7995	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
7996
7997	/** @} */
7998

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 87561

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