HMSVMR0.cpp@ 90379

Last change on this file since 90379 was 90379, checked in by vboxsync, 3 years ago
VMM: Implementing blocking on critical sections in ring-0 HM context (actual code is disabled). bugref:6695
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1	/* $Id: HMSVMR0.cpp 90379 2021-07-28 20:00:43Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vmcc.h>
37	#include <VBox/err.h>
38	#include "HMSVMR0.h"
39	#include "dtrace/VBoxVMM.h"
40
41	#ifdef DEBUG_ramshankar
42	# define HMSVM_SYNC_FULL_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll); \
65	if ((u64ExitCode) == SVM_EXIT_NPF) \
66	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
67	else \
68	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
69	} while (0)
70	# endif
71	#else
72	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
73	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
74	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
75	# endif
76	#endif /* !VBOX_WITH_STATISTICS */
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static VBOXSTRICTRC
81
82	/**
83	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
84	* guest using hardware-assisted SVM.
85	*
86	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
87	* are swapped and restored across the world-switch and also registers like
88	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
89	* \#VMEXIT.
90	*/
91	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
92	\| CPUMCTX_EXTRN_RFLAGS \
93	\| CPUMCTX_EXTRN_RAX \
94	\| CPUMCTX_EXTRN_RSP \
95	\| CPUMCTX_EXTRN_SREG_MASK \
96	\| CPUMCTX_EXTRN_CR0 \
97	\| CPUMCTX_EXTRN_CR2 \
98	\| CPUMCTX_EXTRN_CR3 \
99	\| CPUMCTX_EXTRN_TABLE_MASK \
100	\| CPUMCTX_EXTRN_DR6 \
101	\| CPUMCTX_EXTRN_DR7 \
102	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
103	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
104	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
105	\| CPUMCTX_EXTRN_HWVIRT \
106	\| CPUMCTX_EXTRN_HM_SVM_MASK)
107
108	/**
109	* Subset of the guest-CPU state that is shared between the guest and host.
110	*/
111	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
112
113	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
114	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
115	do { \
116	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
117	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
118	} while (0)
119
120	/** Assert that the required state bits are fetched. */
121	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
122	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
123	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
124
125	/** Assert that preemption is disabled or covered by thread-context hooks. */
126	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
127	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
128
129	/** Assert that we haven't migrated CPUs when thread-context hooks are not
130	* used. */
131	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
132	\|\| (a_pVCpu)->hmr0.s.idEnteredCpu == RTMpCpuId(), \
133	("Illegal migration! Entered on CPU %u Current %u\n", \
134	(a_pVCpu)->hmr0.s.idEnteredCpu, RTMpCpuId()));
135
136	/** Assert that we're not executing a nested-guest. */
137	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
139	#else
140	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
141	#endif
142
143	/** Assert that we're executing a nested-guest. */
144	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
145	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
146	#else
147	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
148	#endif
149
150	/** Macro for checking and returning from the using function for
151	* \#VMEXIT intercepts that maybe caused during delivering of another
152	* event in the guest. */
153	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
154	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
155	do \
156	{ \
157	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
158	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
159	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
160	else if ( rc == VINF_EM_RESET \
161	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
162	{ \
163	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
164	return IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0); \
165	} \
166	else \
167	return rc; \
168	} while (0)
169	#else
170	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
171	do \
172	{ \
173	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
174	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
175	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
176	else \
177	return rc; \
178	} while (0)
179	#endif
180
181	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
182	* instruction that exited. */
183	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
184	do { \
185	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
186	(a_rc) = VINF_EM_DBG_STEPPED; \
187	} while (0)
188
189	/** Validate segment descriptor granularity bit. */
190	#ifdef VBOX_STRICT
191	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
192	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
193	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
194	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
195	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
196	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
197	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
198	#else
199	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
200	#endif
201
202	/**
203	* Exception bitmap mask for all contributory exceptions.
204	*
205	* Page fault is deliberately excluded here as it's conditional as to whether
206	* it's contributory or benign. Page faults are handled separately.
207	*/
208	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
209	\| RT_BIT(X86_XCPT_DE))
210
211	/**
212	* Mandatory/unconditional guest control intercepts.
213	*
214	* SMIs can and do happen in normal operation. We need not intercept them
215	* while executing the guest (or nested-guest).
216	*/
217	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
218	\| SVM_CTRL_INTERCEPT_NMI \
219	\| SVM_CTRL_INTERCEPT_INIT \
220	\| SVM_CTRL_INTERCEPT_RDPMC \
221	\| SVM_CTRL_INTERCEPT_CPUID \
222	\| SVM_CTRL_INTERCEPT_RSM \
223	\| SVM_CTRL_INTERCEPT_HLT \
224	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
225	\| SVM_CTRL_INTERCEPT_MSR_PROT \
226	\| SVM_CTRL_INTERCEPT_INVLPGA \
227	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
228	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
229	\| SVM_CTRL_INTERCEPT_VMRUN \
230	\| SVM_CTRL_INTERCEPT_SKINIT \
231	\| SVM_CTRL_INTERCEPT_WBINVD \
232	\| SVM_CTRL_INTERCEPT_MONITOR \
233	\| SVM_CTRL_INTERCEPT_MWAIT \
234	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
235	\| SVM_CTRL_INTERCEPT_XSETBV)
236
237	/** @name VMCB Clean Bits.
238	*
239	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
240	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
241	* memory.
242	*
243	* @{ */
244	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
245	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
246	/** I/O permission bitmap, MSR permission bitmap. */
247	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
248	/** ASID. */
249	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
250	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
251	V_INTR_VECTOR. */
252	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
253	/** Nested Paging: Nested CR3 (nCR3), PAT. */
254	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
255	/** Control registers (CR0, CR3, CR4, EFER). */
256	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
257	/** Debug registers (DR6, DR7). */
258	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
259	/** GDT, IDT limit and base. */
260	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
261	/** Segment register: CS, SS, DS, ES limit and base. */
262	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
263	/** CR2.*/
264	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
265	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
266	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
267	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
268	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
269	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
270	/** Mask of all valid VMCB Clean bits. */
271	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
272	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
273	\| HMSVM_VMCB_CLEAN_ASID \
274	\| HMSVM_VMCB_CLEAN_INT_CTRL \
275	\| HMSVM_VMCB_CLEAN_NP \
276	\| HMSVM_VMCB_CLEAN_CRX_EFER \
277	\| HMSVM_VMCB_CLEAN_DRX \
278	\| HMSVM_VMCB_CLEAN_DT \
279	\| HMSVM_VMCB_CLEAN_SEG \
280	\| HMSVM_VMCB_CLEAN_CR2 \
281	\| HMSVM_VMCB_CLEAN_LBR \
282	\| HMSVM_VMCB_CLEAN_AVIC)
283	/** @} */
284
285	/** @name SVM transient.
286	*
287	* A state structure for holding miscellaneous information across AMD-V
288	* VMRUN/\#VMEXIT operation, restored after the transition.
289	*
290	* @{ */
291	typedef struct SVMTRANSIENT
292	{
293	/** The host's rflags/eflags. */
294	RTCCUINTREG fEFlags;
295	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
296	uint64_t u64ExitCode;
297
298	/** The guest's TPR value used for TPR shadowing. */
299	uint8_t u8GuestTpr;
300	/** Alignment. */
301	uint8_t abAlignment0[7];
302
303	/** Pointer to the currently executing VMCB. */
304	PSVMVMCB pVmcb;
305
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308	/** Whether the guest debug state was active at the time of \#VMEXIT. */
309	bool fWasGuestDebugStateActive;
310	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
311	bool fWasHyperDebugStateActive;
312	/** Whether the TSC offset mode needs to be updated. */
313	bool fUpdateTscOffsetting;
314	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
315	bool fRestoreTscAuxMsr;
316	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
317	* contributary exception or a page-fault. */
318	bool fVectoringDoublePF;
319	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
320	* external interrupt or NMI. */
321	bool fVectoringPF;
322	/** Padding. */
323	bool afPadding0;
324	} SVMTRANSIENT;
325	/** Pointer to SVM transient state. */
326	typedef SVMTRANSIENT *PSVMTRANSIENT;
327	/** Pointer to a const SVM transient state. */
328	typedef const SVMTRANSIENT *PCSVMTRANSIENT;
329
330	AssertCompileSizeAlignment(SVMTRANSIENT, sizeof(uint64_t));
331	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
332	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
333	/** @} */
334
335	/**
336	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
337	*/
338	typedef enum SVMMSREXITREAD
339	{
340	/** Reading this MSR causes a \#VMEXIT. */
341	SVMMSREXIT_INTERCEPT_READ = 0xb,
342	/** Reading this MSR does not cause a \#VMEXIT. */
343	SVMMSREXIT_PASSTHRU_READ
344	} SVMMSREXITREAD;
345
346	/**
347	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
348	*/
349	typedef enum SVMMSREXITWRITE
350	{
351	/** Writing to this MSR causes a \#VMEXIT. */
352	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
353	/** Writing to this MSR does not cause a \#VMEXIT. */
354	SVMMSREXIT_PASSTHRU_WRITE
355	} SVMMSREXITWRITE;
356
357	/**
358	* SVM \#VMEXIT handler.
359	*
360	* @returns Strict VBox status code.
361	* @param pVCpu The cross context virtual CPU structure.
362	* @param pSvmTransient Pointer to the SVM-transient structure.
363	*/
364	typedef VBOXSTRICTRC FNSVMEXITHANDLER(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
365
366
367	/*********************************************************************************************************************************
368	* Internal Functions *
369	*********************************************************************************************************************************/
370	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu);
371	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState);
372
373
374	/** @name \#VMEXIT handlers.
375	* @{
376	*/
377	static FNSVMEXITHANDLER hmR0SvmExitIntr;
378	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
379	static FNSVMEXITHANDLER hmR0SvmExitInvd;
380	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
381	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
382	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
383	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
384	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
385	static FNSVMEXITHANDLER hmR0SvmExitHlt;
386	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
387	static FNSVMEXITHANDLER hmR0SvmExitMwait;
388	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
389	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
390	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
391	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
392	static FNSVMEXITHANDLER hmR0SvmExitMsr;
393	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
394	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
395	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
396	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
397	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
398	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
399	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
400	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
401	static FNSVMEXITHANDLER hmR0SvmExitPause;
402	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
403	static FNSVMEXITHANDLER hmR0SvmExitIret;
404	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
405	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
406	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
407	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
408	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
409	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
410	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
411	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
412	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
413	#endif
414	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
415	static FNSVMEXITHANDLER hmR0SvmExitClgi;
416	static FNSVMEXITHANDLER hmR0SvmExitStgi;
417	static FNSVMEXITHANDLER hmR0SvmExitVmload;
418	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
419	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
420	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
421	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
422	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
423	#endif
424	/** @} */
425
426	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
427	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
428	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
429	#endif
430
431
432	/*********************************************************************************************************************************
433	* Global Variables *
434	*********************************************************************************************************************************/
435	/** Ring-0 memory object for the IO bitmap. */
436	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
437	/** Physical address of the IO bitmap. */
438	static RTHCPHYS g_HCPhysIOBitmap;
439	/** Pointer to the IO bitmap. */
440	static R0PTRTYPE(void *) g_pvIOBitmap;
441
442	#ifdef VBOX_STRICT
443	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
444	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
445	# define HMSVM_LOG_CS RT_BIT_32(2)
446	# define HMSVM_LOG_SS RT_BIT_32(3)
447	# define HMSVM_LOG_FS RT_BIT_32(4)
448	# define HMSVM_LOG_GS RT_BIT_32(5)
449	# define HMSVM_LOG_LBR RT_BIT_32(6)
450	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
451	\| HMSVM_LOG_CR_REGS \
452	\| HMSVM_LOG_CS \
453	\| HMSVM_LOG_SS \
454	\| HMSVM_LOG_FS \
455	\| HMSVM_LOG_GS \
456	\| HMSVM_LOG_LBR)
457
458	/**
459	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
460	*
461	* @param pVCpu The cross context virtual CPU structure.
462	* @param pVmcb Pointer to the VM control block.
463	* @param pszPrefix Log prefix.
464	* @param fFlags Log flags, see HMSVM_LOG_XXX.
465	* @param uVerbose The verbosity level, currently unused.
466	*/
467	static void hmR0SvmLogState(PVMCPUCC pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
468	{
469	RT_NOREF2(pVCpu, uVerbose);
470	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
471
472	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
473	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
474
475	if (fFlags & HMSVM_LOG_RBP_RSP)
476	{
477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
478	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
479	}
480
481	if (fFlags & HMSVM_LOG_CR_REGS)
482	{
483	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
484	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
485	}
486
487	if (fFlags & HMSVM_LOG_CS)
488	{
489	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
490	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
491	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
492	}
493	if (fFlags & HMSVM_LOG_SS)
494	{
495	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
496	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
497	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
498	}
499	if (fFlags & HMSVM_LOG_FS)
500	{
501	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
502	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
503	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
504	}
505	if (fFlags & HMSVM_LOG_GS)
506	{
507	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
508	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
509	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
510	}
511
512	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
513	if (fFlags & HMSVM_LOG_LBR)
514	{
515	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
516	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
517	}
518	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
519	}
520	#endif /* VBOX_STRICT */
521
522
523	/**
524	* Sets up and activates AMD-V on the current CPU.
525	*
526	* @returns VBox status code.
527	* @param pHostCpu The HM physical-CPU structure.
528	* @param pVM The cross context VM structure. Can be
529	* NULL after a resume!
530	* @param pvCpuPage Pointer to the global CPU page.
531	* @param HCPhysCpuPage Physical address of the global CPU page.
532	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
533	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
534	* unused).
535	*/
536	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
537	PCSUPHWVIRTMSRS pHwvirtMsrs)
538	{
539	Assert(!fEnabledByHost);
540	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
541	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
542	Assert(pvCpuPage); NOREF(pvCpuPage);
543	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
544
545	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
546
547	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
549
550	/*
551	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
552	*/
553	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
554	if (u64HostEfer & MSR_K6_EFER_SVME)
555	{
556	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
557	if ( pVM
558	&& pVM->hm.s.svm.fIgnoreInUseError)
559	pHostCpu->fIgnoreAMDVInUseError = true;
560
561	if (!pHostCpu->fIgnoreAMDVInUseError)
562	{
563	ASMSetFlags(fEFlags);
564	return VERR_SVM_IN_USE;
565	}
566	}
567
568	/* Turn on AMD-V in the EFER MSR. */
569	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
570
571	/* Write the physical page address where the CPU will store the host state while executing the VM. */
572	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
573
574	/* Restore interrupts. */
575	ASMSetFlags(fEFlags);
576
577	/*
578	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
579	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
580	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
581	* entirely with before executing any guest code.
582	*/
583	pHostCpu->fFlushAsidBeforeUse = true;
584
585	/*
586	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
587	*/
588	++pHostCpu->cTlbFlushes;
589
590	return VINF_SUCCESS;
591	}
592
593
594	/**
595	* Deactivates AMD-V on the current CPU.
596	*
597	* @returns VBox status code.
598	* @param pHostCpu The HM physical-CPU structure.
599	* @param pvCpuPage Pointer to the global CPU page.
600	* @param HCPhysCpuPage Physical address of the global CPU page.
601	*/
602	VMMR0DECL(int) SVMR0DisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
603	{
604	RT_NOREF1(pHostCpu);
605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
606	AssertReturn( HCPhysCpuPage
607	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
608	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
609
610	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
611	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
612
613	/* Turn off AMD-V in the EFER MSR. */
614	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
615	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
616
617	/* Invalidate host state physical address. */
618	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
619
620	/* Restore interrupts. */
621	ASMSetFlags(fEFlags);
622
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* Does global AMD-V initialization (called during module initialization).
629	*
630	* @returns VBox status code.
631	*/
632	VMMR0DECL(int) SVMR0GlobalInit(void)
633	{
634	/*
635	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
636	* intercept all IO accesses, it's done once globally here instead of per-VM.
637	*/
638	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
639	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
640	if (RT_FAILURE(rc))
641	return rc;
642
643	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
644	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
645
646	/* Set all bits to intercept all IO accesses. */
647	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Does global AMD-V termination (called during module termination).
655	*/
656	VMMR0DECL(void) SVMR0GlobalTerm(void)
657	{
658	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
661	g_pvIOBitmap = NULL;
662	g_HCPhysIOBitmap = 0;
663	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666
667
668	/**
669	* Frees any allocated per-VCPU structures for a VM.
670	*
671	* @param pVM The cross context VM structure.
672	*/
673	DECLINLINE(void) hmR0SvmFreeStructs(PVMCC pVM)
674	{
675	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
676	{
677	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
678	AssertPtr(pVCpu);
679
680	if (pVCpu->hmr0.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
681	{
682	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcbHost, false);
683	pVCpu->hmr0.s.svm.HCPhysVmcbHost = 0;
684	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
685	}
686
687	if (pVCpu->hmr0.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
688	{
689	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcb, false);
690	pVCpu->hmr0.s.svm.pVmcb = NULL;
691	pVCpu->hmr0.s.svm.HCPhysVmcb = 0;
692	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
693	}
694
695	if (pVCpu->hmr0.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
696	{
697	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, false);
698	pVCpu->hmr0.s.svm.pvMsrBitmap = NULL;
699	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = 0;
700	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
701	}
702	}
703	}
704
705
706	/**
707	* Sets pfnVMRun to the best suited variant.
708	*
709	* This must be called whenever anything changes relative to the SVMR0VMRun
710	* variant selection:
711	* - pVCpu->hm.s.fLoadSaveGuestXcr0
712	* - CPUMCTX_WSF_IBPB_ENTRY in pVCpu->cpum.GstCtx.fWorldSwitcher
713	* - CPUMCTX_WSF_IBPB_EXIT in pVCpu->cpum.GstCtx.fWorldSwitcher
714	* - Perhaps: CPUMIsGuestFPUStateActive() (windows only)
715	* - Perhaps: CPUMCTX.fXStateMask (windows only)
716	*
717	* We currently ASSUME that neither CPUMCTX_WSF_IBPB_ENTRY nor
718	* CPUMCTX_WSF_IBPB_EXIT cannot be changed at runtime.
719	*/
720	static void hmR0SvmUpdateVmRunFunction(PVMCPUCC pVCpu)
721	{
722	static const struct CLANGWORKAROUND { PFNHMSVMVMRUN pfn; } s_aHmR0SvmVmRunFunctions[] =
723	{
724	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit },
725	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit },
726	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit },
727	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit },
728	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit },
729	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit },
730	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit },
731	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit },
732	};
733	uintptr_t const idx = (pVCpu->hmr0.s.fLoadSaveGuestXcr0 ? 1 : 0)
734	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_ENTRY ? 2 : 0)
735	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_EXIT ? 4 : 0);
736	PFNHMSVMVMRUN const pfnVMRun = s_aHmR0SvmVmRunFunctions[idx].pfn;
737	if (pVCpu->hmr0.s.svm.pfnVMRun != pfnVMRun)
738	pVCpu->hmr0.s.svm.pfnVMRun = pfnVMRun;
739	}
740
741
742	/**
743	* Selector FNHMSVMVMRUN implementation.
744	*/
745	static DECLCALLBACK(int) hmR0SvmVMRunSelector(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB)
746	{
747	hmR0SvmUpdateVmRunFunction(pVCpu);
748	return pVCpu->hmr0.s.svm.pfnVMRun(pVM, pVCpu, HCPhysVMCB);
749	}
750
751
752	/**
753	* Does per-VM AMD-V initialization.
754	*
755	* @returns VBox status code.
756	* @param pVM The cross context VM structure.
757	*/
758	VMMR0DECL(int) SVMR0InitVM(PVMCC pVM)
759	{
760	int rc = VERR_INTERNAL_ERROR_5;
761
762	/*
763	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
764	*/
765	uint32_t u32Family;
766	uint32_t u32Model;
767	uint32_t u32Stepping;
768	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
769	{
770	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
771	pVM->hmr0.s.svm.fAlwaysFlushTLB = true;
772	}
773
774	/*
775	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
776	*/
777	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
778	{
779	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
780	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
781	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
782	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
783	}
784
785	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
786	{
787	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
788
789	/*
790	* Initialize the hardware-assisted SVM guest-execution handler.
791	* We now use a single handler for both 32-bit and 64-bit guests, see @bugref{6208#c73}.
792	*/
793	pVCpu->hmr0.s.svm.pfnVMRun = hmR0SvmVMRunSelector;
794
795	/*
796	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
797	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
798	*/
799	/** @todo Does this need to be below 4G? */
800	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
801	if (RT_FAILURE(rc))
802	goto failure_cleanup;
803
804	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcbHost);
805	pVCpu->hmr0.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcbHost, 0 /* iPage */);
806	Assert(pVCpu->hmr0.s.svm.HCPhysVmcbHost < _4G);
807	ASMMemZeroPage(pvVmcbHost);
808
809	/*
810	* Allocate one page for the guest-state VMCB.
811	*/
812	/** @todo Does this need to be below 4G? */
813	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
814	if (RT_FAILURE(rc))
815	goto failure_cleanup;
816
817	pVCpu->hmr0.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcb);
818	pVCpu->hmr0.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcb, 0 /* iPage */);
819	Assert(pVCpu->hmr0.s.svm.HCPhysVmcb < _4G);
820	ASMMemZeroPage(pVCpu->hmr0.s.svm.pVmcb);
821
822	/*
823	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
824	* SVM to not require one.
825	*/
826	/** @todo Does this need to be below 4G? */
827	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
828	false /* fExecutable */);
829	if (RT_FAILURE(rc))
830	goto failure_cleanup;
831
832	pVCpu->hmr0.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjMsrBitmap);
833	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
834	/* Set all bits to intercept all MSR accesses (changed later on). */
835	ASMMemFill32(pVCpu->hmr0.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
836	}
837
838	return VINF_SUCCESS;
839
840	failure_cleanup:
841	hmR0SvmFreeStructs(pVM);
842	return rc;
843	}
844
845
846	/**
847	* Does per-VM AMD-V termination.
848	*
849	* @returns VBox status code.
850	* @param pVM The cross context VM structure.
851	*/
852	VMMR0DECL(int) SVMR0TermVM(PVMCC pVM)
853	{
854	hmR0SvmFreeStructs(pVM);
855	return VINF_SUCCESS;
856	}
857
858
859	/**
860	* Returns whether the VMCB Clean Bits feature is supported.
861	*
862	* @returns @c true if supported, @c false otherwise.
863	* @param pVCpu The cross context virtual CPU structure.
864	* @param fIsNestedGuest Whether we are currently executing the nested-guest.
865	*/
866	DECL_FORCE_INLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPUCC pVCpu, bool fIsNestedGuest)
867	{
868	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
869	bool const fHostVmcbCleanBits = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
870	if (!fIsNestedGuest)
871	return fHostVmcbCleanBits;
872	return fHostVmcbCleanBits && pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
873	}
874
875
876	/**
877	* Returns whether the decode assists feature is supported.
878	*
879	* @returns @c true if supported, @c false otherwise.
880	* @param pVCpu The cross context virtual CPU structure.
881	*/
882	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPUCC pVCpu)
883	{
884	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
885	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
886	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
887	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
888	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
889	#endif
890	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
891	}
892
893
894	/**
895	* Returns whether the NRIP_SAVE feature is supported.
896	*
897	* @returns @c true if supported, @c false otherwise.
898	* @param pVCpu The cross context virtual CPU structure.
899	*/
900	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPUCC pVCpu)
901	{
902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
903	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
904	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
905	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
906	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
907	#endif
908	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
909	}
910
911
912	/**
913	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
914	*
915	* @param pVCpu The cross context virtual CPU structure.
916	* @param pbMsrBitmap Pointer to the MSR bitmap.
917	* @param idMsr The MSR for which the permissions are being set.
918	* @param enmRead MSR read permissions.
919	* @param enmWrite MSR write permissions.
920	*
921	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
922	* caller needs to take care of this.
923	*/
924	static void hmR0SvmSetMsrPermission(PVMCPUCC pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
925	SVMMSREXITWRITE enmWrite)
926	{
927	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
928	uint16_t offMsrpm;
929	uint8_t uMsrpmBit;
930	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
931	AssertRC(rc);
932
933	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
934	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
935
936	pbMsrBitmap += offMsrpm;
937	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
938	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
939	else
940	{
941	if (!fInNestedGuestMode)
942	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
943	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
944	else
945	{
946	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
947	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
948	pbNstGstMsrBitmap += offMsrpm;
949	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
950	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
951	else
952	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
953	}
954	#endif
955	}
956
957	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
958	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
959	else
960	{
961	if (!fInNestedGuestMode)
962	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
963	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
964	else
965	{
966	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
967	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
968	pbNstGstMsrBitmap += offMsrpm;
969	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
970	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
971	else
972	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
973	}
974	#endif
975	}
976	}
977
978
979	/**
980	* Sets up AMD-V for the specified VM.
981	* This function is only called once per-VM during initalization.
982	*
983	* @returns VBox status code.
984	* @param pVM The cross context VM structure.
985	*/
986	VMMR0DECL(int) SVMR0SetupVM(PVMCC pVM)
987	{
988	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
989	AssertReturn(pVM, VERR_INVALID_PARAMETER);
990
991	/*
992	* Validate and copy over some parameters.
993	*/
994	AssertReturn(pVM->hm.s.svm.fSupported, VERR_INCOMPATIBLE_CONFIG);
995	bool const fNestedPaging = pVM->hm.s.fNestedPagingCfg;
996	AssertReturn(!fNestedPaging \|\| (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING), VERR_INCOMPATIBLE_CONFIG);
997	pVM->hmr0.s.fNestedPaging = fNestedPaging;
998	pVM->hmr0.s.fAllow64BitGuests = pVM->hm.s.fAllow64BitGuestsCfg;
999
1000	/*
1001	* Determin some configuration parameters.
1002	*/
1003	bool const fPauseFilter = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1004	bool const fPauseFilterThreshold = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1005	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
1006
1007	bool const fLbrVirt = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1008	bool const fUseLbrVirt = fLbrVirt && pVM->hm.s.svm.fLbrVirt; /** @todo IEM implementation etc. */
1009
1010	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1011	bool const fVirtVmsaveVmload = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1012	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && fNestedPaging;
1013
1014	bool const fVGif = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1015	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
1016	#endif
1017
1018	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
1019	PSVMVMCB pVmcb0 = pVCpu0->hmr0.s.svm.pVmcb;
1020	AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
1021	PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
1022
1023	/* Always trap #AC for reasons of security. */
1024	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
1025
1026	/* Always trap #DB for reasons of security. */
1027	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
1028
1029	/* Trap exceptions unconditionally (debug purposes). */
1030	#ifdef HMSVM_ALWAYS_TRAP_PF
1031	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_PF);
1032	#endif
1033	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1034	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
1035	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_BP)
1036	\| RT_BIT_32(X86_XCPT_DE)
1037	\| RT_BIT_32(X86_XCPT_NM)
1038	\| RT_BIT_32(X86_XCPT_UD)
1039	\| RT_BIT_32(X86_XCPT_NP)
1040	\| RT_BIT_32(X86_XCPT_SS)
1041	\| RT_BIT_32(X86_XCPT_GP)
1042	\| RT_BIT_32(X86_XCPT_PF)
1043	\| RT_BIT_32(X86_XCPT_MF)
1044	;
1045	#endif
1046
1047	/* Apply the exceptions intercepts needed by the GIM provider. */
1048	if (pVCpu0->hm.s.fGIMTrapXcptUD \|\| pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1049	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1050
1051	/* The mesa 3d driver hack needs #GP. */
1052	if (pVCpu0->hm.s.fTrapXcptGpForLovelyMesaDrv)
1053	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
1054
1055	/* Set up unconditional intercepts and conditions. */
1056	pVmcbCtrl0->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
1057	\| SVM_CTRL_INTERCEPT_VMMCALL
1058	\| SVM_CTRL_INTERCEPT_VMSAVE
1059	\| SVM_CTRL_INTERCEPT_VMLOAD
1060	\| SVM_CTRL_INTERCEPT_CLGI
1061	\| SVM_CTRL_INTERCEPT_STGI;
1062
1063	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1064	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1065	#endif
1066
1067	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1068	if (pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm)
1069	{
1070	/* Virtualized VMSAVE/VMLOAD. */
1071	if (fUseVirtVmsaveVmload)
1072	{
1073	pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload = 1;
1074	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_VMSAVE
1075	\| SVM_CTRL_INTERCEPT_VMLOAD);
1076	}
1077	else
1078	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1079
1080	/* Virtual GIF. */
1081	if (fUseVGif)
1082	{
1083	pVmcbCtrl0->IntCtrl.n.u1VGifEnable = 1;
1084	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_CLGI
1085	\| SVM_CTRL_INTERCEPT_STGI);
1086	}
1087	else
1088	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1089	}
1090	else
1091	#endif
1092	{
1093	Assert(!pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm);
1094	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1095	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1096	}
1097
1098	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1099	pVmcbCtrl0->u16InterceptWrCRx = RT_BIT(4);
1100
1101	/* Intercept all DRx reads and writes by default. Changed later on. */
1102	pVmcbCtrl0->u16InterceptRdDRx = 0xffff;
1103	pVmcbCtrl0->u16InterceptWrDRx = 0xffff;
1104
1105	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1106	pVmcbCtrl0->IntCtrl.n.u1VIntrMasking = 1;
1107
1108	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1109	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1110	pVmcbCtrl0->IntCtrl.n.u1IgnoreTPR = 1;
1111
1112	/* Set the IO permission bitmap physical addresses. */
1113	pVmcbCtrl0->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1114
1115	/* LBR virtualization. */
1116	pVmcbCtrl0->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1117
1118	/* The host ASID MBZ, for the guest start with 1. */
1119	pVmcbCtrl0->TLBCtrl.n.u32ASID = 1;
1120
1121	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1122	pVmcbCtrl0->NestedPagingCtrl.n.u1NestedPaging = fNestedPaging;
1123
1124	/* Without Nested Paging, we need additionally intercepts. */
1125	if (!fNestedPaging)
1126	{
1127	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1128	pVmcbCtrl0->u16InterceptRdCRx \|= RT_BIT(3);
1129	pVmcbCtrl0->u16InterceptWrCRx \|= RT_BIT(3);
1130
1131	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1132	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1133	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1134
1135	/* Page faults must be intercepted to implement shadow paging. */
1136	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1137	}
1138
1139	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1140	if (fUsePauseFilter)
1141	{
1142	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1143	pVmcbCtrl0->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1144	if (fPauseFilterThreshold)
1145	pVmcbCtrl0->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1146	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1147	}
1148
1149	/*
1150	* Setup the MSR permission bitmap.
1151	* The following MSRs are saved/restored automatically during the world-switch.
1152	* Don't intercept guest read/write accesses to these MSRs.
1153	*/
1154	uint8_t pbMsrBitmap0 = (uint8_t )pVCpu0->hmr0.s.svm.pvMsrBitmap;
1155	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1156	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1157	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1158	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1159	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1160	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1161	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1162	if (!pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1163	{
1164	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1165	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1166	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1167	}
1168	else
1169	{
1170	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1171	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1172	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1173	}
1174	pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hmr0.s.svm.HCPhysMsrBitmap;
1175
1176	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1177	Assert(pVmcbCtrl0->u32VmcbCleanBits == 0);
1178
1179	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1180	{
1181	PVMCPUCC pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
1182	PSVMVMCB pVmcbCur = pVCpuCur->hmr0.s.svm.pVmcb;
1183	AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
1184	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1185
1186	/* Copy the VMCB control area. */
1187	memcpy(pVmcbCtrlCur, pVmcbCtrl0, sizeof(*pVmcbCtrlCur));
1188
1189	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1190	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hmr0.s.svm.pvMsrBitmap;
1191	memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1192	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hmr0.s.svm.HCPhysMsrBitmap;
1193
1194	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1195	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1196
1197	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1198	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu0->hm.s.fGIMTrapXcptUD);
1199	}
1200
1201	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1202	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1203	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1204	#else
1205	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1206	#endif
1207	return VINF_SUCCESS;
1208	}
1209
1210
1211	/**
1212	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1213	*
1214	* @returns Pointer to the current context VMCB.
1215	* @param pVCpu The cross context virtual CPU structure.
1216	*/
1217	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPUCC pVCpu)
1218	{
1219	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1220	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1221	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1222	#endif
1223	return pVCpu->hmr0.s.svm.pVmcb;
1224	}
1225
1226
1227	/**
1228	* Gets a pointer to the nested-guest VMCB cache.
1229	*
1230	* @returns Pointer to the nested-guest VMCB cache.
1231	* @param pVCpu The cross context virtual CPU structure.
1232	*/
1233	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPUCC pVCpu)
1234	{
1235	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1236	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1237	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1238	#else
1239	RT_NOREF(pVCpu);
1240	return NULL;
1241	#endif
1242	}
1243
1244
1245	/**
1246	* Invalidates a guest page by guest virtual address.
1247	*
1248	* @returns VBox status code.
1249	* @param pVCpu The cross context virtual CPU structure.
1250	* @param GCVirt Guest virtual address of the page to invalidate.
1251	*/
1252	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1253	{
1254	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1255
1256	bool const fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH) \|\| pVCpu->CTX_SUFF(pVM)->hmr0.s.svm.fAlwaysFlushTLB;
1257
1258	/* Skip it if a TLB flush is already pending. */
1259	if (!fFlushPending)
1260	{
1261	Log4Func(("%#RGv\n", GCVirt));
1262
1263	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1264	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1265
1266	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1267	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1268	}
1269	return VINF_SUCCESS;
1270	}
1271
1272
1273	/**
1274	* Flushes the appropriate tagged-TLB entries.
1275	*
1276	* @param pHostCpu The HM physical-CPU structure.
1277	* @param pVCpu The cross context virtual CPU structure.
1278	* @param pVmcb Pointer to the VM control block.
1279	*/
1280	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1281	{
1282	/*
1283	* Force a TLB flush for the first world switch if the current CPU differs from the one
1284	* we ran on last. This can happen both for start & resume due to long jumps back to
1285	* ring-3.
1286	*
1287	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1288	* correlation between it and the physical CPU.
1289	*
1290	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1291	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1292	*/
1293	bool fNewAsid = false;
1294	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1295	if ( pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
1296	\|\| pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes
1297	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1298	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1299	#endif
1300	)
1301	{
1302	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1303	pVCpu->hmr0.s.fForceTLBFlush = true;
1304	fNewAsid = true;
1305	}
1306
1307	/* Set TLB flush state as checked until we return from the world switch. */
1308	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1309
1310	/* Check for explicit TLB flushes. */
1311	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1312	{
1313	pVCpu->hmr0.s.fForceTLBFlush = true;
1314	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1315	}
1316
1317	/*
1318	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1319	* This Host CPU requirement takes precedence.
1320	*/
1321	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1322	if (pVM->hmr0.s.svm.fAlwaysFlushTLB)
1323	{
1324	pHostCpu->uCurrentAsid = 1;
1325	pVCpu->hmr0.s.uCurrentAsid = 1;
1326	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1327	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1328	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1329
1330	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1331	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1332	}
1333	else
1334	{
1335	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1336	if (pVCpu->hmr0.s.fForceTLBFlush)
1337	{
1338	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1339	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1340
1341	if (fNewAsid)
1342	{
1343	++pHostCpu->uCurrentAsid;
1344
1345	bool fHitASIDLimit = false;
1346	if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid)
1347	{
1348	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1349	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1350	fHitASIDLimit = true;
1351	}
1352
1353	if ( fHitASIDLimit
1354	\|\| pHostCpu->fFlushAsidBeforeUse)
1355	{
1356	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1357	pHostCpu->fFlushAsidBeforeUse = false;
1358	}
1359
1360	pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1361	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1362	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1363	}
1364	else
1365	{
1366	if (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1367	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1368	else
1369	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1370	}
1371
1372	pVCpu->hmr0.s.fForceTLBFlush = false;
1373	}
1374	}
1375
1376	/* Update VMCB with the ASID. */
1377	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hmr0.s.uCurrentAsid)
1378	{
1379	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hmr0.s.uCurrentAsid;
1380	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1381	}
1382
1383	AssertMsg(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu,
1384	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hmr0.s.idLastCpu, pHostCpu->idCpu));
1385	AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1386	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1387	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid,
1388	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1389	AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid,
1390	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
1391
1392	#ifdef VBOX_WITH_STATISTICS
1393	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1394	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1395	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1396	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1397	{
1398	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1399	}
1400	else
1401	{
1402	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1403	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1404	}
1405	#endif
1406	}
1407
1408
1409	/**
1410	* Sets an exception intercept in the specified VMCB.
1411	*
1412	* @param pVmcb Pointer to the VM control block.
1413	* @param uXcpt The exception (X86_XCPT_*).
1414	*/
1415	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1416	{
1417	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1418	{
1419	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1420	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1421	}
1422	}
1423
1424
1425	/**
1426	* Clears an exception intercept in the specified VMCB.
1427	*
1428	* @param pVCpu The cross context virtual CPU structure.
1429	* @param pVmcb Pointer to the VM control block.
1430	* @param uXcpt The exception (X86_XCPT_*).
1431	*
1432	* @remarks This takes into account if we're executing a nested-guest and only
1433	* removes the exception intercept if both the guest -and- nested-guest
1434	* are not intercepting it.
1435	*/
1436	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1437	{
1438	Assert(uXcpt != X86_XCPT_DB);
1439	Assert(uXcpt != X86_XCPT_AC);
1440	Assert(uXcpt != X86_XCPT_GP);
1441	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1442	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1443	{
1444	bool fRemove = true;
1445	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1446	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1447	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1448	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1449	{
1450	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1451	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1452	}
1453	# else
1454	RT_NOREF(pVCpu);
1455	# endif
1456	if (fRemove)
1457	{
1458	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1459	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1460	}
1461	}
1462	#else
1463	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1464	#endif
1465	}
1466
1467
1468	/**
1469	* Sets a control intercept in the specified VMCB.
1470	*
1471	* @param pVmcb Pointer to the VM control block.
1472	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1473	*/
1474	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1475	{
1476	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1477	{
1478	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1479	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1480	}
1481	}
1482
1483
1484	/**
1485	* Clears a control intercept in the specified VMCB.
1486	*
1487	* @returns @c true if the intercept is still set, @c false otherwise.
1488	* @param pVCpu The cross context virtual CPU structure.
1489	* @param pVmcb Pointer to the VM control block.
1490	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1491	*
1492	* @remarks This takes into account if we're executing a nested-guest and only
1493	* removes the control intercept if both the guest -and- nested-guest
1494	* are not intercepting it.
1495	*/
1496	static bool hmR0SvmClearCtrlIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1497	{
1498	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1499	{
1500	bool fRemove = true;
1501	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1502	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1503	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1504	{
1505	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1506	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1507	}
1508	#else
1509	RT_NOREF(pVCpu);
1510	#endif
1511	if (fRemove)
1512	{
1513	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1514	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1515	}
1516	}
1517
1518	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1519	}
1520
1521
1522	/**
1523	* Exports the guest (or nested-guest) CR0 into the VMCB.
1524	*
1525	* @param pVCpu The cross context virtual CPU structure.
1526	* @param pVmcb Pointer to the VM control block.
1527	*
1528	* @remarks This assumes we always pre-load the guest FPU.
1529	* @remarks No-long-jump zone!!!
1530	*/
1531	static void hmR0SvmExportGuestCR0(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1532	{
1533	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1534
1535	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1536	uint64_t const uGuestCr0 = pCtx->cr0;
1537	uint64_t uShadowCr0 = uGuestCr0;
1538
1539	/* Always enable caching. */
1540	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1541
1542	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1543	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1544	{
1545	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1546	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1547	}
1548
1549	/*
1550	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1551	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1552	* see @bugref{7243#c103}.
1553	*/
1554	if (!(uGuestCr0 & X86_CR0_NE))
1555	{
1556	uShadowCr0 \|= X86_CR0_NE;
1557	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1558	}
1559	else
1560	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1561
1562	/*
1563	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1564	*
1565	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1566	* see @bugref{6944}.
1567	*
1568	* We also don't ever want to honor weird things like cache disable from the guest.
1569	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1570	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1571	*/
1572	if (uShadowCr0 == uGuestCr0)
1573	{
1574	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1575	{
1576	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1577	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1578	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1579	}
1580	else
1581	{
1582	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1583	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1584	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1585	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1586	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1587	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1588	}
1589	}
1590	else
1591	{
1592	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1593	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1594	}
1595	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1596
1597	Assert(!RT_HI_U32(uShadowCr0));
1598	if (pVmcb->guest.u64CR0 != uShadowCr0)
1599	{
1600	pVmcb->guest.u64CR0 = uShadowCr0;
1601	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1602	}
1603	}
1604
1605
1606	/**
1607	* Exports the guest (or nested-guest) CR3 into the VMCB.
1608	*
1609	* @param pVCpu The cross context virtual CPU structure.
1610	* @param pVmcb Pointer to the VM control block.
1611	*
1612	* @remarks No-long-jump zone!!!
1613	*/
1614	static void hmR0SvmExportGuestCR3(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1615	{
1616	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1617
1618	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1619	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1620	if (pVM->hmr0.s.fNestedPaging)
1621	{
1622	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetHyperCR3(pVCpu);
1623	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1624	pVmcb->guest.u64CR3 = pCtx->cr3;
1625	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1626	}
1627	else
1628	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1629
1630	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1631	}
1632
1633
1634	/**
1635	* Exports the guest (or nested-guest) CR4 into the VMCB.
1636	*
1637	* @param pVCpu The cross context virtual CPU structure.
1638	* @param pVmcb Pointer to the VM control block.
1639	*
1640	* @remarks No-long-jump zone!!!
1641	*/
1642	static int hmR0SvmExportGuestCR4(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1643	{
1644	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1645
1646	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1647	uint64_t uShadowCr4 = pCtx->cr4;
1648	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1649	{
1650	switch (pVCpu->hm.s.enmShadowMode)
1651	{
1652	case PGMMODE_REAL:
1653	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1654	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1655
1656	case PGMMODE_32_BIT: /* 32-bit paging. */
1657	uShadowCr4 &= ~X86_CR4_PAE;
1658	break;
1659
1660	case PGMMODE_PAE: /* PAE paging. */
1661	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1662	/** Must use PAE paging as we could use physical memory > 4 GB */
1663	uShadowCr4 \|= X86_CR4_PAE;
1664	break;
1665
1666	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1667	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1668	#ifdef VBOX_WITH_64_BITS_GUESTS
1669	break;
1670	#else
1671	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1672	#endif
1673
1674	default: /* shut up gcc */
1675	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1676	}
1677	}
1678
1679	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1680	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1681	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
1682	{
1683	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
1684	hmR0SvmUpdateVmRunFunction(pVCpu);
1685	}
1686
1687	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1688	if (uShadowCr4 == pCtx->cr4)
1689	{
1690	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1691	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1692	else
1693	{
1694	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1695	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1696	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1697	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1698	}
1699	}
1700	else
1701	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1702
1703	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1704	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1705
1706	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1707	Assert(!RT_HI_U32(uShadowCr4));
1708	pVmcb->guest.u64CR4 = uShadowCr4;
1709	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1710
1711	return VINF_SUCCESS;
1712	}
1713
1714
1715	/**
1716	* Exports the guest (or nested-guest) control registers into the VMCB.
1717	*
1718	* @returns VBox status code.
1719	* @param pVCpu The cross context virtual CPU structure.
1720	* @param pVmcb Pointer to the VM control block.
1721	*
1722	* @remarks No-long-jump zone!!!
1723	*/
1724	static int hmR0SvmExportGuestControlRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1725	{
1726	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1727
1728	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1729	{
1730	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1731	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1732
1733	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1734	{
1735	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1736	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1737	}
1738
1739	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1740	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1741
1742	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1743	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1744	{
1745	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1746	if (RT_FAILURE(rc))
1747	return rc;
1748	}
1749
1750	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1751	}
1752	return VINF_SUCCESS;
1753	}
1754
1755
1756	/**
1757	* Exports the guest (or nested-guest) segment registers into the VMCB.
1758	*
1759	* @returns VBox status code.
1760	* @param pVCpu The cross context virtual CPU structure.
1761	* @param pVmcb Pointer to the VM control block.
1762	*
1763	* @remarks No-long-jump zone!!!
1764	*/
1765	static void hmR0SvmExportGuestSegmentRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1766	{
1767	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1768	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1769
1770	/* Guest segment registers. */
1771	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1772	{
1773	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1774	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1775
1776	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1777	{
1778	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1779	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1780	}
1781
1782	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1783	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1784
1785	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1786	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1787
1788	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1789	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1790
1791	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1792	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1793
1794	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1795	}
1796
1797	/* Guest TR. */
1798	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1799	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1800
1801	/* Guest LDTR. */
1802	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1803	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1804
1805	/* Guest GDTR. */
1806	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1807	{
1808	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1809	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1810	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1811	}
1812
1813	/* Guest IDTR. */
1814	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1815	{
1816	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1817	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1818	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1819	}
1820
1821	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1822	\| HM_CHANGED_GUEST_TABLE_MASK);
1823	}
1824
1825
1826	/**
1827	* Exports the guest (or nested-guest) MSRs into the VMCB.
1828	*
1829	* @param pVCpu The cross context virtual CPU structure.
1830	* @param pVmcb Pointer to the VM control block.
1831	*
1832	* @remarks No-long-jump zone!!!
1833	*/
1834	static void hmR0SvmExportGuestMsrs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1835	{
1836	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1837	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1838
1839	/* Guest Sysenter MSRs. */
1840	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1841	{
1842	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1843	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1844
1845	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1846	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1847
1848	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1849	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1850	}
1851
1852	/*
1853	* Guest EFER MSR.
1854	* AMD-V requires guest EFER.SVME to be set. Weird.
1855	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1856	*/
1857	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1858	{
1859	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1860	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1861	}
1862
1863	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1864	if ( !CPUMIsGuestInLongModeEx(pCtx)
1865	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1866	{
1867	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1868	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1869	}
1870
1871	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1872	{
1873	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1874	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1875	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1876	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1877	}
1878
1879	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1880	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1881
1882	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1883	\| HM_CHANGED_GUEST_EFER_MSR
1884	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1885	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1886
1887	/*
1888	* Setup the PAT MSR (applicable for Nested Paging only).
1889	*
1890	* The default value should be MSR_IA32_CR_PAT_INIT_VAL, but we treat all guest memory
1891	* as WB, so choose type 6 for all PAT slots, see @bugref{9634}.
1892	*
1893	* While guests can modify and see the modified values through the shadow values,
1894	* we shall not honor any guest modifications of this MSR to ensure caching is always
1895	* enabled similar to how we clear CR0.CD and NW bits.
1896	*
1897	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1898	*/
1899	pVmcb->guest.u64PAT = UINT64_C(0x0006060606060606);
1900
1901	/* Enable the last branch record bit if LBR virtualization is enabled. */
1902	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1903	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1904	}
1905
1906
1907	/**
1908	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1909	* the necessary intercepts accordingly.
1910	*
1911	* @param pVCpu The cross context virtual CPU structure.
1912	* @param pVmcb Pointer to the VM control block.
1913	*
1914	* @remarks No-long-jump zone!!!
1915	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1916	*/
1917	static void hmR0SvmExportSharedDebugState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1918	{
1919	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1920
1921	/*
1922	* Anyone single stepping on the host side? If so, we'll have to use the
1923	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1924	* the VMM level like the VT-x implementations does.
1925	*/
1926	bool fInterceptMovDRx = false;
1927	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1928	if (fStepping)
1929	{
1930	pVCpu->hmr0.s.fClearTrapFlag = true;
1931	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1932	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1933	}
1934
1935	if ( fStepping
1936	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1937	{
1938	/*
1939	* Use the combined guest and host DRx values found in the hypervisor
1940	* register set because the debugger has breakpoints active or someone
1941	* is single stepping on the host side.
1942	*
1943	* Note! DBGF expects a clean DR6 state before executing guest code.
1944	*/
1945	if (!CPUMIsHyperDebugStateActive(pVCpu))
1946	{
1947	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1948	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1949	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1950	}
1951
1952	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1953	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1954	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1955	{
1956	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1957	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1958	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1959	}
1960
1961	/** @todo If we cared, we could optimize to allow the guest to read registers
1962	* with the same values. */
1963	fInterceptMovDRx = true;
1964	pVCpu->hmr0.s.fUsingHyperDR7 = true;
1965	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1966	}
1967	else
1968	{
1969	/*
1970	* Update DR6, DR7 with the guest values if necessary.
1971	*/
1972	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1973	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1974	{
1975	pVmcb->guest.u64DR7 = pCtx->dr[7];
1976	pVmcb->guest.u64DR6 = pCtx->dr[6];
1977	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1978	}
1979	pVCpu->hmr0.s.fUsingHyperDR7 = false;
1980
1981	/*
1982	* If the guest has enabled debug registers, we need to load them prior to
1983	* executing guest code so they'll trigger at the right time.
1984	*/
1985	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1986	{
1987	if (!CPUMIsGuestDebugStateActive(pVCpu))
1988	{
1989	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1990	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1991	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1992	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1993	}
1994	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
1995	}
1996	/*
1997	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1998	* intercept #DB as DR6 is updated in the VMCB.
1999	*
2000	* Note! If we cared and dared, we could skip intercepting \#DB here.
2001	* However, \#DB shouldn't be performance critical, so we'll play safe
2002	* and keep the code similar to the VT-x code and always intercept it.
2003	*/
2004	else if (!CPUMIsGuestDebugStateActive(pVCpu))
2005	fInterceptMovDRx = true;
2006	}
2007
2008	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
2009	if (fInterceptMovDRx)
2010	{
2011	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
2012	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
2013	{
2014	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
2015	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
2016	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2017	}
2018	}
2019	else
2020	{
2021	if ( pVmcb->ctrl.u16InterceptRdDRx
2022	\|\| pVmcb->ctrl.u16InterceptWrDRx)
2023	{
2024	pVmcb->ctrl.u16InterceptRdDRx = 0;
2025	pVmcb->ctrl.u16InterceptWrDRx = 0;
2026	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2027	}
2028	}
2029	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2030	}
2031
2032	/**
2033	* Exports the hardware virtualization state into the nested-guest
2034	* VMCB.
2035	*
2036	* @param pVCpu The cross context virtual CPU structure.
2037	* @param pVmcb Pointer to the VM control block.
2038	*
2039	* @remarks No-long-jump zone!!!
2040	*/
2041	static void hmR0SvmExportGuestHwvirtState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2042	{
2043	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2044
2045	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
2046	{
2047	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2048	{
2049	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2050	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
2051
2052	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx); /* Nested VGIF is not supported yet. */
2053	Assert(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Physical hardware supports VGIF. */
2054	Assert(HMIsSvmVGifActive(pVM)); /* Outer VM has enabled VGIF. */
2055	NOREF(pVM);
2056
2057	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
2058	}
2059
2060	/*
2061	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2062	* since SVM doesn't have a preemption timer.
2063	*
2064	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
2065	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2066	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2067	*/
2068	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2069	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2070	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2071	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2072	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_PAUSE))
2073	{
2074	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2075	pVmcbCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2076	pVmcbCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2077	}
2078	else
2079	{
2080	/** @todo r=ramshankar: We can turn these assignments into assertions. */
2081	pVmcbCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2082	pVmcbCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2083	}
2084	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2085
2086	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
2087	}
2088	}
2089
2090
2091	/**
2092	* Exports the guest APIC TPR state into the VMCB.
2093	*
2094	* @returns VBox status code.
2095	* @param pVCpu The cross context virtual CPU structure.
2096	* @param pVmcb Pointer to the VM control block.
2097	*/
2098	static int hmR0SvmExportGuestApicTpr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2099	{
2100	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2101
2102	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2103	{
2104	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2105	if ( PDMHasApic(pVM)
2106	&& APICIsEnabled(pVCpu))
2107	{
2108	bool fPendingIntr;
2109	uint8_t u8Tpr;
2110	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2111	AssertRCReturn(rc, rc);
2112
2113	/* Assume that we need to trap all TPR accesses and thus need not check on
2114	every #VMEXIT if we should update the TPR. */
2115	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2116	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2117
2118	if (!pVM->hm.s.fTprPatchingActive)
2119	{
2120	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2121	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2122
2123	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2124	can deliver the interrupt to the guest. */
2125	if (fPendingIntr)
2126	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2127	else
2128	{
2129	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2130	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2131	}
2132
2133	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2134	}
2135	else
2136	{
2137	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2138	pVmcb->guest.u64LSTAR = u8Tpr;
2139	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hmr0.s.svm.pvMsrBitmap;
2140
2141	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2142	if (fPendingIntr)
2143	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2144	else
2145	{
2146	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2147	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2148	}
2149	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2150	}
2151	}
2152	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2153	}
2154	return VINF_SUCCESS;
2155	}
2156
2157
2158	/**
2159	* Sets up the exception interrupts required for guest execution in the VMCB.
2160	*
2161	* @param pVCpu The cross context virtual CPU structure.
2162	* @param pVmcb Pointer to the VM control block.
2163	*
2164	* @remarks No-long-jump zone!!!
2165	*/
2166	static void hmR0SvmExportGuestXcptIntercepts(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2167	{
2168	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2169
2170	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2171	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_SVM_XCPT_INTERCEPTS)
2172	{
2173	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2174	if (pVCpu->hm.s.fGIMTrapXcptUD \|\| pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
2175	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2176	else
2177	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2178
2179	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2180	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2181	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2182	else
2183	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2184
2185	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2186	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_SVM_XCPT_INTERCEPTS);
2187	}
2188	}
2189
2190
2191	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2192	/**
2193	* Merges guest and nested-guest intercepts for executing the nested-guest using
2194	* hardware-assisted SVM.
2195	*
2196	* This merges the guest and nested-guest intercepts in a way that if the outer
2197	* guest intercept is set we need to intercept it in the nested-guest as
2198	* well.
2199	*
2200	* @param pVCpu The cross context virtual CPU structure.
2201	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2202	*/
2203	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
2204	{
2205	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2206	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
2207	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2208	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2209
2210	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2211	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2212	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2213
2214	/* Always intercept CR4 writes for tracking PGM mode changes. */
2215	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2216
2217	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2218	if (!pVM->hmr0.s.fNestedPaging)
2219	{
2220	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2221	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2222	}
2223
2224	/** @todo Figure out debugging with nested-guests, till then just intercept
2225	* all DR[0-15] accesses. */
2226	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2227	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2228
2229	/*
2230	* Merge the guest's exception intercepts into the nested-guest VMCB.
2231	*
2232	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2233	* while executing the nested-guest.
2234	*
2235	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2236	* be tweaked later depending on how we wish to implement breakpoints.
2237	*
2238	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2239	* loaded into their guests, not ours.
2240	*
2241	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2242	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2243	*/
2244	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2245	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2246	& ~( RT_BIT(X86_XCPT_UD)
2247	\| RT_BIT(X86_XCPT_BP)
2248	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2249	#else
2250	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2251	#endif
2252
2253	/*
2254	* Adjust intercepts while executing the nested-guest that differ from the
2255	* outer guest intercepts.
2256	*
2257	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2258	* that belong to the nested-guest to the outer guest.
2259	*
2260	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2261	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2262	*/
2263	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2264	\| SVM_CTRL_INTERCEPT_VMMCALL))
2265	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2266
2267	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2268	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2269
2270	/* Finally, update the VMCB clean bits. */
2271	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2272	}
2273	#endif
2274
2275
2276	/**
2277	* Enters the AMD-V session.
2278	*
2279	* @returns VBox status code.
2280	* @param pVCpu The cross context virtual CPU structure.
2281	*/
2282	VMMR0DECL(int) SVMR0Enter(PVMCPUCC pVCpu)
2283	{
2284	AssertPtr(pVCpu);
2285	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2286	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2287
2288	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2289	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2290	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2291
2292	pVCpu->hmr0.s.fLeaveDone = false;
2293	return VINF_SUCCESS;
2294	}
2295
2296
2297	/**
2298	* Thread-context callback for AMD-V.
2299	*
2300	* This is used together with RTThreadCtxHookCreate() on platforms which
2301	* supports it, and directly from VMMR0EmtPrepareForBlocking() and
2302	* VMMR0EmtResumeAfterBlocking() on platforms which don't.
2303	*
2304	* @param enmEvent The thread-context event.
2305	* @param pVCpu The cross context virtual CPU structure.
2306	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2307	* @thread EMT(pVCpu)
2308	*/
2309	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
2310	{
2311	NOREF(fGlobalInit);
2312
2313	switch (enmEvent)
2314	{
2315	case RTTHREADCTXEVENT_OUT:
2316	{
2317	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2318	VMCPU_ASSERT_EMT(pVCpu);
2319
2320	/* No longjmps (log-flush, locks) in this fragile context. */
2321	VMMRZCallRing3Disable(pVCpu);
2322
2323	if (!pVCpu->hmr0.s.fLeaveDone)
2324	{
2325	hmR0SvmLeave(pVCpu, false /* fImportState */);
2326	pVCpu->hmr0.s.fLeaveDone = true;
2327	}
2328
2329	/* Leave HM context, takes care of local init (term). */
2330	int rc = HMR0LeaveCpu(pVCpu);
2331	AssertRC(rc); NOREF(rc);
2332
2333	/* Restore longjmp state. */
2334	VMMRZCallRing3Enable(pVCpu);
2335	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2336	break;
2337	}
2338
2339	case RTTHREADCTXEVENT_IN:
2340	{
2341	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2342	VMCPU_ASSERT_EMT(pVCpu);
2343
2344	/* No longjmps (log-flush, locks) in this fragile context. */
2345	VMMRZCallRing3Disable(pVCpu);
2346
2347	/*
2348	* Initialize the bare minimum state required for HM. This takes care of
2349	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2350	*/
2351	int rc = hmR0EnterCpu(pVCpu);
2352	AssertRC(rc); NOREF(rc);
2353	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2354	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2355
2356	pVCpu->hmr0.s.fLeaveDone = false;
2357
2358	/* Restore longjmp state. */
2359	VMMRZCallRing3Enable(pVCpu);
2360	break;
2361	}
2362
2363	default:
2364	break;
2365	}
2366	}
2367
2368
2369	/**
2370	* Saves the host state.
2371	*
2372	* @returns VBox status code.
2373	* @param pVCpu The cross context virtual CPU structure.
2374	*
2375	* @remarks No-long-jump zone!!!
2376	*/
2377	VMMR0DECL(int) SVMR0ExportHostState(PVMCPUCC pVCpu)
2378	{
2379	NOREF(pVCpu);
2380
2381	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2382	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2383	return VINF_SUCCESS;
2384	}
2385
2386
2387	/**
2388	* Exports the guest or nested-guest state from the virtual-CPU context into the
2389	* VMCB.
2390	*
2391	* Also sets up the appropriate VMRUN function to execute guest or nested-guest
2392	* code based on the virtual-CPU mode.
2393	*
2394	* @returns VBox status code.
2395	* @param pVCpu The cross context virtual CPU structure.
2396	* @param pSvmTransient Pointer to the SVM-transient structure.
2397	*
2398	* @remarks No-long-jump zone!!!
2399	*/
2400	static int hmR0SvmExportGuestState(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
2401	{
2402	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2403
2404	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2405	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2406	Assert(pVmcb);
2407
2408	pVmcb->guest.u64RIP = pCtx->rip;
2409	pVmcb->guest.u64RSP = pCtx->rsp;
2410	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2411	pVmcb->guest.u64RAX = pCtx->rax;
2412
2413	bool const fIsNestedGuest = pSvmTransient->fIsNestedGuest;
2414	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2415
2416	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2417	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2418	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2419	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2420	hmR0SvmExportGuestHwvirtState(pVCpu, pVmcb);
2421
2422	ASMSetFlags(fEFlags);
2423
2424	if (!fIsNestedGuest)
2425	{
2426	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2427	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2428	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2429	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2430	}
2431
2432	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2433	uint64_t fUnusedMask = HM_CHANGED_GUEST_RIP
2434	\| HM_CHANGED_GUEST_RFLAGS
2435	\| HM_CHANGED_GUEST_GPRS_MASK
2436	\| HM_CHANGED_GUEST_X87
2437	\| HM_CHANGED_GUEST_SSE_AVX
2438	\| HM_CHANGED_GUEST_OTHER_XSAVE
2439	\| HM_CHANGED_GUEST_XCRx
2440	\| HM_CHANGED_GUEST_TSC_AUX
2441	\| HM_CHANGED_GUEST_OTHER_MSRS;
2442	if (fIsNestedGuest)
2443	fUnusedMask \|= HM_CHANGED_SVM_XCPT_INTERCEPTS
2444	\| HM_CHANGED_GUEST_APIC_TPR;
2445
2446	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( fUnusedMask
2447	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2448
2449	#ifdef VBOX_STRICT
2450	/*
2451	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2452	* except for the host-context and/or shared host-guest context bits.
2453	*/
2454	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2455	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2456	("fCtxChanged=%#RX64\n", fCtxChanged));
2457
2458	/*
2459	* If we need to log state that isn't always imported, we'll need to import them here.
2460	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2461	*/
2462	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2463	#endif
2464
2465	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2466	return VINF_SUCCESS;
2467	}
2468
2469
2470	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2471	/**
2472	* Merges the guest and nested-guest MSR permission bitmap.
2473	*
2474	* If the guest is intercepting an MSR we need to intercept it regardless of
2475	* whether the nested-guest is intercepting it or not.
2476	*
2477	* @param pHostCpu The HM physical-CPU structure.
2478	* @param pVCpu The cross context virtual CPU structure.
2479	*
2480	* @remarks No-long-jmp zone!!!
2481	*/
2482	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2483	{
2484	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hmr0.s.svm.pvMsrBitmap;
2485	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2486	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2487
2488	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2489	uint32_t const offRsvdQwords = 0x1800 >> 3;
2490	for (uint32_t i = 0; i < offRsvdQwords; i++)
2491	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2492	}
2493
2494
2495	/**
2496	* Caches the nested-guest VMCB fields before we modify them for execution using
2497	* hardware-assisted SVM.
2498	*
2499	* @returns true if the VMCB was previously already cached, false otherwise.
2500	* @param pVCpu The cross context virtual CPU structure.
2501	*
2502	* @sa HMNotifySvmNstGstVmexit.
2503	*/
2504	static bool hmR0SvmCacheVmcbNested(PVMCPUCC pVCpu)
2505	{
2506	/*
2507	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2508	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2509	*
2510	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2511	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2512	*/
2513	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2514	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2515	if (!fWasCached)
2516	{
2517	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2518	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2519	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2520	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2521	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2522	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2523	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2524	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2525	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2526	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2527	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2528	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2529	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2530	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2531	pVmcbNstGstCache->fCacheValid = true;
2532	Log4Func(("Cached VMCB fields\n"));
2533	}
2534
2535	return fWasCached;
2536	}
2537
2538
2539	/**
2540	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2541	*
2542	* This is done the first time we enter nested-guest execution using SVM R0
2543	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2544	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2545	*
2546	* @param pVCpu The cross context virtual CPU structure.
2547	*/
2548	static void hmR0SvmSetupVmcbNested(PVMCPUCC pVCpu)
2549	{
2550	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2551	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2552
2553	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2554
2555	/*
2556	* First cache the nested-guest VMCB fields we may potentially modify.
2557	*/
2558	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2559	if (!fVmcbCached)
2560	{
2561	/*
2562	* The IOPM of the nested-guest can be ignored because the the guest always
2563	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2564	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2565	*/
2566	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2567
2568	/*
2569	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2570	* nested-paging suddenly while executing a VM (see assertion at the end of
2571	* Trap0eHandler() in PGMAllBth.h).
2572	*/
2573	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging;
2574
2575	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2576	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2577
2578	/*
2579	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2580	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2581	*/
2582	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2583
2584	#ifdef DEBUG_ramshankar
2585	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2586	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2587	#endif
2588
2589	/*
2590	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2591	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2592	*/
2593	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2594	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2595	\| SVM_CTRL_INTERCEPT_VMLOAD;
2596
2597	/*
2598	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2599	* CLGI/STGI instructions executed by the nested-guest.
2600	*/
2601	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2602	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2603	\| SVM_CTRL_INTERCEPT_STGI;
2604
2605	/* Merge the guest and nested-guest intercepts. */
2606	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2607
2608	/* Update the VMCB clean bits. */
2609	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2610	}
2611	else
2612	{
2613	Assert(!pVCpu->hmr0.s.svm.fSyncVTpr);
2614	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2615	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2616	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPagingCfg == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2617	}
2618	}
2619	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2620
2621
2622	/**
2623	* Exports the state shared between the host and guest (or nested-guest) into
2624	* the VMCB.
2625	*
2626	* @param pVCpu The cross context virtual CPU structure.
2627	* @param pVmcb Pointer to the VM control block.
2628	*
2629	* @remarks No-long-jump zone!!!
2630	*/
2631	static void hmR0SvmExportSharedState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2632	{
2633	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2634	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2635
2636	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2637	{
2638	/** @todo Figure out stepping with nested-guest. */
2639	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2640	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2641	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2642	else
2643	{
2644	pVmcb->guest.u64DR6 = pCtx->dr[6];
2645	pVmcb->guest.u64DR7 = pCtx->dr[7];
2646	}
2647	}
2648
2649	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2650	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2651	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2652	}
2653
2654
2655	/**
2656	* Worker for SVMR0ImportStateOnDemand.
2657	*
2658	* @param pVCpu The cross context virtual CPU structure.
2659	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2660	*/
2661	static void hmR0SvmImportGuestState(PVMCPUCC pVCpu, uint64_t fWhat)
2662	{
2663	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2664
2665	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2666	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2667	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2668	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2669
2670	/*
2671	* We disable interrupts to make the updating of the state and in particular
2672	* the fExtrn modification atomic wrt to preemption hooks.
2673	*/
2674	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2675
2676	fWhat &= pCtx->fExtrn;
2677	if (fWhat)
2678	{
2679	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2680	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2681	{
2682	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2683	{
2684	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2685	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2686	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2687	}
2688	}
2689
2690	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2691	{
2692	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2693	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2694	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2695	}
2696	#endif
2697
2698	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2699	{
2700	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2701	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2702	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2703	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2704	}
2705
2706	if (fWhat & CPUMCTX_EXTRN_RIP)
2707	pCtx->rip = pVmcbGuest->u64RIP;
2708
2709	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2710	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2711
2712	if (fWhat & CPUMCTX_EXTRN_RSP)
2713	pCtx->rsp = pVmcbGuest->u64RSP;
2714
2715	if (fWhat & CPUMCTX_EXTRN_RAX)
2716	pCtx->rax = pVmcbGuest->u64RAX;
2717
2718	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2719	{
2720	if (fWhat & CPUMCTX_EXTRN_CS)
2721	{
2722	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2723	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2724	/** @todo SELM might need to be fixed as it too should not care about the
2725	* granularity bit. See @bugref{6785}. */
2726	if ( !pCtx->cs.Attr.n.u1Granularity
2727	&& pCtx->cs.Attr.n.u1Present
2728	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2729	{
2730	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2731	pCtx->cs.Attr.n.u1Granularity = 1;
2732	}
2733	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2734	}
2735	if (fWhat & CPUMCTX_EXTRN_SS)
2736	{
2737	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2738	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2739	/*
2740	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2741	* VMCB and uses that and thus it's possible that when the CPL changes during
2742	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2743	* AMD Fusion CPUs with 64-bit guests.
2744	*
2745	* See AMD spec. 15.5.1 "Basic operation".
2746	*/
2747	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2748	uint8_t const uCpl = pVmcbGuest->u8CPL;
2749	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2750	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2751	}
2752	if (fWhat & CPUMCTX_EXTRN_DS)
2753	{
2754	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2755	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2756	}
2757	if (fWhat & CPUMCTX_EXTRN_ES)
2758	{
2759	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2760	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2761	}
2762	if (fWhat & CPUMCTX_EXTRN_FS)
2763	{
2764	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2765	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2766	}
2767	if (fWhat & CPUMCTX_EXTRN_GS)
2768	{
2769	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2770	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2771	}
2772	}
2773
2774	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2775	{
2776	if (fWhat & CPUMCTX_EXTRN_TR)
2777	{
2778	/*
2779	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2780	* are used between Intel and AMD, see @bugref{6208#c39}.
2781	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2782	*/
2783	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2784	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2785	{
2786	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2787	\|\| CPUMIsGuestInLongModeEx(pCtx))
2788	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2789	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2790	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2791	}
2792	}
2793
2794	if (fWhat & CPUMCTX_EXTRN_LDTR)
2795	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2796
2797	if (fWhat & CPUMCTX_EXTRN_GDTR)
2798	{
2799	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2800	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2801	}
2802
2803	if (fWhat & CPUMCTX_EXTRN_IDTR)
2804	{
2805	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2806	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2807	}
2808	}
2809
2810	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2811	{
2812	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2813	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2814	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2815	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2816	}
2817
2818	if ( (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2819	&& !pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit /* Intercepted. AMD-V would clear the high 32 bits of EIP & ESP. */)
2820	{
2821	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2822	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2823	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2824	}
2825
2826	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2827	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2828
2829	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2830	{
2831	if (fWhat & CPUMCTX_EXTRN_DR6)
2832	{
2833	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2834	pCtx->dr[6] = pVmcbGuest->u64DR6;
2835	else
2836	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2837	}
2838
2839	if (fWhat & CPUMCTX_EXTRN_DR7)
2840	{
2841	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2842	pCtx->dr[7] = pVmcbGuest->u64DR7;
2843	else
2844	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2845	}
2846	}
2847
2848	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2849	{
2850	if (fWhat & CPUMCTX_EXTRN_CR0)
2851	{
2852	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2853	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2854	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2855	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2856	CPUMSetGuestCR0(pVCpu, uCr0);
2857	VMMRZCallRing3Enable(pVCpu);
2858	}
2859
2860	if (fWhat & CPUMCTX_EXTRN_CR2)
2861	pCtx->cr2 = pVmcbGuest->u64CR2;
2862
2863	if (fWhat & CPUMCTX_EXTRN_CR3)
2864	{
2865	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2866	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2867	{
2868	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2869	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2870	}
2871	}
2872
2873	/* Changes to CR4 are always intercepted. */
2874	}
2875
2876	/* Update fExtrn. */
2877	pCtx->fExtrn &= ~fWhat;
2878
2879	/* If everything has been imported, clear the HM keeper bit. */
2880	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2881	{
2882	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2883	Assert(!pCtx->fExtrn);
2884	}
2885	}
2886	else
2887	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
2888
2889	ASMSetFlags(fEFlags);
2890
2891	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
2892
2893	/*
2894	* Honor any pending CR3 updates.
2895	*
2896	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
2897	* -> SVMR0CallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
2898	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
2899	* handling -> hmR0SvmImportGuestState() and here we are.
2900	*
2901	* The reason for such complicated handling is because VM-exits that call into PGM expect
2902	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
2903	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
2904	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
2905	*
2906	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
2907	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
2908	*/
2909	if ( VMMRZCallRing3IsEnabled(pVCpu)
2910	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2911	{
2912	AssertMsg(pCtx->cr3 == pVmcbGuest->u64CR3, ("cr3=%#RX64 vmcb_cr3=%#RX64\n", pCtx->cr3, pVmcbGuest->u64CR3));
2913	PGMUpdateCR3(pVCpu, pCtx->cr3);
2914	}
2915	}
2916
2917
2918	/**
2919	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2920	* context.
2921	*
2922	* Currently there is no residual state left in the CPU that is not updated in the
2923	* VMCB.
2924	*
2925	* @returns VBox status code.
2926	* @param pVCpu The cross context virtual CPU structure.
2927	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2928	*/
2929	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2930	{
2931	hmR0SvmImportGuestState(pVCpu, fWhat);
2932	return VINF_SUCCESS;
2933	}
2934
2935
2936	/**
2937	* Does the necessary state syncing before returning to ring-3 for any reason
2938	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2939	*
2940	* @param pVCpu The cross context virtual CPU structure.
2941	* @param fImportState Whether to import the guest state from the VMCB back
2942	* to the guest-CPU context.
2943	*
2944	* @remarks No-long-jmp zone!!!
2945	*/
2946	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState)
2947	{
2948	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2949	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2950	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2951
2952	/*
2953	* !!! IMPORTANT !!!
2954	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2955	*/
2956
2957	/* Save the guest state if necessary. */
2958	if (fImportState)
2959	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2960
2961	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2962	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2963	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2964
2965	/*
2966	* Restore host debug registers if necessary and resync on next R0 reentry.
2967	*/
2968	#ifdef VBOX_STRICT
2969	if (CPUMIsHyperDebugStateActive(pVCpu))
2970	{
2971	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb; /** @todo nested-guest. */
2972	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2973	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2974	}
2975	#endif
2976	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2977	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2978	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2979
2980	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2981	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
2982	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
2983	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
2984	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
2985	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
2986	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2987
2988	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2989	}
2990
2991
2992	/**
2993	* Leaves the AMD-V session.
2994	*
2995	* Only used while returning to ring-3 either due to longjump or exits to
2996	* ring-3.
2997	*
2998	* @returns VBox status code.
2999	* @param pVCpu The cross context virtual CPU structure.
3000	*/
3001	static int hmR0SvmLeaveSession(PVMCPUCC pVCpu)
3002	{
3003	HM_DISABLE_PREEMPT(pVCpu);
3004	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3005	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3006
3007	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3008	and done this from the SVMR0ThreadCtxCallback(). */
3009	if (!pVCpu->hmr0.s.fLeaveDone)
3010	{
3011	hmR0SvmLeave(pVCpu, true /* fImportState */);
3012	pVCpu->hmr0.s.fLeaveDone = true;
3013	}
3014
3015	/*
3016	* !!! IMPORTANT !!!
3017	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
3018	*/
3019
3020	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3021	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3022	VMMR0ThreadCtxHookDisable(pVCpu);
3023
3024	/* Leave HM context. This takes care of local init (term). */
3025	int rc = HMR0LeaveCpu(pVCpu);
3026
3027	HM_RESTORE_PREEMPT();
3028	return rc;
3029	}
3030
3031
3032	/**
3033	* Does the necessary state syncing before doing a longjmp to ring-3.
3034	*
3035	* @returns VBox status code.
3036	* @param pVCpu The cross context virtual CPU structure.
3037	*
3038	* @remarks No-long-jmp zone!!!
3039	*/
3040	static int hmR0SvmLongJmpToRing3(PVMCPUCC pVCpu)
3041	{
3042	return hmR0SvmLeaveSession(pVCpu);
3043	}
3044
3045
3046	/**
3047	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3048	* any remaining host state) before we longjump to ring-3 and possibly get
3049	* preempted.
3050	*
3051	* @param pVCpu The cross context virtual CPU structure.
3052	* @param enmOperation The operation causing the ring-3 longjump.
3053	*/
3054	VMMR0DECL(int) SVMR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
3055	{
3056	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3057	{
3058	/*
3059	* !!! IMPORTANT !!!
3060	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3061	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3062	*/
3063	VMMRZCallRing3RemoveNotification(pVCpu);
3064	VMMRZCallRing3Disable(pVCpu);
3065	HM_DISABLE_PREEMPT(pVCpu);
3066
3067	/* Import the entire guest state. */
3068	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3069
3070	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3071	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3072
3073	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3074	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3075
3076	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3077	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3078	VMMR0ThreadCtxHookDisable(pVCpu);
3079
3080	/* Leave HM context. This takes care of local init (term). */
3081	HMR0LeaveCpu(pVCpu);
3082
3083	HM_RESTORE_PREEMPT();
3084	return VINF_SUCCESS;
3085	}
3086
3087	Assert(pVCpu);
3088	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3089	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3090
3091	VMMRZCallRing3Disable(pVCpu);
3092	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3093
3094	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3095	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3096	AssertRCReturn(rc, rc);
3097
3098	VMMRZCallRing3Enable(pVCpu);
3099	return VINF_SUCCESS;
3100	}
3101
3102
3103	/**
3104	* Take necessary actions before going back to ring-3.
3105	*
3106	* An action requires us to go back to ring-3. This function does the necessary
3107	* steps before we can safely return to ring-3. This is not the same as longjmps
3108	* to ring-3, this is voluntary.
3109	*
3110	* @returns Strict VBox status code.
3111	* @param pVCpu The cross context virtual CPU structure.
3112	* @param rcExit The reason for exiting to ring-3. Can be
3113	* VINF_VMM_UNKNOWN_RING3_CALL.
3114	*/
3115	static VBOXSTRICTRC hmR0SvmExitToRing3(PVMCPUCC pVCpu, VBOXSTRICTRC rcExit)
3116	{
3117	Assert(pVCpu);
3118	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3119
3120	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3121	VMMRZCallRing3Disable(pVCpu);
3122	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", VBOXSTRICTRC_VAL(rcExit), (uint64_t)pVCpu->fLocalForcedActions,
3123	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3124
3125	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3126	if (pVCpu->hm.s.Event.fPending)
3127	{
3128	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3129	Assert(!pVCpu->hm.s.Event.fPending);
3130	}
3131
3132	/* Sync. the necessary state for going back to ring-3. */
3133	hmR0SvmLeaveSession(pVCpu);
3134	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3135
3136	/* Thread-context hooks are unregistered at this point!!! */
3137	/* Ring-3 callback notifications are unregistered at this point!!! */
3138
3139	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3140	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3141	\| CPUM_CHANGED_LDTR
3142	\| CPUM_CHANGED_GDTR
3143	\| CPUM_CHANGED_IDTR
3144	\| CPUM_CHANGED_TR
3145	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3146	if ( pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging
3147	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3148	{
3149	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3150	}
3151
3152	/* Update the exit-to-ring 3 reason. */
3153	pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
3154
3155	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3156	if ( rcExit != VINF_EM_RAW_INTERRUPT
3157	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3158	{
3159	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3160	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3161	}
3162
3163	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3164	VMMRZCallRing3Enable(pVCpu);
3165
3166	/*
3167	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3168	* and if we're injecting an event we should have a TRPM trap pending.
3169	*/
3170	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3171	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3172	VERR_SVM_IPE_5);
3173	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3174	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3175	VERR_SVM_IPE_4);
3176
3177	return rcExit;
3178	}
3179
3180
3181	/**
3182	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3183	* intercepts.
3184	*
3185	* @param pVCpu The cross context virtual CPU structure.
3186	* @param pVmcb Pointer to the VM control block.
3187	*
3188	* @remarks No-long-jump zone!!!
3189	*/
3190	static void hmR0SvmUpdateTscOffsetting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3191	{
3192	/*
3193	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3194	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3195	* RDTSC/RDTSCP as well.
3196	*/
3197	bool fParavirtTsc;
3198	uint64_t uTscOffset;
3199	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3200
3201	bool fIntercept;
3202	if (fCanUseRealTsc)
3203	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3204	else
3205	{
3206	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3207	fIntercept = true;
3208	}
3209
3210	if (!fIntercept)
3211	{
3212	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3213	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3214	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3215	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
3216	#endif
3217
3218	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3219	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3220	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3221	}
3222
3223	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3224	information before every VM-entry, hence we have nothing to do here at the moment. */
3225	if (fParavirtTsc)
3226	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3227	}
3228
3229
3230	/**
3231	* Sets an event as a pending event to be injected into the guest.
3232	*
3233	* @param pVCpu The cross context virtual CPU structure.
3234	* @param pEvent Pointer to the SVM event.
3235	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3236	* page-fault.
3237	*
3238	* @remarks Statistics counter assumes this is a guest event being reflected to
3239	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3240	*/
3241	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPUCC pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3242	{
3243	Assert(!pVCpu->hm.s.Event.fPending);
3244	Assert(pEvent->n.u1Valid);
3245
3246	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3247	pVCpu->hm.s.Event.fPending = true;
3248	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3249
3250	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3251	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3252	}
3253
3254
3255	/**
3256	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3257	*
3258	* @param pVCpu The cross context virtual CPU structure.
3259	*/
3260	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPUCC pVCpu)
3261	{
3262	SVMEVENT Event;
3263	Event.u = 0;
3264	Event.n.u1Valid = 1;
3265	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3266	Event.n.u8Vector = X86_XCPT_UD;
3267	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3268	}
3269
3270
3271	/**
3272	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3273	*
3274	* @param pVCpu The cross context virtual CPU structure.
3275	*/
3276	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPUCC pVCpu)
3277	{
3278	SVMEVENT Event;
3279	Event.u = 0;
3280	Event.n.u1Valid = 1;
3281	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3282	Event.n.u8Vector = X86_XCPT_DB;
3283	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3284	}
3285
3286
3287	/**
3288	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3289	*
3290	* @param pVCpu The cross context virtual CPU structure.
3291	* @param u32ErrCode The error-code for the page-fault.
3292	* @param uFaultAddress The page fault address (CR2).
3293	*
3294	* @remarks This updates the guest CR2 with @a uFaultAddress!
3295	*/
3296	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPUCC pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3297	{
3298	SVMEVENT Event;
3299	Event.u = 0;
3300	Event.n.u1Valid = 1;
3301	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3302	Event.n.u8Vector = X86_XCPT_PF;
3303	Event.n.u1ErrorCodeValid = 1;
3304	Event.n.u32ErrorCode = u32ErrCode;
3305
3306	/* Update CR2 of the guest. */
3307	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3308	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3309	{
3310	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3311	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3312	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3313	}
3314
3315	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3316	}
3317
3318
3319	/**
3320	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3321	*
3322	* @param pVCpu The cross context virtual CPU structure.
3323	*/
3324	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPUCC pVCpu)
3325	{
3326	SVMEVENT Event;
3327	Event.u = 0;
3328	Event.n.u1Valid = 1;
3329	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3330	Event.n.u8Vector = X86_XCPT_MF;
3331	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3332	}
3333
3334
3335	/**
3336	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3337	*
3338	* @param pVCpu The cross context virtual CPU structure.
3339	*/
3340	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPUCC pVCpu)
3341	{
3342	SVMEVENT Event;
3343	Event.u = 0;
3344	Event.n.u1Valid = 1;
3345	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3346	Event.n.u8Vector = X86_XCPT_DF;
3347	Event.n.u1ErrorCodeValid = 1;
3348	Event.n.u32ErrorCode = 0;
3349	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3350	}
3351
3352
3353	/**
3354	* Injects an event into the guest upon VMRUN by updating the relevant field
3355	* in the VMCB.
3356	*
3357	* @param pVCpu The cross context virtual CPU structure.
3358	* @param pVmcb Pointer to the guest VM control block.
3359	* @param pEvent Pointer to the event.
3360	*
3361	* @remarks No-long-jump zone!!!
3362	* @remarks Requires CR0!
3363	*/
3364	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3365	{
3366	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3367	pVmcb->ctrl.EventInject.u = pEvent->u;
3368	if ( pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_EXCEPTION
3369	\|\| pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_NMI)
3370	{
3371	Assert(pEvent->n.u8Vector <= X86_XCPT_LAST);
3372	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedXcptsR0[pEvent->n.u8Vector]);
3373	}
3374	else
3375	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3376	RT_NOREF(pVCpu);
3377
3378	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3379	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3380	}
3381
3382
3383
3384	/**
3385	* Converts any TRPM trap into a pending HM event. This is typically used when
3386	* entering from ring-3 (not longjmp returns).
3387	*
3388	* @param pVCpu The cross context virtual CPU structure.
3389	*/
3390	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
3391	{
3392	Assert(TRPMHasTrap(pVCpu));
3393	Assert(!pVCpu->hm.s.Event.fPending);
3394
3395	uint8_t uVector;
3396	TRPMEVENT enmTrpmEvent;
3397	uint32_t uErrCode;
3398	RTGCUINTPTR GCPtrFaultAddress;
3399	uint8_t cbInstr;
3400
3401	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, NULL /* pfIcebp */);
3402	AssertRC(rc);
3403
3404	SVMEVENT Event;
3405	Event.u = 0;
3406	Event.n.u1Valid = 1;
3407	Event.n.u8Vector = uVector;
3408
3409	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3410	if (enmTrpmEvent == TRPM_TRAP)
3411	{
3412	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3413	switch (uVector)
3414	{
3415	case X86_XCPT_NMI:
3416	{
3417	Event.n.u3Type = SVM_EVENT_NMI;
3418	break;
3419	}
3420
3421	case X86_XCPT_BP:
3422	case X86_XCPT_OF:
3423	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3424	RT_FALL_THRU();
3425
3426	case X86_XCPT_PF:
3427	case X86_XCPT_DF:
3428	case X86_XCPT_TS:
3429	case X86_XCPT_NP:
3430	case X86_XCPT_SS:
3431	case X86_XCPT_GP:
3432	case X86_XCPT_AC:
3433	{
3434	Event.n.u1ErrorCodeValid = 1;
3435	Event.n.u32ErrorCode = uErrCode;
3436	break;
3437	}
3438	}
3439	}
3440	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3441	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3442	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3443	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3444	else
3445	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3446
3447	rc = TRPMResetTrap(pVCpu);
3448	AssertRC(rc);
3449
3450	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3451	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3452
3453	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3454	}
3455
3456
3457	/**
3458	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3459	* AMD-V to execute any instruction.
3460	*
3461	* @param pVCpu The cross context virtual CPU structure.
3462	*/
3463	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu)
3464	{
3465	Assert(pVCpu->hm.s.Event.fPending);
3466	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3467
3468	SVMEVENT Event;
3469	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3470
3471	uint8_t uVector = Event.n.u8Vector;
3472	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3473
3474	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3475
3476	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3477	AssertRC(rc);
3478
3479	if (Event.n.u1ErrorCodeValid)
3480	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3481
3482	if ( enmTrapType == TRPM_TRAP
3483	&& uVector == X86_XCPT_PF)
3484	{
3485	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3486	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3487	}
3488	else if (enmTrapType == TRPM_SOFTWARE_INT)
3489	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3490	pVCpu->hm.s.Event.fPending = false;
3491	}
3492
3493
3494	/**
3495	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3496	* now.
3497	*
3498	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3499	* @param pVCpu The cross context virtual CPU structure.
3500	*
3501	* @remarks No-long-jump zone!!!
3502	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3503	*/
3504	static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
3505	{
3506	/*
3507	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3508	* completes. Check if we should inhibit interrupts or clear any existing
3509	* interrupt inhibition.
3510	*/
3511	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3512	{
3513	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3514	{
3515	/*
3516	* We can clear the inhibit force flag as even if we go back to the recompiler
3517	* without executing guest code in AMD-V, the flag's condition to be cleared is
3518	* met and thus the cleared state is correct.
3519	*/
3520	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3521	return false;
3522	}
3523	return true;
3524	}
3525	return false;
3526	}
3527
3528
3529	/**
3530	* Sets the virtual interrupt intercept control in the VMCB.
3531	*
3532	* @param pVCpu The cross context virtual CPU structure.
3533	* @param pVmcb Pointer to the VM control block.
3534	*/
3535	static void hmR0SvmSetIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3536	{
3537	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3538
3539	/*
3540	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3541	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3542	* (updating ISR at the right time) and inject the interrupt.
3543	*
3544	* With AVIC is supported, we could make use of the asynchronously delivery without
3545	* #VMEXIT and we would be passing the AVIC page to SVM.
3546	*
3547	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3548	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3549	*/
3550	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3551	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3552	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3553	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3554	Log4(("Set VINTR intercept\n"));
3555	}
3556
3557
3558	/**
3559	* Clears the virtual interrupt intercept control in the VMCB as
3560	* we are figured the guest is unable process any interrupts
3561	* at this point of time.
3562	*
3563	* @param pVCpu The cross context virtual CPU structure.
3564	* @param pVmcb Pointer to the VM control block.
3565	*/
3566	static void hmR0SvmClearIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3567	{
3568	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3569
3570	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3571	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3572	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3573	{
3574	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3575	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3576	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3577	Log4(("Cleared VINTR intercept\n"));
3578	}
3579	}
3580
3581
3582	/**
3583	* Evaluates the event to be delivered to the guest and sets it as the pending
3584	* event.
3585	*
3586	* @returns Strict VBox status code.
3587	* @param pVCpu The cross context virtual CPU structure.
3588	* @param pSvmTransient Pointer to the SVM transient structure.
3589	*/
3590	static VBOXSTRICTRC hmR0SvmEvaluatePendingEvent(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
3591	{
3592	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3593	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3594	\| CPUMCTX_EXTRN_RFLAGS
3595	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3596	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3597
3598	Assert(!pVCpu->hm.s.Event.fPending);
3599	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3600	Assert(pVmcb);
3601
3602	bool const fGif = CPUMGetGuestGif(pCtx);
3603	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3604	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3605
3606	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3607	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3608	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3609
3610	/** @todo SMI. SMIs take priority over NMIs. */
3611
3612	/*
3613	* Check if the guest or nested-guest can receive NMIs.
3614	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3615	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3616	*/
3617	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3618	&& !fBlockNmi)
3619	{
3620	if ( fGif
3621	&& !fIntShadow)
3622	{
3623	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3624	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3625	{
3626	Log4(("Intercepting NMI -> #VMEXIT\n"));
3627	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3628	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3629	}
3630	#endif
3631	Log4(("Setting NMI pending for injection\n"));
3632	SVMEVENT Event;
3633	Event.u = 0;
3634	Event.n.u1Valid = 1;
3635	Event.n.u8Vector = X86_XCPT_NMI;
3636	Event.n.u3Type = SVM_EVENT_NMI;
3637	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3638	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3639	}
3640	else if (!fGif)
3641	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3642	else if (!pSvmTransient->fIsNestedGuest)
3643	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3644	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3645	}
3646	/*
3647	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3648	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3649	* it from the APIC device.
3650	*
3651	* For nested-guests, physical interrupts always take priority over virtual interrupts.
3652	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3653	* do that work when we execute nested-guest code esp. since all the required information
3654	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3655	* the virtual interrupt controller.
3656	*
3657	* See AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3658	*/
3659	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3660	&& !pVCpu->hm.s.fSingleInstruction)
3661	{
3662	bool const fBlockInt = !pSvmTransient->fIsNestedGuest ? !(pCtx->eflags.u32 & X86_EFL_IF)
3663	: CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx);
3664	if ( fGif
3665	&& !fBlockInt
3666	&& !fIntShadow)
3667	{
3668	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3669	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3670	{
3671	Log4(("Intercepting INTR -> #VMEXIT\n"));
3672	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3673	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3674	}
3675	#endif
3676	uint8_t u8Interrupt;
3677	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3678	if (RT_SUCCESS(rc))
3679	{
3680	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3681	SVMEVENT Event;
3682	Event.u = 0;
3683	Event.n.u1Valid = 1;
3684	Event.n.u8Vector = u8Interrupt;
3685	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3686	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3687	}
3688	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3689	{
3690	/*
3691	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3692	* updated eventually when the TPR is written by the guest.
3693	*/
3694	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3695	}
3696	else
3697	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3698	}
3699	else if (!fGif)
3700	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3701	else if (!pSvmTransient->fIsNestedGuest)
3702	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3703	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3704	}
3705
3706	return VINF_SUCCESS;
3707	}
3708
3709
3710	/**
3711	* Injects any pending events into the guest (or nested-guest).
3712	*
3713	* @param pVCpu The cross context virtual CPU structure.
3714	* @param pVmcb Pointer to the VM control block.
3715	*
3716	* @remarks Must only be called when we are guaranteed to enter
3717	* hardware-assisted SVM execution and not return to ring-3
3718	* prematurely.
3719	*/
3720	static void hmR0SvmInjectPendingEvent(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3721	{
3722	Assert(!TRPMHasTrap(pVCpu));
3723	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3724
3725	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3726	#ifdef VBOX_STRICT
3727	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3728	bool const fGif = CPUMGetGuestGif(pCtx);
3729	bool fAllowInt = fGif;
3730	if (fGif)
3731	{
3732	/*
3733	* For nested-guests we have no way to determine if we're injecting a physical or
3734	* virtual interrupt at this point. Hence the partial verification below.
3735	*/
3736	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3737	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3738	else
3739	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3740	}
3741	#endif
3742
3743	if (pVCpu->hm.s.Event.fPending)
3744	{
3745	SVMEVENT Event;
3746	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3747	Assert(Event.n.u1Valid);
3748
3749	/*
3750	* Validate event injection pre-conditions.
3751	*/
3752	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3753	{
3754	Assert(fAllowInt);
3755	Assert(!fIntShadow);
3756	}
3757	else if (Event.n.u3Type == SVM_EVENT_NMI)
3758	{
3759	Assert(fGif);
3760	Assert(!fIntShadow);
3761	}
3762
3763	/*
3764	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3765	* do this only when we are surely going to inject the NMI as otherwise if we return
3766	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3767	* SVM R0.
3768	*
3769	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3770	* which will set the VMCS field after actually delivering the NMI which we read on
3771	* VM-exit to determine the state.
3772	*/
3773	if ( Event.n.u3Type == SVM_EVENT_NMI
3774	&& Event.n.u8Vector == X86_XCPT_NMI
3775	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3776	{
3777	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3778	}
3779
3780	/*
3781	* Inject it (update VMCB for injection by the hardware).
3782	*/
3783	Log4(("Injecting pending HM event\n"));
3784	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
3785	pVCpu->hm.s.Event.fPending = false;
3786
3787	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3788	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3789	else
3790	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3791	}
3792	else
3793	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3794
3795	/*
3796	* We could have injected an NMI through IEM and continue guest execution using
3797	* hardware-assisted SVM. In which case, we would not have any events pending (above)
3798	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
3799	*/
3800	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3801	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
3802
3803	/*
3804	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3805	*
3806	* For nested-guests: We need to update it too for the scenario where IEM executes
3807	* the nested-guest but execution later continues here with an interrupt shadow active.
3808	*/
3809	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3810	}
3811
3812
3813	/**
3814	* Reports world-switch error and dumps some useful debug info.
3815	*
3816	* @param pVCpu The cross context virtual CPU structure.
3817	* @param rcVMRun The return code from VMRUN (or
3818	* VERR_SVM_INVALID_GUEST_STATE for invalid
3819	* guest-state).
3820	*/
3821	static void hmR0SvmReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun)
3822	{
3823	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3824	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
3825	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3826
3827	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3828	{
3829	#ifdef VBOX_STRICT
3830	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
3831	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3832	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3833	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3834	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3835	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3836	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3837	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3838	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3839	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3840	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3841	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3842
3843	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3844	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3845	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3846
3847	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3848	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3849	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3850	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3851	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3852	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3853	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3854	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3855	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3856	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3857	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3858	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3859
3860	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3861	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3862	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3863	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3864	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3865	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3866	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3867	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3868	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3869	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3870	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3871	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3872	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3873	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3874	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3875	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3876	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3877	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3878	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3879	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3880
3881	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3882
3883	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3884	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3885
3886	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3887	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3888	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3889	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3890	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3891	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3892	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3893	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3894	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3895	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3896	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3897	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3898	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3899	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3900	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3901	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3902	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3903	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3904	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3905	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3906
3907	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3908	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3909
3910	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3911	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3912	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3913	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3914
3915	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3916	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3917
3918	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3919	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3920	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3921	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3922
3923	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3924	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3925	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3926	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3927	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3928	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3929	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3930
3931	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3932	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3933	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3934	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3935
3936	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3937	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3938	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3939
3940	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3941	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3942	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3943	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3944	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3945	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3946	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
3947	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3948	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3949	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3950	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3951	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3952
3953	NOREF(pVmcb);
3954	#endif /* VBOX_STRICT */
3955	}
3956	else
3957	Log4Func(("rcVMRun=%d\n", rcVMRun));
3958	}
3959
3960
3961	/**
3962	* Check per-VM and per-VCPU force flag actions that require us to go back to
3963	* ring-3 for one reason or another.
3964	*
3965	* @returns Strict VBox status code (information status code included).
3966	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3967	* ring-3.
3968	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3969	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3970	* interrupts)
3971	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3972	* all EMTs to be in ring-3.
3973	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3974	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3975	* to the EM loop.
3976	*
3977	* @param pVCpu The cross context virtual CPU structure.
3978	*/
3979	static VBOXSTRICTRC hmR0SvmCheckForceFlags(PVMCPUCC pVCpu)
3980	{
3981	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3982	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3983
3984	/* Could happen as a result of longjump. */
3985	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3986	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
3987
3988	/* Update pending interrupts into the APIC's IRR. */
3989	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3990	APICUpdatePendingInterrupts(pVCpu);
3991
3992	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3993	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
3994	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3995	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
3996	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3997	{
3998	/* Pending PGM C3 sync. */
3999	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4000	{
4001	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
4002	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4003	if (rc != VINF_SUCCESS)
4004	{
4005	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4006	return rc;
4007	}
4008	}
4009
4010	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4011	/* -XXX- what was that about single stepping? */
4012	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
4013	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4014	{
4015	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4016	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
4017	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4018	return rc;
4019	}
4020
4021	/* Pending VM request packets, such as hardware interrupts. */
4022	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
4023	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
4024	{
4025	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
4026	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4027	return VINF_EM_PENDING_REQUEST;
4028	}
4029
4030	/* Pending PGM pool flushes. */
4031	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4032	{
4033	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
4034	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4035	return VINF_PGM_POOL_FLUSH_PENDING;
4036	}
4037
4038	/* Pending DMA requests. */
4039	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
4040	{
4041	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
4042	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4043	return VINF_EM_RAW_TO_R3;
4044	}
4045	}
4046
4047	return VINF_SUCCESS;
4048	}
4049
4050
4051	/**
4052	* Does the preparations before executing guest code in AMD-V.
4053	*
4054	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4055	* recompiler. We must be cautious what we do here regarding committing
4056	* guest-state information into the VMCB assuming we assuredly execute the guest
4057	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4058	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4059	* that the recompiler can (and should) use them when it resumes guest
4060	* execution. Otherwise such operations must be done when we can no longer
4061	* exit to ring-3.
4062	*
4063	* @returns Strict VBox status code (informational status codes included).
4064	* @retval VINF_SUCCESS if we can proceed with running the guest.
4065	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4066	*
4067	* @param pVCpu The cross context virtual CPU structure.
4068	* @param pSvmTransient Pointer to the SVM transient structure.
4069	*/
4070	static VBOXSTRICTRC hmR0SvmPreRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4071	{
4072	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4073
4074	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4075	if (pSvmTransient->fIsNestedGuest)
4076	{
4077	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4078	return VINF_EM_RESCHEDULE_REM;
4079	}
4080	#endif
4081
4082	/* Check force flag actions that might require us to go back to ring-3. */
4083	VBOXSTRICTRC rc = hmR0SvmCheckForceFlags(pVCpu);
4084	if (rc != VINF_SUCCESS)
4085	return rc;
4086
4087	if (TRPMHasTrap(pVCpu))
4088	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4089	else if (!pVCpu->hm.s.Event.fPending)
4090	{
4091	rc = hmR0SvmEvaluatePendingEvent(pVCpu, pSvmTransient);
4092	if ( rc != VINF_SUCCESS
4093	\|\| pSvmTransient->fIsNestedGuest != CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4094	{
4095	/* If a nested-guest VM-exit occurred, bail. */
4096	if (pSvmTransient->fIsNestedGuest)
4097	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4098	return rc;
4099	}
4100	}
4101
4102	/*
4103	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4104	* Just do it in software, see @bugref{8411}.
4105	* NB: If we could continue a task switch exit we wouldn't need to do this.
4106	*/
4107	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4108	if (RT_UNLIKELY( !g_fHmSvmFeatures
4109	&& pVCpu->hm.s.Event.fPending
4110	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4111	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4112
4113	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4114	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4115	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4116	#endif
4117
4118	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4119	/*
4120	* Set up the nested-guest VMCB for execution using hardware-assisted SVM.
4121	*/
4122	if (pSvmTransient->fIsNestedGuest)
4123	hmR0SvmSetupVmcbNested(pVCpu);
4124	#endif
4125
4126	/*
4127	* Export the guest state bits that are not shared with the host in any way as we can
4128	* longjmp or get preempted in the midst of exporting some of the state.
4129	*/
4130	rc = hmR0SvmExportGuestState(pVCpu, pSvmTransient);
4131	AssertRCReturn(rc, rc);
4132	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4133
4134	/* Ensure we've cached (and hopefully modified) the nested-guest VMCB for execution using hardware-assisted SVM. */
4135	Assert(!pSvmTransient->fIsNestedGuest \|\| pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4136
4137	/*
4138	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4139	* world-switch so we can update it on the way back if the guest changed the TPR.
4140	*/
4141	if (pVCpu->hmr0.s.svm.fSyncVTpr)
4142	{
4143	Assert(!pSvmTransient->fIsNestedGuest);
4144	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4145	if (pVM->hm.s.fTprPatchingActive)
4146	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4147	else
4148	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4149	}
4150
4151	/*
4152	* No longjmps to ring-3 from this point on!!!
4153	*
4154	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4155	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4156	*/
4157	VMMRZCallRing3Disable(pVCpu);
4158
4159	/*
4160	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4161	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4162	* preemption disabled for a while. Since this is purly to aid the
4163	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4164	* disable interrupt on NT.
4165	*
4166	* We need to check for force-flags that could've possible been altered since we last
4167	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4168	* see @bugref{6398}).
4169	*
4170	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4171	* to ring-3 before executing guest code.
4172	*/
4173	pSvmTransient->fEFlags = ASMIntDisableFlags();
4174	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4175	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4176	{
4177	ASMSetFlags(pSvmTransient->fEFlags);
4178	VMMRZCallRing3Enable(pVCpu);
4179	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4180	return VINF_EM_RAW_TO_R3;
4181	}
4182	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4183	{
4184	ASMSetFlags(pSvmTransient->fEFlags);
4185	VMMRZCallRing3Enable(pVCpu);
4186	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4187	return VINF_EM_RAW_INTERRUPT;
4188	}
4189
4190	return VINF_SUCCESS;
4191	}
4192
4193
4194	/**
4195	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4196	* doing so.
4197	*
4198	* This means there is no backing out to ring-3 or anywhere else at this point.
4199	*
4200	* @param pVCpu The cross context virtual CPU structure.
4201	* @param pSvmTransient Pointer to the SVM transient structure.
4202	*
4203	* @remarks Called with preemption disabled.
4204	* @remarks No-long-jump zone!!!
4205	*/
4206	static void hmR0SvmPreRunGuestCommitted(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4207	{
4208	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4209	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4210	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4211
4212	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4213	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4214
4215	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4216	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4217
4218	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4219
4220	if (!CPUMIsGuestFPUStateActive(pVCpu))
4221	{
4222	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4223	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4224	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4225	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4226	}
4227
4228	/* Load the state shared between host and guest (FPU, debug). */
4229	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4230	hmR0SvmExportSharedState(pVCpu, pVmcb);
4231
4232	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4233	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4234
4235	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4236	RTCPUID const idHostCpu = pHostCpu->idCpu;
4237	bool const fMigratedHostCpu = idHostCpu != pVCpu->hmr0.s.idLastCpu;
4238
4239	/* Setup TSC offsetting. */
4240	if ( pSvmTransient->fUpdateTscOffsetting
4241	\|\| fMigratedHostCpu)
4242	{
4243	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4244	pSvmTransient->fUpdateTscOffsetting = false;
4245	}
4246
4247	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
4248	if (!(pVmcb->ctrl.u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
4249	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4250	else
4251	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4252
4253	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4254	if (fMigratedHostCpu)
4255	pVmcb->ctrl.u32VmcbCleanBits = 0;
4256
4257	/* Store status of the shared guest-host state at the time of VMRUN. */
4258	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4259	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4260
4261	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4262	uint8_t *pbMsrBitmap;
4263	if (!pSvmTransient->fIsNestedGuest)
4264	pbMsrBitmap = (uint8_t *)pVCpu->hmr0.s.svm.pvMsrBitmap;
4265	else
4266	{
4267	/** @todo We could perhaps optimize this by monitoring if the guest modifies its
4268	* MSRPM and only perform this if it changed also use EVEX.POR when it
4269	* does. */
4270	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4271
4272	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4273	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4274	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4275	}
4276	#else
4277	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4278	#endif
4279
4280	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4281	/* Flush the appropriate tagged-TLB entries. */
4282	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4283	Assert(pVCpu->hmr0.s.idLastCpu == idHostCpu);
4284
4285	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4286
4287	TMNotifyStartOfExecution(pVM, pVCpu); /* Finally, notify TM to resume its clocks as we're about
4288	to start executing. */
4289
4290	/*
4291	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4292	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4293	*
4294	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4295	*/
4296	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4297	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4298	{
4299	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4300	pVCpu->hmr0.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4301	if (uGuestTscAux != pVCpu->hmr0.s.svm.u64HostTscAux)
4302	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4303	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4304	pSvmTransient->fRestoreTscAuxMsr = true;
4305	}
4306	else
4307	{
4308	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4309	pSvmTransient->fRestoreTscAuxMsr = false;
4310	}
4311	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4312
4313	/*
4314	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4315	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4316	* from the VMCB.
4317	*/
4318	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pSvmTransient->fIsNestedGuest);
4319	if (!fSupportsVmcbCleanBits)
4320	pVmcb->ctrl.u32VmcbCleanBits = 0;
4321	}
4322
4323
4324	/**
4325	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4326	*
4327	* @returns VBox strict status code.
4328	* @param pVCpu The cross context virtual CPU structure.
4329	* @param HCPhysVmcb The host physical address of the VMCB.
4330	*
4331	* @remarks No-long-jump zone!!!
4332	*/
4333	DECLINLINE(int) hmR0SvmRunGuest(PVMCPUCC pVCpu, RTHCPHYS HCPhysVmcb)
4334	{
4335	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4336	pVCpu->cpum.GstCtx.fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4337	return pVCpu->hmr0.s.svm.pfnVMRun(pVCpu->CTX_SUFF(pVM), pVCpu, HCPhysVmcb);
4338	}
4339
4340
4341	/**
4342	* Performs some essential restoration of state after running guest (or
4343	* nested-guest) code in AMD-V.
4344	*
4345	* @param pVCpu The cross context virtual CPU structure.
4346	* @param pSvmTransient Pointer to the SVM transient structure.
4347	* @param rcVMRun Return code of VMRUN.
4348	*
4349	* @remarks Called with interrupts disabled.
4350	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4351	* unconditionally when it is safe to do so.
4352	*/
4353	static void hmR0SvmPostRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient, VBOXSTRICTRC rcVMRun)
4354	{
4355	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4356
4357	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4358	ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4359
4360	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4361	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4362
4363	/* TSC read must be done early for maximum accuracy. */
4364	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4365	{
4366	if (!pSvmTransient->fIsNestedGuest)
4367	TMCpuTickSetLastSeen(pVCpu, pVCpu->hmr0.s.uTscExit + pVmcbCtrl->u64TSCOffset);
4368	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4369	else
4370	{
4371	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4372	uint64_t const uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, pVCpu->hmr0.s.uTscExit + pVmcbCtrl->u64TSCOffset);
4373	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4374	}
4375	#endif
4376	}
4377
4378	if (pSvmTransient->fRestoreTscAuxMsr)
4379	{
4380	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4381	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4382	if (u64GuestTscAuxMsr != pVCpu->hmr0.s.svm.u64HostTscAux)
4383	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hmr0.s.svm.u64HostTscAux);
4384	}
4385
4386	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4387	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4388	TMNotifyEndOfExecution(pVM, pVCpu, pVCpu->hmr0.s.uTscExit); /* Notify TM that the guest is no longer running. */
4389	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4390
4391	Assert(!(ASMGetFlags() & X86_EFL_IF));
4392	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4393	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4394
4395	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4396	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4397	{
4398	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", VBOXSTRICTRC_VAL(rcVMRun)));
4399	return;
4400	}
4401
4402	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4403	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4404	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4405	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4406
4407	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4408	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4409	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4410	#else
4411	/*
4412	* Always import the following:
4413	*
4414	* - RIP for exit optimizations and evaluating event injection on re-entry.
4415	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4416	* state on preemption.
4417	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4418	* - CS for exit optimizations.
4419	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4420	* assembly switcher code.
4421	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4422	*/
4423	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4424	\| CPUMCTX_EXTRN_RFLAGS
4425	\| CPUMCTX_EXTRN_RAX
4426	\| CPUMCTX_EXTRN_RSP
4427	\| CPUMCTX_EXTRN_CS
4428	\| CPUMCTX_EXTRN_HWVIRT
4429	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4430	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4431	\| HMSVM_CPUMCTX_SHARED_STATE);
4432	#endif
4433
4434	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4435	&& pVCpu->hmr0.s.svm.fSyncVTpr)
4436	{
4437	Assert(!pSvmTransient->fIsNestedGuest);
4438	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4439	if ( pVM->hm.s.fTprPatchingActive
4440	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4441	{
4442	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4443	AssertRC(rc);
4444	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4445	}
4446	/* Sync TPR when we aren't intercepting CR8 writes. */
4447	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4448	{
4449	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4450	AssertRC(rc);
4451	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4452	}
4453	}
4454
4455	#ifdef DEBUG_ramshankar
4456	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4457	{
4458	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4459	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4460	0 /* uVerbose */);
4461	}
4462	#endif
4463
4464	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4465	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4466	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, pVCpu->hmr0.s.uTscExit);
4467	}
4468
4469
4470	/**
4471	* Runs the guest code using AMD-V.
4472	*
4473	* @returns Strict VBox status code.
4474	* @param pVCpu The cross context virtual CPU structure.
4475	* @param pcLoops Pointer to the number of executed loops.
4476	*/
4477	static VBOXSTRICTRC hmR0SvmRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
4478	{
4479	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4480	Assert(pcLoops);
4481	Assert(*pcLoops <= cMaxResumeLoops);
4482
4483	SVMTRANSIENT SvmTransient;
4484	RT_ZERO(SvmTransient);
4485	SvmTransient.fUpdateTscOffsetting = true;
4486	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4487
4488	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4489	for (;;)
4490	{
4491	Assert(!HMR0SuspendPending());
4492	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4493
4494	/* Preparatory work for running nested-guest code, this may force us to return to
4495	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4496	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4497	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4498	if (rc != VINF_SUCCESS)
4499	break;
4500
4501	/*
4502	* No longjmps to ring-3 from this point on!!!
4503	*
4504	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4505	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4506	*/
4507	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4508	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4509
4510	/* Restore any residual host-state and save any bits shared between host and guest
4511	into the guest-CPU state. Re-enables interrupts! */
4512	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4513
4514	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4515	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4516	{
4517	if (rc == VINF_SUCCESS)
4518	rc = VERR_SVM_INVALID_GUEST_STATE;
4519	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4520	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4521	break;
4522	}
4523
4524	/* Handle the #VMEXIT. */
4525	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4526	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4527	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4528	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4529	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4530	if (rc != VINF_SUCCESS)
4531	break;
4532	if (++(*pcLoops) >= cMaxResumeLoops)
4533	{
4534	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4535	rc = VINF_EM_RAW_INTERRUPT;
4536	break;
4537	}
4538	}
4539
4540	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4541	return rc;
4542	}
4543
4544
4545	/**
4546	* Runs the guest code using AMD-V in single step mode.
4547	*
4548	* @returns Strict VBox status code.
4549	* @param pVCpu The cross context virtual CPU structure.
4550	* @param pcLoops Pointer to the number of executed loops.
4551	*/
4552	static VBOXSTRICTRC hmR0SvmRunGuestCodeStep(PVMCPUCC pVCpu, uint32_t *pcLoops)
4553	{
4554	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4555	Assert(pcLoops);
4556	Assert(*pcLoops <= cMaxResumeLoops);
4557
4558	SVMTRANSIENT SvmTransient;
4559	RT_ZERO(SvmTransient);
4560	SvmTransient.fUpdateTscOffsetting = true;
4561	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4562
4563	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4564	uint16_t const uCsStart = pCtx->cs.Sel;
4565	uint64_t const uRipStart = pCtx->rip;
4566
4567	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4568	for (;;)
4569	{
4570	Assert(!HMR0SuspendPending());
4571	AssertMsg(pVCpu->hmr0.s.idEnteredCpu == RTMpCpuId(),
4572	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hmr0.s.idEnteredCpu,
4573	(unsigned)RTMpCpuId(), *pcLoops));
4574
4575	/* Preparatory work for running nested-guest code, this may force us to return to
4576	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4577	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4578	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4579	if (rc != VINF_SUCCESS)
4580	break;
4581
4582	/*
4583	* No longjmps to ring-3 from this point on!!!
4584	*
4585	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4586	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4587	*/
4588	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4589
4590	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4591
4592	/* Restore any residual host-state and save any bits shared between host and guest
4593	into the guest-CPU state. Re-enables interrupts! */
4594	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4595
4596	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4597	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4598	{
4599	if (rc == VINF_SUCCESS)
4600	rc = VERR_SVM_INVALID_GUEST_STATE;
4601	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4602	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4603	return rc;
4604	}
4605
4606	/* Handle the #VMEXIT. */
4607	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4608	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4609	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4610	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4611	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4612	if (rc != VINF_SUCCESS)
4613	break;
4614	if (++(*pcLoops) >= cMaxResumeLoops)
4615	{
4616	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4617	rc = VINF_EM_RAW_INTERRUPT;
4618	break;
4619	}
4620
4621	/*
4622	* Did the RIP change, if so, consider it a single step.
4623	* Otherwise, make sure one of the TFs gets set.
4624	*/
4625	if ( pCtx->rip != uRipStart
4626	\|\| pCtx->cs.Sel != uCsStart)
4627	{
4628	rc = VINF_EM_DBG_STEPPED;
4629	break;
4630	}
4631	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4632	}
4633
4634	/*
4635	* Clear the X86_EFL_TF if necessary.
4636	*/
4637	if (pVCpu->hmr0.s.fClearTrapFlag)
4638	{
4639	pVCpu->hmr0.s.fClearTrapFlag = false;
4640	pCtx->eflags.Bits.u1TF = 0;
4641	}
4642
4643	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4644	return rc;
4645	}
4646
4647	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4648	/**
4649	* Runs the nested-guest code using AMD-V.
4650	*
4651	* @returns Strict VBox status code.
4652	* @param pVCpu The cross context virtual CPU structure.
4653	* @param pcLoops Pointer to the number of executed loops. If we're switching
4654	* from the guest-code execution loop to this nested-guest
4655	* execution loop pass the remainder value, else pass 0.
4656	*/
4657	static VBOXSTRICTRC hmR0SvmRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
4658	{
4659	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4660	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4661	Assert(pcLoops);
4662	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops);
4663
4664	SVMTRANSIENT SvmTransient;
4665	RT_ZERO(SvmTransient);
4666	SvmTransient.fUpdateTscOffsetting = true;
4667	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4668	SvmTransient.fIsNestedGuest = true;
4669
4670	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_4;
4671	for (;;)
4672	{
4673	Assert(!HMR0SuspendPending());
4674	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4675
4676	/* Preparatory work for running nested-guest code, this may force us to return to
4677	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4678	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4679	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4680	if ( rc != VINF_SUCCESS
4681	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4682	break;
4683
4684	/*
4685	* No longjmps to ring-3 from this point on!!!
4686	*
4687	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4688	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4689	*/
4690	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4691
4692	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
4693
4694	/* Restore any residual host-state and save any bits shared between host and guest
4695	into the guest-CPU state. Re-enables interrupts! */
4696	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4697
4698	if (RT_LIKELY( rc == VINF_SUCCESS
4699	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4700	{ /* extremely likely */ }
4701	else
4702	{
4703	/* VMRUN failed, shouldn't really happen, Guru. */
4704	if (rc != VINF_SUCCESS)
4705	break;
4706
4707	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4708	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4709	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4710	rc = IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0);
4711	break;
4712	}
4713
4714	/* Handle the #VMEXIT. */
4715	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4716	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4717	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4718	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
4719	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4720	if (rc == VINF_SUCCESS)
4721	{
4722	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4723	{
4724	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4725	rc = VINF_SVM_VMEXIT;
4726	}
4727	else
4728	{
4729	if (++(*pcLoops) <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops)
4730	continue;
4731	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4732	rc = VINF_EM_RAW_INTERRUPT;
4733	}
4734	}
4735	else
4736	Assert(rc != VINF_SVM_VMEXIT);
4737	break;
4738	/** @todo NSTSVM: handle single-stepping. */
4739	}
4740
4741	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4742	return rc;
4743	}
4744	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
4745
4746
4747	/**
4748	* Runs the guest code using AMD-V.
4749	*
4750	* @returns Strict VBox status code.
4751	* @param pVCpu The cross context virtual CPU structure.
4752	*/
4753	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPUCC pVCpu)
4754	{
4755	AssertPtr(pVCpu);
4756	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4757	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4758	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4759	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4760
4761	uint32_t cLoops = 0;
4762	VBOXSTRICTRC rc;
4763	for (;;)
4764	{
4765	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4766	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
4767	#else
4768	NOREF(pCtx);
4769	bool const fInNestedGuestMode = false;
4770	#endif
4771	if (!fInNestedGuestMode)
4772	{
4773	if (!pVCpu->hm.s.fSingleInstruction)
4774	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
4775	else
4776	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
4777	}
4778	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4779	else
4780	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
4781
4782	if (rc == VINF_SVM_VMRUN)
4783	{
4784	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4785	continue;
4786	}
4787	if (rc == VINF_SVM_VMEXIT)
4788	{
4789	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4790	continue;
4791	}
4792	#endif
4793	break;
4794	}
4795
4796	/* Fixup error codes. */
4797	if (rc == VERR_EM_INTERPRETER)
4798	rc = VINF_EM_RAW_EMULATE_INSTR;
4799	else if (rc == VINF_EM_RESET)
4800	rc = VINF_EM_TRIPLE_FAULT;
4801
4802	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4803	rc = hmR0SvmExitToRing3(pVCpu, rc);
4804	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4805	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4806	return rc;
4807	}
4808
4809
4810	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4811	/**
4812	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
4813	*
4814	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4815	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4816	*/
4817	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4818	{
4819	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4820	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4821	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4822	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4823	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
4824	const bool fRep = pIoExitInfo->n.u1Rep;
4825	const bool fStrIo = pIoExitInfo->n.u1Str;
4826
4827	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4828	NULL /* pIoExitInfo */);
4829	}
4830
4831
4832	/**
4833	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4834	* SVM_EXIT_INVALID).
4835	*
4836	* @returns VBox status code (informational status codes included).
4837	* @param pVCpu The cross context virtual CPU structure.
4838	* @param pSvmTransient Pointer to the SVM transient structure.
4839	*/
4840	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4841	{
4842	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4843	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4844	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4845
4846	/*
4847	* We import the complete state here because we use separate VMCBs for the guest and the
4848	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
4849	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
4850	*/
4851	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4852	do { \
4853	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
4854	return IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); \
4855	} while (0)
4856
4857	/*
4858	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
4859	* nested-guest. If it isn't, it should be handled by the (outer) guest.
4860	*/
4861	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
4862	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4863	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4864	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4865	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4866	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4867
4868	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4869	switch (uExitCode)
4870	{
4871	case SVM_EXIT_CPUID:
4872	{
4873	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4874	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4875	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
4876	}
4877
4878	case SVM_EXIT_RDTSC:
4879	{
4880	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4881	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4882	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
4883	}
4884
4885	case SVM_EXIT_RDTSCP:
4886	{
4887	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4888	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4889	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
4890	}
4891
4892	case SVM_EXIT_MONITOR:
4893	{
4894	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4895	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4896	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
4897	}
4898
4899	case SVM_EXIT_MWAIT:
4900	{
4901	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4902	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4903	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
4904	}
4905
4906	case SVM_EXIT_HLT:
4907	{
4908	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4909	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4910	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
4911	}
4912
4913	case SVM_EXIT_MSR:
4914	{
4915	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4916	{
4917	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
4918	uint16_t offMsrpm;
4919	uint8_t uMsrpmBit;
4920	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4921	if (RT_SUCCESS(rc))
4922	{
4923	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
4924	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
4925
4926	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4927	pbMsrBitmap += offMsrpm;
4928	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
4929	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
4930
4931	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4932	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4933	{
4934	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4935	}
4936	}
4937	else
4938	{
4939	/*
4940	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4941	* See AMD-V spec. "15.11 MSR Intercepts".
4942	*/
4943	Assert(rc == VERR_OUT_OF_RANGE);
4944	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4945	}
4946	}
4947	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
4948	}
4949
4950	case SVM_EXIT_IOIO:
4951	{
4952	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4953	{
4954	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
4955	SVMIOIOEXITINFO IoExitInfo;
4956	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4957	bool const fIntercept = hmR0SvmIsIoInterceptSet(pvIoBitmap, &IoExitInfo);
4958	if (fIntercept)
4959	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4960	}
4961	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
4962	}
4963
4964	case SVM_EXIT_XCPT_PF:
4965	{
4966	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4967	if (pVM->hmr0.s.fNestedPaging)
4968	{
4969	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4970	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4971
4972	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4973	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4974	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4975
4976	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
4977	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
4978	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
4979	return VINF_SUCCESS;
4980	}
4981	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
4982	}
4983
4984	case SVM_EXIT_XCPT_UD:
4985	{
4986	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
4987	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4988	hmR0SvmSetPendingXcptUD(pVCpu);
4989	return VINF_SUCCESS;
4990	}
4991
4992	case SVM_EXIT_XCPT_MF:
4993	{
4994	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
4995	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4996	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
4997	}
4998
4999	case SVM_EXIT_XCPT_DB:
5000	{
5001	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5002	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5003	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
5004	}
5005
5006	case SVM_EXIT_XCPT_AC:
5007	{
5008	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5009	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5010	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
5011	}
5012
5013	case SVM_EXIT_XCPT_BP:
5014	{
5015	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5016	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5017	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
5018	}
5019
5020	case SVM_EXIT_READ_CR0:
5021	case SVM_EXIT_READ_CR3:
5022	case SVM_EXIT_READ_CR4:
5023	{
5024	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5025	if (CPUMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5026	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5027	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5028	}
5029
5030	case SVM_EXIT_CR0_SEL_WRITE:
5031	{
5032	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5033	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5034	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5035	}
5036
5037	case SVM_EXIT_WRITE_CR0:
5038	case SVM_EXIT_WRITE_CR3:
5039	case SVM_EXIT_WRITE_CR4:
5040	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5041	{
5042	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5043	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5044
5045	if (CPUMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5046	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5047	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5048	}
5049
5050	case SVM_EXIT_PAUSE:
5051	{
5052	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5053	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5054	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5055	}
5056
5057	case SVM_EXIT_VINTR:
5058	{
5059	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5060	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5061	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5062	}
5063
5064	case SVM_EXIT_INTR:
5065	case SVM_EXIT_NMI:
5066	case SVM_EXIT_SMI:
5067	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5068	{
5069	/*
5070	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5071	*
5072	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5073	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5074	* nested-guest #VMEXIT.
5075	*
5076	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5077	* while trying to inject interrupts, see comment at the top of this function.
5078	*/
5079	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5080	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5081	}
5082
5083	case SVM_EXIT_FERR_FREEZE:
5084	{
5085	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5086	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5087	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5088	}
5089
5090	case SVM_EXIT_INVLPG:
5091	{
5092	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5093	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5094	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5095	}
5096
5097	case SVM_EXIT_WBINVD:
5098	{
5099	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5100	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5101	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5102	}
5103
5104	case SVM_EXIT_INVD:
5105	{
5106	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5107	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5108	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5109	}
5110
5111	case SVM_EXIT_RDPMC:
5112	{
5113	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5114	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5115	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5116	}
5117
5118	default:
5119	{
5120	switch (uExitCode)
5121	{
5122	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5123	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5124	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5125	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5126	{
5127	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5128	if (CPUMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5129	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5130	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5131	}
5132
5133	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5134	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5135	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5136	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5137	{
5138	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5139	if (CPUMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5140	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5141	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5142	}
5143
5144	case SVM_EXIT_XCPT_DE:
5145	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5146	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5147	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5148	case SVM_EXIT_XCPT_OF:
5149	case SVM_EXIT_XCPT_BR:
5150	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5151	case SVM_EXIT_XCPT_NM:
5152	case SVM_EXIT_XCPT_DF:
5153	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5154	case SVM_EXIT_XCPT_TS:
5155	case SVM_EXIT_XCPT_NP:
5156	case SVM_EXIT_XCPT_SS:
5157	case SVM_EXIT_XCPT_GP:
5158	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5159	case SVM_EXIT_XCPT_15: /* Reserved. */
5160	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5161	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5162	case SVM_EXIT_XCPT_MC:
5163	case SVM_EXIT_XCPT_XF:
5164	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5165	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5166	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5167	{
5168	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5169	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5170	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5171	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5172	}
5173
5174	case SVM_EXIT_XSETBV:
5175	{
5176	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5177	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5178	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5179	}
5180
5181	case SVM_EXIT_TASK_SWITCH:
5182	{
5183	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5184	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5185	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5186	}
5187
5188	case SVM_EXIT_IRET:
5189	{
5190	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5191	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5192	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5193	}
5194
5195	case SVM_EXIT_SHUTDOWN:
5196	{
5197	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5198	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5199	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5200	}
5201
5202	case SVM_EXIT_VMMCALL:
5203	{
5204	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5205	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5206	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5207	}
5208
5209	case SVM_EXIT_CLGI:
5210	{
5211	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5212	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5213	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5214	}
5215
5216	case SVM_EXIT_STGI:
5217	{
5218	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5219	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5220	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5221	}
5222
5223	case SVM_EXIT_VMLOAD:
5224	{
5225	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5226	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5227	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5228	}
5229
5230	case SVM_EXIT_VMSAVE:
5231	{
5232	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5233	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5234	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5235	}
5236
5237	case SVM_EXIT_INVLPGA:
5238	{
5239	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5240	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5241	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5242	}
5243
5244	case SVM_EXIT_VMRUN:
5245	{
5246	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5247	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5248	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5249	}
5250
5251	case SVM_EXIT_RSM:
5252	{
5253	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5254	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5255	hmR0SvmSetPendingXcptUD(pVCpu);
5256	return VINF_SUCCESS;
5257	}
5258
5259	case SVM_EXIT_SKINIT:
5260	{
5261	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5262	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5263	hmR0SvmSetPendingXcptUD(pVCpu);
5264	return VINF_SUCCESS;
5265	}
5266
5267	case SVM_EXIT_NPF:
5268	{
5269	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5270	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5271	}
5272
5273	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5274	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5275
5276	default:
5277	{
5278	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5279	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5280	return VERR_SVM_UNKNOWN_EXIT;
5281	}
5282	}
5283	}
5284	}
5285	/* not reached */
5286
5287	#undef NST_GST_VMEXIT_CALL_RET
5288	}
5289	#endif
5290
5291
5292	/**
5293	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5294	*
5295	* @returns Strict VBox status code (informational status codes included).
5296	* @param pVCpu The cross context virtual CPU structure.
5297	* @param pSvmTransient Pointer to the SVM transient structure.
5298	*/
5299	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5300	{
5301	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5302	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5303
5304	#ifdef DEBUG_ramshankar
5305	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5306	do { \
5307	if ((a_fDbg) == 1) \
5308	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5309	int rc = a_CallExpr; \
5310	if ((a_fDbg) == 1) \
5311	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5312	return rc; \
5313	} while (0)
5314	#else
5315	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5316	#endif
5317
5318	/*
5319	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5320	* for most guests under normal workloads (for some definition of "normal").
5321	*/
5322	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5323	switch (uExitCode)
5324	{
5325	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5326	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5327	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5328	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5329	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5330	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5331	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5332	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5333	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5334	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5335
5336	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5337	case SVM_EXIT_INTR:
5338	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5339
5340	case SVM_EXIT_READ_CR0:
5341	case SVM_EXIT_READ_CR3:
5342	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5343
5344	case SVM_EXIT_CR0_SEL_WRITE:
5345	case SVM_EXIT_WRITE_CR0:
5346	case SVM_EXIT_WRITE_CR3:
5347	case SVM_EXIT_WRITE_CR4:
5348	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5349
5350	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5351	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5352	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5353	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5354	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5355	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5356	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5357	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5358	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5359	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5360	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5361	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5362	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5363	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5364	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5365	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5366
5367	default:
5368	{
5369	switch (pSvmTransient->u64ExitCode)
5370	{
5371	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5372	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5373	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5374	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5375	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5376
5377	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5378	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5379	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5380	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5381	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5382
5383	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5384	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5385
5386	case SVM_EXIT_SMI:
5387	case SVM_EXIT_INIT:
5388	{
5389	/*
5390	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5391	* If it ever does, we want to know about it so log the exit code and bail.
5392	*/
5393	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5394	}
5395
5396	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5397	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5398	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5399	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5400	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5401	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5402	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5403	#else
5404	case SVM_EXIT_CLGI:
5405	case SVM_EXIT_STGI:
5406	case SVM_EXIT_VMLOAD:
5407	case SVM_EXIT_VMSAVE:
5408	case SVM_EXIT_INVLPGA:
5409	case SVM_EXIT_VMRUN:
5410	#endif
5411	case SVM_EXIT_RSM:
5412	case SVM_EXIT_SKINIT:
5413	{
5414	hmR0SvmSetPendingXcptUD(pVCpu);
5415	return VINF_SUCCESS;
5416	}
5417
5418	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5419	case SVM_EXIT_XCPT_DE:
5420	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5421	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5422	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5423	case SVM_EXIT_XCPT_OF:
5424	case SVM_EXIT_XCPT_BR:
5425	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5426	case SVM_EXIT_XCPT_NM:
5427	case SVM_EXIT_XCPT_DF:
5428	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5429	case SVM_EXIT_XCPT_TS:
5430	case SVM_EXIT_XCPT_NP:
5431	case SVM_EXIT_XCPT_SS:
5432	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5433	/* SVM_EXIT_XCPT_PF: */
5434	case SVM_EXIT_XCPT_15: /* Reserved. */
5435	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5436	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5437	case SVM_EXIT_XCPT_MC:
5438	case SVM_EXIT_XCPT_XF:
5439	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5440	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5441	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5442	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5443	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5444
5445	default:
5446	{
5447	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5448	pVCpu->hm.s.u32HMError = uExitCode;
5449	return VERR_SVM_UNKNOWN_EXIT;
5450	}
5451	}
5452	}
5453	}
5454	/* not reached */
5455	#undef VMEXIT_CALL_RET
5456	}
5457
5458
5459	#ifdef VBOX_STRICT
5460	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5461	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5462	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5463
5464	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5465	do \
5466	{ \
5467	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5468	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5469	} while (0)
5470
5471	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5472	do { \
5473	AssertPtr((a_pVCpu)); \
5474	AssertPtr((a_pSvmTransient)); \
5475	Assert(ASMIntAreEnabled()); \
5476	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5477	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5478	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5479	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5480	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5481	HMSVM_ASSERT_PREEMPT_CPUID(); \
5482	} while (0)
5483	#else
5484	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5485	do { \
5486	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5487	} while (0)
5488	#endif
5489
5490
5491	/**
5492	* Gets the IEM exception flags for the specified SVM event.
5493	*
5494	* @returns The IEM exception flags.
5495	* @param pEvent Pointer to the SVM event.
5496	*
5497	* @remarks This function currently only constructs flags required for
5498	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5499	* and CR2 aspects of an exception are not included).
5500	*/
5501	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5502	{
5503	uint8_t const uEventType = pEvent->n.u3Type;
5504	uint32_t fIemXcptFlags;
5505	switch (uEventType)
5506	{
5507	case SVM_EVENT_EXCEPTION:
5508	/*
5509	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5510	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5511	*/
5512	if (pEvent->n.u8Vector == X86_XCPT_BP)
5513	{
5514	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5515	break;
5516	}
5517	if (pEvent->n.u8Vector == X86_XCPT_OF)
5518	{
5519	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5520	break;
5521	}
5522	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5523	RT_FALL_THRU();
5524	case SVM_EVENT_NMI:
5525	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5526	break;
5527
5528	case SVM_EVENT_EXTERNAL_IRQ:
5529	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5530	break;
5531
5532	case SVM_EVENT_SOFTWARE_INT:
5533	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5534	break;
5535
5536	default:
5537	fIemXcptFlags = 0;
5538	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5539	break;
5540	}
5541	return fIemXcptFlags;
5542	}
5543
5544
5545	/**
5546	* Handle a condition that occurred while delivering an event through the guest
5547	* IDT.
5548	*
5549	* @returns VBox status code (informational error codes included).
5550	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5551	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5552	* continue execution of the guest which will delivery the \#DF.
5553	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5554	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5555	*
5556	* @param pVCpu The cross context virtual CPU structure.
5557	* @param pSvmTransient Pointer to the SVM transient structure.
5558	*
5559	* @remarks No-long-jump zone!!!
5560	*/
5561	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5562	{
5563	int rc = VINF_SUCCESS;
5564	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5565	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5566
5567	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5568	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5569	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5570
5571	/*
5572	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5573	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5574	*
5575	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5576	*/
5577	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5578	{
5579	IEMXCPTRAISE enmRaise;
5580	IEMXCPTRAISEINFO fRaiseInfo;
5581	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5582	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5583	if (fExitIsHwXcpt)
5584	{
5585	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5586	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5587	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5588	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5589	}
5590	else
5591	{
5592	/*
5593	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5594	* then we end up here.
5595	*
5596	* If the event was:
5597	* - a software interrupt, we can re-execute the instruction which will
5598	* regenerate the event.
5599	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5600	* - a hardware exception or external interrupt, we re-inject it.
5601	*/
5602	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5603	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5604	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5605	else
5606	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5607	}
5608
5609	switch (enmRaise)
5610	{
5611	case IEMXCPTRAISE_CURRENT_XCPT:
5612	case IEMXCPTRAISE_PREV_EVENT:
5613	{
5614	/* For software interrupts, we shall re-execute the instruction. */
5615	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5616	{
5617	RTGCUINTPTR GCPtrFaultAddress = 0;
5618
5619	/* If we are re-injecting an NMI, clear NMI blocking. */
5620	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5621	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5622
5623	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5624	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5625	{
5626	pSvmTransient->fVectoringPF = true;
5627	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5628	pVCpu->cpum.GstCtx.cr2));
5629	}
5630	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5631	&& uIdtVector == X86_XCPT_PF)
5632	{
5633	/*
5634	* If the previous exception was a #PF, we need to recover the CR2 value.
5635	* This can't happen with shadow paging.
5636	*/
5637	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5638	}
5639
5640	/*
5641	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5642	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5643	*/
5644	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5645	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
5646	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5647
5648	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5649	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5650	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5651	}
5652	break;
5653	}
5654
5655	case IEMXCPTRAISE_REEXEC_INSTR:
5656	{
5657	Assert(rc == VINF_SUCCESS);
5658	break;
5659	}
5660
5661	case IEMXCPTRAISE_DOUBLE_FAULT:
5662	{
5663	/*
5664	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5665	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5666	* converted into a #DF.
5667	*/
5668	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5669	{
5670	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5671	pSvmTransient->fVectoringDoublePF = true;
5672	Assert(rc == VINF_SUCCESS);
5673	}
5674	else
5675	{
5676	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
5677	hmR0SvmSetPendingXcptDF(pVCpu);
5678	rc = VINF_HM_DOUBLE_FAULT;
5679	}
5680	break;
5681	}
5682
5683	case IEMXCPTRAISE_TRIPLE_FAULT:
5684	{
5685	rc = VINF_EM_RESET;
5686	break;
5687	}
5688
5689	case IEMXCPTRAISE_CPU_HANG:
5690	{
5691	rc = VERR_EM_GUEST_CPU_HANG;
5692	break;
5693	}
5694
5695	default:
5696	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
5697	}
5698	}
5699	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5700	return rc;
5701	}
5702
5703
5704	/**
5705	* Advances the guest RIP by the number of bytes specified in @a cb.
5706	*
5707	* @param pVCpu The cross context virtual CPU structure.
5708	* @param cb RIP increment value in bytes.
5709	*/
5710	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
5711	{
5712	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5713	pCtx->rip += cb;
5714
5715	/* Update interrupt shadow. */
5716	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5717	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
5718	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5719	}
5720
5721
5722	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5723	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5724	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5725
5726	/** @name \#VMEXIT handlers.
5727	* @{
5728	*/
5729
5730	/**
5731	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5732	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5733	*/
5734	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5735	{
5736	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5737
5738	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5739	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5740	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5741	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5742
5743	/*
5744	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
5745	* signal -before- the timer fires if the current interrupt is our own timer or a some
5746	* other host interrupt. We also cannot examine what interrupt it is until the host
5747	* actually take the interrupt.
5748	*
5749	* Going back to executing guest code here unconditionally causes random scheduling
5750	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5751	*/
5752	return VINF_EM_RAW_INTERRUPT;
5753	}
5754
5755
5756	/**
5757	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5758	*/
5759	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5760	{
5761	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5762
5763	VBOXSTRICTRC rcStrict;
5764	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5765	if (fSupportsNextRipSave)
5766	{
5767	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5768	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5769	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5770	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
5771	}
5772	else
5773	{
5774	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5775	rcStrict = IEMExecOne(pVCpu);
5776	}
5777
5778	if (rcStrict == VINF_IEM_RAISED_XCPT)
5779	{
5780	rcStrict = VINF_SUCCESS;
5781	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5782	}
5783	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5784	return rcStrict;
5785	}
5786
5787
5788	/**
5789	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5790	*/
5791	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5792	{
5793	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5794
5795	VBOXSTRICTRC rcStrict;
5796	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5797	if (fSupportsNextRipSave)
5798	{
5799	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5800	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5801	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5802	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
5803	}
5804	else
5805	{
5806	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5807	rcStrict = IEMExecOne(pVCpu);
5808	}
5809
5810	if (rcStrict == VINF_IEM_RAISED_XCPT)
5811	{
5812	rcStrict = VINF_SUCCESS;
5813	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5814	}
5815	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5816	return rcStrict;
5817	}
5818
5819
5820	/**
5821	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5822	*/
5823	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5824	{
5825	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5826
5827	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
5828	VBOXSTRICTRC rcStrict;
5829	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
5830	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
5831	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
5832	if (!pExitRec)
5833	{
5834	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5835	if (fSupportsNextRipSave)
5836	{
5837	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5838	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5839	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
5840	}
5841	else
5842	{
5843	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5844	rcStrict = IEMExecOne(pVCpu);
5845	}
5846
5847	if (rcStrict == VINF_IEM_RAISED_XCPT)
5848	{
5849	rcStrict = VINF_SUCCESS;
5850	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5851	}
5852	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5853	}
5854	else
5855	{
5856	/*
5857	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
5858	*/
5859	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5860
5861	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
5862	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
5863
5864	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
5865
5866	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
5867	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
5868	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
5869	}
5870	return rcStrict;
5871	}
5872
5873
5874	/**
5875	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5876	*/
5877	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5878	{
5879	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5880
5881	VBOXSTRICTRC rcStrict;
5882	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5883	if (fSupportsNextRipSave)
5884	{
5885	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5886	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5887	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5888	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
5889	}
5890	else
5891	{
5892	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5893	rcStrict = IEMExecOne(pVCpu);
5894	}
5895
5896	if (rcStrict == VINF_SUCCESS)
5897	pSvmTransient->fUpdateTscOffsetting = true;
5898	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5899	{
5900	rcStrict = VINF_SUCCESS;
5901	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5902	}
5903	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5904	return rcStrict;
5905	}
5906
5907
5908	/**
5909	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5910	*/
5911	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5912	{
5913	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5914
5915	VBOXSTRICTRC rcStrict;
5916	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5917	if (fSupportsNextRipSave)
5918	{
5919	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
5920	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5921	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5922	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
5923	}
5924	else
5925	{
5926	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5927	rcStrict = IEMExecOne(pVCpu);
5928	}
5929
5930	if (rcStrict == VINF_SUCCESS)
5931	pSvmTransient->fUpdateTscOffsetting = true;
5932	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5933	{
5934	rcStrict = VINF_SUCCESS;
5935	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5936	}
5937	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5938	return rcStrict;
5939	}
5940
5941
5942	/**
5943	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5944	*/
5945	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5946	{
5947	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5948
5949	VBOXSTRICTRC rcStrict;
5950	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5951	if (fSupportsNextRipSave)
5952	{
5953	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5954	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5955	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5956	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
5957	}
5958	else
5959	{
5960	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5961	rcStrict = IEMExecOne(pVCpu);
5962	}
5963
5964	if (rcStrict == VINF_IEM_RAISED_XCPT)
5965	{
5966	rcStrict = VINF_SUCCESS;
5967	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5968	}
5969	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5970	return rcStrict;
5971	}
5972
5973
5974	/**
5975	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5976	*/
5977	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5978	{
5979	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5980	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5981
5982	VBOXSTRICTRC rcStrict;
5983	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
5984	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5985	if ( fSupportsDecodeAssists
5986	&& fSupportsNextRipSave)
5987	{
5988	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
5989	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5990	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5991	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
5992	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
5993	}
5994	else
5995	{
5996	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5997	rcStrict = IEMExecOne(pVCpu);
5998	}
5999
6000	if (rcStrict == VINF_IEM_RAISED_XCPT)
6001	{
6002	rcStrict = VINF_SUCCESS;
6003	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6004	}
6005	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6006	return VBOXSTRICTRC_VAL(rcStrict);
6007	}
6008
6009
6010	/**
6011	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6012	*/
6013	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6014	{
6015	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6016
6017	VBOXSTRICTRC rcStrict;
6018	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6019	if (fSupportsNextRipSave)
6020	{
6021	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6022	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6023	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6024	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6025	}
6026	else
6027	{
6028	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6029	rcStrict = IEMExecOne(pVCpu);
6030	}
6031
6032	if ( rcStrict == VINF_EM_HALT
6033	\|\| rcStrict == VINF_SUCCESS)
6034	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6035	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6036	{
6037	rcStrict = VINF_SUCCESS;
6038	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6039	}
6040	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6041	if (rcStrict != VINF_SUCCESS)
6042	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6043	return VBOXSTRICTRC_VAL(rcStrict);;
6044	}
6045
6046
6047	/**
6048	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6049	*/
6050	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6051	{
6052	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6053
6054	/*
6055	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6056	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6057	* segment override prefix or other prefixes might be used, in which case we fallback to
6058	* IEMExecOne() to figure out.
6059	*/
6060	VBOXSTRICTRC rcStrict;
6061	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6062	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6063	if (cbInstr)
6064	{
6065	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6066	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6067	}
6068	else
6069	{
6070	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6071	rcStrict = IEMExecOne(pVCpu);
6072	}
6073
6074	if (rcStrict == VINF_IEM_RAISED_XCPT)
6075	{
6076	rcStrict = VINF_SUCCESS;
6077	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6078	}
6079	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6080	return rcStrict;
6081	}
6082
6083
6084	/**
6085	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6086	*/
6087	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6088	{
6089	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6090
6091	VBOXSTRICTRC rcStrict;
6092	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6093	if (fSupportsNextRipSave)
6094	{
6095	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6096	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6097	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6098	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6099	}
6100	else
6101	{
6102	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6103	rcStrict = IEMExecOne(pVCpu);
6104	}
6105
6106	if ( rcStrict == VINF_EM_HALT
6107	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6108	rcStrict = VINF_SUCCESS;
6109	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6110	{
6111	rcStrict = VINF_SUCCESS;
6112	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6113	}
6114	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6115	return rcStrict;
6116	}
6117
6118
6119	/**
6120	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6121	* \#VMEXIT.
6122	*/
6123	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6124	{
6125	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6126	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6127	return VINF_EM_RESET;
6128	}
6129
6130
6131	/**
6132	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6133	*/
6134	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6135	{
6136	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6137	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6138	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6139	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6140	RT_NOREF(pVmcb);
6141	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6142	return VERR_SVM_UNEXPECTED_EXIT;
6143	}
6144
6145
6146	/**
6147	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6148	*/
6149	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6150	{
6151	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6152
6153	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6154	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6155	#ifdef VBOX_WITH_STATISTICS
6156	switch (pSvmTransient->u64ExitCode)
6157	{
6158	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6159	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6160	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6161	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6162	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6163	}
6164	#endif
6165
6166	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6167	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6168	if ( fSupportsDecodeAssists
6169	&& fSupportsNextRipSave)
6170	{
6171	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6172	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6173	if (fMovCRx)
6174	{
6175	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6176	\| CPUMCTX_EXTRN_APIC_TPR);
6177	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6178	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6179	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6180	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6181	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6182	return VBOXSTRICTRC_VAL(rcStrict);
6183	}
6184	/* else: SMSW instruction, fall back below to IEM for this. */
6185	}
6186
6187	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6188	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6189	AssertMsg( rcStrict == VINF_SUCCESS
6190	\|\| rcStrict == VINF_PGM_SYNC_CR3
6191	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6192	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6193	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6194	if (rcStrict == VINF_IEM_RAISED_XCPT)
6195	{
6196	rcStrict = VINF_SUCCESS;
6197	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6198	}
6199	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6200	return rcStrict;
6201	}
6202
6203
6204	/**
6205	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6206	*/
6207	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6208	{
6209	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6210
6211	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6212	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6213	Assert(iCrReg <= 15);
6214
6215	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6216	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6217	bool fDecodedInstr = false;
6218	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6219	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6220	if ( fSupportsDecodeAssists
6221	&& fSupportsNextRipSave)
6222	{
6223	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6224	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6225	if (fMovCRx)
6226	{
6227	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6228	\| CPUMCTX_EXTRN_APIC_TPR);
6229	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6230	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6231	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6232	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6233	fDecodedInstr = true;
6234	}
6235	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6236	}
6237
6238	if (!fDecodedInstr)
6239	{
6240	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6241	Log4Func(("iCrReg=%#x\n", iCrReg));
6242	rcStrict = IEMExecOne(pVCpu);
6243	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6244	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6245	rcStrict = VERR_EM_INTERPRETER;
6246	}
6247
6248	if (rcStrict == VINF_SUCCESS)
6249	{
6250	switch (iCrReg)
6251	{
6252	case 0:
6253	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6254	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6255	break;
6256
6257	case 2:
6258	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6259	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6260	break;
6261
6262	case 3:
6263	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6264	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6265	break;
6266
6267	case 4:
6268	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6269	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6270	break;
6271
6272	case 8:
6273	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6274	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6275	break;
6276
6277	default:
6278	{
6279	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6280	pSvmTransient->u64ExitCode, iCrReg));
6281	break;
6282	}
6283	}
6284	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6285	}
6286	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6287	{
6288	rcStrict = VINF_SUCCESS;
6289	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6290	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6291	}
6292	else
6293	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6294	return rcStrict;
6295	}
6296
6297
6298	/**
6299	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6300	*
6301	* @returns Strict VBox status code.
6302	* @param pVCpu The cross context virtual CPU structure.
6303	* @param pVmcb Pointer to the VM control block.
6304	*/
6305	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
6306	{
6307	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6308	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6309
6310	VBOXSTRICTRC rcStrict;
6311	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6312	if (fSupportsNextRipSave)
6313	{
6314	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6315	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6316	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6317	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6318	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6319	}
6320	else
6321	{
6322	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6323	rcStrict = IEMExecOne(pVCpu);
6324	}
6325
6326	AssertMsg( rcStrict == VINF_SUCCESS
6327	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6328	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6329	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6330
6331	if (rcStrict == VINF_IEM_RAISED_XCPT)
6332	{
6333	rcStrict = VINF_SUCCESS;
6334	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6335	}
6336	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6337	return rcStrict;
6338	}
6339
6340
6341	/**
6342	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6343	*
6344	* @returns Strict VBox status code.
6345	* @param pVCpu The cross context virtual CPU structure.
6346	* @param pVmcb Pointer to the VM control block.
6347	* @param pSvmTransient Pointer to the SVM-transient structure.
6348	*/
6349	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6350	{
6351	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6352	uint32_t const idMsr = pCtx->ecx;
6353	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6354	Log4Func(("idMsr=%#RX32\n", idMsr));
6355
6356	/*
6357	* Handle TPR patching MSR writes.
6358	* We utilitize the LSTAR MSR for patching.
6359	*/
6360	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6361	if ( idMsr == MSR_K8_LSTAR
6362	&& pVCpu->CTX_SUFF(pVM)->hm.s.fTprPatchingActive)
6363	{
6364	unsigned cbInstr;
6365	if (fSupportsNextRipSave)
6366	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6367	else
6368	{
6369	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
6370	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6371	if ( rc == VINF_SUCCESS
6372	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6373	Assert(cbInstr > 0);
6374	else
6375	cbInstr = 0;
6376	}
6377
6378	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6379	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6380	{
6381	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6382	AssertRCReturn(rc, rc);
6383	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6384	}
6385
6386	int rc = VINF_SUCCESS;
6387	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6388	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6389	return rc;
6390	}
6391
6392	/*
6393	* Handle regular MSR writes.
6394	*/
6395	VBOXSTRICTRC rcStrict;
6396	if (fSupportsNextRipSave)
6397	{
6398	/** @todo Optimize this: We don't need to get much of the MSR state here
6399	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6400	* clear the applicable extern flags. */
6401	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6402	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6403	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6404	}
6405	else
6406	{
6407	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6408	rcStrict = IEMExecOne(pVCpu);
6409	}
6410
6411	AssertMsg( rcStrict == VINF_SUCCESS
6412	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6413	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6414	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6415
6416	if (rcStrict == VINF_SUCCESS)
6417	{
6418	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6419	if ( idMsr >= MSR_IA32_X2APIC_START
6420	&& idMsr <= MSR_IA32_X2APIC_END)
6421	{
6422	/*
6423	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6424	* When full APIC register virtualization is implemented we'll have to make sure
6425	* APIC state is saved from the VMCB before IEM changes it.
6426	*/
6427	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6428	}
6429	else
6430	{
6431	switch (idMsr)
6432	{
6433	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6434	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6435	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6436	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6437	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6438	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6439	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6440	}
6441	}
6442	}
6443	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6444	{
6445	rcStrict = VINF_SUCCESS;
6446	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6447	}
6448	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6449	return rcStrict;
6450	}
6451
6452
6453	/**
6454	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6455	* \#VMEXIT.
6456	*/
6457	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6458	{
6459	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6460
6461	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6462	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6463	return hmR0SvmExitReadMsr(pVCpu, pVmcb);
6464
6465	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6466	return hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient);
6467	}
6468
6469
6470	/**
6471	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6472	*/
6473	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6474	{
6475	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6476	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6477
6478	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6479
6480	/** @todo Stepping with nested-guest. */
6481	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6482	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6483	{
6484	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6485	if (pSvmTransient->fWasGuestDebugStateActive)
6486	{
6487	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6488	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6489	return VERR_SVM_UNEXPECTED_EXIT;
6490	}
6491
6492	/*
6493	* Lazy DR0-3 loading.
6494	*/
6495	if (!pSvmTransient->fWasHyperDebugStateActive)
6496	{
6497	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6498	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6499
6500	/* Don't intercept DRx read and writes. */
6501	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
6502	pVmcb->ctrl.u16InterceptRdDRx = 0;
6503	pVmcb->ctrl.u16InterceptWrDRx = 0;
6504	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6505
6506	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6507	VMMRZCallRing3Disable(pVCpu);
6508	HM_DISABLE_PREEMPT(pVCpu);
6509
6510	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6511	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6512	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6513
6514	HM_RESTORE_PREEMPT();
6515	VMMRZCallRing3Enable(pVCpu);
6516
6517	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6518	return VINF_SUCCESS;
6519	}
6520	}
6521
6522	/*
6523	* Interpret the read/writing of DRx.
6524	*/
6525	/** @todo Decode assist. */
6526	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6527	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6528	if (RT_LIKELY(rc == VINF_SUCCESS))
6529	{
6530	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6531	/** @todo CPUM should set this flag! */
6532	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6533	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6534	}
6535	else
6536	Assert(rc == VERR_EM_INTERPRETER);
6537	return rc;
6538	}
6539
6540
6541	/**
6542	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6543	*/
6544	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6545	{
6546	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6547	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6548	VBOXSTRICTRC rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6549	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6550	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6551	return rc;
6552	}
6553
6554
6555	/**
6556	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6557	*/
6558	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6559	{
6560	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6561	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6562
6563	/** @todo decode assists... */
6564	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6565	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6566	{
6567	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6568	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6569	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], fLoadSaveGuestXcr0, pCtx->cr4));
6570	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
6571	{
6572	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
6573	hmR0SvmUpdateVmRunFunction(pVCpu);
6574	}
6575	}
6576	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6577	{
6578	rcStrict = VINF_SUCCESS;
6579	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6580	}
6581	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6582	return rcStrict;
6583	}
6584
6585
6586	/**
6587	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6588	*/
6589	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6590	{
6591	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6592	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6593
6594	/* I/O operation lookup arrays. */
6595	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6596	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6597	the result (in AL/AX/EAX). */
6598	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6599	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6600	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6601
6602	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6603
6604	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6605	SVMIOIOEXITINFO IoExitInfo;
6606	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6607	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6608	uint32_t cbValue = s_aIOSize[uIOWidth];
6609	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6610
6611	if (RT_UNLIKELY(!cbValue))
6612	{
6613	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6614	return VERR_EM_INTERPRETER;
6615	}
6616
6617	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6618	VBOXSTRICTRC rcStrict;
6619	PCEMEXITREC pExitRec = NULL;
6620	if ( !pVCpu->hm.s.fSingleInstruction
6621	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6622	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6623	!IoExitInfo.n.u1Str
6624	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6625	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6626	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6627	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6628	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6629	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6630	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6631	if (!pExitRec)
6632	{
6633	bool fUpdateRipAlready = false;
6634	if (IoExitInfo.n.u1Str)
6635	{
6636	/* INS/OUTS - I/O String instruction. */
6637	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6638	* in EXITINFO1? Investigate once this thing is up and running. */
6639	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6640	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6641	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6642	static IEMMODE const s_aenmAddrMode[8] =
6643	{
6644	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6645	};
6646	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6647	if (enmAddrMode != (IEMMODE)-1)
6648	{
6649	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6650	if (cbInstr <= 15 && cbInstr >= 1)
6651	{
6652	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6653	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6654	{
6655	/* Don't know exactly how to detect whether u3Seg is valid, currently
6656	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6657	2384 Opterons when only checking NRIP. */
6658	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6659	if ( fSupportsNextRipSave
6660	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6661	{
6662	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6663	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6664	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6665	IoExitInfo.n.u3Seg, true /fIoChecked/);
6666	}
6667	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6668	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6669	X86_SREG_DS, true /fIoChecked/);
6670	else
6671	rcStrict = IEMExecOne(pVCpu);
6672	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6673	}
6674	else
6675	{
6676	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6677	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6678	true /fIoChecked/);
6679	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6680	}
6681	}
6682	else
6683	{
6684	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6685	rcStrict = IEMExecOne(pVCpu);
6686	}
6687	}
6688	else
6689	{
6690	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6691	rcStrict = IEMExecOne(pVCpu);
6692	}
6693	fUpdateRipAlready = true;
6694	}
6695	else
6696	{
6697	/* IN/OUT - I/O instruction. */
6698	Assert(!IoExitInfo.n.u1Rep);
6699
6700	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6701	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6702	{
6703	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6704	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6705	&& !pCtx->eflags.Bits.u1TF)
6706	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
6707	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6708	}
6709	else
6710	{
6711	uint32_t u32Val = 0;
6712	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6713	if (IOM_SUCCESS(rcStrict))
6714	{
6715	/* Save result of I/O IN instr. in AL/AX/EAX. */
6716	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6717	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6718	}
6719	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6720	&& !pCtx->eflags.Bits.u1TF)
6721	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
6722
6723	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6724	}
6725	}
6726
6727	if (IOM_SUCCESS(rcStrict))
6728	{
6729	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6730	if (!fUpdateRipAlready)
6731	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6732
6733	/*
6734	* If any I/O breakpoints are armed, we need to check if one triggered
6735	* and take appropriate action.
6736	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6737	*/
6738	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6739	* execution engines about whether hyper BPs and such are pending. */
6740	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
6741	uint32_t const uDr7 = pCtx->dr[7];
6742	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6743	&& X86_DR7_ANY_RW_IO(uDr7)
6744	&& (pCtx->cr4 & X86_CR4_DE))
6745	\|\| DBGFBpIsHwIoArmed(pVM)))
6746	{
6747	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6748	VMMRZCallRing3Disable(pVCpu);
6749	HM_DISABLE_PREEMPT(pVCpu);
6750
6751	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6752	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6753
6754	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
6755	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6756	{
6757	/* Raise #DB. */
6758	pVmcb->guest.u64DR6 = pCtx->dr[6];
6759	pVmcb->guest.u64DR7 = pCtx->dr[7];
6760	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6761	hmR0SvmSetPendingXcptDB(pVCpu);
6762	}
6763	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6764	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6765	else if ( rcStrict2 != VINF_SUCCESS
6766	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6767	rcStrict = rcStrict2;
6768	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6769
6770	HM_RESTORE_PREEMPT();
6771	VMMRZCallRing3Enable(pVCpu);
6772	}
6773
6774	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6775	}
6776
6777	#ifdef VBOX_STRICT
6778	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6779	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
6780	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6781	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6782	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
6783	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
6784	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6785	else
6786	{
6787	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6788	* statuses, that the VMM device and some others may return. See
6789	* IOM_SUCCESS() for guidance. */
6790	AssertMsg( RT_FAILURE(rcStrict)
6791	\|\| rcStrict == VINF_SUCCESS
6792	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6793	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6794	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6795	\|\| rcStrict == VINF_EM_DBG_STEPPED
6796	\|\| rcStrict == VINF_EM_RAW_TO_R3
6797	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
6798	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6799	}
6800	#endif
6801	}
6802	else
6803	{
6804	/*
6805	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6806	*/
6807	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6808	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
6809	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
6810	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
6811	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
6812	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
6813	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
6814
6815	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6816	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6817
6818	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6819	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6820	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6821	}
6822	return rcStrict;
6823	}
6824
6825
6826	/**
6827	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6828	*/
6829	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6830	{
6831	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6832	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6833	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6834
6835	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6836	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6837	Assert(pVM->hmr0.s.fNestedPaging);
6838
6839	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6840	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6841	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6842	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
6843	thus intentionally not copied into u32ErrCode. */
6844
6845	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x cbInstrFetched=%u %.15Rhxs\n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
6846	u32ErrCode, pVmcb->ctrl.cbInstrFetched, pVmcb->ctrl.abInstr));
6847
6848	/*
6849	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
6850	*/
6851	if ( pVM->hm.s.fTprPatchingAllowed
6852	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6853	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6854	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6855	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
6856	&& !CPUMIsGuestInLongModeEx(pCtx)
6857	&& !CPUMGetGuestCPL(pVCpu)
6858	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6859	{
6860	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6861	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6862
6863	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6864	{
6865	/* Only attempt to patch the instruction once. */
6866	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6867	if (!pPatch)
6868	return VINF_EM_HM_PATCH_TPR_INSTR;
6869	}
6870	}
6871
6872	/*
6873	* Determine the nested paging mode.
6874	*/
6875	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
6876	PGMMODE const enmNestedPagingMode = PGMGetHostMode(pVM);
6877
6878	/*
6879	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6880	*/
6881	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6882	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6883	{
6884	/*
6885	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
6886	* injecting the original pending event would most likely cause the same MMIO #NPF.
6887	*/
6888	if (pVCpu->hm.s.Event.fPending)
6889	{
6890	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
6891	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6892	}
6893
6894	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
6895	VBOXSTRICTRC rcStrict;
6896	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6897	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
6898	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6899	if (!pExitRec)
6900	{
6901
6902	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6903	u32ErrCode);
6904
6905	/*
6906	* If we succeed, resume guest execution.
6907	*
6908	* If we fail in interpreting the instruction because we couldn't get the guest
6909	* physical address of the page containing the instruction via the guest's page
6910	* tables (we would invalidate the guest page in the host TLB), resume execution
6911	* which would cause a guest page fault to let the guest handle this weird case.
6912	*
6913	* See @bugref{6043}.
6914	*/
6915	if ( rcStrict == VINF_SUCCESS
6916	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
6917	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
6918	{
6919	/* Successfully handled MMIO operation. */
6920	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6921	rcStrict = VINF_SUCCESS;
6922	}
6923	}
6924	else
6925	{
6926	/*
6927	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6928	*/
6929	Assert(pCtx == &pVCpu->cpum.GstCtx);
6930	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6931	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
6932	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
6933
6934	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6935	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6936
6937	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6938	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6939	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6940	}
6941	return rcStrict;
6942	}
6943
6944	/*
6945	* Nested page-fault.
6946	*/
6947	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6948	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6949	TRPMResetTrap(pVCpu);
6950
6951	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6952
6953	/*
6954	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6955	*/
6956	if ( rc == VINF_SUCCESS
6957	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6958	\|\| rc == VERR_PAGE_NOT_PRESENT)
6959	{
6960	/* We've successfully synced our shadow page tables. */
6961	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6962	rc = VINF_SUCCESS;
6963	}
6964
6965	/*
6966	* If delivering an event causes an #NPF (and not MMIO), we shall resolve the fault and
6967	* re-inject the original event.
6968	*/
6969	if (pVCpu->hm.s.Event.fPending)
6970	{
6971	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
6972
6973	/*
6974	* If the #NPF handler requested emulation of the instruction, ignore it.
6975	* We need to re-inject the original event so as to not lose it.
6976	* Reproducible when booting ReactOS 0.4.12 with BTRFS (installed using BootCD,
6977	* LiveCD is broken for other reasons).
6978	*/
6979	if (rc == VINF_EM_RAW_EMULATE_INSTR)
6980	rc = VINF_EM_RAW_INJECT_TRPM_EVENT;
6981	}
6982
6983	return rc;
6984	}
6985
6986
6987	/**
6988	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6989	* \#VMEXIT.
6990	*/
6991	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6992	{
6993	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6994	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
6995
6996	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6997	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6998	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
6999
7000	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7001	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7002	return VINF_SUCCESS;
7003	}
7004
7005
7006	/**
7007	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7008	* \#VMEXIT.
7009	*/
7010	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7011	{
7012	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7013	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7014
7015	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7016	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
7017	#endif
7018
7019	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7020	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7021	{
7022	/*
7023	* AMD-V provides us with the exception which caused the TS; we collect
7024	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7025	*/
7026	Log4Func(("TS occurred during event delivery\n"));
7027	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7028	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7029	}
7030
7031	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7032	* emulation. */
7033	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7034	return VERR_EM_INTERPRETER;
7035	}
7036
7037
7038	/**
7039	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7040	*/
7041	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7042	{
7043	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7044	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7045
7046	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7047	if (pVM->hm.s.fTprPatchingAllowed)
7048	{
7049	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
7050	if (rc != VERR_NOT_FOUND)
7051	{
7052	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
7053	return rc;
7054	}
7055	}
7056
7057	if (EMAreHypercallInstructionsEnabled(pVCpu))
7058	{
7059	unsigned cbInstr;
7060	if (hmR0SvmSupportsNextRipSave(pVCpu))
7061	{
7062	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7063	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7064	}
7065	else
7066	{
7067	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7068	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7069	if ( rc == VINF_SUCCESS
7070	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7071	Assert(cbInstr > 0);
7072	else
7073	cbInstr = 0;
7074	}
7075
7076	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7077	if (RT_SUCCESS(rcStrict))
7078	{
7079	/* Only update the RIP if we're continuing guest execution and not in the case
7080	of say VINF_GIM_R3_HYPERCALL. */
7081	if (rcStrict == VINF_SUCCESS)
7082	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7083
7084	return VBOXSTRICTRC_VAL(rcStrict);
7085	}
7086	else
7087	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7088	}
7089
7090	hmR0SvmSetPendingXcptUD(pVCpu);
7091	return VINF_SUCCESS;
7092	}
7093
7094
7095	/**
7096	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7097	*/
7098	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7099	{
7100	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7101
7102	unsigned cbInstr;
7103	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7104	if (fSupportsNextRipSave)
7105	{
7106	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7107	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7108	}
7109	else
7110	{
7111	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7112	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7113	if ( rc == VINF_SUCCESS
7114	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7115	Assert(cbInstr > 0);
7116	else
7117	cbInstr = 0;
7118	}
7119
7120	/** @todo The guest has likely hit a contended spinlock. We might want to
7121	* poke a schedule different guest VCPU. */
7122	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7123	return VINF_EM_RAW_INTERRUPT;
7124	}
7125
7126
7127	/**
7128	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7129	* \#VMEXIT.
7130	*/
7131	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7132	{
7133	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7134	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7135	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7136
7137	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7138	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7139	}
7140
7141
7142	/**
7143	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7144	*/
7145	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7146	{
7147	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7148
7149	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now (almost) ready. */
7150	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7151	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7152
7153	/* Emulate the IRET. We have to execute the IRET before an NMI, but must potentially
7154	* deliver a pending NMI right after. If the IRET faults, an NMI can come before the
7155	* handler executes. Yes, x86 is ugly.
7156	*/
7157	return VINF_EM_RAW_EMULATE_INSTR;
7158	}
7159
7160
7161	/**
7162	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7163	* Conditional \#VMEXIT.
7164	*/
7165	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7166	{
7167	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7168	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7169	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7170
7171	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7172	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7173	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7174	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7175	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7176	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7177
7178	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7179	if (pVM->hmr0.s.fNestedPaging)
7180	{
7181	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7182	if ( !pSvmTransient->fVectoringDoublePF
7183	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7184	{
7185	/* A genuine guest #PF, reflect it to the guest. */
7186	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7187	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7188	uFaultAddress, uErrCode));
7189	}
7190	else
7191	{
7192	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7193	hmR0SvmSetPendingXcptDF(pVCpu);
7194	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7195	}
7196	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7197	return VINF_SUCCESS;
7198	}
7199	#endif
7200
7201	Assert(!pVM->hmr0.s.fNestedPaging);
7202
7203	/*
7204	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7205	*/
7206	if ( pVM->hm.s.fTprPatchingAllowed
7207	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7208	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7209	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7210	&& !CPUMIsGuestInLongModeEx(pCtx)
7211	&& !CPUMGetGuestCPL(pVCpu)
7212	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7213	{
7214	RTGCPHYS GCPhysApicBase;
7215	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7216	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7217
7218	/* Check if the page at the fault-address is the APIC base. */
7219	RTGCPHYS GCPhysPage;
7220	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7221	if ( rc2 == VINF_SUCCESS
7222	&& GCPhysPage == GCPhysApicBase)
7223	{
7224	/* Only attempt to patch the instruction once. */
7225	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7226	if (!pPatch)
7227	return VINF_EM_HM_PATCH_TPR_INSTR;
7228	}
7229	}
7230
7231	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7232	pCtx->rip, uErrCode, pCtx->cr3));
7233
7234	/*
7235	* If it's a vectoring #PF, emulate injecting the original event injection as
7236	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7237	* event injection that caused a #PF. See @bugref{6607}.
7238	*/
7239	if (pSvmTransient->fVectoringPF)
7240	{
7241	Assert(pVCpu->hm.s.Event.fPending);
7242	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7243	}
7244
7245	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7246	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7247
7248	Log4Func(("#PF: rc=%Rrc\n", rc));
7249
7250	if (rc == VINF_SUCCESS)
7251	{
7252	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7253	TRPMResetTrap(pVCpu);
7254	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7255	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7256	return rc;
7257	}
7258
7259	if (rc == VINF_EM_RAW_GUEST_TRAP)
7260	{
7261	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7262
7263	/*
7264	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7265	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7266	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7267	*/
7268	if ( !pSvmTransient->fVectoringDoublePF
7269	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7270	{
7271	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7272	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7273	TRPMResetTrap(pVCpu);
7274
7275	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7276	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7277	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7278	&& CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
7279	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress);
7280	#endif
7281
7282	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7283	}
7284	else
7285	{
7286	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7287	TRPMResetTrap(pVCpu);
7288	hmR0SvmSetPendingXcptDF(pVCpu);
7289	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7290	}
7291
7292	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7293	return VINF_SUCCESS;
7294	}
7295
7296	TRPMResetTrap(pVCpu);
7297	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7298	return rc;
7299	}
7300
7301
7302	/**
7303	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7304	* Conditional \#VMEXIT.
7305	*/
7306	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7307	{
7308	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7309	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7310	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7311
7312	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7313	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7314	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7315
7316	/** @todo if we accumulate more optional stuff here, we ought to combine the
7317	* reading of opcode bytes to avoid doing more than once. */
7318
7319	VBOXSTRICTRC rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7320	if (pVCpu->hm.s.fGIMTrapXcptUD)
7321	{
7322	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7323	uint8_t cbInstr = 0;
7324	rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7325	if (rcStrict == VINF_SUCCESS)
7326	{
7327	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7328	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7329	rcStrict = VINF_SUCCESS;
7330	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7331	}
7332	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7333	rcStrict = VINF_SUCCESS;
7334	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7335	rcStrict = VINF_GIM_R3_HYPERCALL;
7336	else
7337	{
7338	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7339	rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7340	}
7341	}
7342
7343	if (pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
7344	{
7345	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_SS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS
7346	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7347	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
7348	{
7349	/* Ideally, IEM should just handle all these special #UD situations, but
7350	we don't quite trust things to behave optimially when doing that. So,
7351	for now we'll restrict ourselves to a handful of possible sysenter and
7352	sysexit encodings that we filter right here. */
7353	uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
7354	uint8_t cbInstr = pVmcb->ctrl.cbInstrFetched;
7355	uint32_t const uCpl = CPUMGetGuestCPL(pVCpu);
7356	uint8_t const cbMin = uCpl != 0 ? 2 : 1 + 2;
7357	RTGCPTR const GCPtrInstr = pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base;
7358	if (cbInstr < cbMin \|\| cbInstr > SVM_CTRL_GUEST_INSTR_BYTES_MAX)
7359	{
7360	cbInstr = cbMin;
7361	int rc2 = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, GCPtrInstr, cbInstr);
7362	AssertRCStmt(rc2, cbInstr = 0);
7363	}
7364	else
7365	memcpy(abInstr, pVmcb->ctrl.abInstr, cbInstr); /* unlikely */
7366	if ( cbInstr == 0 /* read error */
7367	\|\| (cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x34) /* sysenter */
7368	\|\| ( uCpl == 0
7369	&& ( ( cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x35) /* sysexit */
7370	\|\| ( cbInstr >= 3 && abInstr[1] == 0x0f && abInstr[2] == 0x35 /* rex.w sysexit */
7371	&& (abInstr[0] & (X86_OP_REX_W \| 0xf0)) == X86_OP_REX_W))))
7372	{
7373	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK
7374	\| CPUMCTX_EXTRN_SREG_MASK /* without ES+DS+GS the app will #GP later - go figure */);
7375	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7376	rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), GCPtrInstr, abInstr, cbInstr);
7377	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: rcStrict=%Rrc %04x:%08RX64 %08RX64 %04x:%08RX64\n",
7378	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u,
7379	pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.rsp));
7380	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7381	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK); /** @todo Lazy bird. */
7382	if (rcStrict == VINF_IEM_RAISED_XCPT)
7383	rcStrict = VINF_SUCCESS;
7384	return rcStrict;
7385	}
7386	Log6(("hmR0SvmExitXcptUD: not sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7387	}
7388	else
7389	Log6(("hmR0SvmExitXcptUD: not in long mode at %04x:%llx\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7390	}
7391
7392	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7393	if (RT_FAILURE(rcStrict))
7394	{
7395	hmR0SvmSetPendingXcptUD(pVCpu);
7396	rcStrict = VINF_SUCCESS;
7397	}
7398
7399	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7400	return rcStrict;
7401	}
7402
7403
7404	/**
7405	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7406	* Conditional \#VMEXIT.
7407	*/
7408	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7409	{
7410	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7411	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7412	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7413
7414	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7415	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7416
7417	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7418	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7419
7420	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7421
7422	if (!(pCtx->cr0 & X86_CR0_NE))
7423	{
7424	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7425	PDISSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7426	unsigned cbInstr;
7427	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7428	if (RT_SUCCESS(rc))
7429	{
7430	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7431	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7432	if (RT_SUCCESS(rc))
7433	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7434	}
7435	else
7436	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7437	return rc;
7438	}
7439
7440	hmR0SvmSetPendingXcptMF(pVCpu);
7441	return VINF_SUCCESS;
7442	}
7443
7444
7445	/**
7446	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7447	* \#VMEXIT.
7448	*/
7449	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7450	{
7451	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7452	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7453	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7454	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7455
7456	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7457	{
7458	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7459	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7460	}
7461
7462	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7463
7464	/*
7465	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7466	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7467	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7468	*/
7469	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7470	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7471	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7472	int rc = DBGFTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7473	if (rc == VINF_EM_RAW_GUEST_TRAP)
7474	{
7475	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7476	if (CPUMIsHyperDebugStateActive(pVCpu))
7477	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7478
7479	/* Reflect the exception back to the guest. */
7480	hmR0SvmSetPendingXcptDB(pVCpu);
7481	rc = VINF_SUCCESS;
7482	}
7483
7484	/*
7485	* Update DR6.
7486	*/
7487	if (CPUMIsHyperDebugStateActive(pVCpu))
7488	{
7489	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7490	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7491	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7492	}
7493	else
7494	{
7495	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7496	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7497	}
7498
7499	return rc;
7500	}
7501
7502
7503	/**
7504	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7505	* Conditional \#VMEXIT.
7506	*/
7507	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7508	{
7509	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7510	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7511	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
7512
7513	SVMEVENT Event;
7514	Event.u = 0;
7515	Event.n.u1Valid = 1;
7516	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7517	Event.n.u8Vector = X86_XCPT_AC;
7518	Event.n.u1ErrorCodeValid = 1;
7519	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7520	return VINF_SUCCESS;
7521	}
7522
7523
7524	/**
7525	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7526	* Conditional \#VMEXIT.
7527	*/
7528	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7529	{
7530	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7531	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7532	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7533	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
7534
7535	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7536	int rc = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7537	if (rc == VINF_EM_RAW_GUEST_TRAP)
7538	{
7539	SVMEVENT Event;
7540	Event.u = 0;
7541	Event.n.u1Valid = 1;
7542	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7543	Event.n.u8Vector = X86_XCPT_BP;
7544	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7545	rc = VINF_SUCCESS;
7546	}
7547
7548	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_DBG_BREAKPOINT);
7549	return rc;
7550	}
7551
7552
7553	/**
7554	* Hacks its way around the lovely mesa driver's backdoor accesses.
7555	*
7556	* @sa hmR0VmxHandleMesaDrvGp
7557	*/
7558	static int hmR0SvmHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7559	{
7560	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7561	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7562	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7563	RT_NOREF(pCtx, pVmcb);
7564
7565	/* For now we'll just skip the instruction. */
7566	hmR0SvmAdvanceRip(pVCpu, 1);
7567	return VINF_SUCCESS;
7568	}
7569
7570
7571	/**
7572	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7573	* backdoor logging w/o checking what it is running inside.
7574	*
7575	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7576	* backdoor port and magic numbers loaded in registers.
7577	*
7578	* @returns true if it is, false if it isn't.
7579	* @sa hmR0VmxIsMesaDrvGp
7580	*/
7581	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7582	{
7583	/* Check magic and port. */
7584	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7585	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7586	if (pCtx->dx != UINT32_C(0x5658))
7587	return false;
7588	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7589	return false;
7590
7591	/* Check that it is #GP(0). */
7592	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7593	return false;
7594
7595	/* Flat ring-3 CS. */
7596	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7597	if (pVmcb->guest.u8CPL != 3)
7598	return false;
7599	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7600	return false;
7601
7602	/* 0xed: IN eAX,dx */
7603	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7604	{
7605	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7606	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7607	uint8_t abInstr[1];
7608	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7609	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7610	if (RT_FAILURE(rc))
7611	return false;
7612	if (abInstr[0] != 0xed)
7613	return false;
7614	}
7615	else
7616	{
7617	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7618	if (pVmcb->ctrl.abInstr[0] != 0xed)
7619	return false;
7620	}
7621	return true;
7622	}
7623
7624
7625	/**
7626	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7627	* Conditional \#VMEXIT.
7628	*/
7629	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7630	{
7631	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7632	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7633	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
7634
7635	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7636	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7637
7638	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7639	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7640	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7641	{
7642	SVMEVENT Event;
7643	Event.u = 0;
7644	Event.n.u1Valid = 1;
7645	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7646	Event.n.u8Vector = X86_XCPT_GP;
7647	Event.n.u1ErrorCodeValid = 1;
7648	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7649	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7650	return VINF_SUCCESS;
7651	}
7652	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7653	}
7654
7655
7656	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7657	/**
7658	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7659	*/
7660	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7661	{
7662	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7663	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7664
7665	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7666	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7667	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7668	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7669	Assert(uVector <= X86_XCPT_LAST);
7670	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7671
7672	SVMEVENT Event;
7673	Event.u = 0;
7674	Event.n.u1Valid = 1;
7675	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7676	Event.n.u8Vector = uVector;
7677	switch (uVector)
7678	{
7679	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7680	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7681	case X86_XCPT_DF:
7682	case X86_XCPT_TS:
7683	case X86_XCPT_NP:
7684	case X86_XCPT_SS:
7685	case X86_XCPT_GP:
7686	case X86_XCPT_AC:
7687	{
7688	Event.n.u1ErrorCodeValid = 1;
7689	Event.n.u32ErrorCode = uErrCode;
7690	break;
7691	}
7692	}
7693
7694	#ifdef VBOX_WITH_STATISTICS
7695	switch (uVector)
7696	{
7697	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
7698	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
7699	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
7700	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7701	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
7702	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
7703	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7704	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
7705	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
7706	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
7707	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
7708	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
7709	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
7710	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
7711	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
7712	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
7713	default:
7714	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
7715	break;
7716	}
7717	#endif
7718
7719	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7720	return VINF_SUCCESS;
7721	}
7722	#endif
7723
7724	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7725	/**
7726	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7727	*/
7728	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7729	{
7730	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7731
7732	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7733	Assert(pVmcb);
7734	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7735
7736	VBOXSTRICTRC rcStrict;
7737	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7738	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7739	if (fSupportsNextRipSave)
7740	{
7741	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7742	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7743	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7744	}
7745	else
7746	{
7747	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7748	rcStrict = IEMExecOne(pVCpu);
7749	}
7750
7751	if (rcStrict == VINF_SUCCESS)
7752	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7753	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7754	{
7755	rcStrict = VINF_SUCCESS;
7756	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7757	}
7758	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7759	return rcStrict;
7760	}
7761
7762
7763	/**
7764	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7765	*/
7766	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7767	{
7768	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7769
7770	/*
7771	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7772	* we only intercept STGI when events are pending for GIF to become 1.
7773	*/
7774	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7775	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7776	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7777
7778	VBOXSTRICTRC rcStrict;
7779	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7780	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7781	if (fSupportsNextRipSave)
7782	{
7783	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7784	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7785	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7786	}
7787	else
7788	{
7789	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7790	rcStrict = IEMExecOne(pVCpu);
7791	}
7792
7793	if (rcStrict == VINF_SUCCESS)
7794	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7795	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7796	{
7797	rcStrict = VINF_SUCCESS;
7798	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7799	}
7800	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7801	return rcStrict;
7802	}
7803
7804
7805	/**
7806	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7807	*/
7808	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7809	{
7810	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7811
7812	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7813	Assert(pVmcb);
7814	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7815
7816	VBOXSTRICTRC rcStrict;
7817	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7818	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7819	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7820	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7821	if (fSupportsNextRipSave)
7822	{
7823	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7824	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7825	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7826	}
7827	else
7828	{
7829	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7830	rcStrict = IEMExecOne(pVCpu);
7831	}
7832
7833	if (rcStrict == VINF_SUCCESS)
7834	{
7835	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7836	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7837	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7838	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7839	}
7840	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7841	{
7842	rcStrict = VINF_SUCCESS;
7843	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7844	}
7845	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7846	return rcStrict;
7847	}
7848
7849
7850	/**
7851	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7852	*/
7853	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7854	{
7855	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7856
7857	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7858	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7859
7860	VBOXSTRICTRC rcStrict;
7861	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7862	if (fSupportsNextRipSave)
7863	{
7864	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7865	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7866	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7867	}
7868	else
7869	{
7870	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7871	rcStrict = IEMExecOne(pVCpu);
7872	}
7873
7874	if (rcStrict == VINF_IEM_RAISED_XCPT)
7875	{
7876	rcStrict = VINF_SUCCESS;
7877	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7878	}
7879	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7880	return rcStrict;
7881	}
7882
7883
7884	/**
7885	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7886	*/
7887	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7888	{
7889	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7890
7891	VBOXSTRICTRC rcStrict;
7892	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7893	if (fSupportsNextRipSave)
7894	{
7895	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7896	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7897	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7898	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7899	}
7900	else
7901	{
7902	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7903	rcStrict = IEMExecOne(pVCpu);
7904	}
7905
7906	if (rcStrict == VINF_IEM_RAISED_XCPT)
7907	{
7908	rcStrict = VINF_SUCCESS;
7909	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7910	}
7911	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7912	return rcStrict;
7913	}
7914
7915
7916	/**
7917	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7918	*/
7919	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7920	{
7921	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7922	/* We shall import the entire state here, just in case we enter and continue execution of
7923	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
7924	could lose lose part of CPU state. */
7925	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7926
7927	VBOXSTRICTRC rcStrict;
7928	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7929	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
7930	if (fSupportsNextRipSave)
7931	{
7932	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7933	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7934	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7935	}
7936	else
7937	{
7938	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
7939	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
7940	instruction itself, see @bugref{7243#c126} */
7941	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
7942	}
7943	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
7944
7945	if (rcStrict == VINF_SUCCESS)
7946	{
7947	rcStrict = VINF_SVM_VMRUN;
7948	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
7949	}
7950	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7951	{
7952	rcStrict = VINF_SUCCESS;
7953	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7954	}
7955	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7956	return rcStrict;
7957	}
7958
7959
7960	/**
7961	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7962	* Unconditional \#VMEXIT.
7963	*/
7964	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7965	{
7966	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7967	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7968
7969	if (pVCpu->hm.s.Event.fPending)
7970	{
7971	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7972	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7973	}
7974
7975	hmR0SvmSetPendingXcptDB(pVCpu);
7976	return VINF_SUCCESS;
7977	}
7978
7979
7980	/**
7981	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7982	* Conditional \#VMEXIT.
7983	*/
7984	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7985	{
7986	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7987	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7988
7989	SVMEVENT Event;
7990	Event.u = 0;
7991	Event.n.u1Valid = 1;
7992	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7993	Event.n.u8Vector = X86_XCPT_BP;
7994	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7995	return VINF_SUCCESS;
7996	}
7997	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
7998
7999	/** @} */
8000

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 90379

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