HMSVMR0.cpp@ 92392

Last change on this file since 92392 was 92392, checked in by vboxsync, 3 years ago
VMM: Removed the callring-3 API and some of the associated stuff. bugref:10093
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 319.2 KB

Line
1	/* $Id: HMSVMR0.cpp 92392 2021-11-12 10:39:56Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/em.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#include "HMInternal.h"
36	#include <VBox/vmm/vmcc.h>
37	#include <VBox/err.h>
38	#include "HMSVMR0.h"
39	#include "dtrace/VBoxVMM.h"
40
41	#ifdef DEBUG_ramshankar
42	# define HMSVM_SYNC_FULL_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.aStatExitReason[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60
61	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
62	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
64	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll); \
65	if ((u64ExitCode) == SVM_EXIT_NPF) \
66	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
67	else \
68	STAM_COUNTER_INC(&pVCpu->hm.s.aStatNestedExitReason[(u64ExitCode) & MASK_EXITREASON_STAT]); \
69	} while (0)
70	# endif
71	#else
72	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
73	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
74	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
75	# endif
76	#endif /* !VBOX_WITH_STATISTICS */
77
78	/** If we decide to use a function table approach this can be useful to
79	* switch to a "static DECLCALLBACK(int)". */
80	#define HMSVM_EXIT_DECL static VBOXSTRICTRC
81
82	/**
83	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
84	* guest using hardware-assisted SVM.
85	*
86	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
87	* are swapped and restored across the world-switch and also registers like
88	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
89	* \#VMEXIT.
90	*/
91	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
92	\| CPUMCTX_EXTRN_RFLAGS \
93	\| CPUMCTX_EXTRN_RAX \
94	\| CPUMCTX_EXTRN_RSP \
95	\| CPUMCTX_EXTRN_SREG_MASK \
96	\| CPUMCTX_EXTRN_CR0 \
97	\| CPUMCTX_EXTRN_CR2 \
98	\| CPUMCTX_EXTRN_CR3 \
99	\| CPUMCTX_EXTRN_TABLE_MASK \
100	\| CPUMCTX_EXTRN_DR6 \
101	\| CPUMCTX_EXTRN_DR7 \
102	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
103	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
104	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
105	\| CPUMCTX_EXTRN_HWVIRT \
106	\| CPUMCTX_EXTRN_HM_SVM_MASK)
107
108	/**
109	* Subset of the guest-CPU state that is shared between the guest and host.
110	*/
111	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
112
113	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
114	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
115	do { \
116	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
117	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
118	} while (0)
119
120	/** Assert that the required state bits are fetched. */
121	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
122	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
123	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
124
125	/** Assert that preemption is disabled or covered by thread-context hooks. */
126	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
127	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
128
129	/** Assert that we haven't migrated CPUs when thread-context hooks are not
130	* used. */
131	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
132	\|\| (a_pVCpu)->hmr0.s.idEnteredCpu == RTMpCpuId(), \
133	("Illegal migration! Entered on CPU %u Current %u\n", \
134	(a_pVCpu)->hmr0.s.idEnteredCpu, RTMpCpuId()));
135
136	/** Assert that we're not executing a nested-guest. */
137	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
139	#else
140	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
141	#endif
142
143	/** Assert that we're executing a nested-guest. */
144	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
145	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
146	#else
147	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
148	#endif
149
150	/** Macro for checking and returning from the using function for
151	* \#VMEXIT intercepts that maybe caused during delivering of another
152	* event in the guest. */
153	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
154	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
155	do \
156	{ \
157	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
158	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
159	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
160	else if ( rc == VINF_EM_RESET \
161	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
162	{ \
163	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
164	return IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0); \
165	} \
166	else \
167	return rc; \
168	} while (0)
169	#else
170	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
171	do \
172	{ \
173	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
174	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
175	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
176	else \
177	return rc; \
178	} while (0)
179	#endif
180
181	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
182	* instruction that exited. */
183	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
184	do { \
185	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
186	(a_rc) = VINF_EM_DBG_STEPPED; \
187	} while (0)
188
189	/** Validate segment descriptor granularity bit. */
190	#ifdef VBOX_STRICT
191	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
192	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
193	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
194	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
195	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
196	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
197	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
198	#else
199	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
200	#endif
201
202	/**
203	* Exception bitmap mask for all contributory exceptions.
204	*
205	* Page fault is deliberately excluded here as it's conditional as to whether
206	* it's contributory or benign. Page faults are handled separately.
207	*/
208	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
209	\| RT_BIT(X86_XCPT_DE))
210
211	/**
212	* Mandatory/unconditional guest control intercepts.
213	*
214	* SMIs can and do happen in normal operation. We need not intercept them
215	* while executing the guest (or nested-guest).
216	*/
217	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
218	\| SVM_CTRL_INTERCEPT_NMI \
219	\| SVM_CTRL_INTERCEPT_INIT \
220	\| SVM_CTRL_INTERCEPT_RDPMC \
221	\| SVM_CTRL_INTERCEPT_CPUID \
222	\| SVM_CTRL_INTERCEPT_RSM \
223	\| SVM_CTRL_INTERCEPT_HLT \
224	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
225	\| SVM_CTRL_INTERCEPT_MSR_PROT \
226	\| SVM_CTRL_INTERCEPT_INVLPGA \
227	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
228	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
229	\| SVM_CTRL_INTERCEPT_VMRUN \
230	\| SVM_CTRL_INTERCEPT_SKINIT \
231	\| SVM_CTRL_INTERCEPT_WBINVD \
232	\| SVM_CTRL_INTERCEPT_MONITOR \
233	\| SVM_CTRL_INTERCEPT_MWAIT \
234	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
235	\| SVM_CTRL_INTERCEPT_XSETBV)
236
237	/** @name VMCB Clean Bits.
238	*
239	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
240	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
241	* memory.
242	*
243	* @{ */
244	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
245	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
246	/** I/O permission bitmap, MSR permission bitmap. */
247	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
248	/** ASID. */
249	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
250	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
251	V_INTR_VECTOR. */
252	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
253	/** Nested Paging: Nested CR3 (nCR3), PAT. */
254	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
255	/** Control registers (CR0, CR3, CR4, EFER). */
256	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
257	/** Debug registers (DR6, DR7). */
258	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
259	/** GDT, IDT limit and base. */
260	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
261	/** Segment register: CS, SS, DS, ES limit and base. */
262	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
263	/** CR2.*/
264	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
265	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
266	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
267	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
268	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
269	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
270	/** Mask of all valid VMCB Clean bits. */
271	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
272	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
273	\| HMSVM_VMCB_CLEAN_ASID \
274	\| HMSVM_VMCB_CLEAN_INT_CTRL \
275	\| HMSVM_VMCB_CLEAN_NP \
276	\| HMSVM_VMCB_CLEAN_CRX_EFER \
277	\| HMSVM_VMCB_CLEAN_DRX \
278	\| HMSVM_VMCB_CLEAN_DT \
279	\| HMSVM_VMCB_CLEAN_SEG \
280	\| HMSVM_VMCB_CLEAN_CR2 \
281	\| HMSVM_VMCB_CLEAN_LBR \
282	\| HMSVM_VMCB_CLEAN_AVIC)
283	/** @} */
284
285	/** @name SVM transient.
286	*
287	* A state structure for holding miscellaneous information across AMD-V
288	* VMRUN/\#VMEXIT operation, restored after the transition.
289	*
290	* @{ */
291	typedef struct SVMTRANSIENT
292	{
293	/** The host's rflags/eflags. */
294	RTCCUINTREG fEFlags;
295	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
296	uint64_t u64ExitCode;
297
298	/** The guest's TPR value used for TPR shadowing. */
299	uint8_t u8GuestTpr;
300	/** Alignment. */
301	uint8_t abAlignment0[7];
302
303	/** Pointer to the currently executing VMCB. */
304	PSVMVMCB pVmcb;
305
306	/** Whether we are currently executing a nested-guest. */
307	bool fIsNestedGuest;
308	/** Whether the guest debug state was active at the time of \#VMEXIT. */
309	bool fWasGuestDebugStateActive;
310	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
311	bool fWasHyperDebugStateActive;
312	/** Whether the TSC offset mode needs to be updated. */
313	bool fUpdateTscOffsetting;
314	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
315	bool fRestoreTscAuxMsr;
316	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
317	* contributary exception or a page-fault. */
318	bool fVectoringDoublePF;
319	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
320	* external interrupt or NMI. */
321	bool fVectoringPF;
322	/** Padding. */
323	bool afPadding0;
324	} SVMTRANSIENT;
325	/** Pointer to SVM transient state. */
326	typedef SVMTRANSIENT *PSVMTRANSIENT;
327	/** Pointer to a const SVM transient state. */
328	typedef const SVMTRANSIENT *PCSVMTRANSIENT;
329
330	AssertCompileSizeAlignment(SVMTRANSIENT, sizeof(uint64_t));
331	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
332	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
333	/** @} */
334
335	/**
336	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
337	*/
338	typedef enum SVMMSREXITREAD
339	{
340	/** Reading this MSR causes a \#VMEXIT. */
341	SVMMSREXIT_INTERCEPT_READ = 0xb,
342	/** Reading this MSR does not cause a \#VMEXIT. */
343	SVMMSREXIT_PASSTHRU_READ
344	} SVMMSREXITREAD;
345
346	/**
347	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
348	*/
349	typedef enum SVMMSREXITWRITE
350	{
351	/** Writing to this MSR causes a \#VMEXIT. */
352	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
353	/** Writing to this MSR does not cause a \#VMEXIT. */
354	SVMMSREXIT_PASSTHRU_WRITE
355	} SVMMSREXITWRITE;
356
357	/**
358	* SVM \#VMEXIT handler.
359	*
360	* @returns Strict VBox status code.
361	* @param pVCpu The cross context virtual CPU structure.
362	* @param pSvmTransient Pointer to the SVM-transient structure.
363	*/
364	typedef VBOXSTRICTRC FNSVMEXITHANDLER(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
365
366
367	/*********************************************************************************************************************************
368	* Internal Functions *
369	*********************************************************************************************************************************/
370	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu);
371	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState);
372
373
374	/** @name \#VMEXIT handlers.
375	* @{
376	*/
377	static FNSVMEXITHANDLER hmR0SvmExitIntr;
378	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
379	static FNSVMEXITHANDLER hmR0SvmExitInvd;
380	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
381	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
382	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
383	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
384	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
385	static FNSVMEXITHANDLER hmR0SvmExitHlt;
386	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
387	static FNSVMEXITHANDLER hmR0SvmExitMwait;
388	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
389	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
390	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
391	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
392	static FNSVMEXITHANDLER hmR0SvmExitMsr;
393	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
394	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
395	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
396	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
397	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
398	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
399	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
400	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
401	static FNSVMEXITHANDLER hmR0SvmExitPause;
402	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
403	static FNSVMEXITHANDLER hmR0SvmExitIret;
404	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
405	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
406	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
407	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
408	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
409	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
410	static FNSVMEXITHANDLER hmR0SvmExitXcptGP;
411	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
412	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
413	#endif
414	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
415	static FNSVMEXITHANDLER hmR0SvmExitClgi;
416	static FNSVMEXITHANDLER hmR0SvmExitStgi;
417	static FNSVMEXITHANDLER hmR0SvmExitVmload;
418	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
419	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
420	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
421	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
422	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
423	#endif
424	/** @} */
425
426	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
427	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
428	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient);
429	#endif
430
431
432	/*********************************************************************************************************************************
433	* Global Variables *
434	*********************************************************************************************************************************/
435	/** Ring-0 memory object for the IO bitmap. */
436	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
437	/** Physical address of the IO bitmap. */
438	static RTHCPHYS g_HCPhysIOBitmap;
439	/** Pointer to the IO bitmap. */
440	static R0PTRTYPE(void *) g_pvIOBitmap;
441
442	#ifdef VBOX_STRICT
443	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
444	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
445	# define HMSVM_LOG_CS RT_BIT_32(2)
446	# define HMSVM_LOG_SS RT_BIT_32(3)
447	# define HMSVM_LOG_FS RT_BIT_32(4)
448	# define HMSVM_LOG_GS RT_BIT_32(5)
449	# define HMSVM_LOG_LBR RT_BIT_32(6)
450	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
451	\| HMSVM_LOG_CR_REGS \
452	\| HMSVM_LOG_CS \
453	\| HMSVM_LOG_SS \
454	\| HMSVM_LOG_FS \
455	\| HMSVM_LOG_GS \
456	\| HMSVM_LOG_LBR)
457
458	/**
459	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
460	*
461	* @param pVCpu The cross context virtual CPU structure.
462	* @param pVmcb Pointer to the VM control block.
463	* @param pszPrefix Log prefix.
464	* @param fFlags Log flags, see HMSVM_LOG_XXX.
465	* @param uVerbose The verbosity level, currently unused.
466	*/
467	static void hmR0SvmLogState(PVMCPUCC pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
468	{
469	RT_NOREF2(pVCpu, uVerbose);
470	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
471
472	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
473	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
474
475	if (fFlags & HMSVM_LOG_RBP_RSP)
476	{
477	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
478	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
479	}
480
481	if (fFlags & HMSVM_LOG_CR_REGS)
482	{
483	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
484	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
485	}
486
487	if (fFlags & HMSVM_LOG_CS)
488	{
489	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
490	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
491	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
492	}
493	if (fFlags & HMSVM_LOG_SS)
494	{
495	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
496	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
497	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
498	}
499	if (fFlags & HMSVM_LOG_FS)
500	{
501	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
502	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
503	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
504	}
505	if (fFlags & HMSVM_LOG_GS)
506	{
507	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
508	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
509	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
510	}
511
512	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
513	if (fFlags & HMSVM_LOG_LBR)
514	{
515	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
516	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
517	}
518	NOREF(pszPrefix); NOREF(pVmcbGuest); NOREF(pCtx);
519	}
520	#endif /* VBOX_STRICT */
521
522
523	/**
524	* Sets up and activates AMD-V on the current CPU.
525	*
526	* @returns VBox status code.
527	* @param pHostCpu The HM physical-CPU structure.
528	* @param pVM The cross context VM structure. Can be
529	* NULL after a resume!
530	* @param pvCpuPage Pointer to the global CPU page.
531	* @param HCPhysCpuPage Physical address of the global CPU page.
532	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
533	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs (currently
534	* unused).
535	*/
536	VMMR0DECL(int) SVMR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
537	PCSUPHWVIRTMSRS pHwvirtMsrs)
538	{
539	Assert(!fEnabledByHost);
540	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
541	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
542	Assert(pvCpuPage); NOREF(pvCpuPage);
543	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
544
545	RT_NOREF2(fEnabledByHost, pHwvirtMsrs);
546
547	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
549
550	/*
551	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
552	*/
553	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
554	if (u64HostEfer & MSR_K6_EFER_SVME)
555	{
556	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
557	if ( pVM
558	&& pVM->hm.s.svm.fIgnoreInUseError)
559	pHostCpu->fIgnoreAMDVInUseError = true;
560
561	if (!pHostCpu->fIgnoreAMDVInUseError)
562	{
563	ASMSetFlags(fEFlags);
564	return VERR_SVM_IN_USE;
565	}
566	}
567
568	/* Turn on AMD-V in the EFER MSR. */
569	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
570
571	/* Write the physical page address where the CPU will store the host state while executing the VM. */
572	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
573
574	/* Restore interrupts. */
575	ASMSetFlags(fEFlags);
576
577	/*
578	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
579	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
580	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
581	* entirely with before executing any guest code.
582	*/
583	pHostCpu->fFlushAsidBeforeUse = true;
584
585	/*
586	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
587	*/
588	++pHostCpu->cTlbFlushes;
589
590	return VINF_SUCCESS;
591	}
592
593
594	/**
595	* Deactivates AMD-V on the current CPU.
596	*
597	* @returns VBox status code.
598	* @param pHostCpu The HM physical-CPU structure.
599	* @param pvCpuPage Pointer to the global CPU page.
600	* @param HCPhysCpuPage Physical address of the global CPU page.
601	*/
602	VMMR0DECL(int) SVMR0DisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
603	{
604	RT_NOREF1(pHostCpu);
605	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
606	AssertReturn( HCPhysCpuPage
607	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
608	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
609
610	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
611	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
612
613	/* Turn off AMD-V in the EFER MSR. */
614	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
615	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
616
617	/* Invalidate host state physical address. */
618	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
619
620	/* Restore interrupts. */
621	ASMSetFlags(fEFlags);
622
623	return VINF_SUCCESS;
624	}
625
626
627	/**
628	* Does global AMD-V initialization (called during module initialization).
629	*
630	* @returns VBox status code.
631	*/
632	VMMR0DECL(int) SVMR0GlobalInit(void)
633	{
634	/*
635	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
636	* intercept all IO accesses, it's done once globally here instead of per-VM.
637	*/
638	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
639	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
640	if (RT_FAILURE(rc))
641	return rc;
642
643	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
644	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
645
646	/* Set all bits to intercept all IO accesses. */
647	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* Does global AMD-V termination (called during module termination).
655	*/
656	VMMR0DECL(void) SVMR0GlobalTerm(void)
657	{
658	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
661	g_pvIOBitmap = NULL;
662	g_HCPhysIOBitmap = 0;
663	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666
667
668	/**
669	* Frees any allocated per-VCPU structures for a VM.
670	*
671	* @param pVM The cross context VM structure.
672	*/
673	DECLINLINE(void) hmR0SvmFreeStructs(PVMCC pVM)
674	{
675	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
676	{
677	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
678	AssertPtr(pVCpu);
679
680	if (pVCpu->hmr0.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
681	{
682	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcbHost, false);
683	pVCpu->hmr0.s.svm.HCPhysVmcbHost = 0;
684	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
685	}
686
687	if (pVCpu->hmr0.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
688	{
689	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjVmcb, false);
690	pVCpu->hmr0.s.svm.pVmcb = NULL;
691	pVCpu->hmr0.s.svm.HCPhysVmcb = 0;
692	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
693	}
694
695	if (pVCpu->hmr0.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
696	{
697	RTR0MemObjFree(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, false);
698	pVCpu->hmr0.s.svm.pvMsrBitmap = NULL;
699	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = 0;
700	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
701	}
702	}
703	}
704
705
706	/**
707	* Sets pfnVMRun to the best suited variant.
708	*
709	* This must be called whenever anything changes relative to the SVMR0VMRun
710	* variant selection:
711	* - pVCpu->hm.s.fLoadSaveGuestXcr0
712	* - CPUMCTX_WSF_IBPB_ENTRY in pVCpu->cpum.GstCtx.fWorldSwitcher
713	* - CPUMCTX_WSF_IBPB_EXIT in pVCpu->cpum.GstCtx.fWorldSwitcher
714	* - Perhaps: CPUMIsGuestFPUStateActive() (windows only)
715	* - Perhaps: CPUMCTX.fXStateMask (windows only)
716	*
717	* We currently ASSUME that neither CPUMCTX_WSF_IBPB_ENTRY nor
718	* CPUMCTX_WSF_IBPB_EXIT cannot be changed at runtime.
719	*/
720	static void hmR0SvmUpdateVmRunFunction(PVMCPUCC pVCpu)
721	{
722	static const struct CLANGWORKAROUND { PFNHMSVMVMRUN pfn; } s_aHmR0SvmVmRunFunctions[] =
723	{
724	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit },
725	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit },
726	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit },
727	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit },
728	{ hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit },
729	{ hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit },
730	{ hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit },
731	{ hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit },
732	};
733	uintptr_t const idx = (pVCpu->hmr0.s.fLoadSaveGuestXcr0 ? 1 : 0)
734	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_ENTRY ? 2 : 0)
735	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_EXIT ? 4 : 0);
736	PFNHMSVMVMRUN const pfnVMRun = s_aHmR0SvmVmRunFunctions[idx].pfn;
737	if (pVCpu->hmr0.s.svm.pfnVMRun != pfnVMRun)
738	pVCpu->hmr0.s.svm.pfnVMRun = pfnVMRun;
739	}
740
741
742	/**
743	* Selector FNHMSVMVMRUN implementation.
744	*/
745	static DECLCALLBACK(int) hmR0SvmVMRunSelector(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB)
746	{
747	hmR0SvmUpdateVmRunFunction(pVCpu);
748	return pVCpu->hmr0.s.svm.pfnVMRun(pVM, pVCpu, HCPhysVMCB);
749	}
750
751
752	/**
753	* Does per-VM AMD-V initialization.
754	*
755	* @returns VBox status code.
756	* @param pVM The cross context VM structure.
757	*/
758	VMMR0DECL(int) SVMR0InitVM(PVMCC pVM)
759	{
760	int rc = VERR_INTERNAL_ERROR_5;
761
762	/*
763	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
764	*/
765	uint32_t u32Family;
766	uint32_t u32Model;
767	uint32_t u32Stepping;
768	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
769	{
770	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
771	pVM->hmr0.s.svm.fAlwaysFlushTLB = true;
772	}
773
774	/*
775	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
776	*/
777	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
778	{
779	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
780	pVCpu->hmr0.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
781	pVCpu->hmr0.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
782	pVCpu->hmr0.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
783	}
784
785	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
786	{
787	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
788
789	/*
790	* Initialize the hardware-assisted SVM guest-execution handler.
791	* We now use a single handler for both 32-bit and 64-bit guests, see @bugref{6208#c73}.
792	*/
793	pVCpu->hmr0.s.svm.pfnVMRun = hmR0SvmVMRunSelector;
794
795	/*
796	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
797	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
798	*/
799	/** @todo Does this need to be below 4G? */
800	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
801	if (RT_FAILURE(rc))
802	goto failure_cleanup;
803
804	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcbHost);
805	pVCpu->hmr0.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcbHost, 0 /* iPage */);
806	Assert(pVCpu->hmr0.s.svm.HCPhysVmcbHost < _4G);
807	ASMMemZeroPage(pvVmcbHost);
808
809	/*
810	* Allocate one page for the guest-state VMCB.
811	*/
812	/** @todo Does this need to be below 4G? */
813	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
814	if (RT_FAILURE(rc))
815	goto failure_cleanup;
816
817	pVCpu->hmr0.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjVmcb);
818	pVCpu->hmr0.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjVmcb, 0 /* iPage */);
819	Assert(pVCpu->hmr0.s.svm.HCPhysVmcb < _4G);
820	ASMMemZeroPage(pVCpu->hmr0.s.svm.pVmcb);
821
822	/*
823	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
824	* SVM to not require one.
825	*/
826	/** @todo Does this need to be below 4G? */
827	rc = RTR0MemObjAllocCont(&pVCpu->hmr0.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
828	false /* fExecutable */);
829	if (RT_FAILURE(rc))
830	goto failure_cleanup;
831
832	pVCpu->hmr0.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hmr0.s.svm.hMemObjMsrBitmap);
833	pVCpu->hmr0.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hmr0.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
834	/* Set all bits to intercept all MSR accesses (changed later on). */
835	ASMMemFill32(pVCpu->hmr0.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
836	}
837
838	return VINF_SUCCESS;
839
840	failure_cleanup:
841	hmR0SvmFreeStructs(pVM);
842	return rc;
843	}
844
845
846	/**
847	* Does per-VM AMD-V termination.
848	*
849	* @returns VBox status code.
850	* @param pVM The cross context VM structure.
851	*/
852	VMMR0DECL(int) SVMR0TermVM(PVMCC pVM)
853	{
854	hmR0SvmFreeStructs(pVM);
855	return VINF_SUCCESS;
856	}
857
858
859	/**
860	* Returns whether the VMCB Clean Bits feature is supported.
861	*
862	* @returns @c true if supported, @c false otherwise.
863	* @param pVCpu The cross context virtual CPU structure.
864	* @param fIsNestedGuest Whether we are currently executing the nested-guest.
865	*/
866	DECL_FORCE_INLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPUCC pVCpu, bool fIsNestedGuest)
867	{
868	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
869	bool const fHostVmcbCleanBits = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
870	if (!fIsNestedGuest)
871	return fHostVmcbCleanBits;
872	return fHostVmcbCleanBits && pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
873	}
874
875
876	/**
877	* Returns whether the decode assists feature is supported.
878	*
879	* @returns @c true if supported, @c false otherwise.
880	* @param pVCpu The cross context virtual CPU structure.
881	*/
882	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPUCC pVCpu)
883	{
884	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
885	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
886	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
887	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
888	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
889	#endif
890	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
891	}
892
893
894	/**
895	* Returns whether the NRIP_SAVE feature is supported.
896	*
897	* @returns @c true if supported, @c false otherwise.
898	* @param pVCpu The cross context virtual CPU structure.
899	*/
900	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPUCC pVCpu)
901	{
902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
903	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
904	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
905	return (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
906	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
907	#endif
908	return RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
909	}
910
911
912	/**
913	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
914	*
915	* @param pVCpu The cross context virtual CPU structure.
916	* @param pbMsrBitmap Pointer to the MSR bitmap.
917	* @param idMsr The MSR for which the permissions are being set.
918	* @param enmRead MSR read permissions.
919	* @param enmWrite MSR write permissions.
920	*
921	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
922	* caller needs to take care of this.
923	*/
924	static void hmR0SvmSetMsrPermission(PVMCPUCC pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
925	SVMMSREXITWRITE enmWrite)
926	{
927	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
928	uint16_t offMsrpm;
929	uint8_t uMsrpmBit;
930	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
931	AssertRC(rc);
932
933	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
934	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
935
936	pbMsrBitmap += offMsrpm;
937	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
938	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
939	else
940	{
941	if (!fInNestedGuestMode)
942	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
943	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
944	else
945	{
946	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
947	if (!(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap[offMsrpm] & RT_BIT(uMsrpmBit)))
948	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
949	else
950	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
951	}
952	#endif
953	}
954
955	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
956	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
957	else
958	{
959	if (!fInNestedGuestMode)
960	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
961	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
962	else
963	{
964	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
965	if (!(pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap[offMsrpm] & RT_BIT(uMsrpmBit + 1)))
966	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
967	else
968	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
969	}
970	#endif
971	}
972	}
973
974
975	/**
976	* Sets up AMD-V for the specified VM.
977	* This function is only called once per-VM during initalization.
978	*
979	* @returns VBox status code.
980	* @param pVM The cross context VM structure.
981	*/
982	VMMR0DECL(int) SVMR0SetupVM(PVMCC pVM)
983	{
984	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
985	AssertReturn(pVM, VERR_INVALID_PARAMETER);
986
987	/*
988	* Validate and copy over some parameters.
989	*/
990	AssertReturn(pVM->hm.s.svm.fSupported, VERR_INCOMPATIBLE_CONFIG);
991	bool const fNestedPaging = pVM->hm.s.fNestedPagingCfg;
992	AssertReturn(!fNestedPaging \|\| (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING), VERR_INCOMPATIBLE_CONFIG);
993	pVM->hmr0.s.fNestedPaging = fNestedPaging;
994	pVM->hmr0.s.fAllow64BitGuests = pVM->hm.s.fAllow64BitGuestsCfg;
995
996	/*
997	* Determin some configuration parameters.
998	*/
999	bool const fPauseFilter = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
1000	bool const fPauseFilterThreshold = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
1001	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
1002
1003	bool const fLbrVirt = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
1004	bool const fUseLbrVirt = fLbrVirt && pVM->hm.s.svm.fLbrVirt; /** @todo IEM implementation etc. */
1005
1006	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1007	bool const fVirtVmsaveVmload = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
1008	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && fNestedPaging;
1009
1010	bool const fVGif = RT_BOOL(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF);
1011	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
1012	#endif
1013
1014	PVMCPUCC pVCpu0 = VMCC_GET_CPU_0(pVM);
1015	PSVMVMCB pVmcb0 = pVCpu0->hmr0.s.svm.pVmcb;
1016	AssertMsgReturn(RT_VALID_PTR(pVmcb0), ("Invalid pVmcb (%p) for vcpu[0]\n", pVmcb0), VERR_SVM_INVALID_PVMCB);
1017	PSVMVMCBCTRL pVmcbCtrl0 = &pVmcb0->ctrl;
1018
1019	/* Always trap #AC for reasons of security. */
1020	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
1021
1022	/* Always trap #DB for reasons of security. */
1023	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
1024
1025	/* Trap exceptions unconditionally (debug purposes). */
1026	#ifdef HMSVM_ALWAYS_TRAP_PF
1027	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_PF);
1028	#endif
1029	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1030	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
1031	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_BP)
1032	\| RT_BIT_32(X86_XCPT_DE)
1033	\| RT_BIT_32(X86_XCPT_NM)
1034	\| RT_BIT_32(X86_XCPT_UD)
1035	\| RT_BIT_32(X86_XCPT_NP)
1036	\| RT_BIT_32(X86_XCPT_SS)
1037	\| RT_BIT_32(X86_XCPT_GP)
1038	\| RT_BIT_32(X86_XCPT_PF)
1039	\| RT_BIT_32(X86_XCPT_MF)
1040	;
1041	#endif
1042
1043	/* Apply the exceptions intercepts needed by the GIM provider. */
1044	if (pVCpu0->hm.s.fGIMTrapXcptUD \|\| pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1045	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1046
1047	/* The mesa 3d driver hack needs #GP. */
1048	if (pVCpu0->hm.s.fTrapXcptGpForLovelyMesaDrv)
1049	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_GP);
1050
1051	/* Set up unconditional intercepts and conditions. */
1052	pVmcbCtrl0->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
1053	\| SVM_CTRL_INTERCEPT_VMMCALL
1054	\| SVM_CTRL_INTERCEPT_VMSAVE
1055	\| SVM_CTRL_INTERCEPT_VMLOAD
1056	\| SVM_CTRL_INTERCEPT_CLGI
1057	\| SVM_CTRL_INTERCEPT_STGI;
1058
1059	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1060	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1061	#endif
1062
1063	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1064	if (pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm)
1065	{
1066	/* Virtualized VMSAVE/VMLOAD. */
1067	if (fUseVirtVmsaveVmload)
1068	{
1069	pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload = 1;
1070	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_VMSAVE
1071	\| SVM_CTRL_INTERCEPT_VMLOAD);
1072	}
1073	else
1074	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1075
1076	/* Virtual GIF. */
1077	if (fUseVGif)
1078	{
1079	pVmcbCtrl0->IntCtrl.n.u1VGifEnable = 1;
1080	pVmcbCtrl0->u64InterceptCtrl &= ~( SVM_CTRL_INTERCEPT_CLGI
1081	\| SVM_CTRL_INTERCEPT_STGI);
1082	}
1083	else
1084	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1085	}
1086	else
1087	#endif
1088	{
1089	Assert(!pVCpu0->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvm);
1090	Assert(!pVmcbCtrl0->LbrVirt.n.u1VirtVmsaveVmload);
1091	Assert(!pVmcbCtrl0->IntCtrl.n.u1VGifEnable);
1092	}
1093
1094	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1095	pVmcbCtrl0->u16InterceptWrCRx = RT_BIT(4);
1096
1097	/* Intercept all DRx reads and writes by default. Changed later on. */
1098	pVmcbCtrl0->u16InterceptRdDRx = 0xffff;
1099	pVmcbCtrl0->u16InterceptWrDRx = 0xffff;
1100
1101	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1102	pVmcbCtrl0->IntCtrl.n.u1VIntrMasking = 1;
1103
1104	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1105	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1106	pVmcbCtrl0->IntCtrl.n.u1IgnoreTPR = 1;
1107
1108	/* Set the IO permission bitmap physical addresses. */
1109	pVmcbCtrl0->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1110
1111	/* LBR virtualization. */
1112	pVmcbCtrl0->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1113
1114	/* The host ASID MBZ, for the guest start with 1. */
1115	pVmcbCtrl0->TLBCtrl.n.u32ASID = 1;
1116
1117	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1118	pVmcbCtrl0->NestedPagingCtrl.n.u1NestedPaging = fNestedPaging;
1119
1120	/* Without Nested Paging, we need additionally intercepts. */
1121	if (!fNestedPaging)
1122	{
1123	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1124	pVmcbCtrl0->u16InterceptRdCRx \|= RT_BIT(3);
1125	pVmcbCtrl0->u16InterceptWrCRx \|= RT_BIT(3);
1126
1127	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1128	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1129	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1130
1131	/* Page faults must be intercepted to implement shadow paging. */
1132	pVmcbCtrl0->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1133	}
1134
1135	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1136	if (fUsePauseFilter)
1137	{
1138	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1139	pVmcbCtrl0->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1140	if (fPauseFilterThreshold)
1141	pVmcbCtrl0->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1142	pVmcbCtrl0->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1143	}
1144
1145	/*
1146	* Setup the MSR permission bitmap.
1147	* The following MSRs are saved/restored automatically during the world-switch.
1148	* Don't intercept guest read/write accesses to these MSRs.
1149	*/
1150	uint8_t pbMsrBitmap0 = (uint8_t )pVCpu0->hmr0.s.svm.pvMsrBitmap;
1151	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1152	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1153	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1154	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1155	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1156	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1157	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1158	if (!pVCpu0->hm.s.svm.fEmulateLongModeSysEnterExit)
1159	{
1160	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1161	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1162	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1163	}
1164	else
1165	{
1166	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_CS, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1167	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1168	hmR0SvmSetMsrPermission(pVCpu0, pbMsrBitmap0, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
1169	}
1170	pVmcbCtrl0->u64MSRPMPhysAddr = pVCpu0->hmr0.s.svm.HCPhysMsrBitmap;
1171
1172	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1173	Assert(pVmcbCtrl0->u32VmcbCleanBits == 0);
1174
1175	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
1176	{
1177	PVMCPUCC pVCpuCur = VMCC_GET_CPU(pVM, idCpu);
1178	PSVMVMCB pVmcbCur = pVCpuCur->hmr0.s.svm.pVmcb;
1179	AssertMsgReturn(RT_VALID_PTR(pVmcbCur), ("Invalid pVmcb (%p) for vcpu[%u]\n", pVmcbCur, idCpu), VERR_SVM_INVALID_PVMCB);
1180	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1181
1182	/* Copy the VMCB control area. */
1183	memcpy(pVmcbCtrlCur, pVmcbCtrl0, sizeof(*pVmcbCtrlCur));
1184
1185	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1186	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hmr0.s.svm.pvMsrBitmap;
1187	memcpy(pbMsrBitmapCur, pbMsrBitmap0, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1188	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hmr0.s.svm.HCPhysMsrBitmap;
1189
1190	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1191	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1192
1193	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1194	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu0->hm.s.fGIMTrapXcptUD);
1195	}
1196
1197	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1198	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1199	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1200	#else
1201	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1202	#endif
1203	return VINF_SUCCESS;
1204	}
1205
1206
1207	/**
1208	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1209	*
1210	* @returns Pointer to the current context VMCB.
1211	* @param pVCpu The cross context virtual CPU structure.
1212	*/
1213	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPUCC pVCpu)
1214	{
1215	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1216	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1217	return &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb;
1218	#endif
1219	return pVCpu->hmr0.s.svm.pVmcb;
1220	}
1221
1222
1223	/**
1224	* Gets a pointer to the nested-guest VMCB cache.
1225	*
1226	* @returns Pointer to the nested-guest VMCB cache.
1227	* @param pVCpu The cross context virtual CPU structure.
1228	*/
1229	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPUCC pVCpu)
1230	{
1231	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1232	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1233	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1234	#else
1235	RT_NOREF(pVCpu);
1236	return NULL;
1237	#endif
1238	}
1239
1240
1241	/**
1242	* Invalidates a guest page by guest virtual address.
1243	*
1244	* @returns VBox status code.
1245	* @param pVCpu The cross context virtual CPU structure.
1246	* @param GCVirt Guest virtual address of the page to invalidate.
1247	*/
1248	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1249	{
1250	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1251
1252	bool const fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH) \|\| pVCpu->CTX_SUFF(pVM)->hmr0.s.svm.fAlwaysFlushTLB;
1253
1254	/* Skip it if a TLB flush is already pending. */
1255	if (!fFlushPending)
1256	{
1257	Log4Func(("%#RGv\n", GCVirt));
1258
1259	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1260	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1261
1262	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1263	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1264	}
1265	return VINF_SUCCESS;
1266	}
1267
1268
1269	/**
1270	* Flushes the appropriate tagged-TLB entries.
1271	*
1272	* @param pHostCpu The HM physical-CPU structure.
1273	* @param pVCpu The cross context virtual CPU structure.
1274	* @param pVmcb Pointer to the VM control block.
1275	*/
1276	static void hmR0SvmFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1277	{
1278	/*
1279	* Force a TLB flush for the first world switch if the current CPU differs from the one
1280	* we ran on last. This can happen both for start & resume due to long jumps back to
1281	* ring-3.
1282	*
1283	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1284	* correlation between it and the physical CPU.
1285	*
1286	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1287	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1288	*/
1289	bool fNewAsid = false;
1290	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1291	if ( pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
1292	\|\| pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes
1293	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1294	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1295	#endif
1296	)
1297	{
1298	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1299	pVCpu->hmr0.s.fForceTLBFlush = true;
1300	fNewAsid = true;
1301	}
1302
1303	/* Set TLB flush state as checked until we return from the world switch. */
1304	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1305
1306	/* Check for explicit TLB flushes. */
1307	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1308	{
1309	pVCpu->hmr0.s.fForceTLBFlush = true;
1310	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1311	}
1312
1313	/*
1314	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1315	* This Host CPU requirement takes precedence.
1316	*/
1317	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1318	if (pVM->hmr0.s.svm.fAlwaysFlushTLB)
1319	{
1320	pHostCpu->uCurrentAsid = 1;
1321	pVCpu->hmr0.s.uCurrentAsid = 1;
1322	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1323	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1324	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1325
1326	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1327	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1328	}
1329	else
1330	{
1331	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1332	if (pVCpu->hmr0.s.fForceTLBFlush)
1333	{
1334	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1335	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1336
1337	if (fNewAsid)
1338	{
1339	++pHostCpu->uCurrentAsid;
1340
1341	bool fHitASIDLimit = false;
1342	if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid)
1343	{
1344	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1345	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1346	fHitASIDLimit = true;
1347	}
1348
1349	if ( fHitASIDLimit
1350	\|\| pHostCpu->fFlushAsidBeforeUse)
1351	{
1352	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1353	pHostCpu->fFlushAsidBeforeUse = false;
1354	}
1355
1356	pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1357	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
1358	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1359	}
1360	else
1361	{
1362	if (g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1363	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1364	else
1365	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1366	}
1367
1368	pVCpu->hmr0.s.fForceTLBFlush = false;
1369	}
1370	}
1371
1372	/* Update VMCB with the ASID. */
1373	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hmr0.s.uCurrentAsid)
1374	{
1375	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hmr0.s.uCurrentAsid;
1376	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1377	}
1378
1379	AssertMsg(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu,
1380	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hmr0.s.idLastCpu, pHostCpu->idCpu));
1381	AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1382	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1383	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid,
1384	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1385	AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid,
1386	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
1387
1388	#ifdef VBOX_WITH_STATISTICS
1389	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1390	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1391	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1392	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1393	{
1394	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1395	}
1396	else
1397	{
1398	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1399	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1400	}
1401	#endif
1402	}
1403
1404
1405	/**
1406	* Sets an exception intercept in the specified VMCB.
1407	*
1408	* @param pVmcb Pointer to the VM control block.
1409	* @param uXcpt The exception (X86_XCPT_*).
1410	*/
1411	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1412	{
1413	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1414	{
1415	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1416	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1417	}
1418	}
1419
1420
1421	/**
1422	* Clears an exception intercept in the specified VMCB.
1423	*
1424	* @param pVCpu The cross context virtual CPU structure.
1425	* @param pVmcb Pointer to the VM control block.
1426	* @param uXcpt The exception (X86_XCPT_*).
1427	*
1428	* @remarks This takes into account if we're executing a nested-guest and only
1429	* removes the exception intercept if both the guest -and- nested-guest
1430	* are not intercepting it.
1431	*/
1432	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1433	{
1434	Assert(uXcpt != X86_XCPT_DB);
1435	Assert(uXcpt != X86_XCPT_AC);
1436	Assert(uXcpt != X86_XCPT_GP);
1437	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1438	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1439	{
1440	bool fRemove = true;
1441	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1442	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1443	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1444	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1445	{
1446	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1447	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1448	}
1449	# else
1450	RT_NOREF(pVCpu);
1451	# endif
1452	if (fRemove)
1453	{
1454	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1455	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1456	}
1457	}
1458	#else
1459	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1460	#endif
1461	}
1462
1463
1464	/**
1465	* Sets a control intercept in the specified VMCB.
1466	*
1467	* @param pVmcb Pointer to the VM control block.
1468	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1469	*/
1470	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1471	{
1472	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1473	{
1474	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1475	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1476	}
1477	}
1478
1479
1480	/**
1481	* Clears a control intercept in the specified VMCB.
1482	*
1483	* @returns @c true if the intercept is still set, @c false otherwise.
1484	* @param pVCpu The cross context virtual CPU structure.
1485	* @param pVmcb Pointer to the VM control block.
1486	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1487	*
1488	* @remarks This takes into account if we're executing a nested-guest and only
1489	* removes the control intercept if both the guest -and- nested-guest
1490	* are not intercepting it.
1491	*/
1492	static bool hmR0SvmClearCtrlIntercept(PVMCPUCC pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1493	{
1494	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1495	{
1496	bool fRemove = true;
1497	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1498	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1499	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1500	{
1501	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1502	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1503	}
1504	#else
1505	RT_NOREF(pVCpu);
1506	#endif
1507	if (fRemove)
1508	{
1509	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1510	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1511	}
1512	}
1513
1514	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1515	}
1516
1517
1518	/**
1519	* Exports the guest (or nested-guest) CR0 into the VMCB.
1520	*
1521	* @param pVCpu The cross context virtual CPU structure.
1522	* @param pVmcb Pointer to the VM control block.
1523	*
1524	* @remarks This assumes we always pre-load the guest FPU.
1525	* @remarks No-long-jump zone!!!
1526	*/
1527	static void hmR0SvmExportGuestCR0(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1528	{
1529	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1530
1531	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1532	uint64_t const uGuestCr0 = pCtx->cr0;
1533	uint64_t uShadowCr0 = uGuestCr0;
1534
1535	/* Always enable caching. */
1536	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1537
1538	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1539	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1540	{
1541	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1542	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1543	}
1544
1545	/*
1546	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1547	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1548	* see @bugref{7243#c103}.
1549	*/
1550	if (!(uGuestCr0 & X86_CR0_NE))
1551	{
1552	uShadowCr0 \|= X86_CR0_NE;
1553	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1554	}
1555	else
1556	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1557
1558	/*
1559	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1560	*
1561	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1562	* see @bugref{6944}.
1563	*
1564	* We also don't ever want to honor weird things like cache disable from the guest.
1565	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1566	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1567	*/
1568	if (uShadowCr0 == uGuestCr0)
1569	{
1570	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1571	{
1572	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1573	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1574	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1575	}
1576	else
1577	{
1578	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1579	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1580	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1581	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1582	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1583	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1584	}
1585	}
1586	else
1587	{
1588	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1589	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1590	}
1591	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1592
1593	Assert(!RT_HI_U32(uShadowCr0));
1594	if (pVmcb->guest.u64CR0 != uShadowCr0)
1595	{
1596	pVmcb->guest.u64CR0 = uShadowCr0;
1597	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1598	}
1599	}
1600
1601
1602	/**
1603	* Exports the guest (or nested-guest) CR3 into the VMCB.
1604	*
1605	* @param pVCpu The cross context virtual CPU structure.
1606	* @param pVmcb Pointer to the VM control block.
1607	*
1608	* @remarks No-long-jump zone!!!
1609	*/
1610	static void hmR0SvmExportGuestCR3(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1611	{
1612	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1613
1614	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1615	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1616	if (pVM->hmr0.s.fNestedPaging)
1617	{
1618	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetHyperCR3(pVCpu);
1619	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1620	pVmcb->guest.u64CR3 = pCtx->cr3;
1621	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1622	}
1623	else
1624	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1625
1626	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1627	}
1628
1629
1630	/**
1631	* Exports the guest (or nested-guest) CR4 into the VMCB.
1632	*
1633	* @param pVCpu The cross context virtual CPU structure.
1634	* @param pVmcb Pointer to the VM control block.
1635	*
1636	* @remarks No-long-jump zone!!!
1637	*/
1638	static int hmR0SvmExportGuestCR4(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1639	{
1640	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1641
1642	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1643	uint64_t uShadowCr4 = pCtx->cr4;
1644	if (!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
1645	{
1646	switch (pVCpu->hm.s.enmShadowMode)
1647	{
1648	case PGMMODE_REAL:
1649	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1650	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1651
1652	case PGMMODE_32_BIT: /* 32-bit paging. */
1653	uShadowCr4 &= ~X86_CR4_PAE;
1654	break;
1655
1656	case PGMMODE_PAE: /* PAE paging. */
1657	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1658	/** Must use PAE paging as we could use physical memory > 4 GB */
1659	uShadowCr4 \|= X86_CR4_PAE;
1660	break;
1661
1662	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1663	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1664	#ifdef VBOX_WITH_64_BITS_GUESTS
1665	break;
1666	#else
1667	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1668	#endif
1669
1670	default: /* shut up gcc */
1671	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1672	}
1673	}
1674
1675	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1676	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1677	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
1678	{
1679	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
1680	hmR0SvmUpdateVmRunFunction(pVCpu);
1681	}
1682
1683	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1684	if (uShadowCr4 == pCtx->cr4)
1685	{
1686	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1687	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1688	else
1689	{
1690	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1691	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1692	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1693	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1694	}
1695	}
1696	else
1697	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1698
1699	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1700	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1701
1702	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1703	Assert(!RT_HI_U32(uShadowCr4));
1704	pVmcb->guest.u64CR4 = uShadowCr4;
1705	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1706
1707	return VINF_SUCCESS;
1708	}
1709
1710
1711	/**
1712	* Exports the guest (or nested-guest) control registers into the VMCB.
1713	*
1714	* @returns VBox status code.
1715	* @param pVCpu The cross context virtual CPU structure.
1716	* @param pVmcb Pointer to the VM control block.
1717	*
1718	* @remarks No-long-jump zone!!!
1719	*/
1720	static int hmR0SvmExportGuestControlRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1721	{
1722	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1723
1724	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1725	{
1726	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1727	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1728
1729	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1730	{
1731	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1732	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1733	}
1734
1735	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1736	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1737
1738	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1739	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1740	{
1741	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1742	if (RT_FAILURE(rc))
1743	return rc;
1744	}
1745
1746	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1747	}
1748	return VINF_SUCCESS;
1749	}
1750
1751
1752	/**
1753	* Exports the guest (or nested-guest) segment registers into the VMCB.
1754	*
1755	* @returns VBox status code.
1756	* @param pVCpu The cross context virtual CPU structure.
1757	* @param pVmcb Pointer to the VM control block.
1758	*
1759	* @remarks No-long-jump zone!!!
1760	*/
1761	static void hmR0SvmExportGuestSegmentRegs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1762	{
1763	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1764	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1765
1766	/* Guest segment registers. */
1767	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1768	{
1769	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1770	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1771
1772	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1773	{
1774	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1775	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1776	}
1777
1778	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1779	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1780
1781	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1782	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1783
1784	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1785	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1786
1787	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1788	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1789
1790	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1791	}
1792
1793	/* Guest TR. */
1794	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1795	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1796
1797	/* Guest LDTR. */
1798	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1799	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1800
1801	/* Guest GDTR. */
1802	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1803	{
1804	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1805	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1806	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1807	}
1808
1809	/* Guest IDTR. */
1810	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1811	{
1812	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1813	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1814	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1815	}
1816
1817	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1818	\| HM_CHANGED_GUEST_TABLE_MASK);
1819	}
1820
1821
1822	/**
1823	* Exports the guest (or nested-guest) MSRs into the VMCB.
1824	*
1825	* @param pVCpu The cross context virtual CPU structure.
1826	* @param pVmcb Pointer to the VM control block.
1827	*
1828	* @remarks No-long-jump zone!!!
1829	*/
1830	static void hmR0SvmExportGuestMsrs(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1831	{
1832	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1833	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1834
1835	/* Guest Sysenter MSRs. */
1836	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1837	{
1838	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1839	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1840
1841	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1842	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1843
1844	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1845	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1846	}
1847
1848	/*
1849	* Guest EFER MSR.
1850	* AMD-V requires guest EFER.SVME to be set. Weird.
1851	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1852	*/
1853	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1854	{
1855	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1856	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1857	}
1858
1859	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1860	if ( !CPUMIsGuestInLongModeEx(pCtx)
1861	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1862	{
1863	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1864	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1865	}
1866
1867	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1868	{
1869	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1870	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1871	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1872	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1873	}
1874
1875	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1876	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1877
1878	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1879	\| HM_CHANGED_GUEST_EFER_MSR
1880	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1881	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1882
1883	/*
1884	* Setup the PAT MSR (applicable for Nested Paging only).
1885	*
1886	* The default value should be MSR_IA32_CR_PAT_INIT_VAL, but we treat all guest memory
1887	* as WB, so choose type 6 for all PAT slots, see @bugref{9634}.
1888	*
1889	* While guests can modify and see the modified values through the shadow values,
1890	* we shall not honor any guest modifications of this MSR to ensure caching is always
1891	* enabled similar to how we clear CR0.CD and NW bits.
1892	*
1893	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1894	*/
1895	pVmcb->guest.u64PAT = UINT64_C(0x0006060606060606);
1896
1897	/* Enable the last branch record bit if LBR virtualization is enabled. */
1898	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1899	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1900	}
1901
1902
1903	/**
1904	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1905	* the necessary intercepts accordingly.
1906	*
1907	* @param pVCpu The cross context virtual CPU structure.
1908	* @param pVmcb Pointer to the VM control block.
1909	*
1910	* @remarks No-long-jump zone!!!
1911	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1912	*/
1913	static void hmR0SvmExportSharedDebugState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
1914	{
1915	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1916
1917	/** @todo Figure out stepping with nested-guest. */
1918	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1919	{
1920	/*
1921	* We don't want to always intercept DRx read/writes for nested-guests as it causes
1922	* problems when the nested hypervisor isn't intercepting them, see @bugref{10080}.
1923	* Instead, they are strictly only requested when the nested hypervisor intercepts
1924	* them -- handled while merging VMCB controls.
1925	*
1926	* If neither the outer nor the nested-hypervisor is intercepting DRx read/writes,
1927	* then the nested-guest debug state should be actively loaded on the host so that
1928	* nested-guest reads/writes its own debug registers without causing VM-exits.
1929	*/
1930	if ( ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1931	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1932	&& !CPUMIsGuestDebugStateActive(pVCpu))
1933	{
1934	CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
1935	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1936	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1937	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1938	}
1939
1940	pVmcb->guest.u64DR6 = pCtx->dr[6];
1941	pVmcb->guest.u64DR7 = pCtx->dr[7];
1942	return;
1943	}
1944
1945	/*
1946	* Anyone single stepping on the host side? If so, we'll have to use the
1947	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1948	* the VMM level like the VT-x implementations does.
1949	*/
1950	bool fInterceptMovDRx = false;
1951	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1952	if (fStepping)
1953	{
1954	pVCpu->hmr0.s.fClearTrapFlag = true;
1955	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1956	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1957	}
1958
1959	if ( fStepping
1960	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1961	{
1962	/*
1963	* Use the combined guest and host DRx values found in the hypervisor
1964	* register set because the debugger has breakpoints active or someone
1965	* is single stepping on the host side.
1966	*
1967	* Note! DBGF expects a clean DR6 state before executing guest code.
1968	*/
1969	if (!CPUMIsHyperDebugStateActive(pVCpu))
1970	{
1971	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1972	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1973	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1974	}
1975
1976	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1977	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1978	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1979	{
1980	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1981	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1982	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1983	}
1984
1985	/** @todo If we cared, we could optimize to allow the guest to read registers
1986	* with the same values. */
1987	fInterceptMovDRx = true;
1988	pVCpu->hmr0.s.fUsingHyperDR7 = true;
1989	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1990	}
1991	else
1992	{
1993	/*
1994	* Update DR6, DR7 with the guest values if necessary.
1995	*/
1996	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1997	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1998	{
1999	pVmcb->guest.u64DR7 = pCtx->dr[7];
2000	pVmcb->guest.u64DR6 = pCtx->dr[6];
2001	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
2002	}
2003	pVCpu->hmr0.s.fUsingHyperDR7 = false;
2004
2005	/*
2006	* If the guest has enabled debug registers, we need to load them prior to
2007	* executing guest code so they'll trigger at the right time.
2008	*/
2009	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
2010	{
2011	if (!CPUMIsGuestDebugStateActive(pVCpu))
2012	{
2013	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
2014	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
2015	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2016	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2017	}
2018	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
2019	}
2020	/*
2021	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
2022	* intercept #DB as DR6 is updated in the VMCB.
2023	*
2024	* Note! If we cared and dared, we could skip intercepting \#DB here.
2025	* However, \#DB shouldn't be performance critical, so we'll play safe
2026	* and keep the code similar to the VT-x code and always intercept it.
2027	*/
2028	else if (!CPUMIsGuestDebugStateActive(pVCpu))
2029	fInterceptMovDRx = true;
2030	}
2031
2032	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
2033	if (fInterceptMovDRx)
2034	{
2035	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
2036	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
2037	{
2038	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
2039	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
2040	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2041	}
2042	}
2043	else
2044	{
2045	if ( pVmcb->ctrl.u16InterceptRdDRx
2046	\|\| pVmcb->ctrl.u16InterceptWrDRx)
2047	{
2048	pVmcb->ctrl.u16InterceptRdDRx = 0;
2049	pVmcb->ctrl.u16InterceptWrDRx = 0;
2050	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2051	}
2052	}
2053	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2054	}
2055
2056	/**
2057	* Exports the hardware virtualization state into the nested-guest
2058	* VMCB.
2059	*
2060	* @param pVCpu The cross context virtual CPU structure.
2061	* @param pVmcb Pointer to the VM control block.
2062	*
2063	* @remarks No-long-jump zone!!!
2064	*/
2065	static void hmR0SvmExportGuestHwvirtState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2066	{
2067	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2068
2069	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
2070	{
2071	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2072	{
2073	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2074	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
2075
2076	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx); /* Nested VGIF is not supported yet. */
2077	Assert(g_fHmSvmFeatures & X86_CPUID_SVM_FEATURE_EDX_VGIF); /* Physical hardware supports VGIF. */
2078	Assert(HMIsSvmVGifActive(pVM)); /* Outer VM has enabled VGIF. */
2079	NOREF(pVM);
2080
2081	pVmcb->ctrl.IntCtrl.n.u1VGif = CPUMGetGuestGif(pCtx);
2082	}
2083
2084	/*
2085	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2086	* since SVM doesn't have a preemption timer.
2087	*
2088	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
2089	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2090	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2091	*/
2092	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2093	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2094	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2095	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2096	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_PAUSE))
2097	{
2098	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2099	pVmcbCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2100	pVmcbCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2101	}
2102	else
2103	{
2104	/** @todo r=ramshankar: We can turn these assignments into assertions. */
2105	pVmcbCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2106	pVmcbCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2107	}
2108	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2109
2110	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
2111	}
2112	}
2113
2114
2115	/**
2116	* Exports the guest APIC TPR state into the VMCB.
2117	*
2118	* @returns VBox status code.
2119	* @param pVCpu The cross context virtual CPU structure.
2120	* @param pVmcb Pointer to the VM control block.
2121	*/
2122	static int hmR0SvmExportGuestApicTpr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2123	{
2124	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2125
2126	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2127	{
2128	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2129	if ( PDMHasApic(pVM)
2130	&& APICIsEnabled(pVCpu))
2131	{
2132	bool fPendingIntr;
2133	uint8_t u8Tpr;
2134	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2135	AssertRCReturn(rc, rc);
2136
2137	/* Assume that we need to trap all TPR accesses and thus need not check on
2138	every #VMEXIT if we should update the TPR. */
2139	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2140	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2141
2142	if (!pVM->hm.s.fTprPatchingActive)
2143	{
2144	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2145	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2146
2147	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2148	can deliver the interrupt to the guest. */
2149	if (fPendingIntr)
2150	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2151	else
2152	{
2153	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2154	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2155	}
2156
2157	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2158	}
2159	else
2160	{
2161	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2162	pVmcb->guest.u64LSTAR = u8Tpr;
2163	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hmr0.s.svm.pvMsrBitmap;
2164
2165	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2166	if (fPendingIntr)
2167	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2168	else
2169	{
2170	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2171	pVCpu->hmr0.s.svm.fSyncVTpr = true;
2172	}
2173	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2174	}
2175	}
2176	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2177	}
2178	return VINF_SUCCESS;
2179	}
2180
2181
2182	/**
2183	* Sets up the exception interrupts required for guest execution in the VMCB.
2184	*
2185	* @param pVCpu The cross context virtual CPU structure.
2186	* @param pVmcb Pointer to the VM control block.
2187	*
2188	* @remarks No-long-jump zone!!!
2189	*/
2190	static void hmR0SvmExportGuestXcptIntercepts(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2191	{
2192	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2193
2194	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2195	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_SVM_XCPT_INTERCEPTS)
2196	{
2197	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2198	if (pVCpu->hm.s.fGIMTrapXcptUD \|\| pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
2199	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2200	else
2201	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2202
2203	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2204	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2205	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2206	else
2207	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2208
2209	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2210	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_SVM_XCPT_INTERCEPTS);
2211	}
2212	}
2213
2214
2215	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2216	/**
2217	* Merges guest and nested-guest intercepts for executing the nested-guest using
2218	* hardware-assisted SVM.
2219	*
2220	* This merges the guest and nested-guest intercepts in a way that if the outer
2221	* guest intercept is set we need to intercept it in the nested-guest as
2222	* well.
2223	*
2224	* @param pVCpu The cross context virtual CPU structure.
2225	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2226	*/
2227	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPUCC pVCpu)
2228	{
2229	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2230	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
2231	PSVMVMCB pVmcbNstGst = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb;
2232	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2233
2234	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2235	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2236	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2237
2238	/* Always intercept CR4 writes for tracking PGM mode changes. */
2239	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2240
2241	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2242	if (!pVM->hmr0.s.fNestedPaging)
2243	{
2244	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2245	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2246	}
2247
2248	/* Merge the guest's DR intercepts into the nested-guest VMCB. */
2249	pVmcbNstGstCtrl->u16InterceptRdDRx \|= pVmcb->ctrl.u16InterceptRdDRx;
2250	pVmcbNstGstCtrl->u16InterceptWrDRx \|= pVmcb->ctrl.u16InterceptWrDRx;
2251
2252	/*
2253	* Merge the guest's exception intercepts into the nested-guest VMCB.
2254	*
2255	* - #UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2256	* while executing the nested-guest.
2257	*
2258	* - #BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2259	* be tweaked later depending on how we wish to implement breakpoints.
2260	*
2261	* - #GP: Exclude these as it's the inner VMMs problem to get vmsvga 3d drivers
2262	* loaded into their guests, not ours.
2263	*
2264	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2265	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2266	*/
2267	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2268	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt
2269	& ~( RT_BIT(X86_XCPT_UD)
2270	\| RT_BIT(X86_XCPT_BP)
2271	\| (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv ? RT_BIT(X86_XCPT_GP) : 0));
2272	#else
2273	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2274	#endif
2275
2276	/*
2277	* Adjust intercepts while executing the nested-guest that differ from the
2278	* outer guest intercepts.
2279	*
2280	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2281	* that belong to the nested-guest to the outer guest.
2282	*
2283	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2284	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2285	*/
2286	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2287	\| SVM_CTRL_INTERCEPT_VMMCALL))
2288	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2289
2290	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2291	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2292
2293	/* Finally, update the VMCB clean bits. */
2294	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2295	}
2296	#endif
2297
2298
2299	/**
2300	* Enters the AMD-V session.
2301	*
2302	* @returns VBox status code.
2303	* @param pVCpu The cross context virtual CPU structure.
2304	*/
2305	VMMR0DECL(int) SVMR0Enter(PVMCPUCC pVCpu)
2306	{
2307	AssertPtr(pVCpu);
2308	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2309	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2310
2311	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2312	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2313	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2314
2315	pVCpu->hmr0.s.fLeaveDone = false;
2316	return VINF_SUCCESS;
2317	}
2318
2319
2320	/**
2321	* Thread-context callback for AMD-V.
2322	*
2323	* This is used together with RTThreadCtxHookCreate() on platforms which
2324	* supports it, and directly from VMMR0EmtPrepareForBlocking() and
2325	* VMMR0EmtResumeAfterBlocking() on platforms which don't.
2326	*
2327	* @param enmEvent The thread-context event.
2328	* @param pVCpu The cross context virtual CPU structure.
2329	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2330	* @thread EMT(pVCpu)
2331	*/
2332	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
2333	{
2334	NOREF(fGlobalInit);
2335
2336	switch (enmEvent)
2337	{
2338	case RTTHREADCTXEVENT_OUT:
2339	{
2340	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2341	VMCPU_ASSERT_EMT(pVCpu);
2342
2343	/* No longjmps (log-flush, locks) in this fragile context. */
2344	VMMRZCallRing3Disable(pVCpu);
2345
2346	if (!pVCpu->hmr0.s.fLeaveDone)
2347	{
2348	hmR0SvmLeave(pVCpu, false /* fImportState */);
2349	pVCpu->hmr0.s.fLeaveDone = true;
2350	}
2351
2352	/* Leave HM context, takes care of local init (term). */
2353	int rc = HMR0LeaveCpu(pVCpu);
2354	AssertRC(rc); NOREF(rc);
2355
2356	/* Restore longjmp state. */
2357	VMMRZCallRing3Enable(pVCpu);
2358	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2359	break;
2360	}
2361
2362	case RTTHREADCTXEVENT_IN:
2363	{
2364	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2365	VMCPU_ASSERT_EMT(pVCpu);
2366
2367	/* No longjmps (log-flush, locks) in this fragile context. */
2368	VMMRZCallRing3Disable(pVCpu);
2369
2370	/*
2371	* Initialize the bare minimum state required for HM. This takes care of
2372	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2373	*/
2374	int rc = hmR0EnterCpu(pVCpu);
2375	AssertRC(rc); NOREF(rc);
2376	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2377	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2378
2379	pVCpu->hmr0.s.fLeaveDone = false;
2380
2381	/* Restore longjmp state. */
2382	VMMRZCallRing3Enable(pVCpu);
2383	break;
2384	}
2385
2386	default:
2387	break;
2388	}
2389	}
2390
2391
2392	/**
2393	* Saves the host state.
2394	*
2395	* @returns VBox status code.
2396	* @param pVCpu The cross context virtual CPU structure.
2397	*
2398	* @remarks No-long-jump zone!!!
2399	*/
2400	VMMR0DECL(int) SVMR0ExportHostState(PVMCPUCC pVCpu)
2401	{
2402	NOREF(pVCpu);
2403
2404	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2405	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2406	return VINF_SUCCESS;
2407	}
2408
2409
2410	/**
2411	* Exports the guest or nested-guest state from the virtual-CPU context into the
2412	* VMCB.
2413	*
2414	* Also sets up the appropriate VMRUN function to execute guest or nested-guest
2415	* code based on the virtual-CPU mode.
2416	*
2417	* @returns VBox status code.
2418	* @param pVCpu The cross context virtual CPU structure.
2419	* @param pSvmTransient Pointer to the SVM-transient structure.
2420	*
2421	* @remarks No-long-jump zone!!!
2422	*/
2423	static int hmR0SvmExportGuestState(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
2424	{
2425	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2426
2427	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2428	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2429	Assert(pVmcb);
2430
2431	pVmcb->guest.u64RIP = pCtx->rip;
2432	pVmcb->guest.u64RSP = pCtx->rsp;
2433	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2434	pVmcb->guest.u64RAX = pCtx->rax;
2435
2436	bool const fIsNestedGuest = pSvmTransient->fIsNestedGuest;
2437	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2438
2439	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2440	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2441	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2442	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2443	hmR0SvmExportGuestHwvirtState(pVCpu, pVmcb);
2444
2445	ASMSetFlags(fEFlags);
2446
2447	if (!fIsNestedGuest)
2448	{
2449	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2450	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2451	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2452	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2453	}
2454
2455	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2456	uint64_t fUnusedMask = HM_CHANGED_GUEST_RIP
2457	\| HM_CHANGED_GUEST_RFLAGS
2458	\| HM_CHANGED_GUEST_GPRS_MASK
2459	\| HM_CHANGED_GUEST_X87
2460	\| HM_CHANGED_GUEST_SSE_AVX
2461	\| HM_CHANGED_GUEST_OTHER_XSAVE
2462	\| HM_CHANGED_GUEST_XCRx
2463	\| HM_CHANGED_GUEST_TSC_AUX
2464	\| HM_CHANGED_GUEST_OTHER_MSRS;
2465	if (fIsNestedGuest)
2466	fUnusedMask \|= HM_CHANGED_SVM_XCPT_INTERCEPTS
2467	\| HM_CHANGED_GUEST_APIC_TPR;
2468
2469	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( fUnusedMask
2470	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2471
2472	#ifdef VBOX_STRICT
2473	/*
2474	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2475	* except for the host-context and/or shared host-guest context bits.
2476	*/
2477	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2478	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2479	("fCtxChanged=%#RX64\n", fCtxChanged));
2480
2481	/*
2482	* If we need to log state that isn't always imported, we'll need to import them here.
2483	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2484	*/
2485	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2486	#endif
2487
2488	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2489	return VINF_SUCCESS;
2490	}
2491
2492	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2493
2494	/**
2495	* Merges the guest and nested-guest MSR permission bitmap.
2496	*
2497	* If the guest is intercepting an MSR we need to intercept it regardless of
2498	* whether the nested-guest is intercepting it or not.
2499	*
2500	* @param pHostCpu The HM physical-CPU structure.
2501	* @param pVCpu The cross context virtual CPU structure.
2502	*
2503	* @remarks No-long-jmp zone!!!
2504	*/
2505	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2506	{
2507	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hmr0.s.svm.pvMsrBitmap;
2508	uint64_t const pu64NstGstMsrpm = (uint64_t const )&pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap[0];
2509	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2510
2511	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2512	uint32_t const offRsvdQwords = 0x1800 >> 3;
2513	for (uint32_t i = 0; i < offRsvdQwords; i++)
2514	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2515	}
2516
2517
2518	/**
2519	* Caches the nested-guest VMCB fields before we modify them for execution using
2520	* hardware-assisted SVM.
2521	*
2522	* @returns true if the VMCB was previously already cached, false otherwise.
2523	* @param pVCpu The cross context virtual CPU structure.
2524	*
2525	* @sa HMNotifySvmNstGstVmexit.
2526	*/
2527	static bool hmR0SvmCacheVmcbNested(PVMCPUCC pVCpu)
2528	{
2529	/*
2530	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2531	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2532	*
2533	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2534	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2535	*/
2536	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2537	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2538	if (!fWasCached)
2539	{
2540	PCSVMVMCB pVmcbNstGst = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb;
2541	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2542	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2543	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2544	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2545	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2546	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2547	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2548	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2549	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2550	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2551	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2552	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2553	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2554	pVmcbNstGstCache->fCacheValid = true;
2555	Log4Func(("Cached VMCB fields\n"));
2556	}
2557
2558	return fWasCached;
2559	}
2560
2561
2562	/**
2563	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2564	*
2565	* This is done the first time we enter nested-guest execution using SVM R0
2566	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2567	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2568	*
2569	* @param pVCpu The cross context virtual CPU structure.
2570	*/
2571	static void hmR0SvmSetupVmcbNested(PVMCPUCC pVCpu)
2572	{
2573	PSVMVMCB pVmcbNstGst = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb;
2574	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2575
2576	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
2577
2578	/*
2579	* First cache the nested-guest VMCB fields we may potentially modify.
2580	*/
2581	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2582	if (!fVmcbCached)
2583	{
2584	/*
2585	* The IOPM of the nested-guest can be ignored because the the guest always
2586	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2587	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2588	*/
2589	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2590
2591	/*
2592	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2593	* nested-paging suddenly while executing a VM (see assertion at the end of
2594	* Trap0eHandler() in PGMAllBth.h).
2595	*/
2596	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging;
2597
2598	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2599	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2600
2601	/*
2602	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2603	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2604	*/
2605	pVCpu->hmr0.s.svm.fSyncVTpr = false;
2606
2607	# ifdef DEBUG_ramshankar
2608	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2609	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2610	# endif
2611
2612	/*
2613	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2614	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2615	*/
2616	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2617	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2618	\| SVM_CTRL_INTERCEPT_VMLOAD;
2619
2620	/*
2621	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2622	* CLGI/STGI instructions executed by the nested-guest.
2623	*/
2624	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2625	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2626	\| SVM_CTRL_INTERCEPT_STGI;
2627
2628	/* Merge the guest and nested-guest intercepts. */
2629	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2630
2631	/* Update the VMCB clean bits. */
2632	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2633	}
2634	else
2635	{
2636	Assert(!pVCpu->hmr0.s.svm.fSyncVTpr);
2637	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2638	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2639	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPagingCfg == pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
2640	}
2641	}
2642
2643	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2644
2645	/**
2646	* Exports the state shared between the host and guest (or nested-guest) into
2647	* the VMCB.
2648	*
2649	* @param pVCpu The cross context virtual CPU structure.
2650	* @param pVmcb Pointer to the VM control block.
2651	*
2652	* @remarks No-long-jump zone!!!
2653	*/
2654	static void hmR0SvmExportSharedState(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
2655	{
2656	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2657	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2658
2659	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2660	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2661
2662	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2663	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2664	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2665	}
2666
2667
2668	/**
2669	* Worker for SVMR0ImportStateOnDemand.
2670	*
2671	* @param pVCpu The cross context virtual CPU structure.
2672	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2673	*/
2674	static void hmR0SvmImportGuestState(PVMCPUCC pVCpu, uint64_t fWhat)
2675	{
2676	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2677
2678	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2679	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2680	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2681	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2682
2683	/*
2684	* We disable interrupts to make the updating of the state and in particular
2685	* the fExtrn modification atomic wrt to preemption hooks.
2686	*/
2687	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2688
2689	fWhat &= pCtx->fExtrn;
2690	if (fWhat)
2691	{
2692	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2693	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2694	{
2695	if (pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2696	{
2697	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx)); /* We don't yet support passing VGIF feature to the guest. */
2698	Assert(HMIsSvmVGifActive(pVCpu->CTX_SUFF(pVM))); /* VM has configured it. */
2699	CPUMSetGuestGif(pCtx, pVmcbCtrl->IntCtrl.n.u1VGif);
2700	}
2701	}
2702
2703	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2704	{
2705	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2706	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2707	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2708	}
2709	#endif
2710
2711	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2712	{
2713	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2714	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2715	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2716	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2717	}
2718
2719	if (fWhat & CPUMCTX_EXTRN_RIP)
2720	pCtx->rip = pVmcbGuest->u64RIP;
2721
2722	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2723	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2724
2725	if (fWhat & CPUMCTX_EXTRN_RSP)
2726	pCtx->rsp = pVmcbGuest->u64RSP;
2727
2728	if (fWhat & CPUMCTX_EXTRN_RAX)
2729	pCtx->rax = pVmcbGuest->u64RAX;
2730
2731	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2732	{
2733	if (fWhat & CPUMCTX_EXTRN_CS)
2734	{
2735	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2736	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2737	/** @todo SELM might need to be fixed as it too should not care about the
2738	* granularity bit. See @bugref{6785}. */
2739	if ( !pCtx->cs.Attr.n.u1Granularity
2740	&& pCtx->cs.Attr.n.u1Present
2741	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2742	{
2743	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2744	pCtx->cs.Attr.n.u1Granularity = 1;
2745	}
2746	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2747	}
2748	if (fWhat & CPUMCTX_EXTRN_SS)
2749	{
2750	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2751	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2752	/*
2753	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2754	* VMCB and uses that and thus it's possible that when the CPL changes during
2755	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2756	* AMD Fusion CPUs with 64-bit guests.
2757	*
2758	* See AMD spec. 15.5.1 "Basic operation".
2759	*/
2760	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2761	uint8_t const uCpl = pVmcbGuest->u8CPL;
2762	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2763	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2764	}
2765	if (fWhat & CPUMCTX_EXTRN_DS)
2766	{
2767	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2768	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2769	}
2770	if (fWhat & CPUMCTX_EXTRN_ES)
2771	{
2772	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2773	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2774	}
2775	if (fWhat & CPUMCTX_EXTRN_FS)
2776	{
2777	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2778	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2779	}
2780	if (fWhat & CPUMCTX_EXTRN_GS)
2781	{
2782	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2783	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2784	}
2785	}
2786
2787	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2788	{
2789	if (fWhat & CPUMCTX_EXTRN_TR)
2790	{
2791	/*
2792	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2793	* are used between Intel and AMD, see @bugref{6208#c39}.
2794	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2795	*/
2796	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2797	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2798	{
2799	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2800	\|\| CPUMIsGuestInLongModeEx(pCtx))
2801	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2802	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2803	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2804	}
2805	}
2806
2807	if (fWhat & CPUMCTX_EXTRN_LDTR)
2808	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2809
2810	if (fWhat & CPUMCTX_EXTRN_GDTR)
2811	{
2812	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2813	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2814	}
2815
2816	if (fWhat & CPUMCTX_EXTRN_IDTR)
2817	{
2818	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2819	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2820	}
2821	}
2822
2823	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2824	{
2825	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2826	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2827	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2828	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2829	}
2830
2831	if ( (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2832	&& !pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit /* Intercepted. AMD-V would clear the high 32 bits of EIP & ESP. */)
2833	{
2834	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2835	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2836	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2837	}
2838
2839	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2840	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2841
2842	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2843	{
2844	if (fWhat & CPUMCTX_EXTRN_DR6)
2845	{
2846	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2847	pCtx->dr[6] = pVmcbGuest->u64DR6;
2848	else
2849	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2850	}
2851
2852	if (fWhat & CPUMCTX_EXTRN_DR7)
2853	{
2854	if (!pVCpu->hmr0.s.fUsingHyperDR7)
2855	pCtx->dr[7] = pVmcbGuest->u64DR7;
2856	else
2857	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2858	}
2859	}
2860
2861	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2862	{
2863	if (fWhat & CPUMCTX_EXTRN_CR0)
2864	{
2865	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2866	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2867	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2868	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2869	CPUMSetGuestCR0(pVCpu, uCr0);
2870	VMMRZCallRing3Enable(pVCpu);
2871	}
2872
2873	if (fWhat & CPUMCTX_EXTRN_CR2)
2874	pCtx->cr2 = pVmcbGuest->u64CR2;
2875
2876	if (fWhat & CPUMCTX_EXTRN_CR3)
2877	{
2878	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2879	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2880	{
2881	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2882	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2883	}
2884	}
2885
2886	/* Changes to CR4 are always intercepted. */
2887	}
2888
2889	/* Update fExtrn. */
2890	pCtx->fExtrn &= ~fWhat;
2891
2892	/* If everything has been imported, clear the HM keeper bit. */
2893	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2894	{
2895	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2896	Assert(!pCtx->fExtrn);
2897	}
2898	}
2899	else
2900	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
2901
2902	ASMSetFlags(fEFlags);
2903
2904	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
2905
2906	/*
2907	* Honor any pending CR3 updates.
2908	*
2909	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
2910	* -> SVMR0CallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
2911	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
2912	* handling -> hmR0SvmImportGuestState() and here we are.
2913	*
2914	* The reason for such complicated handling is because VM-exits that call into PGM expect
2915	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
2916	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
2917	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
2918	*
2919	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
2920	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
2921	*/
2922	if ( VMMRZCallRing3IsEnabled(pVCpu)
2923	&& VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
2924	{
2925	AssertMsg(pCtx->cr3 == pVmcbGuest->u64CR3, ("cr3=%#RX64 vmcb_cr3=%#RX64\n", pCtx->cr3, pVmcbGuest->u64CR3));
2926	PGMUpdateCR3(pVCpu, pCtx->cr3, false /* fPdpesMapped */);
2927	}
2928	}
2929
2930
2931	/**
2932	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2933	* context.
2934	*
2935	* Currently there is no residual state left in the CPU that is not updated in the
2936	* VMCB.
2937	*
2938	* @returns VBox status code.
2939	* @param pVCpu The cross context virtual CPU structure.
2940	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2941	*/
2942	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2943	{
2944	hmR0SvmImportGuestState(pVCpu, fWhat);
2945	return VINF_SUCCESS;
2946	}
2947
2948
2949	/**
2950	* Does the necessary state syncing before returning to ring-3 for any reason
2951	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2952	*
2953	* @param pVCpu The cross context virtual CPU structure.
2954	* @param fImportState Whether to import the guest state from the VMCB back
2955	* to the guest-CPU context.
2956	*
2957	* @remarks No-long-jmp zone!!!
2958	*/
2959	static void hmR0SvmLeave(PVMCPUCC pVCpu, bool fImportState)
2960	{
2961	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2962	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2963
2964	/*
2965	* !!! IMPORTANT !!!
2966	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
2967	*/
2968
2969	/* Save the guest state if necessary. */
2970	if (fImportState)
2971	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
2972
2973	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2974	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2975	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2976
2977	/*
2978	* Restore host debug registers if necessary and resync on next R0 reentry.
2979	*/
2980	#ifdef VBOX_STRICT
2981	if (CPUMIsHyperDebugStateActive(pVCpu))
2982	{
2983	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb; /** @todo nested-guest. */
2984	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2985	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2986	}
2987	#endif
2988	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2989	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2990	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2991
2992	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2993	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
2994	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
2995	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
2996	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
2997	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
2998	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2999
3000	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
3001	}
3002
3003
3004	/**
3005	* Leaves the AMD-V session.
3006	*
3007	* Only used while returning to ring-3 either due to longjump or exits to
3008	* ring-3.
3009	*
3010	* @returns VBox status code.
3011	* @param pVCpu The cross context virtual CPU structure.
3012	*/
3013	static int hmR0SvmLeaveSession(PVMCPUCC pVCpu)
3014	{
3015	HM_DISABLE_PREEMPT(pVCpu);
3016	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3017	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3018
3019	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3020	and done this from the SVMR0ThreadCtxCallback(). */
3021	if (!pVCpu->hmr0.s.fLeaveDone)
3022	{
3023	hmR0SvmLeave(pVCpu, true /* fImportState */);
3024	pVCpu->hmr0.s.fLeaveDone = true;
3025	}
3026
3027	/*
3028	* !!! IMPORTANT !!!
3029	* If you modify code here, make sure to check whether SVMR0CallRing3Callback() needs to be updated too.
3030	*/
3031
3032	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3033	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3034	VMMR0ThreadCtxHookDisable(pVCpu);
3035
3036	/* Leave HM context. This takes care of local init (term). */
3037	int rc = HMR0LeaveCpu(pVCpu);
3038
3039	HM_RESTORE_PREEMPT();
3040	return rc;
3041	}
3042
3043
3044	/**
3045	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3046	* any remaining host state) before we go back to ring-3 due to an assertion.
3047	*
3048	* @param pVCpu The cross context virtual CPU structure.
3049	*/
3050	VMMR0DECL(int) SVMR0AssertionCallback(PVMCPUCC pVCpu)
3051	{
3052	/*
3053	* !!! IMPORTANT !!!
3054	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3055	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3056	*/
3057	VMMR0AssertionRemoveNotification(pVCpu);
3058	VMMRZCallRing3Disable(pVCpu);
3059	HM_DISABLE_PREEMPT(pVCpu);
3060
3061	/* Import the entire guest state. */
3062	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3063
3064	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3065	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3066
3067	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3068	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3069
3070	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3071	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3072	VMMR0ThreadCtxHookDisable(pVCpu);
3073
3074	/* Leave HM context. This takes care of local init (term). */
3075	HMR0LeaveCpu(pVCpu);
3076
3077	HM_RESTORE_PREEMPT();
3078	return VINF_SUCCESS;
3079	}
3080
3081
3082	/**
3083	* Take necessary actions before going back to ring-3.
3084	*
3085	* An action requires us to go back to ring-3. This function does the necessary
3086	* steps before we can safely return to ring-3. This is not the same as longjmps
3087	* to ring-3, this is voluntary.
3088	*
3089	* @returns Strict VBox status code.
3090	* @param pVCpu The cross context virtual CPU structure.
3091	* @param rcExit The reason for exiting to ring-3. Can be
3092	* VINF_VMM_UNKNOWN_RING3_CALL.
3093	*/
3094	static VBOXSTRICTRC hmR0SvmExitToRing3(PVMCPUCC pVCpu, VBOXSTRICTRC rcExit)
3095	{
3096	Assert(pVCpu);
3097	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3098
3099	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3100	VMMRZCallRing3Disable(pVCpu);
3101	Log4Func(("rcExit=%d LocalFF=%#RX64 GlobalFF=%#RX32\n", VBOXSTRICTRC_VAL(rcExit), (uint64_t)pVCpu->fLocalForcedActions,
3102	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3103
3104	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3105	if (pVCpu->hm.s.Event.fPending)
3106	{
3107	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3108	Assert(!pVCpu->hm.s.Event.fPending);
3109	}
3110
3111	/* Sync. the necessary state for going back to ring-3. */
3112	hmR0SvmLeaveSession(pVCpu);
3113	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3114
3115	/* Thread-context hooks are unregistered at this point!!! */
3116	/* Ring-3 callback notifications are unregistered at this point!!! */
3117
3118	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3119	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3120	\| CPUM_CHANGED_LDTR
3121	\| CPUM_CHANGED_GDTR
3122	\| CPUM_CHANGED_IDTR
3123	\| CPUM_CHANGED_TR
3124	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3125	if ( pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging
3126	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3127	{
3128	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3129	}
3130
3131	/* Update the exit-to-ring 3 reason. */
3132	pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
3133
3134	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3135	if ( rcExit != VINF_EM_RAW_INTERRUPT
3136	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3137	{
3138	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3139	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3140	}
3141
3142	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3143	VMMRZCallRing3Enable(pVCpu);
3144
3145	/*
3146	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3147	* and if we're injecting an event we should have a TRPM trap pending.
3148	*/
3149	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3150	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3151	VERR_SVM_IPE_5);
3152	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3153	pVCpu->hm.s.u32HMError = VBOXSTRICTRC_VAL(rcExit),
3154	VERR_SVM_IPE_4);
3155
3156	return rcExit;
3157	}
3158
3159
3160	/**
3161	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3162	* intercepts.
3163	*
3164	* @param pVCpu The cross context virtual CPU structure.
3165	* @param pVmcb Pointer to the VM control block.
3166	*
3167	* @remarks No-long-jump zone!!!
3168	*/
3169	static void hmR0SvmUpdateTscOffsetting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3170	{
3171	/*
3172	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3173	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3174	* RDTSC/RDTSCP as well.
3175	*/
3176	bool fParavirtTsc;
3177	uint64_t uTscOffset;
3178	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3179
3180	bool fIntercept;
3181	if (fCanUseRealTsc)
3182	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3183	else
3184	{
3185	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3186	fIntercept = true;
3187	}
3188
3189	if (!fIntercept)
3190	{
3191	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3192	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3193	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3194	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
3195	#endif
3196
3197	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3198	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3199	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3200	}
3201
3202	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3203	information before every VM-entry, hence we have nothing to do here at the moment. */
3204	if (fParavirtTsc)
3205	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3206	}
3207
3208
3209	/**
3210	* Sets an event as a pending event to be injected into the guest.
3211	*
3212	* @param pVCpu The cross context virtual CPU structure.
3213	* @param pEvent Pointer to the SVM event.
3214	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3215	* page-fault.
3216	*
3217	* @remarks Statistics counter assumes this is a guest event being reflected to
3218	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3219	*/
3220	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPUCC pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3221	{
3222	Assert(!pVCpu->hm.s.Event.fPending);
3223	Assert(pEvent->n.u1Valid);
3224
3225	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3226	pVCpu->hm.s.Event.fPending = true;
3227	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3228
3229	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3230	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3231	}
3232
3233
3234	/**
3235	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3236	*
3237	* @param pVCpu The cross context virtual CPU structure.
3238	*/
3239	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPUCC pVCpu)
3240	{
3241	SVMEVENT Event;
3242	Event.u = 0;
3243	Event.n.u1Valid = 1;
3244	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3245	Event.n.u8Vector = X86_XCPT_UD;
3246	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3247	}
3248
3249
3250	/**
3251	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3252	*
3253	* @param pVCpu The cross context virtual CPU structure.
3254	*/
3255	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPUCC pVCpu)
3256	{
3257	SVMEVENT Event;
3258	Event.u = 0;
3259	Event.n.u1Valid = 1;
3260	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3261	Event.n.u8Vector = X86_XCPT_DB;
3262	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3263	}
3264
3265
3266	/**
3267	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3268	*
3269	* @param pVCpu The cross context virtual CPU structure.
3270	* @param u32ErrCode The error-code for the page-fault.
3271	* @param uFaultAddress The page fault address (CR2).
3272	*
3273	* @remarks This updates the guest CR2 with @a uFaultAddress!
3274	*/
3275	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPUCC pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3276	{
3277	SVMEVENT Event;
3278	Event.u = 0;
3279	Event.n.u1Valid = 1;
3280	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3281	Event.n.u8Vector = X86_XCPT_PF;
3282	Event.n.u1ErrorCodeValid = 1;
3283	Event.n.u32ErrorCode = u32ErrCode;
3284
3285	/* Update CR2 of the guest. */
3286	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3287	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3288	{
3289	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3290	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3291	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3292	}
3293
3294	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3295	}
3296
3297
3298	/**
3299	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3300	*
3301	* @param pVCpu The cross context virtual CPU structure.
3302	*/
3303	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPUCC pVCpu)
3304	{
3305	SVMEVENT Event;
3306	Event.u = 0;
3307	Event.n.u1Valid = 1;
3308	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3309	Event.n.u8Vector = X86_XCPT_MF;
3310	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3311	}
3312
3313
3314	/**
3315	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3316	*
3317	* @param pVCpu The cross context virtual CPU structure.
3318	*/
3319	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPUCC pVCpu)
3320	{
3321	SVMEVENT Event;
3322	Event.u = 0;
3323	Event.n.u1Valid = 1;
3324	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3325	Event.n.u8Vector = X86_XCPT_DF;
3326	Event.n.u1ErrorCodeValid = 1;
3327	Event.n.u32ErrorCode = 0;
3328	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3329	}
3330
3331
3332	/**
3333	* Injects an event into the guest upon VMRUN by updating the relevant field
3334	* in the VMCB.
3335	*
3336	* @param pVCpu The cross context virtual CPU structure.
3337	* @param pVmcb Pointer to the guest VM control block.
3338	* @param pEvent Pointer to the event.
3339	*
3340	* @remarks No-long-jump zone!!!
3341	* @remarks Requires CR0!
3342	*/
3343	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3344	{
3345	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3346	pVmcb->ctrl.EventInject.u = pEvent->u;
3347	if ( pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_EXCEPTION
3348	\|\| pVmcb->ctrl.EventInject.n.u3Type == SVM_EVENT_NMI)
3349	{
3350	Assert(pEvent->n.u8Vector <= X86_XCPT_LAST);
3351	STAM_COUNTER_INC(&pVCpu->hm.s.aStatInjectedXcpts[pEvent->n.u8Vector]);
3352	}
3353	else
3354	STAM_COUNTER_INC(&pVCpu->hm.s.aStatInjectedIrqs[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3355	RT_NOREF(pVCpu);
3356
3357	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3358	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3359	}
3360
3361
3362
3363	/**
3364	* Converts any TRPM trap into a pending HM event. This is typically used when
3365	* entering from ring-3 (not longjmp returns).
3366	*
3367	* @param pVCpu The cross context virtual CPU structure.
3368	*/
3369	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
3370	{
3371	Assert(TRPMHasTrap(pVCpu));
3372	Assert(!pVCpu->hm.s.Event.fPending);
3373
3374	uint8_t uVector;
3375	TRPMEVENT enmTrpmEvent;
3376	uint32_t uErrCode;
3377	RTGCUINTPTR GCPtrFaultAddress;
3378	uint8_t cbInstr;
3379
3380	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, NULL /* pfIcebp */);
3381	AssertRC(rc);
3382
3383	SVMEVENT Event;
3384	Event.u = 0;
3385	Event.n.u1Valid = 1;
3386	Event.n.u8Vector = uVector;
3387
3388	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3389	if (enmTrpmEvent == TRPM_TRAP)
3390	{
3391	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3392	switch (uVector)
3393	{
3394	case X86_XCPT_NMI:
3395	{
3396	Event.n.u3Type = SVM_EVENT_NMI;
3397	break;
3398	}
3399
3400	case X86_XCPT_BP:
3401	case X86_XCPT_OF:
3402	AssertMsgFailed(("Invalid TRPM vector %d for event type %d\n", uVector, enmTrpmEvent));
3403	RT_FALL_THRU();
3404
3405	case X86_XCPT_PF:
3406	case X86_XCPT_DF:
3407	case X86_XCPT_TS:
3408	case X86_XCPT_NP:
3409	case X86_XCPT_SS:
3410	case X86_XCPT_GP:
3411	case X86_XCPT_AC:
3412	{
3413	Event.n.u1ErrorCodeValid = 1;
3414	Event.n.u32ErrorCode = uErrCode;
3415	break;
3416	}
3417	}
3418	}
3419	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3420	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3421	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3422	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3423	else
3424	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3425
3426	rc = TRPMResetTrap(pVCpu);
3427	AssertRC(rc);
3428
3429	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3430	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3431
3432	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3433	}
3434
3435
3436	/**
3437	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3438	* AMD-V to execute any instruction.
3439	*
3440	* @param pVCpu The cross context virtual CPU structure.
3441	*/
3442	static void hmR0SvmPendingEventToTrpmTrap(PVMCPUCC pVCpu)
3443	{
3444	Assert(pVCpu->hm.s.Event.fPending);
3445	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3446
3447	SVMEVENT Event;
3448	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3449
3450	uint8_t uVector = Event.n.u8Vector;
3451	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event, uVector);
3452
3453	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, Event.n.u3Type));
3454
3455	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3456	AssertRC(rc);
3457
3458	if (Event.n.u1ErrorCodeValid)
3459	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3460
3461	if ( enmTrapType == TRPM_TRAP
3462	&& uVector == X86_XCPT_PF)
3463	{
3464	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3465	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3466	}
3467	else if (enmTrapType == TRPM_SOFTWARE_INT)
3468	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3469	pVCpu->hm.s.Event.fPending = false;
3470	}
3471
3472
3473	/**
3474	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3475	* now.
3476	*
3477	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3478	* @param pVCpu The cross context virtual CPU structure.
3479	*
3480	* @remarks No-long-jump zone!!!
3481	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3482	*/
3483	static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
3484	{
3485	/*
3486	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3487	* completes. Check if we should inhibit interrupts or clear any existing
3488	* interrupt inhibition.
3489	*/
3490	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3491	{
3492	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3493	{
3494	/*
3495	* We can clear the inhibit force flag as even if we go back to the recompiler
3496	* without executing guest code in AMD-V, the flag's condition to be cleared is
3497	* met and thus the cleared state is correct.
3498	*/
3499	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3500	return false;
3501	}
3502	return true;
3503	}
3504	return false;
3505	}
3506
3507
3508	/**
3509	* Sets the virtual interrupt intercept control in the VMCB.
3510	*
3511	* @param pVCpu The cross context virtual CPU structure.
3512	* @param pVmcb Pointer to the VM control block.
3513	*/
3514	static void hmR0SvmSetIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3515	{
3516	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3517
3518	/*
3519	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3520	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3521	* (updating ISR at the right time) and inject the interrupt.
3522	*
3523	* With AVIC is supported, we could make use of the asynchronously delivery without
3524	* #VMEXIT and we would be passing the AVIC page to SVM.
3525	*
3526	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3527	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3528	*/
3529	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3530	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3531	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3532	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3533	Log4(("Set VINTR intercept\n"));
3534	}
3535
3536
3537	/**
3538	* Clears the virtual interrupt intercept control in the VMCB as
3539	* we are figured the guest is unable process any interrupts
3540	* at this point of time.
3541	*
3542	* @param pVCpu The cross context virtual CPU structure.
3543	* @param pVmcb Pointer to the VM control block.
3544	*/
3545	static void hmR0SvmClearIntWindowExiting(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3546	{
3547	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx); NOREF(pVCpu);
3548
3549	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3550	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3551	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3552	{
3553	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3554	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3555	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3556	Log4(("Cleared VINTR intercept\n"));
3557	}
3558	}
3559
3560
3561	/**
3562	* Evaluates the event to be delivered to the guest and sets it as the pending
3563	* event.
3564	*
3565	* @returns Strict VBox status code.
3566	* @param pVCpu The cross context virtual CPU structure.
3567	* @param pSvmTransient Pointer to the SVM transient structure.
3568	*/
3569	static VBOXSTRICTRC hmR0SvmEvaluatePendingEvent(PVMCPUCC pVCpu, PCSVMTRANSIENT pSvmTransient)
3570	{
3571	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3572	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3573	\| CPUMCTX_EXTRN_RFLAGS
3574	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3575	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3576
3577	Assert(!pVCpu->hm.s.Event.fPending);
3578	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3579	Assert(pVmcb);
3580
3581	bool const fGif = CPUMGetGuestGif(pCtx);
3582	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3583	bool const fBlockNmi = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3584
3585	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3586	fGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3587	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3588
3589	/** @todo SMI. SMIs take priority over NMIs. */
3590
3591	/*
3592	* Check if the guest or nested-guest can receive NMIs.
3593	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3594	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3595	*/
3596	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3597	&& !fBlockNmi)
3598	{
3599	if ( fGif
3600	&& !fIntShadow)
3601	{
3602	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3603	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3604	{
3605	Log4(("Intercepting NMI -> #VMEXIT\n"));
3606	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3607	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3608	}
3609	#endif
3610	Log4(("Setting NMI pending for injection\n"));
3611	SVMEVENT Event;
3612	Event.u = 0;
3613	Event.n.u1Valid = 1;
3614	Event.n.u8Vector = X86_XCPT_NMI;
3615	Event.n.u3Type = SVM_EVENT_NMI;
3616	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3617	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3618	}
3619	else if (!fGif)
3620	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3621	else if (!pSvmTransient->fIsNestedGuest)
3622	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3623	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3624	}
3625	/*
3626	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3627	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3628	* it from the APIC device.
3629	*
3630	* For nested-guests, physical interrupts always take priority over virtual interrupts.
3631	* We don't need to inject nested-guest virtual interrupts here, we can let the hardware
3632	* do that work when we execute nested-guest code esp. since all the required information
3633	* is in the VMCB, unlike physical interrupts where we need to fetch the interrupt from
3634	* the virtual interrupt controller.
3635	*
3636	* See AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3637	*/
3638	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3639	&& !pVCpu->hm.s.fSingleInstruction)
3640	{
3641	bool const fBlockInt = !pSvmTransient->fIsNestedGuest ? !(pCtx->eflags.u32 & X86_EFL_IF)
3642	: CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx);
3643	if ( fGif
3644	&& !fBlockInt
3645	&& !fIntShadow)
3646	{
3647	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3648	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3649	{
3650	Log4(("Intercepting INTR -> #VMEXIT\n"));
3651	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3652	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3653	}
3654	#endif
3655	uint8_t u8Interrupt;
3656	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3657	if (RT_SUCCESS(rc))
3658	{
3659	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3660	SVMEVENT Event;
3661	Event.u = 0;
3662	Event.n.u1Valid = 1;
3663	Event.n.u8Vector = u8Interrupt;
3664	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3665	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3666	}
3667	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3668	{
3669	/*
3670	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3671	* updated eventually when the TPR is written by the guest.
3672	*/
3673	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3674	}
3675	else
3676	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3677	}
3678	else if (!fGif)
3679	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3680	else if (!pSvmTransient->fIsNestedGuest)
3681	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3682	/* else: for nested-guests, interrupt-window exiting will be picked up when merging VMCB controls. */
3683	}
3684
3685	return VINF_SUCCESS;
3686	}
3687
3688
3689	/**
3690	* Injects any pending events into the guest (or nested-guest).
3691	*
3692	* @param pVCpu The cross context virtual CPU structure.
3693	* @param pVmcb Pointer to the VM control block.
3694	*
3695	* @remarks Must only be called when we are guaranteed to enter
3696	* hardware-assisted SVM execution and not return to ring-3
3697	* prematurely.
3698	*/
3699	static void hmR0SvmInjectPendingEvent(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
3700	{
3701	Assert(!TRPMHasTrap(pVCpu));
3702	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3703
3704	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3705	#ifdef VBOX_STRICT
3706	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3707	bool const fGif = CPUMGetGuestGif(pCtx);
3708	bool fAllowInt = fGif;
3709	if (fGif)
3710	{
3711	/*
3712	* For nested-guests we have no way to determine if we're injecting a physical or
3713	* virtual interrupt at this point. Hence the partial verification below.
3714	*/
3715	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3716	fAllowInt = CPUMIsGuestSvmPhysIntrEnabled(pVCpu, pCtx) \|\| CPUMIsGuestSvmVirtIntrEnabled(pVCpu, pCtx);
3717	else
3718	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3719	}
3720	#endif
3721
3722	if (pVCpu->hm.s.Event.fPending)
3723	{
3724	SVMEVENT Event;
3725	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3726	Assert(Event.n.u1Valid);
3727
3728	/*
3729	* Validate event injection pre-conditions.
3730	*/
3731	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3732	{
3733	Assert(fAllowInt);
3734	Assert(!fIntShadow);
3735	}
3736	else if (Event.n.u3Type == SVM_EVENT_NMI)
3737	{
3738	Assert(fGif);
3739	Assert(!fIntShadow);
3740	}
3741
3742	/*
3743	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3744	* do this only when we are surely going to inject the NMI as otherwise if we return
3745	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3746	* SVM R0.
3747	*
3748	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3749	* which will set the VMCS field after actually delivering the NMI which we read on
3750	* VM-exit to determine the state.
3751	*/
3752	if ( Event.n.u3Type == SVM_EVENT_NMI
3753	&& Event.n.u8Vector == X86_XCPT_NMI
3754	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3755	{
3756	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3757	}
3758
3759	/*
3760	* Inject it (update VMCB for injection by the hardware).
3761	*/
3762	Log4(("Injecting pending HM event\n"));
3763	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
3764	pVCpu->hm.s.Event.fPending = false;
3765
3766	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3767	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3768	else
3769	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3770	}
3771	else
3772	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3773
3774	/*
3775	* We could have injected an NMI through IEM and continue guest execution using
3776	* hardware-assisted SVM. In which case, we would not have any events pending (above)
3777	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
3778	*/
3779	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
3780	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
3781
3782	/*
3783	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
3784	*
3785	* For nested-guests: We need to update it too for the scenario where IEM executes
3786	* the nested-guest but execution later continues here with an interrupt shadow active.
3787	*/
3788	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3789	}
3790
3791
3792	/**
3793	* Reports world-switch error and dumps some useful debug info.
3794	*
3795	* @param pVCpu The cross context virtual CPU structure.
3796	* @param rcVMRun The return code from VMRUN (or
3797	* VERR_SVM_INVALID_GUEST_STATE for invalid
3798	* guest-state).
3799	*/
3800	static void hmR0SvmReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun)
3801	{
3802	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3803	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
3804	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3805
3806	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3807	{
3808	#ifdef VBOX_STRICT
3809	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
3810	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3811	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3812	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3813	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3814	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3815	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3816	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3817	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3818	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3819	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3820	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3821
3822	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3823	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3824	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3825
3826	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3827	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3828	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3829	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
3830	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3831	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3832	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3833	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3834	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3835	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
3836	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3837	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3838
3839	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3840	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3841	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3842	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3843	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3844	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3845	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3846	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3847	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3848	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3849	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3850	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
3851	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
3852	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
3853	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3854	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3855	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3856	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3857	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3858	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3859
3860	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3861
3862	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3863	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3864
3865	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3866	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3867	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3868	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3869	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3870	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3871	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3872	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3873	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3874	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3875	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3876	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3877	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3878	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3879	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3880	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3881	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3882	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3883	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3884	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3885
3886	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3887	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3888
3889	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3890	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3891	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3892	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3893
3894	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3895	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3896
3897	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3898	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3899	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3900	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3901
3902	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3903	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3904	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3905	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3906	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3907	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3908	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3909
3910	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3911	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3912	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3913	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3914
3915	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3916	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3917	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3918
3919	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3920	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3921	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3922	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3923	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3924	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3925	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
3926	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3927	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3928	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3929	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3930	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3931
3932	NOREF(pVmcb);
3933	#endif /* VBOX_STRICT */
3934	}
3935	else
3936	Log4Func(("rcVMRun=%d\n", rcVMRun));
3937	}
3938
3939
3940	/**
3941	* Check per-VM and per-VCPU force flag actions that require us to go back to
3942	* ring-3 for one reason or another.
3943	*
3944	* @returns Strict VBox status code (information status code included).
3945	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3946	* ring-3.
3947	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3948	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3949	* interrupts)
3950	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3951	* all EMTs to be in ring-3.
3952	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3953	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3954	* to the EM loop.
3955	*
3956	* @param pVCpu The cross context virtual CPU structure.
3957	*/
3958	static VBOXSTRICTRC hmR0SvmCheckForceFlags(PVMCPUCC pVCpu)
3959	{
3960	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3961
3962	/* Could happen as a result of longjump. */
3963	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3964	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu), false /* fPdpesMapped */);
3965
3966	/* Update pending interrupts into the APIC's IRR. */
3967	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3968	APICUpdatePendingInterrupts(pVCpu);
3969
3970	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3971	if ( VM_FF_IS_ANY_SET(pVM, !pVCpu->hm.s.fSingleInstruction
3972	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3973	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction
3974	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3975	{
3976	/* Pending PGM C3 sync. */
3977	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3978	{
3979	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
3980	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3981	if (rc != VINF_SUCCESS)
3982	{
3983	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3984	return rc;
3985	}
3986	}
3987
3988	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3989	/* -XXX- what was that about single stepping? */
3990	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
3991	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3992	{
3993	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3994	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
3995	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3996	return rc;
3997	}
3998
3999	/* Pending VM request packets, such as hardware interrupts. */
4000	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
4001	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
4002	{
4003	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
4004	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4005	return VINF_EM_PENDING_REQUEST;
4006	}
4007
4008	/* Pending PGM pool flushes. */
4009	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4010	{
4011	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
4012	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4013	return VINF_PGM_POOL_FLUSH_PENDING;
4014	}
4015
4016	/* Pending DMA requests. */
4017	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
4018	{
4019	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
4020	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4021	return VINF_EM_RAW_TO_R3;
4022	}
4023	}
4024
4025	return VINF_SUCCESS;
4026	}
4027
4028
4029	/**
4030	* Does the preparations before executing guest code in AMD-V.
4031	*
4032	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4033	* recompiler. We must be cautious what we do here regarding committing
4034	* guest-state information into the VMCB assuming we assuredly execute the guest
4035	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4036	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4037	* that the recompiler can (and should) use them when it resumes guest
4038	* execution. Otherwise such operations must be done when we can no longer
4039	* exit to ring-3.
4040	*
4041	* @returns Strict VBox status code (informational status codes included).
4042	* @retval VINF_SUCCESS if we can proceed with running the guest.
4043	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4044	*
4045	* @param pVCpu The cross context virtual CPU structure.
4046	* @param pSvmTransient Pointer to the SVM transient structure.
4047	*/
4048	static VBOXSTRICTRC hmR0SvmPreRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4049	{
4050	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4051
4052	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
4053	if (pSvmTransient->fIsNestedGuest)
4054	{
4055	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4056	return VINF_EM_RESCHEDULE_REM;
4057	}
4058	#endif
4059
4060	/* Check force flag actions that might require us to go back to ring-3. */
4061	VBOXSTRICTRC rc = hmR0SvmCheckForceFlags(pVCpu);
4062	if (rc != VINF_SUCCESS)
4063	return rc;
4064
4065	if (TRPMHasTrap(pVCpu))
4066	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4067	else if (!pVCpu->hm.s.Event.fPending)
4068	{
4069	rc = hmR0SvmEvaluatePendingEvent(pVCpu, pSvmTransient);
4070	if ( rc != VINF_SUCCESS
4071	\|\| pSvmTransient->fIsNestedGuest != CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4072	{
4073	/* If a nested-guest VM-exit occurred, bail. */
4074	if (pSvmTransient->fIsNestedGuest)
4075	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4076	return rc;
4077	}
4078	}
4079
4080	/*
4081	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4082	* Just do it in software, see @bugref{8411}.
4083	* NB: If we could continue a task switch exit we wouldn't need to do this.
4084	*/
4085	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4086	if (RT_UNLIKELY( !g_fHmSvmFeatures
4087	&& pVCpu->hm.s.Event.fPending
4088	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4089	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4090
4091	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4092	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4093	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4094	#endif
4095
4096	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4097	/*
4098	* Set up the nested-guest VMCB for execution using hardware-assisted SVM.
4099	*/
4100	if (pSvmTransient->fIsNestedGuest)
4101	hmR0SvmSetupVmcbNested(pVCpu);
4102	#endif
4103
4104	/*
4105	* Export the guest state bits that are not shared with the host in any way as we can
4106	* longjmp or get preempted in the midst of exporting some of the state.
4107	*/
4108	rc = hmR0SvmExportGuestState(pVCpu, pSvmTransient);
4109	AssertRCReturn(rc, rc);
4110	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4111
4112	/* Ensure we've cached (and hopefully modified) the nested-guest VMCB for execution using hardware-assisted SVM. */
4113	Assert(!pSvmTransient->fIsNestedGuest \|\| pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4114
4115	/*
4116	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4117	* world-switch so we can update it on the way back if the guest changed the TPR.
4118	*/
4119	if (pVCpu->hmr0.s.svm.fSyncVTpr)
4120	{
4121	Assert(!pSvmTransient->fIsNestedGuest);
4122	PCSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4123	if (pVM->hm.s.fTprPatchingActive)
4124	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4125	else
4126	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4127	}
4128
4129	/*
4130	* No longjmps to ring-3 from this point on!!!
4131	*
4132	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4133	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4134	*/
4135	VMMRZCallRing3Disable(pVCpu);
4136
4137	/*
4138	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4139	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4140	* preemption disabled for a while. Since this is purly to aid the
4141	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4142	* disable interrupt on NT.
4143	*
4144	* We need to check for force-flags that could've possible been altered since we last
4145	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4146	* see @bugref{6398}).
4147	*
4148	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4149	* to ring-3 before executing guest code.
4150	*/
4151	pSvmTransient->fEFlags = ASMIntDisableFlags();
4152	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4153	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4154	{
4155	ASMSetFlags(pSvmTransient->fEFlags);
4156	VMMRZCallRing3Enable(pVCpu);
4157	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4158	return VINF_EM_RAW_TO_R3;
4159	}
4160	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4161	{
4162	ASMSetFlags(pSvmTransient->fEFlags);
4163	VMMRZCallRing3Enable(pVCpu);
4164	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4165	return VINF_EM_RAW_INTERRUPT;
4166	}
4167
4168	return VINF_SUCCESS;
4169	}
4170
4171
4172	/**
4173	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4174	* doing so.
4175	*
4176	* This means there is no backing out to ring-3 or anywhere else at this point.
4177	*
4178	* @param pVCpu The cross context virtual CPU structure.
4179	* @param pSvmTransient Pointer to the SVM transient structure.
4180	*
4181	* @remarks Called with preemption disabled.
4182	* @remarks No-long-jump zone!!!
4183	*/
4184	static void hmR0SvmPreRunGuestCommitted(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4185	{
4186	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4187	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4188
4189	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4190	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4191
4192	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4193	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4194
4195	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4196
4197	if (!CPUMIsGuestFPUStateActive(pVCpu))
4198	{
4199	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4200	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4201	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4202	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4203	}
4204
4205	/* Load the state shared between host and guest (FPU, debug). */
4206	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4207	hmR0SvmExportSharedState(pVCpu, pVmcb);
4208
4209	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4210	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4211
4212	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
4213	RTCPUID const idHostCpu = pHostCpu->idCpu;
4214	bool const fMigratedHostCpu = idHostCpu != pVCpu->hmr0.s.idLastCpu;
4215
4216	/* Setup TSC offsetting. */
4217	if ( pSvmTransient->fUpdateTscOffsetting
4218	\|\| fMigratedHostCpu)
4219	{
4220	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4221	pSvmTransient->fUpdateTscOffsetting = false;
4222	}
4223
4224	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
4225	if (!(pVmcb->ctrl.u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
4226	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4227	else
4228	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4229
4230	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4231	if (fMigratedHostCpu)
4232	pVmcb->ctrl.u32VmcbCleanBits = 0;
4233
4234	/* Store status of the shared guest-host state at the time of VMRUN. */
4235	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4236	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4237
4238	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4239	uint8_t *pbMsrBitmap;
4240	if (!pSvmTransient->fIsNestedGuest)
4241	pbMsrBitmap = (uint8_t *)pVCpu->hmr0.s.svm.pvMsrBitmap;
4242	else
4243	{
4244	/** @todo We could perhaps optimize this by monitoring if the guest modifies its
4245	* MSRPM and only perform this if it changed also use EVEX.POR when it
4246	* does. */
4247	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4248
4249	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4250	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4251	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4252	}
4253	#else
4254	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4255	#endif
4256
4257	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4258	/* Flush the appropriate tagged-TLB entries. */
4259	hmR0SvmFlushTaggedTlb(pHostCpu, pVCpu, pVmcb);
4260	Assert(pVCpu->hmr0.s.idLastCpu == idHostCpu);
4261
4262	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4263
4264	TMNotifyStartOfExecution(pVM, pVCpu); /* Finally, notify TM to resume its clocks as we're about
4265	to start executing. */
4266
4267	/*
4268	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4269	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4270	*
4271	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4272	*/
4273	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4274	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4275	{
4276	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4277	pVCpu->hmr0.s.svm.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4278	if (uGuestTscAux != pVCpu->hmr0.s.svm.u64HostTscAux)
4279	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4280	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4281	pSvmTransient->fRestoreTscAuxMsr = true;
4282	}
4283	else
4284	{
4285	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4286	pSvmTransient->fRestoreTscAuxMsr = false;
4287	}
4288	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4289
4290	/*
4291	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4292	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4293	* from the VMCB.
4294	*/
4295	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pSvmTransient->fIsNestedGuest);
4296	if (!fSupportsVmcbCleanBits)
4297	pVmcb->ctrl.u32VmcbCleanBits = 0;
4298	}
4299
4300
4301	/**
4302	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4303	*
4304	* @returns VBox strict status code.
4305	* @param pVCpu The cross context virtual CPU structure.
4306	* @param HCPhysVmcb The host physical address of the VMCB.
4307	*
4308	* @remarks No-long-jump zone!!!
4309	*/
4310	DECLINLINE(int) hmR0SvmRunGuest(PVMCPUCC pVCpu, RTHCPHYS HCPhysVmcb)
4311	{
4312	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4313	pVCpu->cpum.GstCtx.fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4314	return pVCpu->hmr0.s.svm.pfnVMRun(pVCpu->CTX_SUFF(pVM), pVCpu, HCPhysVmcb);
4315	}
4316
4317
4318	/**
4319	* Performs some essential restoration of state after running guest (or
4320	* nested-guest) code in AMD-V.
4321	*
4322	* @param pVCpu The cross context virtual CPU structure.
4323	* @param pSvmTransient Pointer to the SVM transient structure.
4324	* @param rcVMRun Return code of VMRUN.
4325	*
4326	* @remarks Called with interrupts disabled.
4327	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4328	* unconditionally when it is safe to do so.
4329	*/
4330	static void hmR0SvmPostRunGuest(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient, VBOXSTRICTRC rcVMRun)
4331	{
4332	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4333
4334	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4335	ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4336
4337	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4338	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4339
4340	/* TSC read must be done early for maximum accuracy. */
4341	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4342	{
4343	if (!pSvmTransient->fIsNestedGuest)
4344	TMCpuTickSetLastSeen(pVCpu, pVCpu->hmr0.s.uTscExit + pVmcbCtrl->u64TSCOffset);
4345	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4346	else
4347	{
4348	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMNotifySvmNstGstVmexit(). */
4349	uint64_t const uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, pVCpu->hmr0.s.uTscExit + pVmcbCtrl->u64TSCOffset);
4350	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4351	}
4352	#endif
4353	}
4354
4355	if (pSvmTransient->fRestoreTscAuxMsr)
4356	{
4357	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4358	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4359	if (u64GuestTscAuxMsr != pVCpu->hmr0.s.svm.u64HostTscAux)
4360	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hmr0.s.svm.u64HostTscAux);
4361	}
4362
4363	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4364	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4365	TMNotifyEndOfExecution(pVM, pVCpu, pVCpu->hmr0.s.uTscExit); /* Notify TM that the guest is no longer running. */
4366	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4367
4368	Assert(!(ASMGetFlags() & X86_EFL_IF));
4369	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4370	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4371
4372	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4373	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4374	{
4375	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", VBOXSTRICTRC_VAL(rcVMRun)));
4376	return;
4377	}
4378
4379	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4380	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4381	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4382	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4383
4384	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4385	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4386	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4387	#else
4388	/*
4389	* Always import the following:
4390	*
4391	* - RIP for exit optimizations and evaluating event injection on re-entry.
4392	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4393	* state on preemption.
4394	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4395	* - CS for exit optimizations.
4396	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4397	* assembly switcher code.
4398	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4399	*/
4400	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4401	\| CPUMCTX_EXTRN_RFLAGS
4402	\| CPUMCTX_EXTRN_RAX
4403	\| CPUMCTX_EXTRN_RSP
4404	\| CPUMCTX_EXTRN_CS
4405	\| CPUMCTX_EXTRN_HWVIRT
4406	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4407	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4408	\| HMSVM_CPUMCTX_SHARED_STATE);
4409	#endif
4410
4411	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4412	&& pVCpu->hmr0.s.svm.fSyncVTpr)
4413	{
4414	Assert(!pSvmTransient->fIsNestedGuest);
4415	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4416	if ( pVM->hm.s.fTprPatchingActive
4417	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4418	{
4419	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4420	AssertRC(rc);
4421	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4422	}
4423	/* Sync TPR when we aren't intercepting CR8 writes. */
4424	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4425	{
4426	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4427	AssertRC(rc);
4428	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4429	}
4430	}
4431
4432	#ifdef DEBUG_ramshankar
4433	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4434	{
4435	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4436	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4437	0 /* uVerbose */);
4438	}
4439	#endif
4440
4441	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4442	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4443	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, pVCpu->hmr0.s.uTscExit);
4444	}
4445
4446
4447	/**
4448	* Runs the guest code using AMD-V.
4449	*
4450	* @returns Strict VBox status code.
4451	* @param pVCpu The cross context virtual CPU structure.
4452	* @param pcLoops Pointer to the number of executed loops.
4453	*/
4454	static VBOXSTRICTRC hmR0SvmRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
4455	{
4456	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4457	Assert(pcLoops);
4458	Assert(*pcLoops <= cMaxResumeLoops);
4459
4460	SVMTRANSIENT SvmTransient;
4461	RT_ZERO(SvmTransient);
4462	SvmTransient.fUpdateTscOffsetting = true;
4463	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4464
4465	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4466	for (;;)
4467	{
4468	Assert(!HMR0SuspendPending());
4469	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4470
4471	/* Preparatory work for running nested-guest code, this may force us to return to
4472	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4473	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4474	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4475	if (rc != VINF_SUCCESS)
4476	break;
4477
4478	/*
4479	* No longjmps to ring-3 from this point on!!!
4480	*
4481	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4482	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4483	*/
4484	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4485	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4486
4487	/* Restore any residual host-state and save any bits shared between host and guest
4488	into the guest-CPU state. Re-enables interrupts! */
4489	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4490
4491	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4492	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4493	{
4494	if (rc == VINF_SUCCESS)
4495	rc = VERR_SVM_INVALID_GUEST_STATE;
4496	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4497	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4498	break;
4499	}
4500
4501	/* Handle the #VMEXIT. */
4502	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4503	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4504	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4505	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4506	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4507	if (rc != VINF_SUCCESS)
4508	break;
4509	if (++(*pcLoops) >= cMaxResumeLoops)
4510	{
4511	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4512	rc = VINF_EM_RAW_INTERRUPT;
4513	break;
4514	}
4515	}
4516
4517	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4518	return rc;
4519	}
4520
4521
4522	/**
4523	* Runs the guest code using AMD-V in single step mode.
4524	*
4525	* @returns Strict VBox status code.
4526	* @param pVCpu The cross context virtual CPU structure.
4527	* @param pcLoops Pointer to the number of executed loops.
4528	*/
4529	static VBOXSTRICTRC hmR0SvmRunGuestCodeStep(PVMCPUCC pVCpu, uint32_t *pcLoops)
4530	{
4531	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
4532	Assert(pcLoops);
4533	Assert(*pcLoops <= cMaxResumeLoops);
4534
4535	SVMTRANSIENT SvmTransient;
4536	RT_ZERO(SvmTransient);
4537	SvmTransient.fUpdateTscOffsetting = true;
4538	SvmTransient.pVmcb = pVCpu->hmr0.s.svm.pVmcb;
4539
4540	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4541	uint16_t const uCsStart = pCtx->cs.Sel;
4542	uint64_t const uRipStart = pCtx->rip;
4543
4544	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_5;
4545	for (;;)
4546	{
4547	Assert(!HMR0SuspendPending());
4548	AssertMsg(pVCpu->hmr0.s.idEnteredCpu == RTMpCpuId(),
4549	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hmr0.s.idEnteredCpu,
4550	(unsigned)RTMpCpuId(), *pcLoops));
4551
4552	/* Preparatory work for running nested-guest code, this may force us to return to
4553	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4554	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4555	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4556	if (rc != VINF_SUCCESS)
4557	break;
4558
4559	/*
4560	* No longjmps to ring-3 from this point on!!!
4561	*
4562	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4563	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4564	*/
4565	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4566
4567	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hmr0.s.svm.HCPhysVmcb);
4568
4569	/* Restore any residual host-state and save any bits shared between host and guest
4570	into the guest-CPU state. Re-enables interrupts! */
4571	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4572
4573	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4574	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4575	{
4576	if (rc == VINF_SUCCESS)
4577	rc = VERR_SVM_INVALID_GUEST_STATE;
4578	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4579	hmR0SvmReportWorldSwitchError(pVCpu, VBOXSTRICTRC_VAL(rc));
4580	return rc;
4581	}
4582
4583	/* Handle the #VMEXIT. */
4584	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4585	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4586	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hmr0.s.svm.pVmcb);
4587	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4588	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4589	if (rc != VINF_SUCCESS)
4590	break;
4591	if (++(*pcLoops) >= cMaxResumeLoops)
4592	{
4593	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4594	rc = VINF_EM_RAW_INTERRUPT;
4595	break;
4596	}
4597
4598	/*
4599	* Did the RIP change, if so, consider it a single step.
4600	* Otherwise, make sure one of the TFs gets set.
4601	*/
4602	if ( pCtx->rip != uRipStart
4603	\|\| pCtx->cs.Sel != uCsStart)
4604	{
4605	rc = VINF_EM_DBG_STEPPED;
4606	break;
4607	}
4608	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4609	}
4610
4611	/*
4612	* Clear the X86_EFL_TF if necessary.
4613	*/
4614	if (pVCpu->hmr0.s.fClearTrapFlag)
4615	{
4616	pVCpu->hmr0.s.fClearTrapFlag = false;
4617	pCtx->eflags.Bits.u1TF = 0;
4618	}
4619
4620	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4621	return rc;
4622	}
4623
4624	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4625	/**
4626	* Runs the nested-guest code using AMD-V.
4627	*
4628	* @returns Strict VBox status code.
4629	* @param pVCpu The cross context virtual CPU structure.
4630	* @param pcLoops Pointer to the number of executed loops. If we're switching
4631	* from the guest-code execution loop to this nested-guest
4632	* execution loop pass the remainder value, else pass 0.
4633	*/
4634	static VBOXSTRICTRC hmR0SvmRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
4635	{
4636	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4637	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4638	Assert(pcLoops);
4639	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops);
4640	/** @todo r=bird: Sharing this with ring-3 isn't safe in the long run, I fear... */
4641	RTHCPHYS const HCPhysVmcb = GVMMR0ConvertGVMPtr2HCPhys(pVCpu->pGVM, &pCtx->hwvirt.svm.Vmcb);
4642
4643	SVMTRANSIENT SvmTransient;
4644	RT_ZERO(SvmTransient);
4645	SvmTransient.fUpdateTscOffsetting = true;
4646	SvmTransient.pVmcb = &pCtx->hwvirt.svm.Vmcb;
4647	SvmTransient.fIsNestedGuest = true;
4648
4649	VBOXSTRICTRC rc = VERR_INTERNAL_ERROR_4;
4650	for (;;)
4651	{
4652	Assert(!HMR0SuspendPending());
4653	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4654
4655	/* Preparatory work for running nested-guest code, this may force us to return to
4656	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4657	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4658	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4659	if ( rc != VINF_SUCCESS
4660	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4661	break;
4662
4663	/*
4664	* No longjmps to ring-3 from this point on!!!
4665	*
4666	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4667	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4668	*/
4669	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4670
4671	rc = hmR0SvmRunGuest(pVCpu, HCPhysVmcb);
4672
4673	/* Restore any residual host-state and save any bits shared between host and guest
4674	into the guest-CPU state. Re-enables interrupts! */
4675	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4676
4677	if (RT_LIKELY( rc == VINF_SUCCESS
4678	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4679	{ /* extremely likely */ }
4680	else
4681	{
4682	/* VMRUN failed, shouldn't really happen, Guru. */
4683	if (rc != VINF_SUCCESS)
4684	break;
4685
4686	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4687	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4688	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4689	rc = IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0);
4690	break;
4691	}
4692
4693	/* Handle the #VMEXIT. */
4694	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4695	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4696	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, &pCtx->hwvirt.svm.Vmcb);
4697	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
4698	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4699	if (rc == VINF_SUCCESS)
4700	{
4701	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4702	{
4703	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
4704	rc = VINF_SVM_VMEXIT;
4705	}
4706	else
4707	{
4708	if (++(*pcLoops) <= pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops)
4709	continue;
4710	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4711	rc = VINF_EM_RAW_INTERRUPT;
4712	}
4713	}
4714	else
4715	Assert(rc != VINF_SVM_VMEXIT);
4716	break;
4717	/** @todo NSTSVM: handle single-stepping. */
4718	}
4719
4720	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4721	return rc;
4722	}
4723	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
4724
4725
4726	/**
4727	* Runs the guest code using AMD-V.
4728	*
4729	* @returns Strict VBox status code.
4730	* @param pVCpu The cross context virtual CPU structure.
4731	*/
4732	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPUCC pVCpu)
4733	{
4734	AssertPtr(pVCpu);
4735	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4736	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4737	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4738	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4739
4740	uint32_t cLoops = 0;
4741	VBOXSTRICTRC rc;
4742	for (;;)
4743	{
4744	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4745	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(pCtx);
4746	#else
4747	NOREF(pCtx);
4748	bool const fInNestedGuestMode = false;
4749	#endif
4750	if (!fInNestedGuestMode)
4751	{
4752	if (!pVCpu->hm.s.fSingleInstruction)
4753	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
4754	else
4755	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
4756	}
4757	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4758	else
4759	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
4760
4761	if (rc == VINF_SVM_VMRUN)
4762	{
4763	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4764	continue;
4765	}
4766	if (rc == VINF_SVM_VMEXIT)
4767	{
4768	Assert(!CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
4769	continue;
4770	}
4771	#endif
4772	break;
4773	}
4774
4775	/* Fixup error codes. */
4776	if (rc == VERR_EM_INTERPRETER)
4777	rc = VINF_EM_RAW_EMULATE_INSTR;
4778	else if (rc == VINF_EM_RESET)
4779	rc = VINF_EM_TRIPLE_FAULT;
4780
4781	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4782	rc = hmR0SvmExitToRing3(pVCpu, rc);
4783	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
4784	Assert(!VMMR0AssertionIsNotificationSet(pVCpu));
4785	return rc;
4786	}
4787
4788
4789	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4790	/**
4791	* Determines whether the given I/O access should cause a nested-guest \#VMEXIT.
4792	*
4793	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4794	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4795	*/
4796	static bool hmR0SvmIsIoInterceptSet(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4797	{
4798	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4799	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4800	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4801	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4802	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
4803	const bool fRep = pIoExitInfo->n.u1Rep;
4804	const bool fStrIo = pIoExitInfo->n.u1Str;
4805
4806	return CPUMIsSvmIoInterceptSet(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4807	NULL /* pIoExitInfo */);
4808	}
4809
4810
4811	/**
4812	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4813	* SVM_EXIT_INVALID).
4814	*
4815	* @returns VBox status code (informational status codes included).
4816	* @param pVCpu The cross context virtual CPU structure.
4817	* @param pSvmTransient Pointer to the SVM transient structure.
4818	*/
4819	static VBOXSTRICTRC hmR0SvmHandleExitNested(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
4820	{
4821	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4822	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4823	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4824
4825	/*
4826	* We import the complete state here because we use separate VMCBs for the guest and the
4827	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
4828	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
4829	*/
4830	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4831	do { \
4832	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
4833	return IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); \
4834	} while (0)
4835
4836	/*
4837	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
4838	* nested-guest. If it isn't, it should be handled by the (outer) guest.
4839	*/
4840	PSVMVMCB pVmcbNstGst = &pVCpu->cpum.GstCtx.hwvirt.svm.Vmcb;
4841	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4842	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4843	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
4844	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
4845	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
4846
4847	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
4848	switch (uExitCode)
4849	{
4850	case SVM_EXIT_CPUID:
4851	{
4852	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
4853	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4854	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
4855	}
4856
4857	case SVM_EXIT_RDTSC:
4858	{
4859	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
4860	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4861	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
4862	}
4863
4864	case SVM_EXIT_RDTSCP:
4865	{
4866	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
4867	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4868	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
4869	}
4870
4871	case SVM_EXIT_MONITOR:
4872	{
4873	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
4874	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4875	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
4876	}
4877
4878	case SVM_EXIT_MWAIT:
4879	{
4880	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
4881	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4882	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
4883	}
4884
4885	case SVM_EXIT_HLT:
4886	{
4887	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
4888	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4889	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
4890	}
4891
4892	case SVM_EXIT_MSR:
4893	{
4894	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
4895	{
4896	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
4897	uint16_t offMsrpm;
4898	uint8_t uMsrpmBit;
4899	int rc = CPUMGetSvmMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
4900	if (RT_SUCCESS(rc))
4901	{
4902	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
4903	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
4904
4905	uint8_t const * const pbMsrBitmap = &pVCpu->cpum.GstCtx.hwvirt.svm.abMsrBitmap[offMsrpm];
4906	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
4907	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
4908
4909	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4910	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
4911	{
4912	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4913	}
4914	}
4915	else
4916	{
4917	/*
4918	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
4919	* See AMD-V spec. "15.11 MSR Intercepts".
4920	*/
4921	Assert(rc == VERR_OUT_OF_RANGE);
4922	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4923	}
4924	}
4925	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
4926	}
4927
4928	case SVM_EXIT_IOIO:
4929	{
4930	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
4931	{
4932	SVMIOIOEXITINFO IoExitInfo;
4933	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
4934	bool const fIntercept = hmR0SvmIsIoInterceptSet(pVCpu->cpum.GstCtx.hwvirt.svm.abIoBitmap, &IoExitInfo);
4935	if (fIntercept)
4936	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4937	}
4938	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
4939	}
4940
4941	case SVM_EXIT_XCPT_PF:
4942	{
4943	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4944	if (pVM->hmr0.s.fNestedPaging)
4945	{
4946	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
4947	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
4948
4949	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
4950	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
4951	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
4952
4953	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
4954	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
4955	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
4956	return VINF_SUCCESS;
4957	}
4958	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
4959	}
4960
4961	case SVM_EXIT_XCPT_UD:
4962	{
4963	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
4964	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4965	hmR0SvmSetPendingXcptUD(pVCpu);
4966	return VINF_SUCCESS;
4967	}
4968
4969	case SVM_EXIT_XCPT_MF:
4970	{
4971	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
4972	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4973	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
4974	}
4975
4976	case SVM_EXIT_XCPT_DB:
4977	{
4978	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
4979	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4980	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
4981	}
4982
4983	case SVM_EXIT_XCPT_AC:
4984	{
4985	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
4986	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4987	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
4988	}
4989
4990	case SVM_EXIT_XCPT_BP:
4991	{
4992	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
4993	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
4994	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
4995	}
4996
4997	case SVM_EXIT_READ_CR0:
4998	case SVM_EXIT_READ_CR3:
4999	case SVM_EXIT_READ_CR4:
5000	{
5001	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5002	if (CPUMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5003	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5004	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5005	}
5006
5007	case SVM_EXIT_CR0_SEL_WRITE:
5008	{
5009	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5010	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5011	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5012	}
5013
5014	case SVM_EXIT_WRITE_CR0:
5015	case SVM_EXIT_WRITE_CR3:
5016	case SVM_EXIT_WRITE_CR4:
5017	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5018	{
5019	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5020	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5021
5022	if (CPUMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5023	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5024	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5025	}
5026
5027	case SVM_EXIT_PAUSE:
5028	{
5029	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5030	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5031	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5032	}
5033
5034	case SVM_EXIT_VINTR:
5035	{
5036	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5037	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5038	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5039	}
5040
5041	case SVM_EXIT_INTR:
5042	case SVM_EXIT_NMI:
5043	case SVM_EXIT_SMI:
5044	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5045	{
5046	/*
5047	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5048	*
5049	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5050	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5051	* nested-guest #VMEXIT.
5052	*
5053	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5054	* while trying to inject interrupts, see comment at the top of this function.
5055	*/
5056	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5057	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5058	}
5059
5060	case SVM_EXIT_FERR_FREEZE:
5061	{
5062	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5063	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5064	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5065	}
5066
5067	case SVM_EXIT_INVLPG:
5068	{
5069	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5070	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5071	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5072	}
5073
5074	case SVM_EXIT_WBINVD:
5075	{
5076	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5077	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5078	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5079	}
5080
5081	case SVM_EXIT_INVD:
5082	{
5083	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5084	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5085	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5086	}
5087
5088	case SVM_EXIT_RDPMC:
5089	{
5090	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5091	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5092	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5093	}
5094
5095	default:
5096	{
5097	switch (uExitCode)
5098	{
5099	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5100	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5101	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5102	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5103	{
5104	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5105	if (CPUMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5106	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5107	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5108	}
5109
5110	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5111	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5112	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5113	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5114	{
5115	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5116	if (CPUMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5117	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5118	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5119	}
5120
5121	case SVM_EXIT_XCPT_DE:
5122	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5123	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5124	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5125	case SVM_EXIT_XCPT_OF:
5126	case SVM_EXIT_XCPT_BR:
5127	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5128	case SVM_EXIT_XCPT_NM:
5129	case SVM_EXIT_XCPT_DF:
5130	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5131	case SVM_EXIT_XCPT_TS:
5132	case SVM_EXIT_XCPT_NP:
5133	case SVM_EXIT_XCPT_SS:
5134	case SVM_EXIT_XCPT_GP:
5135	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5136	case SVM_EXIT_XCPT_15: /* Reserved. */
5137	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5138	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5139	case SVM_EXIT_XCPT_MC:
5140	case SVM_EXIT_XCPT_XF:
5141	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5142	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5143	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5144	{
5145	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5146	if (CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5147	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5148	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5149	}
5150
5151	case SVM_EXIT_XSETBV:
5152	{
5153	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5154	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5155	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5156	}
5157
5158	case SVM_EXIT_TASK_SWITCH:
5159	{
5160	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5161	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5162	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5163	}
5164
5165	case SVM_EXIT_IRET:
5166	{
5167	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5168	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5169	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5170	}
5171
5172	case SVM_EXIT_SHUTDOWN:
5173	{
5174	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5175	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5176	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5177	}
5178
5179	case SVM_EXIT_VMMCALL:
5180	{
5181	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5182	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5183	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5184	}
5185
5186	case SVM_EXIT_CLGI:
5187	{
5188	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5189	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5190	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5191	}
5192
5193	case SVM_EXIT_STGI:
5194	{
5195	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5196	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5197	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5198	}
5199
5200	case SVM_EXIT_VMLOAD:
5201	{
5202	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5203	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5204	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5205	}
5206
5207	case SVM_EXIT_VMSAVE:
5208	{
5209	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5210	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5211	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5212	}
5213
5214	case SVM_EXIT_INVLPGA:
5215	{
5216	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5217	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5218	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5219	}
5220
5221	case SVM_EXIT_VMRUN:
5222	{
5223	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5224	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5225	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5226	}
5227
5228	case SVM_EXIT_RSM:
5229	{
5230	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5231	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5232	hmR0SvmSetPendingXcptUD(pVCpu);
5233	return VINF_SUCCESS;
5234	}
5235
5236	case SVM_EXIT_SKINIT:
5237	{
5238	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5239	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5240	hmR0SvmSetPendingXcptUD(pVCpu);
5241	return VINF_SUCCESS;
5242	}
5243
5244	case SVM_EXIT_NPF:
5245	{
5246	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5247	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5248	}
5249
5250	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5251	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5252
5253	default:
5254	{
5255	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5256	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5257	return VERR_SVM_UNKNOWN_EXIT;
5258	}
5259	}
5260	}
5261	}
5262	/* not reached */
5263
5264	#undef NST_GST_VMEXIT_CALL_RET
5265	}
5266	#endif
5267
5268
5269	/**
5270	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5271	*
5272	* @returns Strict VBox status code (informational status codes included).
5273	* @param pVCpu The cross context virtual CPU structure.
5274	* @param pSvmTransient Pointer to the SVM transient structure.
5275	*/
5276	static VBOXSTRICTRC hmR0SvmHandleExit(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5277	{
5278	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5279	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5280
5281	#ifdef DEBUG_ramshankar
5282	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5283	do { \
5284	if ((a_fDbg) == 1) \
5285	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5286	int rc = a_CallExpr; \
5287	if ((a_fDbg) == 1) \
5288	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5289	return rc; \
5290	} while (0)
5291	#else
5292	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5293	#endif
5294
5295	/*
5296	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5297	* for most guests under normal workloads (for some definition of "normal").
5298	*/
5299	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5300	switch (uExitCode)
5301	{
5302	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5303	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5304	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5305	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5306	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5307	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5308	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5309	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5310	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5311	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5312
5313	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5314	case SVM_EXIT_INTR:
5315	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5316
5317	case SVM_EXIT_READ_CR0:
5318	case SVM_EXIT_READ_CR3:
5319	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5320
5321	case SVM_EXIT_CR0_SEL_WRITE:
5322	case SVM_EXIT_WRITE_CR0:
5323	case SVM_EXIT_WRITE_CR3:
5324	case SVM_EXIT_WRITE_CR4:
5325	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5326
5327	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5328	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5329	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5330	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5331	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5332	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5333	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5334	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5335	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5336	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5337	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5338	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5339	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5340	case SVM_EXIT_XCPT_GP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptGP(pVCpu, pSvmTransient));
5341	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5342	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5343
5344	default:
5345	{
5346	switch (pSvmTransient->u64ExitCode)
5347	{
5348	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5349	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5350	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5351	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5352	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5353
5354	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5355	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5356	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5357	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5358	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5359
5360	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5361	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5362
5363	case SVM_EXIT_SMI:
5364	case SVM_EXIT_INIT:
5365	{
5366	/*
5367	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5368	* If it ever does, we want to know about it so log the exit code and bail.
5369	*/
5370	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5371	}
5372
5373	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5374	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5375	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5376	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5377	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5378	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5379	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5380	#else
5381	case SVM_EXIT_CLGI:
5382	case SVM_EXIT_STGI:
5383	case SVM_EXIT_VMLOAD:
5384	case SVM_EXIT_VMSAVE:
5385	case SVM_EXIT_INVLPGA:
5386	case SVM_EXIT_VMRUN:
5387	#endif
5388	case SVM_EXIT_RSM:
5389	case SVM_EXIT_SKINIT:
5390	{
5391	hmR0SvmSetPendingXcptUD(pVCpu);
5392	return VINF_SUCCESS;
5393	}
5394
5395	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5396	case SVM_EXIT_XCPT_DE:
5397	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5398	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5399	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5400	case SVM_EXIT_XCPT_OF:
5401	case SVM_EXIT_XCPT_BR:
5402	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5403	case SVM_EXIT_XCPT_NM:
5404	case SVM_EXIT_XCPT_DF:
5405	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5406	case SVM_EXIT_XCPT_TS:
5407	case SVM_EXIT_XCPT_NP:
5408	case SVM_EXIT_XCPT_SS:
5409	/* SVM_EXIT_XCPT_GP: / / Handled above. */
5410	/* SVM_EXIT_XCPT_PF: */
5411	case SVM_EXIT_XCPT_15: /* Reserved. */
5412	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5413	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5414	case SVM_EXIT_XCPT_MC:
5415	case SVM_EXIT_XCPT_XF:
5416	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5417	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5418	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5419	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5420	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5421
5422	default:
5423	{
5424	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5425	pVCpu->hm.s.u32HMError = uExitCode;
5426	return VERR_SVM_UNKNOWN_EXIT;
5427	}
5428	}
5429	}
5430	}
5431	/* not reached */
5432	#undef VMEXIT_CALL_RET
5433	}
5434
5435
5436	#ifdef VBOX_STRICT
5437	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5438	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5439	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5440
5441	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5442	do \
5443	{ \
5444	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5445	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5446	} while (0)
5447
5448	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5449	do { \
5450	AssertPtr((a_pVCpu)); \
5451	AssertPtr((a_pSvmTransient)); \
5452	Assert(ASMIntAreEnabled()); \
5453	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5454	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5455	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5456	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5457	if (!VMMRZCallRing3IsEnabled((a_pVCpu))) \
5458	HMSVM_ASSERT_PREEMPT_CPUID(); \
5459	} while (0)
5460	#else
5461	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5462	do { \
5463	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5464	} while (0)
5465	#endif
5466
5467
5468	/**
5469	* Gets the IEM exception flags for the specified SVM event.
5470	*
5471	* @returns The IEM exception flags.
5472	* @param pEvent Pointer to the SVM event.
5473	*
5474	* @remarks This function currently only constructs flags required for
5475	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5476	* and CR2 aspects of an exception are not included).
5477	*/
5478	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5479	{
5480	uint8_t const uEventType = pEvent->n.u3Type;
5481	uint32_t fIemXcptFlags;
5482	switch (uEventType)
5483	{
5484	case SVM_EVENT_EXCEPTION:
5485	/*
5486	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5487	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5488	*/
5489	if (pEvent->n.u8Vector == X86_XCPT_BP)
5490	{
5491	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5492	break;
5493	}
5494	if (pEvent->n.u8Vector == X86_XCPT_OF)
5495	{
5496	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5497	break;
5498	}
5499	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5500	RT_FALL_THRU();
5501	case SVM_EVENT_NMI:
5502	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5503	break;
5504
5505	case SVM_EVENT_EXTERNAL_IRQ:
5506	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5507	break;
5508
5509	case SVM_EVENT_SOFTWARE_INT:
5510	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5511	break;
5512
5513	default:
5514	fIemXcptFlags = 0;
5515	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5516	break;
5517	}
5518	return fIemXcptFlags;
5519	}
5520
5521
5522	/**
5523	* Handle a condition that occurred while delivering an event through the guest
5524	* IDT.
5525	*
5526	* @returns VBox status code (informational error codes included).
5527	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5528	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5529	* continue execution of the guest which will delivery the \#DF.
5530	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5531	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5532	*
5533	* @param pVCpu The cross context virtual CPU structure.
5534	* @param pSvmTransient Pointer to the SVM transient structure.
5535	*
5536	* @remarks No-long-jump zone!!!
5537	*/
5538	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5539	{
5540	int rc = VINF_SUCCESS;
5541	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5542	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5543
5544	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5545	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5546	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5547
5548	/*
5549	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5550	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5551	*
5552	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5553	*/
5554	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5555	{
5556	IEMXCPTRAISE enmRaise;
5557	IEMXCPTRAISEINFO fRaiseInfo;
5558	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5559	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5560	if (fExitIsHwXcpt)
5561	{
5562	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5563	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5564	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5565	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5566	}
5567	else
5568	{
5569	/*
5570	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5571	* then we end up here.
5572	*
5573	* If the event was:
5574	* - a software interrupt, we can re-execute the instruction which will
5575	* regenerate the event.
5576	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5577	* - a hardware exception or external interrupt, we re-inject it.
5578	*/
5579	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5580	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5581	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5582	else
5583	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5584	}
5585
5586	switch (enmRaise)
5587	{
5588	case IEMXCPTRAISE_CURRENT_XCPT:
5589	case IEMXCPTRAISE_PREV_EVENT:
5590	{
5591	/* For software interrupts, we shall re-execute the instruction. */
5592	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5593	{
5594	RTGCUINTPTR GCPtrFaultAddress = 0;
5595
5596	/* If we are re-injecting an NMI, clear NMI blocking. */
5597	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5598	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5599
5600	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5601	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5602	{
5603	pSvmTransient->fVectoringPF = true;
5604	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5605	pVCpu->cpum.GstCtx.cr2));
5606	}
5607	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5608	&& uIdtVector == X86_XCPT_PF)
5609	{
5610	/*
5611	* If the previous exception was a #PF, we need to recover the CR2 value.
5612	* This can't happen with shadow paging.
5613	*/
5614	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5615	}
5616
5617	/*
5618	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5619	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5620	*/
5621	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5622	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
5623	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5624
5625	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5626	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5627	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5628	}
5629	break;
5630	}
5631
5632	case IEMXCPTRAISE_REEXEC_INSTR:
5633	{
5634	Assert(rc == VINF_SUCCESS);
5635	break;
5636	}
5637
5638	case IEMXCPTRAISE_DOUBLE_FAULT:
5639	{
5640	/*
5641	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5642	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5643	* converted into a #DF.
5644	*/
5645	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5646	{
5647	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5648	pSvmTransient->fVectoringDoublePF = true;
5649	Assert(rc == VINF_SUCCESS);
5650	}
5651	else
5652	{
5653	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
5654	hmR0SvmSetPendingXcptDF(pVCpu);
5655	rc = VINF_HM_DOUBLE_FAULT;
5656	}
5657	break;
5658	}
5659
5660	case IEMXCPTRAISE_TRIPLE_FAULT:
5661	{
5662	rc = VINF_EM_RESET;
5663	break;
5664	}
5665
5666	case IEMXCPTRAISE_CPU_HANG:
5667	{
5668	rc = VERR_EM_GUEST_CPU_HANG;
5669	break;
5670	}
5671
5672	default:
5673	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
5674	}
5675	}
5676	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
5677	return rc;
5678	}
5679
5680
5681	/**
5682	* Advances the guest RIP by the number of bytes specified in @a cb.
5683	*
5684	* @param pVCpu The cross context virtual CPU structure.
5685	* @param cb RIP increment value in bytes.
5686	*/
5687	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
5688	{
5689	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5690	pCtx->rip += cb;
5691
5692	/* Update interrupt shadow. */
5693	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
5694	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
5695	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5696	}
5697
5698
5699	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5700	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
5701	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
5702
5703	/** @name \#VMEXIT handlers.
5704	* @{
5705	*/
5706
5707	/**
5708	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
5709	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
5710	*/
5711	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5712	{
5713	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5714
5715	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
5716	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
5717	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
5718	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
5719
5720	/*
5721	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
5722	* signal -before- the timer fires if the current interrupt is our own timer or a some
5723	* other host interrupt. We also cannot examine what interrupt it is until the host
5724	* actually take the interrupt.
5725	*
5726	* Going back to executing guest code here unconditionally causes random scheduling
5727	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
5728	*/
5729	return VINF_EM_RAW_INTERRUPT;
5730	}
5731
5732
5733	/**
5734	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
5735	*/
5736	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5737	{
5738	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5739
5740	VBOXSTRICTRC rcStrict;
5741	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5742	if (fSupportsNextRipSave)
5743	{
5744	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5745	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5746	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5747	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
5748	}
5749	else
5750	{
5751	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5752	rcStrict = IEMExecOne(pVCpu);
5753	}
5754
5755	if (rcStrict == VINF_IEM_RAISED_XCPT)
5756	{
5757	rcStrict = VINF_SUCCESS;
5758	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5759	}
5760	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5761	return rcStrict;
5762	}
5763
5764
5765	/**
5766	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
5767	*/
5768	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5769	{
5770	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5771
5772	VBOXSTRICTRC rcStrict;
5773	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5774	if (fSupportsNextRipSave)
5775	{
5776	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5777	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5778	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5779	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
5780	}
5781	else
5782	{
5783	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5784	rcStrict = IEMExecOne(pVCpu);
5785	}
5786
5787	if (rcStrict == VINF_IEM_RAISED_XCPT)
5788	{
5789	rcStrict = VINF_SUCCESS;
5790	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5791	}
5792	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5793	return rcStrict;
5794	}
5795
5796
5797	/**
5798	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
5799	*/
5800	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5801	{
5802	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5803
5804	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
5805	VBOXSTRICTRC rcStrict;
5806	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
5807	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
5808	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
5809	if (!pExitRec)
5810	{
5811	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5812	if (fSupportsNextRipSave)
5813	{
5814	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5815	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5816	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
5817	}
5818	else
5819	{
5820	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5821	rcStrict = IEMExecOne(pVCpu);
5822	}
5823
5824	if (rcStrict == VINF_IEM_RAISED_XCPT)
5825	{
5826	rcStrict = VINF_SUCCESS;
5827	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5828	}
5829	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5830	}
5831	else
5832	{
5833	/*
5834	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
5835	*/
5836	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5837
5838	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
5839	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
5840
5841	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
5842
5843	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
5844	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
5845	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
5846	}
5847	return rcStrict;
5848	}
5849
5850
5851	/**
5852	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
5853	*/
5854	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5855	{
5856	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5857
5858	VBOXSTRICTRC rcStrict;
5859	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5860	if (fSupportsNextRipSave)
5861	{
5862	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5863	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5864	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5865	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
5866	}
5867	else
5868	{
5869	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5870	rcStrict = IEMExecOne(pVCpu);
5871	}
5872
5873	if (rcStrict == VINF_SUCCESS)
5874	pSvmTransient->fUpdateTscOffsetting = true;
5875	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5876	{
5877	rcStrict = VINF_SUCCESS;
5878	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5879	}
5880	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5881	return rcStrict;
5882	}
5883
5884
5885	/**
5886	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
5887	*/
5888	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5889	{
5890	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5891
5892	VBOXSTRICTRC rcStrict;
5893	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5894	if (fSupportsNextRipSave)
5895	{
5896	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
5897	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5898	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5899	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
5900	}
5901	else
5902	{
5903	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5904	rcStrict = IEMExecOne(pVCpu);
5905	}
5906
5907	if (rcStrict == VINF_SUCCESS)
5908	pSvmTransient->fUpdateTscOffsetting = true;
5909	else if (rcStrict == VINF_IEM_RAISED_XCPT)
5910	{
5911	rcStrict = VINF_SUCCESS;
5912	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5913	}
5914	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5915	return rcStrict;
5916	}
5917
5918
5919	/**
5920	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
5921	*/
5922	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5923	{
5924	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5925
5926	VBOXSTRICTRC rcStrict;
5927	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5928	if (fSupportsNextRipSave)
5929	{
5930	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
5931	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5932	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5933	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
5934	}
5935	else
5936	{
5937	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5938	rcStrict = IEMExecOne(pVCpu);
5939	}
5940
5941	if (rcStrict == VINF_IEM_RAISED_XCPT)
5942	{
5943	rcStrict = VINF_SUCCESS;
5944	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5945	}
5946	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5947	return rcStrict;
5948	}
5949
5950
5951	/**
5952	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
5953	*/
5954	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5955	{
5956	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5957	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
5958
5959	VBOXSTRICTRC rcStrict;
5960	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
5961	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5962	if ( fSupportsDecodeAssists
5963	&& fSupportsNextRipSave)
5964	{
5965	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
5966	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5967	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
5968	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
5969	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
5970	}
5971	else
5972	{
5973	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
5974	rcStrict = IEMExecOne(pVCpu);
5975	}
5976
5977	if (rcStrict == VINF_IEM_RAISED_XCPT)
5978	{
5979	rcStrict = VINF_SUCCESS;
5980	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
5981	}
5982	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5983	return VBOXSTRICTRC_VAL(rcStrict);
5984	}
5985
5986
5987	/**
5988	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
5989	*/
5990	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
5991	{
5992	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
5993
5994	VBOXSTRICTRC rcStrict;
5995	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
5996	if (fSupportsNextRipSave)
5997	{
5998	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
5999	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6000	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6001	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6002	}
6003	else
6004	{
6005	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6006	rcStrict = IEMExecOne(pVCpu);
6007	}
6008
6009	if ( rcStrict == VINF_EM_HALT
6010	\|\| rcStrict == VINF_SUCCESS)
6011	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6012	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6013	{
6014	rcStrict = VINF_SUCCESS;
6015	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6016	}
6017	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6018	if (rcStrict != VINF_SUCCESS)
6019	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6020	return VBOXSTRICTRC_VAL(rcStrict);;
6021	}
6022
6023
6024	/**
6025	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6026	*/
6027	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6028	{
6029	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6030
6031	/*
6032	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6033	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6034	* segment override prefix or other prefixes might be used, in which case we fallback to
6035	* IEMExecOne() to figure out.
6036	*/
6037	VBOXSTRICTRC rcStrict;
6038	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6039	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6040	if (cbInstr)
6041	{
6042	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6043	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6044	}
6045	else
6046	{
6047	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6048	rcStrict = IEMExecOne(pVCpu);
6049	}
6050
6051	if (rcStrict == VINF_IEM_RAISED_XCPT)
6052	{
6053	rcStrict = VINF_SUCCESS;
6054	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6055	}
6056	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6057	return rcStrict;
6058	}
6059
6060
6061	/**
6062	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6063	*/
6064	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6065	{
6066	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6067
6068	VBOXSTRICTRC rcStrict;
6069	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6070	if (fSupportsNextRipSave)
6071	{
6072	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6073	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6074	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6075	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6076	}
6077	else
6078	{
6079	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6080	rcStrict = IEMExecOne(pVCpu);
6081	}
6082
6083	if ( rcStrict == VINF_EM_HALT
6084	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6085	rcStrict = VINF_SUCCESS;
6086	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6087	{
6088	rcStrict = VINF_SUCCESS;
6089	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6090	}
6091	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6092	return rcStrict;
6093	}
6094
6095
6096	/**
6097	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6098	* \#VMEXIT.
6099	*/
6100	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6101	{
6102	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6103	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6104	return VINF_EM_RESET;
6105	}
6106
6107
6108	/**
6109	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6110	*/
6111	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6112	{
6113	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6114	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6115	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6116	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6117	RT_NOREF(pVmcb);
6118	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6119	return VERR_SVM_UNEXPECTED_EXIT;
6120	}
6121
6122
6123	/**
6124	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6125	*/
6126	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6127	{
6128	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6129
6130	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6131	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6132	#ifdef VBOX_WITH_STATISTICS
6133	switch (pSvmTransient->u64ExitCode)
6134	{
6135	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6136	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6137	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6138	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6139	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6140	}
6141	#endif
6142
6143	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6144	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6145	if ( fSupportsDecodeAssists
6146	&& fSupportsNextRipSave)
6147	{
6148	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6149	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6150	if (fMovCRx)
6151	{
6152	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6153	\| CPUMCTX_EXTRN_APIC_TPR);
6154	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6155	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6156	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6157	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6158	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6159	return VBOXSTRICTRC_VAL(rcStrict);
6160	}
6161	/* else: SMSW instruction, fall back below to IEM for this. */
6162	}
6163
6164	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6165	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6166	AssertMsg( rcStrict == VINF_SUCCESS
6167	\|\| rcStrict == VINF_PGM_SYNC_CR3
6168	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6169	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6170	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6171	if (rcStrict == VINF_IEM_RAISED_XCPT)
6172	{
6173	rcStrict = VINF_SUCCESS;
6174	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6175	}
6176	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6177	return rcStrict;
6178	}
6179
6180
6181	/**
6182	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6183	*/
6184	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6185	{
6186	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6187
6188	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6189	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6190	Assert(iCrReg <= 15);
6191
6192	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6193	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6194	bool fDecodedInstr = false;
6195	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6196	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6197	if ( fSupportsDecodeAssists
6198	&& fSupportsNextRipSave)
6199	{
6200	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6201	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6202	if (fMovCRx)
6203	{
6204	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6205	\| CPUMCTX_EXTRN_APIC_TPR);
6206	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6207	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6208	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6209	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6210	fDecodedInstr = true;
6211	}
6212	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6213	}
6214
6215	if (!fDecodedInstr)
6216	{
6217	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6218	Log4Func(("iCrReg=%#x\n", iCrReg));
6219	rcStrict = IEMExecOne(pVCpu);
6220	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6221	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6222	rcStrict = VERR_EM_INTERPRETER;
6223	}
6224
6225	if (rcStrict == VINF_SUCCESS)
6226	{
6227	switch (iCrReg)
6228	{
6229	case 0:
6230	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6231	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6232	break;
6233
6234	case 2:
6235	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6236	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6237	break;
6238
6239	case 3:
6240	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6241	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6242	break;
6243
6244	case 4:
6245	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6246	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6247	break;
6248
6249	case 8:
6250	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6251	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6252	break;
6253
6254	default:
6255	{
6256	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6257	pSvmTransient->u64ExitCode, iCrReg));
6258	break;
6259	}
6260	}
6261	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6262	}
6263	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6264	{
6265	rcStrict = VINF_SUCCESS;
6266	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6267	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6268	}
6269	else
6270	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6271	return rcStrict;
6272	}
6273
6274
6275	/**
6276	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6277	*
6278	* @returns Strict VBox status code.
6279	* @param pVCpu The cross context virtual CPU structure.
6280	* @param pVmcb Pointer to the VM control block.
6281	*/
6282	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb)
6283	{
6284	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6285	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6286
6287	VBOXSTRICTRC rcStrict;
6288	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6289	if (fSupportsNextRipSave)
6290	{
6291	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6292	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6293	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6294	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6295	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6296	}
6297	else
6298	{
6299	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6300	rcStrict = IEMExecOne(pVCpu);
6301	}
6302
6303	AssertMsg( rcStrict == VINF_SUCCESS
6304	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6305	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6306	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6307
6308	if (rcStrict == VINF_IEM_RAISED_XCPT)
6309	{
6310	rcStrict = VINF_SUCCESS;
6311	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6312	}
6313	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6314	return rcStrict;
6315	}
6316
6317
6318	/**
6319	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6320	*
6321	* @returns Strict VBox status code.
6322	* @param pVCpu The cross context virtual CPU structure.
6323	* @param pVmcb Pointer to the VM control block.
6324	* @param pSvmTransient Pointer to the SVM-transient structure.
6325	*/
6326	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPUCC pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6327	{
6328	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6329	uint32_t const idMsr = pCtx->ecx;
6330	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6331	Log4Func(("idMsr=%#RX32\n", idMsr));
6332
6333	/*
6334	* Handle TPR patching MSR writes.
6335	* We utilitize the LSTAR MSR for patching.
6336	*/
6337	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6338	if ( idMsr == MSR_K8_LSTAR
6339	&& pVCpu->CTX_SUFF(pVM)->hm.s.fTprPatchingActive)
6340	{
6341	unsigned cbInstr;
6342	if (fSupportsNextRipSave)
6343	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6344	else
6345	{
6346	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
6347	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6348	if ( rc == VINF_SUCCESS
6349	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6350	Assert(cbInstr > 0);
6351	else
6352	cbInstr = 0;
6353	}
6354
6355	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6356	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6357	{
6358	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6359	AssertRCReturn(rc, rc);
6360	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6361	}
6362
6363	int rc = VINF_SUCCESS;
6364	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6365	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6366	return rc;
6367	}
6368
6369	/*
6370	* Handle regular MSR writes.
6371	*/
6372	VBOXSTRICTRC rcStrict;
6373	if (fSupportsNextRipSave)
6374	{
6375	/** @todo Optimize this: We don't need to get much of the MSR state here
6376	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6377	* clear the applicable extern flags. */
6378	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6379	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6380	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6381	}
6382	else
6383	{
6384	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6385	rcStrict = IEMExecOne(pVCpu);
6386	}
6387
6388	AssertMsg( rcStrict == VINF_SUCCESS
6389	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6390	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6391	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6392
6393	if (rcStrict == VINF_SUCCESS)
6394	{
6395	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6396	if ( idMsr >= MSR_IA32_X2APIC_START
6397	&& idMsr <= MSR_IA32_X2APIC_END)
6398	{
6399	/*
6400	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6401	* When full APIC register virtualization is implemented we'll have to make sure
6402	* APIC state is saved from the VMCB before IEM changes it.
6403	*/
6404	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6405	}
6406	else
6407	{
6408	switch (idMsr)
6409	{
6410	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6411	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6412	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6413	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6414	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6415	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6416	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6417	}
6418	}
6419	}
6420	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6421	{
6422	rcStrict = VINF_SUCCESS;
6423	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6424	}
6425	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6426	return rcStrict;
6427	}
6428
6429
6430	/**
6431	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6432	* \#VMEXIT.
6433	*/
6434	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6435	{
6436	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6437
6438	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6439	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6440	return hmR0SvmExitReadMsr(pVCpu, pVmcb);
6441
6442	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6443	return hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient);
6444	}
6445
6446
6447	/**
6448	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6449	*/
6450	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6451	{
6452	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6453	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6454
6455	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6456
6457	/** @todo Stepping with nested-guest. */
6458	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6459	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6460	{
6461	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6462	if (pSvmTransient->fWasGuestDebugStateActive)
6463	{
6464	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6465	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6466	return VERR_SVM_UNEXPECTED_EXIT;
6467	}
6468
6469	/*
6470	* Lazy DR0-3 loading.
6471	*/
6472	if (!pSvmTransient->fWasHyperDebugStateActive)
6473	{
6474	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6475	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6476
6477	/* Don't intercept DRx read and writes. */
6478	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
6479	pVmcb->ctrl.u16InterceptRdDRx = 0;
6480	pVmcb->ctrl.u16InterceptWrDRx = 0;
6481	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6482
6483	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6484	VMMRZCallRing3Disable(pVCpu);
6485	HM_DISABLE_PREEMPT(pVCpu);
6486
6487	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6488	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6489	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6490
6491	HM_RESTORE_PREEMPT();
6492	VMMRZCallRing3Enable(pVCpu);
6493
6494	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6495	return VINF_SUCCESS;
6496	}
6497	}
6498
6499	/*
6500	* Interpret the read/writing of DRx.
6501	*/
6502	/** @todo Decode assist. */
6503	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6504	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6505	if (RT_LIKELY(rc == VINF_SUCCESS))
6506	{
6507	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6508	/** @todo CPUM should set this flag! */
6509	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6510	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6511	}
6512	else
6513	Assert(rc == VERR_EM_INTERPRETER);
6514	return rc;
6515	}
6516
6517
6518	/**
6519	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6520	*/
6521	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6522	{
6523	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6524	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6525	VBOXSTRICTRC rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6526	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6527	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6528	return rc;
6529	}
6530
6531
6532	/**
6533	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6534	*/
6535	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6536	{
6537	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6538	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6539
6540	/** @todo decode assists... */
6541	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6542	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6543	{
6544	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6545	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6546	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], fLoadSaveGuestXcr0, pCtx->cr4));
6547	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
6548	{
6549	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
6550	hmR0SvmUpdateVmRunFunction(pVCpu);
6551	}
6552	}
6553	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6554	{
6555	rcStrict = VINF_SUCCESS;
6556	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6557	}
6558	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6559	return rcStrict;
6560	}
6561
6562
6563	/**
6564	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6565	*/
6566	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6567	{
6568	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6569	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6570
6571	/* I/O operation lookup arrays. */
6572	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6573	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6574	the result (in AL/AX/EAX). */
6575	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6576	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6577	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6578
6579	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6580
6581	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6582	SVMIOIOEXITINFO IoExitInfo;
6583	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6584	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6585	uint32_t cbValue = s_aIOSize[uIOWidth];
6586	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6587
6588	if (RT_UNLIKELY(!cbValue))
6589	{
6590	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6591	return VERR_EM_INTERPRETER;
6592	}
6593
6594	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6595	VBOXSTRICTRC rcStrict;
6596	PCEMEXITREC pExitRec = NULL;
6597	if ( !pVCpu->hm.s.fSingleInstruction
6598	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6599	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6600	!IoExitInfo.n.u1Str
6601	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6602	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6603	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6604	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6605	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6606	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6607	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6608	if (!pExitRec)
6609	{
6610	bool fUpdateRipAlready = false;
6611	if (IoExitInfo.n.u1Str)
6612	{
6613	/* INS/OUTS - I/O String instruction. */
6614	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6615	* in EXITINFO1? Investigate once this thing is up and running. */
6616	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6617	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6618	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6619	static IEMMODE const s_aenmAddrMode[8] =
6620	{
6621	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6622	};
6623	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6624	if (enmAddrMode != (IEMMODE)-1)
6625	{
6626	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6627	if (cbInstr <= 15 && cbInstr >= 1)
6628	{
6629	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6630	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6631	{
6632	/* Don't know exactly how to detect whether u3Seg is valid, currently
6633	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6634	2384 Opterons when only checking NRIP. */
6635	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6636	if ( fSupportsNextRipSave
6637	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6638	{
6639	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6640	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6641	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6642	IoExitInfo.n.u3Seg, true /fIoChecked/);
6643	}
6644	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6645	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6646	X86_SREG_DS, true /fIoChecked/);
6647	else
6648	rcStrict = IEMExecOne(pVCpu);
6649	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6650	}
6651	else
6652	{
6653	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
6654	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6655	true /fIoChecked/);
6656	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6657	}
6658	}
6659	else
6660	{
6661	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6662	rcStrict = IEMExecOne(pVCpu);
6663	}
6664	}
6665	else
6666	{
6667	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6668	rcStrict = IEMExecOne(pVCpu);
6669	}
6670	fUpdateRipAlready = true;
6671	}
6672	else
6673	{
6674	/* IN/OUT - I/O instruction. */
6675	Assert(!IoExitInfo.n.u1Rep);
6676
6677	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6678	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6679	{
6680	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6681	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6682	&& !pCtx->eflags.Bits.u1TF)
6683	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
6684	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6685	}
6686	else
6687	{
6688	uint32_t u32Val = 0;
6689	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6690	if (IOM_SUCCESS(rcStrict))
6691	{
6692	/* Save result of I/O IN instr. in AL/AX/EAX. */
6693	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6694	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6695	}
6696	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6697	&& !pCtx->eflags.Bits.u1TF)
6698	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
6699
6700	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6701	}
6702	}
6703
6704	if (IOM_SUCCESS(rcStrict))
6705	{
6706	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6707	if (!fUpdateRipAlready)
6708	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6709
6710	/*
6711	* If any I/O breakpoints are armed, we need to check if one triggered
6712	* and take appropriate action.
6713	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6714	*/
6715	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6716	* execution engines about whether hyper BPs and such are pending. */
6717	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
6718	uint32_t const uDr7 = pCtx->dr[7];
6719	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6720	&& X86_DR7_ANY_RW_IO(uDr7)
6721	&& (pCtx->cr4 & X86_CR4_DE))
6722	\|\| DBGFBpIsHwIoArmed(pVM)))
6723	{
6724	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6725	VMMRZCallRing3Disable(pVCpu);
6726	HM_DISABLE_PREEMPT(pVCpu);
6727
6728	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6729	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6730
6731	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
6732	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6733	{
6734	/* Raise #DB. */
6735	pVmcb->guest.u64DR6 = pCtx->dr[6];
6736	pVmcb->guest.u64DR7 = pCtx->dr[7];
6737	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6738	hmR0SvmSetPendingXcptDB(pVCpu);
6739	}
6740	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6741	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6742	else if ( rcStrict2 != VINF_SUCCESS
6743	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6744	rcStrict = rcStrict2;
6745	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6746
6747	HM_RESTORE_PREEMPT();
6748	VMMRZCallRing3Enable(pVCpu);
6749	}
6750
6751	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6752	}
6753
6754	#ifdef VBOX_STRICT
6755	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
6756	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
6757	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6758	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
6759	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
6760	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
6761	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6762	else
6763	{
6764	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
6765	* statuses, that the VMM device and some others may return. See
6766	* IOM_SUCCESS() for guidance. */
6767	AssertMsg( RT_FAILURE(rcStrict)
6768	\|\| rcStrict == VINF_SUCCESS
6769	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
6770	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
6771	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
6772	\|\| rcStrict == VINF_EM_DBG_STEPPED
6773	\|\| rcStrict == VINF_EM_RAW_TO_R3
6774	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6775	}
6776	#endif
6777	}
6778	else
6779	{
6780	/*
6781	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6782	*/
6783	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6784	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
6785	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
6786	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
6787	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
6788	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
6789	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
6790
6791	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6792	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6793
6794	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6795	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6796	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6797	}
6798	return rcStrict;
6799	}
6800
6801
6802	/**
6803	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
6804	*/
6805	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6806	{
6807	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6808	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6809	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6810
6811	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6812	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6813	Assert(pVM->hmr0.s.fNestedPaging);
6814
6815	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
6816	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6817	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
6818	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
6819	thus intentionally not copied into u32ErrCode. */
6820
6821	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x cbInstrFetched=%u %.15Rhxs\n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
6822	u32ErrCode, pVmcb->ctrl.cbInstrFetched, pVmcb->ctrl.abInstr));
6823
6824	/*
6825	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
6826	*/
6827	if ( pVM->hm.s.fTprPatchingAllowed
6828	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
6829	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
6830	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
6831	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
6832	&& !CPUMIsGuestInLongModeEx(pCtx)
6833	&& !CPUMGetGuestCPL(pVCpu)
6834	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
6835	{
6836	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
6837	GCPhysApicBase &= PAGE_BASE_GC_MASK;
6838
6839	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
6840	{
6841	/* Only attempt to patch the instruction once. */
6842	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
6843	if (!pPatch)
6844	return VINF_EM_HM_PATCH_TPR_INSTR;
6845	}
6846	}
6847
6848	/*
6849	* Determine the nested paging mode.
6850	*/
6851	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
6852	PGMMODE const enmNestedPagingMode = PGMGetHostMode(pVM);
6853
6854	/*
6855	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
6856	*/
6857	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
6858	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
6859	{
6860	/*
6861	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
6862	* injecting the original pending event would most likely cause the same MMIO #NPF.
6863	*/
6864	if (pVCpu->hm.s.Event.fPending)
6865	{
6866	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
6867	return VINF_EM_RAW_INJECT_TRPM_EVENT;
6868	}
6869
6870	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
6871	VBOXSTRICTRC rcStrict;
6872	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6873	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
6874	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6875	if (!pExitRec)
6876	{
6877
6878	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
6879	u32ErrCode);
6880
6881	/*
6882	* If we succeed, resume guest execution.
6883	*
6884	* If we fail in interpreting the instruction because we couldn't get the guest
6885	* physical address of the page containing the instruction via the guest's page
6886	* tables (we would invalidate the guest page in the host TLB), resume execution
6887	* which would cause a guest page fault to let the guest handle this weird case.
6888	*
6889	* See @bugref{6043}.
6890	*/
6891	if ( rcStrict == VINF_SUCCESS
6892	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
6893	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
6894	{
6895	/* Successfully handled MMIO operation. */
6896	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6897	rcStrict = VINF_SUCCESS;
6898	}
6899	}
6900	else
6901	{
6902	/*
6903	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6904	*/
6905	Assert(pCtx == &pVCpu->cpum.GstCtx);
6906	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6907	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
6908	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
6909
6910	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6911	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
6912
6913	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6914	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6915	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6916	}
6917	return rcStrict;
6918	}
6919
6920	/*
6921	* Nested page-fault.
6922	*/
6923	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
6924	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
6925	TRPMResetTrap(pVCpu);
6926
6927	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
6928
6929	/*
6930	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
6931	*/
6932	if ( rc == VINF_SUCCESS
6933	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
6934	\|\| rc == VERR_PAGE_NOT_PRESENT)
6935	{
6936	/* We've successfully synced our shadow page tables. */
6937	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
6938	rc = VINF_SUCCESS;
6939	}
6940
6941	/*
6942	* If delivering an event causes an #NPF (and not MMIO), we shall resolve the fault and
6943	* re-inject the original event.
6944	*/
6945	if (pVCpu->hm.s.Event.fPending)
6946	{
6947	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
6948
6949	/*
6950	* If the #NPF handler requested emulation of the instruction, ignore it.
6951	* We need to re-inject the original event so as to not lose it.
6952	* Reproducible when booting ReactOS 0.4.12 with BTRFS (installed using BootCD,
6953	* LiveCD is broken for other reasons).
6954	*/
6955	if (rc == VINF_EM_RAW_EMULATE_INSTR)
6956	rc = VINF_EM_RAW_INJECT_TRPM_EVENT;
6957	}
6958
6959	return rc;
6960	}
6961
6962
6963	/**
6964	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
6965	* \#VMEXIT.
6966	*/
6967	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6968	{
6969	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6970	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
6971
6972	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
6973	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6974	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
6975
6976	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
6977	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
6978	return VINF_SUCCESS;
6979	}
6980
6981
6982	/**
6983	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
6984	* \#VMEXIT.
6985	*/
6986	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
6987	{
6988	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6989	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
6990
6991	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
6992	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
6993	#endif
6994
6995	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
6996	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
6997	{
6998	/*
6999	* AMD-V provides us with the exception which caused the TS; we collect
7000	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7001	*/
7002	Log4Func(("TS occurred during event delivery\n"));
7003	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7004	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7005	}
7006
7007	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7008	* emulation. */
7009	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7010	return VERR_EM_INTERPRETER;
7011	}
7012
7013
7014	/**
7015	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7016	*/
7017	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7018	{
7019	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7020	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7021
7022	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7023	if (pVM->hm.s.fTprPatchingAllowed)
7024	{
7025	int rc = hmEmulateSvmMovTpr(pVM, pVCpu);
7026	if (rc != VERR_NOT_FOUND)
7027	{
7028	Log4Func(("hmEmulateSvmMovTpr returns %Rrc\n", rc));
7029	return rc;
7030	}
7031	}
7032
7033	if (EMAreHypercallInstructionsEnabled(pVCpu))
7034	{
7035	unsigned cbInstr;
7036	if (hmR0SvmSupportsNextRipSave(pVCpu))
7037	{
7038	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7039	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7040	}
7041	else
7042	{
7043	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7044	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7045	if ( rc == VINF_SUCCESS
7046	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7047	Assert(cbInstr > 0);
7048	else
7049	cbInstr = 0;
7050	}
7051
7052	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7053	if (RT_SUCCESS(rcStrict))
7054	{
7055	/* Only update the RIP if we're continuing guest execution and not in the case
7056	of say VINF_GIM_R3_HYPERCALL. */
7057	if (rcStrict == VINF_SUCCESS)
7058	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7059
7060	return VBOXSTRICTRC_VAL(rcStrict);
7061	}
7062	else
7063	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7064	}
7065
7066	hmR0SvmSetPendingXcptUD(pVCpu);
7067	return VINF_SUCCESS;
7068	}
7069
7070
7071	/**
7072	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7073	*/
7074	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7075	{
7076	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7077
7078	unsigned cbInstr;
7079	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7080	if (fSupportsNextRipSave)
7081	{
7082	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7083	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7084	}
7085	else
7086	{
7087	PDISCPUSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7088	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7089	if ( rc == VINF_SUCCESS
7090	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7091	Assert(cbInstr > 0);
7092	else
7093	cbInstr = 0;
7094	}
7095
7096	/** @todo The guest has likely hit a contended spinlock. We might want to
7097	* poke a schedule different guest VCPU. */
7098	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7099	return VINF_EM_RAW_INTERRUPT;
7100	}
7101
7102
7103	/**
7104	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7105	* \#VMEXIT.
7106	*/
7107	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7108	{
7109	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7110	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7111	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7112
7113	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7114	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7115	}
7116
7117
7118	/**
7119	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7120	*/
7121	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7122	{
7123	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7124
7125	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now (almost) ready. */
7126	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7127	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7128
7129	/* Emulate the IRET. We have to execute the IRET before an NMI, but must potentially
7130	* deliver a pending NMI right after. If the IRET faults, an NMI can come before the
7131	* handler executes. Yes, x86 is ugly.
7132	*/
7133	return VINF_EM_RAW_EMULATE_INSTR;
7134	}
7135
7136
7137	/**
7138	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7139	* Conditional \#VMEXIT.
7140	*/
7141	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7142	{
7143	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7144	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7145	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7146
7147	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7148	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7149	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7150	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7151	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7152	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7153
7154	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7155	if (pVM->hmr0.s.fNestedPaging)
7156	{
7157	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7158	if ( !pSvmTransient->fVectoringDoublePF
7159	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7160	{
7161	/* A genuine guest #PF, reflect it to the guest. */
7162	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7163	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7164	uFaultAddress, uErrCode));
7165	}
7166	else
7167	{
7168	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7169	hmR0SvmSetPendingXcptDF(pVCpu);
7170	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7171	}
7172	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7173	return VINF_SUCCESS;
7174	}
7175	#endif
7176
7177	Assert(!pVM->hmr0.s.fNestedPaging);
7178
7179	/*
7180	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7181	*/
7182	if ( pVM->hm.s.fTprPatchingAllowed
7183	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7184	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7185	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7186	&& !CPUMIsGuestInLongModeEx(pCtx)
7187	&& !CPUMGetGuestCPL(pVCpu)
7188	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7189	{
7190	RTGCPHYS GCPhysApicBase;
7191	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7192	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7193
7194	/* Check if the page at the fault-address is the APIC base. */
7195	RTGCPHYS GCPhysPage;
7196	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7197	if ( rc2 == VINF_SUCCESS
7198	&& GCPhysPage == GCPhysApicBase)
7199	{
7200	/* Only attempt to patch the instruction once. */
7201	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7202	if (!pPatch)
7203	return VINF_EM_HM_PATCH_TPR_INSTR;
7204	}
7205	}
7206
7207	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7208	pCtx->rip, uErrCode, pCtx->cr3));
7209
7210	/*
7211	* If it's a vectoring #PF, emulate injecting the original event injection as
7212	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7213	* event injection that caused a #PF. See @bugref{6607}.
7214	*/
7215	if (pSvmTransient->fVectoringPF)
7216	{
7217	Assert(pVCpu->hm.s.Event.fPending);
7218	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7219	}
7220
7221	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7222	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7223
7224	Log4Func(("#PF: rc=%Rrc\n", rc));
7225
7226	if (rc == VINF_SUCCESS)
7227	{
7228	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7229	TRPMResetTrap(pVCpu);
7230	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7231	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7232	return rc;
7233	}
7234
7235	if (rc == VINF_EM_RAW_GUEST_TRAP)
7236	{
7237	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7238
7239	/*
7240	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7241	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7242	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7243	*/
7244	if ( !pSvmTransient->fVectoringDoublePF
7245	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7246	{
7247	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7248	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7249	TRPMResetTrap(pVCpu);
7250
7251	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7252	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7253	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7254	&& CPUMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
7255	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress);
7256	#endif
7257
7258	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7259	}
7260	else
7261	{
7262	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7263	TRPMResetTrap(pVCpu);
7264	hmR0SvmSetPendingXcptDF(pVCpu);
7265	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7266	}
7267
7268	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7269	return VINF_SUCCESS;
7270	}
7271
7272	TRPMResetTrap(pVCpu);
7273	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7274	return rc;
7275	}
7276
7277
7278	/**
7279	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7280	* Conditional \#VMEXIT.
7281	*/
7282	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7283	{
7284	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7285	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7286	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7287
7288	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7289	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7290	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7291
7292	/** @todo if we accumulate more optional stuff here, we ought to combine the
7293	* reading of opcode bytes to avoid doing more than once. */
7294
7295	VBOXSTRICTRC rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7296	if (pVCpu->hm.s.fGIMTrapXcptUD)
7297	{
7298	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7299	uint8_t cbInstr = 0;
7300	rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7301	if (rcStrict == VINF_SUCCESS)
7302	{
7303	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7304	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7305	rcStrict = VINF_SUCCESS;
7306	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7307	}
7308	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7309	rcStrict = VINF_SUCCESS;
7310	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7311	rcStrict = VINF_GIM_R3_HYPERCALL;
7312	else
7313	{
7314	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7315	rcStrict = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7316	}
7317	}
7318
7319	if (pVCpu->hm.s.svm.fEmulateLongModeSysEnterExit)
7320	{
7321	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_SS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS
7322	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7323	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
7324	{
7325	/* Ideally, IEM should just handle all these special #UD situations, but
7326	we don't quite trust things to behave optimially when doing that. So,
7327	for now we'll restrict ourselves to a handful of possible sysenter and
7328	sysexit encodings that we filter right here. */
7329	uint8_t abInstr[SVM_CTRL_GUEST_INSTR_BYTES_MAX];
7330	uint8_t cbInstr = pVmcb->ctrl.cbInstrFetched;
7331	uint32_t const uCpl = CPUMGetGuestCPL(pVCpu);
7332	uint8_t const cbMin = uCpl != 0 ? 2 : 1 + 2;
7333	RTGCPTR const GCPtrInstr = pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base;
7334	if (cbInstr < cbMin \|\| cbInstr > SVM_CTRL_GUEST_INSTR_BYTES_MAX)
7335	{
7336	cbInstr = cbMin;
7337	int rc2 = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, GCPtrInstr, cbInstr);
7338	AssertRCStmt(rc2, cbInstr = 0);
7339	}
7340	else
7341	memcpy(abInstr, pVmcb->ctrl.abInstr, cbInstr); /* unlikely */
7342	if ( cbInstr == 0 /* read error */
7343	\|\| (cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x34) /* sysenter */
7344	\|\| ( uCpl == 0
7345	&& ( ( cbInstr >= 2 && abInstr[0] == 0x0f && abInstr[1] == 0x35) /* sysexit */
7346	\|\| ( cbInstr >= 3 && abInstr[1] == 0x0f && abInstr[2] == 0x35 /* rex.w sysexit */
7347	&& (abInstr[0] & (X86_OP_REX_W \| 0xf0)) == X86_OP_REX_W))))
7348	{
7349	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK
7350	\| CPUMCTX_EXTRN_SREG_MASK /* without ES+DS+GS the app will #GP later - go figure */);
7351	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7352	rcStrict = IEMExecOneWithPrefetchedByPC(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), GCPtrInstr, abInstr, cbInstr);
7353	Log6(("hmR0SvmExitXcptUD: sysenter/sysexit: rcStrict=%Rrc %04x:%08RX64 %08RX64 %04x:%08RX64\n",
7354	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u,
7355	pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.rsp));
7356	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7357	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK); /** @todo Lazy bird. */
7358	if (rcStrict == VINF_IEM_RAISED_XCPT)
7359	rcStrict = VINF_SUCCESS;
7360	return rcStrict;
7361	}
7362	Log6(("hmR0SvmExitXcptUD: not sysenter/sysexit: %.*Rhxs at %#llx CPL=%u\n", cbInstr, abInstr, GCPtrInstr, uCpl));
7363	}
7364	else
7365	Log6(("hmR0SvmExitXcptUD: not in long mode at %04x:%llx\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7366	}
7367
7368	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7369	if (RT_FAILURE(rcStrict))
7370	{
7371	hmR0SvmSetPendingXcptUD(pVCpu);
7372	rcStrict = VINF_SUCCESS;
7373	}
7374
7375	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7376	return rcStrict;
7377	}
7378
7379
7380	/**
7381	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7382	* Conditional \#VMEXIT.
7383	*/
7384	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7385	{
7386	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7387	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7388	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7389
7390	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7391	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7392
7393	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7394	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7395
7396	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7397
7398	if (!(pCtx->cr0 & X86_CR0_NE))
7399	{
7400	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7401	PDISSTATE pDis = &pVCpu->hmr0.s.svm.DisState;
7402	unsigned cbInstr;
7403	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7404	if (RT_SUCCESS(rc))
7405	{
7406	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7407	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7408	if (RT_SUCCESS(rc))
7409	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7410	}
7411	else
7412	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7413	return rc;
7414	}
7415
7416	hmR0SvmSetPendingXcptMF(pVCpu);
7417	return VINF_SUCCESS;
7418	}
7419
7420
7421	/**
7422	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7423	* \#VMEXIT.
7424	*/
7425	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7426	{
7427	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7428	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7429	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7430	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7431
7432	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7433	{
7434	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7435	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7436	}
7437
7438	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7439
7440	/*
7441	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7442	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7443	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7444	*/
7445	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7446	PSVMVMCB pVmcb = pVCpu->hmr0.s.svm.pVmcb;
7447	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7448	int rc = DBGFTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7449	if (rc == VINF_EM_RAW_GUEST_TRAP)
7450	{
7451	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7452	if (CPUMIsHyperDebugStateActive(pVCpu))
7453	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7454
7455	/* Reflect the exception back to the guest. */
7456	hmR0SvmSetPendingXcptDB(pVCpu);
7457	rc = VINF_SUCCESS;
7458	}
7459
7460	/*
7461	* Update DR6.
7462	*/
7463	if (CPUMIsHyperDebugStateActive(pVCpu))
7464	{
7465	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7466	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7467	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7468	}
7469	else
7470	{
7471	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7472	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7473	}
7474
7475	return rc;
7476	}
7477
7478
7479	/**
7480	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7481	* Conditional \#VMEXIT.
7482	*/
7483	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7484	{
7485	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7486	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7487	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
7488
7489	SVMEVENT Event;
7490	Event.u = 0;
7491	Event.n.u1Valid = 1;
7492	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7493	Event.n.u8Vector = X86_XCPT_AC;
7494	Event.n.u1ErrorCodeValid = 1;
7495	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7496	return VINF_SUCCESS;
7497	}
7498
7499
7500	/**
7501	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7502	* Conditional \#VMEXIT.
7503	*/
7504	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7505	{
7506	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7507	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7508	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7509	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
7510
7511	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7512	int rc = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7513	if (rc == VINF_EM_RAW_GUEST_TRAP)
7514	{
7515	SVMEVENT Event;
7516	Event.u = 0;
7517	Event.n.u1Valid = 1;
7518	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7519	Event.n.u8Vector = X86_XCPT_BP;
7520	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7521	rc = VINF_SUCCESS;
7522	}
7523
7524	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_DBG_BREAKPOINT);
7525	return rc;
7526	}
7527
7528
7529	/**
7530	* Hacks its way around the lovely mesa driver's backdoor accesses.
7531	*
7532	* @sa hmR0VmxHandleMesaDrvGp
7533	*/
7534	static int hmR0SvmHandleMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7535	{
7536	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK);
7537	Log(("hmR0SvmHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n",
7538	pVmcb->guest.CS.u16Sel, pVmcb->guest.u64RIP, pCtx->rcx, pCtx->rbx));
7539	RT_NOREF(pCtx, pVmcb);
7540
7541	/* For now we'll just skip the instruction. */
7542	hmR0SvmAdvanceRip(pVCpu, 1);
7543	return VINF_SUCCESS;
7544	}
7545
7546
7547	/**
7548	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
7549	* backdoor logging w/o checking what it is running inside.
7550	*
7551	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
7552	* backdoor port and magic numbers loaded in registers.
7553	*
7554	* @returns true if it is, false if it isn't.
7555	* @sa hmR0VmxIsMesaDrvGp
7556	*/
7557	DECLINLINE(bool) hmR0SvmIsMesaDrvGp(PVMCPUCC pVCpu, PCPUMCTX pCtx, PCSVMVMCB pVmcb)
7558	{
7559	/* Check magic and port. */
7560	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
7561	/Log8(("hmR0SvmIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax, pCtx->rdx));/
7562	if (pCtx->dx != UINT32_C(0x5658))
7563	return false;
7564	if ((pCtx->fExtrn & CPUMCTX_EXTRN_RAX ? pVmcb->guest.u64RAX : pCtx->rax) != UINT32_C(0x564d5868))
7565	return false;
7566
7567	/* Check that it is #GP(0). */
7568	if (pVmcb->ctrl.u64ExitInfo1 != 0)
7569	return false;
7570
7571	/* Flat ring-3 CS. */
7572	/Log8(("hmR0SvmIsMesaDrvGp: u8CPL=%d base=%RX64\n", pVmcb->guest.u8CPL, pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base));/
7573	if (pVmcb->guest.u8CPL != 3)
7574	return false;
7575	if ((pCtx->fExtrn & CPUMCTX_EXTRN_CS ? pVmcb->guest.CS.u64Base : pCtx->cs.u64Base) != 0)
7576	return false;
7577
7578	/* 0xed: IN eAX,dx */
7579	if (pVmcb->ctrl.cbInstrFetched < 1) /* unlikely, it turns out. */
7580	{
7581	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_GPRS_MASK
7582	\| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
7583	uint8_t abInstr[1];
7584	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
7585	/Log8(("hmR0SvmIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0])); /
7586	if (RT_FAILURE(rc))
7587	return false;
7588	if (abInstr[0] != 0xed)
7589	return false;
7590	}
7591	else
7592	{
7593	/Log8(("hmR0SvmIsMesaDrvGp: %#x\n", pVmcb->ctrl.abInstr));/
7594	if (pVmcb->ctrl.abInstr[0] != 0xed)
7595	return false;
7596	}
7597	return true;
7598	}
7599
7600
7601	/**
7602	* \#VMEXIT handler for general protection faults (SVM_EXIT_XCPT_BP).
7603	* Conditional \#VMEXIT.
7604	*/
7605	HMSVM_EXIT_DECL hmR0SvmExitXcptGP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7606	{
7607	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7608	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7609	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
7610
7611	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7612	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7613
7614	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7615	if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
7616	\|\| !hmR0SvmIsMesaDrvGp(pVCpu, pCtx, pVmcb))
7617	{
7618	SVMEVENT Event;
7619	Event.u = 0;
7620	Event.n.u1Valid = 1;
7621	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7622	Event.n.u8Vector = X86_XCPT_GP;
7623	Event.n.u1ErrorCodeValid = 1;
7624	Event.n.u32ErrorCode = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
7625	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7626	return VINF_SUCCESS;
7627	}
7628	return hmR0SvmHandleMesaDrvGp(pVCpu, pCtx, pVmcb);
7629	}
7630
7631
7632	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7633	/**
7634	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7635	*/
7636	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7637	{
7638	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7639	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7640
7641	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7642	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7643	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7644	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7645	Assert(uVector <= X86_XCPT_LAST);
7646	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7647
7648	SVMEVENT Event;
7649	Event.u = 0;
7650	Event.n.u1Valid = 1;
7651	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7652	Event.n.u8Vector = uVector;
7653	switch (uVector)
7654	{
7655	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7656	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7657	case X86_XCPT_DF:
7658	case X86_XCPT_TS:
7659	case X86_XCPT_NP:
7660	case X86_XCPT_SS:
7661	case X86_XCPT_GP:
7662	case X86_XCPT_AC:
7663	{
7664	Event.n.u1ErrorCodeValid = 1;
7665	Event.n.u32ErrorCode = uErrCode;
7666	break;
7667	}
7668	}
7669
7670	#ifdef VBOX_WITH_STATISTICS
7671	switch (uVector)
7672	{
7673	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
7674	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
7675	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
7676	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7677	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
7678	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
7679	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
7680	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
7681	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
7682	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
7683	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
7684	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
7685	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
7686	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
7687	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
7688	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
7689	default:
7690	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
7691	break;
7692	}
7693	#endif
7694
7695	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7696	return VINF_SUCCESS;
7697	}
7698	#endif
7699
7700	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7701	/**
7702	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7703	*/
7704	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7705	{
7706	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7707
7708	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7709	Assert(pVmcb);
7710	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7711
7712	VBOXSTRICTRC rcStrict;
7713	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7714	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7715	if (fSupportsNextRipSave)
7716	{
7717	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7718	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7719	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7720	}
7721	else
7722	{
7723	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7724	rcStrict = IEMExecOne(pVCpu);
7725	}
7726
7727	if (rcStrict == VINF_SUCCESS)
7728	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7729	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7730	{
7731	rcStrict = VINF_SUCCESS;
7732	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7733	}
7734	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7735	return rcStrict;
7736	}
7737
7738
7739	/**
7740	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7741	*/
7742	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7743	{
7744	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7745
7746	/*
7747	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7748	* we only intercept STGI when events are pending for GIF to become 1.
7749	*/
7750	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7751	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7752	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7753
7754	VBOXSTRICTRC rcStrict;
7755	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7756	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7757	if (fSupportsNextRipSave)
7758	{
7759	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7760	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7761	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7762	}
7763	else
7764	{
7765	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7766	rcStrict = IEMExecOne(pVCpu);
7767	}
7768
7769	if (rcStrict == VINF_SUCCESS)
7770	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7771	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7772	{
7773	rcStrict = VINF_SUCCESS;
7774	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7775	}
7776	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7777	return rcStrict;
7778	}
7779
7780
7781	/**
7782	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7783	*/
7784	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7785	{
7786	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7787
7788	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7789	Assert(pVmcb);
7790	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7791
7792	VBOXSTRICTRC rcStrict;
7793	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7794	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7795	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7796	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7797	if (fSupportsNextRipSave)
7798	{
7799	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7800	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7801	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7802	}
7803	else
7804	{
7805	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7806	rcStrict = IEMExecOne(pVCpu);
7807	}
7808
7809	if (rcStrict == VINF_SUCCESS)
7810	{
7811	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7812	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7813	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7814	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7815	}
7816	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7817	{
7818	rcStrict = VINF_SUCCESS;
7819	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7820	}
7821	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7822	return rcStrict;
7823	}
7824
7825
7826	/**
7827	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7828	*/
7829	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7830	{
7831	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7832
7833	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7834	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7835
7836	VBOXSTRICTRC rcStrict;
7837	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7838	if (fSupportsNextRipSave)
7839	{
7840	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7841	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7842	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7843	}
7844	else
7845	{
7846	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7847	rcStrict = IEMExecOne(pVCpu);
7848	}
7849
7850	if (rcStrict == VINF_IEM_RAISED_XCPT)
7851	{
7852	rcStrict = VINF_SUCCESS;
7853	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7854	}
7855	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7856	return rcStrict;
7857	}
7858
7859
7860	/**
7861	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7862	*/
7863	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7864	{
7865	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7866
7867	VBOXSTRICTRC rcStrict;
7868	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7869	if (fSupportsNextRipSave)
7870	{
7871	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7872	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7873	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7874	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7875	}
7876	else
7877	{
7878	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7879	rcStrict = IEMExecOne(pVCpu);
7880	}
7881
7882	if (rcStrict == VINF_IEM_RAISED_XCPT)
7883	{
7884	rcStrict = VINF_SUCCESS;
7885	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7886	}
7887	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7888	return rcStrict;
7889	}
7890
7891
7892	/**
7893	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7894	*/
7895	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7896	{
7897	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7898	/* We shall import the entire state here, just in case we enter and continue execution of
7899	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
7900	could lose lose part of CPU state. */
7901	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7902
7903	VBOXSTRICTRC rcStrict;
7904	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7905	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
7906	if (fSupportsNextRipSave)
7907	{
7908	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7909	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7910	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7911	}
7912	else
7913	{
7914	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
7915	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
7916	instruction itself, see @bugref{7243#c126} */
7917	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
7918	}
7919	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
7920
7921	if (rcStrict == VINF_SUCCESS)
7922	{
7923	rcStrict = VINF_SVM_VMRUN;
7924	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
7925	}
7926	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7927	{
7928	rcStrict = VINF_SUCCESS;
7929	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7930	}
7931	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7932	return rcStrict;
7933	}
7934
7935
7936	/**
7937	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
7938	* Unconditional \#VMEXIT.
7939	*/
7940	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7941	{
7942	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7943	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7944
7945	if (pVCpu->hm.s.Event.fPending)
7946	{
7947	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
7948	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7949	}
7950
7951	hmR0SvmSetPendingXcptDB(pVCpu);
7952	return VINF_SUCCESS;
7953	}
7954
7955
7956	/**
7957	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7958	* Conditional \#VMEXIT.
7959	*/
7960	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPUCC pVCpu, PSVMTRANSIENT pSvmTransient)
7961	{
7962	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7963	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7964
7965	SVMEVENT Event;
7966	Event.u = 0;
7967	Event.n.u1Valid = 1;
7968	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7969	Event.n.u8Vector = X86_XCPT_BP;
7970	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7971	return VINF_SUCCESS;
7972	}
7973	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
7974
7975	/** @} */
7976

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 92392

Download in other formats: