VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 48302

Last change on this file since 48302 was 48284, checked in by vboxsync, 11 years ago

VMM/HMVMXR0: Avoid calling PGM twice for reading just 4 consecutive bytes.
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1/* $Id: HMVMXR0.cpp 48284 2013-09-05 00:32:23Z vboxsync $ */
2/** @file
3 * HM VMX (Intel VT-x) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2012-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <iprt/asm-amd64-x86.h>
23#include <iprt/thread.h>
24#include <iprt/string.h>
25
26#include "HMInternal.h"
27#include <VBox/vmm/vm.h>
28#include "HMVMXR0.h"
29#include <VBox/vmm/pdmapi.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iem.h>
32#include <VBox/vmm/iom.h>
33#include <VBox/vmm/selm.h>
34#include <VBox/vmm/tm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#ifdef DEBUG_ramshankar
39#define HMVMX_SAVE_FULL_GUEST_STATE
40#define HMVMX_SYNC_FULL_GUEST_STATE
41#define HMVMX_ALWAYS_CHECK_GUEST_STATE
42#define HMVMX_ALWAYS_TRAP_ALL_XCPTS
43#define HMVMX_ALWAYS_TRAP_PF
44#endif
45
46
47/*******************************************************************************
48* Defined Constants And Macros *
49*******************************************************************************/
50#if defined(RT_ARCH_AMD64)
51# define HMVMX_IS_64BIT_HOST_MODE() (true)
52typedef RTHCUINTREG HMVMXHCUINTREG;
53#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54extern "C" uint32_t g_fVMXIs64bitHost;
55# define HMVMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
56typedef uint64_t HMVMXHCUINTREG;
57#else
58# define HMVMX_IS_64BIT_HOST_MODE() (false)
59typedef RTHCUINTREG HMVMXHCUINTREG;
60#endif
61
62/** Use the function table. */
63#define HMVMX_USE_FUNCTION_TABLE
64
65/** Determine which tagged-TLB flush handler to use. */
66#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
67#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
68#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
69#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
70
71/** @name Updated-guest-state flags.
72 * @{ */
73#define HMVMX_UPDATED_GUEST_RIP RT_BIT(0)
74#define HMVMX_UPDATED_GUEST_RSP RT_BIT(1)
75#define HMVMX_UPDATED_GUEST_RFLAGS RT_BIT(2)
76#define HMVMX_UPDATED_GUEST_CR0 RT_BIT(3)
77#define HMVMX_UPDATED_GUEST_CR3 RT_BIT(4)
78#define HMVMX_UPDATED_GUEST_CR4 RT_BIT(5)
79#define HMVMX_UPDATED_GUEST_GDTR RT_BIT(6)
80#define HMVMX_UPDATED_GUEST_IDTR RT_BIT(7)
81#define HMVMX_UPDATED_GUEST_LDTR RT_BIT(8)
82#define HMVMX_UPDATED_GUEST_TR RT_BIT(9)
83#define HMVMX_UPDATED_GUEST_SEGMENT_REGS RT_BIT(10)
84#define HMVMX_UPDATED_GUEST_DEBUG RT_BIT(11)
85#define HMVMX_UPDATED_GUEST_FS_BASE_MSR RT_BIT(12)
86#define HMVMX_UPDATED_GUEST_GS_BASE_MSR RT_BIT(13)
87#define HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR RT_BIT(14)
88#define HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR RT_BIT(15)
89#define HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR RT_BIT(16)
90#define HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS RT_BIT(17)
91#define HMVMX_UPDATED_GUEST_ACTIVITY_STATE RT_BIT(18)
92#define HMVMX_UPDATED_GUEST_APIC_STATE RT_BIT(19)
93#define HMVMX_UPDATED_GUEST_ALL ( HMVMX_UPDATED_GUEST_RIP \
94 | HMVMX_UPDATED_GUEST_RSP \
95 | HMVMX_UPDATED_GUEST_RFLAGS \
96 | HMVMX_UPDATED_GUEST_CR0 \
97 | HMVMX_UPDATED_GUEST_CR3 \
98 | HMVMX_UPDATED_GUEST_CR4 \
99 | HMVMX_UPDATED_GUEST_GDTR \
100 | HMVMX_UPDATED_GUEST_IDTR \
101 | HMVMX_UPDATED_GUEST_LDTR \
102 | HMVMX_UPDATED_GUEST_TR \
103 | HMVMX_UPDATED_GUEST_SEGMENT_REGS \
104 | HMVMX_UPDATED_GUEST_DEBUG \
105 | HMVMX_UPDATED_GUEST_FS_BASE_MSR \
106 | HMVMX_UPDATED_GUEST_GS_BASE_MSR \
107 | HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR \
108 | HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR \
109 | HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR \
110 | HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS \
111 | HMVMX_UPDATED_GUEST_ACTIVITY_STATE \
112 | HMVMX_UPDATED_GUEST_APIC_STATE)
113/** @} */
114
115/** @name
116 * Flags to skip redundant reads of some common VMCS fields that are not part of
117 * the guest-CPU state but are in the transient structure.
118 */
119#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO RT_BIT(0)
120#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE RT_BIT(1)
121#define HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION RT_BIT(2)
122#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN RT_BIT(3)
123#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO RT_BIT(4)
124#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE RT_BIT(5)
125/** @} */
126
127/** @name
128 * States of the VMCS.
129 *
130 * This does not reflect all possible VMCS states but currently only those
131 * needed for maintaining the VMCS consistently even when thread-context hooks
132 * are used. Maybe later this can be extended (i.e. Nested Virtualization).
133 */
134#define HMVMX_VMCS_STATE_CLEAR RT_BIT(0)
135#define HMVMX_VMCS_STATE_ACTIVE RT_BIT(1)
136#define HMVMX_VMCS_STATE_LAUNCHED RT_BIT(2)
137/** @} */
138
139/**
140 * Exception bitmap mask for real-mode guests (real-on-v86).
141 *
142 * We need to intercept all exceptions manually (except #PF). #NM is also
143 * handled separately, see hmR0VmxLoadGuestControlRegs(). #PF need not be
144 * intercepted even in real-mode if we have Nested Paging support.
145 */
146#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NMI) \
147 | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) \
148 | RT_BIT(X86_XCPT_UD) /* RT_BIT(X86_XCPT_NM) */ | RT_BIT(X86_XCPT_DF) \
149 | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) \
150 | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
151 | RT_BIT(X86_XCPT_MF) | RT_BIT(X86_XCPT_AC) | RT_BIT(X86_XCPT_MC) \
152 | RT_BIT(X86_XCPT_XF))
153
154/**
155 * Exception bitmap mask for all contributory exceptions.
156 *
157 * Page fault is deliberately excluded here as it's conditional as to whether
158 * it's contributory or benign. Page faults are handled separately.
159 */
160#define HMVMX_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_TS) \
161 | RT_BIT(X86_XCPT_DE))
162
163/** Maximum VM-instruction error number. */
164#define HMVMX_INSTR_ERROR_MAX 28
165
166/** Profiling macro. */
167#ifdef HM_PROFILE_EXIT_DISPATCH
168# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
169# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
170#else
171# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
172# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
173#endif
174
175/** Assert that preemption is disabled or covered by thread-context hooks. */
176#define HMVMX_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
177 || !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
178
179/** Assert that we haven't migrated CPUs when thread-context hooks are not
180 * used. */
181#define HMVMX_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
182 || pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
183 ("Illegal migration! Entered on CPU %u Current %u\n", \
184 pVCpu->hm.s.idEnteredCpu, RTMpCpuId())); \
185
186/*******************************************************************************
187* Structures and Typedefs *
188*******************************************************************************/
189/**
190 * VMX transient state.
191 *
192 * A state structure for holding miscellaneous information across
193 * VMX non-root operation and restored after the transition.
194 */
195typedef struct VMXTRANSIENT
196{
197 /** The host's rflags/eflags. */
198 RTCCUINTREG uEflags;
199#if HC_ARCH_BITS == 32
200 uint32_t u32Alignment0;
201#endif
202 /** The guest's LSTAR MSR value used for TPR patching for 32-bit guests. */
203 uint64_t u64LStarMsr;
204 /** The guest's TPR value used for TPR shadowing. */
205 uint8_t u8GuestTpr;
206 /** Alignment. */
207 uint8_t abAlignment0[7];
208
209 /** The basic VM-exit reason. */
210 uint16_t uExitReason;
211 /** Alignment. */
212 uint16_t u16Alignment0;
213 /** The VM-exit interruption error code. */
214 uint32_t uExitIntrErrorCode;
215 /** The VM-exit exit qualification. */
216 uint64_t uExitQualification;
217
218 /** The VM-exit interruption-information field. */
219 uint32_t uExitIntrInfo;
220 /** The VM-exit instruction-length field. */
221 uint32_t cbInstr;
222 /** The VM-exit instruction-information field. */
223 union
224 {
225 /** Plain unsigned int representation. */
226 uint32_t u;
227 /** INS and OUTS information. */
228 struct
229 {
230 uint32_t u6Reserved0 : 6;
231 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
232 uint32_t u3AddrSize : 3;
233 uint32_t u5Reserved1 : 5;
234 /** The segment register (X86_SREG_XXX). */
235 uint32_t iSegReg : 3;
236 uint32_t uReserved2 : 14;
237 } StrIo;
238 } ExitInstrInfo;
239 /** Whether the VM-entry failed or not. */
240 bool fVMEntryFailed;
241 /** Alignment. */
242 uint8_t abAlignment1[3];
243
244 /** The VM-entry interruption-information field. */
245 uint32_t uEntryIntrInfo;
246 /** The VM-entry exception error code field. */
247 uint32_t uEntryXcptErrorCode;
248 /** The VM-entry instruction length field. */
249 uint32_t cbEntryInstr;
250
251 /** IDT-vectoring information field. */
252 uint32_t uIdtVectoringInfo;
253 /** IDT-vectoring error code. */
254 uint32_t uIdtVectoringErrorCode;
255
256 /** Mask of currently read VMCS fields; HMVMX_UPDATED_TRANSIENT_*. */
257 uint32_t fVmcsFieldsRead;
258 /** Whether TSC-offsetting should be setup before VM-entry. */
259 bool fUpdateTscOffsettingAndPreemptTimer;
260 /** Whether the VM-exit was caused by a page-fault during delivery of a
261 * contributory exception or a page-fault. */
262 bool fVectoringPF;
263} VMXTRANSIENT;
264AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, sizeof(uint64_t));
265AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntrInfo, sizeof(uint64_t));
266AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntrInfo, sizeof(uint64_t));
267AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
268/** Pointer to VMX transient state. */
269typedef VMXTRANSIENT *PVMXTRANSIENT;
270
271
272/**
273 * MSR-bitmap read permissions.
274 */
275typedef enum VMXMSREXITREAD
276{
277 /** Reading this MSR causes a VM-exit. */
278 VMXMSREXIT_INTERCEPT_READ = 0xb,
279 /** Reading this MSR does not cause a VM-exit. */
280 VMXMSREXIT_PASSTHRU_READ
281} VMXMSREXITREAD;
282
283/**
284 * MSR-bitmap write permissions.
285 */
286typedef enum VMXMSREXITWRITE
287{
288 /** Writing to this MSR causes a VM-exit. */
289 VMXMSREXIT_INTERCEPT_WRITE = 0xd,
290 /** Writing to this MSR does not cause a VM-exit. */
291 VMXMSREXIT_PASSTHRU_WRITE
292} VMXMSREXITWRITE;
293
294/**
295 * VM-exit handler.
296 *
297 * @returns VBox status code.
298 * @param pVCpu Pointer to the VMCPU.
299 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
300 * out-of-sync. Make sure to update the required
301 * fields before using them.
302 * @param pVmxTransient Pointer to the VMX-transient structure.
303 */
304#ifndef HMVMX_USE_FUNCTION_TABLE
305typedef int FNVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
306#else
307typedef DECLCALLBACK(int) FNVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
308/** Pointer to VM-exit handler. */
309typedef FNVMEXITHANDLER *PFNVMEXITHANDLER;
310#endif
311
312
313/*******************************************************************************
314* Internal Functions *
315*******************************************************************************/
316static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMX_FLUSH_EPT enmFlush);
317static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_VPID enmFlush, RTGCPTR GCPtr);
318static void hmR0VmxClearEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx);
319static int hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntrInfo, uint32_t cbInstr,
320 uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress, uint32_t *puIntrState);
321#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
322static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu);
323#endif
324#ifndef HMVMX_USE_FUNCTION_TABLE
325DECLINLINE(int) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason);
326# define HMVMX_EXIT_DECL static int
327#else
328# define HMVMX_EXIT_DECL static DECLCALLBACK(int)
329#endif
330
331/** @name VM-exit handlers.
332 * @{
333 */
334static FNVMEXITHANDLER hmR0VmxExitXcptOrNmi;
335static FNVMEXITHANDLER hmR0VmxExitExtInt;
336static FNVMEXITHANDLER hmR0VmxExitTripleFault;
337static FNVMEXITHANDLER hmR0VmxExitInitSignal;
338static FNVMEXITHANDLER hmR0VmxExitSipi;
339static FNVMEXITHANDLER hmR0VmxExitIoSmi;
340static FNVMEXITHANDLER hmR0VmxExitSmi;
341static FNVMEXITHANDLER hmR0VmxExitIntWindow;
342static FNVMEXITHANDLER hmR0VmxExitNmiWindow;
343static FNVMEXITHANDLER hmR0VmxExitTaskSwitch;
344static FNVMEXITHANDLER hmR0VmxExitCpuid;
345static FNVMEXITHANDLER hmR0VmxExitGetsec;
346static FNVMEXITHANDLER hmR0VmxExitHlt;
347static FNVMEXITHANDLER hmR0VmxExitInvd;
348static FNVMEXITHANDLER hmR0VmxExitInvlpg;
349static FNVMEXITHANDLER hmR0VmxExitRdpmc;
350static FNVMEXITHANDLER hmR0VmxExitRdtsc;
351static FNVMEXITHANDLER hmR0VmxExitRsm;
352static FNVMEXITHANDLER hmR0VmxExitSetPendingXcptUD;
353static FNVMEXITHANDLER hmR0VmxExitMovCRx;
354static FNVMEXITHANDLER hmR0VmxExitMovDRx;
355static FNVMEXITHANDLER hmR0VmxExitIoInstr;
356static FNVMEXITHANDLER hmR0VmxExitRdmsr;
357static FNVMEXITHANDLER hmR0VmxExitWrmsr;
358static FNVMEXITHANDLER hmR0VmxExitErrInvalidGuestState;
359static FNVMEXITHANDLER hmR0VmxExitErrMsrLoad;
360static FNVMEXITHANDLER hmR0VmxExitErrUndefined;
361static FNVMEXITHANDLER hmR0VmxExitMwait;
362static FNVMEXITHANDLER hmR0VmxExitMtf;
363static FNVMEXITHANDLER hmR0VmxExitMonitor;
364static FNVMEXITHANDLER hmR0VmxExitPause;
365static FNVMEXITHANDLER hmR0VmxExitErrMachineCheck;
366static FNVMEXITHANDLER hmR0VmxExitTprBelowThreshold;
367static FNVMEXITHANDLER hmR0VmxExitApicAccess;
368static FNVMEXITHANDLER hmR0VmxExitXdtrAccess;
369static FNVMEXITHANDLER hmR0VmxExitXdtrAccess;
370static FNVMEXITHANDLER hmR0VmxExitEptViolation;
371static FNVMEXITHANDLER hmR0VmxExitEptMisconfig;
372static FNVMEXITHANDLER hmR0VmxExitRdtscp;
373static FNVMEXITHANDLER hmR0VmxExitPreemptTimer;
374static FNVMEXITHANDLER hmR0VmxExitWbinvd;
375static FNVMEXITHANDLER hmR0VmxExitXsetbv;
376static FNVMEXITHANDLER hmR0VmxExitRdrand;
377static FNVMEXITHANDLER hmR0VmxExitInvpcid;
378/** @} */
379
380static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
381static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
382static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
383static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
384static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
385static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
386static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
387static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
388
389/*******************************************************************************
390* Global Variables *
391*******************************************************************************/
392#ifdef HMVMX_USE_FUNCTION_TABLE
393
394/**
395 * VMX_EXIT dispatch table.
396 */
397static const PFNVMEXITHANDLER g_apfnVMExitHandlers[VMX_EXIT_MAX + 1] =
398{
399 /* 00 VMX_EXIT_XCPT_OR_NMI */ hmR0VmxExitXcptOrNmi,
400 /* 01 VMX_EXIT_EXT_INT */ hmR0VmxExitExtInt,
401 /* 02 VMX_EXIT_TRIPLE_FAULT */ hmR0VmxExitTripleFault,
402 /* 03 VMX_EXIT_INIT_SIGNAL */ hmR0VmxExitInitSignal,
403 /* 04 VMX_EXIT_SIPI */ hmR0VmxExitSipi,
404 /* 05 VMX_EXIT_IO_SMI */ hmR0VmxExitIoSmi,
405 /* 06 VMX_EXIT_SMI */ hmR0VmxExitSmi,
406 /* 07 VMX_EXIT_INT_WINDOW */ hmR0VmxExitIntWindow,
407 /* 08 VMX_EXIT_NMI_WINDOW */ hmR0VmxExitNmiWindow,
408 /* 09 VMX_EXIT_TASK_SWITCH */ hmR0VmxExitTaskSwitch,
409 /* 10 VMX_EXIT_CPUID */ hmR0VmxExitCpuid,
410 /* 11 VMX_EXIT_GETSEC */ hmR0VmxExitGetsec,
411 /* 12 VMX_EXIT_HLT */ hmR0VmxExitHlt,
412 /* 13 VMX_EXIT_INVD */ hmR0VmxExitInvd,
413 /* 14 VMX_EXIT_INVLPG */ hmR0VmxExitInvlpg,
414 /* 15 VMX_EXIT_RDPMC */ hmR0VmxExitRdpmc,
415 /* 16 VMX_EXIT_RDTSC */ hmR0VmxExitRdtsc,
416 /* 17 VMX_EXIT_RSM */ hmR0VmxExitRsm,
417 /* 18 VMX_EXIT_VMCALL */ hmR0VmxExitSetPendingXcptUD,
418 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitSetPendingXcptUD,
419 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitSetPendingXcptUD,
420 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitSetPendingXcptUD,
421 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitSetPendingXcptUD,
422 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitSetPendingXcptUD,
423 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitSetPendingXcptUD,
424 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitSetPendingXcptUD,
425 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitSetPendingXcptUD,
426 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitSetPendingXcptUD,
427 /* 28 VMX_EXIT_MOV_CRX */ hmR0VmxExitMovCRx,
428 /* 29 VMX_EXIT_MOV_DRX */ hmR0VmxExitMovDRx,
429 /* 30 VMX_EXIT_IO_INSTR */ hmR0VmxExitIoInstr,
430 /* 31 VMX_EXIT_RDMSR */ hmR0VmxExitRdmsr,
431 /* 32 VMX_EXIT_WRMSR */ hmR0VmxExitWrmsr,
432 /* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ hmR0VmxExitErrInvalidGuestState,
433 /* 34 VMX_EXIT_ERR_MSR_LOAD */ hmR0VmxExitErrMsrLoad,
434 /* 35 UNDEFINED */ hmR0VmxExitErrUndefined,
435 /* 36 VMX_EXIT_MWAIT */ hmR0VmxExitMwait,
436 /* 37 VMX_EXIT_MTF */ hmR0VmxExitMtf,
437 /* 38 UNDEFINED */ hmR0VmxExitErrUndefined,
438 /* 39 VMX_EXIT_MONITOR */ hmR0VmxExitMonitor,
439 /* 40 UNDEFINED */ hmR0VmxExitPause,
440 /* 41 VMX_EXIT_PAUSE */ hmR0VmxExitErrMachineCheck,
441 /* 42 VMX_EXIT_ERR_MACHINE_CHECK */ hmR0VmxExitErrUndefined,
442 /* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ hmR0VmxExitTprBelowThreshold,
443 /* 44 VMX_EXIT_APIC_ACCESS */ hmR0VmxExitApicAccess,
444 /* 45 UNDEFINED */ hmR0VmxExitErrUndefined,
445 /* 46 VMX_EXIT_XDTR_ACCESS */ hmR0VmxExitXdtrAccess,
446 /* 47 VMX_EXIT_TR_ACCESS */ hmR0VmxExitXdtrAccess,
447 /* 48 VMX_EXIT_EPT_VIOLATION */ hmR0VmxExitEptViolation,
448 /* 49 VMX_EXIT_EPT_MISCONFIG */ hmR0VmxExitEptMisconfig,
449 /* 50 VMX_EXIT_INVEPT */ hmR0VmxExitSetPendingXcptUD,
450 /* 51 VMX_EXIT_RDTSCP */ hmR0VmxExitRdtscp,
451 /* 52 VMX_EXIT_PREEMPT_TIMER */ hmR0VmxExitPreemptTimer,
452 /* 53 VMX_EXIT_INVVPID */ hmR0VmxExitSetPendingXcptUD,
453 /* 54 VMX_EXIT_WBINVD */ hmR0VmxExitWbinvd,
454 /* 55 VMX_EXIT_XSETBV */ hmR0VmxExitXsetbv,
455 /* 56 UNDEFINED */ hmR0VmxExitErrUndefined,
456 /* 57 VMX_EXIT_RDRAND */ hmR0VmxExitRdrand,
457 /* 58 VMX_EXIT_INVPCID */ hmR0VmxExitInvpcid,
458 /* 59 VMX_EXIT_VMFUNC */ hmR0VmxExitSetPendingXcptUD
459};
460#endif /* HMVMX_USE_FUNCTION_TABLE */
461
462#ifdef VBOX_STRICT
463static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
464{
465 /* 0 */ "(Not Used)",
466 /* 1 */ "VMCALL executed in VMX root operation.",
467 /* 2 */ "VMCLEAR with invalid physical address.",
468 /* 3 */ "VMCLEAR with VMXON pointer.",
469 /* 4 */ "VMLAUNCH with non-clear VMCS.",
470 /* 5 */ "VMRESUME with non-launched VMCS.",
471 /* 6 */ "VMRESUME after VMXOFF",
472 /* 7 */ "VM entry with invalid control fields.",
473 /* 8 */ "VM entry with invalid host state fields.",
474 /* 9 */ "VMPTRLD with invalid physical address.",
475 /* 10 */ "VMPTRLD with VMXON pointer.",
476 /* 11 */ "VMPTRLD with incorrect revision identifier.",
477 /* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
478 /* 13 */ "VMWRITE to read-only VMCS component.",
479 /* 14 */ "(Not Used)",
480 /* 15 */ "VMXON executed in VMX root operation.",
481 /* 16 */ "VM entry with invalid executive-VMCS pointer.",
482 /* 17 */ "VM entry with non-launched executing VMCS.",
483 /* 18 */ "VM entry with executive-VMCS pointer not VMXON pointer.",
484 /* 19 */ "VMCALL with non-clear VMCS.",
485 /* 20 */ "VMCALL with invalid VM-exit control fields.",
486 /* 21 */ "(Not Used)",
487 /* 22 */ "VMCALL with incorrect MSEG revision identifier.",
488 /* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
489 /* 24 */ "VMCALL with invalid SMM-monitor features.",
490 /* 25 */ "VM entry with invalid VM-execution control fields in executive VMCS.",
491 /* 26 */ "VM entry with events blocked by MOV SS.",
492 /* 27 */ "(Not Used)",
493 /* 28 */ "Invalid operand to INVEPT/INVVPID."
494};
495#endif /* VBOX_STRICT */
496
497
498
499/**
500 * Updates the VM's last error record. If there was a VMX instruction error,
501 * reads the error data from the VMCS and updates VCPU's last error record as
502 * well.
503 *
504 * @param pVM Pointer to the VM.
505 * @param pVCpu Pointer to the VMCPU (can be NULL if @a rc is not
506 * VERR_VMX_UNABLE_TO_START_VM or
507 * VERR_VMX_INVALID_VMCS_FIELD).
508 * @param rc The error code.
509 */
510static void hmR0VmxUpdateErrorRecord(PVM pVM, PVMCPU pVCpu, int rc)
511{
512 AssertPtr(pVM);
513 if ( rc == VERR_VMX_INVALID_VMCS_FIELD
514 || rc == VERR_VMX_UNABLE_TO_START_VM)
515 {
516 AssertPtrReturnVoid(pVCpu);
517 VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
518 }
519 pVM->hm.s.lLastError = rc;
520}
521
522
523/**
524 * Reads the VM-entry interruption-information field from the VMCS into the VMX
525 * transient structure.
526 *
527 * @returns VBox status code.
528 * @param pVmxTransient Pointer to the VMX transient structure.
529 *
530 * @remarks No-long-jump zone!!!
531 */
532DECLINLINE(int) hmR0VmxReadEntryIntrInfoVmcs(PVMXTRANSIENT pVmxTransient)
533{
534 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntrInfo);
535 AssertRCReturn(rc, rc);
536 return VINF_SUCCESS;
537}
538
539
540/**
541 * Reads the VM-entry exception error code field from the VMCS into
542 * the VMX transient structure.
543 *
544 * @returns VBox status code.
545 * @param pVmxTransient Pointer to the VMX transient structure.
546 *
547 * @remarks No-long-jump zone!!!
548 */
549DECLINLINE(int) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
550{
551 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
552 AssertRCReturn(rc, rc);
553 return VINF_SUCCESS;
554}
555
556
557/**
558 * Reads the VM-entry exception error code field from the VMCS into
559 * the VMX transient structure.
560 *
561 * @returns VBox status code.
562 * @param pVCpu Pointer to the VMCPU.
563 * @param pVmxTransient Pointer to the VMX transient structure.
564 *
565 * @remarks No-long-jump zone!!!
566 */
567DECLINLINE(int) hmR0VmxReadEntryInstrLenVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
568{
569 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
570 AssertRCReturn(rc, rc);
571 return VINF_SUCCESS;
572}
573
574
575/**
576 * Reads the VM-exit interruption-information field from the VMCS into the VMX
577 * transient structure.
578 *
579 * @returns VBox status code.
580 * @param pVCpu Pointer to the VMCPU.
581 * @param pVmxTransient Pointer to the VMX transient structure.
582 */
583DECLINLINE(int) hmR0VmxReadExitIntrInfoVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
584{
585 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO))
586 {
587 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntrInfo);
588 AssertRCReturn(rc, rc);
589 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO;
590 }
591 return VINF_SUCCESS;
592}
593
594
595/**
596 * Reads the VM-exit interruption error code from the VMCS into the VMX
597 * transient structure.
598 *
599 * @returns VBox status code.
600 * @param pVCpu Pointer to the VMCPU.
601 * @param pVmxTransient Pointer to the VMX transient structure.
602 */
603DECLINLINE(int) hmR0VmxReadExitIntrErrorCodeVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
604{
605 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE))
606 {
607 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntrErrorCode);
608 AssertRCReturn(rc, rc);
609 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE;
610 }
611 return VINF_SUCCESS;
612}
613
614
615/**
616 * Reads the VM-exit instruction length field from the VMCS into the VMX
617 * transient structure.
618 *
619 * @returns VBox status code.
620 * @param pVCpu Pointer to the VMCPU.
621 * @param pVmxTransient Pointer to the VMX transient structure.
622 */
623DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
624{
625 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN))
626 {
627 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
628 AssertRCReturn(rc, rc);
629 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN;
630 }
631 return VINF_SUCCESS;
632}
633
634
635/**
636 * Reads the VM-exit instruction-information field from the VMCS into
637 * the VMX transient structure.
638 *
639 * @returns VBox status code.
640 * @param pVCpu The cross context per CPU structure.
641 * @param pVmxTransient Pointer to the VMX transient structure.
642 */
643DECLINLINE(int) hmR0VmxReadExitInstrInfoVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
644{
645 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN))
646 {
647 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->cbInstr);
648 AssertRCReturn(rc, rc);
649 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN;
650 }
651 return VINF_SUCCESS;
652}
653
654
655/**
656 * Reads the exit qualification from the VMCS into the VMX transient structure.
657 *
658 * @returns VBox status code.
659 * @param pVCpu Pointer to the VMCPU.
660 * @param pVmxTransient Pointer to the VMX transient structure.
661 */
662DECLINLINE(int) hmR0VmxReadExitQualificationVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
663{
664 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION))
665 {
666 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQualification);
667 AssertRCReturn(rc, rc);
668 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION;
669 }
670 return VINF_SUCCESS;
671}
672
673
674/**
675 * Reads the IDT-vectoring information field from the VMCS into the VMX
676 * transient structure.
677 *
678 * @returns VBox status code.
679 * @param pVmxTransient Pointer to the VMX transient structure.
680 *
681 * @remarks No-long-jump zone!!!
682 */
683DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
684{
685 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO))
686 {
687 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_INFO, &pVmxTransient->uIdtVectoringInfo);
688 AssertRCReturn(rc, rc);
689 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO;
690 }
691 return VINF_SUCCESS;
692}
693
694
695/**
696 * Reads the IDT-vectoring error code from the VMCS into the VMX
697 * transient structure.
698 *
699 * @returns VBox status code.
700 * @param pVmxTransient Pointer to the VMX transient structure.
701 */
702DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
703{
704 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE))
705 {
706 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
707 AssertRCReturn(rc, rc);
708 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE;
709 }
710 return VINF_SUCCESS;
711}
712
713
714/**
715 * Enters VMX root mode operation on the current CPU.
716 *
717 * @returns VBox status code.
718 * @param pVM Pointer to the VM (optional, can be NULL, after
719 * a resume).
720 * @param HCPhysCpuPage Physical address of the VMXON region.
721 * @param pvCpuPage Pointer to the VMXON region.
722 */
723static int hmR0VmxEnterRootMode(PVM pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
724{
725 AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
726 AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
727 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
728
729 if (pVM)
730 {
731 /* Write the VMCS revision dword to the VMXON region. */
732 *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
733 }
734
735 /* Enable the VMX bit in CR4 if necessary. */
736 RTCCUINTREG uCr4 = ASMGetCR4();
737 if (!(uCr4 & X86_CR4_VMXE))
738 ASMSetCR4(uCr4 | X86_CR4_VMXE);
739
740 /* Enter VMX root mode. */
741 int rc = VMXEnable(HCPhysCpuPage);
742 if (RT_FAILURE(rc))
743 ASMSetCR4(uCr4);
744
745 return rc;
746}
747
748
749/**
750 * Exits VMX root mode operation on the current CPU.
751 *
752 * @returns VBox status code.
753 */
754static int hmR0VmxLeaveRootMode(void)
755{
756 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
757
758 /* If we're for some reason not in VMX root mode, then don't leave it. */
759 RTCCUINTREG uHostCR4 = ASMGetCR4();
760 if (uHostCR4 & X86_CR4_VMXE)
761 {
762 /* Exit VMX root mode and clear the VMX bit in CR4. */
763 VMXDisable();
764 ASMSetCR4(uHostCR4 & ~X86_CR4_VMXE);
765 return VINF_SUCCESS;
766 }
767
768 return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
769}
770
771
772/**
773 * Allocates and maps one physically contiguous page. The allocated page is
774 * zero'd out. (Used by various VT-x structures).
775 *
776 * @returns IPRT status code.
777 * @param pMemObj Pointer to the ring-0 memory object.
778 * @param ppVirt Where to store the virtual address of the
779 * allocation.
780 * @param pPhys Where to store the physical address of the
781 * allocation.
782 */
783DECLINLINE(int) hmR0VmxPageAllocZ(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
784{
785 AssertPtrReturn(pMemObj, VERR_INVALID_PARAMETER);
786 AssertPtrReturn(ppVirt, VERR_INVALID_PARAMETER);
787 AssertPtrReturn(pHCPhys, VERR_INVALID_PARAMETER);
788
789 int rc = RTR0MemObjAllocCont(pMemObj, PAGE_SIZE, false /* fExecutable */);
790 if (RT_FAILURE(rc))
791 return rc;
792 *ppVirt = RTR0MemObjAddress(*pMemObj);
793 *pHCPhys = RTR0MemObjGetPagePhysAddr(*pMemObj, 0 /* iPage */);
794 ASMMemZero32(*ppVirt, PAGE_SIZE);
795 return VINF_SUCCESS;
796}
797
798
799/**
800 * Frees and unmaps an allocated physical page.
801 *
802 * @param pMemObj Pointer to the ring-0 memory object.
803 * @param ppVirt Where to re-initialize the virtual address of
804 * allocation as 0.
805 * @param pHCPhys Where to re-initialize the physical address of the
806 * allocation as 0.
807 */
808DECLINLINE(void) hmR0VmxPageFree(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
809{
810 AssertPtr(pMemObj);
811 AssertPtr(ppVirt);
812 AssertPtr(pHCPhys);
813 if (*pMemObj != NIL_RTR0MEMOBJ)
814 {
815 int rc = RTR0MemObjFree(*pMemObj, true /* fFreeMappings */);
816 AssertRC(rc);
817 *pMemObj = NIL_RTR0MEMOBJ;
818 *ppVirt = 0;
819 *pHCPhys = 0;
820 }
821}
822
823
824/**
825 * Worker function to free VT-x related structures.
826 *
827 * @returns IPRT status code.
828 * @param pVM Pointer to the VM.
829 */
830static void hmR0VmxStructsFree(PVM pVM)
831{
832 for (VMCPUID i = 0; i < pVM->cCpus; i++)
833 {
834 PVMCPU pVCpu = &pVM->aCpus[i];
835 AssertPtr(pVCpu);
836
837#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
838 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
839 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
840#endif
841
842 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
843 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
844
845 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic, &pVCpu->hm.s.vmx.HCPhysVirtApic);
846 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
847 }
848
849 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, &pVM->hm.s.vmx.HCPhysApicAccess);
850#ifdef VBOX_WITH_CRASHDUMP_MAGIC
851 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
852#endif
853}
854
855
856/**
857 * Worker function to allocate VT-x related VM structures.
858 *
859 * @returns IPRT status code.
860 * @param pVM Pointer to the VM.
861 */
862static int hmR0VmxStructsAlloc(PVM pVM)
863{
864 /*
865 * Initialize members up-front so we can cleanup properly on allocation failure.
866 */
867#define VMXLOCAL_INIT_VM_MEMOBJ(a_Name, a_VirtPrefix) \
868 pVM->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
869 pVM->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
870 pVM->hm.s.vmx.HCPhys##a_Name = 0;
871
872#define VMXLOCAL_INIT_VMCPU_MEMOBJ(a_Name, a_VirtPrefix) \
873 pVCpu->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
874 pVCpu->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
875 pVCpu->hm.s.vmx.HCPhys##a_Name = 0;
876
877#ifdef VBOX_WITH_CRASHDUMP_MAGIC
878 VMXLOCAL_INIT_VM_MEMOBJ(Scratch, pv);
879#endif
880 VMXLOCAL_INIT_VM_MEMOBJ(ApicAccess, pb);
881
882 AssertCompile(sizeof(VMCPUID) == sizeof(pVM->cCpus));
883 for (VMCPUID i = 0; i < pVM->cCpus; i++)
884 {
885 PVMCPU pVCpu = &pVM->aCpus[i];
886 VMXLOCAL_INIT_VMCPU_MEMOBJ(Vmcs, pv);
887 VMXLOCAL_INIT_VMCPU_MEMOBJ(VirtApic, pb);
888 VMXLOCAL_INIT_VMCPU_MEMOBJ(MsrBitmap, pv);
889#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
890 VMXLOCAL_INIT_VMCPU_MEMOBJ(GuestMsr, pv);
891 VMXLOCAL_INIT_VMCPU_MEMOBJ(HostMsr, pv);
892#endif
893 }
894#undef VMXLOCAL_INIT_VMCPU_MEMOBJ
895#undef VMXLOCAL_INIT_VM_MEMOBJ
896
897 /*
898 * Allocate all the VT-x structures.
899 */
900 int rc = VINF_SUCCESS;
901#ifdef VBOX_WITH_CRASHDUMP_MAGIC
902 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
903 if (RT_FAILURE(rc))
904 goto cleanup;
905 strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
906 *(uint64_t *)(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
907#endif
908
909 /* Allocate the APIC-access page for trapping APIC accesses from the guest. */
910 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
911 {
912 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
913 &pVM->hm.s.vmx.HCPhysApicAccess);
914 if (RT_FAILURE(rc))
915 goto cleanup;
916 }
917
918 /*
919 * Initialize per-VCPU VT-x structures.
920 */
921 for (VMCPUID i = 0; i < pVM->cCpus; i++)
922 {
923 PVMCPU pVCpu = &pVM->aCpus[i];
924 AssertPtr(pVCpu);
925
926 /* Allocate the VM control structure (VMCS). */
927 AssertReturn(MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo) <= PAGE_SIZE, VERR_INTERNAL_ERROR);
928 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
929 if (RT_FAILURE(rc))
930 goto cleanup;
931
932 /* Allocate the Virtual-APIC page for transparent TPR accesses. */
933 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
934 {
935 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
936 &pVCpu->hm.s.vmx.HCPhysVirtApic);
937 if (RT_FAILURE(rc))
938 goto cleanup;
939 }
940
941 /* Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for transparent accesses of specific MSRs. */
942 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
943 {
944 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
945 &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
946 if (RT_FAILURE(rc))
947 goto cleanup;
948 memset(pVCpu->hm.s.vmx.pvMsrBitmap, 0xff, PAGE_SIZE);
949 }
950
951#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
952 /* Allocate the VM-entry MSR-load and VM-exit MSR-store page for the guest MSRs. */
953 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
954 if (RT_FAILURE(rc))
955 goto cleanup;
956
957 /* Allocate the VM-exit MSR-load page for the host MSRs. */
958 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
959 if (RT_FAILURE(rc))
960 goto cleanup;
961#endif
962 }
963
964 return VINF_SUCCESS;
965
966cleanup:
967 hmR0VmxStructsFree(pVM);
968 return rc;
969}
970
971
972/**
973 * Does global VT-x initialization (called during module initialization).
974 *
975 * @returns VBox status code.
976 */
977VMMR0DECL(int) VMXR0GlobalInit(void)
978{
979#ifdef HMVMX_USE_FUNCTION_TABLE
980 AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_apfnVMExitHandlers));
981# ifdef VBOX_STRICT
982 for (unsigned i = 0; i < RT_ELEMENTS(g_apfnVMExitHandlers); i++)
983 Assert(g_apfnVMExitHandlers[i]);
984# endif
985#endif
986 return VINF_SUCCESS;
987}
988
989
990/**
991 * Does global VT-x termination (called during module termination).
992 */
993VMMR0DECL(void) VMXR0GlobalTerm()
994{
995 /* Nothing to do currently. */
996}
997
998
999/**
1000 * Sets up and activates VT-x on the current CPU.
1001 *
1002 * @returns VBox status code.
1003 * @param pCpu Pointer to the global CPU info struct.
1004 * @param pVM Pointer to the VM (can be NULL after a host resume
1005 * operation).
1006 * @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
1007 * fEnabledByHost is true).
1008 * @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
1009 * @a fEnabledByHost is true).
1010 * @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
1011 * enable VT-x on the host.
1012 * @param pvMsrs Opaque pointer to VMXMSRS struct.
1013 */
1014VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
1015 void *pvMsrs)
1016{
1017 AssertReturn(pCpu, VERR_INVALID_PARAMETER);
1018 AssertReturn(pvMsrs, VERR_INVALID_PARAMETER);
1019 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1020
1021 /* Enable VT-x if it's not already enabled by the host. */
1022 if (!fEnabledByHost)
1023 {
1024 int rc = hmR0VmxEnterRootMode(pVM, HCPhysCpuPage, pvCpuPage);
1025 if (RT_FAILURE(rc))
1026 return rc;
1027 }
1028
1029 /*
1030 * Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been using EPTPs) so
1031 * we don't retain any stale guest-physical mappings which won't get invalidated when flushing by VPID.
1032 */
1033 PVMXMSRS pMsrs = (PVMXMSRS)pvMsrs;
1034 if (pMsrs->u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1035 {
1036 hmR0VmxFlushEpt(NULL /* pVCpu */, VMX_FLUSH_EPT_ALL_CONTEXTS);
1037 pCpu->fFlushAsidBeforeUse = false;
1038 }
1039 else
1040 pCpu->fFlushAsidBeforeUse = true;
1041
1042 /* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
1043 ++pCpu->cTlbFlushes;
1044
1045 return VINF_SUCCESS;
1046}
1047
1048
1049/**
1050 * Deactivates VT-x on the current CPU.
1051 *
1052 * @returns VBox status code.
1053 * @param pCpu Pointer to the global CPU info struct.
1054 * @param pvCpuPage Pointer to the VMXON region.
1055 * @param HCPhysCpuPage Physical address of the VMXON region.
1056 *
1057 * @remarks This function should never be called when SUPR0EnableVTx() or
1058 * similar was used to enable VT-x on the host.
1059 */
1060VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
1061{
1062 NOREF(pCpu);
1063 NOREF(pvCpuPage);
1064 NOREF(HCPhysCpuPage);
1065
1066 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1067 return hmR0VmxLeaveRootMode();
1068}
1069
1070
1071/**
1072 * Sets the permission bits for the specified MSR in the MSR bitmap.
1073 *
1074 * @param pVCpu Pointer to the VMCPU.
1075 * @param uMSR The MSR value.
1076 * @param enmRead Whether reading this MSR causes a VM-exit.
1077 * @param enmWrite Whether writing this MSR causes a VM-exit.
1078 */
1079static void hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite)
1080{
1081 int32_t iBit;
1082 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1083
1084 /*
1085 * Layout:
1086 * 0x000 - 0x3ff - Low MSR read bits
1087 * 0x400 - 0x7ff - High MSR read bits
1088 * 0x800 - 0xbff - Low MSR write bits
1089 * 0xc00 - 0xfff - High MSR write bits
1090 */
1091 if (uMsr <= 0x00001FFF)
1092 iBit = uMsr;
1093 else if ( uMsr >= 0xC0000000
1094 && uMsr <= 0xC0001FFF)
1095 {
1096 iBit = (uMsr - 0xC0000000);
1097 pbMsrBitmap += 0x400;
1098 }
1099 else
1100 {
1101 AssertMsgFailed(("hmR0VmxSetMsrPermission: Invalid MSR %#RX32\n", uMsr));
1102 return;
1103 }
1104
1105 Assert(iBit <= 0x1fff);
1106 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
1107 ASMBitSet(pbMsrBitmap, iBit);
1108 else
1109 ASMBitClear(pbMsrBitmap, iBit);
1110
1111 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
1112 ASMBitSet(pbMsrBitmap + 0x800, iBit);
1113 else
1114 ASMBitClear(pbMsrBitmap + 0x800, iBit);
1115}
1116
1117
1118/**
1119 * Flushes the TLB using EPT.
1120 *
1121 * @returns VBox status code.
1122 * @param pVCpu Pointer to the VMCPU (can be NULL depending on @a
1123 * enmFlush).
1124 * @param enmFlush Type of flush.
1125 *
1126 * @remarks Caller is responsible for making sure this function is called only
1127 * when NestedPaging is supported and providing @a enmFlush that is
1128 * supported by the CPU.
1129 */
1130static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMX_FLUSH_EPT enmFlush)
1131{
1132 uint64_t au64Descriptor[2];
1133 if (enmFlush == VMX_FLUSH_EPT_ALL_CONTEXTS)
1134 au64Descriptor[0] = 0;
1135 else
1136 {
1137 Assert(pVCpu);
1138 au64Descriptor[0] = pVCpu->hm.s.vmx.HCPhysEPTP;
1139 }
1140 au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
1141
1142 int rc = VMXR0InvEPT(enmFlush, &au64Descriptor[0]);
1143 AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvEPT %#x %RGv failed with %Rrc\n", enmFlush, pVCpu ? pVCpu->hm.s.vmx.HCPhysEPTP : 0,
1144 rc));
1145 if ( RT_SUCCESS(rc)
1146 && pVCpu)
1147 {
1148 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
1149 }
1150}
1151
1152
1153/**
1154 * Flushes the TLB using VPID.
1155 *
1156 * @returns VBox status code.
1157 * @param pVM Pointer to the VM.
1158 * @param pVCpu Pointer to the VMCPU (can be NULL depending on @a
1159 * enmFlush).
1160 * @param enmFlush Type of flush.
1161 * @param GCPtr Virtual address of the page to flush (can be 0 depending
1162 * on @a enmFlush).
1163 */
1164static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMX_FLUSH_VPID enmFlush, RTGCPTR GCPtr)
1165{
1166 AssertPtr(pVM);
1167 Assert(pVM->hm.s.vmx.fVpid);
1168
1169 uint64_t au64Descriptor[2];
1170 if (enmFlush == VMX_FLUSH_VPID_ALL_CONTEXTS)
1171 {
1172 au64Descriptor[0] = 0;
1173 au64Descriptor[1] = 0;
1174 }
1175 else
1176 {
1177 AssertPtr(pVCpu);
1178 AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1179 AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1180 au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
1181 au64Descriptor[1] = GCPtr;
1182 }
1183
1184 int rc = VMXR0InvVPID(enmFlush, &au64Descriptor[0]); NOREF(rc);
1185 AssertMsg(rc == VINF_SUCCESS,
1186 ("VMXR0InvVPID %#x %u %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
1187 if ( RT_SUCCESS(rc)
1188 && pVCpu)
1189 {
1190 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1191 }
1192}
1193
1194
1195/**
1196 * Invalidates a guest page by guest virtual address. Only relevant for
1197 * EPT/VPID, otherwise there is nothing really to invalidate.
1198 *
1199 * @returns VBox status code.
1200 * @param pVM Pointer to the VM.
1201 * @param pVCpu Pointer to the VMCPU.
1202 * @param GCVirt Guest virtual address of the page to invalidate.
1203 */
1204VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1205{
1206 AssertPtr(pVM);
1207 AssertPtr(pVCpu);
1208 LogFlowFunc(("pVM=%p pVCpu=%p GCVirt=%RGv\n", pVM, pVCpu, GCVirt));
1209
1210 bool fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1211 if (!fFlushPending)
1212 {
1213 /*
1214 * We must invalidate the guest TLB entry in either case, we cannot ignore it even for the EPT case
1215 * See @bugref{6043} and @bugref{6177}.
1216 *
1217 * Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*() as this
1218 * function maybe called in a loop with individual addresses.
1219 */
1220 if (pVM->hm.s.vmx.fVpid)
1221 {
1222 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1223 {
1224 hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, GCVirt);
1225 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1226 }
1227 else
1228 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1229 }
1230 else if (pVM->hm.s.fNestedPaging)
1231 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1232 }
1233
1234 return VINF_SUCCESS;
1235}
1236
1237
1238/**
1239 * Invalidates a guest page by physical address. Only relevant for EPT/VPID,
1240 * otherwise there is nothing really to invalidate.
1241 *
1242 * @returns VBox status code.
1243 * @param pVM Pointer to the VM.
1244 * @param pVCpu Pointer to the VMCPU.
1245 * @param GCPhys Guest physical address of the page to invalidate.
1246 */
1247VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
1248{
1249 LogFlowFunc(("%RGp\n", GCPhys));
1250
1251 /*
1252 * We cannot flush a page by guest-physical address. invvpid takes only a linear address while invept only flushes
1253 * by EPT not individual addresses. We update the force flag here and flush before the next VM-entry in hmR0VmxFlushTLB*().
1254 * This function might be called in a loop. This should cause a flush-by-EPT if EPT is in use. See @bugref{6568}.
1255 */
1256 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1257 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys);
1258 return VINF_SUCCESS;
1259}
1260
1261
1262/**
1263 * Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
1264 * case where neither EPT nor VPID is supported by the CPU.
1265 *
1266 * @param pVM Pointer to the VM.
1267 * @param pVCpu Pointer to the VMCPU.
1268 * @param pCpu Pointer to the global HM struct.
1269 *
1270 * @remarks Called with interrupts disabled.
1271 */
1272static void hmR0VmxFlushTaggedTlbNone(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1273{
1274 AssertPtr(pVCpu);
1275 AssertPtr(pCpu);
1276 NOREF(pVM);
1277
1278 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1279 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1280
1281 pVCpu->hm.s.TlbShootdown.cPages = 0;
1282 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1283 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1284 pVCpu->hm.s.fForceTLBFlush = false;
1285 return;
1286}
1287
1288
1289/**
1290 * Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
1291 *
1292 * @param pVM Pointer to the VM.
1293 * @param pVCpu Pointer to the VMCPU.
1294 * @param pCpu Pointer to the global HM CPU struct.
1295 * @remarks All references to "ASID" in this function pertains to "VPID" in
1296 * Intel's nomenclature. The reason is, to avoid confusion in compare
1297 * statements since the host-CPU copies are named "ASID".
1298 *
1299 * @remarks Called with interrupts disabled.
1300 */
1301static void hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1302{
1303#ifdef VBOX_WITH_STATISTICS
1304 bool fTlbFlushed = false;
1305# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
1306# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
1307 if (!fTlbFlushed) \
1308 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
1309 } while (0)
1310#else
1311# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
1312# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
1313#endif
1314
1315 AssertPtr(pVM);
1316 AssertPtr(pCpu);
1317 AssertPtr(pVCpu);
1318 AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
1319 ("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
1320 "fNestedPaging=%RTbool fVpid=%RTbool", pVM->hm.s.fNestedPaging, pVM->hm.s.vmx.fVpid));
1321
1322
1323 /*
1324 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
1325 * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
1326 * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
1327 */
1328 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1329 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1330 {
1331 ++pCpu->uCurrentAsid;
1332 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1333 {
1334 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
1335 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1336 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1337 }
1338
1339 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1340 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1341 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1342
1343 /*
1344 * Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
1345 * invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
1346 */
1347 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
1348 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1349 HMVMX_SET_TAGGED_TLB_FLUSHED();
1350 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH); /* Already flushed-by-EPT, skip doing it again below. */
1351 }
1352
1353 /* Check for explicit TLB shootdowns. */
1354 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1355 {
1356 /*
1357 * Changes to the EPT paging structure by VMM requires flushing by EPT as the CPU creates
1358 * guest-physical (only EPT-tagged) mappings while traversing the EPT tables when EPT is in use.
1359 * Flushing by VPID will only flush linear (only VPID-tagged) and combined (EPT+VPID tagged) mappings
1360 * but not guest-physical mappings.
1361 * See Intel spec. 28.3.2 "Creating and Using Cached Translation Information". See @bugref{6568}.
1362 */
1363 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
1364 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1365 HMVMX_SET_TAGGED_TLB_FLUSHED();
1366 }
1367
1368 /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
1369 * not be executed. See hmQueueInvlPage() where it is commented
1370 * out. Support individual entry flushing someday. */
1371 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1372 {
1373 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
1374
1375 /*
1376 * Flush individual guest entries using VPID from the TLB or as little as possible with EPT
1377 * as supported by the CPU.
1378 */
1379 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1380 {
1381 for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
1382 hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
1383 }
1384 else
1385 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
1386
1387 HMVMX_SET_TAGGED_TLB_FLUSHED();
1388 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1389 }
1390
1391 pVCpu->hm.s.TlbShootdown.cPages = 0;
1392 pVCpu->hm.s.fForceTLBFlush = false;
1393
1394 HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
1395
1396 Assert(pVCpu->hm.s.idLastCpu == pCpu->idCpu);
1397 Assert(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes);
1398 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1399 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1400 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1401 ("cpu%d uCurrentAsid = %u\n", pCpu->idCpu, pCpu->uCurrentAsid));
1402 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1403 ("cpu%d VM uCurrentAsid = %u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1404
1405 /* Update VMCS with the VPID. */
1406 int rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
1407 AssertRC(rc);
1408
1409#undef HMVMX_SET_TAGGED_TLB_FLUSHED
1410}
1411
1412
1413/**
1414 * Flushes the tagged-TLB entries for EPT CPUs as necessary.
1415 *
1416 * @returns VBox status code.
1417 * @param pVM Pointer to the VM.
1418 * @param pVCpu Pointer to the VMCPU.
1419 * @param pCpu Pointer to the global HM CPU struct.
1420 *
1421 * @remarks Called with interrupts disabled.
1422 */
1423static void hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1424{
1425 AssertPtr(pVM);
1426 AssertPtr(pVCpu);
1427 AssertPtr(pCpu);
1428 AssertMsg(pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with NestedPaging disabled."));
1429 AssertMsg(!pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID enabled."));
1430
1431 /*
1432 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
1433 * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
1434 */
1435 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1436 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1437 {
1438 pVCpu->hm.s.fForceTLBFlush = true;
1439 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1440 }
1441
1442 /* Check for explicit TLB shootdown flushes. */
1443 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1444 {
1445 pVCpu->hm.s.fForceTLBFlush = true;
1446 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1447 }
1448
1449 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1450 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1451
1452 if (pVCpu->hm.s.fForceTLBFlush)
1453 {
1454 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
1455 pVCpu->hm.s.fForceTLBFlush = false;
1456 }
1457 else
1458 {
1459 /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
1460 * not be executed. See hmQueueInvlPage() where it is commented
1461 * out. Support individual entry flushing someday. */
1462 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1463 {
1464 /* We cannot flush individual entries without VPID support. Flush using EPT. */
1465 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
1466 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
1467 }
1468 else
1469 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1470 }
1471
1472 pVCpu->hm.s.TlbShootdown.cPages = 0;
1473 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1474}
1475
1476
1477/**
1478 * Flushes the tagged-TLB entries for VPID CPUs as necessary.
1479 *
1480 * @returns VBox status code.
1481 * @param pVM Pointer to the VM.
1482 * @param pVCpu Pointer to the VMCPU.
1483 * @param pCpu Pointer to the global HM CPU struct.
1484 *
1485 * @remarks Called with interrupts disabled.
1486 */
1487static void hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1488{
1489 AssertPtr(pVM);
1490 AssertPtr(pVCpu);
1491 AssertPtr(pCpu);
1492 AssertMsg(pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked with VPID disabled."));
1493 AssertMsg(!pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging enabled"));
1494
1495 /*
1496 * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1497 * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
1498 * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
1499 */
1500 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1501 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1502 {
1503 pVCpu->hm.s.fForceTLBFlush = true;
1504 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1505 }
1506
1507 /* Check for explicit TLB shootdown flushes. */
1508 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1509 {
1510 /*
1511 * If we ever support VPID flush combinations other than ALL or SINGLE-context (see hmR0VmxSetupTaggedTlb())
1512 * we would need to explicitly flush in this case (add an fExplicitFlush = true here and change the
1513 * pCpu->fFlushAsidBeforeUse check below to include fExplicitFlush's too) - an obscure corner case.
1514 */
1515 pVCpu->hm.s.fForceTLBFlush = true;
1516 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1517 }
1518
1519 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1520 if (pVCpu->hm.s.fForceTLBFlush)
1521 {
1522 ++pCpu->uCurrentAsid;
1523 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1524 {
1525 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
1526 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1527 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1528 }
1529
1530 pVCpu->hm.s.fForceTLBFlush = false;
1531 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1532 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1533 if (pCpu->fFlushAsidBeforeUse)
1534 hmR0VmxFlushVpid(pVM, pVCpu, pVM->hm.s.vmx.enmFlushVpid, 0 /* GCPtr */);
1535 }
1536 else
1537 {
1538 AssertMsg(pVCpu->hm.s.uCurrentAsid && pCpu->uCurrentAsid,
1539 ("hm->uCurrentAsid=%lu hm->cTlbFlushes=%lu cpu->uCurrentAsid=%lu cpu->cTlbFlushes=%lu\n",
1540 pVCpu->hm.s.uCurrentAsid, pVCpu->hm.s.cTlbFlushes,
1541 pCpu->uCurrentAsid, pCpu->cTlbFlushes));
1542
1543 /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
1544 * not be executed. See hmQueueInvlPage() where it is commented
1545 * out. Support individual entry flushing someday. */
1546 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1547 {
1548 /* Flush individual guest entries using VPID or as little as possible with EPT as supported by the CPU. */
1549 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1550 {
1551 for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
1552 hmR0VmxFlushVpid(pVM, pVCpu, VMX_FLUSH_VPID_INDIV_ADDR, pVCpu->hm.s.TlbShootdown.aPages[i]);
1553 }
1554 else
1555 hmR0VmxFlushVpid(pVM, pVCpu, pVM->hm.s.vmx.enmFlushVpid, 0 /* GCPtr */);
1556 }
1557 else
1558 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1559 }
1560
1561 pVCpu->hm.s.TlbShootdown.cPages = 0;
1562 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1563
1564 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1565 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1566 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1567 ("cpu%d uCurrentAsid = %u\n", pCpu->idCpu, pCpu->uCurrentAsid));
1568 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1569 ("cpu%d VM uCurrentAsid = %u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1570
1571 int rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hm.s.uCurrentAsid);
1572 AssertRC(rc);
1573}
1574
1575
1576/**
1577 * Flushes the guest TLB entry based on CPU capabilities.
1578 *
1579 * @param pVCpu Pointer to the VMCPU.
1580 * @param pCpu Pointer to the global HM CPU struct.
1581 */
1582DECLINLINE(void) hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1583{
1584 PVM pVM = pVCpu->CTX_SUFF(pVM);
1585 switch (pVM->hm.s.vmx.uFlushTaggedTlb)
1586 {
1587 case HMVMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVM, pVCpu, pCpu); break;
1588 case HMVMX_FLUSH_TAGGED_TLB_EPT: hmR0VmxFlushTaggedTlbEpt(pVM, pVCpu, pCpu); break;
1589 case HMVMX_FLUSH_TAGGED_TLB_VPID: hmR0VmxFlushTaggedTlbVpid(pVM, pVCpu, pCpu); break;
1590 case HMVMX_FLUSH_TAGGED_TLB_NONE: hmR0VmxFlushTaggedTlbNone(pVM, pVCpu, pCpu); break;
1591 default:
1592 AssertMsgFailed(("Invalid flush-tag function identifier\n"));
1593 break;
1594 }
1595}
1596
1597
1598/**
1599 * Sets up the appropriate tagged TLB-flush level and handler for flushing guest
1600 * TLB entries from the host TLB before VM-entry.
1601 *
1602 * @returns VBox status code.
1603 * @param pVM Pointer to the VM.
1604 */
1605static int hmR0VmxSetupTaggedTlb(PVM pVM)
1606{
1607 /*
1608 * Determine optimal flush type for Nested Paging.
1609 * We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup unrestricted
1610 * guest execution (see hmR3InitFinalizeR0()).
1611 */
1612 if (pVM->hm.s.fNestedPaging)
1613 {
1614 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
1615 {
1616 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
1617 pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT;
1618 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1619 pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS;
1620 else
1621 {
1622 /* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
1623 pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
1624 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1625 }
1626
1627 /* Make sure the write-back cacheable memory type for EPT is supported. */
1628 if (!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB))
1629 {
1630 LogRel(("hmR0VmxSetupTaggedTlb: Unsupported EPTP memory type %#x.\n", pVM->hm.s.vmx.Msrs.u64EptVpidCaps));
1631 pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
1632 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1633 }
1634 }
1635 else
1636 {
1637 /* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
1638 pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED;
1639 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1640 }
1641 }
1642
1643 /*
1644 * Determine optimal flush type for VPID.
1645 */
1646 if (pVM->hm.s.vmx.fVpid)
1647 {
1648 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
1649 {
1650 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
1651 pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT;
1652 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
1653 pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS;
1654 else
1655 {
1656 /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
1657 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1658 LogRel(("hmR0VmxSetupTaggedTlb: Only INDIV_ADDR supported. Ignoring VPID.\n"));
1659 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1660 LogRel(("hmR0VmxSetupTaggedTlb: Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
1661 pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED;
1662 pVM->hm.s.vmx.fVpid = false;
1663 }
1664 }
1665 else
1666 {
1667 /* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
1668 Log4(("hmR0VmxSetupTaggedTlb: VPID supported without INVEPT support. Ignoring VPID.\n"));
1669 pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NOT_SUPPORTED;
1670 pVM->hm.s.vmx.fVpid = false;
1671 }
1672 }
1673
1674 /*
1675 * Setup the handler for flushing tagged-TLBs.
1676 */
1677 if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
1678 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT_VPID;
1679 else if (pVM->hm.s.fNestedPaging)
1680 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT;
1681 else if (pVM->hm.s.vmx.fVpid)
1682 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_VPID;
1683 else
1684 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_NONE;
1685 return VINF_SUCCESS;
1686}
1687
1688
1689/**
1690 * Sets up pin-based VM-execution controls in the VMCS.
1691 *
1692 * @returns VBox status code.
1693 * @param pVM Pointer to the VM.
1694 * @param pVCpu Pointer to the VMCPU.
1695 */
1696static int hmR0VmxSetupPinCtls(PVM pVM, PVMCPU pVCpu)
1697{
1698 AssertPtr(pVM);
1699 AssertPtr(pVCpu);
1700
1701 uint32_t val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0; /* Bits set here must always be set. */
1702 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
1703
1704 val |= VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT /* External interrupts causes a VM-exits. */
1705 | VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT; /* Non-maskable interrupts causes a VM-exit. */
1706 Assert(!(val & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI));
1707
1708 /* Enable the VMX preemption timer. */
1709 if (pVM->hm.s.vmx.fUsePreemptTimer)
1710 {
1711 Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1712 val |= VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER;
1713 }
1714
1715 if ((val & zap) != val)
1716 {
1717 LogRel(("hmR0VmxSetupPinCtls: invalid pin-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
1718 pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0, val, zap));
1719 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
1720 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1721 }
1722
1723 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, val);
1724 AssertRCReturn(rc, rc);
1725
1726 /* Update VCPU with the currently set pin-based VM-execution controls. */
1727 pVCpu->hm.s.vmx.u32PinCtls = val;
1728 return rc;
1729}
1730
1731
1732/**
1733 * Sets up processor-based VM-execution controls in the VMCS.
1734 *
1735 * @returns VBox status code.
1736 * @param pVM Pointer to the VM.
1737 * @param pVMCPU Pointer to the VMCPU.
1738 */
1739static int hmR0VmxSetupProcCtls(PVM pVM, PVMCPU pVCpu)
1740{
1741 AssertPtr(pVM);
1742 AssertPtr(pVCpu);
1743
1744 int rc = VERR_INTERNAL_ERROR_5;
1745 uint32_t val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
1746 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
1747
1748 val |= VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT /* HLT causes a VM-exit. */
1749 | VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
1750 | VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
1751 | VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
1752 | VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT /* RDPMC causes a VM-exit. */
1753 | VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT /* MONITOR causes a VM-exit. */
1754 | VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
1755
1756 /* We toggle VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
1757 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT)
1758 || (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT))
1759 {
1760 LogRel(("hmR0VmxSetupProcCtls: unsupported VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT combo!"));
1761 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
1762 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1763 }
1764
1765 /* Without Nested Paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
1766 if (!pVM->hm.s.fNestedPaging)
1767 {
1768 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest); /* Paranoia. */
1769 val |= VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT
1770 | VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
1771 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
1772 }
1773
1774 /* Use TPR shadowing if supported by the CPU. */
1775 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
1776 {
1777 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
1778 Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
1779 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
1780 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
1781 AssertRCReturn(rc, rc);
1782
1783 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
1784 /* CR8 writes causes a VM-exit based on TPR threshold. */
1785 Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT));
1786 Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT));
1787 }
1788 else
1789 {
1790 val |= VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT /* CR8 reads causes a VM-exit. */
1791 | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT; /* CR8 writes causes a VM-exit. */
1792 }
1793
1794 /* Use MSR-bitmaps if supported by the CPU. */
1795 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1796 {
1797 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS;
1798
1799 Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1800 Assert(!(pVCpu->hm.s.vmx.HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
1801 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1802 AssertRCReturn(rc, rc);
1803
1804 /*
1805 * The guest can access the following MSRs (read, write) without causing VM-exits; they are loaded/stored
1806 * automatically (either as part of the MSR-load/store areas or dedicated fields in the VMCS).
1807 */
1808 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1809 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1810 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1811 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_LSTAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1812 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_STAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1813 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_SF_MASK, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1814 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1815 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1816 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_FS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1817 }
1818
1819 /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
1820 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1821 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
1822
1823 if ((val & zap) != val)
1824 {
1825 LogRel(("hmR0VmxSetupProcCtls: invalid processor-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
1826 pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0, val, zap));
1827 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
1828 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1829 }
1830
1831 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, val);
1832 AssertRCReturn(rc, rc);
1833
1834 /* Update VCPU with the currently set processor-based VM-execution controls. */
1835 pVCpu->hm.s.vmx.u32ProcCtls = val;
1836
1837 /*
1838 * Secondary processor-based VM-execution controls.
1839 */
1840 if (RT_LIKELY(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL))
1841 {
1842 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */
1843 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
1844
1845 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
1846 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT; /* WBINVD causes a VM-exit. */
1847
1848 if (pVM->hm.s.fNestedPaging)
1849 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT; /* Enable EPT. */
1850 else
1851 {
1852 /*
1853 * Without Nested Paging, INVPCID should cause a VM-exit. Enabling this bit causes the CPU to refer to
1854 * VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT when INVPCID is executed by the guest.
1855 * See Intel spec. 25.4 "Changes to instruction behaviour in VMX non-root operation".
1856 */
1857 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_INVPCID)
1858 val |= VMX_VMCS_CTRL_PROC_EXEC2_INVPCID;
1859 }
1860
1861 if (pVM->hm.s.vmx.fVpid)
1862 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID; /* Enable VPID. */
1863
1864 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1865 val |= VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST; /* Enable Unrestricted Execution. */
1866
1867 /* Enable Virtual-APIC page accesses if supported by the CPU. This is essentially where the TPR shadow resides. */
1868 /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
1869 * done dynamically. */
1870 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
1871 {
1872 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
1873 Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
1874 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC; /* Virtualize APIC accesses. */
1875 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
1876 AssertRCReturn(rc, rc);
1877 }
1878
1879 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
1880 {
1881 val |= VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP; /* Enable RDTSCP support. */
1882 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1883 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1884 }
1885
1886 if ((val & zap) != val)
1887 {
1888 LogRel(("hmR0VmxSetupProcCtls: invalid secondary processor-based VM-execution controls combo! "
1889 "cpu=%#RX64 val=%#RX64 zap=%#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0, val, zap));
1890 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1891 }
1892
1893 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, val);
1894 AssertRCReturn(rc, rc);
1895
1896 /* Update VCPU with the currently set secondary processor-based VM-execution controls. */
1897 pVCpu->hm.s.vmx.u32ProcCtls2 = val;
1898 }
1899 else if (RT_UNLIKELY(pVM->hm.s.vmx.fUnrestrictedGuest))
1900 {
1901 LogRel(("hmR0VmxSetupProcCtls: Unrestricted Guest set as true when secondary processor-based VM-execution controls not "
1902 "available\n"));
1903 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1904 }
1905
1906 return VINF_SUCCESS;
1907}
1908
1909
1910/**
1911 * Sets up miscellaneous (everything other than Pin & Processor-based
1912 * VM-execution) control fields in the VMCS.
1913 *
1914 * @returns VBox status code.
1915 * @param pVM Pointer to the VM.
1916 * @param pVCpu Pointer to the VMCPU.
1917 */
1918static int hmR0VmxSetupMiscCtls(PVM pVM, PVMCPU pVCpu)
1919{
1920 AssertPtr(pVM);
1921 AssertPtr(pVCpu);
1922
1923 int rc = VERR_GENERAL_FAILURE;
1924
1925 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
1926#if 0
1927 /* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxLoadGuestControlRegs())*/
1928 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0); AssertRCReturn(rc, rc);
1929 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0); AssertRCReturn(rc, rc);
1930
1931 /*
1932 * Set MASK & MATCH to 0. VMX checks if GuestPFErrCode & MASK == MATCH. If equal (in our case it always is)
1933 * and if the X86_XCPT_PF bit in the exception bitmap is set it causes a VM-exit, if clear doesn't cause an exit.
1934 * We thus use the exception bitmap to control it rather than use both.
1935 */
1936 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0); AssertRCReturn(rc, rc);
1937 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0); AssertRCReturn(rc, rc);
1938
1939 /** @todo Explore possibility of using IO-bitmaps. */
1940 /* All IO & IOIO instructions cause VM-exits. */
1941 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0); AssertRCReturn(rc, rc);
1942 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0); AssertRCReturn(rc, rc);
1943
1944 /* Initialize the MSR-bitmap area. */
1945 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0); AssertRCReturn(rc, rc);
1946 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0); AssertRCReturn(rc, rc);
1947 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0); AssertRCReturn(rc, rc);
1948#endif
1949
1950#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
1951 /* Setup MSR autoloading/storing. */
1952 Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
1953 Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf)); /* Lower 4 bits MBZ. */
1954 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
1955 AssertRCReturn(rc, rc);
1956 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
1957 AssertRCReturn(rc, rc);
1958
1959 Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
1960 Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf)); /* Lower 4 bits MBZ. */
1961 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
1962 AssertRCReturn(rc, rc);
1963#endif
1964
1965 /* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
1966 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
1967 AssertRCReturn(rc, rc);
1968
1969 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
1970#if 0
1971 /* Setup debug controls */
1972 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0); /** @todo We don't support IA32_DEBUGCTL MSR. Should we? */
1973 AssertRCReturn(rc, rc);
1974 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
1975 AssertRCReturn(rc, rc);
1976#endif
1977
1978 return rc;
1979}
1980
1981
1982/**
1983 * Sets up the initial exception bitmap in the VMCS based on static conditions
1984 * (i.e. conditions that cannot ever change after starting the VM).
1985 *
1986 * @returns VBox status code.
1987 * @param pVM Pointer to the VM.
1988 * @param pVCpu Pointer to the VMCPU.
1989 */
1990static int hmR0VmxInitXcptBitmap(PVM pVM, PVMCPU pVCpu)
1991{
1992 AssertPtr(pVM);
1993 AssertPtr(pVCpu);
1994
1995 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1996
1997 uint32_t u32XcptBitmap = 0;
1998
1999 /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
2000 if (!pVM->hm.s.fNestedPaging)
2001 u32XcptBitmap |= RT_BIT(X86_XCPT_PF);
2002
2003 pVCpu->hm.s.vmx.u32XcptBitmap = u32XcptBitmap;
2004 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);
2005 AssertRCReturn(rc, rc);
2006 return rc;
2007}
2008
2009
2010/**
2011 * Sets up the initial guest-state mask. The guest-state mask is consulted
2012 * before reading guest-state fields from the VMCS as VMREADs can be expensive
2013 * for the nested virtualization case (as it would cause a VM-exit).
2014 *
2015 * @param pVCpu Pointer to the VMCPU.
2016 */
2017static int hmR0VmxInitUpdatedGuestStateMask(PVMCPU pVCpu)
2018{
2019 /* Initially the guest-state is up-to-date as there is nothing in the VMCS. */
2020 pVCpu->hm.s.vmx.fUpdatedGuestState = HMVMX_UPDATED_GUEST_ALL;
2021 return VINF_SUCCESS;
2022}
2023
2024
2025/**
2026 * Does per-VM VT-x initialization.
2027 *
2028 * @returns VBox status code.
2029 * @param pVM Pointer to the VM.
2030 */
2031VMMR0DECL(int) VMXR0InitVM(PVM pVM)
2032{
2033 LogFlowFunc(("pVM=%p\n", pVM));
2034
2035 int rc = hmR0VmxStructsAlloc(pVM);
2036 if (RT_FAILURE(rc))
2037 {
2038 LogRel(("VMXR0InitVM: hmR0VmxStructsAlloc failed! rc=%Rrc\n", rc));
2039 return rc;
2040 }
2041
2042 return VINF_SUCCESS;
2043}
2044
2045
2046/**
2047 * Does per-VM VT-x termination.
2048 *
2049 * @returns VBox status code.
2050 * @param pVM Pointer to the VM.
2051 */
2052VMMR0DECL(int) VMXR0TermVM(PVM pVM)
2053{
2054 LogFlowFunc(("pVM=%p\n", pVM));
2055
2056#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2057 if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
2058 ASMMemZero32(pVM->hm.s.vmx.pvScratch, PAGE_SIZE);
2059#endif
2060 hmR0VmxStructsFree(pVM);
2061 return VINF_SUCCESS;
2062}
2063
2064
2065/**
2066 * Sets up the VM for execution under VT-x.
2067 * This function is only called once per-VM during initialization.
2068 *
2069 * @returns VBox status code.
2070 * @param pVM Pointer to the VM.
2071 */
2072VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
2073{
2074 AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
2075 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2076
2077 LogFlowFunc(("pVM=%p\n", pVM));
2078
2079 /*
2080 * Without UnrestrictedGuest, pRealModeTSS and pNonPagingModeEPTPageTable *must* always be allocated.
2081 * We no longer support the highly unlikely case of UnrestrictedGuest without pRealModeTSS. See hmR3InitFinalizeR0().
2082 */
2083 /* -XXX- change hmR3InitFinalizeR0Intel() to fail if pRealModeTSS alloc fails. */
2084 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
2085 && ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
2086 || !pVM->hm.s.vmx.pRealModeTSS))
2087 {
2088 LogRel(("VMXR0SetupVM: invalid real-on-v86 state.\n"));
2089 return VERR_INTERNAL_ERROR;
2090 }
2091
2092#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2093 /*
2094 * This is for the darwin 32-bit/PAE kernels trying to execute 64-bit guests. We don't bother with
2095 * the 32<->64 switcher in this case. This is a rare, legacy use-case with barely any test coverage.
2096 */
2097 if ( pVM->hm.s.fAllow64BitGuests
2098 && !HMVMX_IS_64BIT_HOST_MODE())
2099 {
2100 LogRel(("VMXR0SetupVM: Unsupported guest and host paging mode combination.\n"));
2101 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
2102 }
2103#endif
2104
2105 /* Initialize these always, see hmR3InitFinalizeR0().*/
2106 pVM->hm.s.vmx.enmFlushEpt = VMX_FLUSH_EPT_NONE;
2107 pVM->hm.s.vmx.enmFlushVpid = VMX_FLUSH_VPID_NONE;
2108
2109 /* Setup the tagged-TLB flush handlers. */
2110 int rc = hmR0VmxSetupTaggedTlb(pVM);
2111 if (RT_FAILURE(rc))
2112 {
2113 LogRel(("VMXR0SetupVM: hmR0VmxSetupTaggedTlb failed! rc=%Rrc\n", rc));
2114 return rc;
2115 }
2116
2117 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2118 {
2119 PVMCPU pVCpu = &pVM->aCpus[i];
2120 AssertPtr(pVCpu);
2121 AssertPtr(pVCpu->hm.s.vmx.pvVmcs);
2122
2123 /* Log the VCPU pointers, useful for debugging SMP VMs. */
2124 Log4(("VMXR0SetupVM: pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
2125
2126 /* Set revision dword at the beginning of the VMCS structure. */
2127 *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
2128
2129 /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
2130 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2131 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2132 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2133
2134 /* Load this VMCS as the current VMCS. */
2135 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2136 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2137 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2138
2139 rc = hmR0VmxSetupPinCtls(pVM, pVCpu);
2140 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2141 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2142
2143 rc = hmR0VmxSetupProcCtls(pVM, pVCpu);
2144 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2145 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2146
2147 rc = hmR0VmxSetupMiscCtls(pVM, pVCpu);
2148 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2149 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2150
2151 rc = hmR0VmxInitXcptBitmap(pVM, pVCpu);
2152 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2153 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2154
2155 rc = hmR0VmxInitUpdatedGuestStateMask(pVCpu);
2156 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitUpdatedGuestStateMask failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2157 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2158
2159#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2160 rc = hmR0VmxInitVmcsReadCache(pVM, pVCpu);
2161 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2162 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2163#endif
2164
2165 /* Re-sync the CPU's internal data into our VMCS memory region & reset the launch state to "clear". */
2166 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2167 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2168 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2169
2170 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
2171
2172 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc);
2173 }
2174
2175 return VINF_SUCCESS;
2176}
2177
2178
2179/**
2180 * Saves the host control registers (CR0, CR3, CR4) into the host-state area in
2181 * the VMCS.
2182 *
2183 * @returns VBox status code.
2184 * @param pVM Pointer to the VM.
2185 * @param pVCpu Pointer to the VMCPU.
2186 */
2187DECLINLINE(int) hmR0VmxSaveHostControlRegs(PVM pVM, PVMCPU pVCpu)
2188{
2189 RTCCUINTREG uReg = ASMGetCR0();
2190 int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
2191 AssertRCReturn(rc, rc);
2192
2193#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2194 /* For the darwin 32-bit hybrid kernel, we need the 64-bit CR3 as it uses 64-bit paging. */
2195 if (HMVMX_IS_64BIT_HOST_MODE())
2196 {
2197 uint64_t uRegCR3 = HMR0Get64bitCR3();
2198 rc = VMXWriteVmcs64(VMX_VMCS_HOST_CR3, uRegCR3);
2199 }
2200 else
2201#endif
2202 {
2203 uReg = ASMGetCR3();
2204 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
2205 }
2206 AssertRCReturn(rc, rc);
2207
2208 uReg = ASMGetCR4();
2209 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
2210 AssertRCReturn(rc, rc);
2211 return rc;
2212}
2213
2214
2215/**
2216 * Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
2217 * the host-state area in the VMCS.
2218 *
2219 * @returns VBox status code.
2220 * @param pVM Pointer to the VM.
2221 * @param pVCpu Pointer to the VMCPU.
2222 */
2223DECLINLINE(int) hmR0VmxSaveHostSegmentRegs(PVM pVM, PVMCPU pVCpu)
2224{
2225 int rc = VERR_INTERNAL_ERROR_5;
2226 RTSEL uSelDS = 0;
2227 RTSEL uSelES = 0;
2228 RTSEL uSelFS = 0;
2229 RTSEL uSelGS = 0;
2230 RTSEL uSelTR = 0;
2231
2232 /*
2233 * Host DS, ES, FS and GS segment registers.
2234 */
2235#if HC_ARCH_BITS == 64
2236 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
2237 uSelDS = ASMGetDS();
2238 uSelES = ASMGetES();
2239 uSelFS = ASMGetFS();
2240 uSelGS = ASMGetGS();
2241#endif
2242
2243 /*
2244 * Host CS and SS segment registers.
2245 */
2246 RTSEL uSelCS;
2247 RTSEL uSelSS;
2248#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2249 if (HMVMX_IS_64BIT_HOST_MODE())
2250 {
2251 uSelCS = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
2252 uSelSS = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
2253 }
2254 else
2255 {
2256 /* Seems darwin uses the LDT (TI flag is set) in the CS & SS selectors which VT-x doesn't like. */
2257 uSelCS = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
2258 uSelSS = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
2259 }
2260#else
2261 uSelCS = ASMGetCS();
2262 uSelSS = ASMGetSS();
2263#endif
2264
2265 /*
2266 * Host TR segment register.
2267 */
2268 uSelTR = ASMGetTR();
2269
2270#if HC_ARCH_BITS == 64
2271 /*
2272 * Determine if the host segment registers are suitable for VT-x. Otherwise use zero to gain VM-entry and restore them
2273 * before we get preempted. See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
2274 */
2275 if (uSelDS & (X86_SEL_RPL | X86_SEL_LDT))
2276 {
2277 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_DS;
2278 pVCpu->hm.s.vmx.RestoreHost.uHostSelDS = uSelDS;
2279 uSelDS = 0;
2280 }
2281 if (uSelES & (X86_SEL_RPL | X86_SEL_LDT))
2282 {
2283 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_ES;
2284 pVCpu->hm.s.vmx.RestoreHost.uHostSelES = uSelES;
2285 uSelES = 0;
2286 }
2287 if (uSelFS & (X86_SEL_RPL | X86_SEL_LDT))
2288 {
2289 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_FS;
2290 pVCpu->hm.s.vmx.RestoreHost.uHostSelFS = uSelFS;
2291 uSelFS = 0;
2292 }
2293 if (uSelGS & (X86_SEL_RPL | X86_SEL_LDT))
2294 {
2295 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_GS;
2296 pVCpu->hm.s.vmx.RestoreHost.uHostSelGS = uSelGS;
2297 uSelGS = 0;
2298 }
2299#endif
2300
2301 /* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
2302 Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
2303 Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
2304 Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
2305 Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
2306 Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
2307 Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
2308 Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
2309 Assert(uSelCS);
2310 Assert(uSelTR);
2311
2312 /* Assertion is right but we would not have updated u32ExitCtls yet. */
2313#if 0
2314 if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE))
2315 Assert(uSelSS != 0);
2316#endif
2317
2318 /* Write these host selector fields into the host-state area in the VMCS. */
2319 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_CS, uSelCS); AssertRCReturn(rc, rc);
2320 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_SS, uSelSS); AssertRCReturn(rc, rc);
2321#if HC_ARCH_BITS == 64
2322 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_DS, uSelDS); AssertRCReturn(rc, rc);
2323 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_ES, uSelES); AssertRCReturn(rc, rc);
2324 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_FS, uSelFS); AssertRCReturn(rc, rc);
2325 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_GS, uSelGS); AssertRCReturn(rc, rc);
2326#endif
2327 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_FIELD_TR, uSelTR); AssertRCReturn(rc, rc);
2328
2329 /*
2330 * Host GDTR and IDTR.
2331 */
2332 RTGDTR Gdtr;
2333 RT_ZERO(Gdtr);
2334#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2335 if (HMVMX_IS_64BIT_HOST_MODE())
2336 {
2337 X86XDTR64 Gdtr64;
2338 X86XDTR64 Idtr64;
2339 HMR0Get64bitGdtrAndIdtr(&Gdtr64, &Idtr64);
2340 rc = VMXWriteVmcs64(VMX_VMCS_HOST_GDTR_BASE, Gdtr64.uAddr); AssertRCReturn(rc, rc);
2341 rc = VMXWriteVmcs64(VMX_VMCS_HOST_IDTR_BASE, Idtr64.uAddr); AssertRCReturn(rc, rc);
2342
2343 Gdtr.cbGdt = Gdtr64.cb;
2344 Gdtr.pGdt = (uintptr_t)Gdtr64.uAddr;
2345 }
2346 else
2347#endif
2348 {
2349 RTIDTR Idtr;
2350 ASMGetGDTR(&Gdtr);
2351 ASMGetIDTR(&Idtr);
2352 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt); AssertRCReturn(rc, rc);
2353 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt); AssertRCReturn(rc, rc);
2354
2355#if HC_ARCH_BITS == 64
2356 /*
2357 * Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps them to the
2358 * maximum limit (0xffff) on every VM-exit.
2359 */
2360 if (Gdtr.cbGdt != 0xffff)
2361 {
2362 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDTR;
2363 AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
2364 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
2365 }
2366
2367 /*
2368 * IDT limit is practically 0xfff. Therefore if the host has the limit as 0xfff, VT-x bloating the limit to 0xffff
2369 * is not a problem as it's not possible to get at them anyway. See Intel spec. 6.14.1 "64-Bit Mode IDT" and
2370 * Intel spec. 6.2 "Exception and Interrupt Vectors".
2371 */
2372 if (Idtr.cbIdt < 0x0fff)
2373 {
2374 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_IDTR;
2375 AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
2376 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
2377 }
2378#endif
2379 }
2380
2381 /*
2382 * Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI and RPL bits
2383 * is effectively what the CPU does for "scaling by 8". TI is always 0 and RPL should be too in most cases.
2384 */
2385 if ((uSelTR & X86_SEL_MASK) > Gdtr.cbGdt)
2386 {
2387 AssertMsgFailed(("hmR0VmxSaveHostSegmentRegs: TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt));
2388 return VERR_VMX_INVALID_HOST_STATE;
2389 }
2390
2391 PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
2392#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2393 if (HMVMX_IS_64BIT_HOST_MODE())
2394 {
2395 /* We need the 64-bit TR base for hybrid darwin. */
2396 uint64_t u64TRBase = X86DESC64_BASE((PX86DESC64)pDesc);
2397 rc = VMXWriteVmcs64(VMX_VMCS_HOST_TR_BASE, u64TRBase);
2398 }
2399 else
2400#endif
2401 {
2402 uintptr_t uTRBase;
2403#if HC_ARCH_BITS == 64
2404 uTRBase = X86DESC64_BASE(pDesc);
2405
2406 /*
2407 * VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on all VM-exits.
2408 * The type is the same for 64-bit busy TSS[1]. The limit needs manual restoration if the host has something else.
2409 * Task switching is not supported in 64-bit mode[2], but the limit still matters as IOPM is supported in 64-bit mode.
2410 * Restoring the limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
2411 *
2412 * [1] See Intel spec. 3.5 "System Descriptor Types".
2413 * [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
2414 */
2415 Assert(pDesc->System.u4Type == 11);
2416 if ( pDesc->System.u16LimitLow != 0x67
2417 || pDesc->System.u4LimitHigh)
2418 {
2419 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_TR;
2420 pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
2421
2422 /* Store the GDTR here as we need it while restoring TR. */
2423 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
2424 }
2425#else
2426 uTRBase = X86DESC_BASE(pDesc);
2427#endif
2428 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_TR_BASE, uTRBase);
2429 }
2430 AssertRCReturn(rc, rc);
2431
2432 /*
2433 * Host FS base and GS base.
2434 */
2435#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2436 if (HMVMX_IS_64BIT_HOST_MODE())
2437 {
2438 uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
2439 uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
2440 rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase); AssertRCReturn(rc, rc);
2441 rc = VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase); AssertRCReturn(rc, rc);
2442
2443# if HC_ARCH_BITS == 64
2444 /* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
2445 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
2446 pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
2447 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
2448 pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
2449# endif
2450 }
2451#endif
2452 return rc;
2453}
2454
2455
2456/**
2457 * Saves certain host MSRs in the VM-Exit MSR-load area and some in the
2458 * host-state area of the VMCS. Theses MSRs will be automatically restored on
2459 * the host after every successful VM exit.
2460 *
2461 * @returns VBox status code.
2462 * @param pVM Pointer to the VM.
2463 * @param pVCpu Pointer to the VMCPU.
2464 */
2465DECLINLINE(int) hmR0VmxSaveHostMsrs(PVM pVM, PVMCPU pVCpu)
2466{
2467 AssertPtr(pVCpu);
2468 AssertPtr(pVCpu->hm.s.vmx.pvHostMsr);
2469
2470 int rc = VINF_SUCCESS;
2471#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2472 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
2473 uint32_t cHostMsrs = 0;
2474 uint32_t u32HostExtFeatures = pVM->hm.s.cpuid.u32AMDFeatureEDX;
2475
2476 if (u32HostExtFeatures & (X86_CPUID_EXT_FEATURE_EDX_NX | X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
2477 {
2478 uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
2479
2480# if HC_ARCH_BITS == 64
2481 /* Paranoia. 64-bit code requires these bits to be set always. */
2482 Assert((u64HostEfer & (MSR_K6_EFER_LMA | MSR_K6_EFER_LME)) == (MSR_K6_EFER_LMA | MSR_K6_EFER_LME));
2483
2484 /*
2485 * We currently do not save/restore host EFER, we just make sure it doesn't get modified by VT-x operation.
2486 * All guest accesses (read, write) on EFER cause VM-exits. If we are to conditionally load the guest EFER for
2487 * some reason (e.g. allow transparent reads) we would activate the code below.
2488 */
2489# if 0
2490 /* All our supported 64-bit host platforms must have NXE bit set. Otherwise we can change the below code to save EFER. */
2491 Assert(u64HostEfer & (MSR_K6_EFER_NXE));
2492 /* The SCE bit is only applicable in 64-bit mode. Save EFER if it doesn't match what the guest has.
2493 See Intel spec. 30.10.4.3 "Handling the SYSCALL and SYSRET Instructions". */
2494 if (CPUMIsGuestInLongMode(pVCpu))
2495 {
2496 uint64_t u64GuestEfer;
2497 rc = CPUMQueryGuestMsr(pVCpu, MSR_K6_EFER, &u64GuestEfer);
2498 AssertRC(rc);
2499
2500 if ((u64HostEfer & MSR_K6_EFER_SCE) != (u64GuestEfer & MSR_K6_EFER_SCE))
2501 {
2502 pHostMsr->u32Msr = MSR_K6_EFER;
2503 pHostMsr->u32Reserved = 0;
2504 pHostMsr->u64Value = u64HostEfer;
2505 pHostMsr++; cHostMsrs++;
2506 }
2507 }
2508# endif
2509# else /* HC_ARCH_BITS != 64 */
2510 pHostMsr->u32Msr = MSR_K6_EFER;
2511 pHostMsr->u32Reserved = 0;
2512# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2513 if (CPUMIsGuestInLongMode(pVCpu))
2514 {
2515 /* Must match the EFER value in our 64 bits switcher. */
2516 pHostMsr->u64Value = u64HostEfer | MSR_K6_EFER_LME | MSR_K6_EFER_SCE | MSR_K6_EFER_NXE;
2517 }
2518 else
2519# endif
2520 pHostMsr->u64Value = u64HostEfer;
2521 pHostMsr++; cHostMsrs++;
2522# endif /* HC_ARCH_BITS == 64 */
2523 }
2524
2525# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2526 if (HMVMX_IS_64BIT_HOST_MODE())
2527 {
2528 pHostMsr->u32Msr = MSR_K6_STAR;
2529 pHostMsr->u32Reserved = 0;
2530 pHostMsr->u64Value = ASMRdMsr(MSR_K6_STAR); /* legacy syscall eip, cs & ss */
2531 pHostMsr++; cHostMsrs++;
2532 pHostMsr->u32Msr = MSR_K8_LSTAR;
2533 pHostMsr->u32Reserved = 0;
2534 pHostMsr->u64Value = ASMRdMsr(MSR_K8_LSTAR); /* 64-bit mode syscall rip */
2535 pHostMsr++; cHostMsrs++;
2536 pHostMsr->u32Msr = MSR_K8_SF_MASK;
2537 pHostMsr->u32Reserved = 0;
2538 pHostMsr->u64Value = ASMRdMsr(MSR_K8_SF_MASK); /* syscall flag mask */
2539 pHostMsr++; cHostMsrs++;
2540 pHostMsr->u32Msr = MSR_K8_KERNEL_GS_BASE;
2541 pHostMsr->u32Reserved = 0;
2542 pHostMsr->u64Value = ASMRdMsr(MSR_K8_KERNEL_GS_BASE); /* swapgs exchange value */
2543 pHostMsr++; cHostMsrs++;
2544 }
2545# endif
2546
2547 /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
2548 if (RT_UNLIKELY(cHostMsrs > MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc)))
2549 {
2550 LogRel(("cHostMsrs=%u Cpu=%u\n", cHostMsrs, (unsigned)MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc)));
2551 pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE;
2552 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2553 }
2554
2555 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cHostMsrs);
2556#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
2557
2558 /*
2559 * Host Sysenter MSRs.
2560 */
2561 rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
2562 AssertRCReturn(rc, rc);
2563#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2564 if (HMVMX_IS_64BIT_HOST_MODE())
2565 {
2566 rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
2567 AssertRCReturn(rc, rc);
2568 rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
2569 }
2570 else
2571 {
2572 rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
2573 AssertRCReturn(rc, rc);
2574 rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
2575 }
2576#elif HC_ARCH_BITS == 32
2577 rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
2578 AssertRCReturn(rc, rc);
2579 rc = VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
2580#else
2581 rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
2582 AssertRCReturn(rc, rc);
2583 rc = VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
2584#endif
2585 AssertRCReturn(rc, rc);
2586
2587 /** @todo IA32_PERF_GLOBALCTRL, IA32_PAT, IA32_EFER, also see
2588 * hmR0VmxSetupExitCtls() !! */
2589 return rc;
2590}
2591
2592
2593/**
2594 * Sets up VM-entry controls in the VMCS. These controls can affect things done
2595 * on VM-exit; e.g. "load debug controls", see Intel spec. 24.8.1 "VM-entry
2596 * controls".
2597 *
2598 * @returns VBox status code.
2599 * @param pVCpu Pointer to the VMCPU.
2600 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2601 * out-of-sync. Make sure to update the required fields
2602 * before using them.
2603 *
2604 * @remarks No-long-jump zone!!!
2605 */
2606DECLINLINE(int) hmR0VmxLoadGuestEntryCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2607{
2608 int rc = VINF_SUCCESS;
2609 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_ENTRY_CTLS)
2610 {
2611 PVM pVM = pVCpu->CTX_SUFF(pVM);
2612 uint32_t val = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0; /* Bits set here must be set in the VMCS. */
2613 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2614
2615 /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
2616 val |= VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG;
2617
2618 /* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
2619 if (CPUMIsGuestInLongModeEx(pMixedCtx))
2620 val |= VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST;
2621 else
2622 Assert(!(val & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST));
2623
2624 /*
2625 * The following should not be set (since we're not in SMM mode):
2626 * - VMX_VMCS_CTRL_ENTRY_ENTRY_SMM
2627 * - VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON
2628 */
2629
2630 /** @todo VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR,
2631 * VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR,
2632 * VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR */
2633
2634 if ((val & zap) != val)
2635 {
2636 LogRel(("hmR0VmxLoadGuestEntryCtls: invalid VM-entry controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
2637 pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0, val, zap));
2638 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
2639 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2640 }
2641
2642 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, val);
2643 AssertRCReturn(rc, rc);
2644
2645 /* Update VCPU with the currently set VM-exit controls. */
2646 pVCpu->hm.s.vmx.u32EntryCtls = val;
2647 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_ENTRY_CTLS;
2648 }
2649 return rc;
2650}
2651
2652
2653/**
2654 * Sets up the VM-exit controls in the VMCS.
2655 *
2656 * @returns VBox status code.
2657 * @param pVM Pointer to the VM.
2658 * @param pVCpu Pointer to the VMCPU.
2659 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2660 * out-of-sync. Make sure to update the required fields
2661 * before using them.
2662 *
2663 * @remarks requires EFER.
2664 */
2665DECLINLINE(int) hmR0VmxLoadGuestExitCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2666{
2667 int rc = VINF_SUCCESS;
2668 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_EXIT_CTLS)
2669 {
2670 PVM pVM = pVCpu->CTX_SUFF(pVM);
2671 uint32_t val = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0; /* Bits set here must be set in the VMCS. */
2672 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2673
2674 /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
2675 val |= VMX_VMCS_CTRL_EXIT_SAVE_DEBUG;
2676
2677 /*
2678 * Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary.
2679 * On VM-exit, VT-x sets both the host EFER.LMA and EFER.LME bit to this value. See assertion in hmR0VmxSaveHostMsrs().
2680 */
2681#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2682 if (HMVMX_IS_64BIT_HOST_MODE())
2683 val |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
2684 else
2685 Assert(!(val & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE));
2686#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
2687 if (CPUMIsGuestInLongModeEx(pMixedCtx))
2688 val |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE; /* The switcher goes to long mode. */
2689 else
2690 Assert(!(val & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE));
2691#endif
2692
2693 /* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
2694 Assert(!(val & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT));
2695
2696 /** @todo VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR,
2697 * VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR,
2698 * VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR,
2699 * VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR,
2700 * VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR. */
2701
2702 if (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER)
2703 val |= VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER;
2704
2705 if ((val & zap) != val)
2706 {
2707 LogRel(("hmR0VmxSetupProcCtls: invalid VM-exit controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
2708 pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0, val, zap));
2709 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
2710 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2711 }
2712
2713 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, val);
2714 AssertRCReturn(rc, rc);
2715
2716 /* Update VCPU with the currently set VM-exit controls. */
2717 pVCpu->hm.s.vmx.u32ExitCtls = val;
2718 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_EXIT_CTLS;
2719 }
2720 return rc;
2721}
2722
2723
2724/**
2725 * Loads the guest APIC and related state.
2726 *
2727 * @returns VBox status code.
2728 * @param pVM Pointer to the VM.
2729 * @param pVCpu Pointer to the VMCPU.
2730 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2731 * out-of-sync. Make sure to update the required fields
2732 * before using them.
2733 */
2734DECLINLINE(int) hmR0VmxLoadGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2735{
2736 int rc = VINF_SUCCESS;
2737 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_GUEST_APIC_STATE)
2738 {
2739 /* Setup TPR shadowing. Also setup TPR patching for 32-bit guests. */
2740 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
2741 {
2742 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
2743
2744 bool fPendingIntr = false;
2745 uint8_t u8Tpr = 0;
2746 uint8_t u8PendingIntr = 0;
2747 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
2748 AssertRCReturn(rc, rc);
2749
2750 /*
2751 * If there are external interrupts pending but masked by the TPR value, instruct VT-x to cause a VM-exit when
2752 * the guest lowers its TPR below the highest-priority pending interrupt and we can deliver the interrupt.
2753 * If there are no external interrupts pending, set threshold to 0 to not cause a VM-exit. We will eventually deliver
2754 * the interrupt when we VM-exit for other reasons.
2755 */
2756 pVCpu->hm.s.vmx.pbVirtApic[0x80] = u8Tpr; /* Offset 0x80 is TPR in the APIC MMIO range. */
2757 uint32_t u32TprThreshold = 0;
2758 if (fPendingIntr)
2759 {
2760 /* Bits 3-0 of the TPR threshold field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2761 const uint8_t u8PendingPriority = (u8PendingIntr >> 4);
2762 const uint8_t u8TprPriority = (u8Tpr >> 4) & 7;
2763 if (u8PendingPriority <= u8TprPriority)
2764 u32TprThreshold = u8PendingPriority;
2765 else
2766 u32TprThreshold = u8TprPriority; /* Required for Vista 64-bit guest, see @bugref{6398}. */
2767 }
2768 Assert(!(u32TprThreshold & 0xfffffff0)); /* Bits 31:4 MBZ. */
2769
2770 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
2771 AssertRCReturn(rc, rc);
2772 }
2773
2774 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_GUEST_APIC_STATE;
2775 }
2776 return rc;
2777}
2778
2779
2780/**
2781 * Gets the guest's interruptibility-state ("interrupt shadow" as AMD calls it).
2782 *
2783 * @returns Guest's interruptibility-state.
2784 * @param pVCpu Pointer to the VMCPU.
2785 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2786 * out-of-sync. Make sure to update the required fields
2787 * before using them.
2788 *
2789 * @remarks No-long-jump zone!!!
2790 * @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2791 */
2792DECLINLINE(uint32_t) hmR0VmxGetGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2793{
2794 /*
2795 * Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2796 * inhibit interrupts or clear any existing interrupt-inhibition.
2797 */
2798 uint32_t uIntrState = 0;
2799 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2800 {
2801 /* If inhibition is active, RIP & RFLAGS should've been accessed (i.e. read previously from the VMCS or from ring-3). */
2802 AssertMsg((pVCpu->hm.s.vmx.fUpdatedGuestState & (HMVMX_UPDATED_GUEST_RIP | HMVMX_UPDATED_GUEST_RFLAGS))
2803 == (HMVMX_UPDATED_GUEST_RIP | HMVMX_UPDATED_GUEST_RFLAGS), ("%#x\n", pVCpu->hm.s.vmx.fUpdatedGuestState));
2804 if (pMixedCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2805 {
2806 /*
2807 * We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2808 * VT-x, the flag's condition to be cleared is met and thus the cleared state is correct.
2809 */
2810 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2811 }
2812 else if (pMixedCtx->eflags.Bits.u1IF)
2813 uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
2814 else
2815 uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS;
2816 }
2817 return uIntrState;
2818}
2819
2820
2821/**
2822 * Loads the guest's interruptibility-state into the guest-state area in the
2823 * VMCS.
2824 *
2825 * @returns VBox status code.
2826 * @param pVCpu Pointer to the VMCPU.
2827 * @param uIntrState The interruptibility-state to set.
2828 */
2829static int hmR0VmxLoadGuestIntrState(PVMCPU pVCpu, uint32_t uIntrState)
2830{
2831 AssertMsg(!(uIntrState & 0xfffffff0), ("%#x\n", uIntrState)); /* Bits 31:4 MBZ. */
2832 Assert((uIntrState & 0x3) != 0x3); /* Block-by-STI and MOV SS cannot be simultaneously set. */
2833 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, uIntrState);
2834 AssertRCReturn(rc, rc);
2835 return rc;
2836}
2837
2838
2839/**
2840 * Loads the guest's RIP into the guest-state area in the VMCS.
2841 *
2842 * @returns VBox status code.
2843 * @param pVCpu Pointer to the VMCPU.
2844 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2845 * out-of-sync. Make sure to update the required fields
2846 * before using them.
2847 *
2848 * @remarks No-long-jump zone!!!
2849 */
2850static int hmR0VmxLoadGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2851{
2852 int rc = VINF_SUCCESS;
2853 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RIP)
2854 {
2855 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pMixedCtx->rip);
2856 AssertRCReturn(rc, rc);
2857 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_RIP;
2858 Log4(("Load: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#x\n", pMixedCtx->rip, pVCpu->hm.s.fContextUseFlags));
2859 }
2860 return rc;
2861}
2862
2863
2864/**
2865 * Loads the guest's RSP into the guest-state area in the VMCS.
2866 *
2867 * @returns VBox status code.
2868 * @param pVCpu Pointer to the VMCPU.
2869 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2870 * out-of-sync. Make sure to update the required fields
2871 * before using them.
2872 *
2873 * @remarks No-long-jump zone!!!
2874 */
2875static int hmR0VmxLoadGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2876{
2877 int rc = VINF_SUCCESS;
2878 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RSP)
2879 {
2880 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pMixedCtx->rsp);
2881 AssertRCReturn(rc, rc);
2882 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_RSP;
2883 Log4(("Load: VMX_VMCS_GUEST_RSP=%#RX64\n", pMixedCtx->rsp));
2884 }
2885 return rc;
2886}
2887
2888
2889/**
2890 * Loads the guest's RFLAGS into the guest-state area in the VMCS.
2891 *
2892 * @returns VBox status code.
2893 * @param pVCpu Pointer to the VMCPU.
2894 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2895 * out-of-sync. Make sure to update the required fields
2896 * before using them.
2897 *
2898 * @remarks No-long-jump zone!!!
2899 */
2900static int hmR0VmxLoadGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2901{
2902 int rc = VINF_SUCCESS;
2903 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RFLAGS)
2904 {
2905 /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
2906 Let us assert it as such and use 32-bit VMWRITE. */
2907 Assert(!(pMixedCtx->rflags.u64 >> 32));
2908 X86EFLAGS Eflags = pMixedCtx->eflags;
2909 Eflags.u32 &= VMX_EFLAGS_RESERVED_0; /* Bits 22-31, 15, 5 & 3 MBZ. */
2910 Eflags.u32 |= VMX_EFLAGS_RESERVED_1; /* Bit 1 MB1. */
2911
2912 /*
2913 * If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so we can restore them on VM exit.
2914 * Modify the real-mode guest's eflags so that VT-x can run the real-mode guest code under Virtual 8086 mode.
2915 */
2916 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
2917 {
2918 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
2919 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
2920 pVCpu->hm.s.vmx.RealMode.Eflags.u32 = Eflags.u32; /* Save the original eflags of the real-mode guest. */
2921 Eflags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
2922 Eflags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
2923 }
2924
2925 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_RFLAGS, Eflags.u32);
2926 AssertRCReturn(rc, rc);
2927
2928 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_RFLAGS;
2929 Log4(("Load: VMX_VMCS_GUEST_RFLAGS=%#RX32\n", Eflags.u32));
2930 }
2931 return rc;
2932}
2933
2934
2935/**
2936 * Loads the guest RIP, RSP and RFLAGS into the guest-state area in the VMCS.
2937 *
2938 * @returns VBox status code.
2939 * @param pVCpu Pointer to the VMCPU.
2940 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2941 * out-of-sync. Make sure to update the required fields
2942 * before using them.
2943 *
2944 * @remarks No-long-jump zone!!!
2945 */
2946DECLINLINE(int) hmR0VmxLoadGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2947{
2948 int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
2949 AssertRCReturn(rc, rc);
2950 rc = hmR0VmxLoadGuestRsp(pVCpu, pMixedCtx);
2951 AssertRCReturn(rc, rc);
2952 rc = hmR0VmxLoadGuestRflags(pVCpu, pMixedCtx);
2953 AssertRCReturn(rc, rc);
2954 return rc;
2955}
2956
2957
2958/**
2959 * Loads the guest CR0 control register into the guest-state area in the VMCS.
2960 * CR0 is partially shared with the host and we have to consider the FPU bits.
2961 *
2962 * @returns VBox status code.
2963 * @param pVM Pointer to the VM.
2964 * @param pVCpu Pointer to the VMCPU.
2965 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
2966 * out-of-sync. Make sure to update the required fields
2967 * before using them.
2968 *
2969 * @remarks No-long-jump zone!!!
2970 */
2971static int hmR0VmxLoadSharedCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
2972{
2973 /*
2974 * Guest CR0.
2975 * Guest FPU.
2976 */
2977 int rc = VINF_SUCCESS;
2978 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
2979 {
2980 Assert(!(pMixedCtx->cr0 >> 32));
2981 uint32_t u32GuestCR0 = pMixedCtx->cr0;
2982 PVM pVM = pVCpu->CTX_SUFF(pVM);
2983
2984 /* The guest's view (read access) of its CR0 is unblemished. */
2985 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, u32GuestCR0);
2986 AssertRCReturn(rc, rc);
2987 Log4(("Load: VMX_VMCS_CTRL_CR0_READ_SHADOW=%#RX32\n", u32GuestCR0));
2988
2989 /* Setup VT-x's view of the guest CR0. */
2990 /* Minimize VM-exits due to CR3 changes when we have NestedPaging. */
2991 if (pVM->hm.s.fNestedPaging)
2992 {
2993 if (CPUMIsGuestPagingEnabledEx(pMixedCtx))
2994 {
2995 /* The guest has paging enabled, let it access CR3 without causing a VM exit if supported. */
2996 pVCpu->hm.s.vmx.u32ProcCtls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
2997 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
2998 }
2999 else
3000 {
3001 /* The guest doesn't have paging enabled, make CR3 access to cause VM exits to update our shadow. */
3002 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
3003 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3004 }
3005
3006 /* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
3007 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3008 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3009
3010 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
3011 AssertRCReturn(rc, rc);
3012 }
3013 else
3014 u32GuestCR0 |= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
3015
3016 /*
3017 * Guest FPU bits.
3018 * Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be set on the first
3019 * CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
3020 */
3021 u32GuestCR0 |= X86_CR0_NE;
3022 bool fInterceptNM = false;
3023 if (CPUMIsGuestFPUStateActive(pVCpu))
3024 {
3025 fInterceptNM = false; /* Guest FPU active, no need to VM-exit on #NM. */
3026 /* The guest should still get #NM exceptions when it expects it to, so we should not clear TS & MP bits here.
3027 We're only concerned about -us- not intercepting #NMs when the guest-FPU is active. Not the guest itself! */
3028 }
3029 else
3030 {
3031 fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
3032 u32GuestCR0 |= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
3033 | X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
3034 }
3035
3036 /* Catch floating point exceptions if we need to report them to the guest in a different way. */
3037 bool fInterceptMF = false;
3038 if (!(pMixedCtx->cr0 & X86_CR0_NE))
3039 fInterceptMF = true;
3040
3041 /* Finally, intercept all exceptions as we cannot directly inject them in real-mode, see hmR0VmxInjectEventVmcs(). */
3042 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3043 {
3044 Assert(PDMVmmDevHeapIsEnabled(pVM));
3045 Assert(pVM->hm.s.vmx.pRealModeTSS);
3046 pVCpu->hm.s.vmx.u32XcptBitmap |= HMVMX_REAL_MODE_XCPT_MASK;
3047 fInterceptNM = true;
3048 fInterceptMF = true;
3049 }
3050 else
3051 pVCpu->hm.s.vmx.u32XcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
3052
3053 if (fInterceptNM)
3054 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_NM);
3055 else
3056 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_NM);
3057
3058 if (fInterceptMF)
3059 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_MF);
3060 else
3061 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_MF);
3062
3063 /* Additional intercepts for debugging, define these yourself explicitly. */
3064#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3065 pVCpu->hm.s.vmx.u32XcptBitmap |= 0
3066 | RT_BIT(X86_XCPT_BP)
3067 | RT_BIT(X86_XCPT_DB)
3068 | RT_BIT(X86_XCPT_DE)
3069 | RT_BIT(X86_XCPT_NM)
3070 | RT_BIT(X86_XCPT_UD)
3071 | RT_BIT(X86_XCPT_NP)
3072 | RT_BIT(X86_XCPT_SS)
3073 | RT_BIT(X86_XCPT_GP)
3074 | RT_BIT(X86_XCPT_PF)
3075 | RT_BIT(X86_XCPT_MF)
3076 ;
3077#elif defined(HMVMX_ALWAYS_TRAP_PF)
3078 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_PF);
3079#endif
3080
3081 Assert(pVM->hm.s.fNestedPaging || (pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT(X86_XCPT_PF)));
3082
3083 /* Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW). */
3084 uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3085 uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3086 if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */
3087 uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG);
3088 else
3089 Assert((uSetCR0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG));
3090
3091 u32GuestCR0 |= uSetCR0;
3092 u32GuestCR0 &= uZapCR0;
3093 u32GuestCR0 &= ~(X86_CR0_CD | X86_CR0_NW); /* Always enable caching. */
3094
3095 /* Write VT-x's view of the guest CR0 into the VMCS and update the exception bitmap. */
3096 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCR0);
3097 AssertRCReturn(rc, rc);
3098 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
3099 AssertRCReturn(rc, rc);
3100 Log4(("Load: VMX_VMCS_GUEST_CR0=%#RX32 (uSetCR0=%#RX32 uZapCR0=%#RX32)\n", u32GuestCR0, uSetCR0, uZapCR0));
3101
3102 /*
3103 * CR0 is shared between host and guest along with a CR0 read shadow. Therefore, certain bits must not be changed
3104 * by the guest because VT-x ignores saving/restoring them (namely CD, ET, NW) and for certain other bits
3105 * we want to be notified immediately of guest CR0 changes (e.g. PG to update our shadow page tables).
3106 */
3107 uint32_t u32CR0Mask = 0;
3108 u32CR0Mask = X86_CR0_PE
3109 | X86_CR0_NE
3110 | X86_CR0_WP
3111 | X86_CR0_PG
3112 | X86_CR0_ET /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
3113 | X86_CR0_CD /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
3114 | X86_CR0_NW; /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.NW */
3115 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3116 u32CR0Mask &= ~X86_CR0_PE;
3117 if (pVM->hm.s.fNestedPaging)
3118 u32CR0Mask &= ~X86_CR0_WP;
3119
3120 /* If the guest FPU state is active, don't need to VM-exit on writes to FPU related bits in CR0. */
3121 if (fInterceptNM)
3122 u32CR0Mask |= (X86_CR0_TS | X86_CR0_MP);
3123 else
3124 u32CR0Mask &= ~(X86_CR0_TS | X86_CR0_MP);
3125
3126 /* Write the CR0 mask into the VMCS and update the VCPU's copy of the current CR0 mask. */
3127 pVCpu->hm.s.vmx.u32CR0Mask = u32CR0Mask;
3128 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32CR0Mask);
3129 AssertRCReturn(rc, rc);
3130
3131 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR0;
3132 }
3133 return rc;
3134}
3135
3136
3137/**
3138 * Loads the guest control registers (CR3, CR4) into the guest-state area
3139 * in the VMCS.
3140 *
3141 * @returns VBox status code.
3142 * @param pVM Pointer to the VM.
3143 * @param pVCpu Pointer to the VMCPU.
3144 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3145 * out-of-sync. Make sure to update the required fields
3146 * before using them.
3147 *
3148 * @remarks No-long-jump zone!!!
3149 */
3150static int hmR0VmxLoadGuestCR3AndCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3151{
3152 int rc = VINF_SUCCESS;
3153 PVM pVM = pVCpu->CTX_SUFF(pVM);
3154
3155 /*
3156 * Guest CR2.
3157 * It's always loaded in the assembler code. Nothing to do here.
3158 */
3159
3160 /*
3161 * Guest CR3.
3162 */
3163 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
3164 {
3165 RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
3166 if (pVM->hm.s.fNestedPaging)
3167 {
3168 pVCpu->hm.s.vmx.HCPhysEPTP = PGMGetHyperCR3(pVCpu);
3169
3170 /* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
3171 Assert(pVCpu->hm.s.vmx.HCPhysEPTP);
3172 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & UINT64_C(0xfff0000000000000)));
3173 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & 0xfff));
3174
3175 /* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
3176 pVCpu->hm.s.vmx.HCPhysEPTP |= VMX_EPT_MEMTYPE_WB
3177 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
3178
3179 /* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
3180 AssertMsg( ((pVCpu->hm.s.vmx.HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
3181 && ((pVCpu->hm.s.vmx.HCPhysEPTP >> 6) & 0x3f) == 0, /* Bits 6:11 MBZ. */
3182 ("EPTP %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3183
3184 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.HCPhysEPTP);
3185 AssertRCReturn(rc, rc);
3186 Log4(("Load: VMX_VMCS64_CTRL_EPTP_FULL=%#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3187
3188 if ( pVM->hm.s.vmx.fUnrestrictedGuest
3189 || CPUMIsGuestPagingEnabledEx(pMixedCtx))
3190 {
3191 /* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
3192 if (CPUMIsGuestInPAEModeEx(pMixedCtx))
3193 {
3194 rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]); AssertRCReturn(rc, rc);
3195 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u); AssertRCReturn(rc, rc);
3196 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u); AssertRCReturn(rc, rc);
3197 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u); AssertRCReturn(rc, rc);
3198 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u); AssertRCReturn(rc, rc);
3199 }
3200
3201 /* The guest's view of its CR3 is unblemished with Nested Paging when the guest is using paging or we
3202 have Unrestricted Execution to handle the guest when it's not using paging. */
3203 GCPhysGuestCR3 = pMixedCtx->cr3;
3204 }
3205 else
3206 {
3207 /*
3208 * The guest is not using paging, but the CPU (VT-x) has to. While the guest thinks it accesses physical memory
3209 * directly, we use our identity-mapped page table to map guest-linear to guest-physical addresses.
3210 * EPT takes care of translating it to host-physical addresses.
3211 */
3212 RTGCPHYS GCPhys;
3213 Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
3214 Assert(PDMVmmDevHeapIsEnabled(pVM));
3215
3216 /* We obtain it here every time as the guest could have relocated this PCI region. */
3217 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
3218 AssertRCReturn(rc, rc);
3219
3220 GCPhysGuestCR3 = GCPhys;
3221 }
3222
3223 Log4(("Load: VMX_VMCS_GUEST_CR3=%#RGv (GstN)\n", GCPhysGuestCR3));
3224 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR3, GCPhysGuestCR3);
3225 }
3226 else
3227 {
3228 /* Non-nested paging case, just use the hypervisor's CR3. */
3229 RTHCPHYS HCPhysGuestCR3 = PGMGetHyperCR3(pVCpu);
3230
3231 Log4(("Load: VMX_VMCS_GUEST_CR3=%#RHv (HstN)\n", HCPhysGuestCR3));
3232 rc = VMXWriteVmcsHstN(VMX_VMCS_GUEST_CR3, HCPhysGuestCR3);
3233 }
3234 AssertRCReturn(rc, rc);
3235
3236 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR3;
3237 }
3238
3239 /*
3240 * Guest CR4.
3241 */
3242 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
3243 {
3244 Assert(!(pMixedCtx->cr4 >> 32));
3245 uint32_t u32GuestCR4 = pMixedCtx->cr4;
3246
3247 /* The guest's view of its CR4 is unblemished. */
3248 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32GuestCR4);
3249 AssertRCReturn(rc, rc);
3250 Log4(("Load: VMX_VMCS_CTRL_CR4_READ_SHADOW=%#RX32\n", u32GuestCR4));
3251
3252 /* Setup VT-x's view of the guest CR4. */
3253 /*
3254 * If we're emulating real-mode using virtual-8086 mode, we want to redirect software interrupts to the 8086 program
3255 * interrupt handler. Clear the VME bit (the interrupt redirection bitmap is already all 0, see hmR3InitFinalizeR0())
3256 * See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
3257 */
3258 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3259 {
3260 Assert(pVM->hm.s.vmx.pRealModeTSS);
3261 Assert(PDMVmmDevHeapIsEnabled(pVM));
3262 u32GuestCR4 &= ~X86_CR4_VME;
3263 }
3264
3265 if (pVM->hm.s.fNestedPaging)
3266 {
3267 if ( !CPUMIsGuestPagingEnabledEx(pMixedCtx)
3268 && !pVM->hm.s.vmx.fUnrestrictedGuest)
3269 {
3270 /* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
3271 u32GuestCR4 |= X86_CR4_PSE;
3272 /* Our identity mapping is a 32 bits page directory. */
3273 u32GuestCR4 &= ~X86_CR4_PAE;
3274 }
3275 /* else use guest CR4.*/
3276 }
3277 else
3278 {
3279 /*
3280 * The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
3281 * paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
3282 */
3283 switch (pVCpu->hm.s.enmShadowMode)
3284 {
3285 case PGMMODE_REAL: /* Real-mode. */
3286 case PGMMODE_PROTECTED: /* Protected mode without paging. */
3287 case PGMMODE_32_BIT: /* 32-bit paging. */
3288 {
3289 u32GuestCR4 &= ~X86_CR4_PAE;
3290 break;
3291 }
3292
3293 case PGMMODE_PAE: /* PAE paging. */
3294 case PGMMODE_PAE_NX: /* PAE paging with NX. */
3295 {
3296 u32GuestCR4 |= X86_CR4_PAE;
3297 break;
3298 }
3299
3300 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
3301 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
3302#ifdef VBOX_ENABLE_64_BITS_GUESTS
3303 break;
3304#endif
3305 default:
3306 AssertFailed();
3307 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
3308 }
3309 }
3310
3311 /* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */
3312 uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
3313 uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
3314 u32GuestCR4 |= uSetCR4;
3315 u32GuestCR4 &= uZapCR4;
3316
3317 /* Write VT-x's view of the guest CR4 into the VMCS. */
3318 Log4(("Load: VMX_VMCS_GUEST_CR4=%#RX32 (Set=%#RX32 Zap=%#RX32)\n", u32GuestCR4, uSetCR4, uZapCR4));
3319 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCR4);
3320 AssertRCReturn(rc, rc);
3321
3322 /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them, that would cause a VM exit. */
3323 uint32_t u32CR4Mask = 0;
3324 u32CR4Mask = X86_CR4_VME
3325 | X86_CR4_PAE
3326 | X86_CR4_PGE
3327 | X86_CR4_PSE
3328 | X86_CR4_VMXE;
3329 pVCpu->hm.s.vmx.u32CR4Mask = u32CR4Mask;
3330 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
3331 AssertRCReturn(rc, rc);
3332
3333 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR4;
3334 }
3335 return rc;
3336}
3337
3338
3339/**
3340 * Loads the guest debug registers into the guest-state area in the VMCS.
3341 * This also sets up whether #DB and MOV DRx accesses cause VM exits.
3342 *
3343 * The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
3344 *
3345 * @returns VBox status code.
3346 * @param pVCpu Pointer to the VMCPU.
3347 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3348 * out-of-sync. Make sure to update the required fields
3349 * before using them.
3350 *
3351 * @remarks No-long-jump zone!!!
3352 */
3353static int hmR0VmxLoadSharedDebugState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3354{
3355 if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG))
3356 return VINF_SUCCESS;
3357
3358#ifdef VBOX_STRICT
3359 /* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
3360 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
3361 {
3362 /* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
3363 Assert((pMixedCtx->dr[7] & (X86_DR7_MBZ_MASK | X86_DR7_RAZ_MASK)) == 0); /* Bits 63:32, 15, 14, 12, 11 are reserved. */
3364 Assert((pMixedCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); /* Bit 10 is reserved (RA1). */
3365 }
3366#endif
3367
3368 int rc;
3369 PVM pVM = pVCpu->CTX_SUFF(pVM);
3370 bool fInterceptDB = false;
3371 bool fInterceptMovDRx = false;
3372 if (pVCpu->hm.s.fSingleInstruction || DBGFIsStepping(pVCpu))
3373 {
3374 /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
3375 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG)
3376 {
3377 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
3378 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
3379 AssertRCReturn(rc, rc);
3380 Assert(fInterceptDB == false);
3381 }
3382 else
3383 {
3384 pMixedCtx->eflags.u32 |= X86_EFL_TF;
3385 pVCpu->hm.s.fClearTrapFlag = true;
3386 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RFLAGS;
3387 fInterceptDB = true;
3388 }
3389 }
3390
3391 if (fInterceptDB || (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
3392 {
3393 /*
3394 * Use the combined guest and host DRx values found in the hypervisor
3395 * register set because the debugger has breakpoints active or someone
3396 * is single stepping on the host side without a monitor trap flag.
3397 *
3398 * Note! DBGF expects a clean DR6 state before executing guest code.
3399 */
3400 if (!CPUMIsHyperDebugStateActive(pVCpu))
3401 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
3402 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
3403 Assert(CPUMIsHyperDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
3404
3405 /* Update DR7. (The other DRx values are handled by CPUM one way or the other.) */
3406 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)CPUMGetHyperDR7(pVCpu));
3407 AssertRCReturn(rc, rc);
3408
3409 fInterceptDB = true;
3410 fInterceptMovDRx = true;
3411 }
3412 else
3413 {
3414 /*
3415 * If the guest has enabled debug registers, we need to load them prior to
3416 * executing guest code so they'll trigger at the right time.
3417 */
3418 if (pMixedCtx->dr[7] & (X86_DR7_ENABLED_MASK | X86_DR7_GD)) /** @todo Why GD? */
3419 {
3420 if (!CPUMIsGuestDebugStateActive(pVCpu))
3421 {
3422 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
3423 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
3424 }
3425 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
3426 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
3427 }
3428 /*
3429 * If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
3430 * must intercept #DB in order to maintain a correct DR6 guest value.
3431 */
3432 else if (!CPUMIsGuestDebugStateActive(pVCpu))
3433 {
3434 fInterceptMovDRx = true;
3435 fInterceptDB = true;
3436 }
3437
3438 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
3439 AssertRCReturn(rc, rc);
3440 }
3441
3442 /*
3443 * Update the exception bitmap regarding intercepting #DB generated by the guest.
3444 */
3445 if (fInterceptDB)
3446 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_DB);
3447 else if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3448 {
3449#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3450 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_DB);
3451#endif
3452 }
3453 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
3454 AssertRCReturn(rc, rc);
3455
3456 /*
3457 * Update the processor-based VM-execution controls regarding intercepting MOV DRx instructions.
3458 */
3459 if (fInterceptMovDRx)
3460 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
3461 else
3462 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
3463 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
3464 AssertRCReturn(rc, rc);
3465
3466 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_DEBUG;
3467 return VINF_SUCCESS;
3468}
3469
3470
3471#ifdef VBOX_STRICT
3472/**
3473 * Strict function to validate segment registers.
3474 *
3475 * @remarks ASSUMES CR0 is up to date.
3476 */
3477static void hmR0VmxValidateSegmentRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3478{
3479 /* Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */
3480 /* NOTE: The reason we check for attribute value 0 and not just the unusable bit here is because hmR0VmxWriteSegmentReg()
3481 * only updates the VMCS' copy of the value with the unusable bit and doesn't change the guest-context value. */
3482 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
3483 && ( !CPUMIsGuestInRealModeEx(pCtx)
3484 && !CPUMIsGuestInV86ModeEx(pCtx)))
3485 {
3486 /* Protected mode checks */
3487 /* CS */
3488 Assert(pCtx->cs.Attr.n.u1Present);
3489 Assert(!(pCtx->cs.Attr.u & 0xf00));
3490 Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
3491 Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
3492 || !(pCtx->cs.Attr.n.u1Granularity));
3493 Assert( !(pCtx->cs.u32Limit & 0xfff00000)
3494 || (pCtx->cs.Attr.n.u1Granularity));
3495 /* CS cannot be loaded with NULL in protected mode. */
3496 Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS?!? */
3497 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
3498 Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
3499 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
3500 Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
3501 else
3502 AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
3503 /* SS */
3504 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
3505 Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
3506 if ( !(pCtx->cr0 & X86_CR0_PE)
3507 || pCtx->cs.Attr.n.u4Type == 3)
3508 {
3509 Assert(!pCtx->ss.Attr.n.u2Dpl);
3510 }
3511 if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
3512 {
3513 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
3514 Assert(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7);
3515 Assert(pCtx->ss.Attr.n.u1Present);
3516 Assert(!(pCtx->ss.Attr.u & 0xf00));
3517 Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
3518 Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
3519 || !(pCtx->ss.Attr.n.u1Granularity));
3520 Assert( !(pCtx->ss.u32Limit & 0xfff00000)
3521 || (pCtx->ss.Attr.n.u1Granularity));
3522 }
3523 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
3524 if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
3525 {
3526 Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
3527 Assert(pCtx->ds.Attr.n.u1Present);
3528 Assert(pCtx->ds.Attr.n.u4Type > 11 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
3529 Assert(!(pCtx->ds.Attr.u & 0xf00));
3530 Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
3531 Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
3532 || !(pCtx->ds.Attr.n.u1Granularity));
3533 Assert( !(pCtx->ds.u32Limit & 0xfff00000)
3534 || (pCtx->ds.Attr.n.u1Granularity));
3535 Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
3536 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
3537 }
3538 if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
3539 {
3540 Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
3541 Assert(pCtx->es.Attr.n.u1Present);
3542 Assert(pCtx->es.Attr.n.u4Type > 11 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
3543 Assert(!(pCtx->es.Attr.u & 0xf00));
3544 Assert(!(pCtx->es.Attr.u & 0xfffe0000));
3545 Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
3546 || !(pCtx->es.Attr.n.u1Granularity));
3547 Assert( !(pCtx->es.u32Limit & 0xfff00000)
3548 || (pCtx->es.Attr.n.u1Granularity));
3549 Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
3550 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
3551 }
3552 if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
3553 {
3554 Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
3555 Assert(pCtx->fs.Attr.n.u1Present);
3556 Assert(pCtx->fs.Attr.n.u4Type > 11 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
3557 Assert(!(pCtx->fs.Attr.u & 0xf00));
3558 Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
3559 Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
3560 || !(pCtx->fs.Attr.n.u1Granularity));
3561 Assert( !(pCtx->fs.u32Limit & 0xfff00000)
3562 || (pCtx->fs.Attr.n.u1Granularity));
3563 Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
3564 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
3565 }
3566 if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
3567 {
3568 Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
3569 Assert(pCtx->gs.Attr.n.u1Present);
3570 Assert(pCtx->gs.Attr.n.u4Type > 11 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
3571 Assert(!(pCtx->gs.Attr.u & 0xf00));
3572 Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
3573 Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
3574 || !(pCtx->gs.Attr.n.u1Granularity));
3575 Assert( !(pCtx->gs.u32Limit & 0xfff00000)
3576 || (pCtx->gs.Attr.n.u1Granularity));
3577 Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
3578 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
3579 }
3580 /* 64-bit capable CPUs. */
3581# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3582 Assert(!(pCtx->cs.u64Base >> 32));
3583 Assert(!pCtx->ss.Attr.u || !(pCtx->ss.u64Base >> 32));
3584 Assert(!pCtx->ds.Attr.u || !(pCtx->ds.u64Base >> 32));
3585 Assert(!pCtx->es.Attr.u || !(pCtx->es.u64Base >> 32));
3586# endif
3587 }
3588 else if ( CPUMIsGuestInV86ModeEx(pCtx)
3589 || ( CPUMIsGuestInRealModeEx(pCtx)
3590 && !pVM->hm.s.vmx.fUnrestrictedGuest))
3591 {
3592 /* Real and v86 mode checks. */
3593 /* hmR0VmxWriteSegmentReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
3594 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
3595 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3596 {
3597 u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3; u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
3598 }
3599 else
3600 {
3601 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
3602 u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
3603 }
3604
3605 /* CS */
3606 AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
3607 Assert(pCtx->cs.u32Limit == 0xffff);
3608 Assert(u32CSAttr == 0xf3);
3609 /* SS */
3610 Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
3611 Assert(pCtx->ss.u32Limit == 0xffff);
3612 Assert(u32SSAttr == 0xf3);
3613 /* DS */
3614 Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
3615 Assert(pCtx->ds.u32Limit == 0xffff);
3616 Assert(u32DSAttr == 0xf3);
3617 /* ES */
3618 Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
3619 Assert(pCtx->es.u32Limit == 0xffff);
3620 Assert(u32ESAttr == 0xf3);
3621 /* FS */
3622 Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
3623 Assert(pCtx->fs.u32Limit == 0xffff);
3624 Assert(u32FSAttr == 0xf3);
3625 /* GS */
3626 Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
3627 Assert(pCtx->gs.u32Limit == 0xffff);
3628 Assert(u32GSAttr == 0xf3);
3629 /* 64-bit capable CPUs. */
3630# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3631 Assert(!(pCtx->cs.u64Base >> 32));
3632 Assert(!u32SSAttr || !(pCtx->ss.u64Base >> 32));
3633 Assert(!u32DSAttr || !(pCtx->ds.u64Base >> 32));
3634 Assert(!u32ESAttr || !(pCtx->es.u64Base >> 32));
3635# endif
3636 }
3637}
3638#endif /* VBOX_STRICT */
3639
3640
3641/**
3642 * Writes a guest segment register into the guest-state area in the VMCS.
3643 *
3644 * @returns VBox status code.
3645 * @param pVCpu Pointer to the VMCPU.
3646 * @param idxSel Index of the selector in the VMCS.
3647 * @param idxLimit Index of the segment limit in the VMCS.
3648 * @param idxBase Index of the segment base in the VMCS.
3649 * @param idxAccess Index of the access rights of the segment in the VMCS.
3650 * @param pSelReg Pointer to the segment selector.
3651 * @param pCtx Pointer to the guest-CPU context.
3652 *
3653 * @remarks No-long-jump zone!!!
3654 */
3655static int hmR0VmxWriteSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase,
3656 uint32_t idxAccess, PCPUMSELREG pSelReg, PCPUMCTX pCtx)
3657{
3658 int rc = VMXWriteVmcs32(idxSel, pSelReg->Sel); /* 16-bit guest selector field. */
3659 AssertRCReturn(rc, rc);
3660 rc = VMXWriteVmcs32(idxLimit, pSelReg->u32Limit); /* 32-bit guest segment limit field. */
3661 AssertRCReturn(rc, rc);
3662 rc = VMXWriteVmcsGstN(idxBase, pSelReg->u64Base); /* Natural width guest segment base field.*/
3663 AssertRCReturn(rc, rc);
3664
3665 uint32_t u32Access = pSelReg->Attr.u;
3666 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3667 {
3668 /* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
3669 u32Access = 0xf3;
3670 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
3671 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
3672 }
3673 else
3674 {
3675 /*
3676 * The way to differentiate between whether this is really a null selector or was just a selector loaded with 0 in
3677 * real-mode is using the segment attributes. A selector loaded in real-mode with the value 0 is valid and usable in
3678 * protected-mode and we should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures NULL selectors
3679 * loaded in protected-mode have their attribute as 0.
3680 */
3681 if (!u32Access)
3682 u32Access = X86DESCATTR_UNUSABLE;
3683 }
3684
3685 /* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
3686 AssertMsg((u32Access & X86DESCATTR_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
3687 ("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
3688
3689 rc = VMXWriteVmcs32(idxAccess, u32Access); /* 32-bit guest segment access-rights field. */
3690 AssertRCReturn(rc, rc);
3691 return rc;
3692}
3693
3694
3695/**
3696 * Loads the guest segment registers, GDTR, IDTR, LDTR, (TR, FS and GS bases)
3697 * into the guest-state area in the VMCS.
3698 *
3699 * @returns VBox status code.
3700 * @param pVM Pointer to the VM.
3701 * @param pVCPU Pointer to the VMCPU.
3702 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3703 * out-of-sync. Make sure to update the required fields
3704 * before using them.
3705 *
3706 * @remarks ASSUMES CR0 is up to date (strict builds validation).
3707 * @remarks No-long-jump zone!!!
3708 */
3709static int hmR0VmxLoadGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3710{
3711 int rc = VERR_INTERNAL_ERROR_5;
3712 PVM pVM = pVCpu->CTX_SUFF(pVM);
3713
3714 /*
3715 * Guest Segment registers: CS, SS, DS, ES, FS, GS.
3716 */
3717 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
3718 {
3719 /* Save the segment attributes for real-on-v86 mode hack, so we can restore them on VM-exit. */
3720 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3721 {
3722 pVCpu->hm.s.vmx.RealMode.AttrCS.u = pMixedCtx->cs.Attr.u;
3723 pVCpu->hm.s.vmx.RealMode.AttrSS.u = pMixedCtx->ss.Attr.u;
3724 pVCpu->hm.s.vmx.RealMode.AttrDS.u = pMixedCtx->ds.Attr.u;
3725 pVCpu->hm.s.vmx.RealMode.AttrES.u = pMixedCtx->es.Attr.u;
3726 pVCpu->hm.s.vmx.RealMode.AttrFS.u = pMixedCtx->fs.Attr.u;
3727 pVCpu->hm.s.vmx.RealMode.AttrGS.u = pMixedCtx->gs.Attr.u;
3728 }
3729
3730#ifdef VBOX_WITH_REM
3731 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
3732 {
3733 Assert(pVM->hm.s.vmx.pRealModeTSS);
3734 AssertCompile(PGMMODE_REAL < PGMMODE_PROTECTED);
3735 if ( pVCpu->hm.s.vmx.fWasInRealMode
3736 && PGMGetGuestMode(pVCpu) >= PGMMODE_PROTECTED)
3737 {
3738 /* Signal that the recompiler must flush its code-cache as the guest -may- rewrite code it will later execute
3739 in real-mode (e.g. OpenBSD 4.0) */
3740 REMFlushTBs(pVM);
3741 Log4(("Load: Switch to protected mode detected!\n"));
3742 pVCpu->hm.s.vmx.fWasInRealMode = false;
3743 }
3744 }
3745#endif
3746 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_CS, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
3747 VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS, &pMixedCtx->cs, pMixedCtx);
3748 AssertRCReturn(rc, rc);
3749 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_SS, VMX_VMCS32_GUEST_SS_LIMIT, VMX_VMCS_GUEST_SS_BASE,
3750 VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS, &pMixedCtx->ss, pMixedCtx);
3751 AssertRCReturn(rc, rc);
3752 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_DS, VMX_VMCS32_GUEST_DS_LIMIT, VMX_VMCS_GUEST_DS_BASE,
3753 VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS, &pMixedCtx->ds, pMixedCtx);
3754 AssertRCReturn(rc, rc);
3755 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_ES, VMX_VMCS32_GUEST_ES_LIMIT, VMX_VMCS_GUEST_ES_BASE,
3756 VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, &pMixedCtx->es, pMixedCtx);
3757 AssertRCReturn(rc, rc);
3758 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_FS, VMX_VMCS32_GUEST_FS_LIMIT, VMX_VMCS_GUEST_FS_BASE,
3759 VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS, &pMixedCtx->fs, pMixedCtx);
3760 AssertRCReturn(rc, rc);
3761 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_GS, VMX_VMCS32_GUEST_GS_LIMIT, VMX_VMCS_GUEST_GS_BASE,
3762 VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS, &pMixedCtx->gs, pMixedCtx);
3763 AssertRCReturn(rc, rc);
3764
3765 Log4(("Load: CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pMixedCtx->cs.Sel, pMixedCtx->cs.u64Base,
3766 pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
3767#ifdef VBOX_STRICT
3768 hmR0VmxValidateSegmentRegs(pVM, pVCpu, pMixedCtx);
3769#endif
3770 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SEGMENT_REGS;
3771 }
3772
3773 /*
3774 * Guest TR.
3775 */
3776 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
3777 {
3778 /*
3779 * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is achieved
3780 * using the interrupt redirection bitmap (all bits cleared to let the guest handle INT-n's) in the TSS.
3781 * See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
3782 */
3783 uint16_t u16Sel = 0;
3784 uint32_t u32Limit = 0;
3785 uint64_t u64Base = 0;
3786 uint32_t u32AccessRights = 0;
3787
3788 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3789 {
3790 u16Sel = pMixedCtx->tr.Sel;
3791 u32Limit = pMixedCtx->tr.u32Limit;
3792 u64Base = pMixedCtx->tr.u64Base;
3793 u32AccessRights = pMixedCtx->tr.Attr.u;
3794 }
3795 else
3796 {
3797 Assert(pVM->hm.s.vmx.pRealModeTSS);
3798 Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMR3CanExecuteGuest() -XXX- what about inner loop changes? */
3799
3800 /* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
3801 RTGCPHYS GCPhys;
3802 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
3803 AssertRCReturn(rc, rc);
3804
3805 X86DESCATTR DescAttr;
3806 DescAttr.u = 0;
3807 DescAttr.n.u1Present = 1;
3808 DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
3809
3810 u16Sel = 0;
3811 u32Limit = HM_VTX_TSS_SIZE;
3812 u64Base = GCPhys; /* in real-mode phys = virt. */
3813 u32AccessRights = DescAttr.u;
3814 }
3815
3816 /* Validate. */
3817 Assert(!(u16Sel & RT_BIT(2)));
3818 AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
3819 || (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
3820 AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
3821 Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
3822 Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
3823 Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
3824 Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
3825 Assert( (u32Limit & 0xfff) == 0xfff
3826 || !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
3827 Assert( !(pMixedCtx->tr.u32Limit & 0xfff00000)
3828 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
3829
3830 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_TR, u16Sel); AssertRCReturn(rc, rc);
3831 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit); AssertRCReturn(rc, rc);
3832 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE, u64Base); AssertRCReturn(rc, rc);
3833 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights); AssertRCReturn(rc, rc);
3834
3835 Log4(("Load: VMX_VMCS_GUEST_TR_BASE=%#RX64\n", u64Base));
3836 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_TR;
3837 }
3838
3839 /*
3840 * Guest GDTR.
3841 */
3842 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
3843 {
3844 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt); AssertRCReturn(rc, rc);
3845 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pMixedCtx->gdtr.pGdt); AssertRCReturn(rc, rc);
3846
3847 Assert(!(pMixedCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
3848 Log4(("Load: VMX_VMCS_GUEST_GDTR_BASE=%#RX64\n", pMixedCtx->gdtr.pGdt));
3849 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_GDTR;
3850 }
3851
3852 /*
3853 * Guest LDTR.
3854 */
3855 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
3856 {
3857 /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
3858 uint32_t u32Access = 0;
3859 if (!pMixedCtx->ldtr.Attr.u)
3860 u32Access = X86DESCATTR_UNUSABLE;
3861 else
3862 u32Access = pMixedCtx->ldtr.Attr.u;
3863
3864 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_FIELD_LDTR, pMixedCtx->ldtr.Sel); AssertRCReturn(rc, rc);
3865 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pMixedCtx->ldtr.u32Limit); AssertRCReturn(rc, rc);
3866 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE, pMixedCtx->ldtr.u64Base); AssertRCReturn(rc, rc);
3867 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access); AssertRCReturn(rc, rc);
3868
3869 /* Validate. */
3870 if (!(u32Access & X86DESCATTR_UNUSABLE))
3871 {
3872 Assert(!(pMixedCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
3873 Assert(pMixedCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
3874 Assert(!pMixedCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
3875 Assert(pMixedCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
3876 Assert(!pMixedCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
3877 Assert(!(pMixedCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
3878 Assert( (pMixedCtx->ldtr.u32Limit & 0xfff) == 0xfff
3879 || !pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
3880 Assert( !(pMixedCtx->ldtr.u32Limit & 0xfff00000)
3881 || pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
3882 }
3883
3884 Log4(("Load: VMX_VMCS_GUEST_LDTR_BASE=%#RX64\n", pMixedCtx->ldtr.u64Base));
3885 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_LDTR;
3886 }
3887
3888 /*
3889 * Guest IDTR.
3890 */
3891 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
3892 {
3893 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt); AssertRCReturn(rc, rc);
3894 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, pMixedCtx->idtr.pIdt); AssertRCReturn(rc, rc);
3895
3896 Assert(!(pMixedCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
3897 Log4(("Load: VMX_VMCS_GUEST_IDTR_BASE=%#RX64\n", pMixedCtx->idtr.pIdt));
3898 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_IDTR;
3899 }
3900
3901 return VINF_SUCCESS;
3902}
3903
3904
3905/**
3906 * Loads certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
3907 * areas. These MSRs will automatically be loaded to the host CPU on every
3908 * successful VM entry and stored from the host CPU on every successful VM exit.
3909 * Also loads the sysenter MSRs into the guest-state area in the VMCS.
3910 *
3911 * @returns VBox status code.
3912 * @param pVCpu Pointer to the VMCPU.
3913 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3914 * out-of-sync. Make sure to update the required fields
3915 * before using them.
3916 *
3917 * @remarks No-long-jump zone!!!
3918 */
3919static int hmR0VmxLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3920{
3921 AssertPtr(pVCpu);
3922 AssertPtr(pVCpu->hm.s.vmx.pvGuestMsr);
3923
3924 /*
3925 * MSRs covered by Auto-load/store: EFER, LSTAR, STAR, SF_MASK, TSC_AUX (RDTSCP).
3926 */
3927 int rc = VINF_SUCCESS;
3928 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_GUEST_AUTO_MSRS)
3929 {
3930#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
3931 PVM pVM = pVCpu->CTX_SUFF(pVM);
3932 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
3933 uint32_t cGuestMsrs = 0;
3934
3935 /* See Intel spec. 4.1.4 "Enumeration of Paging Features by CPUID". */
3936 /** @todo r=ramshankar: Optimize this further to do lazy restoration and only
3937 * when the guest really is in 64-bit mode. */
3938 bool fSupportsLongMode = CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3939 if (fSupportsLongMode)
3940 {
3941 pGuestMsr->u32Msr = MSR_K8_LSTAR;
3942 pGuestMsr->u32Reserved = 0;
3943 pGuestMsr->u64Value = pMixedCtx->msrLSTAR; /* 64 bits mode syscall rip */
3944 pGuestMsr++; cGuestMsrs++;
3945 pGuestMsr->u32Msr = MSR_K6_STAR;
3946 pGuestMsr->u32Reserved = 0;
3947 pGuestMsr->u64Value = pMixedCtx->msrSTAR; /* legacy syscall eip, cs & ss */
3948 pGuestMsr++; cGuestMsrs++;
3949 pGuestMsr->u32Msr = MSR_K8_SF_MASK;
3950 pGuestMsr->u32Reserved = 0;
3951 pGuestMsr->u64Value = pMixedCtx->msrSFMASK; /* syscall flag mask */
3952 pGuestMsr++; cGuestMsrs++;
3953 pGuestMsr->u32Msr = MSR_K8_KERNEL_GS_BASE;
3954 pGuestMsr->u32Reserved = 0;
3955 pGuestMsr->u64Value = pMixedCtx->msrKERNELGSBASE; /* swapgs exchange value */
3956 pGuestMsr++; cGuestMsrs++;
3957 }
3958
3959 /*
3960 * RDTSCP requires the TSC_AUX MSR. Host and guest share the physical MSR. So we have to
3961 * load the guest's copy if the guest can execute RDTSCP without causing VM-exits.
3962 */
3963 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP)
3964 && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP))
3965 {
3966 pGuestMsr->u32Msr = MSR_K8_TSC_AUX;
3967 pGuestMsr->u32Reserved = 0;
3968 rc = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &pGuestMsr->u64Value);
3969 AssertRCReturn(rc, rc);
3970 pGuestMsr++; cGuestMsrs++;
3971 }
3972
3973 /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
3974 if (cGuestMsrs > MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc))
3975 {
3976 LogRel(("CPU autoload/store MSR count in VMCS exceeded cGuestMsrs=%u.\n", cGuestMsrs));
3977 pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
3978 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3979 }
3980
3981 /* Update the VCPU's copy of the guest MSR count. */
3982 pVCpu->hm.s.vmx.cGuestMsrs = cGuestMsrs;
3983 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cGuestMsrs); AssertRCReturn(rc, rc);
3984 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cGuestMsrs); AssertRCReturn(rc, rc);
3985#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
3986
3987 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_GUEST_AUTO_MSRS;
3988 }
3989
3990 /*
3991 * Guest Sysenter MSRs.
3992 * These flags are only set when MSR-bitmaps are not supported by the CPU and we cause
3993 * VM-exits on WRMSRs for these MSRs.
3994 */
3995 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
3996 {
3997 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pMixedCtx->SysEnter.cs); AssertRCReturn(rc, rc);
3998 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_CS_MSR;
3999 }
4000 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
4001 {
4002 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip); AssertRCReturn(rc, rc);
4003 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR;
4004 }
4005 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
4006 {
4007 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp); AssertRCReturn(rc, rc);
4008 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR;
4009 }
4010
4011 return rc;
4012}
4013
4014
4015/**
4016 * Loads the guest activity state into the guest-state area in the VMCS.
4017 *
4018 * @returns VBox status code.
4019 * @param pVCpu Pointer to the VMCPU.
4020 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4021 * out-of-sync. Make sure to update the required fields
4022 * before using them.
4023 *
4024 * @remarks No-long-jump zone!!!
4025 */
4026static int hmR0VmxLoadGuestActivityState(PVMCPU pVCpu, PCPUMCTX pCtx)
4027{
4028 /** @todo See if we can make use of other states, e.g.
4029 * VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN or HLT. */
4030 int rc = VINF_SUCCESS;
4031 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_VMX_GUEST_ACTIVITY_STATE)
4032 {
4033 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
4034 AssertRCReturn(rc, rc);
4035 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_VMX_GUEST_ACTIVITY_STATE;
4036 }
4037 return rc;
4038}
4039
4040
4041/**
4042 * Sets up the appropriate function to run guest code.
4043 *
4044 * @returns VBox status code.
4045 * @param pVCpu Pointer to the VMCPU.
4046 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4047 * out-of-sync. Make sure to update the required fields
4048 * before using them.
4049 *
4050 * @remarks No-long-jump zone!!!
4051 */
4052static int hmR0VmxSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4053{
4054 if (CPUMIsGuestInLongModeEx(pMixedCtx))
4055 {
4056#ifndef VBOX_ENABLE_64_BITS_GUESTS
4057 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4058#endif
4059 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
4060#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4061 /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
4062 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
4063 {
4064 pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
4065 /** @todo this isn't necessary, but I'm still seeing tripple faults. */
4066 VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
4067 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_EXIT_CTLS;
4068 }
4069#else
4070 /* 64-bit host or hybrid host. */
4071 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM64;
4072#endif
4073 }
4074 else
4075 {
4076 /* Guest is not in long mode, use the 32-bit handler. */
4077#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4078 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32)
4079 {
4080 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4081 /** @todo r=bird: Don't we need to set up the host resume (after
4082 * vmlaunch/vmresume) state here?? I'm forcing a trip to ring-3 now
4083 * in the hope that it will prevent crashing the host. A better
4084 * fix should be found as the guest may be going back and forth
4085 * between 16/32-bit and long mode frequently at times. */
4086 VMCPU_FF_SET(pVCpu, VMCPU_FF_TO_R3);
4087 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_EXIT_CTLS;
4088 }
4089#else
4090 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4091#endif
4092 }
4093 Assert(pVCpu->hm.s.vmx.pfnStartVM);
4094 return VINF_SUCCESS;
4095}
4096
4097
4098/**
4099 * Wrapper for running the guest code in VT-x.
4100 *
4101 * @returns VBox strict status code.
4102 * @param pVM Pointer to the VM.
4103 * @param pVCpu Pointer to the VMCPU.
4104 * @param pCtx Pointer to the guest-CPU context.
4105 *
4106 * @remarks No-long-jump zone!!!
4107 */
4108DECLINLINE(int) hmR0VmxRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4109{
4110 /*
4111 * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4112 * using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4113 * Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4114 */
4115 const bool fResumeVM = !!(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
4116 /** @todo Add stats for resume vs launch. */
4117#ifdef VBOX_WITH_KERNEL_USING_XMM
4118 return HMR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
4119#else
4120 return pVCpu->hm.s.vmx.pfnStartVM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu);
4121#endif
4122}
4123
4124
4125/**
4126 * Reports world-switch error and dumps some useful debug info.
4127 *
4128 * @param pVM Pointer to the VM.
4129 * @param pVCpu Pointer to the VMCPU.
4130 * @param rcVMRun The return code from VMLAUNCH/VMRESUME.
4131 * @param pCtx Pointer to the guest-CPU context.
4132 * @param pVmxTransient Pointer to the VMX transient structure (only
4133 * exitReason updated).
4134 */
4135static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx, PVMXTRANSIENT pVmxTransient)
4136{
4137 Assert(pVM);
4138 Assert(pVCpu);
4139 Assert(pCtx);
4140 Assert(pVmxTransient);
4141 HMVMX_ASSERT_PREEMPT_SAFE();
4142
4143 Log4(("VM-entry failure: %Rrc\n", rcVMRun));
4144 switch (rcVMRun)
4145 {
4146 case VERR_VMX_INVALID_VMXON_PTR:
4147 AssertFailed();
4148 break;
4149 case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
4150 case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
4151 {
4152 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
4153 rc |= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
4154 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
4155 AssertRC(rc);
4156
4157 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
4158 /* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
4159 Cannot do it here as we may have been long preempted. */
4160
4161#ifdef VBOX_STRICT
4162 Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
4163 pVmxTransient->uExitReason));
4164 Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQualification));
4165 Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
4166 if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
4167 Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
4168 else
4169 Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
4170 Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
4171 Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
4172
4173 /* VMX control bits. */
4174 uint32_t u32Val;
4175 uint64_t u64Val;
4176 HMVMXHCUINTREG uHCReg;
4177 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc);
4178 Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val));
4179 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc);
4180 Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val));
4181 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);
4182 Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val));
4183 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);
4184 Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val));
4185 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);
4186 Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val));
4187 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc);
4188 Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val));
4189 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc);
4190 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val));
4191 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc);
4192 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val));
4193 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc);
4194 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val));
4195 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc);
4196 Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val));
4197 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc);
4198 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val));
4199 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
4200 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val));
4201 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
4202 Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val));
4203 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc);
4204 Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val));
4205 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc);
4206 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val));
4207 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc);
4208 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val));
4209 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
4210 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
4211 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
4212 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
4213 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
4214 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
4215 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
4216 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
4217 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
4218 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
4219
4220 /* Guest bits. */
4221 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);
4222 Log4(("Old Guest Rip %#RX64 New %#RX64\n", pCtx->rip, u64Val));
4223 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);
4224 Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pCtx->rsp, u64Val));
4225 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);
4226 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pCtx->eflags.u32, u32Val));
4227 rc = VMXReadVmcs32(VMX_VMCS16_GUEST_FIELD_VPID, &u32Val); AssertRC(rc);
4228 Log4(("VMX_VMCS16_GUEST_FIELD_VPID %u\n", u32Val));
4229
4230 /* Host bits. */
4231 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);
4232 Log4(("Host CR0 %#RHr\n", uHCReg));
4233 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);
4234 Log4(("Host CR3 %#RHr\n", uHCReg));
4235 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);
4236 Log4(("Host CR4 %#RHr\n", uHCReg));
4237
4238 RTGDTR HostGdtr;
4239 PCX86DESCHC pDesc;
4240 ASMGetGDTR(&HostGdtr);
4241 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_CS, &u32Val); AssertRC(rc);
4242 Log4(("Host CS %#08x\n", u32Val));
4243 if (u32Val < HostGdtr.cbGdt)
4244 {
4245 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
4246 HMR0DumpDescriptor(pDesc, u32Val, "CS: ");
4247 }
4248
4249 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_DS, &u32Val); AssertRC(rc);
4250 Log4(("Host DS %#08x\n", u32Val));
4251 if (u32Val < HostGdtr.cbGdt)
4252 {
4253 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
4254 HMR0DumpDescriptor(pDesc, u32Val, "DS: ");
4255 }
4256
4257 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_ES, &u32Val); AssertRC(rc);
4258 Log4(("Host ES %#08x\n", u32Val));
4259 if (u32Val < HostGdtr.cbGdt)
4260 {
4261 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
4262 HMR0DumpDescriptor(pDesc, u32Val, "ES: ");
4263 }
4264
4265 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_FS, &u32Val); AssertRC(rc);
4266 Log4(("Host FS %#08x\n", u32Val));
4267 if (u32Val < HostGdtr.cbGdt)
4268 {
4269 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
4270 HMR0DumpDescriptor(pDesc, u32Val, "FS: ");
4271 }
4272
4273 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_GS, &u32Val); AssertRC(rc);
4274 Log4(("Host GS %#08x\n", u32Val));
4275 if (u32Val < HostGdtr.cbGdt)
4276 {
4277 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
4278 HMR0DumpDescriptor(pDesc, u32Val, "GS: ");
4279 }
4280
4281 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_SS, &u32Val); AssertRC(rc);
4282 Log4(("Host SS %#08x\n", u32Val));
4283 if (u32Val < HostGdtr.cbGdt)
4284 {
4285 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
4286 HMR0DumpDescriptor(pDesc, u32Val, "SS: ");
4287 }
4288
4289 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FIELD_TR, &u32Val); AssertRC(rc);
4290 Log4(("Host TR %#08x\n", u32Val));
4291 if (u32Val < HostGdtr.cbGdt)
4292 {
4293 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
4294 HMR0DumpDescriptor(pDesc, u32Val, "TR: ");
4295 }
4296
4297 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);
4298 Log4(("Host TR Base %#RHv\n", uHCReg));
4299 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);
4300 Log4(("Host GDTR Base %#RHv\n", uHCReg));
4301 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);
4302 Log4(("Host IDTR Base %#RHv\n", uHCReg));
4303 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);
4304 Log4(("Host SYSENTER CS %#08x\n", u32Val));
4305 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);
4306 Log4(("Host SYSENTER EIP %#RHv\n", uHCReg));
4307 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);
4308 Log4(("Host SYSENTER ESP %#RHv\n", uHCReg));
4309 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);
4310 Log4(("Host RSP %#RHv\n", uHCReg));
4311 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);
4312 Log4(("Host RIP %#RHv\n", uHCReg));
4313# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4314 if (HMVMX_IS_64BIT_HOST_MODE())
4315 {
4316 Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
4317 Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
4318 Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4319 Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4320 Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4321 Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
4322 }
4323# endif
4324#endif /* VBOX_STRICT */
4325 break;
4326 }
4327
4328 default:
4329 /* Impossible */
4330 AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
4331 break;
4332 }
4333 NOREF(pVM);
4334}
4335
4336
4337#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4338#ifndef VMX_USE_CACHED_VMCS_ACCESSES
4339# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
4340#endif
4341#ifdef VBOX_STRICT
4342static bool hmR0VmxIsValidWriteField(uint32_t idxField)
4343{
4344 switch (idxField)
4345 {
4346 case VMX_VMCS_GUEST_RIP:
4347 case VMX_VMCS_GUEST_RSP:
4348 case VMX_VMCS_GUEST_SYSENTER_EIP:
4349 case VMX_VMCS_GUEST_SYSENTER_ESP:
4350 case VMX_VMCS_GUEST_GDTR_BASE:
4351 case VMX_VMCS_GUEST_IDTR_BASE:
4352 case VMX_VMCS_GUEST_CS_BASE:
4353 case VMX_VMCS_GUEST_DS_BASE:
4354 case VMX_VMCS_GUEST_ES_BASE:
4355 case VMX_VMCS_GUEST_FS_BASE:
4356 case VMX_VMCS_GUEST_GS_BASE:
4357 case VMX_VMCS_GUEST_SS_BASE:
4358 case VMX_VMCS_GUEST_LDTR_BASE:
4359 case VMX_VMCS_GUEST_TR_BASE:
4360 case VMX_VMCS_GUEST_CR3:
4361 return true;
4362 }
4363 return false;
4364}
4365
4366static bool hmR0VmxIsValidReadField(uint32_t idxField)
4367{
4368 switch (idxField)
4369 {
4370 /* Read-only fields. */
4371 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4372 return true;
4373 }
4374 /* Remaining readable fields should also be writable. */
4375 return hmR0VmxIsValidWriteField(idxField);
4376}
4377#endif /* VBOX_STRICT */
4378
4379
4380/**
4381 * Executes the specified handler in 64-bit mode.
4382 *
4383 * @returns VBox status code.
4384 * @param pVM Pointer to the VM.
4385 * @param pVCpu Pointer to the VMCPU.
4386 * @param pCtx Pointer to the guest CPU context.
4387 * @param enmOp The operation to perform.
4388 * @param cbParam Number of parameters.
4389 * @param paParam Array of 32-bit parameters.
4390 */
4391VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
4392 uint32_t *paParam)
4393{
4394 int rc, rc2;
4395 PHMGLOBALCPUINFO pCpu;
4396 RTHCPHYS HCPhysCpuPage;
4397 RTCCUINTREG uOldEflags;
4398
4399 AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
4400 Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
4401 Assert(pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Write.aField));
4402 Assert(pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Read.aField));
4403
4404#ifdef VBOX_STRICT
4405 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries; i++)
4406 Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VMCSCache.Write.aField[i]));
4407
4408 for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries; i++)
4409 Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VMCSCache.Read.aField[i]));
4410#endif
4411
4412 /* Disable interrupts. */
4413 uOldEflags = ASMIntDisableFlags();
4414
4415#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
4416 RTCPUID idHostCpu = RTMpCpuId();
4417 CPUMR0SetLApic(pVCpu, idHostCpu);
4418#endif
4419
4420 pCpu = HMR0GetCurrentCpu();
4421 HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
4422
4423 /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
4424 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
4425
4426 /* Leave VMX Root Mode. */
4427 VMXDisable();
4428
4429 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4430
4431 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
4432 CPUMSetHyperEIP(pVCpu, enmOp);
4433 for (int i = (int)cbParam - 1; i >= 0; i--)
4434 CPUMPushHyper(pVCpu, paParam[i]);
4435
4436 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
4437
4438 /* Call the switcher. */
4439 rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
4440 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
4441
4442 /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
4443 /* Make sure the VMX instructions don't cause #UD faults. */
4444 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
4445
4446 /* Re-enter VMX Root Mode */
4447 rc2 = VMXEnable(HCPhysCpuPage);
4448 if (RT_FAILURE(rc2))
4449 {
4450 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4451 ASMSetFlags(uOldEflags);
4452 return rc2;
4453 }
4454
4455 rc2 = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
4456 AssertRC(rc2);
4457 Assert(!(ASMGetFlags() & X86_EFL_IF));
4458 ASMSetFlags(uOldEflags);
4459 return rc;
4460}
4461
4462
4463/**
4464 * Prepares for and executes VMLAUNCH (64 bits guests) for 32-bit hosts
4465 * supporting 64-bit guests.
4466 *
4467 * @returns VBox status code.
4468 * @param fResume Whether to VMLAUNCH or VMRESUME.
4469 * @param pCtx Pointer to the guest-CPU context.
4470 * @param pCache Pointer to the VMCS cache.
4471 * @param pVM Pointer to the VM.
4472 * @param pVCpu Pointer to the VMCPU.
4473 */
4474DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4475{
4476 uint32_t aParam[6];
4477 PHMGLOBALCPUINFO pCpu = NULL;
4478 RTHCPHYS HCPhysCpuPage = 0;
4479 int rc = VERR_INTERNAL_ERROR_5;
4480
4481 pCpu = HMR0GetCurrentCpu();
4482 HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
4483
4484#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4485 pCache->uPos = 1;
4486 pCache->interPD = PGMGetInterPaeCR3(pVM);
4487 pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
4488#endif
4489
4490#ifdef VBOX_STRICT
4491 pCache->TestIn.HCPhysCpuPage = 0;
4492 pCache->TestIn.HCPhysVmcs = 0;
4493 pCache->TestIn.pCache = 0;
4494 pCache->TestOut.HCPhysVmcs = 0;
4495 pCache->TestOut.pCache = 0;
4496 pCache->TestOut.pCtx = 0;
4497 pCache->TestOut.eflags = 0;
4498#endif
4499
4500 aParam[0] = (uint32_t)(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
4501 aParam[1] = (uint32_t)(HCPhysCpuPage >> 32); /* Param 1: VMXON physical address - Hi. */
4502 aParam[2] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
4503 aParam[3] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs >> 32); /* Param 2: VMCS physical address - Hi. */
4504 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
4505 aParam[5] = 0;
4506
4507#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4508 pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
4509 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
4510#endif
4511 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_VMXRCStartVM64, 6, &aParam[0]);
4512
4513#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4514 Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
4515 Assert(pCtx->dr[4] == 10);
4516 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
4517#endif
4518
4519#ifdef VBOX_STRICT
4520 AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
4521 AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
4522 pVCpu->hm.s.vmx.HCPhysVmcs));
4523 AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
4524 pCache->TestOut.HCPhysVmcs));
4525 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
4526 pCache->TestOut.pCache));
4527 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
4528 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
4529 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
4530 pCache->TestOut.pCtx));
4531 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4532#endif
4533 return rc;
4534}
4535
4536
4537/**
4538 * Initialize the VMCS-Read cache. The VMCS cache is used for 32-bit hosts
4539 * running 64-bit guests (except 32-bit Darwin which runs with 64-bit paging in
4540 * 32-bit mode) for 64-bit fields that cannot be accessed in 32-bit mode. Some
4541 * 64-bit fields -can- be accessed (those that have a 32-bit FULL & HIGH part).
4542 *
4543 * @returns VBox status code.
4544 * @param pVM Pointer to the VM.
4545 * @param pVCpu Pointer to the VMCPU.
4546 */
4547static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu)
4548{
4549#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \
4550{ \
4551 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
4552 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
4553 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
4554 ++cReadFields; \
4555}
4556
4557 AssertPtr(pVM);
4558 AssertPtr(pVCpu);
4559 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
4560 uint32_t cReadFields = 0;
4561
4562 /*
4563 * Don't remove the #if 0'd fields in this code. They're listed here for consistency
4564 * and serve to indicate exceptions to the rules.
4565 */
4566
4567 /* Guest-natural selector base fields. */
4568#if 0
4569 /* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */
4570 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR0);
4571 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR4);
4572#endif
4573 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_ES_BASE);
4574 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CS_BASE);
4575 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SS_BASE);
4576 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DS_BASE);
4577 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_FS_BASE);
4578 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GS_BASE);
4579 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_LDTR_BASE);
4580 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_TR_BASE);
4581 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
4582 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
4583 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
4584 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
4585#if 0
4586 /* Unused natural width guest-state fields. */
4587 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS);
4588 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3); /* Handled in Nested Paging case */
4589#endif
4590 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
4591 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
4592
4593 /* 64-bit guest-state fields; unused as we use two 32-bit VMREADs for these 64-bit fields (using "FULL" and "HIGH" fields). */
4594#if 0
4595 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL);
4596 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_DEBUGCTL_FULL);
4597 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PAT_FULL);
4598 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_EFER_FULL);
4599 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL);
4600 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE0_FULL);
4601 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE1_FULL);
4602 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE2_FULL);
4603 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE3_FULL);
4604#endif
4605
4606 /* Natural width guest-state fields. */
4607 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
4608#if 0
4609 /* Currently unused field. */
4610 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR);
4611#endif
4612
4613 if (pVM->hm.s.fNestedPaging)
4614 {
4615 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
4616 AssertMsg(cReadFields == VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields,
4617 VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX));
4618 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
4619 }
4620 else
4621 {
4622 AssertMsg(cReadFields == VMX_VMCS_MAX_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields, VMX_VMCS_MAX_CACHE_IDX));
4623 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
4624 }
4625
4626#undef VMXLOCAL_INIT_READ_CACHE_FIELD
4627 return VINF_SUCCESS;
4628}
4629
4630
4631/**
4632 * Writes a field into the VMCS. This can either directly invoke a VMWRITE or
4633 * queue up the VMWRITE by using the VMCS write cache (on 32-bit hosts, except
4634 * darwin, running 64-bit guests).
4635 *
4636 * @returns VBox status code.
4637 * @param pVCpu Pointer to the VMCPU.
4638 * @param idxField The VMCS field encoding.
4639 * @param u64Val 16, 32 or 64 bits value.
4640 */
4641VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4642{
4643 int rc;
4644 switch (idxField)
4645 {
4646 /*
4647 * These fields consists of a "FULL" and a "HIGH" part which can be written to individually.
4648 */
4649 /* 64-bit Control fields. */
4650 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
4651 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
4652 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
4653 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
4654 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
4655 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
4656 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
4657 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
4658 case VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL:
4659 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
4660 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
4661 case VMX_VMCS64_CTRL_EPTP_FULL:
4662 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
4663 /* 64-bit Guest-state fields. */
4664 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
4665 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
4666 case VMX_VMCS64_GUEST_PAT_FULL:
4667 case VMX_VMCS64_GUEST_EFER_FULL:
4668 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
4669 case VMX_VMCS64_GUEST_PDPTE0_FULL:
4670 case VMX_VMCS64_GUEST_PDPTE1_FULL:
4671 case VMX_VMCS64_GUEST_PDPTE2_FULL:
4672 case VMX_VMCS64_GUEST_PDPTE3_FULL:
4673 /* 64-bit Host-state fields. */
4674 case VMX_VMCS64_HOST_FIELD_PAT_FULL:
4675 case VMX_VMCS64_HOST_FIELD_EFER_FULL:
4676 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
4677 {
4678 rc = VMXWriteVmcs32(idxField, u64Val);
4679 rc |= VMXWriteVmcs32(idxField + 1, (uint32_t)(u64Val >> 32));
4680 break;
4681 }
4682
4683 /*
4684 * These fields do not have high and low parts. Queue up the VMWRITE by using the VMCS write-cache (for 64-bit
4685 * values). When we switch the host to 64-bit mode for running 64-bit guests, these VMWRITEs get executed then.
4686 */
4687 /* Natural-width Guest-state fields. */
4688 case VMX_VMCS_GUEST_CR3:
4689 case VMX_VMCS_GUEST_ES_BASE:
4690 case VMX_VMCS_GUEST_CS_BASE:
4691 case VMX_VMCS_GUEST_SS_BASE:
4692 case VMX_VMCS_GUEST_DS_BASE:
4693 case VMX_VMCS_GUEST_FS_BASE:
4694 case VMX_VMCS_GUEST_GS_BASE:
4695 case VMX_VMCS_GUEST_LDTR_BASE:
4696 case VMX_VMCS_GUEST_TR_BASE:
4697 case VMX_VMCS_GUEST_GDTR_BASE:
4698 case VMX_VMCS_GUEST_IDTR_BASE:
4699 case VMX_VMCS_GUEST_RSP:
4700 case VMX_VMCS_GUEST_RIP:
4701 case VMX_VMCS_GUEST_SYSENTER_ESP:
4702 case VMX_VMCS_GUEST_SYSENTER_EIP:
4703 {
4704 if (!(u64Val >> 32))
4705 {
4706 /* If this field is 64-bit, VT-x will zero out the top bits. */
4707 rc = VMXWriteVmcs32(idxField, (uint32_t)u64Val);
4708 }
4709 else
4710 {
4711 /* Assert that only the 32->64 switcher case should ever come here. */
4712 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests);
4713 rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
4714 }
4715 break;
4716 }
4717
4718 default:
4719 {
4720 AssertMsgFailed(("VMXWriteVmcs64Ex: Invalid field %#RX32 (pVCpu=%p u64Val=%#RX64)\n", idxField, pVCpu, u64Val));
4721 rc = VERR_INVALID_PARAMETER;
4722 break;
4723 }
4724 }
4725 AssertRCReturn(rc, rc);
4726 return rc;
4727}
4728
4729
4730/**
4731 * Queue up a VMWRITE by using the VMCS write cache. This is only used on 32-bit
4732 * hosts (except darwin) for 64-bit guests.
4733 *
4734 * @param pVCpu Pointer to the VMCPU.
4735 * @param idxField The VMCS field encoding.
4736 * @param u64Val 16, 32 or 64 bits value.
4737 */
4738VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4739{
4740 AssertPtr(pVCpu);
4741 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
4742
4743 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
4744 ("entries=%u\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4745
4746 /* Make sure there are no duplicates. */
4747 for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
4748 {
4749 if (pCache->Write.aField[i] == idxField)
4750 {
4751 pCache->Write.aFieldVal[i] = u64Val;
4752 return VINF_SUCCESS;
4753 }
4754 }
4755
4756 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4757 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4758 pCache->Write.cValidEntries++;
4759 return VINF_SUCCESS;
4760}
4761
4762/* Enable later when the assembly code uses these as callbacks. */
4763#if 0
4764/*
4765 * Loads the VMCS write-cache into the CPU (by executing VMWRITEs).
4766 *
4767 * @param pVCpu Pointer to the VMCPU.
4768 * @param pCache Pointer to the VMCS cache.
4769 *
4770 * @remarks No-long-jump zone!!!
4771 */
4772VMMR0DECL(void) VMXWriteCachedVmcsLoad(PVMCPU pVCpu, PVMCSCACHE pCache)
4773{
4774 AssertPtr(pCache);
4775 for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
4776 {
4777 int rc = VMXWriteVmcs64(pCache->Write.aField[i], pCache->Write.aFieldVal[i]);
4778 AssertRC(rc);
4779 }
4780 pCache->Write.cValidEntries = 0;
4781}
4782
4783
4784/**
4785 * Stores the VMCS read-cache from the CPU (by executing VMREADs).
4786 *
4787 * @param pVCpu Pointer to the VMCPU.
4788 * @param pCache Pointer to the VMCS cache.
4789 *
4790 * @remarks No-long-jump zone!!!
4791 */
4792VMMR0DECL(void) VMXReadCachedVmcsStore(PVMCPU pVCpu, PVMCSCACHE pCache)
4793{
4794 AssertPtr(pCache);
4795 for (uint32_t i = 0; i < pCache->Read.cValidEntries; i++)
4796 {
4797 int rc = VMXReadVmcs64(pCache->Read.aField[i], &pCache->Read.aFieldVal[i]);
4798 AssertRC(rc);
4799 }
4800}
4801#endif
4802#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4803
4804
4805/**
4806 * Sets up the usage of TSC-offsetting and updates the VMCS. If offsetting is
4807 * not possible, cause VM-exits on RDTSC(P)s. Also sets up the VMX preemption
4808 * timer.
4809 *
4810 * @returns VBox status code.
4811 * @param pVCpu Pointer to the VMCPU.
4812 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4813 * out-of-sync. Make sure to update the required fields
4814 * before using them.
4815 * @remarks No-long-jump zone!!!
4816 */
4817static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4818{
4819 int rc = VERR_INTERNAL_ERROR_5;
4820 bool fOffsettedTsc = false;
4821 PVM pVM = pVCpu->CTX_SUFF(pVM);
4822 if (pVM->hm.s.vmx.fUsePreemptTimer)
4823 {
4824 uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVCpu, &fOffsettedTsc, &pVCpu->hm.s.vmx.u64TSCOffset);
4825
4826 /* Make sure the returned values have sane upper and lower boundaries. */
4827 uint64_t u64CpuHz = SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage);
4828 cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second */
4829 cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
4830 cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
4831
4832 uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
4833 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE, cPreemptionTickCount); AssertRC(rc);
4834 }
4835 else
4836 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset);
4837
4838 if (fOffsettedTsc)
4839 {
4840 uint64_t u64CurTSC = ASMReadTSC();
4841 if (u64CurTSC + pVCpu->hm.s.vmx.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
4842 {
4843 /* Note: VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
4844 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset); AssertRC(rc);
4845
4846 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
4847 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
4848 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
4849 }
4850 else
4851 {
4852 /* VM-exit on RDTSC(P) as we would otherwise pass decreasing TSC values to the guest. */
4853 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
4854 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
4855 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
4856 }
4857 }
4858 else
4859 {
4860 /* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
4861 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
4862 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
4863 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
4864 }
4865}
4866
4867
4868/**
4869 * Determines if an exception is a contributory exception. Contributory
4870 * exceptions are ones which can cause double-faults. Page-fault is
4871 * intentionally not included here as it's a conditional contributory exception.
4872 *
4873 * @returns true if the exception is contributory, false otherwise.
4874 * @param uVector The exception vector.
4875 */
4876DECLINLINE(bool) hmR0VmxIsContributoryXcpt(const uint32_t uVector)
4877{
4878 switch (uVector)
4879 {
4880 case X86_XCPT_GP:
4881 case X86_XCPT_SS:
4882 case X86_XCPT_NP:
4883 case X86_XCPT_TS:
4884 case X86_XCPT_DE:
4885 return true;
4886 default:
4887 break;
4888 }
4889 return false;
4890}
4891
4892
4893/**
4894 * Sets an event as a pending event to be injected into the guest.
4895 *
4896 * @param pVCpu Pointer to the VMCPU.
4897 * @param u32IntrInfo The VM-entry interruption-information field.
4898 * @param cbInstr The VM-entry instruction length in bytes (for software
4899 * interrupts, exceptions and privileged software
4900 * exceptions).
4901 * @param u32ErrCode The VM-entry exception error code.
4902 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a
4903 * page-fault.
4904 *
4905 * @remarks Statistics counter assumes this is a guest event being injected or
4906 * re-injected into the guest, i.e. 'StatInjectPendingReflect' is
4907 * always incremented.
4908 */
4909DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntrInfo, uint32_t cbInstr, uint32_t u32ErrCode,
4910 RTGCUINTPTR GCPtrFaultAddress)
4911{
4912 Assert(!pVCpu->hm.s.Event.fPending);
4913 pVCpu->hm.s.Event.fPending = true;
4914 pVCpu->hm.s.Event.u64IntrInfo = u32IntrInfo;
4915 pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
4916 pVCpu->hm.s.Event.cbInstr = cbInstr;
4917 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
4918
4919 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4920}
4921
4922
4923/**
4924 * Sets a double-fault (#DF) exception as pending-for-injection into the VM.
4925 *
4926 * @param pVCpu Pointer to the VMCPU.
4927 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4928 * out-of-sync. Make sure to update the required fields
4929 * before using them.
4930 */
4931DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4932{
4933 uint32_t u32IntrInfo = X86_XCPT_DF | VMX_EXIT_INTERRUPTION_INFO_VALID;
4934 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
4935 u32IntrInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
4936 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
4937}
4938
4939
4940/**
4941 * Handle a condition that occurred while delivering an event through the guest
4942 * IDT.
4943 *
4944 * @returns VBox status code (informational error codes included).
4945 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
4946 * @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
4947 * continue execution of the guest which will delivery the #DF.
4948 * @retval VINF_EM_RESET if we detected a triple-fault condition.
4949 *
4950 * @param pVCpu Pointer to the VMCPU.
4951 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4952 * out-of-sync. Make sure to update the required fields
4953 * before using them.
4954 * @param pVmxTransient Pointer to the VMX transient structure.
4955 *
4956 * @remarks No-long-jump zone!!!
4957 */
4958static int hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
4959{
4960 int rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
4961 AssertRCReturn(rc, rc);
4962 if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
4963 {
4964 rc = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
4965 AssertRCReturn(rc, rc);
4966
4967 uint32_t uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
4968 uint32_t uExitVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntrInfo);
4969 uint32_t uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
4970
4971 typedef enum
4972 {
4973 VMXREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4974 VMXREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4975 VMXREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4976 VMXREFLECTXCPT_NONE /* Nothing to reflect. */
4977 } VMXREFLECTXCPT;
4978
4979 /* See Intel spec. 30.7.1.1 "Reflecting Exceptions to Guest Software". */
4980 VMXREFLECTXCPT enmReflect = VMXREFLECTXCPT_NONE;
4981 if (VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntrInfo))
4982 {
4983 if (uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT)
4984 {
4985 enmReflect = VMXREFLECTXCPT_XCPT;
4986#ifdef VBOX_STRICT
4987 if ( hmR0VmxIsContributoryXcpt(uIdtVector)
4988 && uExitVector == X86_XCPT_PF)
4989 {
4990 Log4(("IDT: vcpu[%RU32] Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
4991 }
4992#endif
4993 if ( uExitVector == X86_XCPT_PF
4994 && uIdtVector == X86_XCPT_PF)
4995 {
4996 pVmxTransient->fVectoringPF = true;
4997 Log4(("IDT: vcpu[%RU32] Vectoring #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
4998 }
4999 else if ( (pVCpu->hm.s.vmx.u32XcptBitmap & HMVMX_CONTRIBUTORY_XCPT_MASK)
5000 && hmR0VmxIsContributoryXcpt(uExitVector)
5001 && ( hmR0VmxIsContributoryXcpt(uIdtVector)
5002 || uIdtVector == X86_XCPT_PF))
5003 {
5004 enmReflect = VMXREFLECTXCPT_DF;
5005 }
5006 else if (uIdtVector == X86_XCPT_DF)
5007 enmReflect = VMXREFLECTXCPT_TF;
5008 }
5009 else if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
5010 || uIntType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
5011 || uIntType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
5012 {
5013 /*
5014 * Ignore software interrupts (INT n), software exceptions (#BP, #OF) and privileged software exception
5015 * (whatever they are) as they reoccur when restarting the instruction.
5016 */
5017 enmReflect = VMXREFLECTXCPT_XCPT;
5018 }
5019 }
5020 else
5021 {
5022 /*
5023 * If event delivery caused an EPT violation/misconfig or APIC access VM-exit, then the VM-exit
5024 * interruption-information will not be valid and we end up here. In such cases, it is sufficient to reflect the
5025 * original exception to the guest after handling the VM-exit.
5026 */
5027 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
5028 || uIntType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
5029 || uIntType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
5030 {
5031 enmReflect = VMXREFLECTXCPT_XCPT;
5032 }
5033 }
5034
5035 switch (enmReflect)
5036 {
5037 case VMXREFLECTXCPT_XCPT:
5038 {
5039 Assert( uIntType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT
5040 && uIntType != VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
5041 && uIntType != VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
5042
5043 uint32_t u32ErrCode = 0;
5044 if (VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo))
5045 {
5046 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
5047 AssertRCReturn(rc, rc);
5048 u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
5049 }
5050
5051 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF. See hmR0VmxExitXcptPF(). */
5052 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INTR_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
5053 0 /* cbInstr */, u32ErrCode, pMixedCtx->cr2);
5054 rc = VINF_SUCCESS;
5055 Log4(("IDT: vcpu[%RU32] Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->idCpu,
5056 pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.u32ErrCode));
5057
5058 break;
5059 }
5060
5061 case VMXREFLECTXCPT_DF:
5062 {
5063 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
5064 rc = VINF_HM_DOUBLE_FAULT;
5065 Log4(("IDT: vcpu[%RU32] Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->idCpu,
5066 pVCpu->hm.s.Event.u64IntrInfo, uIdtVector, uExitVector));
5067
5068 break;
5069 }
5070
5071 case VMXREFLECTXCPT_TF:
5072 {
5073 rc = VINF_EM_RESET;
5074 Log4(("IDT: vcpu[%RU32] Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", pVCpu->idCpu, uIdtVector,
5075 uExitVector));
5076 break;
5077 }
5078
5079 default:
5080 Assert(rc == VINF_SUCCESS);
5081 break;
5082 }
5083 }
5084 Assert(rc == VINF_SUCCESS || rc == VINF_HM_DOUBLE_FAULT || rc == VINF_EM_RESET);
5085 return rc;
5086}
5087
5088
5089/**
5090 * Saves the guest's CR0 register from the VMCS into the guest-CPU context.
5091 *
5092 * @returns VBox status code.
5093 * @param pVCpu Pointer to the VMCPU.
5094 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5095 * out-of-sync. Make sure to update the required fields
5096 * before using them.
5097 *
5098 * @remarks No-long-jump zone!!!
5099 */
5100static int hmR0VmxSaveGuestCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5101{
5102 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR0))
5103 {
5104 uint32_t uVal = 0;
5105 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &uVal);
5106 AssertRCReturn(rc, rc);
5107 uint32_t uShadow = 0;
5108 rc = VMXReadVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uShadow);
5109 AssertRCReturn(rc, rc);
5110
5111 uVal = (uShadow & pVCpu->hm.s.vmx.u32CR0Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR0Mask);
5112 CPUMSetGuestCR0(pVCpu, uVal);
5113 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR0;
5114 }
5115 return VINF_SUCCESS;
5116}
5117
5118
5119/**
5120 * Saves the guest's CR4 register from the VMCS into the guest-CPU context.
5121 *
5122 * @returns VBox status code.
5123 * @param pVCpu Pointer to the VMCPU.
5124 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5125 * out-of-sync. Make sure to update the required fields
5126 * before using them.
5127 *
5128 * @remarks No-long-jump zone!!!
5129 */
5130static int hmR0VmxSaveGuestCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5131{
5132 int rc = VINF_SUCCESS;
5133 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR4))
5134 {
5135 uint32_t uVal = 0;
5136 uint32_t uShadow = 0;
5137 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &uVal);
5138 AssertRCReturn(rc, rc);
5139 rc = VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uShadow);
5140 AssertRCReturn(rc, rc);
5141
5142 uVal = (uShadow & pVCpu->hm.s.vmx.u32CR4Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR4Mask);
5143 CPUMSetGuestCR4(pVCpu, uVal);
5144 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR4;
5145 }
5146 return rc;
5147}
5148
5149
5150/**
5151 * Saves the guest's RIP register from the VMCS into the guest-CPU context.
5152 *
5153 * @returns VBox status code.
5154 * @param pVCpu Pointer to the VMCPU.
5155 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5156 * out-of-sync. Make sure to update the required fields
5157 * before using them.
5158 *
5159 * @remarks No-long-jump zone!!!
5160 */
5161static int hmR0VmxSaveGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5162{
5163 int rc = VINF_SUCCESS;
5164 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RIP))
5165 {
5166 uint64_t u64Val = 0;
5167 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);
5168 AssertRCReturn(rc, rc);
5169
5170 pMixedCtx->rip = u64Val;
5171 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RIP;
5172 }
5173 return rc;
5174}
5175
5176
5177/**
5178 * Saves the guest's RSP register from the VMCS into the guest-CPU context.
5179 *
5180 * @returns VBox status code.
5181 * @param pVCpu Pointer to the VMCPU.
5182 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5183 * out-of-sync. Make sure to update the required fields
5184 * before using them.
5185 *
5186 * @remarks No-long-jump zone!!!
5187 */
5188static int hmR0VmxSaveGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5189{
5190 int rc = VINF_SUCCESS;
5191 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RSP))
5192 {
5193 uint64_t u64Val = 0;
5194 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);
5195 AssertRCReturn(rc, rc);
5196
5197 pMixedCtx->rsp = u64Val;
5198 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RSP;
5199 }
5200 return rc;
5201}
5202
5203
5204/**
5205 * Saves the guest's RFLAGS from the VMCS into the guest-CPU context.
5206 *
5207 * @returns VBox status code.
5208 * @param pVCpu Pointer to the VMCPU.
5209 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5210 * out-of-sync. Make sure to update the required fields
5211 * before using them.
5212 *
5213 * @remarks No-long-jump zone!!!
5214 */
5215static int hmR0VmxSaveGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5216{
5217 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS))
5218 {
5219 uint32_t uVal = 0;
5220 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &uVal);
5221 AssertRCReturn(rc, rc);
5222
5223 pMixedCtx->eflags.u32 = uVal;
5224 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active) /* Undo our real-on-v86-mode changes to eflags if necessary. */
5225 {
5226 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
5227 Log4(("Saving real-mode EFLAGS VT-x view=%#RX32\n", pMixedCtx->eflags.u32));
5228
5229 pMixedCtx->eflags.Bits.u1VM = 0;
5230 pMixedCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.Eflags.Bits.u2IOPL;
5231 }
5232
5233 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_RFLAGS;
5234 }
5235 return VINF_SUCCESS;
5236}
5237
5238
5239/**
5240 * Wrapper for saving the guest's RIP, RSP and RFLAGS from the VMCS into the
5241 * guest-CPU context.
5242 */
5243DECLINLINE(int) hmR0VmxSaveGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5244{
5245 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
5246 rc |= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
5247 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
5248 return rc;
5249}
5250
5251
5252/**
5253 * Saves the guest's interruptibility-state ("interrupt shadow" as AMD calls it)
5254 * from the guest-state area in the VMCS.
5255 *
5256 * @param pVCpu Pointer to the VMCPU.
5257 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5258 * out-of-sync. Make sure to update the required fields
5259 * before using them.
5260 *
5261 * @remarks No-long-jump zone!!!
5262 */
5263static void hmR0VmxSaveGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5264{
5265 uint32_t uIntrState = 0;
5266 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
5267 AssertRC(rc);
5268
5269 if (!uIntrState)
5270 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5271 else
5272 {
5273 Assert( uIntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
5274 || uIntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
5275 rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
5276 AssertRC(rc);
5277 rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* for hmR0VmxGetGuestIntrState(). */
5278 AssertRC(rc);
5279
5280 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
5281 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
5282 }
5283}
5284
5285
5286/**
5287 * Saves the guest's activity state.
5288 *
5289 * @returns VBox status code.
5290 * @param pVCpu Pointer to the VMCPU.
5291 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5292 * out-of-sync. Make sure to update the required fields
5293 * before using them.
5294 *
5295 * @remarks No-long-jump zone!!!
5296 */
5297static int hmR0VmxSaveGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5298{
5299 /* Nothing to do for now until we make use of different guest-CPU activity state. Just update the flag. */
5300 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_ACTIVITY_STATE;
5301 return VINF_SUCCESS;
5302}
5303
5304
5305/**
5306 * Saves the guest SYSENTER MSRs (SYSENTER_CS, SYSENTER_EIP, SYSENTER_ESP) from
5307 * the current VMCS into the guest-CPU context.
5308 *
5309 * @returns VBox status code.
5310 * @param pVCpu Pointer to the VMCPU.
5311 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5312 * out-of-sync. Make sure to update the required fields
5313 * before using them.
5314 *
5315 * @remarks No-long-jump zone!!!
5316 */
5317static int hmR0VmxSaveGuestSysenterMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5318{
5319 int rc = VINF_SUCCESS;
5320 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR))
5321 {
5322 uint32_t u32Val = 0;
5323 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val); AssertRCReturn(rc, rc);
5324 pMixedCtx->SysEnter.cs = u32Val;
5325 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR;
5326 }
5327
5328 uint64_t u64Val = 0;
5329 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR))
5330 {
5331 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &u64Val); AssertRCReturn(rc, rc);
5332 pMixedCtx->SysEnter.eip = u64Val;
5333 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR;
5334 }
5335 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR))
5336 {
5337 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &u64Val); AssertRCReturn(rc, rc);
5338 pMixedCtx->SysEnter.esp = u64Val;
5339 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR;
5340 }
5341 return rc;
5342}
5343
5344
5345/**
5346 * Saves the guest FS_BASE MSRs from the current VMCS into the guest-CPU
5347 * context.
5348 *
5349 * @returns VBox status code.
5350 * @param pVCpu Pointer to the VMCPU.
5351 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5352 * out-of-sync. Make sure to update the required fields
5353 * before using them.
5354 *
5355 * @remarks No-long-jump zone!!!
5356 */
5357static int hmR0VmxSaveGuestFSBaseMsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5358{
5359 int rc = VINF_SUCCESS;
5360 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_FS_BASE_MSR))
5361 {
5362 uint64_t u64Val = 0;
5363 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_FS_BASE, &u64Val); AssertRCReturn(rc, rc);
5364 pMixedCtx->fs.u64Base = u64Val;
5365 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_FS_BASE_MSR;
5366 }
5367 return rc;
5368}
5369
5370
5371/**
5372 * Saves the guest GS_BASE MSRs from the current VMCS into the guest-CPU
5373 * context.
5374 *
5375 * @returns VBox status code.
5376 * @param pVCpu Pointer to the VMCPU.
5377 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5378 * out-of-sync. Make sure to update the required fields
5379 * before using them.
5380 *
5381 * @remarks No-long-jump zone!!!
5382 */
5383static int hmR0VmxSaveGuestGSBaseMsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5384{
5385 int rc = VINF_SUCCESS;
5386 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_GS_BASE_MSR))
5387 {
5388 uint64_t u64Val = 0;
5389 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GS_BASE, &u64Val); AssertRCReturn(rc, rc);
5390 pMixedCtx->gs.u64Base = u64Val;
5391 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_GS_BASE_MSR;
5392 }
5393 return rc;
5394}
5395
5396
5397/**
5398 * Saves the auto load/store'd guest MSRs from the current VMCS into the
5399 * guest-CPU context. Currently these are LSTAR, STAR, SFMASK, KERNEL-GS BASE
5400 * and TSC_AUX.
5401 *
5402 * @returns VBox status code.
5403 * @param pVCpu Pointer to the VMCPU.
5404 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5405 * out-of-sync. Make sure to update the required fields
5406 * before using them.
5407 *
5408 * @remarks No-long-jump zone!!!
5409 */
5410static int hmR0VmxSaveGuestAutoLoadStoreMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5411{
5412 if (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS)
5413 return VINF_SUCCESS;
5414
5415#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
5416 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cGuestMsrs; i++)
5417 {
5418 PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
5419 pMsr += i;
5420 switch (pMsr->u32Msr)
5421 {
5422 case MSR_K8_LSTAR: pMixedCtx->msrLSTAR = pMsr->u64Value; break;
5423 case MSR_K6_STAR: pMixedCtx->msrSTAR = pMsr->u64Value; break;
5424 case MSR_K8_SF_MASK: pMixedCtx->msrSFMASK = pMsr->u64Value; break;
5425 case MSR_K8_TSC_AUX: CPUMSetGuestMsr(pVCpu, MSR_K8_TSC_AUX, pMsr->u64Value); break;
5426 case MSR_K8_KERNEL_GS_BASE: pMixedCtx->msrKERNELGSBASE = pMsr->u64Value; break;
5427 case MSR_K6_EFER: /* EFER can't be changed without causing a VM-exit. */ break;
5428 default:
5429 {
5430 AssertFailed();
5431 return VERR_HM_UNEXPECTED_LD_ST_MSR;
5432 }
5433 }
5434 }
5435#endif
5436
5437 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS;
5438 return VINF_SUCCESS;
5439}
5440
5441
5442/**
5443 * Saves the guest control registers from the current VMCS into the guest-CPU
5444 * context.
5445 *
5446 * @returns VBox status code.
5447 * @param pVCpu Pointer to the VMCPU.
5448 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5449 * out-of-sync. Make sure to update the required fields
5450 * before using them.
5451 *
5452 * @remarks No-long-jump zone!!!
5453 */
5454static int hmR0VmxSaveGuestControlRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5455{
5456 /* Guest CR0. Guest FPU. */
5457 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
5458 AssertRCReturn(rc, rc);
5459
5460 /* Guest CR4. */
5461 rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
5462 AssertRCReturn(rc, rc);
5463
5464 /* Guest CR2 - updated always during the world-switch or in #PF. */
5465 /* Guest CR3. Only changes with Nested Paging. This must be done -after- saving CR0 and CR4 from the guest! */
5466 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR3))
5467 {
5468 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR0);
5469 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR4);
5470
5471 PVM pVM = pVCpu->CTX_SUFF(pVM);
5472 if ( pVM->hm.s.vmx.fUnrestrictedGuest
5473 || ( pVM->hm.s.fNestedPaging
5474 && CPUMIsGuestPagingEnabledEx(pMixedCtx)))
5475 {
5476 uint64_t u64Val = 0;
5477 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
5478 if (pMixedCtx->cr3 != u64Val)
5479 {
5480 CPUMSetGuestCR3(pVCpu, u64Val);
5481 if (VMMRZCallRing3IsEnabled(pVCpu))
5482 {
5483 PGMUpdateCR3(pVCpu, u64Val);
5484 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
5485 }
5486 else
5487 {
5488 /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMUpdateCR3().*/
5489 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
5490 }
5491 }
5492
5493 /* If the guest is in PAE mode, sync back the PDPE's into the guest state. */
5494 if (CPUMIsGuestInPAEModeEx(pMixedCtx)) /* Reads CR0, CR4 and EFER MSR (EFER is always up-to-date). */
5495 {
5496 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u); AssertRCReturn(rc, rc);
5497 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u); AssertRCReturn(rc, rc);
5498 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u); AssertRCReturn(rc, rc);
5499 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u); AssertRCReturn(rc, rc);
5500
5501 if (VMMRZCallRing3IsEnabled(pVCpu))
5502 {
5503 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
5504 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
5505 }
5506 else
5507 {
5508 /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMGstUpdatePaePdpes(). */
5509 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
5510 }
5511 }
5512 }
5513
5514 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_CR3;
5515 }
5516
5517 /*
5518 * Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> hmR0VmxCallRing3Callback()
5519 * -> VMMRZCallRing3Disable() -> hmR0VmxSaveGuestState() -> Set VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
5520 * -> continue with VM-exit handling -> hmR0VmxSaveGuestControlRegs() and here we are.
5521 *
5522 * The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
5523 */
5524 if (VMMRZCallRing3IsEnabled(pVCpu))
5525 {
5526 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
5527 PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
5528
5529 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
5530 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
5531
5532 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
5533 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
5534 }
5535
5536 return rc;
5537}
5538
5539
5540/**
5541 * Reads a guest segment register from the current VMCS into the guest-CPU
5542 * context.
5543 *
5544 * @returns VBox status code.
5545 * @param pVCpu Pointer to the VMCPU.
5546 * @param idxSel Index of the selector in the VMCS.
5547 * @param idxLimit Index of the segment limit in the VMCS.
5548 * @param idxBase Index of the segment base in the VMCS.
5549 * @param idxAccess Index of the access rights of the segment in the VMCS.
5550 * @param pSelReg Pointer to the segment selector.
5551 *
5552 * @remarks No-long-jump zone!!!
5553 * @remarks Never call this function directly!!! Use the VMXLOCAL_READ_SEG()
5554 * macro as that takes care of whether to read from the VMCS cache or
5555 * not.
5556 */
5557DECLINLINE(int) hmR0VmxReadSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
5558 PCPUMSELREG pSelReg)
5559{
5560 uint32_t u32Val = 0;
5561 int rc = VMXReadVmcs32(idxSel, &u32Val);
5562 AssertRCReturn(rc, rc);
5563 pSelReg->Sel = (uint16_t)u32Val;
5564 pSelReg->ValidSel = (uint16_t)u32Val;
5565 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
5566
5567 rc = VMXReadVmcs32(idxLimit, &u32Val);
5568 AssertRCReturn(rc, rc);
5569 pSelReg->u32Limit = u32Val;
5570
5571 uint64_t u64Val = 0;
5572 rc = VMXReadVmcsGstNByIdxVal(idxBase, &u64Val);
5573 AssertRCReturn(rc, rc);
5574 pSelReg->u64Base = u64Val;
5575
5576 rc = VMXReadVmcs32(idxAccess, &u32Val);
5577 AssertRCReturn(rc, rc);
5578 pSelReg->Attr.u = u32Val;
5579
5580 /*
5581 * If VT-x marks the segment as unusable, most other bits remain undefined:
5582 * - For CS the L, D and G bits have meaning.
5583 * - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
5584 * - For the remaining data segments no bits are defined.
5585 *
5586 * The present bit and the unusable bit has been observed to be set at the
5587 * same time (the selector was supposed to invalid as we started executing
5588 * a V8086 interrupt in ring-0).
5589 *
5590 * What should be important for the rest of the VBox code that the P bit is
5591 * cleared. Some of the other VBox code recognizes the unusable bit, but
5592 * AMD-V certainly don't, and REM doesn't really either. So, to be on the
5593 * safe side here, we'll strip off P and other bits we don't care about. If
5594 * any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
5595 *
5596 * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
5597 */
5598 if (pSelReg->Attr.u & X86DESCATTR_UNUSABLE)
5599 {
5600 Assert(idxSel != VMX_VMCS16_GUEST_FIELD_TR); /* TR is the only selector that can never be unusable. */
5601
5602 /* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
5603 pSelReg->Attr.u &= X86DESCATTR_UNUSABLE | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
5604 | X86DESCATTR_DPL | X86DESCATTR_TYPE | X86DESCATTR_DT;
5605
5606 Log4(("hmR0VmxReadSegmentReg: Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Val, pSelReg->Attr.u));
5607#ifdef DEBUG_bird
5608 AssertMsg((u32Val & ~X86DESCATTR_P) == pSelReg->Attr.u,
5609 ("%#x: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
5610 idxSel, u32Val, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
5611#endif
5612 }
5613 return VINF_SUCCESS;
5614}
5615
5616
5617#ifdef VMX_USE_CACHED_VMCS_ACCESSES
5618# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
5619 hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_##Sel, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
5620 VMX_VMCS_GUEST_##Sel##_BASE_CACHE_IDX, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
5621#else
5622# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
5623 hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_FIELD_##Sel, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
5624 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
5625#endif
5626
5627
5628/**
5629 * Saves the guest segment registers from the current VMCS into the guest-CPU
5630 * context.
5631 *
5632 * @returns VBox status code.
5633 * @param pVCpu Pointer to the VMCPU.
5634 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5635 * out-of-sync. Make sure to update the required fields
5636 * before using them.
5637 *
5638 * @remarks No-long-jump zone!!!
5639 */
5640static int hmR0VmxSaveGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5641{
5642 /* Guest segment registers. */
5643 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_SEGMENT_REGS))
5644 {
5645 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); AssertRCReturn(rc, rc);
5646 rc = VMXLOCAL_READ_SEG(CS, cs); AssertRCReturn(rc, rc);
5647 rc = VMXLOCAL_READ_SEG(SS, ss); AssertRCReturn(rc, rc);
5648 rc = VMXLOCAL_READ_SEG(DS, ds); AssertRCReturn(rc, rc);
5649 rc = VMXLOCAL_READ_SEG(ES, es); AssertRCReturn(rc, rc);
5650 rc = VMXLOCAL_READ_SEG(FS, fs); AssertRCReturn(rc, rc);
5651 rc = VMXLOCAL_READ_SEG(GS, gs); AssertRCReturn(rc, rc);
5652
5653 /* Restore segment attributes for real-on-v86 mode hack. */
5654 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
5655 {
5656 pMixedCtx->cs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrCS.u;
5657 pMixedCtx->ss.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrSS.u;
5658 pMixedCtx->ds.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrDS.u;
5659 pMixedCtx->es.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrES.u;
5660 pMixedCtx->fs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrFS.u;
5661 pMixedCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrGS.u;
5662 }
5663 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_SEGMENT_REGS;
5664 }
5665
5666 return VINF_SUCCESS;
5667}
5668
5669
5670/**
5671 * Saves the guest descriptor table registers and task register from the current
5672 * VMCS into the guest-CPU context.
5673 *
5674 * @returns VBox status code.
5675 * @param pVCpu Pointer to the VMCPU.
5676 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5677 * out-of-sync. Make sure to update the required fields
5678 * before using them.
5679 *
5680 * @remarks No-long-jump zone!!!
5681 */
5682static int hmR0VmxSaveGuestTableRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5683{
5684 int rc = VINF_SUCCESS;
5685
5686 /* Guest LDTR. */
5687 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_LDTR))
5688 {
5689 rc = VMXLOCAL_READ_SEG(LDTR, ldtr);
5690 AssertRCReturn(rc, rc);
5691 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_LDTR;
5692 }
5693
5694 /* Guest GDTR. */
5695 uint64_t u64Val = 0;
5696 uint32_t u32Val = 0;
5697 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_GDTR))
5698 {
5699 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val); AssertRCReturn(rc, rc);
5700 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
5701 pMixedCtx->gdtr.pGdt = u64Val;
5702 pMixedCtx->gdtr.cbGdt = u32Val;
5703 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_GDTR;
5704 }
5705
5706 /* Guest IDTR. */
5707 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_IDTR))
5708 {
5709 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val); AssertRCReturn(rc, rc);
5710 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
5711 pMixedCtx->idtr.pIdt = u64Val;
5712 pMixedCtx->idtr.cbIdt = u32Val;
5713 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_IDTR;
5714 }
5715
5716 /* Guest TR. */
5717 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_TR))
5718 {
5719 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
5720 AssertRCReturn(rc, rc);
5721
5722 /* For real-mode emulation using virtual-8086 mode we have the fake TSS (pRealModeTSS) in TR, don't save the fake one. */
5723 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
5724 {
5725 rc = VMXLOCAL_READ_SEG(TR, tr);
5726 AssertRCReturn(rc, rc);
5727 }
5728 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_TR;
5729 }
5730 return rc;
5731}
5732
5733#undef VMXLOCAL_READ_SEG
5734
5735
5736/**
5737 * Saves the guest debug-register DR7 from the current VMCS into the guest-CPU
5738 * context.
5739 *
5740 * @returns VBox status code.
5741 * @param pVCpu Pointer to the VMCPU.
5742 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5743 * out-of-sync. Make sure to update the required fields
5744 * before using them.
5745 *
5746 * @remarks No-long-jump zone!!!
5747 */
5748static int hmR0VmxSaveGuestDR7(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5749{
5750 if (!(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_DEBUG))
5751 {
5752 if (!CPUMIsHyperDebugStateActive(pVCpu))
5753 {
5754 /* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
5755 uint32_t u32Val;
5756 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val); AssertRCReturn(rc, rc);
5757 pMixedCtx->dr[7] = u32Val;
5758 }
5759
5760 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_DEBUG;
5761 }
5762 return VINF_SUCCESS;
5763}
5764
5765
5766/**
5767 * Saves the guest APIC state from the current VMCS into the guest-CPU context.
5768 *
5769 * @returns VBox status code.
5770 * @param pVCpu Pointer to the VMCPU.
5771 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
5772 * out-of-sync. Make sure to update the required fields
5773 * before using them.
5774 *
5775 * @remarks No-long-jump zone!!!
5776 */
5777static int hmR0VmxSaveGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5778{
5779 /* Updating TPR is already done in hmR0VmxPostRunGuest(). Just update the flag. */
5780 pVCpu->hm.s.vmx.fUpdatedGuestState |= HMVMX_UPDATED_GUEST_APIC_STATE;
5781 return VINF_SUCCESS;
5782}
5783
5784
5785/**
5786 * Saves the entire guest state from the currently active VMCS into the
5787 * guest-CPU context. This essentially VMREADs all guest-data.
5788 *
5789 * @returns VBox status code.
5790 * @param pVCpu Pointer to the VMCPU.
5791 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
5792 * out-of-sync. Make sure to update the required fields
5793 * before using them.
5794 */
5795static int hmR0VmxSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5796{
5797 Assert(pVCpu);
5798 Assert(pMixedCtx);
5799
5800 if (pVCpu->hm.s.vmx.fUpdatedGuestState == HMVMX_UPDATED_GUEST_ALL)
5801 return VINF_SUCCESS;
5802
5803 /* Though we can longjmp to ring-3 due to log-flushes here and get recalled
5804 again on the ring-3 callback path, there is no real need to. */
5805 if (VMMRZCallRing3IsEnabled(pVCpu))
5806 VMMR0LogFlushDisable(pVCpu);
5807 else
5808 Assert(VMMR0IsLogFlushDisabled(pVCpu));
5809 Log4Func(("vcpu[%RU32]\n", pVCpu->idCpu));
5810
5811 int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
5812 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestRipRspRflags failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5813
5814 rc = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
5815 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestControlRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5816
5817 rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
5818 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSegmentRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5819
5820 rc = hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
5821 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestTableRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5822
5823 rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
5824 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestDR7 failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5825
5826 rc = hmR0VmxSaveGuestSysenterMsrs(pVCpu, pMixedCtx);
5827 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSysenterMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5828
5829 rc = hmR0VmxSaveGuestFSBaseMsr(pVCpu, pMixedCtx);
5830 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestFSBaseMsr failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5831
5832 rc = hmR0VmxSaveGuestGSBaseMsr(pVCpu, pMixedCtx);
5833 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestGSBaseMsr failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5834
5835 rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
5836 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestAutoLoadStoreMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5837
5838 rc = hmR0VmxSaveGuestActivityState(pVCpu, pMixedCtx);
5839 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestActivityState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5840
5841 rc = hmR0VmxSaveGuestApicState(pVCpu, pMixedCtx);
5842 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestApicState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
5843
5844 AssertMsg(pVCpu->hm.s.vmx.fUpdatedGuestState == HMVMX_UPDATED_GUEST_ALL,
5845 ("Missed guest state bits while saving state; residue %RX32\n", pVCpu->hm.s.vmx.fUpdatedGuestState));
5846
5847 if (VMMRZCallRing3IsEnabled(pVCpu))
5848 VMMR0LogFlushEnable(pVCpu);
5849
5850 return rc;
5851}
5852
5853
5854/**
5855 * Check per-VM and per-VCPU force flag actions that require us to go back to
5856 * ring-3 for one reason or another.
5857 *
5858 * @returns VBox status code (information status code included).
5859 * @retval VINF_SUCCESS if we don't have any actions that require going back to
5860 * ring-3.
5861 * @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
5862 * @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
5863 * interrupts)
5864 * @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
5865 * all EMTs to be in ring-3.
5866 * @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
5867 * @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
5868 * to the EM loop.
5869 *
5870 * @param pVM Pointer to the VM.
5871 * @param pVCpu Pointer to the VMCPU.
5872 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
5873 * out-of-sync. Make sure to update the required fields
5874 * before using them.
5875 */
5876static int hmR0VmxCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5877{
5878 Assert(VMMRZCallRing3IsEnabled(pVCpu));
5879
5880 if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
5881 ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
5882 || VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
5883 ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
5884 {
5885 /* We need the control registers now, make sure the guest-CPU context is updated. */
5886 int rc3 = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
5887 AssertRCReturn(rc3, rc3);
5888
5889 /* Pending HM CR3 sync. */
5890 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
5891 {
5892 int rc2 = PGMUpdateCR3(pVCpu, pMixedCtx->cr3);
5893 AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
5894 ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
5895 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
5896 }
5897
5898 /* Pending HM PAE PDPEs. */
5899 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
5900 {
5901 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
5902 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
5903 }
5904
5905 /* Pending PGM C3 sync. */
5906 if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
5907 {
5908 int rc2 = PGMSyncCR3(pVCpu, pMixedCtx->cr0, pMixedCtx->cr3, pMixedCtx->cr4,
5909 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
5910 if (rc2 != VINF_SUCCESS)
5911 {
5912 AssertRC(rc2);
5913 Log4(("hmR0VmxCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", rc2));
5914 return rc2;
5915 }
5916 }
5917
5918 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
5919 if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
5920 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
5921 {
5922 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
5923 int rc2 = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
5924 Log4(("hmR0VmxCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc2));
5925 return rc2;
5926 }
5927
5928 /* Pending VM request packets, such as hardware interrupts. */
5929 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
5930 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
5931 {
5932 Log4(("hmR0VmxCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
5933 return VINF_EM_PENDING_REQUEST;
5934 }
5935
5936 /* Pending PGM pool flushes. */
5937 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
5938 {
5939 Log4(("hmR0VmxCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
5940 return VINF_PGM_POOL_FLUSH_PENDING;
5941 }
5942
5943 /* Pending DMA requests. */
5944 if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
5945 {
5946 Log4(("hmR0VmxCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
5947 return VINF_EM_RAW_TO_R3;
5948 }
5949 }
5950
5951 return VINF_SUCCESS;
5952}
5953
5954
5955/**
5956 * Converts any TRPM trap into a pending HM event. This is typically used when
5957 * entering from ring-3 (not longjmp returns).
5958 *
5959 * @param pVCpu Pointer to the VMCPU.
5960 */
5961static void hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu)
5962{
5963 Assert(TRPMHasTrap(pVCpu));
5964 Assert(!pVCpu->hm.s.Event.fPending);
5965
5966 uint8_t uVector;
5967 TRPMEVENT enmTrpmEvent;
5968 RTGCUINT uErrCode;
5969 RTGCUINTPTR GCPtrFaultAddress;
5970 uint8_t cbInstr;
5971
5972 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
5973 AssertRC(rc);
5974
5975 /* Refer Intel spec. 24.8.3 "VM-entry Controls for Event Injection" for the format of u32IntrInfo. */
5976 uint32_t u32IntrInfo = uVector | VMX_EXIT_INTERRUPTION_INFO_VALID;
5977 if (enmTrpmEvent == TRPM_TRAP)
5978 {
5979 switch (uVector)
5980 {
5981 case X86_XCPT_BP:
5982 case X86_XCPT_OF:
5983 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
5984 break;
5985
5986 case X86_XCPT_PF:
5987 case X86_XCPT_DF:
5988 case X86_XCPT_TS:
5989 case X86_XCPT_NP:
5990 case X86_XCPT_SS:
5991 case X86_XCPT_GP:
5992 case X86_XCPT_AC:
5993 u32IntrInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
5994 /* no break! */
5995 default:
5996 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
5997 break;
5998 }
5999 }
6000 else if (enmTrpmEvent == TRPM_HARDWARE_INT)
6001 {
6002 if (uVector == X86_XCPT_NMI)
6003 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6004 else
6005 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6006 }
6007 else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
6008 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6009 else
6010 AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
6011
6012 rc = TRPMResetTrap(pVCpu);
6013 AssertRC(rc);
6014 Log4(("TRPM->HM event: u32IntrInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
6015 u32IntrInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
6016
6017 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, cbInstr, uErrCode, GCPtrFaultAddress);
6018 STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
6019}
6020
6021
6022/**
6023 * Converts any pending HM event into a TRPM trap. Typically used when leaving
6024 * VT-x to execute any instruction.
6025 *
6026 * @param pvCpu Pointer to the VMCPU.
6027 */
6028static void hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu)
6029{
6030 Assert(pVCpu->hm.s.Event.fPending);
6031
6032 uint32_t uVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVCpu->hm.s.Event.u64IntrInfo);
6033 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVCpu->hm.s.Event.u64IntrInfo);
6034 bool fErrorCodeValid = !!VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.u64IntrInfo);
6035 uint32_t uErrorCode = pVCpu->hm.s.Event.u32ErrCode;
6036
6037 /* If a trap was already pending, we did something wrong! */
6038 Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
6039
6040 TRPMEVENT enmTrapType;
6041 switch (uVectorType)
6042 {
6043 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
6044 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
6045 enmTrapType = TRPM_HARDWARE_INT;
6046 break;
6047
6048 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
6049 enmTrapType = TRPM_SOFTWARE_INT;
6050 break;
6051
6052 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
6053 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* #BP and #OF */
6054 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
6055 enmTrapType = TRPM_TRAP;
6056 break;
6057
6058 default:
6059 AssertMsgFailed(("Invalid trap type %#x\n", uVectorType));
6060 enmTrapType = TRPM_32BIT_HACK;
6061 break;
6062 }
6063
6064 Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
6065
6066 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
6067 AssertRC(rc);
6068
6069 if (fErrorCodeValid)
6070 TRPMSetErrorCode(pVCpu, uErrorCode);
6071
6072 if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
6073 && uVector == X86_XCPT_PF)
6074 {
6075 TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
6076 }
6077 else if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
6078 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
6079 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
6080 {
6081 AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
6082 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
6083 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
6084 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
6085 }
6086 pVCpu->hm.s.Event.fPending = false;
6087}
6088
6089
6090/**
6091 * Does the necessary state syncing before returning to ring-3 for any reason
6092 * (longjmp, preemption, voluntary exits to ring-3) from VT-x.
6093 *
6094 * @returns VBox status code.
6095 * @param pVM Pointer to the VM.
6096 * @param pVCpu Pointer to the VMCPU.
6097 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6098 * out-of-sync. Make sure to update the required fields
6099 * before using them.
6100 *
6101 * @remarks No-long-jmp zone!!!
6102 */
6103static int hmR0VmxLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6104{
6105 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
6106 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
6107
6108 RTCPUID idCpu = RTMpCpuId();
6109 Log4Func(("HostCpuId=%u\n", idCpu));
6110
6111 /* Save the guest state if necessary. */
6112 if (pVCpu->hm.s.vmx.fUpdatedGuestState != HMVMX_UPDATED_GUEST_ALL)
6113 {
6114 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
6115 AssertRCReturn(rc, rc);
6116 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState == HMVMX_UPDATED_GUEST_ALL);
6117 }
6118
6119 /* Restore host FPU state if necessary and resync on next R0 reentry .*/
6120 if (CPUMIsGuestFPUStateActive(pVCpu))
6121 {
6122 CPUMR0SaveGuestFPU(pVM, pVCpu, pMixedCtx);
6123 Assert(!CPUMIsGuestFPUStateActive(pVCpu));
6124 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
6125 }
6126
6127 /* Restore host debug registers if necessary and resync on next R0 reentry. */
6128#ifdef VBOX_STRICT
6129 if (CPUMIsHyperDebugStateActive(pVCpu))
6130 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
6131#endif
6132 if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */))
6133 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
6134 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
6135 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
6136
6137 /* Restore host-state bits that VT-x only restores partially. */
6138 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
6139 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
6140 {
6141 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags, idCpu));
6142 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
6143 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
6144 }
6145
6146 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
6147 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
6148 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
6149 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
6150 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
6151 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
6152 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
6153 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
6154
6155 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
6156
6157 /** @todo This kinda defeats the purpose of having preemption hooks.
6158 * The problem is, deregistering the hooks should be moved to a place that
6159 * lasts until the EMT is about to be destroyed not everytime while leaving HM
6160 * context.
6161 */
6162 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
6163 {
6164 int rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
6165 AssertRCReturn(rc, rc);
6166
6167 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
6168 Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
6169 }
6170 Assert(!(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED));
6171 NOREF(idCpu);
6172
6173 return VINF_SUCCESS;
6174}
6175
6176
6177/**
6178 * Leaves the VT-x session.
6179 *
6180 * @returns VBox status code.
6181 * @param pVM Pointer to the VM.
6182 * @param pVCpu Pointer to the VMCPU.
6183 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6184 * out-of-sync. Make sure to update the required fields
6185 * before using them.
6186 *
6187 * @remarks No-long-jmp zone!!!
6188 */
6189DECLINLINE(int) hmR0VmxLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6190{
6191 HM_DISABLE_PREEMPT_IF_NEEDED();
6192 HMVMX_ASSERT_CPU_SAFE();
6193 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
6194 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
6195
6196 /* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
6197 and done this from the VMXR0ThreadCtxCallback(). */
6198 if (!pVCpu->hm.s.fLeaveDone)
6199 {
6200 int rc2 = hmR0VmxLeave(pVM, pVCpu, pMixedCtx);
6201 AssertRCReturn(rc2, rc2);
6202 pVCpu->hm.s.fLeaveDone = true;
6203 }
6204
6205 /* Deregister hook now that we've left HM context before re-enabling preemption. */
6206 /** @todo This is bad. Deregistering here means we need to VMCLEAR always
6207 * (longjmp/exit-to-r3) in VT-x which is not efficient. */
6208 if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
6209 VMMR0ThreadCtxHooksDeregister(pVCpu);
6210
6211 /* Leave HM context. This takes care of local init (term). */
6212 int rc = HMR0LeaveCpu(pVCpu);
6213
6214 HM_RESTORE_PREEMPT_IF_NEEDED();
6215
6216 return rc;
6217}
6218
6219
6220/**
6221 * Does the necessary state syncing before doing a longjmp to ring-3.
6222 *
6223 * @returns VBox status code.
6224 * @param pVM Pointer to the VM.
6225 * @param pVCpu Pointer to the VMCPU.
6226 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6227 * out-of-sync. Make sure to update the required fields
6228 * before using them.
6229 *
6230 * @remarks No-long-jmp zone!!!
6231 */
6232DECLINLINE(int) hmR0VmxLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6233{
6234 return hmR0VmxLeaveSession(pVM, pVCpu, pMixedCtx);
6235}
6236
6237
6238/**
6239 * Take necessary actions before going back to ring-3.
6240 *
6241 * An action requires us to go back to ring-3. This function does the necessary
6242 * steps before we can safely return to ring-3. This is not the same as longjmps
6243 * to ring-3, this is voluntary and prepares the guest so it may continue
6244 * executing outside HM (recompiler/IEM).
6245 *
6246 * @returns VBox status code.
6247 * @param pVM Pointer to the VM.
6248 * @param pVCpu Pointer to the VMCPU.
6249 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6250 * out-of-sync. Make sure to update the required fields
6251 * before using them.
6252 * @param rcExit The reason for exiting to ring-3. Can be
6253 * VINF_VMM_UNKNOWN_RING3_CALL.
6254 */
6255static int hmR0VmxExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, int rcExit)
6256{
6257 Assert(pVM);
6258 Assert(pVCpu);
6259 Assert(pMixedCtx);
6260 HMVMX_ASSERT_PREEMPT_SAFE();
6261
6262 if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_GUEST_STATE))
6263 {
6264 /* We've done what is required in hmR0VmxExitErrInvalidGuestState(). We're not going to continue guest execution... */
6265 return VINF_SUCCESS;
6266 }
6267 else if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
6268 {
6269 VMXGetActivatedVmcs(&pVCpu->hm.s.vmx.LastError.u64VMCSPhys);
6270 pVCpu->hm.s.vmx.LastError.u32VMCSRevision = *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs;
6271 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
6272 /* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
6273 return VINF_SUCCESS;
6274 }
6275
6276 /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
6277 VMMRZCallRing3Disable(pVCpu);
6278 Log4(("hmR0VmxExitToRing3: pVCpu=%p idCpu=%RU32 rcExit=%d\n", pVCpu, pVCpu->idCpu, rcExit));
6279
6280 /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
6281 if (pVCpu->hm.s.Event.fPending)
6282 {
6283 hmR0VmxPendingEventToTrpmTrap(pVCpu);
6284 Assert(!pVCpu->hm.s.Event.fPending);
6285 }
6286
6287 /* Save guest state and restore host state bits. */
6288 int rc = hmR0VmxLeaveSession(pVM, pVCpu, pMixedCtx);
6289 STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
6290
6291 /* Sync recompiler state. */
6292 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
6293 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
6294 | CPUM_CHANGED_LDTR
6295 | CPUM_CHANGED_GDTR
6296 | CPUM_CHANGED_IDTR
6297 | CPUM_CHANGED_TR
6298 | CPUM_CHANGED_HIDDEN_SEL_REGS);
6299 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_CR0);
6300 if ( pVM->hm.s.fNestedPaging
6301 && CPUMIsGuestPagingEnabledEx(pMixedCtx))
6302 {
6303 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
6304 }
6305
6306 /*
6307 * Clear the X86_EFL_TF if necessary.
6308 */
6309 if (pVCpu->hm.s.fClearTrapFlag)
6310 {
6311 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS);
6312 pMixedCtx->eflags.Bits.u1TF = 0;
6313 pVCpu->hm.s.fClearTrapFlag = false;
6314 }
6315 /** @todo there seems to be issues with the resume flag when the monitor trap
6316 * flag is pending without being used. Seen early in bios init when
6317 * accessing APIC page in prot mode. */
6318
6319 /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
6320 if (rcExit != VINF_EM_RAW_INTERRUPT)
6321 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
6322
6323 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
6324
6325 /* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
6326 VMMRZCallRing3RemoveNotification(pVCpu);
6327 VMMRZCallRing3Enable(pVCpu);
6328
6329 return rc;
6330}
6331
6332
6333/**
6334 * VMMRZCallRing3() callback wrapper which saves the guest state before we
6335 * longjump to ring-3 and possibly get preempted.
6336 *
6337 * @returns VBox status code.
6338 * @param pVCpu Pointer to the VMCPU.
6339 * @param enmOperation The operation causing the ring-3 longjump.
6340 * @param pvUser Opaque pointer to the guest-CPU context. The data
6341 * may be out-of-sync. Make sure to update the required
6342 * fields before using them.
6343 *
6344 * @remarks Must never be called with @a enmOperation ==
6345 * VMMCALLRING3_VM_R0_ASSERTION. We can't assert it here because if it
6346 * it -does- get called with VMMCALLRING3_VM_R0_ASSERTION, we'll end up
6347 * with an infinite recursion.
6348 */
6349DECLCALLBACK(int) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
6350{
6351 /* VMMRZCallRing3() already makes sure we never get called as a result of an longjmp due to an assertion. */
6352 Assert(pVCpu);
6353 Assert(pvUser);
6354 Assert(VMMRZCallRing3IsEnabled(pVCpu));
6355 HMVMX_ASSERT_PREEMPT_SAFE();
6356
6357 VMMRZCallRing3Disable(pVCpu);
6358 Assert(VMMR0IsLogFlushDisabled(pVCpu));
6359
6360 Log4(("hmR0VmxCallRing3Callback->hmR0VmxLongJmpToRing3 pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
6361 int rc = hmR0VmxLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
6362 AssertRCReturn(rc, rc);
6363
6364 VMMRZCallRing3Enable(pVCpu);
6365 return VINF_SUCCESS;
6366}
6367
6368
6369/**
6370 * Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
6371 * cause a VM-exit as soon as the guest is in a state to receive interrupts.
6372 *
6373 * @param pVCpu Pointer to the VMCPU.
6374 */
6375DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
6376{
6377 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
6378 {
6379 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
6380 {
6381 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
6382 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
6383 AssertRC(rc);
6384 }
6385 } /* else we will deliver interrupts whenever the guest exits next and is in a state to receive events. */
6386}
6387
6388
6389/**
6390 * Evaluates the event to be delivered to the guest and sets it as the pending
6391 * event.
6392 *
6393 * @param pVCpu Pointer to the VMCPU.
6394 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6395 * out-of-sync. Make sure to update the required fields
6396 * before using them.
6397 */
6398static void hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6399{
6400 Assert(!pVCpu->hm.s.Event.fPending);
6401
6402 /* Get the current interruptibility-state of the guest and then figure out what can be injected. */
6403 uint32_t uIntrState = hmR0VmxGetGuestIntrState(pVCpu, pMixedCtx);
6404 bool fBlockMovSS = !!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
6405 bool fBlockSti = !!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
6406
6407 Assert(!fBlockSti || (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS));
6408 Assert( !(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI) /* We don't support block-by-NMI and SMI yet.*/
6409 && !(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI));
6410 Assert(!fBlockSti || pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
6411 Assert(!TRPMHasTrap(pVCpu));
6412
6413 /** @todo SMI. SMIs take priority over NMIs. */
6414 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
6415 {
6416 /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
6417 if ( !fBlockMovSS
6418 && !fBlockSti)
6419 {
6420 /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
6421 Log4(("Pending NMI vcpu[%RU32]\n", pVCpu->idCpu));
6422 uint32_t u32IntrInfo = X86_XCPT_NMI | VMX_EXIT_INTERRUPTION_INFO_VALID;
6423 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6424
6425 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddres */);
6426 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
6427 }
6428 else
6429 hmR0VmxSetIntWindowExitVmcs(pVCpu);
6430 }
6431 else if ( VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
6432 && !pVCpu->hm.s.fSingleInstruction)
6433 {
6434 /*
6435 * Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
6436 * the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
6437 * evaluated here and not set as pending, solely based on the force-flags.
6438 */
6439 int rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
6440 AssertRC(rc);
6441 const bool fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
6442 if ( !fBlockInt
6443 && !fBlockSti
6444 && !fBlockMovSS)
6445 {
6446 uint8_t u8Interrupt;
6447 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
6448 if (RT_SUCCESS(rc))
6449 {
6450 Log4(("Pending interrupt vcpu[%RU32] u8Interrupt=%#x \n", pVCpu->idCpu, u8Interrupt));
6451 uint32_t u32IntrInfo = u8Interrupt | VMX_EXIT_INTERRUPTION_INFO_VALID;
6452 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6453
6454 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrfaultAddress */);
6455 }
6456 else
6457 {
6458 /** @todo Does this actually happen? If not turn it into an assertion. */
6459 Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)));
6460 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
6461 }
6462 }
6463 else
6464 hmR0VmxSetIntWindowExitVmcs(pVCpu);
6465 }
6466}
6467
6468
6469/**
6470 * Injects any pending events into the guest if the guest is in a state to
6471 * receive them.
6472 *
6473 * @returns VBox status code (informational status codes included).
6474 * @param pVCpu Pointer to the VMCPU.
6475 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6476 * out-of-sync. Make sure to update the required fields
6477 * before using them.
6478 */
6479static int hmR0VmxInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6480{
6481 HMVMX_ASSERT_PREEMPT_SAFE();
6482 Assert(VMMRZCallRing3IsEnabled(pVCpu));
6483
6484 /* Get the current interruptibility-state of the guest and then figure out what can be injected. */
6485 uint32_t uIntrState = hmR0VmxGetGuestIntrState(pVCpu, pMixedCtx);
6486 bool fBlockMovSS = !!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
6487 bool fBlockSti = !!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
6488
6489 Assert(!fBlockSti || (pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS));
6490 Assert( !(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI) /* We don't support block-by-NMI and SMI yet.*/
6491 && !(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI));
6492 Assert(!fBlockSti || pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
6493 Assert(!TRPMHasTrap(pVCpu));
6494
6495 int rc = VINF_SUCCESS;
6496 if (pVCpu->hm.s.Event.fPending)
6497 {
6498#if defined(VBOX_STRICT) || defined(VBOX_WITH_STATISTICS)
6499 uint32_t uIntrType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.u64IntrInfo);
6500 if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
6501 {
6502 rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
6503 AssertRCReturn(rc, rc);
6504 const bool fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
6505 Assert(!fBlockInt);
6506 Assert(!fBlockSti);
6507 Assert(!fBlockMovSS);
6508 }
6509 else if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
6510 {
6511 Assert(!fBlockSti);
6512 Assert(!fBlockMovSS);
6513 }
6514#endif
6515 Log4(("Injecting pending event vcpu[%RU32] u64IntrInfo=%#RX64\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntrInfo));
6516 rc = hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.cbInstr,
6517 pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress, &uIntrState);
6518 AssertRCReturn(rc, rc);
6519
6520 /* Update the interruptibility-state as it could have been changed by
6521 hmR0VmxInjectEventVmcs() (e.g. real-on-v86 guest injecting software interrupts) */
6522 fBlockMovSS = !!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
6523 fBlockSti = !!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
6524
6525#ifdef VBOX_WITH_STATISTICS
6526 if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
6527 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
6528 else
6529 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
6530#endif
6531 }
6532
6533 /* Delivery pending debug exception if the guest is single-stepping. Evaluate and set the BS bit. */
6534 int rc2 = VINF_SUCCESS;
6535 if ( fBlockSti
6536 || fBlockMovSS)
6537 {
6538 if (!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu))
6539 {
6540 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RFLAGS);
6541 if (pMixedCtx->eflags.Bits.u1TF) /* We don't have any IA32_DEBUGCTL MSR for guests. Treat as all bits 0. */
6542 {
6543 /*
6544 * The pending-debug exceptions field is cleared on all VM-exits except VMX_EXIT_TPR_BELOW_THRESHOLD,
6545 * VMX_EXIT_MTF, VMX_EXIT_APIC_WRITE and VMX_EXIT_VIRTUALIZED_EOI.
6546 * See Intel spec. 27.3.4 "Saving Non-Register State".
6547 */
6548 rc2 = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS);
6549 AssertRCReturn(rc, rc);
6550 }
6551 }
6552 else
6553 {
6554 /* We are single-stepping in the hypervisor debugger, clear interrupt inhibition as setting the BS bit would mean
6555 delivering a #DB to the guest upon VM-entry when it shouldn't be. */
6556 uIntrState = 0;
6557 }
6558 }
6559
6560 /*
6561 * There's no need to clear the VM entry-interruption information field here if we're not injecting anything.
6562 * VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
6563 */
6564 rc2 = hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
6565 AssertRC(rc2);
6566
6567 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RESET);
6568 return rc;
6569}
6570
6571
6572/**
6573 * Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
6574 *
6575 * @param pVCpu Pointer to the VMCPU.
6576 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6577 * out-of-sync. Make sure to update the required fields
6578 * before using them.
6579 */
6580DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6581{
6582 uint32_t u32IntrInfo = X86_XCPT_UD | VMX_EXIT_INTERRUPTION_INFO_VALID;
6583 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
6584}
6585
6586
6587/**
6588 * Injects a double-fault (#DF) exception into the VM.
6589 *
6590 * @returns VBox status code (informational status code included).
6591 * @param pVCpu Pointer to the VMCPU.
6592 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6593 * out-of-sync. Make sure to update the required fields
6594 * before using them.
6595 */
6596DECLINLINE(int) hmR0VmxInjectXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t *puIntrState)
6597{
6598 uint32_t u32IntrInfo = X86_XCPT_DF | VMX_EXIT_INTERRUPTION_INFO_VALID;
6599 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6600 u32IntrInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
6601 return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntrInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */,
6602 puIntrState);
6603}
6604
6605
6606/**
6607 * Sets a debug (#DB) exception as pending-for-injection into the VM.
6608 *
6609 * @param pVCpu Pointer to the VMCPU.
6610 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6611 * out-of-sync. Make sure to update the required fields
6612 * before using them.
6613 */
6614DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6615{
6616 uint32_t u32IntrInfo = X86_XCPT_DB | VMX_EXIT_INTERRUPTION_INFO_VALID;
6617 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6618 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
6619}
6620
6621
6622/**
6623 * Sets an overflow (#OF) exception as pending-for-injection into the VM.
6624 *
6625 * @param pVCpu Pointer to the VMCPU.
6626 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6627 * out-of-sync. Make sure to update the required fields
6628 * before using them.
6629 * @param cbInstr The value of RIP that is to be pushed on the guest
6630 * stack.
6631 */
6632DECLINLINE(void) hmR0VmxSetPendingXcptOF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr)
6633{
6634 uint32_t u32IntrInfo = X86_XCPT_OF | VMX_EXIT_INTERRUPTION_INFO_VALID;
6635 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6636 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
6637}
6638
6639
6640/**
6641 * Injects a general-protection (#GP) fault into the VM.
6642 *
6643 * @returns VBox status code (informational status code included).
6644 * @param pVCpu Pointer to the VMCPU.
6645 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6646 * out-of-sync. Make sure to update the required fields
6647 * before using them.
6648 * @param u32ErrorCode The error code associated with the #GP.
6649 */
6650DECLINLINE(int) hmR0VmxInjectXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fErrorCodeValid, uint32_t u32ErrorCode,
6651 uint32_t *puIntrState)
6652{
6653 uint32_t u32IntrInfo = X86_XCPT_GP | VMX_EXIT_INTERRUPTION_INFO_VALID;
6654 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6655 if (fErrorCodeValid)
6656 u32IntrInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
6657 return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntrInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */,
6658 puIntrState);
6659}
6660
6661
6662/**
6663 * Sets a software interrupt (INTn) as pending-for-injection into the VM.
6664 *
6665 * @param pVCpu Pointer to the VMCPU.
6666 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6667 * out-of-sync. Make sure to update the required fields
6668 * before using them.
6669 * @param uVector The software interrupt vector number.
6670 * @param cbInstr The value of RIP that is to be pushed on the guest
6671 * stack.
6672 */
6673DECLINLINE(void) hmR0VmxSetPendingIntN(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint16_t uVector, uint32_t cbInstr)
6674{
6675 uint32_t u32IntrInfo = uVector | VMX_EXIT_INTERRUPTION_INFO_VALID;
6676 if ( uVector == X86_XCPT_BP
6677 || uVector == X86_XCPT_OF)
6678 {
6679 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6680 }
6681 else
6682 u32IntrInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
6683 hmR0VmxSetPendingEvent(pVCpu, u32IntrInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
6684}
6685
6686
6687/**
6688 * Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
6689 * stack.
6690 *
6691 * @returns VBox status code (information status code included).
6692 * @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
6693 * @param pVM Pointer to the VM.
6694 * @param pMixedCtx Pointer to the guest-CPU context.
6695 * @param uValue The value to push to the guest stack.
6696 */
6697DECLINLINE(int) hmR0VmxRealModeGuestStackPush(PVM pVM, PCPUMCTX pMixedCtx, uint16_t uValue)
6698{
6699 /*
6700 * The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
6701 * virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
6702 * See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
6703 */
6704 if (pMixedCtx->sp == 1)
6705 return VINF_EM_RESET;
6706 pMixedCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
6707 int rc = PGMPhysSimpleWriteGCPhys(pVM, pMixedCtx->ss.u64Base + pMixedCtx->sp, &uValue, sizeof(uint16_t));
6708 AssertRCReturn(rc, rc);
6709 return rc;
6710}
6711
6712
6713/**
6714 * Injects an event into the guest upon VM-entry by updating the relevant fields
6715 * in the VM-entry area in the VMCS.
6716 *
6717 * @returns VBox status code (informational error codes included).
6718 * @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
6719 * @retval VINF_EM_RESET if event injection resulted in a triple-fault.
6720 *
6721 * @param pVCpu Pointer to the VMCPU.
6722 * @param pMixedCtx Pointer to the guest-CPU context. The data may
6723 * be out-of-sync. Make sure to update the required
6724 * fields before using them.
6725 * @param u64IntrInfo The VM-entry interruption-information field.
6726 * @param cbInstr The VM-entry instruction length in bytes (for
6727 * software interrupts, exceptions and privileged
6728 * software exceptions).
6729 * @param u32ErrCode The VM-entry exception error code.
6730 * @param GCPtrFaultAddress The page-fault address for #PF exceptions.
6731 * @param puIntrState Pointer to the current guest interruptibility-state.
6732 * This interruptibility-state will be updated if
6733 * necessary. This cannot not be NULL.
6734 *
6735 * @remarks Requires CR0!
6736 * @remarks No-long-jump zone!!!
6737 */
6738static int hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntrInfo, uint32_t cbInstr,
6739 uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress, uint32_t *puIntrState)
6740{
6741 /* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
6742 AssertMsg(u64IntrInfo >> 32 == 0, ("%#RX64\n", u64IntrInfo));
6743 Assert(puIntrState);
6744 uint32_t u32IntrInfo = (uint32_t)u64IntrInfo;
6745
6746 const uint32_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(u32IntrInfo);
6747 const uint32_t uIntrType = VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntrInfo);
6748
6749#ifdef VBOX_STRICT
6750 /* Validate the error-code-valid bit for hardware exceptions. */
6751 if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT)
6752 {
6753 switch (uVector)
6754 {
6755 case X86_XCPT_PF:
6756 case X86_XCPT_DF:
6757 case X86_XCPT_TS:
6758 case X86_XCPT_NP:
6759 case X86_XCPT_SS:
6760 case X86_XCPT_GP:
6761 case X86_XCPT_AC:
6762 AssertMsg(VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntrInfo),
6763 ("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
6764 /* fallthru */
6765 default:
6766 break;
6767 }
6768 }
6769#endif
6770
6771 /* Cannot inject an NMI when block-by-MOV SS is in effect. */
6772 Assert( uIntrType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
6773 || !(*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS));
6774
6775 STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
6776
6777 /* We require CR0 to check if the guest is in real-mode. */
6778 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6779 AssertRCReturn(rc, rc);
6780
6781 /*
6782 * Hardware interrupts & exceptions cannot be delivered through the software interrupt redirection bitmap to the real
6783 * mode task in virtual-8086 mode. We must jump to the interrupt handler in the (real-mode) guest.
6784 * See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode" for interrupt & exception classes.
6785 * See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
6786 */
6787 if (CPUMIsGuestInRealModeEx(pMixedCtx))
6788 {
6789 PVM pVM = pVCpu->CTX_SUFF(pVM);
6790 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
6791 {
6792 Assert(PDMVmmDevHeapIsEnabled(pVM));
6793 Assert(pVM->hm.s.vmx.pRealModeTSS);
6794
6795 /* We require RIP, RSP, RFLAGS, CS, IDTR. Save the required ones from the VMCS. */
6796 rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
6797 rc |= hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
6798 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
6799 AssertRCReturn(rc, rc);
6800 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState & HMVMX_UPDATED_GUEST_RIP);
6801
6802 /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
6803 const size_t cbIdtEntry = sizeof(X86IDTR16);
6804 if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pMixedCtx->idtr.cbIdt)
6805 {
6806 /* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
6807 if (uVector == X86_XCPT_DF)
6808 return VINF_EM_RESET;
6809 else if (uVector == X86_XCPT_GP)
6810 {
6811 /* If we're injecting a #GP with no valid IDT entry, inject a double-fault. */
6812 return hmR0VmxInjectXcptDF(pVCpu, pMixedCtx, puIntrState);
6813 }
6814
6815 /* If we're injecting an interrupt/exception with no valid IDT entry, inject a general-protection fault. */
6816 /* No error codes for exceptions in real-mode. See Intel spec. 20.1.4 "Interrupt and Exception Handling" */
6817 return hmR0VmxInjectXcptGP(pVCpu, pMixedCtx, false /* fErrCodeValid */, 0 /* u32ErrCode */, puIntrState);
6818 }
6819
6820 /* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
6821 uint16_t uGuestIp = pMixedCtx->ip;
6822 if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT)
6823 {
6824 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
6825 /* #BP and #OF are both benign traps, we need to resume the next instruction. */
6826 uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
6827 }
6828 else if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT)
6829 uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
6830
6831 /* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
6832 X86IDTR16 IdtEntry;
6833 RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pMixedCtx->idtr.pIdt + uVector * cbIdtEntry;
6834 rc = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
6835 AssertRCReturn(rc, rc);
6836
6837 /* Construct the stack frame for the interrupt/exception handler. */
6838 rc = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->eflags.u32);
6839 rc |= hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->cs.Sel);
6840 rc |= hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, uGuestIp);
6841 AssertRCReturn(rc, rc);
6842
6843 /* Clear the required eflag bits and jump to the interrupt/exception handler. */
6844 if (rc == VINF_SUCCESS)
6845 {
6846 pMixedCtx->eflags.u32 &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
6847 pMixedCtx->rip = IdtEntry.offSel;
6848 pMixedCtx->cs.Sel = IdtEntry.uSel;
6849 pMixedCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
6850 if ( uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
6851 && uVector == X86_XCPT_PF)
6852 {
6853 pMixedCtx->cr2 = GCPtrFaultAddress;
6854 }
6855
6856 /* If any other guest-state bits are changed here, make sure to update
6857 hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
6858 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SEGMENT_REGS
6859 | HM_CHANGED_GUEST_RIP
6860 | HM_CHANGED_GUEST_RFLAGS
6861 | HM_CHANGED_GUEST_RSP;
6862
6863 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
6864 if (*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
6865 {
6866 Assert( uIntrType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
6867 && uIntrType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
6868 Log4(("Clearing inhibition due to STI.\n"));
6869 *puIntrState &= ~VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
6870 }
6871 Log4(("Injecting real-mode: u32IntrInfo=%#x u32ErrCode=%#x instrlen=%#x\n", u32IntrInfo, u32ErrCode, cbInstr));
6872
6873 /* The event has been truly dispatched. Mark it as no longer pending so we don't attempt to 'undo'
6874 it, if we are returning to ring-3 before executing guest code. */
6875 pVCpu->hm.s.Event.fPending = false;
6876 }
6877 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RESET);
6878 return rc;
6879 }
6880 else
6881 {
6882 /*
6883 * For unrestricted execution enabled CPUs running real-mode guests, we must not set the deliver-error-code bit.
6884 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
6885 */
6886 u32IntrInfo &= ~VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
6887 }
6888 }
6889
6890 /* Validate. */
6891 Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(u32IntrInfo)); /* Bit 31 (Valid bit) must be set by caller. */
6892 Assert(!VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK(u32IntrInfo)); /* Bit 12 MBZ. */
6893 Assert(!(u32IntrInfo & 0x7ffff000)); /* Bits 30:12 MBZ. */
6894
6895 /* Inject. */
6896 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntrInfo);
6897 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntrInfo))
6898 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
6899 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
6900
6901 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntrInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
6902 && uVector == X86_XCPT_PF)
6903 {
6904 pMixedCtx->cr2 = GCPtrFaultAddress;
6905 }
6906
6907 Log4(("Injecting vcpu[%RU32] u32IntrInfo=%#x u32ErrCode=%#x cbInstr=%#x pMixedCtx->uCR2=%#RX64\n", pVCpu->idCpu,
6908 u32IntrInfo, u32ErrCode, cbInstr, pMixedCtx->cr2));
6909
6910 AssertRCReturn(rc, rc);
6911 return rc;
6912}
6913
6914
6915/**
6916 * Clears the current event in the VMCS.
6917 *
6918 * @returns VBox status code.
6919 * @param pVCpu Pointer to the VMCPU.
6920 *
6921 * @remarks Use this function only to clear events that have not yet been
6922 * delivered to the guest but are injected in the VMCS!
6923 * @remarks No-long-jump zone!!!
6924 */
6925static void hmR0VmxClearEventVmcs(PVMCPU pVCpu)
6926{
6927 if (!pVCpu->hm.s.Event.fPending)
6928 return;
6929
6930#ifdef VBOX_STRICT
6931 uint32_t u32EntryInfo;
6932 int rc2 = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
6933 AssertRC(rc2);
6934 Assert(VMX_ENTRY_INTERRUPTION_INFO_VALID(u32EntryInfo));
6935#endif
6936
6937 /* Clear the entry-interruption field (including the valid bit). */
6938 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0);
6939 AssertRC(rc);
6940
6941 /* Clear the pending debug exception field. */
6942 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
6943 AssertRC(rc);
6944}
6945
6946
6947/**
6948 * Enters the VT-x session.
6949 *
6950 * @returns VBox status code.
6951 * @param pVM Pointer to the VM.
6952 * @param pVCpu Pointer to the VMCPU.
6953 * @param pCpu Pointer to the CPU info struct.
6954 */
6955VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
6956{
6957 AssertPtr(pVM);
6958 AssertPtr(pVCpu);
6959 Assert(pVM->hm.s.vmx.fSupported);
6960 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
6961 NOREF(pCpu);
6962
6963 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
6964 Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
6965
6966#ifdef VBOX_STRICT
6967 /* Make sure we're in VMX root mode. */
6968 RTCCUINTREG u32HostCR4 = ASMGetCR4();
6969 if (!(u32HostCR4 & X86_CR4_VMXE))
6970 {
6971 LogRel(("VMXR0Enter: X86_CR4_VMXE bit in CR4 is not set!\n"));
6972 return VERR_VMX_X86_CR4_VMXE_CLEARED;
6973 }
6974#endif
6975
6976 /*
6977 * Load the VCPU's VMCS as the current (and active) one.
6978 */
6979 Assert(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR);
6980 int rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
6981 if (RT_FAILURE(rc))
6982 return rc;
6983
6984 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
6985 pVCpu->hm.s.fLeaveDone = false;
6986 Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
6987
6988 return VINF_SUCCESS;
6989}
6990
6991
6992/**
6993 * The thread-context callback (only on platforms which support it).
6994 *
6995 * @param enmEvent The thread-context event.
6996 * @param pVCpu Pointer to the VMCPU.
6997 * @param fGlobalInit Whether global VT-x/AMD-V init. was used.
6998 * @thread EMT.
6999 */
7000VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
7001{
7002 switch (enmEvent)
7003 {
7004 case RTTHREADCTXEVENT_PREEMPTING:
7005 {
7006 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7007 Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
7008 VMCPU_ASSERT_EMT(pVCpu);
7009
7010 PVM pVM = pVCpu->CTX_SUFF(pVM);
7011 PCPUMCTX pMixedCtx = CPUMQueryGuestCtxPtr(pVCpu);
7012
7013 /* No longjmps (logger flushes, locks) in this fragile context. */
7014 VMMRZCallRing3Disable(pVCpu);
7015 Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
7016
7017 /* Save the guest-state, restore host-state (FPU, debug etc.). */
7018 if (!pVCpu->hm.s.fLeaveDone)
7019 {
7020 hmR0VmxLeave(pVM, pVCpu, pMixedCtx);
7021 pVCpu->hm.s.fLeaveDone = true;
7022 }
7023
7024 /* Leave HM context, takes care of local init (term). */
7025 int rc = HMR0LeaveCpu(pVCpu);
7026 AssertRC(rc); NOREF(rc);
7027
7028 /* Restore longjmp state. */
7029 VMMRZCallRing3Enable(pVCpu);
7030 STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptPreempting);
7031 break;
7032 }
7033
7034 case RTTHREADCTXEVENT_RESUMED:
7035 {
7036 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7037 Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
7038 VMCPU_ASSERT_EMT(pVCpu);
7039
7040 /* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
7041 VMMRZCallRing3Disable(pVCpu);
7042 Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
7043
7044 /* Initialize the bare minimum state required for HM. This takes care of
7045 initializing VT-x if necessary (onlined CPUs, local init etc.) */
7046 int rc = HMR0EnterCpu(pVCpu);
7047 AssertRC(rc);
7048 Assert(pVCpu->hm.s.fContextUseFlags & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
7049
7050 /* Load the active VMCS as the current one. */
7051 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR)
7052 {
7053 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7054 AssertRC(rc); NOREF(rc);
7055 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
7056 Log4Func(("Resumed: Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
7057 }
7058 pVCpu->hm.s.fLeaveDone = false;
7059
7060 /* Restore longjmp state. */
7061 VMMRZCallRing3Enable(pVCpu);
7062 break;
7063 }
7064
7065 default:
7066 break;
7067 }
7068}
7069
7070
7071/**
7072 * Saves the host state in the VMCS host-state.
7073 * Sets up the VM-exit MSR-load area.
7074 *
7075 * The CPU state will be loaded from these fields on every successful VM-exit.
7076 *
7077 * @returns VBox status code.
7078 * @param pVM Pointer to the VM.
7079 * @param pVCpu Pointer to the VMCPU.
7080 *
7081 * @remarks No-long-jump zone!!!
7082 */
7083static int hmR0VmxSaveHostState(PVM pVM, PVMCPU pVCpu)
7084{
7085 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7086
7087 if (!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT))
7088 return VINF_SUCCESS;
7089
7090 int rc = hmR0VmxSaveHostControlRegs(pVM, pVCpu);
7091 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostControlRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7092
7093 rc = hmR0VmxSaveHostSegmentRegs(pVM, pVCpu);
7094 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostSegmentRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7095
7096 rc = hmR0VmxSaveHostMsrs(pVM, pVCpu);
7097 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostMsrs failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7098
7099 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_HOST_CONTEXT;
7100 return rc;
7101}
7102
7103
7104/**
7105 * Saves the host state in the VMCS host-state.
7106 *
7107 * @returns VBox status code.
7108 * @param pVM Pointer to the VM.
7109 * @param pVCpu Pointer to the VMCPU.
7110 *
7111 * @remarks No-long-jump zone!!!
7112 */
7113VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
7114{
7115 AssertPtr(pVM);
7116 AssertPtr(pVCpu);
7117
7118 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
7119
7120 /* Save the host state here while entering HM context. When thread-context hooks are used, we might get preempted
7121 and have to resave the host state but most of the time we won't be, so do it here before we disable interrupts. */
7122 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7123 return hmR0VmxSaveHostState(pVM, pVCpu);
7124}
7125
7126
7127/**
7128 * Loads the guest state into the VMCS guest-state area. The CPU state will be
7129 * loaded from these fields on every successful VM-entry.
7130 *
7131 * Sets up the VM-entry MSR-load and VM-exit MSR-store areas.
7132 * Sets up the VM-entry controls.
7133 * Sets up the appropriate VMX non-root function to execute guest code based on
7134 * the guest CPU mode.
7135 *
7136 * @returns VBox status code.
7137 * @param pVM Pointer to the VM.
7138 * @param pVCpu Pointer to the VMCPU.
7139 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7140 * out-of-sync. Make sure to update the required fields
7141 * before using them.
7142 *
7143 * @remarks No-long-jump zone!!!
7144 */
7145static int hmR0VmxLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7146{
7147 AssertPtr(pVM);
7148 AssertPtr(pVCpu);
7149 AssertPtr(pMixedCtx);
7150 HMVMX_ASSERT_PREEMPT_SAFE();
7151
7152#ifdef LOG_ENABLED
7153 /** @todo r=ramshankar: I'm not able to use VMMRZCallRing3Disable() here,
7154 * probably not initialized yet? Anyway this will do for now.
7155 *
7156 * Update: Should be possible once VMXR0LoadGuestState() is removed as an
7157 * interface and disable ring-3 calls when thread-context hooks are not
7158 * available. */
7159 bool fCallerDisabledLogFlush = VMMR0IsLogFlushDisabled(pVCpu);
7160 VMMR0LogFlushDisable(pVCpu);
7161#endif
7162
7163 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
7164
7165 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
7166
7167 /* Determine real-on-v86 mode. */
7168 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
7169 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
7170 && CPUMIsGuestInRealModeEx(pMixedCtx))
7171 {
7172 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
7173 }
7174
7175 /*
7176 * Load the guest-state into the VMCS.
7177 * Any ordering dependency among the sub-functions below must be explicitly stated using comments.
7178 * Ideally, assert that the cross-dependent bits are up to date at the point of using it.
7179 */
7180 int rc = hmR0VmxLoadGuestEntryCtls(pVCpu, pMixedCtx);
7181 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestEntryCtls! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7182
7183 rc = hmR0VmxLoadGuestExitCtls(pVCpu, pMixedCtx);
7184 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupExitCtls failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7185
7186 rc = hmR0VmxLoadGuestActivityState(pVCpu, pMixedCtx);
7187 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestActivityState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7188
7189 rc = hmR0VmxLoadGuestCR3AndCR4(pVCpu, pMixedCtx);
7190 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestCR3AndCR4: rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7191
7192 /* Assumes CR0 is up-to-date (strict builds require CR0 for segment register validation checks). */
7193 rc = hmR0VmxLoadGuestSegmentRegs(pVCpu, pMixedCtx);
7194 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestSegmentRegs: rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7195
7196 rc = hmR0VmxLoadGuestMsrs(pVCpu, pMixedCtx);
7197 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestMsrs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7198
7199 rc = hmR0VmxLoadGuestApicState(pVCpu, pMixedCtx);
7200 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7201
7202 /*
7203 * Loading Rflags here is fine, even though Rflags.TF might depend on guest debug state (which is not loaded here).
7204 * It is re-evaluated and updated if necessary in hmR0VmxLoadSharedState().
7205 */
7206 rc = hmR0VmxLoadGuestRipRspRflags(pVCpu, pMixedCtx);
7207 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestRipRspRflags! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7208
7209 rc = hmR0VmxSetupVMRunHandler(pVCpu, pMixedCtx);
7210 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
7211
7212 /* Clear any unused and reserved bits. */
7213 pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_GUEST_CR2;
7214
7215#ifdef LOG_ENABLED
7216 /* Only reenable log-flushing if the caller has it enabled. */
7217 if (!fCallerDisabledLogFlush)
7218 VMMR0LogFlushEnable(pVCpu);
7219#endif
7220
7221 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
7222 return rc;
7223}
7224
7225
7226/**
7227 * Loads the state shared between the host and guest into the VMCS.
7228 *
7229 * @param pVM Pointer to the VM.
7230 * @param pVCpu Pointer to the VMCPU.
7231 * @param pCtx Pointer to the guest-CPU context.
7232 *
7233 * @remarks No-long-jump zone!!!
7234 */
7235static void hmR0VmxLoadSharedState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
7236{
7237 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7238 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7239
7240 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
7241 {
7242 int rc = hmR0VmxLoadSharedCR0(pVCpu, pCtx);
7243 AssertRC(rc);
7244 }
7245
7246 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG)
7247 {
7248 int rc = hmR0VmxLoadSharedDebugState(pVCpu, pCtx);
7249 AssertRC(rc);
7250
7251 /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
7252 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_RFLAGS)
7253 {
7254 rc = hmR0VmxLoadGuestRflags(pVCpu, pCtx);
7255 AssertRC(rc);
7256 }
7257 }
7258
7259 AssertMsg(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE), ("fContextUseFlags=%#x\n",
7260 pVCpu->hm.s.fContextUseFlags));
7261}
7262
7263
7264/**
7265 * Worker for loading the guest-state bits in the inner VT-x execution loop.
7266 *
7267 * @param pVM Pointer to the VM.
7268 * @param pVCpu Pointer to the VMCPU.
7269 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7270 * out-of-sync. Make sure to update the required fields
7271 * before using them.
7272 */
7273DECLINLINE(void) hmR0VmxLoadGuestStateOptimal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7274{
7275 HMVMX_ASSERT_PREEMPT_SAFE();
7276
7277 Log5(("LoadFlags=%#RX32\n", pVCpu->hm.s.fContextUseFlags));
7278#ifdef HMVMX_SYNC_FULL_GUEST_STATE
7279 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
7280#endif
7281
7282 if (pVCpu->hm.s.fContextUseFlags == HM_CHANGED_GUEST_RIP)
7283 {
7284 int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
7285 AssertRC(rc);
7286 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadMinimal);
7287 }
7288 else if (pVCpu->hm.s.fContextUseFlags)
7289 {
7290 int rc = hmR0VmxLoadGuestState(pVM, pVCpu, pMixedCtx);
7291 AssertRC(rc);
7292 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
7293 }
7294
7295 /* All the guest state bits should be loaded except maybe the host context and shared host/guest bits. */
7296 AssertMsg( !(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_ALL_GUEST)
7297 || !(pVCpu->hm.s.fContextUseFlags & ~(HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE)),
7298 ("fContextUseFlags=%#x\n", pVCpu->hm.s.fContextUseFlags));
7299
7300#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
7301 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVM, pVCpu, pMixedCtx);
7302 if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
7303 Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
7304#endif
7305}
7306
7307
7308/**
7309 * Does the preparations before executing guest code in VT-x.
7310 *
7311 * This may cause longjmps to ring-3 and may even result in rescheduling to the
7312 * recompiler. We must be cautious what we do here regarding committing
7313 * guest-state information into the VMCS assuming we assuredly execute the
7314 * guest in VT-x mode. If we fall back to the recompiler after updating the VMCS
7315 * and clearing the common-state (TRPM/forceflags), we must undo those changes
7316 * so that the recompiler can (and should) use them when it resumes guest
7317 * execution. Otherwise such operations must be done when we can no longer
7318 * exit to ring-3.
7319 *
7320 * @returns Strict VBox status code.
7321 * @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
7322 * have been disabled.
7323 * @retval VINF_EM_RESET if a triple-fault occurs while injecting a
7324 * double-fault into the guest.
7325 * @retval VINF_* scheduling changes, we have to go back to ring-3.
7326 *
7327 * @param pVM Pointer to the VM.
7328 * @param pVCpu Pointer to the VMCPU.
7329 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7330 * out-of-sync. Make sure to update the required fields
7331 * before using them.
7332 * @param pVmxTransient Pointer to the VMX transient structure.
7333 *
7334 * @remarks Called with preemption disabled. In the VINF_SUCCESS return case
7335 * interrupts will be disabled.
7336 */
7337static int hmR0VmxPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
7338{
7339 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7340
7341#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
7342 PGMRZDynMapFlushAutoSet(pVCpu);
7343#endif
7344
7345 /* Check force flag actions that might require us to go back to ring-3. */
7346 int rc = hmR0VmxCheckForceFlags(pVM, pVCpu, pMixedCtx);
7347 if (rc != VINF_SUCCESS)
7348 return rc;
7349
7350#ifndef IEM_VERIFICATION_MODE_FULL
7351 /* Setup the Virtualized APIC accesses. pMixedCtx->msrApicBase is always up-to-date. It's not part of the VMCS. */
7352 if ( pVCpu->hm.s.vmx.u64MsrApicBase != pMixedCtx->msrApicBase
7353 && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
7354 {
7355 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
7356 RTGCPHYS GCPhysApicBase;
7357 GCPhysApicBase = pMixedCtx->msrApicBase;
7358 GCPhysApicBase &= PAGE_BASE_GC_MASK;
7359
7360 /* Unalias any existing mapping. */
7361 rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
7362 AssertRCReturn(rc, rc);
7363
7364 /* Map the HC APIC-access page into the GC space, this also updates the shadow page tables if necessary. */
7365 Log4(("Mapped HC APIC-access page into GC: GCPhysApicBase=%#RGv\n", GCPhysApicBase));
7366 rc = IOMMMIOMapMMIOHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
7367 AssertRCReturn(rc, rc);
7368
7369 pVCpu->hm.s.vmx.u64MsrApicBase = pMixedCtx->msrApicBase;
7370 }
7371#endif /* !IEM_VERIFICATION_MODE_FULL */
7372
7373 /* Load the guest state bits, we can handle longjmps/getting preempted here. */
7374 hmR0VmxLoadGuestStateOptimal(pVM, pVCpu, pMixedCtx);
7375
7376 /*
7377 * Evaluate events as pending-for-injection into the guest. Toggling of force-flags here is safe as long as
7378 * we update TRPM on premature exits to ring-3 before executing guest code. We must NOT restore the force-flags.
7379 */
7380 if (TRPMHasTrap(pVCpu))
7381 hmR0VmxTrpmTrapToPendingEvent(pVCpu);
7382 else if (!pVCpu->hm.s.Event.fPending)
7383 hmR0VmxEvaluatePendingEvent(pVCpu, pMixedCtx);
7384
7385 /*
7386 * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus needs to be done with
7387 * longjmps or interrupts + preemption enabled. Event injection might also result in triple-faulting the VM.
7388 */
7389 rc = hmR0VmxInjectPendingEvent(pVCpu, pMixedCtx);
7390 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7391 {
7392 Assert(rc == VINF_EM_RESET);
7393 return rc;
7394 }
7395
7396 /*
7397 * No longjmps to ring-3 from this point on!!!
7398 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
7399 * This also disables flushing of the R0-logger instance (if any).
7400 */
7401 VMMRZCallRing3Disable(pVCpu);
7402
7403 /*
7404 * We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
7405 * when thread-context hooks aren't used and we've been running with preemption disabled for a while.
7406 *
7407 * We need to check for force-flags that could've possible been altered since we last checked them (e.g.
7408 * by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
7409 *
7410 * We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
7411 * executing guest code.
7412 */
7413 pVmxTransient->uEflags = ASMIntDisableFlags();
7414 if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
7415 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
7416 {
7417 hmR0VmxClearEventVmcs(pVCpu);
7418 ASMSetFlags(pVmxTransient->uEflags);
7419 VMMRZCallRing3Enable(pVCpu);
7420 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
7421 return VINF_EM_RAW_TO_R3;
7422 }
7423 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
7424 {
7425 hmR0VmxClearEventVmcs(pVCpu);
7426 ASMSetFlags(pVmxTransient->uEflags);
7427 VMMRZCallRing3Enable(pVCpu);
7428 STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
7429 return VINF_EM_RAW_INTERRUPT;
7430 }
7431
7432 /* We've injected any pending events. This is really the point of no return (to ring-3). */
7433 pVCpu->hm.s.Event.fPending = false;
7434
7435 return VINF_SUCCESS;
7436}
7437
7438
7439/**
7440 * Prepares to run guest code in VT-x and we've committed to doing so. This
7441 * means there is no backing out to ring-3 or anywhere else at this
7442 * point.
7443 *
7444 * @param pVM Pointer to the VM.
7445 * @param pVCpu Pointer to the VMCPU.
7446 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7447 * out-of-sync. Make sure to update the required fields
7448 * before using them.
7449 * @param pVmxTransient Pointer to the VMX transient structure.
7450 *
7451 * @remarks Called with preemption disabled.
7452 * @remarks No-long-jump zone!!!
7453 */
7454static void hmR0VmxPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
7455{
7456 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7457 Assert(VMMR0IsLogFlushDisabled(pVCpu));
7458 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7459
7460 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
7461 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
7462
7463 /*
7464 * If we are injecting events to a real-on-v86 mode guest, we may have to update
7465 * RIP and some other registers, i.e. hmR0VmxInjectPendingEvent()->hmR0VmxInjectEventVmcs().
7466 * Reload only the necessary state, the assertion will catch if other parts of the code
7467 * change.
7468 */
7469 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
7470 {
7471 hmR0VmxLoadGuestRipRspRflags(pVCpu, pMixedCtx);
7472 hmR0VmxLoadGuestSegmentRegs(pVCpu, pMixedCtx);
7473 }
7474
7475 /*
7476 * Load the host state bits as we may've been preempted (only happens when
7477 * thread-context hooks are used).
7478 */
7479 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT)
7480 {
7481 Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
7482 int rc = hmR0VmxSaveHostState(pVM, pVCpu);
7483 AssertRC(rc);
7484 STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptSaveHostState);
7485 }
7486 Assert(!(pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_CONTEXT));
7487
7488 /*
7489 * Load the state shared between host and guest (FPU, debug).
7490 */
7491 if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_HOST_GUEST_SHARED_STATE)
7492 hmR0VmxLoadSharedState(pVM, pVCpu, pMixedCtx);
7493 AssertMsg(!pVCpu->hm.s.fContextUseFlags, ("fContextUseFlags=%#x\n", pVCpu->hm.s.fContextUseFlags));
7494
7495 /*
7496 * Cache the TPR-shadow for checking on every VM-exit if it might have changed.
7497 */
7498 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
7499 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[0x80];
7500
7501 PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
7502 RTCPUID idCurrentCpu = pCpu->idCpu;
7503 if ( pVmxTransient->fUpdateTscOffsettingAndPreemptTimer
7504 || idCurrentCpu != pVCpu->hm.s.idLastCpu)
7505 {
7506 hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVCpu, pMixedCtx);
7507 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
7508 }
7509
7510 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
7511 hmR0VmxFlushTaggedTlb(pVCpu, pCpu); /* Invalidate the appropriate guest entries from the TLB. */
7512 Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
7513 pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Update the error reporting info. with the current host CPU. */
7514
7515 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
7516
7517 TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
7518 to start executing. */
7519
7520#ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
7521 /*
7522 * Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
7523 * RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
7524 */
7525 if ( (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
7526 && !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
7527 {
7528 pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
7529 uint64_t u64HostTscAux = 0;
7530 int rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64HostTscAux);
7531 AssertRC(rc2);
7532 ASMWrMsr(MSR_K8_TSC_AUX, u64HostTscAux);
7533 }
7534#endif
7535}
7536
7537
7538/**
7539 * Performs some essential restoration of state after running guest code in
7540 * VT-x.
7541 *
7542 * @param pVM Pointer to the VM.
7543 * @param pVCpu Pointer to the VMCPU.
7544 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
7545 * out-of-sync. Make sure to update the required fields
7546 * before using them.
7547 * @param pVmxTransient Pointer to the VMX transient structure.
7548 * @param rcVMRun Return code of VMLAUNCH/VMRESUME.
7549 *
7550 * @remarks Called with interrupts disabled, and returns with interrups enabled!
7551 *
7552 * @remarks No-long-jump zone!!! This function will however re-enable longjmps
7553 * unconditionally when it is safe to do so.
7554 */
7555static void hmR0VmxPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, int rcVMRun)
7556{
7557 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7558
7559 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
7560 ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
7561 pVCpu->hm.s.vmx.fUpdatedGuestState = 0; /* Exits/longjmps to ring-3 requires saving the guest state. */
7562 pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
7563 pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
7564
7565 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
7566 {
7567#ifndef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
7568 /* Restore host's TSC_AUX. */
7569 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
7570 ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
7571#endif
7572 /** @todo Find a way to fix hardcoding a guestimate. */
7573 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC()
7574 + pVCpu->hm.s.vmx.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
7575 }
7576
7577 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
7578 TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
7579 Assert(!(ASMGetFlags() & X86_EFL_IF));
7580 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
7581
7582 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_REQUIRED; /* Host state messed up by VT-x, we must restore. */
7583 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
7584 ASMSetFlags(pVmxTransient->uEflags); /* Enable interrupts. */
7585 VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
7586
7587 /* Save the basic VM-exit reason. Refer Intel spec. 24.9.1 "Basic VM-exit Information". */
7588 uint32_t uExitReason;
7589 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
7590 rc |= hmR0VmxReadEntryIntrInfoVmcs(pVmxTransient);
7591 AssertRC(rc);
7592 pVmxTransient->uExitReason = (uint16_t)VMX_EXIT_REASON_BASIC(uExitReason);
7593 pVmxTransient->fVMEntryFailed = !!VMX_ENTRY_INTERRUPTION_INFO_VALID(pVmxTransient->uEntryIntrInfo);
7594
7595 /* If the VMLAUNCH/VMRESUME failed, we can bail out early. This does -not- cover VMX_EXIT_ERR_*. */
7596 if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
7597 {
7598 Log4(("VM-entry failure: pVCpu=%p idCpu=%RU32 rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", pVCpu, pVCpu->idCpu, rcVMRun,
7599 pVmxTransient->fVMEntryFailed));
7600 return;
7601 }
7602
7603 if (RT_LIKELY(!pVmxTransient->fVMEntryFailed))
7604 {
7605 /* Update the guest interruptibility-state from the VMCS. */
7606 hmR0VmxSaveGuestIntrState(pVCpu, pMixedCtx);
7607#if defined(HMVMX_SYNC_FULL_GUEST_STATE) || defined(HMVMX_SAVE_FULL_GUEST_STATE)
7608 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
7609 AssertRC(rc);
7610#endif
7611 /*
7612 * If the TPR was raised by the guest, it wouldn't cause a VM-exit immediately. Instead we sync the TPR lazily whenever
7613 * we eventually get a VM-exit for any reason. This maybe expensive as PDMApicSetTPR() can longjmp to ring-3 and which is
7614 * why it's done here as it's easier and no less efficient to deal with it here than making hmR0VmxSaveGuestState()
7615 * cope with longjmps safely (see VMCPU_FF_HM_UPDATE_CR3 handling).
7616 */
7617 if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
7618 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[0x80])
7619 {
7620 rc = PDMApicSetTPR(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[0x80]);
7621 AssertRC(rc);
7622 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
7623 }
7624 }
7625}
7626
7627
7628
7629/**
7630 * Runs the guest code using VT-x the normal way.
7631 *
7632 * @returns VBox status code.
7633 * @param pVM Pointer to the VM.
7634 * @param pVCpu Pointer to the VMCPU.
7635 * @param pCtx Pointer to the guest-CPU context.
7636 *
7637 * @note Mostly the same as hmR0VmxRunGuestCodeStep.
7638 * @remarks Called with preemption disabled.
7639 */
7640static int hmR0VmxRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
7641{
7642 VMXTRANSIENT VmxTransient;
7643 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
7644 int rc = VERR_INTERNAL_ERROR_5;
7645 uint32_t cLoops = 0;
7646
7647 for (;; cLoops++)
7648 {
7649 Assert(!HMR0SuspendPending());
7650 HMVMX_ASSERT_CPU_SAFE();
7651
7652 /* Preparatory work for running guest code, this may force us to return
7653 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
7654 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
7655 rc = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient);
7656 if (rc != VINF_SUCCESS)
7657 break;
7658
7659 hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
7660 rc = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
7661 /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
7662
7663 /* Restore any residual host-state and save any bits shared between host
7664 and guest into the guest-CPU state. Re-enables interrupts! */
7665 hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rc);
7666
7667 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
7668 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7669 {
7670 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
7671 hmR0VmxReportWorldSwitchError(pVM, pVCpu, rc, pCtx, &VmxTransient);
7672 return rc;
7673 }
7674
7675 /* Handle the VM-exit. */
7676 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
7677 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
7678 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
7679 HMVMX_START_EXIT_DISPATCH_PROF();
7680#ifdef HMVMX_USE_FUNCTION_TABLE
7681 rc = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, pCtx, &VmxTransient);
7682#else
7683 rc = hmR0VmxHandleExit(pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason);
7684#endif
7685 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
7686 if (rc != VINF_SUCCESS)
7687 break;
7688 else if (cLoops > pVM->hm.s.cMaxResumeLoops)
7689 {
7690 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
7691 rc = VINF_EM_RAW_INTERRUPT;
7692 break;
7693 }
7694 }
7695
7696 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
7697 return rc;
7698}
7699
7700
7701/**
7702 * Single steps guest code using VT-x.
7703 *
7704 * @returns VBox status code.
7705 * @param pVM Pointer to the VM.
7706 * @param pVCpu Pointer to the VMCPU.
7707 * @param pCtx Pointer to the guest-CPU context.
7708 *
7709 * @note Mostly the same as hmR0VmxRunGuestCodeNormal.
7710 * @remarks Called with preemption disabled.
7711 */
7712static int hmR0VmxRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
7713{
7714 VMXTRANSIENT VmxTransient;
7715 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
7716 int rc = VERR_INTERNAL_ERROR_5;
7717 uint32_t cLoops = 0;
7718 uint16_t uCsStart = pCtx->cs.Sel;
7719 uint64_t uRipStart = pCtx->rip;
7720
7721 for (;; cLoops++)
7722 {
7723 Assert(!HMR0SuspendPending());
7724 HMVMX_ASSERT_CPU_SAFE();
7725
7726 /* Preparatory work for running guest code, this may force us to return
7727 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
7728 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
7729 rc = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient);
7730 if (rc != VINF_SUCCESS)
7731 break;
7732
7733 hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
7734 rc = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
7735 /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
7736
7737 /* Restore any residual host-state and save any bits shared between host
7738 and guest into the guest-CPU state. Re-enables interrupts! */
7739 hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rc);
7740
7741 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
7742 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7743 {
7744 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
7745 hmR0VmxReportWorldSwitchError(pVM, pVCpu, rc, pCtx, &VmxTransient);
7746 return rc;
7747 }
7748
7749 /* Handle the VM-exit. */
7750 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
7751 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
7752 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
7753 HMVMX_START_EXIT_DISPATCH_PROF();
7754#ifdef HMVMX_USE_FUNCTION_TABLE
7755 rc = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, pCtx, &VmxTransient);
7756#else
7757 rc = hmR0VmxHandleExit(pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason);
7758#endif
7759 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
7760 if (rc != VINF_SUCCESS)
7761 break;
7762 else if (cLoops > pVM->hm.s.cMaxResumeLoops)
7763 {
7764 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
7765 rc = VINF_EM_RAW_INTERRUPT;
7766 break;
7767 }
7768
7769 /*
7770 * Did the RIP change, if so, consider it a single step.
7771 * Otherwise, make sure one of the TFs gets set.
7772 */
7773 int rc2 = hmR0VmxSaveGuestRip(pVCpu, pCtx);
7774 rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pCtx);
7775 AssertRCReturn(rc2, rc2);
7776 if ( pCtx->rip != uRipStart
7777 || pCtx->cs.Sel != uCsStart)
7778 {
7779 rc = VINF_EM_DBG_STEPPED;
7780 break;
7781 }
7782 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
7783 }
7784
7785 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
7786 return rc;
7787}
7788
7789
7790/**
7791 * Runs the guest code using VT-x.
7792 *
7793 * @returns VBox status code.
7794 * @param pVM Pointer to the VM.
7795 * @param pVCpu Pointer to the VMCPU.
7796 * @param pCtx Pointer to the guest-CPU context.
7797 *
7798 * @remarks Called with preemption disabled.
7799 */
7800VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
7801{
7802 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7803 Assert(pVCpu->hm.s.vmx.fUpdatedGuestState == HMVMX_UPDATED_GUEST_ALL);
7804 HMVMX_ASSERT_PREEMPT_SAFE();
7805
7806 VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
7807
7808 int rc;
7809 if (!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu))
7810 rc = hmR0VmxRunGuestCodeNormal(pVM, pVCpu, pCtx);
7811 else
7812 rc = hmR0VmxRunGuestCodeStep(pVM, pVCpu, pCtx);
7813
7814 if (rc == VERR_EM_INTERPRETER)
7815 rc = VINF_EM_RAW_EMULATE_INSTR;
7816 else if (rc == VINF_EM_RESET)
7817 rc = VINF_EM_TRIPLE_FAULT;
7818
7819 int rc2 = hmR0VmxExitToRing3(pVM, pVCpu, pCtx, rc);
7820 if (RT_FAILURE(rc2))
7821 {
7822 pVCpu->hm.s.u32HMError = rc;
7823 rc = rc2;
7824 }
7825 Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
7826 return rc;
7827}
7828
7829
7830#ifndef HMVMX_USE_FUNCTION_TABLE
7831DECLINLINE(int) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason)
7832{
7833 int rc;
7834 switch (rcReason)
7835 {
7836 case VMX_EXIT_EPT_MISCONFIG: rc = hmR0VmxExitEptMisconfig(pVCpu, pMixedCtx, pVmxTransient); break;
7837 case VMX_EXIT_EPT_VIOLATION: rc = hmR0VmxExitEptViolation(pVCpu, pMixedCtx, pVmxTransient); break;
7838 case VMX_EXIT_IO_INSTR: rc = hmR0VmxExitIoInstr(pVCpu, pMixedCtx, pVmxTransient); break;
7839 case VMX_EXIT_CPUID: rc = hmR0VmxExitCpuid(pVCpu, pMixedCtx, pVmxTransient); break;
7840 case VMX_EXIT_RDTSC: rc = hmR0VmxExitRdtsc(pVCpu, pMixedCtx, pVmxTransient); break;
7841 case VMX_EXIT_RDTSCP: rc = hmR0VmxExitRdtscp(pVCpu, pMixedCtx, pVmxTransient); break;
7842 case VMX_EXIT_APIC_ACCESS: rc = hmR0VmxExitApicAccess(pVCpu, pMixedCtx, pVmxTransient); break;
7843 case VMX_EXIT_XCPT_OR_NMI: rc = hmR0VmxExitXcptOrNmi(pVCpu, pMixedCtx, pVmxTransient); break;
7844 case VMX_EXIT_MOV_CRX: rc = hmR0VmxExitMovCRx(pVCpu, pMixedCtx, pVmxTransient); break;
7845 case VMX_EXIT_EXT_INT: rc = hmR0VmxExitExtInt(pVCpu, pMixedCtx, pVmxTransient); break;
7846 case VMX_EXIT_INT_WINDOW: rc = hmR0VmxExitIntWindow(pVCpu, pMixedCtx, pVmxTransient); break;
7847 case VMX_EXIT_MWAIT: rc = hmR0VmxExitMwait(pVCpu, pMixedCtx, pVmxTransient); break;
7848 case VMX_EXIT_MONITOR: rc = hmR0VmxExitMonitor(pVCpu, pMixedCtx, pVmxTransient); break;
7849 case VMX_EXIT_TASK_SWITCH: rc = hmR0VmxExitTaskSwitch(pVCpu, pMixedCtx, pVmxTransient); break;
7850 case VMX_EXIT_PREEMPT_TIMER: rc = hmR0VmxExitPreemptTimer(pVCpu, pMixedCtx, pVmxTransient); break;
7851 case VMX_EXIT_RDMSR: rc = hmR0VmxExitRdmsr(pVCpu, pMixedCtx, pVmxTransient); break;
7852 case VMX_EXIT_WRMSR: rc = hmR0VmxExitWrmsr(pVCpu, pMixedCtx, pVmxTransient); break;
7853 case VMX_EXIT_MOV_DRX: rc = hmR0VmxExitMovDRx(pVCpu, pMixedCtx, pVmxTransient); break;
7854 case VMX_EXIT_TPR_BELOW_THRESHOLD: rc = hmR0VmxExitTprBelowThreshold(pVCpu, pMixedCtx, pVmxTransient); break;
7855 case VMX_EXIT_HLT: rc = hmR0VmxExitHlt(pVCpu, pMixedCtx, pVmxTransient); break;
7856 case VMX_EXIT_INVD: rc = hmR0VmxExitInvd(pVCpu, pMixedCtx, pVmxTransient); break;
7857 case VMX_EXIT_INVLPG: rc = hmR0VmxExitInvlpg(pVCpu, pMixedCtx, pVmxTransient); break;
7858 case VMX_EXIT_RSM: rc = hmR0VmxExitRsm(pVCpu, pMixedCtx, pVmxTransient); break;
7859 case VMX_EXIT_MTF: rc = hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient); break;
7860 case VMX_EXIT_PAUSE: rc = hmR0VmxExitPause(pVCpu, pMixedCtx, pVmxTransient); break;
7861 case VMX_EXIT_XDTR_ACCESS: rc = hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient); break;
7862 case VMX_EXIT_TR_ACCESS: rc = hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient); break;
7863 case VMX_EXIT_WBINVD: rc = hmR0VmxExitWbinvd(pVCpu, pMixedCtx, pVmxTransient); break;
7864 case VMX_EXIT_XSETBV: rc = hmR0VmxExitXsetbv(pVCpu, pMixedCtx, pVmxTransient); break;
7865 case VMX_EXIT_RDRAND: rc = hmR0VmxExitRdrand(pVCpu, pMixedCtx, pVmxTransient); break;
7866 case VMX_EXIT_INVPCID: rc = hmR0VmxExitInvpcid(pVCpu, pMixedCtx, pVmxTransient); break;
7867 case VMX_EXIT_GETSEC: rc = hmR0VmxExitGetsec(pVCpu, pMixedCtx, pVmxTransient); break;
7868 case VMX_EXIT_RDPMC: rc = hmR0VmxExitRdpmc(pVCpu, pMixedCtx, pVmxTransient); break;
7869
7870 case VMX_EXIT_TRIPLE_FAULT: rc = hmR0VmxExitTripleFault(pVCpu, pMixedCtx, pVmxTransient); break;
7871 case VMX_EXIT_NMI_WINDOW: rc = hmR0VmxExitNmiWindow(pVCpu, pMixedCtx, pVmxTransient); break;
7872 case VMX_EXIT_INIT_SIGNAL: rc = hmR0VmxExitInitSignal(pVCpu, pMixedCtx, pVmxTransient); break;
7873 case VMX_EXIT_SIPI: rc = hmR0VmxExitSipi(pVCpu, pMixedCtx, pVmxTransient); break;
7874 case VMX_EXIT_IO_SMI: rc = hmR0VmxExitIoSmi(pVCpu, pMixedCtx, pVmxTransient); break;
7875 case VMX_EXIT_SMI: rc = hmR0VmxExitSmi(pVCpu, pMixedCtx, pVmxTransient); break;
7876 case VMX_EXIT_ERR_MSR_LOAD: rc = hmR0VmxExitErrMsrLoad(pVCpu, pMixedCtx, pVmxTransient); break;
7877 case VMX_EXIT_ERR_INVALID_GUEST_STATE: rc = hmR0VmxExitErrInvalidGuestState(pVCpu, pMixedCtx, pVmxTransient); break;
7878 case VMX_EXIT_ERR_MACHINE_CHECK: rc = hmR0VmxExitErrMachineCheck(pVCpu, pMixedCtx, pVmxTransient); break;
7879
7880 case VMX_EXIT_VMCALL:
7881 case VMX_EXIT_VMCLEAR:
7882 case VMX_EXIT_VMLAUNCH:
7883 case VMX_EXIT_VMPTRLD:
7884 case VMX_EXIT_VMPTRST:
7885 case VMX_EXIT_VMREAD:
7886 case VMX_EXIT_VMRESUME:
7887 case VMX_EXIT_VMWRITE:
7888 case VMX_EXIT_VMXOFF:
7889 case VMX_EXIT_VMXON:
7890 case VMX_EXIT_INVEPT:
7891 case VMX_EXIT_INVVPID:
7892 case VMX_EXIT_VMFUNC:
7893 rc = hmR0VmxExitSetPendingXcptUD(pVCpu, pMixedCtx, pVmxTransient);
7894 break;
7895 default:
7896 rc = hmR0VmxExitErrUndefined(pVCpu, pMixedCtx, pVmxTransient);
7897 break;
7898 }
7899 return rc;
7900}
7901#endif
7902
7903#ifdef DEBUG
7904/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
7905# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
7906 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
7907
7908# define HMVMX_ASSERT_PREEMPT_CPUID() \
7909 do \
7910 { \
7911 RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
7912 AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
7913 } while (0)
7914
7915# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
7916 do { \
7917 AssertPtr(pVCpu); \
7918 AssertPtr(pMixedCtx); \
7919 AssertPtr(pVmxTransient); \
7920 Assert(pVmxTransient->fVMEntryFailed == false); \
7921 Assert(ASMIntAreEnabled()); \
7922 HMVMX_ASSERT_PREEMPT_SAFE(); \
7923 HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
7924 Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", pVCpu->idCpu)); \
7925 HMVMX_ASSERT_PREEMPT_SAFE(); \
7926 if (VMMR0IsLogFlushDisabled(pVCpu)) \
7927 HMVMX_ASSERT_PREEMPT_CPUID(); \
7928 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
7929 } while (0)
7930
7931# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() \
7932 do { \
7933 Log4Func(("\n")); \
7934 } while(0)
7935#else /* Release builds */
7936# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() do { HMVMX_STOP_EXIT_DISPATCH_PROF(); } while(0)
7937# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() do { } while(0)
7938#endif
7939
7940
7941/**
7942 * Advances the guest RIP after reading it from the VMCS.
7943 *
7944 * @returns VBox status code.
7945 * @param pVCpu Pointer to the VMCPU.
7946 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
7947 * out-of-sync. Make sure to update the required fields
7948 * before using them.
7949 * @param pVmxTransient Pointer to the VMX transient structure.
7950 *
7951 * @remarks No-long-jump zone!!!
7952 */
7953DECLINLINE(int) hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
7954{
7955 int rc = hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
7956 rc |= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
7957 AssertRCReturn(rc, rc);
7958
7959 pMixedCtx->rip += pVmxTransient->cbInstr;
7960 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
7961 return rc;
7962}
7963
7964
7965/**
7966 * Tries to determine what part of the guest-state VT-x has deemed as invalid
7967 * and update error record fields accordingly.
7968 *
7969 * @return VMX_IGS_* return codes.
7970 * @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
7971 * wrong with the guest state.
7972 *
7973 * @param pVM Pointer to the VM.
7974 * @param pVCpu Pointer to the VMCPU.
7975 * @param pCtx Pointer to the guest-CPU state.
7976 */
7977static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
7978{
7979#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
7980#define HMVMX_CHECK_BREAK(expr, err) if (!(expr)) { \
7981 uError = (err); \
7982 break; \
7983 } else do {} while (0)
7984/* Duplicate of IEM_IS_CANONICAL(). */
7985#define HMVMX_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
7986
7987 int rc;
7988 uint64_t u64Val;
7989 uint32_t u32Val;
7990 uint32_t uError = VMX_IGS_ERROR;
7991 bool fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
7992
7993 do
7994 {
7995 /*
7996 * CR0.
7997 */
7998 uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
7999 uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
8000 /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG).
8001 See Intel spec. 26.3.1 "Checks on guest Guest Control Registers, Debug Registers and MSRs." */
8002 if (fUnrestrictedGuest)
8003 uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG);
8004
8005 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val);
8006 AssertRCBreak(rc);
8007 HMVMX_CHECK_BREAK((u32Val & uSetCR0) == uSetCR0, VMX_IGS_CR0_FIXED1);
8008 HMVMX_CHECK_BREAK(!(u32Val & ~uZapCR0), VMX_IGS_CR0_FIXED0);
8009 if ( !fUnrestrictedGuest
8010 && (u32Val & X86_CR0_PG)
8011 && !(u32Val & X86_CR0_PE))
8012 {
8013 HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
8014 }
8015
8016 /*
8017 * CR4.
8018 */
8019 uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
8020 uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
8021 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32Val);
8022 AssertRCBreak(rc);
8023 HMVMX_CHECK_BREAK((u32Val & uSetCR4) == uSetCR4, VMX_IGS_CR4_FIXED1);
8024 HMVMX_CHECK_BREAK(!(u32Val & ~uZapCR4), VMX_IGS_CR4_FIXED0);
8025
8026 /*
8027 * IA32_DEBUGCTL MSR.
8028 */
8029 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
8030 AssertRCBreak(rc);
8031 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
8032 && (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
8033 {
8034 HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
8035 }
8036 uint64_t u64DebugCtlMsr = u64Val;
8037
8038#ifdef VBOX_STRICT
8039 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
8040 AssertRCBreak(rc);
8041 Assert(u32Val == pVCpu->hm.s.vmx.u32ProcCtls);
8042#endif
8043 bool const fLongModeGuest = !!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
8044
8045 /*
8046 * RIP and RFLAGS.
8047 */
8048 uint32_t u32Eflags;
8049#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
8050 if (HMVMX_IS_64BIT_HOST_MODE())
8051 {
8052 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RIP, &u64Val);
8053 AssertRCBreak(rc);
8054 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
8055 if ( !fLongModeGuest
8056 || !pCtx->cs.Attr.n.u1Long)
8057 {
8058 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
8059 }
8060 /** @todo If the processor supports N < 64 linear-address bits, bits 63:N
8061 * must be identical if the "IA32e mode guest" VM-entry control is 1
8062 * and CS.L is 1. No check applies if the CPU supports 64
8063 * linear-address bits. */
8064
8065 /* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
8066 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RFLAGS, &u64Val);
8067 AssertRCBreak(rc);
8068 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
8069 VMX_IGS_RFLAGS_RESERVED);
8070 HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
8071 u32Eflags = u64Val;
8072 }
8073 else
8074#endif
8075 {
8076 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Eflags);
8077 AssertRCBreak(rc);
8078 HMVMX_CHECK_BREAK(!(u32Eflags & 0xffc08028), VMX_IGS_RFLAGS_RESERVED); /* Bit 31:22, Bit 15, 5, 3 MBZ. */
8079 HMVMX_CHECK_BREAK((u32Eflags & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
8080 }
8081
8082 if ( fLongModeGuest
8083 || !(pCtx->cr0 & X86_CR0_PE))
8084 {
8085 HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
8086 }
8087
8088 uint32_t u32EntryInfo;
8089 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
8090 AssertRCBreak(rc);
8091 if ( VMX_ENTRY_INTERRUPTION_INFO_VALID(u32EntryInfo)
8092 && VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
8093 {
8094 HMVMX_CHECK_BREAK(u32Val & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
8095 }
8096
8097 /*
8098 * 64-bit checks.
8099 */
8100#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
8101 if (HMVMX_IS_64BIT_HOST_MODE())
8102 {
8103 if ( fLongModeGuest
8104 && !fUnrestrictedGuest)
8105 {
8106 HMVMX_CHECK_BREAK(CPUMIsGuestPagingEnabledEx(pCtx), VMX_IGS_CR0_PG_LONGMODE);
8107 HMVMX_CHECK_BREAK((pCtx->cr4 & X86_CR4_PAE), VMX_IGS_CR4_PAE_LONGMODE);
8108 }
8109
8110 if ( !fLongModeGuest
8111 && (pCtx->cr4 & X86_CR4_PCIDE))
8112 {
8113 HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
8114 }
8115
8116 /** @todo CR3 field must be such that bits 63:52 and bits in the range
8117 * 51:32 beyond the processor's physical-address width are 0. */
8118
8119 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
8120 && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
8121 {
8122 HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
8123 }
8124
8125 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
8126 AssertRCBreak(rc);
8127 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
8128
8129 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
8130 AssertRCBreak(rc);
8131 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
8132 }
8133#endif
8134
8135 /*
8136 * PERF_GLOBAL MSR.
8137 */
8138 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR)
8139 {
8140 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
8141 AssertRCBreak(rc);
8142 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
8143 VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
8144 }
8145
8146 /*
8147 * PAT MSR.
8148 */
8149 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR)
8150 {
8151 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
8152 AssertRCBreak(rc);
8153 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
8154 for (unsigned i = 0; i < 8; i++)
8155 {
8156 uint8_t u8Val = (u64Val & 0x7);
8157 if ( u8Val != 0 /* UC */
8158 || u8Val != 1 /* WC */
8159 || u8Val != 4 /* WT */
8160 || u8Val != 5 /* WP */
8161 || u8Val != 6 /* WB */
8162 || u8Val != 7 /* UC- */)
8163 {
8164 HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
8165 }
8166 u64Val >>= 3;
8167 }
8168 }
8169
8170 /*
8171 * EFER MSR.
8172 */
8173 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
8174 {
8175 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
8176 AssertRCBreak(rc);
8177 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
8178 VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
8179 HMVMX_CHECK_BREAK((u64Val & MSR_K6_EFER_LMA) == (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST),
8180 VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
8181 HMVMX_CHECK_BREAK( fUnrestrictedGuest
8182 || (u64Val & MSR_K6_EFER_LMA) == (pCtx->cr0 & X86_CR0_PG), VMX_IGS_EFER_LMA_PG_MISMATCH);
8183 }
8184
8185 /*
8186 * Segment registers.
8187 */
8188 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
8189 || !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
8190 if (!(u32Eflags & X86_EFL_VM))
8191 {
8192 /* CS */
8193 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
8194 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
8195 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
8196 HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
8197 || !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
8198 HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
8199 || (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
8200 /* CS cannot be loaded with NULL in protected mode. */
8201 HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
8202 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
8203 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
8204 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
8205 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
8206 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
8207 else if (pVM->hm.s.vmx.fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
8208 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
8209 else
8210 HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
8211
8212 /* SS */
8213 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
8214 || (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
8215 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
8216 if ( !(pCtx->cr0 & X86_CR0_PE)
8217 || pCtx->cs.Attr.n.u4Type == 3)
8218 {
8219 HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
8220 }
8221 if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
8222 {
8223 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
8224 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
8225 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
8226 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
8227 HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
8228 || !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
8229 HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
8230 || (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
8231 }
8232
8233 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
8234 if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
8235 {
8236 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
8237 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
8238 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
8239 || pCtx->ds.Attr.n.u4Type > 11
8240 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
8241 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
8242 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
8243 HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
8244 || !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
8245 HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
8246 || (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
8247 HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
8248 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
8249 }
8250 if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
8251 {
8252 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
8253 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
8254 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
8255 || pCtx->es.Attr.n.u4Type > 11
8256 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
8257 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
8258 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
8259 HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
8260 || !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
8261 HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
8262 || (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
8263 HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
8264 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
8265 }
8266 if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
8267 {
8268 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
8269 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
8270 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
8271 || pCtx->fs.Attr.n.u4Type > 11
8272 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
8273 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
8274 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
8275 HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
8276 || !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
8277 HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
8278 || (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
8279 HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
8280 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
8281 }
8282 if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
8283 {
8284 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
8285 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
8286 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
8287 || pCtx->gs.Attr.n.u4Type > 11
8288 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
8289 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
8290 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
8291 HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
8292 || !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
8293 HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
8294 || (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
8295 HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
8296 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
8297 }
8298 /* 64-bit capable CPUs. */
8299#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
8300 if (HMVMX_IS_64BIT_HOST_MODE())
8301 {
8302 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
8303 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
8304 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
8305 || HMVMX_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
8306 HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
8307 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
8308 VMX_IGS_LONGMODE_SS_BASE_INVALID);
8309 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
8310 VMX_IGS_LONGMODE_DS_BASE_INVALID);
8311 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
8312 VMX_IGS_LONGMODE_ES_BASE_INVALID);
8313 }
8314#endif
8315 }
8316 else
8317 {
8318 /* V86 mode checks. */
8319 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
8320 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
8321 {
8322 u32CSAttr = 0xf3; u32SSAttr = 0xf3;
8323 u32DSAttr = 0xf3; u32ESAttr = 0xf3;
8324 u32FSAttr = 0xf3; u32GSAttr = 0xf3;
8325 }
8326 else
8327 {
8328 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
8329 u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
8330 u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
8331 }
8332
8333 /* CS */
8334 HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
8335 HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
8336 HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
8337 /* SS */
8338 HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
8339 HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
8340 HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
8341 /* DS */
8342 HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
8343 HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
8344 HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
8345 /* ES */
8346 HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
8347 HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
8348 HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
8349 /* FS */
8350 HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
8351 HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
8352 HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
8353 /* GS */
8354 HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
8355 HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
8356 HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
8357 /* 64-bit capable CPUs. */
8358#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
8359 if (HMVMX_IS_64BIT_HOST_MODE())
8360 {
8361 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
8362 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
8363 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
8364 || HMVMX_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
8365 HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
8366 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
8367 VMX_IGS_LONGMODE_SS_BASE_INVALID);
8368 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
8369 VMX_IGS_LONGMODE_DS_BASE_INVALID);
8370 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
8371 VMX_IGS_LONGMODE_ES_BASE_INVALID);
8372 }
8373#endif
8374 }
8375
8376 /*
8377 * TR.
8378 */
8379 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
8380 /* 64-bit capable CPUs. */
8381#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
8382 if (HMVMX_IS_64BIT_HOST_MODE())
8383 {
8384 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
8385 }
8386#endif
8387 if (fLongModeGuest)
8388 {
8389 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
8390 VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
8391 }
8392 else
8393 {
8394 HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
8395 || pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
8396 VMX_IGS_TR_ATTR_TYPE_INVALID);
8397 }
8398 HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
8399 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
8400 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
8401 HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
8402 || !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
8403 HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
8404 || (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
8405 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
8406
8407 /*
8408 * GDTR and IDTR.
8409 */
8410#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
8411 if (HMVMX_IS_64BIT_HOST_MODE())
8412 {
8413 rc = VMXReadVmcs64(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
8414 AssertRCBreak(rc);
8415 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
8416
8417 rc = VMXReadVmcs64(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
8418 AssertRCBreak(rc);
8419 HMVMX_CHECK_BREAK(HMVMX_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
8420 }
8421#endif
8422
8423 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
8424 AssertRCBreak(rc);
8425 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
8426
8427 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
8428 AssertRCBreak(rc);
8429 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
8430
8431 /*
8432 * Guest Non-Register State.
8433 */
8434 /* Activity State. */
8435 uint32_t u32ActivityState;
8436 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
8437 AssertRCBreak(rc);
8438 HMVMX_CHECK_BREAK( !u32ActivityState
8439 || (u32ActivityState & MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.Msrs.u64Misc)),
8440 VMX_IGS_ACTIVITY_STATE_INVALID);
8441 HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
8442 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
8443 uint32_t u32IntrState;
8444 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &u32IntrState);
8445 AssertRCBreak(rc);
8446 if ( u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS
8447 || u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
8448 {
8449 HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
8450 }
8451
8452 /** @todo Activity state and injecting interrupts. Left as a todo since we
8453 * currently don't use activity states but ACTIVE. */
8454
8455 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
8456 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
8457
8458 /* Guest interruptibility-state. */
8459 HMVMX_CHECK_BREAK(!(u32IntrState & 0xfffffff0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
8460 HMVMX_CHECK_BREAK((u32IntrState & ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
8461 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS))
8462 != ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
8463 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
8464 VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
8465 HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
8466 || !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
8467 VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
8468 if (VMX_ENTRY_INTERRUPTION_INFO_VALID(u32EntryInfo))
8469 {
8470 if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
8471 {
8472 HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
8473 && !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
8474 VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
8475 }
8476 else if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
8477 {
8478 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
8479 VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
8480 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
8481 VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
8482 }
8483 }
8484 /** @todo Assumes the processor is not in SMM. */
8485 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
8486 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
8487 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
8488 || (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
8489 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
8490 if ( (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
8491 && VMX_ENTRY_INTERRUPTION_INFO_VALID(u32EntryInfo)
8492 && VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
8493 {
8494 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI),
8495 VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
8496 }
8497
8498 /* Pending debug exceptions. */
8499 if (HMVMX_IS_64BIT_HOST_MODE())
8500 {
8501 rc = VMXReadVmcs64(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u64Val);
8502 AssertRCBreak(rc);
8503 /* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
8504 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
8505 u32Val = u64Val; /* For pending debug exceptions checks below. */
8506 }
8507 else
8508 {
8509 rc = VMXReadVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u32Val);
8510 AssertRCBreak(rc);
8511 /* Bits 31:15, Bit 13, Bits 11:4 MBZ. */
8512 HMVMX_CHECK_BREAK(!(u64Val & 0xffffaff0), VMX_IGS_PENDING_DEBUG_RESERVED);
8513 }
8514
8515 if ( (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
8516 || (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS)
8517 || u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
8518 {
8519 if ( (u32Eflags & X86_EFL_TF)
8520 && !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
8521 {
8522 /* Bit 14 is PendingDebug.BS. */
8523 HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
8524 }
8525 if ( !(u32Eflags & X86_EFL_TF)
8526 || (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
8527 {
8528 /* Bit 14 is PendingDebug.BS. */
8529 HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
8530 }
8531 }
8532
8533 /* VMCS link pointer. */
8534 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
8535 AssertRCBreak(rc);
8536 if (u64Val != UINT64_C(0xffffffffffffffff))
8537 {
8538 HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
8539 /** @todo Bits beyond the processor's physical-address width MBZ. */
8540 /** @todo 32-bit located in memory referenced by value of this field (as a
8541 * physical address) must contain the processor's VMCS revision ID. */
8542 /** @todo SMM checks. */
8543 }
8544
8545 /** @todo Checks on Guest Page-Directory-Pointer-Table Entries. */
8546
8547 /* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
8548 if (uError == VMX_IGS_ERROR)
8549 uError = VMX_IGS_REASON_NOT_FOUND;
8550 } while (0);
8551
8552 pVCpu->hm.s.u32HMError = uError;
8553 return uError;
8554
8555#undef HMVMX_ERROR_BREAK
8556#undef HMVMX_CHECK_BREAK
8557#undef HMVMX_IS_CANONICAL
8558}
8559
8560/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
8561/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
8562/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
8563
8564/** @name VM-exit handlers.
8565 * @{
8566 */
8567
8568/**
8569 * VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
8570 */
8571HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8572{
8573 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8574 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
8575 /* 32-bit Windows hosts (4 cores) has trouble with this; causes higher interrupt latency. */
8576#if HC_ARCH_BITS == 64
8577 Assert(ASMIntAreEnabled());
8578 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUsePreemptTimer)
8579 return VINF_SUCCESS;
8580#endif
8581 return VINF_EM_RAW_INTERRUPT;
8582}
8583
8584
8585/**
8586 * VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
8587 */
8588HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8589{
8590 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8591 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
8592
8593 int rc = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
8594 AssertRCReturn(rc, rc);
8595
8596 uint32_t uIntrType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntrInfo);
8597 Assert( !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT)
8598 && uIntrType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
8599 Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntrInfo));
8600
8601 if (uIntrType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
8602 {
8603 /*
8604 * This cannot be a guest NMI as the only way for the guest to receive an NMI is if we injected it ourselves and
8605 * anything we inject is not going to cause a VM-exit directly for the event being injected.
8606 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
8607 *
8608 * Dispatch the NMI to the host. See Intel spec. 27.5.5 "Updating Non-Register State".
8609 */
8610 VMXDispatchHostNmi();
8611 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
8612 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
8613 return VINF_SUCCESS;
8614 }
8615
8616 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
8617 rc = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
8618 if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT))
8619 {
8620 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
8621 return VINF_SUCCESS;
8622 }
8623 else if (RT_UNLIKELY(rc == VINF_EM_RESET))
8624 {
8625 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
8626 return rc;
8627 }
8628
8629 uint32_t uExitIntrInfo = pVmxTransient->uExitIntrInfo;
8630 uint32_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(uExitIntrInfo);
8631 switch (uIntrType)
8632 {
8633 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT: /* Software exception. (#BP or #OF) */
8634 Assert(uVector == X86_XCPT_DB || uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
8635 /* no break */
8636 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT:
8637 {
8638 switch (uVector)
8639 {
8640 case X86_XCPT_PF: rc = hmR0VmxExitXcptPF(pVCpu, pMixedCtx, pVmxTransient); break;
8641 case X86_XCPT_GP: rc = hmR0VmxExitXcptGP(pVCpu, pMixedCtx, pVmxTransient); break;
8642 case X86_XCPT_NM: rc = hmR0VmxExitXcptNM(pVCpu, pMixedCtx, pVmxTransient); break;
8643 case X86_XCPT_MF: rc = hmR0VmxExitXcptMF(pVCpu, pMixedCtx, pVmxTransient); break;
8644 case X86_XCPT_DB: rc = hmR0VmxExitXcptDB(pVCpu, pMixedCtx, pVmxTransient); break;
8645 case X86_XCPT_BP: rc = hmR0VmxExitXcptBP(pVCpu, pMixedCtx, pVmxTransient); break;
8646#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
8647 case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF);
8648 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
8649 case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
8650 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
8651 case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
8652 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
8653 case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
8654 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
8655 case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
8656 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
8657#endif
8658 default:
8659 {
8660 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
8661 AssertRCReturn(rc, rc);
8662
8663 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
8664 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
8665 {
8666 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
8667 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
8668 Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
8669
8670 rc = hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
8671 rc |= hmR0VmxReadExitIntrErrorCodeVmcs(pVCpu, pVmxTransient);
8672 AssertRCReturn(rc, rc);
8673 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(uExitIntrInfo),
8674 pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode,
8675 0 /* GCPtrFaultAddress */);
8676 AssertRCReturn(rc, rc);
8677 }
8678 else
8679 {
8680 AssertMsgFailed(("Unexpected VM-exit caused by exception %#x\n", uVector));
8681 pVCpu->hm.s.u32HMError = uVector;
8682 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
8683 }
8684 break;
8685 }
8686 }
8687 break;
8688 }
8689
8690 default:
8691 {
8692 pVCpu->hm.s.u32HMError = uExitIntrInfo;
8693 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
8694 AssertMsgFailed(("Unexpected interruption code %#x\n", VMX_EXIT_INTERRUPTION_INFO_TYPE(uExitIntrInfo)));
8695 break;
8696 }
8697 }
8698 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
8699 return rc;
8700}
8701
8702
8703/**
8704 * VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
8705 */
8706HMVMX_EXIT_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8707{
8708 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8709
8710 /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
8711 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
8712 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
8713 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
8714 AssertRCReturn(rc, rc);
8715
8716 /* Deliver the pending interrupt via hmR0VmxPreRunGuest()->hmR0VmxInjectEvent() and resume guest execution. */
8717 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
8718 return VINF_SUCCESS;
8719}
8720
8721
8722/**
8723 * VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
8724 */
8725HMVMX_EXIT_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8726{
8727 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8728 AssertMsgFailed(("Unexpected NMI-window exit.\n"));
8729 pVCpu->hm.s.u32HMError = VMX_EXIT_NMI_WINDOW;
8730 return VERR_VMX_UNEXPECTED_EXIT_CODE;
8731}
8732
8733
8734/**
8735 * VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
8736 */
8737HMVMX_EXIT_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8738{
8739 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8740 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
8741 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8742}
8743
8744
8745/**
8746 * VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
8747 */
8748HMVMX_EXIT_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8749{
8750 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8751 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
8752 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8753}
8754
8755
8756/**
8757 * VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
8758 */
8759HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8760{
8761 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8762 PVM pVM = pVCpu->CTX_SUFF(pVM);
8763 int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
8764 if (RT_LIKELY(rc == VINF_SUCCESS))
8765 {
8766 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8767 Assert(pVmxTransient->cbInstr == 2);
8768 }
8769 else
8770 {
8771 AssertMsgFailed(("hmR0VmxExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
8772 rc = VERR_EM_INTERPRETER;
8773 }
8774 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
8775 return rc;
8776}
8777
8778
8779/**
8780 * VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
8781 */
8782HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8783{
8784 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8785 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
8786 AssertRCReturn(rc, rc);
8787
8788 if (pMixedCtx->cr4 & X86_CR4_SMXE)
8789 return VINF_EM_RAW_EMULATE_INSTR;
8790
8791 AssertMsgFailed(("hmR0VmxExitGetsec: unexpected VM-exit when CR4.SMXE is 0.\n"));
8792 pVCpu->hm.s.u32HMError = VMX_EXIT_GETSEC;
8793 return VERR_VMX_UNEXPECTED_EXIT_CODE;
8794}
8795
8796
8797/**
8798 * VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
8799 */
8800HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8801{
8802 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8803 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx); /** @todo review if CR4 is really required by EM. */
8804 AssertRCReturn(rc, rc);
8805
8806 PVM pVM = pVCpu->CTX_SUFF(pVM);
8807 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
8808 if (RT_LIKELY(rc == VINF_SUCCESS))
8809 {
8810 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8811 Assert(pVmxTransient->cbInstr == 2);
8812 /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
8813 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
8814 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
8815 }
8816 else
8817 {
8818 AssertMsgFailed(("hmR0VmxExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
8819 rc = VERR_EM_INTERPRETER;
8820 }
8821 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
8822 return rc;
8823}
8824
8825
8826/**
8827 * VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
8828 */
8829HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8830{
8831 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8832 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx); /** @todo review if CR4 is really required by EM. */
8833 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx); /* For MSR_K8_TSC_AUX */
8834 AssertRCReturn(rc, rc);
8835
8836 PVM pVM = pVCpu->CTX_SUFF(pVM);
8837 rc = EMInterpretRdtscp(pVM, pVCpu, pMixedCtx);
8838 if (RT_LIKELY(rc == VINF_SUCCESS))
8839 {
8840 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8841 Assert(pVmxTransient->cbInstr == 3);
8842 /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
8843 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
8844 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
8845 }
8846 else
8847 {
8848 AssertMsgFailed(("hmR0VmxExitRdtscp: EMInterpretRdtscp failed with %Rrc\n", rc));
8849 rc = VERR_EM_INTERPRETER;
8850 }
8851 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
8852 return rc;
8853}
8854
8855
8856/**
8857 * VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
8858 */
8859HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8860{
8861 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8862 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx); /** @todo review if CR4 is really required by EM. */
8863 rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx); /** @todo review if CR0 is really required by EM. */
8864 AssertRCReturn(rc, rc);
8865
8866 PVM pVM = pVCpu->CTX_SUFF(pVM);
8867 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
8868 if (RT_LIKELY(rc == VINF_SUCCESS))
8869 {
8870 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8871 Assert(pVmxTransient->cbInstr == 2);
8872 }
8873 else
8874 {
8875 AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
8876 rc = VERR_EM_INTERPRETER;
8877 }
8878 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
8879 return rc;
8880}
8881
8882
8883/**
8884 * VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
8885 */
8886HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8887{
8888 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8889 PVM pVM = pVCpu->CTX_SUFF(pVM);
8890 Assert(!pVM->hm.s.fNestedPaging);
8891
8892 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
8893 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
8894 AssertRCReturn(rc, rc);
8895
8896 VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), pVmxTransient->uExitQualification);
8897 rc = VBOXSTRICTRC_VAL(rc2);
8898 if (RT_LIKELY(rc == VINF_SUCCESS))
8899 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8900 else
8901 {
8902 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitInvlpg: EMInterpretInvlpg %#RX64 failed with %Rrc\n",
8903 pVmxTransient->uExitQualification, rc));
8904 }
8905 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
8906 return rc;
8907}
8908
8909
8910/**
8911 * VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
8912 */
8913HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8914{
8915 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8916 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
8917 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
8918 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
8919 AssertRCReturn(rc, rc);
8920
8921 PVM pVM = pVCpu->CTX_SUFF(pVM);
8922 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
8923 if (RT_LIKELY(rc == VINF_SUCCESS))
8924 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8925 else
8926 {
8927 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
8928 rc = VERR_EM_INTERPRETER;
8929 }
8930 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
8931 return rc;
8932}
8933
8934
8935/**
8936 * VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
8937 */
8938HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8939{
8940 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
8941 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
8942 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
8943 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
8944 AssertRCReturn(rc, rc);
8945
8946 PVM pVM = pVCpu->CTX_SUFF(pVM);
8947 VBOXSTRICTRC rc2 = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
8948 rc = VBOXSTRICTRC_VAL(rc2);
8949 if (RT_LIKELY( rc == VINF_SUCCESS
8950 || rc == VINF_EM_HALT))
8951 {
8952 int rc3 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
8953 AssertRCReturn(rc3, rc3);
8954
8955 if ( rc == VINF_EM_HALT
8956 && EMShouldContinueAfterHalt(pVCpu, pMixedCtx))
8957 {
8958 rc = VINF_SUCCESS;
8959 }
8960 }
8961 else
8962 {
8963 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
8964 rc = VERR_EM_INTERPRETER;
8965 }
8966 AssertMsg(rc == VINF_SUCCESS || rc == VINF_EM_HALT || rc == VERR_EM_INTERPRETER,
8967 ("hmR0VmxExitMwait: failed, invalid error code %Rrc\n", rc));
8968 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
8969 return rc;
8970}
8971
8972
8973/**
8974 * VM-exit handler for RSM (VMX_EXIT_RSM). Unconditional VM-exit.
8975 */
8976HMVMX_EXIT_DECL hmR0VmxExitRsm(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8977{
8978 /*
8979 * Execution of RSM outside of SMM mode causes #UD regardless of VMX root or VMX non-root mode. In theory, we should never
8980 * get this VM-exit. This can happen only if dual-monitor treatment of SMI and VMX is enabled, which can (only?) be done by
8981 * executing VMCALL in VMX root operation. If we get here, something funny is going on.
8982 * See Intel spec. "33.15.5 Enabling the Dual-Monitor Treatment".
8983 */
8984 AssertMsgFailed(("Unexpected RSM VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
8985 pVCpu->hm.s.u32HMError = VMX_EXIT_RSM;
8986 return VERR_VMX_UNEXPECTED_EXIT_CODE;
8987}
8988
8989
8990/**
8991 * VM-exit handler for SMI (VMX_EXIT_SMI). Unconditional VM-exit.
8992 */
8993HMVMX_EXIT_DECL hmR0VmxExitSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8994{
8995 /*
8996 * This can only happen if we support dual-monitor treatment of SMI, which can be activated by executing VMCALL in VMX
8997 * root operation. Only an STM (SMM transfer monitor) would get this exit when we (the executive monitor) execute a VMCALL
8998 * in VMX root mode or receive an SMI. If we get here, something funny is going on.
8999 * See Intel spec. "33.15.6 Activating the Dual-Monitor Treatment" and Intel spec. 25.3 "Other Causes of VM-Exits"
9000 */
9001 AssertMsgFailed(("Unexpected SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9002 pVCpu->hm.s.u32HMError = VMX_EXIT_SMI;
9003 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9004}
9005
9006
9007/**
9008 * VM-exit handler for IO SMI (VMX_EXIT_IO_SMI). Unconditional VM-exit.
9009 */
9010HMVMX_EXIT_DECL hmR0VmxExitIoSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9011{
9012 /* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
9013 AssertMsgFailed(("Unexpected IO SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9014 pVCpu->hm.s.u32HMError = VMX_EXIT_IO_SMI;
9015 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9016}
9017
9018
9019/**
9020 * VM-exit handler for SIPI (VMX_EXIT_SIPI). Conditional VM-exit.
9021 */
9022HMVMX_EXIT_DECL hmR0VmxExitSipi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9023{
9024 /*
9025 * SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest activity state is used. We currently
9026 * don't make use of it (see hmR0VmxLoadGuestActivityState()) as our guests don't have direct access to the host LAPIC.
9027 * See Intel spec. 25.3 "Other Causes of VM-exits".
9028 */
9029 AssertMsgFailed(("Unexpected SIPI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9030 pVCpu->hm.s.u32HMError = VMX_EXIT_SIPI;
9031 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9032}
9033
9034
9035/**
9036 * VM-exit handler for INIT signal (VMX_EXIT_INIT_SIGNAL). Unconditional
9037 * VM-exit.
9038 */
9039HMVMX_EXIT_DECL hmR0VmxExitInitSignal(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9040{
9041 /*
9042 * INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
9043 * See Intel spec. 33.14.1 Default Treatment of SMI Delivery" and Intel spec. 29.3 "VMX Instructions" for "VMXON".
9044 *
9045 * It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these VM-exits.
9046 * See Intel spec. "23.8 Restrictions on VMX operation".
9047 */
9048 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9049 return VINF_SUCCESS;
9050}
9051
9052
9053/**
9054 * VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
9055 * VM-exit.
9056 */
9057HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9058{
9059 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9060 return VINF_EM_RESET;
9061}
9062
9063
9064/**
9065 * VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
9066 */
9067HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9068{
9069 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9070 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
9071 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
9072 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
9073 AssertRCReturn(rc, rc);
9074
9075 pMixedCtx->rip++;
9076 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
9077 if (EMShouldContinueAfterHalt(pVCpu, pMixedCtx)) /* Requires eflags. */
9078 rc = VINF_SUCCESS;
9079 else
9080 rc = VINF_EM_HALT;
9081
9082 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
9083 return rc;
9084}
9085
9086
9087/**
9088 * VM-exit handler for instructions that result in a #UD exception delivered to
9089 * the guest.
9090 */
9091HMVMX_EXIT_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9092{
9093 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9094 hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx);
9095 return VINF_SUCCESS;
9096}
9097
9098
9099/**
9100 * VM-exit handler for expiry of the VMX preemption timer.
9101 */
9102HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9103{
9104 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9105
9106 /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
9107 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9108
9109 /* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
9110 PVM pVM = pVCpu->CTX_SUFF(pVM);
9111 bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
9112 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
9113 return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
9114}
9115
9116
9117/**
9118 * VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
9119 */
9120HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9121{
9122 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9123
9124 /* We expose XSETBV to the guest, fallback to the recompiler for emulation. */
9125 /** @todo check if XSETBV is supported by the recompiler. */
9126 return VERR_EM_INTERPRETER;
9127}
9128
9129
9130/**
9131 * VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
9132 */
9133HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9134{
9135 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9136
9137 /* The guest should not invalidate the host CPU's TLBs, fallback to recompiler. */
9138 /** @todo implement EMInterpretInvpcid() */
9139 return VERR_EM_INTERPRETER;
9140}
9141
9142
9143/**
9144 * VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE).
9145 * Error VM-exit.
9146 */
9147HMVMX_EXIT_DECL hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9148{
9149 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9150 AssertRCReturn(rc, rc);
9151
9152 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
9153 NOREF(uInvalidReason);
9154
9155#ifdef VBOX_STRICT
9156 uint32_t uIntrState;
9157 HMVMXHCUINTREG uHCReg;
9158 uint64_t u64Val;
9159 uint32_t u32Val;
9160
9161 rc = hmR0VmxReadEntryIntrInfoVmcs(pVmxTransient);
9162 rc |= hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
9163 rc |= hmR0VmxReadEntryInstrLenVmcs(pVCpu, pVmxTransient);
9164 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
9165 AssertRCReturn(rc, rc);
9166
9167 Log4(("uInvalidReason %u\n", uInvalidReason));
9168 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntrInfo));
9169 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
9170 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
9171 Log4(("VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE %#RX32\n", uIntrState));
9172
9173 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val); AssertRC(rc);
9174 Log4(("VMX_VMCS_GUEST_CR0 %#RX32\n", u32Val));
9175 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
9176 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
9177 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
9178 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
9179 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
9180 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
9181 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
9182 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
9183 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
9184 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
9185#endif
9186
9187 PVM pVM = pVCpu->CTX_SUFF(pVM);
9188 HMDumpRegs(pVM, pVCpu, pMixedCtx);
9189
9190 return VERR_VMX_INVALID_GUEST_STATE;
9191}
9192
9193
9194/**
9195 * VM-exit handler for VM-entry failure due to an MSR-load
9196 * (VMX_EXIT_ERR_MSR_LOAD). Error VM-exit.
9197 */
9198HMVMX_EXIT_DECL hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9199{
9200 AssertMsgFailed(("Unexpected MSR-load exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9201 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9202}
9203
9204
9205/**
9206 * VM-exit handler for VM-entry failure due to a machine-check event
9207 * (VMX_EXIT_ERR_MACHINE_CHECK). Error VM-exit.
9208 */
9209HMVMX_EXIT_DECL hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9210{
9211 AssertMsgFailed(("Unexpected machine-check event exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9212 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9213}
9214
9215
9216/**
9217 * VM-exit handler for all undefined reasons. Should never ever happen.. in
9218 * theory.
9219 */
9220HMVMX_EXIT_DECL hmR0VmxExitErrUndefined(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9221{
9222 AssertMsgFailed(("Huh!? Undefined VM-exit reason %d. pVCpu=%p pMixedCtx=%p\n", pVmxTransient->uExitReason, pVCpu, pMixedCtx));
9223 return VERR_VMX_UNDEFINED_EXIT_CODE;
9224}
9225
9226
9227/**
9228 * VM-exit handler for XDTR (LGDT, SGDT, LIDT, SIDT) accesses
9229 * (VMX_EXIT_XDTR_ACCESS) and LDT and TR access (LLDT, LTR, SLDT, STR).
9230 * Conditional VM-exit.
9231 */
9232HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9233{
9234 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9235
9236 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */
9237 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
9238 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
9239 return VERR_EM_INTERPRETER;
9240 AssertMsgFailed(("Unexpected XDTR access. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9241 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9242}
9243
9244
9245/**
9246 * VM-exit handler for RDRAND (VMX_EXIT_RDRAND). Conditional VM-exit.
9247 */
9248HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9249{
9250 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9251
9252 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */
9253 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdrand);
9254 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT)
9255 return VERR_EM_INTERPRETER;
9256 AssertMsgFailed(("Unexpected RDRAND exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9257 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9258}
9259
9260
9261/**
9262 * VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
9263 */
9264HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9265{
9266 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9267
9268 /* EMInterpretRdmsr() requires CR0, Eflags and SS segment register. */
9269 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
9270 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
9271 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
9272 AssertRCReturn(rc, rc);
9273 Log4(("CS:RIP=%04x:%#RX64 ECX=%X\n", pMixedCtx->cs.Sel, pMixedCtx->rip, pMixedCtx->ecx));
9274
9275 PVM pVM = pVCpu->CTX_SUFF(pVM);
9276 rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
9277 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER,
9278 ("hmR0VmxExitRdmsr: failed, invalid error code %Rrc\n", rc));
9279 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
9280
9281 if (RT_LIKELY(rc == VINF_SUCCESS))
9282 {
9283 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
9284 Assert(pVmxTransient->cbInstr == 2);
9285 }
9286 return rc;
9287}
9288
9289
9290/**
9291 * VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
9292 */
9293HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9294{
9295 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9296 PVM pVM = pVCpu->CTX_SUFF(pVM);
9297 int rc = VINF_SUCCESS;
9298
9299 /* EMInterpretWrmsr() requires CR0, EFLAGS and SS segment register. */
9300 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
9301 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
9302 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
9303 AssertRCReturn(rc, rc);
9304 Log4(("ecx=%#RX32\n", pMixedCtx->ecx));
9305
9306 rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
9307 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER, ("hmR0VmxExitWrmsr: failed, invalid error code %Rrc\n", rc));
9308 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
9309
9310 if (RT_LIKELY(rc == VINF_SUCCESS))
9311 {
9312 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
9313
9314 /* If this is an X2APIC WRMSR access, update the APIC state as well. */
9315 if ( pMixedCtx->ecx >= MSR_IA32_X2APIC_START
9316 && pMixedCtx->ecx <= MSR_IA32_X2APIC_END)
9317 {
9318 /* We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
9319 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before
9320 EMInterpretWrmsr() changes it. */
9321 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
9322 }
9323 else if (pMixedCtx->ecx == MSR_K6_EFER) /* EFER is the only MSR we auto-load but don't allow write-passthrough. */
9324 {
9325 rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
9326 AssertRCReturn(rc, rc);
9327 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_AUTO_MSRS;
9328 }
9329 else if (pMixedCtx->ecx == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
9330 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9331
9332 /* Update MSRs that are part of the VMCS when MSR-bitmaps are not supported. */
9333 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
9334 {
9335 switch (pMixedCtx->ecx)
9336 {
9337 case MSR_IA32_SYSENTER_CS: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_CS_MSR; break;
9338 case MSR_IA32_SYSENTER_EIP: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_EIP_MSR; break;
9339 case MSR_IA32_SYSENTER_ESP: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SYSENTER_ESP_MSR; break;
9340 case MSR_K8_FS_BASE: /* no break */
9341 case MSR_K8_GS_BASE: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_SEGMENT_REGS; break;
9342 case MSR_K8_KERNEL_GS_BASE: pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_AUTO_MSRS; break;
9343 }
9344 }
9345#ifdef VBOX_STRICT
9346 else
9347 {
9348 /* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
9349 switch (pMixedCtx->ecx)
9350 {
9351 case MSR_IA32_SYSENTER_CS:
9352 case MSR_IA32_SYSENTER_EIP:
9353 case MSR_IA32_SYSENTER_ESP:
9354 case MSR_K8_FS_BASE:
9355 case MSR_K8_GS_BASE:
9356 {
9357 AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", pMixedCtx->ecx));
9358 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9359 }
9360
9361 case MSR_K8_LSTAR:
9362 case MSR_K6_STAR:
9363 case MSR_K8_SF_MASK:
9364 case MSR_K8_TSC_AUX:
9365 case MSR_K8_KERNEL_GS_BASE:
9366 {
9367 AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
9368 pMixedCtx->ecx));
9369 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9370 }
9371 }
9372 }
9373#endif /* VBOX_STRICT */
9374 }
9375 return rc;
9376}
9377
9378
9379/**
9380 * VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
9381 */
9382HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9383{
9384 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9385
9386 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT. */
9387 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
9388 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT)
9389 return VERR_EM_INTERPRETER;
9390 AssertMsgFailed(("Unexpected PAUSE exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9391 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9392}
9393
9394
9395/**
9396 * VM-exit handler for when the TPR value is lowered below the specified
9397 * threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
9398 */
9399HMVMX_EXIT_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9400{
9401 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9402 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
9403
9404 /*
9405 * The TPR has already been updated, see hmR0VMXPostRunGuest(). RIP is also updated as part of the VM-exit by VT-x. Update
9406 * the threshold in the VMCS, deliver the pending interrupt via hmR0VmxPreRunGuest()->hmR0VmxInjectEvent() and
9407 * resume guest execution.
9408 */
9409 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
9410 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
9411 return VINF_SUCCESS;
9412}
9413
9414
9415/**
9416 * VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
9417 * VM-exit.
9418 *
9419 * @retval VINF_SUCCESS when guest execution can continue.
9420 * @retval VINF_PGM_CHANGE_MODE when shadow paging mode changed, back to ring-3.
9421 * @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
9422 * @retval VERR_EM_INTERPRETER when something unexpected happened, fallback to
9423 * recompiler.
9424 */
9425HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9426{
9427 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9428 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
9429 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9430 AssertRCReturn(rc, rc);
9431
9432 const RTGCUINTPTR uExitQualification = pVmxTransient->uExitQualification;
9433 const uint32_t uAccessType = VMX_EXIT_QUALIFICATION_CRX_ACCESS(uExitQualification);
9434 PVM pVM = pVCpu->CTX_SUFF(pVM);
9435 switch (uAccessType)
9436 {
9437 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE: /* MOV to CRx */
9438 {
9439#if 0
9440 /* EMInterpretCRxWrite() references a lot of guest state (EFER, RFLAGS, Segment Registers, etc.) Sync entire state */
9441 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9442#else
9443 rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
9444 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
9445 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
9446#endif
9447 AssertRCReturn(rc, rc);
9448
9449 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
9450 VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification),
9451 VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification));
9452 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
9453
9454 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification))
9455 {
9456 case 0: /* CR0 */
9457 Log4(("CRX CR0 write rc=%d CR0=%#RX64\n", rc, pMixedCtx->cr0));
9458 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
9459 break;
9460 case 2: /* C2 **/
9461 /* Nothing to do here, CR2 it's not part of the VMCS. */
9462 break;
9463 case 3: /* CR3 */
9464 Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx));
9465 Log4(("CRX CR3 write rc=%d CR3=%#RX64\n", rc, pMixedCtx->cr3));
9466 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR3;
9467 break;
9468 case 4: /* CR4 */
9469 Log4(("CRX CR4 write rc=%d CR4=%#RX64\n", rc, pMixedCtx->cr4));
9470 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR4;
9471 break;
9472 case 8: /* CR8 */
9473 Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
9474 /* CR8 contains the APIC TPR. Was updated by EMInterpretCRxWrite(). */
9475 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_VMX_GUEST_APIC_STATE;
9476 break;
9477 default:
9478 AssertMsgFailed(("Invalid CRx register %#x\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)));
9479 break;
9480 }
9481
9482 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
9483 break;
9484 }
9485
9486 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ: /* MOV from CRx */
9487 {
9488 /* EMInterpretCRxRead() requires EFER MSR, CS. */
9489 rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
9490 AssertRCReturn(rc, rc);
9491 Assert( !pVM->hm.s.fNestedPaging
9492 || !CPUMIsGuestPagingEnabledEx(pMixedCtx)
9493 || VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 3);
9494
9495 /* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
9496 Assert( VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 8
9497 || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
9498
9499 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
9500 VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification),
9501 VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification));
9502 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
9503 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
9504 Log4(("CRX CR%d Read access rc=%d\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification), rc));
9505 break;
9506 }
9507
9508 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */
9509 {
9510 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
9511 AssertRCReturn(rc, rc);
9512 rc = EMInterpretCLTS(pVM, pVCpu);
9513 AssertRCReturn(rc, rc);
9514 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
9515 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
9516 Log4(("CRX CLTS write rc=%d\n", rc));
9517 break;
9518 }
9519
9520 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
9521 {
9522 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
9523 AssertRCReturn(rc, rc);
9524 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification));
9525 if (RT_LIKELY(rc == VINF_SUCCESS))
9526 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
9527 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
9528 Log4(("CRX LMSW write rc=%d\n", rc));
9529 break;
9530 }
9531
9532 default:
9533 {
9534 AssertMsgFailed(("Invalid access-type in Mov CRx exit qualification %#x\n", uAccessType));
9535 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
9536 }
9537 }
9538
9539 /* Validate possible error codes. */
9540 Assert(rc == VINF_SUCCESS || rc == VINF_PGM_CHANGE_MODE || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_SYNC_CR3
9541 || rc == VERR_VMX_UNEXPECTED_EXCEPTION);
9542 if (RT_SUCCESS(rc))
9543 {
9544 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
9545 AssertRCReturn(rc2, rc2);
9546 }
9547
9548 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
9549 return rc;
9550}
9551
9552
9553/**
9554 * VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
9555 * VM-exit.
9556 */
9557HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9558{
9559 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9560 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
9561
9562 int rc2 = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9563 rc2 |= hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
9564 rc2 |= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
9565 rc2 |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* Eflag checks in EMInterpretDisasCurrent(). */
9566 rc2 |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx); /* CR0 checks & PGM* in EMInterpretDisasCurrent(). */
9567 rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* SELM checks in EMInterpretDisasCurrent(). */
9568 /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
9569 AssertRCReturn(rc2, rc2);
9570
9571 /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
9572 uint32_t uIOPort = VMX_EXIT_QUALIFICATION_IO_PORT(pVmxTransient->uExitQualification);
9573 uint8_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(pVmxTransient->uExitQualification);
9574 bool fIOWrite = ( VMX_EXIT_QUALIFICATION_IO_DIRECTION(pVmxTransient->uExitQualification)
9575 == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
9576 bool fIOString = VMX_EXIT_QUALIFICATION_IO_IS_STRING(pVmxTransient->uExitQualification);
9577 AssertReturn(uIOWidth <= 3 && uIOWidth != 2, VERR_HMVMX_IPE_1);
9578
9579 /* I/O operation lookup arrays. */
9580 static const uint32_t s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses. */
9581 static const uint32_t s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving the result (in AL/AX/EAX). */
9582
9583 VBOXSTRICTRC rcStrict;
9584 const uint32_t cbValue = s_aIOSizes[uIOWidth];
9585 const uint32_t cbInstr = pVmxTransient->cbInstr;
9586 bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
9587 PVM pVM = pVCpu->CTX_SUFF(pVM);
9588 if (fIOString)
9589 {
9590 /*
9591 * INS/OUTS - I/O String instruction.
9592 *
9593 * Use instruction-information if available, otherwise fall back on
9594 * interpreting the instruction.
9595 */
9596 Log4(("CS:RIP=%04x:%#RX64 %#06x/%u %c str\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
9597#if 0 /* Not quite ready, seem iSegReg assertion trigger once... Do we perhaps need to always read that in longjmp / preempt scenario? */
9598 AssertReturn(pMixedCtx->dx == uIOPort, VERR_HMVMX_IPE_2);
9599 if (MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))
9600 {
9601 rc2 = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
9602 /** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
9603 rc2 |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9604 AssertRCReturn(rc2, rc2);
9605 AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_HMVMX_IPE_3);
9606 AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
9607 IEMMODE enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
9608 bool fRep = VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification);
9609 if (fIOWrite)
9610 {
9611 rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
9612 pVmxTransient->ExitInstrInfo.StrIo.iSegReg);
9613 //if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
9614 // hmR0SavePendingIOPortWriteStr(pVCpu, pMixedCtx->rip, cbValue, enmAddrMode, fRep, cbInstr,
9615 // pVmxTransient->ExitInstrInfo.StrIo.iSegReg);
9616 }
9617 else
9618 {
9619 AssertMsgReturn(pVmxTransient->ExitInstrInfo.StrIo.iSegReg == X86_SREG_ES,
9620 ("%#x (%#llx)\n", pVmxTransient->ExitInstrInfo.StrIo.iSegReg, pVmxTransient->ExitInstrInfo.u),
9621 VERR_HMVMX_IPE_4);
9622 rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr);
9623 //if (rcStrict == VINF_IOM_R3_IOPORT_READ)
9624 // hmR0SavePendingIOPortReadStr(pVCpu, pMixedCtx->rip, cbValue, enmAddrMode, fRep, cbInstr);
9625 }
9626 }
9627 else
9628 {
9629 /** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
9630 rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9631 AssertRCReturn(rc2, rc2);
9632 rcStrict = IEMExecOne(pVCpu);
9633 }
9634 /** @todo IEM needs to be setting these flags somehow. */
9635 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
9636 fUpdateRipAlready = true;
9637#else
9638 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
9639 rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
9640 if (RT_SUCCESS(rcStrict))
9641 {
9642 if (fIOWrite)
9643 {
9644 rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
9645 (DISCPUMODE)pDis->uAddrMode, cbValue);
9646 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
9647 }
9648 else
9649 {
9650 rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
9651 (DISCPUMODE)pDis->uAddrMode, cbValue);
9652 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
9653 }
9654 }
9655 else
9656 {
9657 AssertMsg(rcStrict == VERR_EM_INTERPRETER, ("rcStrict=%Rrc RIP %#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->rip));
9658 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
9659 }
9660#endif
9661 }
9662 else
9663 {
9664 /*
9665 * IN/OUT - I/O instruction.
9666 */
9667 Log4(("CS:RIP=%04x:%#RX64 %#06x/%u %c\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
9668 const uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
9669 Assert(!VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification));
9670 if (fIOWrite)
9671 {
9672 rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pMixedCtx->eax & uAndVal, cbValue);
9673 if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
9674 HMR0SavePendingIOPortWrite(pVCpu, pMixedCtx->rip, pMixedCtx->rip + cbInstr, uIOPort, uAndVal, cbValue);
9675 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
9676 }
9677 else
9678 {
9679 uint32_t u32Result = 0;
9680 rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
9681 if (IOM_SUCCESS(rcStrict))
9682 {
9683 /* Save result of I/O IN instr. in AL/AX/EAX. */
9684 pMixedCtx->eax = (pMixedCtx->eax & ~uAndVal) | (u32Result & uAndVal);
9685 }
9686 else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
9687 HMR0SavePendingIOPortRead(pVCpu, pMixedCtx->rip, pMixedCtx->rip + cbInstr, uIOPort, uAndVal, cbValue);
9688 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
9689 }
9690 }
9691
9692 if (IOM_SUCCESS(rcStrict))
9693 {
9694 if (!fUpdateRipAlready)
9695 {
9696 pMixedCtx->rip += cbInstr;
9697 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
9698 }
9699
9700 /*
9701 * If any I/O breakpoints are armed, we need to check if one triggered
9702 * and take appropriate action.
9703 * Note that the I/O breakpoint type is undefined if CR4.DE is 0.
9704 */
9705 rc2 = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
9706 AssertRCReturn(rc2, rc2);
9707
9708 /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
9709 * execution engines about whether hyper BPs and such are pending. */
9710 uint32_t const uDr7 = pMixedCtx->dr[7];
9711 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
9712 && X86_DR7_ANY_RW_IO(uDr7)
9713 && (pMixedCtx->cr4 & X86_CR4_DE))
9714 || DBGFBpIsHwIoArmed(pVM)))
9715 {
9716 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
9717
9718 /* We're playing with the host CPU state here, make sure we don't preempt. */
9719 HM_DISABLE_PREEMPT_IF_NEEDED();
9720 bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /*fDr6*/);
9721
9722 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pMixedCtx, uIOPort, cbValue);
9723 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
9724 {
9725 /* Raise #DB. */
9726 if (fIsGuestDbgActive)
9727 ASMSetDR6(pMixedCtx->dr[6]);
9728 if (pMixedCtx->dr[7] != uDr7)
9729 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
9730
9731 hmR0VmxSetPendingXcptDB(pVCpu, pMixedCtx);
9732 }
9733 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
9734 else if ( rcStrict2 != VINF_SUCCESS
9735 && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
9736 rcStrict = rcStrict2;
9737
9738 HM_RESTORE_PREEMPT_IF_NEEDED();
9739 }
9740 }
9741
9742#ifdef DEBUG
9743 if (rcStrict == VINF_IOM_R3_IOPORT_READ)
9744 Assert(!fIOWrite);
9745 else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
9746 Assert(fIOWrite);
9747 else
9748 {
9749 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
9750 * statuses, that the VMM device and some others may return. See
9751 * IOM_SUCCESS() for guidance. */
9752 AssertMsg( RT_FAILURE(rcStrict)
9753 || rcStrict == VINF_SUCCESS
9754 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
9755 || rcStrict == VINF_EM_DBG_BREAKPOINT
9756 || rcStrict == VINF_EM_RAW_GUEST_TRAP
9757 || rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
9758 }
9759#endif
9760
9761 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
9762 return VBOXSTRICTRC_TODO(rcStrict);
9763}
9764
9765
9766/**
9767 * VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
9768 * VM-exit.
9769 */
9770HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9771{
9772 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9773
9774 /* Check if this task-switch occurred while delivery an event through the guest IDT. */
9775 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9776 AssertRCReturn(rc, rc);
9777 if (VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT)
9778 {
9779 rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
9780 AssertRCReturn(rc, rc);
9781 if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
9782 {
9783 uint32_t uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
9784
9785 /* Software interrupts and exceptions will be regenerated when the recompiler restarts the instruction. */
9786 if ( uIntType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT
9787 && uIntType != VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
9788 && uIntType != VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
9789 {
9790 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
9791 bool fErrorCodeValid = !!VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo);
9792
9793 /* Save it as a pending event and it'll be converted to a TRPM event on the way out to ring-3. */
9794 Assert(!pVCpu->hm.s.Event.fPending);
9795 pVCpu->hm.s.Event.fPending = true;
9796 pVCpu->hm.s.Event.u64IntrInfo = pVmxTransient->uIdtVectoringInfo;
9797 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
9798 AssertRCReturn(rc, rc);
9799 if (fErrorCodeValid)
9800 pVCpu->hm.s.Event.u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
9801 else
9802 pVCpu->hm.s.Event.u32ErrCode = 0;
9803 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
9804 && uVector == X86_XCPT_PF)
9805 {
9806 pVCpu->hm.s.Event.GCPtrFaultAddress = pMixedCtx->cr2;
9807 }
9808
9809 Log4(("Pending event on TaskSwitch uIntType=%#x uVector=%#x\n", uIntType, uVector));
9810 }
9811 }
9812 }
9813
9814 /** @todo Emulate task switch someday, currently just going back to ring-3 for
9815 * emulation. */
9816 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
9817 return VERR_EM_INTERPRETER;
9818}
9819
9820
9821/**
9822 * VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
9823 */
9824HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9825{
9826 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9827 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
9828 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
9829 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
9830 AssertRCReturn(rc, rc);
9831 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
9832 return VINF_EM_DBG_STEPPED;
9833}
9834
9835
9836/**
9837 * VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
9838 */
9839HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9840{
9841 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9842
9843 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
9844 int rc = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
9845 if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT))
9846 return VINF_SUCCESS;
9847 else if (RT_UNLIKELY(rc == VINF_EM_RESET))
9848 return rc;
9849
9850#if 0
9851 /** @todo Investigate if IOMMMIOPhysHandler() requires a lot of state, for now
9852 * just sync the whole thing. */
9853 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9854#else
9855 /* Aggressive state sync. for now. */
9856 rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
9857 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
9858 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
9859#endif
9860 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9861 AssertRCReturn(rc, rc);
9862
9863 /* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
9864 uint32_t uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(pVmxTransient->uExitQualification);
9865 switch (uAccessType)
9866 {
9867 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
9868 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
9869 {
9870 if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
9871 && VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) == 0x80)
9872 {
9873 AssertMsgFailed(("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
9874 }
9875
9876 RTGCPHYS GCPhys = pMixedCtx->msrApicBase; /* Always up-to-date, msrApicBase is not part of the VMCS. */
9877 GCPhys &= PAGE_BASE_GC_MASK;
9878 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification);
9879 PVM pVM = pVCpu->CTX_SUFF(pVM);
9880 Log4(("ApicAccess uAccessType=%#x GCPhys=%#RGv Off=%#x\n", uAccessType, GCPhys,
9881 VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification)));
9882
9883 VBOXSTRICTRC rc2 = IOMMMIOPhysHandler(pVM, pVCpu,
9884 (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW,
9885 CPUMCTX2CORE(pMixedCtx), GCPhys);
9886 rc = VBOXSTRICTRC_VAL(rc2);
9887 Log4(("ApicAccess rc=%d\n", rc));
9888 if ( rc == VINF_SUCCESS
9889 || rc == VERR_PAGE_TABLE_NOT_PRESENT
9890 || rc == VERR_PAGE_NOT_PRESENT)
9891 {
9892 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
9893 | HM_CHANGED_VMX_GUEST_APIC_STATE;
9894 rc = VINF_SUCCESS;
9895 }
9896 break;
9897 }
9898
9899 default:
9900 Log4(("ApicAccess uAccessType=%#x\n", uAccessType));
9901 rc = VINF_EM_RAW_EMULATE_INSTR;
9902 break;
9903 }
9904
9905 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
9906 return rc;
9907}
9908
9909
9910/**
9911 * VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
9912 * VM-exit.
9913 */
9914HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9915{
9916 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
9917
9918 /* We should -not- get this VM-exit if the guest is debugging. */
9919 if (CPUMIsGuestDebugStateActive(pVCpu))
9920 {
9921 AssertMsgFailed(("Unexpected MOV DRx exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
9922 return VERR_VMX_UNEXPECTED_EXIT_CODE;
9923 }
9924
9925 int rc = VERR_INTERNAL_ERROR_5;
9926 if ( !DBGFIsStepping(pVCpu)
9927 && !pVCpu->hm.s.fSingleInstruction
9928 && !CPUMIsHyperDebugStateActive(pVCpu))
9929 {
9930 /* Don't intercept MOV DRx and #DB any more. */
9931 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
9932 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
9933 AssertRCReturn(rc, rc);
9934
9935 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
9936 {
9937#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
9938 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_DB);
9939 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
9940 AssertRCReturn(rc, rc);
9941#endif
9942 }
9943
9944 /* We're playing with the host CPU state here, make sure we can't preempt. */
9945 HM_DISABLE_PREEMPT_IF_NEEDED();
9946
9947 /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
9948 PVM pVM = pVCpu->CTX_SUFF(pVM);
9949 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
9950 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
9951
9952 HM_RESTORE_PREEMPT_IF_NEEDED();
9953
9954#ifdef VBOX_WITH_STATISTICS
9955 rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9956 AssertRCReturn(rc, rc);
9957 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
9958 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
9959 else
9960 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
9961#endif
9962 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
9963 return VINF_SUCCESS;
9964 }
9965
9966 /*
9967 * EMInterpretDRx[Write|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER, CS. EFER is always up-to-date, see
9968 * hmR0VmxSaveGuestAutoLoadStoreMsrs(). Update only the segment registers from the CPU.
9969 */
9970 rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9971 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
9972 AssertRCReturn(rc, rc);
9973 Log4(("CS:RIP=%04x:%#RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
9974
9975 PVM pVM = pVCpu->CTX_SUFF(pVM);
9976 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
9977 {
9978 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
9979 VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification),
9980 VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification));
9981 if (RT_SUCCESS(rc))
9982 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
9983 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
9984 }
9985 else
9986 {
9987 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
9988 VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification),
9989 VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification));
9990 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
9991 }
9992
9993 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
9994 if (RT_SUCCESS(rc))
9995 {
9996 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
9997 AssertRCReturn(rc2, rc2);
9998 }
9999 return rc;
10000}
10001
10002
10003/**
10004 * VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
10005 * Conditional VM-exit.
10006 */
10007HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10008{
10009 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
10010 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
10011
10012 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
10013 int rc = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
10014 if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT))
10015 return VINF_SUCCESS;
10016 else if (RT_UNLIKELY(rc == VINF_EM_RESET))
10017 return rc;
10018
10019 RTGCPHYS GCPhys = 0;
10020 rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
10021
10022#if 0
10023 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
10024#else
10025 /* Aggressive state sync. for now. */
10026 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
10027 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
10028 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
10029#endif
10030 AssertRCReturn(rc, rc);
10031
10032 /*
10033 * If we succeed, resume guest execution.
10034 * If we fail in interpreting the instruction because we couldn't get the guest physical address
10035 * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
10036 * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
10037 * weird case. See @bugref{6043}.
10038 */
10039 PVM pVM = pVCpu->CTX_SUFF(pVM);
10040 VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pMixedCtx), GCPhys, UINT32_MAX);
10041 rc = VBOXSTRICTRC_VAL(rc2);
10042 Log4(("EPT misconfig at %#RGv RIP=%#RX64 rc=%d\n", GCPhys, pMixedCtx->rip, rc));
10043 if ( rc == VINF_SUCCESS
10044 || rc == VERR_PAGE_TABLE_NOT_PRESENT
10045 || rc == VERR_PAGE_NOT_PRESENT)
10046 {
10047 /* Successfully handled MMIO operation. */
10048 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
10049 | HM_CHANGED_VMX_GUEST_APIC_STATE;
10050 rc = VINF_SUCCESS;
10051 }
10052 return rc;
10053}
10054
10055
10056/**
10057 * VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
10058 * VM-exit.
10059 */
10060HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10061{
10062 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
10063 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
10064
10065 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
10066 int rc = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
10067 if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT))
10068 return VINF_SUCCESS;
10069 else if (RT_UNLIKELY(rc == VINF_EM_RESET))
10070 return rc;
10071
10072 RTGCPHYS GCPhys = 0;
10073 rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
10074 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
10075#if 0
10076 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
10077#else
10078 /* Aggressive state sync. for now. */
10079 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
10080 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
10081 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
10082#endif
10083 AssertRCReturn(rc, rc);
10084
10085 /* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
10086 AssertMsg(((pVmxTransient->uExitQualification >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQualification));
10087
10088 RTGCUINT uErrorCode = 0;
10089 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
10090 uErrorCode |= X86_TRAP_PF_ID;
10091 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
10092 uErrorCode |= X86_TRAP_PF_RW;
10093 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
10094 uErrorCode |= X86_TRAP_PF_P;
10095
10096 TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
10097
10098 Log4(("EPT violation %#x at %#RX64 ErrorCode %#x CS:EIP=%04x:%#RX64\n", pVmxTransient->uExitQualification, GCPhys,
10099 uErrorCode, pMixedCtx->cs.Sel, pMixedCtx->rip));
10100
10101 /* Handle the pagefault trap for the nested shadow table. */
10102 PVM pVM = pVCpu->CTX_SUFF(pVM);
10103 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pMixedCtx), GCPhys);
10104 TRPMResetTrap(pVCpu);
10105
10106 /* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
10107 if ( rc == VINF_SUCCESS
10108 || rc == VERR_PAGE_TABLE_NOT_PRESENT
10109 || rc == VERR_PAGE_NOT_PRESENT)
10110 {
10111 /* Successfully synced our nested page tables. */
10112 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
10113 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS;
10114 return VINF_SUCCESS;
10115 }
10116
10117 Log4(("EPT return to ring-3 rc=%d\n"));
10118 return rc;
10119}
10120
10121/** @} */
10122
10123/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
10124/* -=-=-=-=-=-=-=-=-=- VM-exit Exception Handlers -=-=-=-=-=-=-=-=-=-=- */
10125/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
10126
10127/** @name VM-exit exception handlers.
10128 * @{
10129 */
10130
10131/**
10132 * VM-exit exception handler for #MF (Math Fault: floating point exception).
10133 */
10134static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10135{
10136 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
10137 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
10138
10139 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
10140 AssertRCReturn(rc, rc);
10141
10142 if (!(pMixedCtx->cr0 & X86_CR0_NE))
10143 {
10144 /* Old-style FPU error reporting needs some extra work. */
10145 /** @todo don't fall back to the recompiler, but do it manually. */
10146 return VERR_EM_INTERPRETER;
10147 }
10148
10149 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10150 pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode, 0 /* GCPtrFaultAddress */);
10151 return rc;
10152}
10153
10154
10155/**
10156 * VM-exit exception handler for #BP (Breakpoint exception).
10157 */
10158static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10159{
10160 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
10161 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
10162
10163 /** @todo Try optimize this by not saving the entire guest state unless
10164 * really needed. */
10165 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
10166 AssertRCReturn(rc, rc);
10167
10168 PVM pVM = pVCpu->CTX_SUFF(pVM);
10169 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
10170 if (rc == VINF_EM_RAW_GUEST_TRAP)
10171 {
10172 rc = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
10173 rc |= hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
10174 rc |= hmR0VmxReadExitIntrErrorCodeVmcs(pVCpu, pVmxTransient);
10175 AssertRCReturn(rc, rc);
10176
10177 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10178 pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode, 0 /* GCPtrFaultAddress */);
10179 }
10180
10181 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_EM_DBG_BREAKPOINT);
10182 return rc;
10183}
10184
10185
10186/**
10187 * VM-exit exception handler for #DB (Debug exception).
10188 */
10189static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10190{
10191 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
10192 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
10193 Log6(("XcptDB\n"));
10194
10195 /*
10196 * Get the DR6-like values from the exit qualification and pass it to DBGF
10197 * for processing.
10198 */
10199 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
10200 AssertRCReturn(rc, rc);
10201
10202 /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
10203 uint64_t uDR6 = X86_DR6_INIT_VAL;
10204 uDR6 |= ( pVmxTransient->uExitQualification
10205 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3 | X86_DR6_BD | X86_DR6_BS));
10206
10207 rc = DBGFRZTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pMixedCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
10208 if (rc == VINF_EM_RAW_GUEST_TRAP)
10209 {
10210 /*
10211 * The exception was for the guest. Update DR6, DR7.GD and
10212 * IA32_DEBUGCTL.LBR before forwarding it.
10213 * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
10214 */
10215 HM_DISABLE_PREEMPT_IF_NEEDED();
10216
10217 pMixedCtx->dr[6] &= ~X86_DR6_B_MASK;
10218 pMixedCtx->dr[6] |= uDR6;
10219 if (CPUMIsGuestDebugStateActive(pVCpu))
10220 ASMSetDR6(pMixedCtx->dr[6]);
10221
10222 HM_RESTORE_PREEMPT_IF_NEEDED();
10223
10224 rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
10225 AssertRCReturn(rc, rc);
10226
10227 /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
10228 pMixedCtx->dr[7] &= ~X86_DR7_GD;
10229
10230 /* Paranoia. */
10231 pMixedCtx->dr[7] &= ~X86_DR7_RAZ_MASK;
10232 pMixedCtx->dr[7] |= X86_DR7_RA1_MASK;
10233
10234 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pMixedCtx->dr[7]);
10235 AssertRCReturn(rc, rc);
10236
10237 /*
10238 * Raise #DB in the guest.
10239 */
10240 rc = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
10241 rc |= hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
10242 rc |= hmR0VmxReadExitIntrErrorCodeVmcs(pVCpu, pVmxTransient);
10243 AssertRCReturn(rc, rc);
10244 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10245 pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode, 0 /* GCPtrFaultAddress */);
10246 return VINF_SUCCESS;
10247 }
10248
10249 /*
10250 * Not a guest trap, must be a hypervisor related debug event then.
10251 * Update DR6 in case someone is interested in it.
10252 */
10253 AssertMsg(rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
10254 AssertReturn(CPUMIsHyperDebugStateActive(pVCpu), VERR_HM_IPE_5);
10255 CPUMSetHyperDR6(pVCpu, uDR6);
10256
10257 return rc;
10258}
10259
10260
10261/**
10262 * VM-exit exception handler for #NM (Device-not-available exception: floating
10263 * point exception).
10264 */
10265static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10266{
10267 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
10268
10269#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
10270 Assert(!CPUMIsGuestFPUStateActive(pVCpu));
10271#endif
10272
10273 /* We require CR0 and EFER. EFER is always up-to-date. */
10274 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
10275 AssertRCReturn(rc, rc);
10276
10277 /* We're playing with the host CPU state here, have to disable preemption. */
10278 HM_DISABLE_PREEMPT_IF_NEEDED();
10279
10280 /* Lazy FPU loading; load the guest-FPU state transparently and continue execution of the guest. */
10281 PVM pVM = pVCpu->CTX_SUFF(pVM);
10282 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pMixedCtx);
10283 if (rc == VINF_SUCCESS)
10284 {
10285 Assert(CPUMIsGuestFPUStateActive(pVCpu));
10286 HM_RESTORE_PREEMPT_IF_NEEDED();
10287
10288 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_CR0;
10289 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
10290 return VINF_SUCCESS;
10291 }
10292
10293 HM_RESTORE_PREEMPT_IF_NEEDED();
10294
10295 /* Forward #NM to the guest. */
10296 Assert(rc == VINF_EM_RAW_GUEST_TRAP);
10297 rc = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
10298 AssertRCReturn(rc, rc);
10299 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10300 pVmxTransient->cbInstr, 0 /* error code */, 0 /* GCPtrFaultAddress */);
10301 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
10302 return rc;
10303}
10304
10305
10306/**
10307 * VM-exit exception handler for #GP (General-protection exception).
10308 *
10309 * @remarks Requires pVmxTransient->uExitIntrInfo to be up-to-date.
10310 */
10311static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10312{
10313 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
10314 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
10315
10316 int rc = VERR_INTERNAL_ERROR_5;
10317 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
10318 {
10319#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
10320 /* If the guest is not in real-mode or we have unrestricted execution support, reflect #GP to the guest. */
10321 rc = hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
10322 rc |= hmR0VmxReadExitIntrErrorCodeVmcs(pVCpu, pVmxTransient);
10323 rc |= hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
10324 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
10325 AssertRCReturn(rc, rc);
10326 Log4(("#GP Gst: RIP %#RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u\n", pMixedCtx->rip, pVmxTransient->uExitIntrErrorCode,
10327 pMixedCtx->cr0, CPUMGetGuestCPL(pVCpu)));
10328 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10329 pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode, 0 /* GCPtrFaultAddress */);
10330 return rc;
10331#else
10332 /* We don't intercept #GP. */
10333 AssertMsgFailed(("Unexpected VM-exit caused by #GP exception\n"));
10334 return VERR_VMX_UNEXPECTED_EXCEPTION;
10335#endif
10336 }
10337
10338 Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
10339 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest);
10340
10341 /* EMInterpretDisasCurrent() requires a lot of the state, save the entire state. */
10342 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
10343 AssertRCReturn(rc, rc);
10344
10345 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
10346 uint32_t cbOp = 0;
10347 PVM pVM = pVCpu->CTX_SUFF(pVM);
10348 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
10349 if (RT_SUCCESS(rc))
10350 {
10351 rc = VINF_SUCCESS;
10352 Assert(cbOp == pDis->cbInstr);
10353 Log4(("#GP Disas OpCode=%u CS:EIP %04x:%#RX64\n", pDis->pCurInstr->uOpcode, pMixedCtx->cs.Sel, pMixedCtx->rip));
10354 switch (pDis->pCurInstr->uOpcode)
10355 {
10356 case OP_CLI:
10357 {
10358 pMixedCtx->eflags.Bits.u1IF = 0;
10359 pMixedCtx->rip += pDis->cbInstr;
10360 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS;
10361 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
10362 break;
10363 }
10364
10365 case OP_STI:
10366 {
10367 pMixedCtx->eflags.Bits.u1IF = 1;
10368 pMixedCtx->rip += pDis->cbInstr;
10369 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
10370 Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
10371 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS;
10372 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
10373 break;
10374 }
10375
10376 case OP_HLT:
10377 {
10378 rc = VINF_EM_HALT;
10379 pMixedCtx->rip += pDis->cbInstr;
10380 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP;
10381 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
10382 break;
10383 }
10384
10385 case OP_POPF:
10386 {
10387 Log4(("POPF CS:RIP %04x:%#RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
10388 uint32_t cbParm = 0;
10389 uint32_t uMask = 0;
10390 if (pDis->fPrefix & DISPREFIX_OPSIZE)
10391 {
10392 cbParm = 4;
10393 uMask = 0xffffffff;
10394 }
10395 else
10396 {
10397 cbParm = 2;
10398 uMask = 0xffff;
10399 }
10400
10401 /* Get the stack pointer & pop the contents of the stack onto Eflags. */
10402 RTGCPTR GCPtrStack = 0;
10403 X86EFLAGS Eflags;
10404 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
10405 &GCPtrStack);
10406 if (RT_SUCCESS(rc))
10407 {
10408 Assert(sizeof(Eflags.u32) >= cbParm);
10409 Eflags.u32 = 0;
10410 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u32, cbParm);
10411 }
10412 if (RT_FAILURE(rc))
10413 {
10414 rc = VERR_EM_INTERPRETER;
10415 break;
10416 }
10417 Log4(("POPF %#x -> %#RX64 mask=%#x RIP=%#RX64\n", Eflags.u, pMixedCtx->rsp, uMask, pMixedCtx->rip));
10418 pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ~(X86_EFL_POPF_BITS & uMask))
10419 | (Eflags.u32 & X86_EFL_POPF_BITS & uMask);
10420 /* The RF bit is always cleared by POPF; see Intel Instruction reference for POPF. */
10421 pMixedCtx->eflags.Bits.u1RF = 0;
10422 pMixedCtx->esp += cbParm;
10423 pMixedCtx->esp &= uMask;
10424 pMixedCtx->rip += pDis->cbInstr;
10425 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS;
10426 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPopf);
10427 break;
10428 }
10429
10430 case OP_PUSHF:
10431 {
10432 uint32_t cbParm = 0;
10433 uint32_t uMask = 0;
10434 if (pDis->fPrefix & DISPREFIX_OPSIZE)
10435 {
10436 cbParm = 4;
10437 uMask = 0xffffffff;
10438 }
10439 else
10440 {
10441 cbParm = 2;
10442 uMask = 0xffff;
10443 }
10444
10445 /* Get the stack pointer & push the contents of eflags onto the stack. */
10446 RTGCPTR GCPtrStack = 0;
10447 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), (pMixedCtx->esp - cbParm) & uMask,
10448 SELMTOFLAT_FLAGS_CPL0, &GCPtrStack);
10449 if (RT_FAILURE(rc))
10450 {
10451 rc = VERR_EM_INTERPRETER;
10452 break;
10453 }
10454 X86EFLAGS Eflags = pMixedCtx->eflags;
10455 /* The RF & VM bits are cleared on image stored on stack; see Intel Instruction reference for PUSHF. */
10456 Eflags.Bits.u1RF = 0;
10457 Eflags.Bits.u1VM = 0;
10458
10459 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u, cbParm);
10460 if (RT_FAILURE(rc))
10461 {
10462 rc = VERR_EM_INTERPRETER;
10463 break;
10464 }
10465 Log4(("PUSHF %#x -> %#RGv\n", Eflags.u, GCPtrStack));
10466 pMixedCtx->esp -= cbParm;
10467 pMixedCtx->esp &= uMask;
10468 pMixedCtx->rip += pDis->cbInstr;
10469 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP;
10470 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPushf);
10471 break;
10472 }
10473
10474 case OP_IRET:
10475 {
10476 /** @todo Handle 32-bit operand sizes and check stack limits. See Intel
10477 * instruction reference. */
10478 RTGCPTR GCPtrStack = 0;
10479 uint32_t uMask = 0xffff;
10480 uint16_t aIretFrame[3];
10481 if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
10482 {
10483 rc = VERR_EM_INTERPRETER;
10484 break;
10485 }
10486 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
10487 &GCPtrStack);
10488 if (RT_SUCCESS(rc))
10489 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
10490 if (RT_FAILURE(rc))
10491 {
10492 rc = VERR_EM_INTERPRETER;
10493 break;
10494 }
10495 pMixedCtx->eip = 0;
10496 pMixedCtx->ip = aIretFrame[0];
10497 pMixedCtx->cs.Sel = aIretFrame[1];
10498 pMixedCtx->cs.ValidSel = aIretFrame[1];
10499 pMixedCtx->cs.u64Base = (uint64_t)pMixedCtx->cs.Sel << 4;
10500 pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ~(X86_EFL_POPF_BITS & uMask))
10501 | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
10502 pMixedCtx->sp += sizeof(aIretFrame);
10503 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_SEGMENT_REGS | HM_CHANGED_GUEST_RSP
10504 | HM_CHANGED_GUEST_RFLAGS;
10505 Log4(("IRET %#RX32 to %04x:%x\n", GCPtrStack, pMixedCtx->cs.Sel, pMixedCtx->ip));
10506 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIret);
10507 break;
10508 }
10509
10510 case OP_INT:
10511 {
10512 uint16_t uVector = pDis->Param1.uValue & 0xff;
10513 hmR0VmxSetPendingIntN(pVCpu, pMixedCtx, uVector, pDis->cbInstr);
10514 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
10515 break;
10516 }
10517
10518 case OP_INTO:
10519 {
10520 if (pMixedCtx->eflags.Bits.u1OF)
10521 {
10522 hmR0VmxSetPendingXcptOF(pVCpu, pMixedCtx, pDis->cbInstr);
10523 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
10524 }
10525 break;
10526 }
10527
10528 default:
10529 {
10530 VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pMixedCtx), 0 /* pvFault */,
10531 EMCODETYPE_SUPERVISOR);
10532 rc = VBOXSTRICTRC_VAL(rc2);
10533 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
10534 Log4(("#GP rc=%Rrc\n", rc));
10535 break;
10536 }
10537 }
10538 }
10539 else
10540 rc = VERR_EM_INTERPRETER;
10541
10542 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT,
10543 ("#GP Unexpected rc=%Rrc\n", rc));
10544 return rc;
10545}
10546
10547
10548/**
10549 * VM-exit exception handler wrapper for generic exceptions. Simply re-injects
10550 * the exception reported in the VMX transient structure back into the VM.
10551 *
10552 * @remarks Requires uExitIntrInfo in the VMX transient structure to be
10553 * up-to-date.
10554 */
10555static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10556{
10557 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
10558
10559 /* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in
10560 hmR0VmxCheckExitDueToEventDelivery(). */
10561 int rc = hmR0VmxReadExitIntrErrorCodeVmcs(pVCpu, pVmxTransient);
10562 rc |= hmR0VmxReadExitInstrLenVmcs(pVCpu, pVmxTransient);
10563 AssertRCReturn(rc, rc);
10564 Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
10565
10566 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10567 pVmxTransient->cbInstr, pVmxTransient->uExitIntrErrorCode, 0 /* GCPtrFaultAddress */);
10568 return VINF_SUCCESS;
10569}
10570
10571
10572/**
10573 * VM-exit exception handler for #PF (Page-fault exception).
10574 */
10575static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10576{
10577 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
10578 PVM pVM = pVCpu->CTX_SUFF(pVM);
10579 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
10580 rc |= hmR0VmxReadExitIntrInfoVmcs(pVCpu, pVmxTransient);
10581 rc |= hmR0VmxReadExitIntrErrorCodeVmcs(pVCpu, pVmxTransient);
10582 AssertRCReturn(rc, rc);
10583
10584#if defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) || defined(HMVMX_ALWAYS_TRAP_PF)
10585 if (pVM->hm.s.fNestedPaging)
10586 {
10587 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
10588 if (RT_LIKELY(!pVmxTransient->fVectoringPF))
10589 {
10590 pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
10591 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10592 0 /* cbInstr */, pVmxTransient->uExitIntrErrorCode, pVmxTransient->uExitQualification);
10593 }
10594 else
10595 {
10596 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
10597 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
10598 Log4(("Pending #DF due to vectoring #PF. NP\n"));
10599 }
10600 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
10601 return rc;
10602 }
10603#else
10604 Assert(!pVM->hm.s.fNestedPaging);
10605#endif
10606
10607 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
10608 AssertRCReturn(rc, rc);
10609
10610 Log4(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQualification,
10611 pMixedCtx->cs.Sel, pMixedCtx->rip, pVmxTransient->uExitIntrErrorCode, pMixedCtx->cr3));
10612
10613 TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQualification, (RTGCUINT)pVmxTransient->uExitIntrErrorCode);
10614 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntrErrorCode, CPUMCTX2CORE(pMixedCtx),
10615 (RTGCPTR)pVmxTransient->uExitQualification);
10616
10617 Log4(("#PF: rc=%Rrc\n", rc));
10618 if (rc == VINF_SUCCESS)
10619 {
10620 /* Successfully synced shadow pages tables or emulated an MMIO instruction. */
10621 /** @todo this isn't quite right, what if guest does lgdt with some MMIO
10622 * memory? We don't update the whole state here... */
10623 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
10624 | HM_CHANGED_VMX_GUEST_APIC_STATE;
10625 TRPMResetTrap(pVCpu);
10626 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
10627 return rc;
10628 }
10629 else if (rc == VINF_EM_RAW_GUEST_TRAP)
10630 {
10631 if (!pVmxTransient->fVectoringPF)
10632 {
10633 /* It's a guest page fault and needs to be reflected to the guest. */
10634 uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);
10635 TRPMResetTrap(pVCpu);
10636 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
10637 pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
10638 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntrInfo),
10639 0 /* cbInstr */, uGstErrorCode, pVmxTransient->uExitQualification);
10640 }
10641 else
10642 {
10643 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
10644 TRPMResetTrap(pVCpu);
10645 pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
10646 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
10647 Log4(("#PF: Pending #DF due to vectoring #PF\n"));
10648 }
10649
10650 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
10651 return VINF_SUCCESS;
10652 }
10653
10654 TRPMResetTrap(pVCpu);
10655 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
10656 return rc;
10657}
10658
10659/** @} */
10660
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