VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 66717

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1/* $Id: HMVMXR0.cpp 66717 2017-04-28 08:39:22Z vboxsync $ */
2/** @file
3 * HM VMX (Intel VT-x) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2012-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <iprt/x86.h>
24#include <iprt/asm-amd64-x86.h>
25#include <iprt/thread.h>
26
27#include <VBox/vmm/pdmapi.h>
28#include <VBox/vmm/dbgf.h>
29#include <VBox/vmm/iem.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/selm.h>
32#include <VBox/vmm/tm.h>
33#include <VBox/vmm/gim.h>
34#include <VBox/vmm/apic.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include "HMInternal.h"
39#include <VBox/vmm/vm.h>
40#include "HMVMXR0.h"
41#include "dtrace/VBoxVMM.h"
42
43#define HMVMX_USE_IEM_EVENT_REFLECTION
44#ifdef DEBUG_ramshankar
45# define HMVMX_ALWAYS_SAVE_GUEST_RFLAGS
46# define HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE
47# define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
48# define HMVMX_ALWAYS_CHECK_GUEST_STATE
49# define HMVMX_ALWAYS_TRAP_ALL_XCPTS
50# define HMVMX_ALWAYS_TRAP_PF
51# define HMVMX_ALWAYS_SWAP_FPU_STATE
52# define HMVMX_ALWAYS_FLUSH_TLB
53# define HMVMX_ALWAYS_SWAP_EFER
54#endif
55
56
57/*********************************************************************************************************************************
58* Defined Constants And Macros *
59*********************************************************************************************************************************/
60/** Use the function table. */
61#define HMVMX_USE_FUNCTION_TABLE
62
63/** Determine which tagged-TLB flush handler to use. */
64#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
65#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
66#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
67#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
68
69/** @name Updated-guest-state flags.
70 * @{ */
71#define HMVMX_UPDATED_GUEST_RIP RT_BIT(0)
72#define HMVMX_UPDATED_GUEST_RSP RT_BIT(1)
73#define HMVMX_UPDATED_GUEST_RFLAGS RT_BIT(2)
74#define HMVMX_UPDATED_GUEST_CR0 RT_BIT(3)
75#define HMVMX_UPDATED_GUEST_CR3 RT_BIT(4)
76#define HMVMX_UPDATED_GUEST_CR4 RT_BIT(5)
77#define HMVMX_UPDATED_GUEST_GDTR RT_BIT(6)
78#define HMVMX_UPDATED_GUEST_IDTR RT_BIT(7)
79#define HMVMX_UPDATED_GUEST_LDTR RT_BIT(8)
80#define HMVMX_UPDATED_GUEST_TR RT_BIT(9)
81#define HMVMX_UPDATED_GUEST_SEGMENT_REGS RT_BIT(10)
82#define HMVMX_UPDATED_GUEST_DR7 RT_BIT(11)
83#define HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR RT_BIT(12)
84#define HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR RT_BIT(13)
85#define HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR RT_BIT(14)
86#define HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS RT_BIT(15)
87#define HMVMX_UPDATED_GUEST_LAZY_MSRS RT_BIT(16)
88#define HMVMX_UPDATED_GUEST_ACTIVITY_STATE RT_BIT(17)
89#define HMVMX_UPDATED_GUEST_INTR_STATE RT_BIT(18)
90#define HMVMX_UPDATED_GUEST_APIC_STATE RT_BIT(19)
91#define HMVMX_UPDATED_GUEST_ALL ( HMVMX_UPDATED_GUEST_RIP \
92 | HMVMX_UPDATED_GUEST_RSP \
93 | HMVMX_UPDATED_GUEST_RFLAGS \
94 | HMVMX_UPDATED_GUEST_CR0 \
95 | HMVMX_UPDATED_GUEST_CR3 \
96 | HMVMX_UPDATED_GUEST_CR4 \
97 | HMVMX_UPDATED_GUEST_GDTR \
98 | HMVMX_UPDATED_GUEST_IDTR \
99 | HMVMX_UPDATED_GUEST_LDTR \
100 | HMVMX_UPDATED_GUEST_TR \
101 | HMVMX_UPDATED_GUEST_SEGMENT_REGS \
102 | HMVMX_UPDATED_GUEST_DR7 \
103 | HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR \
104 | HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR \
105 | HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR \
106 | HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS \
107 | HMVMX_UPDATED_GUEST_LAZY_MSRS \
108 | HMVMX_UPDATED_GUEST_ACTIVITY_STATE \
109 | HMVMX_UPDATED_GUEST_INTR_STATE \
110 | HMVMX_UPDATED_GUEST_APIC_STATE)
111/** @} */
112
113/** @name
114 * Flags to skip redundant reads of some common VMCS fields that are not part of
115 * the guest-CPU state but are in the transient structure.
116 */
117#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO RT_BIT(0)
118#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE RT_BIT(1)
119#define HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION RT_BIT(2)
120#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN RT_BIT(3)
121#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO RT_BIT(4)
122#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE RT_BIT(5)
123#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO RT_BIT(6)
124/** @} */
125
126/** @name
127 * States of the VMCS.
128 *
129 * This does not reflect all possible VMCS states but currently only those
130 * needed for maintaining the VMCS consistently even when thread-context hooks
131 * are used. Maybe later this can be extended (i.e. Nested Virtualization).
132 */
133#define HMVMX_VMCS_STATE_CLEAR RT_BIT(0)
134#define HMVMX_VMCS_STATE_ACTIVE RT_BIT(1)
135#define HMVMX_VMCS_STATE_LAUNCHED RT_BIT(2)
136/** @} */
137
138/**
139 * Exception bitmap mask for real-mode guests (real-on-v86).
140 *
141 * We need to intercept all exceptions manually except:
142 * - \#NM, \#MF handled in hmR0VmxLoadSharedCR0().
143 * - \#AC and \#DB are always intercepted to prevent the CPU from deadlocking
144 * due to bugs in Intel CPUs.
145 * - \#PF need not be intercepted even in real-mode if we have Nested Paging
146 * support.
147 */
148#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) /* always: | RT_BIT(X86_XCPT_DB) */ | RT_BIT(X86_XCPT_NMI) \
149 | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) \
150 | RT_BIT(X86_XCPT_UD) /* RT_BIT(X86_XCPT_NM) */ | RT_BIT(X86_XCPT_DF) \
151 | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) \
152 | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
153 /* RT_BIT(X86_XCPT_MF) always: | RT_BIT(X86_XCPT_AC) */ | RT_BIT(X86_XCPT_MC) \
154 | RT_BIT(X86_XCPT_XF))
155
156/**
157 * Exception bitmap mask for all contributory exceptions.
158 *
159 * Page fault is deliberately excluded here as it's conditional as to whether
160 * it's contributory or benign. Page faults are handled separately.
161 */
162#define HMVMX_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_TS) \
163 | RT_BIT(X86_XCPT_DE))
164
165/** Maximum VM-instruction error number. */
166#define HMVMX_INSTR_ERROR_MAX 28
167
168/** Profiling macro. */
169#ifdef HM_PROFILE_EXIT_DISPATCH
170# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
171# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
172#else
173# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
174# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
175#endif
176
177/** Assert that preemption is disabled or covered by thread-context hooks. */
178#define HMVMX_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
179 || !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
180
181/** Assert that we haven't migrated CPUs when thread-context hooks are not
182 * used. */
183#define HMVMX_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
184 || pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
185 ("Illegal migration! Entered on CPU %u Current %u\n", \
186 pVCpu->hm.s.idEnteredCpu, RTMpCpuId())); \
187
188/** Helper macro for VM-exit handlers called unexpectedly. */
189#define HMVMX_RETURN_UNEXPECTED_EXIT() \
190 do { \
191 pVCpu->hm.s.u32HMError = pVmxTransient->uExitReason; \
192 return VERR_VMX_UNEXPECTED_EXIT; \
193 } while (0)
194
195
196/*********************************************************************************************************************************
197* Structures and Typedefs *
198*********************************************************************************************************************************/
199/**
200 * VMX transient state.
201 *
202 * A state structure for holding miscellaneous information across
203 * VMX non-root operation and restored after the transition.
204 */
205typedef struct VMXTRANSIENT
206{
207 /** The host's rflags/eflags. */
208 RTCCUINTREG fEFlags;
209#if HC_ARCH_BITS == 32
210 uint32_t u32Alignment0;
211#endif
212 /** The guest's TPR value used for TPR shadowing. */
213 uint8_t u8GuestTpr;
214 /** Alignment. */
215 uint8_t abAlignment0[7];
216
217 /** The basic VM-exit reason. */
218 uint16_t uExitReason;
219 /** Alignment. */
220 uint16_t u16Alignment0;
221 /** The VM-exit interruption error code. */
222 uint32_t uExitIntErrorCode;
223 /** The VM-exit exit code qualification. */
224 uint64_t uExitQualification;
225
226 /** The VM-exit interruption-information field. */
227 uint32_t uExitIntInfo;
228 /** The VM-exit instruction-length field. */
229 uint32_t cbInstr;
230 /** The VM-exit instruction-information field. */
231 union
232 {
233 /** Plain unsigned int representation. */
234 uint32_t u;
235 /** INS and OUTS information. */
236 struct
237 {
238 uint32_t u7Reserved0 : 7;
239 /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
240 uint32_t u3AddrSize : 3;
241 uint32_t u5Reserved1 : 5;
242 /** The segment register (X86_SREG_XXX). */
243 uint32_t iSegReg : 3;
244 uint32_t uReserved2 : 14;
245 } StrIo;
246 } ExitInstrInfo;
247 /** Whether the VM-entry failed or not. */
248 bool fVMEntryFailed;
249 /** Alignment. */
250 uint8_t abAlignment1[3];
251
252 /** The VM-entry interruption-information field. */
253 uint32_t uEntryIntInfo;
254 /** The VM-entry exception error code field. */
255 uint32_t uEntryXcptErrorCode;
256 /** The VM-entry instruction length field. */
257 uint32_t cbEntryInstr;
258
259 /** IDT-vectoring information field. */
260 uint32_t uIdtVectoringInfo;
261 /** IDT-vectoring error code. */
262 uint32_t uIdtVectoringErrorCode;
263
264 /** Mask of currently read VMCS fields; HMVMX_UPDATED_TRANSIENT_*. */
265 uint32_t fVmcsFieldsRead;
266
267 /** Whether the guest FPU was active at the time of VM-exit. */
268 bool fWasGuestFPUStateActive;
269 /** Whether the guest debug state was active at the time of VM-exit. */
270 bool fWasGuestDebugStateActive;
271 /** Whether the hyper debug state was active at the time of VM-exit. */
272 bool fWasHyperDebugStateActive;
273 /** Whether TSC-offsetting should be setup before VM-entry. */
274 bool fUpdateTscOffsettingAndPreemptTimer;
275 /** Whether the VM-exit was caused by a page-fault during delivery of a
276 * contributory exception or a page-fault. */
277 bool fVectoringDoublePF;
278 /** Whether the VM-exit was caused by a page-fault during delivery of an
279 * external interrupt or NMI. */
280 bool fVectoringPF;
281} VMXTRANSIENT;
282AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, sizeof(uint64_t));
283AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntInfo, sizeof(uint64_t));
284AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntInfo, sizeof(uint64_t));
285AssertCompileMemberAlignment(VMXTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
286AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
287/** Pointer to VMX transient state. */
288typedef VMXTRANSIENT *PVMXTRANSIENT;
289
290
291/**
292 * MSR-bitmap read permissions.
293 */
294typedef enum VMXMSREXITREAD
295{
296 /** Reading this MSR causes a VM-exit. */
297 VMXMSREXIT_INTERCEPT_READ = 0xb,
298 /** Reading this MSR does not cause a VM-exit. */
299 VMXMSREXIT_PASSTHRU_READ
300} VMXMSREXITREAD;
301/** Pointer to MSR-bitmap read permissions. */
302typedef VMXMSREXITREAD* PVMXMSREXITREAD;
303
304/**
305 * MSR-bitmap write permissions.
306 */
307typedef enum VMXMSREXITWRITE
308{
309 /** Writing to this MSR causes a VM-exit. */
310 VMXMSREXIT_INTERCEPT_WRITE = 0xd,
311 /** Writing to this MSR does not cause a VM-exit. */
312 VMXMSREXIT_PASSTHRU_WRITE
313} VMXMSREXITWRITE;
314/** Pointer to MSR-bitmap write permissions. */
315typedef VMXMSREXITWRITE* PVMXMSREXITWRITE;
316
317
318/**
319 * VMX VM-exit handler.
320 *
321 * @returns Strict VBox status code (i.e. informational status codes too).
322 * @param pVCpu The cross context virtual CPU structure.
323 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
324 * out-of-sync. Make sure to update the required
325 * fields before using them.
326 * @param pVmxTransient Pointer to the VMX-transient structure.
327 */
328#ifndef HMVMX_USE_FUNCTION_TABLE
329typedef VBOXSTRICTRC FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
330#else
331typedef DECLCALLBACK(VBOXSTRICTRC) FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
332/** Pointer to VM-exit handler. */
333typedef FNVMXEXITHANDLER *PFNVMXEXITHANDLER;
334#endif
335
336/**
337 * VMX VM-exit handler, non-strict status code.
338 *
339 * This is generally the same as FNVMXEXITHANDLER, the NSRC bit is just FYI.
340 *
341 * @returns VBox status code, no informational status code returned.
342 * @param pVCpu The cross context virtual CPU structure.
343 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
344 * out-of-sync. Make sure to update the required
345 * fields before using them.
346 * @param pVmxTransient Pointer to the VMX-transient structure.
347 *
348 * @remarks This is not used on anything returning VERR_EM_INTERPRETER as the
349 * use of that status code will be replaced with VINF_EM_SOMETHING
350 * later when switching over to IEM.
351 */
352#ifndef HMVMX_USE_FUNCTION_TABLE
353typedef int FNVMXEXITHANDLERNSRC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
354#else
355typedef FNVMXEXITHANDLER FNVMXEXITHANDLERNSRC;
356#endif
357
358
359/*********************************************************************************************************************************
360* Internal Functions *
361*********************************************************************************************************************************/
362static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush);
363static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr);
364static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu);
365static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr,
366 uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress,
367 bool fStepping, uint32_t *puIntState);
368#if HC_ARCH_BITS == 32
369static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu);
370#endif
371#ifndef HMVMX_USE_FUNCTION_TABLE
372DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason);
373# define HMVMX_EXIT_DECL DECLINLINE(VBOXSTRICTRC)
374# define HMVMX_EXIT_NSRC_DECL DECLINLINE(int)
375#else
376# define HMVMX_EXIT_DECL static DECLCALLBACK(VBOXSTRICTRC)
377# define HMVMX_EXIT_NSRC_DECL HMVMX_EXIT_DECL
378#endif
379
380
381/** @name VM-exit handlers.
382 * @{
383 */
384static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmi;
385static FNVMXEXITHANDLER hmR0VmxExitExtInt;
386static FNVMXEXITHANDLER hmR0VmxExitTripleFault;
387static FNVMXEXITHANDLERNSRC hmR0VmxExitInitSignal;
388static FNVMXEXITHANDLERNSRC hmR0VmxExitSipi;
389static FNVMXEXITHANDLERNSRC hmR0VmxExitIoSmi;
390static FNVMXEXITHANDLERNSRC hmR0VmxExitSmi;
391static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindow;
392static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindow;
393static FNVMXEXITHANDLER hmR0VmxExitTaskSwitch;
394static FNVMXEXITHANDLER hmR0VmxExitCpuid;
395static FNVMXEXITHANDLER hmR0VmxExitGetsec;
396static FNVMXEXITHANDLER hmR0VmxExitHlt;
397static FNVMXEXITHANDLERNSRC hmR0VmxExitInvd;
398static FNVMXEXITHANDLER hmR0VmxExitInvlpg;
399static FNVMXEXITHANDLER hmR0VmxExitRdpmc;
400static FNVMXEXITHANDLER hmR0VmxExitVmcall;
401static FNVMXEXITHANDLER hmR0VmxExitRdtsc;
402static FNVMXEXITHANDLERNSRC hmR0VmxExitRsm;
403static FNVMXEXITHANDLERNSRC hmR0VmxExitSetPendingXcptUD;
404static FNVMXEXITHANDLER hmR0VmxExitMovCRx;
405static FNVMXEXITHANDLER hmR0VmxExitMovDRx;
406static FNVMXEXITHANDLER hmR0VmxExitIoInstr;
407static FNVMXEXITHANDLER hmR0VmxExitRdmsr;
408static FNVMXEXITHANDLER hmR0VmxExitWrmsr;
409static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestState;
410static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMsrLoad;
411static FNVMXEXITHANDLERNSRC hmR0VmxExitErrUndefined;
412static FNVMXEXITHANDLER hmR0VmxExitMwait;
413static FNVMXEXITHANDLER hmR0VmxExitMtf;
414static FNVMXEXITHANDLER hmR0VmxExitMonitor;
415static FNVMXEXITHANDLER hmR0VmxExitPause;
416static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMachineCheck;
417static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThreshold;
418static FNVMXEXITHANDLER hmR0VmxExitApicAccess;
419static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
420static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
421static FNVMXEXITHANDLER hmR0VmxExitEptViolation;
422static FNVMXEXITHANDLER hmR0VmxExitEptMisconfig;
423static FNVMXEXITHANDLER hmR0VmxExitRdtscp;
424static FNVMXEXITHANDLER hmR0VmxExitPreemptTimer;
425static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvd;
426static FNVMXEXITHANDLER hmR0VmxExitXsetbv;
427static FNVMXEXITHANDLER hmR0VmxExitRdrand;
428static FNVMXEXITHANDLER hmR0VmxExitInvpcid;
429/** @} */
430
431static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
432static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
433static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
434static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
435static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
436static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
437static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
438static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
439static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
440
441
442/*********************************************************************************************************************************
443* Global Variables *
444*********************************************************************************************************************************/
445#ifdef HMVMX_USE_FUNCTION_TABLE
446
447/**
448 * VMX_EXIT dispatch table.
449 */
450static const PFNVMXEXITHANDLER g_apfnVMExitHandlers[VMX_EXIT_MAX + 1] =
451{
452 /* 00 VMX_EXIT_XCPT_OR_NMI */ hmR0VmxExitXcptOrNmi,
453 /* 01 VMX_EXIT_EXT_INT */ hmR0VmxExitExtInt,
454 /* 02 VMX_EXIT_TRIPLE_FAULT */ hmR0VmxExitTripleFault,
455 /* 03 VMX_EXIT_INIT_SIGNAL */ hmR0VmxExitInitSignal,
456 /* 04 VMX_EXIT_SIPI */ hmR0VmxExitSipi,
457 /* 05 VMX_EXIT_IO_SMI */ hmR0VmxExitIoSmi,
458 /* 06 VMX_EXIT_SMI */ hmR0VmxExitSmi,
459 /* 07 VMX_EXIT_INT_WINDOW */ hmR0VmxExitIntWindow,
460 /* 08 VMX_EXIT_NMI_WINDOW */ hmR0VmxExitNmiWindow,
461 /* 09 VMX_EXIT_TASK_SWITCH */ hmR0VmxExitTaskSwitch,
462 /* 10 VMX_EXIT_CPUID */ hmR0VmxExitCpuid,
463 /* 11 VMX_EXIT_GETSEC */ hmR0VmxExitGetsec,
464 /* 12 VMX_EXIT_HLT */ hmR0VmxExitHlt,
465 /* 13 VMX_EXIT_INVD */ hmR0VmxExitInvd,
466 /* 14 VMX_EXIT_INVLPG */ hmR0VmxExitInvlpg,
467 /* 15 VMX_EXIT_RDPMC */ hmR0VmxExitRdpmc,
468 /* 16 VMX_EXIT_RDTSC */ hmR0VmxExitRdtsc,
469 /* 17 VMX_EXIT_RSM */ hmR0VmxExitRsm,
470 /* 18 VMX_EXIT_VMCALL */ hmR0VmxExitVmcall,
471 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitSetPendingXcptUD,
472 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitSetPendingXcptUD,
473 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitSetPendingXcptUD,
474 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitSetPendingXcptUD,
475 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitSetPendingXcptUD,
476 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitSetPendingXcptUD,
477 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitSetPendingXcptUD,
478 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitSetPendingXcptUD,
479 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitSetPendingXcptUD,
480 /* 28 VMX_EXIT_MOV_CRX */ hmR0VmxExitMovCRx,
481 /* 29 VMX_EXIT_MOV_DRX */ hmR0VmxExitMovDRx,
482 /* 30 VMX_EXIT_IO_INSTR */ hmR0VmxExitIoInstr,
483 /* 31 VMX_EXIT_RDMSR */ hmR0VmxExitRdmsr,
484 /* 32 VMX_EXIT_WRMSR */ hmR0VmxExitWrmsr,
485 /* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ hmR0VmxExitErrInvalidGuestState,
486 /* 34 VMX_EXIT_ERR_MSR_LOAD */ hmR0VmxExitErrMsrLoad,
487 /* 35 UNDEFINED */ hmR0VmxExitErrUndefined,
488 /* 36 VMX_EXIT_MWAIT */ hmR0VmxExitMwait,
489 /* 37 VMX_EXIT_MTF */ hmR0VmxExitMtf,
490 /* 38 UNDEFINED */ hmR0VmxExitErrUndefined,
491 /* 39 VMX_EXIT_MONITOR */ hmR0VmxExitMonitor,
492 /* 40 UNDEFINED */ hmR0VmxExitPause,
493 /* 41 VMX_EXIT_PAUSE */ hmR0VmxExitErrMachineCheck,
494 /* 42 VMX_EXIT_ERR_MACHINE_CHECK */ hmR0VmxExitErrUndefined,
495 /* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ hmR0VmxExitTprBelowThreshold,
496 /* 44 VMX_EXIT_APIC_ACCESS */ hmR0VmxExitApicAccess,
497 /* 45 UNDEFINED */ hmR0VmxExitErrUndefined,
498 /* 46 VMX_EXIT_XDTR_ACCESS */ hmR0VmxExitXdtrAccess,
499 /* 47 VMX_EXIT_TR_ACCESS */ hmR0VmxExitXdtrAccess,
500 /* 48 VMX_EXIT_EPT_VIOLATION */ hmR0VmxExitEptViolation,
501 /* 49 VMX_EXIT_EPT_MISCONFIG */ hmR0VmxExitEptMisconfig,
502 /* 50 VMX_EXIT_INVEPT */ hmR0VmxExitSetPendingXcptUD,
503 /* 51 VMX_EXIT_RDTSCP */ hmR0VmxExitRdtscp,
504 /* 52 VMX_EXIT_PREEMPT_TIMER */ hmR0VmxExitPreemptTimer,
505 /* 53 VMX_EXIT_INVVPID */ hmR0VmxExitSetPendingXcptUD,
506 /* 54 VMX_EXIT_WBINVD */ hmR0VmxExitWbinvd,
507 /* 55 VMX_EXIT_XSETBV */ hmR0VmxExitXsetbv,
508 /* 56 VMX_EXIT_APIC_WRITE */ hmR0VmxExitErrUndefined,
509 /* 57 VMX_EXIT_RDRAND */ hmR0VmxExitRdrand,
510 /* 58 VMX_EXIT_INVPCID */ hmR0VmxExitInvpcid,
511 /* 59 VMX_EXIT_VMFUNC */ hmR0VmxExitSetPendingXcptUD,
512 /* 60 VMX_EXIT_ENCLS */ hmR0VmxExitErrUndefined,
513 /* 61 VMX_EXIT_RDSEED */ hmR0VmxExitErrUndefined, /* only spurious exits, so undefined */
514 /* 62 VMX_EXIT_PML_FULL */ hmR0VmxExitErrUndefined,
515 /* 63 VMX_EXIT_XSAVES */ hmR0VmxExitSetPendingXcptUD,
516 /* 64 VMX_EXIT_XRSTORS */ hmR0VmxExitSetPendingXcptUD,
517};
518#endif /* HMVMX_USE_FUNCTION_TABLE */
519
520#ifdef VBOX_STRICT
521static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
522{
523 /* 0 */ "(Not Used)",
524 /* 1 */ "VMCALL executed in VMX root operation.",
525 /* 2 */ "VMCLEAR with invalid physical address.",
526 /* 3 */ "VMCLEAR with VMXON pointer.",
527 /* 4 */ "VMLAUNCH with non-clear VMCS.",
528 /* 5 */ "VMRESUME with non-launched VMCS.",
529 /* 6 */ "VMRESUME after VMXOFF",
530 /* 7 */ "VM-entry with invalid control fields.",
531 /* 8 */ "VM-entry with invalid host state fields.",
532 /* 9 */ "VMPTRLD with invalid physical address.",
533 /* 10 */ "VMPTRLD with VMXON pointer.",
534 /* 11 */ "VMPTRLD with incorrect revision identifier.",
535 /* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
536 /* 13 */ "VMWRITE to read-only VMCS component.",
537 /* 14 */ "(Not Used)",
538 /* 15 */ "VMXON executed in VMX root operation.",
539 /* 16 */ "VM-entry with invalid executive-VMCS pointer.",
540 /* 17 */ "VM-entry with non-launched executing VMCS.",
541 /* 18 */ "VM-entry with executive-VMCS pointer not VMXON pointer.",
542 /* 19 */ "VMCALL with non-clear VMCS.",
543 /* 20 */ "VMCALL with invalid VM-exit control fields.",
544 /* 21 */ "(Not Used)",
545 /* 22 */ "VMCALL with incorrect MSEG revision identifier.",
546 /* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
547 /* 24 */ "VMCALL with invalid SMM-monitor features.",
548 /* 25 */ "VM-entry with invalid VM-execution control fields in executive VMCS.",
549 /* 26 */ "VM-entry with events blocked by MOV SS.",
550 /* 27 */ "(Not Used)",
551 /* 28 */ "Invalid operand to INVEPT/INVVPID."
552};
553#endif /* VBOX_STRICT */
554
555
556
557/**
558 * Updates the VM's last error record.
559 *
560 * If there was a VMX instruction error, reads the error data from the VMCS and
561 * updates VCPU's last error record as well.
562 *
563 * @param pVM The cross context VM structure.
564 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
565 * Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
566 * VERR_VMX_INVALID_VMCS_FIELD.
567 * @param rc The error code.
568 */
569static void hmR0VmxUpdateErrorRecord(PVM pVM, PVMCPU pVCpu, int rc)
570{
571 AssertPtr(pVM);
572 if ( rc == VERR_VMX_INVALID_VMCS_FIELD
573 || rc == VERR_VMX_UNABLE_TO_START_VM)
574 {
575 AssertPtrReturnVoid(pVCpu);
576 VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
577 }
578 pVM->hm.s.lLastError = rc;
579}
580
581
582/**
583 * Reads the VM-entry interruption-information field from the VMCS into the VMX
584 * transient structure.
585 *
586 * @returns VBox status code.
587 * @param pVmxTransient Pointer to the VMX transient structure.
588 *
589 * @remarks No-long-jump zone!!!
590 */
591DECLINLINE(int) hmR0VmxReadEntryIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
592{
593 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);
594 AssertRCReturn(rc, rc);
595 return VINF_SUCCESS;
596}
597
598
599#ifdef VBOX_STRICT
600/**
601 * Reads the VM-entry exception error code field from the VMCS into
602 * the VMX transient structure.
603 *
604 * @returns VBox status code.
605 * @param pVmxTransient Pointer to the VMX transient structure.
606 *
607 * @remarks No-long-jump zone!!!
608 */
609DECLINLINE(int) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
610{
611 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
612 AssertRCReturn(rc, rc);
613 return VINF_SUCCESS;
614}
615#endif /* VBOX_STRICT */
616
617
618#ifdef VBOX_STRICT
619/**
620 * Reads the VM-entry exception error code field from the VMCS into
621 * the VMX transient structure.
622 *
623 * @returns VBox status code.
624 * @param pVmxTransient Pointer to the VMX transient structure.
625 *
626 * @remarks No-long-jump zone!!!
627 */
628DECLINLINE(int) hmR0VmxReadEntryInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
629{
630 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
631 AssertRCReturn(rc, rc);
632 return VINF_SUCCESS;
633}
634#endif /* VBOX_STRICT */
635
636
637/**
638 * Reads the VM-exit interruption-information field from the VMCS into the VMX
639 * transient structure.
640 *
641 * @returns VBox status code.
642 * @param pVmxTransient Pointer to the VMX transient structure.
643 */
644DECLINLINE(int) hmR0VmxReadExitIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
645{
646 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO))
647 {
648 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
649 AssertRCReturn(rc, rc);
650 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO;
651 }
652 return VINF_SUCCESS;
653}
654
655
656/**
657 * Reads the VM-exit interruption error code from the VMCS into the VMX
658 * transient structure.
659 *
660 * @returns VBox status code.
661 * @param pVmxTransient Pointer to the VMX transient structure.
662 */
663DECLINLINE(int) hmR0VmxReadExitIntErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
664{
665 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE))
666 {
667 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
668 AssertRCReturn(rc, rc);
669 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE;
670 }
671 return VINF_SUCCESS;
672}
673
674
675/**
676 * Reads the VM-exit instruction length field from the VMCS into the VMX
677 * transient structure.
678 *
679 * @returns VBox status code.
680 * @param pVmxTransient Pointer to the VMX transient structure.
681 */
682DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
683{
684 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN))
685 {
686 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
687 AssertRCReturn(rc, rc);
688 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN;
689 }
690 return VINF_SUCCESS;
691}
692
693
694/**
695 * Reads the VM-exit instruction-information field from the VMCS into
696 * the VMX transient structure.
697 *
698 * @returns VBox status code.
699 * @param pVmxTransient Pointer to the VMX transient structure.
700 */
701DECLINLINE(int) hmR0VmxReadExitInstrInfoVmcs(PVMXTRANSIENT pVmxTransient)
702{
703 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO))
704 {
705 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
706 AssertRCReturn(rc, rc);
707 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO;
708 }
709 return VINF_SUCCESS;
710}
711
712
713/**
714 * Reads the exit code qualification from the VMCS into the VMX transient
715 * structure.
716 *
717 * @returns VBox status code.
718 * @param pVCpu The cross context virtual CPU structure of the
719 * calling EMT. (Required for the VMCS cache case.)
720 * @param pVmxTransient Pointer to the VMX transient structure.
721 */
722DECLINLINE(int) hmR0VmxReadExitQualificationVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
723{
724 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION))
725 {
726 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQualification); NOREF(pVCpu);
727 AssertRCReturn(rc, rc);
728 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION;
729 }
730 return VINF_SUCCESS;
731}
732
733
734/**
735 * Reads the IDT-vectoring information field from the VMCS into the VMX
736 * transient structure.
737 *
738 * @returns VBox status code.
739 * @param pVmxTransient Pointer to the VMX transient structure.
740 *
741 * @remarks No-long-jump zone!!!
742 */
743DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
744{
745 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO))
746 {
747 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_INFO, &pVmxTransient->uIdtVectoringInfo);
748 AssertRCReturn(rc, rc);
749 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO;
750 }
751 return VINF_SUCCESS;
752}
753
754
755/**
756 * Reads the IDT-vectoring error code from the VMCS into the VMX
757 * transient structure.
758 *
759 * @returns VBox status code.
760 * @param pVmxTransient Pointer to the VMX transient structure.
761 */
762DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
763{
764 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE))
765 {
766 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
767 AssertRCReturn(rc, rc);
768 pVmxTransient->fVmcsFieldsRead |= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE;
769 }
770 return VINF_SUCCESS;
771}
772
773
774/**
775 * Enters VMX root mode operation on the current CPU.
776 *
777 * @returns VBox status code.
778 * @param pVM The cross context VM structure. Can be
779 * NULL, after a resume.
780 * @param HCPhysCpuPage Physical address of the VMXON region.
781 * @param pvCpuPage Pointer to the VMXON region.
782 */
783static int hmR0VmxEnterRootMode(PVM pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
784{
785 Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
786 Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
787 Assert(pvCpuPage);
788 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
789
790 if (pVM)
791 {
792 /* Write the VMCS revision dword to the VMXON region. */
793 *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
794 }
795
796 /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
797 RTCCUINTREG fEFlags = ASMIntDisableFlags();
798
799 /* Enable the VMX bit in CR4 if necessary. */
800 RTCCUINTREG uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
801
802 /* Enter VMX root mode. */
803 int rc = VMXEnable(HCPhysCpuPage);
804 if (RT_FAILURE(rc))
805 {
806 if (!(uOldCr4 & X86_CR4_VMXE))
807 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
808
809 if (pVM)
810 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
811 }
812
813 /* Restore interrupts. */
814 ASMSetFlags(fEFlags);
815 return rc;
816}
817
818
819/**
820 * Exits VMX root mode operation on the current CPU.
821 *
822 * @returns VBox status code.
823 */
824static int hmR0VmxLeaveRootMode(void)
825{
826 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
827
828 /* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
829 RTCCUINTREG fEFlags = ASMIntDisableFlags();
830
831 /* If we're for some reason not in VMX root mode, then don't leave it. */
832 RTCCUINTREG uHostCR4 = ASMGetCR4();
833
834 int rc;
835 if (uHostCR4 & X86_CR4_VMXE)
836 {
837 /* Exit VMX root mode and clear the VMX bit in CR4. */
838 VMXDisable();
839 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
840 rc = VINF_SUCCESS;
841 }
842 else
843 rc = VERR_VMX_NOT_IN_VMX_ROOT_MODE;
844
845 /* Restore interrupts. */
846 ASMSetFlags(fEFlags);
847 return rc;
848}
849
850
851/**
852 * Allocates and maps one physically contiguous page. The allocated page is
853 * zero'd out. (Used by various VT-x structures).
854 *
855 * @returns IPRT status code.
856 * @param pMemObj Pointer to the ring-0 memory object.
857 * @param ppVirt Where to store the virtual address of the
858 * allocation.
859 * @param pHCPhys Where to store the physical address of the
860 * allocation.
861 */
862DECLINLINE(int) hmR0VmxPageAllocZ(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
863{
864 AssertPtrReturn(pMemObj, VERR_INVALID_PARAMETER);
865 AssertPtrReturn(ppVirt, VERR_INVALID_PARAMETER);
866 AssertPtrReturn(pHCPhys, VERR_INVALID_PARAMETER);
867
868 int rc = RTR0MemObjAllocCont(pMemObj, PAGE_SIZE, false /* fExecutable */);
869 if (RT_FAILURE(rc))
870 return rc;
871 *ppVirt = RTR0MemObjAddress(*pMemObj);
872 *pHCPhys = RTR0MemObjGetPagePhysAddr(*pMemObj, 0 /* iPage */);
873 ASMMemZero32(*ppVirt, PAGE_SIZE);
874 return VINF_SUCCESS;
875}
876
877
878/**
879 * Frees and unmaps an allocated physical page.
880 *
881 * @param pMemObj Pointer to the ring-0 memory object.
882 * @param ppVirt Where to re-initialize the virtual address of
883 * allocation as 0.
884 * @param pHCPhys Where to re-initialize the physical address of the
885 * allocation as 0.
886 */
887DECLINLINE(void) hmR0VmxPageFree(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
888{
889 AssertPtr(pMemObj);
890 AssertPtr(ppVirt);
891 AssertPtr(pHCPhys);
892 if (*pMemObj != NIL_RTR0MEMOBJ)
893 {
894 int rc = RTR0MemObjFree(*pMemObj, true /* fFreeMappings */);
895 AssertRC(rc);
896 *pMemObj = NIL_RTR0MEMOBJ;
897 *ppVirt = 0;
898 *pHCPhys = 0;
899 }
900}
901
902
903/**
904 * Worker function to free VT-x related structures.
905 *
906 * @returns IPRT status code.
907 * @param pVM The cross context VM structure.
908 */
909static void hmR0VmxStructsFree(PVM pVM)
910{
911 for (VMCPUID i = 0; i < pVM->cCpus; i++)
912 {
913 PVMCPU pVCpu = &pVM->aCpus[i];
914 AssertPtr(pVCpu);
915
916 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
917 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
918
919 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
920 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
921
922 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
923 }
924
925 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, &pVM->hm.s.vmx.HCPhysApicAccess);
926#ifdef VBOX_WITH_CRASHDUMP_MAGIC
927 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
928#endif
929}
930
931
932/**
933 * Worker function to allocate VT-x related VM structures.
934 *
935 * @returns IPRT status code.
936 * @param pVM The cross context VM structure.
937 */
938static int hmR0VmxStructsAlloc(PVM pVM)
939{
940 /*
941 * Initialize members up-front so we can cleanup properly on allocation failure.
942 */
943#define VMXLOCAL_INIT_VM_MEMOBJ(a_Name, a_VirtPrefix) \
944 pVM->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
945 pVM->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
946 pVM->hm.s.vmx.HCPhys##a_Name = 0;
947
948#define VMXLOCAL_INIT_VMCPU_MEMOBJ(a_Name, a_VirtPrefix) \
949 pVCpu->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
950 pVCpu->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
951 pVCpu->hm.s.vmx.HCPhys##a_Name = 0;
952
953#ifdef VBOX_WITH_CRASHDUMP_MAGIC
954 VMXLOCAL_INIT_VM_MEMOBJ(Scratch, pv);
955#endif
956 VMXLOCAL_INIT_VM_MEMOBJ(ApicAccess, pb);
957
958 AssertCompile(sizeof(VMCPUID) == sizeof(pVM->cCpus));
959 for (VMCPUID i = 0; i < pVM->cCpus; i++)
960 {
961 PVMCPU pVCpu = &pVM->aCpus[i];
962 VMXLOCAL_INIT_VMCPU_MEMOBJ(Vmcs, pv);
963 VMXLOCAL_INIT_VMCPU_MEMOBJ(MsrBitmap, pv);
964 VMXLOCAL_INIT_VMCPU_MEMOBJ(GuestMsr, pv);
965 VMXLOCAL_INIT_VMCPU_MEMOBJ(HostMsr, pv);
966 }
967#undef VMXLOCAL_INIT_VMCPU_MEMOBJ
968#undef VMXLOCAL_INIT_VM_MEMOBJ
969
970 /* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
971 AssertReturnStmt(MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo) <= PAGE_SIZE,
972 (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
973 VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
974
975 /*
976 * Allocate all the VT-x structures.
977 */
978 int rc = VINF_SUCCESS;
979#ifdef VBOX_WITH_CRASHDUMP_MAGIC
980 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
981 if (RT_FAILURE(rc))
982 goto cleanup;
983 strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
984 *(uint64_t *)(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
985#endif
986
987 /* Allocate the APIC-access page for trapping APIC accesses from the guest. */
988 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
989 {
990 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
991 &pVM->hm.s.vmx.HCPhysApicAccess);
992 if (RT_FAILURE(rc))
993 goto cleanup;
994 }
995
996 /*
997 * Initialize per-VCPU VT-x structures.
998 */
999 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1000 {
1001 PVMCPU pVCpu = &pVM->aCpus[i];
1002 AssertPtr(pVCpu);
1003
1004 /* Allocate the VM control structure (VMCS). */
1005 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
1006 if (RT_FAILURE(rc))
1007 goto cleanup;
1008
1009 /* Get the allocated virtual-APIC page from the APIC device for transparent TPR accesses. */
1010 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
1011 {
1012 rc = APICGetApicPageForCpu(pVCpu, &pVCpu->hm.s.vmx.HCPhysVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
1013 NULL /* pR3Ptr */, NULL /* pRCPtr */);
1014 if (RT_FAILURE(rc))
1015 goto cleanup;
1016 }
1017
1018 /*
1019 * Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for
1020 * transparent accesses of specific MSRs.
1021 *
1022 * If the condition for enabling MSR bitmaps changes here, don't forget to
1023 * update HMAreMsrBitmapsAvailable().
1024 */
1025 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1026 {
1027 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
1028 &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1029 if (RT_FAILURE(rc))
1030 goto cleanup;
1031 ASMMemFill32(pVCpu->hm.s.vmx.pvMsrBitmap, PAGE_SIZE, UINT32_C(0xffffffff));
1032 }
1033
1034 /* Allocate the VM-entry MSR-load and VM-exit MSR-store page for the guest MSRs. */
1035 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
1036 if (RT_FAILURE(rc))
1037 goto cleanup;
1038
1039 /* Allocate the VM-exit MSR-load page for the host MSRs. */
1040 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
1041 if (RT_FAILURE(rc))
1042 goto cleanup;
1043 }
1044
1045 return VINF_SUCCESS;
1046
1047cleanup:
1048 hmR0VmxStructsFree(pVM);
1049 return rc;
1050}
1051
1052
1053/**
1054 * Does global VT-x initialization (called during module initialization).
1055 *
1056 * @returns VBox status code.
1057 */
1058VMMR0DECL(int) VMXR0GlobalInit(void)
1059{
1060#ifdef HMVMX_USE_FUNCTION_TABLE
1061 AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_apfnVMExitHandlers));
1062# ifdef VBOX_STRICT
1063 for (unsigned i = 0; i < RT_ELEMENTS(g_apfnVMExitHandlers); i++)
1064 Assert(g_apfnVMExitHandlers[i]);
1065# endif
1066#endif
1067 return VINF_SUCCESS;
1068}
1069
1070
1071/**
1072 * Does global VT-x termination (called during module termination).
1073 */
1074VMMR0DECL(void) VMXR0GlobalTerm()
1075{
1076 /* Nothing to do currently. */
1077}
1078
1079
1080/**
1081 * Sets up and activates VT-x on the current CPU.
1082 *
1083 * @returns VBox status code.
1084 * @param pCpu Pointer to the global CPU info struct.
1085 * @param pVM The cross context VM structure. Can be
1086 * NULL after a host resume operation.
1087 * @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
1088 * fEnabledByHost is @c true).
1089 * @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
1090 * @a fEnabledByHost is @c true).
1091 * @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
1092 * enable VT-x on the host.
1093 * @param pvMsrs Opaque pointer to VMXMSRS struct.
1094 */
1095VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
1096 void *pvMsrs)
1097{
1098 Assert(pCpu);
1099 Assert(pvMsrs);
1100 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1101
1102 /* Enable VT-x if it's not already enabled by the host. */
1103 if (!fEnabledByHost)
1104 {
1105 int rc = hmR0VmxEnterRootMode(pVM, HCPhysCpuPage, pvCpuPage);
1106 if (RT_FAILURE(rc))
1107 return rc;
1108 }
1109
1110 /*
1111 * Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been using EPTPs) so
1112 * we don't retain any stale guest-physical mappings which won't get invalidated when flushing by VPID.
1113 */
1114 PVMXMSRS pMsrs = (PVMXMSRS)pvMsrs;
1115 if (pMsrs->u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1116 {
1117 hmR0VmxFlushEpt(NULL /* pVCpu */, VMXFLUSHEPT_ALL_CONTEXTS);
1118 pCpu->fFlushAsidBeforeUse = false;
1119 }
1120 else
1121 pCpu->fFlushAsidBeforeUse = true;
1122
1123 /* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
1124 ++pCpu->cTlbFlushes;
1125
1126 return VINF_SUCCESS;
1127}
1128
1129
1130/**
1131 * Deactivates VT-x on the current CPU.
1132 *
1133 * @returns VBox status code.
1134 * @param pCpu Pointer to the global CPU info struct.
1135 * @param pvCpuPage Pointer to the VMXON region.
1136 * @param HCPhysCpuPage Physical address of the VMXON region.
1137 *
1138 * @remarks This function should never be called when SUPR0EnableVTx() or
1139 * similar was used to enable VT-x on the host.
1140 */
1141VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
1142{
1143 NOREF(pCpu);
1144 NOREF(pvCpuPage);
1145 NOREF(HCPhysCpuPage);
1146
1147 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1148 return hmR0VmxLeaveRootMode();
1149}
1150
1151
1152/**
1153 * Sets the permission bits for the specified MSR in the MSR bitmap.
1154 *
1155 * @param pVCpu The cross context virtual CPU structure.
1156 * @param uMsr The MSR value.
1157 * @param enmRead Whether reading this MSR causes a VM-exit.
1158 * @param enmWrite Whether writing this MSR causes a VM-exit.
1159 */
1160static void hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite)
1161{
1162 int32_t iBit;
1163 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1164
1165 /*
1166 * Layout:
1167 * 0x000 - 0x3ff - Low MSR read bits
1168 * 0x400 - 0x7ff - High MSR read bits
1169 * 0x800 - 0xbff - Low MSR write bits
1170 * 0xc00 - 0xfff - High MSR write bits
1171 */
1172 if (uMsr <= 0x00001FFF)
1173 iBit = uMsr;
1174 else if (uMsr - UINT32_C(0xC0000000) <= UINT32_C(0x00001FFF))
1175 {
1176 iBit = uMsr - UINT32_C(0xC0000000);
1177 pbMsrBitmap += 0x400;
1178 }
1179 else
1180 AssertMsgFailedReturnVoid(("hmR0VmxSetMsrPermission: Invalid MSR %#RX32\n", uMsr));
1181
1182 Assert(iBit <= 0x1fff);
1183 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
1184 ASMBitSet(pbMsrBitmap, iBit);
1185 else
1186 ASMBitClear(pbMsrBitmap, iBit);
1187
1188 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
1189 ASMBitSet(pbMsrBitmap + 0x800, iBit);
1190 else
1191 ASMBitClear(pbMsrBitmap + 0x800, iBit);
1192}
1193
1194
1195#ifdef VBOX_STRICT
1196/**
1197 * Gets the permission bits for the specified MSR in the MSR bitmap.
1198 *
1199 * @returns VBox status code.
1200 * @retval VINF_SUCCESS if the specified MSR is found.
1201 * @retval VERR_NOT_FOUND if the specified MSR is not found.
1202 * @retval VERR_NOT_SUPPORTED if VT-x doesn't allow the MSR.
1203 *
1204 * @param pVCpu The cross context virtual CPU structure.
1205 * @param uMsr The MSR.
1206 * @param penmRead Where to store the read permissions.
1207 * @param penmWrite Where to store the write permissions.
1208 */
1209static int hmR0VmxGetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, PVMXMSREXITREAD penmRead, PVMXMSREXITWRITE penmWrite)
1210{
1211 AssertPtrReturn(penmRead, VERR_INVALID_PARAMETER);
1212 AssertPtrReturn(penmWrite, VERR_INVALID_PARAMETER);
1213 int32_t iBit;
1214 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1215
1216 /* See hmR0VmxSetMsrPermission() for the layout. */
1217 if (uMsr <= 0x00001FFF)
1218 iBit = uMsr;
1219 else if ( uMsr >= 0xC0000000
1220 && uMsr <= 0xC0001FFF)
1221 {
1222 iBit = (uMsr - 0xC0000000);
1223 pbMsrBitmap += 0x400;
1224 }
1225 else
1226 AssertMsgFailedReturn(("hmR0VmxGetMsrPermission: Invalid MSR %#RX32\n", uMsr), VERR_NOT_SUPPORTED);
1227
1228 Assert(iBit <= 0x1fff);
1229 if (ASMBitTest(pbMsrBitmap, iBit))
1230 *penmRead = VMXMSREXIT_INTERCEPT_READ;
1231 else
1232 *penmRead = VMXMSREXIT_PASSTHRU_READ;
1233
1234 if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
1235 *penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
1236 else
1237 *penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
1238 return VINF_SUCCESS;
1239}
1240#endif /* VBOX_STRICT */
1241
1242
1243/**
1244 * Updates the VMCS with the number of effective MSRs in the auto-load/store MSR
1245 * area.
1246 *
1247 * @returns VBox status code.
1248 * @param pVCpu The cross context virtual CPU structure.
1249 * @param cMsrs The number of MSRs.
1250 */
1251DECLINLINE(int) hmR0VmxSetAutoLoadStoreMsrCount(PVMCPU pVCpu, uint32_t cMsrs)
1252{
1253 /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
1254 uint32_t const cMaxSupportedMsrs = MSR_IA32_VMX_MISC_MAX_MSR(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc);
1255 if (RT_UNLIKELY(cMsrs > cMaxSupportedMsrs))
1256 {
1257 LogRel(("CPU auto-load/store MSR count in VMCS exceeded cMsrs=%u Supported=%u.\n", cMsrs, cMaxSupportedMsrs));
1258 pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
1259 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1260 }
1261
1262 /* Update number of guest MSRs to load/store across the world-switch. */
1263 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs);
1264 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs);
1265
1266 /* Update number of host MSRs to load after the world-switch. Identical to guest-MSR count as it's always paired. */
1267 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs);
1268 AssertRCReturn(rc, rc);
1269
1270 /* Update the VCPU's copy of the MSR count. */
1271 pVCpu->hm.s.vmx.cMsrs = cMsrs;
1272
1273 return VINF_SUCCESS;
1274}
1275
1276
1277/**
1278 * Adds a new (or updates the value of an existing) guest/host MSR
1279 * pair to be swapped during the world-switch as part of the
1280 * auto-load/store MSR area in the VMCS.
1281 *
1282 * @returns VBox status code.
1283 * @param pVCpu The cross context virtual CPU structure.
1284 * @param uMsr The MSR.
1285 * @param uGuestMsrValue Value of the guest MSR.
1286 * @param fUpdateHostMsr Whether to update the value of the host MSR if
1287 * necessary.
1288 * @param pfAddedAndUpdated Where to store whether the MSR was added -and-
1289 * its value was updated. Optional, can be NULL.
1290 */
1291static int hmR0VmxAddAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr, uint64_t uGuestMsrValue, bool fUpdateHostMsr,
1292 bool *pfAddedAndUpdated)
1293{
1294 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1295 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1296 uint32_t i;
1297 for (i = 0; i < cMsrs; i++)
1298 {
1299 if (pGuestMsr->u32Msr == uMsr)
1300 break;
1301 pGuestMsr++;
1302 }
1303
1304 bool fAdded = false;
1305 if (i == cMsrs)
1306 {
1307 ++cMsrs;
1308 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1309 AssertMsgRCReturn(rc, ("hmR0VmxAddAutoLoadStoreMsr: Insufficient space to add MSR %u\n", uMsr), rc);
1310
1311 /* Now that we're swapping MSRs during the world-switch, allow the guest to read/write them without causing VM-exits. */
1312 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1313 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1314
1315 fAdded = true;
1316 }
1317
1318 /* Update the MSR values in the auto-load/store MSR area. */
1319 pGuestMsr->u32Msr = uMsr;
1320 pGuestMsr->u64Value = uGuestMsrValue;
1321
1322 /* Create/update the MSR slot in the host MSR area. */
1323 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1324 pHostMsr += i;
1325 pHostMsr->u32Msr = uMsr;
1326
1327 /*
1328 * Update the host MSR only when requested by the caller AND when we're
1329 * adding it to the auto-load/store area. Otherwise, it would have been
1330 * updated by hmR0VmxSaveHostMsrs(). We do this for performance reasons.
1331 */
1332 bool fUpdatedMsrValue = false;
1333 if ( fAdded
1334 && fUpdateHostMsr)
1335 {
1336 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1337 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1338 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1339 fUpdatedMsrValue = true;
1340 }
1341
1342 if (pfAddedAndUpdated)
1343 *pfAddedAndUpdated = fUpdatedMsrValue;
1344 return VINF_SUCCESS;
1345}
1346
1347
1348/**
1349 * Removes a guest/host MSR pair to be swapped during the world-switch from the
1350 * auto-load/store MSR area in the VMCS.
1351 *
1352 * @returns VBox status code.
1353 * @param pVCpu The cross context virtual CPU structure.
1354 * @param uMsr The MSR.
1355 */
1356static int hmR0VmxRemoveAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr)
1357{
1358 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1359 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1360 for (uint32_t i = 0; i < cMsrs; i++)
1361 {
1362 /* Find the MSR. */
1363 if (pGuestMsr->u32Msr == uMsr)
1364 {
1365 /* If it's the last MSR, simply reduce the count. */
1366 if (i == cMsrs - 1)
1367 {
1368 --cMsrs;
1369 break;
1370 }
1371
1372 /* Remove it by swapping the last MSR in place of it, and reducing the count. */
1373 PVMXAUTOMSR pLastGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1374 pLastGuestMsr += cMsrs - 1;
1375 pGuestMsr->u32Msr = pLastGuestMsr->u32Msr;
1376 pGuestMsr->u64Value = pLastGuestMsr->u64Value;
1377
1378 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1379 PVMXAUTOMSR pLastHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1380 pLastHostMsr += cMsrs - 1;
1381 pHostMsr->u32Msr = pLastHostMsr->u32Msr;
1382 pHostMsr->u64Value = pLastHostMsr->u64Value;
1383 --cMsrs;
1384 break;
1385 }
1386 pGuestMsr++;
1387 }
1388
1389 /* Update the VMCS if the count changed (meaning the MSR was found). */
1390 if (cMsrs != pVCpu->hm.s.vmx.cMsrs)
1391 {
1392 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1393 AssertRCReturn(rc, rc);
1394
1395 /* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
1396 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1397 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
1398
1399 Log4(("Removed MSR %#RX32 new cMsrs=%u\n", uMsr, pVCpu->hm.s.vmx.cMsrs));
1400 return VINF_SUCCESS;
1401 }
1402
1403 return VERR_NOT_FOUND;
1404}
1405
1406
1407/**
1408 * Checks if the specified guest MSR is part of the auto-load/store area in
1409 * the VMCS.
1410 *
1411 * @returns true if found, false otherwise.
1412 * @param pVCpu The cross context virtual CPU structure.
1413 * @param uMsr The MSR to find.
1414 */
1415static bool hmR0VmxIsAutoLoadStoreGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1416{
1417 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1418 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1419
1420 for (uint32_t i = 0; i < cMsrs; i++, pGuestMsr++)
1421 {
1422 if (pGuestMsr->u32Msr == uMsr)
1423 return true;
1424 }
1425 return false;
1426}
1427
1428
1429/**
1430 * Updates the value of all host MSRs in the auto-load/store area in the VMCS.
1431 *
1432 * @param pVCpu The cross context virtual CPU structure.
1433 *
1434 * @remarks No-long-jump zone!!!
1435 */
1436static void hmR0VmxUpdateAutoLoadStoreHostMsrs(PVMCPU pVCpu)
1437{
1438 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1439 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1440 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1441 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1442
1443 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1444 {
1445 AssertReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr);
1446
1447 /*
1448 * Performance hack for the host EFER MSR. We use the cached value rather than re-read it.
1449 * Strict builds will catch mismatches in hmR0VmxCheckAutoLoadStoreMsrs(). See @bugref{7368}.
1450 */
1451 if (pHostMsr->u32Msr == MSR_K6_EFER)
1452 pHostMsr->u64Value = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.u64HostEfer;
1453 else
1454 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1455 }
1456
1457 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
1458}
1459
1460
1461/**
1462 * Saves a set of host MSRs to allow read/write passthru access to the guest and
1463 * perform lazy restoration of the host MSRs while leaving VT-x.
1464 *
1465 * @param pVCpu The cross context virtual CPU structure.
1466 *
1467 * @remarks No-long-jump zone!!!
1468 */
1469static void hmR0VmxLazySaveHostMsrs(PVMCPU pVCpu)
1470{
1471 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1472
1473 /*
1474 * Note: If you're adding MSRs here, make sure to update the MSR-bitmap permissions in hmR0VmxSetupProcCtls().
1475 */
1476 if (!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST))
1477 {
1478 Assert(!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */
1479#if HC_ARCH_BITS == 64
1480 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1481 {
1482 pVCpu->hm.s.vmx.u64HostLStarMsr = ASMRdMsr(MSR_K8_LSTAR);
1483 pVCpu->hm.s.vmx.u64HostStarMsr = ASMRdMsr(MSR_K6_STAR);
1484 pVCpu->hm.s.vmx.u64HostSFMaskMsr = ASMRdMsr(MSR_K8_SF_MASK);
1485 pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1486 }
1487#endif
1488 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_SAVED_HOST;
1489 }
1490}
1491
1492
1493/**
1494 * Checks whether the MSR belongs to the set of guest MSRs that we restore
1495 * lazily while leaving VT-x.
1496 *
1497 * @returns true if it does, false otherwise.
1498 * @param pVCpu The cross context virtual CPU structure.
1499 * @param uMsr The MSR to check.
1500 */
1501static bool hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1502{
1503 NOREF(pVCpu);
1504#if HC_ARCH_BITS == 64
1505 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1506 {
1507 switch (uMsr)
1508 {
1509 case MSR_K8_LSTAR:
1510 case MSR_K6_STAR:
1511 case MSR_K8_SF_MASK:
1512 case MSR_K8_KERNEL_GS_BASE:
1513 return true;
1514 }
1515 }
1516#else
1517 RT_NOREF(pVCpu, uMsr);
1518#endif
1519 return false;
1520}
1521
1522
1523/**
1524 * Saves a set of guest MSRs back into the guest-CPU context.
1525 *
1526 * @param pVCpu The cross context virtual CPU structure.
1527 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
1528 * out-of-sync. Make sure to update the required fields
1529 * before using them.
1530 *
1531 * @remarks No-long-jump zone!!!
1532 */
1533static void hmR0VmxLazySaveGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1534{
1535 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1536 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1537
1538 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1539 {
1540 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1541#if HC_ARCH_BITS == 64
1542 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1543 {
1544 pMixedCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
1545 pMixedCtx->msrSTAR = ASMRdMsr(MSR_K6_STAR);
1546 pMixedCtx->msrSFMASK = ASMRdMsr(MSR_K8_SF_MASK);
1547 pMixedCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1548 }
1549#else
1550 NOREF(pMixedCtx);
1551#endif
1552 }
1553}
1554
1555
1556/**
1557 * Loads a set of guests MSRs to allow read/passthru to the guest.
1558 *
1559 * The name of this function is slightly confusing. This function does NOT
1560 * postpone loading, but loads the MSR right now. "hmR0VmxLazy" is simply a
1561 * common prefix for functions dealing with "lazy restoration" of the shared
1562 * MSRs.
1563 *
1564 * @param pVCpu The cross context virtual CPU structure.
1565 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
1566 * out-of-sync. Make sure to update the required fields
1567 * before using them.
1568 *
1569 * @remarks No-long-jump zone!!!
1570 */
1571static void hmR0VmxLazyLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1572{
1573 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1574 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1575
1576 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1577#if HC_ARCH_BITS == 64
1578 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1579 {
1580 /*
1581 * If the guest MSRs are not loaded -and- if all the guest MSRs are identical
1582 * to the MSRs on the CPU (which are the saved host MSRs, see assertion above) then
1583 * we can skip a few MSR writes.
1584 *
1585 * Otherwise, it implies either 1. they're not loaded, or 2. they're loaded but the
1586 * guest MSR values in the guest-CPU context might be different to what's currently
1587 * loaded in the CPU. In either case, we need to write the new guest MSR values to the
1588 * CPU, see @bugref{8728}.
1589 */
1590 if ( !(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1591 && pMixedCtx->msrKERNELGSBASE == pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr
1592 && pMixedCtx->msrLSTAR == pVCpu->hm.s.vmx.u64HostLStarMsr
1593 && pMixedCtx->msrSTAR == pVCpu->hm.s.vmx.u64HostStarMsr
1594 && pMixedCtx->msrSFMASK == pVCpu->hm.s.vmx.u64HostSFMaskMsr)
1595 {
1596#ifdef VBOX_STRICT
1597 Assert(ASMRdMsr(MSR_K8_KERNEL_GS_BASE) == pMixedCtx->msrKERNELGSBASE);
1598 Assert(ASMRdMsr(MSR_K8_LSTAR) == pMixedCtx->msrLSTAR);
1599 Assert(ASMRdMsr(MSR_K6_STAR) == pMixedCtx->msrSTAR);
1600 Assert(ASMRdMsr(MSR_K8_SF_MASK) == pMixedCtx->msrSFMASK);
1601#endif
1602 }
1603 else
1604 {
1605 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pMixedCtx->msrKERNELGSBASE);
1606 ASMWrMsr(MSR_K8_LSTAR, pMixedCtx->msrLSTAR);
1607 ASMWrMsr(MSR_K6_STAR, pMixedCtx->msrSTAR);
1608 ASMWrMsr(MSR_K8_SF_MASK, pMixedCtx->msrSFMASK);
1609 }
1610 }
1611#else
1612 RT_NOREF(pMixedCtx);
1613#endif
1614 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_LOADED_GUEST;
1615}
1616
1617
1618/**
1619 * Performs lazy restoration of the set of host MSRs if they were previously
1620 * loaded with guest MSR values.
1621 *
1622 * @param pVCpu The cross context virtual CPU structure.
1623 *
1624 * @remarks No-long-jump zone!!!
1625 * @remarks The guest MSRs should have been saved back into the guest-CPU
1626 * context by hmR0VmxSaveGuestLazyMsrs()!!!
1627 */
1628static void hmR0VmxLazyRestoreHostMsrs(PVMCPU pVCpu)
1629{
1630 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1631 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1632
1633 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1634 {
1635 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1636#if HC_ARCH_BITS == 64
1637 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1638 {
1639 ASMWrMsr(MSR_K8_LSTAR, pVCpu->hm.s.vmx.u64HostLStarMsr);
1640 ASMWrMsr(MSR_K6_STAR, pVCpu->hm.s.vmx.u64HostStarMsr);
1641 ASMWrMsr(MSR_K8_SF_MASK, pVCpu->hm.s.vmx.u64HostSFMaskMsr);
1642 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr);
1643 }
1644#endif
1645 }
1646 pVCpu->hm.s.vmx.fLazyMsrs &= ~(VMX_LAZY_MSRS_LOADED_GUEST | VMX_LAZY_MSRS_SAVED_HOST);
1647}
1648
1649
1650/**
1651 * Verifies that our cached values of the VMCS controls are all
1652 * consistent with what's actually present in the VMCS.
1653 *
1654 * @returns VBox status code.
1655 * @param pVCpu The cross context virtual CPU structure.
1656 */
1657static int hmR0VmxCheckVmcsCtls(PVMCPU pVCpu)
1658{
1659 uint32_t u32Val;
1660 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
1661 AssertRCReturn(rc, rc);
1662 AssertMsgReturn(pVCpu->hm.s.vmx.u32EntryCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32EntryCtls, u32Val),
1663 VERR_VMX_ENTRY_CTLS_CACHE_INVALID);
1664
1665 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);
1666 AssertRCReturn(rc, rc);
1667 AssertMsgReturn(pVCpu->hm.s.vmx.u32ExitCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ExitCtls, u32Val),
1668 VERR_VMX_EXIT_CTLS_CACHE_INVALID);
1669
1670 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);
1671 AssertRCReturn(rc, rc);
1672 AssertMsgReturn(pVCpu->hm.s.vmx.u32PinCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32PinCtls, u32Val),
1673 VERR_VMX_PIN_EXEC_CTLS_CACHE_INVALID);
1674
1675 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
1676 AssertRCReturn(rc, rc);
1677 AssertMsgReturn(pVCpu->hm.s.vmx.u32ProcCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ProcCtls, u32Val),
1678 VERR_VMX_PROC_EXEC_CTLS_CACHE_INVALID);
1679
1680 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1681 {
1682 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
1683 AssertRCReturn(rc, rc);
1684 AssertMsgReturn(pVCpu->hm.s.vmx.u32ProcCtls2 == u32Val,
1685 ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ProcCtls2, u32Val),
1686 VERR_VMX_PROC_EXEC2_CTLS_CACHE_INVALID);
1687 }
1688
1689 return VINF_SUCCESS;
1690}
1691
1692
1693#ifdef VBOX_STRICT
1694/**
1695 * Verifies that our cached host EFER value has not changed
1696 * since we cached it.
1697 *
1698 * @param pVCpu The cross context virtual CPU structure.
1699 */
1700static void hmR0VmxCheckHostEferMsr(PVMCPU pVCpu)
1701{
1702 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1703
1704 if (pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
1705 {
1706 uint64_t u64Val;
1707 int rc = VMXReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &u64Val);
1708 AssertRC(rc);
1709
1710 uint64_t u64HostEferMsr = ASMRdMsr(MSR_K6_EFER);
1711 AssertMsgReturnVoid(u64HostEferMsr == u64Val, ("u64HostEferMsr=%#RX64 u64Val=%#RX64\n", u64HostEferMsr, u64Val));
1712 }
1713}
1714
1715
1716/**
1717 * Verifies whether the guest/host MSR pairs in the auto-load/store area in the
1718 * VMCS are correct.
1719 *
1720 * @param pVCpu The cross context virtual CPU structure.
1721 */
1722static void hmR0VmxCheckAutoLoadStoreMsrs(PVMCPU pVCpu)
1723{
1724 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1725
1726 /* Verify MSR counts in the VMCS are what we think it should be. */
1727 uint32_t cMsrs;
1728 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1729 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1730
1731 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cMsrs); AssertRC(rc);
1732 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1733
1734 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1735 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1736
1737 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1738 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1739 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1740 {
1741 /* Verify that the MSRs are paired properly and that the host MSR has the correct value. */
1742 AssertMsgReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr, ("HostMsr=%#RX32 GuestMsr=%#RX32 cMsrs=%u\n", pHostMsr->u32Msr,
1743 pGuestMsr->u32Msr, cMsrs));
1744
1745 uint64_t u64Msr = ASMRdMsr(pHostMsr->u32Msr);
1746 AssertMsgReturnVoid(pHostMsr->u64Value == u64Msr, ("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
1747 pHostMsr->u32Msr, pHostMsr->u64Value, u64Msr, cMsrs));
1748
1749 /* Verify that the permissions are as expected in the MSR bitmap. */
1750 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1751 {
1752 VMXMSREXITREAD enmRead;
1753 VMXMSREXITWRITE enmWrite;
1754 rc = hmR0VmxGetMsrPermission(pVCpu, pGuestMsr->u32Msr, &enmRead, &enmWrite);
1755 AssertMsgReturnVoid(rc == VINF_SUCCESS, ("hmR0VmxGetMsrPermission! failed. rc=%Rrc\n", rc));
1756 if (pGuestMsr->u32Msr == MSR_K6_EFER)
1757 {
1758 AssertMsgReturnVoid(enmRead == VMXMSREXIT_INTERCEPT_READ, ("Passthru read for EFER!?\n"));
1759 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_INTERCEPT_WRITE, ("Passthru write for EFER!?\n"));
1760 }
1761 else
1762 {
1763 AssertMsgReturnVoid(enmRead == VMXMSREXIT_PASSTHRU_READ, ("u32Msr=%#RX32 cMsrs=%u No passthru read!\n",
1764 pGuestMsr->u32Msr, cMsrs));
1765 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_PASSTHRU_WRITE, ("u32Msr=%#RX32 cMsrs=%u No passthru write!\n",
1766 pGuestMsr->u32Msr, cMsrs));
1767 }
1768 }
1769 }
1770}
1771#endif /* VBOX_STRICT */
1772
1773
1774/**
1775 * Flushes the TLB using EPT.
1776 *
1777 * @returns VBox status code.
1778 * @param pVCpu The cross context virtual CPU structure of the calling
1779 * EMT. Can be NULL depending on @a enmFlush.
1780 * @param enmFlush Type of flush.
1781 *
1782 * @remarks Caller is responsible for making sure this function is called only
1783 * when NestedPaging is supported and providing @a enmFlush that is
1784 * supported by the CPU.
1785 * @remarks Can be called with interrupts disabled.
1786 */
1787static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush)
1788{
1789 uint64_t au64Descriptor[2];
1790 if (enmFlush == VMXFLUSHEPT_ALL_CONTEXTS)
1791 au64Descriptor[0] = 0;
1792 else
1793 {
1794 Assert(pVCpu);
1795 au64Descriptor[0] = pVCpu->hm.s.vmx.HCPhysEPTP;
1796 }
1797 au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
1798
1799 int rc = VMXR0InvEPT(enmFlush, &au64Descriptor[0]);
1800 AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvEPT %#x %RGv failed with %Rrc\n", enmFlush, pVCpu ? pVCpu->hm.s.vmx.HCPhysEPTP : 0,
1801 rc));
1802 if ( RT_SUCCESS(rc)
1803 && pVCpu)
1804 {
1805 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
1806 }
1807}
1808
1809
1810/**
1811 * Flushes the TLB using VPID.
1812 *
1813 * @returns VBox status code.
1814 * @param pVM The cross context VM structure.
1815 * @param pVCpu The cross context virtual CPU structure of the calling
1816 * EMT. Can be NULL depending on @a enmFlush.
1817 * @param enmFlush Type of flush.
1818 * @param GCPtr Virtual address of the page to flush (can be 0 depending
1819 * on @a enmFlush).
1820 *
1821 * @remarks Can be called with interrupts disabled.
1822 */
1823static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr)
1824{
1825 NOREF(pVM);
1826 AssertPtr(pVM);
1827 Assert(pVM->hm.s.vmx.fVpid);
1828
1829 uint64_t au64Descriptor[2];
1830 if (enmFlush == VMXFLUSHVPID_ALL_CONTEXTS)
1831 {
1832 au64Descriptor[0] = 0;
1833 au64Descriptor[1] = 0;
1834 }
1835 else
1836 {
1837 AssertPtr(pVCpu);
1838 AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1839 AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1840 au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
1841 au64Descriptor[1] = GCPtr;
1842 }
1843
1844 int rc = VMXR0InvVPID(enmFlush, &au64Descriptor[0]); NOREF(rc);
1845 AssertMsg(rc == VINF_SUCCESS,
1846 ("VMXR0InvVPID %#x %u %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
1847 if ( RT_SUCCESS(rc)
1848 && pVCpu)
1849 {
1850 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1851 }
1852}
1853
1854
1855/**
1856 * Invalidates a guest page by guest virtual address. Only relevant for
1857 * EPT/VPID, otherwise there is nothing really to invalidate.
1858 *
1859 * @returns VBox status code.
1860 * @param pVM The cross context VM structure.
1861 * @param pVCpu The cross context virtual CPU structure.
1862 * @param GCVirt Guest virtual address of the page to invalidate.
1863 */
1864VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1865{
1866 AssertPtr(pVM);
1867 AssertPtr(pVCpu);
1868 LogFlowFunc(("pVM=%p pVCpu=%p GCVirt=%RGv\n", pVM, pVCpu, GCVirt));
1869
1870 bool fFlushPending = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1871 if (!fFlushPending)
1872 {
1873 /*
1874 * We must invalidate the guest TLB entry in either case, we cannot ignore it even for the EPT case
1875 * See @bugref{6043} and @bugref{6177}.
1876 *
1877 * Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*() as this
1878 * function maybe called in a loop with individual addresses.
1879 */
1880 if (pVM->hm.s.vmx.fVpid)
1881 {
1882 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1883 {
1884 hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_INDIV_ADDR, GCVirt);
1885 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1886 }
1887 else
1888 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1889 }
1890 else if (pVM->hm.s.fNestedPaging)
1891 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1892 }
1893
1894 return VINF_SUCCESS;
1895}
1896
1897
1898/**
1899 * Invalidates a guest page by physical address. Only relevant for EPT/VPID,
1900 * otherwise there is nothing really to invalidate.
1901 *
1902 * @returns VBox status code.
1903 * @param pVM The cross context VM structure.
1904 * @param pVCpu The cross context virtual CPU structure.
1905 * @param GCPhys Guest physical address of the page to invalidate.
1906 */
1907VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
1908{
1909 NOREF(pVM); NOREF(GCPhys);
1910 LogFlowFunc(("%RGp\n", GCPhys));
1911
1912 /*
1913 * We cannot flush a page by guest-physical address. invvpid takes only a linear address while invept only flushes
1914 * by EPT not individual addresses. We update the force flag here and flush before the next VM-entry in hmR0VmxFlushTLB*().
1915 * This function might be called in a loop. This should cause a flush-by-EPT if EPT is in use. See @bugref{6568}.
1916 */
1917 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1918 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys);
1919 return VINF_SUCCESS;
1920}
1921
1922
1923/**
1924 * Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
1925 * case where neither EPT nor VPID is supported by the CPU.
1926 *
1927 * @param pVM The cross context VM structure.
1928 * @param pVCpu The cross context virtual CPU structure.
1929 * @param pCpu Pointer to the global HM struct.
1930 *
1931 * @remarks Called with interrupts disabled.
1932 */
1933static void hmR0VmxFlushTaggedTlbNone(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1934{
1935 AssertPtr(pVCpu);
1936 AssertPtr(pCpu);
1937 NOREF(pVM);
1938
1939 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1940
1941 Assert(pCpu->idCpu != NIL_RTCPUID);
1942 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1943 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1944 pVCpu->hm.s.fForceTLBFlush = false;
1945 return;
1946}
1947
1948
1949/**
1950 * Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
1951 *
1952 * @param pVM The cross context VM structure.
1953 * @param pVCpu The cross context virtual CPU structure.
1954 * @param pCpu Pointer to the global HM CPU struct.
1955 * @remarks All references to "ASID" in this function pertains to "VPID" in
1956 * Intel's nomenclature. The reason is, to avoid confusion in compare
1957 * statements since the host-CPU copies are named "ASID".
1958 *
1959 * @remarks Called with interrupts disabled.
1960 */
1961static void hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1962{
1963#ifdef VBOX_WITH_STATISTICS
1964 bool fTlbFlushed = false;
1965# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
1966# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
1967 if (!fTlbFlushed) \
1968 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
1969 } while (0)
1970#else
1971# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
1972# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
1973#endif
1974
1975 AssertPtr(pVM);
1976 AssertPtr(pCpu);
1977 AssertPtr(pVCpu);
1978 Assert(pCpu->idCpu != NIL_RTCPUID);
1979
1980 AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
1981 ("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
1982 "fNestedPaging=%RTbool fVpid=%RTbool", pVM->hm.s.fNestedPaging, pVM->hm.s.vmx.fVpid));
1983
1984 /*
1985 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
1986 * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
1987 * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
1988 */
1989 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1990 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1991 {
1992 ++pCpu->uCurrentAsid;
1993 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1994 {
1995 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
1996 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1997 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1998 }
1999
2000 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
2001 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2002 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2003
2004 /*
2005 * Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
2006 * invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
2007 */
2008 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2009 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2010 HMVMX_SET_TAGGED_TLB_FLUSHED();
2011 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH); /* Already flushed-by-EPT, skip doing it again below. */
2012 }
2013
2014 /* Check for explicit TLB flushes. */
2015 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2016 {
2017 /*
2018 * Changes to the EPT paging structure by VMM requires flushing by EPT as the CPU creates
2019 * guest-physical (only EPT-tagged) mappings while traversing the EPT tables when EPT is in use.
2020 * Flushing by VPID will only flush linear (only VPID-tagged) and combined (EPT+VPID tagged) mappings
2021 * but not guest-physical mappings.
2022 * See Intel spec. 28.3.2 "Creating and Using Cached Translation Information". See @bugref{6568}.
2023 */
2024 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2025 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2026 HMVMX_SET_TAGGED_TLB_FLUSHED();
2027 }
2028
2029 pVCpu->hm.s.fForceTLBFlush = false;
2030 HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
2031
2032 Assert(pVCpu->hm.s.idLastCpu == pCpu->idCpu);
2033 Assert(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes);
2034 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2035 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2036 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2037 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2038 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2039 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2040 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2041
2042 /* Update VMCS with the VPID. */
2043 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2044 AssertRC(rc);
2045
2046#undef HMVMX_SET_TAGGED_TLB_FLUSHED
2047}
2048
2049
2050/**
2051 * Flushes the tagged-TLB entries for EPT CPUs as necessary.
2052 *
2053 * @returns VBox status code.
2054 * @param pVM The cross context VM structure.
2055 * @param pVCpu The cross context virtual CPU structure.
2056 * @param pCpu Pointer to the global HM CPU struct.
2057 *
2058 * @remarks Called with interrupts disabled.
2059 */
2060static void hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2061{
2062 AssertPtr(pVM);
2063 AssertPtr(pVCpu);
2064 AssertPtr(pCpu);
2065 Assert(pCpu->idCpu != NIL_RTCPUID);
2066 AssertMsg(pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with NestedPaging disabled."));
2067 AssertMsg(!pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID enabled."));
2068
2069 /*
2070 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
2071 * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
2072 */
2073 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2074 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2075 {
2076 pVCpu->hm.s.fForceTLBFlush = true;
2077 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2078 }
2079
2080 /* Check for explicit TLB flushes. */
2081 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2082 {
2083 pVCpu->hm.s.fForceTLBFlush = true;
2084 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2085 }
2086
2087 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2088 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2089
2090 if (pVCpu->hm.s.fForceTLBFlush)
2091 {
2092 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2093 pVCpu->hm.s.fForceTLBFlush = false;
2094 }
2095}
2096
2097
2098/**
2099 * Flushes the tagged-TLB entries for VPID CPUs as necessary.
2100 *
2101 * @returns VBox status code.
2102 * @param pVM The cross context VM structure.
2103 * @param pVCpu The cross context virtual CPU structure.
2104 * @param pCpu Pointer to the global HM CPU struct.
2105 *
2106 * @remarks Called with interrupts disabled.
2107 */
2108static void hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2109{
2110 AssertPtr(pVM);
2111 AssertPtr(pVCpu);
2112 AssertPtr(pCpu);
2113 Assert(pCpu->idCpu != NIL_RTCPUID);
2114 AssertMsg(pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked with VPID disabled."));
2115 AssertMsg(!pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging enabled"));
2116
2117 /*
2118 * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
2119 * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
2120 * or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
2121 */
2122 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2123 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2124 {
2125 pVCpu->hm.s.fForceTLBFlush = true;
2126 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2127 }
2128
2129 /* Check for explicit TLB flushes. */
2130 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2131 {
2132 /*
2133 * If we ever support VPID flush combinations other than ALL or SINGLE-context (see hmR0VmxSetupTaggedTlb())
2134 * we would need to explicitly flush in this case (add an fExplicitFlush = true here and change the
2135 * pCpu->fFlushAsidBeforeUse check below to include fExplicitFlush's too) - an obscure corner case.
2136 */
2137 pVCpu->hm.s.fForceTLBFlush = true;
2138 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2139 }
2140
2141 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2142 if (pVCpu->hm.s.fForceTLBFlush)
2143 {
2144 ++pCpu->uCurrentAsid;
2145 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
2146 {
2147 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
2148 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
2149 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
2150 }
2151
2152 pVCpu->hm.s.fForceTLBFlush = false;
2153 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2154 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
2155 if (pCpu->fFlushAsidBeforeUse)
2156 {
2157 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
2158 hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
2159 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
2160 {
2161 hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
2162 pCpu->fFlushAsidBeforeUse = false;
2163 }
2164 else
2165 {
2166 /* hmR0VmxSetupTaggedTlb() ensures we never get here. Paranoia. */
2167 AssertMsgFailed(("Unsupported VPID-flush context type.\n"));
2168 }
2169 }
2170 }
2171
2172 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2173 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2174 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2175 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2176 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2177 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2178 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2179
2180 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2181 AssertRC(rc);
2182}
2183
2184
2185/**
2186 * Flushes the guest TLB entry based on CPU capabilities.
2187 *
2188 * @param pVCpu The cross context virtual CPU structure.
2189 * @param pCpu Pointer to the global HM CPU struct.
2190 */
2191DECLINLINE(void) hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2192{
2193#ifdef HMVMX_ALWAYS_FLUSH_TLB
2194 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2195#endif
2196 PVM pVM = pVCpu->CTX_SUFF(pVM);
2197 switch (pVM->hm.s.vmx.uFlushTaggedTlb)
2198 {
2199 case HMVMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVM, pVCpu, pCpu); break;
2200 case HMVMX_FLUSH_TAGGED_TLB_EPT: hmR0VmxFlushTaggedTlbEpt(pVM, pVCpu, pCpu); break;
2201 case HMVMX_FLUSH_TAGGED_TLB_VPID: hmR0VmxFlushTaggedTlbVpid(pVM, pVCpu, pCpu); break;
2202 case HMVMX_FLUSH_TAGGED_TLB_NONE: hmR0VmxFlushTaggedTlbNone(pVM, pVCpu, pCpu); break;
2203 default:
2204 AssertMsgFailed(("Invalid flush-tag function identifier\n"));
2205 break;
2206 }
2207
2208 /* Don't assert that VMCPU_FF_TLB_FLUSH should no longer be pending. It can be set by other EMTs. */
2209}
2210
2211
2212/**
2213 * Sets up the appropriate tagged TLB-flush level and handler for flushing guest
2214 * TLB entries from the host TLB before VM-entry.
2215 *
2216 * @returns VBox status code.
2217 * @param pVM The cross context VM structure.
2218 */
2219static int hmR0VmxSetupTaggedTlb(PVM pVM)
2220{
2221 /*
2222 * Determine optimal flush type for Nested Paging.
2223 * We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup unrestricted
2224 * guest execution (see hmR3InitFinalizeR0()).
2225 */
2226 if (pVM->hm.s.fNestedPaging)
2227 {
2228 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
2229 {
2230 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
2231 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_SINGLE_CONTEXT;
2232 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
2233 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_ALL_CONTEXTS;
2234 else
2235 {
2236 /* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
2237 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2238 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED;
2239 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2240 }
2241
2242 /* Make sure the write-back cacheable memory type for EPT is supported. */
2243 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
2244 {
2245 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2246 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_MEM_TYPE_NOT_WB;
2247 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2248 }
2249
2250 /* EPT requires a page-walk length of 4. */
2251 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
2252 {
2253 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2254 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED;
2255 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2256 }
2257 }
2258 else
2259 {
2260 /* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
2261 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2262 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_INVEPT_UNAVAILABLE;
2263 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2264 }
2265 }
2266
2267 /*
2268 * Determine optimal flush type for VPID.
2269 */
2270 if (pVM->hm.s.vmx.fVpid)
2271 {
2272 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
2273 {
2274 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
2275 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_SINGLE_CONTEXT;
2276 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
2277 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_ALL_CONTEXTS;
2278 else
2279 {
2280 /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
2281 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
2282 LogRel(("hmR0VmxSetupTaggedTlb: Only INDIV_ADDR supported. Ignoring VPID.\n"));
2283 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
2284 LogRel(("hmR0VmxSetupTaggedTlb: Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
2285 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
2286 pVM->hm.s.vmx.fVpid = false;
2287 }
2288 }
2289 else
2290 {
2291 /* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
2292 Log4(("hmR0VmxSetupTaggedTlb: VPID supported without INVEPT support. Ignoring VPID.\n"));
2293 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
2294 pVM->hm.s.vmx.fVpid = false;
2295 }
2296 }
2297
2298 /*
2299 * Setup the handler for flushing tagged-TLBs.
2300 */
2301 if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
2302 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT_VPID;
2303 else if (pVM->hm.s.fNestedPaging)
2304 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT;
2305 else if (pVM->hm.s.vmx.fVpid)
2306 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_VPID;
2307 else
2308 pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_NONE;
2309 return VINF_SUCCESS;
2310}
2311
2312
2313/**
2314 * Sets up pin-based VM-execution controls in the VMCS.
2315 *
2316 * @returns VBox status code.
2317 * @param pVM The cross context VM structure.
2318 * @param pVCpu The cross context virtual CPU structure.
2319 */
2320static int hmR0VmxSetupPinCtls(PVM pVM, PVMCPU pVCpu)
2321{
2322 AssertPtr(pVM);
2323 AssertPtr(pVCpu);
2324
2325 uint32_t val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0; /* Bits set here must always be set. */
2326 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
2327
2328 val |= VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT /* External interrupts cause a VM-exit. */
2329 | VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT; /* Non-maskable interrupts (NMIs) cause a VM-exit. */
2330
2331 if (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
2332 val |= VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
2333
2334 /* Enable the VMX preemption timer. */
2335 if (pVM->hm.s.vmx.fUsePreemptTimer)
2336 {
2337 Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
2338 val |= VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER;
2339 }
2340
2341#if 0
2342 /* Enable posted-interrupt processing. */
2343 if (pVM->hm.s.fPostedIntrs)
2344 {
2345 Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
2346 Assert(pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
2347 val |= VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR;
2348 }
2349#endif
2350
2351 if ((val & zap) != val)
2352 {
2353 LogRel(("hmR0VmxSetupPinCtls: Invalid pin-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
2354 pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0, val, zap));
2355 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
2356 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2357 }
2358
2359 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, val);
2360 AssertRCReturn(rc, rc);
2361
2362 pVCpu->hm.s.vmx.u32PinCtls = val;
2363 return rc;
2364}
2365
2366
2367/**
2368 * Sets up processor-based VM-execution controls in the VMCS.
2369 *
2370 * @returns VBox status code.
2371 * @param pVM The cross context VM structure.
2372 * @param pVCpu The cross context virtual CPU structure.
2373 */
2374static int hmR0VmxSetupProcCtls(PVM pVM, PVMCPU pVCpu)
2375{
2376 AssertPtr(pVM);
2377 AssertPtr(pVCpu);
2378
2379 int rc = VERR_INTERNAL_ERROR_5;
2380 uint32_t val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
2381 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2382
2383 val |= VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT /* HLT causes a VM-exit. */
2384 | VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2385 | VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2386 | VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2387 | VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2388 | VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2389 | VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2390
2391 /* We toggle VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2392 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT)
2393 || (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT))
2394 {
2395 LogRel(("hmR0VmxSetupProcCtls: Unsupported VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT combo!"));
2396 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2397 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2398 }
2399
2400 /* Without Nested Paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
2401 if (!pVM->hm.s.fNestedPaging)
2402 {
2403 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest); /* Paranoia. */
2404 val |= VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT
2405 | VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
2406 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
2407 }
2408
2409 /* Use TPR shadowing if supported by the CPU. */
2410 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
2411 {
2412 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
2413 Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
2414 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
2415 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
2416 AssertRCReturn(rc, rc);
2417
2418 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2419 /* CR8 writes cause a VM-exit based on TPR threshold. */
2420 Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT));
2421 Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT));
2422 }
2423 else
2424 {
2425 /*
2426 * Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is invalid on 32-bit Intel CPUs.
2427 * Set this control only for 64-bit guests.
2428 */
2429 if (pVM->hm.s.fAllow64BitGuests)
2430 {
2431 val |= VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2432 | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2433 }
2434 }
2435
2436 /* Use MSR-bitmaps if supported by the CPU. */
2437 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
2438 {
2439 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS;
2440
2441 Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2442 Assert(!(pVCpu->hm.s.vmx.HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
2443 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2444 AssertRCReturn(rc, rc);
2445
2446 /*
2447 * The guest can access the following MSRs (read, write) without causing VM-exits; they are loaded/stored
2448 * automatically using dedicated fields in the VMCS.
2449 */
2450 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2451 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2452 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2453 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2454 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_FS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2455
2456#if HC_ARCH_BITS == 64
2457 /*
2458 * Set passthru permissions for the following MSRs (mandatory for VT-x) required for 64-bit guests.
2459 */
2460 if (pVM->hm.s.fAllow64BitGuests)
2461 {
2462 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_LSTAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2463 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_STAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2464 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_SF_MASK, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2465 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2466 }
2467#endif
2468 /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */
2469 }
2470
2471 /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2472 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
2473 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
2474
2475 if ((val & zap) != val)
2476 {
2477 LogRel(("hmR0VmxSetupProcCtls: Invalid processor-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
2478 pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0, val, zap));
2479 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2480 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2481 }
2482
2483 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, val);
2484 AssertRCReturn(rc, rc);
2485
2486 pVCpu->hm.s.vmx.u32ProcCtls = val;
2487
2488 /*
2489 * Secondary processor-based VM-execution controls.
2490 */
2491 if (RT_LIKELY(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL))
2492 {
2493 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */
2494 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2495
2496 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
2497 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT; /* WBINVD causes a VM-exit. */
2498
2499 if (pVM->hm.s.fNestedPaging)
2500 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT; /* Enable EPT. */
2501 else
2502 {
2503 /*
2504 * Without Nested Paging, INVPCID should cause a VM-exit. Enabling this bit causes the CPU to refer to
2505 * VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT when INVPCID is executed by the guest.
2506 * See Intel spec. 25.4 "Changes to instruction behaviour in VMX non-root operation".
2507 */
2508 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_INVPCID)
2509 val |= VMX_VMCS_CTRL_PROC_EXEC2_INVPCID;
2510 }
2511
2512 if (pVM->hm.s.vmx.fVpid)
2513 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID; /* Enable VPID. */
2514
2515 if (pVM->hm.s.vmx.fUnrestrictedGuest)
2516 val |= VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST; /* Enable Unrestricted Execution. */
2517
2518#if 0
2519 if (pVM->hm.s.fVirtApicRegs)
2520 {
2521 Assert(pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
2522 val |= VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT; /* Enable APIC-register virtualization. */
2523
2524 Assert(pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
2525 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY; /* Enable virtual-interrupt delivery. */
2526 }
2527#endif
2528
2529 /* Enable Virtual-APIC page accesses if supported by the CPU. This is essentially where the TPR shadow resides. */
2530 /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
2531 * done dynamically. */
2532 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2533 {
2534 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
2535 Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
2536 val |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC; /* Virtualize APIC accesses. */
2537 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
2538 AssertRCReturn(rc, rc);
2539 }
2540
2541 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
2542 val |= VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP; /* Enable RDTSCP support. */
2543
2544 if ( pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT
2545 && pVM->hm.s.vmx.cPleGapTicks
2546 && pVM->hm.s.vmx.cPleWindowTicks)
2547 {
2548 val |= VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT; /* Enable pause-loop exiting. */
2549
2550 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks);
2551 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks);
2552 AssertRCReturn(rc, rc);
2553 }
2554
2555 if ((val & zap) != val)
2556 {
2557 LogRel(("hmR0VmxSetupProcCtls: Invalid secondary processor-based VM-execution controls combo! "
2558 "cpu=%#RX64 val=%#RX64 zap=%#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0, val, zap));
2559 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
2560 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2561 }
2562
2563 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, val);
2564 AssertRCReturn(rc, rc);
2565
2566 pVCpu->hm.s.vmx.u32ProcCtls2 = val;
2567 }
2568 else if (RT_UNLIKELY(pVM->hm.s.vmx.fUnrestrictedGuest))
2569 {
2570 LogRel(("hmR0VmxSetupProcCtls: Unrestricted Guest set as true when secondary processor-based VM-execution controls not "
2571 "available\n"));
2572 pVCpu->hm.s.u32HMError = VMX_UFC_INVALID_UX_COMBO;
2573 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2574 }
2575
2576 return VINF_SUCCESS;
2577}
2578
2579
2580/**
2581 * Sets up miscellaneous (everything other than Pin & Processor-based
2582 * VM-execution) control fields in the VMCS.
2583 *
2584 * @returns VBox status code.
2585 * @param pVM The cross context VM structure.
2586 * @param pVCpu The cross context virtual CPU structure.
2587 */
2588static int hmR0VmxSetupMiscCtls(PVM pVM, PVMCPU pVCpu)
2589{
2590 NOREF(pVM);
2591 AssertPtr(pVM);
2592 AssertPtr(pVCpu);
2593
2594 int rc = VERR_GENERAL_FAILURE;
2595
2596 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2597#if 0
2598 /* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxLoadGuestCR3AndCR4())*/
2599 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
2600 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
2601
2602 /*
2603 * Set MASK & MATCH to 0. VMX checks if GuestPFErrCode & MASK == MATCH. If equal (in our case it always is)
2604 * and if the X86_XCPT_PF bit in the exception bitmap is set it causes a VM-exit, if clear doesn't cause an exit.
2605 * We thus use the exception bitmap to control it rather than use both.
2606 */
2607 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
2608 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
2609
2610 /** @todo Explore possibility of using IO-bitmaps. */
2611 /* All IO & IOIO instructions cause VM-exits. */
2612 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
2613 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
2614
2615 /* Initialize the MSR-bitmap area. */
2616 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
2617 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
2618 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
2619 AssertRCReturn(rc, rc);
2620#endif
2621
2622 /* Setup MSR auto-load/store area. */
2623 Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
2624 Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf)); /* Lower 4 bits MBZ. */
2625 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2626 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2627 AssertRCReturn(rc, rc);
2628
2629 Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
2630 Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf)); /* Lower 4 bits MBZ. */
2631 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
2632 AssertRCReturn(rc, rc);
2633
2634 /* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
2635 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
2636 AssertRCReturn(rc, rc);
2637
2638 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2639#if 0
2640 /* Setup debug controls */
2641 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0); /** @todo We don't support IA32_DEBUGCTL MSR. Should we? */
2642 rc |= VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
2643 AssertRCReturn(rc, rc);
2644#endif
2645
2646 return rc;
2647}
2648
2649
2650/**
2651 * Sets up the initial exception bitmap in the VMCS based on static conditions.
2652 *
2653 * We shall setup those exception intercepts that don't change during the
2654 * lifetime of the VM here. The rest are done dynamically while loading the
2655 * guest state.
2656 *
2657 * @returns VBox status code.
2658 * @param pVM The cross context VM structure.
2659 * @param pVCpu The cross context virtual CPU structure.
2660 */
2661static int hmR0VmxInitXcptBitmap(PVM pVM, PVMCPU pVCpu)
2662{
2663 AssertPtr(pVM);
2664 AssertPtr(pVCpu);
2665
2666 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2667
2668 uint32_t u32XcptBitmap = 0;
2669
2670 /* Must always intercept #AC to prevent the guest from hanging the CPU. */
2671 u32XcptBitmap |= RT_BIT_32(X86_XCPT_AC);
2672
2673 /* Because we need to maintain the DR6 state even when intercepting DRx reads
2674 and writes, and because recursive #DBs can cause the CPU hang, we must always
2675 intercept #DB. */
2676 u32XcptBitmap |= RT_BIT_32(X86_XCPT_DB);
2677
2678 /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
2679 if (!pVM->hm.s.fNestedPaging)
2680 u32XcptBitmap |= RT_BIT(X86_XCPT_PF);
2681
2682 pVCpu->hm.s.vmx.u32XcptBitmap = u32XcptBitmap;
2683 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);
2684 AssertRCReturn(rc, rc);
2685 return rc;
2686}
2687
2688
2689/**
2690 * Sets up the initial guest-state mask. The guest-state mask is consulted
2691 * before reading guest-state fields from the VMCS as VMREADs can be expensive
2692 * for the nested virtualization case (as it would cause a VM-exit).
2693 *
2694 * @param pVCpu The cross context virtual CPU structure.
2695 */
2696static int hmR0VmxInitUpdatedGuestStateMask(PVMCPU pVCpu)
2697{
2698 /* Initially the guest-state is up-to-date as there is nothing in the VMCS. */
2699 HMVMXCPU_GST_RESET_TO(pVCpu, HMVMX_UPDATED_GUEST_ALL);
2700 return VINF_SUCCESS;
2701}
2702
2703
2704/**
2705 * Does per-VM VT-x initialization.
2706 *
2707 * @returns VBox status code.
2708 * @param pVM The cross context VM structure.
2709 */
2710VMMR0DECL(int) VMXR0InitVM(PVM pVM)
2711{
2712 LogFlowFunc(("pVM=%p\n", pVM));
2713
2714 int rc = hmR0VmxStructsAlloc(pVM);
2715 if (RT_FAILURE(rc))
2716 {
2717 LogRel(("VMXR0InitVM: hmR0VmxStructsAlloc failed! rc=%Rrc\n", rc));
2718 return rc;
2719 }
2720
2721 return VINF_SUCCESS;
2722}
2723
2724
2725/**
2726 * Does per-VM VT-x termination.
2727 *
2728 * @returns VBox status code.
2729 * @param pVM The cross context VM structure.
2730 */
2731VMMR0DECL(int) VMXR0TermVM(PVM pVM)
2732{
2733 LogFlowFunc(("pVM=%p\n", pVM));
2734
2735#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2736 if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
2737 ASMMemZero32(pVM->hm.s.vmx.pvScratch, PAGE_SIZE);
2738#endif
2739 hmR0VmxStructsFree(pVM);
2740 return VINF_SUCCESS;
2741}
2742
2743
2744/**
2745 * Sets up the VM for execution under VT-x.
2746 * This function is only called once per-VM during initialization.
2747 *
2748 * @returns VBox status code.
2749 * @param pVM The cross context VM structure.
2750 */
2751VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
2752{
2753 AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
2754 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2755
2756 LogFlowFunc(("pVM=%p\n", pVM));
2757
2758 /*
2759 * Without UnrestrictedGuest, pRealModeTSS and pNonPagingModeEPTPageTable *must* always be allocated.
2760 * We no longer support the highly unlikely case of UnrestrictedGuest without pRealModeTSS. See hmR3InitFinalizeR0Intel().
2761 */
2762 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
2763 && ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
2764 || !pVM->hm.s.vmx.pRealModeTSS))
2765 {
2766 LogRel(("VMXR0SetupVM: Invalid real-on-v86 state.\n"));
2767 return VERR_INTERNAL_ERROR;
2768 }
2769
2770 /* Initialize these always, see hmR3InitFinalizeR0().*/
2771 pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NONE;
2772 pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NONE;
2773
2774 /* Setup the tagged-TLB flush handlers. */
2775 int rc = hmR0VmxSetupTaggedTlb(pVM);
2776 if (RT_FAILURE(rc))
2777 {
2778 LogRel(("VMXR0SetupVM: hmR0VmxSetupTaggedTlb failed! rc=%Rrc\n", rc));
2779 return rc;
2780 }
2781
2782 /* Check if we can use the VMCS controls for swapping the EFER MSR. */
2783 Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
2784#if HC_ARCH_BITS == 64
2785 if ( (pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
2786 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
2787 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR))
2788 {
2789 pVM->hm.s.vmx.fSupportsVmcsEfer = true;
2790 }
2791#endif
2792
2793 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
2794 RTCCUINTREG uHostCR4 = ASMGetCR4();
2795 if (RT_UNLIKELY(!(uHostCR4 & X86_CR4_VMXE)))
2796 return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
2797
2798 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2799 {
2800 PVMCPU pVCpu = &pVM->aCpus[i];
2801 AssertPtr(pVCpu);
2802 AssertPtr(pVCpu->hm.s.vmx.pvVmcs);
2803
2804 /* Log the VCPU pointers, useful for debugging SMP VMs. */
2805 Log4(("VMXR0SetupVM: pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
2806
2807 /* Initialize the VM-exit history array with end-of-array markers (UINT16_MAX). */
2808 Assert(!pVCpu->hm.s.idxExitHistoryFree);
2809 HMCPU_EXIT_HISTORY_RESET(pVCpu);
2810
2811 /* Set revision dword at the beginning of the VMCS structure. */
2812 *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
2813
2814 /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
2815 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2816 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2817 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2818
2819 /* Load this VMCS as the current VMCS. */
2820 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2821 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2822 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2823
2824 rc = hmR0VmxSetupPinCtls(pVM, pVCpu);
2825 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2826 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2827
2828 rc = hmR0VmxSetupProcCtls(pVM, pVCpu);
2829 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2830 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2831
2832 rc = hmR0VmxSetupMiscCtls(pVM, pVCpu);
2833 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2834 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2835
2836 rc = hmR0VmxInitXcptBitmap(pVM, pVCpu);
2837 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2838 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2839
2840 rc = hmR0VmxInitUpdatedGuestStateMask(pVCpu);
2841 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitUpdatedGuestStateMask failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2842 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2843
2844#if HC_ARCH_BITS == 32
2845 rc = hmR0VmxInitVmcsReadCache(pVM, pVCpu);
2846 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2847 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2848#endif
2849
2850 /* Re-sync the CPU's internal data into our VMCS memory region & reset the launch state to "clear". */
2851 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2852 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2853 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2854
2855 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
2856
2857 hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc);
2858 }
2859
2860 return VINF_SUCCESS;
2861}
2862
2863
2864/**
2865 * Saves the host control registers (CR0, CR3, CR4) into the host-state area in
2866 * the VMCS.
2867 *
2868 * @returns VBox status code.
2869 * @param pVM The cross context VM structure.
2870 * @param pVCpu The cross context virtual CPU structure.
2871 */
2872DECLINLINE(int) hmR0VmxSaveHostControlRegs(PVM pVM, PVMCPU pVCpu)
2873{
2874 NOREF(pVM); NOREF(pVCpu);
2875
2876 RTCCUINTREG uReg = ASMGetCR0();
2877 int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
2878 AssertRCReturn(rc, rc);
2879
2880 uReg = ASMGetCR3();
2881 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
2882 AssertRCReturn(rc, rc);
2883
2884 uReg = ASMGetCR4();
2885 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
2886 AssertRCReturn(rc, rc);
2887 return rc;
2888}
2889
2890
2891#if HC_ARCH_BITS == 64
2892/**
2893 * Macro for adjusting host segment selectors to satisfy VT-x's VM-entry
2894 * requirements. See hmR0VmxSaveHostSegmentRegs().
2895 */
2896# define VMXLOCAL_ADJUST_HOST_SEG(seg, selValue) \
2897 if ((selValue) & (X86_SEL_RPL | X86_SEL_LDT)) \
2898 { \
2899 bool fValidSelector = true; \
2900 if ((selValue) & X86_SEL_LDT) \
2901 { \
2902 uint32_t uAttr = ASMGetSegAttr((selValue)); \
2903 fValidSelector = RT_BOOL(uAttr != UINT32_MAX && (uAttr & X86_DESC_P)); \
2904 } \
2905 if (fValidSelector) \
2906 { \
2907 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_##seg; \
2908 pVCpu->hm.s.vmx.RestoreHost.uHostSel##seg = (selValue); \
2909 } \
2910 (selValue) = 0; \
2911 }
2912#endif
2913
2914
2915/**
2916 * Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
2917 * the host-state area in the VMCS.
2918 *
2919 * @returns VBox status code.
2920 * @param pVM The cross context VM structure.
2921 * @param pVCpu The cross context virtual CPU structure.
2922 */
2923DECLINLINE(int) hmR0VmxSaveHostSegmentRegs(PVM pVM, PVMCPU pVCpu)
2924{
2925 int rc = VERR_INTERNAL_ERROR_5;
2926
2927#if HC_ARCH_BITS == 64
2928 /*
2929 * If we've executed guest code using VT-x, the host-state bits will be messed up. We
2930 * should -not- save the messed up state without restoring the original host-state. See @bugref{7240}.
2931 *
2932 * This apparently can happen (most likely the FPU changes), deal with it rather than asserting.
2933 * Was observed booting Solaris10u10 32-bit guest.
2934 */
2935 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
2936 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
2937 {
2938 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags,
2939 pVCpu->idCpu));
2940 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
2941 }
2942 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
2943#else
2944 RT_NOREF(pVCpu);
2945#endif
2946
2947 /*
2948 * Host DS, ES, FS and GS segment registers.
2949 */
2950#if HC_ARCH_BITS == 64
2951 RTSEL uSelDS = ASMGetDS();
2952 RTSEL uSelES = ASMGetES();
2953 RTSEL uSelFS = ASMGetFS();
2954 RTSEL uSelGS = ASMGetGS();
2955#else
2956 RTSEL uSelDS = 0;
2957 RTSEL uSelES = 0;
2958 RTSEL uSelFS = 0;
2959 RTSEL uSelGS = 0;
2960#endif
2961
2962 /*
2963 * Host CS and SS segment registers.
2964 */
2965 RTSEL uSelCS = ASMGetCS();
2966 RTSEL uSelSS = ASMGetSS();
2967
2968 /*
2969 * Host TR segment register.
2970 */
2971 RTSEL uSelTR = ASMGetTR();
2972
2973#if HC_ARCH_BITS == 64
2974 /*
2975 * Determine if the host segment registers are suitable for VT-x. Otherwise use zero to gain VM-entry and restore them
2976 * before we get preempted. See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
2977 */
2978 VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
2979 VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
2980 VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
2981 VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
2982# undef VMXLOCAL_ADJUST_HOST_SEG
2983#endif
2984
2985 /* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
2986 Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
2987 Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
2988 Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
2989 Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
2990 Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
2991 Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
2992 Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
2993 Assert(uSelCS);
2994 Assert(uSelTR);
2995
2996 /* Assertion is right but we would not have updated u32ExitCtls yet. */
2997#if 0
2998 if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE))
2999 Assert(uSelSS != 0);
3000#endif
3001
3002 /* Write these host selector fields into the host-state area in the VMCS. */
3003 rc = VMXWriteVmcs32(VMX_VMCS16_HOST_CS_SEL, uSelCS);
3004 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_SS_SEL, uSelSS);
3005#if HC_ARCH_BITS == 64
3006 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_DS_SEL, uSelDS);
3007 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_ES_SEL, uSelES);
3008 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FS_SEL, uSelFS);
3009 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_GS_SEL, uSelGS);
3010#else
3011 NOREF(uSelDS);
3012 NOREF(uSelES);
3013 NOREF(uSelFS);
3014 NOREF(uSelGS);
3015#endif
3016 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_TR_SEL, uSelTR);
3017 AssertRCReturn(rc, rc);
3018
3019 /*
3020 * Host GDTR and IDTR.
3021 */
3022 RTGDTR Gdtr;
3023 RTIDTR Idtr;
3024 RT_ZERO(Gdtr);
3025 RT_ZERO(Idtr);
3026 ASMGetGDTR(&Gdtr);
3027 ASMGetIDTR(&Idtr);
3028 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
3029 rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
3030 AssertRCReturn(rc, rc);
3031
3032#if HC_ARCH_BITS == 64
3033 /*
3034 * Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps them to the
3035 * maximum limit (0xffff) on every VM-exit.
3036 */
3037 if (Gdtr.cbGdt != 0xffff)
3038 {
3039 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDTR;
3040 AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
3041 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3042 }
3043
3044 /*
3045 * IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT"
3046 * and Intel spec. 6.2 "Exception and Interrupt Vectors".) Therefore if the host has the limit as 0xfff, VT-x
3047 * bloating the limit to 0xffff shouldn't cause any different CPU behavior. However, several hosts either insists
3048 * on 0xfff being the limit (Windows Patch Guard) or uses the limit for other purposes (darwin puts the CPU ID in there
3049 * but botches sidt alignment in at least one consumer). So, we're only allowing IDTR.LIMIT to be left at 0xffff on
3050 * hosts where we are pretty sure it won't cause trouble.
3051 */
3052# if defined(RT_OS_LINUX) || defined(RT_OS_SOLARIS)
3053 if (Idtr.cbIdt < 0x0fff)
3054# else
3055 if (Idtr.cbIdt != 0xffff)
3056# endif
3057 {
3058 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_IDTR;
3059 AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
3060 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
3061 }
3062#endif
3063
3064 /*
3065 * Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI and RPL bits
3066 * is effectively what the CPU does for "scaling by 8". TI is always 0 and RPL should be too in most cases.
3067 */
3068 AssertMsgReturn((uSelTR | X86_SEL_RPL_LDT) <= Gdtr.cbGdt,
3069 ("hmR0VmxSaveHostSegmentRegs: TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt),
3070 VERR_VMX_INVALID_HOST_STATE);
3071
3072 PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
3073#if HC_ARCH_BITS == 64
3074 uintptr_t uTRBase = X86DESC64_BASE(pDesc);
3075
3076 /*
3077 * VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on all VM-exits.
3078 * The type is the same for 64-bit busy TSS[1]. The limit needs manual restoration if the host has something else.
3079 * Task switching is not supported in 64-bit mode[2], but the limit still matters as IOPM is supported in 64-bit mode.
3080 * Restoring the limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
3081 *
3082 * [1] See Intel spec. 3.5 "System Descriptor Types".
3083 * [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
3084 */
3085 Assert(pDesc->System.u4Type == 11);
3086 if ( pDesc->System.u16LimitLow != 0x67
3087 || pDesc->System.u4LimitHigh)
3088 {
3089 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_TR;
3090 /* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */
3091 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)
3092 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_READ_ONLY;
3093 pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
3094
3095 /* Store the GDTR here as we need it while restoring TR. */
3096 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3097 }
3098#else
3099 NOREF(pVM);
3100 uintptr_t uTRBase = X86DESC_BASE(pDesc);
3101#endif
3102 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_TR_BASE, uTRBase);
3103 AssertRCReturn(rc, rc);
3104
3105 /*
3106 * Host FS base and GS base.
3107 */
3108#if HC_ARCH_BITS == 64
3109 uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
3110 uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
3111 rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
3112 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
3113 AssertRCReturn(rc, rc);
3114
3115 /* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
3116 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
3117 pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
3118 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
3119 pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
3120#endif
3121 return rc;
3122}
3123
3124
3125/**
3126 * Saves certain host MSRs in the VM-exit MSR-load area and some in the
3127 * host-state area of the VMCS. Theses MSRs will be automatically restored on
3128 * the host after every successful VM-exit.
3129 *
3130 * @returns VBox status code.
3131 * @param pVM The cross context VM structure.
3132 * @param pVCpu The cross context virtual CPU structure.
3133 *
3134 * @remarks No-long-jump zone!!!
3135 */
3136DECLINLINE(int) hmR0VmxSaveHostMsrs(PVM pVM, PVMCPU pVCpu)
3137{
3138 NOREF(pVM);
3139
3140 AssertPtr(pVCpu);
3141 AssertPtr(pVCpu->hm.s.vmx.pvHostMsr);
3142
3143 /*
3144 * Save MSRs that we restore lazily (due to preemption or transition to ring-3)
3145 * rather than swapping them on every VM-entry.
3146 */
3147 hmR0VmxLazySaveHostMsrs(pVCpu);
3148
3149 /*
3150 * Host Sysenter MSRs.
3151 */
3152 int rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
3153#if HC_ARCH_BITS == 32
3154 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
3155 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
3156#else
3157 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
3158 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
3159#endif
3160 AssertRCReturn(rc, rc);
3161
3162 /*
3163 * Host EFER MSR.
3164 * If the CPU supports the newer VMCS controls for managing EFER, use it.
3165 * Otherwise it's done as part of auto-load/store MSR area in the VMCS, see hmR0VmxLoadGuestMsrs().
3166 */
3167 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
3168 {
3169 rc = VMXWriteVmcs64(VMX_VMCS64_HOST_EFER_FULL, pVM->hm.s.vmx.u64HostEfer);
3170 AssertRCReturn(rc, rc);
3171 }
3172
3173 /** @todo IA32_PERF_GLOBALCTRL, IA32_PAT also see
3174 * hmR0VmxLoadGuestExitCtls() !! */
3175
3176 return rc;
3177}
3178
3179
3180/**
3181 * Figures out if we need to swap the EFER MSR which is particularly expensive.
3182 *
3183 * We check all relevant bits. For now, that's everything besides LMA/LME, as
3184 * these two bits are handled by VM-entry, see hmR0VmxLoadGuestExitCtls() and
3185 * hmR0VMxLoadGuestEntryCtls().
3186 *
3187 * @returns true if we need to load guest EFER, false otherwise.
3188 * @param pVCpu The cross context virtual CPU structure.
3189 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3190 * out-of-sync. Make sure to update the required fields
3191 * before using them.
3192 *
3193 * @remarks Requires EFER, CR4.
3194 * @remarks No-long-jump zone!!!
3195 */
3196static bool hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3197{
3198#ifdef HMVMX_ALWAYS_SWAP_EFER
3199 return true;
3200#endif
3201
3202#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
3203 /* For 32-bit hosts running 64-bit guests, we always swap EFER in the world-switcher. Nothing to do here. */
3204 if (CPUMIsGuestInLongMode(pVCpu))
3205 return false;
3206#endif
3207
3208 PVM pVM = pVCpu->CTX_SUFF(pVM);
3209 uint64_t u64HostEfer = pVM->hm.s.vmx.u64HostEfer;
3210 uint64_t u64GuestEfer = pMixedCtx->msrEFER;
3211
3212 /*
3213 * For 64-bit guests, if EFER.SCE bit differs, we need to swap to ensure that the
3214 * guest's SYSCALL behaviour isn't screwed. See @bugref{7386}.
3215 */
3216 if ( CPUMIsGuestInLongMode(pVCpu)
3217 && (u64GuestEfer & MSR_K6_EFER_SCE) != (u64HostEfer & MSR_K6_EFER_SCE))
3218 {
3219 return true;
3220 }
3221
3222 /*
3223 * If the guest uses PAE and EFER.NXE bit differs, we need to swap EFER as it
3224 * affects guest paging. 64-bit paging implies CR4.PAE as well.
3225 * See Intel spec. 4.5 "IA-32e Paging" and Intel spec. 4.1.1 "Three Paging Modes".
3226 */
3227 if ( (pMixedCtx->cr4 & X86_CR4_PAE)
3228 && (pMixedCtx->cr0 & X86_CR0_PG)
3229 && (u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE))
3230 {
3231 /* Assert that host is PAE capable. */
3232 Assert(pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_NX);
3233 return true;
3234 }
3235
3236 /** @todo Check the latest Intel spec. for any other bits,
3237 * like SMEP/SMAP? */
3238 return false;
3239}
3240
3241
3242/**
3243 * Sets up VM-entry controls in the VMCS. These controls can affect things done
3244 * on VM-exit; e.g. "load debug controls", see Intel spec. 24.8.1 "VM-entry
3245 * controls".
3246 *
3247 * @returns VBox status code.
3248 * @param pVCpu The cross context virtual CPU structure.
3249 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3250 * out-of-sync. Make sure to update the required fields
3251 * before using them.
3252 *
3253 * @remarks Requires EFER.
3254 * @remarks No-long-jump zone!!!
3255 */
3256DECLINLINE(int) hmR0VmxLoadGuestEntryCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3257{
3258 int rc = VINF_SUCCESS;
3259 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS))
3260 {
3261 PVM pVM = pVCpu->CTX_SUFF(pVM);
3262 uint32_t val = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0; /* Bits set here must be set in the VMCS. */
3263 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3264
3265 /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
3266 val |= VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG;
3267
3268 /* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
3269 if (CPUMIsGuestInLongModeEx(pMixedCtx))
3270 {
3271 val |= VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST;
3272 Log4(("Load[%RU32]: VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST\n", pVCpu->idCpu));
3273 }
3274 else
3275 Assert(!(val & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST));
3276
3277 /* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it. */
3278 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3279 && hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
3280 {
3281 val |= VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR;
3282 Log4(("Load[%RU32]: VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR\n", pVCpu->idCpu));
3283 }
3284
3285 /*
3286 * The following should -not- be set (since we're not in SMM mode):
3287 * - VMX_VMCS_CTRL_ENTRY_ENTRY_SMM
3288 * - VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON
3289 */
3290
3291 /** @todo VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR,
3292 * VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR. */
3293
3294 if ((val & zap) != val)
3295 {
3296 LogRel(("hmR0VmxLoadGuestEntryCtls: Invalid VM-entry controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
3297 pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0, val, zap));
3298 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
3299 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3300 }
3301
3302 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, val);
3303 AssertRCReturn(rc, rc);
3304
3305 pVCpu->hm.s.vmx.u32EntryCtls = val;
3306 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS);
3307 }
3308 return rc;
3309}
3310
3311
3312/**
3313 * Sets up the VM-exit controls in the VMCS.
3314 *
3315 * @returns VBox status code.
3316 * @param pVCpu The cross context virtual CPU structure.
3317 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3318 * out-of-sync. Make sure to update the required fields
3319 * before using them.
3320 *
3321 * @remarks Requires EFER.
3322 */
3323DECLINLINE(int) hmR0VmxLoadGuestExitCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3324{
3325 NOREF(pMixedCtx);
3326
3327 int rc = VINF_SUCCESS;
3328 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_EXIT_CTLS))
3329 {
3330 PVM pVM = pVCpu->CTX_SUFF(pVM);
3331 uint32_t val = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0; /* Bits set here must be set in the VMCS. */
3332 uint32_t zap = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3333
3334 /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
3335 val |= VMX_VMCS_CTRL_EXIT_SAVE_DEBUG;
3336
3337 /*
3338 * Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary.
3339 * On VM-exit, VT-x sets both the host EFER.LMA and EFER.LME bit to this value. See assertion in hmR0VmxSaveHostMsrs().
3340 */
3341#if HC_ARCH_BITS == 64
3342 val |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
3343 Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n", pVCpu->idCpu));
3344#else
3345 Assert( pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64
3346 || pVCpu->hm.s.vmx.pfnStartVM == VMXR0StartVM32);
3347 /* Set the host address-space size based on the switcher, not guest state. See @bugref{8432}. */
3348 if (pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64)
3349 {
3350 /* The switcher returns to long mode, EFER is managed by the switcher. */
3351 val |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
3352 Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n", pVCpu->idCpu));
3353 }
3354 else
3355 Assert(!(val & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE));
3356#endif
3357
3358 /* If the newer VMCS fields for managing EFER exists, use it. */
3359 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3360 && hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
3361 {
3362 val |= VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR
3363 | VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR;
3364 Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR\n", pVCpu->idCpu));
3365 }
3366
3367 /* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
3368 Assert(!(val & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT));
3369
3370 /** @todo VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR,
3371 * VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR,
3372 * VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR. */
3373
3374 if ( pVM->hm.s.vmx.fUsePreemptTimer
3375 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER))
3376 val |= VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER;
3377
3378 if ((val & zap) != val)
3379 {
3380 LogRel(("hmR0VmxSetupProcCtls: Invalid VM-exit controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
3381 pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0, val, zap));
3382 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
3383 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3384 }
3385
3386 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, val);
3387 AssertRCReturn(rc, rc);
3388
3389 pVCpu->hm.s.vmx.u32ExitCtls = val;
3390 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_EXIT_CTLS);
3391 }
3392 return rc;
3393}
3394
3395
3396/**
3397 * Sets the TPR threshold in the VMCS.
3398 *
3399 * @returns VBox status code.
3400 * @param pVCpu The cross context virtual CPU structure.
3401 * @param u32TprThreshold The TPR threshold (task-priority class only).
3402 */
3403DECLINLINE(int) hmR0VmxApicSetTprThreshold(PVMCPU pVCpu, uint32_t u32TprThreshold)
3404{
3405 Assert(!(u32TprThreshold & 0xfffffff0)); /* Bits 31:4 MBZ. */
3406 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
3407 return VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
3408}
3409
3410
3411/**
3412 * Loads the guest APIC and related state.
3413 *
3414 * @returns VBox status code.
3415 * @param pVCpu The cross context virtual CPU structure.
3416 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3417 * out-of-sync. Make sure to update the required fields
3418 * before using them.
3419 *
3420 * @remarks No-long-jump zone!!!
3421 */
3422DECLINLINE(int) hmR0VmxLoadGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3423{
3424 NOREF(pMixedCtx);
3425
3426 int rc = VINF_SUCCESS;
3427 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE))
3428 {
3429 if ( PDMHasApic(pVCpu->CTX_SUFF(pVM))
3430 && APICIsEnabled(pVCpu))
3431 {
3432 /*
3433 * Setup TPR shadowing.
3434 */
3435 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
3436 {
3437 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
3438
3439 bool fPendingIntr = false;
3440 uint8_t u8Tpr = 0;
3441 uint8_t u8PendingIntr = 0;
3442 rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
3443 AssertRCReturn(rc, rc);
3444
3445 /*
3446 * If there are interrupts pending but masked by the TPR, instruct VT-x to cause a TPR-below-threshold VM-exit
3447 * when the guest lowers its TPR below the priority of the pending interrupt so we can deliver the interrupt.
3448 * If there are no interrupts pending, set threshold to 0 to not cause any TPR-below-threshold VM-exits.
3449 */
3450 pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR] = u8Tpr;
3451 uint32_t u32TprThreshold = 0;
3452 if (fPendingIntr)
3453 {
3454 /* Bits 3:0 of the TPR threshold field correspond to bits 7:4 of the TPR (which is the Task-Priority Class). */
3455 const uint8_t u8PendingPriority = u8PendingIntr >> 4;
3456 const uint8_t u8TprPriority = u8Tpr >> 4;
3457 if (u8PendingPriority <= u8TprPriority)
3458 u32TprThreshold = u8PendingPriority;
3459 }
3460
3461 rc = hmR0VmxApicSetTprThreshold(pVCpu, u32TprThreshold);
3462 AssertRCReturn(rc, rc);
3463 }
3464 }
3465 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
3466 }
3467
3468 return rc;
3469}
3470
3471
3472/**
3473 * Gets the guest's interruptibility-state ("interrupt shadow" as AMD calls it).
3474 *
3475 * @returns Guest's interruptibility-state.
3476 * @param pVCpu The cross context virtual CPU structure.
3477 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3478 * out-of-sync. Make sure to update the required fields
3479 * before using them.
3480 *
3481 * @remarks No-long-jump zone!!!
3482 */
3483DECLINLINE(uint32_t) hmR0VmxGetGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3484{
3485 /*
3486 * Check if we should inhibit interrupt delivery due to instructions like STI and MOV SS.
3487 */
3488 uint32_t uIntrState = 0;
3489 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3490 {
3491 /* If inhibition is active, RIP & RFLAGS should've been accessed (i.e. read previously from the VMCS or from ring-3). */
3492 AssertMsg(HMVMXCPU_GST_IS_SET(pVCpu, HMVMX_UPDATED_GUEST_RIP | HMVMX_UPDATED_GUEST_RFLAGS),
3493 ("%#x\n", HMVMXCPU_GST_VALUE(pVCpu)));
3494 if (pMixedCtx->rip == EMGetInhibitInterruptsPC(pVCpu))
3495 {
3496 if (pMixedCtx->eflags.Bits.u1IF)
3497 uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
3498 else
3499 uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS;
3500 }
3501 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3502 {
3503 /*
3504 * We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3505 * VT-x, the flag's condition to be cleared is met and thus the cleared state is correct.
3506 */
3507 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3508 }
3509 }
3510
3511 /*
3512 * NMIs to the guest are blocked after an NMI is injected until the guest executes an IRET. We only
3513 * bother with virtual-NMI blocking when we have support for virtual NMIs in the CPU, otherwise
3514 * setting this would block host-NMIs and IRET will not clear the blocking.
3515 *
3516 * See Intel spec. 26.6.1 "Interruptibility state". See @bugref{7445}.
3517 */
3518 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
3519 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
3520 {
3521 uIntrState |= VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI;
3522 }
3523
3524 return uIntrState;
3525}
3526
3527
3528/**
3529 * Loads the guest's interruptibility-state into the guest-state area in the
3530 * VMCS.
3531 *
3532 * @returns VBox status code.
3533 * @param pVCpu The cross context virtual CPU structure.
3534 * @param uIntrState The interruptibility-state to set.
3535 */
3536static int hmR0VmxLoadGuestIntrState(PVMCPU pVCpu, uint32_t uIntrState)
3537{
3538 NOREF(pVCpu);
3539 AssertMsg(!(uIntrState & 0xfffffff0), ("%#x\n", uIntrState)); /* Bits 31:4 MBZ. */
3540 Assert((uIntrState & 0x3) != 0x3); /* Block-by-STI and MOV SS cannot be simultaneously set. */
3541 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, uIntrState);
3542 AssertRC(rc);
3543 return rc;
3544}
3545
3546
3547/**
3548 * Loads the exception intercepts required for guest execution in the VMCS.
3549 *
3550 * @returns VBox status code.
3551 * @param pVCpu The cross context virtual CPU structure.
3552 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3553 * out-of-sync. Make sure to update the required fields
3554 * before using them.
3555 */
3556static int hmR0VmxLoadGuestXcptIntercepts(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3557{
3558 NOREF(pMixedCtx);
3559 int rc = VINF_SUCCESS;
3560 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
3561 {
3562 /* The remaining exception intercepts are handled elsewhere, e.g. in hmR0VmxLoadSharedCR0(). */
3563 if (pVCpu->hm.s.fGIMTrapXcptUD)
3564 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_UD);
3565#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3566 else
3567 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_UD);
3568#endif
3569
3570 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_AC));
3571 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
3572
3573 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
3574 AssertRCReturn(rc, rc);
3575
3576 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
3577 Log4(("Load[%RU32]: VMX_VMCS32_CTRL_EXCEPTION_BITMAP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu,
3578 pVCpu->hm.s.vmx.u32XcptBitmap, HMCPU_CF_VALUE(pVCpu)));
3579 }
3580 return rc;
3581}
3582
3583
3584/**
3585 * Loads the guest's RIP into the guest-state area in the VMCS.
3586 *
3587 * @returns VBox status code.
3588 * @param pVCpu The cross context virtual CPU structure.
3589 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3590 * out-of-sync. Make sure to update the required fields
3591 * before using them.
3592 *
3593 * @remarks No-long-jump zone!!!
3594 */
3595static int hmR0VmxLoadGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3596{
3597 int rc = VINF_SUCCESS;
3598 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP))
3599 {
3600 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pMixedCtx->rip);
3601 AssertRCReturn(rc, rc);
3602
3603 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP);
3604 Log4(("Load[%RU32]: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu, pMixedCtx->rip,
3605 HMCPU_CF_VALUE(pVCpu)));
3606 }
3607 return rc;
3608}
3609
3610
3611/**
3612 * Loads the guest's RSP into the guest-state area in the VMCS.
3613 *
3614 * @returns VBox status code.
3615 * @param pVCpu The cross context virtual CPU structure.
3616 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3617 * out-of-sync. Make sure to update the required fields
3618 * before using them.
3619 *
3620 * @remarks No-long-jump zone!!!
3621 */
3622static int hmR0VmxLoadGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3623{
3624 int rc = VINF_SUCCESS;
3625 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP))
3626 {
3627 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pMixedCtx->rsp);
3628 AssertRCReturn(rc, rc);
3629
3630 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RSP);
3631 Log4(("Load[%RU32]: VMX_VMCS_GUEST_RSP=%#RX64\n", pVCpu->idCpu, pMixedCtx->rsp));
3632 }
3633 return rc;
3634}
3635
3636
3637/**
3638 * Loads the guest's RFLAGS into the guest-state area in the VMCS.
3639 *
3640 * @returns VBox status code.
3641 * @param pVCpu The cross context virtual CPU structure.
3642 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3643 * out-of-sync. Make sure to update the required fields
3644 * before using them.
3645 *
3646 * @remarks No-long-jump zone!!!
3647 */
3648static int hmR0VmxLoadGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3649{
3650 int rc = VINF_SUCCESS;
3651 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
3652 {
3653 /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
3654 Let us assert it as such and use 32-bit VMWRITE. */
3655 Assert(!(pMixedCtx->rflags.u64 >> 32));
3656 X86EFLAGS Eflags = pMixedCtx->eflags;
3657 /** @todo r=bird: There shall be no need to OR in X86_EFL_1 here, nor
3658 * shall there be any reason for clearing bits 63:22, 15, 5 and 3.
3659 * These will never be cleared/set, unless some other part of the VMM
3660 * code is buggy - in which case we're better of finding and fixing
3661 * those bugs than hiding them. */
3662 Assert(Eflags.u32 & X86_EFL_RA1_MASK);
3663 Assert(!(Eflags.u32 & ~(X86_EFL_1 | X86_EFL_LIVE_MASK)));
3664 Eflags.u32 &= VMX_EFLAGS_RESERVED_0; /* Bits 22-31, 15, 5 & 3 MBZ. */
3665 Eflags.u32 |= VMX_EFLAGS_RESERVED_1; /* Bit 1 MB1. */
3666
3667 /*
3668 * If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so we can restore them on VM-exit.
3669 * Modify the real-mode guest's eflags so that VT-x can run the real-mode guest code under Virtual 8086 mode.
3670 */
3671 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3672 {
3673 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
3674 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
3675 pVCpu->hm.s.vmx.RealMode.Eflags.u32 = Eflags.u32; /* Save the original eflags of the real-mode guest. */
3676 Eflags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
3677 Eflags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
3678 }
3679
3680 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_RFLAGS, Eflags.u32);
3681 AssertRCReturn(rc, rc);
3682
3683 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RFLAGS);
3684 Log4(("Load[%RU32]: VMX_VMCS_GUEST_RFLAGS=%#RX32\n", pVCpu->idCpu, Eflags.u32));
3685 }
3686 return rc;
3687}
3688
3689
3690/**
3691 * Loads the guest RIP, RSP and RFLAGS into the guest-state area in the VMCS.
3692 *
3693 * @returns VBox status code.
3694 * @param pVCpu The cross context virtual CPU structure.
3695 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3696 * out-of-sync. Make sure to update the required fields
3697 * before using them.
3698 *
3699 * @remarks No-long-jump zone!!!
3700 */
3701DECLINLINE(int) hmR0VmxLoadGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3702{
3703 int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
3704 rc |= hmR0VmxLoadGuestRsp(pVCpu, pMixedCtx);
3705 rc |= hmR0VmxLoadGuestRflags(pVCpu, pMixedCtx);
3706 AssertRCReturn(rc, rc);
3707 return rc;
3708}
3709
3710
3711/**
3712 * Loads the guest CR0 control register into the guest-state area in the VMCS.
3713 * CR0 is partially shared with the host and we have to consider the FPU bits.
3714 *
3715 * @returns VBox status code.
3716 * @param pVCpu The cross context virtual CPU structure.
3717 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3718 * out-of-sync. Make sure to update the required fields
3719 * before using them.
3720 *
3721 * @remarks No-long-jump zone!!!
3722 */
3723static int hmR0VmxLoadSharedCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3724{
3725 /*
3726 * Guest CR0.
3727 * Guest FPU.
3728 */
3729 int rc = VINF_SUCCESS;
3730 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
3731 {
3732 Assert(!(pMixedCtx->cr0 >> 32));
3733 uint32_t u32GuestCR0 = pMixedCtx->cr0;
3734 PVM pVM = pVCpu->CTX_SUFF(pVM);
3735
3736 /* The guest's view (read access) of its CR0 is unblemished. */
3737 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, u32GuestCR0);
3738 AssertRCReturn(rc, rc);
3739 Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR0_READ_SHADOW=%#RX32\n", pVCpu->idCpu, u32GuestCR0));
3740
3741 /* Setup VT-x's view of the guest CR0. */
3742 /* Minimize VM-exits due to CR3 changes when we have NestedPaging. */
3743 if (pVM->hm.s.fNestedPaging)
3744 {
3745 if (CPUMIsGuestPagingEnabledEx(pMixedCtx))
3746 {
3747 /* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
3748 pVCpu->hm.s.vmx.u32ProcCtls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
3749 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
3750 }
3751 else
3752 {
3753 /* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
3754 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
3755 | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3756 }
3757
3758 /* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
3759 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3760 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3761
3762 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
3763 AssertRCReturn(rc, rc);
3764 }
3765 else
3766 u32GuestCR0 |= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
3767
3768 /*
3769 * Guest FPU bits.
3770 * Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be set on the first
3771 * CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
3772 */
3773 u32GuestCR0 |= X86_CR0_NE;
3774 bool fInterceptNM = false;
3775 if (CPUMIsGuestFPUStateActive(pVCpu))
3776 {
3777 fInterceptNM = false; /* Guest FPU active, no need to VM-exit on #NM. */
3778 /* The guest should still get #NM exceptions when it expects it to, so we should not clear TS & MP bits here.
3779 We're only concerned about -us- not intercepting #NMs when the guest-FPU is active. Not the guest itself! */
3780 }
3781 else
3782 {
3783 fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
3784 u32GuestCR0 |= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
3785 | X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
3786 }
3787
3788 /* Catch floating point exceptions if we need to report them to the guest in a different way. */
3789 bool fInterceptMF = false;
3790 if (!(pMixedCtx->cr0 & X86_CR0_NE))
3791 fInterceptMF = true;
3792
3793 /* Finally, intercept all exceptions as we cannot directly inject them in real-mode, see hmR0VmxInjectEventVmcs(). */
3794 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3795 {
3796 Assert(PDMVmmDevHeapIsEnabled(pVM));
3797 Assert(pVM->hm.s.vmx.pRealModeTSS);
3798 pVCpu->hm.s.vmx.u32XcptBitmap |= HMVMX_REAL_MODE_XCPT_MASK;
3799 fInterceptNM = true;
3800 fInterceptMF = true;
3801 }
3802 else
3803 {
3804 /* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */
3805 pVCpu->hm.s.vmx.u32XcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
3806 }
3807 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
3808
3809 if (fInterceptNM)
3810 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_NM);
3811 else
3812 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_NM);
3813
3814 if (fInterceptMF)
3815 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_MF);
3816 else
3817 pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_MF);
3818
3819 /* Additional intercepts for debugging, define these yourself explicitly. */
3820#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3821 pVCpu->hm.s.vmx.u32XcptBitmap |= 0
3822 | RT_BIT(X86_XCPT_BP)
3823 | RT_BIT(X86_XCPT_DE)
3824 | RT_BIT(X86_XCPT_NM)
3825 | RT_BIT(X86_XCPT_TS)
3826 | RT_BIT(X86_XCPT_UD)
3827 | RT_BIT(X86_XCPT_NP)
3828 | RT_BIT(X86_XCPT_SS)
3829 | RT_BIT(X86_XCPT_GP)
3830 | RT_BIT(X86_XCPT_PF)
3831 | RT_BIT(X86_XCPT_MF)
3832 ;
3833#elif defined(HMVMX_ALWAYS_TRAP_PF)
3834 pVCpu->hm.s.vmx.u32XcptBitmap |= RT_BIT(X86_XCPT_PF);
3835#endif
3836
3837 Assert(pVM->hm.s.fNestedPaging || (pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT(X86_XCPT_PF)));
3838
3839 /* Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW). */
3840 uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3841 uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3842 if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */
3843 uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG);
3844 else
3845 Assert((uSetCR0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG));
3846
3847 u32GuestCR0 |= uSetCR0;
3848 u32GuestCR0 &= uZapCR0;
3849 u32GuestCR0 &= ~(X86_CR0_CD | X86_CR0_NW); /* Always enable caching. */
3850
3851 /* Write VT-x's view of the guest CR0 into the VMCS. */
3852 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCR0);
3853 AssertRCReturn(rc, rc);
3854 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR0=%#RX32 (uSetCR0=%#RX32 uZapCR0=%#RX32)\n", pVCpu->idCpu, u32GuestCR0, uSetCR0,
3855 uZapCR0));
3856
3857 /*
3858 * CR0 is shared between host and guest along with a CR0 read shadow. Therefore, certain bits must not be changed
3859 * by the guest because VT-x ignores saving/restoring them (namely CD, ET, NW) and for certain other bits
3860 * we want to be notified immediately of guest CR0 changes (e.g. PG to update our shadow page tables).
3861 */
3862 uint32_t u32CR0Mask = 0;
3863 u32CR0Mask = X86_CR0_PE
3864 | X86_CR0_NE
3865 | X86_CR0_WP
3866 | X86_CR0_PG
3867 | X86_CR0_ET /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
3868 | X86_CR0_CD /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
3869 | X86_CR0_NW; /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.NW */
3870
3871 /** @todo Avoid intercepting CR0.PE with unrestricted guests. Fix PGM
3872 * enmGuestMode to be in-sync with the current mode. See @bugref{6398}
3873 * and @bugref{6944}. */
3874#if 0
3875 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3876 u32CR0Mask &= ~X86_CR0_PE;
3877#endif
3878 if (pVM->hm.s.fNestedPaging)
3879 u32CR0Mask &= ~X86_CR0_WP;
3880
3881 /* If the guest FPU state is active, don't need to VM-exit on writes to FPU related bits in CR0. */
3882 if (fInterceptNM)
3883 {
3884 u32CR0Mask |= X86_CR0_TS
3885 | X86_CR0_MP;
3886 }
3887
3888 /* Write the CR0 mask into the VMCS and update the VCPU's copy of the current CR0 mask. */
3889 pVCpu->hm.s.vmx.u32CR0Mask = u32CR0Mask;
3890 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32CR0Mask);
3891 AssertRCReturn(rc, rc);
3892 Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR0_MASK=%#RX32\n", pVCpu->idCpu, u32CR0Mask));
3893
3894 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
3895 }
3896 return rc;
3897}
3898
3899
3900/**
3901 * Loads the guest control registers (CR3, CR4) into the guest-state area
3902 * in the VMCS.
3903 *
3904 * @returns VBox strict status code.
3905 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
3906 * without unrestricted guest access and the VMMDev is not presently
3907 * mapped (e.g. EFI32).
3908 *
3909 * @param pVCpu The cross context virtual CPU structure.
3910 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
3911 * out-of-sync. Make sure to update the required fields
3912 * before using them.
3913 *
3914 * @remarks No-long-jump zone!!!
3915 */
3916static VBOXSTRICTRC hmR0VmxLoadGuestCR3AndCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3917{
3918 int rc = VINF_SUCCESS;
3919 PVM pVM = pVCpu->CTX_SUFF(pVM);
3920
3921 /*
3922 * Guest CR2.
3923 * It's always loaded in the assembler code. Nothing to do here.
3924 */
3925
3926 /*
3927 * Guest CR3.
3928 */
3929 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
3930 {
3931 RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
3932 if (pVM->hm.s.fNestedPaging)
3933 {
3934 pVCpu->hm.s.vmx.HCPhysEPTP = PGMGetHyperCR3(pVCpu);
3935
3936 /* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
3937 Assert(pVCpu->hm.s.vmx.HCPhysEPTP);
3938 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & UINT64_C(0xfff0000000000000)));
3939 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & 0xfff));
3940
3941 /* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
3942 pVCpu->hm.s.vmx.HCPhysEPTP |= VMX_EPT_MEMTYPE_WB
3943 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
3944
3945 /* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
3946 AssertMsg( ((pVCpu->hm.s.vmx.HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
3947 && ((pVCpu->hm.s.vmx.HCPhysEPTP >> 7) & 0x1f) == 0, /* Bits 7:11 MBZ. */
3948 ("EPTP %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3949 AssertMsg( !((pVCpu->hm.s.vmx.HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */
3950 || (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
3951 ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3952
3953 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.HCPhysEPTP);
3954 AssertRCReturn(rc, rc);
3955 Log4(("Load[%RU32]: VMX_VMCS64_CTRL_EPTP_FULL=%#RX64\n", pVCpu->idCpu, pVCpu->hm.s.vmx.HCPhysEPTP));
3956
3957 if ( pVM->hm.s.vmx.fUnrestrictedGuest
3958 || CPUMIsGuestPagingEnabledEx(pMixedCtx))
3959 {
3960 /* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
3961 if (CPUMIsGuestInPAEModeEx(pMixedCtx))
3962 {
3963 rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
3964 AssertRCReturn(rc, rc);
3965 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);
3966 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);
3967 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);
3968 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);
3969 AssertRCReturn(rc, rc);
3970 }
3971
3972 /* The guest's view of its CR3 is unblemished with Nested Paging when the guest is using paging or we
3973 have Unrestricted Execution to handle the guest when it's not using paging. */
3974 GCPhysGuestCR3 = pMixedCtx->cr3;
3975 }
3976 else
3977 {
3978 /*
3979 * The guest is not using paging, but the CPU (VT-x) has to. While the guest thinks it accesses physical memory
3980 * directly, we use our identity-mapped page table to map guest-linear to guest-physical addresses.
3981 * EPT takes care of translating it to host-physical addresses.
3982 */
3983 RTGCPHYS GCPhys;
3984 Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
3985
3986 /* We obtain it here every time as the guest could have relocated this PCI region. */
3987 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
3988 if (RT_SUCCESS(rc))
3989 { /* likely */ }
3990 else if (rc == VERR_PDM_DEV_HEAP_R3_TO_GCPHYS)
3991 {
3992 Log4(("Load[%RU32]: VERR_PDM_DEV_HEAP_R3_TO_GCPHYS -> VINF_EM_RESCHEDULE_REM\n", pVCpu->idCpu));
3993 return VINF_EM_RESCHEDULE_REM; /* We cannot execute now, switch to REM/IEM till the guest maps in VMMDev. */
3994 }
3995 else
3996 AssertMsgFailedReturn(("%Rrc\n", rc), rc);
3997
3998 GCPhysGuestCR3 = GCPhys;
3999 }
4000
4001 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR3=%#RGp (GstN)\n", pVCpu->idCpu, GCPhysGuestCR3));
4002 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR3, GCPhysGuestCR3);
4003 }
4004 else
4005 {
4006 /* Non-nested paging case, just use the hypervisor's CR3. */
4007 RTHCPHYS HCPhysGuestCR3 = PGMGetHyperCR3(pVCpu);
4008
4009 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR3=%#RHv (HstN)\n", pVCpu->idCpu, HCPhysGuestCR3));
4010 rc = VMXWriteVmcsHstN(VMX_VMCS_GUEST_CR3, HCPhysGuestCR3);
4011 }
4012 AssertRCReturn(rc, rc);
4013
4014 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
4015 }
4016
4017 /*
4018 * Guest CR4.
4019 * ASSUMES this is done everytime we get in from ring-3! (XCR0)
4020 */
4021 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
4022 {
4023 Assert(!(pMixedCtx->cr4 >> 32));
4024 uint32_t u32GuestCR4 = pMixedCtx->cr4;
4025
4026 /* The guest's view of its CR4 is unblemished. */
4027 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32GuestCR4);
4028 AssertRCReturn(rc, rc);
4029 Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR4_READ_SHADOW=%#RX32\n", pVCpu->idCpu, u32GuestCR4));
4030
4031 /* Setup VT-x's view of the guest CR4. */
4032 /*
4033 * If we're emulating real-mode using virtual-8086 mode, we want to redirect software interrupts to the 8086 program
4034 * interrupt handler. Clear the VME bit (the interrupt redirection bitmap is already all 0, see hmR3InitFinalizeR0())
4035 * See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
4036 */
4037 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4038 {
4039 Assert(pVM->hm.s.vmx.pRealModeTSS);
4040 Assert(PDMVmmDevHeapIsEnabled(pVM));
4041 u32GuestCR4 &= ~X86_CR4_VME;
4042 }
4043
4044 if (pVM->hm.s.fNestedPaging)
4045 {
4046 if ( !CPUMIsGuestPagingEnabledEx(pMixedCtx)
4047 && !pVM->hm.s.vmx.fUnrestrictedGuest)
4048 {
4049 /* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
4050 u32GuestCR4 |= X86_CR4_PSE;
4051 /* Our identity mapping is a 32-bit page directory. */
4052 u32GuestCR4 &= ~X86_CR4_PAE;
4053 }
4054 /* else use guest CR4.*/
4055 }
4056 else
4057 {
4058 /*
4059 * The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
4060 * paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
4061 */
4062 switch (pVCpu->hm.s.enmShadowMode)
4063 {
4064 case PGMMODE_REAL: /* Real-mode. */
4065 case PGMMODE_PROTECTED: /* Protected mode without paging. */
4066 case PGMMODE_32_BIT: /* 32-bit paging. */
4067 {
4068 u32GuestCR4 &= ~X86_CR4_PAE;
4069 break;
4070 }
4071
4072 case PGMMODE_PAE: /* PAE paging. */
4073 case PGMMODE_PAE_NX: /* PAE paging with NX. */
4074 {
4075 u32GuestCR4 |= X86_CR4_PAE;
4076 break;
4077 }
4078
4079 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
4080 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
4081#ifdef VBOX_ENABLE_64_BITS_GUESTS
4082 break;
4083#endif
4084 default:
4085 AssertFailed();
4086 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4087 }
4088 }
4089
4090 /* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */
4091 uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4092 uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4093 u32GuestCR4 |= uSetCR4;
4094 u32GuestCR4 &= uZapCR4;
4095
4096 /* Write VT-x's view of the guest CR4 into the VMCS. */
4097 Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR4=%#RX32 (Set=%#RX32 Zap=%#RX32)\n", pVCpu->idCpu, u32GuestCR4, uSetCR4, uZapCR4));
4098 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCR4);
4099 AssertRCReturn(rc, rc);
4100
4101 /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them, that would cause a VM-exit. */
4102 uint32_t u32CR4Mask = X86_CR4_VME
4103 | X86_CR4_PAE
4104 | X86_CR4_PGE
4105 | X86_CR4_PSE
4106 | X86_CR4_VMXE;
4107 if (pVM->cpum.ro.HostFeatures.fXSaveRstor)
4108 u32CR4Mask |= X86_CR4_OSXSAVE;
4109 pVCpu->hm.s.vmx.u32CR4Mask = u32CR4Mask;
4110 rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
4111 AssertRCReturn(rc, rc);
4112
4113 /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
4114 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
4115
4116 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
4117 }
4118 return rc;
4119}
4120
4121
4122/**
4123 * Loads the guest debug registers into the guest-state area in the VMCS.
4124 *
4125 * This also sets up whether \#DB and MOV DRx accesses cause VM-exits.
4126 *
4127 * The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
4128 *
4129 * @returns VBox status code.
4130 * @param pVCpu The cross context virtual CPU structure.
4131 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4132 * out-of-sync. Make sure to update the required fields
4133 * before using them.
4134 *
4135 * @remarks No-long-jump zone!!!
4136 */
4137static int hmR0VmxLoadSharedDebugState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4138{
4139 if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
4140 return VINF_SUCCESS;
4141
4142#ifdef VBOX_STRICT
4143 /* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
4144 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
4145 {
4146 /* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
4147 Assert((pMixedCtx->dr[7] & (X86_DR7_MBZ_MASK | X86_DR7_RAZ_MASK)) == 0); /* Bits 63:32, 15, 14, 12, 11 are reserved. */
4148 Assert((pMixedCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); /* Bit 10 is reserved (RA1). */
4149 }
4150#endif
4151
4152 int rc;
4153 PVM pVM = pVCpu->CTX_SUFF(pVM);
4154 bool fSteppingDB = false;
4155 bool fInterceptMovDRx = false;
4156 if (pVCpu->hm.s.fSingleInstruction)
4157 {
4158 /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
4159 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG)
4160 {
4161 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
4162 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
4163 AssertRCReturn(rc, rc);
4164 Assert(fSteppingDB == false);
4165 }
4166 else
4167 {
4168 pMixedCtx->eflags.u32 |= X86_EFL_TF;
4169 pVCpu->hm.s.fClearTrapFlag = true;
4170 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
4171 fSteppingDB = true;
4172 }
4173 }
4174
4175 if ( fSteppingDB
4176 || (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
4177 {
4178 /*
4179 * Use the combined guest and host DRx values found in the hypervisor
4180 * register set because the debugger has breakpoints active or someone
4181 * is single stepping on the host side without a monitor trap flag.
4182 *
4183 * Note! DBGF expects a clean DR6 state before executing guest code.
4184 */
4185#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4186 if ( CPUMIsGuestInLongModeEx(pMixedCtx)
4187 && !CPUMIsHyperDebugStateActivePending(pVCpu))
4188 {
4189 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4190 Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
4191 Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
4192 }
4193 else
4194#endif
4195 if (!CPUMIsHyperDebugStateActive(pVCpu))
4196 {
4197 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4198 Assert(CPUMIsHyperDebugStateActive(pVCpu));
4199 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
4200 }
4201
4202 /* Update DR7. (The other DRx values are handled by CPUM one way or the other.) */
4203 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)CPUMGetHyperDR7(pVCpu));
4204 AssertRCReturn(rc, rc);
4205
4206 pVCpu->hm.s.fUsingHyperDR7 = true;
4207 fInterceptMovDRx = true;
4208 }
4209 else
4210 {
4211 /*
4212 * If the guest has enabled debug registers, we need to load them prior to
4213 * executing guest code so they'll trigger at the right time.
4214 */
4215 if (pMixedCtx->dr[7] & (X86_DR7_ENABLED_MASK | X86_DR7_GD)) /** @todo Why GD? */
4216 {
4217#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4218 if ( CPUMIsGuestInLongModeEx(pMixedCtx)
4219 && !CPUMIsGuestDebugStateActivePending(pVCpu))
4220 {
4221 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4222 Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
4223 Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
4224 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4225 }
4226 else
4227#endif
4228 if (!CPUMIsGuestDebugStateActive(pVCpu))
4229 {
4230 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4231 Assert(CPUMIsGuestDebugStateActive(pVCpu));
4232 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
4233 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4234 }
4235 Assert(!fInterceptMovDRx);
4236 }
4237 /*
4238 * If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
4239 * must intercept #DB in order to maintain a correct DR6 guest value, and
4240 * because we need to intercept it to prevent nested #DBs from hanging the
4241 * CPU, we end up always having to intercept it. See hmR0VmxInitXcptBitmap.
4242 */
4243#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4244 else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
4245 && !CPUMIsGuestDebugStateActive(pVCpu))
4246#else
4247 else if (!CPUMIsGuestDebugStateActive(pVCpu))
4248#endif
4249 {
4250 fInterceptMovDRx = true;
4251 }
4252
4253 /* Update guest DR7. */
4254 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
4255 AssertRCReturn(rc, rc);
4256
4257 pVCpu->hm.s.fUsingHyperDR7 = false;
4258 }
4259
4260 /*
4261 * Update the processor-based VM-execution controls regarding intercepting MOV DRx instructions.
4262 */
4263 if (fInterceptMovDRx)
4264 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
4265 else
4266 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
4267 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
4268 AssertRCReturn(rc, rc);
4269
4270 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
4271 return VINF_SUCCESS;
4272}
4273
4274
4275#ifdef VBOX_STRICT
4276/**
4277 * Strict function to validate segment registers.
4278 *
4279 * @remarks ASSUMES CR0 is up to date.
4280 */
4281static void hmR0VmxValidateSegmentRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4282{
4283 /* Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */
4284 /* NOTE: The reason we check for attribute value 0 and not just the unusable bit here is because hmR0VmxWriteSegmentReg()
4285 * only updates the VMCS' copy of the value with the unusable bit and doesn't change the guest-context value. */
4286 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
4287 && ( !CPUMIsGuestInRealModeEx(pCtx)
4288 && !CPUMIsGuestInV86ModeEx(pCtx)))
4289 {
4290 /* Protected mode checks */
4291 /* CS */
4292 Assert(pCtx->cs.Attr.n.u1Present);
4293 Assert(!(pCtx->cs.Attr.u & 0xf00));
4294 Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
4295 Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
4296 || !(pCtx->cs.Attr.n.u1Granularity));
4297 Assert( !(pCtx->cs.u32Limit & 0xfff00000)
4298 || (pCtx->cs.Attr.n.u1Granularity));
4299 /* CS cannot be loaded with NULL in protected mode. */
4300 Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS? */
4301 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
4302 Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
4303 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
4304 Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
4305 else
4306 AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
4307 /* SS */
4308 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4309 Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
4310 if ( !(pCtx->cr0 & X86_CR0_PE)
4311 || pCtx->cs.Attr.n.u4Type == 3)
4312 {
4313 Assert(!pCtx->ss.Attr.n.u2Dpl);
4314 }
4315 if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
4316 {
4317 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4318 Assert(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7);
4319 Assert(pCtx->ss.Attr.n.u1Present);
4320 Assert(!(pCtx->ss.Attr.u & 0xf00));
4321 Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
4322 Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
4323 || !(pCtx->ss.Attr.n.u1Granularity));
4324 Assert( !(pCtx->ss.u32Limit & 0xfff00000)
4325 || (pCtx->ss.Attr.n.u1Granularity));
4326 }
4327 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
4328 if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
4329 {
4330 Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4331 Assert(pCtx->ds.Attr.n.u1Present);
4332 Assert(pCtx->ds.Attr.n.u4Type > 11 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
4333 Assert(!(pCtx->ds.Attr.u & 0xf00));
4334 Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
4335 Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
4336 || !(pCtx->ds.Attr.n.u1Granularity));
4337 Assert( !(pCtx->ds.u32Limit & 0xfff00000)
4338 || (pCtx->ds.Attr.n.u1Granularity));
4339 Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4340 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
4341 }
4342 if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
4343 {
4344 Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4345 Assert(pCtx->es.Attr.n.u1Present);
4346 Assert(pCtx->es.Attr.n.u4Type > 11 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
4347 Assert(!(pCtx->es.Attr.u & 0xf00));
4348 Assert(!(pCtx->es.Attr.u & 0xfffe0000));
4349 Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
4350 || !(pCtx->es.Attr.n.u1Granularity));
4351 Assert( !(pCtx->es.u32Limit & 0xfff00000)
4352 || (pCtx->es.Attr.n.u1Granularity));
4353 Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4354 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
4355 }
4356 if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
4357 {
4358 Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4359 Assert(pCtx->fs.Attr.n.u1Present);
4360 Assert(pCtx->fs.Attr.n.u4Type > 11 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
4361 Assert(!(pCtx->fs.Attr.u & 0xf00));
4362 Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
4363 Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
4364 || !(pCtx->fs.Attr.n.u1Granularity));
4365 Assert( !(pCtx->fs.u32Limit & 0xfff00000)
4366 || (pCtx->fs.Attr.n.u1Granularity));
4367 Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4368 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4369 }
4370 if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
4371 {
4372 Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4373 Assert(pCtx->gs.Attr.n.u1Present);
4374 Assert(pCtx->gs.Attr.n.u4Type > 11 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
4375 Assert(!(pCtx->gs.Attr.u & 0xf00));
4376 Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
4377 Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
4378 || !(pCtx->gs.Attr.n.u1Granularity));
4379 Assert( !(pCtx->gs.u32Limit & 0xfff00000)
4380 || (pCtx->gs.Attr.n.u1Granularity));
4381 Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4382 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4383 }
4384 /* 64-bit capable CPUs. */
4385# if HC_ARCH_BITS == 64
4386 Assert(!(pCtx->cs.u64Base >> 32));
4387 Assert(!pCtx->ss.Attr.u || !(pCtx->ss.u64Base >> 32));
4388 Assert(!pCtx->ds.Attr.u || !(pCtx->ds.u64Base >> 32));
4389 Assert(!pCtx->es.Attr.u || !(pCtx->es.u64Base >> 32));
4390# endif
4391 }
4392 else if ( CPUMIsGuestInV86ModeEx(pCtx)
4393 || ( CPUMIsGuestInRealModeEx(pCtx)
4394 && !pVM->hm.s.vmx.fUnrestrictedGuest))
4395 {
4396 /* Real and v86 mode checks. */
4397 /* hmR0VmxWriteSegmentReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
4398 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
4399 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4400 {
4401 u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3; u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
4402 }
4403 else
4404 {
4405 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
4406 u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
4407 }
4408
4409 /* CS */
4410 AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
4411 Assert(pCtx->cs.u32Limit == 0xffff);
4412 Assert(u32CSAttr == 0xf3);
4413 /* SS */
4414 Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
4415 Assert(pCtx->ss.u32Limit == 0xffff);
4416 Assert(u32SSAttr == 0xf3);
4417 /* DS */
4418 Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
4419 Assert(pCtx->ds.u32Limit == 0xffff);
4420 Assert(u32DSAttr == 0xf3);
4421 /* ES */
4422 Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
4423 Assert(pCtx->es.u32Limit == 0xffff);
4424 Assert(u32ESAttr == 0xf3);
4425 /* FS */
4426 Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
4427 Assert(pCtx->fs.u32Limit == 0xffff);
4428 Assert(u32FSAttr == 0xf3);
4429 /* GS */
4430 Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
4431 Assert(pCtx->gs.u32Limit == 0xffff);
4432 Assert(u32GSAttr == 0xf3);
4433 /* 64-bit capable CPUs. */
4434# if HC_ARCH_BITS == 64
4435 Assert(!(pCtx->cs.u64Base >> 32));
4436 Assert(!u32SSAttr || !(pCtx->ss.u64Base >> 32));
4437 Assert(!u32DSAttr || !(pCtx->ds.u64Base >> 32));
4438 Assert(!u32ESAttr || !(pCtx->es.u64Base >> 32));
4439# endif
4440 }
4441}
4442#endif /* VBOX_STRICT */
4443
4444
4445/**
4446 * Writes a guest segment register into the guest-state area in the VMCS.
4447 *
4448 * @returns VBox status code.
4449 * @param pVCpu The cross context virtual CPU structure.
4450 * @param idxSel Index of the selector in the VMCS.
4451 * @param idxLimit Index of the segment limit in the VMCS.
4452 * @param idxBase Index of the segment base in the VMCS.
4453 * @param idxAccess Index of the access rights of the segment in the VMCS.
4454 * @param pSelReg Pointer to the segment selector.
4455 *
4456 * @remarks No-long-jump zone!!!
4457 */
4458static int hmR0VmxWriteSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase,
4459 uint32_t idxAccess, PCPUMSELREG pSelReg)
4460{
4461 int rc = VMXWriteVmcs32(idxSel, pSelReg->Sel); /* 16-bit guest selector field. */
4462 rc |= VMXWriteVmcs32(idxLimit, pSelReg->u32Limit); /* 32-bit guest segment limit field. */
4463 rc |= VMXWriteVmcsGstN(idxBase, pSelReg->u64Base); /* Natural width guest segment base field.*/
4464 AssertRCReturn(rc, rc);
4465
4466 uint32_t u32Access = pSelReg->Attr.u;
4467 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4468 {
4469 /* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
4470 u32Access = 0xf3;
4471 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
4472 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
4473 }
4474 else
4475 {
4476 /*
4477 * The way to differentiate between whether this is really a null selector or was just a selector loaded with 0 in
4478 * real-mode is using the segment attributes. A selector loaded in real-mode with the value 0 is valid and usable in
4479 * protected-mode and we should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures NULL selectors
4480 * loaded in protected-mode have their attribute as 0.
4481 */
4482 if (!u32Access)
4483 u32Access = X86DESCATTR_UNUSABLE;
4484 }
4485
4486 /* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
4487 AssertMsg((u32Access & X86DESCATTR_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
4488 ("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
4489
4490 rc = VMXWriteVmcs32(idxAccess, u32Access); /* 32-bit guest segment access-rights field. */
4491 AssertRCReturn(rc, rc);
4492 return rc;
4493}
4494
4495
4496/**
4497 * Loads the guest segment registers, GDTR, IDTR, LDTR, (TR, FS and GS bases)
4498 * into the guest-state area in the VMCS.
4499 *
4500 * @returns VBox status code.
4501 * @param pVCpu The cross context virtual CPU structure.
4502 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4503 * out-of-sync. Make sure to update the required fields
4504 * before using them.
4505 *
4506 * @remarks ASSUMES pMixedCtx->cr0 is up to date (strict builds validation).
4507 * @remarks No-long-jump zone!!!
4508 */
4509static int hmR0VmxLoadGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4510{
4511 int rc = VERR_INTERNAL_ERROR_5;
4512 PVM pVM = pVCpu->CTX_SUFF(pVM);
4513
4514 /*
4515 * Guest Segment registers: CS, SS, DS, ES, FS, GS.
4516 */
4517 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
4518 {
4519 /* Save the segment attributes for real-on-v86 mode hack, so we can restore them on VM-exit. */
4520 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4521 {
4522 pVCpu->hm.s.vmx.RealMode.AttrCS.u = pMixedCtx->cs.Attr.u;
4523 pVCpu->hm.s.vmx.RealMode.AttrSS.u = pMixedCtx->ss.Attr.u;
4524 pVCpu->hm.s.vmx.RealMode.AttrDS.u = pMixedCtx->ds.Attr.u;
4525 pVCpu->hm.s.vmx.RealMode.AttrES.u = pMixedCtx->es.Attr.u;
4526 pVCpu->hm.s.vmx.RealMode.AttrFS.u = pMixedCtx->fs.Attr.u;
4527 pVCpu->hm.s.vmx.RealMode.AttrGS.u = pMixedCtx->gs.Attr.u;
4528 }
4529
4530#ifdef VBOX_WITH_REM
4531 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
4532 {
4533 Assert(pVM->hm.s.vmx.pRealModeTSS);
4534 AssertCompile(PGMMODE_REAL < PGMMODE_PROTECTED);
4535 if ( pVCpu->hm.s.vmx.fWasInRealMode
4536 && PGMGetGuestMode(pVCpu) >= PGMMODE_PROTECTED)
4537 {
4538 /* Signal that the recompiler must flush its code-cache as the guest -may- rewrite code it will later execute
4539 in real-mode (e.g. OpenBSD 4.0) */
4540 REMFlushTBs(pVM);
4541 Log4(("Load[%RU32]: Switch to protected mode detected!\n", pVCpu->idCpu));
4542 pVCpu->hm.s.vmx.fWasInRealMode = false;
4543 }
4544 }
4545#endif
4546 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_CS_SEL, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
4547 VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS, &pMixedCtx->cs);
4548 AssertRCReturn(rc, rc);
4549 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_SS_SEL, VMX_VMCS32_GUEST_SS_LIMIT, VMX_VMCS_GUEST_SS_BASE,
4550 VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS, &pMixedCtx->ss);
4551 AssertRCReturn(rc, rc);
4552 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_DS_SEL, VMX_VMCS32_GUEST_DS_LIMIT, VMX_VMCS_GUEST_DS_BASE,
4553 VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS, &pMixedCtx->ds);
4554 AssertRCReturn(rc, rc);
4555 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_ES_SEL, VMX_VMCS32_GUEST_ES_LIMIT, VMX_VMCS_GUEST_ES_BASE,
4556 VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, &pMixedCtx->es);
4557 AssertRCReturn(rc, rc);
4558 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FS_SEL, VMX_VMCS32_GUEST_FS_LIMIT, VMX_VMCS_GUEST_FS_BASE,
4559 VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS, &pMixedCtx->fs);
4560 AssertRCReturn(rc, rc);
4561 rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_GS_SEL, VMX_VMCS32_GUEST_GS_LIMIT, VMX_VMCS_GUEST_GS_BASE,
4562 VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS, &pMixedCtx->gs);
4563 AssertRCReturn(rc, rc);
4564
4565#ifdef VBOX_STRICT
4566 /* Validate. */
4567 hmR0VmxValidateSegmentRegs(pVM, pVCpu, pMixedCtx);
4568#endif
4569
4570 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
4571 Log4(("Load[%RU32]: CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pVCpu->idCpu, pMixedCtx->cs.Sel,
4572 pMixedCtx->cs.u64Base, pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
4573 }
4574
4575 /*
4576 * Guest TR.
4577 */
4578 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
4579 {
4580 /*
4581 * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is achieved
4582 * using the interrupt redirection bitmap (all bits cleared to let the guest handle INT-n's) in the TSS.
4583 * See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
4584 */
4585 uint16_t u16Sel = 0;
4586 uint32_t u32Limit = 0;
4587 uint64_t u64Base = 0;
4588 uint32_t u32AccessRights = 0;
4589
4590 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4591 {
4592 u16Sel = pMixedCtx->tr.Sel;
4593 u32Limit = pMixedCtx->tr.u32Limit;
4594 u64Base = pMixedCtx->tr.u64Base;
4595 u32AccessRights = pMixedCtx->tr.Attr.u;
4596 }
4597 else
4598 {
4599 Assert(pVM->hm.s.vmx.pRealModeTSS);
4600 Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMR3CanExecuteGuest() -XXX- what about inner loop changes? */
4601
4602 /* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
4603 RTGCPHYS GCPhys;
4604 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
4605 AssertRCReturn(rc, rc);
4606
4607 X86DESCATTR DescAttr;
4608 DescAttr.u = 0;
4609 DescAttr.n.u1Present = 1;
4610 DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
4611
4612 u16Sel = 0;
4613 u32Limit = HM_VTX_TSS_SIZE;
4614 u64Base = GCPhys; /* in real-mode phys = virt. */
4615 u32AccessRights = DescAttr.u;
4616 }
4617
4618 /* Validate. */
4619 Assert(!(u16Sel & RT_BIT(2)));
4620 AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
4621 || (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
4622 AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
4623 Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
4624 Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
4625 Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
4626 Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
4627 Assert( (u32Limit & 0xfff) == 0xfff
4628 || !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
4629 Assert( !(pMixedCtx->tr.u32Limit & 0xfff00000)
4630 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
4631
4632 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_TR_SEL, u16Sel);
4633 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit);
4634 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE, u64Base);
4635 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);
4636 AssertRCReturn(rc, rc);
4637
4638 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
4639 Log4(("Load[%RU32]: VMX_VMCS_GUEST_TR_BASE=%#RX64\n", pVCpu->idCpu, u64Base));
4640 }
4641
4642 /*
4643 * Guest GDTR.
4644 */
4645 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
4646 {
4647 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt);
4648 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pMixedCtx->gdtr.pGdt);
4649 AssertRCReturn(rc, rc);
4650
4651 /* Validate. */
4652 Assert(!(pMixedCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4653
4654 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
4655 Log4(("Load[%RU32]: VMX_VMCS_GUEST_GDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->gdtr.pGdt));
4656 }
4657
4658 /*
4659 * Guest LDTR.
4660 */
4661 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
4662 {
4663 /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
4664 uint32_t u32Access = 0;
4665 if (!pMixedCtx->ldtr.Attr.u)
4666 u32Access = X86DESCATTR_UNUSABLE;
4667 else
4668 u32Access = pMixedCtx->ldtr.Attr.u;
4669
4670 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_LDTR_SEL, pMixedCtx->ldtr.Sel);
4671 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pMixedCtx->ldtr.u32Limit);
4672 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE, pMixedCtx->ldtr.u64Base);
4673 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);
4674 AssertRCReturn(rc, rc);
4675
4676 /* Validate. */
4677 if (!(u32Access & X86DESCATTR_UNUSABLE))
4678 {
4679 Assert(!(pMixedCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
4680 Assert(pMixedCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
4681 Assert(!pMixedCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
4682 Assert(pMixedCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
4683 Assert(!pMixedCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
4684 Assert(!(pMixedCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
4685 Assert( (pMixedCtx->ldtr.u32Limit & 0xfff) == 0xfff
4686 || !pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
4687 Assert( !(pMixedCtx->ldtr.u32Limit & 0xfff00000)
4688 || pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
4689 }
4690
4691 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
4692 Log4(("Load[%RU32]: VMX_VMCS_GUEST_LDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->ldtr.u64Base));
4693 }
4694
4695 /*
4696 * Guest IDTR.
4697 */
4698 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
4699 {
4700 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt);
4701 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, pMixedCtx->idtr.pIdt);
4702 AssertRCReturn(rc, rc);
4703
4704 /* Validate. */
4705 Assert(!(pMixedCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4706
4707 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
4708 Log4(("Load[%RU32]: VMX_VMCS_GUEST_IDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->idtr.pIdt));
4709 }
4710
4711 return VINF_SUCCESS;
4712}
4713
4714
4715/**
4716 * Loads certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
4717 * areas.
4718 *
4719 * These MSRs will automatically be loaded to the host CPU on every successful
4720 * VM-entry and stored from the host CPU on every successful VM-exit. This also
4721 * creates/updates MSR slots for the host MSRs. The actual host MSR values are
4722 * -not- updated here for performance reasons. See hmR0VmxSaveHostMsrs().
4723 *
4724 * Also loads the sysenter MSRs into the guest-state area in the VMCS.
4725 *
4726 * @returns VBox status code.
4727 * @param pVCpu The cross context virtual CPU structure.
4728 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4729 * out-of-sync. Make sure to update the required fields
4730 * before using them.
4731 *
4732 * @remarks No-long-jump zone!!!
4733 */
4734static int hmR0VmxLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4735{
4736 AssertPtr(pVCpu);
4737 AssertPtr(pVCpu->hm.s.vmx.pvGuestMsr);
4738
4739 /*
4740 * MSRs that we use the auto-load/store MSR area in the VMCS.
4741 */
4742 PVM pVM = pVCpu->CTX_SUFF(pVM);
4743 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS))
4744 {
4745 /* For 64-bit hosts, we load/restore them lazily, see hmR0VmxLazyLoadGuestMsrs(). */
4746#if HC_ARCH_BITS == 32
4747 if (pVM->hm.s.fAllow64BitGuests)
4748 {
4749 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_LSTAR, pMixedCtx->msrLSTAR, false, NULL);
4750 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_STAR, pMixedCtx->msrSTAR, false, NULL);
4751 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_SF_MASK, pMixedCtx->msrSFMASK, false, NULL);
4752 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_KERNEL_GS_BASE, pMixedCtx->msrKERNELGSBASE, false, NULL);
4753 AssertRCReturn(rc, rc);
4754# ifdef LOG_ENABLED
4755 PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
4756 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cMsrs; i++, pMsr++)
4757 {
4758 Log4(("Load[%RU32]: MSR[%RU32]: u32Msr=%#RX32 u64Value=%#RX64\n", pVCpu->idCpu, i, pMsr->u32Msr,
4759 pMsr->u64Value));
4760 }
4761# endif
4762 }
4763#endif
4764 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
4765 }
4766
4767 /*
4768 * Guest Sysenter MSRs.
4769 * These flags are only set when MSR-bitmaps are not supported by the CPU and we cause
4770 * VM-exits on WRMSRs for these MSRs.
4771 */
4772 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR))
4773 {
4774 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pMixedCtx->SysEnter.cs); AssertRCReturn(rc, rc);
4775 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
4776 }
4777
4778 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR))
4779 {
4780 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip); AssertRCReturn(rc, rc);
4781 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
4782 }
4783
4784 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR))
4785 {
4786 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp); AssertRCReturn(rc, rc);
4787 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
4788 }
4789
4790 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
4791 {
4792 if (hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
4793 {
4794 /*
4795 * If the CPU supports VMCS controls for swapping EFER, use it. Otherwise, we have no option
4796 * but to use the auto-load store MSR area in the VMCS for swapping EFER. See @bugref{7368}.
4797 */
4798 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
4799 {
4800 int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, pMixedCtx->msrEFER);
4801 AssertRCReturn(rc,rc);
4802 Log4(("Load[%RU32]: VMX_VMCS64_GUEST_EFER_FULL=%#RX64\n", pVCpu->idCpu, pMixedCtx->msrEFER));
4803 }
4804 else
4805 {
4806 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_EFER, pMixedCtx->msrEFER, false /* fUpdateHostMsr */,
4807 NULL /* pfAddedAndUpdated */);
4808 AssertRCReturn(rc, rc);
4809
4810 /* We need to intercept reads too, see @bugref{7386#c16}. */
4811 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
4812 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
4813 Log4(("Load[%RU32]: MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", pVCpu->idCpu, MSR_K6_EFER,
4814 pMixedCtx->msrEFER, pVCpu->hm.s.vmx.cMsrs));
4815 }
4816 }
4817 else if (!pVM->hm.s.vmx.fSupportsVmcsEfer)
4818 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K6_EFER);
4819 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4820 }
4821
4822 return VINF_SUCCESS;
4823}
4824
4825
4826/**
4827 * Loads the guest activity state into the guest-state area in the VMCS.
4828 *
4829 * @returns VBox status code.
4830 * @param pVCpu The cross context virtual CPU structure.
4831 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4832 * out-of-sync. Make sure to update the required fields
4833 * before using them.
4834 *
4835 * @remarks No-long-jump zone!!!
4836 */
4837static int hmR0VmxLoadGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4838{
4839 NOREF(pMixedCtx);
4840 /** @todo See if we can make use of other states, e.g.
4841 * VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN or HLT. */
4842 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE))
4843 {
4844 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
4845 AssertRCReturn(rc, rc);
4846
4847 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE);
4848 }
4849 return VINF_SUCCESS;
4850}
4851
4852
4853#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
4854/**
4855 * Check if guest state allows safe use of 32-bit switcher again.
4856 *
4857 * Segment bases and protected mode structures must be 32-bit addressable
4858 * because the 32-bit switcher will ignore high dword when writing these VMCS
4859 * fields. See @bugref{8432} for details.
4860 *
4861 * @returns true if safe, false if must continue to use the 64-bit switcher.
4862 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4863 * out-of-sync. Make sure to update the required fields
4864 * before using them.
4865 *
4866 * @remarks No-long-jump zone!!!
4867 */
4868static bool hmR0VmxIs32BitSwitcherSafe(PCPUMCTX pMixedCtx)
4869{
4870 if (pMixedCtx->gdtr.pGdt & UINT64_C(0xffffffff00000000))
4871 return false;
4872 if (pMixedCtx->idtr.pIdt & UINT64_C(0xffffffff00000000))
4873 return false;
4874 if (pMixedCtx->ldtr.u64Base & UINT64_C(0xffffffff00000000))
4875 return false;
4876 if (pMixedCtx->tr.u64Base & UINT64_C(0xffffffff00000000))
4877 return false;
4878 if (pMixedCtx->es.u64Base & UINT64_C(0xffffffff00000000))
4879 return false;
4880 if (pMixedCtx->cs.u64Base & UINT64_C(0xffffffff00000000))
4881 return false;
4882 if (pMixedCtx->ss.u64Base & UINT64_C(0xffffffff00000000))
4883 return false;
4884 if (pMixedCtx->ds.u64Base & UINT64_C(0xffffffff00000000))
4885 return false;
4886 if (pMixedCtx->fs.u64Base & UINT64_C(0xffffffff00000000))
4887 return false;
4888 if (pMixedCtx->gs.u64Base & UINT64_C(0xffffffff00000000))
4889 return false;
4890 /* All good, bases are 32-bit. */
4891 return true;
4892}
4893#endif
4894
4895
4896/**
4897 * Sets up the appropriate function to run guest code.
4898 *
4899 * @returns VBox status code.
4900 * @param pVCpu The cross context virtual CPU structure.
4901 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
4902 * out-of-sync. Make sure to update the required fields
4903 * before using them.
4904 *
4905 * @remarks No-long-jump zone!!!
4906 */
4907static int hmR0VmxSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4908{
4909 if (CPUMIsGuestInLongModeEx(pMixedCtx))
4910 {
4911#ifndef VBOX_ENABLE_64_BITS_GUESTS
4912 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4913#endif
4914 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
4915#if HC_ARCH_BITS == 32
4916 /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
4917 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
4918 {
4919 if (pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4920 {
4921 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4922 AssertMsg(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_VMX_EXIT_CTLS
4923 | HM_CHANGED_VMX_ENTRY_CTLS
4924 | HM_CHANGED_GUEST_EFER_MSR), ("flags=%#x\n", HMCPU_CF_VALUE(pVCpu)));
4925 }
4926 pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
4927
4928 /* Mark that we've switched to 64-bit handler, we can't safely switch back to 32-bit for
4929 the rest of the VM run (until VM reset). See @bugref{8432#c7}. */
4930 pVCpu->hm.s.vmx.fSwitchedTo64on32 = true;
4931 Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 64-bit switcher\n", pVCpu->idCpu));
4932 }
4933#else
4934 /* 64-bit host. */
4935 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM64;
4936#endif
4937 }
4938 else
4939 {
4940 /* Guest is not in long mode, use the 32-bit handler. */
4941#if HC_ARCH_BITS == 32
4942 if ( pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32
4943 && !pVCpu->hm.s.vmx.fSwitchedTo64on32 /* If set, guest mode change does not imply switcher change. */
4944 && pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4945 {
4946 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4947 AssertMsg(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_VMX_EXIT_CTLS
4948 | HM_CHANGED_VMX_ENTRY_CTLS
4949 | HM_CHANGED_GUEST_EFER_MSR), ("flags=%#x\n", HMCPU_CF_VALUE(pVCpu)));
4950 }
4951# ifdef VBOX_ENABLE_64_BITS_GUESTS
4952 /*
4953 * Keep using the 64-bit switcher even though we're in 32-bit because of bad Intel design, see @bugref{8432#c7}.
4954 * If real-on-v86 mode is active, clear the 64-bit switcher flag because now we know the guest is in a sane
4955 * state where it's safe to use the 32-bit switcher. Otherwise check the guest state if it's safe to use
4956 * the much faster 32-bit switcher again.
4957 */
4958 if (!pVCpu->hm.s.vmx.fSwitchedTo64on32)
4959 {
4960 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32)
4961 Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 32-bit switcher\n", pVCpu->idCpu));
4962 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4963 }
4964 else
4965 {
4966 Assert(pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64);
4967 if ( pVCpu->hm.s.vmx.RealMode.fRealOnV86Active
4968 || hmR0VmxIs32BitSwitcherSafe(pMixedCtx))
4969 {
4970 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
4971 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4972 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR
4973 | HM_CHANGED_VMX_ENTRY_CTLS
4974 | HM_CHANGED_VMX_EXIT_CTLS
4975 | HM_CHANGED_HOST_CONTEXT);
4976 Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 32-bit switcher (safe)\n", pVCpu->idCpu));
4977 }
4978 }
4979# else
4980 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4981# endif
4982#else
4983 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4984#endif
4985 }
4986 Assert(pVCpu->hm.s.vmx.pfnStartVM);
4987 return VINF_SUCCESS;
4988}
4989
4990
4991/**
4992 * Wrapper for running the guest code in VT-x.
4993 *
4994 * @returns VBox status code, no informational status codes.
4995 * @param pVM The cross context VM structure.
4996 * @param pVCpu The cross context virtual CPU structure.
4997 * @param pCtx Pointer to the guest-CPU context.
4998 *
4999 * @remarks No-long-jump zone!!!
5000 */
5001DECLINLINE(int) hmR0VmxRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5002{
5003 /*
5004 * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
5005 * using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
5006 * Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
5007 */
5008 bool const fResumeVM = RT_BOOL(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
5009 /** @todo Add stats for resume vs launch. */
5010#ifdef VBOX_WITH_KERNEL_USING_XMM
5011 int rc = hmR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
5012#else
5013 int rc = pVCpu->hm.s.vmx.pfnStartVM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu);
5014#endif
5015 AssertMsg(rc <= VINF_SUCCESS, ("%Rrc\n", rc));
5016 return rc;
5017}
5018
5019
5020/**
5021 * Reports world-switch error and dumps some useful debug info.
5022 *
5023 * @param pVM The cross context VM structure.
5024 * @param pVCpu The cross context virtual CPU structure.
5025 * @param rcVMRun The return code from VMLAUNCH/VMRESUME.
5026 * @param pCtx Pointer to the guest-CPU context.
5027 * @param pVmxTransient Pointer to the VMX transient structure (only
5028 * exitReason updated).
5029 */
5030static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx, PVMXTRANSIENT pVmxTransient)
5031{
5032 Assert(pVM);
5033 Assert(pVCpu);
5034 Assert(pCtx);
5035 Assert(pVmxTransient);
5036 HMVMX_ASSERT_PREEMPT_SAFE();
5037
5038 Log4(("VM-entry failure: %Rrc\n", rcVMRun));
5039 switch (rcVMRun)
5040 {
5041 case VERR_VMX_INVALID_VMXON_PTR:
5042 AssertFailed();
5043 break;
5044 case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
5045 case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
5046 {
5047 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
5048 rc |= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
5049 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
5050 AssertRC(rc);
5051
5052 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
5053 /* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
5054 Cannot do it here as we may have been long preempted. */
5055
5056#ifdef VBOX_STRICT
5057 Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
5058 pVmxTransient->uExitReason));
5059 Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQualification));
5060 Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
5061 if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
5062 Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
5063 else
5064 Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
5065 Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
5066 Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
5067
5068 /* VMX control bits. */
5069 uint32_t u32Val;
5070 uint64_t u64Val;
5071 RTHCUINTREG uHCReg;
5072 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc);
5073 Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val));
5074 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc);
5075 Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val));
5076 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
5077 {
5078 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);
5079 Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val));
5080 }
5081 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);
5082 Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val));
5083 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);
5084 Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val));
5085 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc);
5086 Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val));
5087 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc);
5088 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val));
5089 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc);
5090 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val));
5091 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc);
5092 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val));
5093 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc);
5094 Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val));
5095 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc);
5096 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val));
5097 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5098 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val));
5099 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5100 Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val));
5101 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc);
5102 Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val));
5103 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc);
5104 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val));
5105 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc);
5106 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val));
5107 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
5108 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
5109 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
5110 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5111 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
5112 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
5113 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
5114 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5115 if (pVM->hm.s.fNestedPaging)
5116 {
5117 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
5118 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
5119 }
5120
5121 /* Guest bits. */
5122 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);
5123 Log4(("Old Guest Rip %#RX64 New %#RX64\n", pCtx->rip, u64Val));
5124 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);
5125 Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pCtx->rsp, u64Val));
5126 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);
5127 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pCtx->eflags.u32, u32Val));
5128 if (pVM->hm.s.vmx.fVpid)
5129 {
5130 rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val); AssertRC(rc);
5131 Log4(("VMX_VMCS16_VPID %u\n", u32Val));
5132 }
5133
5134 /* Host bits. */
5135 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);
5136 Log4(("Host CR0 %#RHr\n", uHCReg));
5137 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);
5138 Log4(("Host CR3 %#RHr\n", uHCReg));
5139 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);
5140 Log4(("Host CR4 %#RHr\n", uHCReg));
5141
5142 RTGDTR HostGdtr;
5143 PCX86DESCHC pDesc;
5144 ASMGetGDTR(&HostGdtr);
5145 rc = VMXReadVmcs32(VMX_VMCS16_HOST_CS_SEL, &u32Val); AssertRC(rc);
5146 Log4(("Host CS %#08x\n", u32Val));
5147 if (u32Val < HostGdtr.cbGdt)
5148 {
5149 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5150 hmR0DumpDescriptor(pDesc, u32Val, "CS: ");
5151 }
5152
5153 rc = VMXReadVmcs32(VMX_VMCS16_HOST_DS_SEL, &u32Val); AssertRC(rc);
5154 Log4(("Host DS %#08x\n", u32Val));
5155 if (u32Val < HostGdtr.cbGdt)
5156 {
5157 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5158 hmR0DumpDescriptor(pDesc, u32Val, "DS: ");
5159 }
5160
5161 rc = VMXReadVmcs32(VMX_VMCS16_HOST_ES_SEL, &u32Val); AssertRC(rc);
5162 Log4(("Host ES %#08x\n", u32Val));
5163 if (u32Val < HostGdtr.cbGdt)
5164 {
5165 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5166 hmR0DumpDescriptor(pDesc, u32Val, "ES: ");
5167 }
5168
5169 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FS_SEL, &u32Val); AssertRC(rc);
5170 Log4(("Host FS %#08x\n", u32Val));
5171 if (u32Val < HostGdtr.cbGdt)
5172 {
5173 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5174 hmR0DumpDescriptor(pDesc, u32Val, "FS: ");
5175 }
5176
5177 rc = VMXReadVmcs32(VMX_VMCS16_HOST_GS_SEL, &u32Val); AssertRC(rc);
5178 Log4(("Host GS %#08x\n", u32Val));
5179 if (u32Val < HostGdtr.cbGdt)
5180 {
5181 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5182 hmR0DumpDescriptor(pDesc, u32Val, "GS: ");
5183 }
5184
5185 rc = VMXReadVmcs32(VMX_VMCS16_HOST_SS_SEL, &u32Val); AssertRC(rc);
5186 Log4(("Host SS %#08x\n", u32Val));
5187 if (u32Val < HostGdtr.cbGdt)
5188 {
5189 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5190 hmR0DumpDescriptor(pDesc, u32Val, "SS: ");
5191 }
5192
5193 rc = VMXReadVmcs32(VMX_VMCS16_HOST_TR_SEL, &u32Val); AssertRC(rc);
5194 Log4(("Host TR %#08x\n", u32Val));
5195 if (u32Val < HostGdtr.cbGdt)
5196 {
5197 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5198 hmR0DumpDescriptor(pDesc, u32Val, "TR: ");
5199 }
5200
5201 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);
5202 Log4(("Host TR Base %#RHv\n", uHCReg));
5203 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);
5204 Log4(("Host GDTR Base %#RHv\n", uHCReg));
5205 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);
5206 Log4(("Host IDTR Base %#RHv\n", uHCReg));
5207 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);
5208 Log4(("Host SYSENTER CS %#08x\n", u32Val));
5209 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);
5210 Log4(("Host SYSENTER EIP %#RHv\n", uHCReg));
5211 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);
5212 Log4(("Host SYSENTER ESP %#RHv\n", uHCReg));
5213 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);
5214 Log4(("Host RSP %#RHv\n", uHCReg));
5215 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);
5216 Log4(("Host RIP %#RHv\n", uHCReg));
5217# if HC_ARCH_BITS == 64
5218 Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
5219 Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
5220 Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
5221 Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
5222 Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
5223 Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
5224# endif
5225#endif /* VBOX_STRICT */
5226 break;
5227 }
5228
5229 default:
5230 /* Impossible */
5231 AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
5232 break;
5233 }
5234 NOREF(pVM); NOREF(pCtx);
5235}
5236
5237
5238#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
5239#ifndef VMX_USE_CACHED_VMCS_ACCESSES
5240# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
5241#endif
5242#ifdef VBOX_STRICT
5243static bool hmR0VmxIsValidWriteField(uint32_t idxField)
5244{
5245 switch (idxField)
5246 {
5247 case VMX_VMCS_GUEST_RIP:
5248 case VMX_VMCS_GUEST_RSP:
5249 case VMX_VMCS_GUEST_SYSENTER_EIP:
5250 case VMX_VMCS_GUEST_SYSENTER_ESP:
5251 case VMX_VMCS_GUEST_GDTR_BASE:
5252 case VMX_VMCS_GUEST_IDTR_BASE:
5253 case VMX_VMCS_GUEST_CS_BASE:
5254 case VMX_VMCS_GUEST_DS_BASE:
5255 case VMX_VMCS_GUEST_ES_BASE:
5256 case VMX_VMCS_GUEST_FS_BASE:
5257 case VMX_VMCS_GUEST_GS_BASE:
5258 case VMX_VMCS_GUEST_SS_BASE:
5259 case VMX_VMCS_GUEST_LDTR_BASE:
5260 case VMX_VMCS_GUEST_TR_BASE:
5261 case VMX_VMCS_GUEST_CR3:
5262 return true;
5263 }
5264 return false;
5265}
5266
5267static bool hmR0VmxIsValidReadField(uint32_t idxField)
5268{
5269 switch (idxField)
5270 {
5271 /* Read-only fields. */
5272 case VMX_VMCS_RO_EXIT_QUALIFICATION:
5273 return true;
5274 }
5275 /* Remaining readable fields should also be writable. */
5276 return hmR0VmxIsValidWriteField(idxField);
5277}
5278#endif /* VBOX_STRICT */
5279
5280
5281/**
5282 * Executes the specified handler in 64-bit mode.
5283 *
5284 * @returns VBox status code (no informational status codes).
5285 * @param pVM The cross context VM structure.
5286 * @param pVCpu The cross context virtual CPU structure.
5287 * @param pCtx Pointer to the guest CPU context.
5288 * @param enmOp The operation to perform.
5289 * @param cParams Number of parameters.
5290 * @param paParam Array of 32-bit parameters.
5291 */
5292VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
5293 uint32_t cParams, uint32_t *paParam)
5294{
5295 NOREF(pCtx);
5296
5297 AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
5298 Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
5299 Assert(pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Write.aField));
5300 Assert(pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Read.aField));
5301
5302#ifdef VBOX_STRICT
5303 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries; i++)
5304 Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VMCSCache.Write.aField[i]));
5305
5306 for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries; i++)
5307 Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VMCSCache.Read.aField[i]));
5308#endif
5309
5310 /* Disable interrupts. */
5311 RTCCUINTREG fOldEFlags = ASMIntDisableFlags();
5312
5313#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
5314 RTCPUID idHostCpu = RTMpCpuId();
5315 CPUMR0SetLApic(pVCpu, idHostCpu);
5316#endif
5317
5318 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5319 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5320
5321 /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
5322 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5323 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
5324
5325 /* Leave VMX Root Mode. */
5326 VMXDisable();
5327
5328 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5329
5330 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
5331 CPUMSetHyperEIP(pVCpu, enmOp);
5332 for (int i = (int)cParams - 1; i >= 0; i--)
5333 CPUMPushHyper(pVCpu, paParam[i]);
5334
5335 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
5336
5337 /* Call the switcher. */
5338 int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
5339 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
5340
5341 /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
5342 /* Make sure the VMX instructions don't cause #UD faults. */
5343 SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
5344
5345 /* Re-enter VMX Root Mode */
5346 int rc2 = VMXEnable(HCPhysCpuPage);
5347 if (RT_FAILURE(rc2))
5348 {
5349 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5350 ASMSetFlags(fOldEFlags);
5351 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
5352 return rc2;
5353 }
5354
5355 rc2 = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5356 AssertRC(rc2);
5357 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
5358 Assert(!(ASMGetFlags() & X86_EFL_IF));
5359 ASMSetFlags(fOldEFlags);
5360 return rc;
5361}
5362
5363
5364/**
5365 * Prepares for and executes VMLAUNCH (64-bit guests) for 32-bit hosts
5366 * supporting 64-bit guests.
5367 *
5368 * @returns VBox status code.
5369 * @param fResume Whether to VMLAUNCH or VMRESUME.
5370 * @param pCtx Pointer to the guest-CPU context.
5371 * @param pCache Pointer to the VMCS cache.
5372 * @param pVM The cross context VM structure.
5373 * @param pVCpu The cross context virtual CPU structure.
5374 */
5375DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
5376{
5377 NOREF(fResume);
5378
5379 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5380 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5381
5382#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5383 pCache->uPos = 1;
5384 pCache->interPD = PGMGetInterPaeCR3(pVM);
5385 pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
5386#endif
5387
5388#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5389 pCache->TestIn.HCPhysCpuPage = 0;
5390 pCache->TestIn.HCPhysVmcs = 0;
5391 pCache->TestIn.pCache = 0;
5392 pCache->TestOut.HCPhysVmcs = 0;
5393 pCache->TestOut.pCache = 0;
5394 pCache->TestOut.pCtx = 0;
5395 pCache->TestOut.eflags = 0;
5396#else
5397 NOREF(pCache);
5398#endif
5399
5400 uint32_t aParam[10];
5401 aParam[0] = (uint32_t)(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
5402 aParam[1] = (uint32_t)(HCPhysCpuPage >> 32); /* Param 1: VMXON physical address - Hi. */
5403 aParam[2] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
5404 aParam[3] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs >> 32); /* Param 2: VMCS physical address - Hi. */
5405 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
5406 aParam[5] = 0;
5407 aParam[6] = VM_RC_ADDR(pVM, pVM);
5408 aParam[7] = 0;
5409 aParam[8] = VM_RC_ADDR(pVM, pVCpu);
5410 aParam[9] = 0;
5411
5412#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5413 pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
5414 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
5415#endif
5416 int rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_VMXRCStartVM64, RT_ELEMENTS(aParam), &aParam[0]);
5417
5418#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5419 Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
5420 Assert(pCtx->dr[4] == 10);
5421 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
5422#endif
5423
5424#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5425 AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
5426 AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5427 pVCpu->hm.s.vmx.HCPhysVmcs));
5428 AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5429 pCache->TestOut.HCPhysVmcs));
5430 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
5431 pCache->TestOut.pCache));
5432 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
5433 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
5434 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
5435 pCache->TestOut.pCtx));
5436 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
5437#endif
5438 return rc;
5439}
5440
5441
5442/**
5443 * Initialize the VMCS-Read cache.
5444 *
5445 * The VMCS cache is used for 32-bit hosts running 64-bit guests (except 32-bit
5446 * Darwin which runs with 64-bit paging in 32-bit mode) for 64-bit fields that
5447 * cannot be accessed in 32-bit mode. Some 64-bit fields -can- be accessed
5448 * (those that have a 32-bit FULL & HIGH part).
5449 *
5450 * @returns VBox status code.
5451 * @param pVM The cross context VM structure.
5452 * @param pVCpu The cross context virtual CPU structure.
5453 */
5454static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu)
5455{
5456#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \
5457{ \
5458 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
5459 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
5460 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
5461 ++cReadFields; \
5462}
5463
5464 AssertPtr(pVM);
5465 AssertPtr(pVCpu);
5466 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5467 uint32_t cReadFields = 0;
5468
5469 /*
5470 * Don't remove the #if 0'd fields in this code. They're listed here for consistency
5471 * and serve to indicate exceptions to the rules.
5472 */
5473
5474 /* Guest-natural selector base fields. */
5475#if 0
5476 /* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */
5477 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR0);
5478 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR4);
5479#endif
5480 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_ES_BASE);
5481 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CS_BASE);
5482 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SS_BASE);
5483 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DS_BASE);
5484 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_FS_BASE);
5485 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GS_BASE);
5486 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_LDTR_BASE);
5487 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_TR_BASE);
5488 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
5489 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
5490 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
5491 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
5492#if 0
5493 /* Unused natural width guest-state fields. */
5494 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS);
5495 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3); /* Handled in Nested Paging case */
5496#endif
5497 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
5498 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
5499
5500 /* 64-bit guest-state fields; unused as we use two 32-bit VMREADs for these 64-bit fields (using "FULL" and "HIGH" fields). */
5501#if 0
5502 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL);
5503 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_DEBUGCTL_FULL);
5504 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PAT_FULL);
5505 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_EFER_FULL);
5506 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL);
5507 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE0_FULL);
5508 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE1_FULL);
5509 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE2_FULL);
5510 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE3_FULL);
5511#endif
5512
5513 /* Natural width guest-state fields. */
5514 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
5515#if 0
5516 /* Currently unused field. */
5517 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR);
5518#endif
5519
5520 if (pVM->hm.s.fNestedPaging)
5521 {
5522 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
5523 AssertMsg(cReadFields == VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields,
5524 VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX));
5525 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
5526 }
5527 else
5528 {
5529 AssertMsg(cReadFields == VMX_VMCS_MAX_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields, VMX_VMCS_MAX_CACHE_IDX));
5530 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
5531 }
5532
5533#undef VMXLOCAL_INIT_READ_CACHE_FIELD
5534 return VINF_SUCCESS;
5535}
5536
5537
5538/**
5539 * Writes a field into the VMCS. This can either directly invoke a VMWRITE or
5540 * queue up the VMWRITE by using the VMCS write cache (on 32-bit hosts, except
5541 * darwin, running 64-bit guests).
5542 *
5543 * @returns VBox status code.
5544 * @param pVCpu The cross context virtual CPU structure.
5545 * @param idxField The VMCS field encoding.
5546 * @param u64Val 16, 32 or 64-bit value.
5547 */
5548VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5549{
5550 int rc;
5551 switch (idxField)
5552 {
5553 /*
5554 * These fields consists of a "FULL" and a "HIGH" part which can be written to individually.
5555 */
5556 /* 64-bit Control fields. */
5557 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
5558 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
5559 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
5560 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
5561 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
5562 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
5563 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
5564 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
5565 case VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL:
5566 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
5567 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
5568 case VMX_VMCS64_CTRL_EPTP_FULL:
5569 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
5570 /* 64-bit Guest-state fields. */
5571 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
5572 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
5573 case VMX_VMCS64_GUEST_PAT_FULL:
5574 case VMX_VMCS64_GUEST_EFER_FULL:
5575 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
5576 case VMX_VMCS64_GUEST_PDPTE0_FULL:
5577 case VMX_VMCS64_GUEST_PDPTE1_FULL:
5578 case VMX_VMCS64_GUEST_PDPTE2_FULL:
5579 case VMX_VMCS64_GUEST_PDPTE3_FULL:
5580 /* 64-bit Host-state fields. */
5581 case VMX_VMCS64_HOST_PAT_FULL:
5582 case VMX_VMCS64_HOST_EFER_FULL:
5583 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
5584 {
5585 rc = VMXWriteVmcs32(idxField, u64Val);
5586 rc |= VMXWriteVmcs32(idxField + 1, (uint32_t)(u64Val >> 32));
5587 break;
5588 }
5589
5590 /*
5591 * These fields do not have high and low parts. Queue up the VMWRITE by using the VMCS write-cache (for 64-bit
5592 * values). When we switch the host to 64-bit mode for running 64-bit guests, these VMWRITEs get executed then.
5593 */
5594 /* Natural-width Guest-state fields. */
5595 case VMX_VMCS_GUEST_CR3:
5596 case VMX_VMCS_GUEST_ES_BASE:
5597 case VMX_VMCS_GUEST_CS_BASE:
5598 case VMX_VMCS_GUEST_SS_BASE:
5599 case VMX_VMCS_GUEST_DS_BASE:
5600 case VMX_VMCS_GUEST_FS_BASE:
5601 case VMX_VMCS_GUEST_GS_BASE:
5602 case VMX_VMCS_GUEST_LDTR_BASE:
5603 case VMX_VMCS_GUEST_TR_BASE:
5604 case VMX_VMCS_GUEST_GDTR_BASE:
5605 case VMX_VMCS_GUEST_IDTR_BASE:
5606 case VMX_VMCS_GUEST_RSP:
5607 case VMX_VMCS_GUEST_RIP:
5608 case VMX_VMCS_GUEST_SYSENTER_ESP:
5609 case VMX_VMCS_GUEST_SYSENTER_EIP:
5610 {
5611 if (!(u64Val >> 32))
5612 {
5613 /* If this field is 64-bit, VT-x will zero out the top bits. */
5614 rc = VMXWriteVmcs32(idxField, (uint32_t)u64Val);
5615 }
5616 else
5617 {
5618 /* Assert that only the 32->64 switcher case should ever come here. */
5619 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests);
5620 rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
5621 }
5622 break;
5623 }
5624
5625 default:
5626 {
5627 AssertMsgFailed(("VMXWriteVmcs64Ex: Invalid field %#RX32 (pVCpu=%p u64Val=%#RX64)\n", idxField, pVCpu, u64Val));
5628 rc = VERR_INVALID_PARAMETER;
5629 break;
5630 }
5631 }
5632 AssertRCReturn(rc, rc);
5633 return rc;
5634}
5635
5636
5637/**
5638 * Queue up a VMWRITE by using the VMCS write cache.
5639 * This is only used on 32-bit hosts (except darwin) for 64-bit guests.
5640 *
5641 * @param pVCpu The cross context virtual CPU structure.
5642 * @param idxField The VMCS field encoding.
5643 * @param u64Val 16, 32 or 64-bit value.
5644 */
5645VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5646{
5647 AssertPtr(pVCpu);
5648 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5649
5650 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
5651 ("entries=%u\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
5652
5653 /* Make sure there are no duplicates. */
5654 for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
5655 {
5656 if (pCache->Write.aField[i] == idxField)
5657 {
5658 pCache->Write.aFieldVal[i] = u64Val;
5659 return VINF_SUCCESS;
5660 }
5661 }
5662
5663 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
5664 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
5665 pCache->Write.cValidEntries++;
5666 return VINF_SUCCESS;
5667}
5668#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
5669
5670
5671/**
5672 * Sets up the usage of TSC-offsetting and updates the VMCS.
5673 *
5674 * If offsetting is not possible, cause VM-exits on RDTSC(P)s. Also sets up the
5675 * VMX preemption timer.
5676 *
5677 * @returns VBox status code.
5678 * @param pVM The cross context VM structure.
5679 * @param pVCpu The cross context virtual CPU structure.
5680 *
5681 * @remarks No-long-jump zone!!!
5682 */
5683static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVM pVM, PVMCPU pVCpu)
5684{
5685 int rc;
5686 bool fOffsettedTsc;
5687 bool fParavirtTsc;
5688 if (pVM->hm.s.vmx.fUsePreemptTimer)
5689 {
5690 uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset,
5691 &fOffsettedTsc, &fParavirtTsc);
5692
5693 /* Make sure the returned values have sane upper and lower boundaries. */
5694 uint64_t u64CpuHz = SUPGetCpuHzFromGipBySetIndex(g_pSUPGlobalInfoPage, pVCpu->iHostCpuSet);
5695 cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second */
5696 cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
5697 cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
5698
5699 uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
5700 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE, cPreemptionTickCount); AssertRC(rc);
5701 }
5702 else
5703 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset, &fParavirtTsc);
5704
5705 /** @todo later optimize this to be done elsewhere and not before every
5706 * VM-entry. */
5707 if (fParavirtTsc)
5708 {
5709 /* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
5710 information before every VM-entry, hence disable it for performance sake. */
5711#if 0
5712 rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
5713 AssertRC(rc);
5714#endif
5715 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
5716 }
5717
5718 if (fOffsettedTsc && RT_LIKELY(!pVCpu->hm.s.fDebugWantRdTscExit))
5719 {
5720 /* Note: VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
5721 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset); AssertRC(rc);
5722
5723 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
5724 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
5725 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
5726 }
5727 else
5728 {
5729 /* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
5730 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
5731 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
5732 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
5733 }
5734}
5735
5736
5737#ifdef HMVMX_USE_IEM_EVENT_REFLECTION
5738/**
5739 * Gets the IEM exception flags for the specified vector and IDT vectoring /
5740 * VM-exit interruption info type.
5741 *
5742 * @returns The IEM exception flags.
5743 * @param uVector The event vector.
5744 * @param uVmxVectorType The VMX event type.
5745 */
5746static uint32_t hmR0VmxGetIemXcptFlags(uint8_t uVector, uint32_t uVmxVectorType)
5747{
5748 uint32_t fIemXcptFlags;
5749 switch (uVmxVectorType)
5750 {
5751 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
5752 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
5753 fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5754 break;
5755
5756 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
5757 fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5758 break;
5759
5760 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
5761 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT | IEM_XCPT_FLAGS_ICEBP_INSTR;
5762 break;
5763
5764 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT:
5765 {
5766 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5767 if (uVector == X86_XCPT_BP)
5768 fIemXcptFlags |= IEM_XCPT_FLAGS_BP_INSTR;
5769 else if (uVector == X86_XCPT_OF)
5770 fIemXcptFlags |= IEM_XCPT_FLAGS_OF_INSTR;
5771 else
5772 {
5773 fIemXcptFlags = 0;
5774 AssertMsgFailed(("Unexpected vector for software int. uVector=%#x", uVector));
5775 }
5776 break;
5777 }
5778
5779 default:
5780 fIemXcptFlags = 0;
5781 AssertMsgFailed(("Unexpected vector type! uVmxVectorType=%#x uVector=%#x", uVmxVectorType, uVector));
5782 break;
5783 }
5784 return fIemXcptFlags;
5785}
5786
5787#else
5788/**
5789 * Determines if an exception is a contributory exception.
5790 *
5791 * Contributory exceptions are ones which can cause double-faults unless the
5792 * original exception was a benign exception. Page-fault is intentionally not
5793 * included here as it's a conditional contributory exception.
5794 *
5795 * @returns true if the exception is contributory, false otherwise.
5796 * @param uVector The exception vector.
5797 */
5798DECLINLINE(bool) hmR0VmxIsContributoryXcpt(const uint32_t uVector)
5799{
5800 switch (uVector)
5801 {
5802 case X86_XCPT_GP:
5803 case X86_XCPT_SS:
5804 case X86_XCPT_NP:
5805 case X86_XCPT_TS:
5806 case X86_XCPT_DE:
5807 return true;
5808 default:
5809 break;
5810 }
5811 return false;
5812}
5813#endif /* HMVMX_USE_IEM_EVENT_REFLECTION */
5814
5815
5816/**
5817 * Sets an event as a pending event to be injected into the guest.
5818 *
5819 * @param pVCpu The cross context virtual CPU structure.
5820 * @param u32IntInfo The VM-entry interruption-information field.
5821 * @param cbInstr The VM-entry instruction length in bytes (for software
5822 * interrupts, exceptions and privileged software
5823 * exceptions).
5824 * @param u32ErrCode The VM-entry exception error code.
5825 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a
5826 * page-fault.
5827 *
5828 * @remarks Statistics counter assumes this is a guest event being injected or
5829 * re-injected into the guest, i.e. 'StatInjectPendingReflect' is
5830 * always incremented.
5831 */
5832DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
5833 RTGCUINTPTR GCPtrFaultAddress)
5834{
5835 Assert(!pVCpu->hm.s.Event.fPending);
5836 pVCpu->hm.s.Event.fPending = true;
5837 pVCpu->hm.s.Event.u64IntInfo = u32IntInfo;
5838 pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
5839 pVCpu->hm.s.Event.cbInstr = cbInstr;
5840 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
5841}
5842
5843
5844/**
5845 * Sets a double-fault (\#DF) exception as pending-for-injection into the VM.
5846 *
5847 * @param pVCpu The cross context virtual CPU structure.
5848 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
5849 * out-of-sync. Make sure to update the required fields
5850 * before using them.
5851 */
5852DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5853{
5854 NOREF(pMixedCtx);
5855 uint32_t u32IntInfo = X86_XCPT_DF | VMX_EXIT_INTERRUPTION_INFO_VALID;
5856 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
5857 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
5858 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5859}
5860
5861
5862/**
5863 * Handle a condition that occurred while delivering an event through the guest
5864 * IDT.
5865 *
5866 * @returns Strict VBox status code (i.e. informational status codes too).
5867 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
5868 * @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought
5869 * to continue execution of the guest which will delivery the \#DF.
5870 * @retval VINF_EM_RESET if we detected a triple-fault condition.
5871 * @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5872 *
5873 * @param pVCpu The cross context virtual CPU structure.
5874 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
5875 * out-of-sync. Make sure to update the required fields
5876 * before using them.
5877 * @param pVmxTransient Pointer to the VMX transient structure.
5878 *
5879 * @remarks No-long-jump zone!!!
5880 */
5881static VBOXSTRICTRC hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
5882{
5883 uint32_t const uExitVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
5884
5885 int rc2 = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient); AssertRCReturn(rc2, rc2);
5886 rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient); AssertRCReturn(rc2, rc2);
5887
5888 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
5889 if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
5890 {
5891 uint32_t const uIdtVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
5892 uint32_t const uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
5893#ifdef HMVMX_USE_IEM_EVENT_REFLECTION
5894 /* See Intel spec. 30.7.1.1 "Reflecting Exceptions to Guest Software". */
5895 IEMXCPTRAISE enmRaise;
5896 IEMXCPTRAISEINFO fRaiseInfo;
5897 if (VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo))
5898 {
5899 uint32_t const uExitVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uExitIntInfo);
5900 uint32_t const fIdtVectorFlags = hmR0VmxGetIemXcptFlags(uIdtVector, uIdtVectorType);
5901 uint32_t const fExitVectorFlags = hmR0VmxGetIemXcptFlags(uExitVector, uExitVectorType);
5902 AssertMsg( uExitVectorType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
5903 || uExitVectorType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI,
5904 ("hmR0VmxCheckExitDueToEventDelivery: Unexpected VM-exit interruption info. type %#x!\n", uExitVectorType));
5905 enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector,
5906 &fRaiseInfo);
5907
5908 if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_XCPT | IEMXCPTRAISEINFO_NMI_XCPT))
5909 {
5910 /*
5911 * For some reason we go back to the interpreter if delivery of an external interrupt or
5912 * NMI causes an exception, see hmR0VmxExitXcptOrNmi. As long as we go back to the interpret
5913 * we need to keep the previous (first) event pending, hence this hack.
5914 */
5915 enmRaise = IEMXCPTRAISE_PREV_EVENT;
5916
5917 /* Determine a vectoring #PF condition, see comment in hmR0VmxExitXcptPF(). */
5918 if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF | IEMXCPTRAISEINFO_NMI_PF))
5919 pVmxTransient->fVectoringPF = true;
5920 }
5921 }
5922 else
5923 {
5924 /*
5925 * If event delivery caused an EPT violation/misconfig or APIC access VM-exit, then the VM-exit
5926 * interruption-information will not be valid as it's not an exception and we end up here.
5927 *
5928 * If the event was an external interrupt or hardare exception (incl. NMI) it is sufficient to
5929 * reflect this event to the guest after handling the VM-exit.
5930 *
5931 * If the event was a software interrupt (generated with INT n) or a software exception (generated
5932 * by INT3/INTO) or a privileged software exception (generated by INT1), we can handle the VM-exit
5933 * and continue guest execution which will re-execute the instruction rather than re-injecting the
5934 * event, as that can cause premature trips to ring-3 before injection and involve TRPM which
5935 * currently has no way of storing that the exceptions were caused by these special instructions.
5936 */
5937 if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
5938 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
5939 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT)
5940 enmRaise = IEMXCPTRAISE_PREV_EVENT;
5941 else
5942 enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5943 fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5944 }
5945
5946 /*
5947 * On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig
5948 * etc.) occurred while delivering the NMI, we need to clear the block-by-NMI field in the guest
5949 * interruptibility-state before re-delivering the NMI after handling the VM-exit. Otherwise the
5950 * subsequent VM-entry would fail.
5951 *
5952 * See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
5953 */
5954 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
5955 && uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
5956 && ( enmRaise == IEMXCPTRAISE_PREV_EVENT
5957 || (fRaiseInfo & IEMXCPTRAISEINFO_NMI_PF))
5958 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
5959 {
5960 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5961 }
5962
5963 switch (enmRaise)
5964 {
5965 case IEMXCPTRAISE_CURRENT_XCPT:
5966 case IEMXCPTRAISE_REEXEC_INSTR:
5967 Assert(rcStrict == VINF_SUCCESS);
5968 break;
5969
5970 case IEMXCPTRAISE_PREV_EVENT:
5971 {
5972 /*
5973 * Re-raise the previous (first) exception/interrupt as delivery caused a premature VM-exit.
5974 */
5975 Assert( uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT
5976 && uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
5977 && uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
5978
5979 uint32_t u32ErrCode;
5980 if (VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo))
5981 {
5982 rc2 = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
5983 AssertRCReturn(rc2, rc2);
5984 u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
5985 }
5986 else
5987 u32ErrCode = 0;
5988
5989 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF, see hmR0VmxExitXcptPF(). */
5990 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5991 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
5992 0 /* cbInstr */, u32ErrCode, pMixedCtx->cr2);
5993
5994 Log4(("IDT: vcpu[%RU32] Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
5995 pVCpu->hm.s.Event.u32ErrCode));
5996 Assert(rcStrict == VINF_SUCCESS);
5997 break;
5998 }
5999
6000 case IEMXCPTRAISE_DOUBLE_FAULT:
6001 {
6002 /*
6003 * Determing a vectoring double #PF condition. Used later, when PGM evaluates the
6004 * second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
6005 */
6006 if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
6007 {
6008 pVmxTransient->fVectoringDoublePF = true;
6009 Log4(("IDT: vcpu[%RU32] Vectoring double #PF %#RX64 cr2=%#RX64\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
6010 pMixedCtx->cr2));
6011 rcStrict = VINF_SUCCESS;
6012 }
6013 else
6014 {
6015 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6016 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
6017 Log4(("IDT: vcpu[%RU32] Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->idCpu,
6018 pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
6019 rcStrict = VINF_HM_DOUBLE_FAULT;
6020 }
6021 break;
6022 }
6023
6024 case IEMXCPTRAISE_TRIPLE_FAULT:
6025 {
6026 Log4(("IDT: vcpu[%RU32] Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", pVCpu->idCpu, uIdtVector,
6027 uExitVector));
6028 rcStrict = VINF_EM_RESET;
6029 break;
6030 }
6031
6032 case IEMXCPTRAISE_CPU_HANG:
6033 {
6034 Log4(("IDT: vcpu[%RU32] Bad guest! Entering CPU hang. fRaiseInfo=%#x\n", pVCpu->idCpu, fRaiseInfo));
6035 rcStrict = VERR_EM_GUEST_CPU_HANG;
6036 break;
6037 }
6038
6039 default:
6040 {
6041 AssertMsgFailed(("IDT: vcpu[%RU32] Unexpected/invalid value! enmRaise=%#x\n", pVCpu->idCpu, enmRaise));
6042 rcStrict = VERR_VMX_IPE_2;
6043 break;
6044 }
6045 }
6046#else
6047 typedef enum
6048 {
6049 VMXREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
6050 VMXREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
6051 VMXREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
6052 VMXREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
6053 VMXREFLECTXCPT_NONE /* Nothing to reflect. */
6054 } VMXREFLECTXCPT;
6055
6056 /* See Intel spec. 30.7.1.1 "Reflecting Exceptions to Guest Software". */
6057 VMXREFLECTXCPT enmReflect = VMXREFLECTXCPT_NONE;
6058 if (VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo))
6059 {
6060 if (uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT)
6061 {
6062 enmReflect = VMXREFLECTXCPT_XCPT;
6063#ifdef VBOX_STRICT
6064 if ( hmR0VmxIsContributoryXcpt(uIdtVector)
6065 && uExitVector == X86_XCPT_PF)
6066 {
6067 Log4(("IDT: vcpu[%RU32] Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
6068 }
6069#endif
6070 if ( uExitVector == X86_XCPT_PF
6071 && uIdtVector == X86_XCPT_PF)
6072 {
6073 pVmxTransient->fVectoringDoublePF = true;
6074 Log4(("IDT: vcpu[%RU32] Vectoring Double #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
6075 }
6076 else if ( uExitVector == X86_XCPT_AC
6077 && uIdtVector == X86_XCPT_AC)
6078 {
6079 enmReflect = VMXREFLECTXCPT_HANG;
6080 Log4(("IDT: Nested #AC - Bad guest\n"));
6081 }
6082 else if ( (pVCpu->hm.s.vmx.u32XcptBitmap & HMVMX_CONTRIBUTORY_XCPT_MASK)
6083 && hmR0VmxIsContributoryXcpt(uExitVector)
6084 && ( hmR0VmxIsContributoryXcpt(uIdtVector)
6085 || uIdtVector == X86_XCPT_PF))
6086 {
6087 enmReflect = VMXREFLECTXCPT_DF;
6088 }
6089 else if (uIdtVector == X86_XCPT_DF)
6090 enmReflect = VMXREFLECTXCPT_TF;
6091 }
6092 else if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
6093 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
6094 {
6095 /*
6096 * Ignore software interrupts (INT n), software exceptions (#BP, #OF) and
6097 * privileged software exception (#DB from ICEBP) as they reoccur when restarting the instruction.
6098 */
6099 enmReflect = VMXREFLECTXCPT_XCPT;
6100
6101 if (uExitVector == X86_XCPT_PF)
6102 {
6103 pVmxTransient->fVectoringPF = true;
6104 Log4(("IDT: vcpu[%RU32] Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
6105 }
6106 }
6107 }
6108 else if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
6109 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
6110 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
6111 {
6112 /*
6113 * If event delivery caused an EPT violation/misconfig or APIC access VM-exit, then the VM-exit
6114 * interruption-information will not be valid as it's not an exception and we end up here. In such cases,
6115 * it is sufficient to reflect the original exception to the guest after handling the VM-exit.
6116 */
6117 enmReflect = VMXREFLECTXCPT_XCPT;
6118 }
6119
6120 /*
6121 * On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig etc.) occurred
6122 * while delivering the NMI, we need to clear the block-by-NMI field in the guest interruptibility-state before
6123 * re-delivering the NMI after handling the VM-exit. Otherwise the subsequent VM-entry would fail.
6124 *
6125 * See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
6126 */
6127 if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
6128 && enmReflect == VMXREFLECTXCPT_XCPT
6129 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
6130 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6131 {
6132 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6133 }
6134
6135 switch (enmReflect)
6136 {
6137 case VMXREFLECTXCPT_XCPT:
6138 {
6139 Assert( uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT
6140 && uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
6141 && uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
6142
6143 uint32_t u32ErrCode = 0;
6144 if (VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo))
6145 {
6146 rc2 = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
6147 AssertRCReturn(rc2, rc2);
6148 u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
6149 }
6150
6151 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF. See hmR0VmxExitXcptPF(). */
6152 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6153 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
6154 0 /* cbInstr */, u32ErrCode, pMixedCtx->cr2);
6155 rcStrict = VINF_SUCCESS;
6156 Log4(("IDT: vcpu[%RU32] Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->idCpu,
6157 pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.u32ErrCode));
6158
6159 break;
6160 }
6161
6162 case VMXREFLECTXCPT_DF:
6163 {
6164 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6165 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
6166 rcStrict = VINF_HM_DOUBLE_FAULT;
6167 Log4(("IDT: vcpu[%RU32] Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->idCpu,
6168 pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
6169
6170 break;
6171 }
6172
6173 case VMXREFLECTXCPT_TF:
6174 {
6175 rcStrict = VINF_EM_RESET;
6176 Log4(("IDT: vcpu[%RU32] Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", pVCpu->idCpu, uIdtVector,
6177 uExitVector));
6178 break;
6179 }
6180
6181 case VMXREFLECTXCPT_HANG:
6182 {
6183 rcStrict = VERR_EM_GUEST_CPU_HANG;
6184 break;
6185 }
6186
6187 default:
6188 Assert(rcStrict == VINF_SUCCESS);
6189 break;
6190 }
6191#endif /* HMVMX_USE_IEM_EVENT_REFLECTION */
6192 }
6193 else if ( VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo)
6194 && VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(pVmxTransient->uExitIntInfo)
6195 && uExitVector != X86_XCPT_DF
6196 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
6197 {
6198 /*
6199 * Execution of IRET caused this fault when NMI blocking was in effect (i.e we're in the guest NMI handler).
6200 * We need to set the block-by-NMI field so that NMIs remain blocked until the IRET execution is restarted.
6201 * See Intel spec. 30.7.1.2 "Resuming guest software after handling an exception".
6202 */
6203 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6204 {
6205 Log4(("hmR0VmxCheckExitDueToEventDelivery: vcpu[%RU32] Setting VMCPU_FF_BLOCK_NMIS. Valid=%RTbool uExitReason=%u\n",
6206 pVCpu->idCpu, VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo), pVmxTransient->uExitReason));
6207 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6208 }
6209 }
6210
6211 Assert( rcStrict == VINF_SUCCESS || rcStrict == VINF_HM_DOUBLE_FAULT
6212 || rcStrict == VINF_EM_RESET || rcStrict == VERR_EM_GUEST_CPU_HANG);
6213 return rcStrict;
6214}
6215
6216
6217/**
6218 * Saves the guest's CR0 register from the VMCS into the guest-CPU context.
6219 *
6220 * @returns VBox status code.
6221 * @param pVCpu The cross context virtual CPU structure.
6222 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6223 * out-of-sync. Make sure to update the required fields
6224 * before using them.
6225 *
6226 * @remarks No-long-jump zone!!!
6227 */
6228static int hmR0VmxSaveGuestCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6229{
6230 NOREF(pMixedCtx);
6231
6232 /*
6233 * While in the middle of saving guest-CR0, we could get preempted and re-invoked from the preemption hook,
6234 * see hmR0VmxLeave(). Safer to just make this code non-preemptible.
6235 */
6236 VMMRZCallRing3Disable(pVCpu);
6237 HM_DISABLE_PREEMPT();
6238
6239 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0))
6240 {
6241#ifndef DEBUG_bird /** @todo this triggers running bs3-cpu-generated-1.img with --debug-command-line
6242 * and 'dbgc-init' containing:
6243 * sxe "xcpt_de"
6244 * sxe "xcpt_bp"
6245 * sxi "xcpt_gp"
6246 * sxi "xcpt_ss"
6247 * sxi "xcpt_np"
6248 */
6249 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
6250#endif
6251 uint32_t uVal = 0;
6252 uint32_t uShadow = 0;
6253 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &uVal);
6254 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uShadow);
6255 AssertRCReturn(rc, rc);
6256
6257 uVal = (uShadow & pVCpu->hm.s.vmx.u32CR0Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR0Mask);
6258 CPUMSetGuestCR0(pVCpu, uVal);
6259 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0);
6260 }
6261
6262 HM_RESTORE_PREEMPT();
6263 VMMRZCallRing3Enable(pVCpu);
6264 return VINF_SUCCESS;
6265}
6266
6267
6268/**
6269 * Saves the guest's CR4 register from the VMCS into the guest-CPU context.
6270 *
6271 * @returns VBox status code.
6272 * @param pVCpu The cross context virtual CPU structure.
6273 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6274 * out-of-sync. Make sure to update the required fields
6275 * before using them.
6276 *
6277 * @remarks No-long-jump zone!!!
6278 */
6279static int hmR0VmxSaveGuestCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6280{
6281 NOREF(pMixedCtx);
6282
6283 int rc = VINF_SUCCESS;
6284 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4))
6285 {
6286 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4));
6287 uint32_t uVal = 0;
6288 uint32_t uShadow = 0;
6289 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &uVal);
6290 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uShadow);
6291 AssertRCReturn(rc, rc);
6292
6293 uVal = (uShadow & pVCpu->hm.s.vmx.u32CR4Mask) | (uVal & ~pVCpu->hm.s.vmx.u32CR4Mask);
6294 CPUMSetGuestCR4(pVCpu, uVal);
6295 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4);
6296 }
6297 return rc;
6298}
6299
6300
6301/**
6302 * Saves the guest's RIP register from the VMCS into the guest-CPU context.
6303 *
6304 * @returns VBox status code.
6305 * @param pVCpu The cross context virtual CPU structure.
6306 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6307 * out-of-sync. Make sure to update the required fields
6308 * before using them.
6309 *
6310 * @remarks No-long-jump zone!!!
6311 */
6312static int hmR0VmxSaveGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6313{
6314 int rc = VINF_SUCCESS;
6315 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP))
6316 {
6317 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP));
6318 uint64_t u64Val = 0;
6319 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);
6320 AssertRCReturn(rc, rc);
6321
6322 pMixedCtx->rip = u64Val;
6323 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP);
6324 }
6325 return rc;
6326}
6327
6328
6329/**
6330 * Saves the guest's RSP register from the VMCS into the guest-CPU context.
6331 *
6332 * @returns VBox status code.
6333 * @param pVCpu The cross context virtual CPU structure.
6334 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6335 * out-of-sync. Make sure to update the required fields
6336 * before using them.
6337 *
6338 * @remarks No-long-jump zone!!!
6339 */
6340static int hmR0VmxSaveGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6341{
6342 int rc = VINF_SUCCESS;
6343 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RSP))
6344 {
6345 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP));
6346 uint64_t u64Val = 0;
6347 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);
6348 AssertRCReturn(rc, rc);
6349
6350 pMixedCtx->rsp = u64Val;
6351 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RSP);
6352 }
6353 return rc;
6354}
6355
6356
6357/**
6358 * Saves the guest's RFLAGS from the VMCS into the guest-CPU context.
6359 *
6360 * @returns VBox status code.
6361 * @param pVCpu The cross context virtual CPU structure.
6362 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6363 * out-of-sync. Make sure to update the required fields
6364 * before using them.
6365 *
6366 * @remarks No-long-jump zone!!!
6367 */
6368static int hmR0VmxSaveGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6369{
6370 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS))
6371 {
6372 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS));
6373 uint32_t uVal = 0;
6374 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &uVal);
6375 AssertRCReturn(rc, rc);
6376
6377 pMixedCtx->eflags.u32 = uVal;
6378 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active) /* Undo our real-on-v86-mode changes to eflags if necessary. */
6379 {
6380 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
6381 Log4(("Saving real-mode EFLAGS VT-x view=%#RX32\n", pMixedCtx->eflags.u32));
6382
6383 pMixedCtx->eflags.Bits.u1VM = 0;
6384 pMixedCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.Eflags.Bits.u2IOPL;
6385 }
6386
6387 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS);
6388 }
6389 return VINF_SUCCESS;
6390}
6391
6392
6393/**
6394 * Wrapper for saving the guest's RIP, RSP and RFLAGS from the VMCS into the
6395 * guest-CPU context.
6396 */
6397DECLINLINE(int) hmR0VmxSaveGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6398{
6399 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6400 rc |= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
6401 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
6402 return rc;
6403}
6404
6405
6406/**
6407 * Saves the guest's interruptibility-state ("interrupt shadow" as AMD calls it)
6408 * from the guest-state area in the VMCS.
6409 *
6410 * @param pVCpu The cross context virtual CPU structure.
6411 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6412 * out-of-sync. Make sure to update the required fields
6413 * before using them.
6414 *
6415 * @remarks No-long-jump zone!!!
6416 */
6417static void hmR0VmxSaveGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6418{
6419 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_INTR_STATE))
6420 {
6421 uint32_t uIntrState = 0;
6422 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
6423 AssertRC(rc);
6424
6425 if (!uIntrState)
6426 {
6427 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6428 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6429
6430 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6431 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6432 }
6433 else
6434 {
6435 if (uIntrState & ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS
6436 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI))
6437 {
6438 rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6439 AssertRC(rc);
6440 rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* for hmR0VmxGetGuestIntrState(). */
6441 AssertRC(rc);
6442
6443 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
6444 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
6445 }
6446 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6447 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6448
6449 if (uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI)
6450 {
6451 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6452 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6453 }
6454 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6455 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6456 }
6457
6458 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_INTR_STATE);
6459 }
6460}
6461
6462
6463/**
6464 * Saves the guest's activity state.
6465 *
6466 * @returns VBox status code.
6467 * @param pVCpu The cross context virtual CPU structure.
6468 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6469 * out-of-sync. Make sure to update the required fields
6470 * before using them.
6471 *
6472 * @remarks No-long-jump zone!!!
6473 */
6474static int hmR0VmxSaveGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6475{
6476 NOREF(pMixedCtx);
6477 /* Nothing to do for now until we make use of different guest-CPU activity state. Just update the flag. */
6478 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_ACTIVITY_STATE);
6479 return VINF_SUCCESS;
6480}
6481
6482
6483/**
6484 * Saves the guest SYSENTER MSRs (SYSENTER_CS, SYSENTER_EIP, SYSENTER_ESP) from
6485 * the current VMCS into the guest-CPU context.
6486 *
6487 * @returns VBox status code.
6488 * @param pVCpu The cross context virtual CPU structure.
6489 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6490 * out-of-sync. Make sure to update the required fields
6491 * before using them.
6492 *
6493 * @remarks No-long-jump zone!!!
6494 */
6495static int hmR0VmxSaveGuestSysenterMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6496{
6497 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR))
6498 {
6499 Assert(!HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR));
6500 uint32_t u32Val = 0;
6501 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val); AssertRCReturn(rc, rc);
6502 pMixedCtx->SysEnter.cs = u32Val;
6503 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR);
6504 }
6505
6506 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR))
6507 {
6508 Assert(!HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR));
6509 uint64_t u64Val = 0;
6510 int rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &u64Val); AssertRCReturn(rc, rc);
6511 pMixedCtx->SysEnter.eip = u64Val;
6512 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR);
6513 }
6514 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR))
6515 {
6516 Assert(!HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR));
6517 uint64_t u64Val = 0;
6518 int rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &u64Val); AssertRCReturn(rc, rc);
6519 pMixedCtx->SysEnter.esp = u64Val;
6520 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR);
6521 }
6522 return VINF_SUCCESS;
6523}
6524
6525
6526/**
6527 * Saves the set of guest MSRs (that we restore lazily while leaving VT-x) from
6528 * the CPU back into the guest-CPU context.
6529 *
6530 * @returns VBox status code.
6531 * @param pVCpu The cross context virtual CPU structure.
6532 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6533 * out-of-sync. Make sure to update the required fields
6534 * before using them.
6535 *
6536 * @remarks No-long-jump zone!!!
6537 */
6538static int hmR0VmxSaveGuestLazyMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6539{
6540 /* Since this can be called from our preemption hook it's safer to make the guest-MSRs update non-preemptible. */
6541 VMMRZCallRing3Disable(pVCpu);
6542 HM_DISABLE_PREEMPT();
6543
6544 /* Doing the check here ensures we don't overwrite already-saved guest MSRs from a preemption hook. */
6545 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS))
6546 {
6547 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS));
6548 hmR0VmxLazySaveGuestMsrs(pVCpu, pMixedCtx);
6549 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS);
6550 }
6551
6552 HM_RESTORE_PREEMPT();
6553 VMMRZCallRing3Enable(pVCpu);
6554
6555 return VINF_SUCCESS;
6556}
6557
6558
6559/**
6560 * Saves the auto load/store'd guest MSRs from the current VMCS into
6561 * the guest-CPU context.
6562 *
6563 * @returns VBox status code.
6564 * @param pVCpu The cross context virtual CPU structure.
6565 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6566 * out-of-sync. Make sure to update the required fields
6567 * before using them.
6568 *
6569 * @remarks No-long-jump zone!!!
6570 */
6571static int hmR0VmxSaveGuestAutoLoadStoreMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6572{
6573 if (HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS))
6574 return VINF_SUCCESS;
6575
6576 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS));
6577 PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
6578 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
6579 Log4(("hmR0VmxSaveGuestAutoLoadStoreMsrs: cMsrs=%u\n", cMsrs));
6580 for (uint32_t i = 0; i < cMsrs; i++, pMsr++)
6581 {
6582 switch (pMsr->u32Msr)
6583 {
6584 case MSR_K8_TSC_AUX: CPUMR0SetGuestTscAux(pVCpu, pMsr->u64Value); break;
6585 case MSR_K8_LSTAR: pMixedCtx->msrLSTAR = pMsr->u64Value; break;
6586 case MSR_K6_STAR: pMixedCtx->msrSTAR = pMsr->u64Value; break;
6587 case MSR_K8_SF_MASK: pMixedCtx->msrSFMASK = pMsr->u64Value; break;
6588 case MSR_K8_KERNEL_GS_BASE: pMixedCtx->msrKERNELGSBASE = pMsr->u64Value; break;
6589 case MSR_K6_EFER: /* Nothing to do here since we intercept writes, see hmR0VmxLoadGuestMsrs(). */
6590 break;
6591
6592 default:
6593 {
6594 AssertMsgFailed(("Unexpected MSR in auto-load/store area. uMsr=%#RX32 cMsrs=%u\n", pMsr->u32Msr, cMsrs));
6595 pVCpu->hm.s.u32HMError = pMsr->u32Msr;
6596 return VERR_HM_UNEXPECTED_LD_ST_MSR;
6597 }
6598 }
6599 }
6600
6601 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS);
6602 return VINF_SUCCESS;
6603}
6604
6605
6606/**
6607 * Saves the guest control registers from the current VMCS into the guest-CPU
6608 * context.
6609 *
6610 * @returns VBox status code.
6611 * @param pVCpu The cross context virtual CPU structure.
6612 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6613 * out-of-sync. Make sure to update the required fields
6614 * before using them.
6615 *
6616 * @remarks No-long-jump zone!!!
6617 */
6618static int hmR0VmxSaveGuestControlRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6619{
6620 /* Guest CR0. Guest FPU. */
6621 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6622 AssertRCReturn(rc, rc);
6623
6624 /* Guest CR4. */
6625 rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
6626 AssertRCReturn(rc, rc);
6627
6628 /* Guest CR2 - updated always during the world-switch or in #PF. */
6629 /* Guest CR3. Only changes with Nested Paging. This must be done -after- saving CR0 and CR4 from the guest! */
6630 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR3))
6631 {
6632 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3));
6633 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
6634 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4));
6635
6636 PVM pVM = pVCpu->CTX_SUFF(pVM);
6637 if ( pVM->hm.s.vmx.fUnrestrictedGuest
6638 || ( pVM->hm.s.fNestedPaging
6639 && CPUMIsGuestPagingEnabledEx(pMixedCtx)))
6640 {
6641 uint64_t u64Val = 0;
6642 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
6643 if (pMixedCtx->cr3 != u64Val)
6644 {
6645 CPUMSetGuestCR3(pVCpu, u64Val);
6646 if (VMMRZCallRing3IsEnabled(pVCpu))
6647 {
6648 PGMUpdateCR3(pVCpu, u64Val);
6649 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6650 }
6651 else
6652 {
6653 /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMUpdateCR3().*/
6654 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
6655 }
6656 }
6657
6658 /* If the guest is in PAE mode, sync back the PDPE's into the guest state. */
6659 if (CPUMIsGuestInPAEModeEx(pMixedCtx)) /* Reads CR0, CR4 and EFER MSR (EFER is always up-to-date). */
6660 {
6661 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
6662 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
6663 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
6664 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
6665 AssertRCReturn(rc, rc);
6666
6667 if (VMMRZCallRing3IsEnabled(pVCpu))
6668 {
6669 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6670 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6671 }
6672 else
6673 {
6674 /* Set the force flag to inform PGM about it when necessary. It is cleared by PGMGstUpdatePaePdpes(). */
6675 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
6676 }
6677 }
6678 }
6679
6680 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR3);
6681 }
6682
6683 /*
6684 * Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> hmR0VmxCallRing3Callback()
6685 * -> VMMRZCallRing3Disable() -> hmR0VmxSaveGuestState() -> Set VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
6686 * -> continue with VM-exit handling -> hmR0VmxSaveGuestControlRegs() and here we are.
6687 *
6688 * The reason for such complicated handling is because VM-exits that call into PGM expect CR3 to be up-to-date and thus
6689 * if any CR3-saves -before- the VM-exit (longjmp) postponed the CR3 update via the force-flag, any VM-exit handler that
6690 * calls into PGM when it re-saves CR3 will end up here and we call PGMUpdateCR3(). This is why the code below should
6691 * -NOT- check if HMVMX_UPDATED_GUEST_CR3 is already set or not!
6692 *
6693 * The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
6694 */
6695 if (VMMRZCallRing3IsEnabled(pVCpu))
6696 {
6697 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6698 PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
6699
6700 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6701 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6702
6703 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6704 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6705 }
6706
6707 return rc;
6708}
6709
6710
6711/**
6712 * Reads a guest segment register from the current VMCS into the guest-CPU
6713 * context.
6714 *
6715 * @returns VBox status code.
6716 * @param pVCpu The cross context virtual CPU structure.
6717 * @param idxSel Index of the selector in the VMCS.
6718 * @param idxLimit Index of the segment limit in the VMCS.
6719 * @param idxBase Index of the segment base in the VMCS.
6720 * @param idxAccess Index of the access rights of the segment in the VMCS.
6721 * @param pSelReg Pointer to the segment selector.
6722 *
6723 * @remarks No-long-jump zone!!!
6724 * @remarks Never call this function directly!!! Use the VMXLOCAL_READ_SEG()
6725 * macro as that takes care of whether to read from the VMCS cache or
6726 * not.
6727 */
6728DECLINLINE(int) hmR0VmxReadSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
6729 PCPUMSELREG pSelReg)
6730{
6731 NOREF(pVCpu);
6732
6733 uint32_t u32Val = 0;
6734 int rc = VMXReadVmcs32(idxSel, &u32Val);
6735 AssertRCReturn(rc, rc);
6736 pSelReg->Sel = (uint16_t)u32Val;
6737 pSelReg->ValidSel = (uint16_t)u32Val;
6738 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6739
6740 rc = VMXReadVmcs32(idxLimit, &u32Val);
6741 AssertRCReturn(rc, rc);
6742 pSelReg->u32Limit = u32Val;
6743
6744 uint64_t u64Val = 0;
6745 rc = VMXReadVmcsGstNByIdxVal(idxBase, &u64Val);
6746 AssertRCReturn(rc, rc);
6747 pSelReg->u64Base = u64Val;
6748
6749 rc = VMXReadVmcs32(idxAccess, &u32Val);
6750 AssertRCReturn(rc, rc);
6751 pSelReg->Attr.u = u32Val;
6752
6753 /*
6754 * If VT-x marks the segment as unusable, most other bits remain undefined:
6755 * - For CS the L, D and G bits have meaning.
6756 * - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
6757 * - For the remaining data segments no bits are defined.
6758 *
6759 * The present bit and the unusable bit has been observed to be set at the
6760 * same time (the selector was supposed to be invalid as we started executing
6761 * a V8086 interrupt in ring-0).
6762 *
6763 * What should be important for the rest of the VBox code, is that the P bit is
6764 * cleared. Some of the other VBox code recognizes the unusable bit, but
6765 * AMD-V certainly don't, and REM doesn't really either. So, to be on the
6766 * safe side here, we'll strip off P and other bits we don't care about. If
6767 * any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
6768 *
6769 * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
6770 */
6771 if (pSelReg->Attr.u & X86DESCATTR_UNUSABLE)
6772 {
6773 Assert(idxSel != VMX_VMCS16_GUEST_TR_SEL); /* TR is the only selector that can never be unusable. */
6774
6775 /* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
6776 pSelReg->Attr.u &= X86DESCATTR_UNUSABLE | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
6777 | X86DESCATTR_DPL | X86DESCATTR_TYPE | X86DESCATTR_DT;
6778
6779 Log4(("hmR0VmxReadSegmentReg: Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Val, pSelReg->Attr.u));
6780#ifdef DEBUG_bird
6781 AssertMsg((u32Val & ~X86DESCATTR_P) == pSelReg->Attr.u,
6782 ("%#x: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
6783 idxSel, u32Val, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
6784#endif
6785 }
6786 return VINF_SUCCESS;
6787}
6788
6789
6790#ifdef VMX_USE_CACHED_VMCS_ACCESSES
6791# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
6792 hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
6793 VMX_VMCS_GUEST_##Sel##_BASE_CACHE_IDX, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
6794#else
6795# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
6796 hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
6797 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
6798#endif
6799
6800
6801/**
6802 * Saves the guest segment registers from the current VMCS into the guest-CPU
6803 * context.
6804 *
6805 * @returns VBox status code.
6806 * @param pVCpu The cross context virtual CPU structure.
6807 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6808 * out-of-sync. Make sure to update the required fields
6809 * before using them.
6810 *
6811 * @remarks No-long-jump zone!!!
6812 */
6813static int hmR0VmxSaveGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6814{
6815 /* Guest segment registers. */
6816 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SEGMENT_REGS))
6817 {
6818 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS));
6819 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6820 AssertRCReturn(rc, rc);
6821
6822 rc = VMXLOCAL_READ_SEG(CS, cs);
6823 rc |= VMXLOCAL_READ_SEG(SS, ss);
6824 rc |= VMXLOCAL_READ_SEG(DS, ds);
6825 rc |= VMXLOCAL_READ_SEG(ES, es);
6826 rc |= VMXLOCAL_READ_SEG(FS, fs);
6827 rc |= VMXLOCAL_READ_SEG(GS, gs);
6828 AssertRCReturn(rc, rc);
6829
6830 /* Restore segment attributes for real-on-v86 mode hack. */
6831 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6832 {
6833 pMixedCtx->cs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrCS.u;
6834 pMixedCtx->ss.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrSS.u;
6835 pMixedCtx->ds.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrDS.u;
6836 pMixedCtx->es.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrES.u;
6837 pMixedCtx->fs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrFS.u;
6838 pMixedCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrGS.u;
6839 }
6840 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SEGMENT_REGS);
6841 }
6842
6843 return VINF_SUCCESS;
6844}
6845
6846
6847/**
6848 * Saves the guest descriptor table registers and task register from the current
6849 * VMCS into the guest-CPU context.
6850 *
6851 * @returns VBox status code.
6852 * @param pVCpu The cross context virtual CPU structure.
6853 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6854 * out-of-sync. Make sure to update the required fields
6855 * before using them.
6856 *
6857 * @remarks No-long-jump zone!!!
6858 */
6859static int hmR0VmxSaveGuestTableRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6860{
6861 int rc = VINF_SUCCESS;
6862
6863 /* Guest LDTR. */
6864 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LDTR))
6865 {
6866 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR));
6867 rc = VMXLOCAL_READ_SEG(LDTR, ldtr);
6868 AssertRCReturn(rc, rc);
6869 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LDTR);
6870 }
6871
6872 /* Guest GDTR. */
6873 uint64_t u64Val = 0;
6874 uint32_t u32Val = 0;
6875 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_GDTR))
6876 {
6877 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR));
6878 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
6879 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
6880 pMixedCtx->gdtr.pGdt = u64Val;
6881 pMixedCtx->gdtr.cbGdt = u32Val;
6882 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_GDTR);
6883 }
6884
6885 /* Guest IDTR. */
6886 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_IDTR))
6887 {
6888 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR));
6889 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
6890 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
6891 pMixedCtx->idtr.pIdt = u64Val;
6892 pMixedCtx->idtr.cbIdt = u32Val;
6893 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_IDTR);
6894 }
6895
6896 /* Guest TR. */
6897 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_TR))
6898 {
6899 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR));
6900 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6901 AssertRCReturn(rc, rc);
6902
6903 /* For real-mode emulation using virtual-8086 mode we have the fake TSS (pRealModeTSS) in TR, don't save the fake one. */
6904 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6905 {
6906 rc = VMXLOCAL_READ_SEG(TR, tr);
6907 AssertRCReturn(rc, rc);
6908 }
6909 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_TR);
6910 }
6911 return rc;
6912}
6913
6914#undef VMXLOCAL_READ_SEG
6915
6916
6917/**
6918 * Saves the guest debug-register DR7 from the current VMCS into the guest-CPU
6919 * context.
6920 *
6921 * @returns VBox status code.
6922 * @param pVCpu The cross context virtual CPU structure.
6923 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6924 * out-of-sync. Make sure to update the required fields
6925 * before using them.
6926 *
6927 * @remarks No-long-jump zone!!!
6928 */
6929static int hmR0VmxSaveGuestDR7(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6930{
6931 if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_DR7))
6932 {
6933 if (!pVCpu->hm.s.fUsingHyperDR7)
6934 {
6935 /* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
6936 uint32_t u32Val;
6937 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val); AssertRCReturn(rc, rc);
6938 pMixedCtx->dr[7] = u32Val;
6939 }
6940
6941 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_DR7);
6942 }
6943 return VINF_SUCCESS;
6944}
6945
6946
6947/**
6948 * Saves the guest APIC state from the current VMCS into the guest-CPU context.
6949 *
6950 * @returns VBox status code.
6951 * @param pVCpu The cross context virtual CPU structure.
6952 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6953 * out-of-sync. Make sure to update the required fields
6954 * before using them.
6955 *
6956 * @remarks No-long-jump zone!!!
6957 */
6958static int hmR0VmxSaveGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6959{
6960 NOREF(pMixedCtx);
6961
6962 /* Updating TPR is already done in hmR0VmxPostRunGuest(). Just update the flag. */
6963 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_APIC_STATE);
6964 return VINF_SUCCESS;
6965}
6966
6967
6968/**
6969 * Saves the entire guest state from the currently active VMCS into the
6970 * guest-CPU context.
6971 *
6972 * This essentially VMREADs all guest-data.
6973 *
6974 * @returns VBox status code.
6975 * @param pVCpu The cross context virtual CPU structure.
6976 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
6977 * out-of-sync. Make sure to update the required fields
6978 * before using them.
6979 */
6980static int hmR0VmxSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6981{
6982 Assert(pVCpu);
6983 Assert(pMixedCtx);
6984
6985 if (HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL)
6986 return VINF_SUCCESS;
6987
6988 /* Though we can longjmp to ring-3 due to log-flushes here and get recalled
6989 again on the ring-3 callback path, there is no real need to. */
6990 if (VMMRZCallRing3IsEnabled(pVCpu))
6991 VMMR0LogFlushDisable(pVCpu);
6992 else
6993 Assert(VMMR0IsLogFlushDisabled(pVCpu));
6994 Log4Func(("vcpu[%RU32]\n", pVCpu->idCpu));
6995
6996 int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
6997 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestRipRspRflags failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6998
6999 rc = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
7000 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestControlRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7001
7002 rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
7003 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSegmentRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7004
7005 rc = hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
7006 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestTableRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7007
7008 rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
7009 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestDR7 failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7010
7011 rc = hmR0VmxSaveGuestSysenterMsrs(pVCpu, pMixedCtx);
7012 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSysenterMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7013
7014 rc = hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
7015 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestLazyMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7016
7017 rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
7018 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestAutoLoadStoreMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7019
7020 rc = hmR0VmxSaveGuestActivityState(pVCpu, pMixedCtx);
7021 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestActivityState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7022
7023 rc = hmR0VmxSaveGuestApicState(pVCpu, pMixedCtx);
7024 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestApicState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
7025
7026 AssertMsg(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL,
7027 ("Missed guest state bits while saving state; missing %RX32 (got %RX32, want %RX32) - check log for any previous errors!\n",
7028 HMVMX_UPDATED_GUEST_ALL ^ HMVMXCPU_GST_VALUE(pVCpu), HMVMXCPU_GST_VALUE(pVCpu), HMVMX_UPDATED_GUEST_ALL));
7029
7030 if (VMMRZCallRing3IsEnabled(pVCpu))
7031 VMMR0LogFlushEnable(pVCpu);
7032
7033 return VINF_SUCCESS;
7034}
7035
7036
7037/**
7038 * Saves basic guest registers needed for IEM instruction execution.
7039 *
7040 * @returns VBox status code (OR-able).
7041 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7042 * @param pMixedCtx Pointer to the CPU context of the guest.
7043 * @param fMemory Whether the instruction being executed operates on
7044 * memory or not. Only CR0 is synced up if clear.
7045 * @param fNeedRsp Need RSP (any instruction working on GPRs or stack).
7046 */
7047static int hmR0VmxSaveGuestRegsForIemExec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fMemory, bool fNeedRsp)
7048{
7049 /*
7050 * We assume all general purpose registers other than RSP are available.
7051 *
7052 * - RIP is a must, as it will be incremented or otherwise changed.
7053 * - RFLAGS are always required to figure the CPL.
7054 * - RSP isn't always required, however it's a GPR, so frequently required.
7055 * - SS and CS are the only segment register needed if IEM doesn't do memory
7056 * access (CPL + 16/32/64-bit mode), but we can only get all segment registers.
7057 * - CR0 is always required by IEM for the CPL, while CR3 and CR4 will only
7058 * be required for memory accesses.
7059 *
7060 * Note! Before IEM dispatches an exception, it will call us to sync in everything.
7061 */
7062 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
7063 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
7064 if (fNeedRsp)
7065 rc |= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
7066 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
7067 if (!fMemory)
7068 rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
7069 else
7070 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
7071 AssertRCReturn(rc, rc);
7072 return rc;
7073}
7074
7075
7076/**
7077 * Ensures that we've got a complete basic guest-context.
7078 *
7079 * This excludes the FPU, SSE, AVX, and similar extended state. The interface
7080 * is for the interpreter.
7081 *
7082 * @returns VBox status code.
7083 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
7084 * @param pMixedCtx Pointer to the guest-CPU context which may have data
7085 * needing to be synced in.
7086 * @thread EMT(pVCpu)
7087 */
7088VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7089{
7090 /* Note! Since this is only applicable to VT-x, the implementation is placed
7091 in the VT-x part of the sources instead of the generic stuff. */
7092 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
7093 {
7094 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
7095 /*
7096 * For now, imply that the caller might change everything too. Do this after
7097 * saving the guest state so as to not trigger assertions.
7098 */
7099 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7100 return rc;
7101 }
7102 return VINF_SUCCESS;
7103}
7104
7105
7106/**
7107 * Check per-VM and per-VCPU force flag actions that require us to go back to
7108 * ring-3 for one reason or another.
7109 *
7110 * @returns Strict VBox status code (i.e. informational status codes too)
7111 * @retval VINF_SUCCESS if we don't have any actions that require going back to
7112 * ring-3.
7113 * @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
7114 * @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
7115 * interrupts)
7116 * @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
7117 * all EMTs to be in ring-3.
7118 * @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
7119 * @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
7120 * to the EM loop.
7121 *
7122 * @param pVM The cross context VM structure.
7123 * @param pVCpu The cross context virtual CPU structure.
7124 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7125 * out-of-sync. Make sure to update the required fields
7126 * before using them.
7127 * @param fStepping Running in hmR0VmxRunGuestCodeStep().
7128 */
7129static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping)
7130{
7131 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7132
7133 /*
7134 * Anything pending? Should be more likely than not if we're doing a good job.
7135 */
7136 if ( !fStepping
7137 ? !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_MASK)
7138 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)
7139 : !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK)
7140 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
7141 return VINF_SUCCESS;
7142
7143 /* We need the control registers now, make sure the guest-CPU context is updated. */
7144 int rc3 = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
7145 AssertRCReturn(rc3, rc3);
7146
7147 /* Pending HM CR3 sync. */
7148 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
7149 {
7150 int rc2 = PGMUpdateCR3(pVCpu, pMixedCtx->cr3);
7151 AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
7152 ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
7153 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
7154 }
7155
7156 /* Pending HM PAE PDPEs. */
7157 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
7158 {
7159 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
7160 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
7161 }
7162
7163 /* Pending PGM C3 sync. */
7164 if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
7165 {
7166 VBOXSTRICTRC rcStrict2 = PGMSyncCR3(pVCpu, pMixedCtx->cr0, pMixedCtx->cr3, pMixedCtx->cr4,
7167 VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
7168 if (rcStrict2 != VINF_SUCCESS)
7169 {
7170 AssertRC(VBOXSTRICTRC_VAL(rcStrict2));
7171 Log4(("hmR0VmxCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
7172 return rcStrict2;
7173 }
7174 }
7175
7176 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
7177 if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
7178 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
7179 {
7180 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
7181 int rc2 = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
7182 Log4(("hmR0VmxCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc2));
7183 return rc2;
7184 }
7185
7186 /* Pending VM request packets, such as hardware interrupts. */
7187 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
7188 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
7189 {
7190 Log4(("hmR0VmxCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
7191 return VINF_EM_PENDING_REQUEST;
7192 }
7193
7194 /* Pending PGM pool flushes. */
7195 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
7196 {
7197 Log4(("hmR0VmxCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
7198 return VINF_PGM_POOL_FLUSH_PENDING;
7199 }
7200
7201 /* Pending DMA requests. */
7202 if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
7203 {
7204 Log4(("hmR0VmxCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
7205 return VINF_EM_RAW_TO_R3;
7206 }
7207
7208 return VINF_SUCCESS;
7209}
7210
7211
7212/**
7213 * Converts any TRPM trap into a pending HM event. This is typically used when
7214 * entering from ring-3 (not longjmp returns).
7215 *
7216 * @param pVCpu The cross context virtual CPU structure.
7217 */
7218static void hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu)
7219{
7220 Assert(TRPMHasTrap(pVCpu));
7221 Assert(!pVCpu->hm.s.Event.fPending);
7222
7223 uint8_t uVector;
7224 TRPMEVENT enmTrpmEvent;
7225 RTGCUINT uErrCode;
7226 RTGCUINTPTR GCPtrFaultAddress;
7227 uint8_t cbInstr;
7228
7229 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
7230 AssertRC(rc);
7231
7232 /* Refer Intel spec. 24.8.3 "VM-entry Controls for Event Injection" for the format of u32IntInfo. */
7233 uint32_t u32IntInfo = uVector | VMX_EXIT_INTERRUPTION_INFO_VALID;
7234 if (enmTrpmEvent == TRPM_TRAP)
7235 {
7236 switch (uVector)
7237 {
7238 case X86_XCPT_NMI:
7239 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7240 break;
7241
7242 case X86_XCPT_BP:
7243 case X86_XCPT_OF:
7244 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7245 break;
7246
7247 case X86_XCPT_PF:
7248 case X86_XCPT_DF:
7249 case X86_XCPT_TS:
7250 case X86_XCPT_NP:
7251 case X86_XCPT_SS:
7252 case X86_XCPT_GP:
7253 case X86_XCPT_AC:
7254 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7255 /* fall thru */
7256 default:
7257 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7258 break;
7259 }
7260 }
7261 else if (enmTrpmEvent == TRPM_HARDWARE_INT)
7262 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7263 else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
7264 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7265 else
7266 AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
7267
7268 rc = TRPMResetTrap(pVCpu);
7269 AssertRC(rc);
7270 Log4(("TRPM->HM event: u32IntInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
7271 u32IntInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
7272
7273 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, uErrCode, GCPtrFaultAddress);
7274}
7275
7276
7277/**
7278 * Converts the pending HM event into a TRPM trap.
7279 *
7280 * @param pVCpu The cross context virtual CPU structure.
7281 */
7282static void hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu)
7283{
7284 Assert(pVCpu->hm.s.Event.fPending);
7285
7286 uint32_t uVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7287 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo);
7288 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.u64IntInfo);
7289 uint32_t uErrorCode = pVCpu->hm.s.Event.u32ErrCode;
7290
7291 /* If a trap was already pending, we did something wrong! */
7292 Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
7293
7294 TRPMEVENT enmTrapType;
7295 switch (uVectorType)
7296 {
7297 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
7298 enmTrapType = TRPM_HARDWARE_INT;
7299 break;
7300
7301 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
7302 enmTrapType = TRPM_SOFTWARE_INT;
7303 break;
7304
7305 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
7306 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
7307 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7308 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
7309 enmTrapType = TRPM_TRAP;
7310 break;
7311
7312 default:
7313 AssertMsgFailed(("Invalid trap type %#x\n", uVectorType));
7314 enmTrapType = TRPM_32BIT_HACK;
7315 break;
7316 }
7317
7318 Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
7319
7320 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7321 AssertRC(rc);
7322
7323 if (fErrorCodeValid)
7324 TRPMSetErrorCode(pVCpu, uErrorCode);
7325
7326 if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
7327 && uVector == X86_XCPT_PF)
7328 {
7329 TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
7330 }
7331 else if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7332 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
7333 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
7334 {
7335 AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7336 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7337 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
7338 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
7339 }
7340
7341 /* Clear any pending events from the VMCS. */
7342 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc);
7343 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0); AssertRC(rc);
7344
7345 /* We're now done converting the pending event. */
7346 pVCpu->hm.s.Event.fPending = false;
7347}
7348
7349
7350/**
7351 * Does the necessary state syncing before returning to ring-3 for any reason
7352 * (longjmp, preemption, voluntary exits to ring-3) from VT-x.
7353 *
7354 * @returns VBox status code.
7355 * @param pVCpu The cross context virtual CPU structure.
7356 * @param pMixedCtx Pointer to the guest-CPU context. The data may
7357 * be out-of-sync. Make sure to update the required
7358 * fields before using them.
7359 * @param fSaveGuestState Whether to save the guest state or not.
7360 *
7361 * @remarks No-long-jmp zone!!!
7362 */
7363static int hmR0VmxLeave(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fSaveGuestState)
7364{
7365 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7366 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7367
7368 RTCPUID idCpu = RTMpCpuId();
7369 Log4Func(("HostCpuId=%u\n", idCpu));
7370
7371 /*
7372 * !!! IMPORTANT !!!
7373 * If you modify code here, check whether hmR0VmxCallRing3Callback() needs to be updated too.
7374 */
7375
7376 /* Save the guest state if necessary. */
7377 if ( fSaveGuestState
7378 && HMVMXCPU_GST_VALUE(pVCpu) != HMVMX_UPDATED_GUEST_ALL)
7379 {
7380 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
7381 AssertRCReturn(rc, rc);
7382 Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
7383 }
7384
7385 /* Restore host FPU state if necessary and resync on next R0 reentry .*/
7386 if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
7387 {
7388 /* We shouldn't reload CR0 without saving it first. */
7389 if (!fSaveGuestState)
7390 {
7391 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
7392 AssertRCReturn(rc, rc);
7393 }
7394 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7395 }
7396
7397 /* Restore host debug registers if necessary and resync on next R0 reentry. */
7398#ifdef VBOX_STRICT
7399 if (CPUMIsHyperDebugStateActive(pVCpu))
7400 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
7401#endif
7402 if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */))
7403 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
7404 Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
7405 Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
7406
7407#if HC_ARCH_BITS == 64
7408 /* Restore host-state bits that VT-x only restores partially. */
7409 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7410 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7411 {
7412 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags, idCpu));
7413 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7414 }
7415 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7416#endif
7417
7418 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7419 if (pVCpu->hm.s.vmx.fLazyMsrs)
7420 {
7421 /* We shouldn't reload the guest MSRs without saving it first. */
7422 if (!fSaveGuestState)
7423 {
7424 int rc = hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
7425 AssertRCReturn(rc, rc);
7426 }
7427 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS));
7428 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7429 Assert(!pVCpu->hm.s.vmx.fLazyMsrs);
7430 }
7431
7432 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7433 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7434
7435 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
7436 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
7437 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
7438 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
7439 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
7440 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
7441 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
7442 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7443
7444 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7445
7446 /** @todo This partially defeats the purpose of having preemption hooks.
7447 * The problem is, deregistering the hooks should be moved to a place that
7448 * lasts until the EMT is about to be destroyed not everytime while leaving HM
7449 * context.
7450 */
7451 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7452 {
7453 int rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7454 AssertRCReturn(rc, rc);
7455
7456 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7457 Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
7458 }
7459 Assert(!(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED));
7460 NOREF(idCpu);
7461
7462 return VINF_SUCCESS;
7463}
7464
7465
7466/**
7467 * Leaves the VT-x session.
7468 *
7469 * @returns VBox status code.
7470 * @param pVCpu The cross context virtual CPU structure.
7471 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7472 * out-of-sync. Make sure to update the required fields
7473 * before using them.
7474 *
7475 * @remarks No-long-jmp zone!!!
7476 */
7477DECLINLINE(int) hmR0VmxLeaveSession(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7478{
7479 HM_DISABLE_PREEMPT();
7480 HMVMX_ASSERT_CPU_SAFE();
7481 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7482 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7483
7484 /* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
7485 and done this from the VMXR0ThreadCtxCallback(). */
7486 if (!pVCpu->hm.s.fLeaveDone)
7487 {
7488 int rc2 = hmR0VmxLeave(pVCpu, pMixedCtx, true /* fSaveGuestState */);
7489 AssertRCReturnStmt(rc2, HM_RESTORE_PREEMPT(), rc2);
7490 pVCpu->hm.s.fLeaveDone = true;
7491 }
7492 Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
7493
7494 /*
7495 * !!! IMPORTANT !!!
7496 * If you modify code here, make sure to check whether hmR0VmxCallRing3Callback() needs to be updated too.
7497 */
7498
7499 /* Deregister hook now that we've left HM context before re-enabling preemption. */
7500 /** @todo Deregistering here means we need to VMCLEAR always
7501 * (longjmp/exit-to-r3) in VT-x which is not efficient. */
7502 /** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7503 VMMR0ThreadCtxHookDisable(pVCpu);
7504
7505 /* Leave HM context. This takes care of local init (term). */
7506 int rc = HMR0LeaveCpu(pVCpu);
7507
7508 HM_RESTORE_PREEMPT();
7509 return rc;
7510}
7511
7512
7513/**
7514 * Does the necessary state syncing before doing a longjmp to ring-3.
7515 *
7516 * @returns VBox status code.
7517 * @param pVCpu The cross context virtual CPU structure.
7518 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7519 * out-of-sync. Make sure to update the required fields
7520 * before using them.
7521 *
7522 * @remarks No-long-jmp zone!!!
7523 */
7524DECLINLINE(int) hmR0VmxLongJmpToRing3(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7525{
7526 return hmR0VmxLeaveSession(pVCpu, pMixedCtx);
7527}
7528
7529
7530/**
7531 * Take necessary actions before going back to ring-3.
7532 *
7533 * An action requires us to go back to ring-3. This function does the necessary
7534 * steps before we can safely return to ring-3. This is not the same as longjmps
7535 * to ring-3, this is voluntary and prepares the guest so it may continue
7536 * executing outside HM (recompiler/IEM).
7537 *
7538 * @returns VBox status code.
7539 * @param pVM The cross context VM structure.
7540 * @param pVCpu The cross context virtual CPU structure.
7541 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7542 * out-of-sync. Make sure to update the required fields
7543 * before using them.
7544 * @param rcExit The reason for exiting to ring-3. Can be
7545 * VINF_VMM_UNKNOWN_RING3_CALL.
7546 */
7547static int hmR0VmxExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, VBOXSTRICTRC rcExit)
7548{
7549 Assert(pVM);
7550 Assert(pVCpu);
7551 Assert(pMixedCtx);
7552 HMVMX_ASSERT_PREEMPT_SAFE();
7553
7554 if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
7555 {
7556 VMXGetActivatedVmcs(&pVCpu->hm.s.vmx.LastError.u64VMCSPhys);
7557 pVCpu->hm.s.vmx.LastError.u32VMCSRevision = *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs;
7558 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
7559 /* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
7560 }
7561
7562 /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
7563 VMMRZCallRing3Disable(pVCpu);
7564 Log4(("hmR0VmxExitToRing3: pVCpu=%p idCpu=%RU32 rcExit=%d\n", pVCpu, pVCpu->idCpu, VBOXSTRICTRC_VAL(rcExit)));
7565
7566 /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
7567 if (pVCpu->hm.s.Event.fPending)
7568 {
7569 hmR0VmxPendingEventToTrpmTrap(pVCpu);
7570 Assert(!pVCpu->hm.s.Event.fPending);
7571 }
7572
7573 /* Clear interrupt-window and NMI-window controls as we re-evaluate it when we return from ring-3. */
7574 hmR0VmxClearIntNmiWindowsVmcs(pVCpu);
7575
7576 /* If we're emulating an instruction, we shouldn't have any TRPM traps pending
7577 and if we're injecting an event we should have a TRPM trap pending. */
7578 AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT || TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7579#ifndef DEBUG_bird /* Triggered after firing an NMI against NT4SP1, possibly a tripple fault in progress. */
7580 AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR || !TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7581#endif
7582
7583 /* Save guest state and restore host state bits. */
7584 int rc = hmR0VmxLeaveSession(pVCpu, pMixedCtx);
7585 AssertRCReturn(rc, rc);
7586 STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7587 /* Thread-context hooks are unregistered at this point!!! */
7588
7589 /* Sync recompiler state. */
7590 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
7591 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
7592 | CPUM_CHANGED_LDTR
7593 | CPUM_CHANGED_GDTR
7594 | CPUM_CHANGED_IDTR
7595 | CPUM_CHANGED_TR
7596 | CPUM_CHANGED_HIDDEN_SEL_REGS);
7597 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
7598 if ( pVM->hm.s.fNestedPaging
7599 && CPUMIsGuestPagingEnabledEx(pMixedCtx))
7600 {
7601 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
7602 }
7603
7604 Assert(!pVCpu->hm.s.fClearTrapFlag);
7605
7606 /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
7607 if (rcExit != VINF_EM_RAW_INTERRUPT)
7608 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7609
7610 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
7611
7612 /* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
7613 VMMRZCallRing3RemoveNotification(pVCpu);
7614 VMMRZCallRing3Enable(pVCpu);
7615
7616 return rc;
7617}
7618
7619
7620/**
7621 * VMMRZCallRing3() callback wrapper which saves the guest state before we
7622 * longjump to ring-3 and possibly get preempted.
7623 *
7624 * @returns VBox status code.
7625 * @param pVCpu The cross context virtual CPU structure.
7626 * @param enmOperation The operation causing the ring-3 longjump.
7627 * @param pvUser Opaque pointer to the guest-CPU context. The data
7628 * may be out-of-sync. Make sure to update the required
7629 * fields before using them.
7630 */
7631static DECLCALLBACK(int) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
7632{
7633 if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
7634 {
7635 /*
7636 * !!! IMPORTANT !!!
7637 * If you modify code here, check whether hmR0VmxLeave() and hmR0VmxLeaveSession() needs to be updated too.
7638 * This is a stripped down version which gets out ASAP, trying to not trigger any further assertions.
7639 */
7640 VMMRZCallRing3RemoveNotification(pVCpu);
7641 VMMRZCallRing3Disable(pVCpu);
7642 RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
7643 RTThreadPreemptDisable(&PreemptState);
7644
7645 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7646 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7647
7648#if HC_ARCH_BITS == 64
7649 /* Restore host-state bits that VT-x only restores partially. */
7650 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7651 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7652 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7653 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7654#endif
7655 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7656 if (pVCpu->hm.s.vmx.fLazyMsrs)
7657 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7658
7659 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7660 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7661 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7662 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7663 {
7664 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7665 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7666 }
7667
7668 /** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7669 VMMR0ThreadCtxHookDisable(pVCpu);
7670 HMR0LeaveCpu(pVCpu);
7671 RTThreadPreemptRestore(&PreemptState);
7672 return VINF_SUCCESS;
7673 }
7674
7675 Assert(pVCpu);
7676 Assert(pvUser);
7677 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7678 HMVMX_ASSERT_PREEMPT_SAFE();
7679
7680 VMMRZCallRing3Disable(pVCpu);
7681 Assert(VMMR0IsLogFlushDisabled(pVCpu));
7682
7683 Log4(("hmR0VmxCallRing3Callback->hmR0VmxLongJmpToRing3 pVCpu=%p idCpu=%RU32 enmOperation=%d\n", pVCpu, pVCpu->idCpu,
7684 enmOperation));
7685
7686 int rc = hmR0VmxLongJmpToRing3(pVCpu, (PCPUMCTX)pvUser);
7687 AssertRCReturn(rc, rc);
7688
7689 VMMRZCallRing3Enable(pVCpu);
7690 return VINF_SUCCESS;
7691}
7692
7693
7694/**
7695 * Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
7696 * cause a VM-exit as soon as the guest is in a state to receive interrupts.
7697 *
7698 * @param pVCpu The cross context virtual CPU structure.
7699 */
7700DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
7701{
7702 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
7703 {
7704 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
7705 {
7706 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
7707 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7708 AssertRC(rc);
7709 Log4(("Setup interrupt-window exiting\n"));
7710 }
7711 } /* else we will deliver interrupts whenever the guest exits next and is in a state to receive events. */
7712}
7713
7714
7715/**
7716 * Clears the interrupt-window exiting control in the VMCS.
7717 *
7718 * @param pVCpu The cross context virtual CPU structure.
7719 */
7720DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu)
7721{
7722 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
7723 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
7724 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7725 AssertRC(rc);
7726 Log4(("Cleared interrupt-window exiting\n"));
7727}
7728
7729
7730/**
7731 * Sets the NMI-window exiting control in the VMCS which instructs VT-x to
7732 * cause a VM-exit as soon as the guest is in a state to receive NMIs.
7733 *
7734 * @param pVCpu The cross context virtual CPU structure.
7735 */
7736DECLINLINE(void) hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu)
7737{
7738 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
7739 {
7740 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
7741 {
7742 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
7743 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7744 AssertRC(rc);
7745 Log4(("Setup NMI-window exiting\n"));
7746 }
7747 } /* else we will deliver NMIs whenever we VM-exit next, even possibly nesting NMIs. Can't be helped on ancient CPUs. */
7748}
7749
7750
7751/**
7752 * Clears the NMI-window exiting control in the VMCS.
7753 *
7754 * @param pVCpu The cross context virtual CPU structure.
7755 */
7756DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu)
7757{
7758 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
7759 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
7760 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7761 AssertRC(rc);
7762 Log4(("Cleared NMI-window exiting\n"));
7763}
7764
7765
7766/**
7767 * Evaluates the event to be delivered to the guest and sets it as the pending
7768 * event.
7769 *
7770 * @returns The VT-x guest-interruptibility state.
7771 * @param pVCpu The cross context virtual CPU structure.
7772 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7773 * out-of-sync. Make sure to update the required fields
7774 * before using them.
7775 */
7776static uint32_t hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7777{
7778 /* Get the current interruptibility-state of the guest and then figure out what can be injected. */
7779 uint32_t const uIntrState = hmR0VmxGetGuestIntrState(pVCpu, pMixedCtx);
7780 bool const fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7781 bool const fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7782 bool const fBlockNmi = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI);
7783
7784 Assert(!fBlockSti || HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS));
7785 Assert(!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7786 Assert(!fBlockSti || pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7787 Assert(!TRPMHasTrap(pVCpu));
7788
7789 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
7790 APICUpdatePendingInterrupts(pVCpu);
7791
7792 /*
7793 * Toggling of interrupt force-flags here is safe since we update TRPM on premature exits
7794 * to ring-3 before executing guest code, see hmR0VmxExitToRing3(). We must NOT restore these force-flags.
7795 */
7796 /** @todo SMI. SMIs take priority over NMIs. */
7797 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
7798 {
7799 /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
7800 if ( !pVCpu->hm.s.Event.fPending
7801 && !fBlockNmi
7802 && !fBlockSti
7803 && !fBlockMovSS)
7804 {
7805 Log4(("Pending NMI vcpu[%RU32]\n", pVCpu->idCpu));
7806 uint32_t u32IntInfo = X86_XCPT_NMI | VMX_EXIT_INTERRUPTION_INFO_VALID;
7807 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7808
7809 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7810 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
7811 }
7812 else
7813 hmR0VmxSetNmiWindowExitVmcs(pVCpu);
7814 }
7815 /*
7816 * Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
7817 * a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
7818 */
7819 else if ( VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
7820 && !pVCpu->hm.s.fSingleInstruction)
7821 {
7822 Assert(!DBGFIsStepping(pVCpu));
7823 int rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
7824 AssertRC(rc);
7825 bool const fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
7826 if ( !pVCpu->hm.s.Event.fPending
7827 && !fBlockInt
7828 && !fBlockSti
7829 && !fBlockMovSS)
7830 {
7831 uint8_t u8Interrupt;
7832 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
7833 if (RT_SUCCESS(rc))
7834 {
7835 Log4(("Pending interrupt vcpu[%RU32] u8Interrupt=%#x \n", pVCpu->idCpu, u8Interrupt));
7836 uint32_t u32IntInfo = u8Interrupt | VMX_EXIT_INTERRUPTION_INFO_VALID;
7837 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7838
7839 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrfaultAddress */);
7840 }
7841 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
7842 {
7843 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
7844 hmR0VmxApicSetTprThreshold(pVCpu, u8Interrupt >> 4);
7845 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
7846
7847 /*
7848 * If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
7849 * APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
7850 * need to re-set this force-flag here.
7851 */
7852 }
7853 else
7854 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
7855 }
7856 else
7857 hmR0VmxSetIntWindowExitVmcs(pVCpu);
7858 }
7859
7860 return uIntrState;
7861}
7862
7863
7864/**
7865 * Sets a pending-debug exception to be delivered to the guest if the guest is
7866 * single-stepping in the VMCS.
7867 *
7868 * @param pVCpu The cross context virtual CPU structure.
7869 */
7870DECLINLINE(void) hmR0VmxSetPendingDebugXcptVmcs(PVMCPU pVCpu)
7871{
7872 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS)); NOREF(pVCpu);
7873 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS);
7874 AssertRC(rc);
7875}
7876
7877
7878/**
7879 * Injects any pending events into the guest if the guest is in a state to
7880 * receive them.
7881 *
7882 * @returns Strict VBox status code (i.e. informational status codes too).
7883 * @param pVCpu The cross context virtual CPU structure.
7884 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7885 * out-of-sync. Make sure to update the required fields
7886 * before using them.
7887 * @param uIntrState The VT-x guest-interruptibility state.
7888 * @param fStepping Running in hmR0VmxRunGuestCodeStep() and we should
7889 * return VINF_EM_DBG_STEPPED if the event was
7890 * dispatched directly.
7891 */
7892static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t uIntrState, bool fStepping)
7893{
7894 HMVMX_ASSERT_PREEMPT_SAFE();
7895 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7896
7897 bool fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7898 bool fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7899
7900 Assert(!fBlockSti || HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS));
7901 Assert(!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7902 Assert(!fBlockSti || pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7903 Assert(!TRPMHasTrap(pVCpu));
7904
7905 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
7906 if (pVCpu->hm.s.Event.fPending)
7907 {
7908 /*
7909 * Do -not- clear any interrupt-window exiting control here. We might have an interrupt
7910 * pending even while injecting an event and in this case, we want a VM-exit as soon as
7911 * the guest is ready for the next interrupt, see @bugref{6208#c45}.
7912 *
7913 * See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
7914 */
7915 uint32_t const uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7916#ifdef VBOX_STRICT
7917 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
7918 {
7919 bool const fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
7920 Assert(!fBlockInt);
7921 Assert(!fBlockSti);
7922 Assert(!fBlockMovSS);
7923 }
7924 else if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
7925 {
7926 bool const fBlockNmi = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI);
7927 Assert(!fBlockSti);
7928 Assert(!fBlockMovSS);
7929 Assert(!fBlockNmi);
7930 }
7931#endif
7932 Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#x\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
7933 (uint8_t)uIntType));
7934 rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.cbInstr,
7935 pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress,
7936 fStepping, &uIntrState);
7937 AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7938
7939 /* Update the interruptibility-state as it could have been changed by
7940 hmR0VmxInjectEventVmcs() (e.g. real-on-v86 guest injecting software interrupts) */
7941 fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7942 fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7943
7944 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
7945 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
7946 else
7947 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
7948 }
7949
7950 /* Deliver pending debug exception if the guest is single-stepping. Evaluate and set the BS bit. */
7951 if ( fBlockSti
7952 || fBlockMovSS)
7953 {
7954 if (!pVCpu->hm.s.fSingleInstruction)
7955 {
7956 /*
7957 * The pending-debug exceptions field is cleared on all VM-exits except VMX_EXIT_TPR_BELOW_THRESHOLD,
7958 * VMX_EXIT_MTF, VMX_EXIT_APIC_WRITE and VMX_EXIT_VIRTUALIZED_EOI.
7959 * See Intel spec. 27.3.4 "Saving Non-Register State".
7960 */
7961 Assert(!DBGFIsStepping(pVCpu));
7962 int rc2 = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
7963 AssertRCReturn(rc2, rc2);
7964 if (pMixedCtx->eflags.Bits.u1TF)
7965 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
7966 }
7967 else if (pMixedCtx->eflags.Bits.u1TF)
7968 {
7969 /*
7970 * We are single-stepping in the hypervisor debugger using EFLAGS.TF. Clear interrupt inhibition as setting the
7971 * BS bit would mean delivering a #DB to the guest upon VM-entry when it shouldn't be.
7972 */
7973 Assert(!(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG));
7974 uIntrState = 0;
7975 }
7976 }
7977
7978 /*
7979 * There's no need to clear the VM-entry interruption-information field here if we're not injecting anything.
7980 * VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7981 */
7982 int rc2 = hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
7983 AssertRC(rc2);
7984
7985 Assert(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping));
7986 NOREF(fBlockMovSS); NOREF(fBlockSti);
7987 return rcStrict;
7988}
7989
7990
7991/**
7992 * Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
7993 *
7994 * @param pVCpu The cross context virtual CPU structure.
7995 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
7996 * out-of-sync. Make sure to update the required fields
7997 * before using them.
7998 */
7999DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8000{
8001 NOREF(pMixedCtx);
8002 uint32_t u32IntInfo = X86_XCPT_UD | VMX_EXIT_INTERRUPTION_INFO_VALID;
8003 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
8004}
8005
8006
8007/**
8008 * Injects a double-fault (\#DF) exception into the VM.
8009 *
8010 * @returns Strict VBox status code (i.e. informational status codes too).
8011 * @param pVCpu The cross context virtual CPU structure.
8012 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8013 * out-of-sync. Make sure to update the required fields
8014 * before using them.
8015 * @param fStepping Whether we're running in hmR0VmxRunGuestCodeStep()
8016 * and should return VINF_EM_DBG_STEPPED if the event
8017 * is injected directly (register modified by us, not
8018 * by hardware on VM-entry).
8019 * @param puIntrState Pointer to the current guest interruptibility-state.
8020 * This interruptibility-state will be updated if
8021 * necessary. This cannot not be NULL.
8022 */
8023DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping, uint32_t *puIntrState)
8024{
8025 uint32_t u32IntInfo = X86_XCPT_DF | VMX_EXIT_INTERRUPTION_INFO_VALID;
8026 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
8027 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
8028 return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */,
8029 fStepping, puIntrState);
8030}
8031
8032
8033/**
8034 * Sets a debug (\#DB) exception as pending-for-injection into the VM.
8035 *
8036 * @param pVCpu The cross context virtual CPU structure.
8037 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8038 * out-of-sync. Make sure to update the required fields
8039 * before using them.
8040 */
8041DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8042{
8043 NOREF(pMixedCtx);
8044 uint32_t u32IntInfo = X86_XCPT_DB | VMX_EXIT_INTERRUPTION_INFO_VALID;
8045 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
8046 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
8047}
8048
8049
8050/**
8051 * Sets an overflow (\#OF) exception as pending-for-injection into the VM.
8052 *
8053 * @param pVCpu The cross context virtual CPU structure.
8054 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8055 * out-of-sync. Make sure to update the required fields
8056 * before using them.
8057 * @param cbInstr The value of RIP that is to be pushed on the guest
8058 * stack.
8059 */
8060DECLINLINE(void) hmR0VmxSetPendingXcptOF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr)
8061{
8062 NOREF(pMixedCtx);
8063 uint32_t u32IntInfo = X86_XCPT_OF | VMX_EXIT_INTERRUPTION_INFO_VALID;
8064 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
8065 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
8066}
8067
8068
8069/**
8070 * Injects a general-protection (\#GP) fault into the VM.
8071 *
8072 * @returns Strict VBox status code (i.e. informational status codes too).
8073 * @param pVCpu The cross context virtual CPU structure.
8074 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8075 * out-of-sync. Make sure to update the required fields
8076 * before using them.
8077 * @param fErrorCodeValid Whether the error code is valid (depends on the CPU
8078 * mode, i.e. in real-mode it's not valid).
8079 * @param u32ErrorCode The error code associated with the \#GP.
8080 * @param fStepping Whether we're running in
8081 * hmR0VmxRunGuestCodeStep() and should return
8082 * VINF_EM_DBG_STEPPED if the event is injected
8083 * directly (register modified by us, not by
8084 * hardware on VM-entry).
8085 * @param puIntrState Pointer to the current guest interruptibility-state.
8086 * This interruptibility-state will be updated if
8087 * necessary. This cannot not be NULL.
8088 */
8089DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fErrorCodeValid, uint32_t u32ErrorCode,
8090 bool fStepping, uint32_t *puIntrState)
8091{
8092 uint32_t u32IntInfo = X86_XCPT_GP | VMX_EXIT_INTERRUPTION_INFO_VALID;
8093 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
8094 if (fErrorCodeValid)
8095 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
8096 return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */,
8097 fStepping, puIntrState);
8098}
8099
8100
8101#if 0 /* unused */
8102/**
8103 * Sets a general-protection (\#GP) exception as pending-for-injection into the
8104 * VM.
8105 *
8106 * @param pVCpu The cross context virtual CPU structure.
8107 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8108 * out-of-sync. Make sure to update the required fields
8109 * before using them.
8110 * @param u32ErrorCode The error code associated with the \#GP.
8111 */
8112DECLINLINE(void) hmR0VmxSetPendingXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t u32ErrorCode)
8113{
8114 NOREF(pMixedCtx);
8115 uint32_t u32IntInfo = X86_XCPT_GP | VMX_EXIT_INTERRUPTION_INFO_VALID;
8116 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
8117 u32IntInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
8118 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */);
8119}
8120#endif /* unused */
8121
8122
8123/**
8124 * Sets a software interrupt (INTn) as pending-for-injection into the VM.
8125 *
8126 * @param pVCpu The cross context virtual CPU structure.
8127 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8128 * out-of-sync. Make sure to update the required fields
8129 * before using them.
8130 * @param uVector The software interrupt vector number.
8131 * @param cbInstr The value of RIP that is to be pushed on the guest
8132 * stack.
8133 */
8134DECLINLINE(void) hmR0VmxSetPendingIntN(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint16_t uVector, uint32_t cbInstr)
8135{
8136 NOREF(pMixedCtx);
8137 uint32_t u32IntInfo = uVector | VMX_EXIT_INTERRUPTION_INFO_VALID;
8138 if ( uVector == X86_XCPT_BP
8139 || uVector == X86_XCPT_OF)
8140 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
8141 else
8142 u32IntInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
8143 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
8144}
8145
8146
8147/**
8148 * Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
8149 * stack.
8150 *
8151 * @returns Strict VBox status code (i.e. informational status codes too).
8152 * @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
8153 * @param pVM The cross context VM structure.
8154 * @param pMixedCtx Pointer to the guest-CPU context.
8155 * @param uValue The value to push to the guest stack.
8156 */
8157DECLINLINE(VBOXSTRICTRC) hmR0VmxRealModeGuestStackPush(PVM pVM, PCPUMCTX pMixedCtx, uint16_t uValue)
8158{
8159 /*
8160 * The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
8161 * virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
8162 * See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
8163 */
8164 if (pMixedCtx->sp == 1)
8165 return VINF_EM_RESET;
8166 pMixedCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
8167 int rc = PGMPhysSimpleWriteGCPhys(pVM, pMixedCtx->ss.u64Base + pMixedCtx->sp, &uValue, sizeof(uint16_t));
8168 AssertRC(rc);
8169 return rc;
8170}
8171
8172
8173/**
8174 * Injects an event into the guest upon VM-entry by updating the relevant fields
8175 * in the VM-entry area in the VMCS.
8176 *
8177 * @returns Strict VBox status code (i.e. informational status codes too).
8178 * @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
8179 * @retval VINF_EM_RESET if event injection resulted in a triple-fault.
8180 *
8181 * @param pVCpu The cross context virtual CPU structure.
8182 * @param pMixedCtx Pointer to the guest-CPU context. The data may
8183 * be out-of-sync. Make sure to update the required
8184 * fields before using them.
8185 * @param u64IntInfo The VM-entry interruption-information field.
8186 * @param cbInstr The VM-entry instruction length in bytes (for
8187 * software interrupts, exceptions and privileged
8188 * software exceptions).
8189 * @param u32ErrCode The VM-entry exception error code.
8190 * @param GCPtrFaultAddress The page-fault address for \#PF exceptions.
8191 * @param puIntrState Pointer to the current guest interruptibility-state.
8192 * This interruptibility-state will be updated if
8193 * necessary. This cannot not be NULL.
8194 * @param fStepping Whether we're running in
8195 * hmR0VmxRunGuestCodeStep() and should return
8196 * VINF_EM_DBG_STEPPED if the event is injected
8197 * directly (register modified by us, not by
8198 * hardware on VM-entry).
8199 *
8200 * @remarks Requires CR0!
8201 */
8202static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr,
8203 uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress, bool fStepping,
8204 uint32_t *puIntrState)
8205{
8206 /* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
8207 AssertMsg(u64IntInfo >> 32 == 0, ("%#RX64\n", u64IntInfo));
8208 Assert(puIntrState);
8209 uint32_t u32IntInfo = (uint32_t)u64IntInfo;
8210
8211 uint32_t const uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(u32IntInfo);
8212 uint32_t const uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntInfo);
8213
8214#ifdef VBOX_STRICT
8215 /* Validate the error-code-valid bit for hardware exceptions. */
8216 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT)
8217 {
8218 switch (uVector)
8219 {
8220 case X86_XCPT_PF:
8221 case X86_XCPT_DF:
8222 case X86_XCPT_TS:
8223 case X86_XCPT_NP:
8224 case X86_XCPT_SS:
8225 case X86_XCPT_GP:
8226 case X86_XCPT_AC:
8227 AssertMsg(VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntInfo),
8228 ("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
8229 /* fall thru */
8230 default:
8231 break;
8232 }
8233 }
8234#endif
8235
8236 /* Cannot inject an NMI when block-by-MOV SS is in effect. */
8237 Assert( uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
8238 || !(*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS));
8239
8240 STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
8241
8242 /* We require CR0 to check if the guest is in real-mode. */
8243 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
8244 AssertRCReturn(rc, rc);
8245
8246 /*
8247 * Hardware interrupts & exceptions cannot be delivered through the software interrupt redirection bitmap to the real
8248 * mode task in virtual-8086 mode. We must jump to the interrupt handler in the (real-mode) guest.
8249 * See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode" for interrupt & exception classes.
8250 * See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
8251 */
8252 if (CPUMIsGuestInRealModeEx(pMixedCtx))
8253 {
8254 PVM pVM = pVCpu->CTX_SUFF(pVM);
8255 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
8256 {
8257 Assert(PDMVmmDevHeapIsEnabled(pVM));
8258 Assert(pVM->hm.s.vmx.pRealModeTSS);
8259
8260 /* We require RIP, RSP, RFLAGS, CS, IDTR. Save the required ones from the VMCS. */
8261 rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
8262 rc |= hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
8263 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
8264 AssertRCReturn(rc, rc);
8265 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP));
8266
8267 /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
8268 size_t const cbIdtEntry = sizeof(X86IDTR16);
8269 if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pMixedCtx->idtr.cbIdt)
8270 {
8271 /* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
8272 if (uVector == X86_XCPT_DF)
8273 return VINF_EM_RESET;
8274
8275 /* If we're injecting a #GP with no valid IDT entry, inject a double-fault. */
8276 if (uVector == X86_XCPT_GP)
8277 return hmR0VmxInjectXcptDF(pVCpu, pMixedCtx, fStepping, puIntrState);
8278
8279 /* If we're injecting an interrupt/exception with no valid IDT entry, inject a general-protection fault. */
8280 /* No error codes for exceptions in real-mode. See Intel spec. 20.1.4 "Interrupt and Exception Handling" */
8281 return hmR0VmxInjectXcptGP(pVCpu, pMixedCtx, false /* fErrCodeValid */, 0 /* u32ErrCode */,
8282 fStepping, puIntrState);
8283 }
8284
8285 /* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
8286 uint16_t uGuestIp = pMixedCtx->ip;
8287 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT)
8288 {
8289 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
8290 /* #BP and #OF are both benign traps, we need to resume the next instruction. */
8291 uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
8292 }
8293 else if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT)
8294 uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
8295
8296 /* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
8297 X86IDTR16 IdtEntry;
8298 RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pMixedCtx->idtr.pIdt + uVector * cbIdtEntry;
8299 rc = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
8300 AssertRCReturn(rc, rc);
8301
8302 /* Construct the stack frame for the interrupt/exception handler. */
8303 VBOXSTRICTRC rcStrict;
8304 rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->eflags.u32);
8305 if (rcStrict == VINF_SUCCESS)
8306 rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->cs.Sel);
8307 if (rcStrict == VINF_SUCCESS)
8308 rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, uGuestIp);
8309
8310 /* Clear the required eflag bits and jump to the interrupt/exception handler. */
8311 if (rcStrict == VINF_SUCCESS)
8312 {
8313 pMixedCtx->eflags.u32 &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
8314 pMixedCtx->rip = IdtEntry.offSel;
8315 pMixedCtx->cs.Sel = IdtEntry.uSel;
8316 pMixedCtx->cs.ValidSel = IdtEntry.uSel;
8317 pMixedCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
8318 if ( uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
8319 && uVector == X86_XCPT_PF)
8320 pMixedCtx->cr2 = GCPtrFaultAddress;
8321
8322 /* If any other guest-state bits are changed here, make sure to update
8323 hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
8324 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
8325 | HM_CHANGED_GUEST_RIP
8326 | HM_CHANGED_GUEST_RFLAGS
8327 | HM_CHANGED_GUEST_RSP);
8328
8329 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
8330 if (*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
8331 {
8332 Assert( uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
8333 && uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
8334 Log4(("Clearing inhibition due to STI.\n"));
8335 *puIntrState &= ~VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
8336 }
8337 Log4(("Injecting real-mode: u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x Eflags=%#x CS:EIP=%04x:%04x\n",
8338 u32IntInfo, u32ErrCode, cbInstr, pMixedCtx->eflags.u, pMixedCtx->cs.Sel, pMixedCtx->eip));
8339
8340 /* The event has been truly dispatched. Mark it as no longer pending so we don't attempt to 'undo'
8341 it, if we are returning to ring-3 before executing guest code. */
8342 pVCpu->hm.s.Event.fPending = false;
8343
8344 /* Make hmR0VmxPreRunGuest return if we're stepping since we've changed cs:rip. */
8345 if (fStepping)
8346 rcStrict = VINF_EM_DBG_STEPPED;
8347 }
8348 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8349 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8350 return rcStrict;
8351 }
8352
8353 /*
8354 * For unrestricted execution enabled CPUs running real-mode guests, we must not set the deliver-error-code bit.
8355 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
8356 */
8357 u32IntInfo &= ~VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
8358 }
8359
8360 /* Validate. */
8361 Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(u32IntInfo)); /* Bit 31 (Valid bit) must be set by caller. */
8362 Assert(!VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(u32IntInfo)); /* Bit 12 MBZ. */
8363 Assert(!(u32IntInfo & 0x7ffff000)); /* Bits 30:12 MBZ. */
8364
8365 /* Inject. */
8366 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
8367 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntInfo))
8368 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
8369 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
8370
8371 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
8372 && uVector == X86_XCPT_PF)
8373 pMixedCtx->cr2 = GCPtrFaultAddress;
8374
8375 Log4(("Injecting vcpu[%RU32] u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x pMixedCtx->uCR2=%#RX64\n", pVCpu->idCpu,
8376 u32IntInfo, u32ErrCode, cbInstr, pMixedCtx->cr2));
8377
8378 AssertRCReturn(rc, rc);
8379 return VINF_SUCCESS;
8380}
8381
8382
8383/**
8384 * Clears the interrupt-window exiting control in the VMCS and if necessary
8385 * clears the current event in the VMCS as well.
8386 *
8387 * @returns VBox status code.
8388 * @param pVCpu The cross context virtual CPU structure.
8389 *
8390 * @remarks Use this function only to clear events that have not yet been
8391 * delivered to the guest but are injected in the VMCS!
8392 * @remarks No-long-jump zone!!!
8393 */
8394static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu)
8395{
8396 Log4Func(("vcpu[%d]\n", pVCpu->idCpu));
8397
8398 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT)
8399 hmR0VmxClearIntWindowExitVmcs(pVCpu);
8400
8401 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)
8402 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
8403}
8404
8405
8406/**
8407 * Enters the VT-x session.
8408 *
8409 * @returns VBox status code.
8410 * @param pVM The cross context VM structure.
8411 * @param pVCpu The cross context virtual CPU structure.
8412 * @param pCpu Pointer to the CPU info struct.
8413 */
8414VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
8415{
8416 AssertPtr(pVM);
8417 AssertPtr(pVCpu);
8418 Assert(pVM->hm.s.vmx.fSupported);
8419 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8420 NOREF(pCpu); NOREF(pVM);
8421
8422 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8423 Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
8424
8425#ifdef VBOX_STRICT
8426 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
8427 RTCCUINTREG uHostCR4 = ASMGetCR4();
8428 if (!(uHostCR4 & X86_CR4_VMXE))
8429 {
8430 LogRel(("VMXR0Enter: X86_CR4_VMXE bit in CR4 is not set!\n"));
8431 return VERR_VMX_X86_CR4_VMXE_CLEARED;
8432 }
8433#endif
8434
8435 /*
8436 * Load the VCPU's VMCS as the current (and active) one.
8437 */
8438 Assert(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR);
8439 int rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8440 if (RT_FAILURE(rc))
8441 return rc;
8442
8443 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8444 pVCpu->hm.s.fLeaveDone = false;
8445 Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8446
8447 return VINF_SUCCESS;
8448}
8449
8450
8451/**
8452 * The thread-context callback (only on platforms which support it).
8453 *
8454 * @param enmEvent The thread-context event.
8455 * @param pVCpu The cross context virtual CPU structure.
8456 * @param fGlobalInit Whether global VT-x/AMD-V init. was used.
8457 * @thread EMT(pVCpu)
8458 */
8459VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
8460{
8461 NOREF(fGlobalInit);
8462
8463 switch (enmEvent)
8464 {
8465 case RTTHREADCTXEVENT_OUT:
8466 {
8467 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8468 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8469 VMCPU_ASSERT_EMT(pVCpu);
8470
8471 PCPUMCTX pMixedCtx = CPUMQueryGuestCtxPtr(pVCpu);
8472
8473 /* No longjmps (logger flushes, locks) in this fragile context. */
8474 VMMRZCallRing3Disable(pVCpu);
8475 Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
8476
8477 /*
8478 * Restore host-state (FPU, debug etc.)
8479 */
8480 if (!pVCpu->hm.s.fLeaveDone)
8481 {
8482 /* Do -not- save guest-state here as we might already be in the middle of saving it (esp. bad if we are
8483 holding the PGM lock while saving the guest state (see hmR0VmxSaveGuestControlRegs()). */
8484 hmR0VmxLeave(pVCpu, pMixedCtx, false /* fSaveGuestState */);
8485 pVCpu->hm.s.fLeaveDone = true;
8486 }
8487
8488 /* Leave HM context, takes care of local init (term). */
8489 int rc = HMR0LeaveCpu(pVCpu);
8490 AssertRC(rc); NOREF(rc);
8491
8492 /* Restore longjmp state. */
8493 VMMRZCallRing3Enable(pVCpu);
8494 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
8495 break;
8496 }
8497
8498 case RTTHREADCTXEVENT_IN:
8499 {
8500 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8501 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8502 VMCPU_ASSERT_EMT(pVCpu);
8503
8504 /* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
8505 VMMRZCallRing3Disable(pVCpu);
8506 Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
8507
8508 /* Initialize the bare minimum state required for HM. This takes care of
8509 initializing VT-x if necessary (onlined CPUs, local init etc.) */
8510 int rc = HMR0EnterCpu(pVCpu);
8511 AssertRC(rc);
8512 Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
8513
8514 /* Load the active VMCS as the current one. */
8515 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR)
8516 {
8517 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8518 AssertRC(rc); NOREF(rc);
8519 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8520 Log4Func(("Resumed: Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8521 }
8522 pVCpu->hm.s.fLeaveDone = false;
8523
8524 /* Restore longjmp state. */
8525 VMMRZCallRing3Enable(pVCpu);
8526 break;
8527 }
8528
8529 default:
8530 break;
8531 }
8532}
8533
8534
8535/**
8536 * Saves the host state in the VMCS host-state.
8537 * Sets up the VM-exit MSR-load area.
8538 *
8539 * The CPU state will be loaded from these fields on every successful VM-exit.
8540 *
8541 * @returns VBox status code.
8542 * @param pVM The cross context VM structure.
8543 * @param pVCpu The cross context virtual CPU structure.
8544 *
8545 * @remarks No-long-jump zone!!!
8546 */
8547static int hmR0VmxSaveHostState(PVM pVM, PVMCPU pVCpu)
8548{
8549 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8550
8551 int rc = VINF_SUCCESS;
8552 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
8553 {
8554 rc = hmR0VmxSaveHostControlRegs(pVM, pVCpu);
8555 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostControlRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8556
8557 rc = hmR0VmxSaveHostSegmentRegs(pVM, pVCpu);
8558 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostSegmentRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8559
8560 rc = hmR0VmxSaveHostMsrs(pVM, pVCpu);
8561 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostMsrs failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8562
8563 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
8564 }
8565 return rc;
8566}
8567
8568
8569/**
8570 * Saves the host state in the VMCS host-state.
8571 *
8572 * @returns VBox status code.
8573 * @param pVM The cross context VM structure.
8574 * @param pVCpu The cross context virtual CPU structure.
8575 *
8576 * @remarks No-long-jump zone!!!
8577 */
8578VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
8579{
8580 AssertPtr(pVM);
8581 AssertPtr(pVCpu);
8582
8583 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8584
8585 /* Save the host state here while entering HM context. When thread-context hooks are used, we might get preempted
8586 and have to resave the host state but most of the time we won't be, so do it here before we disable interrupts. */
8587 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8588 return hmR0VmxSaveHostState(pVM, pVCpu);
8589}
8590
8591
8592/**
8593 * Loads the guest state into the VMCS guest-state area.
8594 *
8595 * The will typically be done before VM-entry when the guest-CPU state and the
8596 * VMCS state may potentially be out of sync.
8597 *
8598 * Sets up the VM-entry MSR-load and VM-exit MSR-store areas. Sets up the
8599 * VM-entry controls.
8600 * Sets up the appropriate VMX non-root function to execute guest code based on
8601 * the guest CPU mode.
8602 *
8603 * @returns VBox strict status code.
8604 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8605 * without unrestricted guest access and the VMMDev is not presently
8606 * mapped (e.g. EFI32).
8607 *
8608 * @param pVM The cross context VM structure.
8609 * @param pVCpu The cross context virtual CPU structure.
8610 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8611 * out-of-sync. Make sure to update the required fields
8612 * before using them.
8613 *
8614 * @remarks No-long-jump zone!!!
8615 */
8616static VBOXSTRICTRC hmR0VmxLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8617{
8618 AssertPtr(pVM);
8619 AssertPtr(pVCpu);
8620 AssertPtr(pMixedCtx);
8621 HMVMX_ASSERT_PREEMPT_SAFE();
8622
8623 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8624
8625 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
8626
8627 /* Determine real-on-v86 mode. */
8628 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
8629 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
8630 && CPUMIsGuestInRealModeEx(pMixedCtx))
8631 {
8632 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
8633 }
8634
8635 /*
8636 * Load the guest-state into the VMCS.
8637 * Any ordering dependency among the sub-functions below must be explicitly stated using comments.
8638 * Ideally, assert that the cross-dependent bits are up-to-date at the point of using it.
8639 */
8640 int rc = hmR0VmxSetupVMRunHandler(pVCpu, pMixedCtx);
8641 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8642
8643 /* This needs to be done after hmR0VmxSetupVMRunHandler() as changing pfnStartVM may require VM-entry control updates. */
8644 rc = hmR0VmxLoadGuestEntryCtls(pVCpu, pMixedCtx);
8645 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestEntryCtls! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8646
8647 /* This needs to be done after hmR0VmxSetupVMRunHandler() as changing pfnStartVM may require VM-exit control updates. */
8648 rc = hmR0VmxLoadGuestExitCtls(pVCpu, pMixedCtx);
8649 AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupExitCtls failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8650
8651 rc = hmR0VmxLoadGuestActivityState(pVCpu, pMixedCtx);
8652 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestActivityState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8653
8654 VBOXSTRICTRC rcStrict = hmR0VmxLoadGuestCR3AndCR4(pVCpu, pMixedCtx);
8655 if (rcStrict == VINF_SUCCESS)
8656 { /* likely */ }
8657 else
8658 {
8659 Assert(rcStrict == VINF_EM_RESCHEDULE_REM || RT_FAILURE_NP(rcStrict));
8660 return rcStrict;
8661 }
8662
8663 /* Assumes pMixedCtx->cr0 is up-to-date (strict builds require CR0 for segment register validation checks). */
8664 rc = hmR0VmxLoadGuestSegmentRegs(pVCpu, pMixedCtx);
8665 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestSegmentRegs: rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8666
8667 /* This needs to be done after hmR0VmxLoadGuestEntryCtls() and hmR0VmxLoadGuestExitCtls() as it may alter controls if we
8668 determine we don't have to swap EFER after all. */
8669 rc = hmR0VmxLoadGuestMsrs(pVCpu, pMixedCtx);
8670 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestMsrs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8671
8672 rc = hmR0VmxLoadGuestApicState(pVCpu, pMixedCtx);
8673 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8674
8675 rc = hmR0VmxLoadGuestXcptIntercepts(pVCpu, pMixedCtx);
8676 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8677
8678 /*
8679 * Loading Rflags here is fine, even though Rflags.TF might depend on guest debug state (which is not loaded here).
8680 * It is re-evaluated and updated if necessary in hmR0VmxLoadSharedState().
8681 */
8682 rc = hmR0VmxLoadGuestRipRspRflags(pVCpu, pMixedCtx);
8683 AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestRipRspRflags! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8684
8685 /* Clear any unused and reserved bits. */
8686 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
8687
8688 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
8689 return rc;
8690}
8691
8692
8693/**
8694 * Loads the state shared between the host and guest into the VMCS.
8695 *
8696 * @param pVM The cross context VM structure.
8697 * @param pVCpu The cross context virtual CPU structure.
8698 * @param pCtx Pointer to the guest-CPU context.
8699 *
8700 * @remarks No-long-jump zone!!!
8701 */
8702static void hmR0VmxLoadSharedState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
8703{
8704 NOREF(pVM);
8705
8706 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8707 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8708
8709 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
8710 {
8711 int rc = hmR0VmxLoadSharedCR0(pVCpu, pCtx);
8712 AssertRC(rc);
8713 }
8714
8715 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
8716 {
8717 int rc = hmR0VmxLoadSharedDebugState(pVCpu, pCtx);
8718 AssertRC(rc);
8719
8720 /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
8721 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
8722 {
8723 rc = hmR0VmxLoadGuestRflags(pVCpu, pCtx);
8724 AssertRC(rc);
8725 }
8726 }
8727
8728 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS))
8729 {
8730 hmR0VmxLazyLoadGuestMsrs(pVCpu, pCtx);
8731 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
8732 }
8733
8734 /* Loading CR0, debug state might have changed intercepts, update VMCS. */
8735 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
8736 {
8737 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_AC));
8738 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
8739 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
8740 AssertRC(rc);
8741 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
8742 }
8743
8744 AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
8745 ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8746}
8747
8748
8749/**
8750 * Worker for loading the guest-state bits in the inner VT-x execution loop.
8751 *
8752 * @returns Strict VBox status code (i.e. informational status codes too).
8753 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8754 * without unrestricted guest access and the VMMDev is not presently
8755 * mapped (e.g. EFI32).
8756 *
8757 * @param pVM The cross context VM structure.
8758 * @param pVCpu The cross context virtual CPU structure.
8759 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8760 * out-of-sync. Make sure to update the required fields
8761 * before using them.
8762 *
8763 * @remarks No-long-jump zone!!!
8764 */
8765static VBOXSTRICTRC hmR0VmxLoadGuestStateOptimal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8766{
8767 HMVMX_ASSERT_PREEMPT_SAFE();
8768 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8769 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8770
8771 Log5(("LoadFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8772#ifdef HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
8773 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
8774#endif
8775
8776 /*
8777 * RIP is what changes the most often and hence if it's the only bit needing to be
8778 * updated, we shall handle it early for performance reasons.
8779 */
8780 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
8781 if (HMCPU_CF_IS_SET_ONLY(pVCpu, HM_CHANGED_GUEST_RIP))
8782 {
8783 rcStrict = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
8784 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8785 { /* likely */}
8786 else
8787 {
8788 AssertMsgFailedReturn(("hmR0VmxLoadGuestStateOptimal: hmR0VmxLoadGuestRip failed! rc=%Rrc\n",
8789 VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
8790 }
8791 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadMinimal);
8792 }
8793 else if (HMCPU_CF_VALUE(pVCpu))
8794 {
8795 rcStrict = hmR0VmxLoadGuestState(pVM, pVCpu, pMixedCtx);
8796 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8797 { /* likely */}
8798 else
8799 {
8800 AssertMsg(rcStrict == VINF_EM_RESCHEDULE_REM,
8801 ("hmR0VmxLoadGuestStateOptimal: hmR0VmxLoadGuestState failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8802 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8803 return rcStrict;
8804 }
8805 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
8806 }
8807
8808 /* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
8809 AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
8810 || HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE),
8811 ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8812 return rcStrict;
8813}
8814
8815
8816/**
8817 * Does the preparations before executing guest code in VT-x.
8818 *
8819 * This may cause longjmps to ring-3 and may even result in rescheduling to the
8820 * recompiler/IEM. We must be cautious what we do here regarding committing
8821 * guest-state information into the VMCS assuming we assuredly execute the
8822 * guest in VT-x mode.
8823 *
8824 * If we fall back to the recompiler/IEM after updating the VMCS and clearing
8825 * the common-state (TRPM/forceflags), we must undo those changes so that the
8826 * recompiler/IEM can (and should) use them when it resumes guest execution.
8827 * Otherwise such operations must be done when we can no longer exit to ring-3.
8828 *
8829 * @returns Strict VBox status code (i.e. informational status codes too).
8830 * @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
8831 * have been disabled.
8832 * @retval VINF_EM_RESET if a triple-fault occurs while injecting a
8833 * double-fault into the guest.
8834 * @retval VINF_EM_DBG_STEPPED if @a fStepping is true and an event was
8835 * dispatched directly.
8836 * @retval VINF_* scheduling changes, we have to go back to ring-3.
8837 *
8838 * @param pVM The cross context VM structure.
8839 * @param pVCpu The cross context virtual CPU structure.
8840 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8841 * out-of-sync. Make sure to update the required fields
8842 * before using them.
8843 * @param pVmxTransient Pointer to the VMX transient structure.
8844 * @param fStepping Set if called from hmR0VmxRunGuestCodeStep(). Makes
8845 * us ignore some of the reasons for returning to
8846 * ring-3, and return VINF_EM_DBG_STEPPED if event
8847 * dispatching took place.
8848 */
8849static VBOXSTRICTRC hmR0VmxPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, bool fStepping)
8850{
8851 Assert(VMMRZCallRing3IsEnabled(pVCpu));
8852
8853#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
8854 PGMRZDynMapFlushAutoSet(pVCpu);
8855#endif
8856
8857 /* Check force flag actions that might require us to go back to ring-3. */
8858 VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVM, pVCpu, pMixedCtx, fStepping);
8859 if (rcStrict == VINF_SUCCESS)
8860 { /* FFs doesn't get set all the time. */ }
8861 else
8862 return rcStrict;
8863
8864#ifndef IEM_VERIFICATION_MODE_FULL
8865 /*
8866 * Setup the virtualized-APIC accesses.
8867 *
8868 * Note! This can cause a longjumps to R3 due to the acquisition of the PGM lock
8869 * in both PGMHandlerPhysicalReset() and IOMMMIOMapMMIOHCPage(), see @bugref{8721}.
8870 *
8871 * This is the reason we do it here and not in hmR0VmxLoadGuestState().
8872 */
8873 if ( !pVCpu->hm.s.vmx.u64MsrApicBase
8874 && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
8875 && PDMHasApic(pVM))
8876 {
8877 uint64_t const u64MsrApicBase = APICGetBaseMsrNoCheck(pVCpu);
8878 Assert(u64MsrApicBase);
8879 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
8880
8881 RTGCPHYS const GCPhysApicBase = u64MsrApicBase & PAGE_BASE_GC_MASK;
8882
8883 /* Unalias any existing mapping. */
8884 int rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
8885 AssertRCReturn(rc, rc);
8886
8887 /* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */
8888 Log4(("hmR0VmxPreRunGuest: VCPU%u: Mapped HC APIC-access page at %#RGp\n", pVCpu->idCpu, GCPhysApicBase));
8889 rc = IOMMMIOMapMMIOHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
8890 AssertRCReturn(rc, rc);
8891
8892 /* Update the per-VCPU cache of the APIC base MSR. */
8893 pVCpu->hm.s.vmx.u64MsrApicBase = u64MsrApicBase;
8894 }
8895#endif /* !IEM_VERIFICATION_MODE_FULL */
8896
8897 if (TRPMHasTrap(pVCpu))
8898 hmR0VmxTrpmTrapToPendingEvent(pVCpu);
8899 uint32_t uIntrState = hmR0VmxEvaluatePendingEvent(pVCpu, pMixedCtx);
8900
8901 /*
8902 * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus needs to be done with
8903 * longjmps or interrupts + preemption enabled. Event injection might also result in triple-faulting the VM.
8904 */
8905 rcStrict = hmR0VmxInjectPendingEvent(pVCpu, pMixedCtx, uIntrState, fStepping);
8906 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8907 { /* likely */ }
8908 else
8909 {
8910 AssertMsg(rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8911 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8912 return rcStrict;
8913 }
8914
8915 /*
8916 * No longjmps to ring-3 from this point on!!!
8917 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
8918 * This also disables flushing of the R0-logger instance (if any).
8919 */
8920 VMMRZCallRing3Disable(pVCpu);
8921
8922 /*
8923 * Load the guest state bits.
8924 *
8925 * We cannot perform longjmps while loading the guest state because we do not preserve the
8926 * host/guest state (although the VMCS will be preserved) across longjmps which can cause
8927 * CPU migration.
8928 *
8929 * If we are injecting events to a real-on-v86 mode guest, we will have to update
8930 * RIP and some segment registers, i.e. hmR0VmxInjectPendingEvent()->hmR0VmxInjectEventVmcs().
8931 * Hence, loading of the guest state needs to be done -after- injection of events.
8932 */
8933 rcStrict = hmR0VmxLoadGuestStateOptimal(pVM, pVCpu, pMixedCtx);
8934 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8935 { /* likely */ }
8936 else
8937 {
8938 VMMRZCallRing3Enable(pVCpu);
8939 return rcStrict;
8940 }
8941
8942 /*
8943 * We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
8944 * when thread-context hooks aren't used and we've been running with preemption disabled for a while.
8945 *
8946 * We need to check for force-flags that could've possible been altered since we last checked them (e.g.
8947 * by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
8948 *
8949 * We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
8950 * executing guest code.
8951 */
8952 pVmxTransient->fEFlags = ASMIntDisableFlags();
8953
8954 if ( ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
8955 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
8956 || ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */
8957 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT))) )
8958 {
8959 if (!RTThreadPreemptIsPending(NIL_RTTHREAD))
8960 {
8961 pVCpu->hm.s.Event.fPending = false;
8962
8963 /*
8964 * We've injected any pending events. This is really the point of no return (to ring-3).
8965 *
8966 * Note! The caller expects to continue with interrupts & longjmps disabled on successful
8967 * returns from this function, so don't enable them here.
8968 */
8969 return VINF_SUCCESS;
8970 }
8971
8972 STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
8973 rcStrict = VINF_EM_RAW_INTERRUPT;
8974 }
8975 else
8976 {
8977 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
8978 rcStrict = VINF_EM_RAW_TO_R3;
8979 }
8980
8981 ASMSetFlags(pVmxTransient->fEFlags);
8982 VMMRZCallRing3Enable(pVCpu);
8983
8984 return rcStrict;
8985}
8986
8987
8988/**
8989 * Prepares to run guest code in VT-x and we've committed to doing so. This
8990 * means there is no backing out to ring-3 or anywhere else at this
8991 * point.
8992 *
8993 * @param pVM The cross context VM structure.
8994 * @param pVCpu The cross context virtual CPU structure.
8995 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
8996 * out-of-sync. Make sure to update the required fields
8997 * before using them.
8998 * @param pVmxTransient Pointer to the VMX transient structure.
8999 *
9000 * @remarks Called with preemption disabled.
9001 * @remarks No-long-jump zone!!!
9002 */
9003static void hmR0VmxPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
9004{
9005 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
9006 Assert(VMMR0IsLogFlushDisabled(pVCpu));
9007 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
9008
9009 /*
9010 * Indicate start of guest execution and where poking EMT out of guest-context is recognized.
9011 */
9012 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
9013 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
9014
9015#ifdef HMVMX_ALWAYS_SWAP_FPU_STATE
9016 if (!CPUMIsGuestFPUStateActive(pVCpu))
9017 if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
9018 HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
9019 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9020#endif
9021
9022 if ( pVCpu->hm.s.fPreloadGuestFpu
9023 && !CPUMIsGuestFPUStateActive(pVCpu))
9024 {
9025 if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
9026 HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
9027 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
9028 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9029 }
9030
9031 /*
9032 * Lazy-update of the host MSRs values in the auto-load/store MSR area.
9033 */
9034 if ( !pVCpu->hm.s.vmx.fUpdatedHostMsrs
9035 && pVCpu->hm.s.vmx.cMsrs > 0)
9036 {
9037 hmR0VmxUpdateAutoLoadStoreHostMsrs(pVCpu);
9038 }
9039
9040 /*
9041 * Load the host state bits as we may've been preempted (only happens when
9042 * thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
9043 * Note that the 64-on-32 switcher saves the (64-bit) host state into the VMCS and
9044 * if we change the switcher back to 32-bit, we *must* save the 32-bit host state here.
9045 * See @bugref{8432}.
9046 */
9047 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
9048 {
9049 int rc = hmR0VmxSaveHostState(pVM, pVCpu);
9050 AssertRC(rc);
9051 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreemptSaveHostState);
9052 }
9053 Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT));
9054
9055 /*
9056 * Load the state shared between host and guest (FPU, debug, lazy MSRs).
9057 */
9058 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
9059 hmR0VmxLoadSharedState(pVM, pVCpu, pMixedCtx);
9060 AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
9061
9062 /* Store status of the shared guest-host state at the time of VM-entry. */
9063#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
9064 if (CPUMIsGuestInLongModeEx(pMixedCtx))
9065 {
9066 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
9067 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
9068 }
9069 else
9070#endif
9071 {
9072 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
9073 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
9074 }
9075 pVmxTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
9076
9077 /*
9078 * Cache the TPR-shadow for checking on every VM-exit if it might have changed.
9079 */
9080 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
9081 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR];
9082
9083 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
9084 RTCPUID idCurrentCpu = pCpu->idCpu;
9085 if ( pVmxTransient->fUpdateTscOffsettingAndPreemptTimer
9086 || idCurrentCpu != pVCpu->hm.s.idLastCpu)
9087 {
9088 hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVM, pVCpu);
9089 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
9090 }
9091
9092 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
9093 hmR0VmxFlushTaggedTlb(pVCpu, pCpu); /* Invalidate the appropriate guest entries from the TLB. */
9094 Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
9095 pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Update the error reporting info. with the current host CPU. */
9096
9097 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
9098
9099 TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
9100 to start executing. */
9101
9102 /*
9103 * Load the TSC_AUX MSR when we are not intercepting RDTSCP.
9104 */
9105 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
9106 {
9107 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
9108 {
9109 bool fMsrUpdated;
9110 int rc2 = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
9111 AssertRC(rc2);
9112 Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS));
9113
9114 rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, CPUMR0GetGuestTscAux(pVCpu), true /* fUpdateHostMsr */,
9115 &fMsrUpdated);
9116 AssertRC(rc2);
9117 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
9118
9119 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
9120 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
9121 }
9122 else
9123 {
9124 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX);
9125 Assert(!pVCpu->hm.s.vmx.cMsrs || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
9126 }
9127 }
9128
9129#ifdef VBOX_STRICT
9130 hmR0VmxCheckAutoLoadStoreMsrs(pVCpu);
9131 hmR0VmxCheckHostEferMsr(pVCpu);
9132 AssertRC(hmR0VmxCheckVmcsCtls(pVCpu));
9133#endif
9134#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
9135 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVM, pVCpu, pMixedCtx);
9136 if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
9137 Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
9138#endif
9139}
9140
9141
9142/**
9143 * Performs some essential restoration of state after running guest code in
9144 * VT-x.
9145 *
9146 * @param pVM The cross context VM structure.
9147 * @param pVCpu The cross context virtual CPU structure.
9148 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
9149 * out-of-sync. Make sure to update the required fields
9150 * before using them.
9151 * @param pVmxTransient Pointer to the VMX transient structure.
9152 * @param rcVMRun Return code of VMLAUNCH/VMRESUME.
9153 *
9154 * @remarks Called with interrupts disabled, and returns with interrupts enabled!
9155 *
9156 * @remarks No-long-jump zone!!! This function will however re-enable longjmps
9157 * unconditionally when it is safe to do so.
9158 */
9159static void hmR0VmxPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, int rcVMRun)
9160{
9161 NOREF(pVM);
9162
9163 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
9164
9165 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
9166 ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
9167 HMVMXCPU_GST_RESET_TO(pVCpu, 0); /* Exits/longjmps to ring-3 requires saving the guest state. */
9168 pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
9169 pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
9170 pVmxTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
9171
9172 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
9173 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVCpu->hm.s.vmx.u64TSCOffset);
9174
9175 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
9176 TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
9177 Assert(!ASMIntAreEnabled());
9178 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
9179
9180#ifdef HMVMX_ALWAYS_SWAP_FPU_STATE
9181 if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVM, pVCpu))
9182 {
9183 hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
9184 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9185 }
9186#endif
9187
9188#if HC_ARCH_BITS == 64
9189 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_REQUIRED; /* Host state messed up by VT-x, we must restore. */
9190#endif
9191#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
9192 /* The 64-on-32 switcher maintains uVmcsState on its own and we need to leave it alone here. */
9193 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
9194 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
9195#else
9196 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
9197#endif
9198#ifdef VBOX_STRICT
9199 hmR0VmxCheckHostEferMsr(pVCpu); /* Verify that VMRUN/VMLAUNCH didn't modify host EFER. */
9200#endif
9201 ASMSetFlags(pVmxTransient->fEFlags); /* Enable interrupts. */
9202 VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
9203
9204 /* Save the basic VM-exit reason. Refer Intel spec. 24.9.1 "Basic VM-exit Information". */
9205 uint32_t uExitReason;
9206 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
9207 rc |= hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
9208 AssertRC(rc);
9209 pVmxTransient->uExitReason = (uint16_t)VMX_EXIT_REASON_BASIC(uExitReason);
9210 pVmxTransient->fVMEntryFailed = VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uEntryIntInfo);
9211
9212 /* If the VMLAUNCH/VMRESUME failed, we can bail out early. This does -not- cover VMX_EXIT_ERR_*. */
9213 if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
9214 {
9215 Log4(("VM-entry failure: pVCpu=%p idCpu=%RU32 rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", pVCpu, pVCpu->idCpu, rcVMRun,
9216 pVmxTransient->fVMEntryFailed));
9217 return;
9218 }
9219
9220 /*
9221 * Update the VM-exit history array here even if the VM-entry failed due to:
9222 * - Invalid guest state.
9223 * - MSR loading.
9224 * - Machine-check event.
9225 *
9226 * In any of the above cases we will still have a "valid" VM-exit reason
9227 * despite @a fVMEntryFailed being false.
9228 *
9229 * See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
9230 */
9231 HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmxTransient->uExitReason);
9232
9233 if (RT_LIKELY(!pVmxTransient->fVMEntryFailed))
9234 {
9235 /** @todo We can optimize this by only syncing with our force-flags when
9236 * really needed and keeping the VMCS state as it is for most
9237 * VM-exits. */
9238 /* Update the guest interruptibility-state from the VMCS. */
9239 hmR0VmxSaveGuestIntrState(pVCpu, pMixedCtx);
9240
9241#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) || defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
9242 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9243 AssertRC(rc);
9244#elif defined(HMVMX_ALWAYS_SAVE_GUEST_RFLAGS)
9245 rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
9246 AssertRC(rc);
9247#endif
9248
9249 /*
9250 * Sync the TPR shadow with our APIC state.
9251 */
9252 if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
9253 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR])
9254 {
9255 rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]);
9256 AssertRC(rc);
9257 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
9258 }
9259 }
9260}
9261
9262
9263/**
9264 * Runs the guest code using VT-x the normal way.
9265 *
9266 * @returns VBox status code.
9267 * @param pVM The cross context VM structure.
9268 * @param pVCpu The cross context virtual CPU structure.
9269 * @param pCtx Pointer to the guest-CPU context.
9270 *
9271 * @note Mostly the same as hmR0VmxRunGuestCodeStep().
9272 */
9273static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9274{
9275 VMXTRANSIENT VmxTransient;
9276 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
9277 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
9278 uint32_t cLoops = 0;
9279
9280 for (;; cLoops++)
9281 {
9282 Assert(!HMR0SuspendPending());
9283 HMVMX_ASSERT_CPU_SAFE();
9284
9285 /* Preparatory work for running guest code, this may force us to return
9286 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
9287 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
9288 rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, false /* fStepping */);
9289 if (rcStrict != VINF_SUCCESS)
9290 break;
9291
9292 hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
9293 int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
9294 /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
9295
9296 /* Restore any residual host-state and save any bits shared between host
9297 and guest into the guest-CPU state. Re-enables interrupts! */
9298 hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rcRun);
9299
9300 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
9301 if (RT_SUCCESS(rcRun))
9302 { /* very likely */ }
9303 else
9304 {
9305 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
9306 hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
9307 return rcRun;
9308 }
9309
9310 /* Profile the VM-exit. */
9311 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
9312 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
9313 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
9314 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
9315 HMVMX_START_EXIT_DISPATCH_PROF();
9316
9317 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, pCtx, VmxTransient.uExitReason);
9318
9319 /* Handle the VM-exit. */
9320#ifdef HMVMX_USE_FUNCTION_TABLE
9321 rcStrict = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, pCtx, &VmxTransient);
9322#else
9323 rcStrict = hmR0VmxHandleExit(pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason);
9324#endif
9325 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
9326 if (rcStrict == VINF_SUCCESS)
9327 {
9328 if (cLoops <= pVM->hm.s.cMaxResumeLoops)
9329 continue; /* likely */
9330 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
9331 rcStrict = VINF_EM_RAW_INTERRUPT;
9332 }
9333 break;
9334 }
9335
9336 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
9337 return rcStrict;
9338}
9339
9340
9341
9342/** @name Execution loop for single stepping, DBGF events and expensive Dtrace
9343 * probes.
9344 *
9345 * The following few functions and associated structure contains the bloat
9346 * necessary for providing detailed debug events and dtrace probes as well as
9347 * reliable host side single stepping. This works on the principle of
9348 * "subclassing" the normal execution loop and workers. We replace the loop
9349 * method completely and override selected helpers to add necessary adjustments
9350 * to their core operation.
9351 *
9352 * The goal is to keep the "parent" code lean and mean, so as not to sacrifice
9353 * any performance for debug and analysis features.
9354 *
9355 * @{
9356 */
9357
9358/**
9359 * Transient per-VCPU debug state of VMCS and related info. we save/restore in
9360 * the debug run loop.
9361 */
9362typedef struct VMXRUNDBGSTATE
9363{
9364 /** The RIP we started executing at. This is for detecting that we stepped. */
9365 uint64_t uRipStart;
9366 /** The CS we started executing with. */
9367 uint16_t uCsStart;
9368
9369 /** Whether we've actually modified the 1st execution control field. */
9370 bool fModifiedProcCtls : 1;
9371 /** Whether we've actually modified the 2nd execution control field. */
9372 bool fModifiedProcCtls2 : 1;
9373 /** Whether we've actually modified the exception bitmap. */
9374 bool fModifiedXcptBitmap : 1;
9375
9376 /** We desire the modified the CR0 mask to be cleared. */
9377 bool fClearCr0Mask : 1;
9378 /** We desire the modified the CR4 mask to be cleared. */
9379 bool fClearCr4Mask : 1;
9380 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC. */
9381 uint32_t fCpe1Extra;
9382 /** Stuff we do not want in VMX_VMCS32_CTRL_PROC_EXEC. */
9383 uint32_t fCpe1Unwanted;
9384 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC2. */
9385 uint32_t fCpe2Extra;
9386 /** Extra stuff we need in VMX_VMCS32_CTRL_EXCEPTION_BITMAP. */
9387 uint32_t bmXcptExtra;
9388 /** The sequence number of the Dtrace provider settings the state was
9389 * configured against. */
9390 uint32_t uDtraceSettingsSeqNo;
9391 /** VM-exits to check (one bit per VM-exit). */
9392 uint32_t bmExitsToCheck[3];
9393
9394 /** The initial VMX_VMCS32_CTRL_PROC_EXEC value (helps with restore). */
9395 uint32_t fProcCtlsInitial;
9396 /** The initial VMX_VMCS32_CTRL_PROC_EXEC2 value (helps with restore). */
9397 uint32_t fProcCtls2Initial;
9398 /** The initial VMX_VMCS32_CTRL_EXCEPTION_BITMAP value (helps with restore). */
9399 uint32_t bmXcptInitial;
9400} VMXRUNDBGSTATE;
9401AssertCompileMemberSize(VMXRUNDBGSTATE, bmExitsToCheck, (VMX_EXIT_MAX + 1 + 31) / 32 * 4);
9402typedef VMXRUNDBGSTATE *PVMXRUNDBGSTATE;
9403
9404
9405/**
9406 * Initializes the VMXRUNDBGSTATE structure.
9407 *
9408 * @param pVCpu The cross context virtual CPU structure of the
9409 * calling EMT.
9410 * @param pCtx The CPU register context to go with @a pVCpu.
9411 * @param pDbgState The structure to initialize.
9412 */
9413DECLINLINE(void) hmR0VmxRunDebugStateInit(PVMCPU pVCpu, PCCPUMCTX pCtx, PVMXRUNDBGSTATE pDbgState)
9414{
9415 pDbgState->uRipStart = pCtx->rip;
9416 pDbgState->uCsStart = pCtx->cs.Sel;
9417
9418 pDbgState->fModifiedProcCtls = false;
9419 pDbgState->fModifiedProcCtls2 = false;
9420 pDbgState->fModifiedXcptBitmap = false;
9421 pDbgState->fClearCr0Mask = false;
9422 pDbgState->fClearCr4Mask = false;
9423 pDbgState->fCpe1Extra = 0;
9424 pDbgState->fCpe1Unwanted = 0;
9425 pDbgState->fCpe2Extra = 0;
9426 pDbgState->bmXcptExtra = 0;
9427 pDbgState->fProcCtlsInitial = pVCpu->hm.s.vmx.u32ProcCtls;
9428 pDbgState->fProcCtls2Initial = pVCpu->hm.s.vmx.u32ProcCtls2;
9429 pDbgState->bmXcptInitial = pVCpu->hm.s.vmx.u32XcptBitmap;
9430}
9431
9432
9433/**
9434 * Updates the VMSC fields with changes requested by @a pDbgState.
9435 *
9436 * This is performed after hmR0VmxPreRunGuestDebugStateUpdate as well
9437 * immediately before executing guest code, i.e. when interrupts are disabled.
9438 * We don't check status codes here as we cannot easily assert or return in the
9439 * latter case.
9440 *
9441 * @param pVCpu The cross context virtual CPU structure.
9442 * @param pDbgState The debug state.
9443 */
9444DECLINLINE(void) hmR0VmxPreRunGuestDebugStateApply(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9445{
9446 /*
9447 * Ensure desired flags in VMCS control fields are set.
9448 * (Ignoring write failure here, as we're committed and it's just debug extras.)
9449 *
9450 * Note! We load the shadow CR0 & CR4 bits when we flag the clearing, so
9451 * there should be no stale data in pCtx at this point.
9452 */
9453 if ( (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Extra) != pDbgState->fCpe1Extra
9454 || (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Unwanted))
9455 {
9456 pVCpu->hm.s.vmx.u32ProcCtls |= pDbgState->fCpe1Extra;
9457 pVCpu->hm.s.vmx.u32ProcCtls &= ~pDbgState->fCpe1Unwanted;
9458 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
9459 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls));
9460 pDbgState->fModifiedProcCtls = true;
9461 }
9462
9463 if ((pVCpu->hm.s.vmx.u32ProcCtls2 & pDbgState->fCpe2Extra) != pDbgState->fCpe2Extra)
9464 {
9465 pVCpu->hm.s.vmx.u32ProcCtls2 |= pDbgState->fCpe2Extra;
9466 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVCpu->hm.s.vmx.u32ProcCtls2);
9467 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls2));
9468 pDbgState->fModifiedProcCtls2 = true;
9469 }
9470
9471 if ((pVCpu->hm.s.vmx.u32XcptBitmap & pDbgState->bmXcptExtra) != pDbgState->bmXcptExtra)
9472 {
9473 pVCpu->hm.s.vmx.u32XcptBitmap |= pDbgState->bmXcptExtra;
9474 VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
9475 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVCpu->hm.s.vmx.u32XcptBitmap));
9476 pDbgState->fModifiedXcptBitmap = true;
9477 }
9478
9479 if (pDbgState->fClearCr0Mask && pVCpu->hm.s.vmx.u32CR0Mask != 0)
9480 {
9481 pVCpu->hm.s.vmx.u32CR0Mask = 0;
9482 VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, 0);
9483 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS_CTRL_CR0_MASK: 0\n"));
9484 }
9485
9486 if (pDbgState->fClearCr4Mask && pVCpu->hm.s.vmx.u32CR4Mask != 0)
9487 {
9488 pVCpu->hm.s.vmx.u32CR4Mask = 0;
9489 VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, 0);
9490 Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS_CTRL_CR4_MASK: 0\n"));
9491 }
9492}
9493
9494
9495DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugStateRevert(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, VBOXSTRICTRC rcStrict)
9496{
9497 /*
9498 * Restore VM-exit control settings as we may not reenter this function the
9499 * next time around.
9500 */
9501 /* We reload the initial value, trigger what we can of recalculations the
9502 next time around. From the looks of things, that's all that's required atm. */
9503 if (pDbgState->fModifiedProcCtls)
9504 {
9505 if (!(pDbgState->fProcCtlsInitial & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
9506 pDbgState->fProcCtlsInitial |= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
9507 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
9508 AssertRCReturn(rc2, rc2);
9509 pVCpu->hm.s.vmx.u32ProcCtls = pDbgState->fProcCtlsInitial;
9510 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_DEBUG);
9511 }
9512
9513 /* We're currently the only ones messing with this one, so just restore the
9514 cached value and reload the field. */
9515 if ( pDbgState->fModifiedProcCtls2
9516 && pVCpu->hm.s.vmx.u32ProcCtls2 != pDbgState->fProcCtls2Initial)
9517 {
9518 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);
9519 AssertRCReturn(rc2, rc2);
9520 pVCpu->hm.s.vmx.u32ProcCtls2 = pDbgState->fProcCtls2Initial;
9521 }
9522
9523 /* If we've modified the exception bitmap, we restore it and trigger
9524 reloading and partial recalculation the next time around. */
9525 if (pDbgState->fModifiedXcptBitmap)
9526 {
9527 pVCpu->hm.s.vmx.u32XcptBitmap = pDbgState->bmXcptInitial;
9528 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS | HM_CHANGED_GUEST_CR0);
9529 }
9530
9531 /* We assume hmR0VmxLoadSharedCR0 will recalculate and load the CR0 mask. */
9532 if (pDbgState->fClearCr0Mask)
9533 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9534
9535 /* We assume hmR0VmxLoadGuestCR3AndCR4 will recalculate and load the CR4 mask. */
9536 if (pDbgState->fClearCr4Mask)
9537 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
9538
9539 return rcStrict;
9540}
9541
9542
9543/**
9544 * Configures VM-exit controls for current DBGF and DTrace settings.
9545 *
9546 * This updates @a pDbgState and the VMCS execution control fields to reflect
9547 * the necessary VM-exits demanded by DBGF and DTrace.
9548 *
9549 * @param pVM The cross context VM structure.
9550 * @param pVCpu The cross context virtual CPU structure.
9551 * @param pCtx Pointer to the guest-CPU context.
9552 * @param pDbgState The debug state.
9553 * @param pVmxTransient Pointer to the VMX transient structure. May update
9554 * fUpdateTscOffsettingAndPreemptTimer.
9555 */
9556static void hmR0VmxPreRunGuestDebugStateUpdate(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx,
9557 PVMXRUNDBGSTATE pDbgState, PVMXTRANSIENT pVmxTransient)
9558{
9559 /*
9560 * Take down the dtrace serial number so we can spot changes.
9561 */
9562 pDbgState->uDtraceSettingsSeqNo = VBOXVMM_GET_SETTINGS_SEQ_NO();
9563 ASMCompilerBarrier();
9564
9565 /*
9566 * We'll rebuild most of the middle block of data members (holding the
9567 * current settings) as we go along here, so start by clearing it all.
9568 */
9569 pDbgState->bmXcptExtra = 0;
9570 pDbgState->fCpe1Extra = 0;
9571 pDbgState->fCpe1Unwanted = 0;
9572 pDbgState->fCpe2Extra = 0;
9573 for (unsigned i = 0; i < RT_ELEMENTS(pDbgState->bmExitsToCheck); i++)
9574 pDbgState->bmExitsToCheck[i] = 0;
9575
9576 /*
9577 * Software interrupts (INT XXh) - no idea how to trigger these...
9578 */
9579 if ( DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_INTERRUPT_SOFTWARE)
9580 || VBOXVMM_INT_SOFTWARE_ENABLED())
9581 {
9582 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9583 }
9584
9585 /*
9586 * INT3 breakpoints - triggered by #BP exceptions.
9587 */
9588 if (pVM->dbgf.ro.cEnabledInt3Breakpoints > 0)
9589 pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9590
9591 /*
9592 * Exception bitmap and XCPT events+probes.
9593 */
9594 for (int iXcpt = 0; iXcpt < (DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST + 1); iXcpt++)
9595 if (DBGF_IS_EVENT_ENABLED(pVM, (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + iXcpt)))
9596 pDbgState->bmXcptExtra |= RT_BIT_32(iXcpt);
9597
9598 if (VBOXVMM_XCPT_DE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DE);
9599 if (VBOXVMM_XCPT_DB_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DB);
9600 if (VBOXVMM_XCPT_BP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9601 if (VBOXVMM_XCPT_OF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_OF);
9602 if (VBOXVMM_XCPT_BR_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BR);
9603 if (VBOXVMM_XCPT_UD_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_UD);
9604 if (VBOXVMM_XCPT_NM_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NM);
9605 if (VBOXVMM_XCPT_DF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DF);
9606 if (VBOXVMM_XCPT_TS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_TS);
9607 if (VBOXVMM_XCPT_NP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NP);
9608 if (VBOXVMM_XCPT_SS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SS);
9609 if (VBOXVMM_XCPT_GP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_GP);
9610 if (VBOXVMM_XCPT_PF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_PF);
9611 if (VBOXVMM_XCPT_MF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_MF);
9612 if (VBOXVMM_XCPT_AC_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_AC);
9613 if (VBOXVMM_XCPT_XF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_XF);
9614 if (VBOXVMM_XCPT_VE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_VE);
9615 if (VBOXVMM_XCPT_SX_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SX);
9616
9617 if (pDbgState->bmXcptExtra)
9618 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9619
9620 /*
9621 * Process events and probes for VM-exits, making sure we get the wanted VM-exits.
9622 *
9623 * Note! This is the reverse of waft hmR0VmxHandleExitDtraceEvents does.
9624 * So, when adding/changing/removing please don't forget to update it.
9625 *
9626 * Some of the macros are picking up local variables to save horizontal space,
9627 * (being able to see it in a table is the lesser evil here).
9628 */
9629#define IS_EITHER_ENABLED(a_pVM, a_EventSubName) \
9630 ( DBGF_IS_EVENT_ENABLED(a_pVM, RT_CONCAT(DBGFEVENT_, a_EventSubName)) \
9631 || RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)() )
9632#define SET_ONLY_XBM_IF_EITHER_EN(a_EventSubName, a_uExit) \
9633 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9634 { AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9635 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9636 } else do { } while (0)
9637#define SET_CPE1_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec) \
9638 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9639 { \
9640 (pDbgState)->fCpe1Extra |= (a_fCtrlProcExec); \
9641 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9642 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9643 } else do { } while (0)
9644#define SET_CPEU_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fUnwantedCtrlProcExec) \
9645 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9646 { \
9647 (pDbgState)->fCpe1Unwanted |= (a_fUnwantedCtrlProcExec); \
9648 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9649 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9650 } else do { } while (0)
9651#define SET_CPE2_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec2) \
9652 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9653 { \
9654 (pDbgState)->fCpe2Extra |= (a_fCtrlProcExec2); \
9655 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9656 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9657 } else do { } while (0)
9658
9659 SET_ONLY_XBM_IF_EITHER_EN(EXIT_TASK_SWITCH, VMX_EXIT_TASK_SWITCH); /* unconditional */
9660 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_VIOLATION, VMX_EXIT_EPT_VIOLATION); /* unconditional */
9661 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_MISCONFIG, VMX_EXIT_EPT_MISCONFIG); /* unconditional (unless #VE) */
9662 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_ACCESS, VMX_EXIT_APIC_ACCESS); /* feature dependent, nothing to enable here */
9663 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */
9664
9665 SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */
9666 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID);
9667 SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */
9668 SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC);
9669 SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT); /* paranoia */
9670 SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT);
9671 SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */
9672 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD);
9673 SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
9674 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG);
9675 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
9676 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC);
9677 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
9678 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC);
9679 SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */
9680 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM);
9681 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */
9682 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL);
9683 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */
9684 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR);
9685 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */
9686 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH);
9687 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */
9688 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD);
9689 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */
9690 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST);
9691 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */
9692 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD);
9693 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */
9694 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME);
9695 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */
9696 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE);
9697 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */
9698 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF);
9699 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */
9700 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON);
9701
9702 if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)
9703 || IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9704 {
9705 int rc2 = hmR0VmxSaveGuestCR0(pVCpu, pCtx);
9706 rc2 |= hmR0VmxSaveGuestCR4(pVCpu, pCtx);
9707 rc2 |= hmR0VmxSaveGuestApicState(pVCpu, pCtx);
9708 AssertRC(rc2);
9709
9710#if 0 /** @todo fix me */
9711 pDbgState->fClearCr0Mask = true;
9712 pDbgState->fClearCr4Mask = true;
9713#endif
9714 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
9715 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT;
9716 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9717 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT;
9718 pDbgState->fCpe1Unwanted |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* risky? */
9719 /* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT. It would
9720 require clearing here and in the loop if we start using it. */
9721 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_CRX);
9722 }
9723 else
9724 {
9725 if (pDbgState->fClearCr0Mask)
9726 {
9727 pDbgState->fClearCr0Mask = false;
9728 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9729 }
9730 if (pDbgState->fClearCr4Mask)
9731 {
9732 pDbgState->fClearCr4Mask = false;
9733 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
9734 }
9735 }
9736 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX);
9737 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX);
9738
9739 if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ)
9740 || IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE))
9741 {
9742 /** @todo later, need to fix handler as it assumes this won't usually happen. */
9743 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX);
9744 }
9745 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX);
9746 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX);
9747
9748 SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); /* risky clearing this? */
9749 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR);
9750 SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
9751 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR);
9752 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT); /* paranoia */
9753 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT);
9754 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT); /* paranoia */
9755 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR);
9756#if 0 /** @todo too slow, fix handler. */
9757 SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
9758#endif
9759 SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE);
9760
9761 if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT)
9762 || IS_EITHER_ENABLED(pVM, INSTR_SIDT)
9763 || IS_EITHER_ENABLED(pVM, INSTR_LGDT)
9764 || IS_EITHER_ENABLED(pVM, INSTR_LIDT))
9765 {
9766 pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
9767 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XDTR_ACCESS);
9768 }
9769 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_XDTR_ACCESS);
9770 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_XDTR_ACCESS);
9771 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_XDTR_ACCESS);
9772 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_XDTR_ACCESS);
9773
9774 if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT)
9775 || IS_EITHER_ENABLED(pVM, INSTR_STR)
9776 || IS_EITHER_ENABLED(pVM, INSTR_LLDT)
9777 || IS_EITHER_ENABLED(pVM, INSTR_LTR))
9778 {
9779 pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
9780 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_TR_ACCESS);
9781 }
9782 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_TR_ACCESS);
9783 SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_TR_ACCESS);
9784 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_TR_ACCESS);
9785 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_TR_ACCESS);
9786
9787 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */
9788 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT);
9789 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
9790 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP);
9791 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */
9792 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID);
9793 SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
9794 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD);
9795 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */
9796 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV);
9797 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
9798 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND);
9799 SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
9800 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID);
9801 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */
9802 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC);
9803 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
9804 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED);
9805 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */
9806 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES);
9807 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */
9808 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS);
9809
9810#undef IS_EITHER_ENABLED
9811#undef SET_ONLY_XBM_IF_EITHER_EN
9812#undef SET_CPE1_XBM_IF_EITHER_EN
9813#undef SET_CPEU_XBM_IF_EITHER_EN
9814#undef SET_CPE2_XBM_IF_EITHER_EN
9815
9816 /*
9817 * Sanitize the control stuff.
9818 */
9819 pDbgState->fCpe2Extra &= pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
9820 if (pDbgState->fCpe2Extra)
9821 pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
9822 pDbgState->fCpe1Extra &= pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
9823 pDbgState->fCpe1Unwanted &= ~pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
9824 if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
9825 {
9826 pVCpu->hm.s.fDebugWantRdTscExit ^= true;
9827 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9828 }
9829
9830 Log6(("HM: debug state: cpe1=%#RX32 cpeu=%#RX32 cpe2=%#RX32%s%s\n",
9831 pDbgState->fCpe1Extra, pDbgState->fCpe1Unwanted, pDbgState->fCpe2Extra,
9832 pDbgState->fClearCr0Mask ? " clr-cr0" : "",
9833 pDbgState->fClearCr4Mask ? " clr-cr4" : ""));
9834}
9835
9836
9837/**
9838 * Fires off DBGF events and dtrace probes for a VM-exit, when it's
9839 * appropriate.
9840 *
9841 * The caller has checked the VM-exit against the
9842 * VMXRUNDBGSTATE::bmExitsToCheck bitmap. The caller has checked for NMIs
9843 * already, so we don't have to do that either.
9844 *
9845 * @returns Strict VBox status code (i.e. informational status codes too).
9846 * @param pVM The cross context VM structure.
9847 * @param pVCpu The cross context virtual CPU structure.
9848 * @param pMixedCtx Pointer to the guest-CPU context.
9849 * @param pVmxTransient Pointer to the VMX-transient structure.
9850 * @param uExitReason The VM-exit reason.
9851 *
9852 * @remarks The name of this function is displayed by dtrace, so keep it short
9853 * and to the point. No longer than 33 chars long, please.
9854 */
9855static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx,
9856 PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
9857{
9858 /*
9859 * Translate the event into a DBGF event (enmEvent + uEventArg) and at the
9860 * same time check whether any corresponding Dtrace event is enabled (fDtrace).
9861 *
9862 * Note! This is the reverse operation of what hmR0VmxPreRunGuestDebugStateUpdate
9863 * does. Must add/change/remove both places. Same ordering, please.
9864 *
9865 * Added/removed events must also be reflected in the next section
9866 * where we dispatch dtrace events.
9867 */
9868 bool fDtrace1 = false;
9869 bool fDtrace2 = false;
9870 DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END;
9871 DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END;
9872 uint32_t uEventArg = 0;
9873#define SET_EXIT(a_EventSubName) \
9874 do { \
9875 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9876 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9877 } while (0)
9878#define SET_BOTH(a_EventSubName) \
9879 do { \
9880 enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \
9881 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9882 fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \
9883 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9884 } while (0)
9885 switch (uExitReason)
9886 {
9887 case VMX_EXIT_MTF:
9888 return hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient);
9889
9890 case VMX_EXIT_XCPT_OR_NMI:
9891 {
9892 uint8_t const idxVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
9893 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo))
9894 {
9895 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT:
9896 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT:
9897 case VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT:
9898 if (idxVector <= (unsigned)(DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST))
9899 {
9900 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uExitIntInfo))
9901 {
9902 hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
9903 uEventArg = pVmxTransient->uExitIntErrorCode;
9904 }
9905 enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);
9906 switch (enmEvent1)
9907 {
9908 case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break;
9909 case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break;
9910 case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break;
9911 case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break;
9912 case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break;
9913 case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break;
9914 case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break;
9915 case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break;
9916 case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break;
9917 case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break;
9918 case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break;
9919 case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break;
9920 case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break;
9921 case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break;
9922 case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break;
9923 case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break;
9924 case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break;
9925 case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break;
9926 default: break;
9927 }
9928 }
9929 else
9930 AssertFailed();
9931 break;
9932
9933 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT:
9934 uEventArg = idxVector;
9935 enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE;
9936 fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED();
9937 break;
9938 }
9939 break;
9940 }
9941
9942 case VMX_EXIT_TRIPLE_FAULT:
9943 enmEvent1 = DBGFEVENT_TRIPLE_FAULT;
9944 //fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();
9945 break;
9946 case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break;
9947 case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break;
9948 case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break;
9949 case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break;
9950 case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break;
9951
9952 /* Instruction specific VM-exits: */
9953 case VMX_EXIT_CPUID: SET_BOTH(CPUID); break;
9954 case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break;
9955 case VMX_EXIT_HLT: SET_BOTH(HALT); break;
9956 case VMX_EXIT_INVD: SET_BOTH(INVD); break;
9957 case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break;
9958 case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break;
9959 case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break;
9960 case VMX_EXIT_RSM: SET_BOTH(RSM); break;
9961 case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break;
9962 case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break;
9963 case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break;
9964 case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break;
9965 case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break;
9966 case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break;
9967 case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break;
9968 case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break;
9969 case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break;
9970 case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break;
9971 case VMX_EXIT_MOV_CRX:
9972 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9973/** @todo r=bird: I feel these macros aren't very descriptive and needs to be at least 30 chars longer! ;-)
9974* Sensible abbreviations strongly recommended here because even with 130 columns this stuff get too wide! */
9975 if ( VMX_EXIT_QUALIFICATION_CRX_ACCESS(pVmxTransient->uExitQualification)
9976 == VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ)
9977 SET_BOTH(CRX_READ);
9978 else
9979 SET_BOTH(CRX_WRITE);
9980 uEventArg = VMX_EXIT_QUALIFICATION_CRX_REGISTER(pVmxTransient->uExitQualification);
9981 break;
9982 case VMX_EXIT_MOV_DRX:
9983 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9984 if ( VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification)
9985 == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ)
9986 SET_BOTH(DRX_READ);
9987 else
9988 SET_BOTH(DRX_WRITE);
9989 uEventArg = VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification);
9990 break;
9991 case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break;
9992 case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break;
9993 case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break;
9994 case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break;
9995 case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break;
9996 case VMX_EXIT_XDTR_ACCESS:
9997 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9998 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_XDTR_INSINFO_INSTR_ID))
9999 {
10000 case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break;
10001 case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break;
10002 case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break;
10003 case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break;
10004 }
10005 break;
10006
10007 case VMX_EXIT_TR_ACCESS:
10008 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
10009 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_YYTR_INSINFO_INSTR_ID))
10010 {
10011 case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break;
10012 case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break;
10013 case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break;
10014 case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break;
10015 }
10016 break;
10017
10018 case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break;
10019 case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break;
10020 case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break;
10021 case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break;
10022 case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break;
10023 case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break;
10024 case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break;
10025 case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break;
10026 case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break;
10027 case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break;
10028 case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break;
10029
10030 /* Events that aren't relevant at this point. */
10031 case VMX_EXIT_EXT_INT:
10032 case VMX_EXIT_INT_WINDOW:
10033 case VMX_EXIT_NMI_WINDOW:
10034 case VMX_EXIT_TPR_BELOW_THRESHOLD:
10035 case VMX_EXIT_PREEMPT_TIMER:
10036 case VMX_EXIT_IO_INSTR:
10037 break;
10038
10039 /* Errors and unexpected events. */
10040 case VMX_EXIT_INIT_SIGNAL:
10041 case VMX_EXIT_SIPI:
10042 case VMX_EXIT_IO_SMI:
10043 case VMX_EXIT_SMI:
10044 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
10045 case VMX_EXIT_ERR_MSR_LOAD:
10046 case VMX_EXIT_ERR_MACHINE_CHECK:
10047 break;
10048
10049 default:
10050 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
10051 break;
10052 }
10053#undef SET_BOTH
10054#undef SET_EXIT
10055
10056 /*
10057 * Dtrace tracepoints go first. We do them here at once so we don't
10058 * have to copy the guest state saving and stuff a few dozen times.
10059 * Down side is that we've got to repeat the switch, though this time
10060 * we use enmEvent since the probes are a subset of what DBGF does.
10061 */
10062 if (fDtrace1 || fDtrace2)
10063 {
10064 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
10065 hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
10066 switch (enmEvent1)
10067 {
10068 /** @todo consider which extra parameters would be helpful for each probe. */
10069 case DBGFEVENT_END: break;
10070 case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pMixedCtx); break;
10071 case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pMixedCtx, pMixedCtx->dr[6]); break;
10072 case DBGFEVENT_XCPT_BP: VBOXVMM_XCPT_BP(pVCpu, pMixedCtx); break;
10073 case DBGFEVENT_XCPT_OF: VBOXVMM_XCPT_OF(pVCpu, pMixedCtx); break;
10074 case DBGFEVENT_XCPT_BR: VBOXVMM_XCPT_BR(pVCpu, pMixedCtx); break;
10075 case DBGFEVENT_XCPT_UD: VBOXVMM_XCPT_UD(pVCpu, pMixedCtx); break;
10076 case DBGFEVENT_XCPT_NM: VBOXVMM_XCPT_NM(pVCpu, pMixedCtx); break;
10077 case DBGFEVENT_XCPT_DF: VBOXVMM_XCPT_DF(pVCpu, pMixedCtx); break;
10078 case DBGFEVENT_XCPT_TS: VBOXVMM_XCPT_TS(pVCpu, pMixedCtx, uEventArg); break;
10079 case DBGFEVENT_XCPT_NP: VBOXVMM_XCPT_NP(pVCpu, pMixedCtx, uEventArg); break;
10080 case DBGFEVENT_XCPT_SS: VBOXVMM_XCPT_SS(pVCpu, pMixedCtx, uEventArg); break;
10081 case DBGFEVENT_XCPT_GP: VBOXVMM_XCPT_GP(pVCpu, pMixedCtx, uEventArg); break;
10082 case DBGFEVENT_XCPT_PF: VBOXVMM_XCPT_PF(pVCpu, pMixedCtx, uEventArg, pMixedCtx->cr2); break;
10083 case DBGFEVENT_XCPT_MF: VBOXVMM_XCPT_MF(pVCpu, pMixedCtx); break;
10084 case DBGFEVENT_XCPT_AC: VBOXVMM_XCPT_AC(pVCpu, pMixedCtx); break;
10085 case DBGFEVENT_XCPT_XF: VBOXVMM_XCPT_XF(pVCpu, pMixedCtx); break;
10086 case DBGFEVENT_XCPT_VE: VBOXVMM_XCPT_VE(pVCpu, pMixedCtx); break;
10087 case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pMixedCtx, uEventArg); break;
10088 case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10089 case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break;
10090 case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pMixedCtx); break;
10091 case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pMixedCtx); break;
10092 case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pMixedCtx); break;
10093 case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pMixedCtx); break;
10094 case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pMixedCtx); break;
10095 case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pMixedCtx); break;
10096 case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pMixedCtx); break;
10097 case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10098 case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10099 case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10100 case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10101 case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pMixedCtx, pMixedCtx->ecx); break;
10102 case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pMixedCtx, pMixedCtx->ecx,
10103 RT_MAKE_U64(pMixedCtx->eax, pMixedCtx->edx)); break;
10104 case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pMixedCtx); break;
10105 case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pMixedCtx); break;
10106 case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pMixedCtx); break;
10107 case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pMixedCtx); break;
10108 case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pMixedCtx); break;
10109 case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pMixedCtx); break;
10110 case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pMixedCtx); break;
10111 case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pMixedCtx); break;
10112 case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pMixedCtx); break;
10113 case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pMixedCtx); break;
10114 case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pMixedCtx); break;
10115 case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pMixedCtx); break;
10116 case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pMixedCtx); break;
10117 case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pMixedCtx); break;
10118 case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pMixedCtx); break;
10119 case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pMixedCtx); break;
10120 case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pMixedCtx); break;
10121 case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pMixedCtx); break;
10122 case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pMixedCtx); break;
10123 case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pMixedCtx); break;
10124 case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pMixedCtx); break;
10125 case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pMixedCtx); break;
10126 case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pMixedCtx); break;
10127 case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pMixedCtx); break;
10128 case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pMixedCtx); break;
10129 case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pMixedCtx); break;
10130 case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pMixedCtx); break;
10131 case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pMixedCtx); break;
10132 case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pMixedCtx); break;
10133 case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pMixedCtx); break;
10134 case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pMixedCtx); break;
10135 case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pMixedCtx); break;
10136 default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break;
10137 }
10138 switch (enmEvent2)
10139 {
10140 /** @todo consider which extra parameters would be helpful for each probe. */
10141 case DBGFEVENT_END: break;
10142 case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pMixedCtx); break;
10143 case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break;
10144 case DBGFEVENT_EXIT_GETSEC: VBOXVMM_EXIT_GETSEC(pVCpu, pMixedCtx); break;
10145 case DBGFEVENT_EXIT_HALT: VBOXVMM_EXIT_HALT(pVCpu, pMixedCtx); break;
10146 case DBGFEVENT_EXIT_INVD: VBOXVMM_EXIT_INVD(pVCpu, pMixedCtx); break;
10147 case DBGFEVENT_EXIT_INVLPG: VBOXVMM_EXIT_INVLPG(pVCpu, pMixedCtx); break;
10148 case DBGFEVENT_EXIT_RDPMC: VBOXVMM_EXIT_RDPMC(pVCpu, pMixedCtx); break;
10149 case DBGFEVENT_EXIT_RDTSC: VBOXVMM_EXIT_RDTSC(pVCpu, pMixedCtx); break;
10150 case DBGFEVENT_EXIT_RSM: VBOXVMM_EXIT_RSM(pVCpu, pMixedCtx); break;
10151 case DBGFEVENT_EXIT_CRX_READ: VBOXVMM_EXIT_CRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10152 case DBGFEVENT_EXIT_CRX_WRITE: VBOXVMM_EXIT_CRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10153 case DBGFEVENT_EXIT_DRX_READ: VBOXVMM_EXIT_DRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10154 case DBGFEVENT_EXIT_DRX_WRITE: VBOXVMM_EXIT_DRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
10155 case DBGFEVENT_EXIT_RDMSR: VBOXVMM_EXIT_RDMSR(pVCpu, pMixedCtx, pMixedCtx->ecx); break;
10156 case DBGFEVENT_EXIT_WRMSR: VBOXVMM_EXIT_WRMSR(pVCpu, pMixedCtx, pMixedCtx->ecx,
10157 RT_MAKE_U64(pMixedCtx->eax, pMixedCtx->edx)); break;
10158 case DBGFEVENT_EXIT_MWAIT: VBOXVMM_EXIT_MWAIT(pVCpu, pMixedCtx); break;
10159 case DBGFEVENT_EXIT_MONITOR: VBOXVMM_EXIT_MONITOR(pVCpu, pMixedCtx); break;
10160 case DBGFEVENT_EXIT_PAUSE: VBOXVMM_EXIT_PAUSE(pVCpu, pMixedCtx); break;
10161 case DBGFEVENT_EXIT_SGDT: VBOXVMM_EXIT_SGDT(pVCpu, pMixedCtx); break;
10162 case DBGFEVENT_EXIT_SIDT: VBOXVMM_EXIT_SIDT(pVCpu, pMixedCtx); break;
10163 case DBGFEVENT_EXIT_LGDT: VBOXVMM_EXIT_LGDT(pVCpu, pMixedCtx); break;
10164 case DBGFEVENT_EXIT_LIDT: VBOXVMM_EXIT_LIDT(pVCpu, pMixedCtx); break;
10165 case DBGFEVENT_EXIT_SLDT: VBOXVMM_EXIT_SLDT(pVCpu, pMixedCtx); break;
10166 case DBGFEVENT_EXIT_STR: VBOXVMM_EXIT_STR(pVCpu, pMixedCtx); break;
10167 case DBGFEVENT_EXIT_LLDT: VBOXVMM_EXIT_LLDT(pVCpu, pMixedCtx); break;
10168 case DBGFEVENT_EXIT_LTR: VBOXVMM_EXIT_LTR(pVCpu, pMixedCtx); break;
10169 case DBGFEVENT_EXIT_RDTSCP: VBOXVMM_EXIT_RDTSCP(pVCpu, pMixedCtx); break;
10170 case DBGFEVENT_EXIT_WBINVD: VBOXVMM_EXIT_WBINVD(pVCpu, pMixedCtx); break;
10171 case DBGFEVENT_EXIT_XSETBV: VBOXVMM_EXIT_XSETBV(pVCpu, pMixedCtx); break;
10172 case DBGFEVENT_EXIT_RDRAND: VBOXVMM_EXIT_RDRAND(pVCpu, pMixedCtx); break;
10173 case DBGFEVENT_EXIT_RDSEED: VBOXVMM_EXIT_RDSEED(pVCpu, pMixedCtx); break;
10174 case DBGFEVENT_EXIT_XSAVES: VBOXVMM_EXIT_XSAVES(pVCpu, pMixedCtx); break;
10175 case DBGFEVENT_EXIT_XRSTORS: VBOXVMM_EXIT_XRSTORS(pVCpu, pMixedCtx); break;
10176 case DBGFEVENT_EXIT_VMM_CALL: VBOXVMM_EXIT_VMM_CALL(pVCpu, pMixedCtx); break;
10177 case DBGFEVENT_EXIT_VMX_VMCLEAR: VBOXVMM_EXIT_VMX_VMCLEAR(pVCpu, pMixedCtx); break;
10178 case DBGFEVENT_EXIT_VMX_VMLAUNCH: VBOXVMM_EXIT_VMX_VMLAUNCH(pVCpu, pMixedCtx); break;
10179 case DBGFEVENT_EXIT_VMX_VMPTRLD: VBOXVMM_EXIT_VMX_VMPTRLD(pVCpu, pMixedCtx); break;
10180 case DBGFEVENT_EXIT_VMX_VMPTRST: VBOXVMM_EXIT_VMX_VMPTRST(pVCpu, pMixedCtx); break;
10181 case DBGFEVENT_EXIT_VMX_VMREAD: VBOXVMM_EXIT_VMX_VMREAD(pVCpu, pMixedCtx); break;
10182 case DBGFEVENT_EXIT_VMX_VMRESUME: VBOXVMM_EXIT_VMX_VMRESUME(pVCpu, pMixedCtx); break;
10183 case DBGFEVENT_EXIT_VMX_VMWRITE: VBOXVMM_EXIT_VMX_VMWRITE(pVCpu, pMixedCtx); break;
10184 case DBGFEVENT_EXIT_VMX_VMXOFF: VBOXVMM_EXIT_VMX_VMXOFF(pVCpu, pMixedCtx); break;
10185 case DBGFEVENT_EXIT_VMX_VMXON: VBOXVMM_EXIT_VMX_VMXON(pVCpu, pMixedCtx); break;
10186 case DBGFEVENT_EXIT_VMX_INVEPT: VBOXVMM_EXIT_VMX_INVEPT(pVCpu, pMixedCtx); break;
10187 case DBGFEVENT_EXIT_VMX_INVVPID: VBOXVMM_EXIT_VMX_INVVPID(pVCpu, pMixedCtx); break;
10188 case DBGFEVENT_EXIT_VMX_INVPCID: VBOXVMM_EXIT_VMX_INVPCID(pVCpu, pMixedCtx); break;
10189 case DBGFEVENT_EXIT_VMX_VMFUNC: VBOXVMM_EXIT_VMX_VMFUNC(pVCpu, pMixedCtx); break;
10190 case DBGFEVENT_EXIT_VMX_EPT_MISCONFIG: VBOXVMM_EXIT_VMX_EPT_MISCONFIG(pVCpu, pMixedCtx); break;
10191 case DBGFEVENT_EXIT_VMX_EPT_VIOLATION: VBOXVMM_EXIT_VMX_EPT_VIOLATION(pVCpu, pMixedCtx); break;
10192 case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pMixedCtx); break;
10193 case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pMixedCtx); break;
10194 default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break;
10195 }
10196 }
10197
10198 /*
10199 * Fire of the DBGF event, if enabled (our check here is just a quick one,
10200 * the DBGF call will do a full check).
10201 *
10202 * Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap.
10203 * Note! If we have to events, we prioritize the first, i.e. the instruction
10204 * one, in order to avoid event nesting.
10205 */
10206 if ( enmEvent1 != DBGFEVENT_END
10207 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
10208 {
10209 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent1, uEventArg, DBGFEVENTCTX_HM);
10210 if (rcStrict != VINF_SUCCESS)
10211 return rcStrict;
10212 }
10213 else if ( enmEvent2 != DBGFEVENT_END
10214 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent2))
10215 {
10216 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent2, uEventArg, DBGFEVENTCTX_HM);
10217 if (rcStrict != VINF_SUCCESS)
10218 return rcStrict;
10219 }
10220
10221 return VINF_SUCCESS;
10222}
10223
10224
10225/**
10226 * Single-stepping VM-exit filtering.
10227 *
10228 * This is preprocessing the VM-exits and deciding whether we've gotten far
10229 * enough to return VINF_EM_DBG_STEPPED already. If not, normal VM-exit
10230 * handling is performed.
10231 *
10232 * @returns Strict VBox status code (i.e. informational status codes too).
10233 * @param pVM The cross context VM structure.
10234 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
10235 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
10236 * out-of-sync. Make sure to update the required
10237 * fields before using them.
10238 * @param pVmxTransient Pointer to the VMX-transient structure.
10239 * @param uExitReason The VM-exit reason.
10240 * @param pDbgState The debug state.
10241 */
10242DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient,
10243 uint32_t uExitReason, PVMXRUNDBGSTATE pDbgState)
10244{
10245 /*
10246 * Expensive (saves context) generic dtrace VM-exit probe.
10247 */
10248 if (!VBOXVMM_R0_HMVMX_VMEXIT_ENABLED())
10249 { /* more likely */ }
10250 else
10251 {
10252 hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
10253 hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
10254 VBOXVMM_R0_HMVMX_VMEXIT(pVCpu, pMixedCtx, pVmxTransient->uExitReason, pVmxTransient->uExitQualification);
10255 }
10256
10257 /*
10258 * Check for host NMI, just to get that out of the way.
10259 */
10260 if (uExitReason != VMX_EXIT_XCPT_OR_NMI)
10261 { /* normally likely */ }
10262 else
10263 {
10264 int rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
10265 AssertRCReturn(rc2, rc2);
10266 uint32_t uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo);
10267 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
10268 return hmR0VmxExitXcptOrNmi(pVCpu, pMixedCtx, pVmxTransient);
10269 }
10270
10271 /*
10272 * Check for single stepping event if we're stepping.
10273 */
10274 if (pVCpu->hm.s.fSingleInstruction)
10275 {
10276 switch (uExitReason)
10277 {
10278 case VMX_EXIT_MTF:
10279 return hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient);
10280
10281 /* Various events: */
10282 case VMX_EXIT_XCPT_OR_NMI:
10283 case VMX_EXIT_EXT_INT:
10284 case VMX_EXIT_TRIPLE_FAULT:
10285 case VMX_EXIT_INT_WINDOW:
10286 case VMX_EXIT_NMI_WINDOW:
10287 case VMX_EXIT_TASK_SWITCH:
10288 case VMX_EXIT_TPR_BELOW_THRESHOLD:
10289 case VMX_EXIT_APIC_ACCESS:
10290 case VMX_EXIT_EPT_VIOLATION:
10291 case VMX_EXIT_EPT_MISCONFIG:
10292 case VMX_EXIT_PREEMPT_TIMER:
10293
10294 /* Instruction specific VM-exits: */
10295 case VMX_EXIT_CPUID:
10296 case VMX_EXIT_GETSEC:
10297 case VMX_EXIT_HLT:
10298 case VMX_EXIT_INVD:
10299 case VMX_EXIT_INVLPG:
10300 case VMX_EXIT_RDPMC:
10301 case VMX_EXIT_RDTSC:
10302 case VMX_EXIT_RSM:
10303 case VMX_EXIT_VMCALL:
10304 case VMX_EXIT_VMCLEAR:
10305 case VMX_EXIT_VMLAUNCH:
10306 case VMX_EXIT_VMPTRLD:
10307 case VMX_EXIT_VMPTRST:
10308 case VMX_EXIT_VMREAD:
10309 case VMX_EXIT_VMRESUME:
10310 case VMX_EXIT_VMWRITE:
10311 case VMX_EXIT_VMXOFF:
10312 case VMX_EXIT_VMXON:
10313 case VMX_EXIT_MOV_CRX:
10314 case VMX_EXIT_MOV_DRX:
10315 case VMX_EXIT_IO_INSTR:
10316 case VMX_EXIT_RDMSR:
10317 case VMX_EXIT_WRMSR:
10318 case VMX_EXIT_MWAIT:
10319 case VMX_EXIT_MONITOR:
10320 case VMX_EXIT_PAUSE:
10321 case VMX_EXIT_XDTR_ACCESS:
10322 case VMX_EXIT_TR_ACCESS:
10323 case VMX_EXIT_INVEPT:
10324 case VMX_EXIT_RDTSCP:
10325 case VMX_EXIT_INVVPID:
10326 case VMX_EXIT_WBINVD:
10327 case VMX_EXIT_XSETBV:
10328 case VMX_EXIT_RDRAND:
10329 case VMX_EXIT_INVPCID:
10330 case VMX_EXIT_VMFUNC:
10331 case VMX_EXIT_RDSEED:
10332 case VMX_EXIT_XSAVES:
10333 case VMX_EXIT_XRSTORS:
10334 {
10335 int rc2 = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
10336 rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
10337 AssertRCReturn(rc2, rc2);
10338 if ( pMixedCtx->rip != pDbgState->uRipStart
10339 || pMixedCtx->cs.Sel != pDbgState->uCsStart)
10340 return VINF_EM_DBG_STEPPED;
10341 break;
10342 }
10343
10344 /* Errors and unexpected events: */
10345 case VMX_EXIT_INIT_SIGNAL:
10346 case VMX_EXIT_SIPI:
10347 case VMX_EXIT_IO_SMI:
10348 case VMX_EXIT_SMI:
10349 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
10350 case VMX_EXIT_ERR_MSR_LOAD:
10351 case VMX_EXIT_ERR_MACHINE_CHECK:
10352 case VMX_EXIT_APIC_WRITE: /* Some talk about this being fault like, so I guess we must process it? */
10353 break;
10354
10355 default:
10356 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
10357 break;
10358 }
10359 }
10360
10361 /*
10362 * Check for debugger event breakpoints and dtrace probes.
10363 */
10364 if ( uExitReason < RT_ELEMENTS(pDbgState->bmExitsToCheck) * 32U
10365 && ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
10366 {
10367 VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVM, pVCpu, pMixedCtx, pVmxTransient, uExitReason);
10368 if (rcStrict != VINF_SUCCESS)
10369 return rcStrict;
10370 }
10371
10372 /*
10373 * Normal processing.
10374 */
10375#ifdef HMVMX_USE_FUNCTION_TABLE
10376 return g_apfnVMExitHandlers[uExitReason](pVCpu, pMixedCtx, pVmxTransient);
10377#else
10378 return hmR0VmxHandleExit(pVCpu, pMixedCtx, pVmxTransient, uExitReason);
10379#endif
10380}
10381
10382
10383/**
10384 * Single steps guest code using VT-x.
10385 *
10386 * @returns Strict VBox status code (i.e. informational status codes too).
10387 * @param pVM The cross context VM structure.
10388 * @param pVCpu The cross context virtual CPU structure.
10389 * @param pCtx Pointer to the guest-CPU context.
10390 *
10391 * @note Mostly the same as hmR0VmxRunGuestCodeNormal().
10392 */
10393static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10394{
10395 VMXTRANSIENT VmxTransient;
10396 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
10397
10398 /* Set HMCPU indicators. */
10399 bool const fSavedSingleInstruction = pVCpu->hm.s.fSingleInstruction;
10400 pVCpu->hm.s.fSingleInstruction = pVCpu->hm.s.fSingleInstruction || DBGFIsStepping(pVCpu);
10401 pVCpu->hm.s.fDebugWantRdTscExit = false;
10402 pVCpu->hm.s.fUsingDebugLoop = true;
10403
10404 /* State we keep to help modify and later restore the VMCS fields we alter, and for detecting steps. */
10405 VMXRUNDBGSTATE DbgState;
10406 hmR0VmxRunDebugStateInit(pVCpu, pCtx, &DbgState);
10407 hmR0VmxPreRunGuestDebugStateUpdate(pVM, pVCpu, pCtx, &DbgState, &VmxTransient);
10408
10409 /*
10410 * The loop.
10411 */
10412 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
10413 for (uint32_t cLoops = 0; ; cLoops++)
10414 {
10415 Assert(!HMR0SuspendPending());
10416 HMVMX_ASSERT_CPU_SAFE();
10417 bool fStepping = pVCpu->hm.s.fSingleInstruction;
10418
10419 /*
10420 * Preparatory work for running guest code, this may force us to return
10421 * to ring-3. This bugger disables interrupts on VINF_SUCCESS!
10422 */
10423 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
10424 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Set up execute controls the next to can respond to. */
10425 rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, fStepping);
10426 if (rcStrict != VINF_SUCCESS)
10427 break;
10428
10429 hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
10430 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Override any obnoxious code in the above two calls. */
10431
10432 /*
10433 * Now we can run the guest code.
10434 */
10435 int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
10436
10437 /* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
10438
10439 /*
10440 * Restore any residual host-state and save any bits shared between host
10441 * and guest into the guest-CPU state. Re-enables interrupts!
10442 */
10443 hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rcRun);
10444
10445 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
10446 if (RT_SUCCESS(rcRun))
10447 { /* very likely */ }
10448 else
10449 {
10450 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
10451 hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
10452 return rcRun;
10453 }
10454
10455 /* Profile the VM-exit. */
10456 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
10457 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
10458 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
10459 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
10460 HMVMX_START_EXIT_DISPATCH_PROF();
10461
10462 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, pCtx, VmxTransient.uExitReason);
10463
10464 /*
10465 * Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
10466 */
10467 rcStrict = hmR0VmxRunDebugHandleExit(pVM, pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason, &DbgState);
10468 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
10469 if (rcStrict != VINF_SUCCESS)
10470 break;
10471 if (cLoops > pVM->hm.s.cMaxResumeLoops)
10472 {
10473 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
10474 rcStrict = VINF_EM_RAW_INTERRUPT;
10475 break;
10476 }
10477
10478 /*
10479 * Stepping: Did the RIP change, if so, consider it a single step.
10480 * Otherwise, make sure one of the TFs gets set.
10481 */
10482 if (fStepping)
10483 {
10484 int rc2 = hmR0VmxSaveGuestRip(pVCpu, pCtx);
10485 rc2 |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pCtx);
10486 AssertRCReturn(rc2, rc2);
10487 if ( pCtx->rip != DbgState.uRipStart
10488 || pCtx->cs.Sel != DbgState.uCsStart)
10489 {
10490 rcStrict = VINF_EM_DBG_STEPPED;
10491 break;
10492 }
10493 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
10494 }
10495
10496 /*
10497 * Update when dtrace settings changes (DBGF kicks us, so no need to check).
10498 */
10499 if (VBOXVMM_GET_SETTINGS_SEQ_NO() != DbgState.uDtraceSettingsSeqNo)
10500 hmR0VmxPreRunGuestDebugStateUpdate(pVM, pVCpu, pCtx, &DbgState, &VmxTransient);
10501 }
10502
10503 /*
10504 * Clear the X86_EFL_TF if necessary.
10505 */
10506 if (pVCpu->hm.s.fClearTrapFlag)
10507 {
10508 int rc2 = hmR0VmxSaveGuestRflags(pVCpu, pCtx);
10509 AssertRCReturn(rc2, rc2);
10510 pVCpu->hm.s.fClearTrapFlag = false;
10511 pCtx->eflags.Bits.u1TF = 0;
10512 }
10513 /** @todo there seems to be issues with the resume flag when the monitor trap
10514 * flag is pending without being used. Seen early in bios init when
10515 * accessing APIC page in protected mode. */
10516
10517 /*
10518 * Restore VM-exit control settings as we may not reenter this function the
10519 * next time around.
10520 */
10521 rcStrict = hmR0VmxRunDebugStateRevert(pVCpu, &DbgState, rcStrict);
10522
10523 /* Restore HMCPU indicators. */
10524 pVCpu->hm.s.fUsingDebugLoop = false;
10525 pVCpu->hm.s.fDebugWantRdTscExit = false;
10526 pVCpu->hm.s.fSingleInstruction = fSavedSingleInstruction;
10527
10528 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
10529 return rcStrict;
10530}
10531
10532
10533/** @} */
10534
10535
10536/**
10537 * Checks if any expensive dtrace probes are enabled and we should go to the
10538 * debug loop.
10539 *
10540 * @returns true if we should use debug loop, false if not.
10541 */
10542static bool hmR0VmxAnyExpensiveProbesEnabled(void)
10543{
10544 /* It's probably faster to OR the raw 32-bit counter variables together.
10545 Since the variables are in an array and the probes are next to one
10546 another (more or less), we have good locality. So, better read
10547 eight-nine cache lines ever time and only have one conditional, than
10548 128+ conditionals, right? */
10549 return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */
10550 | VBOXVMM_XCPT_DE_ENABLED_RAW()
10551 | VBOXVMM_XCPT_DB_ENABLED_RAW()
10552 | VBOXVMM_XCPT_BP_ENABLED_RAW()
10553 | VBOXVMM_XCPT_OF_ENABLED_RAW()
10554 | VBOXVMM_XCPT_BR_ENABLED_RAW()
10555 | VBOXVMM_XCPT_UD_ENABLED_RAW()
10556 | VBOXVMM_XCPT_NM_ENABLED_RAW()
10557 | VBOXVMM_XCPT_DF_ENABLED_RAW()
10558 | VBOXVMM_XCPT_TS_ENABLED_RAW()
10559 | VBOXVMM_XCPT_NP_ENABLED_RAW()
10560 | VBOXVMM_XCPT_SS_ENABLED_RAW()
10561 | VBOXVMM_XCPT_GP_ENABLED_RAW()
10562 | VBOXVMM_XCPT_PF_ENABLED_RAW()
10563 | VBOXVMM_XCPT_MF_ENABLED_RAW()
10564 | VBOXVMM_XCPT_AC_ENABLED_RAW()
10565 | VBOXVMM_XCPT_XF_ENABLED_RAW()
10566 | VBOXVMM_XCPT_VE_ENABLED_RAW()
10567 | VBOXVMM_XCPT_SX_ENABLED_RAW()
10568 | VBOXVMM_INT_SOFTWARE_ENABLED_RAW()
10569 | VBOXVMM_INT_HARDWARE_ENABLED_RAW()
10570 ) != 0
10571 || ( VBOXVMM_INSTR_HALT_ENABLED_RAW()
10572 | VBOXVMM_INSTR_MWAIT_ENABLED_RAW()
10573 | VBOXVMM_INSTR_MONITOR_ENABLED_RAW()
10574 | VBOXVMM_INSTR_CPUID_ENABLED_RAW()
10575 | VBOXVMM_INSTR_INVD_ENABLED_RAW()
10576 | VBOXVMM_INSTR_WBINVD_ENABLED_RAW()
10577 | VBOXVMM_INSTR_INVLPG_ENABLED_RAW()
10578 | VBOXVMM_INSTR_RDTSC_ENABLED_RAW()
10579 | VBOXVMM_INSTR_RDTSCP_ENABLED_RAW()
10580 | VBOXVMM_INSTR_RDPMC_ENABLED_RAW()
10581 | VBOXVMM_INSTR_RDMSR_ENABLED_RAW()
10582 | VBOXVMM_INSTR_WRMSR_ENABLED_RAW()
10583 | VBOXVMM_INSTR_CRX_READ_ENABLED_RAW()
10584 | VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW()
10585 | VBOXVMM_INSTR_DRX_READ_ENABLED_RAW()
10586 | VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW()
10587 | VBOXVMM_INSTR_PAUSE_ENABLED_RAW()
10588 | VBOXVMM_INSTR_XSETBV_ENABLED_RAW()
10589 | VBOXVMM_INSTR_SIDT_ENABLED_RAW()
10590 | VBOXVMM_INSTR_LIDT_ENABLED_RAW()
10591 | VBOXVMM_INSTR_SGDT_ENABLED_RAW()
10592 | VBOXVMM_INSTR_LGDT_ENABLED_RAW()
10593 | VBOXVMM_INSTR_SLDT_ENABLED_RAW()
10594 | VBOXVMM_INSTR_LLDT_ENABLED_RAW()
10595 | VBOXVMM_INSTR_STR_ENABLED_RAW()
10596 | VBOXVMM_INSTR_LTR_ENABLED_RAW()
10597 | VBOXVMM_INSTR_GETSEC_ENABLED_RAW()
10598 | VBOXVMM_INSTR_RSM_ENABLED_RAW()
10599 | VBOXVMM_INSTR_RDRAND_ENABLED_RAW()
10600 | VBOXVMM_INSTR_RDSEED_ENABLED_RAW()
10601 | VBOXVMM_INSTR_XSAVES_ENABLED_RAW()
10602 | VBOXVMM_INSTR_XRSTORS_ENABLED_RAW()
10603 | VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW()
10604 | VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW()
10605 | VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW()
10606 | VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW()
10607 | VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW()
10608 | VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW()
10609 | VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW()
10610 | VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW()
10611 | VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW()
10612 | VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW()
10613 | VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW()
10614 | VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW()
10615 | VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW()
10616 | VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW()
10617 ) != 0
10618 || ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW()
10619 | VBOXVMM_EXIT_HALT_ENABLED_RAW()
10620 | VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
10621 | VBOXVMM_EXIT_MONITOR_ENABLED_RAW()
10622 | VBOXVMM_EXIT_CPUID_ENABLED_RAW()
10623 | VBOXVMM_EXIT_INVD_ENABLED_RAW()
10624 | VBOXVMM_EXIT_WBINVD_ENABLED_RAW()
10625 | VBOXVMM_EXIT_INVLPG_ENABLED_RAW()
10626 | VBOXVMM_EXIT_RDTSC_ENABLED_RAW()
10627 | VBOXVMM_EXIT_RDTSCP_ENABLED_RAW()
10628 | VBOXVMM_EXIT_RDPMC_ENABLED_RAW()
10629 | VBOXVMM_EXIT_RDMSR_ENABLED_RAW()
10630 | VBOXVMM_EXIT_WRMSR_ENABLED_RAW()
10631 | VBOXVMM_EXIT_CRX_READ_ENABLED_RAW()
10632 | VBOXVMM_EXIT_CRX_WRITE_ENABLED_RAW()
10633 | VBOXVMM_EXIT_DRX_READ_ENABLED_RAW()
10634 | VBOXVMM_EXIT_DRX_WRITE_ENABLED_RAW()
10635 | VBOXVMM_EXIT_PAUSE_ENABLED_RAW()
10636 | VBOXVMM_EXIT_XSETBV_ENABLED_RAW()
10637 | VBOXVMM_EXIT_SIDT_ENABLED_RAW()
10638 | VBOXVMM_EXIT_LIDT_ENABLED_RAW()
10639 | VBOXVMM_EXIT_SGDT_ENABLED_RAW()
10640 | VBOXVMM_EXIT_LGDT_ENABLED_RAW()
10641 | VBOXVMM_EXIT_SLDT_ENABLED_RAW()
10642 | VBOXVMM_EXIT_LLDT_ENABLED_RAW()
10643 | VBOXVMM_EXIT_STR_ENABLED_RAW()
10644 | VBOXVMM_EXIT_LTR_ENABLED_RAW()
10645 | VBOXVMM_EXIT_GETSEC_ENABLED_RAW()
10646 | VBOXVMM_EXIT_RSM_ENABLED_RAW()
10647 | VBOXVMM_EXIT_RDRAND_ENABLED_RAW()
10648 | VBOXVMM_EXIT_RDSEED_ENABLED_RAW()
10649 | VBOXVMM_EXIT_XSAVES_ENABLED_RAW()
10650 | VBOXVMM_EXIT_XRSTORS_ENABLED_RAW()
10651 | VBOXVMM_EXIT_VMM_CALL_ENABLED_RAW()
10652 | VBOXVMM_EXIT_VMX_VMCLEAR_ENABLED_RAW()
10653 | VBOXVMM_EXIT_VMX_VMLAUNCH_ENABLED_RAW()
10654 | VBOXVMM_EXIT_VMX_VMPTRLD_ENABLED_RAW()
10655 | VBOXVMM_EXIT_VMX_VMPTRST_ENABLED_RAW()
10656 | VBOXVMM_EXIT_VMX_VMREAD_ENABLED_RAW()
10657 | VBOXVMM_EXIT_VMX_VMRESUME_ENABLED_RAW()
10658 | VBOXVMM_EXIT_VMX_VMWRITE_ENABLED_RAW()
10659 | VBOXVMM_EXIT_VMX_VMXOFF_ENABLED_RAW()
10660 | VBOXVMM_EXIT_VMX_VMXON_ENABLED_RAW()
10661 | VBOXVMM_EXIT_VMX_VMFUNC_ENABLED_RAW()
10662 | VBOXVMM_EXIT_VMX_INVEPT_ENABLED_RAW()
10663 | VBOXVMM_EXIT_VMX_INVVPID_ENABLED_RAW()
10664 | VBOXVMM_EXIT_VMX_INVPCID_ENABLED_RAW()
10665 | VBOXVMM_EXIT_VMX_EPT_VIOLATION_ENABLED_RAW()
10666 | VBOXVMM_EXIT_VMX_EPT_MISCONFIG_ENABLED_RAW()
10667 | VBOXVMM_EXIT_VMX_VAPIC_ACCESS_ENABLED_RAW()
10668 | VBOXVMM_EXIT_VMX_VAPIC_WRITE_ENABLED_RAW()
10669 ) != 0;
10670}
10671
10672
10673/**
10674 * Runs the guest code using VT-x.
10675 *
10676 * @returns Strict VBox status code (i.e. informational status codes too).
10677 * @param pVM The cross context VM structure.
10678 * @param pVCpu The cross context virtual CPU structure.
10679 * @param pCtx Pointer to the guest-CPU context.
10680 */
10681VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10682{
10683 Assert(VMMRZCallRing3IsEnabled(pVCpu));
10684 Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
10685 HMVMX_ASSERT_PREEMPT_SAFE();
10686
10687 VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
10688
10689 VBOXSTRICTRC rcStrict;
10690 if ( !pVCpu->hm.s.fUseDebugLoop
10691 && (!VBOXVMM_ANY_PROBES_ENABLED() || !hmR0VmxAnyExpensiveProbesEnabled())
10692 && !DBGFIsStepping(pVCpu)
10693 && !pVM->dbgf.ro.cEnabledInt3Breakpoints)
10694 rcStrict = hmR0VmxRunGuestCodeNormal(pVM, pVCpu, pCtx);
10695 else
10696 rcStrict = hmR0VmxRunGuestCodeDebug(pVM, pVCpu, pCtx);
10697
10698 if (rcStrict == VERR_EM_INTERPRETER)
10699 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
10700 else if (rcStrict == VINF_EM_RESET)
10701 rcStrict = VINF_EM_TRIPLE_FAULT;
10702
10703 int rc2 = hmR0VmxExitToRing3(pVM, pVCpu, pCtx, rcStrict);
10704 if (RT_FAILURE(rc2))
10705 {
10706 pVCpu->hm.s.u32HMError = (uint32_t)VBOXSTRICTRC_VAL(rcStrict);
10707 rcStrict = rc2;
10708 }
10709 Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
10710 return rcStrict;
10711}
10712
10713
10714#ifndef HMVMX_USE_FUNCTION_TABLE
10715DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason)
10716{
10717# ifdef DEBUG_ramshankar
10718# define RETURN_EXIT_CALL(a_CallExpr) \
10719 do { \
10720 int rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx); AssertRC(rc2); \
10721 VBOXSTRICTRC rcStrict = a_CallExpr; \
10722 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); \
10723 return rcStrict; \
10724 } while (0)
10725# else
10726# define RETURN_EXIT_CALL(a_CallExpr) return a_CallExpr
10727# endif
10728 switch (rcReason)
10729 {
10730 case VMX_EXIT_EPT_MISCONFIG: RETURN_EXIT_CALL(hmR0VmxExitEptMisconfig(pVCpu, pMixedCtx, pVmxTransient));
10731 case VMX_EXIT_EPT_VIOLATION: RETURN_EXIT_CALL(hmR0VmxExitEptViolation(pVCpu, pMixedCtx, pVmxTransient));
10732 case VMX_EXIT_IO_INSTR: RETURN_EXIT_CALL(hmR0VmxExitIoInstr(pVCpu, pMixedCtx, pVmxTransient));
10733 case VMX_EXIT_CPUID: RETURN_EXIT_CALL(hmR0VmxExitCpuid(pVCpu, pMixedCtx, pVmxTransient));
10734 case VMX_EXIT_RDTSC: RETURN_EXIT_CALL(hmR0VmxExitRdtsc(pVCpu, pMixedCtx, pVmxTransient));
10735 case VMX_EXIT_RDTSCP: RETURN_EXIT_CALL(hmR0VmxExitRdtscp(pVCpu, pMixedCtx, pVmxTransient));
10736 case VMX_EXIT_APIC_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitApicAccess(pVCpu, pMixedCtx, pVmxTransient));
10737 case VMX_EXIT_XCPT_OR_NMI: RETURN_EXIT_CALL(hmR0VmxExitXcptOrNmi(pVCpu, pMixedCtx, pVmxTransient));
10738 case VMX_EXIT_MOV_CRX: RETURN_EXIT_CALL(hmR0VmxExitMovCRx(pVCpu, pMixedCtx, pVmxTransient));
10739 case VMX_EXIT_EXT_INT: RETURN_EXIT_CALL(hmR0VmxExitExtInt(pVCpu, pMixedCtx, pVmxTransient));
10740 case VMX_EXIT_INT_WINDOW: RETURN_EXIT_CALL(hmR0VmxExitIntWindow(pVCpu, pMixedCtx, pVmxTransient));
10741 case VMX_EXIT_MWAIT: RETURN_EXIT_CALL(hmR0VmxExitMwait(pVCpu, pMixedCtx, pVmxTransient));
10742 case VMX_EXIT_MONITOR: RETURN_EXIT_CALL(hmR0VmxExitMonitor(pVCpu, pMixedCtx, pVmxTransient));
10743 case VMX_EXIT_TASK_SWITCH: RETURN_EXIT_CALL(hmR0VmxExitTaskSwitch(pVCpu, pMixedCtx, pVmxTransient));
10744 case VMX_EXIT_PREEMPT_TIMER: RETURN_EXIT_CALL(hmR0VmxExitPreemptTimer(pVCpu, pMixedCtx, pVmxTransient));
10745 case VMX_EXIT_RDMSR: RETURN_EXIT_CALL(hmR0VmxExitRdmsr(pVCpu, pMixedCtx, pVmxTransient));
10746 case VMX_EXIT_WRMSR: RETURN_EXIT_CALL(hmR0VmxExitWrmsr(pVCpu, pMixedCtx, pVmxTransient));
10747 case VMX_EXIT_MOV_DRX: RETURN_EXIT_CALL(hmR0VmxExitMovDRx(pVCpu, pMixedCtx, pVmxTransient));
10748 case VMX_EXIT_TPR_BELOW_THRESHOLD: RETURN_EXIT_CALL(hmR0VmxExitTprBelowThreshold(pVCpu, pMixedCtx, pVmxTransient));
10749 case VMX_EXIT_HLT: RETURN_EXIT_CALL(hmR0VmxExitHlt(pVCpu, pMixedCtx, pVmxTransient));
10750 case VMX_EXIT_INVD: RETURN_EXIT_CALL(hmR0VmxExitInvd(pVCpu, pMixedCtx, pVmxTransient));
10751 case VMX_EXIT_INVLPG: RETURN_EXIT_CALL(hmR0VmxExitInvlpg(pVCpu, pMixedCtx, pVmxTransient));
10752 case VMX_EXIT_RSM: RETURN_EXIT_CALL(hmR0VmxExitRsm(pVCpu, pMixedCtx, pVmxTransient));
10753 case VMX_EXIT_MTF: RETURN_EXIT_CALL(hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient));
10754 case VMX_EXIT_PAUSE: RETURN_EXIT_CALL(hmR0VmxExitPause(pVCpu, pMixedCtx, pVmxTransient));
10755 case VMX_EXIT_XDTR_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient));
10756 case VMX_EXIT_TR_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient));
10757 case VMX_EXIT_WBINVD: RETURN_EXIT_CALL(hmR0VmxExitWbinvd(pVCpu, pMixedCtx, pVmxTransient));
10758 case VMX_EXIT_XSETBV: RETURN_EXIT_CALL(hmR0VmxExitXsetbv(pVCpu, pMixedCtx, pVmxTransient));
10759 case VMX_EXIT_RDRAND: RETURN_EXIT_CALL(hmR0VmxExitRdrand(pVCpu, pMixedCtx, pVmxTransient));
10760 case VMX_EXIT_INVPCID: RETURN_EXIT_CALL(hmR0VmxExitInvpcid(pVCpu, pMixedCtx, pVmxTransient));
10761 case VMX_EXIT_GETSEC: RETURN_EXIT_CALL(hmR0VmxExitGetsec(pVCpu, pMixedCtx, pVmxTransient));
10762 case VMX_EXIT_RDPMC: RETURN_EXIT_CALL(hmR0VmxExitRdpmc(pVCpu, pMixedCtx, pVmxTransient));
10763 case VMX_EXIT_VMCALL: RETURN_EXIT_CALL(hmR0VmxExitVmcall(pVCpu, pMixedCtx, pVmxTransient));
10764
10765 case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFault(pVCpu, pMixedCtx, pVmxTransient);
10766 case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindow(pVCpu, pMixedCtx, pVmxTransient);
10767 case VMX_EXIT_INIT_SIGNAL: return hmR0VmxExitInitSignal(pVCpu, pMixedCtx, pVmxTransient);
10768 case VMX_EXIT_SIPI: return hmR0VmxExitSipi(pVCpu, pMixedCtx, pVmxTransient);
10769 case VMX_EXIT_IO_SMI: return hmR0VmxExitIoSmi(pVCpu, pMixedCtx, pVmxTransient);
10770 case VMX_EXIT_SMI: return hmR0VmxExitSmi(pVCpu, pMixedCtx, pVmxTransient);
10771 case VMX_EXIT_ERR_MSR_LOAD: return hmR0VmxExitErrMsrLoad(pVCpu, pMixedCtx, pVmxTransient);
10772 case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestState(pVCpu, pMixedCtx, pVmxTransient);
10773 case VMX_EXIT_ERR_MACHINE_CHECK: return hmR0VmxExitErrMachineCheck(pVCpu, pMixedCtx, pVmxTransient);
10774
10775 case VMX_EXIT_VMCLEAR:
10776 case VMX_EXIT_VMLAUNCH:
10777 case VMX_EXIT_VMPTRLD:
10778 case VMX_EXIT_VMPTRST:
10779 case VMX_EXIT_VMREAD:
10780 case VMX_EXIT_VMRESUME:
10781 case VMX_EXIT_VMWRITE:
10782 case VMX_EXIT_VMXOFF:
10783 case VMX_EXIT_VMXON:
10784 case VMX_EXIT_INVEPT:
10785 case VMX_EXIT_INVVPID:
10786 case VMX_EXIT_VMFUNC:
10787 case VMX_EXIT_XSAVES:
10788 case VMX_EXIT_XRSTORS:
10789 return hmR0VmxExitSetPendingXcptUD(pVCpu, pMixedCtx, pVmxTransient);
10790 case VMX_EXIT_ENCLS:
10791 case VMX_EXIT_RDSEED: /* only spurious VM-exits, so undefined */
10792 case VMX_EXIT_PML_FULL:
10793 default:
10794 return hmR0VmxExitErrUndefined(pVCpu, pMixedCtx, pVmxTransient);
10795 }
10796#undef RETURN_EXIT_CALL
10797}
10798#endif /* !HMVMX_USE_FUNCTION_TABLE */
10799
10800
10801#ifdef VBOX_STRICT
10802/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
10803# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
10804 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
10805
10806# define HMVMX_ASSERT_PREEMPT_CPUID() \
10807 do { \
10808 RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
10809 AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
10810 } while (0)
10811
10812# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
10813 do { \
10814 AssertPtr(pVCpu); \
10815 AssertPtr(pMixedCtx); \
10816 AssertPtr(pVmxTransient); \
10817 Assert(pVmxTransient->fVMEntryFailed == false); \
10818 Assert(ASMIntAreEnabled()); \
10819 HMVMX_ASSERT_PREEMPT_SAFE(); \
10820 HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
10821 Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", pVCpu->idCpu)); \
10822 HMVMX_ASSERT_PREEMPT_SAFE(); \
10823 if (VMMR0IsLogFlushDisabled(pVCpu)) \
10824 HMVMX_ASSERT_PREEMPT_CPUID(); \
10825 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10826 } while (0)
10827
10828# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() \
10829 do { \
10830 Log4Func(("\n")); \
10831 } while (0)
10832#else /* nonstrict builds: */
10833# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
10834 do { \
10835 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10836 NOREF(pVCpu); NOREF(pMixedCtx); NOREF(pVmxTransient); \
10837 } while (0)
10838# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() do { } while (0)
10839#endif
10840
10841
10842/**
10843 * Advances the guest RIP by the specified number of bytes.
10844 *
10845 * @param pVCpu The cross context virtual CPU structure.
10846 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
10847 * out-of-sync. Make sure to update the required fields
10848 * before using them.
10849 * @param cbInstr Number of bytes to advance the RIP by.
10850 *
10851 * @remarks No-long-jump zone!!!
10852 */
10853DECLINLINE(void) hmR0VmxAdvanceGuestRipBy(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr)
10854{
10855 /* Advance the RIP. */
10856 pMixedCtx->rip += cbInstr;
10857 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
10858
10859 /* Update interrupt inhibition. */
10860 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10861 && pMixedCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
10862 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
10863}
10864
10865
10866/**
10867 * Advances the guest RIP after reading it from the VMCS.
10868 *
10869 * @returns VBox status code, no informational status codes.
10870 * @param pVCpu The cross context virtual CPU structure.
10871 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
10872 * out-of-sync. Make sure to update the required fields
10873 * before using them.
10874 * @param pVmxTransient Pointer to the VMX transient structure.
10875 *
10876 * @remarks No-long-jump zone!!!
10877 */
10878static int hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10879{
10880 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
10881 rc |= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
10882 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
10883 AssertRCReturn(rc, rc);
10884
10885 hmR0VmxAdvanceGuestRipBy(pVCpu, pMixedCtx, pVmxTransient->cbInstr);
10886
10887 /*
10888 * Deliver a debug exception to the guest if it is single-stepping. Don't directly inject a #DB but use the
10889 * pending debug exception field as it takes care of priority of events.
10890 *
10891 * See Intel spec. 32.2.1 "Debug Exceptions".
10892 */
10893 if ( !pVCpu->hm.s.fSingleInstruction
10894 && pMixedCtx->eflags.Bits.u1TF)
10895 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
10896
10897 return VINF_SUCCESS;
10898}
10899
10900
10901/**
10902 * Tries to determine what part of the guest-state VT-x has deemed as invalid
10903 * and update error record fields accordingly.
10904 *
10905 * @return VMX_IGS_* return codes.
10906 * @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
10907 * wrong with the guest state.
10908 *
10909 * @param pVM The cross context VM structure.
10910 * @param pVCpu The cross context virtual CPU structure.
10911 * @param pCtx Pointer to the guest-CPU state.
10912 *
10913 * @remarks This function assumes our cache of the VMCS controls
10914 * are valid, i.e. hmR0VmxCheckVmcsCtls() succeeded.
10915 */
10916static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10917{
10918#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
10919#define HMVMX_CHECK_BREAK(expr, err) if (!(expr)) { \
10920 uError = (err); \
10921 break; \
10922 } else do { } while (0)
10923
10924 int rc;
10925 uint32_t uError = VMX_IGS_ERROR;
10926 uint32_t u32Val;
10927 bool fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
10928
10929 do
10930 {
10931 /*
10932 * CR0.
10933 */
10934 uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10935 uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10936 /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG).
10937 See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
10938 if (fUnrestrictedGuest)
10939 uSetCR0 &= ~(X86_CR0_PE | X86_CR0_PG);
10940
10941 uint32_t u32GuestCR0;
10942 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32GuestCR0);
10943 AssertRCBreak(rc);
10944 HMVMX_CHECK_BREAK((u32GuestCR0 & uSetCR0) == uSetCR0, VMX_IGS_CR0_FIXED1);
10945 HMVMX_CHECK_BREAK(!(u32GuestCR0 & ~uZapCR0), VMX_IGS_CR0_FIXED0);
10946 if ( !fUnrestrictedGuest
10947 && (u32GuestCR0 & X86_CR0_PG)
10948 && !(u32GuestCR0 & X86_CR0_PE))
10949 {
10950 HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
10951 }
10952
10953 /*
10954 * CR4.
10955 */
10956 uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10957 uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10958
10959 uint32_t u32GuestCR4;
10960 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCR4);
10961 AssertRCBreak(rc);
10962 HMVMX_CHECK_BREAK((u32GuestCR4 & uSetCR4) == uSetCR4, VMX_IGS_CR4_FIXED1);
10963 HMVMX_CHECK_BREAK(!(u32GuestCR4 & ~uZapCR4), VMX_IGS_CR4_FIXED0);
10964
10965 /*
10966 * IA32_DEBUGCTL MSR.
10967 */
10968 uint64_t u64Val;
10969 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
10970 AssertRCBreak(rc);
10971 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
10972 && (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
10973 {
10974 HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
10975 }
10976 uint64_t u64DebugCtlMsr = u64Val;
10977
10978#ifdef VBOX_STRICT
10979 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
10980 AssertRCBreak(rc);
10981 Assert(u32Val == pVCpu->hm.s.vmx.u32EntryCtls);
10982#endif
10983 bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
10984
10985 /*
10986 * RIP and RFLAGS.
10987 */
10988 uint32_t u32Eflags;
10989#if HC_ARCH_BITS == 64
10990 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RIP, &u64Val);
10991 AssertRCBreak(rc);
10992 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
10993 if ( !fLongModeGuest
10994 || !pCtx->cs.Attr.n.u1Long)
10995 {
10996 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
10997 }
10998 /** @todo If the processor supports N < 64 linear-address bits, bits 63:N
10999 * must be identical if the "IA-32e mode guest" VM-entry
11000 * control is 1 and CS.L is 1. No check applies if the
11001 * CPU supports 64 linear-address bits. */
11002
11003 /* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
11004 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RFLAGS, &u64Val);
11005 AssertRCBreak(rc);
11006 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
11007 VMX_IGS_RFLAGS_RESERVED);
11008 HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
11009 u32Eflags = u64Val;
11010#else
11011 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Eflags);
11012 AssertRCBreak(rc);
11013 HMVMX_CHECK_BREAK(!(u32Eflags & 0xffc08028), VMX_IGS_RFLAGS_RESERVED); /* Bit 31:22, Bit 15, 5, 3 MBZ. */
11014 HMVMX_CHECK_BREAK((u32Eflags & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
11015#endif
11016
11017 if ( fLongModeGuest
11018 || ( fUnrestrictedGuest
11019 && !(u32GuestCR0 & X86_CR0_PE)))
11020 {
11021 HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
11022 }
11023
11024 uint32_t u32EntryInfo;
11025 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
11026 AssertRCBreak(rc);
11027 if ( VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo)
11028 && VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
11029 {
11030 HMVMX_CHECK_BREAK(u32Eflags & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
11031 }
11032
11033 /*
11034 * 64-bit checks.
11035 */
11036#if HC_ARCH_BITS == 64
11037 if (fLongModeGuest)
11038 {
11039 HMVMX_CHECK_BREAK(u32GuestCR0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE);
11040 HMVMX_CHECK_BREAK(u32GuestCR4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
11041 }
11042
11043 if ( !fLongModeGuest
11044 && (u32GuestCR4 & X86_CR4_PCIDE))
11045 {
11046 HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
11047 }
11048
11049 /** @todo CR3 field must be such that bits 63:52 and bits in the range
11050 * 51:32 beyond the processor's physical-address width are 0. */
11051
11052 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
11053 && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
11054 {
11055 HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
11056 }
11057
11058 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
11059 AssertRCBreak(rc);
11060 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
11061
11062 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
11063 AssertRCBreak(rc);
11064 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
11065#endif
11066
11067 /*
11068 * PERF_GLOBAL MSR.
11069 */
11070 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR)
11071 {
11072 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
11073 AssertRCBreak(rc);
11074 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
11075 VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
11076 }
11077
11078 /*
11079 * PAT MSR.
11080 */
11081 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR)
11082 {
11083 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
11084 AssertRCBreak(rc);
11085 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
11086 for (unsigned i = 0; i < 8; i++)
11087 {
11088 uint8_t u8Val = (u64Val & 0xff);
11089 if ( u8Val != 0 /* UC */
11090 && u8Val != 1 /* WC */
11091 && u8Val != 4 /* WT */
11092 && u8Val != 5 /* WP */
11093 && u8Val != 6 /* WB */
11094 && u8Val != 7 /* UC- */)
11095 {
11096 HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
11097 }
11098 u64Val >>= 8;
11099 }
11100 }
11101
11102 /*
11103 * EFER MSR.
11104 */
11105 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
11106 {
11107 Assert(pVM->hm.s.vmx.fSupportsVmcsEfer);
11108 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
11109 AssertRCBreak(rc);
11110 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
11111 VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
11112 HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL( pVCpu->hm.s.vmx.u32EntryCtls
11113 & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST),
11114 VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
11115 HMVMX_CHECK_BREAK( fUnrestrictedGuest
11116 || !(u32GuestCR0 & X86_CR0_PG)
11117 || RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(u64Val & MSR_K6_EFER_LME),
11118 VMX_IGS_EFER_LMA_LME_MISMATCH);
11119 }
11120
11121 /*
11122 * Segment registers.
11123 */
11124 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
11125 || !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
11126 if (!(u32Eflags & X86_EFL_VM))
11127 {
11128 /* CS */
11129 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
11130 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
11131 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
11132 HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
11133 || !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
11134 HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
11135 || (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
11136 /* CS cannot be loaded with NULL in protected mode. */
11137 HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
11138 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
11139 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
11140 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
11141 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
11142 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
11143 else if (pVM->hm.s.vmx.fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
11144 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
11145 else
11146 HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
11147
11148 /* SS */
11149 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
11150 || (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
11151 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
11152 if ( !(pCtx->cr0 & X86_CR0_PE)
11153 || pCtx->cs.Attr.n.u4Type == 3)
11154 {
11155 HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
11156 }
11157 if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
11158 {
11159 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
11160 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
11161 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
11162 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
11163 HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
11164 || !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
11165 HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
11166 || (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
11167 }
11168
11169 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
11170 if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
11171 {
11172 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
11173 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
11174 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
11175 || pCtx->ds.Attr.n.u4Type > 11
11176 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
11177 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
11178 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
11179 HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
11180 || !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
11181 HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
11182 || (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
11183 HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
11184 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
11185 }
11186 if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
11187 {
11188 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
11189 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
11190 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
11191 || pCtx->es.Attr.n.u4Type > 11
11192 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
11193 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
11194 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
11195 HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
11196 || !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
11197 HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
11198 || (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
11199 HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
11200 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
11201 }
11202 if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
11203 {
11204 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
11205 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
11206 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
11207 || pCtx->fs.Attr.n.u4Type > 11
11208 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
11209 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
11210 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
11211 HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
11212 || !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
11213 HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
11214 || (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
11215 HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
11216 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
11217 }
11218 if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
11219 {
11220 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
11221 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
11222 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
11223 || pCtx->gs.Attr.n.u4Type > 11
11224 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
11225 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
11226 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
11227 HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
11228 || !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
11229 HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
11230 || (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
11231 HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
11232 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
11233 }
11234 /* 64-bit capable CPUs. */
11235#if HC_ARCH_BITS == 64
11236 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
11237 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
11238 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
11239 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
11240 HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
11241 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
11242 VMX_IGS_LONGMODE_SS_BASE_INVALID);
11243 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
11244 VMX_IGS_LONGMODE_DS_BASE_INVALID);
11245 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
11246 VMX_IGS_LONGMODE_ES_BASE_INVALID);
11247#endif
11248 }
11249 else
11250 {
11251 /* V86 mode checks. */
11252 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
11253 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11254 {
11255 u32CSAttr = 0xf3; u32SSAttr = 0xf3;
11256 u32DSAttr = 0xf3; u32ESAttr = 0xf3;
11257 u32FSAttr = 0xf3; u32GSAttr = 0xf3;
11258 }
11259 else
11260 {
11261 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
11262 u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
11263 u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
11264 }
11265
11266 /* CS */
11267 HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
11268 HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
11269 HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
11270 /* SS */
11271 HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
11272 HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
11273 HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
11274 /* DS */
11275 HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
11276 HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
11277 HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
11278 /* ES */
11279 HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
11280 HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
11281 HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
11282 /* FS */
11283 HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
11284 HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
11285 HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
11286 /* GS */
11287 HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
11288 HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
11289 HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
11290 /* 64-bit capable CPUs. */
11291#if HC_ARCH_BITS == 64
11292 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
11293 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
11294 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
11295 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
11296 HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
11297 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ss.u64Base >> 32),
11298 VMX_IGS_LONGMODE_SS_BASE_INVALID);
11299 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->ds.u64Base >> 32),
11300 VMX_IGS_LONGMODE_DS_BASE_INVALID);
11301 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !(pCtx->es.u64Base >> 32),
11302 VMX_IGS_LONGMODE_ES_BASE_INVALID);
11303#endif
11304 }
11305
11306 /*
11307 * TR.
11308 */
11309 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
11310 /* 64-bit capable CPUs. */
11311#if HC_ARCH_BITS == 64
11312 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
11313#endif
11314 if (fLongModeGuest)
11315 {
11316 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
11317 VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
11318 }
11319 else
11320 {
11321 HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
11322 || pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
11323 VMX_IGS_TR_ATTR_TYPE_INVALID);
11324 }
11325 HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
11326 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
11327 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
11328 HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
11329 || !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
11330 HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
11331 || (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
11332 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
11333
11334 /*
11335 * GDTR and IDTR.
11336 */
11337#if HC_ARCH_BITS == 64
11338 rc = VMXReadVmcs64(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
11339 AssertRCBreak(rc);
11340 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
11341
11342 rc = VMXReadVmcs64(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
11343 AssertRCBreak(rc);
11344 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
11345#endif
11346
11347 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
11348 AssertRCBreak(rc);
11349 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
11350
11351 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
11352 AssertRCBreak(rc);
11353 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
11354
11355 /*
11356 * Guest Non-Register State.
11357 */
11358 /* Activity State. */
11359 uint32_t u32ActivityState;
11360 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
11361 AssertRCBreak(rc);
11362 HMVMX_CHECK_BREAK( !u32ActivityState
11363 || (u32ActivityState & MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.Msrs.u64Misc)),
11364 VMX_IGS_ACTIVITY_STATE_INVALID);
11365 HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
11366 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
11367 uint32_t u32IntrState;
11368 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &u32IntrState);
11369 AssertRCBreak(rc);
11370 if ( u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS
11371 || u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11372 {
11373 HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
11374 }
11375
11376 /** @todo Activity state and injecting interrupts. Left as a todo since we
11377 * currently don't use activity states but ACTIVE. */
11378
11379 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
11380 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
11381
11382 /* Guest interruptibility-state. */
11383 HMVMX_CHECK_BREAK(!(u32IntrState & 0xfffffff0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
11384 HMVMX_CHECK_BREAK((u32IntrState & ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
11385 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS))
11386 != ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
11387 | VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11388 VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
11389 HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
11390 || !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
11391 VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
11392 if (VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo))
11393 {
11394 if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
11395 {
11396 HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11397 && !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11398 VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
11399 }
11400 else if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11401 {
11402 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11403 VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
11404 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
11405 VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
11406 }
11407 }
11408 /** @todo Assumes the processor is not in SMM. */
11409 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
11410 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
11411 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
11412 || (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
11413 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
11414 if ( (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
11415 && VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo)
11416 && VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11417 {
11418 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI),
11419 VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
11420 }
11421
11422 /* Pending debug exceptions. */
11423#if HC_ARCH_BITS == 64
11424 rc = VMXReadVmcs64(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u64Val);
11425 AssertRCBreak(rc);
11426 /* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
11427 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
11428 u32Val = u64Val; /* For pending debug exceptions checks below. */
11429#else
11430 rc = VMXReadVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u32Val);
11431 AssertRCBreak(rc);
11432 /* Bits 31:15, Bit 13, Bits 11:4 MBZ. */
11433 HMVMX_CHECK_BREAK(!(u32Val & 0xffffaff0), VMX_IGS_PENDING_DEBUG_RESERVED);
11434#endif
11435
11436 if ( (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11437 || (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS)
11438 || u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
11439 {
11440 if ( (u32Eflags & X86_EFL_TF)
11441 && !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11442 {
11443 /* Bit 14 is PendingDebug.BS. */
11444 HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
11445 }
11446 if ( !(u32Eflags & X86_EFL_TF)
11447 || (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11448 {
11449 /* Bit 14 is PendingDebug.BS. */
11450 HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
11451 }
11452 }
11453
11454 /* VMCS link pointer. */
11455 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
11456 AssertRCBreak(rc);
11457 if (u64Val != UINT64_C(0xffffffffffffffff))
11458 {
11459 HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
11460 /** @todo Bits beyond the processor's physical-address width MBZ. */
11461 /** @todo 32-bit located in memory referenced by value of this field (as a
11462 * physical address) must contain the processor's VMCS revision ID. */
11463 /** @todo SMM checks. */
11464 }
11465
11466 /** @todo Checks on Guest Page-Directory-Pointer-Table Entries when guest is
11467 * not using Nested Paging? */
11468 if ( pVM->hm.s.fNestedPaging
11469 && !fLongModeGuest
11470 && CPUMIsGuestInPAEModeEx(pCtx))
11471 {
11472 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);
11473 AssertRCBreak(rc);
11474 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11475
11476 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);
11477 AssertRCBreak(rc);
11478 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11479
11480 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);
11481 AssertRCBreak(rc);
11482 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11483
11484 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);
11485 AssertRCBreak(rc);
11486 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11487 }
11488
11489 /* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
11490 if (uError == VMX_IGS_ERROR)
11491 uError = VMX_IGS_REASON_NOT_FOUND;
11492 } while (0);
11493
11494 pVCpu->hm.s.u32HMError = uError;
11495 return uError;
11496
11497#undef HMVMX_ERROR_BREAK
11498#undef HMVMX_CHECK_BREAK
11499}
11500
11501/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11502/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
11503/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11504
11505/** @name VM-exit handlers.
11506 * @{
11507 */
11508
11509/**
11510 * VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
11511 */
11512HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11513{
11514 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11515 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
11516 /* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
11517 if (VMMR0ThreadCtxHookIsEnabled(pVCpu))
11518 return VINF_SUCCESS;
11519 return VINF_EM_RAW_INTERRUPT;
11520}
11521
11522
11523/**
11524 * VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
11525 */
11526HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11527{
11528 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11529 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
11530
11531 int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
11532 AssertRCReturn(rc, rc);
11533
11534 uint32_t uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo);
11535 Assert( !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT)
11536 && uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
11537 Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
11538
11539 if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11540 {
11541 /*
11542 * This cannot be a guest NMI as the only way for the guest to receive an NMI is if we injected it ourselves and
11543 * anything we inject is not going to cause a VM-exit directly for the event being injected.
11544 * See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
11545 *
11546 * Dispatch the NMI to the host. See Intel spec. 27.5.5 "Updating Non-Register State".
11547 */
11548 VMXDispatchHostNmi();
11549 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
11550 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11551 return VINF_SUCCESS;
11552 }
11553
11554 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
11555 VBOXSTRICTRC rcStrictRc1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
11556 if (RT_UNLIKELY(rcStrictRc1 == VINF_SUCCESS))
11557 { /* likely */ }
11558 else
11559 {
11560 if (rcStrictRc1 == VINF_HM_DOUBLE_FAULT)
11561 rcStrictRc1 = VINF_SUCCESS;
11562 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11563 return rcStrictRc1;
11564 }
11565
11566 uint32_t uExitIntInfo = pVmxTransient->uExitIntInfo;
11567 uint32_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(uExitIntInfo);
11568 switch (uIntType)
11569 {
11570 case VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT: /* Privileged software exception. (#DB from ICEBP) */
11571 Assert(uVector == X86_XCPT_DB);
11572 /* fall thru */
11573 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT: /* Software exception. (#BP or #OF) */
11574 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF || uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT);
11575 /* fall thru */
11576 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT:
11577 {
11578 /*
11579 * If there's any exception caused as a result of event injection, go back to
11580 * the interpreter. The page-fault case is complicated and we manually handle
11581 * any currently pending event in hmR0VmxExitXcptPF. Nested #ACs are already
11582 * handled in hmR0VmxCheckExitDueToEventDelivery.
11583 */
11584 if (!pVCpu->hm.s.Event.fPending)
11585 { /* likely */ }
11586 else if ( uVector != X86_XCPT_PF
11587 && uVector != X86_XCPT_AC)
11588 {
11589 /** @todo Why do we need to fallback to the interpreter here? */
11590 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
11591 rc = VERR_EM_INTERPRETER;
11592 break;
11593 }
11594
11595 switch (uVector)
11596 {
11597 case X86_XCPT_PF: rc = hmR0VmxExitXcptPF(pVCpu, pMixedCtx, pVmxTransient); break;
11598 case X86_XCPT_GP: rc = hmR0VmxExitXcptGP(pVCpu, pMixedCtx, pVmxTransient); break;
11599 case X86_XCPT_NM: rc = hmR0VmxExitXcptNM(pVCpu, pMixedCtx, pVmxTransient); break;
11600 case X86_XCPT_MF: rc = hmR0VmxExitXcptMF(pVCpu, pMixedCtx, pVmxTransient); break;
11601 case X86_XCPT_DB: rc = hmR0VmxExitXcptDB(pVCpu, pMixedCtx, pVmxTransient); break;
11602 case X86_XCPT_BP: rc = hmR0VmxExitXcptBP(pVCpu, pMixedCtx, pVmxTransient); break;
11603 case X86_XCPT_AC: rc = hmR0VmxExitXcptAC(pVCpu, pMixedCtx, pVmxTransient); break;
11604
11605 case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF);
11606 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11607 case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
11608 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11609 case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
11610 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11611 case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
11612 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11613 case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
11614 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11615 case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS);
11616 rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11617 default:
11618 {
11619 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11620 AssertRCReturn(rc, rc);
11621
11622 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
11623 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11624 {
11625 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
11626 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
11627 Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
11628
11629 rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11630 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
11631 AssertRCReturn(rc, rc);
11632 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(uExitIntInfo),
11633 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode,
11634 0 /* GCPtrFaultAddress */);
11635 AssertRCReturn(rc, rc);
11636 }
11637 else
11638 {
11639 AssertMsgFailed(("Unexpected VM-exit caused by exception %#x\n", uVector));
11640 pVCpu->hm.s.u32HMError = uVector;
11641 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
11642 }
11643 break;
11644 }
11645 }
11646 break;
11647 }
11648
11649 default:
11650 {
11651 pVCpu->hm.s.u32HMError = uExitIntInfo;
11652 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
11653 AssertMsgFailed(("Unexpected interruption info %#x\n", VMX_EXIT_INTERRUPTION_INFO_TYPE(uExitIntInfo)));
11654 break;
11655 }
11656 }
11657 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11658 return rc;
11659}
11660
11661
11662/**
11663 * VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
11664 */
11665HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11666{
11667 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11668
11669 /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
11670 hmR0VmxClearIntWindowExitVmcs(pVCpu);
11671
11672 /* Deliver the pending interrupts via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11673 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
11674 return VINF_SUCCESS;
11675}
11676
11677
11678/**
11679 * VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
11680 */
11681HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11682{
11683 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11684 if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)))
11685 {
11686 AssertMsgFailed(("Unexpected NMI-window exit.\n"));
11687 HMVMX_RETURN_UNEXPECTED_EXIT();
11688 }
11689
11690 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
11691
11692 /*
11693 * If block-by-STI is set when we get this VM-exit, it means the CPU doesn't block NMIs following STI.
11694 * It is therefore safe to unblock STI and deliver the NMI ourselves. See @bugref{7445}.
11695 */
11696 uint32_t uIntrState = 0;
11697 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
11698 AssertRCReturn(rc, rc);
11699
11700 bool const fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
11701 if ( fBlockSti
11702 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
11703 {
11704 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
11705 }
11706
11707 /* Indicate that we no longer need to VM-exit when the guest is ready to receive NMIs, it is now ready */
11708 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
11709
11710 /* Deliver the pending NMI via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11711 return VINF_SUCCESS;
11712}
11713
11714
11715/**
11716 * VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
11717 */
11718HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11719{
11720 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11721 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
11722 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11723}
11724
11725
11726/**
11727 * VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
11728 */
11729HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11730{
11731 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11732 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
11733 return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11734}
11735
11736
11737/**
11738 * VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
11739 */
11740HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11741{
11742 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11743 PVM pVM = pVCpu->CTX_SUFF(pVM);
11744 int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11745 if (RT_LIKELY(rc == VINF_SUCCESS))
11746 {
11747 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11748 Assert(pVmxTransient->cbInstr == 2);
11749 }
11750 else
11751 {
11752 AssertMsgFailed(("hmR0VmxExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
11753 rc = VERR_EM_INTERPRETER;
11754 }
11755 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
11756 return rc;
11757}
11758
11759
11760/**
11761 * VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
11762 */
11763HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11764{
11765 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11766 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11767 AssertRCReturn(rc, rc);
11768
11769 if (pMixedCtx->cr4 & X86_CR4_SMXE)
11770 return VINF_EM_RAW_EMULATE_INSTR;
11771
11772 AssertMsgFailed(("hmR0VmxExitGetsec: unexpected VM-exit when CR4.SMXE is 0.\n"));
11773 HMVMX_RETURN_UNEXPECTED_EXIT();
11774}
11775
11776
11777/**
11778 * VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
11779 */
11780HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11781{
11782 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11783 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11784 AssertRCReturn(rc, rc);
11785
11786 PVM pVM = pVCpu->CTX_SUFF(pVM);
11787 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11788 if (RT_LIKELY(rc == VINF_SUCCESS))
11789 {
11790 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11791 Assert(pVmxTransient->cbInstr == 2);
11792 /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
11793 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
11794 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11795 }
11796 else
11797 rc = VERR_EM_INTERPRETER;
11798 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
11799 return rc;
11800}
11801
11802
11803/**
11804 * VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
11805 */
11806HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11807{
11808 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11809 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11810 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx); /* For MSR_K8_TSC_AUX */
11811 AssertRCReturn(rc, rc);
11812
11813 PVM pVM = pVCpu->CTX_SUFF(pVM);
11814 rc = EMInterpretRdtscp(pVM, pVCpu, pMixedCtx);
11815 if (RT_SUCCESS(rc))
11816 {
11817 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11818 Assert(pVmxTransient->cbInstr == 3);
11819 /* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
11820 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
11821 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11822 }
11823 else
11824 {
11825 AssertMsgFailed(("hmR0VmxExitRdtscp: EMInterpretRdtscp failed with %Rrc\n", rc));
11826 rc = VERR_EM_INTERPRETER;
11827 }
11828 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
11829 return rc;
11830}
11831
11832
11833/**
11834 * VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
11835 */
11836HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11837{
11838 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11839 int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11840 rc |= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11841 AssertRCReturn(rc, rc);
11842
11843 PVM pVM = pVCpu->CTX_SUFF(pVM);
11844 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11845 if (RT_LIKELY(rc == VINF_SUCCESS))
11846 {
11847 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11848 Assert(pVmxTransient->cbInstr == 2);
11849 }
11850 else
11851 {
11852 AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
11853 rc = VERR_EM_INTERPRETER;
11854 }
11855 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
11856 return rc;
11857}
11858
11859
11860/**
11861 * VM-exit handler for VMCALL (VMX_EXIT_VMCALL). Unconditional VM-exit.
11862 */
11863HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11864{
11865 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11866 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
11867
11868 VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
11869 if (pVCpu->hm.s.fHypercallsEnabled)
11870 {
11871#if 0
11872 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
11873#else
11874 /* Aggressive state sync. for now. */
11875 int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
11876 rc |= hmR0VmxSaveGuestRflags(pVCpu,pMixedCtx); /* For CPL checks in gimHvHypercall() & gimKvmHypercall() */
11877 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* For long-mode checks in gimKvmHypercall(). */
11878 AssertRCReturn(rc, rc);
11879#endif
11880
11881 /* Perform the hypercall. */
11882 rcStrict = GIMHypercall(pVCpu, pMixedCtx);
11883 if (rcStrict == VINF_SUCCESS)
11884 {
11885 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11886 AssertRCReturn(rc, rc);
11887 }
11888 else
11889 Assert( rcStrict == VINF_GIM_R3_HYPERCALL
11890 || rcStrict == VINF_GIM_HYPERCALL_CONTINUING
11891 || RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
11892
11893 /* If the hypercall changes anything other than guest's general-purpose registers,
11894 we would need to reload the guest changed bits here before VM-entry. */
11895 }
11896 else
11897 Log4(("hmR0VmxExitVmcall: Hypercalls not enabled\n"));
11898
11899 /* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
11900 if (RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)))
11901 {
11902 hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx);
11903 rcStrict = VINF_SUCCESS;
11904 }
11905
11906 return rcStrict;
11907}
11908
11909
11910/**
11911 * VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
11912 */
11913HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11914{
11915 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11916 PVM pVM = pVCpu->CTX_SUFF(pVM);
11917 Assert(!pVM->hm.s.fNestedPaging || pVCpu->hm.s.fUsingDebugLoop);
11918
11919 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
11920 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
11921 AssertRCReturn(rc, rc);
11922
11923 VBOXSTRICTRC rcStrict = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), pVmxTransient->uExitQualification);
11924 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11925 rcStrict = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11926 else
11927 AssertMsg(rcStrict == VERR_EM_INTERPRETER, ("hmR0VmxExitInvlpg: EMInterpretInvlpg %#RX64 failed with %Rrc\n",
11928 pVmxTransient->uExitQualification, VBOXSTRICTRC_VAL(rcStrict)));
11929 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
11930 return rcStrict;
11931}
11932
11933
11934/**
11935 * VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
11936 */
11937HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11938{
11939 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11940 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11941 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
11942 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
11943 AssertRCReturn(rc, rc);
11944
11945 PVM pVM = pVCpu->CTX_SUFF(pVM);
11946 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11947 if (RT_LIKELY(rc == VINF_SUCCESS))
11948 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11949 else
11950 {
11951 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
11952 rc = VERR_EM_INTERPRETER;
11953 }
11954 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
11955 return rc;
11956}
11957
11958
11959/**
11960 * VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
11961 */
11962HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11963{
11964 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11965 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11966 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
11967 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
11968 AssertRCReturn(rc, rc);
11969
11970 PVM pVM = pVCpu->CTX_SUFF(pVM);
11971 VBOXSTRICTRC rc2 = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11972 rc = VBOXSTRICTRC_VAL(rc2);
11973 if (RT_LIKELY( rc == VINF_SUCCESS
11974 || rc == VINF_EM_HALT))
11975 {
11976 int rc3 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11977 AssertRCReturn(rc3, rc3);
11978
11979 if ( rc == VINF_EM_HALT
11980 && EMMonitorWaitShouldContinue(pVCpu, pMixedCtx))
11981 {
11982 rc = VINF_SUCCESS;
11983 }
11984 }
11985 else
11986 {
11987 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
11988 rc = VERR_EM_INTERPRETER;
11989 }
11990 AssertMsg(rc == VINF_SUCCESS || rc == VINF_EM_HALT || rc == VERR_EM_INTERPRETER,
11991 ("hmR0VmxExitMwait: failed, invalid error code %Rrc\n", rc));
11992 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
11993 return rc;
11994}
11995
11996
11997/**
11998 * VM-exit handler for RSM (VMX_EXIT_RSM). Unconditional VM-exit.
11999 */
12000HMVMX_EXIT_NSRC_DECL hmR0VmxExitRsm(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12001{
12002 /*
12003 * Execution of RSM outside of SMM mode causes #UD regardless of VMX root or VMX non-root mode. In theory, we should never
12004 * get this VM-exit. This can happen only if dual-monitor treatment of SMI and VMX is enabled, which can (only?) be done by
12005 * executing VMCALL in VMX root operation. If we get here, something funny is going on.
12006 * See Intel spec. "33.15.5 Enabling the Dual-Monitor Treatment".
12007 */
12008 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12009 AssertMsgFailed(("Unexpected RSM VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12010 HMVMX_RETURN_UNEXPECTED_EXIT();
12011}
12012
12013
12014/**
12015 * VM-exit handler for SMI (VMX_EXIT_SMI). Unconditional VM-exit.
12016 */
12017HMVMX_EXIT_NSRC_DECL hmR0VmxExitSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12018{
12019 /*
12020 * This can only happen if we support dual-monitor treatment of SMI, which can be activated by executing VMCALL in VMX
12021 * root operation. Only an STM (SMM transfer monitor) would get this VM-exit when we (the executive monitor) execute a VMCALL
12022 * in VMX root mode or receive an SMI. If we get here, something funny is going on.
12023 * See Intel spec. "33.15.6 Activating the Dual-Monitor Treatment" and Intel spec. 25.3 "Other Causes of VM-Exits"
12024 */
12025 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12026 AssertMsgFailed(("Unexpected SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12027 HMVMX_RETURN_UNEXPECTED_EXIT();
12028}
12029
12030
12031/**
12032 * VM-exit handler for IO SMI (VMX_EXIT_IO_SMI). Unconditional VM-exit.
12033 */
12034HMVMX_EXIT_NSRC_DECL hmR0VmxExitIoSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12035{
12036 /* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
12037 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12038 AssertMsgFailed(("Unexpected IO SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12039 HMVMX_RETURN_UNEXPECTED_EXIT();
12040}
12041
12042
12043/**
12044 * VM-exit handler for SIPI (VMX_EXIT_SIPI). Conditional VM-exit.
12045 */
12046HMVMX_EXIT_NSRC_DECL hmR0VmxExitSipi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12047{
12048 /*
12049 * SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest activity state is used. We currently
12050 * don't make use of it (see hmR0VmxLoadGuestActivityState()) as our guests don't have direct access to the host LAPIC.
12051 * See Intel spec. 25.3 "Other Causes of VM-exits".
12052 */
12053 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12054 AssertMsgFailed(("Unexpected SIPI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12055 HMVMX_RETURN_UNEXPECTED_EXIT();
12056}
12057
12058
12059/**
12060 * VM-exit handler for INIT signal (VMX_EXIT_INIT_SIGNAL). Unconditional
12061 * VM-exit.
12062 */
12063HMVMX_EXIT_NSRC_DECL hmR0VmxExitInitSignal(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12064{
12065 /*
12066 * INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
12067 * See Intel spec. 33.14.1 Default Treatment of SMI Delivery" and Intel spec. 29.3 "VMX Instructions" for "VMXON".
12068 *
12069 * It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these VM-exits.
12070 * See Intel spec. "23.8 Restrictions on VMX operation".
12071 */
12072 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12073 return VINF_SUCCESS;
12074}
12075
12076
12077/**
12078 * VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
12079 * VM-exit.
12080 */
12081HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12082{
12083 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12084 return VINF_EM_RESET;
12085}
12086
12087
12088/**
12089 * VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
12090 */
12091HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12092{
12093 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12094 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
12095
12096 int rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12097 AssertRCReturn(rc, rc);
12098
12099 if (EMShouldContinueAfterHalt(pVCpu, pMixedCtx)) /* Requires eflags. */
12100 rc = VINF_SUCCESS;
12101 else
12102 rc = VINF_EM_HALT;
12103
12104 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
12105 if (rc != VINF_SUCCESS)
12106 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
12107 return rc;
12108}
12109
12110
12111/**
12112 * VM-exit handler for instructions that result in a \#UD exception delivered to
12113 * the guest.
12114 */
12115HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12116{
12117 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12118 hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx);
12119 return VINF_SUCCESS;
12120}
12121
12122
12123/**
12124 * VM-exit handler for expiry of the VMX preemption timer.
12125 */
12126HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12127{
12128 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12129
12130 /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
12131 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
12132
12133 /* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
12134 PVM pVM = pVCpu->CTX_SUFF(pVM);
12135 bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
12136 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
12137 return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
12138}
12139
12140
12141/**
12142 * VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
12143 */
12144HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12145{
12146 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12147
12148 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12149 rc |= hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /*fMemory*/, false /*fNeedRsp*/);
12150 rc |= hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
12151 AssertRCReturn(rc, rc);
12152
12153 VBOXSTRICTRC rcStrict = IEMExecDecodedXsetbv(pVCpu, pVmxTransient->cbInstr);
12154 HMCPU_CF_SET(pVCpu, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS : HM_CHANGED_ALL_GUEST);
12155
12156 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
12157
12158 return rcStrict;
12159}
12160
12161
12162/**
12163 * VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
12164 */
12165HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12166{
12167 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12168
12169 /* The guest should not invalidate the host CPU's TLBs, fallback to interpreter. */
12170 /** @todo implement EMInterpretInvpcid() */
12171 return VERR_EM_INTERPRETER;
12172}
12173
12174
12175/**
12176 * VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE).
12177 * Error VM-exit.
12178 */
12179HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12180{
12181 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12182 AssertRCReturn(rc, rc);
12183
12184 rc = hmR0VmxCheckVmcsCtls(pVCpu);
12185 AssertRCReturn(rc, rc);
12186
12187 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
12188 NOREF(uInvalidReason);
12189
12190#ifdef VBOX_STRICT
12191 uint32_t uIntrState;
12192 RTHCUINTREG uHCReg;
12193 uint64_t u64Val;
12194 uint32_t u32Val;
12195
12196 rc = hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
12197 rc |= hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
12198 rc |= hmR0VmxReadEntryInstrLenVmcs(pVmxTransient);
12199 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
12200 AssertRCReturn(rc, rc);
12201
12202 Log4(("uInvalidReason %u\n", uInvalidReason));
12203 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntInfo));
12204 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
12205 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
12206 Log4(("VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE %#RX32\n", uIntrState));
12207
12208 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val); AssertRC(rc);
12209 Log4(("VMX_VMCS_GUEST_CR0 %#RX32\n", u32Val));
12210 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
12211 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
12212 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
12213 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
12214 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
12215 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
12216 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
12217 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
12218 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
12219 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
12220#else
12221 NOREF(pVmxTransient);
12222#endif
12223
12224 hmR0DumpRegs(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
12225 return VERR_VMX_INVALID_GUEST_STATE;
12226}
12227
12228
12229/**
12230 * VM-exit handler for VM-entry failure due to an MSR-load
12231 * (VMX_EXIT_ERR_MSR_LOAD). Error VM-exit.
12232 */
12233HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12234{
12235 NOREF(pVmxTransient);
12236 AssertMsgFailed(("Unexpected MSR-load exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx)); NOREF(pMixedCtx);
12237 HMVMX_RETURN_UNEXPECTED_EXIT();
12238}
12239
12240
12241/**
12242 * VM-exit handler for VM-entry failure due to a machine-check event
12243 * (VMX_EXIT_ERR_MACHINE_CHECK). Error VM-exit.
12244 */
12245HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12246{
12247 NOREF(pVmxTransient);
12248 AssertMsgFailed(("Unexpected machine-check event exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx)); NOREF(pMixedCtx);
12249 HMVMX_RETURN_UNEXPECTED_EXIT();
12250}
12251
12252
12253/**
12254 * VM-exit handler for all undefined reasons. Should never ever happen.. in
12255 * theory.
12256 */
12257HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrUndefined(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12258{
12259 AssertMsgFailed(("Huh!? Undefined VM-exit reason %d. pVCpu=%p pMixedCtx=%p\n", pVmxTransient->uExitReason, pVCpu, pMixedCtx));
12260 NOREF(pVCpu); NOREF(pMixedCtx); NOREF(pVmxTransient);
12261 return VERR_VMX_UNDEFINED_EXIT_CODE;
12262}
12263
12264
12265/**
12266 * VM-exit handler for XDTR (LGDT, SGDT, LIDT, SIDT) accesses
12267 * (VMX_EXIT_XDTR_ACCESS) and LDT and TR access (LLDT, LTR, SLDT, STR).
12268 * Conditional VM-exit.
12269 */
12270HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12271{
12272 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12273
12274 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */
12275 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
12276 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
12277 return VERR_EM_INTERPRETER;
12278 AssertMsgFailed(("Unexpected XDTR access. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12279 HMVMX_RETURN_UNEXPECTED_EXIT();
12280}
12281
12282
12283/**
12284 * VM-exit handler for RDRAND (VMX_EXIT_RDRAND). Conditional VM-exit.
12285 */
12286HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12287{
12288 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12289
12290 /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */
12291 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdrand);
12292 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT)
12293 return VERR_EM_INTERPRETER;
12294 AssertMsgFailed(("Unexpected RDRAND exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12295 HMVMX_RETURN_UNEXPECTED_EXIT();
12296}
12297
12298
12299/**
12300 * VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
12301 */
12302HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12303{
12304 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12305
12306 /* EMInterpretRdmsr() requires CR0, Eflags and SS segment register. */
12307 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
12308 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
12309 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12310 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12311 {
12312 rc |= hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
12313 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
12314 }
12315 AssertRCReturn(rc, rc);
12316 Log4(("ecx=%#RX32\n", pMixedCtx->ecx));
12317
12318#ifdef VBOX_STRICT
12319 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
12320 {
12321 if ( hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx)
12322 && pMixedCtx->ecx != MSR_K6_EFER)
12323 {
12324 AssertMsgFailed(("Unexpected RDMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12325 pMixedCtx->ecx));
12326 HMVMX_RETURN_UNEXPECTED_EXIT();
12327 }
12328 if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12329 {
12330 VMXMSREXITREAD enmRead;
12331 VMXMSREXITWRITE enmWrite;
12332 int rc2 = hmR0VmxGetMsrPermission(pVCpu, pMixedCtx->ecx, &enmRead, &enmWrite);
12333 AssertRCReturn(rc2, rc2);
12334 if (enmRead == VMXMSREXIT_PASSTHRU_READ)
12335 {
12336 AssertMsgFailed(("Unexpected RDMSR for a passthru lazy-restore MSR. ecx=%#RX32\n", pMixedCtx->ecx));
12337 HMVMX_RETURN_UNEXPECTED_EXIT();
12338 }
12339 }
12340 }
12341#endif
12342
12343 PVM pVM = pVCpu->CTX_SUFF(pVM);
12344 rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
12345 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER,
12346 ("hmR0VmxExitRdmsr: failed, invalid error code %Rrc\n", rc));
12347 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
12348 if (RT_SUCCESS(rc))
12349 {
12350 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12351 Assert(pVmxTransient->cbInstr == 2);
12352 }
12353 return rc;
12354}
12355
12356
12357/**
12358 * VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
12359 */
12360HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12361{
12362 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12363 PVM pVM = pVCpu->CTX_SUFF(pVM);
12364 int rc = VINF_SUCCESS;
12365
12366 /* EMInterpretWrmsr() requires CR0, EFLAGS and SS segment register. */
12367 rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
12368 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
12369 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12370 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12371 {
12372 rc |= hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
12373 rc |= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
12374 }
12375 AssertRCReturn(rc, rc);
12376 Log4(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", pMixedCtx->ecx, pMixedCtx->edx, pMixedCtx->eax));
12377
12378 rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
12379 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER, ("hmR0VmxExitWrmsr: failed, invalid error code %Rrc\n", rc));
12380 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
12381
12382 if (RT_SUCCESS(rc))
12383 {
12384 rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12385
12386 /* If this is an X2APIC WRMSR access, update the APIC state as well. */
12387 if ( pMixedCtx->ecx == MSR_IA32_APICBASE
12388 || ( pMixedCtx->ecx >= MSR_IA32_X2APIC_START
12389 && pMixedCtx->ecx <= MSR_IA32_X2APIC_END))
12390 {
12391 /*
12392 * We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
12393 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before
12394 * EMInterpretWrmsr() changes it.
12395 */
12396 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
12397 }
12398 else if (pMixedCtx->ecx == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
12399 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
12400 else if (pMixedCtx->ecx == MSR_K6_EFER)
12401 {
12402 /*
12403 * If the guest touches EFER we need to update the VM-Entry and VM-Exit controls as well,
12404 * even if it is -not- touching bits that cause paging mode changes (LMA/LME). We care about
12405 * the other bits as well, SCE and NXE. See @bugref{7368}.
12406 */
12407 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR | HM_CHANGED_VMX_ENTRY_CTLS | HM_CHANGED_VMX_EXIT_CTLS);
12408 }
12409
12410 /* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not supported. */
12411 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12412 {
12413 switch (pMixedCtx->ecx)
12414 {
12415 /*
12416 * For SYSENTER CS, EIP, ESP MSRs, we set both the flags here so we don't accidentally
12417 * overwrite the changed guest-CPU context value while going to ring-3, see @bufref{8745}.
12418 */
12419 case MSR_IA32_SYSENTER_CS:
12420 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
12421 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR);
12422 break;
12423 case MSR_IA32_SYSENTER_EIP:
12424 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
12425 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR);
12426 break;
12427 case MSR_IA32_SYSENTER_ESP:
12428 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
12429 HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR);
12430 break;
12431 case MSR_K8_FS_BASE: /* fall thru */
12432 case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
12433 case MSR_K6_EFER: /* already handled above */ break;
12434 default:
12435 {
12436 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
12437 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
12438 else if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12439 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
12440 break;
12441 }
12442 }
12443 }
12444#ifdef VBOX_STRICT
12445 else
12446 {
12447 /* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
12448 switch (pMixedCtx->ecx)
12449 {
12450 case MSR_IA32_SYSENTER_CS:
12451 case MSR_IA32_SYSENTER_EIP:
12452 case MSR_IA32_SYSENTER_ESP:
12453 case MSR_K8_FS_BASE:
12454 case MSR_K8_GS_BASE:
12455 {
12456 AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", pMixedCtx->ecx));
12457 HMVMX_RETURN_UNEXPECTED_EXIT();
12458 }
12459
12460 /* Writes to MSRs in auto-load/store area/swapped MSRs, shouldn't cause VM-exits with MSR-bitmaps. */
12461 default:
12462 {
12463 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
12464 {
12465 /* EFER writes are always intercepted, see hmR0VmxLoadGuestMsrs(). */
12466 if (pMixedCtx->ecx != MSR_K6_EFER)
12467 {
12468 AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12469 pMixedCtx->ecx));
12470 HMVMX_RETURN_UNEXPECTED_EXIT();
12471 }
12472 }
12473
12474 if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12475 {
12476 VMXMSREXITREAD enmRead;
12477 VMXMSREXITWRITE enmWrite;
12478 int rc2 = hmR0VmxGetMsrPermission(pVCpu, pMixedCtx->ecx, &enmRead, &enmWrite);
12479 AssertRCReturn(rc2, rc2);
12480 if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)
12481 {
12482 AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", pMixedCtx->ecx));
12483 HMVMX_RETURN_UNEXPECTED_EXIT();
12484 }
12485 }
12486 break;
12487 }
12488 }
12489 }
12490#endif /* VBOX_STRICT */
12491 }
12492 return rc;
12493}
12494
12495
12496/**
12497 * VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
12498 */
12499HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12500{
12501 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12502
12503 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
12504 return VINF_EM_RAW_INTERRUPT;
12505}
12506
12507
12508/**
12509 * VM-exit handler for when the TPR value is lowered below the specified
12510 * threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
12511 */
12512HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12513{
12514 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12515 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
12516
12517 /*
12518 * The TPR shadow would've been synced with the APIC TPR in hmR0VmxPostRunGuest(). We'll re-evaluate
12519 * pending interrupts and inject them before the next VM-entry so we can just continue execution here.
12520 */
12521 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
12522 return VINF_SUCCESS;
12523}
12524
12525
12526/**
12527 * VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
12528 * VM-exit.
12529 *
12530 * @retval VINF_SUCCESS when guest execution can continue.
12531 * @retval VINF_PGM_CHANGE_MODE when shadow paging mode changed, back to ring-3.
12532 * @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
12533 * @retval VERR_EM_INTERPRETER when something unexpected happened, fallback to
12534 * interpreter.
12535 */
12536HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12537{
12538 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12539 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
12540 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12541 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12542 AssertRCReturn(rc, rc);
12543
12544 RTGCUINTPTR const uExitQualification = pVmxTransient->uExitQualification;
12545 uint32_t const uAccessType = VMX_EXIT_QUALIFICATION_CRX_ACCESS(uExitQualification);
12546 PVM pVM = pVCpu->CTX_SUFF(pVM);
12547 VBOXSTRICTRC rcStrict;
12548 rc = hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /*fMemory*/, true /*fNeedRsp*/);
12549 switch (uAccessType)
12550 {
12551 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE: /* MOV to CRx */
12552 {
12553 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12554 AssertRCReturn(rc, rc);
12555
12556 rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, pVmxTransient->cbInstr,
12557 VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification),
12558 VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification));
12559 AssertMsg( rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT || rcStrict == VINF_PGM_CHANGE_MODE
12560 || rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12561 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification))
12562 {
12563 case 0: /* CR0 */
12564 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12565 Log4(("CRX CR0 write rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr0));
12566 break;
12567 case 2: /* CR2 */
12568 /* Nothing to do here, CR2 it's not part of the VMCS. */
12569 break;
12570 case 3: /* CR3 */
12571 Assert(!pVM->hm.s.fNestedPaging || !CPUMIsGuestPagingEnabledEx(pMixedCtx) || pVCpu->hm.s.fUsingDebugLoop);
12572 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
12573 Log4(("CRX CR3 write rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr3));
12574 break;
12575 case 4: /* CR4 */
12576 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
12577 Log4(("CRX CR4 write rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n",
12578 VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr4, pVCpu->hm.s.fLoadSaveGuestXcr0));
12579 break;
12580 case 8: /* CR8 */
12581 Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
12582 /* CR8 contains the APIC TPR. Was updated by IEMExecDecodedMovCRxWrite(). */
12583 HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
12584 break;
12585 default:
12586 AssertMsgFailed(("Invalid CRx register %#x\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)));
12587 break;
12588 }
12589
12590 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
12591 break;
12592 }
12593
12594 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ: /* MOV from CRx */
12595 {
12596 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12597 AssertRCReturn(rc, rc);
12598
12599 Assert( !pVM->hm.s.fNestedPaging
12600 || !CPUMIsGuestPagingEnabledEx(pMixedCtx)
12601 || pVCpu->hm.s.fUsingDebugLoop
12602 || VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 3);
12603
12604 /* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
12605 Assert( VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 8
12606 || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
12607
12608 rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr,
12609 VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification),
12610 VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification));
12611 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12612 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
12613 Log4(("CRX CR%d Read access rcStrict=%Rrc\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification),
12614 VBOXSTRICTRC_VAL(rcStrict)));
12615 break;
12616 }
12617
12618 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */
12619 {
12620 AssertRCReturn(rc, rc);
12621 rcStrict = IEMExecDecodedClts(pVCpu, pVmxTransient->cbInstr);
12622 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12623 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12624 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
12625 Log4(("CRX CLTS rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12626 break;
12627 }
12628
12629 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
12630 {
12631 AssertRCReturn(rc, rc);
12632 rcStrict = IEMExecDecodedLmsw(pVCpu, pVmxTransient->cbInstr,
12633 VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification));
12634 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_IEM_RAISED_XCPT || rcStrict == VINF_PGM_CHANGE_MODE,
12635 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12636 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12637 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
12638 Log4(("CRX LMSW rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12639 break;
12640 }
12641
12642 default:
12643 AssertMsgFailedReturn(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType),
12644 VERR_VMX_UNEXPECTED_EXCEPTION);
12645 }
12646
12647 HMCPU_CF_SET(pVCpu, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS : HM_CHANGED_ALL_GUEST);
12648 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
12649 NOREF(pVM);
12650 return rcStrict;
12651}
12652
12653
12654/**
12655 * VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
12656 * VM-exit.
12657 */
12658HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12659{
12660 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12661 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
12662
12663 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12664 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12665 rc |= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
12666 rc |= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* Eflag checks in EMInterpretDisasCurrent(). */
12667 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx); /* CR0 checks & PGM* in EMInterpretDisasCurrent(). */
12668 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* SELM checks in EMInterpretDisasCurrent(). */
12669 /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
12670 AssertRCReturn(rc, rc);
12671
12672 /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
12673 uint32_t uIOPort = VMX_EXIT_QUALIFICATION_IO_PORT(pVmxTransient->uExitQualification);
12674 uint8_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(pVmxTransient->uExitQualification);
12675 bool fIOWrite = ( VMX_EXIT_QUALIFICATION_IO_DIRECTION(pVmxTransient->uExitQualification)
12676 == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
12677 bool fIOString = VMX_EXIT_QUALIFICATION_IO_IS_STRING(pVmxTransient->uExitQualification);
12678 bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
12679 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
12680 AssertReturn(uIOWidth <= 3 && uIOWidth != 2, VERR_VMX_IPE_1);
12681
12682 /* I/O operation lookup arrays. */
12683 static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses. */
12684 static uint32_t const s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving the result (in AL/AX/EAX). */
12685
12686 VBOXSTRICTRC rcStrict;
12687 uint32_t const cbValue = s_aIOSizes[uIOWidth];
12688 uint32_t const cbInstr = pVmxTransient->cbInstr;
12689 bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
12690 PVM pVM = pVCpu->CTX_SUFF(pVM);
12691 if (fIOString)
12692 {
12693#ifdef VBOX_WITH_2ND_IEM_STEP /* This used to gurus with debian 32-bit guest without NP (on ATA reads).
12694 See @bugref{5752#c158}. Should work now. */
12695 /*
12696 * INS/OUTS - I/O String instruction.
12697 *
12698 * Use instruction-information if available, otherwise fall back on
12699 * interpreting the instruction.
12700 */
12701 Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue,
12702 fIOWrite ? 'w' : 'r'));
12703 AssertReturn(pMixedCtx->dx == uIOPort, VERR_VMX_IPE_2);
12704 if (MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))
12705 {
12706 int rc2 = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12707 /** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
12708 rc2 |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12709 AssertRCReturn(rc2, rc2);
12710 AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3);
12711 AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
12712 IEMMODE enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
12713 bool fRep = VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification);
12714 if (fIOWrite)
12715 {
12716 rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
12717 pVmxTransient->ExitInstrInfo.StrIo.iSegReg, true /*fIoChecked*/);
12718 }
12719 else
12720 {
12721 /*
12722 * The segment prefix for INS cannot be overridden and is always ES. We can safely assume X86_SREG_ES.
12723 * Hence "iSegReg" field is undefined in the instruction-information field in VT-x for INS.
12724 * See Intel Instruction spec. for "INS".
12725 * See Intel spec. Table 27-8 "Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS".
12726 */
12727 rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr, true /*fIoChecked*/);
12728 }
12729 }
12730 else
12731 {
12732 /** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
12733 int rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12734 AssertRCReturn(rc2, rc2);
12735 rcStrict = IEMExecOne(pVCpu);
12736 }
12737 /** @todo IEM needs to be setting these flags somehow. */
12738 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
12739 fUpdateRipAlready = true;
12740#else
12741 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
12742 rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
12743 if (RT_SUCCESS(rcStrict))
12744 {
12745 if (fIOWrite)
12746 {
12747 rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
12748 (DISCPUMODE)pDis->uAddrMode, cbValue);
12749 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
12750 }
12751 else
12752 {
12753 rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
12754 (DISCPUMODE)pDis->uAddrMode, cbValue);
12755 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
12756 }
12757 }
12758 else
12759 {
12760 AssertMsg(rcStrict == VERR_EM_INTERPRETER, ("rcStrict=%Rrc RIP=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict),
12761 pMixedCtx->rip));
12762 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
12763 }
12764#endif
12765 }
12766 else
12767 {
12768 /*
12769 * IN/OUT - I/O instruction.
12770 */
12771 Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12772 uint32_t const uAndVal = s_aIOOpAnd[uIOWidth];
12773 Assert(!VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification));
12774 if (fIOWrite)
12775 {
12776 rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pMixedCtx->eax & uAndVal, cbValue);
12777 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
12778 }
12779 else
12780 {
12781 uint32_t u32Result = 0;
12782 rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
12783 if (IOM_SUCCESS(rcStrict))
12784 {
12785 /* Save result of I/O IN instr. in AL/AX/EAX. */
12786 pMixedCtx->eax = (pMixedCtx->eax & ~uAndVal) | (u32Result & uAndVal);
12787 }
12788 else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
12789 HMR0SavePendingIOPortRead(pVCpu, pMixedCtx->rip, pMixedCtx->rip + cbInstr, uIOPort, uAndVal, cbValue);
12790 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
12791 }
12792 }
12793
12794 if (IOM_SUCCESS(rcStrict))
12795 {
12796 if (!fUpdateRipAlready)
12797 {
12798 hmR0VmxAdvanceGuestRipBy(pVCpu, pMixedCtx, cbInstr);
12799 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
12800 }
12801
12802 /*
12803 * INS/OUTS with REP prefix updates RFLAGS, can be observed with triple-fault guru while booting Fedora 17 64-bit guest.
12804 * See Intel Instruction reference for REP/REPE/REPZ/REPNE/REPNZ.
12805 */
12806 if (fIOString)
12807 {
12808 /** @todo Single-step for INS/OUTS with REP prefix? */
12809 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
12810 }
12811 else if ( !fDbgStepping
12812 && fGstStepping)
12813 {
12814 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
12815 }
12816
12817 /*
12818 * If any I/O breakpoints are armed, we need to check if one triggered
12819 * and take appropriate action.
12820 * Note that the I/O breakpoint type is undefined if CR4.DE is 0.
12821 */
12822 int rc2 = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
12823 AssertRCReturn(rc2, rc2);
12824
12825 /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
12826 * execution engines about whether hyper BPs and such are pending. */
12827 uint32_t const uDr7 = pMixedCtx->dr[7];
12828 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
12829 && X86_DR7_ANY_RW_IO(uDr7)
12830 && (pMixedCtx->cr4 & X86_CR4_DE))
12831 || DBGFBpIsHwIoArmed(pVM)))
12832 {
12833 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
12834
12835 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
12836 VMMRZCallRing3Disable(pVCpu);
12837 HM_DISABLE_PREEMPT();
12838
12839 bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
12840
12841 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pMixedCtx, uIOPort, cbValue);
12842 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
12843 {
12844 /* Raise #DB. */
12845 if (fIsGuestDbgActive)
12846 ASMSetDR6(pMixedCtx->dr[6]);
12847 if (pMixedCtx->dr[7] != uDr7)
12848 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
12849
12850 hmR0VmxSetPendingXcptDB(pVCpu, pMixedCtx);
12851 }
12852 /* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
12853 however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
12854 else if ( rcStrict2 != VINF_SUCCESS
12855 && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
12856 rcStrict = rcStrict2;
12857 AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
12858
12859 HM_RESTORE_PREEMPT();
12860 VMMRZCallRing3Enable(pVCpu);
12861 }
12862 }
12863
12864#ifdef VBOX_STRICT
12865 if (rcStrict == VINF_IOM_R3_IOPORT_READ)
12866 Assert(!fIOWrite);
12867 else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
12868 Assert(fIOWrite);
12869 else
12870 {
12871#if 0 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
12872 * statuses, that the VMM device and some others may return. See
12873 * IOM_SUCCESS() for guidance. */
12874 AssertMsg( RT_FAILURE(rcStrict)
12875 || rcStrict == VINF_SUCCESS
12876 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
12877 || rcStrict == VINF_EM_DBG_BREAKPOINT
12878 || rcStrict == VINF_EM_RAW_GUEST_TRAP
12879 || rcStrict == VINF_EM_RAW_TO_R3
12880 || rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12881#endif
12882 }
12883#endif
12884
12885 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
12886 return rcStrict;
12887}
12888
12889
12890/**
12891 * VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
12892 * VM-exit.
12893 */
12894HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12895{
12896 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12897
12898 /* Check if this task-switch occurred while delivery an event through the guest IDT. */
12899 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12900 AssertRCReturn(rc, rc);
12901 if (VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT)
12902 {
12903 rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
12904 AssertRCReturn(rc, rc);
12905 if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
12906 {
12907 uint32_t uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
12908
12909 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
12910 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo);
12911
12912 /* Save it as a pending event and it'll be converted to a TRPM event on the way out to ring-3. */
12913 Assert(!pVCpu->hm.s.Event.fPending);
12914 pVCpu->hm.s.Event.fPending = true;
12915 pVCpu->hm.s.Event.u64IntInfo = pVmxTransient->uIdtVectoringInfo;
12916 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
12917 AssertRCReturn(rc, rc);
12918 if (fErrorCodeValid)
12919 pVCpu->hm.s.Event.u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
12920 else
12921 pVCpu->hm.s.Event.u32ErrCode = 0;
12922 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
12923 && uVector == X86_XCPT_PF)
12924 {
12925 pVCpu->hm.s.Event.GCPtrFaultAddress = pMixedCtx->cr2;
12926 }
12927
12928 Log4(("Pending event on TaskSwitch uIntType=%#x uVector=%#x\n", uIntType, uVector));
12929 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12930 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12931 }
12932 }
12933
12934 /* Fall back to the interpreter to emulate the task-switch. */
12935 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12936 return VERR_EM_INTERPRETER;
12937}
12938
12939
12940/**
12941 * VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
12942 */
12943HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12944{
12945 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12946 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
12947 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
12948 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12949 AssertRCReturn(rc, rc);
12950 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
12951 return VINF_EM_DBG_STEPPED;
12952}
12953
12954
12955/**
12956 * VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
12957 */
12958HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12959{
12960 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12961
12962 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
12963
12964 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12965 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
12966 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12967 {
12968 /* For some crazy guest, if an event delivery causes an APIC-access VM-exit, go to instruction emulation. */
12969 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12970 {
12971 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12972 return VERR_EM_INTERPRETER;
12973 }
12974 }
12975 else
12976 {
12977 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12978 rcStrict1 = VINF_SUCCESS;
12979 return rcStrict1;
12980 }
12981
12982#if 0
12983 /** @todo Investigate if IOMMMIOPhysHandler() requires a lot of state, for now
12984 * just sync the whole thing. */
12985 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12986#else
12987 /* Aggressive state sync. for now. */
12988 int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
12989 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12990 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12991#endif
12992 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12993 AssertRCReturn(rc, rc);
12994
12995 /* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
12996 uint32_t uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(pVmxTransient->uExitQualification);
12997 VBOXSTRICTRC rcStrict2;
12998 switch (uAccessType)
12999 {
13000 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
13001 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
13002 {
13003 AssertMsg( !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
13004 || VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) != XAPIC_OFF_TPR,
13005 ("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
13006
13007 RTGCPHYS GCPhys = pVCpu->hm.s.vmx.u64MsrApicBase; /* Always up-to-date, u64MsrApicBase is not part of the VMCS. */
13008 GCPhys &= PAGE_BASE_GC_MASK;
13009 GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification);
13010 PVM pVM = pVCpu->CTX_SUFF(pVM);
13011 Log4(("ApicAccess uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys,
13012 VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification)));
13013
13014 rcStrict2 = IOMMMIOPhysHandler(pVM, pVCpu,
13015 uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ ? 0 : X86_TRAP_PF_RW,
13016 CPUMCTX2CORE(pMixedCtx), GCPhys);
13017 Log4(("ApicAccess rcStrict2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
13018 if ( rcStrict2 == VINF_SUCCESS
13019 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
13020 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
13021 {
13022 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13023 | HM_CHANGED_GUEST_RSP
13024 | HM_CHANGED_GUEST_RFLAGS
13025 | HM_CHANGED_VMX_GUEST_APIC_STATE);
13026 rcStrict2 = VINF_SUCCESS;
13027 }
13028 break;
13029 }
13030
13031 default:
13032 Log4(("ApicAccess uAccessType=%#x\n", uAccessType));
13033 rcStrict2 = VINF_EM_RAW_EMULATE_INSTR;
13034 break;
13035 }
13036
13037 if (rcStrict2 != VINF_SUCCESS)
13038 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchApicAccessToR3);
13039 return rcStrict2;
13040}
13041
13042
13043/**
13044 * VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
13045 * VM-exit.
13046 */
13047HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13048{
13049 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
13050
13051 /* We should -not- get this VM-exit if the guest's debug registers were active. */
13052 if (pVmxTransient->fWasGuestDebugStateActive)
13053 {
13054 AssertMsgFailed(("Unexpected MOV DRx exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
13055 HMVMX_RETURN_UNEXPECTED_EXIT();
13056 }
13057
13058 if ( !pVCpu->hm.s.fSingleInstruction
13059 && !pVmxTransient->fWasHyperDebugStateActive)
13060 {
13061 Assert(!DBGFIsStepping(pVCpu));
13062 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
13063
13064 /* Don't intercept MOV DRx any more. */
13065 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
13066 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
13067 AssertRCReturn(rc, rc);
13068
13069 /* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
13070 VMMRZCallRing3Disable(pVCpu);
13071 HM_DISABLE_PREEMPT();
13072
13073 /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
13074 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
13075 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
13076
13077 HM_RESTORE_PREEMPT();
13078 VMMRZCallRing3Enable(pVCpu);
13079
13080#ifdef VBOX_WITH_STATISTICS
13081 rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13082 AssertRCReturn(rc, rc);
13083 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
13084 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
13085 else
13086 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
13087#endif
13088 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
13089 return VINF_SUCCESS;
13090 }
13091
13092 /*
13093 * EMInterpretDRx[Write|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER, CS. EFER is always up-to-date.
13094 * Update the segment registers and DR7 from the CPU.
13095 */
13096 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13097 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
13098 rc |= hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
13099 AssertRCReturn(rc, rc);
13100 Log4(("CS:RIP=%04x:%08RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
13101
13102 PVM pVM = pVCpu->CTX_SUFF(pVM);
13103 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
13104 {
13105 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
13106 VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification),
13107 VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification));
13108 if (RT_SUCCESS(rc))
13109 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
13110 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
13111 }
13112 else
13113 {
13114 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
13115 VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification),
13116 VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification));
13117 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
13118 }
13119
13120 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
13121 if (RT_SUCCESS(rc))
13122 {
13123 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
13124 AssertRCReturn(rc2, rc2);
13125 return VINF_SUCCESS;
13126 }
13127 return rc;
13128}
13129
13130
13131/**
13132 * VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
13133 * Conditional VM-exit.
13134 */
13135HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13136{
13137 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
13138 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
13139
13140 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
13141 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
13142 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
13143 {
13144 /* If event delivery causes an EPT misconfig (MMIO), go back to instruction emulation as otherwise
13145 injecting the original pending event would most likely cause the same EPT misconfig VM-exit. */
13146 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
13147 {
13148 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
13149 return VERR_EM_INTERPRETER;
13150 }
13151 }
13152 else
13153 {
13154 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
13155 rcStrict1 = VINF_SUCCESS;
13156 return rcStrict1;
13157 }
13158
13159 RTGCPHYS GCPhys = 0;
13160 int rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
13161
13162#if 0
13163 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
13164#else
13165 /* Aggressive state sync. for now. */
13166 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
13167 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
13168 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
13169#endif
13170 AssertRCReturn(rc, rc);
13171
13172 /*
13173 * If we succeed, resume guest execution.
13174 * If we fail in interpreting the instruction because we couldn't get the guest physical address
13175 * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
13176 * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
13177 * weird case. See @bugref{6043}.
13178 */
13179 PVM pVM = pVCpu->CTX_SUFF(pVM);
13180 VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pMixedCtx), GCPhys, UINT32_MAX);
13181 Log4(("EPT misconfig at %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pMixedCtx->rip, VBOXSTRICTRC_VAL(rcStrict2)));
13182 if ( rcStrict2 == VINF_SUCCESS
13183 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
13184 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
13185 {
13186 /* Successfully handled MMIO operation. */
13187 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13188 | HM_CHANGED_GUEST_RSP
13189 | HM_CHANGED_GUEST_RFLAGS
13190 | HM_CHANGED_VMX_GUEST_APIC_STATE);
13191 return VINF_SUCCESS;
13192 }
13193 return rcStrict2;
13194}
13195
13196
13197/**
13198 * VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
13199 * VM-exit.
13200 */
13201HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13202{
13203 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
13204 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
13205
13206 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
13207 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
13208 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
13209 {
13210 /* In the unlikely case that the EPT violation happened as a result of delivering an event, log it. */
13211 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
13212 Log4(("EPT violation with an event pending u64IntInfo=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo));
13213 }
13214 else
13215 {
13216 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
13217 rcStrict1 = VINF_SUCCESS;
13218 return rcStrict1;
13219 }
13220
13221 RTGCPHYS GCPhys = 0;
13222 int rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
13223 rc |= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13224#if 0
13225 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
13226#else
13227 /* Aggressive state sync. for now. */
13228 rc |= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
13229 rc |= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
13230 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
13231#endif
13232 AssertRCReturn(rc, rc);
13233
13234 /* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
13235 AssertMsg(((pVmxTransient->uExitQualification >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQualification));
13236
13237 RTGCUINT uErrorCode = 0;
13238 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
13239 uErrorCode |= X86_TRAP_PF_ID;
13240 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
13241 uErrorCode |= X86_TRAP_PF_RW;
13242 if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
13243 uErrorCode |= X86_TRAP_PF_P;
13244
13245 TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
13246
13247 Log4(("EPT violation %#x at %#RX64 ErrorCode %#x CS:RIP=%04x:%08RX64\n", pVmxTransient->uExitQualification, GCPhys,
13248 uErrorCode, pMixedCtx->cs.Sel, pMixedCtx->rip));
13249
13250 /* Handle the pagefault trap for the nested shadow table. */
13251 PVM pVM = pVCpu->CTX_SUFF(pVM);
13252 VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pMixedCtx), GCPhys);
13253 TRPMResetTrap(pVCpu);
13254
13255 /* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
13256 if ( rcStrict2 == VINF_SUCCESS
13257 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
13258 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
13259 {
13260 /* Successfully synced our nested page tables. */
13261 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
13262 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13263 | HM_CHANGED_GUEST_RSP
13264 | HM_CHANGED_GUEST_RFLAGS);
13265 return VINF_SUCCESS;
13266 }
13267
13268 Log4(("EPT return to ring-3 rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
13269 return rcStrict2;
13270}
13271
13272/** @} */
13273
13274/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13275/* -=-=-=-=-=-=-=-=-=- VM-exit Exception Handlers -=-=-=-=-=-=-=-=-=-=- */
13276/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13277
13278/** @name VM-exit exception handlers.
13279 * @{
13280 */
13281
13282/**
13283 * VM-exit exception handler for \#MF (Math Fault: floating point exception).
13284 */
13285static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13286{
13287 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13288 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
13289
13290 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
13291 AssertRCReturn(rc, rc);
13292
13293 if (!(pMixedCtx->cr0 & X86_CR0_NE))
13294 {
13295 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
13296 rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
13297
13298 /** @todo r=ramshankar: The Intel spec. does -not- specify that this VM-exit
13299 * provides VM-exit instruction length. If this causes problem later,
13300 * disassemble the instruction like it's done on AMD-V. */
13301 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
13302 AssertRCReturn(rc2, rc2);
13303 return rc;
13304 }
13305
13306 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13307 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13308 return rc;
13309}
13310
13311
13312/**
13313 * VM-exit exception handler for \#BP (Breakpoint exception).
13314 */
13315static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13316{
13317 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13318 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
13319
13320 /** @todo Try optimize this by not saving the entire guest state unless
13321 * really needed. */
13322 int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13323 AssertRCReturn(rc, rc);
13324
13325 PVM pVM = pVCpu->CTX_SUFF(pVM);
13326 rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
13327 if (rc == VINF_EM_RAW_GUEST_TRAP)
13328 {
13329 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13330 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13331 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13332 AssertRCReturn(rc, rc);
13333
13334 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13335 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13336 }
13337
13338 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_EM_DBG_BREAKPOINT);
13339 return rc;
13340}
13341
13342
13343/**
13344 * VM-exit exception handler for \#AC (alignment check exception).
13345 */
13346static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13347{
13348 RT_NOREF_PV(pMixedCtx);
13349 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13350
13351 /*
13352 * Re-inject it. We'll detect any nesting before getting here.
13353 */
13354 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13355 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13356 AssertRCReturn(rc, rc);
13357 Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
13358
13359 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13360 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13361 return VINF_SUCCESS;
13362}
13363
13364
13365/**
13366 * VM-exit exception handler for \#DB (Debug exception).
13367 */
13368static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13369{
13370 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13371 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
13372 Log6(("XcptDB\n"));
13373
13374 /*
13375 * Get the DR6-like values from the VM-exit qualification and pass it to DBGF
13376 * for processing.
13377 */
13378 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13379 AssertRCReturn(rc, rc);
13380
13381 /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
13382 uint64_t uDR6 = X86_DR6_INIT_VAL;
13383 uDR6 |= ( pVmxTransient->uExitQualification
13384 & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3 | X86_DR6_BD | X86_DR6_BS));
13385
13386 rc = DBGFRZTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pMixedCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
13387 if (rc == VINF_EM_RAW_GUEST_TRAP)
13388 {
13389 /*
13390 * The exception was for the guest. Update DR6, DR7.GD and
13391 * IA32_DEBUGCTL.LBR before forwarding it.
13392 * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
13393 */
13394 VMMRZCallRing3Disable(pVCpu);
13395 HM_DISABLE_PREEMPT();
13396
13397 pMixedCtx->dr[6] &= ~X86_DR6_B_MASK;
13398 pMixedCtx->dr[6] |= uDR6;
13399 if (CPUMIsGuestDebugStateActive(pVCpu))
13400 ASMSetDR6(pMixedCtx->dr[6]);
13401
13402 HM_RESTORE_PREEMPT();
13403 VMMRZCallRing3Enable(pVCpu);
13404
13405 rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
13406 AssertRCReturn(rc, rc);
13407
13408 /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
13409 pMixedCtx->dr[7] &= ~X86_DR7_GD;
13410
13411 /* Paranoia. */
13412 pMixedCtx->dr[7] &= ~X86_DR7_RAZ_MASK;
13413 pMixedCtx->dr[7] |= X86_DR7_RA1_MASK;
13414
13415 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pMixedCtx->dr[7]);
13416 AssertRCReturn(rc, rc);
13417
13418 /*
13419 * Raise #DB in the guest.
13420 *
13421 * It is important to reflect what the VM-exit gave us (preserving the interruption-type) rather than use
13422 * hmR0VmxSetPendingXcptDB() as the #DB could've been raised while executing ICEBP and not the 'normal' #DB.
13423 * Thus it -may- trigger different handling in the CPU (like skipped DPL checks). See @bugref{6398}.
13424 *
13425 * Since ICEBP isn't documented on Intel, see AMD spec. 15.20 "Event Injection".
13426 */
13427 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13428 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13429 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13430 AssertRCReturn(rc, rc);
13431 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13432 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13433 return VINF_SUCCESS;
13434 }
13435
13436 /*
13437 * Not a guest trap, must be a hypervisor related debug event then.
13438 * Update DR6 in case someone is interested in it.
13439 */
13440 AssertMsg(rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
13441 AssertReturn(pVmxTransient->fWasHyperDebugStateActive, VERR_HM_IPE_5);
13442 CPUMSetHyperDR6(pVCpu, uDR6);
13443
13444 return rc;
13445}
13446
13447
13448/**
13449 * VM-exit exception handler for \#NM (Device-not-available exception: floating
13450 * point exception).
13451 */
13452static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13453{
13454 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13455
13456 /* We require CR0 and EFER. EFER is always up-to-date. */
13457 int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
13458 AssertRCReturn(rc, rc);
13459
13460 /* We're playing with the host CPU state here, have to disable preemption or longjmp. */
13461 VMMRZCallRing3Disable(pVCpu);
13462 HM_DISABLE_PREEMPT();
13463
13464 /* If the guest FPU was active at the time of the #NM VM-exit, then it's a guest fault. */
13465 if (pVmxTransient->fWasGuestFPUStateActive)
13466 {
13467 rc = VINF_EM_RAW_GUEST_TRAP;
13468 Assert(CPUMIsGuestFPUStateActive(pVCpu) || HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
13469 }
13470 else
13471 {
13472#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13473 Assert(!pVmxTransient->fWasGuestFPUStateActive || pVCpu->hm.s.fUsingDebugLoop);
13474#endif
13475 rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu);
13476 Assert( rc == VINF_EM_RAW_GUEST_TRAP
13477 || ((rc == VINF_SUCCESS || rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
13478 if (rc == VINF_CPUM_HOST_CR0_MODIFIED)
13479 HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
13480 }
13481
13482 HM_RESTORE_PREEMPT();
13483 VMMRZCallRing3Enable(pVCpu);
13484
13485 if (rc == VINF_SUCCESS || rc == VINF_CPUM_HOST_CR0_MODIFIED)
13486 {
13487 /* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
13488 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
13489 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
13490 pVCpu->hm.s.fPreloadGuestFpu = true;
13491 }
13492 else
13493 {
13494 /* Forward #NM to the guest. */
13495 Assert(rc == VINF_EM_RAW_GUEST_TRAP);
13496 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13497 AssertRCReturn(rc, rc);
13498 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13499 pVmxTransient->cbInstr, 0 /* error code */, 0 /* GCPtrFaultAddress */);
13500 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
13501 }
13502
13503 return VINF_SUCCESS;
13504}
13505
13506
13507/**
13508 * VM-exit exception handler for \#GP (General-protection exception).
13509 *
13510 * @remarks Requires pVmxTransient->uExitIntInfo to be up-to-date.
13511 */
13512static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13513{
13514 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13515 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
13516
13517 int rc;
13518 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
13519 { /* likely */ }
13520 else
13521 {
13522#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13523 Assert(pVCpu->hm.s.fUsingDebugLoop);
13524#endif
13525 /* If the guest is not in real-mode or we have unrestricted execution support, reflect #GP to the guest. */
13526 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13527 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13528 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13529 rc |= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13530 AssertRCReturn(rc, rc);
13531 Log4(("#GP Gst: CS:RIP %04x:%08RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u TR=%#04x\n", pMixedCtx->cs.Sel, pMixedCtx->rip,
13532 pVmxTransient->uExitIntErrorCode, pMixedCtx->cr0, CPUMGetGuestCPL(pVCpu), pMixedCtx->tr.Sel));
13533 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13534 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13535 return rc;
13536 }
13537
13538 Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
13539 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest);
13540
13541 /* EMInterpretDisasCurrent() requires a lot of the state, save the entire state. */
13542 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13543 AssertRCReturn(rc, rc);
13544
13545 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
13546 uint32_t cbOp = 0;
13547 PVM pVM = pVCpu->CTX_SUFF(pVM);
13548 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
13549 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
13550 if (RT_SUCCESS(rc))
13551 {
13552 rc = VINF_SUCCESS;
13553 Assert(cbOp == pDis->cbInstr);
13554 Log4(("#GP Disas OpCode=%u CS:EIP %04x:%04RX64\n", pDis->pCurInstr->uOpcode, pMixedCtx->cs.Sel, pMixedCtx->rip));
13555 switch (pDis->pCurInstr->uOpcode)
13556 {
13557 case OP_CLI:
13558 {
13559 pMixedCtx->eflags.Bits.u1IF = 0;
13560 pMixedCtx->eflags.Bits.u1RF = 0;
13561 pMixedCtx->rip += pDis->cbInstr;
13562 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13563 if ( !fDbgStepping
13564 && pMixedCtx->eflags.Bits.u1TF)
13565 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13566 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
13567 break;
13568 }
13569
13570 case OP_STI:
13571 {
13572 bool fOldIF = pMixedCtx->eflags.Bits.u1IF;
13573 pMixedCtx->eflags.Bits.u1IF = 1;
13574 pMixedCtx->eflags.Bits.u1RF = 0;
13575 pMixedCtx->rip += pDis->cbInstr;
13576 if (!fOldIF)
13577 {
13578 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
13579 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
13580 }
13581 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13582 if ( !fDbgStepping
13583 && pMixedCtx->eflags.Bits.u1TF)
13584 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13585 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
13586 break;
13587 }
13588
13589 case OP_HLT:
13590 {
13591 rc = VINF_EM_HALT;
13592 pMixedCtx->rip += pDis->cbInstr;
13593 pMixedCtx->eflags.Bits.u1RF = 0;
13594 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13595 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
13596 break;
13597 }
13598
13599 case OP_POPF:
13600 {
13601 Log4(("POPF CS:EIP %04x:%04RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
13602 uint32_t cbParm;
13603 uint32_t uMask;
13604 bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
13605 if (pDis->fPrefix & DISPREFIX_OPSIZE)
13606 {
13607 cbParm = 4;
13608 uMask = 0xffffffff;
13609 }
13610 else
13611 {
13612 cbParm = 2;
13613 uMask = 0xffff;
13614 }
13615
13616 /* Get the stack pointer & pop the contents of the stack onto Eflags. */
13617 RTGCPTR GCPtrStack = 0;
13618 X86EFLAGS Eflags;
13619 Eflags.u32 = 0;
13620 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13621 &GCPtrStack);
13622 if (RT_SUCCESS(rc))
13623 {
13624 Assert(sizeof(Eflags.u32) >= cbParm);
13625 rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u32, cbParm, PGMACCESSORIGIN_HM));
13626 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13627 }
13628 if (RT_FAILURE(rc))
13629 {
13630 rc = VERR_EM_INTERPRETER;
13631 break;
13632 }
13633 Log4(("POPF %#x -> %#RX64 mask=%#x RIP=%#RX64\n", Eflags.u, pMixedCtx->rsp, uMask, pMixedCtx->rip));
13634 pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ~((X86_EFL_POPF_BITS & uMask) | X86_EFL_RF))
13635 | (Eflags.u32 & X86_EFL_POPF_BITS & uMask);
13636 pMixedCtx->esp += cbParm;
13637 pMixedCtx->esp &= uMask;
13638 pMixedCtx->rip += pDis->cbInstr;
13639 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13640 | HM_CHANGED_GUEST_RSP
13641 | HM_CHANGED_GUEST_RFLAGS);
13642 /* Generate a pending-debug exception when the guest stepping over POPF regardless of how
13643 POPF restores EFLAGS.TF. */
13644 if ( !fDbgStepping
13645 && fGstStepping)
13646 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13647 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPopf);
13648 break;
13649 }
13650
13651 case OP_PUSHF:
13652 {
13653 uint32_t cbParm;
13654 uint32_t uMask;
13655 if (pDis->fPrefix & DISPREFIX_OPSIZE)
13656 {
13657 cbParm = 4;
13658 uMask = 0xffffffff;
13659 }
13660 else
13661 {
13662 cbParm = 2;
13663 uMask = 0xffff;
13664 }
13665
13666 /* Get the stack pointer & push the contents of eflags onto the stack. */
13667 RTGCPTR GCPtrStack = 0;
13668 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), (pMixedCtx->esp - cbParm) & uMask,
13669 SELMTOFLAT_FLAGS_CPL0, &GCPtrStack);
13670 if (RT_FAILURE(rc))
13671 {
13672 rc = VERR_EM_INTERPRETER;
13673 break;
13674 }
13675 X86EFLAGS Eflags = pMixedCtx->eflags;
13676 /* The RF & VM bits are cleared on image stored on stack; see Intel Instruction reference for PUSHF. */
13677 Eflags.Bits.u1RF = 0;
13678 Eflags.Bits.u1VM = 0;
13679
13680 rc = VBOXSTRICTRC_TODO(PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u, cbParm, PGMACCESSORIGIN_HM));
13681 if (RT_UNLIKELY(rc != VINF_SUCCESS))
13682 {
13683 AssertMsgFailed(("%Rrc\n", rc)); /** @todo allow strict return codes here */
13684 rc = VERR_EM_INTERPRETER;
13685 break;
13686 }
13687 Log4(("PUSHF %#x -> %#RGv\n", Eflags.u, GCPtrStack));
13688 pMixedCtx->esp -= cbParm;
13689 pMixedCtx->esp &= uMask;
13690 pMixedCtx->rip += pDis->cbInstr;
13691 pMixedCtx->eflags.Bits.u1RF = 0;
13692 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13693 | HM_CHANGED_GUEST_RSP
13694 | HM_CHANGED_GUEST_RFLAGS);
13695 if ( !fDbgStepping
13696 && pMixedCtx->eflags.Bits.u1TF)
13697 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13698 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPushf);
13699 break;
13700 }
13701
13702 case OP_IRET:
13703 {
13704 /** @todo Handle 32-bit operand sizes and check stack limits. See Intel
13705 * instruction reference. */
13706 RTGCPTR GCPtrStack = 0;
13707 uint32_t uMask = 0xffff;
13708 bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
13709 uint16_t aIretFrame[3];
13710 if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
13711 {
13712 rc = VERR_EM_INTERPRETER;
13713 break;
13714 }
13715 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13716 &GCPtrStack);
13717 if (RT_SUCCESS(rc))
13718 {
13719 rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame),
13720 PGMACCESSORIGIN_HM));
13721 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13722 }
13723 if (RT_FAILURE(rc))
13724 {
13725 rc = VERR_EM_INTERPRETER;
13726 break;
13727 }
13728 pMixedCtx->eip = 0;
13729 pMixedCtx->ip = aIretFrame[0];
13730 pMixedCtx->cs.Sel = aIretFrame[1];
13731 pMixedCtx->cs.ValidSel = aIretFrame[1];
13732 pMixedCtx->cs.u64Base = (uint64_t)pMixedCtx->cs.Sel << 4;
13733 pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF))
13734 | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
13735 pMixedCtx->sp += sizeof(aIretFrame);
13736 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13737 | HM_CHANGED_GUEST_SEGMENT_REGS
13738 | HM_CHANGED_GUEST_RSP
13739 | HM_CHANGED_GUEST_RFLAGS);
13740 /* Generate a pending-debug exception when stepping over IRET regardless of how IRET modifies EFLAGS.TF. */
13741 if ( !fDbgStepping
13742 && fGstStepping)
13743 hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13744 Log4(("IRET %#RX32 to %04x:%04x\n", GCPtrStack, pMixedCtx->cs.Sel, pMixedCtx->ip));
13745 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIret);
13746 break;
13747 }
13748
13749 case OP_INT:
13750 {
13751 uint16_t uVector = pDis->Param1.uValue & 0xff;
13752 hmR0VmxSetPendingIntN(pVCpu, pMixedCtx, uVector, pDis->cbInstr);
13753 /* INT clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13754 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13755 break;
13756 }
13757
13758 case OP_INTO:
13759 {
13760 if (pMixedCtx->eflags.Bits.u1OF)
13761 {
13762 hmR0VmxSetPendingXcptOF(pVCpu, pMixedCtx, pDis->cbInstr);
13763 /* INTO clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13764 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13765 }
13766 else
13767 {
13768 pMixedCtx->eflags.Bits.u1RF = 0;
13769 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
13770 }
13771 break;
13772 }
13773
13774 default:
13775 {
13776 pMixedCtx->eflags.Bits.u1RF = 0; /* This is correct most of the time... */
13777 VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pMixedCtx), 0 /* pvFault */,
13778 EMCODETYPE_SUPERVISOR);
13779 rc = VBOXSTRICTRC_VAL(rc2);
13780 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
13781 /** @todo We have to set pending-debug exceptions here when the guest is
13782 * single-stepping depending on the instruction that was interpreted. */
13783 Log4(("#GP rc=%Rrc\n", rc));
13784 break;
13785 }
13786 }
13787 }
13788 else
13789 rc = VERR_EM_INTERPRETER;
13790
13791 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT,
13792 ("#GP Unexpected rc=%Rrc\n", rc));
13793 return rc;
13794}
13795
13796
13797/**
13798 * VM-exit exception handler wrapper for generic exceptions. Simply re-injects
13799 * the exception reported in the VMX transient structure back into the VM.
13800 *
13801 * @remarks Requires uExitIntInfo in the VMX transient structure to be
13802 * up-to-date.
13803 */
13804static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13805{
13806 RT_NOREF_PV(pMixedCtx);
13807 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13808#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13809 AssertMsg(pVCpu->hm.s.fUsingDebugLoop || pVCpu->hm.s.vmx.RealMode.fRealOnV86Active,
13810 ("uVector=%#04x u32XcptBitmap=%#010RX32\n",
13811 VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo), pVCpu->hm.s.vmx.u32XcptBitmap));
13812#endif
13813
13814 /* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in
13815 hmR0VmxCheckExitDueToEventDelivery(). */
13816 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13817 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13818 AssertRCReturn(rc, rc);
13819 Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
13820
13821#ifdef DEBUG_ramshankar
13822 rc |= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
13823 uint8_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
13824 Log(("hmR0VmxExitXcptGeneric: Reinjecting Xcpt. uVector=%#x cs:rip=%#04x:%#RX64\n", uVector, pCtx->cs.Sel, pCtx->rip));
13825#endif
13826
13827 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13828 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13829 return VINF_SUCCESS;
13830}
13831
13832
13833/**
13834 * VM-exit exception handler for \#PF (Page-fault exception).
13835 */
13836static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13837{
13838 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13839 PVM pVM = pVCpu->CTX_SUFF(pVM);
13840 int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13841 rc |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13842 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13843 AssertRCReturn(rc, rc);
13844
13845 if (!pVM->hm.s.fNestedPaging)
13846 { /* likely */ }
13847 else
13848 {
13849#if !defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) && !defined(HMVMX_ALWAYS_TRAP_PF)
13850 Assert(pVCpu->hm.s.fUsingDebugLoop);
13851#endif
13852 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
13853 if (RT_LIKELY(!pVmxTransient->fVectoringDoublePF))
13854 {
13855 pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
13856 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13857 0 /* cbInstr */, pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQualification);
13858 }
13859 else
13860 {
13861 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13862 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
13863 Log4(("Pending #DF due to vectoring #PF. NP\n"));
13864 }
13865 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13866 return rc;
13867 }
13868
13869 /* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
13870 of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
13871 if (pVmxTransient->fVectoringPF)
13872 {
13873 Assert(pVCpu->hm.s.Event.fPending);
13874 return VINF_EM_RAW_INJECT_TRPM_EVENT;
13875 }
13876
13877 rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13878 AssertRCReturn(rc, rc);
13879
13880 Log4(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQualification,
13881 pMixedCtx->cs.Sel, pMixedCtx->rip, pVmxTransient->uExitIntErrorCode, pMixedCtx->cr3));
13882
13883 TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQualification, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
13884 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pMixedCtx),
13885 (RTGCPTR)pVmxTransient->uExitQualification);
13886
13887 Log4(("#PF: rc=%Rrc\n", rc));
13888 if (rc == VINF_SUCCESS)
13889 {
13890#if 0
13891 /* Successfully synced shadow pages tables or emulated an MMIO instruction. */
13892 /** @todo this isn't quite right, what if guest does lgdt with some MMIO
13893 * memory? We don't update the whole state here... */
13894 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13895 | HM_CHANGED_GUEST_RSP
13896 | HM_CHANGED_GUEST_RFLAGS
13897 | HM_CHANGED_VMX_GUEST_APIC_STATE);
13898#else
13899 /*
13900 * This is typically a shadow page table sync or a MMIO instruction. But we may have
13901 * emulated something like LTR or a far jump. Any part of the CPU context may have changed.
13902 */
13903 /** @todo take advantage of CPUM changed flags instead of brute forcing. */
13904 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
13905#endif
13906 TRPMResetTrap(pVCpu);
13907 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
13908 return rc;
13909 }
13910
13911 if (rc == VINF_EM_RAW_GUEST_TRAP)
13912 {
13913 if (!pVmxTransient->fVectoringDoublePF)
13914 {
13915 /* It's a guest page fault and needs to be reflected to the guest. */
13916 uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);
13917 TRPMResetTrap(pVCpu);
13918 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
13919 pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
13920 hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13921 0 /* cbInstr */, uGstErrorCode, pVmxTransient->uExitQualification);
13922 }
13923 else
13924 {
13925 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13926 TRPMResetTrap(pVCpu);
13927 pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
13928 hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
13929 Log4(("#PF: Pending #DF due to vectoring #PF\n"));
13930 }
13931
13932 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13933 return VINF_SUCCESS;
13934 }
13935
13936 TRPMResetTrap(pVCpu);
13937 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
13938 return rc;
13939}
13940
13941/** @} */
13942
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