VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 73607

Last change on this file since 73607 was 73607, checked in by vboxsync, 7 years ago

VMM/HMVMXR0: Nested VMX: bugref:9180 Darwin build fix.
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1/* $Id: HMVMXR0.cpp 73607 2018-08-10 07:44:56Z vboxsync $ */
2/** @file
3 * HM VMX (Intel VT-x) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2012-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <iprt/x86.h>
25#include <iprt/asm-amd64-x86.h>
26#include <iprt/thread.h>
27
28#include <VBox/vmm/pdmapi.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iem.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/selm.h>
33#include <VBox/vmm/tm.h>
34#include <VBox/vmm/em.h>
35#include <VBox/vmm/gim.h>
36#include <VBox/vmm/apic.h>
37#ifdef VBOX_WITH_REM
38# include <VBox/vmm/rem.h>
39#endif
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include "HMVMXR0.h"
43#include "dtrace/VBoxVMM.h"
44
45#ifdef DEBUG_ramshankar
46# define HMVMX_ALWAYS_SAVE_GUEST_RFLAGS
47# define HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE
48# define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
49# define HMVMX_ALWAYS_CHECK_GUEST_STATE
50# define HMVMX_ALWAYS_TRAP_ALL_XCPTS
51# define HMVMX_ALWAYS_TRAP_PF
52# define HMVMX_ALWAYS_FLUSH_TLB
53# define HMVMX_ALWAYS_SWAP_EFER
54#endif
55
56
57/*********************************************************************************************************************************
58* Defined Constants And Macros *
59*********************************************************************************************************************************/
60/** Use the function table. */
61#define HMVMX_USE_FUNCTION_TABLE
62
63/** Determine which tagged-TLB flush handler to use. */
64#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
65#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
66#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
67#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
68
69/** @name HMVMX_READ_XXX
70 * Flags to skip redundant reads of some common VMCS fields that are not part of
71 * the guest-CPU or VCPU state but are needed while handling VM-exits.
72 */
73#define HMVMX_READ_IDT_VECTORING_INFO RT_BIT_32(0)
74#define HMVMX_READ_IDT_VECTORING_ERROR_CODE RT_BIT_32(1)
75#define HMVMX_READ_EXIT_QUALIFICATION RT_BIT_32(2)
76#define HMVMX_READ_EXIT_INSTR_LEN RT_BIT_32(3)
77#define HMVMX_READ_EXIT_INTERRUPTION_INFO RT_BIT_32(4)
78#define HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE RT_BIT_32(5)
79#define HMVMX_READ_EXIT_INSTR_INFO RT_BIT_32(6)
80/** @} */
81
82/**
83 * States of the VMCS.
84 *
85 * This does not reflect all possible VMCS states but currently only those
86 * needed for maintaining the VMCS consistently even when thread-context hooks
87 * are used. Maybe later this can be extended (i.e. Nested Virtualization).
88 */
89#define HMVMX_VMCS_STATE_CLEAR RT_BIT(0)
90#define HMVMX_VMCS_STATE_ACTIVE RT_BIT(1)
91#define HMVMX_VMCS_STATE_LAUNCHED RT_BIT(2)
92
93/**
94 * Subset of the guest-CPU state that is kept by VMX R0 code while executing the
95 * guest using hardware-assisted VMX.
96 *
97 * This excludes state like GPRs (other than RSP) which are always are
98 * swapped and restored across the world-switch and also registers like EFER,
99 * MSR which cannot be modified by the guest without causing a VM-exit.
100 */
101#define HMVMX_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
102 | CPUMCTX_EXTRN_RFLAGS \
103 | CPUMCTX_EXTRN_RSP \
104 | CPUMCTX_EXTRN_SREG_MASK \
105 | CPUMCTX_EXTRN_TABLE_MASK \
106 | CPUMCTX_EXTRN_KERNEL_GS_BASE \
107 | CPUMCTX_EXTRN_SYSCALL_MSRS \
108 | CPUMCTX_EXTRN_SYSENTER_MSRS \
109 | CPUMCTX_EXTRN_TSC_AUX \
110 | CPUMCTX_EXTRN_OTHER_MSRS \
111 | CPUMCTX_EXTRN_CR0 \
112 | CPUMCTX_EXTRN_CR3 \
113 | CPUMCTX_EXTRN_CR4 \
114 | CPUMCTX_EXTRN_DR7 \
115 | CPUMCTX_EXTRN_HM_VMX_MASK)
116
117/**
118 * Exception bitmap mask for real-mode guests (real-on-v86).
119 *
120 * We need to intercept all exceptions manually except:
121 * - \#AC and \#DB are always intercepted to prevent the CPU from deadlocking
122 * due to bugs in Intel CPUs.
123 * - \#PF need not be intercepted even in real-mode if we have Nested Paging
124 * support.
125 */
126#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) /* always: | RT_BIT(X86_XCPT_DB) */ | RT_BIT(X86_XCPT_NMI) \
127 | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) \
128 | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_DF) \
129 | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) \
130 | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
131 | RT_BIT(X86_XCPT_MF) /* always: | RT_BIT(X86_XCPT_AC) */ | RT_BIT(X86_XCPT_MC) \
132 | RT_BIT(X86_XCPT_XF))
133
134/** Maximum VM-instruction error number. */
135#define HMVMX_INSTR_ERROR_MAX 28
136
137/** Profiling macro. */
138#ifdef HM_PROFILE_EXIT_DISPATCH
139# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
140# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
141#else
142# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
143# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
144#endif
145
146/** Assert that preemption is disabled or covered by thread-context hooks. */
147#define HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
148 || !RTThreadPreemptIsEnabled(NIL_RTTHREAD))
149
150/** Assert that we haven't migrated CPUs when thread-context hooks are not
151 * used. */
152#define HMVMX_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
153 || (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
154 ("Illegal migration! Entered on CPU %u Current %u\n", \
155 (a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()))
156
157/** Asserts that the given CPUMCTX_EXTRN_XXX bits are present in the guest-CPU
158 * context. */
159#define HMVMX_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
160 ("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
161 (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
162
163/** Helper macro for VM-exit handlers called unexpectedly. */
164#define HMVMX_UNEXPECTED_EXIT_RET(a_pVCpu, a_pVmxTransient) \
165 do { \
166 (a_pVCpu)->hm.s.u32HMError = (a_pVmxTransient)->uExitReason; \
167 return VERR_VMX_UNEXPECTED_EXIT; \
168 } while (0)
169
170/** Macro for importing segment registers to the VMCS from the guest-CPU context. */
171#ifdef VMX_USE_CACHED_VMCS_ACCESSES
172# define HMVMX_IMPORT_SREG(Sel, a_pCtxSelReg) \
173 hmR0VmxImportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
174 VMX_VMCS_GUEST_##Sel##_BASE_CACHE_IDX, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
175#else
176# define HMVMX_IMPORT_SREG(Sel, a_pCtxSelReg) \
177 hmR0VmxImportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
178 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
179#endif
180
181/** Macro for exporting segment registers to the VMCS from the guest-CPU context. */
182# define HMVMX_EXPORT_SREG(Sel, a_pCtxSelReg) \
183 hmR0VmxExportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
184 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
185
186
187/*********************************************************************************************************************************
188* Structures and Typedefs *
189*********************************************************************************************************************************/
190/**
191 * VMX transient state.
192 *
193 * A state structure for holding miscellaneous information across
194 * VMX non-root operation and restored after the transition.
195 */
196typedef struct VMXTRANSIENT
197{
198 /** The host's rflags/eflags. */
199 RTCCUINTREG fEFlags;
200#if HC_ARCH_BITS == 32
201 uint32_t u32Alignment0;
202#endif
203 /** The guest's TPR value used for TPR shadowing. */
204 uint8_t u8GuestTpr;
205 /** Alignment. */
206 uint8_t abAlignment0[7];
207
208 /** The basic VM-exit reason. */
209 uint16_t uExitReason;
210 /** Alignment. */
211 uint16_t u16Alignment0;
212 /** The VM-exit interruption error code. */
213 uint32_t uExitIntErrorCode;
214 /** The VM-exit exit code qualification. */
215 uint64_t uExitQual;
216
217 /** The VM-exit interruption-information field. */
218 uint32_t uExitIntInfo;
219 /** The VM-exit instruction-length field. */
220 uint32_t cbInstr;
221 /** The VM-exit instruction-information field. */
222 VMXEXITINSTRINFO ExitInstrInfo;
223 /** Whether the VM-entry failed or not. */
224 bool fVMEntryFailed;
225 /** Alignment. */
226 uint8_t abAlignment1[3];
227
228 /** The VM-entry interruption-information field. */
229 uint32_t uEntryIntInfo;
230 /** The VM-entry exception error code field. */
231 uint32_t uEntryXcptErrorCode;
232 /** The VM-entry instruction length field. */
233 uint32_t cbEntryInstr;
234
235 /** IDT-vectoring information field. */
236 uint32_t uIdtVectoringInfo;
237 /** IDT-vectoring error code. */
238 uint32_t uIdtVectoringErrorCode;
239
240 /** Mask of currently read VMCS fields; HMVMX_READ_XXX. */
241 uint32_t fVmcsFieldsRead;
242
243 /** Whether the guest debug state was active at the time of VM-exit. */
244 bool fWasGuestDebugStateActive;
245 /** Whether the hyper debug state was active at the time of VM-exit. */
246 bool fWasHyperDebugStateActive;
247 /** Whether TSC-offsetting should be setup before VM-entry. */
248 bool fUpdateTscOffsettingAndPreemptTimer;
249 /** Whether the VM-exit was caused by a page-fault during delivery of a
250 * contributory exception or a page-fault. */
251 bool fVectoringDoublePF;
252 /** Whether the VM-exit was caused by a page-fault during delivery of an
253 * external interrupt or NMI. */
254 bool fVectoringPF;
255} VMXTRANSIENT;
256AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, sizeof(uint64_t));
257AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntInfo, sizeof(uint64_t));
258AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntInfo, sizeof(uint64_t));
259AssertCompileMemberAlignment(VMXTRANSIENT, fWasGuestDebugStateActive, sizeof(uint64_t));
260AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
261/** Pointer to VMX transient state. */
262typedef VMXTRANSIENT *PVMXTRANSIENT;
263
264
265/**
266 * MSR-bitmap read permissions.
267 */
268typedef enum VMXMSREXITREAD
269{
270 /** Reading this MSR causes a VM-exit. */
271 VMXMSREXIT_INTERCEPT_READ = 0xb,
272 /** Reading this MSR does not cause a VM-exit. */
273 VMXMSREXIT_PASSTHRU_READ
274} VMXMSREXITREAD;
275/** Pointer to MSR-bitmap read permissions. */
276typedef VMXMSREXITREAD* PVMXMSREXITREAD;
277
278/**
279 * MSR-bitmap write permissions.
280 */
281typedef enum VMXMSREXITWRITE
282{
283 /** Writing to this MSR causes a VM-exit. */
284 VMXMSREXIT_INTERCEPT_WRITE = 0xd,
285 /** Writing to this MSR does not cause a VM-exit. */
286 VMXMSREXIT_PASSTHRU_WRITE
287} VMXMSREXITWRITE;
288/** Pointer to MSR-bitmap write permissions. */
289typedef VMXMSREXITWRITE* PVMXMSREXITWRITE;
290
291
292/**
293 * VMX VM-exit handler.
294 *
295 * @returns Strict VBox status code (i.e. informational status codes too).
296 * @param pVCpu The cross context virtual CPU structure.
297 * @param pVmxTransient Pointer to the VMX-transient structure.
298 */
299#ifndef HMVMX_USE_FUNCTION_TABLE
300typedef VBOXSTRICTRC FNVMXEXITHANDLER(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
301#else
302typedef DECLCALLBACK(VBOXSTRICTRC) FNVMXEXITHANDLER(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
303/** Pointer to VM-exit handler. */
304typedef FNVMXEXITHANDLER *PFNVMXEXITHANDLER;
305#endif
306
307/**
308 * VMX VM-exit handler, non-strict status code.
309 *
310 * This is generally the same as FNVMXEXITHANDLER, the NSRC bit is just FYI.
311 *
312 * @returns VBox status code, no informational status code returned.
313 * @param pVCpu The cross context virtual CPU structure.
314 * @param pVmxTransient Pointer to the VMX-transient structure.
315 *
316 * @remarks This is not used on anything returning VERR_EM_INTERPRETER as the
317 * use of that status code will be replaced with VINF_EM_SOMETHING
318 * later when switching over to IEM.
319 */
320#ifndef HMVMX_USE_FUNCTION_TABLE
321typedef int FNVMXEXITHANDLERNSRC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
322#else
323typedef FNVMXEXITHANDLER FNVMXEXITHANDLERNSRC;
324#endif
325
326
327/*********************************************************************************************************************************
328* Internal Functions *
329*********************************************************************************************************************************/
330static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXTLBFLUSHEPT enmTlbFlush);
331static void hmR0VmxFlushVpid(PVMCPU pVCpu, VMXTLBFLUSHVPID enmTlbFlush, RTGCPTR GCPtr);
332static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu);
333static int hmR0VmxImportGuestState(PVMCPU pVCpu, uint64_t fWhat);
334static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
335 RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *pfIntrState);
336#if HC_ARCH_BITS == 32
337static int hmR0VmxInitVmcsReadCache(PVMCPU pVCpu);
338#endif
339#ifndef HMVMX_USE_FUNCTION_TABLE
340DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t rcReason);
341# define HMVMX_EXIT_DECL DECLINLINE(VBOXSTRICTRC)
342# define HMVMX_EXIT_NSRC_DECL DECLINLINE(int)
343#else
344# define HMVMX_EXIT_DECL static DECLCALLBACK(VBOXSTRICTRC)
345# define HMVMX_EXIT_NSRC_DECL HMVMX_EXIT_DECL
346#endif
347
348
349/** @name VM-exit handlers.
350 * @{
351 */
352static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmi;
353static FNVMXEXITHANDLER hmR0VmxExitExtInt;
354static FNVMXEXITHANDLER hmR0VmxExitTripleFault;
355static FNVMXEXITHANDLERNSRC hmR0VmxExitInitSignal;
356static FNVMXEXITHANDLERNSRC hmR0VmxExitSipi;
357static FNVMXEXITHANDLERNSRC hmR0VmxExitIoSmi;
358static FNVMXEXITHANDLERNSRC hmR0VmxExitSmi;
359static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindow;
360static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindow;
361static FNVMXEXITHANDLER hmR0VmxExitTaskSwitch;
362static FNVMXEXITHANDLER hmR0VmxExitCpuid;
363static FNVMXEXITHANDLER hmR0VmxExitGetsec;
364static FNVMXEXITHANDLER hmR0VmxExitHlt;
365static FNVMXEXITHANDLERNSRC hmR0VmxExitInvd;
366static FNVMXEXITHANDLER hmR0VmxExitInvlpg;
367static FNVMXEXITHANDLER hmR0VmxExitRdpmc;
368static FNVMXEXITHANDLER hmR0VmxExitVmcall;
369#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
370static FNVMXEXITHANDLER hmR0VmxExitVmclear;
371static FNVMXEXITHANDLER hmR0VmxExitVmlaunch;
372static FNVMXEXITHANDLER hmR0VmxExitVmptrld;
373static FNVMXEXITHANDLER hmR0VmxExitVmptrst;
374static FNVMXEXITHANDLER hmR0VmxExitVmread;
375static FNVMXEXITHANDLER hmR0VmxExitVmresume;
376static FNVMXEXITHANDLER hmR0VmxExitVmwrite;
377static FNVMXEXITHANDLER hmR0VmxExitVmxoff;
378static FNVMXEXITHANDLER hmR0VmxExitVmxon;
379#endif
380static FNVMXEXITHANDLER hmR0VmxExitRdtsc;
381static FNVMXEXITHANDLERNSRC hmR0VmxExitRsm;
382static FNVMXEXITHANDLERNSRC hmR0VmxExitSetPendingXcptUD;
383static FNVMXEXITHANDLER hmR0VmxExitMovCRx;
384static FNVMXEXITHANDLER hmR0VmxExitMovDRx;
385static FNVMXEXITHANDLER hmR0VmxExitIoInstr;
386static FNVMXEXITHANDLER hmR0VmxExitRdmsr;
387static FNVMXEXITHANDLER hmR0VmxExitWrmsr;
388static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestState;
389static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMsrLoad;
390static FNVMXEXITHANDLERNSRC hmR0VmxExitErrUndefined;
391static FNVMXEXITHANDLER hmR0VmxExitMwait;
392static FNVMXEXITHANDLER hmR0VmxExitMtf;
393static FNVMXEXITHANDLER hmR0VmxExitMonitor;
394static FNVMXEXITHANDLER hmR0VmxExitPause;
395static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMachineCheck;
396static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThreshold;
397static FNVMXEXITHANDLER hmR0VmxExitApicAccess;
398static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
399static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
400static FNVMXEXITHANDLER hmR0VmxExitEptViolation;
401static FNVMXEXITHANDLER hmR0VmxExitEptMisconfig;
402static FNVMXEXITHANDLER hmR0VmxExitRdtscp;
403static FNVMXEXITHANDLER hmR0VmxExitPreemptTimer;
404static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvd;
405static FNVMXEXITHANDLER hmR0VmxExitXsetbv;
406static FNVMXEXITHANDLER hmR0VmxExitRdrand;
407static FNVMXEXITHANDLER hmR0VmxExitInvpcid;
408/** @} */
409
410static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
411static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
412static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
413static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
414static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
415static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
416static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
417static uint32_t hmR0VmxCheckGuestState(PVMCPU pVCpu);
418
419
420/*********************************************************************************************************************************
421* Global Variables *
422*********************************************************************************************************************************/
423#ifdef HMVMX_USE_FUNCTION_TABLE
424
425/**
426 * VMX_EXIT dispatch table.
427 */
428static const PFNVMXEXITHANDLER g_apfnVMExitHandlers[VMX_EXIT_MAX + 1] =
429{
430 /* 00 VMX_EXIT_XCPT_OR_NMI */ hmR0VmxExitXcptOrNmi,
431 /* 01 VMX_EXIT_EXT_INT */ hmR0VmxExitExtInt,
432 /* 02 VMX_EXIT_TRIPLE_FAULT */ hmR0VmxExitTripleFault,
433 /* 03 VMX_EXIT_INIT_SIGNAL */ hmR0VmxExitInitSignal,
434 /* 04 VMX_EXIT_SIPI */ hmR0VmxExitSipi,
435 /* 05 VMX_EXIT_IO_SMI */ hmR0VmxExitIoSmi,
436 /* 06 VMX_EXIT_SMI */ hmR0VmxExitSmi,
437 /* 07 VMX_EXIT_INT_WINDOW */ hmR0VmxExitIntWindow,
438 /* 08 VMX_EXIT_NMI_WINDOW */ hmR0VmxExitNmiWindow,
439 /* 09 VMX_EXIT_TASK_SWITCH */ hmR0VmxExitTaskSwitch,
440 /* 10 VMX_EXIT_CPUID */ hmR0VmxExitCpuid,
441 /* 11 VMX_EXIT_GETSEC */ hmR0VmxExitGetsec,
442 /* 12 VMX_EXIT_HLT */ hmR0VmxExitHlt,
443 /* 13 VMX_EXIT_INVD */ hmR0VmxExitInvd,
444 /* 14 VMX_EXIT_INVLPG */ hmR0VmxExitInvlpg,
445 /* 15 VMX_EXIT_RDPMC */ hmR0VmxExitRdpmc,
446 /* 16 VMX_EXIT_RDTSC */ hmR0VmxExitRdtsc,
447 /* 17 VMX_EXIT_RSM */ hmR0VmxExitRsm,
448 /* 18 VMX_EXIT_VMCALL */ hmR0VmxExitVmcall,
449#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
450 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitVmclear,
451 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitVmlaunch,
452 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitVmptrld,
453 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitVmptrst,
454 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitVmread,
455 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitVmresume,
456 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitVmwrite,
457 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitVmxoff,
458 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitVmxon,
459#else
460 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitSetPendingXcptUD,
461 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitSetPendingXcptUD,
462 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitSetPendingXcptUD,
463 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitSetPendingXcptUD,
464 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitSetPendingXcptUD,
465 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitSetPendingXcptUD,
466 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitSetPendingXcptUD,
467 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitSetPendingXcptUD,
468 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitSetPendingXcptUD,
469#endif
470 /* 28 VMX_EXIT_MOV_CRX */ hmR0VmxExitMovCRx,
471 /* 29 VMX_EXIT_MOV_DRX */ hmR0VmxExitMovDRx,
472 /* 30 VMX_EXIT_IO_INSTR */ hmR0VmxExitIoInstr,
473 /* 31 VMX_EXIT_RDMSR */ hmR0VmxExitRdmsr,
474 /* 32 VMX_EXIT_WRMSR */ hmR0VmxExitWrmsr,
475 /* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ hmR0VmxExitErrInvalidGuestState,
476 /* 34 VMX_EXIT_ERR_MSR_LOAD */ hmR0VmxExitErrMsrLoad,
477 /* 35 UNDEFINED */ hmR0VmxExitErrUndefined,
478 /* 36 VMX_EXIT_MWAIT */ hmR0VmxExitMwait,
479 /* 37 VMX_EXIT_MTF */ hmR0VmxExitMtf,
480 /* 38 UNDEFINED */ hmR0VmxExitErrUndefined,
481 /* 39 VMX_EXIT_MONITOR */ hmR0VmxExitMonitor,
482 /* 40 UNDEFINED */ hmR0VmxExitPause,
483 /* 41 VMX_EXIT_PAUSE */ hmR0VmxExitErrMachineCheck,
484 /* 42 VMX_EXIT_ERR_MACHINE_CHECK */ hmR0VmxExitErrUndefined,
485 /* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ hmR0VmxExitTprBelowThreshold,
486 /* 44 VMX_EXIT_APIC_ACCESS */ hmR0VmxExitApicAccess,
487 /* 45 UNDEFINED */ hmR0VmxExitErrUndefined,
488 /* 46 VMX_EXIT_XDTR_ACCESS */ hmR0VmxExitXdtrAccess,
489 /* 47 VMX_EXIT_TR_ACCESS */ hmR0VmxExitXdtrAccess,
490 /* 48 VMX_EXIT_EPT_VIOLATION */ hmR0VmxExitEptViolation,
491 /* 49 VMX_EXIT_EPT_MISCONFIG */ hmR0VmxExitEptMisconfig,
492 /* 50 VMX_EXIT_INVEPT */ hmR0VmxExitSetPendingXcptUD,
493 /* 51 VMX_EXIT_RDTSCP */ hmR0VmxExitRdtscp,
494 /* 52 VMX_EXIT_PREEMPT_TIMER */ hmR0VmxExitPreemptTimer,
495 /* 53 VMX_EXIT_INVVPID */ hmR0VmxExitSetPendingXcptUD,
496 /* 54 VMX_EXIT_WBINVD */ hmR0VmxExitWbinvd,
497 /* 55 VMX_EXIT_XSETBV */ hmR0VmxExitXsetbv,
498 /* 56 VMX_EXIT_APIC_WRITE */ hmR0VmxExitErrUndefined,
499 /* 57 VMX_EXIT_RDRAND */ hmR0VmxExitRdrand,
500 /* 58 VMX_EXIT_INVPCID */ hmR0VmxExitInvpcid,
501 /* 59 VMX_EXIT_VMFUNC */ hmR0VmxExitSetPendingXcptUD,
502 /* 60 VMX_EXIT_ENCLS */ hmR0VmxExitErrUndefined,
503 /* 61 VMX_EXIT_RDSEED */ hmR0VmxExitErrUndefined, /* only spurious exits, so undefined */
504 /* 62 VMX_EXIT_PML_FULL */ hmR0VmxExitErrUndefined,
505 /* 63 VMX_EXIT_XSAVES */ hmR0VmxExitSetPendingXcptUD,
506 /* 64 VMX_EXIT_XRSTORS */ hmR0VmxExitSetPendingXcptUD,
507};
508#endif /* HMVMX_USE_FUNCTION_TABLE */
509
510#ifdef VBOX_STRICT
511static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
512{
513 /* 0 */ "(Not Used)",
514 /* 1 */ "VMCALL executed in VMX root operation.",
515 /* 2 */ "VMCLEAR with invalid physical address.",
516 /* 3 */ "VMCLEAR with VMXON pointer.",
517 /* 4 */ "VMLAUNCH with non-clear VMCS.",
518 /* 5 */ "VMRESUME with non-launched VMCS.",
519 /* 6 */ "VMRESUME after VMXOFF",
520 /* 7 */ "VM-entry with invalid control fields.",
521 /* 8 */ "VM-entry with invalid host state fields.",
522 /* 9 */ "VMPTRLD with invalid physical address.",
523 /* 10 */ "VMPTRLD with VMXON pointer.",
524 /* 11 */ "VMPTRLD with incorrect revision identifier.",
525 /* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
526 /* 13 */ "VMWRITE to read-only VMCS component.",
527 /* 14 */ "(Not Used)",
528 /* 15 */ "VMXON executed in VMX root operation.",
529 /* 16 */ "VM-entry with invalid executive-VMCS pointer.",
530 /* 17 */ "VM-entry with non-launched executing VMCS.",
531 /* 18 */ "VM-entry with executive-VMCS pointer not VMXON pointer.",
532 /* 19 */ "VMCALL with non-clear VMCS.",
533 /* 20 */ "VMCALL with invalid VM-exit control fields.",
534 /* 21 */ "(Not Used)",
535 /* 22 */ "VMCALL with incorrect MSEG revision identifier.",
536 /* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
537 /* 24 */ "VMCALL with invalid SMM-monitor features.",
538 /* 25 */ "VM-entry with invalid VM-execution control fields in executive VMCS.",
539 /* 26 */ "VM-entry with events blocked by MOV SS.",
540 /* 27 */ "(Not Used)",
541 /* 28 */ "Invalid operand to INVEPT/INVVPID."
542};
543#endif /* VBOX_STRICT */
544
545
546
547/**
548 * Updates the VM's last error record.
549 *
550 * If there was a VMX instruction error, reads the error data from the VMCS and
551 * updates VCPU's last error record as well.
552 *
553 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
554 * Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
555 * VERR_VMX_INVALID_VMCS_FIELD.
556 * @param rc The error code.
557 */
558static void hmR0VmxUpdateErrorRecord(PVMCPU pVCpu, int rc)
559{
560 if ( rc == VERR_VMX_INVALID_VMCS_FIELD
561 || rc == VERR_VMX_UNABLE_TO_START_VM)
562 {
563 AssertPtrReturnVoid(pVCpu);
564 VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
565 }
566 pVCpu->CTX_SUFF(pVM)->hm.s.rcInit = rc;
567}
568
569
570/**
571 * Reads the VM-entry interruption-information field from the VMCS into the VMX
572 * transient structure.
573 *
574 * @returns VBox status code.
575 * @param pVmxTransient Pointer to the VMX transient structure.
576 *
577 * @remarks No-long-jump zone!!!
578 */
579DECLINLINE(int) hmR0VmxReadEntryIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
580{
581 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);
582 AssertRCReturn(rc, rc);
583 return VINF_SUCCESS;
584}
585
586#ifdef VBOX_STRICT
587/**
588 * Reads the VM-entry exception error code field from the VMCS into
589 * the VMX transient structure.
590 *
591 * @returns VBox status code.
592 * @param pVmxTransient Pointer to the VMX transient structure.
593 *
594 * @remarks No-long-jump zone!!!
595 */
596DECLINLINE(int) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
597{
598 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
599 AssertRCReturn(rc, rc);
600 return VINF_SUCCESS;
601}
602
603
604/**
605 * Reads the VM-entry exception error code field from the VMCS into
606 * the VMX transient structure.
607 *
608 * @returns VBox status code.
609 * @param pVmxTransient Pointer to the VMX transient structure.
610 *
611 * @remarks No-long-jump zone!!!
612 */
613DECLINLINE(int) hmR0VmxReadEntryInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
614{
615 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
616 AssertRCReturn(rc, rc);
617 return VINF_SUCCESS;
618}
619#endif /* VBOX_STRICT */
620
621
622/**
623 * Reads the VM-exit interruption-information field from the VMCS into the VMX
624 * transient structure.
625 *
626 * @returns VBox status code.
627 * @param pVmxTransient Pointer to the VMX transient structure.
628 */
629DECLINLINE(int) hmR0VmxReadExitIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
630{
631 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_INFO))
632 {
633 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
634 AssertRCReturn(rc,rc);
635 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_INFO;
636 }
637 return VINF_SUCCESS;
638}
639
640
641/**
642 * Reads the VM-exit interruption error code from the VMCS into the VMX
643 * transient structure.
644 *
645 * @returns VBox status code.
646 * @param pVmxTransient Pointer to the VMX transient structure.
647 */
648DECLINLINE(int) hmR0VmxReadExitIntErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
649{
650 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE))
651 {
652 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
653 AssertRCReturn(rc, rc);
654 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE;
655 }
656 return VINF_SUCCESS;
657}
658
659
660/**
661 * Reads the VM-exit instruction length field from the VMCS into the VMX
662 * transient structure.
663 *
664 * @returns VBox status code.
665 * @param pVmxTransient Pointer to the VMX transient structure.
666 */
667DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
668{
669 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_LEN))
670 {
671 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
672 AssertRCReturn(rc, rc);
673 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_LEN;
674 }
675 return VINF_SUCCESS;
676}
677
678
679/**
680 * Reads the VM-exit instruction-information field from the VMCS into
681 * the VMX transient structure.
682 *
683 * @returns VBox status code.
684 * @param pVmxTransient Pointer to the VMX transient structure.
685 */
686DECLINLINE(int) hmR0VmxReadExitInstrInfoVmcs(PVMXTRANSIENT pVmxTransient)
687{
688 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_INFO))
689 {
690 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
691 AssertRCReturn(rc, rc);
692 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_INFO;
693 }
694 return VINF_SUCCESS;
695}
696
697
698/**
699 * Reads the exit code qualification from the VMCS into the VMX transient
700 * structure.
701 *
702 * @returns VBox status code.
703 * @param pVCpu The cross context virtual CPU structure of the
704 * calling EMT. (Required for the VMCS cache case.)
705 * @param pVmxTransient Pointer to the VMX transient structure.
706 */
707DECLINLINE(int) hmR0VmxReadExitQualVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
708{
709 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_QUALIFICATION))
710 {
711 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual); NOREF(pVCpu);
712 AssertRCReturn(rc, rc);
713 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_QUALIFICATION;
714 }
715 return VINF_SUCCESS;
716}
717
718
719/**
720 * Reads the IDT-vectoring information field from the VMCS into the VMX
721 * transient structure.
722 *
723 * @returns VBox status code.
724 * @param pVmxTransient Pointer to the VMX transient structure.
725 *
726 * @remarks No-long-jump zone!!!
727 */
728DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
729{
730 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_INFO))
731 {
732 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo);
733 AssertRCReturn(rc, rc);
734 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_INFO;
735 }
736 return VINF_SUCCESS;
737}
738
739
740/**
741 * Reads the IDT-vectoring error code from the VMCS into the VMX
742 * transient structure.
743 *
744 * @returns VBox status code.
745 * @param pVmxTransient Pointer to the VMX transient structure.
746 */
747DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
748{
749 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_ERROR_CODE))
750 {
751 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
752 AssertRCReturn(rc, rc);
753 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_ERROR_CODE;
754 }
755 return VINF_SUCCESS;
756}
757
758
759/**
760 * Enters VMX root mode operation on the current CPU.
761 *
762 * @returns VBox status code.
763 * @param pVM The cross context VM structure. Can be
764 * NULL, after a resume.
765 * @param HCPhysCpuPage Physical address of the VMXON region.
766 * @param pvCpuPage Pointer to the VMXON region.
767 */
768static int hmR0VmxEnterRootMode(PVM pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
769{
770 Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
771 Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
772 Assert(pvCpuPage);
773 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
774
775 if (pVM)
776 {
777 /* Write the VMCS revision dword to the VMXON region. */
778 *(uint32_t *)pvCpuPage = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
779 }
780
781 /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
782 RTCCUINTREG fEFlags = ASMIntDisableFlags();
783
784 /* Enable the VMX bit in CR4 if necessary. */
785 RTCCUINTREG uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
786
787 /* Enter VMX root mode. */
788 int rc = VMXEnable(HCPhysCpuPage);
789 if (RT_FAILURE(rc))
790 {
791 if (!(uOldCr4 & X86_CR4_VMXE))
792 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
793
794 if (pVM)
795 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
796 }
797
798 /* Restore interrupts. */
799 ASMSetFlags(fEFlags);
800 return rc;
801}
802
803
804/**
805 * Exits VMX root mode operation on the current CPU.
806 *
807 * @returns VBox status code.
808 */
809static int hmR0VmxLeaveRootMode(void)
810{
811 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
812
813 /* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
814 RTCCUINTREG fEFlags = ASMIntDisableFlags();
815
816 /* If we're for some reason not in VMX root mode, then don't leave it. */
817 RTCCUINTREG uHostCR4 = ASMGetCR4();
818
819 int rc;
820 if (uHostCR4 & X86_CR4_VMXE)
821 {
822 /* Exit VMX root mode and clear the VMX bit in CR4. */
823 VMXDisable();
824 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
825 rc = VINF_SUCCESS;
826 }
827 else
828 rc = VERR_VMX_NOT_IN_VMX_ROOT_MODE;
829
830 /* Restore interrupts. */
831 ASMSetFlags(fEFlags);
832 return rc;
833}
834
835
836/**
837 * Allocates and maps one physically contiguous page. The allocated page is
838 * zero'd out. (Used by various VT-x structures).
839 *
840 * @returns IPRT status code.
841 * @param pMemObj Pointer to the ring-0 memory object.
842 * @param ppVirt Where to store the virtual address of the
843 * allocation.
844 * @param pHCPhys Where to store the physical address of the
845 * allocation.
846 */
847static int hmR0VmxPageAllocZ(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
848{
849 AssertPtrReturn(pMemObj, VERR_INVALID_PARAMETER);
850 AssertPtrReturn(ppVirt, VERR_INVALID_PARAMETER);
851 AssertPtrReturn(pHCPhys, VERR_INVALID_PARAMETER);
852
853 int rc = RTR0MemObjAllocCont(pMemObj, PAGE_SIZE, false /* fExecutable */);
854 if (RT_FAILURE(rc))
855 return rc;
856 *ppVirt = RTR0MemObjAddress(*pMemObj);
857 *pHCPhys = RTR0MemObjGetPagePhysAddr(*pMemObj, 0 /* iPage */);
858 ASMMemZero32(*ppVirt, PAGE_SIZE);
859 return VINF_SUCCESS;
860}
861
862
863/**
864 * Frees and unmaps an allocated physical page.
865 *
866 * @param pMemObj Pointer to the ring-0 memory object.
867 * @param ppVirt Where to re-initialize the virtual address of
868 * allocation as 0.
869 * @param pHCPhys Where to re-initialize the physical address of the
870 * allocation as 0.
871 */
872static void hmR0VmxPageFree(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
873{
874 AssertPtr(pMemObj);
875 AssertPtr(ppVirt);
876 AssertPtr(pHCPhys);
877 if (*pMemObj != NIL_RTR0MEMOBJ)
878 {
879 int rc = RTR0MemObjFree(*pMemObj, true /* fFreeMappings */);
880 AssertRC(rc);
881 *pMemObj = NIL_RTR0MEMOBJ;
882 *ppVirt = 0;
883 *pHCPhys = 0;
884 }
885}
886
887
888/**
889 * Worker function to free VT-x related structures.
890 *
891 * @returns IPRT status code.
892 * @param pVM The cross context VM structure.
893 */
894static void hmR0VmxStructsFree(PVM pVM)
895{
896 for (VMCPUID i = 0; i < pVM->cCpus; i++)
897 {
898 PVMCPU pVCpu = &pVM->aCpus[i];
899 AssertPtr(pVCpu);
900
901 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
902 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
903
904 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
905 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
906
907 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
908 }
909
910 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, &pVM->hm.s.vmx.HCPhysApicAccess);
911#ifdef VBOX_WITH_CRASHDUMP_MAGIC
912 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
913#endif
914}
915
916
917/**
918 * Worker function to allocate VT-x related VM structures.
919 *
920 * @returns IPRT status code.
921 * @param pVM The cross context VM structure.
922 */
923static int hmR0VmxStructsAlloc(PVM pVM)
924{
925 /*
926 * Initialize members up-front so we can cleanup properly on allocation failure.
927 */
928#define VMXLOCAL_INIT_VM_MEMOBJ(a_Name, a_VirtPrefix) \
929 pVM->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
930 pVM->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
931 pVM->hm.s.vmx.HCPhys##a_Name = 0;
932
933#define VMXLOCAL_INIT_VMCPU_MEMOBJ(a_Name, a_VirtPrefix) \
934 pVCpu->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
935 pVCpu->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
936 pVCpu->hm.s.vmx.HCPhys##a_Name = 0;
937
938#ifdef VBOX_WITH_CRASHDUMP_MAGIC
939 VMXLOCAL_INIT_VM_MEMOBJ(Scratch, pv);
940#endif
941 VMXLOCAL_INIT_VM_MEMOBJ(ApicAccess, pb);
942
943 AssertCompile(sizeof(VMCPUID) == sizeof(pVM->cCpus));
944 for (VMCPUID i = 0; i < pVM->cCpus; i++)
945 {
946 PVMCPU pVCpu = &pVM->aCpus[i];
947 VMXLOCAL_INIT_VMCPU_MEMOBJ(Vmcs, pv);
948 VMXLOCAL_INIT_VMCPU_MEMOBJ(MsrBitmap, pv);
949 VMXLOCAL_INIT_VMCPU_MEMOBJ(GuestMsr, pv);
950 VMXLOCAL_INIT_VMCPU_MEMOBJ(HostMsr, pv);
951 }
952#undef VMXLOCAL_INIT_VMCPU_MEMOBJ
953#undef VMXLOCAL_INIT_VM_MEMOBJ
954
955 /* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
956 AssertReturnStmt(RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_SIZE) <= PAGE_SIZE,
957 (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
958 VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
959
960 /*
961 * Allocate all the VT-x structures.
962 */
963 int rc = VINF_SUCCESS;
964#ifdef VBOX_WITH_CRASHDUMP_MAGIC
965 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
966 if (RT_FAILURE(rc))
967 goto cleanup;
968 strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
969 *(uint64_t *)(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
970#endif
971
972 /* Allocate the APIC-access page for trapping APIC accesses from the guest. */
973 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
974 {
975 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
976 &pVM->hm.s.vmx.HCPhysApicAccess);
977 if (RT_FAILURE(rc))
978 goto cleanup;
979 }
980
981 /*
982 * Initialize per-VCPU VT-x structures.
983 */
984 for (VMCPUID i = 0; i < pVM->cCpus; i++)
985 {
986 PVMCPU pVCpu = &pVM->aCpus[i];
987 AssertPtr(pVCpu);
988
989 /* Allocate the VM control structure (VMCS). */
990 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
991 if (RT_FAILURE(rc))
992 goto cleanup;
993
994 /* Get the allocated virtual-APIC page from the APIC device for transparent TPR accesses. */
995 if ( PDMHasApic(pVM)
996 && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
997 {
998 rc = APICGetApicPageForCpu(pVCpu, &pVCpu->hm.s.vmx.HCPhysVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
999 NULL /* pR3Ptr */, NULL /* pRCPtr */);
1000 if (RT_FAILURE(rc))
1001 goto cleanup;
1002 }
1003
1004 /*
1005 * Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for
1006 * transparent accesses of specific MSRs.
1007 *
1008 * If the condition for enabling MSR bitmaps changes here, don't forget to
1009 * update HMAreMsrBitmapsAvailable().
1010 */
1011 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1012 {
1013 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
1014 &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1015 if (RT_FAILURE(rc))
1016 goto cleanup;
1017 ASMMemFill32(pVCpu->hm.s.vmx.pvMsrBitmap, PAGE_SIZE, UINT32_C(0xffffffff));
1018 }
1019
1020 /* Allocate the VM-entry MSR-load and VM-exit MSR-store page for the guest MSRs. */
1021 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
1022 if (RT_FAILURE(rc))
1023 goto cleanup;
1024
1025 /* Allocate the VM-exit MSR-load page for the host MSRs. */
1026 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
1027 if (RT_FAILURE(rc))
1028 goto cleanup;
1029 }
1030
1031 return VINF_SUCCESS;
1032
1033cleanup:
1034 hmR0VmxStructsFree(pVM);
1035 return rc;
1036}
1037
1038
1039/**
1040 * Does global VT-x initialization (called during module initialization).
1041 *
1042 * @returns VBox status code.
1043 */
1044VMMR0DECL(int) VMXR0GlobalInit(void)
1045{
1046#ifdef HMVMX_USE_FUNCTION_TABLE
1047 AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_apfnVMExitHandlers));
1048# ifdef VBOX_STRICT
1049 for (unsigned i = 0; i < RT_ELEMENTS(g_apfnVMExitHandlers); i++)
1050 Assert(g_apfnVMExitHandlers[i]);
1051# endif
1052#endif
1053 return VINF_SUCCESS;
1054}
1055
1056
1057/**
1058 * Does global VT-x termination (called during module termination).
1059 */
1060VMMR0DECL(void) VMXR0GlobalTerm()
1061{
1062 /* Nothing to do currently. */
1063}
1064
1065
1066/**
1067 * Sets up and activates VT-x on the current CPU.
1068 *
1069 * @returns VBox status code.
1070 * @param pHostCpu Pointer to the global CPU info struct.
1071 * @param pVM The cross context VM structure. Can be
1072 * NULL after a host resume operation.
1073 * @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
1074 * fEnabledByHost is @c true).
1075 * @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
1076 * @a fEnabledByHost is @c true).
1077 * @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
1078 * enable VT-x on the host.
1079 * @param pvMsrs Opaque pointer to VMXMSRS struct.
1080 */
1081VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
1082 void *pvMsrs)
1083{
1084 Assert(pHostCpu);
1085 Assert(pvMsrs);
1086 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1087
1088 /* Enable VT-x if it's not already enabled by the host. */
1089 if (!fEnabledByHost)
1090 {
1091 int rc = hmR0VmxEnterRootMode(pVM, HCPhysCpuPage, pvCpuPage);
1092 if (RT_FAILURE(rc))
1093 return rc;
1094 }
1095
1096 /*
1097 * Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been
1098 * using EPTPs) so we don't retain any stale guest-physical mappings which won't get
1099 * invalidated when flushing by VPID.
1100 */
1101 PVMXMSRS pMsrs = (PVMXMSRS)pvMsrs;
1102 if (pMsrs->u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1103 {
1104 hmR0VmxFlushEpt(NULL /* pVCpu */, VMXTLBFLUSHEPT_ALL_CONTEXTS);
1105 pHostCpu->fFlushAsidBeforeUse = false;
1106 }
1107 else
1108 pHostCpu->fFlushAsidBeforeUse = true;
1109
1110 /* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
1111 ++pHostCpu->cTlbFlushes;
1112
1113 return VINF_SUCCESS;
1114}
1115
1116
1117/**
1118 * Deactivates VT-x on the current CPU.
1119 *
1120 * @returns VBox status code.
1121 * @param pHostCpu Pointer to the global CPU info struct.
1122 * @param pvCpuPage Pointer to the VMXON region.
1123 * @param HCPhysCpuPage Physical address of the VMXON region.
1124 *
1125 * @remarks This function should never be called when SUPR0EnableVTx() or
1126 * similar was used to enable VT-x on the host.
1127 */
1128VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
1129{
1130 RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
1131
1132 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1133 return hmR0VmxLeaveRootMode();
1134}
1135
1136
1137/**
1138 * Sets the permission bits for the specified MSR in the MSR bitmap.
1139 *
1140 * @param pVCpu The cross context virtual CPU structure.
1141 * @param uMsr The MSR value.
1142 * @param enmRead Whether reading this MSR causes a VM-exit.
1143 * @param enmWrite Whether writing this MSR causes a VM-exit.
1144 */
1145static void hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite)
1146{
1147 int32_t iBit;
1148 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1149
1150 /*
1151 * Layout:
1152 * 0x000 - 0x3ff - Low MSR read bits
1153 * 0x400 - 0x7ff - High MSR read bits
1154 * 0x800 - 0xbff - Low MSR write bits
1155 * 0xc00 - 0xfff - High MSR write bits
1156 */
1157 if (uMsr <= 0x00001fff)
1158 iBit = uMsr;
1159 else if (uMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
1160 {
1161 iBit = uMsr - UINT32_C(0xc0000000);
1162 pbMsrBitmap += 0x400;
1163 }
1164 else
1165 AssertMsgFailedReturnVoid(("hmR0VmxSetMsrPermission: Invalid MSR %#RX32\n", uMsr));
1166
1167 Assert(iBit <= 0x1fff);
1168 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
1169 ASMBitSet(pbMsrBitmap, iBit);
1170 else
1171 ASMBitClear(pbMsrBitmap, iBit);
1172
1173 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
1174 ASMBitSet(pbMsrBitmap + 0x800, iBit);
1175 else
1176 ASMBitClear(pbMsrBitmap + 0x800, iBit);
1177}
1178
1179
1180#ifdef VBOX_STRICT
1181/**
1182 * Gets the permission bits for the specified MSR in the MSR bitmap.
1183 *
1184 * @returns VBox status code.
1185 * @retval VINF_SUCCESS if the specified MSR is found.
1186 * @retval VERR_NOT_FOUND if the specified MSR is not found.
1187 * @retval VERR_NOT_SUPPORTED if VT-x doesn't allow the MSR.
1188 *
1189 * @param pVCpu The cross context virtual CPU structure.
1190 * @param uMsr The MSR.
1191 * @param penmRead Where to store the read permissions.
1192 * @param penmWrite Where to store the write permissions.
1193 */
1194static int hmR0VmxGetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, PVMXMSREXITREAD penmRead, PVMXMSREXITWRITE penmWrite)
1195{
1196 AssertPtrReturn(penmRead, VERR_INVALID_PARAMETER);
1197 AssertPtrReturn(penmWrite, VERR_INVALID_PARAMETER);
1198 int32_t iBit;
1199 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1200
1201 /* See hmR0VmxSetMsrPermission() for the layout. */
1202 if (uMsr <= 0x00001fff)
1203 iBit = uMsr;
1204 else if ( uMsr >= 0xc0000000
1205 && uMsr <= 0xc0001fff)
1206 {
1207 iBit = (uMsr - 0xc0000000);
1208 pbMsrBitmap += 0x400;
1209 }
1210 else
1211 AssertMsgFailedReturn(("hmR0VmxGetMsrPermission: Invalid MSR %#RX32\n", uMsr), VERR_NOT_SUPPORTED);
1212
1213 Assert(iBit <= 0x1fff);
1214 if (ASMBitTest(pbMsrBitmap, iBit))
1215 *penmRead = VMXMSREXIT_INTERCEPT_READ;
1216 else
1217 *penmRead = VMXMSREXIT_PASSTHRU_READ;
1218
1219 if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
1220 *penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
1221 else
1222 *penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
1223 return VINF_SUCCESS;
1224}
1225#endif /* VBOX_STRICT */
1226
1227
1228/**
1229 * Updates the VMCS with the number of effective MSRs in the auto-load/store MSR
1230 * area.
1231 *
1232 * @returns VBox status code.
1233 * @param pVCpu The cross context virtual CPU structure.
1234 * @param cMsrs The number of MSRs.
1235 */
1236static int hmR0VmxSetAutoLoadStoreMsrCount(PVMCPU pVCpu, uint32_t cMsrs)
1237{
1238 /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
1239 uint64_t const uVmxMiscMsr = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc;
1240 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(uVmxMiscMsr);
1241 if (RT_UNLIKELY(cMsrs > cMaxSupportedMsrs))
1242 {
1243 LogRel(("CPU auto-load/store MSR count in VMCS exceeded cMsrs=%u Supported=%u.\n", cMsrs, cMaxSupportedMsrs));
1244 pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
1245 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1246 }
1247
1248 /* Update number of guest MSRs to load/store across the world-switch. */
1249 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs);
1250 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs);
1251
1252 /* Update number of host MSRs to load after the world-switch. Identical to guest-MSR count as it's always paired. */
1253 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs);
1254 AssertRCReturn(rc, rc);
1255
1256 /* Update the VCPU's copy of the MSR count. */
1257 pVCpu->hm.s.vmx.cMsrs = cMsrs;
1258
1259 return VINF_SUCCESS;
1260}
1261
1262
1263/**
1264 * Adds a new (or updates the value of an existing) guest/host MSR
1265 * pair to be swapped during the world-switch as part of the
1266 * auto-load/store MSR area in the VMCS.
1267 *
1268 * @returns VBox status code.
1269 * @param pVCpu The cross context virtual CPU structure.
1270 * @param uMsr The MSR.
1271 * @param uGuestMsrValue Value of the guest MSR.
1272 * @param fUpdateHostMsr Whether to update the value of the host MSR if
1273 * necessary.
1274 * @param pfAddedAndUpdated Where to store whether the MSR was added -and-
1275 * its value was updated. Optional, can be NULL.
1276 */
1277static int hmR0VmxAddAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr, uint64_t uGuestMsrValue, bool fUpdateHostMsr,
1278 bool *pfAddedAndUpdated)
1279{
1280 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1281 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1282 uint32_t i;
1283 for (i = 0; i < cMsrs; i++)
1284 {
1285 if (pGuestMsr->u32Msr == uMsr)
1286 break;
1287 pGuestMsr++;
1288 }
1289
1290 bool fAdded = false;
1291 if (i == cMsrs)
1292 {
1293 ++cMsrs;
1294 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1295 AssertMsgRCReturn(rc, ("hmR0VmxAddAutoLoadStoreMsr: Insufficient space to add MSR %u\n", uMsr), rc);
1296
1297 /* Now that we're swapping MSRs during the world-switch, allow the guest to read/write them without causing VM-exits. */
1298 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1299 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1300
1301 fAdded = true;
1302 }
1303
1304 /* Update the MSR values in the auto-load/store MSR area. */
1305 pGuestMsr->u32Msr = uMsr;
1306 pGuestMsr->u64Value = uGuestMsrValue;
1307
1308 /* Create/update the MSR slot in the host MSR area. */
1309 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1310 pHostMsr += i;
1311 pHostMsr->u32Msr = uMsr;
1312
1313 /*
1314 * Update the host MSR only when requested by the caller AND when we're
1315 * adding it to the auto-load/store area. Otherwise, it would have been
1316 * updated by hmR0VmxExportHostMsrs(). We do this for performance reasons.
1317 */
1318 bool fUpdatedMsrValue = false;
1319 if ( fAdded
1320 && fUpdateHostMsr)
1321 {
1322 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1323 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1324 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1325 fUpdatedMsrValue = true;
1326 }
1327
1328 if (pfAddedAndUpdated)
1329 *pfAddedAndUpdated = fUpdatedMsrValue;
1330 return VINF_SUCCESS;
1331}
1332
1333
1334/**
1335 * Removes a guest/host MSR pair to be swapped during the world-switch from the
1336 * auto-load/store MSR area in the VMCS.
1337 *
1338 * @returns VBox status code.
1339 * @param pVCpu The cross context virtual CPU structure.
1340 * @param uMsr The MSR.
1341 */
1342static int hmR0VmxRemoveAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr)
1343{
1344 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1345 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1346 for (uint32_t i = 0; i < cMsrs; i++)
1347 {
1348 /* Find the MSR. */
1349 if (pGuestMsr->u32Msr == uMsr)
1350 {
1351 /* If it's the last MSR, simply reduce the count. */
1352 if (i == cMsrs - 1)
1353 {
1354 --cMsrs;
1355 break;
1356 }
1357
1358 /* Remove it by swapping the last MSR in place of it, and reducing the count. */
1359 PVMXAUTOMSR pLastGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1360 pLastGuestMsr += cMsrs - 1;
1361 pGuestMsr->u32Msr = pLastGuestMsr->u32Msr;
1362 pGuestMsr->u64Value = pLastGuestMsr->u64Value;
1363
1364 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1365 PVMXAUTOMSR pLastHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1366 pLastHostMsr += cMsrs - 1;
1367 pHostMsr->u32Msr = pLastHostMsr->u32Msr;
1368 pHostMsr->u64Value = pLastHostMsr->u64Value;
1369 --cMsrs;
1370 break;
1371 }
1372 pGuestMsr++;
1373 }
1374
1375 /* Update the VMCS if the count changed (meaning the MSR was found). */
1376 if (cMsrs != pVCpu->hm.s.vmx.cMsrs)
1377 {
1378 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1379 AssertRCReturn(rc, rc);
1380
1381 /* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
1382 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1383 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
1384
1385 Log4Func(("Removed MSR %#RX32 new cMsrs=%u\n", uMsr, pVCpu->hm.s.vmx.cMsrs));
1386 return VINF_SUCCESS;
1387 }
1388
1389 return VERR_NOT_FOUND;
1390}
1391
1392
1393/**
1394 * Checks if the specified guest MSR is part of the auto-load/store area in
1395 * the VMCS.
1396 *
1397 * @returns true if found, false otherwise.
1398 * @param pVCpu The cross context virtual CPU structure.
1399 * @param uMsr The MSR to find.
1400 */
1401static bool hmR0VmxIsAutoLoadStoreGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1402{
1403 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1404 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1405
1406 for (uint32_t i = 0; i < cMsrs; i++, pGuestMsr++)
1407 {
1408 if (pGuestMsr->u32Msr == uMsr)
1409 return true;
1410 }
1411 return false;
1412}
1413
1414
1415/**
1416 * Updates the value of all host MSRs in the auto-load/store area in the VMCS.
1417 *
1418 * @param pVCpu The cross context virtual CPU structure.
1419 *
1420 * @remarks No-long-jump zone!!!
1421 */
1422static void hmR0VmxUpdateAutoLoadStoreHostMsrs(PVMCPU pVCpu)
1423{
1424 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1425 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1426 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1427 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1428
1429 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1430 {
1431 AssertReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr);
1432
1433 /*
1434 * Performance hack for the host EFER MSR. We use the cached value rather than re-read it.
1435 * Strict builds will catch mismatches in hmR0VmxCheckAutoLoadStoreMsrs(). See @bugref{7368}.
1436 */
1437 if (pHostMsr->u32Msr == MSR_K6_EFER)
1438 pHostMsr->u64Value = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.u64HostEfer;
1439 else
1440 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1441 }
1442
1443 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
1444}
1445
1446
1447/**
1448 * Saves a set of host MSRs to allow read/write passthru access to the guest and
1449 * perform lazy restoration of the host MSRs while leaving VT-x.
1450 *
1451 * @param pVCpu The cross context virtual CPU structure.
1452 *
1453 * @remarks No-long-jump zone!!!
1454 */
1455static void hmR0VmxLazySaveHostMsrs(PVMCPU pVCpu)
1456{
1457 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1458
1459 /*
1460 * Note: If you're adding MSRs here, make sure to update the MSR-bitmap permissions in hmR0VmxSetupProcCtls().
1461 */
1462 if (!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST))
1463 {
1464 Assert(!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */
1465#if HC_ARCH_BITS == 64
1466 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1467 {
1468 pVCpu->hm.s.vmx.u64HostLStarMsr = ASMRdMsr(MSR_K8_LSTAR);
1469 pVCpu->hm.s.vmx.u64HostStarMsr = ASMRdMsr(MSR_K6_STAR);
1470 pVCpu->hm.s.vmx.u64HostSFMaskMsr = ASMRdMsr(MSR_K8_SF_MASK);
1471 pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1472 }
1473#endif
1474 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_SAVED_HOST;
1475 }
1476}
1477
1478
1479/**
1480 * Checks whether the MSR belongs to the set of guest MSRs that we restore
1481 * lazily while leaving VT-x.
1482 *
1483 * @returns true if it does, false otherwise.
1484 * @param pVCpu The cross context virtual CPU structure.
1485 * @param uMsr The MSR to check.
1486 */
1487static bool hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1488{
1489 NOREF(pVCpu);
1490#if HC_ARCH_BITS == 64
1491 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1492 {
1493 switch (uMsr)
1494 {
1495 case MSR_K8_LSTAR:
1496 case MSR_K6_STAR:
1497 case MSR_K8_SF_MASK:
1498 case MSR_K8_KERNEL_GS_BASE:
1499 return true;
1500 }
1501 }
1502#else
1503 RT_NOREF(pVCpu, uMsr);
1504#endif
1505 return false;
1506}
1507
1508
1509/**
1510 * Loads a set of guests MSRs to allow read/passthru to the guest.
1511 *
1512 * The name of this function is slightly confusing. This function does NOT
1513 * postpone loading, but loads the MSR right now. "hmR0VmxLazy" is simply a
1514 * common prefix for functions dealing with "lazy restoration" of the shared
1515 * MSRs.
1516 *
1517 * @param pVCpu The cross context virtual CPU structure.
1518 *
1519 * @remarks No-long-jump zone!!!
1520 */
1521static void hmR0VmxLazyLoadGuestMsrs(PVMCPU pVCpu)
1522{
1523 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1524 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1525
1526 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1527#if HC_ARCH_BITS == 64
1528 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1529 {
1530 /*
1531 * If the guest MSRs are not loaded -and- if all the guest MSRs are identical
1532 * to the MSRs on the CPU (which are the saved host MSRs, see assertion above) then
1533 * we can skip a few MSR writes.
1534 *
1535 * Otherwise, it implies either 1. they're not loaded, or 2. they're loaded but the
1536 * guest MSR values in the guest-CPU context might be different to what's currently
1537 * loaded in the CPU. In either case, we need to write the new guest MSR values to the
1538 * CPU, see @bugref{8728}.
1539 */
1540 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1541 if ( !(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1542 && pCtx->msrKERNELGSBASE == pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr
1543 && pCtx->msrLSTAR == pVCpu->hm.s.vmx.u64HostLStarMsr
1544 && pCtx->msrSTAR == pVCpu->hm.s.vmx.u64HostStarMsr
1545 && pCtx->msrSFMASK == pVCpu->hm.s.vmx.u64HostSFMaskMsr)
1546 {
1547#ifdef VBOX_STRICT
1548 Assert(ASMRdMsr(MSR_K8_KERNEL_GS_BASE) == pCtx->msrKERNELGSBASE);
1549 Assert(ASMRdMsr(MSR_K8_LSTAR) == pCtx->msrLSTAR);
1550 Assert(ASMRdMsr(MSR_K6_STAR) == pCtx->msrSTAR);
1551 Assert(ASMRdMsr(MSR_K8_SF_MASK) == pCtx->msrSFMASK);
1552#endif
1553 }
1554 else
1555 {
1556 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1557 ASMWrMsr(MSR_K8_LSTAR, pCtx->msrLSTAR);
1558 ASMWrMsr(MSR_K6_STAR, pCtx->msrSTAR);
1559 ASMWrMsr(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1560 }
1561 }
1562#endif
1563 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_LOADED_GUEST;
1564}
1565
1566
1567/**
1568 * Performs lazy restoration of the set of host MSRs if they were previously
1569 * loaded with guest MSR values.
1570 *
1571 * @param pVCpu The cross context virtual CPU structure.
1572 *
1573 * @remarks No-long-jump zone!!!
1574 * @remarks The guest MSRs should have been saved back into the guest-CPU
1575 * context by hmR0VmxImportGuestState()!!!
1576 */
1577static void hmR0VmxLazyRestoreHostMsrs(PVMCPU pVCpu)
1578{
1579 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1580 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1581
1582 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1583 {
1584 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1585#if HC_ARCH_BITS == 64
1586 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1587 {
1588 ASMWrMsr(MSR_K8_LSTAR, pVCpu->hm.s.vmx.u64HostLStarMsr);
1589 ASMWrMsr(MSR_K6_STAR, pVCpu->hm.s.vmx.u64HostStarMsr);
1590 ASMWrMsr(MSR_K8_SF_MASK, pVCpu->hm.s.vmx.u64HostSFMaskMsr);
1591 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr);
1592 }
1593#endif
1594 }
1595 pVCpu->hm.s.vmx.fLazyMsrs &= ~(VMX_LAZY_MSRS_LOADED_GUEST | VMX_LAZY_MSRS_SAVED_HOST);
1596}
1597
1598
1599/**
1600 * Verifies that our cached values of the VMCS fields are all consistent with
1601 * what's actually present in the VMCS.
1602 *
1603 * @returns VBox status code.
1604 * @retval VINF_SUCCESS if all our caches match their respective VMCS fields.
1605 * @retval VERR_VMX_VMCS_FIELD_CACHE_INVALID if a cache field doesn't match the
1606 * VMCS content. HMCPU error-field is
1607 * updated, see VMX_VCI_XXX.
1608 * @param pVCpu The cross context virtual CPU structure.
1609 */
1610static int hmR0VmxCheckVmcsCtls(PVMCPU pVCpu)
1611{
1612 uint32_t u32Val;
1613 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
1614 AssertRCReturn(rc, rc);
1615 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32EntryCtls == u32Val,
1616 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32EntryCtls, u32Val),
1617 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_ENTRY,
1618 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1619
1620 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);
1621 AssertRCReturn(rc, rc);
1622 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32ExitCtls == u32Val,
1623 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32ExitCtls, u32Val),
1624 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_EXIT,
1625 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1626
1627 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);
1628 AssertRCReturn(rc, rc);
1629 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32PinCtls == u32Val,
1630 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32PinCtls, u32Val),
1631 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PIN_EXEC,
1632 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1633
1634 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
1635 AssertRCReturn(rc, rc);
1636 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32ProcCtls == u32Val,
1637 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls, u32Val),
1638 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC,
1639 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1640
1641 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1642 {
1643 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
1644 AssertRCReturn(rc, rc);
1645 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32ProcCtls2 == u32Val,
1646 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls2, u32Val),
1647 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC2,
1648 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1649 }
1650
1651 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val);
1652 AssertRCReturn(rc, rc);
1653 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32XcptBitmap == u32Val,
1654 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32XcptBitmap, u32Val),
1655 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_XCPT_BITMAP,
1656 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1657
1658 uint64_t u64Val;
1659 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, &u64Val);
1660 AssertRCReturn(rc, rc);
1661 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u64TscOffset == u64Val,
1662 ("Cache=%#RX64 VMCS=%#RX64\n", pVCpu->hm.s.vmx.u64TscOffset, u64Val),
1663 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_TSC_OFFSET,
1664 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1665
1666 return VINF_SUCCESS;
1667}
1668
1669
1670#ifdef VBOX_STRICT
1671/**
1672 * Verifies that our cached host EFER value has not changed
1673 * since we cached it.
1674 *
1675 * @param pVCpu The cross context virtual CPU structure.
1676 */
1677static void hmR0VmxCheckHostEferMsr(PVMCPU pVCpu)
1678{
1679 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1680
1681 if (pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1682 {
1683 uint64_t u64Val;
1684 int rc = VMXReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &u64Val);
1685 AssertRC(rc);
1686
1687 uint64_t u64HostEferMsr = ASMRdMsr(MSR_K6_EFER);
1688 AssertMsgReturnVoid(u64HostEferMsr == u64Val, ("u64HostEferMsr=%#RX64 u64Val=%#RX64\n", u64HostEferMsr, u64Val));
1689 }
1690}
1691
1692
1693/**
1694 * Verifies whether the guest/host MSR pairs in the auto-load/store area in the
1695 * VMCS are correct.
1696 *
1697 * @param pVCpu The cross context virtual CPU structure.
1698 */
1699static void hmR0VmxCheckAutoLoadStoreMsrs(PVMCPU pVCpu)
1700{
1701 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1702
1703 /* Verify MSR counts in the VMCS are what we think it should be. */
1704 uint32_t cMsrs;
1705 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1706 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1707
1708 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cMsrs); AssertRC(rc);
1709 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1710
1711 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1712 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1713
1714 PCVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1715 PCVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1716 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1717 {
1718 /* Verify that the MSRs are paired properly and that the host MSR has the correct value. */
1719 AssertMsgReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr, ("HostMsr=%#RX32 GuestMsr=%#RX32 cMsrs=%u\n", pHostMsr->u32Msr,
1720 pGuestMsr->u32Msr, cMsrs));
1721
1722 uint64_t u64Msr = ASMRdMsr(pHostMsr->u32Msr);
1723 AssertMsgReturnVoid(pHostMsr->u64Value == u64Msr, ("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
1724 pHostMsr->u32Msr, pHostMsr->u64Value, u64Msr, cMsrs));
1725
1726 /* Verify that the permissions are as expected in the MSR bitmap. */
1727 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1728 {
1729 VMXMSREXITREAD enmRead;
1730 VMXMSREXITWRITE enmWrite;
1731 rc = hmR0VmxGetMsrPermission(pVCpu, pGuestMsr->u32Msr, &enmRead, &enmWrite);
1732 AssertMsgReturnVoid(rc == VINF_SUCCESS, ("hmR0VmxGetMsrPermission! failed. rc=%Rrc\n", rc));
1733 if (pGuestMsr->u32Msr == MSR_K6_EFER)
1734 {
1735 AssertMsgReturnVoid(enmRead == VMXMSREXIT_INTERCEPT_READ, ("Passthru read for EFER!?\n"));
1736 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_INTERCEPT_WRITE, ("Passthru write for EFER!?\n"));
1737 }
1738 else
1739 {
1740 AssertMsgReturnVoid(enmRead == VMXMSREXIT_PASSTHRU_READ, ("u32Msr=%#RX32 cMsrs=%u No passthru read!\n",
1741 pGuestMsr->u32Msr, cMsrs));
1742 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_PASSTHRU_WRITE, ("u32Msr=%#RX32 cMsrs=%u No passthru write!\n",
1743 pGuestMsr->u32Msr, cMsrs));
1744 }
1745 }
1746 }
1747}
1748#endif /* VBOX_STRICT */
1749
1750
1751/**
1752 * Flushes the TLB using EPT.
1753 *
1754 * @returns VBox status code.
1755 * @param pVCpu The cross context virtual CPU structure of the calling
1756 * EMT. Can be NULL depending on @a enmTlbFlush.
1757 * @param enmTlbFlush Type of flush.
1758 *
1759 * @remarks Caller is responsible for making sure this function is called only
1760 * when NestedPaging is supported and providing @a enmTlbFlush that is
1761 * supported by the CPU.
1762 * @remarks Can be called with interrupts disabled.
1763 */
1764static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXTLBFLUSHEPT enmTlbFlush)
1765{
1766 uint64_t au64Descriptor[2];
1767 if (enmTlbFlush == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1768 au64Descriptor[0] = 0;
1769 else
1770 {
1771 Assert(pVCpu);
1772 au64Descriptor[0] = pVCpu->hm.s.vmx.HCPhysEPTP;
1773 }
1774 au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
1775
1776 int rc = VMXR0InvEPT(enmTlbFlush, &au64Descriptor[0]);
1777 AssertMsg(rc == VINF_SUCCESS,
1778 ("VMXR0InvEPT %#x %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hm.s.vmx.HCPhysEPTP : 0, rc));
1779
1780 if ( RT_SUCCESS(rc)
1781 && pVCpu)
1782 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
1783}
1784
1785
1786/**
1787 * Flushes the TLB using VPID.
1788 *
1789 * @returns VBox status code.
1790 * @param pVCpu The cross context virtual CPU structure of the calling
1791 * EMT. Can be NULL depending on @a enmTlbFlush.
1792 * @param enmTlbFlush Type of flush.
1793 * @param GCPtr Virtual address of the page to flush (can be 0 depending
1794 * on @a enmTlbFlush).
1795 *
1796 * @remarks Can be called with interrupts disabled.
1797 */
1798static void hmR0VmxFlushVpid(PVMCPU pVCpu, VMXTLBFLUSHVPID enmTlbFlush, RTGCPTR GCPtr)
1799{
1800 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid);
1801
1802 uint64_t au64Descriptor[2];
1803 if (enmTlbFlush == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1804 {
1805 au64Descriptor[0] = 0;
1806 au64Descriptor[1] = 0;
1807 }
1808 else
1809 {
1810 AssertPtr(pVCpu);
1811 AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1812 AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1813 au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
1814 au64Descriptor[1] = GCPtr;
1815 }
1816
1817 int rc = VMXR0InvVPID(enmTlbFlush, &au64Descriptor[0]);
1818 AssertMsg(rc == VINF_SUCCESS,
1819 ("VMXR0InvVPID %#x %u %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
1820
1821 if ( RT_SUCCESS(rc)
1822 && pVCpu)
1823 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1824 NOREF(rc);
1825}
1826
1827
1828/**
1829 * Invalidates a guest page by guest virtual address. Only relevant for
1830 * EPT/VPID, otherwise there is nothing really to invalidate.
1831 *
1832 * @returns VBox status code.
1833 * @param pVCpu The cross context virtual CPU structure.
1834 * @param GCVirt Guest virtual address of the page to invalidate.
1835 */
1836VMMR0DECL(int) VMXR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1837{
1838 AssertPtr(pVCpu);
1839 LogFlowFunc(("pVCpu=%p GCVirt=%RGv\n", pVCpu, GCVirt));
1840
1841 bool fFlushPending = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1842 if (!fFlushPending)
1843 {
1844 /*
1845 * We must invalidate the guest TLB entry in either case, we cannot ignore it even for
1846 * the EPT case. See @bugref{6043} and @bugref{6177}.
1847 *
1848 * Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*()
1849 * as this function maybe called in a loop with individual addresses.
1850 */
1851 PVM pVM = pVCpu->CTX_SUFF(pVM);
1852 if (pVM->hm.s.vmx.fVpid)
1853 {
1854 bool fVpidFlush = RT_BOOL(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1855
1856#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1857 /*
1858 * Workaround Erratum BV75, AAJ159 and others that affect several Intel CPUs
1859 * where executing INVVPID outside 64-bit mode does not flush translations of
1860 * 64-bit linear addresses, see @bugref{6208#c72}.
1861 */
1862 if (RT_HI_U32(GCVirt))
1863 fVpidFlush = false;
1864#endif
1865
1866 if (fVpidFlush)
1867 {
1868 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_INDIV_ADDR, GCVirt);
1869 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1870 }
1871 else
1872 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1873 }
1874 else if (pVM->hm.s.fNestedPaging)
1875 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1876 }
1877
1878 return VINF_SUCCESS;
1879}
1880
1881
1882/**
1883 * Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
1884 * case where neither EPT nor VPID is supported by the CPU.
1885 *
1886 * @param pVCpu The cross context virtual CPU structure.
1887 * @param pCpu Pointer to the global HM struct.
1888 *
1889 * @remarks Called with interrupts disabled.
1890 */
1891static void hmR0VmxFlushTaggedTlbNone(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1892{
1893 AssertPtr(pVCpu);
1894 AssertPtr(pCpu);
1895
1896 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1897
1898 Assert(pCpu->idCpu != NIL_RTCPUID);
1899 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1900 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1901 pVCpu->hm.s.fForceTLBFlush = false;
1902 return;
1903}
1904
1905
1906/**
1907 * Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
1908 *
1909 * @param pVCpu The cross context virtual CPU structure.
1910 * @param pCpu Pointer to the global HM CPU struct.
1911 *
1912 * @remarks All references to "ASID" in this function pertains to "VPID" in Intel's
1913 * nomenclature. The reason is, to avoid confusion in compare statements
1914 * since the host-CPU copies are named "ASID".
1915 *
1916 * @remarks Called with interrupts disabled.
1917 */
1918static void hmR0VmxFlushTaggedTlbBoth(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1919{
1920#ifdef VBOX_WITH_STATISTICS
1921 bool fTlbFlushed = false;
1922# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
1923# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
1924 if (!fTlbFlushed) \
1925 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
1926 } while (0)
1927#else
1928# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
1929# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
1930#endif
1931
1932 AssertPtr(pCpu);
1933 AssertPtr(pVCpu);
1934 Assert(pCpu->idCpu != NIL_RTCPUID);
1935
1936 PVM pVM = pVCpu->CTX_SUFF(pVM);
1937 AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
1938 ("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
1939 "fNestedPaging=%RTbool fVpid=%RTbool", pVM->hm.s.fNestedPaging, pVM->hm.s.vmx.fVpid));
1940
1941 /*
1942 * Force a TLB flush for the first world-switch if the current CPU differs from the one we
1943 * ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
1944 * limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
1945 * cannot reuse the current ASID anymore.
1946 */
1947 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1948 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1949 {
1950 ++pCpu->uCurrentAsid;
1951 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1952 {
1953 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
1954 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1955 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1956 }
1957
1958 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1959 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1960 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1961
1962 /*
1963 * Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
1964 * invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
1965 */
1966 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmTlbFlushEpt);
1967 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1968 HMVMX_SET_TAGGED_TLB_FLUSHED();
1969 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1970 }
1971 else if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH)) /* Check for explicit TLB flushes. */
1972 {
1973 /*
1974 * Changes to the EPT paging structure by VMM requires flushing-by-EPT as the CPU
1975 * creates guest-physical (ie. only EPT-tagged) mappings while traversing the EPT
1976 * tables when EPT is in use. Flushing-by-VPID will only flush linear (only
1977 * VPID-tagged) and combined (EPT+VPID tagged) mappings but not guest-physical
1978 * mappings, see @bugref{6568}.
1979 *
1980 * See Intel spec. 28.3.2 "Creating and Using Cached Translation Information".
1981 */
1982 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmTlbFlushEpt);
1983 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1984 HMVMX_SET_TAGGED_TLB_FLUSHED();
1985 }
1986
1987 pVCpu->hm.s.fForceTLBFlush = false;
1988 HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
1989
1990 Assert(pVCpu->hm.s.idLastCpu == pCpu->idCpu);
1991 Assert(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes);
1992 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1993 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1994 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1995 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
1996 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
1997 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1998 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1999
2000 /* Update VMCS with the VPID. */
2001 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2002 AssertRC(rc);
2003
2004#undef HMVMX_SET_TAGGED_TLB_FLUSHED
2005}
2006
2007
2008/**
2009 * Flushes the tagged-TLB entries for EPT CPUs as necessary.
2010 *
2011 * @returns VBox status code.
2012 * @param pVCpu The cross context virtual CPU structure.
2013 * @param pCpu Pointer to the global HM CPU struct.
2014 *
2015 * @remarks Called with interrupts disabled.
2016 */
2017static void hmR0VmxFlushTaggedTlbEpt(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2018{
2019 AssertPtr(pVCpu);
2020 AssertPtr(pCpu);
2021 Assert(pCpu->idCpu != NIL_RTCPUID);
2022 AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked without NestedPaging."));
2023 AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID."));
2024
2025 /*
2026 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
2027 * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
2028 */
2029 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2030 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2031 {
2032 pVCpu->hm.s.fForceTLBFlush = true;
2033 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2034 }
2035
2036 /* Check for explicit TLB flushes. */
2037 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2038 {
2039 pVCpu->hm.s.fForceTLBFlush = true;
2040 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2041 }
2042
2043 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2044 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2045
2046 if (pVCpu->hm.s.fForceTLBFlush)
2047 {
2048 hmR0VmxFlushEpt(pVCpu, pVCpu->CTX_SUFF(pVM)->hm.s.vmx.enmTlbFlushEpt);
2049 pVCpu->hm.s.fForceTLBFlush = false;
2050 }
2051}
2052
2053
2054/**
2055 * Flushes the tagged-TLB entries for VPID CPUs as necessary.
2056 *
2057 * @returns VBox status code.
2058 * @param pVCpu The cross context virtual CPU structure.
2059 * @param pCpu Pointer to the global HM CPU struct.
2060 *
2061 * @remarks Called with interrupts disabled.
2062 */
2063static void hmR0VmxFlushTaggedTlbVpid(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2064{
2065 AssertPtr(pVCpu);
2066 AssertPtr(pCpu);
2067 Assert(pCpu->idCpu != NIL_RTCPUID);
2068 AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked without VPID."));
2069 AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging"));
2070
2071 /*
2072 * Force a TLB flush for the first world switch if the current CPU differs from the one we
2073 * ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
2074 * limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
2075 * cannot reuse the current ASID anymore.
2076 */
2077 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2078 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2079 {
2080 pVCpu->hm.s.fForceTLBFlush = true;
2081 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2082 }
2083
2084 /* Check for explicit TLB flushes. */
2085 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2086 {
2087 /*
2088 * If we ever support VPID flush combinations other than ALL or SINGLE-context (see
2089 * hmR0VmxSetupTaggedTlb()) we would need to explicitly flush in this case (add an
2090 * fExplicitFlush = true here and change the pCpu->fFlushAsidBeforeUse check below to
2091 * include fExplicitFlush's too) - an obscure corner case.
2092 */
2093 pVCpu->hm.s.fForceTLBFlush = true;
2094 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2095 }
2096
2097 PVM pVM = pVCpu->CTX_SUFF(pVM);
2098 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2099 if (pVCpu->hm.s.fForceTLBFlush)
2100 {
2101 ++pCpu->uCurrentAsid;
2102 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
2103 {
2104 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
2105 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
2106 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
2107 }
2108
2109 pVCpu->hm.s.fForceTLBFlush = false;
2110 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2111 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
2112 if (pCpu->fFlushAsidBeforeUse)
2113 {
2114 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
2115 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
2116 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
2117 {
2118 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
2119 pCpu->fFlushAsidBeforeUse = false;
2120 }
2121 else
2122 {
2123 /* hmR0VmxSetupTaggedTlb() ensures we never get here. Paranoia. */
2124 AssertMsgFailed(("Unsupported VPID-flush context type.\n"));
2125 }
2126 }
2127 }
2128
2129 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2130 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2131 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2132 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2133 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2134 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2135 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2136
2137 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2138 AssertRC(rc);
2139}
2140
2141
2142/**
2143 * Flushes the guest TLB entry based on CPU capabilities.
2144 *
2145 * @param pVCpu The cross context virtual CPU structure.
2146 * @param pCpu Pointer to the global HM CPU struct.
2147 */
2148DECLINLINE(void) hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2149{
2150#ifdef HMVMX_ALWAYS_FLUSH_TLB
2151 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2152#endif
2153 PVM pVM = pVCpu->CTX_SUFF(pVM);
2154 switch (pVM->hm.s.vmx.enmTlbFlushType)
2155 {
2156 case VMXTLBFLUSHTYPE_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVCpu, pCpu); break;
2157 case VMXTLBFLUSHTYPE_EPT: hmR0VmxFlushTaggedTlbEpt(pVCpu, pCpu); break;
2158 case VMXTLBFLUSHTYPE_VPID: hmR0VmxFlushTaggedTlbVpid(pVCpu, pCpu); break;
2159 case VMXTLBFLUSHTYPE_NONE: hmR0VmxFlushTaggedTlbNone(pVCpu, pCpu); break;
2160 default:
2161 AssertMsgFailed(("Invalid flush-tag function identifier\n"));
2162 break;
2163 }
2164 /* Don't assert that VMCPU_FF_TLB_FLUSH should no longer be pending. It can be set by other EMTs. */
2165}
2166
2167
2168/**
2169 * Sets up the appropriate tagged TLB-flush level and handler for flushing guest
2170 * TLB entries from the host TLB before VM-entry.
2171 *
2172 * @returns VBox status code.
2173 * @param pVM The cross context VM structure.
2174 */
2175static int hmR0VmxSetupTaggedTlb(PVM pVM)
2176{
2177 /*
2178 * Determine optimal flush type for Nested Paging.
2179 * We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup unrestricted
2180 * guest execution (see hmR3InitFinalizeR0()).
2181 */
2182 if (pVM->hm.s.fNestedPaging)
2183 {
2184 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
2185 {
2186 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
2187 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_SINGLE_CONTEXT;
2188 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
2189 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_ALL_CONTEXTS;
2190 else
2191 {
2192 /* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
2193 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2194 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED;
2195 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2196 }
2197
2198 /* Make sure the write-back cacheable memory type for EPT is supported. */
2199 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
2200 {
2201 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2202 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_MEM_TYPE_NOT_WB;
2203 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2204 }
2205
2206 /* EPT requires a page-walk length of 4. */
2207 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
2208 {
2209 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2210 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED;
2211 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2212 }
2213 }
2214 else
2215 {
2216 /* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
2217 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2218 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_INVEPT_UNAVAILABLE;
2219 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2220 }
2221 }
2222
2223 /*
2224 * Determine optimal flush type for VPID.
2225 */
2226 if (pVM->hm.s.vmx.fVpid)
2227 {
2228 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
2229 {
2230 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
2231 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_SINGLE_CONTEXT;
2232 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
2233 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_ALL_CONTEXTS;
2234 else
2235 {
2236 /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
2237 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
2238 LogRelFunc(("Only INDIV_ADDR supported. Ignoring VPID.\n"));
2239 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
2240 LogRelFunc(("Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
2241 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
2242 pVM->hm.s.vmx.fVpid = false;
2243 }
2244 }
2245 else
2246 {
2247 /* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
2248 Log4Func(("VPID supported without INVEPT support. Ignoring VPID.\n"));
2249 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
2250 pVM->hm.s.vmx.fVpid = false;
2251 }
2252 }
2253
2254 /*
2255 * Setup the handler for flushing tagged-TLBs.
2256 */
2257 if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
2258 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT_VPID;
2259 else if (pVM->hm.s.fNestedPaging)
2260 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT;
2261 else if (pVM->hm.s.vmx.fVpid)
2262 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_VPID;
2263 else
2264 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_NONE;
2265 return VINF_SUCCESS;
2266}
2267
2268
2269/**
2270 * Sets up pin-based VM-execution controls in the VMCS.
2271 *
2272 * @returns VBox status code.
2273 * @param pVCpu The cross context virtual CPU structure.
2274 *
2275 * @remarks We don't really care about optimizing vmwrites here as it's done only
2276 * once per VM and hence we don't care about VMCS-field cache comparisons.
2277 */
2278static int hmR0VmxSetupPinCtls(PVMCPU pVCpu)
2279{
2280 PVM pVM = pVCpu->CTX_SUFF(pVM);
2281 uint32_t fVal = pVM->hm.s.vmx.Msrs.PinCtls.n.disallowed0; /* Bits set here must always be set. */
2282 uint32_t const fZap = pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
2283
2284 fVal |= VMX_PIN_CTLS_EXT_INT_EXIT /* External interrupts cause a VM-exit. */
2285 | VMX_PIN_CTLS_NMI_EXIT; /* Non-maskable interrupts (NMIs) cause a VM-exit. */
2286
2287 if (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
2288 fVal |= VMX_PIN_CTLS_VIRT_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
2289
2290 /* Enable the VMX preemption timer. */
2291 if (pVM->hm.s.vmx.fUsePreemptTimer)
2292 {
2293 Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
2294 fVal |= VMX_PIN_CTLS_PREEMPT_TIMER;
2295 }
2296
2297#if 0
2298 /* Enable posted-interrupt processing. */
2299 if (pVM->hm.s.fPostedIntrs)
2300 {
2301 Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT);
2302 Assert(pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
2303 fVal |= VMX_PIN_CTL_POSTED_INT;
2304 }
2305#endif
2306
2307 if ((fVal & fZap) != fVal)
2308 {
2309 LogRelFunc(("Invalid pin-based VM-execution controls combo! Cpu=%#RX64 fVal=%#RX64 fZap=%#RX64\n",
2310 pVM->hm.s.vmx.Msrs.PinCtls.n.disallowed0, fVal, fZap));
2311 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
2312 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2313 }
2314
2315 /* Commit it to the VMCS and update our cache. */
2316 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, fVal);
2317 AssertRCReturn(rc, rc);
2318 pVCpu->hm.s.vmx.u32PinCtls = fVal;
2319
2320 return VINF_SUCCESS;
2321}
2322
2323
2324/**
2325 * Sets up secondary processor-based VM-execution controls in the VMCS.
2326 *
2327 * @returns VBox status code.
2328 * @param pVCpu The cross context virtual CPU structure.
2329 *
2330 * @remarks We don't really care about optimizing vmwrites here as it's done only
2331 * once per VM and hence we don't care about VMCS-field cache comparisons.
2332 */
2333static int hmR0VmxSetupProcCtls2(PVMCPU pVCpu)
2334{
2335 PVM pVM = pVCpu->CTX_SUFF(pVM);
2336 uint32_t fVal = pVM->hm.s.vmx.Msrs.ProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */
2337 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2338
2339 /* WBINVD causes a VM-exit. */
2340 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
2341 fVal |= VMX_PROC_CTLS2_WBINVD_EXIT;
2342
2343 /* Enable EPT (aka nested-paging). */
2344 if (pVM->hm.s.fNestedPaging)
2345 fVal |= VMX_PROC_CTLS2_EPT;
2346
2347 /*
2348 * Enable the INVPCID instruction if supported by the hardware and we expose
2349 * it to the guest. Without this, guest executing INVPCID would cause a #UD.
2350 */
2351 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID)
2352 && pVM->cpum.ro.GuestFeatures.fInvpcid)
2353 fVal |= VMX_PROC_CTLS2_INVPCID;
2354
2355 /* Enable VPID. */
2356 if (pVM->hm.s.vmx.fVpid)
2357 fVal |= VMX_PROC_CTLS2_VPID;
2358
2359 /* Enable Unrestricted guest execution. */
2360 if (pVM->hm.s.vmx.fUnrestrictedGuest)
2361 fVal |= VMX_PROC_CTLS2_UNRESTRICTED_GUEST;
2362
2363#if 0
2364 if (pVM->hm.s.fVirtApicRegs)
2365 {
2366 /* Enable APIC-register virtualization. */
2367 Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
2368 fVal |= VMX_PROC_CTLS2_APIC_REG_VIRT;
2369
2370 /* Enable virtual-interrupt delivery. */
2371 Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
2372 fVal |= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
2373 }
2374#endif
2375
2376 /* Virtualize-APIC accesses if supported by the CPU. The virtual-APIC page is where the TPR shadow resides. */
2377 /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
2378 * done dynamically. */
2379 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
2380 {
2381 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
2382 Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
2383 fVal |= VMX_PROC_CTLS2_VIRT_APIC_ACCESS; /* Virtualize APIC accesses. */
2384 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
2385 AssertRCReturn(rc, rc);
2386 }
2387
2388 /* Enable RDTSCP. */
2389 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP)
2390 fVal |= VMX_PROC_CTLS2_RDTSCP;
2391
2392 /* Enable Pause-Loop exiting. */
2393 if ( pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT
2394 && pVM->hm.s.vmx.cPleGapTicks
2395 && pVM->hm.s.vmx.cPleWindowTicks)
2396 {
2397 fVal |= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT;
2398
2399 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks);
2400 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks);
2401 AssertRCReturn(rc, rc);
2402 }
2403
2404 if ((fVal & fZap) != fVal)
2405 {
2406 LogRelFunc(("Invalid secondary processor-based VM-execution controls combo! cpu=%#RX64 fVal=%#RX64 fZap=%#RX64\n",
2407 pVM->hm.s.vmx.Msrs.ProcCtls2.n.disallowed0, fVal, fZap));
2408 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
2409 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2410 }
2411
2412 /* Commit it to the VMCS and update our cache. */
2413 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, fVal);
2414 AssertRCReturn(rc, rc);
2415 pVCpu->hm.s.vmx.u32ProcCtls2 = fVal;
2416
2417 return VINF_SUCCESS;
2418}
2419
2420
2421/**
2422 * Sets up processor-based VM-execution controls in the VMCS.
2423 *
2424 * @returns VBox status code.
2425 * @param pVCpu The cross context virtual CPU structure.
2426 *
2427 * @remarks We don't really care about optimizing vmwrites here as it's done only
2428 * once per VM and hence we don't care about VMCS-field cache comparisons.
2429 */
2430static int hmR0VmxSetupProcCtls(PVMCPU pVCpu)
2431{
2432 PVM pVM = pVCpu->CTX_SUFF(pVM);
2433 uint32_t fVal = pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
2434 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2435
2436 fVal |= VMX_PROC_CTLS_HLT_EXIT /* HLT causes a VM-exit. */
2437 | VMX_PROC_CTLS_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2438 | VMX_PROC_CTLS_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2439 | VMX_PROC_CTLS_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2440 | VMX_PROC_CTLS_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2441 | VMX_PROC_CTLS_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2442 | VMX_PROC_CTLS_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2443
2444 /* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2445 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
2446 || (pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
2447 {
2448 LogRelFunc(("Unsupported VMX_PROC_CTLS_MOV_DR_EXIT combo!"));
2449 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2450 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2451 }
2452
2453 /* Without Nested Paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
2454 if (!pVM->hm.s.fNestedPaging)
2455 {
2456 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest); /* Paranoia. */
2457 fVal |= VMX_PROC_CTLS_INVLPG_EXIT
2458 | VMX_PROC_CTLS_CR3_LOAD_EXIT
2459 | VMX_PROC_CTLS_CR3_STORE_EXIT;
2460 }
2461
2462 /* Use TPR shadowing if supported by the CPU. */
2463 if ( PDMHasApic(pVM)
2464 && pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW)
2465 {
2466 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
2467 Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
2468 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
2469 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
2470 AssertRCReturn(rc, rc);
2471
2472 fVal |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2473 /* CR8 writes cause a VM-exit based on TPR threshold. */
2474 Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
2475 Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
2476 }
2477 else
2478 {
2479 /*
2480 * Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is invalid on 32-bit Intel CPUs.
2481 * Set this control only for 64-bit guests.
2482 */
2483 if (pVM->hm.s.fAllow64BitGuests)
2484 {
2485 fVal |= VMX_PROC_CTLS_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2486 | VMX_PROC_CTLS_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2487 }
2488 }
2489
2490 /* Use MSR-bitmaps if supported by the CPU. */
2491 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
2492 {
2493 fVal |= VMX_PROC_CTLS_USE_MSR_BITMAPS;
2494
2495 Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2496 Assert(!(pVCpu->hm.s.vmx.HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
2497 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2498 AssertRCReturn(rc, rc);
2499
2500 /*
2501 * The guest can access the following MSRs (read, write) without causing VM-exits; they are loaded/stored
2502 * automatically using dedicated fields in the VMCS.
2503 */
2504 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2505 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2506 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2507 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2508 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_FS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2509#if HC_ARCH_BITS == 64
2510 /*
2511 * Set passthru permissions for the following MSRs (mandatory for VT-x) required for 64-bit guests.
2512 */
2513 if (pVM->hm.s.fAllow64BitGuests)
2514 {
2515 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_LSTAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2516 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_STAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2517 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_SF_MASK, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2518 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2519 }
2520#endif
2521 /*
2522 * The IA32_PRED_CMD MSR is write-only and has no state associated with it. We never need to intercept
2523 * access (writes need to be executed without exiting, reds will #GP-fault anyway).
2524 */
2525 if (pVM->cpum.ro.GuestFeatures.fIbpb)
2526 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_PRED_CMD, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2527
2528 /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */
2529 }
2530
2531 /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2532 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2533 fVal |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
2534
2535 if ((fVal & fZap) != fVal)
2536 {
2537 LogRelFunc(("Invalid processor-based VM-execution controls combo! cpu=%#RX64 fVal=%#RX64 fZap=%#RX64\n",
2538 pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0, fVal, fZap));
2539 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2540 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2541 }
2542
2543 /* Commit it to the VMCS and update our cache. */
2544 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, fVal);
2545 AssertRCReturn(rc, rc);
2546 pVCpu->hm.s.vmx.u32ProcCtls = fVal;
2547
2548 /* Set up secondary processor-based VM-execution controls if the CPU supports it. */
2549 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2550 return hmR0VmxSetupProcCtls2(pVCpu);
2551
2552 /* Sanity check, should not really happen. */
2553 if (RT_UNLIKELY(pVM->hm.s.vmx.fUnrestrictedGuest))
2554 {
2555 LogRelFunc(("Unrestricted Guest enabled when secondary processor-based VM-execution controls not available\n"));
2556 pVCpu->hm.s.u32HMError = VMX_UFC_INVALID_UX_COMBO;
2557 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2558 }
2559
2560 /* Old CPUs without secondary processor-based VM-execution controls would end up here. */
2561 return VINF_SUCCESS;
2562}
2563
2564
2565/**
2566 * Sets up miscellaneous (everything other than Pin & Processor-based
2567 * VM-execution) control fields in the VMCS.
2568 *
2569 * @returns VBox status code.
2570 * @param pVCpu The cross context virtual CPU structure.
2571 */
2572static int hmR0VmxSetupMiscCtls(PVMCPU pVCpu)
2573{
2574 AssertPtr(pVCpu);
2575
2576 int rc = VERR_GENERAL_FAILURE;
2577
2578 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2579#if 0
2580 /* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxExportGuestCR3AndCR4())*/
2581 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
2582 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
2583
2584 /*
2585 * Set MASK & MATCH to 0. VMX checks if GuestPFErrCode & MASK == MATCH. If equal (in our case it always is)
2586 * and if the X86_XCPT_PF bit in the exception bitmap is set it causes a VM-exit, if clear doesn't cause an exit.
2587 * We thus use the exception bitmap to control it rather than use both.
2588 */
2589 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
2590 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
2591
2592 /* All IO & IOIO instructions cause VM-exits. */
2593 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
2594 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
2595
2596 /* Initialize the MSR-bitmap area. */
2597 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
2598 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
2599 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
2600 AssertRCReturn(rc, rc);
2601#endif
2602
2603 /* Setup MSR auto-load/store area. */
2604 Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
2605 Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf)); /* Lower 4 bits MBZ. */
2606 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2607 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2608 AssertRCReturn(rc, rc);
2609
2610 Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
2611 Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf)); /* Lower 4 bits MBZ. */
2612 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
2613 AssertRCReturn(rc, rc);
2614
2615 /* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
2616 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
2617 AssertRCReturn(rc, rc);
2618
2619 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2620#if 0
2621 /* Setup debug controls */
2622 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0);
2623 rc |= VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
2624 AssertRCReturn(rc, rc);
2625#endif
2626
2627 return rc;
2628}
2629
2630
2631/**
2632 * Sets up the initial exception bitmap in the VMCS based on static conditions.
2633 *
2634 * We shall setup those exception intercepts that don't change during the
2635 * lifetime of the VM here. The rest are done dynamically while loading the
2636 * guest state.
2637 *
2638 * @returns VBox status code.
2639 * @param pVCpu The cross context virtual CPU structure.
2640 */
2641static int hmR0VmxInitXcptBitmap(PVMCPU pVCpu)
2642{
2643 AssertPtr(pVCpu);
2644
2645 uint32_t uXcptBitmap;
2646
2647 /* Must always intercept #AC to prevent the guest from hanging the CPU. */
2648 uXcptBitmap = RT_BIT_32(X86_XCPT_AC);
2649
2650 /* Because we need to maintain the DR6 state even when intercepting DRx reads
2651 and writes, and because recursive #DBs can cause the CPU hang, we must always
2652 intercept #DB. */
2653 uXcptBitmap |= RT_BIT_32(X86_XCPT_DB);
2654
2655 /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
2656 if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
2657 uXcptBitmap |= RT_BIT(X86_XCPT_PF);
2658
2659 /* Commit it to the VMCS. */
2660 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
2661 AssertRCReturn(rc, rc);
2662
2663 /* Update our cache of the exception bitmap. */
2664 pVCpu->hm.s.vmx.u32XcptBitmap = uXcptBitmap;
2665 return VINF_SUCCESS;
2666}
2667
2668
2669/**
2670 * Does per-VM VT-x initialization.
2671 *
2672 * @returns VBox status code.
2673 * @param pVM The cross context VM structure.
2674 */
2675VMMR0DECL(int) VMXR0InitVM(PVM pVM)
2676{
2677 LogFlowFunc(("pVM=%p\n", pVM));
2678
2679 int rc = hmR0VmxStructsAlloc(pVM);
2680 if (RT_FAILURE(rc))
2681 {
2682 LogRelFunc(("hmR0VmxStructsAlloc failed! rc=%Rrc\n", rc));
2683 return rc;
2684 }
2685
2686 return VINF_SUCCESS;
2687}
2688
2689
2690/**
2691 * Does per-VM VT-x termination.
2692 *
2693 * @returns VBox status code.
2694 * @param pVM The cross context VM structure.
2695 */
2696VMMR0DECL(int) VMXR0TermVM(PVM pVM)
2697{
2698 LogFlowFunc(("pVM=%p\n", pVM));
2699
2700#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2701 if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
2702 ASMMemZero32(pVM->hm.s.vmx.pvScratch, PAGE_SIZE);
2703#endif
2704 hmR0VmxStructsFree(pVM);
2705 return VINF_SUCCESS;
2706}
2707
2708
2709/**
2710 * Sets up the VM for execution under VT-x.
2711 * This function is only called once per-VM during initialization.
2712 *
2713 * @returns VBox status code.
2714 * @param pVM The cross context VM structure.
2715 */
2716VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
2717{
2718 AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
2719 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2720
2721 LogFlowFunc(("pVM=%p\n", pVM));
2722
2723 /*
2724 * Without UnrestrictedGuest, pRealModeTSS and pNonPagingModeEPTPageTable *must* always be
2725 * allocated. We no longer support the highly unlikely case of UnrestrictedGuest without
2726 * pRealModeTSS, see hmR3InitFinalizeR0Intel().
2727 */
2728 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
2729 && ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
2730 || !pVM->hm.s.vmx.pRealModeTSS))
2731 {
2732 LogRelFunc(("Invalid real-on-v86 state.\n"));
2733 return VERR_INTERNAL_ERROR;
2734 }
2735
2736 /* Initialize these always, see hmR3InitFinalizeR0().*/
2737 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NONE;
2738 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NONE;
2739
2740 /* Setup the tagged-TLB flush handlers. */
2741 int rc = hmR0VmxSetupTaggedTlb(pVM);
2742 if (RT_FAILURE(rc))
2743 {
2744 LogRelFunc(("hmR0VmxSetupTaggedTlb failed! rc=%Rrc\n", rc));
2745 return rc;
2746 }
2747
2748 /* Check if we can use the VMCS controls for swapping the EFER MSR. */
2749 Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
2750#if HC_ARCH_BITS == 64
2751 if ( (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
2752 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2753 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
2754 {
2755 pVM->hm.s.vmx.fSupportsVmcsEfer = true;
2756 }
2757#endif
2758
2759 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
2760 RTCCUINTREG uHostCR4 = ASMGetCR4();
2761 if (RT_UNLIKELY(!(uHostCR4 & X86_CR4_VMXE)))
2762 return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
2763
2764 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2765 {
2766 PVMCPU pVCpu = &pVM->aCpus[i];
2767 AssertPtr(pVCpu);
2768 AssertPtr(pVCpu->hm.s.vmx.pvVmcs);
2769
2770 /* Log the VCPU pointers, useful for debugging SMP VMs. */
2771 Log4Func(("pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
2772
2773 /* Set revision dword at the beginning of the VMCS structure. */
2774 *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
2775
2776 /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
2777 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2778 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc\n", rc),
2779 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2780
2781 /* Load this VMCS as the current VMCS. */
2782 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2783 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc\n", rc),
2784 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2785
2786 rc = hmR0VmxSetupPinCtls(pVCpu);
2787 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc\n", rc),
2788 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2789
2790 rc = hmR0VmxSetupProcCtls(pVCpu);
2791 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc\n", rc),
2792 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2793
2794 rc = hmR0VmxSetupMiscCtls(pVCpu);
2795 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc\n", rc),
2796 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2797
2798 rc = hmR0VmxInitXcptBitmap(pVCpu);
2799 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc\n", rc),
2800 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2801
2802#if HC_ARCH_BITS == 32
2803 rc = hmR0VmxInitVmcsReadCache(pVCpu);
2804 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc\n", rc),
2805 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2806#endif
2807
2808 /* Re-sync the CPU's internal data into our VMCS memory region & reset the launch state to "clear". */
2809 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2810 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc\n", rc),
2811 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2812
2813 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
2814
2815 hmR0VmxUpdateErrorRecord(pVCpu, rc);
2816 }
2817
2818 return VINF_SUCCESS;
2819}
2820
2821
2822/**
2823 * Saves the host control registers (CR0, CR3, CR4) into the host-state area in
2824 * the VMCS.
2825 *
2826 * @returns VBox status code.
2827 */
2828static int hmR0VmxExportHostControlRegs(void)
2829{
2830 RTCCUINTREG uReg = ASMGetCR0();
2831 int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
2832 AssertRCReturn(rc, rc);
2833
2834 uReg = ASMGetCR3();
2835 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
2836 AssertRCReturn(rc, rc);
2837
2838 uReg = ASMGetCR4();
2839 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
2840 AssertRCReturn(rc, rc);
2841 return rc;
2842}
2843
2844
2845/**
2846 * Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
2847 * the host-state area in the VMCS.
2848 *
2849 * @returns VBox status code.
2850 * @param pVCpu The cross context virtual CPU structure.
2851 */
2852static int hmR0VmxExportHostSegmentRegs(PVMCPU pVCpu)
2853{
2854#if HC_ARCH_BITS == 64
2855/**
2856 * Macro for adjusting host segment selectors to satisfy VT-x's VM-entry
2857 * requirements. See hmR0VmxExportHostSegmentRegs().
2858 */
2859# define VMXLOCAL_ADJUST_HOST_SEG(seg, selValue) \
2860 if ((selValue) & (X86_SEL_RPL | X86_SEL_LDT)) \
2861 { \
2862 bool fValidSelector = true; \
2863 if ((selValue) & X86_SEL_LDT) \
2864 { \
2865 uint32_t uAttr = ASMGetSegAttr((selValue)); \
2866 fValidSelector = RT_BOOL(uAttr != UINT32_MAX && (uAttr & X86_DESC_P)); \
2867 } \
2868 if (fValidSelector) \
2869 { \
2870 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_##seg; \
2871 pVCpu->hm.s.vmx.RestoreHost.uHostSel##seg = (selValue); \
2872 } \
2873 (selValue) = 0; \
2874 }
2875
2876 /*
2877 * If we've executed guest code using VT-x, the host-state bits will be messed up. We
2878 * should -not- save the messed up state without restoring the original host-state,
2879 * see @bugref{7240}.
2880 *
2881 * This apparently can happen (most likely the FPU changes), deal with it rather than
2882 * asserting. Was observed booting Solaris 10u10 32-bit guest.
2883 */
2884 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
2885 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
2886 {
2887 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags,
2888 pVCpu->idCpu));
2889 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
2890 }
2891 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
2892#else
2893 RT_NOREF(pVCpu);
2894#endif
2895
2896 /*
2897 * Host DS, ES, FS and GS segment registers.
2898 */
2899#if HC_ARCH_BITS == 64
2900 RTSEL uSelDS = ASMGetDS();
2901 RTSEL uSelES = ASMGetES();
2902 RTSEL uSelFS = ASMGetFS();
2903 RTSEL uSelGS = ASMGetGS();
2904#else
2905 RTSEL uSelDS = 0;
2906 RTSEL uSelES = 0;
2907 RTSEL uSelFS = 0;
2908 RTSEL uSelGS = 0;
2909#endif
2910
2911 /*
2912 * Host CS and SS segment registers.
2913 */
2914 RTSEL uSelCS = ASMGetCS();
2915 RTSEL uSelSS = ASMGetSS();
2916
2917 /*
2918 * Host TR segment register.
2919 */
2920 RTSEL uSelTR = ASMGetTR();
2921
2922#if HC_ARCH_BITS == 64
2923 /*
2924 * Determine if the host segment registers are suitable for VT-x. Otherwise use zero to
2925 * gain VM-entry and restore them before we get preempted.
2926 *
2927 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
2928 */
2929 VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
2930 VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
2931 VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
2932 VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
2933# undef VMXLOCAL_ADJUST_HOST_SEG
2934#endif
2935
2936 /* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
2937 Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
2938 Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
2939 Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
2940 Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
2941 Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
2942 Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
2943 Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
2944 Assert(uSelCS);
2945 Assert(uSelTR);
2946
2947 /* Assertion is right but we would not have updated u32ExitCtls yet. */
2948#if 0
2949 if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE))
2950 Assert(uSelSS != 0);
2951#endif
2952
2953 /* Write these host selector fields into the host-state area in the VMCS. */
2954 int rc = VMXWriteVmcs32(VMX_VMCS16_HOST_CS_SEL, uSelCS);
2955 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_SS_SEL, uSelSS);
2956#if HC_ARCH_BITS == 64
2957 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_DS_SEL, uSelDS);
2958 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_ES_SEL, uSelES);
2959 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FS_SEL, uSelFS);
2960 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_GS_SEL, uSelGS);
2961#else
2962 NOREF(uSelDS);
2963 NOREF(uSelES);
2964 NOREF(uSelFS);
2965 NOREF(uSelGS);
2966#endif
2967 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_TR_SEL, uSelTR);
2968 AssertRCReturn(rc, rc);
2969
2970 /*
2971 * Host GDTR and IDTR.
2972 */
2973 RTGDTR Gdtr;
2974 RTIDTR Idtr;
2975 RT_ZERO(Gdtr);
2976 RT_ZERO(Idtr);
2977 ASMGetGDTR(&Gdtr);
2978 ASMGetIDTR(&Idtr);
2979 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
2980 rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
2981 AssertRCReturn(rc, rc);
2982
2983#if HC_ARCH_BITS == 64
2984 /*
2985 * Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps
2986 * them to the maximum limit (0xffff) on every VM-exit.
2987 */
2988 if (Gdtr.cbGdt != 0xffff)
2989 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDTR;
2990
2991 /*
2992 * IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT" and
2993 * Intel spec. 6.2 "Exception and Interrupt Vectors".) Therefore if the host has the limit
2994 * as 0xfff, VT-x bloating the limit to 0xffff shouldn't cause any different CPU behavior.
2995 * However, several hosts either insists on 0xfff being the limit (Windows Patch Guard) or
2996 * uses the limit for other purposes (darwin puts the CPU ID in there but botches sidt
2997 * alignment in at least one consumer). So, we're only allowing the IDTR.LIMIT to be left
2998 * at 0xffff on hosts where we are sure it won't cause trouble.
2999 */
3000# if defined(RT_OS_LINUX) || defined(RT_OS_SOLARIS)
3001 if (Idtr.cbIdt < 0x0fff)
3002# else
3003 if (Idtr.cbIdt != 0xffff)
3004# endif
3005 {
3006 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_IDTR;
3007 AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
3008 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
3009 }
3010#endif
3011
3012 /*
3013 * Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI
3014 * and RPL bits is effectively what the CPU does for "scaling by 8". TI is always 0 and
3015 * RPL should be too in most cases.
3016 */
3017 AssertMsgReturn((uSelTR | X86_SEL_RPL_LDT) <= Gdtr.cbGdt,
3018 ("TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt), VERR_VMX_INVALID_HOST_STATE);
3019
3020 PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
3021#if HC_ARCH_BITS == 64
3022 uintptr_t uTRBase = X86DESC64_BASE(pDesc);
3023
3024 /*
3025 * VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on
3026 * all VM-exits. The type is the same for 64-bit busy TSS[1]. The limit needs manual
3027 * restoration if the host has something else. Task switching is not supported in 64-bit
3028 * mode[2], but the limit still matters as IOPM is supported in 64-bit mode. Restoring the
3029 * limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
3030 *
3031 * [1] See Intel spec. 3.5 "System Descriptor Types".
3032 * [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
3033 */
3034 PVM pVM = pVCpu->CTX_SUFF(pVM);
3035 Assert(pDesc->System.u4Type == 11);
3036 if ( pDesc->System.u16LimitLow != 0x67
3037 || pDesc->System.u4LimitHigh)
3038 {
3039 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_TR;
3040 /* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */
3041 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)
3042 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_READ_ONLY;
3043 pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
3044 }
3045
3046 /*
3047 * Store the GDTR as we need it when restoring the GDT and while restoring the TR.
3048 */
3049 if (pVCpu->hm.s.vmx.fRestoreHostFlags & (VMX_RESTORE_HOST_GDTR | VMX_RESTORE_HOST_SEL_TR))
3050 {
3051 AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
3052 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3053 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_NEED_WRITABLE)
3054 {
3055 /* The GDT is read-only but the writable GDT is available. */
3056 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_NEED_WRITABLE;
3057 pVCpu->hm.s.vmx.RestoreHost.HostGdtrRw.cb = Gdtr.cbGdt;
3058 rc = SUPR0GetCurrentGdtRw(&pVCpu->hm.s.vmx.RestoreHost.HostGdtrRw.uAddr);
3059 AssertRCReturn(rc, rc);
3060 }
3061 }
3062#else
3063 uintptr_t uTRBase = X86DESC_BASE(pDesc);
3064#endif
3065 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_TR_BASE, uTRBase);
3066 AssertRCReturn(rc, rc);
3067
3068 /*
3069 * Host FS base and GS base.
3070 */
3071#if HC_ARCH_BITS == 64
3072 uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
3073 uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
3074 rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
3075 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
3076 AssertRCReturn(rc, rc);
3077
3078 /* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
3079 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
3080 pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
3081 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
3082 pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
3083#endif
3084 return VINF_SUCCESS;
3085}
3086
3087
3088/**
3089 * Exports certain host MSRs in the VM-exit MSR-load area and some in the
3090 * host-state area of the VMCS.
3091 *
3092 * Theses MSRs will be automatically restored on the host after every successful
3093 * VM-exit.
3094 *
3095 * @returns VBox status code.
3096 * @param pVCpu The cross context virtual CPU structure.
3097 *
3098 * @remarks No-long-jump zone!!!
3099 */
3100static int hmR0VmxExportHostMsrs(PVMCPU pVCpu)
3101{
3102 AssertPtr(pVCpu);
3103 AssertPtr(pVCpu->hm.s.vmx.pvHostMsr);
3104
3105 /*
3106 * Save MSRs that we restore lazily (due to preemption or transition to ring-3)
3107 * rather than swapping them on every VM-entry.
3108 */
3109 hmR0VmxLazySaveHostMsrs(pVCpu);
3110
3111 /*
3112 * Host Sysenter MSRs.
3113 */
3114 int rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
3115#if HC_ARCH_BITS == 32
3116 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
3117 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
3118#else
3119 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
3120 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
3121#endif
3122 AssertRCReturn(rc, rc);
3123
3124 /*
3125 * Host EFER MSR.
3126 *
3127 * If the CPU supports the newer VMCS controls for managing EFER, use it. Otherwise it's
3128 * done as part of auto-load/store MSR area in the VMCS, see hmR0VmxExportGuestMsrs().
3129 */
3130 PVM pVM = pVCpu->CTX_SUFF(pVM);
3131 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
3132 {
3133 rc = VMXWriteVmcs64(VMX_VMCS64_HOST_EFER_FULL, pVM->hm.s.vmx.u64HostEfer);
3134 AssertRCReturn(rc, rc);
3135 }
3136
3137 /** @todo IA32_PERF_GLOBALCTRL, IA32_PAT also see hmR0VmxExportGuestExitCtls(). */
3138
3139 return VINF_SUCCESS;
3140}
3141
3142
3143/**
3144 * Figures out if we need to swap the EFER MSR which is particularly expensive.
3145 *
3146 * We check all relevant bits. For now, that's everything besides LMA/LME, as
3147 * these two bits are handled by VM-entry, see hmR0VmxExportGuestExitCtls() and
3148 * hmR0VMxExportGuestEntryCtls().
3149 *
3150 * @returns true if we need to load guest EFER, false otherwise.
3151 * @param pVCpu The cross context virtual CPU structure.
3152 *
3153 * @remarks Requires EFER, CR4.
3154 * @remarks No-long-jump zone!!!
3155 */
3156static bool hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu)
3157{
3158#ifdef HMVMX_ALWAYS_SWAP_EFER
3159 return true;
3160#endif
3161
3162 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3163#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
3164 /* For 32-bit hosts running 64-bit guests, we always swap EFER in the world-switcher. Nothing to do here. */
3165 if (CPUMIsGuestInLongModeEx(pCtx))
3166 return false;
3167#endif
3168
3169 PVM pVM = pVCpu->CTX_SUFF(pVM);
3170 uint64_t const u64HostEfer = pVM->hm.s.vmx.u64HostEfer;
3171 uint64_t const u64GuestEfer = pCtx->msrEFER;
3172
3173 /*
3174 * For 64-bit guests, if EFER.SCE bit differs, we need to swap EFER to ensure that the
3175 * guest's SYSCALL behaviour isn't broken, see @bugref{7386}.
3176 */
3177 if ( CPUMIsGuestInLongModeEx(pCtx)
3178 && (u64GuestEfer & MSR_K6_EFER_SCE) != (u64HostEfer & MSR_K6_EFER_SCE))
3179 {
3180 return true;
3181 }
3182
3183 /*
3184 * If the guest uses PAE and EFER.NXE bit differs, we need to swap EFER as it
3185 * affects guest paging. 64-bit paging implies CR4.PAE as well.
3186 * See Intel spec. 4.5 "IA-32e Paging" and Intel spec. 4.1.1 "Three Paging Modes".
3187 */
3188 if ( (pCtx->cr4 & X86_CR4_PAE)
3189 && (pCtx->cr0 & X86_CR0_PG)
3190 && (u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE))
3191 {
3192 /* Assert that host is NX capable. */
3193 Assert(pVCpu->CTX_SUFF(pVM)->cpum.ro.HostFeatures.fNoExecute);
3194 return true;
3195 }
3196
3197 return false;
3198}
3199
3200
3201/**
3202 * Exports the guest state with appropriate VM-entry controls in the VMCS.
3203 *
3204 * These controls can affect things done on VM-exit; e.g. "load debug controls",
3205 * see Intel spec. 24.8.1 "VM-entry controls".
3206 *
3207 * @returns VBox status code.
3208 * @param pVCpu The cross context virtual CPU structure.
3209 *
3210 * @remarks Requires EFER.
3211 * @remarks No-long-jump zone!!!
3212 */
3213static int hmR0VmxExportGuestEntryCtls(PVMCPU pVCpu)
3214{
3215 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_ENTRY_CTLS)
3216 {
3217 PVM pVM = pVCpu->CTX_SUFF(pVM);
3218 uint32_t fVal = pVM->hm.s.vmx.Msrs.EntryCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
3219 uint32_t const fZap = pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3220
3221 /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
3222 fVal |= VMX_ENTRY_CTLS_LOAD_DEBUG;
3223
3224 /* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
3225 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
3226 {
3227 fVal |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
3228 Log4Func(("VMX_ENTRY_CTLS_IA32E_MODE_GUEST\n"));
3229 }
3230 else
3231 Assert(!(fVal & VMX_ENTRY_CTLS_IA32E_MODE_GUEST));
3232
3233 /* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it. */
3234 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3235 && hmR0VmxShouldSwapEferMsr(pVCpu))
3236 {
3237 fVal |= VMX_ENTRY_CTLS_LOAD_EFER_MSR;
3238 Log4Func(("VMX_ENTRY_CTLS_LOAD_EFER_MSR\n"));
3239 }
3240
3241 /*
3242 * The following should -not- be set (since we're not in SMM mode):
3243 * - VMX_ENTRY_CTLS_ENTRY_TO_SMM
3244 * - VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON
3245 */
3246
3247 /** @todo VMX_ENTRY_CTLS_LOAD_PERF_MSR,
3248 * VMX_ENTRY_CTLS_LOAD_PAT_MSR. */
3249
3250 if ((fVal & fZap) != fVal)
3251 {
3252 Log4Func(("Invalid VM-entry controls combo! Cpu=%RX64 fVal=%RX64 fZap=%RX64\n",
3253 pVM->hm.s.vmx.Msrs.EntryCtls.n.disallowed0, fVal, fZap));
3254 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
3255 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3256 }
3257
3258 /* Commit it to the VMCS and update our cache. */
3259 if (pVCpu->hm.s.vmx.u32EntryCtls != fVal)
3260 {
3261 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, fVal);
3262 AssertRCReturn(rc, rc);
3263 pVCpu->hm.s.vmx.u32EntryCtls = fVal;
3264 }
3265
3266 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_ENTRY_CTLS);
3267 }
3268 return VINF_SUCCESS;
3269}
3270
3271
3272/**
3273 * Exports the guest state with appropriate VM-exit controls in the VMCS.
3274 *
3275 * @returns VBox status code.
3276 * @param pVCpu The cross context virtual CPU structure.
3277 *
3278 * @remarks Requires EFER.
3279 */
3280static int hmR0VmxExportGuestExitCtls(PVMCPU pVCpu)
3281{
3282 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_EXIT_CTLS)
3283 {
3284 PVM pVM = pVCpu->CTX_SUFF(pVM);
3285 uint32_t fVal = pVM->hm.s.vmx.Msrs.ExitCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
3286 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3287
3288 /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
3289 fVal |= VMX_EXIT_CTLS_SAVE_DEBUG;
3290
3291 /*
3292 * Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary.
3293 * On VM-exit, VT-x sets both the host EFER.LMA and EFER.LME bit to this value. See assertion in
3294 * hmR0VmxExportHostMsrs().
3295 */
3296#if HC_ARCH_BITS == 64
3297 fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
3298 Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
3299#else
3300 Assert( pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64
3301 || pVCpu->hm.s.vmx.pfnStartVM == VMXR0StartVM32);
3302 /* Set the host address-space size based on the switcher, not guest state. See @bugref{8432}. */
3303 if (pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64)
3304 {
3305 /* The switcher returns to long mode, EFER is managed by the switcher. */
3306 fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
3307 Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
3308 }
3309 else
3310 Assert(!(fVal & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE));
3311#endif
3312
3313 /* If the newer VMCS fields for managing EFER exists, use it. */
3314 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3315 && hmR0VmxShouldSwapEferMsr(pVCpu))
3316 {
3317 fVal |= VMX_EXIT_CTLS_SAVE_EFER_MSR
3318 | VMX_EXIT_CTLS_LOAD_EFER_MSR;
3319 Log4Func(("VMX_EXIT_CTLS_SAVE_EFER_MSR and VMX_EXIT_CTLS_LOAD_EFER_MSR\n"));
3320 }
3321
3322 /* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
3323 Assert(!(fVal & VMX_EXIT_CTLS_ACK_EXT_INT));
3324
3325 /** @todo VMX_EXIT_CTLS_LOAD_PERF_MSR,
3326 * VMX_EXIT_CTLS_SAVE_PAT_MSR,
3327 * VMX_EXIT_CTLS_LOAD_PAT_MSR. */
3328
3329 /* Enable saving of the VMX preemption timer value on VM-exit. */
3330 if ( pVM->hm.s.vmx.fUsePreemptTimer
3331 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER))
3332 fVal |= VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER;
3333
3334 if ((fVal & fZap) != fVal)
3335 {
3336 LogRelFunc(("Invalid VM-exit controls combo! cpu=%RX64 fVal=%RX64 fZap=%RX64\n",
3337 pVM->hm.s.vmx.Msrs.ExitCtls.n.disallowed0, fVal, fZap));
3338 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
3339 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3340 }
3341
3342 /* Commit it to the VMCS and update our cache. */
3343 if (pVCpu->hm.s.vmx.u32ExitCtls != fVal)
3344 {
3345 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, fVal);
3346 AssertRCReturn(rc, rc);
3347 pVCpu->hm.s.vmx.u32ExitCtls = fVal;
3348 }
3349
3350 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_EXIT_CTLS);
3351 }
3352 return VINF_SUCCESS;
3353}
3354
3355
3356/**
3357 * Sets the TPR threshold in the VMCS.
3358 *
3359 * @returns VBox status code.
3360 * @param pVCpu The cross context virtual CPU structure.
3361 * @param u32TprThreshold The TPR threshold (task-priority class only).
3362 */
3363DECLINLINE(int) hmR0VmxApicSetTprThreshold(PVMCPU pVCpu, uint32_t u32TprThreshold)
3364{
3365 Assert(!(u32TprThreshold & 0xfffffff0)); /* Bits 31:4 MBZ. */
3366 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
3367 return VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
3368}
3369
3370
3371/**
3372 * Exports the guest APIC TPR state into the VMCS.
3373 *
3374 * @returns VBox status code.
3375 * @param pVCpu The cross context virtual CPU structure.
3376 *
3377 * @remarks No-long-jump zone!!!
3378 */
3379static int hmR0VmxExportGuestApicTpr(PVMCPU pVCpu)
3380{
3381 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
3382 {
3383 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
3384
3385 if ( PDMHasApic(pVCpu->CTX_SUFF(pVM))
3386 && APICIsEnabled(pVCpu))
3387 {
3388 /*
3389 * Setup TPR shadowing.
3390 */
3391 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3392 {
3393 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
3394
3395 bool fPendingIntr = false;
3396 uint8_t u8Tpr = 0;
3397 uint8_t u8PendingIntr = 0;
3398 int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
3399 AssertRCReturn(rc, rc);
3400
3401 /*
3402 * If there are interrupts pending but masked by the TPR, instruct VT-x to
3403 * cause a TPR-below-threshold VM-exit when the guest lowers its TPR below the
3404 * priority of the pending interrupt so we can deliver the interrupt. If there
3405 * are no interrupts pending, set threshold to 0 to not cause any
3406 * TPR-below-threshold VM-exits.
3407 */
3408 pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR] = u8Tpr;
3409 uint32_t u32TprThreshold = 0;
3410 if (fPendingIntr)
3411 {
3412 /* Bits 3:0 of the TPR threshold field correspond to bits 7:4 of the TPR (which is the Task-Priority Class). */
3413 const uint8_t u8PendingPriority = u8PendingIntr >> 4;
3414 const uint8_t u8TprPriority = u8Tpr >> 4;
3415 if (u8PendingPriority <= u8TprPriority)
3416 u32TprThreshold = u8PendingPriority;
3417 }
3418
3419 rc = hmR0VmxApicSetTprThreshold(pVCpu, u32TprThreshold);
3420 AssertRCReturn(rc, rc);
3421 }
3422 }
3423 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
3424 }
3425 return VINF_SUCCESS;
3426}
3427
3428
3429/**
3430 * Gets the guest's interruptibility-state ("interrupt shadow" as AMD calls it).
3431 *
3432 * @returns Guest's interruptibility-state.
3433 * @param pVCpu The cross context virtual CPU structure.
3434 *
3435 * @remarks No-long-jump zone!!!
3436 */
3437static uint32_t hmR0VmxGetGuestIntrState(PVMCPU pVCpu)
3438{
3439 /*
3440 * Check if we should inhibit interrupt delivery due to instructions like STI and MOV SS.
3441 */
3442 uint32_t fIntrState = 0;
3443 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3444 {
3445 /* If inhibition is active, RIP & RFLAGS should've been accessed
3446 (i.e. read previously from the VMCS or from ring-3). */
3447 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3448#ifdef VBOX_STRICT
3449 uint64_t const fExtrn = ASMAtomicUoReadU64(&pCtx->fExtrn);
3450 AssertMsg(!(fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)), ("%#x\n", fExtrn));
3451#endif
3452 if (pCtx->rip == EMGetInhibitInterruptsPC(pVCpu))
3453 {
3454 if (pCtx->eflags.Bits.u1IF)
3455 fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
3456 else
3457 fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
3458 }
3459 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3460 {
3461 /*
3462 * We can clear the inhibit force flag as even if we go back to the recompiler
3463 * without executing guest code in VT-x, the flag's condition to be cleared is
3464 * met and thus the cleared state is correct.
3465 */
3466 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3467 }
3468 }
3469
3470 /*
3471 * NMIs to the guest are blocked after an NMI is injected until the guest executes an IRET. We only
3472 * bother with virtual-NMI blocking when we have support for virtual NMIs in the CPU, otherwise
3473 * setting this would block host-NMIs and IRET will not clear the blocking.
3474 *
3475 * See Intel spec. 26.6.1 "Interruptibility state". See @bugref{7445}.
3476 */
3477 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
3478 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3479 {
3480 fIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
3481 }
3482
3483 return fIntrState;
3484}
3485
3486
3487/**
3488 * Exports the guest's interruptibility-state into the guest-state area in the
3489 * VMCS.
3490 *
3491 * @returns VBox status code.
3492 * @param pVCpu The cross context virtual CPU structure.
3493 * @param fIntrState The interruptibility-state to set.
3494 */
3495static int hmR0VmxExportGuestIntrState(PVMCPU pVCpu, uint32_t fIntrState)
3496{
3497 NOREF(pVCpu);
3498 AssertMsg(!(fIntrState & 0xfffffff0), ("%#x\n", fIntrState)); /* Bits 31:4 MBZ. */
3499 Assert((fIntrState & 0x3) != 0x3); /* Block-by-STI and MOV SS cannot be simultaneously set. */
3500 return VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
3501}
3502
3503
3504/**
3505 * Exports the exception intercepts required for guest execution in the VMCS.
3506 *
3507 * @returns VBox status code.
3508 * @param pVCpu The cross context virtual CPU structure.
3509 *
3510 * @remarks No-long-jump zone!!!
3511 */
3512static int hmR0VmxExportGuestXcptIntercepts(PVMCPU pVCpu)
3513{
3514 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS)
3515 {
3516 uint32_t uXcptBitmap = pVCpu->hm.s.vmx.u32XcptBitmap;
3517
3518 /* The remaining exception intercepts are handled elsewhere, e.g. in hmR0VmxExportSharedCR0(). */
3519 if (pVCpu->hm.s.fGIMTrapXcptUD)
3520 uXcptBitmap |= RT_BIT(X86_XCPT_UD);
3521#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3522 else
3523 uXcptBitmap &= ~RT_BIT(X86_XCPT_UD);
3524#endif
3525
3526 Assert(uXcptBitmap & RT_BIT_32(X86_XCPT_AC));
3527 Assert(uXcptBitmap & RT_BIT_32(X86_XCPT_DB));
3528
3529 if (uXcptBitmap != pVCpu->hm.s.vmx.u32XcptBitmap)
3530 {
3531 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
3532 AssertRCReturn(rc, rc);
3533 pVCpu->hm.s.vmx.u32XcptBitmap = uXcptBitmap;
3534 }
3535
3536 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS);
3537 Log4Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP=%#RX64\n", uXcptBitmap));
3538 }
3539 return VINF_SUCCESS;
3540}
3541
3542
3543/**
3544 * Exports the guest's RIP into the guest-state area in the VMCS.
3545 *
3546 * @returns VBox status code.
3547 * @param pVCpu The cross context virtual CPU structure.
3548 *
3549 * @remarks No-long-jump zone!!!
3550 */
3551static int hmR0VmxExportGuestRip(PVMCPU pVCpu)
3552{
3553 int rc = VINF_SUCCESS;
3554 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RIP)
3555 {
3556 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP);
3557
3558 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pVCpu->cpum.GstCtx.rip);
3559 AssertRCReturn(rc, rc);
3560
3561 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RIP);
3562 Log4Func(("RIP=%#RX64\n", pVCpu->cpum.GstCtx.rip));
3563 }
3564 return rc;
3565}
3566
3567
3568/**
3569 * Exports the guest's RSP into the guest-state area in the VMCS.
3570 *
3571 * @returns VBox status code.
3572 * @param pVCpu The cross context virtual CPU structure.
3573 *
3574 * @remarks No-long-jump zone!!!
3575 */
3576static int hmR0VmxExportGuestRsp(PVMCPU pVCpu)
3577{
3578 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RSP)
3579 {
3580 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP);
3581
3582 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pVCpu->cpum.GstCtx.rsp);
3583 AssertRCReturn(rc, rc);
3584
3585 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RSP);
3586 }
3587 return VINF_SUCCESS;
3588}
3589
3590
3591/**
3592 * Exports the guest's RFLAGS into the guest-state area in the VMCS.
3593 *
3594 * @returns VBox status code.
3595 * @param pVCpu The cross context virtual CPU structure.
3596 *
3597 * @remarks No-long-jump zone!!!
3598 */
3599static int hmR0VmxExportGuestRflags(PVMCPU pVCpu)
3600{
3601 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RFLAGS)
3602 {
3603 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RFLAGS);
3604
3605 /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
3606 Let us assert it as such and use 32-bit VMWRITE. */
3607 Assert(!RT_HI_U32(pVCpu->cpum.GstCtx.rflags.u64));
3608 X86EFLAGS fEFlags = pVCpu->cpum.GstCtx.eflags;
3609 Assert(fEFlags.u32 & X86_EFL_RA1_MASK);
3610 Assert(!(fEFlags.u32 & ~(X86_EFL_1 | X86_EFL_LIVE_MASK)));
3611
3612 /*
3613 * If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so
3614 * we can restore them on VM-exit. Modify the real-mode guest's eflags so that VT-x
3615 * can run the real-mode guest code under Virtual 8086 mode.
3616 */
3617 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3618 {
3619 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
3620 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
3621 pVCpu->hm.s.vmx.RealMode.Eflags.u32 = fEFlags.u32; /* Save the original eflags of the real-mode guest. */
3622 fEFlags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
3623 fEFlags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
3624 }
3625
3626 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_RFLAGS, fEFlags.u32);
3627 AssertRCReturn(rc, rc);
3628
3629 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RFLAGS);
3630 Log4Func(("EFlags=%#RX32\n", fEFlags.u32));
3631 }
3632 return VINF_SUCCESS;
3633}
3634
3635
3636/**
3637 * Exports the guest CR0 control register into the guest-state area in the VMCS.
3638 *
3639 * The guest FPU state is always pre-loaded hence we don't need to bother about
3640 * sharing FPU related CR0 bits between the guest and host.
3641 *
3642 * @returns VBox status code.
3643 * @param pVCpu The cross context virtual CPU structure.
3644 *
3645 * @remarks No-long-jump zone!!!
3646 */
3647static int hmR0VmxExportGuestCR0(PVMCPU pVCpu)
3648{
3649 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR0)
3650 {
3651 PVM pVM = pVCpu->CTX_SUFF(pVM);
3652 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3653 Assert(!RT_HI_U32(pVCpu->cpum.GstCtx.cr0));
3654
3655 uint32_t const u32ShadowCr0 = pVCpu->cpum.GstCtx.cr0;
3656 uint32_t u32GuestCr0 = pVCpu->cpum.GstCtx.cr0;
3657
3658 /*
3659 * Setup VT-x's view of the guest CR0.
3660 * Minimize VM-exits due to CR3 changes when we have NestedPaging.
3661 */
3662 uint32_t uProcCtls = pVCpu->hm.s.vmx.u32ProcCtls;
3663 if (pVM->hm.s.fNestedPaging)
3664 {
3665 if (CPUMIsGuestPagingEnabled(pVCpu))
3666 {
3667 /* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
3668 uProcCtls &= ~( VMX_PROC_CTLS_CR3_LOAD_EXIT
3669 | VMX_PROC_CTLS_CR3_STORE_EXIT);
3670 }
3671 else
3672 {
3673 /* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
3674 uProcCtls |= VMX_PROC_CTLS_CR3_LOAD_EXIT
3675 | VMX_PROC_CTLS_CR3_STORE_EXIT;
3676 }
3677
3678 /* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
3679 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3680 uProcCtls &= ~VMX_PROC_CTLS_CR3_STORE_EXIT;
3681 }
3682 else
3683 {
3684 /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
3685 u32GuestCr0 |= X86_CR0_WP;
3686 }
3687
3688 /*
3689 * Guest FPU bits.
3690 *
3691 * Since we pre-load the guest FPU always before VM-entry there is no need to track lazy state
3692 * using CR0.TS.
3693 *
3694 * Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be
3695 * set on the first CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
3696 */
3697 u32GuestCr0 |= X86_CR0_NE;
3698
3699 /* If CR0.NE isn't set, we need to intercept #MF exceptions and report them to the guest differently. */
3700 bool const fInterceptMF = !(u32ShadowCr0 & X86_CR0_NE);
3701
3702 /*
3703 * Update exception intercepts.
3704 */
3705 uint32_t uXcptBitmap = pVCpu->hm.s.vmx.u32XcptBitmap;
3706 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3707 {
3708 Assert(PDMVmmDevHeapIsEnabled(pVM));
3709 Assert(pVM->hm.s.vmx.pRealModeTSS);
3710 uXcptBitmap |= HMVMX_REAL_MODE_XCPT_MASK;
3711 }
3712 else
3713 {
3714 /* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */
3715 uXcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
3716 if (fInterceptMF)
3717 uXcptBitmap |= RT_BIT(X86_XCPT_MF);
3718 }
3719
3720 /* Additional intercepts for debugging, define these yourself explicitly. */
3721#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3722 uXcptBitmap |= 0
3723 | RT_BIT(X86_XCPT_BP)
3724 | RT_BIT(X86_XCPT_DE)
3725 | RT_BIT(X86_XCPT_NM)
3726 | RT_BIT(X86_XCPT_TS)
3727 | RT_BIT(X86_XCPT_UD)
3728 | RT_BIT(X86_XCPT_NP)
3729 | RT_BIT(X86_XCPT_SS)
3730 | RT_BIT(X86_XCPT_GP)
3731 | RT_BIT(X86_XCPT_PF)
3732 | RT_BIT(X86_XCPT_MF)
3733 ;
3734#elif defined(HMVMX_ALWAYS_TRAP_PF)
3735 uXcptBitmap |= RT_BIT(X86_XCPT_PF);
3736#endif
3737 Assert(pVM->hm.s.fNestedPaging || (uXcptBitmap & RT_BIT(X86_XCPT_PF)));
3738
3739 /*
3740 * Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW).
3741 */
3742 uint32_t fSetCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3743 uint32_t fZapCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3744 if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */
3745 fSetCr0 &= ~(X86_CR0_PE | X86_CR0_PG);
3746 else
3747 Assert((fSetCr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG));
3748
3749 u32GuestCr0 |= fSetCr0;
3750 u32GuestCr0 &= fZapCr0;
3751 u32GuestCr0 &= ~(X86_CR0_CD | X86_CR0_NW); /* Always enable caching. */
3752
3753 /*
3754 * CR0 is shared between host and guest along with a CR0 read shadow. Therefore, certain bits must not be changed
3755 * by the guest because VT-x ignores saving/restoring them (namely CD, ET, NW) and for certain other bits
3756 * we want to be notified immediately of guest CR0 changes (e.g. PG to update our shadow page tables).
3757 */
3758 uint32_t u32Cr0Mask = X86_CR0_PE
3759 | X86_CR0_NE
3760 | (pVM->hm.s.fNestedPaging ? 0 : X86_CR0_WP)
3761 | X86_CR0_PG
3762 | X86_CR0_ET /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
3763 | X86_CR0_CD /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
3764 | X86_CR0_NW; /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.NW */
3765
3766 /** @todo Avoid intercepting CR0.PE with unrestricted guests. Fix PGM
3767 * enmGuestMode to be in-sync with the current mode. See @bugref{6398}
3768 * and @bugref{6944}. */
3769#if 0
3770 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3771 u32Cr0Mask &= ~X86_CR0_PE;
3772#endif
3773 /*
3774 * Finally, update VMCS fields with the CR0 values and the exception bitmap.
3775 */
3776 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCr0);
3777 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, u32ShadowCr0);
3778 if (u32Cr0Mask != pVCpu->hm.s.vmx.u32Cr0Mask)
3779 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32Cr0Mask);
3780 if (uProcCtls != pVCpu->hm.s.vmx.u32ProcCtls)
3781 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
3782 if (uXcptBitmap != pVCpu->hm.s.vmx.u32XcptBitmap)
3783 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
3784 AssertRCReturn(rc, rc);
3785
3786 /* Update our caches. */
3787 pVCpu->hm.s.vmx.u32Cr0Mask = u32Cr0Mask;
3788 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
3789 pVCpu->hm.s.vmx.u32XcptBitmap = uXcptBitmap;
3790
3791 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR0);
3792
3793 Log4Func(("u32Cr0Mask=%#RX32 u32ShadowCr0=%#RX32 u32GuestCr0=%#RX32 (fSetCr0=%#RX32 fZapCr0=%#RX32\n", u32Cr0Mask,
3794 u32ShadowCr0, u32GuestCr0, fSetCr0, fZapCr0));
3795 }
3796
3797 return VINF_SUCCESS;
3798}
3799
3800
3801/**
3802 * Exports the guest control registers (CR3, CR4) into the guest-state area
3803 * in the VMCS.
3804 *
3805 * @returns VBox strict status code.
3806 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
3807 * without unrestricted guest access and the VMMDev is not presently
3808 * mapped (e.g. EFI32).
3809 *
3810 * @param pVCpu The cross context virtual CPU structure.
3811 *
3812 * @remarks No-long-jump zone!!!
3813 */
3814static VBOXSTRICTRC hmR0VmxExportGuestCR3AndCR4(PVMCPU pVCpu)
3815{
3816 int rc = VINF_SUCCESS;
3817 PVM pVM = pVCpu->CTX_SUFF(pVM);
3818
3819 /*
3820 * Guest CR2.
3821 * It's always loaded in the assembler code. Nothing to do here.
3822 */
3823
3824 /*
3825 * Guest CR3.
3826 */
3827 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR3)
3828 {
3829 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3830
3831 RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
3832 if (pVM->hm.s.fNestedPaging)
3833 {
3834 pVCpu->hm.s.vmx.HCPhysEPTP = PGMGetHyperCR3(pVCpu);
3835
3836 /* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
3837 Assert(pVCpu->hm.s.vmx.HCPhysEPTP);
3838 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & UINT64_C(0xfff0000000000000)));
3839 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & 0xfff));
3840
3841 /* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
3842 pVCpu->hm.s.vmx.HCPhysEPTP |= VMX_EPT_MEMTYPE_WB
3843 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
3844
3845 /* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
3846 AssertMsg( ((pVCpu->hm.s.vmx.HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
3847 && ((pVCpu->hm.s.vmx.HCPhysEPTP >> 7) & 0x1f) == 0, /* Bits 7:11 MBZ. */
3848 ("EPTP %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3849 AssertMsg( !((pVCpu->hm.s.vmx.HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */
3850 || (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
3851 ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3852
3853 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.HCPhysEPTP);
3854 AssertRCReturn(rc, rc);
3855
3856 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3857 if ( pVM->hm.s.vmx.fUnrestrictedGuest
3858 || CPUMIsGuestPagingEnabledEx(pCtx))
3859 {
3860 /* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
3861 if (CPUMIsGuestInPAEModeEx(pCtx))
3862 {
3863 rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
3864 AssertRCReturn(rc, rc);
3865 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);
3866 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);
3867 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);
3868 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);
3869 AssertRCReturn(rc, rc);
3870 }
3871
3872 /*
3873 * The guest's view of its CR3 is unblemished with Nested Paging when the
3874 * guest is using paging or we have unrestricted guest execution to handle
3875 * the guest when it's not using paging.
3876 */
3877 GCPhysGuestCR3 = pCtx->cr3;
3878 }
3879 else
3880 {
3881 /*
3882 * The guest is not using paging, but the CPU (VT-x) has to. While the guest
3883 * thinks it accesses physical memory directly, we use our identity-mapped
3884 * page table to map guest-linear to guest-physical addresses. EPT takes care
3885 * of translating it to host-physical addresses.
3886 */
3887 RTGCPHYS GCPhys;
3888 Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
3889
3890 /* We obtain it here every time as the guest could have relocated this PCI region. */
3891 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
3892 if (RT_SUCCESS(rc))
3893 { /* likely */ }
3894 else if (rc == VERR_PDM_DEV_HEAP_R3_TO_GCPHYS)
3895 {
3896 Log4Func(("VERR_PDM_DEV_HEAP_R3_TO_GCPHYS -> VINF_EM_RESCHEDULE_REM\n"));
3897 return VINF_EM_RESCHEDULE_REM; /* We cannot execute now, switch to REM/IEM till the guest maps in VMMDev. */
3898 }
3899 else
3900 AssertMsgFailedReturn(("%Rrc\n", rc), rc);
3901
3902 GCPhysGuestCR3 = GCPhys;
3903 }
3904
3905 Log4Func(("u32GuestCr3=%#RGp (GstN)\n", GCPhysGuestCR3));
3906 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR3, GCPhysGuestCR3);
3907 AssertRCReturn(rc, rc);
3908 }
3909 else
3910 {
3911 /* Non-nested paging case, just use the hypervisor's CR3. */
3912 RTHCPHYS HCPhysGuestCR3 = PGMGetHyperCR3(pVCpu);
3913
3914 Log4Func(("u32GuestCr3=%#RHv (HstN)\n", HCPhysGuestCR3));
3915 rc = VMXWriteVmcsHstN(VMX_VMCS_GUEST_CR3, HCPhysGuestCR3);
3916 AssertRCReturn(rc, rc);
3917 }
3918
3919 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR3);
3920 }
3921
3922 /*
3923 * Guest CR4.
3924 * ASSUMES this is done everytime we get in from ring-3! (XCR0)
3925 */
3926 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR4)
3927 {
3928 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3929 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3930 Assert(!RT_HI_U32(pCtx->cr4));
3931
3932 uint32_t u32GuestCr4 = pCtx->cr4;
3933 uint32_t const u32ShadowCr4 = pCtx->cr4;
3934
3935 /*
3936 * Setup VT-x's view of the guest CR4.
3937 *
3938 * If we're emulating real-mode using virtual-8086 mode, we want to redirect software
3939 * interrupts to the 8086 program interrupt handler. Clear the VME bit (the interrupt
3940 * redirection bitmap is already all 0, see hmR3InitFinalizeR0())
3941 *
3942 * See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
3943 */
3944 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3945 {
3946 Assert(pVM->hm.s.vmx.pRealModeTSS);
3947 Assert(PDMVmmDevHeapIsEnabled(pVM));
3948 u32GuestCr4 &= ~X86_CR4_VME;
3949 }
3950
3951 if (pVM->hm.s.fNestedPaging)
3952 {
3953 if ( !CPUMIsGuestPagingEnabledEx(pCtx)
3954 && !pVM->hm.s.vmx.fUnrestrictedGuest)
3955 {
3956 /* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
3957 u32GuestCr4 |= X86_CR4_PSE;
3958 /* Our identity mapping is a 32-bit page directory. */
3959 u32GuestCr4 &= ~X86_CR4_PAE;
3960 }
3961 /* else use guest CR4.*/
3962 }
3963 else
3964 {
3965 /*
3966 * The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
3967 * paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
3968 */
3969 switch (pVCpu->hm.s.enmShadowMode)
3970 {
3971 case PGMMODE_REAL: /* Real-mode. */
3972 case PGMMODE_PROTECTED: /* Protected mode without paging. */
3973 case PGMMODE_32_BIT: /* 32-bit paging. */
3974 {
3975 u32GuestCr4 &= ~X86_CR4_PAE;
3976 break;
3977 }
3978
3979 case PGMMODE_PAE: /* PAE paging. */
3980 case PGMMODE_PAE_NX: /* PAE paging with NX. */
3981 {
3982 u32GuestCr4 |= X86_CR4_PAE;
3983 break;
3984 }
3985
3986 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
3987 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
3988#ifdef VBOX_ENABLE_64_BITS_GUESTS
3989 break;
3990#endif
3991 default:
3992 AssertFailed();
3993 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
3994 }
3995 }
3996
3997 /* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */
3998 uint64_t const fSetCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
3999 uint64_t const fZapCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4000 u32GuestCr4 |= fSetCr4;
4001 u32GuestCr4 &= fZapCr4;
4002
4003 /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them,
4004 that would cause a VM-exit. */
4005 uint32_t u32Cr4Mask = X86_CR4_VME
4006 | X86_CR4_PAE
4007 | X86_CR4_PGE
4008 | X86_CR4_PSE
4009 | X86_CR4_VMXE;
4010 if (pVM->cpum.ro.HostFeatures.fXSaveRstor)
4011 u32Cr4Mask |= X86_CR4_OSXSAVE;
4012 if (pVM->cpum.ro.GuestFeatures.fPcid)
4013 u32Cr4Mask |= X86_CR4_PCIDE;
4014
4015 /* Write VT-x's view of the guest CR4, the CR4 modify mask and the read-only CR4 shadow
4016 into the VMCS and update our cache. */
4017 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCr4);
4018 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32ShadowCr4);
4019 if (pVCpu->hm.s.vmx.u32Cr4Mask != u32Cr4Mask)
4020 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32Cr4Mask);
4021 AssertRCReturn(rc, rc);
4022 pVCpu->hm.s.vmx.u32Cr4Mask = u32Cr4Mask;
4023
4024 /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
4025 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4026
4027 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR4);
4028
4029 Log4Func(("u32GuestCr4=%#RX32 u32ShadowCr4=%#RX32 (fSetCr4=%#RX32 fZapCr4=%#RX32)\n", u32GuestCr4, u32ShadowCr4, fSetCr4,
4030 fZapCr4));
4031 }
4032 return rc;
4033}
4034
4035
4036/**
4037 * Exports the guest debug registers into the guest-state area in the VMCS.
4038 * The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
4039 *
4040 * This also sets up whether \#DB and MOV DRx accesses cause VM-exits.
4041 *
4042 * @returns VBox status code.
4043 * @param pVCpu The cross context virtual CPU structure.
4044 *
4045 * @remarks No-long-jump zone!!!
4046 */
4047static int hmR0VmxExportSharedDebugState(PVMCPU pVCpu)
4048{
4049 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4050
4051#ifdef VBOX_STRICT
4052 /* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
4053 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4054 {
4055 /* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
4056 Assert((pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_MBZ_MASK | X86_DR7_RAZ_MASK)) == 0);
4057 Assert((pVCpu->cpum.GstCtx.dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK);
4058 }
4059#endif
4060
4061 bool fSteppingDB = false;
4062 bool fInterceptMovDRx = false;
4063 uint32_t uProcCtls = pVCpu->hm.s.vmx.u32ProcCtls;
4064 if (pVCpu->hm.s.fSingleInstruction)
4065 {
4066 /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
4067 PVM pVM = pVCpu->CTX_SUFF(pVM);
4068 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
4069 {
4070 uProcCtls |= VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
4071 Assert(fSteppingDB == false);
4072 }
4073 else
4074 {
4075 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_TF;
4076 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_GUEST_RFLAGS;
4077 pVCpu->hm.s.fClearTrapFlag = true;
4078 fSteppingDB = true;
4079 }
4080 }
4081
4082 uint32_t u32GuestDr7;
4083 if ( fSteppingDB
4084 || (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
4085 {
4086 /*
4087 * Use the combined guest and host DRx values found in the hypervisor register set
4088 * because the debugger has breakpoints active or someone is single stepping on the
4089 * host side without a monitor trap flag.
4090 *
4091 * Note! DBGF expects a clean DR6 state before executing guest code.
4092 */
4093#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4094 if ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
4095 && !CPUMIsHyperDebugStateActivePending(pVCpu))
4096 {
4097 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4098 Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
4099 Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
4100 }
4101 else
4102#endif
4103 if (!CPUMIsHyperDebugStateActive(pVCpu))
4104 {
4105 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4106 Assert(CPUMIsHyperDebugStateActive(pVCpu));
4107 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
4108 }
4109
4110 /* Update DR7 with the hypervisor value (other DRx registers are handled by CPUM one way or another). */
4111 u32GuestDr7 = (uint32_t)CPUMGetHyperDR7(pVCpu);
4112 pVCpu->hm.s.fUsingHyperDR7 = true;
4113 fInterceptMovDRx = true;
4114 }
4115 else
4116 {
4117 /*
4118 * If the guest has enabled debug registers, we need to load them prior to
4119 * executing guest code so they'll trigger at the right time.
4120 */
4121 if (pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_ENABLED_MASK | X86_DR7_GD))
4122 {
4123#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4124 if ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
4125 && !CPUMIsGuestDebugStateActivePending(pVCpu))
4126 {
4127 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4128 Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
4129 Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
4130 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4131 }
4132 else
4133#endif
4134 if (!CPUMIsGuestDebugStateActive(pVCpu))
4135 {
4136 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4137 Assert(CPUMIsGuestDebugStateActive(pVCpu));
4138 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
4139 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4140 }
4141 Assert(!fInterceptMovDRx);
4142 }
4143 /*
4144 * If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
4145 * must intercept #DB in order to maintain a correct DR6 guest value, and
4146 * because we need to intercept it to prevent nested #DBs from hanging the
4147 * CPU, we end up always having to intercept it. See hmR0VmxInitXcptBitmap.
4148 */
4149#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4150 else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
4151 && !CPUMIsGuestDebugStateActive(pVCpu))
4152#else
4153 else if (!CPUMIsGuestDebugStateActive(pVCpu))
4154#endif
4155 {
4156 fInterceptMovDRx = true;
4157 }
4158
4159 /* Update DR7 with the actual guest value. */
4160 u32GuestDr7 = pVCpu->cpum.GstCtx.dr[7];
4161 pVCpu->hm.s.fUsingHyperDR7 = false;
4162 }
4163
4164 if (fInterceptMovDRx)
4165 uProcCtls |= VMX_PROC_CTLS_MOV_DR_EXIT;
4166 else
4167 uProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
4168
4169 /*
4170 * Update the processor-based VM-execution controls with the MOV-DRx intercepts and the
4171 * monitor-trap flag and update our cache.
4172 */
4173 if (uProcCtls != pVCpu->hm.s.vmx.u32ProcCtls)
4174 {
4175 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
4176 AssertRCReturn(rc2, rc2);
4177 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
4178 }
4179
4180 /*
4181 * Update guest DR7.
4182 */
4183 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, u32GuestDr7);
4184 AssertRCReturn(rc, rc);
4185
4186 return VINF_SUCCESS;
4187}
4188
4189
4190#ifdef VBOX_STRICT
4191/**
4192 * Strict function to validate segment registers.
4193 *
4194 * @param pVCpu The cross context virtual CPU structure.
4195 *
4196 * @remarks Will import guest CR0 on strict builds during validation of
4197 * segments.
4198 */
4199static void hmR0VmxValidateSegmentRegs(PVMCPU pVCpu)
4200{
4201 /*
4202 * Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4203 *
4204 * The reason we check for attribute value 0 in this function and not just the unusable bit is
4205 * because hmR0VmxExportGuestSegmentReg() only updates the VMCS' copy of the value with the unusable bit
4206 * and doesn't change the guest-context value.
4207 */
4208 PVM pVM = pVCpu->CTX_SUFF(pVM);
4209 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4210 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0);
4211 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
4212 && ( !CPUMIsGuestInRealModeEx(pCtx)
4213 && !CPUMIsGuestInV86ModeEx(pCtx)))
4214 {
4215 /* Protected mode checks */
4216 /* CS */
4217 Assert(pCtx->cs.Attr.n.u1Present);
4218 Assert(!(pCtx->cs.Attr.u & 0xf00));
4219 Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
4220 Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
4221 || !(pCtx->cs.Attr.n.u1Granularity));
4222 Assert( !(pCtx->cs.u32Limit & 0xfff00000)
4223 || (pCtx->cs.Attr.n.u1Granularity));
4224 /* CS cannot be loaded with NULL in protected mode. */
4225 Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS? */
4226 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
4227 Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
4228 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
4229 Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
4230 else
4231 AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
4232 /* SS */
4233 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4234 Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
4235 if ( !(pCtx->cr0 & X86_CR0_PE)
4236 || pCtx->cs.Attr.n.u4Type == 3)
4237 {
4238 Assert(!pCtx->ss.Attr.n.u2Dpl);
4239 }
4240 if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
4241 {
4242 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4243 Assert(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7);
4244 Assert(pCtx->ss.Attr.n.u1Present);
4245 Assert(!(pCtx->ss.Attr.u & 0xf00));
4246 Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
4247 Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
4248 || !(pCtx->ss.Attr.n.u1Granularity));
4249 Assert( !(pCtx->ss.u32Limit & 0xfff00000)
4250 || (pCtx->ss.Attr.n.u1Granularity));
4251 }
4252 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSegmentReg(). */
4253 if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
4254 {
4255 Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4256 Assert(pCtx->ds.Attr.n.u1Present);
4257 Assert(pCtx->ds.Attr.n.u4Type > 11 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
4258 Assert(!(pCtx->ds.Attr.u & 0xf00));
4259 Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
4260 Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
4261 || !(pCtx->ds.Attr.n.u1Granularity));
4262 Assert( !(pCtx->ds.u32Limit & 0xfff00000)
4263 || (pCtx->ds.Attr.n.u1Granularity));
4264 Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4265 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
4266 }
4267 if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
4268 {
4269 Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4270 Assert(pCtx->es.Attr.n.u1Present);
4271 Assert(pCtx->es.Attr.n.u4Type > 11 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
4272 Assert(!(pCtx->es.Attr.u & 0xf00));
4273 Assert(!(pCtx->es.Attr.u & 0xfffe0000));
4274 Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
4275 || !(pCtx->es.Attr.n.u1Granularity));
4276 Assert( !(pCtx->es.u32Limit & 0xfff00000)
4277 || (pCtx->es.Attr.n.u1Granularity));
4278 Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4279 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
4280 }
4281 if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
4282 {
4283 Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4284 Assert(pCtx->fs.Attr.n.u1Present);
4285 Assert(pCtx->fs.Attr.n.u4Type > 11 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
4286 Assert(!(pCtx->fs.Attr.u & 0xf00));
4287 Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
4288 Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
4289 || !(pCtx->fs.Attr.n.u1Granularity));
4290 Assert( !(pCtx->fs.u32Limit & 0xfff00000)
4291 || (pCtx->fs.Attr.n.u1Granularity));
4292 Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4293 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4294 }
4295 if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
4296 {
4297 Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4298 Assert(pCtx->gs.Attr.n.u1Present);
4299 Assert(pCtx->gs.Attr.n.u4Type > 11 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
4300 Assert(!(pCtx->gs.Attr.u & 0xf00));
4301 Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
4302 Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
4303 || !(pCtx->gs.Attr.n.u1Granularity));
4304 Assert( !(pCtx->gs.u32Limit & 0xfff00000)
4305 || (pCtx->gs.Attr.n.u1Granularity));
4306 Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4307 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4308 }
4309 /* 64-bit capable CPUs. */
4310# if HC_ARCH_BITS == 64
4311 Assert(!RT_HI_U32(pCtx->cs.u64Base));
4312 Assert(!pCtx->ss.Attr.u || !RT_HI_U32(pCtx->ss.u64Base));
4313 Assert(!pCtx->ds.Attr.u || !RT_HI_U32(pCtx->ds.u64Base));
4314 Assert(!pCtx->es.Attr.u || !RT_HI_U32(pCtx->es.u64Base));
4315# endif
4316 }
4317 else if ( CPUMIsGuestInV86ModeEx(pCtx)
4318 || ( CPUMIsGuestInRealModeEx(pCtx)
4319 && !pVM->hm.s.vmx.fUnrestrictedGuest))
4320 {
4321 /* Real and v86 mode checks. */
4322 /* hmR0VmxExportGuestSegmentReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
4323 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
4324 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4325 {
4326 u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3; u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
4327 }
4328 else
4329 {
4330 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
4331 u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
4332 }
4333
4334 /* CS */
4335 AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
4336 Assert(pCtx->cs.u32Limit == 0xffff);
4337 Assert(u32CSAttr == 0xf3);
4338 /* SS */
4339 Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
4340 Assert(pCtx->ss.u32Limit == 0xffff);
4341 Assert(u32SSAttr == 0xf3);
4342 /* DS */
4343 Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
4344 Assert(pCtx->ds.u32Limit == 0xffff);
4345 Assert(u32DSAttr == 0xf3);
4346 /* ES */
4347 Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
4348 Assert(pCtx->es.u32Limit == 0xffff);
4349 Assert(u32ESAttr == 0xf3);
4350 /* FS */
4351 Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
4352 Assert(pCtx->fs.u32Limit == 0xffff);
4353 Assert(u32FSAttr == 0xf3);
4354 /* GS */
4355 Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
4356 Assert(pCtx->gs.u32Limit == 0xffff);
4357 Assert(u32GSAttr == 0xf3);
4358 /* 64-bit capable CPUs. */
4359# if HC_ARCH_BITS == 64
4360 Assert(!RT_HI_U32(pCtx->cs.u64Base));
4361 Assert(!u32SSAttr || !RT_HI_U32(pCtx->ss.u64Base));
4362 Assert(!u32DSAttr || !RT_HI_U32(pCtx->ds.u64Base));
4363 Assert(!u32ESAttr || !RT_HI_U32(pCtx->es.u64Base));
4364# endif
4365 }
4366}
4367#endif /* VBOX_STRICT */
4368
4369
4370/**
4371 * Exports a guest segment register into the guest-state area in the VMCS.
4372 *
4373 * @returns VBox status code.
4374 * @param pVCpu The cross context virtual CPU structure.
4375 * @param idxSel Index of the selector in the VMCS.
4376 * @param idxLimit Index of the segment limit in the VMCS.
4377 * @param idxBase Index of the segment base in the VMCS.
4378 * @param idxAccess Index of the access rights of the segment in the VMCS.
4379 * @param pSelReg Pointer to the segment selector.
4380 *
4381 * @remarks No-long-jump zone!!!
4382 */
4383static int hmR0VmxExportGuestSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
4384 PCCPUMSELREG pSelReg)
4385{
4386 int rc = VMXWriteVmcs32(idxSel, pSelReg->Sel); /* 16-bit guest selector field. */
4387 rc |= VMXWriteVmcs32(idxLimit, pSelReg->u32Limit); /* 32-bit guest segment limit field. */
4388 rc |= VMXWriteVmcsGstN(idxBase, pSelReg->u64Base); /* Natural width guest segment base field.*/
4389 AssertRCReturn(rc, rc);
4390
4391 uint32_t u32Access = pSelReg->Attr.u;
4392 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4393 {
4394 /* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
4395 u32Access = 0xf3;
4396 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
4397 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
4398 }
4399 else
4400 {
4401 /*
4402 * The way to differentiate between whether this is really a null selector or was just
4403 * a selector loaded with 0 in real-mode is using the segment attributes. A selector
4404 * loaded in real-mode with the value 0 is valid and usable in protected-mode and we
4405 * should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures
4406 * NULL selectors loaded in protected-mode have their attribute as 0.
4407 */
4408 if (!u32Access)
4409 u32Access = X86DESCATTR_UNUSABLE;
4410 }
4411
4412 /* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
4413 AssertMsg((u32Access & X86DESCATTR_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
4414 ("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
4415
4416 rc = VMXWriteVmcs32(idxAccess, u32Access); /* 32-bit guest segment access-rights field. */
4417 AssertRCReturn(rc, rc);
4418 return rc;
4419}
4420
4421
4422/**
4423 * Exports the guest segment registers, GDTR, IDTR, LDTR, (TR, FS and GS bases)
4424 * into the guest-state area in the VMCS.
4425 *
4426 * @returns VBox status code.
4427 * @param pVCpu The cross context virtual CPU structure.
4428 *
4429 * @remarks Will import guest CR0 on strict builds during validation of
4430 * segments.
4431 * @remarks No-long-jump zone!!!
4432 */
4433static int hmR0VmxExportGuestSegmentRegs(PVMCPU pVCpu)
4434{
4435 int rc = VERR_INTERNAL_ERROR_5;
4436 PVM pVM = pVCpu->CTX_SUFF(pVM);
4437 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4438
4439 /*
4440 * Guest Segment registers: CS, SS, DS, ES, FS, GS.
4441 */
4442 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SREG_MASK)
4443 {
4444#ifdef VBOX_WITH_REM
4445 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
4446 {
4447 Assert(pVM->hm.s.vmx.pRealModeTSS);
4448 AssertCompile(PGMMODE_REAL < PGMMODE_PROTECTED);
4449 if ( pVCpu->hm.s.vmx.fWasInRealMode
4450 && PGMGetGuestMode(pVCpu) >= PGMMODE_PROTECTED)
4451 {
4452 /* Signal that the recompiler must flush its code-cache as the guest -may- rewrite code it will later execute
4453 in real-mode (e.g. OpenBSD 4.0) */
4454 REMFlushTBs(pVM);
4455 Log4Func(("Switch to protected mode detected!\n"));
4456 pVCpu->hm.s.vmx.fWasInRealMode = false;
4457 }
4458 }
4459#endif
4460 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CS)
4461 {
4462 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
4463 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4464 pVCpu->hm.s.vmx.RealMode.AttrCS.u = pCtx->cs.Attr.u;
4465 rc = HMVMX_EXPORT_SREG(CS, &pCtx->cs);
4466 AssertRCReturn(rc, rc);
4467 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CS);
4468 }
4469
4470 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SS)
4471 {
4472 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
4473 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4474 pVCpu->hm.s.vmx.RealMode.AttrSS.u = pCtx->ss.Attr.u;
4475 rc = HMVMX_EXPORT_SREG(SS, &pCtx->ss);
4476 AssertRCReturn(rc, rc);
4477 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SS);
4478 }
4479
4480 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_DS)
4481 {
4482 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DS);
4483 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4484 pVCpu->hm.s.vmx.RealMode.AttrDS.u = pCtx->ds.Attr.u;
4485 rc = HMVMX_EXPORT_SREG(DS, &pCtx->ds);
4486 AssertRCReturn(rc, rc);
4487 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_DS);
4488 }
4489
4490 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_ES)
4491 {
4492 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_ES);
4493 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4494 pVCpu->hm.s.vmx.RealMode.AttrES.u = pCtx->es.Attr.u;
4495 rc = HMVMX_EXPORT_SREG(ES, &pCtx->es);
4496 AssertRCReturn(rc, rc);
4497 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_ES);
4498 }
4499
4500 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_FS)
4501 {
4502 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
4503 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4504 pVCpu->hm.s.vmx.RealMode.AttrFS.u = pCtx->fs.Attr.u;
4505 rc = HMVMX_EXPORT_SREG(FS, &pCtx->fs);
4506 AssertRCReturn(rc, rc);
4507 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_FS);
4508 }
4509
4510 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GS)
4511 {
4512 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
4513 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4514 pVCpu->hm.s.vmx.RealMode.AttrGS.u = pCtx->gs.Attr.u;
4515 rc = HMVMX_EXPORT_SREG(GS, &pCtx->gs);
4516 AssertRCReturn(rc, rc);
4517 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GS);
4518 }
4519
4520#ifdef VBOX_STRICT
4521 hmR0VmxValidateSegmentRegs(pVCpu);
4522#endif
4523
4524 Log4Func(("CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pCtx->cs.Sel, pCtx->cs.u64Base,
4525 pCtx->cs.u32Limit, pCtx->cs.Attr.u));
4526 }
4527
4528 /*
4529 * Guest TR.
4530 */
4531 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_TR)
4532 {
4533 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_TR);
4534
4535 /*
4536 * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is
4537 * achieved using the interrupt redirection bitmap (all bits cleared to let the guest
4538 * handle INT-n's) in the TSS. See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
4539 */
4540 uint16_t u16Sel = 0;
4541 uint32_t u32Limit = 0;
4542 uint64_t u64Base = 0;
4543 uint32_t u32AccessRights = 0;
4544
4545 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4546 {
4547 u16Sel = pCtx->tr.Sel;
4548 u32Limit = pCtx->tr.u32Limit;
4549 u64Base = pCtx->tr.u64Base;
4550 u32AccessRights = pCtx->tr.Attr.u;
4551 }
4552 else
4553 {
4554 Assert(pVM->hm.s.vmx.pRealModeTSS);
4555 Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMR3CanExecuteGuest() -XXX- what about inner loop changes? */
4556
4557 /* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
4558 RTGCPHYS GCPhys;
4559 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
4560 AssertRCReturn(rc, rc);
4561
4562 X86DESCATTR DescAttr;
4563 DescAttr.u = 0;
4564 DescAttr.n.u1Present = 1;
4565 DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
4566
4567 u16Sel = 0;
4568 u32Limit = HM_VTX_TSS_SIZE;
4569 u64Base = GCPhys; /* in real-mode phys = virt. */
4570 u32AccessRights = DescAttr.u;
4571 }
4572
4573 /* Validate. */
4574 Assert(!(u16Sel & RT_BIT(2)));
4575 AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
4576 || (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
4577 AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
4578 Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
4579 Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
4580 Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
4581 Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
4582 Assert( (u32Limit & 0xfff) == 0xfff
4583 || !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
4584 Assert( !(pCtx->tr.u32Limit & 0xfff00000)
4585 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
4586
4587 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_TR_SEL, u16Sel);
4588 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit);
4589 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);
4590 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE, u64Base);
4591 AssertRCReturn(rc, rc);
4592
4593 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_TR);
4594 Log4Func(("TR base=%#RX64\n", pCtx->tr.u64Base));
4595 }
4596
4597 /*
4598 * Guest GDTR.
4599 */
4600 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GDTR)
4601 {
4602 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GDTR);
4603
4604 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
4605 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
4606 AssertRCReturn(rc, rc);
4607
4608 /* Validate. */
4609 Assert(!(pCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4610
4611 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GDTR);
4612 Log4Func(("GDTR base=%#RX64\n", pCtx->gdtr.pGdt));
4613 }
4614
4615 /*
4616 * Guest LDTR.
4617 */
4618 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_LDTR)
4619 {
4620 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_LDTR);
4621
4622 /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
4623 uint32_t u32Access = 0;
4624 if (!pCtx->ldtr.Attr.u)
4625 u32Access = X86DESCATTR_UNUSABLE;
4626 else
4627 u32Access = pCtx->ldtr.Attr.u;
4628
4629 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel);
4630 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit);
4631 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);
4632 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base);
4633 AssertRCReturn(rc, rc);
4634
4635 /* Validate. */
4636 if (!(u32Access & X86DESCATTR_UNUSABLE))
4637 {
4638 Assert(!(pCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
4639 Assert(pCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
4640 Assert(!pCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
4641 Assert(pCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
4642 Assert(!pCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
4643 Assert(!(pCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
4644 Assert( (pCtx->ldtr.u32Limit & 0xfff) == 0xfff
4645 || !pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
4646 Assert( !(pCtx->ldtr.u32Limit & 0xfff00000)
4647 || pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
4648 }
4649
4650 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_LDTR);
4651 Log4Func(("LDTR base=%#RX64\n", pCtx->ldtr.u64Base));
4652 }
4653
4654 /*
4655 * Guest IDTR.
4656 */
4657 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_IDTR)
4658 {
4659 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_IDTR);
4660
4661 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
4662 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
4663 AssertRCReturn(rc, rc);
4664
4665 /* Validate. */
4666 Assert(!(pCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4667
4668 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_IDTR);
4669 Log4Func(("IDTR base=%#RX64\n", pCtx->idtr.pIdt));
4670 }
4671
4672 return VINF_SUCCESS;
4673}
4674
4675
4676/**
4677 * Exports certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
4678 * areas.
4679 *
4680 * These MSRs will automatically be loaded to the host CPU on every successful
4681 * VM-entry and stored from the host CPU on every successful VM-exit. This also
4682 * creates/updates MSR slots for the host MSRs. The actual host MSR values are
4683 * -not- updated here for performance reasons. See hmR0VmxExportHostMsrs().
4684 *
4685 * Also exports the guest sysenter MSRs into the guest-state area in the VMCS.
4686 *
4687 * @returns VBox status code.
4688 * @param pVCpu The cross context virtual CPU structure.
4689 *
4690 * @remarks No-long-jump zone!!!
4691 */
4692static int hmR0VmxExportGuestMsrs(PVMCPU pVCpu)
4693{
4694 AssertPtr(pVCpu);
4695 AssertPtr(pVCpu->hm.s.vmx.pvGuestMsr);
4696
4697 /*
4698 * MSRs that we use the auto-load/store MSR area in the VMCS.
4699 * For 64-bit hosts, we load/restore them lazily, see hmR0VmxLazyLoadGuestMsrs().
4700 */
4701 PVM pVM = pVCpu->CTX_SUFF(pVM);
4702 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4703 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_GUEST_AUTO_MSRS)
4704 {
4705 if (pVM->hm.s.fAllow64BitGuests)
4706 {
4707#if HC_ARCH_BITS == 32
4708 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS | CPUMCTX_EXTRN_KERNEL_GS_BASE);
4709
4710 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_LSTAR, pCtx->msrLSTAR, false, NULL);
4711 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_STAR, pCtx->msrSTAR, false, NULL);
4712 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_SF_MASK, pCtx->msrSFMASK, false, NULL);
4713 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE, false, NULL);
4714 AssertRCReturn(rc, rc);
4715# ifdef LOG_ENABLED
4716 PCVMXAUTOMSR pMsr = (PCVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
4717 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cMsrs; i++, pMsr++)
4718 Log4Func(("MSR[%RU32]: u32Msr=%#RX32 u64Value=%#RX64\n", i, pMsr->u32Msr, pMsr->u64Value));
4719# endif
4720#endif
4721 }
4722 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_GUEST_AUTO_MSRS);
4723 }
4724
4725 /*
4726 * Guest Sysenter MSRs.
4727 * These flags are only set when MSR-bitmaps are not supported by the CPU and we cause
4728 * VM-exits on WRMSRs for these MSRs.
4729 */
4730 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
4731 {
4732 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4733
4734 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
4735 {
4736 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
4737 AssertRCReturn(rc, rc);
4738 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_CS_MSR);
4739 }
4740
4741 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
4742 {
4743 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
4744 AssertRCReturn(rc, rc);
4745 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
4746 }
4747
4748 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
4749 {
4750 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
4751 AssertRCReturn(rc, rc);
4752 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
4753 }
4754 }
4755
4756 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_EFER_MSR)
4757 {
4758 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
4759
4760 if (hmR0VmxShouldSwapEferMsr(pVCpu))
4761 {
4762 /*
4763 * If the CPU supports VMCS controls for swapping EFER, use it. Otherwise, we have no option
4764 * but to use the auto-load store MSR area in the VMCS for swapping EFER. See @bugref{7368}.
4765 */
4766 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
4767 {
4768 int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, pCtx->msrEFER);
4769 AssertRCReturn(rc,rc);
4770 Log4Func(("EFER=%#RX64\n", pCtx->msrEFER));
4771 }
4772 else
4773 {
4774 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_EFER, pCtx->msrEFER, false /* fUpdateHostMsr */,
4775 NULL /* pfAddedAndUpdated */);
4776 AssertRCReturn(rc, rc);
4777
4778 /* We need to intercept reads too, see @bugref{7386#c16}. */
4779 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
4780 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
4781 Log4Func(("MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", MSR_K6_EFER, pCtx->msrEFER,
4782 pVCpu->hm.s.vmx.cMsrs));
4783 }
4784 }
4785 else if (!pVM->hm.s.vmx.fSupportsVmcsEfer)
4786 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K6_EFER);
4787 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_EFER_MSR);
4788 }
4789
4790 return VINF_SUCCESS;
4791}
4792
4793
4794#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
4795/**
4796 * Check if guest state allows safe use of 32-bit switcher again.
4797 *
4798 * Segment bases and protected mode structures must be 32-bit addressable
4799 * because the 32-bit switcher will ignore high dword when writing these VMCS
4800 * fields. See @bugref{8432} for details.
4801 *
4802 * @returns true if safe, false if must continue to use the 64-bit switcher.
4803 * @param pCtx Pointer to the guest-CPU context.
4804 *
4805 * @remarks No-long-jump zone!!!
4806 */
4807static bool hmR0VmxIs32BitSwitcherSafe(PCCPUMCTX pCtx)
4808{
4809 if (pCtx->gdtr.pGdt & UINT64_C(0xffffffff00000000)) return false;
4810 if (pCtx->idtr.pIdt & UINT64_C(0xffffffff00000000)) return false;
4811 if (pCtx->ldtr.u64Base & UINT64_C(0xffffffff00000000)) return false;
4812 if (pCtx->tr.u64Base & UINT64_C(0xffffffff00000000)) return false;
4813 if (pCtx->es.u64Base & UINT64_C(0xffffffff00000000)) return false;
4814 if (pCtx->cs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4815 if (pCtx->ss.u64Base & UINT64_C(0xffffffff00000000)) return false;
4816 if (pCtx->ds.u64Base & UINT64_C(0xffffffff00000000)) return false;
4817 if (pCtx->fs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4818 if (pCtx->gs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4819
4820 /* All good, bases are 32-bit. */
4821 return true;
4822}
4823#endif
4824
4825
4826/**
4827 * Selects up the appropriate function to run guest code.
4828 *
4829 * @returns VBox status code.
4830 * @param pVCpu The cross context virtual CPU structure.
4831 *
4832 * @remarks No-long-jump zone!!!
4833 */
4834static int hmR0VmxSelectVMRunHandler(PVMCPU pVCpu)
4835{
4836 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4837 if (CPUMIsGuestInLongModeEx(pCtx))
4838 {
4839#ifndef VBOX_ENABLE_64_BITS_GUESTS
4840 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4841#endif
4842 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
4843#if HC_ARCH_BITS == 32
4844 /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
4845 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
4846 {
4847#ifdef VBOX_STRICT
4848 if (pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4849 {
4850 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4851 uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
4852 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4853 AssertMsg(fCtxChanged & ( HM_CHANGED_VMX_EXIT_CTLS
4854 | HM_CHANGED_VMX_ENTRY_CTLS
4855 | HM_CHANGED_GUEST_EFER_MSR), ("fCtxChanged=%#RX64\n", fCtxChanged));
4856 }
4857#endif
4858 pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
4859
4860 /* Mark that we've switched to 64-bit handler, we can't safely switch back to 32-bit for
4861 the rest of the VM run (until VM reset). See @bugref{8432#c7}. */
4862 pVCpu->hm.s.vmx.fSwitchedTo64on32 = true;
4863 Log4Func(("Selected 64-bit switcher\n"));
4864 }
4865#else
4866 /* 64-bit host. */
4867 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM64;
4868#endif
4869 }
4870 else
4871 {
4872 /* Guest is not in long mode, use the 32-bit handler. */
4873#if HC_ARCH_BITS == 32
4874 if ( pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32
4875 && !pVCpu->hm.s.vmx.fSwitchedTo64on32 /* If set, guest mode change does not imply switcher change. */
4876 && pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4877 {
4878# ifdef VBOX_STRICT
4879 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4880 uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
4881 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4882 AssertMsg(fCtxChanged & ( HM_CHANGED_VMX_EXIT_CTLS
4883 | HM_CHANGED_VMX_ENTRY_CTLS
4884 | HM_CHANGED_GUEST_EFER_MSR), ("fCtxChanged=%#RX64\n", fCtxChanged));
4885# endif
4886 }
4887# ifdef VBOX_ENABLE_64_BITS_GUESTS
4888 /*
4889 * Keep using the 64-bit switcher even though we're in 32-bit because of bad Intel
4890 * design, see @bugref{8432#c7}. If real-on-v86 mode is active, clear the 64-bit
4891 * switcher flag because now we know the guest is in a sane state where it's safe
4892 * to use the 32-bit switcher. Otherwise check the guest state if it's safe to use
4893 * the much faster 32-bit switcher again.
4894 */
4895 if (!pVCpu->hm.s.vmx.fSwitchedTo64on32)
4896 {
4897 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32)
4898 Log4Func(("Selected 32-bit switcher\n"));
4899 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4900 }
4901 else
4902 {
4903 Assert(pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64);
4904 if ( pVCpu->hm.s.vmx.RealMode.fRealOnV86Active
4905 || hmR0VmxIs32BitSwitcherSafe(pCtx))
4906 {
4907 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
4908 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4909 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR
4910 | HM_CHANGED_VMX_ENTRY_CTLS
4911 | HM_CHANGED_VMX_EXIT_CTLS
4912 | HM_CHANGED_HOST_CONTEXT);
4913 Log4Func(("Selected 32-bit switcher (safe)\n"));
4914 }
4915 }
4916# else
4917 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4918# endif
4919#else
4920 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4921#endif
4922 }
4923 Assert(pVCpu->hm.s.vmx.pfnStartVM);
4924 return VINF_SUCCESS;
4925}
4926
4927
4928/**
4929 * Wrapper for running the guest code in VT-x.
4930 *
4931 * @returns VBox status code, no informational status codes.
4932 * @param pVCpu The cross context virtual CPU structure.
4933 *
4934 * @remarks No-long-jump zone!!!
4935 */
4936DECLINLINE(int) hmR0VmxRunGuest(PVMCPU pVCpu)
4937{
4938 /* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4939 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4940 pCtx->fExtrn |= HMVMX_CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_HM;
4941
4942 /*
4943 * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4944 * floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4945 * callee-saved and thus the need for this XMM wrapper.
4946 *
4947 * See MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4948 */
4949 bool const fResumeVM = RT_BOOL(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
4950 /** @todo Add stats for resume vs launch. */
4951 PVM pVM = pVCpu->CTX_SUFF(pVM);
4952#ifdef VBOX_WITH_KERNEL_USING_XMM
4953 int rc = hmR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
4954#else
4955 int rc = pVCpu->hm.s.vmx.pfnStartVM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu);
4956#endif
4957 AssertMsg(rc <= VINF_SUCCESS, ("%Rrc\n", rc));
4958 return rc;
4959}
4960
4961
4962/**
4963 * Reports world-switch error and dumps some useful debug info.
4964 *
4965 * @param pVCpu The cross context virtual CPU structure.
4966 * @param rcVMRun The return code from VMLAUNCH/VMRESUME.
4967 * @param pVmxTransient Pointer to the VMX transient structure (only
4968 * exitReason updated).
4969 */
4970static void hmR0VmxReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun, PVMXTRANSIENT pVmxTransient)
4971{
4972 Assert(pVCpu);
4973 Assert(pVmxTransient);
4974 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
4975
4976 Log4Func(("VM-entry failure: %Rrc\n", rcVMRun));
4977 switch (rcVMRun)
4978 {
4979 case VERR_VMX_INVALID_VMXON_PTR:
4980 AssertFailed();
4981 break;
4982 case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
4983 case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
4984 {
4985 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
4986 rc |= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
4987 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
4988 AssertRC(rc);
4989
4990 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
4991 /* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
4992 Cannot do it here as we may have been long preempted. */
4993
4994#ifdef VBOX_STRICT
4995 Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
4996 pVmxTransient->uExitReason));
4997 Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQual));
4998 Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
4999 if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
5000 Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
5001 else
5002 Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
5003 Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
5004 Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
5005
5006 /* VMX control bits. */
5007 uint32_t u32Val;
5008 uint64_t u64Val;
5009 RTHCUINTREG uHCReg;
5010 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc);
5011 Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val));
5012 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc);
5013 Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val));
5014 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5015 {
5016 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);
5017 Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val));
5018 }
5019 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);
5020 Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val));
5021 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);
5022 Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val));
5023 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc);
5024 Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val));
5025 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc);
5026 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val));
5027 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc);
5028 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val));
5029 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc);
5030 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val));
5031 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc);
5032 Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val));
5033 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc);
5034 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val));
5035 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5036 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val));
5037 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5038 Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val));
5039 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc);
5040 Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val));
5041 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc);
5042 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val));
5043 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc);
5044 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val));
5045 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
5046 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
5047 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
5048 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5049 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
5050 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
5051 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
5052 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5053 if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
5054 {
5055 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
5056 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
5057 }
5058
5059 /* Guest bits. */
5060 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);
5061 Log4(("Old Guest Rip %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rip, u64Val));
5062 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);
5063 Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rsp, u64Val));
5064 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);
5065 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pVCpu->cpum.GstCtx.eflags.u32, u32Val));
5066 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid)
5067 {
5068 rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val); AssertRC(rc);
5069 Log4(("VMX_VMCS16_VPID %u\n", u32Val));
5070 }
5071
5072 /* Host bits. */
5073 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);
5074 Log4(("Host CR0 %#RHr\n", uHCReg));
5075 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);
5076 Log4(("Host CR3 %#RHr\n", uHCReg));
5077 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);
5078 Log4(("Host CR4 %#RHr\n", uHCReg));
5079
5080 RTGDTR HostGdtr;
5081 PCX86DESCHC pDesc;
5082 ASMGetGDTR(&HostGdtr);
5083 rc = VMXReadVmcs32(VMX_VMCS16_HOST_CS_SEL, &u32Val); AssertRC(rc);
5084 Log4(("Host CS %#08x\n", u32Val));
5085 if (u32Val < HostGdtr.cbGdt)
5086 {
5087 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5088 hmR0DumpDescriptor(pDesc, u32Val, "CS: ");
5089 }
5090
5091 rc = VMXReadVmcs32(VMX_VMCS16_HOST_DS_SEL, &u32Val); AssertRC(rc);
5092 Log4(("Host DS %#08x\n", u32Val));
5093 if (u32Val < HostGdtr.cbGdt)
5094 {
5095 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5096 hmR0DumpDescriptor(pDesc, u32Val, "DS: ");
5097 }
5098
5099 rc = VMXReadVmcs32(VMX_VMCS16_HOST_ES_SEL, &u32Val); AssertRC(rc);
5100 Log4(("Host ES %#08x\n", u32Val));
5101 if (u32Val < HostGdtr.cbGdt)
5102 {
5103 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5104 hmR0DumpDescriptor(pDesc, u32Val, "ES: ");
5105 }
5106
5107 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FS_SEL, &u32Val); AssertRC(rc);
5108 Log4(("Host FS %#08x\n", u32Val));
5109 if (u32Val < HostGdtr.cbGdt)
5110 {
5111 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5112 hmR0DumpDescriptor(pDesc, u32Val, "FS: ");
5113 }
5114
5115 rc = VMXReadVmcs32(VMX_VMCS16_HOST_GS_SEL, &u32Val); AssertRC(rc);
5116 Log4(("Host GS %#08x\n", u32Val));
5117 if (u32Val < HostGdtr.cbGdt)
5118 {
5119 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5120 hmR0DumpDescriptor(pDesc, u32Val, "GS: ");
5121 }
5122
5123 rc = VMXReadVmcs32(VMX_VMCS16_HOST_SS_SEL, &u32Val); AssertRC(rc);
5124 Log4(("Host SS %#08x\n", u32Val));
5125 if (u32Val < HostGdtr.cbGdt)
5126 {
5127 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5128 hmR0DumpDescriptor(pDesc, u32Val, "SS: ");
5129 }
5130
5131 rc = VMXReadVmcs32(VMX_VMCS16_HOST_TR_SEL, &u32Val); AssertRC(rc);
5132 Log4(("Host TR %#08x\n", u32Val));
5133 if (u32Val < HostGdtr.cbGdt)
5134 {
5135 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5136 hmR0DumpDescriptor(pDesc, u32Val, "TR: ");
5137 }
5138
5139 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);
5140 Log4(("Host TR Base %#RHv\n", uHCReg));
5141 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);
5142 Log4(("Host GDTR Base %#RHv\n", uHCReg));
5143 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);
5144 Log4(("Host IDTR Base %#RHv\n", uHCReg));
5145 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);
5146 Log4(("Host SYSENTER CS %#08x\n", u32Val));
5147 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);
5148 Log4(("Host SYSENTER EIP %#RHv\n", uHCReg));
5149 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);
5150 Log4(("Host SYSENTER ESP %#RHv\n", uHCReg));
5151 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);
5152 Log4(("Host RSP %#RHv\n", uHCReg));
5153 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);
5154 Log4(("Host RIP %#RHv\n", uHCReg));
5155# if HC_ARCH_BITS == 64
5156 Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
5157 Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
5158 Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
5159 Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
5160 Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
5161 Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
5162# endif
5163#endif /* VBOX_STRICT */
5164 break;
5165 }
5166
5167 default:
5168 /* Impossible */
5169 AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
5170 break;
5171 }
5172}
5173
5174
5175#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
5176#ifndef VMX_USE_CACHED_VMCS_ACCESSES
5177# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
5178#endif
5179#ifdef VBOX_STRICT
5180static bool hmR0VmxIsValidWriteField(uint32_t idxField)
5181{
5182 switch (idxField)
5183 {
5184 case VMX_VMCS_GUEST_RIP:
5185 case VMX_VMCS_GUEST_RSP:
5186 case VMX_VMCS_GUEST_SYSENTER_EIP:
5187 case VMX_VMCS_GUEST_SYSENTER_ESP:
5188 case VMX_VMCS_GUEST_GDTR_BASE:
5189 case VMX_VMCS_GUEST_IDTR_BASE:
5190 case VMX_VMCS_GUEST_CS_BASE:
5191 case VMX_VMCS_GUEST_DS_BASE:
5192 case VMX_VMCS_GUEST_ES_BASE:
5193 case VMX_VMCS_GUEST_FS_BASE:
5194 case VMX_VMCS_GUEST_GS_BASE:
5195 case VMX_VMCS_GUEST_SS_BASE:
5196 case VMX_VMCS_GUEST_LDTR_BASE:
5197 case VMX_VMCS_GUEST_TR_BASE:
5198 case VMX_VMCS_GUEST_CR3:
5199 return true;
5200 }
5201 return false;
5202}
5203
5204static bool hmR0VmxIsValidReadField(uint32_t idxField)
5205{
5206 switch (idxField)
5207 {
5208 /* Read-only fields. */
5209 case VMX_VMCS_RO_EXIT_QUALIFICATION:
5210 return true;
5211 }
5212 /* Remaining readable fields should also be writable. */
5213 return hmR0VmxIsValidWriteField(idxField);
5214}
5215#endif /* VBOX_STRICT */
5216
5217
5218/**
5219 * Executes the specified handler in 64-bit mode.
5220 *
5221 * @returns VBox status code (no informational status codes).
5222 * @param pVCpu The cross context virtual CPU structure.
5223 * @param enmOp The operation to perform.
5224 * @param cParams Number of parameters.
5225 * @param paParam Array of 32-bit parameters.
5226 */
5227VMMR0DECL(int) VMXR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
5228{
5229 PVM pVM = pVCpu->CTX_SUFF(pVM);
5230 AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
5231 Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
5232 Assert(pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Write.aField));
5233 Assert(pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Read.aField));
5234
5235#ifdef VBOX_STRICT
5236 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries; i++)
5237 Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VMCSCache.Write.aField[i]));
5238
5239 for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries; i++)
5240 Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VMCSCache.Read.aField[i]));
5241#endif
5242
5243 /* Disable interrupts. */
5244 RTCCUINTREG fOldEFlags = ASMIntDisableFlags();
5245
5246#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
5247 RTCPUID idHostCpu = RTMpCpuId();
5248 CPUMR0SetLApic(pVCpu, idHostCpu);
5249#endif
5250
5251 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5252 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5253
5254 /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
5255 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5256 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
5257
5258 /* Leave VMX Root Mode. */
5259 VMXDisable();
5260
5261 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5262
5263 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
5264 CPUMSetHyperEIP(pVCpu, enmOp);
5265 for (int i = (int)cParams - 1; i >= 0; i--)
5266 CPUMPushHyper(pVCpu, paParam[i]);
5267
5268 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
5269
5270 /* Call the switcher. */
5271 int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
5272 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
5273
5274 /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
5275 /* Make sure the VMX instructions don't cause #UD faults. */
5276 SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
5277
5278 /* Re-enter VMX Root Mode */
5279 int rc2 = VMXEnable(HCPhysCpuPage);
5280 if (RT_FAILURE(rc2))
5281 {
5282 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5283 ASMSetFlags(fOldEFlags);
5284 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
5285 return rc2;
5286 }
5287
5288 rc2 = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5289 AssertRC(rc2);
5290 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
5291 Assert(!(ASMGetFlags() & X86_EFL_IF));
5292 ASMSetFlags(fOldEFlags);
5293 return rc;
5294}
5295
5296
5297/**
5298 * Prepares for and executes VMLAUNCH (64-bit guests) for 32-bit hosts
5299 * supporting 64-bit guests.
5300 *
5301 * @returns VBox status code.
5302 * @param fResume Whether to VMLAUNCH or VMRESUME.
5303 * @param pCtx Pointer to the guest-CPU context.
5304 * @param pCache Pointer to the VMCS cache.
5305 * @param pVM The cross context VM structure.
5306 * @param pVCpu The cross context virtual CPU structure.
5307 */
5308DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
5309{
5310 NOREF(fResume);
5311
5312 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5313 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5314
5315#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5316 pCache->uPos = 1;
5317 pCache->interPD = PGMGetInterPaeCR3(pVM);
5318 pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
5319#endif
5320
5321#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5322 pCache->TestIn.HCPhysCpuPage = 0;
5323 pCache->TestIn.HCPhysVmcs = 0;
5324 pCache->TestIn.pCache = 0;
5325 pCache->TestOut.HCPhysVmcs = 0;
5326 pCache->TestOut.pCache = 0;
5327 pCache->TestOut.pCtx = 0;
5328 pCache->TestOut.eflags = 0;
5329#else
5330 NOREF(pCache);
5331#endif
5332
5333 uint32_t aParam[10];
5334 aParam[0] = RT_LO_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
5335 aParam[1] = RT_HI_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Hi. */
5336 aParam[2] = RT_LO_U32(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
5337 aParam[3] = RT_HI_U32(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Hi. */
5338 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
5339 aParam[5] = 0;
5340 aParam[6] = VM_RC_ADDR(pVM, pVM);
5341 aParam[7] = 0;
5342 aParam[8] = VM_RC_ADDR(pVM, pVCpu);
5343 aParam[9] = 0;
5344
5345#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5346 pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
5347 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
5348#endif
5349 int rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_VMXRCStartVM64, RT_ELEMENTS(aParam), &aParam[0]);
5350
5351#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5352 Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
5353 Assert(pCtx->dr[4] == 10);
5354 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
5355#endif
5356
5357#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5358 AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
5359 AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5360 pVCpu->hm.s.vmx.HCPhysVmcs));
5361 AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5362 pCache->TestOut.HCPhysVmcs));
5363 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
5364 pCache->TestOut.pCache));
5365 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
5366 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
5367 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
5368 pCache->TestOut.pCtx));
5369 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
5370#endif
5371 NOREF(pCtx);
5372 return rc;
5373}
5374
5375
5376/**
5377 * Initialize the VMCS-Read cache.
5378 *
5379 * The VMCS cache is used for 32-bit hosts running 64-bit guests (except 32-bit
5380 * Darwin which runs with 64-bit paging in 32-bit mode) for 64-bit fields that
5381 * cannot be accessed in 32-bit mode. Some 64-bit fields -can- be accessed
5382 * (those that have a 32-bit FULL & HIGH part).
5383 *
5384 * @returns VBox status code.
5385 * @param pVCpu The cross context virtual CPU structure.
5386 */
5387static int hmR0VmxInitVmcsReadCache(PVMCPU pVCpu)
5388{
5389#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \
5390 do { \
5391 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
5392 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
5393 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
5394 ++cReadFields; \
5395 } while (0)
5396
5397 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5398 uint32_t cReadFields = 0;
5399
5400 /*
5401 * Don't remove the #if 0'd fields in this code. They're listed here for consistency
5402 * and serve to indicate exceptions to the rules.
5403 */
5404
5405 /* Guest-natural selector base fields. */
5406#if 0
5407 /* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */
5408 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR0);
5409 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR4);
5410#endif
5411 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_ES_BASE);
5412 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CS_BASE);
5413 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SS_BASE);
5414 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DS_BASE);
5415 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_FS_BASE);
5416 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GS_BASE);
5417 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_LDTR_BASE);
5418 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_TR_BASE);
5419 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
5420 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
5421 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
5422 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
5423#if 0
5424 /* Unused natural width guest-state fields. */
5425 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS);
5426 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3); /* Handled in Nested Paging case */
5427#endif
5428 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
5429 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
5430
5431 /* 64-bit guest-state fields; unused as we use two 32-bit VMREADs for
5432 these 64-bit fields (using "FULL" and "HIGH" fields). */
5433#if 0
5434 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL);
5435 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_DEBUGCTL_FULL);
5436 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PAT_FULL);
5437 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_EFER_FULL);
5438 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL);
5439 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE0_FULL);
5440 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE1_FULL);
5441 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE2_FULL);
5442 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE3_FULL);
5443#endif
5444
5445 /* Natural width guest-state fields. */
5446 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
5447#if 0
5448 /* Currently unused field. */
5449 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR);
5450#endif
5451
5452 if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
5453 {
5454 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
5455 AssertMsg(cReadFields == VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields,
5456 VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX));
5457 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
5458 }
5459 else
5460 {
5461 AssertMsg(cReadFields == VMX_VMCS_MAX_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields, VMX_VMCS_MAX_CACHE_IDX));
5462 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
5463 }
5464
5465#undef VMXLOCAL_INIT_READ_CACHE_FIELD
5466 return VINF_SUCCESS;
5467}
5468
5469
5470/**
5471 * Writes a field into the VMCS. This can either directly invoke a VMWRITE or
5472 * queue up the VMWRITE by using the VMCS write cache (on 32-bit hosts, except
5473 * darwin, running 64-bit guests).
5474 *
5475 * @returns VBox status code.
5476 * @param pVCpu The cross context virtual CPU structure.
5477 * @param idxField The VMCS field encoding.
5478 * @param u64Val 16, 32 or 64-bit value.
5479 */
5480VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5481{
5482 int rc;
5483 switch (idxField)
5484 {
5485 /*
5486 * These fields consists of a "FULL" and a "HIGH" part which can be written to individually.
5487 */
5488 /* 64-bit Control fields. */
5489 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
5490 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
5491 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
5492 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
5493 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
5494 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
5495 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
5496 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
5497 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
5498 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
5499 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
5500 case VMX_VMCS64_CTRL_EPTP_FULL:
5501 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
5502 /* 64-bit Guest-state fields. */
5503 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
5504 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
5505 case VMX_VMCS64_GUEST_PAT_FULL:
5506 case VMX_VMCS64_GUEST_EFER_FULL:
5507 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
5508 case VMX_VMCS64_GUEST_PDPTE0_FULL:
5509 case VMX_VMCS64_GUEST_PDPTE1_FULL:
5510 case VMX_VMCS64_GUEST_PDPTE2_FULL:
5511 case VMX_VMCS64_GUEST_PDPTE3_FULL:
5512 /* 64-bit Host-state fields. */
5513 case VMX_VMCS64_HOST_PAT_FULL:
5514 case VMX_VMCS64_HOST_EFER_FULL:
5515 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
5516 {
5517 rc = VMXWriteVmcs32(idxField, RT_LO_U32(u64Val));
5518 rc |= VMXWriteVmcs32(idxField + 1, RT_HI_U32(u64Val));
5519 break;
5520 }
5521
5522 /*
5523 * These fields do not have high and low parts. Queue up the VMWRITE by using the VMCS write-cache (for 64-bit
5524 * values). When we switch the host to 64-bit mode for running 64-bit guests, these VMWRITEs get executed then.
5525 */
5526 /* Natural-width Guest-state fields. */
5527 case VMX_VMCS_GUEST_CR3:
5528 case VMX_VMCS_GUEST_ES_BASE:
5529 case VMX_VMCS_GUEST_CS_BASE:
5530 case VMX_VMCS_GUEST_SS_BASE:
5531 case VMX_VMCS_GUEST_DS_BASE:
5532 case VMX_VMCS_GUEST_FS_BASE:
5533 case VMX_VMCS_GUEST_GS_BASE:
5534 case VMX_VMCS_GUEST_LDTR_BASE:
5535 case VMX_VMCS_GUEST_TR_BASE:
5536 case VMX_VMCS_GUEST_GDTR_BASE:
5537 case VMX_VMCS_GUEST_IDTR_BASE:
5538 case VMX_VMCS_GUEST_RSP:
5539 case VMX_VMCS_GUEST_RIP:
5540 case VMX_VMCS_GUEST_SYSENTER_ESP:
5541 case VMX_VMCS_GUEST_SYSENTER_EIP:
5542 {
5543 if (!(RT_HI_U32(u64Val)))
5544 {
5545 /* If this field is 64-bit, VT-x will zero out the top bits. */
5546 rc = VMXWriteVmcs32(idxField, RT_LO_U32(u64Val));
5547 }
5548 else
5549 {
5550 /* Assert that only the 32->64 switcher case should ever come here. */
5551 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests);
5552 rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
5553 }
5554 break;
5555 }
5556
5557 default:
5558 {
5559 AssertMsgFailed(("VMXWriteVmcs64Ex: Invalid field %#RX32 (pVCpu=%p u64Val=%#RX64)\n", idxField, pVCpu, u64Val));
5560 rc = VERR_INVALID_PARAMETER;
5561 break;
5562 }
5563 }
5564 AssertRCReturn(rc, rc);
5565 return rc;
5566}
5567
5568
5569/**
5570 * Queue up a VMWRITE by using the VMCS write cache.
5571 * This is only used on 32-bit hosts (except darwin) for 64-bit guests.
5572 *
5573 * @param pVCpu The cross context virtual CPU structure.
5574 * @param idxField The VMCS field encoding.
5575 * @param u64Val 16, 32 or 64-bit value.
5576 */
5577VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5578{
5579 AssertPtr(pVCpu);
5580 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5581
5582 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
5583 ("entries=%u\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
5584
5585 /* Make sure there are no duplicates. */
5586 for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
5587 {
5588 if (pCache->Write.aField[i] == idxField)
5589 {
5590 pCache->Write.aFieldVal[i] = u64Val;
5591 return VINF_SUCCESS;
5592 }
5593 }
5594
5595 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
5596 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
5597 pCache->Write.cValidEntries++;
5598 return VINF_SUCCESS;
5599}
5600#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
5601
5602
5603/**
5604 * Sets up the usage of TSC-offsetting and updates the VMCS.
5605 *
5606 * If offsetting is not possible, cause VM-exits on RDTSC(P)s. Also sets up the
5607 * VMX preemption timer.
5608 *
5609 * @returns VBox status code.
5610 * @param pVCpu The cross context virtual CPU structure.
5611 *
5612 * @remarks No-long-jump zone!!!
5613 */
5614static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVMCPU pVCpu)
5615{
5616 bool fOffsettedTsc;
5617 bool fParavirtTsc;
5618 PVM pVM = pVCpu->CTX_SUFF(pVM);
5619 uint64_t uTscOffset;
5620 if (pVM->hm.s.vmx.fUsePreemptTimer)
5621 {
5622 uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &uTscOffset, &fOffsettedTsc, &fParavirtTsc);
5623
5624 /* Make sure the returned values have sane upper and lower boundaries. */
5625 uint64_t u64CpuHz = SUPGetCpuHzFromGipBySetIndex(g_pSUPGlobalInfoPage, pVCpu->iHostCpuSet);
5626 cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second */
5627 cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
5628 cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
5629
5630 uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
5631 int rc = VMXWriteVmcs32(VMX_VMCS32_PREEMPT_TIMER_VALUE, cPreemptionTickCount);
5632 AssertRC(rc);
5633 }
5634 else
5635 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
5636
5637 if (fParavirtTsc)
5638 {
5639 /* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
5640 information before every VM-entry, hence disable it for performance sake. */
5641#if 0
5642 int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
5643 AssertRC(rc);
5644#endif
5645 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
5646 }
5647
5648 uint32_t uProcCtls = pVCpu->hm.s.vmx.u32ProcCtls;
5649 if ( fOffsettedTsc
5650 && RT_LIKELY(!pVCpu->hm.s.fDebugWantRdTscExit))
5651 {
5652 if (pVCpu->hm.s.vmx.u64TscOffset != uTscOffset)
5653 {
5654 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, uTscOffset);
5655 AssertRC(rc);
5656 pVCpu->hm.s.vmx.u64TscOffset = uTscOffset;
5657 }
5658
5659 if (uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT)
5660 {
5661 uProcCtls &= ~VMX_PROC_CTLS_RDTSC_EXIT;
5662 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
5663 AssertRC(rc);
5664 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
5665 }
5666 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
5667 }
5668 else
5669 {
5670 /* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
5671 if (!(uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
5672 {
5673 uProcCtls |= VMX_PROC_CTLS_RDTSC_EXIT;
5674 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
5675 AssertRC(rc);
5676 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
5677 }
5678 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
5679 }
5680}
5681
5682
5683/**
5684 * Gets the IEM exception flags for the specified vector and IDT vectoring /
5685 * VM-exit interruption info type.
5686 *
5687 * @returns The IEM exception flags.
5688 * @param uVector The event vector.
5689 * @param uVmxVectorType The VMX event type.
5690 *
5691 * @remarks This function currently only constructs flags required for
5692 * IEMEvaluateRecursiveXcpt and not the complete flags (e.g, error-code
5693 * and CR2 aspects of an exception are not included).
5694 */
5695static uint32_t hmR0VmxGetIemXcptFlags(uint8_t uVector, uint32_t uVmxVectorType)
5696{
5697 uint32_t fIemXcptFlags;
5698 switch (uVmxVectorType)
5699 {
5700 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
5701 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
5702 fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5703 break;
5704
5705 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
5706 fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5707 break;
5708
5709 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
5710 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT | IEM_XCPT_FLAGS_ICEBP_INSTR;
5711 break;
5712
5713 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT:
5714 {
5715 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5716 if (uVector == X86_XCPT_BP)
5717 fIemXcptFlags |= IEM_XCPT_FLAGS_BP_INSTR;
5718 else if (uVector == X86_XCPT_OF)
5719 fIemXcptFlags |= IEM_XCPT_FLAGS_OF_INSTR;
5720 else
5721 {
5722 fIemXcptFlags = 0;
5723 AssertMsgFailed(("Unexpected vector for software int. uVector=%#x", uVector));
5724 }
5725 break;
5726 }
5727
5728 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
5729 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5730 break;
5731
5732 default:
5733 fIemXcptFlags = 0;
5734 AssertMsgFailed(("Unexpected vector type! uVmxVectorType=%#x uVector=%#x", uVmxVectorType, uVector));
5735 break;
5736 }
5737 return fIemXcptFlags;
5738}
5739
5740
5741/**
5742 * Sets an event as a pending event to be injected into the guest.
5743 *
5744 * @param pVCpu The cross context virtual CPU structure.
5745 * @param u32IntInfo The VM-entry interruption-information field.
5746 * @param cbInstr The VM-entry instruction length in bytes (for software
5747 * interrupts, exceptions and privileged software
5748 * exceptions).
5749 * @param u32ErrCode The VM-entry exception error code.
5750 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a
5751 * page-fault.
5752 *
5753 * @remarks Statistics counter assumes this is a guest event being injected or
5754 * re-injected into the guest, i.e. 'StatInjectPendingReflect' is
5755 * always incremented.
5756 */
5757DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
5758 RTGCUINTPTR GCPtrFaultAddress)
5759{
5760 Assert(!pVCpu->hm.s.Event.fPending);
5761 pVCpu->hm.s.Event.fPending = true;
5762 pVCpu->hm.s.Event.u64IntInfo = u32IntInfo;
5763 pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
5764 pVCpu->hm.s.Event.cbInstr = cbInstr;
5765 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
5766}
5767
5768
5769/**
5770 * Sets a double-fault (\#DF) exception as pending-for-injection into the VM.
5771 *
5772 * @param pVCpu The cross context virtual CPU structure.
5773 */
5774DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPU pVCpu)
5775{
5776 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DF)
5777 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5778 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5779 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5780 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5781}
5782
5783
5784/**
5785 * Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
5786 *
5787 * @param pVCpu The cross context virtual CPU structure.
5788 */
5789DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPU pVCpu)
5790{
5791 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_UD)
5792 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5793 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
5794 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5795 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5796}
5797
5798
5799/**
5800 * Sets a debug (\#DB) exception as pending-for-injection into the VM.
5801 *
5802 * @param pVCpu The cross context virtual CPU structure.
5803 */
5804DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPU pVCpu)
5805{
5806 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
5807 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5808 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
5809 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5810 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5811}
5812
5813
5814/**
5815 * Sets an overflow (\#OF) exception as pending-for-injection into the VM.
5816 *
5817 * @param pVCpu The cross context virtual CPU structure.
5818 * @param cbInstr The value of RIP that is to be pushed on the guest
5819 * stack.
5820 */
5821DECLINLINE(void) hmR0VmxSetPendingXcptOF(PVMCPU pVCpu, uint32_t cbInstr)
5822{
5823 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_OF)
5824 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_SW_INT)
5825 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
5826 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5827 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5828}
5829
5830
5831#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5832/**
5833 * Sets a general-protection (\#GP) exception as pending-for-injection into the VM.
5834 *
5835 * @param pVCpu The cross context virtual CPU structure.
5836 * @param u32ErrCode The error code for the general-protection exception.
5837 */
5838DECLINLINE(void) hmR0VmxSetPendingXcptGP(PVMCPU pVCpu, uint32_t u32ErrCode)
5839{
5840 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_GP)
5841 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5842 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5843 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5844 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrCode, 0 /* GCPtrFaultAddress */);
5845}
5846#endif
5847
5848
5849/**
5850 * Sets a stack (\#SS) exception as pending-for-injection into the VM.
5851 *
5852 * @param pVCpu The cross context virtual CPU structure.
5853 * @param u32ErrCode The error code for the stack exception.
5854 */
5855DECLINLINE(void) hmR0VmxSetPendingXcptSS(PVMCPU pVCpu, uint32_t u32ErrCode)
5856{
5857 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_SS)
5858 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5859 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5860 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5861 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrCode, 0 /* GCPtrFaultAddress */);
5862}
5863
5864
5865#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5866
5867/**
5868 * Decodes the memory operand of a VM-exit due to instruction execution.
5869 *
5870 * For instructions with two operands, the second operand is usually found in the
5871 * VM-exit qualification field.
5872 *
5873 * @returns Strict VBox status code (i.e. informational status codes too).
5874 * @retval VINF_SUCCESS if the operand was successfully decoded.
5875 * @retval VINF_HM_PENDING_XCPT if an exception was raised while decoding the
5876 * operand.
5877 * @param pVCpu The cross context virtual CPU structure.
5878 * @param pExitInstrInfo Pointer to the VM-exit instruction information.
5879 * @param fIsWrite Whether the operand is a destination memory operand
5880 * (i.e. writeable memory location) or not.
5881 * @param GCPtrDisp The instruction displacement field, if any. For
5882 * RIP-relative addressing pass RIP + displacement here.
5883 * @param pGCPtrMem Where to store the destination memory operand.
5884 */
5885static VBOXSTRICTRC hmR0VmxDecodeMemOperand(PVMCPU pVCpu, PCVMXEXITINSTRINFO pExitInstrInfo, RTGCPTR GCPtrDisp, bool fIsWrite,
5886 PRTGCPTR pGCPtrMem)
5887{
5888 Assert(pExitInstrInfo);
5889 Assert(pGCPtrMem);
5890 Assert(!CPUMIsGuestInRealOrV86Mode(pVCpu));
5891
5892 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
5893 static uint64_t const s_auAccessSizeMasks[] = { sizeof(uint16_t), sizeof(uint32_t), sizeof(uint64_t) };
5894 AssertCompile(RT_ELEMENTS(s_auAccessSizeMasks) == RT_ELEMENTS(s_auAddrSizeMasks));
5895
5896 uint8_t const uAddrSize = pExitInstrInfo->InvVmxXsaves.u3AddrSize;
5897 uint8_t const iSegReg = pExitInstrInfo->InvVmxXsaves.iSegReg;
5898 bool const fIdxRegValid = !pExitInstrInfo->InvVmxXsaves.fIdxRegInvalid;
5899 uint8_t const iIdxReg = pExitInstrInfo->InvVmxXsaves.iIdxReg;
5900 uint8_t const uScale = pExitInstrInfo->InvVmxXsaves.u2Scaling;
5901 bool const fBaseRegValid = !pExitInstrInfo->InvVmxXsaves.fBaseRegInvalid;
5902 uint8_t const iBaseReg = pExitInstrInfo->InvVmxXsaves.iBaseReg;
5903 bool const fIsMemOperand = !pExitInstrInfo->InvVmxXsaves.fIsRegOperand;
5904 bool const fIsLongMode = CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx);
5905
5906 /*
5907 * Validate instruction information.
5908 * This shouldn't happen on real hardware but useful while testing our nested hardware-virtualization code.
5909 */
5910 AssertLogRelMsgReturn(uAddrSize < RT_ELEMENTS(s_auAddrSizeMasks),
5911 ("Invalid address size. ExitInstrInfo=%#RX32\n", pExitInstrInfo->u), VERR_VMX_IPE_1);
5912 AssertLogRelMsgReturn(iSegReg < X86_SREG_COUNT,
5913 ("Invalid segment register. ExitInstrInfo=%#RX32\n", pExitInstrInfo->u), VERR_VMX_IPE_2);
5914 AssertLogRelMsgReturn(fIsMemOperand,
5915 ("Expected memory operand. ExitInstrInfo=%#RX32\n", pExitInstrInfo->u), VERR_VMX_IPE_3);
5916
5917 /*
5918 * Compute the complete effective address.
5919 *
5920 * See AMD instruction spec. 1.4.2 "SIB Byte Format"
5921 * See AMD spec. 4.5.2 "Segment Registers".
5922 */
5923 RTGCPTR GCPtrMem = GCPtrDisp;
5924 if (fBaseRegValid)
5925 GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iBaseReg].u64;
5926 if (fIdxRegValid)
5927 GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iIdxReg].u64 << uScale;
5928
5929 RTGCPTR const GCPtrOff = GCPtrMem;
5930 if ( !fIsLongMode
5931 || iSegReg >= X86_SREG_FS)
5932 GCPtrMem += pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
5933 GCPtrMem &= s_auAddrSizeMasks[uAddrSize];
5934
5935 /*
5936 * Validate effective address.
5937 * See AMD spec. 4.5.3 "Segment Registers in 64-Bit Mode".
5938 */
5939 uint8_t const cbAccess = s_auAccessSizeMasks[uAddrSize];
5940 Assert(cbAccess > 0);
5941 if (fIsLongMode)
5942 {
5943 if (X86_IS_CANONICAL(GCPtrMem))
5944 {
5945 *pGCPtrMem = GCPtrMem;
5946 return VINF_SUCCESS;
5947 }
5948
5949 Log4Func(("Long mode effective address is not canonical GCPtrMem=%#RX64\n", GCPtrMem));
5950 hmR0VmxSetPendingXcptGP(pVCpu, 0);
5951 return VINF_HM_PENDING_XCPT;
5952 }
5953
5954 /*
5955 * This is a watered down version of iemMemApplySegment().
5956 * Parts that are not applicable for VMX instructions like real-or-v8086 mode
5957 * and segment CPL/DPL checks are skipped.
5958 */
5959 RTGCPTR32 const GCPtrFirst32 = (RTGCPTR32)GCPtrOff;
5960 RTGCPTR32 const GCPtrLast32 = GCPtrFirst32 + cbAccess - 1;
5961 PCCPUMSELREG pSel = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
5962
5963 /* Check if the segment is present and usable. */
5964 if ( pSel->Attr.n.u1Present
5965 && !pSel->Attr.n.u1Unusable)
5966 {
5967 Assert(pSel->Attr.n.u1DescType);
5968 if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_CODE))
5969 {
5970 /* Check permissions for the data segment. */
5971 if ( fIsWrite
5972 && !(pSel->Attr.n.u4Type & X86_SEL_TYPE_WRITE))
5973 {
5974 Log4Func(("Data segment access invalid. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
5975 hmR0VmxSetPendingXcptGP(pVCpu, iSegReg);
5976 return VINF_HM_PENDING_XCPT;
5977 }
5978
5979 /* Check limits if it's a normal data segment. */
5980 if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_DOWN))
5981 {
5982 if ( GCPtrFirst32 > pSel->u32Limit
5983 || GCPtrLast32 > pSel->u32Limit)
5984 {
5985 Log4Func(("Data segment limit exceeded."
5986 "iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
5987 GCPtrLast32, pSel->u32Limit));
5988 if (iSegReg == X86_SREG_SS)
5989 hmR0VmxSetPendingXcptSS(pVCpu, 0);
5990 else
5991 hmR0VmxSetPendingXcptGP(pVCpu, 0);
5992 return VINF_HM_PENDING_XCPT;
5993 }
5994 }
5995 else
5996 {
5997 /* Check limits if it's an expand-down data segment.
5998 Note! The upper boundary is defined by the B bit, not the G bit! */
5999 if ( GCPtrFirst32 < pSel->u32Limit + UINT32_C(1)
6000 || GCPtrLast32 > (pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT32_C(0xffff)))
6001 {
6002 Log4Func(("Expand-down data segment limit exceeded."
6003 "iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
6004 GCPtrLast32, pSel->u32Limit));
6005 if (iSegReg == X86_SREG_SS)
6006 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6007 else
6008 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6009 return VINF_HM_PENDING_XCPT;
6010 }
6011 }
6012 }
6013 else
6014 {
6015 /* Check permissions for the code segment. */
6016 if ( fIsWrite
6017 || !(pSel->Attr.n.u4Type & X86_SEL_TYPE_READ))
6018 {
6019 Log4Func(("Code segment access invalid. Attr=%#RX32\n", pSel->Attr.u));
6020 Assert(!CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx));
6021 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6022 return VINF_HM_PENDING_XCPT;
6023 }
6024
6025 /* Check limits for the code segment (normal/expand-down not applicable for code segments). */
6026 if ( GCPtrFirst32 > pSel->u32Limit
6027 || GCPtrLast32 > pSel->u32Limit)
6028 {
6029 Log4Func(("Code segment limit exceeded. GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n",
6030 GCPtrFirst32, GCPtrLast32, pSel->u32Limit));
6031 if (iSegReg == X86_SREG_SS)
6032 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6033 else
6034 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6035 return VINF_HM_PENDING_XCPT;
6036 }
6037 }
6038 }
6039 else
6040 {
6041 Log4Func(("Not present or unusable segment. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
6042 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6043 return VINF_HM_PENDING_XCPT;
6044 }
6045
6046 *pGCPtrMem = GCPtrMem;
6047 return VINF_SUCCESS;
6048}
6049
6050
6051/**
6052 * Perform the relevant VMX instruction checks for VM-exits that occurred due to the
6053 * guest attempting to execute a VMX instruction.
6054 *
6055 * @returns Strict VBox status code (i.e. informational status codes too).
6056 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
6057 * @retval VINF_HM_PENDING_XCPT if an exception was raised.
6058 *
6059 * @param pVCpu The cross context virtual CPU structure.
6060 * @param pVmxTransient Pointer to the VMX transient structure.
6061 *
6062 * @todo NstVmx: Document other error codes when VM-exit is implemented.
6063 * @remarks No-long-jump zone!!!
6064 */
6065static VBOXSTRICTRC hmR0VmxCheckExitDueToVmxInstr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
6066{
6067 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS
6068 | CPUMCTX_EXTRN_HWVIRT);
6069
6070 if ( CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx)
6071 || ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
6072 && !CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx)))
6073 {
6074 Log4Func(("In real/v86-mode or long-mode outside 64-bit code segment -> #UD\n"));
6075 hmR0VmxSetPendingXcptUD(pVCpu);
6076 return VINF_HM_PENDING_XCPT;
6077 }
6078
6079 if (pVmxTransient->uExitReason == VMX_EXIT_VMXON)
6080 {
6081 /*
6082 * We check CR4.VMXE because it is required to be always set while in VMX operation
6083 * by physical CPUs and our CR4 read shadow is only consulted when executing specific
6084 * instructions (CLTS, LMSW, MOV CR, and SMSW) and thus doesn't affect CPU operation
6085 * otherwise (i.e. physical CPU won't automatically #UD if Cr4Shadow.VMXE is 0).
6086 */
6087 if (!CPUMIsGuestVmxEnabled(&pVCpu->cpum.GstCtx))
6088 {
6089 Log4Func(("CR4.VMXE is not set -> #UD\n"));
6090 hmR0VmxSetPendingXcptUD(pVCpu);
6091 return VINF_HM_PENDING_XCPT;
6092 }
6093 }
6094 else if (!CPUMIsGuestInVmxRootMode(&pVCpu->cpum.GstCtx))
6095 {
6096 /*
6097 * The guest has not entered VMX operation but attempted to execute a VMX instruction
6098 * (other than VMXON), we need to raise a #UD.
6099 */
6100 Log4Func(("Not in VMX root mode -> #UD\n"));
6101 hmR0VmxSetPendingXcptUD(pVCpu);
6102 return VINF_HM_PENDING_XCPT;
6103 }
6104
6105 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
6106 {
6107 /*
6108 * The nested-guest attempted to execute a VMX instruction, cause a VM-exit and let
6109 * the guest hypervisor deal with it.
6110 */
6111 /** @todo NSTVMX: Trigger a VM-exit */
6112 }
6113
6114 /*
6115 * VMX instructions require CPL 0 except in VMX non-root mode where the VM-exit intercept
6116 * (above) takes preceedence over the CPL check.
6117 */
6118 if (CPUMGetGuestCPL(pVCpu) > 0)
6119 {
6120 Log4Func(("CPL > 0 -> #GP(0)\n"));
6121 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6122 return VINF_HM_PENDING_XCPT;
6123 }
6124
6125 return VINF_SUCCESS;
6126}
6127
6128#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
6129
6130
6131/**
6132 * Handle a condition that occurred while delivering an event through the guest
6133 * IDT.
6134 *
6135 * @returns Strict VBox status code (i.e. informational status codes too).
6136 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
6137 * @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought
6138 * to continue execution of the guest which will delivery the \#DF.
6139 * @retval VINF_EM_RESET if we detected a triple-fault condition.
6140 * @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
6141 *
6142 * @param pVCpu The cross context virtual CPU structure.
6143 * @param pVmxTransient Pointer to the VMX transient structure.
6144 *
6145 * @remarks No-long-jump zone!!!
6146 */
6147static VBOXSTRICTRC hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
6148{
6149 uint32_t const uExitVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
6150
6151 int rc2 = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
6152 rc2 |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
6153 AssertRCReturn(rc2, rc2);
6154
6155 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
6156 if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
6157 {
6158 uint32_t const uIdtVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
6159 uint32_t const uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
6160
6161 /*
6162 * If the event was a software interrupt (generated with INT n) or a software exception
6163 * (generated by INT3/INTO) or a privileged software exception (generated by INT1), we
6164 * can handle the VM-exit and continue guest execution which will re-execute the
6165 * instruction rather than re-injecting the exception, as that can cause premature
6166 * trips to ring-3 before injection and involve TRPM which currently has no way of
6167 * storing that these exceptions were caused by these instructions (ICEBP's #DB poses
6168 * the problem).
6169 */
6170 IEMXCPTRAISE enmRaise;
6171 IEMXCPTRAISEINFO fRaiseInfo;
6172 if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
6173 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
6174 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
6175 {
6176 enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
6177 fRaiseInfo = IEMXCPTRAISEINFO_NONE;
6178 }
6179 else if (VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo))
6180 {
6181 uint32_t const uExitVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uExitIntInfo);
6182 uint32_t const fIdtVectorFlags = hmR0VmxGetIemXcptFlags(uIdtVector, uIdtVectorType);
6183 uint32_t const fExitVectorFlags = hmR0VmxGetIemXcptFlags(uExitVector, uExitVectorType);
6184 /** @todo Make AssertMsgReturn as just AssertMsg later. */
6185 AssertMsgReturn(uExitVectorType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT,
6186 ("hmR0VmxCheckExitDueToEventDelivery: Unexpected VM-exit interruption info. %#x!\n",
6187 uExitVectorType), VERR_VMX_IPE_5);
6188
6189 enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
6190
6191 /* Determine a vectoring #PF condition, see comment in hmR0VmxExitXcptPF(). */
6192 if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF | IEMXCPTRAISEINFO_NMI_PF))
6193 {
6194 pVmxTransient->fVectoringPF = true;
6195 enmRaise = IEMXCPTRAISE_PREV_EVENT;
6196 }
6197 }
6198 else
6199 {
6200 /*
6201 * If an exception or hardware interrupt delivery caused an EPT violation/misconfig or APIC access
6202 * VM-exit, then the VM-exit interruption-information will not be valid and we end up here.
6203 * It is sufficient to reflect the original event to the guest after handling the VM-exit.
6204 */
6205 Assert( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
6206 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
6207 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
6208 enmRaise = IEMXCPTRAISE_PREV_EVENT;
6209 fRaiseInfo = IEMXCPTRAISEINFO_NONE;
6210 }
6211
6212 /*
6213 * On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig
6214 * etc.) occurred while delivering the NMI, we need to clear the block-by-NMI field in the guest
6215 * interruptibility-state before re-delivering the NMI after handling the VM-exit. Otherwise the
6216 * subsequent VM-entry would fail.
6217 *
6218 * See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
6219 */
6220 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
6221 && uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
6222 && ( enmRaise == IEMXCPTRAISE_PREV_EVENT
6223 || (fRaiseInfo & IEMXCPTRAISEINFO_NMI_PF))
6224 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6225 {
6226 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6227 }
6228
6229 switch (enmRaise)
6230 {
6231 case IEMXCPTRAISE_CURRENT_XCPT:
6232 {
6233 Log4Func(("IDT: Pending secondary Xcpt: uIdtVectoringInfo=%#RX64 uExitIntInfo=%#RX64\n",
6234 pVmxTransient->uIdtVectoringInfo, pVmxTransient->uExitIntInfo));
6235 Assert(rcStrict == VINF_SUCCESS);
6236 break;
6237 }
6238
6239 case IEMXCPTRAISE_PREV_EVENT:
6240 {
6241 uint32_t u32ErrCode;
6242 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo))
6243 {
6244 rc2 = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
6245 AssertRCReturn(rc2, rc2);
6246 u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
6247 }
6248 else
6249 u32ErrCode = 0;
6250
6251 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF, see hmR0VmxExitXcptPF(). */
6252 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6253 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
6254 0 /* cbInstr */, u32ErrCode, pVCpu->cpum.GstCtx.cr2);
6255
6256 Log4Func(("IDT: Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->hm.s.Event.u64IntInfo,
6257 pVCpu->hm.s.Event.u32ErrCode));
6258 Assert(rcStrict == VINF_SUCCESS);
6259 break;
6260 }
6261
6262 case IEMXCPTRAISE_REEXEC_INSTR:
6263 Assert(rcStrict == VINF_SUCCESS);
6264 break;
6265
6266 case IEMXCPTRAISE_DOUBLE_FAULT:
6267 {
6268 /*
6269 * Determing a vectoring double #PF condition. Used later, when PGM evaluates the
6270 * second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
6271 */
6272 if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
6273 {
6274 pVmxTransient->fVectoringDoublePF = true;
6275 Log4Func(("IDT: Vectoring double #PF %#RX64 cr2=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo,
6276 pVCpu->cpum.GstCtx.cr2));
6277 rcStrict = VINF_SUCCESS;
6278 }
6279 else
6280 {
6281 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6282 hmR0VmxSetPendingXcptDF(pVCpu);
6283 Log4Func(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
6284 uIdtVector, uExitVector));
6285 rcStrict = VINF_HM_DOUBLE_FAULT;
6286 }
6287 break;
6288 }
6289
6290 case IEMXCPTRAISE_TRIPLE_FAULT:
6291 {
6292 Log4Func(("IDT: Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", uIdtVector, uExitVector));
6293 rcStrict = VINF_EM_RESET;
6294 break;
6295 }
6296
6297 case IEMXCPTRAISE_CPU_HANG:
6298 {
6299 Log4Func(("IDT: Bad guest! Entering CPU hang. fRaiseInfo=%#x\n", fRaiseInfo));
6300 rcStrict = VERR_EM_GUEST_CPU_HANG;
6301 break;
6302 }
6303
6304 default:
6305 {
6306 AssertMsgFailed(("IDT: vcpu[%RU32] Unexpected/invalid value! enmRaise=%#x\n", pVCpu->idCpu, enmRaise));
6307 rcStrict = VERR_VMX_IPE_2;
6308 break;
6309 }
6310 }
6311 }
6312 else if ( VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo)
6313 && VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(pVmxTransient->uExitIntInfo)
6314 && uExitVector != X86_XCPT_DF
6315 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6316 {
6317 /*
6318 * Execution of IRET caused this fault when NMI blocking was in effect (i.e we're in the guest NMI handler).
6319 * We need to set the block-by-NMI field so that NMIs remain blocked until the IRET execution is restarted.
6320 * See Intel spec. 30.7.1.2 "Resuming guest software after handling an exception".
6321 */
6322 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6323 {
6324 Log4Func(("Setting VMCPU_FF_BLOCK_NMIS. fValid=%RTbool uExitReason=%u\n",
6325 VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo), pVmxTransient->uExitReason));
6326 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6327 }
6328 }
6329
6330 Assert( rcStrict == VINF_SUCCESS || rcStrict == VINF_HM_DOUBLE_FAULT
6331 || rcStrict == VINF_EM_RESET || rcStrict == VERR_EM_GUEST_CPU_HANG);
6332 return rcStrict;
6333}
6334
6335
6336/**
6337 * Imports a guest segment register from the current VMCS into
6338 * the guest-CPU context.
6339 *
6340 * @returns VBox status code.
6341 * @param pVCpu The cross context virtual CPU structure.
6342 * @param idxSel Index of the selector in the VMCS.
6343 * @param idxLimit Index of the segment limit in the VMCS.
6344 * @param idxBase Index of the segment base in the VMCS.
6345 * @param idxAccess Index of the access rights of the segment in the VMCS.
6346 * @param pSelReg Pointer to the segment selector.
6347 *
6348 * @remarks Called with interrupts and/or preemption disabled, try not to assert and
6349 * do not log!
6350 *
6351 * @remarks Never call this function directly!!! Use the
6352 * HMVMX_IMPORT_SREG() macro as that takes care
6353 * of whether to read from the VMCS cache or not.
6354 */
6355static int hmR0VmxImportGuestSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
6356 PCPUMSELREG pSelReg)
6357{
6358 NOREF(pVCpu);
6359
6360 uint32_t u32Sel;
6361 uint32_t u32Limit;
6362 uint32_t u32Attr;
6363 uint64_t u64Base;
6364 int rc = VMXReadVmcs32(idxSel, &u32Sel);
6365 rc |= VMXReadVmcs32(idxLimit, &u32Limit);
6366 rc |= VMXReadVmcs32(idxAccess, &u32Attr);
6367 rc |= VMXReadVmcsGstNByIdxVal(idxBase, &u64Base);
6368 AssertRCReturn(rc, rc);
6369
6370 pSelReg->Sel = (uint16_t)u32Sel;
6371 pSelReg->ValidSel = (uint16_t)u32Sel;
6372 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6373 pSelReg->u32Limit = u32Limit;
6374 pSelReg->u64Base = u64Base;
6375 pSelReg->Attr.u = u32Attr;
6376
6377 /*
6378 * If VT-x marks the segment as unusable, most other bits remain undefined:
6379 * - For CS the L, D and G bits have meaning.
6380 * - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
6381 * - For the remaining data segments no bits are defined.
6382 *
6383 * The present bit and the unusable bit has been observed to be set at the
6384 * same time (the selector was supposed to be invalid as we started executing
6385 * a V8086 interrupt in ring-0).
6386 *
6387 * What should be important for the rest of the VBox code, is that the P bit is
6388 * cleared. Some of the other VBox code recognizes the unusable bit, but
6389 * AMD-V certainly don't, and REM doesn't really either. So, to be on the
6390 * safe side here, we'll strip off P and other bits we don't care about. If
6391 * any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
6392 *
6393 * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
6394 */
6395 if (pSelReg->Attr.u & X86DESCATTR_UNUSABLE)
6396 {
6397 Assert(idxSel != VMX_VMCS16_GUEST_TR_SEL); /* TR is the only selector that can never be unusable. */
6398
6399 /* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
6400 pSelReg->Attr.u &= X86DESCATTR_UNUSABLE | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
6401 | X86DESCATTR_DPL | X86DESCATTR_TYPE | X86DESCATTR_DT;
6402#ifdef VBOX_STRICT
6403 VMMRZCallRing3Disable(pVCpu);
6404 Log4Func(("Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Sel, pSelReg->Attr.u));
6405# ifdef DEBUG_bird
6406 AssertMsg((u32Attr & ~X86DESCATTR_P) == pSelReg->Attr.u,
6407 ("%#x: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
6408 idxSel, u32Sel, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
6409# endif
6410 VMMRZCallRing3Enable(pVCpu);
6411#endif
6412 }
6413 return VINF_SUCCESS;
6414}
6415
6416
6417/**
6418 * Imports the guest RIP from the VMCS back into the guest-CPU context.
6419 *
6420 * @returns VBox status code.
6421 * @param pVCpu The cross context virtual CPU structure.
6422 *
6423 * @remarks Called with interrupts and/or preemption disabled, should not assert!
6424 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6425 * instead!!!
6426 */
6427DECLINLINE(int) hmR0VmxImportGuestRip(PVMCPU pVCpu)
6428{
6429 uint64_t u64Val;
6430 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6431 if (pCtx->fExtrn & CPUMCTX_EXTRN_RIP)
6432 {
6433 int rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);
6434 if (RT_SUCCESS(rc))
6435 {
6436 pCtx->rip = u64Val;
6437 EMR0HistoryUpdatePC(pVCpu, pCtx->rip, false);
6438 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RIP;
6439 }
6440 return rc;
6441 }
6442 return VINF_SUCCESS;
6443}
6444
6445
6446/**
6447 * Imports the guest RFLAGS from the VMCS back into the guest-CPU context.
6448 *
6449 * @returns VBox status code.
6450 * @param pVCpu The cross context virtual CPU structure.
6451 *
6452 * @remarks Called with interrupts and/or preemption disabled, should not assert!
6453 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6454 * instead!!!
6455 */
6456DECLINLINE(int) hmR0VmxImportGuestRFlags(PVMCPU pVCpu)
6457{
6458 uint32_t u32Val;
6459 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6460 if (pCtx->fExtrn & CPUMCTX_EXTRN_RFLAGS)
6461 {
6462 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val);
6463 if (RT_SUCCESS(rc))
6464 {
6465 pCtx->eflags.u32 = u32Val;
6466
6467 /* Restore eflags for real-on-v86-mode hack. */
6468 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6469 {
6470 pCtx->eflags.Bits.u1VM = 0;
6471 pCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.Eflags.Bits.u2IOPL;
6472 }
6473 }
6474 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
6475 return rc;
6476 }
6477 return VINF_SUCCESS;
6478}
6479
6480
6481/**
6482 * Imports the guest interruptibility-state from the VMCS back into the guest-CPU
6483 * context.
6484 *
6485 * @returns VBox status code.
6486 * @param pVCpu The cross context virtual CPU structure.
6487 *
6488 * @remarks Called with interrupts and/or preemption disabled, try not to assert and
6489 * do not log!
6490 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6491 * instead!!!
6492 */
6493DECLINLINE(int) hmR0VmxImportGuestIntrState(PVMCPU pVCpu)
6494{
6495 uint32_t u32Val;
6496 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6497 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32Val);
6498 if (RT_SUCCESS(rc))
6499 {
6500 /*
6501 * We additionally have a requirement to import RIP, RFLAGS depending on whether we
6502 * might need them in hmR0VmxEvaluatePendingEvent().
6503 */
6504 if (!u32Val)
6505 {
6506 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6507 {
6508 rc = hmR0VmxImportGuestRip(pVCpu);
6509 rc |= hmR0VmxImportGuestRFlags(pVCpu);
6510 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6511 }
6512
6513 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6514 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6515 }
6516 else
6517 {
6518 rc = hmR0VmxImportGuestRip(pVCpu);
6519 rc |= hmR0VmxImportGuestRFlags(pVCpu);
6520
6521 if (u32Val & ( VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
6522 | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
6523 {
6524 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
6525 }
6526 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6527 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6528
6529 if (u32Val & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6530 {
6531 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6532 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6533 }
6534 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6535 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6536 }
6537 }
6538 return rc;
6539}
6540
6541
6542/**
6543 * Worker for VMXR0ImportStateOnDemand.
6544 *
6545 * @returns VBox status code.
6546 * @param pVCpu The cross context virtual CPU structure.
6547 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
6548 */
6549static int hmR0VmxImportGuestState(PVMCPU pVCpu, uint64_t fWhat)
6550{
6551#define VMXLOCAL_BREAK_RC(a_rc) \
6552 if (RT_FAILURE(a_rc)) \
6553 break
6554
6555 int rc = VINF_SUCCESS;
6556 PVM pVM = pVCpu->CTX_SUFF(pVM);
6557 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6558 uint64_t u64Val;
6559 uint32_t u32Val;
6560
6561 Log4Func(("fExtrn=%#RX64 fWhat=%#RX64\n", pCtx->fExtrn, fWhat));
6562 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
6563
6564 /*
6565 * We disable interrupts to make the updating of the state and in particular
6566 * the fExtrn modification atomic wrt to preemption hooks.
6567 */
6568 RTCCUINTREG const fEFlags = ASMIntDisableFlags();
6569
6570 fWhat &= pCtx->fExtrn;
6571 if (fWhat)
6572 {
6573 do
6574 {
6575 if (fWhat & CPUMCTX_EXTRN_RIP)
6576 {
6577 rc = hmR0VmxImportGuestRip(pVCpu);
6578 VMXLOCAL_BREAK_RC(rc);
6579 }
6580
6581 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
6582 {
6583 rc = hmR0VmxImportGuestRFlags(pVCpu);
6584 VMXLOCAL_BREAK_RC(rc);
6585 }
6586
6587 if (fWhat & CPUMCTX_EXTRN_HM_VMX_INT_STATE)
6588 {
6589 rc = hmR0VmxImportGuestIntrState(pVCpu);
6590 VMXLOCAL_BREAK_RC(rc);
6591 }
6592
6593 if (fWhat & CPUMCTX_EXTRN_RSP)
6594 {
6595 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);
6596 VMXLOCAL_BREAK_RC(rc);
6597 pCtx->rsp = u64Val;
6598 }
6599
6600 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
6601 {
6602 if (fWhat & CPUMCTX_EXTRN_CS)
6603 {
6604 rc = HMVMX_IMPORT_SREG(CS, &pCtx->cs);
6605 rc |= hmR0VmxImportGuestRip(pVCpu);
6606 VMXLOCAL_BREAK_RC(rc);
6607 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6608 pCtx->cs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrCS.u;
6609 EMR0HistoryUpdatePC(pVCpu, pCtx->cs.u64Base + pCtx->rip, true);
6610 }
6611 if (fWhat & CPUMCTX_EXTRN_SS)
6612 {
6613 rc = HMVMX_IMPORT_SREG(SS, &pCtx->ss);
6614 VMXLOCAL_BREAK_RC(rc);
6615 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6616 pCtx->ss.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrSS.u;
6617 }
6618 if (fWhat & CPUMCTX_EXTRN_DS)
6619 {
6620 rc = HMVMX_IMPORT_SREG(DS, &pCtx->ds);
6621 VMXLOCAL_BREAK_RC(rc);
6622 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6623 pCtx->ds.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrDS.u;
6624 }
6625 if (fWhat & CPUMCTX_EXTRN_ES)
6626 {
6627 rc = HMVMX_IMPORT_SREG(ES, &pCtx->es);
6628 VMXLOCAL_BREAK_RC(rc);
6629 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6630 pCtx->es.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrES.u;
6631 }
6632 if (fWhat & CPUMCTX_EXTRN_FS)
6633 {
6634 rc = HMVMX_IMPORT_SREG(FS, &pCtx->fs);
6635 VMXLOCAL_BREAK_RC(rc);
6636 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6637 pCtx->fs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrFS.u;
6638 }
6639 if (fWhat & CPUMCTX_EXTRN_GS)
6640 {
6641 rc = HMVMX_IMPORT_SREG(GS, &pCtx->gs);
6642 VMXLOCAL_BREAK_RC(rc);
6643 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6644 pCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrGS.u;
6645 }
6646 }
6647
6648 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
6649 {
6650 if (fWhat & CPUMCTX_EXTRN_LDTR)
6651 {
6652 rc = HMVMX_IMPORT_SREG(LDTR, &pCtx->ldtr);
6653 VMXLOCAL_BREAK_RC(rc);
6654 }
6655
6656 if (fWhat & CPUMCTX_EXTRN_GDTR)
6657 {
6658 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
6659 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
6660 VMXLOCAL_BREAK_RC(rc);
6661 pCtx->gdtr.pGdt = u64Val;
6662 pCtx->gdtr.cbGdt = u32Val;
6663 }
6664
6665 /* Guest IDTR. */
6666 if (fWhat & CPUMCTX_EXTRN_IDTR)
6667 {
6668 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
6669 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
6670 VMXLOCAL_BREAK_RC(rc);
6671 pCtx->idtr.pIdt = u64Val;
6672 pCtx->idtr.cbIdt = u32Val;
6673 }
6674
6675 /* Guest TR. */
6676 if (fWhat & CPUMCTX_EXTRN_TR)
6677 {
6678 /* Real-mode emulation using virtual-8086 mode has the fake TSS (pRealModeTSS) in TR, don't save that one. */
6679 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6680 {
6681 rc = HMVMX_IMPORT_SREG(TR, &pCtx->tr);
6682 VMXLOCAL_BREAK_RC(rc);
6683 }
6684 }
6685 }
6686
6687 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
6688 {
6689 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &pCtx->SysEnter.eip);
6690 rc |= VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &pCtx->SysEnter.esp);
6691 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val);
6692 pCtx->SysEnter.cs = u32Val;
6693 VMXLOCAL_BREAK_RC(rc);
6694 }
6695
6696#if HC_ARCH_BITS == 64
6697 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
6698 {
6699 if ( pVM->hm.s.fAllow64BitGuests
6700 && (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
6701 pCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
6702 }
6703
6704 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
6705 {
6706 if ( pVM->hm.s.fAllow64BitGuests
6707 && (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
6708 {
6709 pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
6710 pCtx->msrSTAR = ASMRdMsr(MSR_K6_STAR);
6711 pCtx->msrSFMASK = ASMRdMsr(MSR_K8_SF_MASK);
6712 }
6713 }
6714#endif
6715
6716 if ( (fWhat & (CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))
6717#if HC_ARCH_BITS == 32
6718 || (fWhat & (CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS))
6719#endif
6720 )
6721 {
6722 PCVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
6723 uint32_t const cMsrs = pVCpu->hm.s.vmx.cMsrs;
6724 for (uint32_t i = 0; i < cMsrs; i++, pMsr++)
6725 {
6726 switch (pMsr->u32Msr)
6727 {
6728#if HC_ARCH_BITS == 32
6729 case MSR_K8_LSTAR: pCtx->msrLSTAR = pMsr->u64Value; break;
6730 case MSR_K6_STAR: pCtx->msrSTAR = pMsr->u64Value; break;
6731 case MSR_K8_SF_MASK: pCtx->msrSFMASK = pMsr->u64Value; break;
6732 case MSR_K8_KERNEL_GS_BASE: pCtx->msrKERNELGSBASE = pMsr->u64Value; break;
6733#endif
6734 case MSR_IA32_SPEC_CTRL: CPUMSetGuestSpecCtrl(pVCpu, pMsr->u64Value); break;
6735 case MSR_K8_TSC_AUX: CPUMSetGuestTscAux(pVCpu, pMsr->u64Value); break;
6736 case MSR_K6_EFER: /* EFER can't be changed without causing a VM-exit */ break;
6737 default:
6738 {
6739 pVCpu->hm.s.u32HMError = pMsr->u32Msr;
6740 ASMSetFlags(fEFlags);
6741 AssertMsgFailed(("Unexpected MSR in auto-load/store area. uMsr=%#RX32 cMsrs=%u\n", pMsr->u32Msr,
6742 cMsrs));
6743 return VERR_HM_UNEXPECTED_LD_ST_MSR;
6744 }
6745 }
6746 }
6747 }
6748
6749 if (fWhat & CPUMCTX_EXTRN_DR7)
6750 {
6751 if (!pVCpu->hm.s.fUsingHyperDR7)
6752 {
6753 /* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
6754 rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val);
6755 VMXLOCAL_BREAK_RC(rc);
6756 pCtx->dr[7] = u32Val;
6757 }
6758 }
6759
6760 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
6761 {
6762 uint32_t u32Shadow;
6763 if (fWhat & CPUMCTX_EXTRN_CR0)
6764 {
6765 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val);
6766 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, &u32Shadow);
6767 VMXLOCAL_BREAK_RC(rc);
6768 u32Val = (u32Val & ~pVCpu->hm.s.vmx.u32Cr0Mask)
6769 | (u32Shadow & pVCpu->hm.s.vmx.u32Cr0Mask);
6770 VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
6771 CPUMSetGuestCR0(pVCpu, u32Val);
6772 VMMRZCallRing3Enable(pVCpu);
6773 }
6774
6775 if (fWhat & CPUMCTX_EXTRN_CR4)
6776 {
6777 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32Val);
6778 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &u32Shadow);
6779 VMXLOCAL_BREAK_RC(rc);
6780 u32Val = (u32Val & ~pVCpu->hm.s.vmx.u32Cr4Mask)
6781 | (u32Shadow & pVCpu->hm.s.vmx.u32Cr4Mask);
6782 CPUMSetGuestCR4(pVCpu, u32Val);
6783 }
6784
6785 if (fWhat & CPUMCTX_EXTRN_CR3)
6786 {
6787 /* CR0.PG bit changes are always intercepted, so it's up to date. */
6788 if ( pVM->hm.s.vmx.fUnrestrictedGuest
6789 || ( pVM->hm.s.fNestedPaging
6790 && CPUMIsGuestPagingEnabledEx(pCtx)))
6791 {
6792 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
6793 if (pCtx->cr3 != u64Val)
6794 {
6795 CPUMSetGuestCR3(pVCpu, u64Val);
6796 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
6797 }
6798
6799 /* If the guest is in PAE mode, sync back the PDPE's into the guest state.
6800 Note: CR4.PAE, CR0.PG, EFER bit changes are always intercepted, so they're up to date. */
6801 if (CPUMIsGuestInPAEModeEx(pCtx))
6802 {
6803 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
6804 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
6805 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
6806 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
6807 VMXLOCAL_BREAK_RC(rc);
6808 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
6809 }
6810 }
6811 }
6812 }
6813 } while (0);
6814
6815 if (RT_SUCCESS(rc))
6816 {
6817 /* Update fExtrn. */
6818 pCtx->fExtrn &= ~fWhat;
6819
6820 /* If everything has been imported, clear the HM keeper bit. */
6821 if (!(pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL))
6822 {
6823 pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
6824 Assert(!pCtx->fExtrn);
6825 }
6826 }
6827 }
6828 else
6829 AssertMsg(!pCtx->fExtrn || (pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL), ("%#RX64\n", pCtx->fExtrn));
6830
6831 ASMSetFlags(fEFlags);
6832
6833 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
6834
6835 /*
6836 * Honor any pending CR3 updates.
6837 *
6838 * Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> hmR0VmxCallRing3Callback()
6839 * -> VMMRZCallRing3Disable() -> hmR0VmxImportGuestState() -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
6840 * -> continue with VM-exit handling -> hmR0VmxImportGuestState() and here we are.
6841 *
6842 * The reason for such complicated handling is because VM-exits that call into PGM expect CR3 to be up-to-date and thus
6843 * if any CR3-saves -before- the VM-exit (longjmp) postponed the CR3 update via the force-flag, any VM-exit handler that
6844 * calls into PGM when it re-saves CR3 will end up here and we call PGMUpdateCR3(). This is why the code below should
6845 * -NOT- check if CPUMCTX_EXTRN_CR3 is set!
6846 *
6847 * The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
6848 */
6849 if (VMMRZCallRing3IsEnabled(pVCpu))
6850 {
6851 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6852 {
6853 Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_CR3));
6854 PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
6855 }
6856
6857 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6858 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6859
6860 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6861 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6862 }
6863
6864 return VINF_SUCCESS;
6865#undef VMXLOCAL_BREAK_RC
6866}
6867
6868
6869/**
6870 * Saves the guest state from the VMCS into the guest-CPU context.
6871 *
6872 * @returns VBox status code.
6873 * @param pVCpu The cross context virtual CPU structure.
6874 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
6875 */
6876VMMR0DECL(int) VMXR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
6877{
6878 return hmR0VmxImportGuestState(pVCpu, fWhat);
6879}
6880
6881
6882/**
6883 * Check per-VM and per-VCPU force flag actions that require us to go back to
6884 * ring-3 for one reason or another.
6885 *
6886 * @returns Strict VBox status code (i.e. informational status codes too)
6887 * @retval VINF_SUCCESS if we don't have any actions that require going back to
6888 * ring-3.
6889 * @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
6890 * @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
6891 * interrupts)
6892 * @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
6893 * all EMTs to be in ring-3.
6894 * @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
6895 * @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
6896 * to the EM loop.
6897 *
6898 * @param pVCpu The cross context virtual CPU structure.
6899 * @param fStepping Running in hmR0VmxRunGuestCodeStep().
6900 */
6901static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVMCPU pVCpu, bool fStepping)
6902{
6903 Assert(VMMRZCallRing3IsEnabled(pVCpu));
6904
6905 /*
6906 * Anything pending? Should be more likely than not if we're doing a good job.
6907 */
6908 PVM pVM = pVCpu->CTX_SUFF(pVM);
6909 if ( !fStepping
6910 ? !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_MASK)
6911 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)
6912 : !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK)
6913 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
6914 return VINF_SUCCESS;
6915
6916 /* Pending PGM C3 sync. */
6917 if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
6918 {
6919 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6920 Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4)));
6921 VBOXSTRICTRC rcStrict2 = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4,
6922 VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
6923 if (rcStrict2 != VINF_SUCCESS)
6924 {
6925 AssertRC(VBOXSTRICTRC_VAL(rcStrict2));
6926 Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
6927 return rcStrict2;
6928 }
6929 }
6930
6931 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
6932 if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
6933 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
6934 {
6935 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
6936 int rc2 = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
6937 Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc2));
6938 return rc2;
6939 }
6940
6941 /* Pending VM request packets, such as hardware interrupts. */
6942 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
6943 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
6944 {
6945 Log4Func(("Pending VM request forcing us back to ring-3\n"));
6946 return VINF_EM_PENDING_REQUEST;
6947 }
6948
6949 /* Pending PGM pool flushes. */
6950 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
6951 {
6952 Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
6953 return VINF_PGM_POOL_FLUSH_PENDING;
6954 }
6955
6956 /* Pending DMA requests. */
6957 if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
6958 {
6959 Log4Func(("Pending DMA request forcing us back to ring-3\n"));
6960 return VINF_EM_RAW_TO_R3;
6961 }
6962
6963 return VINF_SUCCESS;
6964}
6965
6966
6967/**
6968 * Converts any TRPM trap into a pending HM event. This is typically used when
6969 * entering from ring-3 (not longjmp returns).
6970 *
6971 * @param pVCpu The cross context virtual CPU structure.
6972 */
6973static void hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu)
6974{
6975 Assert(TRPMHasTrap(pVCpu));
6976 Assert(!pVCpu->hm.s.Event.fPending);
6977
6978 uint8_t uVector;
6979 TRPMEVENT enmTrpmEvent;
6980 RTGCUINT uErrCode;
6981 RTGCUINTPTR GCPtrFaultAddress;
6982 uint8_t cbInstr;
6983
6984 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
6985 AssertRC(rc);
6986
6987 /* Refer Intel spec. 24.8.3 "VM-entry Controls for Event Injection" for the format of u32IntInfo. */
6988 uint32_t u32IntInfo = uVector | VMX_EXIT_INT_INFO_VALID;
6989 if (enmTrpmEvent == TRPM_TRAP)
6990 {
6991 switch (uVector)
6992 {
6993 case X86_XCPT_NMI:
6994 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_NMI << VMX_EXIT_INT_INFO_TYPE_SHIFT);
6995 break;
6996
6997 case X86_XCPT_BP:
6998 case X86_XCPT_OF:
6999 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_SW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7000 break;
7001
7002 case X86_XCPT_PF:
7003 case X86_XCPT_DF:
7004 case X86_XCPT_TS:
7005 case X86_XCPT_NP:
7006 case X86_XCPT_SS:
7007 case X86_XCPT_GP:
7008 case X86_XCPT_AC:
7009 u32IntInfo |= VMX_EXIT_INT_INFO_ERROR_CODE_VALID;
7010 RT_FALL_THRU();
7011 default:
7012 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7013 break;
7014 }
7015 }
7016 else if (enmTrpmEvent == TRPM_HARDWARE_INT)
7017 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_EXT_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7018 else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
7019 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_SW_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7020 else
7021 AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
7022
7023 rc = TRPMResetTrap(pVCpu);
7024 AssertRC(rc);
7025 Log4(("TRPM->HM event: u32IntInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
7026 u32IntInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
7027
7028 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, uErrCode, GCPtrFaultAddress);
7029}
7030
7031
7032/**
7033 * Converts the pending HM event into a TRPM trap.
7034 *
7035 * @param pVCpu The cross context virtual CPU structure.
7036 */
7037static void hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu)
7038{
7039 Assert(pVCpu->hm.s.Event.fPending);
7040
7041 uint32_t uVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7042 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo);
7043 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVCpu->hm.s.Event.u64IntInfo);
7044 uint32_t uErrorCode = pVCpu->hm.s.Event.u32ErrCode;
7045
7046 /* If a trap was already pending, we did something wrong! */
7047 Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
7048
7049 TRPMEVENT enmTrapType;
7050 switch (uVectorType)
7051 {
7052 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
7053 enmTrapType = TRPM_HARDWARE_INT;
7054 break;
7055
7056 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
7057 enmTrapType = TRPM_SOFTWARE_INT;
7058 break;
7059
7060 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
7061 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
7062 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7063 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
7064 enmTrapType = TRPM_TRAP;
7065 break;
7066
7067 default:
7068 AssertMsgFailed(("Invalid trap type %#x\n", uVectorType));
7069 enmTrapType = TRPM_32BIT_HACK;
7070 break;
7071 }
7072
7073 Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
7074
7075 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7076 AssertRC(rc);
7077
7078 if (fErrorCodeValid)
7079 TRPMSetErrorCode(pVCpu, uErrorCode);
7080
7081 if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
7082 && uVector == X86_XCPT_PF)
7083 {
7084 TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
7085 }
7086 else if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7087 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
7088 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
7089 {
7090 AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7091 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7092 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
7093 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
7094 }
7095
7096 /* Clear any pending events from the VMCS. */
7097 VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0);
7098 VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0);
7099
7100 /* We're now done converting the pending event. */
7101 pVCpu->hm.s.Event.fPending = false;
7102}
7103
7104
7105/**
7106 * Does the necessary state syncing before returning to ring-3 for any reason
7107 * (longjmp, preemption, voluntary exits to ring-3) from VT-x.
7108 *
7109 * @returns VBox status code.
7110 * @param pVCpu The cross context virtual CPU structure.
7111 * @param fImportState Whether to import the guest state from the VMCS back
7112 * to the guest-CPU context.
7113 *
7114 * @remarks No-long-jmp zone!!!
7115 */
7116static int hmR0VmxLeave(PVMCPU pVCpu, bool fImportState)
7117{
7118 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7119 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7120
7121 RTCPUID idCpu = RTMpCpuId();
7122 Log4Func(("HostCpuId=%u\n", idCpu));
7123
7124 /*
7125 * !!! IMPORTANT !!!
7126 * If you modify code here, check whether hmR0VmxCallRing3Callback() needs to be updated too.
7127 */
7128
7129 /* Save the guest state if necessary. */
7130 if (fImportState)
7131 {
7132 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
7133 AssertRCReturn(rc, rc);
7134 }
7135
7136 /* Restore host FPU state if necessary. We will resync on next R0 reentry. */
7137 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7138 Assert(!CPUMIsGuestFPUStateActive(pVCpu));
7139
7140 /* Restore host debug registers if necessary. We will resync on next R0 reentry. */
7141#ifdef VBOX_STRICT
7142 if (CPUMIsHyperDebugStateActive(pVCpu))
7143 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
7144#endif
7145 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7146 Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
7147 Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
7148
7149#if HC_ARCH_BITS == 64
7150 /* Restore host-state bits that VT-x only restores partially. */
7151 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7152 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7153 {
7154 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags, idCpu));
7155 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7156 }
7157 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7158#endif
7159
7160 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7161 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
7162 {
7163 /* We shouldn't restore the host MSRs without saving the guest MSRs first. */
7164 if (!fImportState)
7165 {
7166 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS);
7167 AssertRCReturn(rc, rc);
7168 }
7169 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7170 Assert(!pVCpu->hm.s.vmx.fLazyMsrs);
7171 }
7172 else
7173 pVCpu->hm.s.vmx.fLazyMsrs = 0;
7174
7175 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7176 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7177
7178 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
7179 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
7180 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
7181 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
7182 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
7183 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
7184 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
7185 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
7186 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7187
7188 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7189
7190 /** @todo This partially defeats the purpose of having preemption hooks.
7191 * The problem is, deregistering the hooks should be moved to a place that
7192 * lasts until the EMT is about to be destroyed not everytime while leaving HM
7193 * context.
7194 */
7195 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7196 {
7197 int rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7198 AssertRCReturn(rc, rc);
7199
7200 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7201 Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
7202 }
7203 Assert(!(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED));
7204 NOREF(idCpu);
7205
7206 return VINF_SUCCESS;
7207}
7208
7209
7210/**
7211 * Leaves the VT-x session.
7212 *
7213 * @returns VBox status code.
7214 * @param pVCpu The cross context virtual CPU structure.
7215 *
7216 * @remarks No-long-jmp zone!!!
7217 */
7218static int hmR0VmxLeaveSession(PVMCPU pVCpu)
7219{
7220 HM_DISABLE_PREEMPT(pVCpu);
7221 HMVMX_ASSERT_CPU_SAFE(pVCpu);
7222 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7223 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7224
7225 /* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
7226 and done this from the VMXR0ThreadCtxCallback(). */
7227 if (!pVCpu->hm.s.fLeaveDone)
7228 {
7229 int rc2 = hmR0VmxLeave(pVCpu, true /* fImportState */);
7230 AssertRCReturnStmt(rc2, HM_RESTORE_PREEMPT(), rc2);
7231 pVCpu->hm.s.fLeaveDone = true;
7232 }
7233 Assert(!pVCpu->cpum.GstCtx.fExtrn);
7234
7235 /*
7236 * !!! IMPORTANT !!!
7237 * If you modify code here, make sure to check whether hmR0VmxCallRing3Callback() needs to be updated too.
7238 */
7239
7240 /* Deregister hook now that we've left HM context before re-enabling preemption. */
7241 /** @todo Deregistering here means we need to VMCLEAR always
7242 * (longjmp/exit-to-r3) in VT-x which is not efficient, eliminate need
7243 * for calling VMMR0ThreadCtxHookDisable here! */
7244 VMMR0ThreadCtxHookDisable(pVCpu);
7245
7246 /* Leave HM context. This takes care of local init (term). */
7247 int rc = HMR0LeaveCpu(pVCpu);
7248
7249 HM_RESTORE_PREEMPT();
7250 return rc;
7251}
7252
7253
7254/**
7255 * Does the necessary state syncing before doing a longjmp to ring-3.
7256 *
7257 * @returns VBox status code.
7258 * @param pVCpu The cross context virtual CPU structure.
7259 *
7260 * @remarks No-long-jmp zone!!!
7261 */
7262DECLINLINE(int) hmR0VmxLongJmpToRing3(PVMCPU pVCpu)
7263{
7264 return hmR0VmxLeaveSession(pVCpu);
7265}
7266
7267
7268/**
7269 * Take necessary actions before going back to ring-3.
7270 *
7271 * An action requires us to go back to ring-3. This function does the necessary
7272 * steps before we can safely return to ring-3. This is not the same as longjmps
7273 * to ring-3, this is voluntary and prepares the guest so it may continue
7274 * executing outside HM (recompiler/IEM).
7275 *
7276 * @returns VBox status code.
7277 * @param pVCpu The cross context virtual CPU structure.
7278 * @param rcExit The reason for exiting to ring-3. Can be
7279 * VINF_VMM_UNKNOWN_RING3_CALL.
7280 */
7281static int hmR0VmxExitToRing3(PVMCPU pVCpu, VBOXSTRICTRC rcExit)
7282{
7283 Assert(pVCpu);
7284 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7285
7286 if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
7287 {
7288 VMXGetActivatedVmcs(&pVCpu->hm.s.vmx.LastError.u64VMCSPhys);
7289 pVCpu->hm.s.vmx.LastError.u32VMCSRevision = *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs;
7290 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
7291 /* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
7292 }
7293
7294 /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
7295 VMMRZCallRing3Disable(pVCpu);
7296 Log4Func(("rcExit=%d\n", VBOXSTRICTRC_VAL(rcExit)));
7297
7298 /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
7299 if (pVCpu->hm.s.Event.fPending)
7300 {
7301 hmR0VmxPendingEventToTrpmTrap(pVCpu);
7302 Assert(!pVCpu->hm.s.Event.fPending);
7303 }
7304
7305 /* Clear interrupt-window and NMI-window controls as we re-evaluate it when we return from ring-3. */
7306 hmR0VmxClearIntNmiWindowsVmcs(pVCpu);
7307
7308 /* If we're emulating an instruction, we shouldn't have any TRPM traps pending
7309 and if we're injecting an event we should have a TRPM trap pending. */
7310 AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT || TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7311#ifndef DEBUG_bird /* Triggered after firing an NMI against NT4SP1, possibly a triple fault in progress. */
7312 AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR || !TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7313#endif
7314
7315 /* Save guest state and restore host state bits. */
7316 int rc = hmR0VmxLeaveSession(pVCpu);
7317 AssertRCReturn(rc, rc);
7318 STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7319 /* Thread-context hooks are unregistered at this point!!! */
7320
7321 /* Sync recompiler state. */
7322 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
7323 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
7324 | CPUM_CHANGED_LDTR
7325 | CPUM_CHANGED_GDTR
7326 | CPUM_CHANGED_IDTR
7327 | CPUM_CHANGED_TR
7328 | CPUM_CHANGED_HIDDEN_SEL_REGS);
7329 if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
7330 && CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
7331 {
7332 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
7333 }
7334
7335 Assert(!pVCpu->hm.s.fClearTrapFlag);
7336
7337 /* Update the exit-to-ring 3 reason. */
7338 pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
7339
7340 /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
7341 if (rcExit != VINF_EM_RAW_INTERRUPT)
7342 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7343
7344 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
7345
7346 /* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
7347 VMMRZCallRing3RemoveNotification(pVCpu);
7348 VMMRZCallRing3Enable(pVCpu);
7349
7350 return rc;
7351}
7352
7353
7354/**
7355 * VMMRZCallRing3() callback wrapper which saves the guest state before we
7356 * longjump to ring-3 and possibly get preempted.
7357 *
7358 * @returns VBox status code.
7359 * @param pVCpu The cross context virtual CPU structure.
7360 * @param enmOperation The operation causing the ring-3 longjump.
7361 * @param pvUser User argument, currently unused, NULL.
7362 */
7363static DECLCALLBACK(int) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
7364{
7365 RT_NOREF(pvUser);
7366 if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
7367 {
7368 /*
7369 * !!! IMPORTANT !!!
7370 * If you modify code here, check whether hmR0VmxLeave() and hmR0VmxLeaveSession() needs to be updated too.
7371 * This is a stripped down version which gets out ASAP, trying to not trigger any further assertions.
7372 */
7373 VMMRZCallRing3RemoveNotification(pVCpu);
7374 VMMRZCallRing3Disable(pVCpu);
7375 RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
7376 RTThreadPreemptDisable(&PreemptState);
7377
7378 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
7379 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7380 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7381
7382#if HC_ARCH_BITS == 64
7383 /* Restore host-state bits that VT-x only restores partially. */
7384 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7385 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7386 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7387 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7388#endif
7389
7390 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7391 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
7392 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7393
7394 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7395 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7396 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7397 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7398 {
7399 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7400 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7401 }
7402
7403 /** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7404 VMMR0ThreadCtxHookDisable(pVCpu);
7405 HMR0LeaveCpu(pVCpu);
7406 RTThreadPreemptRestore(&PreemptState);
7407 return VINF_SUCCESS;
7408 }
7409
7410 Assert(pVCpu);
7411 Assert(pvUser);
7412 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7413 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7414
7415 VMMRZCallRing3Disable(pVCpu);
7416 Assert(VMMR0IsLogFlushDisabled(pVCpu));
7417
7418 Log4Func((" -> hmR0VmxLongJmpToRing3 enmOperation=%d\n", enmOperation));
7419
7420 int rc = hmR0VmxLongJmpToRing3(pVCpu);
7421 AssertRCReturn(rc, rc);
7422
7423 VMMRZCallRing3Enable(pVCpu);
7424 return VINF_SUCCESS;
7425}
7426
7427
7428/**
7429 * Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
7430 * cause a VM-exit as soon as the guest is in a state to receive interrupts.
7431 *
7432 * @param pVCpu The cross context virtual CPU structure.
7433 */
7434DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
7435{
7436 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_INT_WINDOW_EXIT))
7437 {
7438 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
7439 {
7440 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_PROC_CTLS_INT_WINDOW_EXIT;
7441 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7442 AssertRC(rc);
7443 Log4Func(("Setup interrupt-window exiting\n"));
7444 }
7445 } /* else we will deliver interrupts whenever the guest exits next and is in a state to receive events. */
7446}
7447
7448
7449/**
7450 * Clears the interrupt-window exiting control in the VMCS.
7451 *
7452 * @param pVCpu The cross context virtual CPU structure.
7453 */
7454DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu)
7455{
7456 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
7457 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_INT_WINDOW_EXIT;
7458 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7459 AssertRC(rc);
7460 Log4Func(("Cleared interrupt-window exiting\n"));
7461}
7462
7463
7464/**
7465 * Sets the NMI-window exiting control in the VMCS which instructs VT-x to
7466 * cause a VM-exit as soon as the guest is in a state to receive NMIs.
7467 *
7468 * @param pVCpu The cross context virtual CPU structure.
7469 */
7470DECLINLINE(void) hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu)
7471{
7472 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
7473 {
7474 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
7475 {
7476 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_PROC_CTLS_NMI_WINDOW_EXIT;
7477 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7478 AssertRC(rc);
7479 Log4Func(("Setup NMI-window exiting\n"));
7480 }
7481 } /* else we will deliver NMIs whenever we VM-exit next, even possibly nesting NMIs. Can't be helped on ancient CPUs. */
7482}
7483
7484
7485/**
7486 * Clears the NMI-window exiting control in the VMCS.
7487 *
7488 * @param pVCpu The cross context virtual CPU structure.
7489 */
7490DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu)
7491{
7492 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
7493 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_NMI_WINDOW_EXIT;
7494 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7495 AssertRC(rc);
7496 Log4Func(("Cleared NMI-window exiting\n"));
7497}
7498
7499
7500/**
7501 * Evaluates the event to be delivered to the guest and sets it as the pending
7502 * event.
7503 *
7504 * @returns The VT-x guest-interruptibility state.
7505 * @param pVCpu The cross context virtual CPU structure.
7506 */
7507static uint32_t hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu)
7508{
7509 /* Get the current interruptibility-state of the guest and then figure out what can be injected. */
7510 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7511 uint32_t const fIntrState = hmR0VmxGetGuestIntrState(pVCpu);
7512 bool const fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
7513 bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
7514 bool const fBlockNmi = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI);
7515
7516 Assert(!fBlockSti || !(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_RFLAGS));
7517 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7518 Assert(!fBlockSti || pCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7519 Assert(!TRPMHasTrap(pVCpu));
7520
7521 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
7522 APICUpdatePendingInterrupts(pVCpu);
7523
7524 /*
7525 * Toggling of interrupt force-flags here is safe since we update TRPM on premature exits
7526 * to ring-3 before executing guest code, see hmR0VmxExitToRing3(). We must NOT restore these force-flags.
7527 */
7528 /** @todo SMI. SMIs take priority over NMIs. */
7529 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
7530 {
7531 /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
7532 if ( !pVCpu->hm.s.Event.fPending
7533 && !fBlockNmi
7534 && !fBlockSti
7535 && !fBlockMovSS)
7536 {
7537 Log4Func(("Pending NMI\n"));
7538 uint32_t u32IntInfo = X86_XCPT_NMI | VMX_EXIT_INT_INFO_VALID;
7539 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_NMI << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7540
7541 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7542 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
7543 }
7544 else
7545 hmR0VmxSetNmiWindowExitVmcs(pVCpu);
7546 }
7547 /*
7548 * Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
7549 * a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
7550 */
7551 else if ( VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
7552 && !pVCpu->hm.s.fSingleInstruction)
7553 {
7554 Assert(!DBGFIsStepping(pVCpu));
7555 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
7556 AssertRCReturn(rc, 0);
7557 bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
7558 if ( !pVCpu->hm.s.Event.fPending
7559 && !fBlockInt
7560 && !fBlockSti
7561 && !fBlockMovSS)
7562 {
7563 uint8_t u8Interrupt;
7564 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
7565 if (RT_SUCCESS(rc))
7566 {
7567 Log4Func(("Pending external interrupt u8Interrupt=%#x\n", u8Interrupt));
7568 uint32_t u32IntInfo = u8Interrupt
7569 | VMX_EXIT_INT_INFO_VALID
7570 | (VMX_EXIT_INT_INFO_TYPE_EXT_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7571
7572 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrfaultAddress */);
7573 }
7574 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
7575 {
7576 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7577 hmR0VmxApicSetTprThreshold(pVCpu, u8Interrupt >> 4);
7578 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
7579
7580 /*
7581 * If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
7582 * APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
7583 * need to re-set this force-flag here.
7584 */
7585 }
7586 else
7587 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
7588 }
7589 else
7590 hmR0VmxSetIntWindowExitVmcs(pVCpu);
7591 }
7592
7593 return fIntrState;
7594}
7595
7596
7597/**
7598 * Sets a pending-debug exception to be delivered to the guest if the guest is
7599 * single-stepping in the VMCS.
7600 *
7601 * @param pVCpu The cross context virtual CPU structure.
7602 */
7603DECLINLINE(int) hmR0VmxSetPendingDebugXcptVmcs(PVMCPU pVCpu)
7604{
7605 Assert(!(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_RFLAGS));
7606 RT_NOREF(pVCpu);
7607 return VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS);
7608}
7609
7610
7611/**
7612 * Injects any pending events into the guest if the guest is in a state to
7613 * receive them.
7614 *
7615 * @returns Strict VBox status code (i.e. informational status codes too).
7616 * @param pVCpu The cross context virtual CPU structure.
7617 * @param fIntrState The VT-x guest-interruptibility state.
7618 * @param fStepping Running in hmR0VmxRunGuestCodeStep() and we should
7619 * return VINF_EM_DBG_STEPPED if the event was
7620 * dispatched directly.
7621 */
7622static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPU pVCpu, uint32_t fIntrState, bool fStepping)
7623{
7624 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7625 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7626
7627 bool fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
7628 bool fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
7629
7630 Assert(!fBlockSti || !(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_RFLAGS));
7631 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7632 Assert(!fBlockSti || pVCpu->cpum.GstCtx.eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7633 Assert(!TRPMHasTrap(pVCpu));
7634
7635 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7636 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
7637 if (pVCpu->hm.s.Event.fPending)
7638 {
7639 /*
7640 * Do -not- clear any interrupt-window exiting control here. We might have an interrupt
7641 * pending even while injecting an event and in this case, we want a VM-exit as soon as
7642 * the guest is ready for the next interrupt, see @bugref{6208#c45}.
7643 *
7644 * See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
7645 */
7646 uint32_t const uIntType = VMX_EXIT_INT_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7647#ifdef VBOX_STRICT
7648 if (uIntType == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
7649 {
7650 bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
7651 Assert(!fBlockInt);
7652 Assert(!fBlockSti);
7653 Assert(!fBlockMovSS);
7654 }
7655 else if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
7656 {
7657 bool const fBlockNmi = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI);
7658 Assert(!fBlockSti);
7659 Assert(!fBlockMovSS);
7660 Assert(!fBlockNmi);
7661 }
7662#endif
7663 Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#RX32\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
7664 uIntType));
7665 rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.cbInstr,
7666 pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress, fStepping,
7667 &fIntrState);
7668 AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7669
7670 /* Update the interruptibility-state as it could have been changed by
7671 hmR0VmxInjectEventVmcs() (e.g. real-on-v86 guest injecting software interrupts) */
7672 fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
7673 fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
7674
7675 if (uIntType == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
7676 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
7677 else
7678 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
7679 }
7680
7681 /* Deliver pending debug exception if the guest is single-stepping. Evaluate and set the BS bit. */
7682 if ( fBlockSti
7683 || fBlockMovSS)
7684 {
7685 if (!pVCpu->hm.s.fSingleInstruction)
7686 {
7687 /*
7688 * The pending-debug exceptions field is cleared on all VM-exits except VMX_EXIT_TPR_BELOW_THRESHOLD,
7689 * VMX_EXIT_MTF, VMX_EXIT_APIC_WRITE and VMX_EXIT_VIRTUALIZED_EOI.
7690 * See Intel spec. 27.3.4 "Saving Non-Register State".
7691 */
7692 Assert(!DBGFIsStepping(pVCpu));
7693 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
7694 AssertRCReturn(rc, rc);
7695 if (pCtx->eflags.Bits.u1TF)
7696 {
7697 int rc2 = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
7698 AssertRCReturn(rc2, rc2);
7699 }
7700 }
7701 else if (pCtx->eflags.Bits.u1TF)
7702 {
7703 /*
7704 * We are single-stepping in the hypervisor debugger using EFLAGS.TF. Clear interrupt inhibition as setting the
7705 * BS bit would mean delivering a #DB to the guest upon VM-entry when it shouldn't be.
7706 */
7707 Assert(!(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG));
7708 fIntrState = 0;
7709 }
7710 }
7711
7712 /*
7713 * There's no need to clear the VM-entry interruption-information field here if we're not injecting anything.
7714 * VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7715 */
7716 int rc3 = hmR0VmxExportGuestIntrState(pVCpu, fIntrState);
7717 AssertRCReturn(rc3, rc3);
7718
7719 Assert(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping));
7720 NOREF(fBlockMovSS); NOREF(fBlockSti);
7721 return rcStrict;
7722}
7723
7724
7725/**
7726 * Injects a double-fault (\#DF) exception into the VM.
7727 *
7728 * @returns Strict VBox status code (i.e. informational status codes too).
7729 * @param pVCpu The cross context virtual CPU structure.
7730 * @param fStepping Whether we're running in hmR0VmxRunGuestCodeStep()
7731 * and should return VINF_EM_DBG_STEPPED if the event
7732 * is injected directly (register modified by us, not
7733 * by hardware on VM-entry).
7734 * @param pfIntrState Pointer to the current guest interruptibility-state.
7735 * This interruptibility-state will be updated if
7736 * necessary. This cannot not be NULL.
7737 */
7738DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptDF(PVMCPU pVCpu, bool fStepping, uint32_t *pfIntrState)
7739{
7740 uint32_t const u32IntInfo = X86_XCPT_DF | VMX_EXIT_INT_INFO_VALID
7741 | (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT)
7742 | VMX_EXIT_INT_INFO_ERROR_CODE_VALID;
7743 return hmR0VmxInjectEventVmcs(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */, fStepping,
7744 pfIntrState);
7745}
7746
7747
7748/**
7749 * Injects a general-protection (\#GP) fault into the VM.
7750 *
7751 * @returns Strict VBox status code (i.e. informational status codes too).
7752 * @param pVCpu The cross context virtual CPU structure.
7753 * @param fErrorCodeValid Whether the error code is valid (depends on the CPU
7754 * mode, i.e. in real-mode it's not valid).
7755 * @param u32ErrorCode The error code associated with the \#GP.
7756 * @param fStepping Whether we're running in
7757 * hmR0VmxRunGuestCodeStep() and should return
7758 * VINF_EM_DBG_STEPPED if the event is injected
7759 * directly (register modified by us, not by
7760 * hardware on VM-entry).
7761 * @param pfIntrState Pointer to the current guest interruptibility-state.
7762 * This interruptibility-state will be updated if
7763 * necessary. This cannot not be NULL.
7764 */
7765DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptGP(PVMCPU pVCpu, bool fErrorCodeValid, uint32_t u32ErrorCode, bool fStepping,
7766 uint32_t *pfIntrState)
7767{
7768 uint32_t const u32IntInfo = X86_XCPT_GP | VMX_EXIT_INT_INFO_VALID
7769 | (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT)
7770 | (fErrorCodeValid ? VMX_EXIT_INT_INFO_ERROR_CODE_VALID : 0);
7771 return hmR0VmxInjectEventVmcs(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */, fStepping,
7772 pfIntrState);
7773}
7774
7775
7776/**
7777 * Sets a software interrupt (INTn) as pending-for-injection into the VM.
7778 *
7779 * @param pVCpu The cross context virtual CPU structure.
7780 * @param uVector The software interrupt vector number.
7781 * @param cbInstr The value of RIP that is to be pushed on the guest
7782 * stack.
7783 */
7784DECLINLINE(void) hmR0VmxSetPendingIntN(PVMCPU pVCpu, uint16_t uVector, uint32_t cbInstr)
7785{
7786 bool const fIsSwXcpt = RT_BOOL(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7787 uint32_t const u32IntType = fIsSwXcpt ? VMX_EXIT_INT_INFO_TYPE_SW_XCPT : VMX_EXIT_INT_INFO_TYPE_SW_INT;
7788 uint32_t const u32IntInfo = uVector | VMX_EXIT_INT_INFO_VALID
7789 | (u32IntType << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7790 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7791}
7792
7793
7794/**
7795 * Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
7796 * stack.
7797 *
7798 * @returns Strict VBox status code (i.e. informational status codes too).
7799 * @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
7800 * @param pVCpu The cross context virtual CPU structure.
7801 * @param uValue The value to push to the guest stack.
7802 */
7803static VBOXSTRICTRC hmR0VmxRealModeGuestStackPush(PVMCPU pVCpu, uint16_t uValue)
7804{
7805 /*
7806 * The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
7807 * virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
7808 * See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
7809 */
7810 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7811 if (pCtx->sp == 1)
7812 return VINF_EM_RESET;
7813 pCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
7814 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->ss.u64Base + pCtx->sp, &uValue, sizeof(uint16_t));
7815 AssertRC(rc);
7816 return rc;
7817}
7818
7819
7820/**
7821 * Injects an event into the guest upon VM-entry by updating the relevant fields
7822 * in the VM-entry area in the VMCS.
7823 *
7824 * @returns Strict VBox status code (i.e. informational status codes too).
7825 * @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
7826 * @retval VINF_EM_RESET if event injection resulted in a triple-fault.
7827 *
7828 * @param pVCpu The cross context virtual CPU structure.
7829 * @param u64IntInfo The VM-entry interruption-information field.
7830 * @param cbInstr The VM-entry instruction length in bytes (for
7831 * software interrupts, exceptions and privileged
7832 * software exceptions).
7833 * @param u32ErrCode The VM-entry exception error code.
7834 * @param GCPtrFaultAddress The page-fault address for \#PF exceptions.
7835 * @param pfIntrState Pointer to the current guest interruptibility-state.
7836 * This interruptibility-state will be updated if
7837 * necessary. This cannot not be NULL.
7838 * @param fStepping Whether we're running in
7839 * hmR0VmxRunGuestCodeStep() and should return
7840 * VINF_EM_DBG_STEPPED if the event is injected
7841 * directly (register modified by us, not by
7842 * hardware on VM-entry).
7843 */
7844static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
7845 RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *pfIntrState)
7846{
7847 /* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
7848 AssertMsg(!RT_HI_U32(u64IntInfo), ("%#RX64\n", u64IntInfo));
7849 Assert(pfIntrState);
7850
7851 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7852 uint32_t u32IntInfo = (uint32_t)u64IntInfo;
7853 uint32_t const uVector = VMX_EXIT_INT_INFO_VECTOR(u32IntInfo);
7854 uint32_t const uIntType = VMX_EXIT_INT_INFO_TYPE(u32IntInfo);
7855
7856#ifdef VBOX_STRICT
7857 /*
7858 * Validate the error-code-valid bit for hardware exceptions.
7859 * No error codes for exceptions in real-mode.
7860 *
7861 * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
7862 */
7863 if ( uIntType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
7864 && !CPUMIsGuestInRealModeEx(pCtx))
7865 {
7866 switch (uVector)
7867 {
7868 case X86_XCPT_PF:
7869 case X86_XCPT_DF:
7870 case X86_XCPT_TS:
7871 case X86_XCPT_NP:
7872 case X86_XCPT_SS:
7873 case X86_XCPT_GP:
7874 case X86_XCPT_AC:
7875 AssertMsg(VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo),
7876 ("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
7877 RT_FALL_THRU();
7878 default:
7879 break;
7880 }
7881 }
7882#endif
7883
7884 /* Cannot inject an NMI when block-by-MOV SS is in effect. */
7885 Assert( uIntType != VMX_EXIT_INT_INFO_TYPE_NMI
7886 || !(*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
7887
7888 STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
7889
7890 /*
7891 * Hardware interrupts & exceptions cannot be delivered through the software interrupt
7892 * redirection bitmap to the real mode task in virtual-8086 mode. We must jump to the
7893 * interrupt handler in the (real-mode) guest.
7894 *
7895 * See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode".
7896 * See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
7897 */
7898 if (CPUMIsGuestInRealModeEx(pCtx)) /* CR0.PE bit changes are always intercepted, so it's up to date. */
7899 {
7900 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest)
7901 {
7902 /*
7903 * For unrestricted execution enabled CPUs running real-mode guests, we must not
7904 * set the deliver-error-code bit.
7905 *
7906 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
7907 */
7908 u32IntInfo &= ~VMX_EXIT_INT_INFO_ERROR_CODE_VALID;
7909 }
7910 else
7911 {
7912 PVM pVM = pVCpu->CTX_SUFF(pVM);
7913 Assert(PDMVmmDevHeapIsEnabled(pVM));
7914 Assert(pVM->hm.s.vmx.pRealModeTSS);
7915
7916 /* We require RIP, RSP, RFLAGS, CS, IDTR, import them. */
7917 int rc2 = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_RIP
7918 | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS);
7919 AssertRCReturn(rc2, rc2);
7920
7921 /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
7922 size_t const cbIdtEntry = sizeof(X86IDTR16);
7923 if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pCtx->idtr.cbIdt)
7924 {
7925 /* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
7926 if (uVector == X86_XCPT_DF)
7927 return VINF_EM_RESET;
7928
7929 /* If we're injecting a #GP with no valid IDT entry, inject a double-fault. */
7930 if (uVector == X86_XCPT_GP)
7931 return hmR0VmxInjectXcptDF(pVCpu, fStepping, pfIntrState);
7932
7933 /*
7934 * If we're injecting an event with no valid IDT entry, inject a #GP.
7935 * No error codes for exceptions in real-mode.
7936 *
7937 * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
7938 */
7939 return hmR0VmxInjectXcptGP(pVCpu, false /* fErrCodeValid */, 0 /* u32ErrCode */, fStepping, pfIntrState);
7940 }
7941
7942 /* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
7943 uint16_t uGuestIp = pCtx->ip;
7944 if (uIntType == VMX_EXIT_INT_INFO_TYPE_SW_XCPT)
7945 {
7946 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7947 /* #BP and #OF are both benign traps, we need to resume the next instruction. */
7948 uGuestIp = pCtx->ip + (uint16_t)cbInstr;
7949 }
7950 else if (uIntType == VMX_EXIT_INT_INFO_TYPE_SW_INT)
7951 uGuestIp = pCtx->ip + (uint16_t)cbInstr;
7952
7953 /* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
7954 X86IDTR16 IdtEntry;
7955 RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pCtx->idtr.pIdt + uVector * cbIdtEntry;
7956 rc2 = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
7957 AssertRCReturn(rc2, rc2);
7958
7959 /* Construct the stack frame for the interrupt/exception handler. */
7960 VBOXSTRICTRC rcStrict;
7961 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->eflags.u32);
7962 if (rcStrict == VINF_SUCCESS)
7963 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->cs.Sel);
7964 if (rcStrict == VINF_SUCCESS)
7965 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, uGuestIp);
7966
7967 /* Clear the required eflag bits and jump to the interrupt/exception handler. */
7968 if (rcStrict == VINF_SUCCESS)
7969 {
7970 pCtx->eflags.u32 &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
7971 pCtx->rip = IdtEntry.offSel;
7972 pCtx->cs.Sel = IdtEntry.uSel;
7973 pCtx->cs.ValidSel = IdtEntry.uSel;
7974 pCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
7975 if ( uIntType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
7976 && uVector == X86_XCPT_PF)
7977 pCtx->cr2 = GCPtrFaultAddress;
7978
7979 /* If any other guest-state bits are changed here, make sure to update
7980 hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
7981 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CS | HM_CHANGED_GUEST_CR2
7982 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
7983 | HM_CHANGED_GUEST_RSP);
7984
7985 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
7986 if (*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
7987 {
7988 Assert( uIntType != VMX_EXIT_INT_INFO_TYPE_NMI
7989 && uIntType != VMX_EXIT_INT_INFO_TYPE_EXT_INT);
7990 Log4Func(("Clearing inhibition due to STI\n"));
7991 *pfIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
7992 }
7993 Log4(("Injecting real-mode: u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x Eflags=%#x CS:EIP=%04x:%04x\n",
7994 u32IntInfo, u32ErrCode, cbInstr, pCtx->eflags.u, pCtx->cs.Sel, pCtx->eip));
7995
7996 /* The event has been truly dispatched. Mark it as no longer pending so we don't attempt to 'undo'
7997 it, if we are returning to ring-3 before executing guest code. */
7998 pVCpu->hm.s.Event.fPending = false;
7999
8000 /* Make hmR0VmxPreRunGuest() return if we're stepping since we've changed cs:rip. */
8001 if (fStepping)
8002 rcStrict = VINF_EM_DBG_STEPPED;
8003 }
8004 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8005 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8006 return rcStrict;
8007 }
8008 }
8009
8010 /* Validate. */
8011 Assert(VMX_EXIT_INT_INFO_IS_VALID(u32IntInfo)); /* Bit 31 (Valid bit) must be set by caller. */
8012 Assert(!VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(u32IntInfo)); /* Bit 12 MBZ. */
8013 Assert(!(u32IntInfo & 0x7ffff000)); /* Bits 30:12 MBZ. */
8014
8015 /* Inject. */
8016 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
8017 if (VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo))
8018 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
8019 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
8020 AssertRCReturn(rc, rc);
8021
8022 /* Update CR2. */
8023 if ( VMX_EXIT_INT_INFO_TYPE(u32IntInfo) == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
8024 && uVector == X86_XCPT_PF)
8025 pCtx->cr2 = GCPtrFaultAddress;
8026
8027 Log4(("Injecting u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x CR2=%#RX64\n", u32IntInfo, u32ErrCode, cbInstr, pCtx->cr2));
8028
8029 return VINF_SUCCESS;
8030}
8031
8032
8033/**
8034 * Clears the interrupt-window exiting control in the VMCS and if necessary
8035 * clears the current event in the VMCS as well.
8036 *
8037 * @returns VBox status code.
8038 * @param pVCpu The cross context virtual CPU structure.
8039 *
8040 * @remarks Use this function only to clear events that have not yet been
8041 * delivered to the guest but are injected in the VMCS!
8042 * @remarks No-long-jump zone!!!
8043 */
8044static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu)
8045{
8046 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
8047 {
8048 hmR0VmxClearIntWindowExitVmcs(pVCpu);
8049 Log4Func(("Cleared interrupt widow\n"));
8050 }
8051
8052 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
8053 {
8054 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
8055 Log4Func(("Cleared interrupt widow\n"));
8056 }
8057}
8058
8059
8060/**
8061 * Enters the VT-x session.
8062 *
8063 * @returns VBox status code.
8064 * @param pVCpu The cross context virtual CPU structure.
8065 * @param pHostCpu Pointer to the global CPU info struct.
8066 */
8067VMMR0DECL(int) VMXR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
8068{
8069 AssertPtr(pVCpu);
8070 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported);
8071 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8072 RT_NOREF(pHostCpu);
8073
8074 LogFlowFunc(("pVCpu=%p\n", pVCpu));
8075 Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8076 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
8077
8078#ifdef VBOX_STRICT
8079 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
8080 RTCCUINTREG uHostCR4 = ASMGetCR4();
8081 if (!(uHostCR4 & X86_CR4_VMXE))
8082 {
8083 LogRelFunc(("X86_CR4_VMXE bit in CR4 is not set!\n"));
8084 return VERR_VMX_X86_CR4_VMXE_CLEARED;
8085 }
8086#endif
8087
8088 /*
8089 * Load the VCPU's VMCS as the current (and active) one.
8090 */
8091 Assert(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR);
8092 int rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8093 if (RT_FAILURE(rc))
8094 return rc;
8095
8096 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8097 pVCpu->hm.s.fLeaveDone = false;
8098 Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8099
8100 return VINF_SUCCESS;
8101}
8102
8103
8104/**
8105 * The thread-context callback (only on platforms which support it).
8106 *
8107 * @param enmEvent The thread-context event.
8108 * @param pVCpu The cross context virtual CPU structure.
8109 * @param fGlobalInit Whether global VT-x/AMD-V init. was used.
8110 * @thread EMT(pVCpu)
8111 */
8112VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
8113{
8114 NOREF(fGlobalInit);
8115
8116 switch (enmEvent)
8117 {
8118 case RTTHREADCTXEVENT_OUT:
8119 {
8120 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8121 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8122 VMCPU_ASSERT_EMT(pVCpu);
8123
8124 /* No longjmps (logger flushes, locks) in this fragile context. */
8125 VMMRZCallRing3Disable(pVCpu);
8126 Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
8127
8128 /*
8129 * Restore host-state (FPU, debug etc.)
8130 */
8131 if (!pVCpu->hm.s.fLeaveDone)
8132 {
8133 /*
8134 * Do -not- import the guest-state here as we might already be in the middle of importing
8135 * it, esp. bad if we're holding the PGM lock, see comment in hmR0VmxImportGuestState().
8136 */
8137 hmR0VmxLeave(pVCpu, false /* fImportState */);
8138 pVCpu->hm.s.fLeaveDone = true;
8139 }
8140
8141 /* Leave HM context, takes care of local init (term). */
8142 int rc = HMR0LeaveCpu(pVCpu);
8143 AssertRC(rc); NOREF(rc);
8144
8145 /* Restore longjmp state. */
8146 VMMRZCallRing3Enable(pVCpu);
8147 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
8148 break;
8149 }
8150
8151 case RTTHREADCTXEVENT_IN:
8152 {
8153 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8154 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8155 VMCPU_ASSERT_EMT(pVCpu);
8156
8157 /* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
8158 VMMRZCallRing3Disable(pVCpu);
8159 Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
8160
8161 /* Initialize the bare minimum state required for HM. This takes care of
8162 initializing VT-x if necessary (onlined CPUs, local init etc.) */
8163 int rc = hmR0EnterCpu(pVCpu);
8164 AssertRC(rc);
8165 Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8166 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
8167
8168 /* Load the active VMCS as the current one. */
8169 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR)
8170 {
8171 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8172 AssertRC(rc); NOREF(rc);
8173 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8174 Log4Func(("Resumed: Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8175 }
8176 pVCpu->hm.s.fLeaveDone = false;
8177
8178 /* Restore longjmp state. */
8179 VMMRZCallRing3Enable(pVCpu);
8180 break;
8181 }
8182
8183 default:
8184 break;
8185 }
8186}
8187
8188
8189/**
8190 * Exports the host state into the VMCS host-state area.
8191 * Sets up the VM-exit MSR-load area.
8192 *
8193 * The CPU state will be loaded from these fields on every successful VM-exit.
8194 *
8195 * @returns VBox status code.
8196 * @param pVCpu The cross context virtual CPU structure.
8197 *
8198 * @remarks No-long-jump zone!!!
8199 */
8200static int hmR0VmxExportHostState(PVMCPU pVCpu)
8201{
8202 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8203
8204 int rc = VINF_SUCCESS;
8205 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
8206 {
8207 rc = hmR0VmxExportHostControlRegs();
8208 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8209
8210 rc = hmR0VmxExportHostSegmentRegs(pVCpu);
8211 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8212
8213 rc = hmR0VmxExportHostMsrs(pVCpu);
8214 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8215
8216 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT;
8217 }
8218 return rc;
8219}
8220
8221
8222/**
8223 * Saves the host state in the VMCS host-state.
8224 *
8225 * @returns VBox status code.
8226 * @param pVCpu The cross context virtual CPU structure.
8227 *
8228 * @remarks No-long-jump zone!!!
8229 */
8230VMMR0DECL(int) VMXR0ExportHostState(PVMCPU pVCpu)
8231{
8232 AssertPtr(pVCpu);
8233 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8234
8235 /*
8236 * Export the host state here while entering HM context.
8237 * When thread-context hooks are used, we might get preempted and have to re-save the host
8238 * state but most of the time we won't be, so do it here before we disable interrupts.
8239 */
8240 return hmR0VmxExportHostState(pVCpu);
8241}
8242
8243
8244/**
8245 * Exports the guest state into the VMCS guest-state area.
8246 *
8247 * The will typically be done before VM-entry when the guest-CPU state and the
8248 * VMCS state may potentially be out of sync.
8249 *
8250 * Sets up the VM-entry MSR-load and VM-exit MSR-store areas. Sets up the
8251 * VM-entry controls.
8252 * Sets up the appropriate VMX non-root function to execute guest code based on
8253 * the guest CPU mode.
8254 *
8255 * @returns VBox strict status code.
8256 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8257 * without unrestricted guest access and the VMMDev is not presently
8258 * mapped (e.g. EFI32).
8259 *
8260 * @param pVCpu The cross context virtual CPU structure.
8261 *
8262 * @remarks No-long-jump zone!!!
8263 */
8264static VBOXSTRICTRC hmR0VmxExportGuestState(PVMCPU pVCpu)
8265{
8266 AssertPtr(pVCpu);
8267 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8268
8269 LogFlowFunc(("pVCpu=%p\n", pVCpu));
8270
8271 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
8272
8273 /* Determine real-on-v86 mode. */
8274 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
8275 if ( !pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest
8276 && CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx))
8277 {
8278 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
8279 }
8280
8281 /*
8282 * Any ordering dependency among the sub-functions below must be explicitly stated using comments.
8283 * Ideally, assert that the cross-dependent bits are up-to-date at the point of using it.
8284 */
8285 int rc = hmR0VmxSelectVMRunHandler(pVCpu);
8286 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8287
8288 /* This needs to be done after hmR0VmxSelectVMRunHandler() as changing pfnStartVM may require VM-entry control updates. */
8289 rc = hmR0VmxExportGuestEntryCtls(pVCpu);
8290 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8291
8292 /* This needs to be done after hmR0VmxSelectVMRunHandler() as changing pfnStartVM may require VM-exit control updates. */
8293 rc = hmR0VmxExportGuestExitCtls(pVCpu);
8294 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8295
8296 rc = hmR0VmxExportGuestCR0(pVCpu);
8297 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8298
8299 VBOXSTRICTRC rcStrict = hmR0VmxExportGuestCR3AndCR4(pVCpu);
8300 if (rcStrict == VINF_SUCCESS)
8301 { /* likely */ }
8302 else
8303 {
8304 Assert(rcStrict == VINF_EM_RESCHEDULE_REM || RT_FAILURE_NP(rcStrict));
8305 return rcStrict;
8306 }
8307
8308 rc = hmR0VmxExportGuestSegmentRegs(pVCpu);
8309 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8310
8311 /* This needs to be done after hmR0VmxExportGuestEntryCtls() and hmR0VmxExportGuestExitCtls() as it
8312 may alter controls if we determine we don't have to swap EFER after all. */
8313 rc = hmR0VmxExportGuestMsrs(pVCpu);
8314 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8315
8316 rc = hmR0VmxExportGuestApicTpr(pVCpu);
8317 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8318
8319 rc = hmR0VmxExportGuestXcptIntercepts(pVCpu);
8320 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8321
8322 /* Exporting RFLAGS here is fine, even though RFLAGS.TF might depend on guest debug state which is
8323 not exported here. It is re-evaluated and updated if necessary in hmR0VmxExportSharedState(). */
8324 rc = hmR0VmxExportGuestRip(pVCpu);
8325 rc |= hmR0VmxExportGuestRsp(pVCpu);
8326 rc |= hmR0VmxExportGuestRflags(pVCpu);
8327 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8328
8329 /* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
8330 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( (HM_CHANGED_GUEST_GPRS_MASK & ~HM_CHANGED_GUEST_RSP)
8331 | HM_CHANGED_GUEST_CR2
8332 | (HM_CHANGED_GUEST_DR_MASK & ~HM_CHANGED_GUEST_DR7)
8333 | HM_CHANGED_GUEST_X87
8334 | HM_CHANGED_GUEST_SSE_AVX
8335 | HM_CHANGED_GUEST_OTHER_XSAVE
8336 | HM_CHANGED_GUEST_XCRx
8337 | HM_CHANGED_GUEST_KERNEL_GS_BASE /* Part of lazy or auto load-store MSRs. */
8338 | HM_CHANGED_GUEST_SYSCALL_MSRS /* Part of lazy or auto load-store MSRs. */
8339 | HM_CHANGED_GUEST_TSC_AUX
8340 | HM_CHANGED_GUEST_OTHER_MSRS
8341 | HM_CHANGED_GUEST_HWVIRT
8342 | (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_VMX_MASK)));
8343
8344 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
8345 return rc;
8346}
8347
8348
8349/**
8350 * Exports the state shared between the host and guest into the VMCS.
8351 *
8352 * @param pVCpu The cross context virtual CPU structure.
8353 *
8354 * @remarks No-long-jump zone!!!
8355 */
8356static void hmR0VmxExportSharedState(PVMCPU pVCpu)
8357{
8358 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8359 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8360
8361 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
8362 {
8363 int rc = hmR0VmxExportSharedDebugState(pVCpu);
8364 AssertRC(rc);
8365 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
8366
8367 /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
8368 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_RFLAGS)
8369 {
8370 rc = hmR0VmxExportGuestRflags(pVCpu);
8371 AssertRC(rc);
8372 }
8373 }
8374
8375 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_GUEST_LAZY_MSRS)
8376 {
8377 hmR0VmxLazyLoadGuestMsrs(pVCpu);
8378 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_VMX_GUEST_LAZY_MSRS;
8379 }
8380
8381 AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE),
8382 ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
8383}
8384
8385
8386/**
8387 * Worker for loading the guest-state bits in the inner VT-x execution loop.
8388 *
8389 * @returns Strict VBox status code (i.e. informational status codes too).
8390 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8391 * without unrestricted guest access and the VMMDev is not presently
8392 * mapped (e.g. EFI32).
8393 *
8394 * @param pVCpu The cross context virtual CPU structure.
8395 *
8396 * @remarks No-long-jump zone!!!
8397 */
8398static VBOXSTRICTRC hmR0VmxExportGuestStateOptimal(PVMCPU pVCpu)
8399{
8400 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8401 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8402 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8403
8404#ifdef HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
8405 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
8406#endif
8407
8408 /*
8409 * For many exits it's only RIP that changes and hence try to export it first
8410 * without going through a lot of change flag checks.
8411 */
8412 VBOXSTRICTRC rcStrict;
8413 uint64_t fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
8414 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
8415 if ((fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)) == HM_CHANGED_GUEST_RIP)
8416 {
8417 rcStrict = hmR0VmxExportGuestRip(pVCpu);
8418 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8419 { /* likely */}
8420 else
8421 AssertMsgFailedReturn(("hmR0VmxExportGuestRip failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
8422 STAM_COUNTER_INC(&pVCpu->hm.s.StatExportMinimal);
8423 }
8424 else if (fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8425 {
8426 rcStrict = hmR0VmxExportGuestState(pVCpu);
8427 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8428 { /* likely */}
8429 else
8430 {
8431 AssertMsg(rcStrict == VINF_EM_RESCHEDULE_REM, ("hmR0VmxExportGuestState failed! rc=%Rrc\n",
8432 VBOXSTRICTRC_VAL(rcStrict)));
8433 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8434 return rcStrict;
8435 }
8436 STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
8437 }
8438 else
8439 rcStrict = VINF_SUCCESS;
8440
8441#ifdef VBOX_STRICT
8442 /* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
8443 fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
8444 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
8445 AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)),
8446 ("fCtxChanged=%#RX64\n", fCtxChanged));
8447#endif
8448 return rcStrict;
8449}
8450
8451
8452/**
8453 * Does the preparations before executing guest code in VT-x.
8454 *
8455 * This may cause longjmps to ring-3 and may even result in rescheduling to the
8456 * recompiler/IEM. We must be cautious what we do here regarding committing
8457 * guest-state information into the VMCS assuming we assuredly execute the
8458 * guest in VT-x mode.
8459 *
8460 * If we fall back to the recompiler/IEM after updating the VMCS and clearing
8461 * the common-state (TRPM/forceflags), we must undo those changes so that the
8462 * recompiler/IEM can (and should) use them when it resumes guest execution.
8463 * Otherwise such operations must be done when we can no longer exit to ring-3.
8464 *
8465 * @returns Strict VBox status code (i.e. informational status codes too).
8466 * @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
8467 * have been disabled.
8468 * @retval VINF_EM_RESET if a triple-fault occurs while injecting a
8469 * double-fault into the guest.
8470 * @retval VINF_EM_DBG_STEPPED if @a fStepping is true and an event was
8471 * dispatched directly.
8472 * @retval VINF_* scheduling changes, we have to go back to ring-3.
8473 *
8474 * @param pVCpu The cross context virtual CPU structure.
8475 * @param pVmxTransient Pointer to the VMX transient structure.
8476 * @param fStepping Set if called from hmR0VmxRunGuestCodeStep(). Makes
8477 * us ignore some of the reasons for returning to
8478 * ring-3, and return VINF_EM_DBG_STEPPED if event
8479 * dispatching took place.
8480 */
8481static VBOXSTRICTRC hmR0VmxPreRunGuest(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, bool fStepping)
8482{
8483 Assert(VMMRZCallRing3IsEnabled(pVCpu));
8484
8485#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_ONLY_IN_IEM
8486 Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
8487 return VINF_EM_RESCHEDULE_REM;
8488#endif
8489
8490#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
8491 PGMRZDynMapFlushAutoSet(pVCpu);
8492#endif
8493
8494 /* Check force flag actions that might require us to go back to ring-3. */
8495 VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVCpu, fStepping);
8496 if (rcStrict == VINF_SUCCESS)
8497 { /* FFs doesn't get set all the time. */ }
8498 else
8499 return rcStrict;
8500
8501 /*
8502 * Setup the virtualized-APIC accesses.
8503 *
8504 * Note! This can cause a longjumps to R3 due to the acquisition of the PGM lock
8505 * in both PGMHandlerPhysicalReset() and IOMMMIOMapMMIOHCPage(), see @bugref{8721}.
8506 *
8507 * This is the reason we do it here and not in hmR0VmxExportGuestState().
8508 */
8509 PVM pVM = pVCpu->CTX_SUFF(pVM);
8510 if ( !pVCpu->hm.s.vmx.u64MsrApicBase
8511 && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
8512 && PDMHasApic(pVM))
8513 {
8514 uint64_t const u64MsrApicBase = APICGetBaseMsrNoCheck(pVCpu);
8515 Assert(u64MsrApicBase);
8516 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
8517
8518 RTGCPHYS const GCPhysApicBase = u64MsrApicBase & PAGE_BASE_GC_MASK;
8519
8520 /* Unalias any existing mapping. */
8521 int rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
8522 AssertRCReturn(rc, rc);
8523
8524 /* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */
8525 Log4Func(("Mapped HC APIC-access page at %#RGp\n", GCPhysApicBase));
8526 rc = IOMMMIOMapMMIOHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
8527 AssertRCReturn(rc, rc);
8528
8529 /* Update the per-VCPU cache of the APIC base MSR. */
8530 pVCpu->hm.s.vmx.u64MsrApicBase = u64MsrApicBase;
8531 }
8532
8533 if (TRPMHasTrap(pVCpu))
8534 hmR0VmxTrpmTrapToPendingEvent(pVCpu);
8535 uint32_t fIntrState = hmR0VmxEvaluatePendingEvent(pVCpu);
8536
8537 /*
8538 * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus
8539 * needs to be done with longjmps or interrupts + preemption enabled. Event injection might
8540 * also result in triple-faulting the VM.
8541 */
8542 rcStrict = hmR0VmxInjectPendingEvent(pVCpu, fIntrState, fStepping);
8543 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8544 { /* likely */ }
8545 else
8546 {
8547 AssertMsg(rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8548 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8549 return rcStrict;
8550 }
8551
8552 /*
8553 * A longjump might result in importing CR3 even for VM-exits that don't necessarily
8554 * import CR3 themselves. We will need to update them here, as even as late as the above
8555 * hmR0VmxInjectPendingEvent() call may lazily import guest-CPU state on demand causing
8556 * the below force flags to be set.
8557 */
8558 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
8559 {
8560 Assert(!(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_CR3));
8561 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
8562 AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
8563 ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
8564 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
8565 }
8566 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
8567 {
8568 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
8569 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
8570 }
8571
8572 /*
8573 * No longjmps to ring-3 from this point on!!!
8574 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
8575 * This also disables flushing of the R0-logger instance (if any).
8576 */
8577 VMMRZCallRing3Disable(pVCpu);
8578
8579 /*
8580 * Export the guest state bits.
8581 *
8582 * We cannot perform longjmps while loading the guest state because we do not preserve the
8583 * host/guest state (although the VMCS will be preserved) across longjmps which can cause
8584 * CPU migration.
8585 *
8586 * If we are injecting events to a real-on-v86 mode guest, we will have to update
8587 * RIP and some segment registers, i.e. hmR0VmxInjectPendingEvent()->hmR0VmxInjectEventVmcs().
8588 * Hence, loading of the guest state needs to be done -after- injection of events.
8589 */
8590 rcStrict = hmR0VmxExportGuestStateOptimal(pVCpu);
8591 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8592 { /* likely */ }
8593 else
8594 {
8595 VMMRZCallRing3Enable(pVCpu);
8596 return rcStrict;
8597 }
8598
8599 /*
8600 * We disable interrupts so that we don't miss any interrupts that would flag preemption
8601 * (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
8602 * preemption disabled for a while. Since this is purly to aid the
8603 * RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
8604 * disable interrupt on NT.
8605 *
8606 * We need to check for force-flags that could've possible been altered since we last
8607 * checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
8608 * see @bugref{6398}).
8609 *
8610 * We also check a couple of other force-flags as a last opportunity to get the EMT back
8611 * to ring-3 before executing guest code.
8612 */
8613 pVmxTransient->fEFlags = ASMIntDisableFlags();
8614
8615 if ( ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
8616 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
8617 || ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */
8618 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT))) )
8619 {
8620 if (!RTThreadPreemptIsPending(NIL_RTTHREAD))
8621 {
8622 pVCpu->hm.s.Event.fPending = false;
8623
8624 /*
8625 * We've injected any pending events. This is really the point of no return (to ring-3).
8626 *
8627 * Note! The caller expects to continue with interrupts & longjmps disabled on successful
8628 * returns from this function, so don't enable them here.
8629 */
8630 return VINF_SUCCESS;
8631 }
8632
8633 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
8634 rcStrict = VINF_EM_RAW_INTERRUPT;
8635 }
8636 else
8637 {
8638 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
8639 rcStrict = VINF_EM_RAW_TO_R3;
8640 }
8641
8642 ASMSetFlags(pVmxTransient->fEFlags);
8643 VMMRZCallRing3Enable(pVCpu);
8644
8645 return rcStrict;
8646}
8647
8648
8649/**
8650 * Prepares to run guest code in VT-x and we've committed to doing so. This
8651 * means there is no backing out to ring-3 or anywhere else at this
8652 * point.
8653 *
8654 * @param pVCpu The cross context virtual CPU structure.
8655 * @param pVmxTransient Pointer to the VMX transient structure.
8656 *
8657 * @remarks Called with preemption disabled.
8658 * @remarks No-long-jump zone!!!
8659 */
8660static void hmR0VmxPreRunGuestCommitted(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
8661{
8662 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8663 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8664 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8665
8666 /*
8667 * Indicate start of guest execution and where poking EMT out of guest-context is recognized.
8668 */
8669 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8670 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
8671
8672 PVM pVM = pVCpu->CTX_SUFF(pVM);
8673 if (!CPUMIsGuestFPUStateActive(pVCpu))
8674 {
8675 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
8676 if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
8677 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT;
8678 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
8679 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
8680 }
8681
8682 /*
8683 * Lazy-update of the host MSRs values in the auto-load/store MSR area.
8684 */
8685 if ( !pVCpu->hm.s.vmx.fUpdatedHostMsrs
8686 && pVCpu->hm.s.vmx.cMsrs > 0)
8687 hmR0VmxUpdateAutoLoadStoreHostMsrs(pVCpu);
8688
8689 /*
8690 * Re-save the host state bits as we may've been preempted (only happens when
8691 * thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
8692 * Note that the 64-on-32 switcher saves the (64-bit) host state into the VMCS and
8693 * if we change the switcher back to 32-bit, we *must* save the 32-bit host state here.
8694 * See @bugref{8432}.
8695 */
8696 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
8697 {
8698 int rc = hmR0VmxExportHostState(pVCpu);
8699 AssertRC(rc);
8700 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreemptExportHostState);
8701 }
8702 Assert(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT));
8703
8704 /*
8705 * Export the state shared between host and guest (FPU, debug, lazy MSRs).
8706 */
8707 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)
8708 hmR0VmxExportSharedState(pVCpu);
8709 AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
8710
8711 /* Store status of the shared guest-host state at the time of VM-entry. */
8712#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
8713 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
8714 {
8715 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
8716 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
8717 }
8718 else
8719#endif
8720 {
8721 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
8722 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
8723 }
8724
8725 /*
8726 * Cache the TPR-shadow for checking on every VM-exit if it might have changed.
8727 */
8728 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
8729 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR];
8730
8731 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
8732 RTCPUID idCurrentCpu = pCpu->idCpu;
8733 if ( pVmxTransient->fUpdateTscOffsettingAndPreemptTimer
8734 || idCurrentCpu != pVCpu->hm.s.idLastCpu)
8735 {
8736 hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVCpu);
8737 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
8738 }
8739
8740 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
8741 hmR0VmxFlushTaggedTlb(pVCpu, pCpu); /* Invalidate the appropriate guest entries from the TLB. */
8742 Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
8743 pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Update the error reporting info. with the current host CPU. */
8744
8745 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
8746
8747 TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
8748 to start executing. */
8749
8750 /*
8751 * Load the TSC_AUX MSR when we are not intercepting RDTSCP.
8752 */
8753 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_RDTSCP)
8754 {
8755 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
8756 {
8757 bool fMsrUpdated;
8758 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
8759 int rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, CPUMGetGuestTscAux(pVCpu), true /* fUpdateHostMsr */,
8760 &fMsrUpdated);
8761 AssertRC(rc2);
8762 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8763 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8764 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8765 }
8766 else
8767 {
8768 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX);
8769 Assert(!pVCpu->hm.s.vmx.cMsrs || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8770 }
8771 }
8772
8773 if (pVM->cpum.ro.GuestFeatures.fIbrs)
8774 {
8775 bool fMsrUpdated;
8776 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_OTHER_MSRS);
8777 int rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_IA32_SPEC_CTRL, CPUMGetGuestSpecCtrl(pVCpu), true /* fUpdateHostMsr */,
8778 &fMsrUpdated);
8779 AssertRC(rc2);
8780 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8781 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8782 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8783 }
8784
8785#ifdef VBOX_STRICT
8786 hmR0VmxCheckAutoLoadStoreMsrs(pVCpu);
8787 hmR0VmxCheckHostEferMsr(pVCpu);
8788 AssertRC(hmR0VmxCheckVmcsCtls(pVCpu));
8789#endif
8790#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
8791 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
8792 {
8793 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu);
8794 if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
8795 Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
8796 }
8797#endif
8798}
8799
8800
8801/**
8802 * Performs some essential restoration of state after running guest code in
8803 * VT-x.
8804 *
8805 * @param pVCpu The cross context virtual CPU structure.
8806 * @param pVmxTransient Pointer to the VMX transient structure.
8807 * @param rcVMRun Return code of VMLAUNCH/VMRESUME.
8808 *
8809 * @remarks Called with interrupts disabled, and returns with interrupts enabled!
8810 *
8811 * @remarks No-long-jump zone!!! This function will however re-enable longjmps
8812 * unconditionally when it is safe to do so.
8813 */
8814static void hmR0VmxPostRunGuest(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, int rcVMRun)
8815{
8816 uint64_t const uHostTsc = ASMReadTSC();
8817 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8818
8819 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
8820 ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
8821 pVCpu->hm.s.fCtxChanged = 0; /* Exits/longjmps to ring-3 requires saving the guest state. */
8822 pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
8823 pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
8824 pVmxTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
8825
8826 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
8827 TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVCpu->hm.s.vmx.u64TscOffset);
8828
8829 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
8830 TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
8831 Assert(!ASMIntAreEnabled());
8832 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8833
8834#if HC_ARCH_BITS == 64
8835 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_REQUIRED; /* Host state messed up by VT-x, we must restore. */
8836#endif
8837#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
8838 /* The 64-on-32 switcher maintains uVmcsState on its own and we need to leave it alone here. */
8839 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
8840 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8841#else
8842 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8843#endif
8844#ifdef VBOX_STRICT
8845 hmR0VmxCheckHostEferMsr(pVCpu); /* Verify that VMRUN/VMLAUNCH didn't modify host EFER. */
8846#endif
8847 ASMSetFlags(pVmxTransient->fEFlags); /* Enable interrupts. */
8848
8849 /* Save the basic VM-exit reason. Refer Intel spec. 24.9.1 "Basic VM-exit Information". */
8850 uint32_t uExitReason;
8851 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
8852 rc |= hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
8853 AssertRC(rc);
8854 pVmxTransient->uExitReason = (uint16_t)VMX_EXIT_REASON_BASIC(uExitReason);
8855 pVmxTransient->fVMEntryFailed = VMX_ENTRY_INT_INFO_IS_VALID(pVmxTransient->uEntryIntInfo);
8856
8857 if (rcVMRun == VINF_SUCCESS)
8858 {
8859 /*
8860 * Update the VM-exit history array here even if the VM-entry failed due to:
8861 * - Invalid guest state.
8862 * - MSR loading.
8863 * - Machine-check event.
8864 *
8865 * In any of the above cases we will still have a "valid" VM-exit reason
8866 * despite @a fVMEntryFailed being false.
8867 *
8868 * See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
8869 *
8870 * Note! We don't have CS or RIP at this point. Will probably address that later
8871 * by amending the history entry added here.
8872 */
8873 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_VMX, pVmxTransient->uExitReason & EMEXIT_F_TYPE_MASK),
8874 UINT64_MAX, uHostTsc);
8875
8876 if (!pVmxTransient->fVMEntryFailed)
8877 {
8878 VMMRZCallRing3Enable(pVCpu);
8879
8880 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
8881 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
8882
8883#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) || defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
8884 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
8885 AssertRC(rc);
8886#elif defined(HMVMX_ALWAYS_SAVE_GUEST_RFLAGS)
8887 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_RFLAGS);
8888 AssertRC(rc);
8889#else
8890 /*
8891 * Import the guest-interruptibility state always as we need it while evaluating
8892 * injecting events on re-entry.
8893 *
8894 * We don't import CR0 (when Unrestricted guest execution is unavailable) despite
8895 * checking for real-mode while exporting the state because all bits that cause
8896 * mode changes wrt CR0 are intercepted.
8897 */
8898 rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_HM_VMX_INT_STATE);
8899 AssertRC(rc);
8900#endif
8901
8902 /*
8903 * Sync the TPR shadow with our APIC state.
8904 */
8905 if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
8906 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR])
8907 {
8908 rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]);
8909 AssertRC(rc);
8910 ASMAtomicOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
8911 }
8912
8913 return;
8914 }
8915 }
8916 else
8917 Log4Func(("VM-entry failure: rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", rcVMRun, pVmxTransient->fVMEntryFailed));
8918
8919 VMMRZCallRing3Enable(pVCpu);
8920}
8921
8922
8923/**
8924 * Runs the guest code using VT-x the normal way.
8925 *
8926 * @returns VBox status code.
8927 * @param pVCpu The cross context virtual CPU structure.
8928 *
8929 * @note Mostly the same as hmR0VmxRunGuestCodeStep().
8930 */
8931static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVMCPU pVCpu)
8932{
8933 VMXTRANSIENT VmxTransient;
8934 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
8935 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
8936 uint32_t cLoops = 0;
8937
8938 for (;; cLoops++)
8939 {
8940 Assert(!HMR0SuspendPending());
8941 HMVMX_ASSERT_CPU_SAFE(pVCpu);
8942
8943 /* Preparatory work for running guest code, this may force us to return
8944 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
8945 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
8946 rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, false /* fStepping */);
8947 if (rcStrict != VINF_SUCCESS)
8948 break;
8949
8950 hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
8951 int rcRun = hmR0VmxRunGuest(pVCpu);
8952
8953 /* Restore any residual host-state and save any bits shared between host
8954 and guest into the guest-CPU state. Re-enables interrupts! */
8955 hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
8956
8957 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
8958 if (RT_SUCCESS(rcRun))
8959 { /* very likely */ }
8960 else
8961 {
8962 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
8963 hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
8964 return rcRun;
8965 }
8966
8967 /* Profile the VM-exit. */
8968 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
8969 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
8970 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
8971 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
8972 HMVMX_START_EXIT_DISPATCH_PROF();
8973
8974 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
8975
8976 /* Handle the VM-exit. */
8977#ifdef HMVMX_USE_FUNCTION_TABLE
8978 rcStrict = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, &VmxTransient);
8979#else
8980 rcStrict = hmR0VmxHandleExit(pVCpu, &VmxTransient, VmxTransient.uExitReason);
8981#endif
8982 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
8983 if (rcStrict == VINF_SUCCESS)
8984 {
8985 if (cLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
8986 continue; /* likely */
8987 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
8988 rcStrict = VINF_EM_RAW_INTERRUPT;
8989 }
8990 break;
8991 }
8992
8993 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
8994 return rcStrict;
8995}
8996
8997
8998
8999/** @name Execution loop for single stepping, DBGF events and expensive Dtrace
9000 * probes.
9001 *
9002 * The following few functions and associated structure contains the bloat
9003 * necessary for providing detailed debug events and dtrace probes as well as
9004 * reliable host side single stepping. This works on the principle of
9005 * "subclassing" the normal execution loop and workers. We replace the loop
9006 * method completely and override selected helpers to add necessary adjustments
9007 * to their core operation.
9008 *
9009 * The goal is to keep the "parent" code lean and mean, so as not to sacrifice
9010 * any performance for debug and analysis features.
9011 *
9012 * @{
9013 */
9014
9015/**
9016 * Transient per-VCPU debug state of VMCS and related info. we save/restore in
9017 * the debug run loop.
9018 */
9019typedef struct VMXRUNDBGSTATE
9020{
9021 /** The RIP we started executing at. This is for detecting that we stepped. */
9022 uint64_t uRipStart;
9023 /** The CS we started executing with. */
9024 uint16_t uCsStart;
9025
9026 /** Whether we've actually modified the 1st execution control field. */
9027 bool fModifiedProcCtls : 1;
9028 /** Whether we've actually modified the 2nd execution control field. */
9029 bool fModifiedProcCtls2 : 1;
9030 /** Whether we've actually modified the exception bitmap. */
9031 bool fModifiedXcptBitmap : 1;
9032
9033 /** We desire the modified the CR0 mask to be cleared. */
9034 bool fClearCr0Mask : 1;
9035 /** We desire the modified the CR4 mask to be cleared. */
9036 bool fClearCr4Mask : 1;
9037 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC. */
9038 uint32_t fCpe1Extra;
9039 /** Stuff we do not want in VMX_VMCS32_CTRL_PROC_EXEC. */
9040 uint32_t fCpe1Unwanted;
9041 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC2. */
9042 uint32_t fCpe2Extra;
9043 /** Extra stuff we need in VMX_VMCS32_CTRL_EXCEPTION_BITMAP. */
9044 uint32_t bmXcptExtra;
9045 /** The sequence number of the Dtrace provider settings the state was
9046 * configured against. */
9047 uint32_t uDtraceSettingsSeqNo;
9048 /** VM-exits to check (one bit per VM-exit). */
9049 uint32_t bmExitsToCheck[3];
9050
9051 /** The initial VMX_VMCS32_CTRL_PROC_EXEC value (helps with restore). */
9052 uint32_t fProcCtlsInitial;
9053 /** The initial VMX_VMCS32_CTRL_PROC_EXEC2 value (helps with restore). */
9054 uint32_t fProcCtls2Initial;
9055 /** The initial VMX_VMCS32_CTRL_EXCEPTION_BITMAP value (helps with restore). */
9056 uint32_t bmXcptInitial;
9057} VMXRUNDBGSTATE;
9058AssertCompileMemberSize(VMXRUNDBGSTATE, bmExitsToCheck, (VMX_EXIT_MAX + 1 + 31) / 32 * 4);
9059typedef VMXRUNDBGSTATE *PVMXRUNDBGSTATE;
9060
9061
9062/**
9063 * Initializes the VMXRUNDBGSTATE structure.
9064 *
9065 * @param pVCpu The cross context virtual CPU structure of the
9066 * calling EMT.
9067 * @param pDbgState The structure to initialize.
9068 */
9069static void hmR0VmxRunDebugStateInit(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9070{
9071 pDbgState->uRipStart = pVCpu->cpum.GstCtx.rip;
9072 pDbgState->uCsStart = pVCpu->cpum.GstCtx.cs.Sel;
9073
9074 pDbgState->fModifiedProcCtls = false;
9075 pDbgState->fModifiedProcCtls2 = false;
9076 pDbgState->fModifiedXcptBitmap = false;
9077 pDbgState->fClearCr0Mask = false;
9078 pDbgState->fClearCr4Mask = false;
9079 pDbgState->fCpe1Extra = 0;
9080 pDbgState->fCpe1Unwanted = 0;
9081 pDbgState->fCpe2Extra = 0;
9082 pDbgState->bmXcptExtra = 0;
9083 pDbgState->fProcCtlsInitial = pVCpu->hm.s.vmx.u32ProcCtls;
9084 pDbgState->fProcCtls2Initial = pVCpu->hm.s.vmx.u32ProcCtls2;
9085 pDbgState->bmXcptInitial = pVCpu->hm.s.vmx.u32XcptBitmap;
9086}
9087
9088
9089/**
9090 * Updates the VMSC fields with changes requested by @a pDbgState.
9091 *
9092 * This is performed after hmR0VmxPreRunGuestDebugStateUpdate as well
9093 * immediately before executing guest code, i.e. when interrupts are disabled.
9094 * We don't check status codes here as we cannot easily assert or return in the
9095 * latter case.
9096 *
9097 * @param pVCpu The cross context virtual CPU structure.
9098 * @param pDbgState The debug state.
9099 */
9100static void hmR0VmxPreRunGuestDebugStateApply(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9101{
9102 /*
9103 * Ensure desired flags in VMCS control fields are set.
9104 * (Ignoring write failure here, as we're committed and it's just debug extras.)
9105 *
9106 * Note! We load the shadow CR0 & CR4 bits when we flag the clearing, so
9107 * there should be no stale data in pCtx at this point.
9108 */
9109 if ( (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Extra) != pDbgState->fCpe1Extra
9110 || (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Unwanted))
9111 {
9112 pVCpu->hm.s.vmx.u32ProcCtls |= pDbgState->fCpe1Extra;
9113 pVCpu->hm.s.vmx.u32ProcCtls &= ~pDbgState->fCpe1Unwanted;
9114 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
9115 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls));
9116 pDbgState->fModifiedProcCtls = true;
9117 }
9118
9119 if ((pVCpu->hm.s.vmx.u32ProcCtls2 & pDbgState->fCpe2Extra) != pDbgState->fCpe2Extra)
9120 {
9121 pVCpu->hm.s.vmx.u32ProcCtls2 |= pDbgState->fCpe2Extra;
9122 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVCpu->hm.s.vmx.u32ProcCtls2);
9123 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls2));
9124 pDbgState->fModifiedProcCtls2 = true;
9125 }
9126
9127 if ((pVCpu->hm.s.vmx.u32XcptBitmap & pDbgState->bmXcptExtra) != pDbgState->bmXcptExtra)
9128 {
9129 pVCpu->hm.s.vmx.u32XcptBitmap |= pDbgState->bmXcptExtra;
9130 VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
9131 Log6Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVCpu->hm.s.vmx.u32XcptBitmap));
9132 pDbgState->fModifiedXcptBitmap = true;
9133 }
9134
9135 if (pDbgState->fClearCr0Mask && pVCpu->hm.s.vmx.u32Cr0Mask != 0)
9136 {
9137 pVCpu->hm.s.vmx.u32Cr0Mask = 0;
9138 VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, 0);
9139 Log6Func(("VMX_VMCS_CTRL_CR0_MASK: 0\n"));
9140 }
9141
9142 if (pDbgState->fClearCr4Mask && pVCpu->hm.s.vmx.u32Cr4Mask != 0)
9143 {
9144 pVCpu->hm.s.vmx.u32Cr4Mask = 0;
9145 VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, 0);
9146 Log6Func(("VMX_VMCS_CTRL_CR4_MASK: 0\n"));
9147 }
9148}
9149
9150
9151/**
9152 * Restores VMCS fields that were changed by hmR0VmxPreRunGuestDebugStateApply for
9153 * re-entry next time around.
9154 *
9155 * @returns Strict VBox status code (i.e. informational status codes too).
9156 * @param pVCpu The cross context virtual CPU structure.
9157 * @param pDbgState The debug state.
9158 * @param rcStrict The return code from executing the guest using single
9159 * stepping.
9160 */
9161static VBOXSTRICTRC hmR0VmxRunDebugStateRevert(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, VBOXSTRICTRC rcStrict)
9162{
9163 /*
9164 * Restore VM-exit control settings as we may not reenter this function the
9165 * next time around.
9166 */
9167 /* We reload the initial value, trigger what we can of recalculations the
9168 next time around. From the looks of things, that's all that's required atm. */
9169 if (pDbgState->fModifiedProcCtls)
9170 {
9171 if (!(pDbgState->fProcCtlsInitial & VMX_PROC_CTLS_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
9172 pDbgState->fProcCtlsInitial |= VMX_PROC_CTLS_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
9173 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
9174 AssertRCReturn(rc2, rc2);
9175 pVCpu->hm.s.vmx.u32ProcCtls = pDbgState->fProcCtlsInitial;
9176 }
9177
9178 /* We're currently the only ones messing with this one, so just restore the
9179 cached value and reload the field. */
9180 if ( pDbgState->fModifiedProcCtls2
9181 && pVCpu->hm.s.vmx.u32ProcCtls2 != pDbgState->fProcCtls2Initial)
9182 {
9183 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);
9184 AssertRCReturn(rc2, rc2);
9185 pVCpu->hm.s.vmx.u32ProcCtls2 = pDbgState->fProcCtls2Initial;
9186 }
9187
9188 /* If we've modified the exception bitmap, we restore it and trigger
9189 reloading and partial recalculation the next time around. */
9190 if (pDbgState->fModifiedXcptBitmap)
9191 pVCpu->hm.s.vmx.u32XcptBitmap = pDbgState->bmXcptInitial;
9192
9193 return rcStrict;
9194}
9195
9196
9197/**
9198 * Configures VM-exit controls for current DBGF and DTrace settings.
9199 *
9200 * This updates @a pDbgState and the VMCS execution control fields to reflect
9201 * the necessary VM-exits demanded by DBGF and DTrace.
9202 *
9203 * @param pVCpu The cross context virtual CPU structure.
9204 * @param pDbgState The debug state.
9205 * @param pVmxTransient Pointer to the VMX transient structure. May update
9206 * fUpdateTscOffsettingAndPreemptTimer.
9207 */
9208static void hmR0VmxPreRunGuestDebugStateUpdate(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, PVMXTRANSIENT pVmxTransient)
9209{
9210 /*
9211 * Take down the dtrace serial number so we can spot changes.
9212 */
9213 pDbgState->uDtraceSettingsSeqNo = VBOXVMM_GET_SETTINGS_SEQ_NO();
9214 ASMCompilerBarrier();
9215
9216 /*
9217 * We'll rebuild most of the middle block of data members (holding the
9218 * current settings) as we go along here, so start by clearing it all.
9219 */
9220 pDbgState->bmXcptExtra = 0;
9221 pDbgState->fCpe1Extra = 0;
9222 pDbgState->fCpe1Unwanted = 0;
9223 pDbgState->fCpe2Extra = 0;
9224 for (unsigned i = 0; i < RT_ELEMENTS(pDbgState->bmExitsToCheck); i++)
9225 pDbgState->bmExitsToCheck[i] = 0;
9226
9227 /*
9228 * Software interrupts (INT XXh) - no idea how to trigger these...
9229 */
9230 PVM pVM = pVCpu->CTX_SUFF(pVM);
9231 if ( DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_INTERRUPT_SOFTWARE)
9232 || VBOXVMM_INT_SOFTWARE_ENABLED())
9233 {
9234 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9235 }
9236
9237 /*
9238 * INT3 breakpoints - triggered by #BP exceptions.
9239 */
9240 if (pVM->dbgf.ro.cEnabledInt3Breakpoints > 0)
9241 pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9242
9243 /*
9244 * Exception bitmap and XCPT events+probes.
9245 */
9246 for (int iXcpt = 0; iXcpt < (DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST + 1); iXcpt++)
9247 if (DBGF_IS_EVENT_ENABLED(pVM, (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + iXcpt)))
9248 pDbgState->bmXcptExtra |= RT_BIT_32(iXcpt);
9249
9250 if (VBOXVMM_XCPT_DE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DE);
9251 if (VBOXVMM_XCPT_DB_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DB);
9252 if (VBOXVMM_XCPT_BP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9253 if (VBOXVMM_XCPT_OF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_OF);
9254 if (VBOXVMM_XCPT_BR_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BR);
9255 if (VBOXVMM_XCPT_UD_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_UD);
9256 if (VBOXVMM_XCPT_NM_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NM);
9257 if (VBOXVMM_XCPT_DF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DF);
9258 if (VBOXVMM_XCPT_TS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_TS);
9259 if (VBOXVMM_XCPT_NP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NP);
9260 if (VBOXVMM_XCPT_SS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SS);
9261 if (VBOXVMM_XCPT_GP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_GP);
9262 if (VBOXVMM_XCPT_PF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_PF);
9263 if (VBOXVMM_XCPT_MF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_MF);
9264 if (VBOXVMM_XCPT_AC_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_AC);
9265 if (VBOXVMM_XCPT_XF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_XF);
9266 if (VBOXVMM_XCPT_VE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_VE);
9267 if (VBOXVMM_XCPT_SX_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SX);
9268
9269 if (pDbgState->bmXcptExtra)
9270 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9271
9272 /*
9273 * Process events and probes for VM-exits, making sure we get the wanted VM-exits.
9274 *
9275 * Note! This is the reverse of what hmR0VmxHandleExitDtraceEvents does.
9276 * So, when adding/changing/removing please don't forget to update it.
9277 *
9278 * Some of the macros are picking up local variables to save horizontal space,
9279 * (being able to see it in a table is the lesser evil here).
9280 */
9281#define IS_EITHER_ENABLED(a_pVM, a_EventSubName) \
9282 ( DBGF_IS_EVENT_ENABLED(a_pVM, RT_CONCAT(DBGFEVENT_, a_EventSubName)) \
9283 || RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)() )
9284#define SET_ONLY_XBM_IF_EITHER_EN(a_EventSubName, a_uExit) \
9285 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9286 { AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9287 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9288 } else do { } while (0)
9289#define SET_CPE1_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec) \
9290 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9291 { \
9292 (pDbgState)->fCpe1Extra |= (a_fCtrlProcExec); \
9293 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9294 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9295 } else do { } while (0)
9296#define SET_CPEU_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fUnwantedCtrlProcExec) \
9297 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9298 { \
9299 (pDbgState)->fCpe1Unwanted |= (a_fUnwantedCtrlProcExec); \
9300 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9301 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9302 } else do { } while (0)
9303#define SET_CPE2_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec2) \
9304 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9305 { \
9306 (pDbgState)->fCpe2Extra |= (a_fCtrlProcExec2); \
9307 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9308 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9309 } else do { } while (0)
9310
9311 SET_ONLY_XBM_IF_EITHER_EN(EXIT_TASK_SWITCH, VMX_EXIT_TASK_SWITCH); /* unconditional */
9312 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_VIOLATION, VMX_EXIT_EPT_VIOLATION); /* unconditional */
9313 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_MISCONFIG, VMX_EXIT_EPT_MISCONFIG); /* unconditional (unless #VE) */
9314 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_ACCESS, VMX_EXIT_APIC_ACCESS); /* feature dependent, nothing to enable here */
9315 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */
9316
9317 SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */
9318 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID);
9319 SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */
9320 SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC);
9321 SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_PROC_CTLS_HLT_EXIT); /* paranoia */
9322 SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT);
9323 SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */
9324 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD);
9325 SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_PROC_CTLS_INVLPG_EXIT);
9326 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG);
9327 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_PROC_CTLS_RDPMC_EXIT);
9328 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC);
9329 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_PROC_CTLS_RDTSC_EXIT);
9330 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC);
9331 SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */
9332 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM);
9333 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */
9334 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL);
9335 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */
9336 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR);
9337 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */
9338 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH);
9339 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */
9340 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD);
9341 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */
9342 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST);
9343 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */
9344 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD);
9345 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */
9346 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME);
9347 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */
9348 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE);
9349 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */
9350 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF);
9351 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */
9352 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON);
9353
9354 if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)
9355 || IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9356 {
9357 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_APIC_TPR);
9358 AssertRC(rc);
9359
9360#if 0 /** @todo fix me */
9361 pDbgState->fClearCr0Mask = true;
9362 pDbgState->fClearCr4Mask = true;
9363#endif
9364 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
9365 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_STORE_EXIT | VMX_PROC_CTLS_CR8_STORE_EXIT;
9366 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9367 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_LOAD_EXIT | VMX_PROC_CTLS_CR8_LOAD_EXIT;
9368 pDbgState->fCpe1Unwanted |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* risky? */
9369 /* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT. It would
9370 require clearing here and in the loop if we start using it. */
9371 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_CRX);
9372 }
9373 else
9374 {
9375 if (pDbgState->fClearCr0Mask)
9376 {
9377 pDbgState->fClearCr0Mask = false;
9378 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
9379 }
9380 if (pDbgState->fClearCr4Mask)
9381 {
9382 pDbgState->fClearCr4Mask = false;
9383 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
9384 }
9385 }
9386 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX);
9387 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX);
9388
9389 if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ)
9390 || IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE))
9391 {
9392 /** @todo later, need to fix handler as it assumes this won't usually happen. */
9393 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX);
9394 }
9395 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX);
9396 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX);
9397
9398 SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS); /* risky clearing this? */
9399 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR);
9400 SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS);
9401 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR);
9402 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_PROC_CTLS_MWAIT_EXIT); /* paranoia */
9403 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT);
9404 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_PROC_CTLS_MONITOR_EXIT); /* paranoia */
9405 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR);
9406#if 0 /** @todo too slow, fix handler. */
9407 SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_PROC_CTLS_PAUSE_EXIT);
9408#endif
9409 SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE);
9410
9411 if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT)
9412 || IS_EITHER_ENABLED(pVM, INSTR_SIDT)
9413 || IS_EITHER_ENABLED(pVM, INSTR_LGDT)
9414 || IS_EITHER_ENABLED(pVM, INSTR_LIDT))
9415 {
9416 pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
9417 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XDTR_ACCESS);
9418 }
9419 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_XDTR_ACCESS);
9420 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_XDTR_ACCESS);
9421 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_XDTR_ACCESS);
9422 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_XDTR_ACCESS);
9423
9424 if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT)
9425 || IS_EITHER_ENABLED(pVM, INSTR_STR)
9426 || IS_EITHER_ENABLED(pVM, INSTR_LLDT)
9427 || IS_EITHER_ENABLED(pVM, INSTR_LTR))
9428 {
9429 pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
9430 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_TR_ACCESS);
9431 }
9432 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_TR_ACCESS);
9433 SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_TR_ACCESS);
9434 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_TR_ACCESS);
9435 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_TR_ACCESS);
9436
9437 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */
9438 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT);
9439 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_PROC_CTLS_RDTSC_EXIT);
9440 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP);
9441 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */
9442 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID);
9443 SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_PROC_CTLS2_WBINVD_EXIT);
9444 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD);
9445 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */
9446 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV);
9447 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_PROC_CTLS2_RDRAND_EXIT);
9448 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND);
9449 SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_PROC_CTLS_INVLPG_EXIT);
9450 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID);
9451 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */
9452 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC);
9453 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_PROC_CTLS2_RDSEED_EXIT);
9454 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED);
9455 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */
9456 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES);
9457 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */
9458 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS);
9459
9460#undef IS_EITHER_ENABLED
9461#undef SET_ONLY_XBM_IF_EITHER_EN
9462#undef SET_CPE1_XBM_IF_EITHER_EN
9463#undef SET_CPEU_XBM_IF_EITHER_EN
9464#undef SET_CPE2_XBM_IF_EITHER_EN
9465
9466 /*
9467 * Sanitize the control stuff.
9468 */
9469 pDbgState->fCpe2Extra &= pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1;
9470 if (pDbgState->fCpe2Extra)
9471 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
9472 pDbgState->fCpe1Extra &= pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1;
9473 pDbgState->fCpe1Unwanted &= ~pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0;
9474 if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_PROC_CTLS_RDTSC_EXIT))
9475 {
9476 pVCpu->hm.s.fDebugWantRdTscExit ^= true;
9477 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9478 }
9479
9480 Log6(("HM: debug state: cpe1=%#RX32 cpeu=%#RX32 cpe2=%#RX32%s%s\n",
9481 pDbgState->fCpe1Extra, pDbgState->fCpe1Unwanted, pDbgState->fCpe2Extra,
9482 pDbgState->fClearCr0Mask ? " clr-cr0" : "",
9483 pDbgState->fClearCr4Mask ? " clr-cr4" : ""));
9484}
9485
9486
9487/**
9488 * Fires off DBGF events and dtrace probes for a VM-exit, when it's
9489 * appropriate.
9490 *
9491 * The caller has checked the VM-exit against the
9492 * VMXRUNDBGSTATE::bmExitsToCheck bitmap. The caller has checked for NMIs
9493 * already, so we don't have to do that either.
9494 *
9495 * @returns Strict VBox status code (i.e. informational status codes too).
9496 * @param pVCpu The cross context virtual CPU structure.
9497 * @param pVmxTransient Pointer to the VMX-transient structure.
9498 * @param uExitReason The VM-exit reason.
9499 *
9500 * @remarks The name of this function is displayed by dtrace, so keep it short
9501 * and to the point. No longer than 33 chars long, please.
9502 */
9503static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
9504{
9505 /*
9506 * Translate the event into a DBGF event (enmEvent + uEventArg) and at the
9507 * same time check whether any corresponding Dtrace event is enabled (fDtrace).
9508 *
9509 * Note! This is the reverse operation of what hmR0VmxPreRunGuestDebugStateUpdate
9510 * does. Must add/change/remove both places. Same ordering, please.
9511 *
9512 * Added/removed events must also be reflected in the next section
9513 * where we dispatch dtrace events.
9514 */
9515 bool fDtrace1 = false;
9516 bool fDtrace2 = false;
9517 DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END;
9518 DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END;
9519 uint32_t uEventArg = 0;
9520#define SET_EXIT(a_EventSubName) \
9521 do { \
9522 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9523 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9524 } while (0)
9525#define SET_BOTH(a_EventSubName) \
9526 do { \
9527 enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \
9528 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9529 fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \
9530 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9531 } while (0)
9532 switch (uExitReason)
9533 {
9534 case VMX_EXIT_MTF:
9535 return hmR0VmxExitMtf(pVCpu, pVmxTransient);
9536
9537 case VMX_EXIT_XCPT_OR_NMI:
9538 {
9539 uint8_t const idxVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
9540 switch (VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo))
9541 {
9542 case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
9543 case VMX_EXIT_INT_INFO_TYPE_SW_XCPT:
9544 case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT:
9545 if (idxVector <= (unsigned)(DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST))
9546 {
9547 if (VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uExitIntInfo))
9548 {
9549 hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
9550 uEventArg = pVmxTransient->uExitIntErrorCode;
9551 }
9552 enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);
9553 switch (enmEvent1)
9554 {
9555 case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break;
9556 case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break;
9557 case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break;
9558 case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break;
9559 case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break;
9560 case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break;
9561 case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break;
9562 case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break;
9563 case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break;
9564 case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break;
9565 case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break;
9566 case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break;
9567 case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break;
9568 case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break;
9569 case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break;
9570 case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break;
9571 case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break;
9572 case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break;
9573 default: break;
9574 }
9575 }
9576 else
9577 AssertFailed();
9578 break;
9579
9580 case VMX_EXIT_INT_INFO_TYPE_SW_INT:
9581 uEventArg = idxVector;
9582 enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE;
9583 fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED();
9584 break;
9585 }
9586 break;
9587 }
9588
9589 case VMX_EXIT_TRIPLE_FAULT:
9590 enmEvent1 = DBGFEVENT_TRIPLE_FAULT;
9591 //fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();
9592 break;
9593 case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break;
9594 case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break;
9595 case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break;
9596 case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break;
9597 case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break;
9598
9599 /* Instruction specific VM-exits: */
9600 case VMX_EXIT_CPUID: SET_BOTH(CPUID); break;
9601 case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break;
9602 case VMX_EXIT_HLT: SET_BOTH(HALT); break;
9603 case VMX_EXIT_INVD: SET_BOTH(INVD); break;
9604 case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break;
9605 case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break;
9606 case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break;
9607 case VMX_EXIT_RSM: SET_BOTH(RSM); break;
9608 case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break;
9609 case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break;
9610 case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break;
9611 case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break;
9612 case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break;
9613 case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break;
9614 case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break;
9615 case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break;
9616 case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break;
9617 case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break;
9618 case VMX_EXIT_MOV_CRX:
9619 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9620 if (VMX_EXIT_QUAL_CRX_ACCESS(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_CRX_ACCESS_READ)
9621 SET_BOTH(CRX_READ);
9622 else
9623 SET_BOTH(CRX_WRITE);
9624 uEventArg = VMX_EXIT_QUAL_CRX_REGISTER(pVmxTransient->uExitQual);
9625 break;
9626 case VMX_EXIT_MOV_DRX:
9627 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9628 if ( VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual)
9629 == VMX_EXIT_QUAL_DRX_DIRECTION_READ)
9630 SET_BOTH(DRX_READ);
9631 else
9632 SET_BOTH(DRX_WRITE);
9633 uEventArg = VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual);
9634 break;
9635 case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break;
9636 case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break;
9637 case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break;
9638 case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break;
9639 case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break;
9640 case VMX_EXIT_XDTR_ACCESS:
9641 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9642 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_XDTR_INSINFO_INSTR_ID))
9643 {
9644 case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break;
9645 case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break;
9646 case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break;
9647 case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break;
9648 }
9649 break;
9650
9651 case VMX_EXIT_TR_ACCESS:
9652 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9653 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_YYTR_INSINFO_INSTR_ID))
9654 {
9655 case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break;
9656 case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break;
9657 case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break;
9658 case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break;
9659 }
9660 break;
9661
9662 case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break;
9663 case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break;
9664 case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break;
9665 case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break;
9666 case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break;
9667 case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break;
9668 case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break;
9669 case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break;
9670 case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break;
9671 case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break;
9672 case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break;
9673
9674 /* Events that aren't relevant at this point. */
9675 case VMX_EXIT_EXT_INT:
9676 case VMX_EXIT_INT_WINDOW:
9677 case VMX_EXIT_NMI_WINDOW:
9678 case VMX_EXIT_TPR_BELOW_THRESHOLD:
9679 case VMX_EXIT_PREEMPT_TIMER:
9680 case VMX_EXIT_IO_INSTR:
9681 break;
9682
9683 /* Errors and unexpected events. */
9684 case VMX_EXIT_INIT_SIGNAL:
9685 case VMX_EXIT_SIPI:
9686 case VMX_EXIT_IO_SMI:
9687 case VMX_EXIT_SMI:
9688 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9689 case VMX_EXIT_ERR_MSR_LOAD:
9690 case VMX_EXIT_ERR_MACHINE_CHECK:
9691 break;
9692
9693 default:
9694 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9695 break;
9696 }
9697#undef SET_BOTH
9698#undef SET_EXIT
9699
9700 /*
9701 * Dtrace tracepoints go first. We do them here at once so we don't
9702 * have to copy the guest state saving and stuff a few dozen times.
9703 * Down side is that we've got to repeat the switch, though this time
9704 * we use enmEvent since the probes are a subset of what DBGF does.
9705 */
9706 if (fDtrace1 || fDtrace2)
9707 {
9708 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9709 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
9710 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
9711 switch (enmEvent1)
9712 {
9713 /** @todo consider which extra parameters would be helpful for each probe. */
9714 case DBGFEVENT_END: break;
9715 case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pCtx); break;
9716 case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pCtx, pCtx->dr[6]); break;
9717 case DBGFEVENT_XCPT_BP: VBOXVMM_XCPT_BP(pVCpu, pCtx); break;
9718 case DBGFEVENT_XCPT_OF: VBOXVMM_XCPT_OF(pVCpu, pCtx); break;
9719 case DBGFEVENT_XCPT_BR: VBOXVMM_XCPT_BR(pVCpu, pCtx); break;
9720 case DBGFEVENT_XCPT_UD: VBOXVMM_XCPT_UD(pVCpu, pCtx); break;
9721 case DBGFEVENT_XCPT_NM: VBOXVMM_XCPT_NM(pVCpu, pCtx); break;
9722 case DBGFEVENT_XCPT_DF: VBOXVMM_XCPT_DF(pVCpu, pCtx); break;
9723 case DBGFEVENT_XCPT_TS: VBOXVMM_XCPT_TS(pVCpu, pCtx, uEventArg); break;
9724 case DBGFEVENT_XCPT_NP: VBOXVMM_XCPT_NP(pVCpu, pCtx, uEventArg); break;
9725 case DBGFEVENT_XCPT_SS: VBOXVMM_XCPT_SS(pVCpu, pCtx, uEventArg); break;
9726 case DBGFEVENT_XCPT_GP: VBOXVMM_XCPT_GP(pVCpu, pCtx, uEventArg); break;
9727 case DBGFEVENT_XCPT_PF: VBOXVMM_XCPT_PF(pVCpu, pCtx, uEventArg, pCtx->cr2); break;
9728 case DBGFEVENT_XCPT_MF: VBOXVMM_XCPT_MF(pVCpu, pCtx); break;
9729 case DBGFEVENT_XCPT_AC: VBOXVMM_XCPT_AC(pVCpu, pCtx); break;
9730 case DBGFEVENT_XCPT_XF: VBOXVMM_XCPT_XF(pVCpu, pCtx); break;
9731 case DBGFEVENT_XCPT_VE: VBOXVMM_XCPT_VE(pVCpu, pCtx); break;
9732 case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pCtx, uEventArg); break;
9733 case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9734 case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
9735 case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pCtx); break;
9736 case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pCtx); break;
9737 case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pCtx); break;
9738 case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pCtx); break;
9739 case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pCtx); break;
9740 case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pCtx); break;
9741 case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pCtx); break;
9742 case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9743 case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9744 case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9745 case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9746 case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
9747 case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pCtx, pCtx->ecx,
9748 RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
9749 case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pCtx); break;
9750 case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pCtx); break;
9751 case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pCtx); break;
9752 case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pCtx); break;
9753 case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pCtx); break;
9754 case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pCtx); break;
9755 case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pCtx); break;
9756 case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pCtx); break;
9757 case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pCtx); break;
9758 case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pCtx); break;
9759 case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pCtx); break;
9760 case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pCtx); break;
9761 case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pCtx); break;
9762 case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pCtx); break;
9763 case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pCtx); break;
9764 case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pCtx); break;
9765 case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pCtx); break;
9766 case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pCtx); break;
9767 case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pCtx); break;
9768 case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pCtx); break;
9769 case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pCtx); break;
9770 case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pCtx); break;
9771 case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pCtx); break;
9772 case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pCtx); break;
9773 case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pCtx); break;
9774 case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pCtx); break;
9775 case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pCtx); break;
9776 case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pCtx); break;
9777 case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pCtx); break;
9778 case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pCtx); break;
9779 case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pCtx); break;
9780 case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pCtx); break;
9781 default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break;
9782 }
9783 switch (enmEvent2)
9784 {
9785 /** @todo consider which extra parameters would be helpful for each probe. */
9786 case DBGFEVENT_END: break;
9787 case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pCtx); break;
9788 case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
9789 case DBGFEVENT_EXIT_GETSEC: VBOXVMM_EXIT_GETSEC(pVCpu, pCtx); break;
9790 case DBGFEVENT_EXIT_HALT: VBOXVMM_EXIT_HALT(pVCpu, pCtx); break;
9791 case DBGFEVENT_EXIT_INVD: VBOXVMM_EXIT_INVD(pVCpu, pCtx); break;
9792 case DBGFEVENT_EXIT_INVLPG: VBOXVMM_EXIT_INVLPG(pVCpu, pCtx); break;
9793 case DBGFEVENT_EXIT_RDPMC: VBOXVMM_EXIT_RDPMC(pVCpu, pCtx); break;
9794 case DBGFEVENT_EXIT_RDTSC: VBOXVMM_EXIT_RDTSC(pVCpu, pCtx); break;
9795 case DBGFEVENT_EXIT_RSM: VBOXVMM_EXIT_RSM(pVCpu, pCtx); break;
9796 case DBGFEVENT_EXIT_CRX_READ: VBOXVMM_EXIT_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9797 case DBGFEVENT_EXIT_CRX_WRITE: VBOXVMM_EXIT_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9798 case DBGFEVENT_EXIT_DRX_READ: VBOXVMM_EXIT_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9799 case DBGFEVENT_EXIT_DRX_WRITE: VBOXVMM_EXIT_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9800 case DBGFEVENT_EXIT_RDMSR: VBOXVMM_EXIT_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
9801 case DBGFEVENT_EXIT_WRMSR: VBOXVMM_EXIT_WRMSR(pVCpu, pCtx, pCtx->ecx,
9802 RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
9803 case DBGFEVENT_EXIT_MWAIT: VBOXVMM_EXIT_MWAIT(pVCpu, pCtx); break;
9804 case DBGFEVENT_EXIT_MONITOR: VBOXVMM_EXIT_MONITOR(pVCpu, pCtx); break;
9805 case DBGFEVENT_EXIT_PAUSE: VBOXVMM_EXIT_PAUSE(pVCpu, pCtx); break;
9806 case DBGFEVENT_EXIT_SGDT: VBOXVMM_EXIT_SGDT(pVCpu, pCtx); break;
9807 case DBGFEVENT_EXIT_SIDT: VBOXVMM_EXIT_SIDT(pVCpu, pCtx); break;
9808 case DBGFEVENT_EXIT_LGDT: VBOXVMM_EXIT_LGDT(pVCpu, pCtx); break;
9809 case DBGFEVENT_EXIT_LIDT: VBOXVMM_EXIT_LIDT(pVCpu, pCtx); break;
9810 case DBGFEVENT_EXIT_SLDT: VBOXVMM_EXIT_SLDT(pVCpu, pCtx); break;
9811 case DBGFEVENT_EXIT_STR: VBOXVMM_EXIT_STR(pVCpu, pCtx); break;
9812 case DBGFEVENT_EXIT_LLDT: VBOXVMM_EXIT_LLDT(pVCpu, pCtx); break;
9813 case DBGFEVENT_EXIT_LTR: VBOXVMM_EXIT_LTR(pVCpu, pCtx); break;
9814 case DBGFEVENT_EXIT_RDTSCP: VBOXVMM_EXIT_RDTSCP(pVCpu, pCtx); break;
9815 case DBGFEVENT_EXIT_WBINVD: VBOXVMM_EXIT_WBINVD(pVCpu, pCtx); break;
9816 case DBGFEVENT_EXIT_XSETBV: VBOXVMM_EXIT_XSETBV(pVCpu, pCtx); break;
9817 case DBGFEVENT_EXIT_RDRAND: VBOXVMM_EXIT_RDRAND(pVCpu, pCtx); break;
9818 case DBGFEVENT_EXIT_RDSEED: VBOXVMM_EXIT_RDSEED(pVCpu, pCtx); break;
9819 case DBGFEVENT_EXIT_XSAVES: VBOXVMM_EXIT_XSAVES(pVCpu, pCtx); break;
9820 case DBGFEVENT_EXIT_XRSTORS: VBOXVMM_EXIT_XRSTORS(pVCpu, pCtx); break;
9821 case DBGFEVENT_EXIT_VMM_CALL: VBOXVMM_EXIT_VMM_CALL(pVCpu, pCtx); break;
9822 case DBGFEVENT_EXIT_VMX_VMCLEAR: VBOXVMM_EXIT_VMX_VMCLEAR(pVCpu, pCtx); break;
9823 case DBGFEVENT_EXIT_VMX_VMLAUNCH: VBOXVMM_EXIT_VMX_VMLAUNCH(pVCpu, pCtx); break;
9824 case DBGFEVENT_EXIT_VMX_VMPTRLD: VBOXVMM_EXIT_VMX_VMPTRLD(pVCpu, pCtx); break;
9825 case DBGFEVENT_EXIT_VMX_VMPTRST: VBOXVMM_EXIT_VMX_VMPTRST(pVCpu, pCtx); break;
9826 case DBGFEVENT_EXIT_VMX_VMREAD: VBOXVMM_EXIT_VMX_VMREAD(pVCpu, pCtx); break;
9827 case DBGFEVENT_EXIT_VMX_VMRESUME: VBOXVMM_EXIT_VMX_VMRESUME(pVCpu, pCtx); break;
9828 case DBGFEVENT_EXIT_VMX_VMWRITE: VBOXVMM_EXIT_VMX_VMWRITE(pVCpu, pCtx); break;
9829 case DBGFEVENT_EXIT_VMX_VMXOFF: VBOXVMM_EXIT_VMX_VMXOFF(pVCpu, pCtx); break;
9830 case DBGFEVENT_EXIT_VMX_VMXON: VBOXVMM_EXIT_VMX_VMXON(pVCpu, pCtx); break;
9831 case DBGFEVENT_EXIT_VMX_INVEPT: VBOXVMM_EXIT_VMX_INVEPT(pVCpu, pCtx); break;
9832 case DBGFEVENT_EXIT_VMX_INVVPID: VBOXVMM_EXIT_VMX_INVVPID(pVCpu, pCtx); break;
9833 case DBGFEVENT_EXIT_VMX_INVPCID: VBOXVMM_EXIT_VMX_INVPCID(pVCpu, pCtx); break;
9834 case DBGFEVENT_EXIT_VMX_VMFUNC: VBOXVMM_EXIT_VMX_VMFUNC(pVCpu, pCtx); break;
9835 case DBGFEVENT_EXIT_VMX_EPT_MISCONFIG: VBOXVMM_EXIT_VMX_EPT_MISCONFIG(pVCpu, pCtx); break;
9836 case DBGFEVENT_EXIT_VMX_EPT_VIOLATION: VBOXVMM_EXIT_VMX_EPT_VIOLATION(pVCpu, pCtx); break;
9837 case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pCtx); break;
9838 case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pCtx); break;
9839 default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break;
9840 }
9841 }
9842
9843 /*
9844 * Fire of the DBGF event, if enabled (our check here is just a quick one,
9845 * the DBGF call will do a full check).
9846 *
9847 * Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap.
9848 * Note! If we have to events, we prioritize the first, i.e. the instruction
9849 * one, in order to avoid event nesting.
9850 */
9851 PVM pVM = pVCpu->CTX_SUFF(pVM);
9852 if ( enmEvent1 != DBGFEVENT_END
9853 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
9854 {
9855 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent1, DBGFEVENTCTX_HM, 1, uEventArg);
9856 if (rcStrict != VINF_SUCCESS)
9857 return rcStrict;
9858 }
9859 else if ( enmEvent2 != DBGFEVENT_END
9860 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent2))
9861 {
9862 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent2, DBGFEVENTCTX_HM, 1, uEventArg);
9863 if (rcStrict != VINF_SUCCESS)
9864 return rcStrict;
9865 }
9866
9867 return VINF_SUCCESS;
9868}
9869
9870
9871/**
9872 * Single-stepping VM-exit filtering.
9873 *
9874 * This is preprocessing the VM-exits and deciding whether we've gotten far
9875 * enough to return VINF_EM_DBG_STEPPED already. If not, normal VM-exit
9876 * handling is performed.
9877 *
9878 * @returns Strict VBox status code (i.e. informational status codes too).
9879 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9880 * @param pVmxTransient Pointer to the VMX-transient structure.
9881 * @param pDbgState The debug state.
9882 */
9883DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState)
9884{
9885 /*
9886 * Expensive (saves context) generic dtrace VM-exit probe.
9887 */
9888 uint32_t const uExitReason = pVmxTransient->uExitReason;
9889 if (!VBOXVMM_R0_HMVMX_VMEXIT_ENABLED())
9890 { /* more likely */ }
9891 else
9892 {
9893 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9894 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
9895 AssertRC(rc);
9896 VBOXVMM_R0_HMVMX_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, pVmxTransient->uExitReason, pVmxTransient->uExitQual);
9897 }
9898
9899 /*
9900 * Check for host NMI, just to get that out of the way.
9901 */
9902 if (uExitReason != VMX_EXIT_XCPT_OR_NMI)
9903 { /* normally likely */ }
9904 else
9905 {
9906 int rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
9907 AssertRCReturn(rc2, rc2);
9908 uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
9909 if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
9910 return hmR0VmxExitXcptOrNmi(pVCpu, pVmxTransient);
9911 }
9912
9913 /*
9914 * Check for single stepping event if we're stepping.
9915 */
9916 if (pVCpu->hm.s.fSingleInstruction)
9917 {
9918 switch (uExitReason)
9919 {
9920 case VMX_EXIT_MTF:
9921 return hmR0VmxExitMtf(pVCpu, pVmxTransient);
9922
9923 /* Various events: */
9924 case VMX_EXIT_XCPT_OR_NMI:
9925 case VMX_EXIT_EXT_INT:
9926 case VMX_EXIT_TRIPLE_FAULT:
9927 case VMX_EXIT_INT_WINDOW:
9928 case VMX_EXIT_NMI_WINDOW:
9929 case VMX_EXIT_TASK_SWITCH:
9930 case VMX_EXIT_TPR_BELOW_THRESHOLD:
9931 case VMX_EXIT_APIC_ACCESS:
9932 case VMX_EXIT_EPT_VIOLATION:
9933 case VMX_EXIT_EPT_MISCONFIG:
9934 case VMX_EXIT_PREEMPT_TIMER:
9935
9936 /* Instruction specific VM-exits: */
9937 case VMX_EXIT_CPUID:
9938 case VMX_EXIT_GETSEC:
9939 case VMX_EXIT_HLT:
9940 case VMX_EXIT_INVD:
9941 case VMX_EXIT_INVLPG:
9942 case VMX_EXIT_RDPMC:
9943 case VMX_EXIT_RDTSC:
9944 case VMX_EXIT_RSM:
9945 case VMX_EXIT_VMCALL:
9946 case VMX_EXIT_VMCLEAR:
9947 case VMX_EXIT_VMLAUNCH:
9948 case VMX_EXIT_VMPTRLD:
9949 case VMX_EXIT_VMPTRST:
9950 case VMX_EXIT_VMREAD:
9951 case VMX_EXIT_VMRESUME:
9952 case VMX_EXIT_VMWRITE:
9953 case VMX_EXIT_VMXOFF:
9954 case VMX_EXIT_VMXON:
9955 case VMX_EXIT_MOV_CRX:
9956 case VMX_EXIT_MOV_DRX:
9957 case VMX_EXIT_IO_INSTR:
9958 case VMX_EXIT_RDMSR:
9959 case VMX_EXIT_WRMSR:
9960 case VMX_EXIT_MWAIT:
9961 case VMX_EXIT_MONITOR:
9962 case VMX_EXIT_PAUSE:
9963 case VMX_EXIT_XDTR_ACCESS:
9964 case VMX_EXIT_TR_ACCESS:
9965 case VMX_EXIT_INVEPT:
9966 case VMX_EXIT_RDTSCP:
9967 case VMX_EXIT_INVVPID:
9968 case VMX_EXIT_WBINVD:
9969 case VMX_EXIT_XSETBV:
9970 case VMX_EXIT_RDRAND:
9971 case VMX_EXIT_INVPCID:
9972 case VMX_EXIT_VMFUNC:
9973 case VMX_EXIT_RDSEED:
9974 case VMX_EXIT_XSAVES:
9975 case VMX_EXIT_XRSTORS:
9976 {
9977 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
9978 AssertRCReturn(rc, rc);
9979 if ( pVCpu->cpum.GstCtx.rip != pDbgState->uRipStart
9980 || pVCpu->cpum.GstCtx.cs.Sel != pDbgState->uCsStart)
9981 return VINF_EM_DBG_STEPPED;
9982 break;
9983 }
9984
9985 /* Errors and unexpected events: */
9986 case VMX_EXIT_INIT_SIGNAL:
9987 case VMX_EXIT_SIPI:
9988 case VMX_EXIT_IO_SMI:
9989 case VMX_EXIT_SMI:
9990 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9991 case VMX_EXIT_ERR_MSR_LOAD:
9992 case VMX_EXIT_ERR_MACHINE_CHECK:
9993 case VMX_EXIT_APIC_WRITE: /* Some talk about this being fault like, so I guess we must process it? */
9994 break;
9995
9996 default:
9997 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9998 break;
9999 }
10000 }
10001
10002 /*
10003 * Check for debugger event breakpoints and dtrace probes.
10004 */
10005 if ( uExitReason < RT_ELEMENTS(pDbgState->bmExitsToCheck) * 32U
10006 && ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
10007 {
10008 VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVCpu, pVmxTransient, uExitReason);
10009 if (rcStrict != VINF_SUCCESS)
10010 return rcStrict;
10011 }
10012
10013 /*
10014 * Normal processing.
10015 */
10016#ifdef HMVMX_USE_FUNCTION_TABLE
10017 return g_apfnVMExitHandlers[uExitReason](pVCpu, pVmxTransient);
10018#else
10019 return hmR0VmxHandleExit(pVCpu, pVmxTransient, uExitReason);
10020#endif
10021}
10022
10023
10024/**
10025 * Single steps guest code using VT-x.
10026 *
10027 * @returns Strict VBox status code (i.e. informational status codes too).
10028 * @param pVCpu The cross context virtual CPU structure.
10029 *
10030 * @note Mostly the same as hmR0VmxRunGuestCodeNormal().
10031 */
10032static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVMCPU pVCpu)
10033{
10034 VMXTRANSIENT VmxTransient;
10035 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
10036
10037 /* Set HMCPU indicators. */
10038 bool const fSavedSingleInstruction = pVCpu->hm.s.fSingleInstruction;
10039 pVCpu->hm.s.fSingleInstruction = pVCpu->hm.s.fSingleInstruction || DBGFIsStepping(pVCpu);
10040 pVCpu->hm.s.fDebugWantRdTscExit = false;
10041 pVCpu->hm.s.fUsingDebugLoop = true;
10042
10043 /* State we keep to help modify and later restore the VMCS fields we alter, and for detecting steps. */
10044 VMXRUNDBGSTATE DbgState;
10045 hmR0VmxRunDebugStateInit(pVCpu, &DbgState);
10046 hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &DbgState, &VmxTransient);
10047
10048 /*
10049 * The loop.
10050 */
10051 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
10052 for (uint32_t cLoops = 0; ; cLoops++)
10053 {
10054 Assert(!HMR0SuspendPending());
10055 HMVMX_ASSERT_CPU_SAFE(pVCpu);
10056 bool fStepping = pVCpu->hm.s.fSingleInstruction;
10057
10058 /*
10059 * Preparatory work for running guest code, this may force us to return
10060 * to ring-3. This bugger disables interrupts on VINF_SUCCESS!
10061 */
10062 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
10063 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Set up execute controls the next to can respond to. */
10064 rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, fStepping);
10065 if (rcStrict != VINF_SUCCESS)
10066 break;
10067
10068 hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
10069 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Override any obnoxious code in the above two calls. */
10070
10071 /*
10072 * Now we can run the guest code.
10073 */
10074 int rcRun = hmR0VmxRunGuest(pVCpu);
10075
10076 /*
10077 * Restore any residual host-state and save any bits shared between host
10078 * and guest into the guest-CPU state. Re-enables interrupts!
10079 */
10080 hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
10081
10082 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
10083 if (RT_SUCCESS(rcRun))
10084 { /* very likely */ }
10085 else
10086 {
10087 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
10088 hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
10089 return rcRun;
10090 }
10091
10092 /* Profile the VM-exit. */
10093 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
10094 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
10095 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
10096 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
10097 HMVMX_START_EXIT_DISPATCH_PROF();
10098
10099 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
10100
10101 /*
10102 * Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
10103 */
10104 rcStrict = hmR0VmxRunDebugHandleExit(pVCpu, &VmxTransient, &DbgState);
10105 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
10106 if (rcStrict != VINF_SUCCESS)
10107 break;
10108 if (cLoops > pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
10109 {
10110 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
10111 rcStrict = VINF_EM_RAW_INTERRUPT;
10112 break;
10113 }
10114
10115 /*
10116 * Stepping: Did the RIP change, if so, consider it a single step.
10117 * Otherwise, make sure one of the TFs gets set.
10118 */
10119 if (fStepping)
10120 {
10121 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
10122 AssertRC(rc);
10123 if ( pVCpu->cpum.GstCtx.rip != DbgState.uRipStart
10124 || pVCpu->cpum.GstCtx.cs.Sel != DbgState.uCsStart)
10125 {
10126 rcStrict = VINF_EM_DBG_STEPPED;
10127 break;
10128 }
10129 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
10130 }
10131
10132 /*
10133 * Update when dtrace settings changes (DBGF kicks us, so no need to check).
10134 */
10135 if (VBOXVMM_GET_SETTINGS_SEQ_NO() != DbgState.uDtraceSettingsSeqNo)
10136 hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &DbgState, &VmxTransient);
10137 }
10138
10139 /*
10140 * Clear the X86_EFL_TF if necessary.
10141 */
10142 if (pVCpu->hm.s.fClearTrapFlag)
10143 {
10144 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
10145 AssertRC(rc);
10146 pVCpu->hm.s.fClearTrapFlag = false;
10147 pVCpu->cpum.GstCtx.eflags.Bits.u1TF = 0;
10148 }
10149 /** @todo there seems to be issues with the resume flag when the monitor trap
10150 * flag is pending without being used. Seen early in bios init when
10151 * accessing APIC page in protected mode. */
10152
10153 /*
10154 * Restore VM-exit control settings as we may not reenter this function the
10155 * next time around.
10156 */
10157 rcStrict = hmR0VmxRunDebugStateRevert(pVCpu, &DbgState, rcStrict);
10158
10159 /* Restore HMCPU indicators. */
10160 pVCpu->hm.s.fUsingDebugLoop = false;
10161 pVCpu->hm.s.fDebugWantRdTscExit = false;
10162 pVCpu->hm.s.fSingleInstruction = fSavedSingleInstruction;
10163
10164 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
10165 return rcStrict;
10166}
10167
10168
10169/** @} */
10170
10171
10172/**
10173 * Checks if any expensive dtrace probes are enabled and we should go to the
10174 * debug loop.
10175 *
10176 * @returns true if we should use debug loop, false if not.
10177 */
10178static bool hmR0VmxAnyExpensiveProbesEnabled(void)
10179{
10180 /* It's probably faster to OR the raw 32-bit counter variables together.
10181 Since the variables are in an array and the probes are next to one
10182 another (more or less), we have good locality. So, better read
10183 eight-nine cache lines ever time and only have one conditional, than
10184 128+ conditionals, right? */
10185 return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */
10186 | VBOXVMM_XCPT_DE_ENABLED_RAW()
10187 | VBOXVMM_XCPT_DB_ENABLED_RAW()
10188 | VBOXVMM_XCPT_BP_ENABLED_RAW()
10189 | VBOXVMM_XCPT_OF_ENABLED_RAW()
10190 | VBOXVMM_XCPT_BR_ENABLED_RAW()
10191 | VBOXVMM_XCPT_UD_ENABLED_RAW()
10192 | VBOXVMM_XCPT_NM_ENABLED_RAW()
10193 | VBOXVMM_XCPT_DF_ENABLED_RAW()
10194 | VBOXVMM_XCPT_TS_ENABLED_RAW()
10195 | VBOXVMM_XCPT_NP_ENABLED_RAW()
10196 | VBOXVMM_XCPT_SS_ENABLED_RAW()
10197 | VBOXVMM_XCPT_GP_ENABLED_RAW()
10198 | VBOXVMM_XCPT_PF_ENABLED_RAW()
10199 | VBOXVMM_XCPT_MF_ENABLED_RAW()
10200 | VBOXVMM_XCPT_AC_ENABLED_RAW()
10201 | VBOXVMM_XCPT_XF_ENABLED_RAW()
10202 | VBOXVMM_XCPT_VE_ENABLED_RAW()
10203 | VBOXVMM_XCPT_SX_ENABLED_RAW()
10204 | VBOXVMM_INT_SOFTWARE_ENABLED_RAW()
10205 | VBOXVMM_INT_HARDWARE_ENABLED_RAW()
10206 ) != 0
10207 || ( VBOXVMM_INSTR_HALT_ENABLED_RAW()
10208 | VBOXVMM_INSTR_MWAIT_ENABLED_RAW()
10209 | VBOXVMM_INSTR_MONITOR_ENABLED_RAW()
10210 | VBOXVMM_INSTR_CPUID_ENABLED_RAW()
10211 | VBOXVMM_INSTR_INVD_ENABLED_RAW()
10212 | VBOXVMM_INSTR_WBINVD_ENABLED_RAW()
10213 | VBOXVMM_INSTR_INVLPG_ENABLED_RAW()
10214 | VBOXVMM_INSTR_RDTSC_ENABLED_RAW()
10215 | VBOXVMM_INSTR_RDTSCP_ENABLED_RAW()
10216 | VBOXVMM_INSTR_RDPMC_ENABLED_RAW()
10217 | VBOXVMM_INSTR_RDMSR_ENABLED_RAW()
10218 | VBOXVMM_INSTR_WRMSR_ENABLED_RAW()
10219 | VBOXVMM_INSTR_CRX_READ_ENABLED_RAW()
10220 | VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW()
10221 | VBOXVMM_INSTR_DRX_READ_ENABLED_RAW()
10222 | VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW()
10223 | VBOXVMM_INSTR_PAUSE_ENABLED_RAW()
10224 | VBOXVMM_INSTR_XSETBV_ENABLED_RAW()
10225 | VBOXVMM_INSTR_SIDT_ENABLED_RAW()
10226 | VBOXVMM_INSTR_LIDT_ENABLED_RAW()
10227 | VBOXVMM_INSTR_SGDT_ENABLED_RAW()
10228 | VBOXVMM_INSTR_LGDT_ENABLED_RAW()
10229 | VBOXVMM_INSTR_SLDT_ENABLED_RAW()
10230 | VBOXVMM_INSTR_LLDT_ENABLED_RAW()
10231 | VBOXVMM_INSTR_STR_ENABLED_RAW()
10232 | VBOXVMM_INSTR_LTR_ENABLED_RAW()
10233 | VBOXVMM_INSTR_GETSEC_ENABLED_RAW()
10234 | VBOXVMM_INSTR_RSM_ENABLED_RAW()
10235 | VBOXVMM_INSTR_RDRAND_ENABLED_RAW()
10236 | VBOXVMM_INSTR_RDSEED_ENABLED_RAW()
10237 | VBOXVMM_INSTR_XSAVES_ENABLED_RAW()
10238 | VBOXVMM_INSTR_XRSTORS_ENABLED_RAW()
10239 | VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW()
10240 | VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW()
10241 | VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW()
10242 | VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW()
10243 | VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW()
10244 | VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW()
10245 | VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW()
10246 | VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW()
10247 | VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW()
10248 | VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW()
10249 | VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW()
10250 | VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW()
10251 | VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW()
10252 | VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW()
10253 ) != 0
10254 || ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW()
10255 | VBOXVMM_EXIT_HALT_ENABLED_RAW()
10256 | VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
10257 | VBOXVMM_EXIT_MONITOR_ENABLED_RAW()
10258 | VBOXVMM_EXIT_CPUID_ENABLED_RAW()
10259 | VBOXVMM_EXIT_INVD_ENABLED_RAW()
10260 | VBOXVMM_EXIT_WBINVD_ENABLED_RAW()
10261 | VBOXVMM_EXIT_INVLPG_ENABLED_RAW()
10262 | VBOXVMM_EXIT_RDTSC_ENABLED_RAW()
10263 | VBOXVMM_EXIT_RDTSCP_ENABLED_RAW()
10264 | VBOXVMM_EXIT_RDPMC_ENABLED_RAW()
10265 | VBOXVMM_EXIT_RDMSR_ENABLED_RAW()
10266 | VBOXVMM_EXIT_WRMSR_ENABLED_RAW()
10267 | VBOXVMM_EXIT_CRX_READ_ENABLED_RAW()
10268 | VBOXVMM_EXIT_CRX_WRITE_ENABLED_RAW()
10269 | VBOXVMM_EXIT_DRX_READ_ENABLED_RAW()
10270 | VBOXVMM_EXIT_DRX_WRITE_ENABLED_RAW()
10271 | VBOXVMM_EXIT_PAUSE_ENABLED_RAW()
10272 | VBOXVMM_EXIT_XSETBV_ENABLED_RAW()
10273 | VBOXVMM_EXIT_SIDT_ENABLED_RAW()
10274 | VBOXVMM_EXIT_LIDT_ENABLED_RAW()
10275 | VBOXVMM_EXIT_SGDT_ENABLED_RAW()
10276 | VBOXVMM_EXIT_LGDT_ENABLED_RAW()
10277 | VBOXVMM_EXIT_SLDT_ENABLED_RAW()
10278 | VBOXVMM_EXIT_LLDT_ENABLED_RAW()
10279 | VBOXVMM_EXIT_STR_ENABLED_RAW()
10280 | VBOXVMM_EXIT_LTR_ENABLED_RAW()
10281 | VBOXVMM_EXIT_GETSEC_ENABLED_RAW()
10282 | VBOXVMM_EXIT_RSM_ENABLED_RAW()
10283 | VBOXVMM_EXIT_RDRAND_ENABLED_RAW()
10284 | VBOXVMM_EXIT_RDSEED_ENABLED_RAW()
10285 | VBOXVMM_EXIT_XSAVES_ENABLED_RAW()
10286 | VBOXVMM_EXIT_XRSTORS_ENABLED_RAW()
10287 | VBOXVMM_EXIT_VMM_CALL_ENABLED_RAW()
10288 | VBOXVMM_EXIT_VMX_VMCLEAR_ENABLED_RAW()
10289 | VBOXVMM_EXIT_VMX_VMLAUNCH_ENABLED_RAW()
10290 | VBOXVMM_EXIT_VMX_VMPTRLD_ENABLED_RAW()
10291 | VBOXVMM_EXIT_VMX_VMPTRST_ENABLED_RAW()
10292 | VBOXVMM_EXIT_VMX_VMREAD_ENABLED_RAW()
10293 | VBOXVMM_EXIT_VMX_VMRESUME_ENABLED_RAW()
10294 | VBOXVMM_EXIT_VMX_VMWRITE_ENABLED_RAW()
10295 | VBOXVMM_EXIT_VMX_VMXOFF_ENABLED_RAW()
10296 | VBOXVMM_EXIT_VMX_VMXON_ENABLED_RAW()
10297 | VBOXVMM_EXIT_VMX_VMFUNC_ENABLED_RAW()
10298 | VBOXVMM_EXIT_VMX_INVEPT_ENABLED_RAW()
10299 | VBOXVMM_EXIT_VMX_INVVPID_ENABLED_RAW()
10300 | VBOXVMM_EXIT_VMX_INVPCID_ENABLED_RAW()
10301 | VBOXVMM_EXIT_VMX_EPT_VIOLATION_ENABLED_RAW()
10302 | VBOXVMM_EXIT_VMX_EPT_MISCONFIG_ENABLED_RAW()
10303 | VBOXVMM_EXIT_VMX_VAPIC_ACCESS_ENABLED_RAW()
10304 | VBOXVMM_EXIT_VMX_VAPIC_WRITE_ENABLED_RAW()
10305 ) != 0;
10306}
10307
10308
10309/**
10310 * Runs the guest code using VT-x.
10311 *
10312 * @returns Strict VBox status code (i.e. informational status codes too).
10313 * @param pVCpu The cross context virtual CPU structure.
10314 */
10315VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPU pVCpu)
10316{
10317 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
10318 Assert(VMMRZCallRing3IsEnabled(pVCpu));
10319 Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
10320 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
10321
10322 VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
10323
10324 VBOXSTRICTRC rcStrict;
10325 if ( !pVCpu->hm.s.fUseDebugLoop
10326 && (!VBOXVMM_ANY_PROBES_ENABLED() || !hmR0VmxAnyExpensiveProbesEnabled())
10327 && !DBGFIsStepping(pVCpu)
10328 && !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
10329 rcStrict = hmR0VmxRunGuestCodeNormal(pVCpu);
10330 else
10331 rcStrict = hmR0VmxRunGuestCodeDebug(pVCpu);
10332
10333 if (rcStrict == VERR_EM_INTERPRETER)
10334 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
10335 else if (rcStrict == VINF_EM_RESET)
10336 rcStrict = VINF_EM_TRIPLE_FAULT;
10337
10338 int rc2 = hmR0VmxExitToRing3(pVCpu, rcStrict);
10339 if (RT_FAILURE(rc2))
10340 {
10341 pVCpu->hm.s.u32HMError = (uint32_t)VBOXSTRICTRC_VAL(rcStrict);
10342 rcStrict = rc2;
10343 }
10344 Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
10345 Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
10346 return rcStrict;
10347}
10348
10349
10350#ifndef HMVMX_USE_FUNCTION_TABLE
10351DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t rcReason)
10352{
10353#ifdef DEBUG_ramshankar
10354#define VMEXIT_CALL_RET(a_fSave, a_CallExpr) \
10355 do { \
10356 if (a_fSave != 0) \
10357 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL); \
10358 VBOXSTRICTRC rcStrict = a_CallExpr; \
10359 if (a_fSave != 0) \
10360 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
10361 return rcStrict; \
10362 } while (0)
10363#else
10364# define VMEXIT_CALL_RET(a_fSave, a_CallExpr) return a_CallExpr
10365#endif
10366 switch (rcReason)
10367 {
10368 case VMX_EXIT_EPT_MISCONFIG: VMEXIT_CALL_RET(0, hmR0VmxExitEptMisconfig(pVCpu, pVmxTransient));
10369 case VMX_EXIT_EPT_VIOLATION: VMEXIT_CALL_RET(0, hmR0VmxExitEptViolation(pVCpu, pVmxTransient));
10370 case VMX_EXIT_IO_INSTR: VMEXIT_CALL_RET(0, hmR0VmxExitIoInstr(pVCpu, pVmxTransient));
10371 case VMX_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0VmxExitCpuid(pVCpu, pVmxTransient));
10372 case VMX_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0VmxExitRdtsc(pVCpu, pVmxTransient));
10373 case VMX_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0VmxExitRdtscp(pVCpu, pVmxTransient));
10374 case VMX_EXIT_APIC_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitApicAccess(pVCpu, pVmxTransient));
10375 case VMX_EXIT_XCPT_OR_NMI: VMEXIT_CALL_RET(0, hmR0VmxExitXcptOrNmi(pVCpu, pVmxTransient));
10376 case VMX_EXIT_MOV_CRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovCRx(pVCpu, pVmxTransient));
10377 case VMX_EXIT_EXT_INT: VMEXIT_CALL_RET(0, hmR0VmxExitExtInt(pVCpu, pVmxTransient));
10378 case VMX_EXIT_INT_WINDOW: VMEXIT_CALL_RET(0, hmR0VmxExitIntWindow(pVCpu, pVmxTransient));
10379 case VMX_EXIT_TPR_BELOW_THRESHOLD: VMEXIT_CALL_RET(0, hmR0VmxExitTprBelowThreshold(pVCpu, pVmxTransient));
10380 case VMX_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0VmxExitMwait(pVCpu, pVmxTransient));
10381 case VMX_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0VmxExitMonitor(pVCpu, pVmxTransient));
10382 case VMX_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0VmxExitTaskSwitch(pVCpu, pVmxTransient));
10383 case VMX_EXIT_PREEMPT_TIMER: VMEXIT_CALL_RET(0, hmR0VmxExitPreemptTimer(pVCpu, pVmxTransient));
10384 case VMX_EXIT_RDMSR: VMEXIT_CALL_RET(0, hmR0VmxExitRdmsr(pVCpu, pVmxTransient));
10385 case VMX_EXIT_WRMSR: VMEXIT_CALL_RET(0, hmR0VmxExitWrmsr(pVCpu, pVmxTransient));
10386 case VMX_EXIT_VMCALL: VMEXIT_CALL_RET(0, hmR0VmxExitVmcall(pVCpu, pVmxTransient));
10387 case VMX_EXIT_MOV_DRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovDRx(pVCpu, pVmxTransient));
10388 case VMX_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0VmxExitHlt(pVCpu, pVmxTransient));
10389 case VMX_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0VmxExitInvd(pVCpu, pVmxTransient));
10390 case VMX_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0VmxExitInvlpg(pVCpu, pVmxTransient));
10391 case VMX_EXIT_RSM: VMEXIT_CALL_RET(0, hmR0VmxExitRsm(pVCpu, pVmxTransient));
10392 case VMX_EXIT_MTF: VMEXIT_CALL_RET(0, hmR0VmxExitMtf(pVCpu, pVmxTransient));
10393 case VMX_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0VmxExitPause(pVCpu, pVmxTransient));
10394 case VMX_EXIT_XDTR_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitXdtrAccess(pVCpu, pVmxTransient));
10395 case VMX_EXIT_TR_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitXdtrAccess(pVCpu, pVmxTransient));
10396 case VMX_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0VmxExitWbinvd(pVCpu, pVmxTransient));
10397 case VMX_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0VmxExitXsetbv(pVCpu, pVmxTransient));
10398 case VMX_EXIT_RDRAND: VMEXIT_CALL_RET(0, hmR0VmxExitRdrand(pVCpu, pVmxTransient));
10399 case VMX_EXIT_INVPCID: VMEXIT_CALL_RET(0, hmR0VmxExitInvpcid(pVCpu, pVmxTransient));
10400 case VMX_EXIT_GETSEC: VMEXIT_CALL_RET(0, hmR0VmxExitGetsec(pVCpu, pVmxTransient));
10401 case VMX_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0VmxExitRdpmc(pVCpu, pVmxTransient));
10402
10403 case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFault(pVCpu, pVmxTransient);
10404 case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindow(pVCpu, pVmxTransient);
10405 case VMX_EXIT_INIT_SIGNAL: return hmR0VmxExitInitSignal(pVCpu, pVmxTransient);
10406 case VMX_EXIT_SIPI: return hmR0VmxExitSipi(pVCpu, pVmxTransient);
10407 case VMX_EXIT_IO_SMI: return hmR0VmxExitIoSmi(pVCpu, pVmxTransient);
10408 case VMX_EXIT_SMI: return hmR0VmxExitSmi(pVCpu, pVmxTransient);
10409 case VMX_EXIT_ERR_MSR_LOAD: return hmR0VmxExitErrMsrLoad(pVCpu, pVmxTransient);
10410 case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestState(pVCpu, pVmxTransient);
10411 case VMX_EXIT_ERR_MACHINE_CHECK: return hmR0VmxExitErrMachineCheck(pVCpu, pVmxTransient);
10412
10413 case VMX_EXIT_VMCLEAR:
10414 case VMX_EXIT_VMLAUNCH:
10415 case VMX_EXIT_VMPTRLD:
10416 case VMX_EXIT_VMPTRST:
10417 case VMX_EXIT_VMREAD:
10418 case VMX_EXIT_VMRESUME:
10419 case VMX_EXIT_VMWRITE:
10420 case VMX_EXIT_VMXOFF:
10421 case VMX_EXIT_VMXON:
10422 case VMX_EXIT_INVEPT:
10423 case VMX_EXIT_INVVPID:
10424 case VMX_EXIT_VMFUNC:
10425 case VMX_EXIT_XSAVES:
10426 case VMX_EXIT_XRSTORS:
10427 return hmR0VmxExitSetPendingXcptUD(pVCpu, pVmxTransient);
10428
10429 case VMX_EXIT_ENCLS:
10430 case VMX_EXIT_RDSEED: /* only spurious VM-exits, so undefined */
10431 case VMX_EXIT_PML_FULL:
10432 default:
10433 return hmR0VmxExitErrUndefined(pVCpu, pVmxTransient);
10434 }
10435#undef VMEXIT_CALL_RET
10436}
10437#endif /* !HMVMX_USE_FUNCTION_TABLE */
10438
10439
10440#ifdef VBOX_STRICT
10441/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
10442# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
10443 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
10444
10445# define HMVMX_ASSERT_PREEMPT_CPUID() \
10446 do { \
10447 RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
10448 AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
10449 } while (0)
10450
10451# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10452 do { \
10453 AssertPtr((a_pVCpu)); \
10454 AssertPtr((a_pVmxTransient)); \
10455 Assert((a_pVmxTransient)->fVMEntryFailed == false); \
10456 Assert(ASMIntAreEnabled()); \
10457 HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
10458 HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
10459 Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", (a_pVCpu)->idCpu)); \
10460 HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
10461 if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
10462 HMVMX_ASSERT_PREEMPT_CPUID(); \
10463 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10464 } while (0)
10465
10466# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10467 do { \
10468 Log4Func(("\n")); \
10469 } while (0)
10470#else
10471# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10472 do { \
10473 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10474 NOREF((a_pVCpu)); NOREF((a_pVmxTransient)); \
10475 } while (0)
10476# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) do { } while (0)
10477#endif
10478
10479
10480/**
10481 * Advances the guest RIP by the specified number of bytes.
10482 *
10483 * @param pVCpu The cross context virtual CPU structure.
10484 * @param cbInstr Number of bytes to advance the RIP by.
10485 *
10486 * @remarks No-long-jump zone!!!
10487 */
10488DECLINLINE(void) hmR0VmxAdvanceGuestRipBy(PVMCPU pVCpu, uint32_t cbInstr)
10489{
10490 /* Advance the RIP. */
10491 pVCpu->cpum.GstCtx.rip += cbInstr;
10492 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
10493
10494 /* Update interrupt inhibition. */
10495 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10496 && pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
10497 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
10498}
10499
10500
10501/**
10502 * Advances the guest RIP after reading it from the VMCS.
10503 *
10504 * @returns VBox status code, no informational status codes.
10505 * @param pVCpu The cross context virtual CPU structure.
10506 * @param pVmxTransient Pointer to the VMX transient structure.
10507 *
10508 * @remarks No-long-jump zone!!!
10509 */
10510static int hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
10511{
10512 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
10513 rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS);
10514 AssertRCReturn(rc, rc);
10515
10516 hmR0VmxAdvanceGuestRipBy(pVCpu, pVmxTransient->cbInstr);
10517
10518 /*
10519 * Deliver a debug exception to the guest if it is single-stepping. Don't directly inject a #DB but use the
10520 * pending debug exception field as it takes care of priority of events.
10521 *
10522 * See Intel spec. 32.2.1 "Debug Exceptions".
10523 */
10524 if ( !pVCpu->hm.s.fSingleInstruction
10525 && pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
10526 {
10527 rc = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
10528 AssertRCReturn(rc, rc);
10529 }
10530
10531 return VINF_SUCCESS;
10532}
10533
10534
10535/**
10536 * Tries to determine what part of the guest-state VT-x has deemed as invalid
10537 * and update error record fields accordingly.
10538 *
10539 * @return VMX_IGS_* return codes.
10540 * @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
10541 * wrong with the guest state.
10542 *
10543 * @param pVCpu The cross context virtual CPU structure.
10544 *
10545 * @remarks This function assumes our cache of the VMCS controls
10546 * are valid, i.e. hmR0VmxCheckVmcsCtls() succeeded.
10547 */
10548static uint32_t hmR0VmxCheckGuestState(PVMCPU pVCpu)
10549{
10550#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
10551#define HMVMX_CHECK_BREAK(expr, err) if (!(expr)) { \
10552 uError = (err); \
10553 break; \
10554 } else do { } while (0)
10555
10556 int rc;
10557 PVM pVM = pVCpu->CTX_SUFF(pVM);
10558 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
10559 uint32_t uError = VMX_IGS_ERROR;
10560 uint32_t u32Val;
10561 bool const fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
10562
10563 do
10564 {
10565 /*
10566 * CR0.
10567 */
10568 uint32_t fSetCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10569 uint32_t const fZapCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10570 /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG).
10571 See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
10572 if (fUnrestrictedGuest)
10573 fSetCr0 &= ~(X86_CR0_PE | X86_CR0_PG);
10574
10575 uint32_t u32GuestCr0;
10576 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32GuestCr0);
10577 AssertRCBreak(rc);
10578 HMVMX_CHECK_BREAK((u32GuestCr0 & fSetCr0) == fSetCr0, VMX_IGS_CR0_FIXED1);
10579 HMVMX_CHECK_BREAK(!(u32GuestCr0 & ~fZapCr0), VMX_IGS_CR0_FIXED0);
10580 if ( !fUnrestrictedGuest
10581 && (u32GuestCr0 & X86_CR0_PG)
10582 && !(u32GuestCr0 & X86_CR0_PE))
10583 {
10584 HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
10585 }
10586
10587 /*
10588 * CR4.
10589 */
10590 uint64_t const fSetCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10591 uint64_t const fZapCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10592
10593 uint32_t u32GuestCr4;
10594 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCr4);
10595 AssertRCBreak(rc);
10596 HMVMX_CHECK_BREAK((u32GuestCr4 & fSetCr4) == fSetCr4, VMX_IGS_CR4_FIXED1);
10597 HMVMX_CHECK_BREAK(!(u32GuestCr4 & ~fZapCr4), VMX_IGS_CR4_FIXED0);
10598
10599 /*
10600 * IA32_DEBUGCTL MSR.
10601 */
10602 uint64_t u64Val;
10603 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
10604 AssertRCBreak(rc);
10605 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
10606 && (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
10607 {
10608 HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
10609 }
10610 uint64_t u64DebugCtlMsr = u64Val;
10611
10612#ifdef VBOX_STRICT
10613 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
10614 AssertRCBreak(rc);
10615 Assert(u32Val == pVCpu->hm.s.vmx.u32EntryCtls);
10616#endif
10617 bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
10618
10619 /*
10620 * RIP and RFLAGS.
10621 */
10622 uint32_t u32Eflags;
10623#if HC_ARCH_BITS == 64
10624 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RIP, &u64Val);
10625 AssertRCBreak(rc);
10626 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
10627 if ( !fLongModeGuest
10628 || !pCtx->cs.Attr.n.u1Long)
10629 {
10630 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
10631 }
10632 /** @todo If the processor supports N < 64 linear-address bits, bits 63:N
10633 * must be identical if the "IA-32e mode guest" VM-entry
10634 * control is 1 and CS.L is 1. No check applies if the
10635 * CPU supports 64 linear-address bits. */
10636
10637 /* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
10638 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RFLAGS, &u64Val);
10639 AssertRCBreak(rc);
10640 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
10641 VMX_IGS_RFLAGS_RESERVED);
10642 HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10643 u32Eflags = u64Val;
10644#else
10645 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Eflags);
10646 AssertRCBreak(rc);
10647 HMVMX_CHECK_BREAK(!(u32Eflags & 0xffc08028), VMX_IGS_RFLAGS_RESERVED); /* Bit 31:22, Bit 15, 5, 3 MBZ. */
10648 HMVMX_CHECK_BREAK((u32Eflags & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10649#endif
10650
10651 if ( fLongModeGuest
10652 || ( fUnrestrictedGuest
10653 && !(u32GuestCr0 & X86_CR0_PE)))
10654 {
10655 HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
10656 }
10657
10658 uint32_t u32EntryInfo;
10659 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
10660 AssertRCBreak(rc);
10661 if ( VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo)
10662 && VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
10663 {
10664 HMVMX_CHECK_BREAK(u32Eflags & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
10665 }
10666
10667 /*
10668 * 64-bit checks.
10669 */
10670#if HC_ARCH_BITS == 64
10671 if (fLongModeGuest)
10672 {
10673 HMVMX_CHECK_BREAK(u32GuestCr0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE);
10674 HMVMX_CHECK_BREAK(u32GuestCr4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
10675 }
10676
10677 if ( !fLongModeGuest
10678 && (u32GuestCr4 & X86_CR4_PCIDE))
10679 {
10680 HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
10681 }
10682
10683 /** @todo CR3 field must be such that bits 63:52 and bits in the range
10684 * 51:32 beyond the processor's physical-address width are 0. */
10685
10686 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
10687 && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
10688 {
10689 HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
10690 }
10691
10692 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
10693 AssertRCBreak(rc);
10694 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
10695
10696 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
10697 AssertRCBreak(rc);
10698 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
10699#endif
10700
10701 /*
10702 * PERF_GLOBAL MSR.
10703 */
10704 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR)
10705 {
10706 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
10707 AssertRCBreak(rc);
10708 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
10709 VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
10710 }
10711
10712 /*
10713 * PAT MSR.
10714 */
10715 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
10716 {
10717 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
10718 AssertRCBreak(rc);
10719 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
10720 for (unsigned i = 0; i < 8; i++)
10721 {
10722 uint8_t u8Val = (u64Val & 0xff);
10723 if ( u8Val != 0 /* UC */
10724 && u8Val != 1 /* WC */
10725 && u8Val != 4 /* WT */
10726 && u8Val != 5 /* WP */
10727 && u8Val != 6 /* WB */
10728 && u8Val != 7 /* UC- */)
10729 {
10730 HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
10731 }
10732 u64Val >>= 8;
10733 }
10734 }
10735
10736 /*
10737 * EFER MSR.
10738 */
10739 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
10740 {
10741 Assert(pVM->hm.s.vmx.fSupportsVmcsEfer);
10742 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
10743 AssertRCBreak(rc);
10744 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
10745 VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
10746 HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL( pVCpu->hm.s.vmx.u32EntryCtls
10747 & VMX_ENTRY_CTLS_IA32E_MODE_GUEST),
10748 VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
10749 HMVMX_CHECK_BREAK( fUnrestrictedGuest
10750 || !(u32GuestCr0 & X86_CR0_PG)
10751 || RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(u64Val & MSR_K6_EFER_LME),
10752 VMX_IGS_EFER_LMA_LME_MISMATCH);
10753 }
10754
10755 /*
10756 * Segment registers.
10757 */
10758 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10759 || !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
10760 if (!(u32Eflags & X86_EFL_VM))
10761 {
10762 /* CS */
10763 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
10764 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
10765 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
10766 HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
10767 || !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10768 HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
10769 || (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10770 /* CS cannot be loaded with NULL in protected mode. */
10771 HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
10772 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
10773 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
10774 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
10775 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
10776 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
10777 else if (pVM->hm.s.vmx.fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
10778 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
10779 else
10780 HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
10781
10782 /* SS */
10783 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10784 || (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
10785 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
10786 if ( !(pCtx->cr0 & X86_CR0_PE)
10787 || pCtx->cs.Attr.n.u4Type == 3)
10788 {
10789 HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
10790 }
10791 if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
10792 {
10793 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
10794 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
10795 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
10796 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
10797 HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
10798 || !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10799 HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
10800 || (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10801 }
10802
10803 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSegmenReg(). */
10804 if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
10805 {
10806 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
10807 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
10808 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10809 || pCtx->ds.Attr.n.u4Type > 11
10810 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10811 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
10812 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
10813 HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
10814 || !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10815 HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
10816 || (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10817 HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10818 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
10819 }
10820 if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
10821 {
10822 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
10823 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
10824 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10825 || pCtx->es.Attr.n.u4Type > 11
10826 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10827 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
10828 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
10829 HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
10830 || !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10831 HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
10832 || (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10833 HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10834 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
10835 }
10836 if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
10837 {
10838 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
10839 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
10840 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10841 || pCtx->fs.Attr.n.u4Type > 11
10842 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
10843 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
10844 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
10845 HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
10846 || !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10847 HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
10848 || (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10849 HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10850 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
10851 }
10852 if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
10853 {
10854 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
10855 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
10856 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10857 || pCtx->gs.Attr.n.u4Type > 11
10858 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
10859 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
10860 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
10861 HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
10862 || !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10863 HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
10864 || (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10865 HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10866 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
10867 }
10868 /* 64-bit capable CPUs. */
10869#if HC_ARCH_BITS == 64
10870 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10871 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10872 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10873 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10874 HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10875 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
10876 VMX_IGS_LONGMODE_SS_BASE_INVALID);
10877 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
10878 VMX_IGS_LONGMODE_DS_BASE_INVALID);
10879 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
10880 VMX_IGS_LONGMODE_ES_BASE_INVALID);
10881#endif
10882 }
10883 else
10884 {
10885 /* V86 mode checks. */
10886 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
10887 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
10888 {
10889 u32CSAttr = 0xf3; u32SSAttr = 0xf3;
10890 u32DSAttr = 0xf3; u32ESAttr = 0xf3;
10891 u32FSAttr = 0xf3; u32GSAttr = 0xf3;
10892 }
10893 else
10894 {
10895 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
10896 u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
10897 u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
10898 }
10899
10900 /* CS */
10901 HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
10902 HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
10903 HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
10904 /* SS */
10905 HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
10906 HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
10907 HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
10908 /* DS */
10909 HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
10910 HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
10911 HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
10912 /* ES */
10913 HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
10914 HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
10915 HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
10916 /* FS */
10917 HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
10918 HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
10919 HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
10920 /* GS */
10921 HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
10922 HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
10923 HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
10924 /* 64-bit capable CPUs. */
10925#if HC_ARCH_BITS == 64
10926 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10927 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10928 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10929 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10930 HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10931 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
10932 VMX_IGS_LONGMODE_SS_BASE_INVALID);
10933 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
10934 VMX_IGS_LONGMODE_DS_BASE_INVALID);
10935 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
10936 VMX_IGS_LONGMODE_ES_BASE_INVALID);
10937#endif
10938 }
10939
10940 /*
10941 * TR.
10942 */
10943 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
10944 /* 64-bit capable CPUs. */
10945#if HC_ARCH_BITS == 64
10946 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
10947#endif
10948 if (fLongModeGuest)
10949 {
10950 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
10951 VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
10952 }
10953 else
10954 {
10955 HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
10956 || pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
10957 VMX_IGS_TR_ATTR_TYPE_INVALID);
10958 }
10959 HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
10960 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
10961 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
10962 HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
10963 || !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10964 HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
10965 || (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10966 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
10967
10968 /*
10969 * GDTR and IDTR.
10970 */
10971#if HC_ARCH_BITS == 64
10972 rc = VMXReadVmcs64(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
10973 AssertRCBreak(rc);
10974 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
10975
10976 rc = VMXReadVmcs64(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
10977 AssertRCBreak(rc);
10978 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
10979#endif
10980
10981 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
10982 AssertRCBreak(rc);
10983 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10984
10985 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
10986 AssertRCBreak(rc);
10987 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10988
10989 /*
10990 * Guest Non-Register State.
10991 */
10992 /* Activity State. */
10993 uint32_t u32ActivityState;
10994 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
10995 AssertRCBreak(rc);
10996 HMVMX_CHECK_BREAK( !u32ActivityState
10997 || (u32ActivityState & RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Misc, VMX_BF_MISC_ACTIVITY_STATES)),
10998 VMX_IGS_ACTIVITY_STATE_INVALID);
10999 HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
11000 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
11001 uint32_t u32IntrState;
11002 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32IntrState);
11003 AssertRCBreak(rc);
11004 if ( u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
11005 || u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11006 {
11007 HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
11008 }
11009
11010 /** @todo Activity state and injecting interrupts. Left as a todo since we
11011 * currently don't use activity states but ACTIVE. */
11012
11013 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
11014 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
11015
11016 /* Guest interruptibility-state. */
11017 HMVMX_CHECK_BREAK(!(u32IntrState & 0xfffffff0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
11018 HMVMX_CHECK_BREAK((u32IntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
11019 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
11020 VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
11021 HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
11022 || !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
11023 VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
11024 if (VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo))
11025 {
11026 if (VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
11027 {
11028 HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11029 && !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
11030 VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
11031 }
11032 else if (VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_NMI)
11033 {
11034 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
11035 VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
11036 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
11037 VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
11038 }
11039 }
11040 /** @todo Assumes the processor is not in SMM. */
11041 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
11042 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
11043 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
11044 || (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
11045 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
11046 if ( (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
11047 && VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo)
11048 && VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_NMI)
11049 {
11050 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI),
11051 VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
11052 }
11053
11054 /* Pending debug exceptions. */
11055#if HC_ARCH_BITS == 64
11056 rc = VMXReadVmcs64(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u64Val);
11057 AssertRCBreak(rc);
11058 /* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
11059 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
11060 u32Val = u64Val; /* For pending debug exceptions checks below. */
11061#else
11062 rc = VMXReadVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u32Val);
11063 AssertRCBreak(rc);
11064 /* Bits 31:15, Bit 13, Bits 11:4 MBZ. */
11065 HMVMX_CHECK_BREAK(!(u32Val & 0xffffaff0), VMX_IGS_PENDING_DEBUG_RESERVED);
11066#endif
11067
11068 if ( (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11069 || (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
11070 || u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
11071 {
11072 if ( (u32Eflags & X86_EFL_TF)
11073 && !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11074 {
11075 /* Bit 14 is PendingDebug.BS. */
11076 HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
11077 }
11078 if ( !(u32Eflags & X86_EFL_TF)
11079 || (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11080 {
11081 /* Bit 14 is PendingDebug.BS. */
11082 HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
11083 }
11084 }
11085
11086 /* VMCS link pointer. */
11087 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
11088 AssertRCBreak(rc);
11089 if (u64Val != UINT64_C(0xffffffffffffffff))
11090 {
11091 HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
11092 /** @todo Bits beyond the processor's physical-address width MBZ. */
11093 /** @todo 32-bit located in memory referenced by value of this field (as a
11094 * physical address) must contain the processor's VMCS revision ID. */
11095 /** @todo SMM checks. */
11096 }
11097
11098 /** @todo Checks on Guest Page-Directory-Pointer-Table Entries when guest is
11099 * not using Nested Paging? */
11100 if ( pVM->hm.s.fNestedPaging
11101 && !fLongModeGuest
11102 && CPUMIsGuestInPAEModeEx(pCtx))
11103 {
11104 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);
11105 AssertRCBreak(rc);
11106 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11107
11108 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);
11109 AssertRCBreak(rc);
11110 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11111
11112 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);
11113 AssertRCBreak(rc);
11114 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11115
11116 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);
11117 AssertRCBreak(rc);
11118 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11119 }
11120
11121 /* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
11122 if (uError == VMX_IGS_ERROR)
11123 uError = VMX_IGS_REASON_NOT_FOUND;
11124 } while (0);
11125
11126 pVCpu->hm.s.u32HMError = uError;
11127 return uError;
11128
11129#undef HMVMX_ERROR_BREAK
11130#undef HMVMX_CHECK_BREAK
11131}
11132
11133
11134/** @name VM-exit handlers.
11135 * @{
11136 */
11137/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11138/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
11139/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11140
11141/**
11142 * VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
11143 */
11144HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11145{
11146 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11147 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
11148 /* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
11149 if (VMMR0ThreadCtxHookIsEnabled(pVCpu))
11150 return VINF_SUCCESS;
11151 return VINF_EM_RAW_INTERRUPT;
11152}
11153
11154
11155/**
11156 * VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
11157 */
11158HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11159{
11160 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11161 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
11162
11163 int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
11164 AssertRCReturn(rc, rc);
11165
11166 uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
11167 Assert( !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
11168 && uIntType != VMX_EXIT_INT_INFO_TYPE_EXT_INT);
11169 Assert(VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
11170
11171 if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
11172 {
11173 /*
11174 * This cannot be a guest NMI as the only way for the guest to receive an NMI is if we
11175 * injected it ourselves and anything we inject is not going to cause a VM-exit directly
11176 * for the event being injected[1]. Go ahead and dispatch the NMI to the host[2].
11177 *
11178 * [1] -- See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
11179 * [2] -- See Intel spec. 27.5.5 "Updating Non-Register State".
11180 */
11181 VMXDispatchHostNmi();
11182 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
11183 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11184 return VINF_SUCCESS;
11185 }
11186
11187 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
11188 VBOXSTRICTRC rcStrictRc1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
11189 if (RT_UNLIKELY(rcStrictRc1 == VINF_SUCCESS))
11190 { /* likely */ }
11191 else
11192 {
11193 if (rcStrictRc1 == VINF_HM_DOUBLE_FAULT)
11194 rcStrictRc1 = VINF_SUCCESS;
11195 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11196 return rcStrictRc1;
11197 }
11198
11199 uint32_t uExitIntInfo = pVmxTransient->uExitIntInfo;
11200 uint32_t uVector = VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo);
11201 switch (uIntType)
11202 {
11203 case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT: /* Privileged software exception. (#DB from ICEBP) */
11204 Assert(uVector == X86_XCPT_DB);
11205 RT_FALL_THRU();
11206 case VMX_EXIT_INT_INFO_TYPE_SW_XCPT: /* Software exception. (#BP or #OF) */
11207 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF || uIntType == VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT);
11208 RT_FALL_THRU();
11209 case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
11210 {
11211 /*
11212 * If there's any exception caused as a result of event injection, the resulting
11213 * secondary/final execption will be pending, we shall continue guest execution
11214 * after injecting the event. The page-fault case is complicated and we manually
11215 * handle any currently pending event in hmR0VmxExitXcptPF.
11216 */
11217 if (!pVCpu->hm.s.Event.fPending)
11218 { /* likely */ }
11219 else if (uVector != X86_XCPT_PF)
11220 {
11221 rc = VINF_SUCCESS;
11222 break;
11223 }
11224
11225 switch (uVector)
11226 {
11227 case X86_XCPT_PF: rc = hmR0VmxExitXcptPF(pVCpu, pVmxTransient); break;
11228 case X86_XCPT_GP: rc = hmR0VmxExitXcptGP(pVCpu, pVmxTransient); break;
11229 case X86_XCPT_MF: rc = hmR0VmxExitXcptMF(pVCpu, pVmxTransient); break;
11230 case X86_XCPT_DB: rc = hmR0VmxExitXcptDB(pVCpu, pVmxTransient); break;
11231 case X86_XCPT_BP: rc = hmR0VmxExitXcptBP(pVCpu, pVmxTransient); break;
11232 case X86_XCPT_AC: rc = hmR0VmxExitXcptAC(pVCpu, pVmxTransient); break;
11233
11234 case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
11235 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11236 case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF);
11237 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11238 case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
11239 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11240 case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
11241 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11242 case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
11243 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11244 case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
11245 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11246 case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS);
11247 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11248 default:
11249 {
11250 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
11251 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11252 {
11253 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
11254 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
11255 Assert(CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx));
11256
11257 rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0);
11258 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11259 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
11260 AssertRCReturn(rc, rc);
11261 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(uExitIntInfo),
11262 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode,
11263 0 /* GCPtrFaultAddress */);
11264 }
11265 else
11266 {
11267 AssertMsgFailed(("Unexpected VM-exit caused by exception %#x\n", uVector));
11268 pVCpu->hm.s.u32HMError = uVector;
11269 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
11270 }
11271 break;
11272 }
11273 }
11274 break;
11275 }
11276
11277 default:
11278 {
11279 pVCpu->hm.s.u32HMError = uExitIntInfo;
11280 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
11281 AssertMsgFailed(("Unexpected interruption info %#x\n", VMX_EXIT_INT_INFO_TYPE(uExitIntInfo)));
11282 break;
11283 }
11284 }
11285 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11286 return rc;
11287}
11288
11289
11290/**
11291 * VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
11292 */
11293HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11294{
11295 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11296
11297 /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
11298 hmR0VmxClearIntWindowExitVmcs(pVCpu);
11299
11300 /* Deliver the pending interrupts via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11301 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
11302 return VINF_SUCCESS;
11303}
11304
11305
11306/**
11307 * VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
11308 */
11309HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11310{
11311 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11312 if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)))
11313 {
11314 AssertMsgFailed(("Unexpected NMI-window exit.\n"));
11315 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11316 }
11317
11318 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
11319
11320 /*
11321 * If block-by-STI is set when we get this VM-exit, it means the CPU doesn't block NMIs following STI.
11322 * It is therefore safe to unblock STI and deliver the NMI ourselves. See @bugref{7445}.
11323 */
11324 uint32_t fIntrState = 0;
11325 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
11326 AssertRCReturn(rc, rc);
11327
11328 bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
11329 if ( fBlockSti
11330 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
11331 {
11332 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
11333 }
11334
11335 /* Indicate that we no longer need to VM-exit when the guest is ready to receive NMIs, it is now ready */
11336 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
11337
11338 /* Deliver the pending NMI via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11339 return VINF_SUCCESS;
11340}
11341
11342
11343/**
11344 * VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
11345 */
11346HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11347{
11348 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11349 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11350}
11351
11352
11353/**
11354 * VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
11355 */
11356HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11357{
11358 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11359 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11360}
11361
11362
11363/**
11364 * VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
11365 */
11366HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11367{
11368 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11369
11370 /*
11371 * Get the state we need and update the exit history entry.
11372 */
11373 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11374 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RCX);
11375 AssertRCReturn(rc, rc);
11376
11377 VBOXSTRICTRC rcStrict;
11378 PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
11379 EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_CPUID),
11380 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
11381 if (!pExitRec)
11382 {
11383 /*
11384 * Regular CPUID instruction execution.
11385 */
11386 rcStrict = IEMExecDecodedCpuid(pVCpu, pVmxTransient->cbInstr);
11387 if (rcStrict == VINF_SUCCESS)
11388 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_RAX
11389 | HM_CHANGED_GUEST_RCX | HM_CHANGED_GUEST_RDX | HM_CHANGED_GUEST_RBX);
11390 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11391 {
11392 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11393 rcStrict = VINF_SUCCESS;
11394 }
11395 }
11396 else
11397 {
11398 /*
11399 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
11400 */
11401 int rc2 = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
11402 AssertRCReturn(rc2, rc2);
11403
11404 Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
11405 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
11406
11407 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
11408 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
11409
11410 Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
11411 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
11412 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
11413 }
11414 return rcStrict;
11415}
11416
11417
11418/**
11419 * VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
11420 */
11421HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11422{
11423 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11424 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR4);
11425 AssertRCReturn(rc, rc);
11426
11427 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_SMXE)
11428 return VINF_EM_RAW_EMULATE_INSTR;
11429
11430 AssertMsgFailed(("hmR0VmxExitGetsec: unexpected VM-exit when CR4.SMXE is 0.\n"));
11431 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11432}
11433
11434
11435/**
11436 * VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
11437 */
11438HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11439{
11440 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11441 int rc = hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
11442 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11443 AssertRCReturn(rc, rc);
11444
11445 VBOXSTRICTRC rcStrict = IEMExecDecodedRdtsc(pVCpu, pVmxTransient->cbInstr);
11446 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11447 {
11448 /* If we get a spurious VM-exit when offsetting is enabled,
11449 we must reset offsetting on VM-reentry. See @bugref{6634}. */
11450 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
11451 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11452 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
11453 | HM_CHANGED_GUEST_RAX | HM_CHANGED_GUEST_RDX);
11454 }
11455 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11456 {
11457 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11458 rcStrict = VINF_SUCCESS;
11459 }
11460 return rcStrict;
11461}
11462
11463
11464/**
11465 * VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
11466 */
11467HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11468{
11469 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11470 int rc = hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_TSC_AUX);
11471 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11472 AssertRCReturn(rc, rc);
11473
11474 VBOXSTRICTRC rcStrict = IEMExecDecodedRdtscp(pVCpu, pVmxTransient->cbInstr);
11475 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11476 {
11477 /* If we get a spurious VM-exit when offsetting is enabled,
11478 we must reset offsetting on VM-reentry. See @bugref{6634}. */
11479 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
11480 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11481 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
11482 | HM_CHANGED_GUEST_RAX | HM_CHANGED_GUEST_RDX | HM_CHANGED_GUEST_RCX);
11483 }
11484 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11485 {
11486 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11487 rcStrict = VINF_SUCCESS;
11488 }
11489 return rcStrict;
11490}
11491
11492
11493/**
11494 * VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
11495 */
11496HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11497{
11498 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11499 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11500 AssertRCReturn(rc, rc);
11501
11502 PVM pVM = pVCpu->CTX_SUFF(pVM);
11503 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11504 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11505 if (RT_LIKELY(rc == VINF_SUCCESS))
11506 {
11507 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11508 Assert(pVmxTransient->cbInstr == 2);
11509 }
11510 else
11511 {
11512 AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
11513 rc = VERR_EM_INTERPRETER;
11514 }
11515 return rc;
11516}
11517
11518
11519/**
11520 * VM-exit handler for VMCALL (VMX_EXIT_VMCALL). Unconditional VM-exit.
11521 */
11522HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11523{
11524 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11525
11526 VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
11527 if (EMAreHypercallInstructionsEnabled(pVCpu))
11528 {
11529 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_SS
11530 | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
11531 AssertRCReturn(rc, rc);
11532
11533 /* Perform the hypercall. */
11534 rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
11535 if (rcStrict == VINF_SUCCESS)
11536 {
11537 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11538 AssertRCReturn(rc, rc);
11539 }
11540 else
11541 Assert( rcStrict == VINF_GIM_R3_HYPERCALL
11542 || rcStrict == VINF_GIM_HYPERCALL_CONTINUING
11543 || RT_FAILURE(rcStrict));
11544
11545 /* If the hypercall changes anything other than guest's general-purpose registers,
11546 we would need to reload the guest changed bits here before VM-entry. */
11547 }
11548 else
11549 Log4Func(("Hypercalls not enabled\n"));
11550
11551 /* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
11552 if (RT_FAILURE(rcStrict))
11553 {
11554 hmR0VmxSetPendingXcptUD(pVCpu);
11555 rcStrict = VINF_SUCCESS;
11556 }
11557
11558 return rcStrict;
11559}
11560
11561
11562/**
11563 * VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
11564 */
11565HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11566{
11567 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11568 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging || pVCpu->hm.s.fUsingDebugLoop);
11569
11570 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
11571 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11572 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK | CPUMCTX_EXTRN_DS);
11573 AssertRCReturn(rc, rc);
11574
11575 VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, pVmxTransient->cbInstr, pVmxTransient->uExitQual);
11576
11577 if (rcStrict == VINF_SUCCESS || rcStrict == VINF_PGM_SYNC_CR3)
11578 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11579 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11580 {
11581 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11582 rcStrict = VINF_SUCCESS;
11583 }
11584 else
11585 AssertMsgFailed(("Unexpected IEMExecDecodedInvlpg(%#RX64) sttus: %Rrc\n", pVmxTransient->uExitQual,
11586 VBOXSTRICTRC_VAL(rcStrict)));
11587 return rcStrict;
11588}
11589
11590
11591/**
11592 * VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
11593 */
11594HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11595{
11596 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11597 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11598 AssertRCReturn(rc, rc);
11599
11600 PVM pVM = pVCpu->CTX_SUFF(pVM);
11601 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11602 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11603 if (RT_LIKELY(rc == VINF_SUCCESS))
11604 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11605 else
11606 {
11607 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
11608 rc = VERR_EM_INTERPRETER;
11609 }
11610 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
11611 return rc;
11612}
11613
11614
11615/**
11616 * VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
11617 */
11618HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11619{
11620 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11621 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11622 AssertRCReturn(rc, rc);
11623
11624 PVM pVM = pVCpu->CTX_SUFF(pVM);
11625 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11626 VBOXSTRICTRC rc2 = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11627 rc = VBOXSTRICTRC_VAL(rc2);
11628 if (RT_LIKELY( rc == VINF_SUCCESS
11629 || rc == VINF_EM_HALT))
11630 {
11631 int rc3 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11632 AssertRCReturn(rc3, rc3);
11633
11634 if ( rc == VINF_EM_HALT
11635 && EMMonitorWaitShouldContinue(pVCpu, pCtx))
11636 rc = VINF_SUCCESS;
11637 }
11638 else
11639 {
11640 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
11641 rc = VERR_EM_INTERPRETER;
11642 }
11643 AssertMsg(rc == VINF_SUCCESS || rc == VINF_EM_HALT || rc == VERR_EM_INTERPRETER,
11644 ("hmR0VmxExitMwait: failed, invalid error code %Rrc\n", rc));
11645 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
11646 return rc;
11647}
11648
11649
11650/**
11651 * VM-exit handler for RSM (VMX_EXIT_RSM). Unconditional VM-exit.
11652 */
11653HMVMX_EXIT_NSRC_DECL hmR0VmxExitRsm(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11654{
11655 /*
11656 * Execution of RSM outside of SMM mode causes #UD regardless of VMX root or VMX non-root
11657 * mode. In theory, we should never get this VM-exit. This can happen only if dual-monitor
11658 * treatment of SMI and VMX is enabled, which can (only?) be done by executing VMCALL in
11659 * VMX root operation. If we get here, something funny is going on.
11660 *
11661 * See Intel spec. 33.15.5 "Enabling the Dual-Monitor Treatment".
11662 */
11663 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11664 AssertMsgFailed(("Unexpected RSM VM-exit\n"));
11665 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11666}
11667
11668
11669/**
11670 * VM-exit handler for SMI (VMX_EXIT_SMI). Unconditional VM-exit.
11671 */
11672HMVMX_EXIT_NSRC_DECL hmR0VmxExitSmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11673{
11674 /*
11675 * This can only happen if we support dual-monitor treatment of SMI, which can be activated
11676 * by executing VMCALL in VMX root operation. Only an STM (SMM transfer monitor) would get
11677 * this VM-exit when we (the executive monitor) execute a VMCALL in VMX root mode or receive
11678 * an SMI. If we get here, something funny is going on.
11679 *
11680 * See Intel spec. 33.15.6 "Activating the Dual-Monitor Treatment"
11681 * See Intel spec. 25.3 "Other Causes of VM-Exits"
11682 */
11683 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11684 AssertMsgFailed(("Unexpected SMI VM-exit\n"));
11685 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11686}
11687
11688
11689/**
11690 * VM-exit handler for IO SMI (VMX_EXIT_IO_SMI). Unconditional VM-exit.
11691 */
11692HMVMX_EXIT_NSRC_DECL hmR0VmxExitIoSmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11693{
11694 /* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
11695 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11696 AssertMsgFailed(("Unexpected IO SMI VM-exit\n"));
11697 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11698}
11699
11700
11701/**
11702 * VM-exit handler for SIPI (VMX_EXIT_SIPI). Conditional VM-exit.
11703 */
11704HMVMX_EXIT_NSRC_DECL hmR0VmxExitSipi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11705{
11706 /*
11707 * SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest activity state is used.
11708 * We don't make use of it as our guests don't have direct access to the host LAPIC.
11709 * See Intel spec. 25.3 "Other Causes of VM-exits".
11710 */
11711 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11712 AssertMsgFailed(("Unexpected SIPI VM-exit\n"));
11713 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11714}
11715
11716
11717/**
11718 * VM-exit handler for INIT signal (VMX_EXIT_INIT_SIGNAL). Unconditional
11719 * VM-exit.
11720 */
11721HMVMX_EXIT_NSRC_DECL hmR0VmxExitInitSignal(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11722{
11723 /*
11724 * INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
11725 * See Intel spec. 33.14.1 Default Treatment of SMI Delivery" and Intel spec. 29.3 "VMX Instructions" for "VMXON".
11726 *
11727 * It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these VM-exits.
11728 * See Intel spec. "23.8 Restrictions on VMX operation".
11729 */
11730 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11731 return VINF_SUCCESS;
11732}
11733
11734
11735/**
11736 * VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
11737 * VM-exit.
11738 */
11739HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11740{
11741 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11742 return VINF_EM_RESET;
11743}
11744
11745
11746/**
11747 * VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
11748 */
11749HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11750{
11751 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11752 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_HLT_EXIT);
11753
11754 int rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11755 rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
11756 AssertRCReturn(rc, rc);
11757
11758 if (EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx)) /* Requires eflags. */
11759 rc = VINF_SUCCESS;
11760 else
11761 rc = VINF_EM_HALT;
11762
11763 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
11764 if (rc != VINF_SUCCESS)
11765 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
11766 return rc;
11767}
11768
11769
11770/**
11771 * VM-exit handler for instructions that result in a \#UD exception delivered to
11772 * the guest.
11773 */
11774HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11775{
11776 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11777 hmR0VmxSetPendingXcptUD(pVCpu);
11778 return VINF_SUCCESS;
11779}
11780
11781
11782/**
11783 * VM-exit handler for expiry of the VMX preemption timer.
11784 */
11785HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11786{
11787 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11788
11789 /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
11790 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11791
11792 /* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
11793 PVM pVM = pVCpu->CTX_SUFF(pVM);
11794 bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
11795 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
11796 return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
11797}
11798
11799
11800/**
11801 * VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
11802 */
11803HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11804{
11805 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11806
11807 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11808 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_CR4);
11809 AssertRCReturn(rc, rc);
11810
11811 VBOXSTRICTRC rcStrict = IEMExecDecodedXsetbv(pVCpu, pVmxTransient->cbInstr);
11812 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
11813 : HM_CHANGED_RAISED_XCPT_MASK);
11814
11815 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11816 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
11817
11818 return rcStrict;
11819}
11820
11821
11822/**
11823 * VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
11824 */
11825HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11826{
11827 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11828 /** @todo Use VM-exit instruction information. */
11829 return VERR_EM_INTERPRETER;
11830}
11831
11832
11833/**
11834 * VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE).
11835 * Error VM-exit.
11836 */
11837HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11838{
11839 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
11840 AssertRCReturn(rc, rc);
11841 rc = hmR0VmxCheckVmcsCtls(pVCpu);
11842 if (RT_FAILURE(rc))
11843 return rc;
11844
11845 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu);
11846 NOREF(uInvalidReason);
11847
11848#ifdef VBOX_STRICT
11849 uint32_t fIntrState;
11850 RTHCUINTREG uHCReg;
11851 uint64_t u64Val;
11852 uint32_t u32Val;
11853
11854 rc = hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
11855 rc |= hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
11856 rc |= hmR0VmxReadEntryInstrLenVmcs(pVmxTransient);
11857 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
11858 AssertRCReturn(rc, rc);
11859
11860 Log4(("uInvalidReason %u\n", uInvalidReason));
11861 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntInfo));
11862 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
11863 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
11864 Log4(("VMX_VMCS32_GUEST_INT_STATE %#RX32\n", fIntrState));
11865
11866 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val); AssertRC(rc);
11867 Log4(("VMX_VMCS_GUEST_CR0 %#RX32\n", u32Val));
11868 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
11869 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
11870 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
11871 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11872 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
11873 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
11874 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
11875 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11876 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
11877 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
11878
11879 hmR0DumpRegs(pVCpu);
11880#else
11881 NOREF(pVmxTransient);
11882#endif
11883
11884 return VERR_VMX_INVALID_GUEST_STATE;
11885}
11886
11887
11888/**
11889 * VM-exit handler for VM-entry failure due to an MSR-load
11890 * (VMX_EXIT_ERR_MSR_LOAD). Error VM-exit.
11891 */
11892HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11893{
11894 AssertMsgFailed(("Unexpected MSR-load exit\n"));
11895 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11896}
11897
11898
11899/**
11900 * VM-exit handler for VM-entry failure due to a machine-check event
11901 * (VMX_EXIT_ERR_MACHINE_CHECK). Error VM-exit.
11902 */
11903HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11904{
11905 AssertMsgFailed(("Unexpected machine-check event exit\n"));
11906 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11907}
11908
11909
11910/**
11911 * VM-exit handler for all undefined reasons. Should never ever happen.. in
11912 * theory.
11913 */
11914HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrUndefined(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11915{
11916 RT_NOREF2(pVCpu, pVmxTransient);
11917 AssertMsgFailed(("Huh!? Undefined VM-exit reason %d\n", pVmxTransient->uExitReason));
11918 return VERR_VMX_UNDEFINED_EXIT_CODE;
11919}
11920
11921
11922/**
11923 * VM-exit handler for XDTR (LGDT, SGDT, LIDT, SIDT) accesses
11924 * (VMX_EXIT_XDTR_ACCESS) and LDT and TR access (LLDT, LTR, SLDT, STR).
11925 * Conditional VM-exit.
11926 */
11927HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11928{
11929 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11930
11931 /* By default, we don't enable VMX_PROC_CTLS2_DESCRIPTOR_TABLE_EXIT. */
11932 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
11933 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT)
11934 return VERR_EM_INTERPRETER;
11935 AssertMsgFailed(("Unexpected XDTR access\n"));
11936 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11937}
11938
11939
11940/**
11941 * VM-exit handler for RDRAND (VMX_EXIT_RDRAND). Conditional VM-exit.
11942 */
11943HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11944{
11945 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11946
11947 /* By default, we don't enable VMX_PROC_CTLS2_RDRAND_EXIT. */
11948 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT)
11949 return VERR_EM_INTERPRETER;
11950 AssertMsgFailed(("Unexpected RDRAND exit\n"));
11951 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11952}
11953
11954
11955/**
11956 * VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
11957 */
11958HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11959{
11960 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11961
11962 /** @todo Optimize this: We currently drag in in the whole MSR state
11963 * (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
11964 * MSRs required. That would require changes to IEM and possibly CPUM too.
11965 * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
11966 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx; NOREF(idMsr); /* Save it. */
11967 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11968 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
11969 AssertRCReturn(rc, rc);
11970
11971 Log4Func(("ecx=%#RX32\n", idMsr));
11972
11973#ifdef VBOX_STRICT
11974 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
11975 {
11976 if ( hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr)
11977 && idMsr != MSR_K6_EFER)
11978 {
11979 AssertMsgFailed(("Unexpected RDMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n", idMsr));
11980 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11981 }
11982 if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
11983 {
11984 VMXMSREXITREAD enmRead;
11985 VMXMSREXITWRITE enmWrite;
11986 int rc2 = hmR0VmxGetMsrPermission(pVCpu, idMsr, &enmRead, &enmWrite);
11987 AssertRCReturn(rc2, rc2);
11988 if (enmRead == VMXMSREXIT_PASSTHRU_READ)
11989 {
11990 AssertMsgFailed(("Unexpected RDMSR for a passthru lazy-restore MSR. ecx=%#RX32\n", idMsr));
11991 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11992 }
11993 }
11994 }
11995#endif
11996
11997 VBOXSTRICTRC rcStrict = IEMExecDecodedRdmsr(pVCpu, pVmxTransient->cbInstr);
11998 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
11999 if (rcStrict == VINF_SUCCESS)
12000 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
12001 | HM_CHANGED_GUEST_RAX | HM_CHANGED_GUEST_RDX);
12002 else if (rcStrict == VINF_IEM_RAISED_XCPT)
12003 {
12004 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
12005 rcStrict = VINF_SUCCESS;
12006 }
12007 else
12008 AssertMsg(rcStrict == VINF_CPUM_R3_MSR_READ, ("Unexpected IEMExecDecodedRdmsr status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12009
12010 return rcStrict;
12011}
12012
12013
12014/**
12015 * VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
12016 */
12017HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12018{
12019 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12020
12021 /** @todo Optimize this: We currently drag in in the whole MSR state
12022 * (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
12023 * MSRs required. That would require changes to IEM and possibly CPUM too.
12024 * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
12025 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx; /* Save it. */
12026 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12027 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
12028 AssertRCReturn(rc, rc);
12029
12030 Log4Func(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", idMsr, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.eax));
12031
12032 VBOXSTRICTRC rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmxTransient->cbInstr);
12033 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
12034
12035 if (rcStrict == VINF_SUCCESS)
12036 {
12037 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
12038
12039 /* If this is an X2APIC WRMSR access, update the APIC state as well. */
12040 if ( idMsr == MSR_IA32_APICBASE
12041 || ( idMsr >= MSR_IA32_X2APIC_START
12042 && idMsr <= MSR_IA32_X2APIC_END))
12043 {
12044 /*
12045 * We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
12046 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before IEM changes it.
12047 */
12048 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
12049 }
12050 else if (idMsr == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
12051 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
12052 else if (idMsr == MSR_K6_EFER)
12053 {
12054 /*
12055 * If the guest touches EFER we need to update the VM-Entry and VM-Exit controls as well,
12056 * even if it is -not- touching bits that cause paging mode changes (LMA/LME). We care about
12057 * the other bits as well, SCE and NXE. See @bugref{7368}.
12058 */
12059 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR | HM_CHANGED_VMX_ENTRY_CTLS
12060 | HM_CHANGED_VMX_EXIT_CTLS);
12061 }
12062
12063 /* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not supported. */
12064 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
12065 {
12066 switch (idMsr)
12067 {
12068 case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
12069 case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
12070 case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
12071 case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
12072 case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
12073 case MSR_K6_EFER: /* Nothing to do, already handled above. */ break;
12074 default:
12075 {
12076 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
12077 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
12078 else if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
12079 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_LAZY_MSRS);
12080 break;
12081 }
12082 }
12083 }
12084#ifdef VBOX_STRICT
12085 else
12086 {
12087 /* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
12088 switch (idMsr)
12089 {
12090 case MSR_IA32_SYSENTER_CS:
12091 case MSR_IA32_SYSENTER_EIP:
12092 case MSR_IA32_SYSENTER_ESP:
12093 case MSR_K8_FS_BASE:
12094 case MSR_K8_GS_BASE:
12095 {
12096 AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", idMsr));
12097 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12098 }
12099
12100 /* Writes to MSRs in auto-load/store area/swapped MSRs, shouldn't cause VM-exits with MSR-bitmaps. */
12101 default:
12102 {
12103 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
12104 {
12105 /* EFER writes are always intercepted, see hmR0VmxExportGuestMsrs(). */
12106 if (idMsr != MSR_K6_EFER)
12107 {
12108 AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12109 idMsr));
12110 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12111 }
12112 }
12113
12114 if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
12115 {
12116 VMXMSREXITREAD enmRead;
12117 VMXMSREXITWRITE enmWrite;
12118 int rc2 = hmR0VmxGetMsrPermission(pVCpu, idMsr, &enmRead, &enmWrite);
12119 AssertRCReturn(rc2, rc2);
12120 if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)
12121 {
12122 AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", idMsr));
12123 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12124 }
12125 }
12126 break;
12127 }
12128 }
12129 }
12130#endif /* VBOX_STRICT */
12131 }
12132 else if (rcStrict == VINF_IEM_RAISED_XCPT)
12133 {
12134 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
12135 rcStrict = VINF_SUCCESS;
12136 }
12137 else
12138 AssertMsg(rcStrict == VINF_CPUM_R3_MSR_WRITE, ("Unexpected IEMExecDecodedWrmsr status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12139
12140 return rcStrict;
12141}
12142
12143
12144/**
12145 * VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
12146 */
12147HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12148{
12149 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12150 /** @todo The guest has likely hit a contended spinlock. We might want to
12151 * poke a schedule different guest VCPU. */
12152 return VINF_EM_RAW_INTERRUPT;
12153}
12154
12155
12156/**
12157 * VM-exit handler for when the TPR value is lowered below the specified
12158 * threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
12159 */
12160HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12161{
12162 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12163 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
12164
12165 /*
12166 * The TPR shadow would've been synced with the APIC TPR in hmR0VmxPostRunGuest(). We'll re-evaluate
12167 * pending interrupts and inject them before the next VM-entry so we can just continue execution here.
12168 */
12169 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
12170 return VINF_SUCCESS;
12171}
12172
12173
12174/**
12175 * VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
12176 * VM-exit.
12177 *
12178 * @retval VINF_SUCCESS when guest execution can continue.
12179 * @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
12180 * @retval VERR_EM_INTERPRETER when something unexpected happened, fallback to
12181 * interpreter.
12182 */
12183HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12184{
12185 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12186 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
12187
12188 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12189 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12190 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12191 AssertRCReturn(rc, rc);
12192
12193 VBOXSTRICTRC rcStrict;
12194 PVM pVM = pVCpu->CTX_SUFF(pVM);
12195 RTGCUINTPTR const uExitQual = pVmxTransient->uExitQual;
12196 uint32_t const uAccessType = VMX_EXIT_QUAL_CRX_ACCESS(uExitQual);
12197 switch (uAccessType)
12198 {
12199 case VMX_EXIT_QUAL_CRX_ACCESS_WRITE: /* MOV to CRx */
12200 {
12201 uint32_t const uOldCr0 = pVCpu->cpum.GstCtx.cr0;
12202 rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_REGISTER(uExitQual),
12203 VMX_EXIT_QUAL_CRX_GENREG(uExitQual));
12204 AssertMsg( rcStrict == VINF_SUCCESS
12205 || rcStrict == VINF_IEM_RAISED_XCPT
12206 || rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12207
12208 switch (VMX_EXIT_QUAL_CRX_REGISTER(uExitQual))
12209 {
12210 case 0:
12211 {
12212 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12213 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12214 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
12215 Log4Func(("CR0 write rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr0));
12216
12217 /*
12218 * This is a kludge for handling switches back to real mode when we try to use
12219 * V86 mode to run real mode code directly. Problem is that V86 mode cannot
12220 * deal with special selector values, so we have to return to ring-3 and run
12221 * there till the selector values are V86 mode compatible.
12222 *
12223 * Note! Using VINF_EM_RESCHEDULE_REM here rather than VINF_EM_RESCHEDULE since the
12224 * latter is an alias for VINF_IEM_RAISED_XCPT which is converted to VINF_SUCCESs
12225 * at the end of this function.
12226 */
12227 if ( rc == VINF_SUCCESS
12228 && !pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest
12229 && CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx)
12230 && (uOldCr0 & X86_CR0_PE)
12231 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
12232 {
12233 /** @todo check selectors rather than returning all the time. */
12234 Log4Func(("CR0 write, back to real mode -> VINF_EM_RESCHEDULE_REM\n"));
12235 rcStrict = VINF_EM_RESCHEDULE_REM;
12236 }
12237 break;
12238 }
12239
12240 case 2:
12241 {
12242 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
12243 /* Nothing to do here, CR2 it's not part of the VMCS. */
12244 break;
12245 }
12246
12247 case 3:
12248 {
12249 Assert( !pVM->hm.s.fNestedPaging
12250 || !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
12251 || pVCpu->hm.s.fUsingDebugLoop);
12252 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
12253 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12254 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR3);
12255 Log4Func(("CR3 write rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr3));
12256 break;
12257 }
12258
12259 case 4:
12260 {
12261 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
12262 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12263 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR4);
12264 Log4Func(("CR4 write rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n", VBOXSTRICTRC_VAL(rcStrict),
12265 pVCpu->cpum.GstCtx.cr4, pVCpu->hm.s.fLoadSaveGuestXcr0));
12266 break;
12267 }
12268
12269 case 8:
12270 {
12271 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
12272 Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
12273 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12274 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_APIC_TPR);
12275 break;
12276 }
12277 default:
12278 AssertMsgFailed(("Invalid CRx register %#x\n", VMX_EXIT_QUAL_CRX_REGISTER(uExitQual)));
12279 break;
12280 }
12281 break;
12282 }
12283
12284 case VMX_EXIT_QUAL_CRX_ACCESS_READ: /* MOV from CRx */
12285 {
12286 Assert( !pVM->hm.s.fNestedPaging
12287 || !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
12288 || pVCpu->hm.s.fUsingDebugLoop
12289 || VMX_EXIT_QUAL_CRX_REGISTER(uExitQual) != 3);
12290 /* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
12291 Assert( VMX_EXIT_QUAL_CRX_REGISTER(uExitQual) != 8
12292 || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
12293
12294 rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_GENREG(uExitQual),
12295 VMX_EXIT_QUAL_CRX_REGISTER(uExitQual));
12296 AssertMsg( rcStrict == VINF_SUCCESS
12297 || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12298#ifdef VBOX_WITH_STATISTICS
12299 switch (VMX_EXIT_QUAL_CRX_REGISTER(uExitQual))
12300 {
12301 case 0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
12302 case 2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
12303 case 3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
12304 case 4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
12305 case 8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
12306 }
12307#endif
12308 Log4Func(("CR%d Read access rcStrict=%Rrc\n", VMX_EXIT_QUAL_CRX_REGISTER(uExitQual),
12309 VBOXSTRICTRC_VAL(rcStrict)));
12310 if (VMX_EXIT_QUAL_CRX_GENREG(uExitQual) == X86_GREG_xSP)
12311 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_RSP);
12312 else
12313 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
12314 break;
12315 }
12316
12317 case VMX_EXIT_QUAL_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */
12318 {
12319 rcStrict = IEMExecDecodedClts(pVCpu, pVmxTransient->cbInstr);
12320 AssertMsg( rcStrict == VINF_SUCCESS
12321 || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12322
12323 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12324 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
12325 Log4Func(("CLTS rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12326 break;
12327 }
12328
12329 case VMX_EXIT_QUAL_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
12330 {
12331 /* Note! LMSW cannot clear CR0.PE, so no fRealOnV86Active kludge needed here. */
12332 rcStrict = IEMExecDecodedLmsw(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_LMSW_DATA(uExitQual));
12333 AssertMsg( rcStrict == VINF_SUCCESS
12334 || rcStrict == VINF_IEM_RAISED_XCPT
12335 , ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12336
12337 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12338 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
12339 Log4Func(("LMSW rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12340 break;
12341 }
12342
12343 default:
12344 AssertMsgFailedReturn(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType),
12345 VERR_VMX_UNEXPECTED_EXCEPTION);
12346 }
12347
12348 Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS))
12349 == (HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS));
12350 if (rcStrict == VINF_IEM_RAISED_XCPT)
12351 {
12352 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
12353 rcStrict = VINF_SUCCESS;
12354 }
12355
12356 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
12357 NOREF(pVM);
12358 return rcStrict;
12359}
12360
12361
12362/**
12363 * VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
12364 * VM-exit.
12365 */
12366HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12367{
12368 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12369 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
12370
12371 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12372 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12373 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12374 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_EFER);
12375 /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
12376 AssertRCReturn(rc, rc);
12377
12378 /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
12379 uint32_t uIOPort = VMX_EXIT_QUAL_IO_PORT(pVmxTransient->uExitQual);
12380 uint8_t uIOWidth = VMX_EXIT_QUAL_IO_WIDTH(pVmxTransient->uExitQual);
12381 bool fIOWrite = (VMX_EXIT_QUAL_IO_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_IO_DIRECTION_OUT);
12382 bool fIOString = VMX_EXIT_QUAL_IO_IS_STRING(pVmxTransient->uExitQual);
12383 bool fGstStepping = RT_BOOL(pCtx->eflags.Bits.u1TF);
12384 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
12385 AssertReturn(uIOWidth <= 3 && uIOWidth != 2, VERR_VMX_IPE_1);
12386
12387 /*
12388 * Update exit history to see if this exit can be optimized.
12389 */
12390 VBOXSTRICTRC rcStrict;
12391 PCEMEXITREC pExitRec = NULL;
12392 if ( !fGstStepping
12393 && !fDbgStepping)
12394 pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
12395 !fIOString
12396 ? !fIOWrite
12397 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
12398 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
12399 : !fIOWrite
12400 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
12401 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
12402 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
12403 if (!pExitRec)
12404 {
12405 /* I/O operation lookup arrays. */
12406 static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses. */
12407 static uint32_t const s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving result in AL/AX/EAX. */
12408 uint32_t const cbValue = s_aIOSizes[uIOWidth];
12409 uint32_t const cbInstr = pVmxTransient->cbInstr;
12410 bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
12411 PVM pVM = pVCpu->CTX_SUFF(pVM);
12412 if (fIOString)
12413 {
12414 /*
12415 * INS/OUTS - I/O String instruction.
12416 *
12417 * Use instruction-information if available, otherwise fall back on
12418 * interpreting the instruction.
12419 */
12420 Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12421 AssertReturn(pCtx->dx == uIOPort, VERR_VMX_IPE_2);
12422 bool const fInsOutsInfo = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
12423 if (fInsOutsInfo)
12424 {
12425 int rc2 = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12426 AssertRCReturn(rc2, rc2);
12427 AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3);
12428 AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
12429 IEMMODE const enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
12430 bool const fRep = VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual);
12431 if (fIOWrite)
12432 rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
12433 pVmxTransient->ExitInstrInfo.StrIo.iSegReg, true /*fIoChecked*/);
12434 else
12435 {
12436 /*
12437 * The segment prefix for INS cannot be overridden and is always ES. We can safely assume X86_SREG_ES.
12438 * Hence "iSegReg" field is undefined in the instruction-information field in VT-x for INS.
12439 * See Intel Instruction spec. for "INS".
12440 * See Intel spec. Table 27-8 "Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS".
12441 */
12442 rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr, true /*fIoChecked*/);
12443 }
12444 }
12445 else
12446 rcStrict = IEMExecOne(pVCpu);
12447
12448 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
12449 fUpdateRipAlready = true;
12450 }
12451 else
12452 {
12453 /*
12454 * IN/OUT - I/O instruction.
12455 */
12456 Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12457 uint32_t const uAndVal = s_aIOOpAnd[uIOWidth];
12458 Assert(!VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual));
12459 if (fIOWrite)
12460 {
12461 rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pCtx->eax & uAndVal, cbValue);
12462 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
12463 if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
12464 && !pCtx->eflags.Bits.u1TF)
12465 rcStrict = EMRZSetPendingIoPortWrite(pVCpu, uIOPort, cbInstr, cbValue, pCtx->eax & uAndVal);
12466 }
12467 else
12468 {
12469 uint32_t u32Result = 0;
12470 rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
12471 if (IOM_SUCCESS(rcStrict))
12472 {
12473 /* Save result of I/O IN instr. in AL/AX/EAX. */
12474 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Result & uAndVal);
12475 }
12476 if ( rcStrict == VINF_IOM_R3_IOPORT_READ
12477 && !pCtx->eflags.Bits.u1TF)
12478 rcStrict = EMRZSetPendingIoPortRead(pVCpu, uIOPort, cbInstr, cbValue);
12479 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
12480 }
12481 }
12482
12483 if (IOM_SUCCESS(rcStrict))
12484 {
12485 if (!fUpdateRipAlready)
12486 {
12487 hmR0VmxAdvanceGuestRipBy(pVCpu, cbInstr);
12488 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
12489 }
12490
12491 /*
12492 * INS/OUTS with REP prefix updates RFLAGS, can be observed with triple-fault guru
12493 * while booting Fedora 17 64-bit guest.
12494 *
12495 * See Intel Instruction reference for REP/REPE/REPZ/REPNE/REPNZ.
12496 */
12497 if (fIOString)
12498 {
12499 /** @todo Single-step for INS/OUTS with REP prefix? */
12500 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RFLAGS);
12501 }
12502 else if ( !fDbgStepping
12503 && fGstStepping)
12504 {
12505 rc = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
12506 AssertRCReturn(rc, rc);
12507 }
12508
12509 /*
12510 * If any I/O breakpoints are armed, we need to check if one triggered
12511 * and take appropriate action.
12512 * Note that the I/O breakpoint type is undefined if CR4.DE is 0.
12513 */
12514 rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_DR7);
12515 AssertRCReturn(rc, rc);
12516
12517 /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
12518 * execution engines about whether hyper BPs and such are pending. */
12519 uint32_t const uDr7 = pCtx->dr[7];
12520 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
12521 && X86_DR7_ANY_RW_IO(uDr7)
12522 && (pCtx->cr4 & X86_CR4_DE))
12523 || DBGFBpIsHwIoArmed(pVM)))
12524 {
12525 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
12526
12527 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
12528 VMMRZCallRing3Disable(pVCpu);
12529 HM_DISABLE_PREEMPT(pVCpu);
12530
12531 bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
12532
12533 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, uIOPort, cbValue);
12534 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
12535 {
12536 /* Raise #DB. */
12537 if (fIsGuestDbgActive)
12538 ASMSetDR6(pCtx->dr[6]);
12539 if (pCtx->dr[7] != uDr7)
12540 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_GUEST_DR7;
12541
12542 hmR0VmxSetPendingXcptDB(pVCpu);
12543 }
12544 /* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
12545 however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
12546 else if ( rcStrict2 != VINF_SUCCESS
12547 && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
12548 rcStrict = rcStrict2;
12549 AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
12550
12551 HM_RESTORE_PREEMPT();
12552 VMMRZCallRing3Enable(pVCpu);
12553 }
12554 }
12555
12556#ifdef VBOX_STRICT
12557 if ( rcStrict == VINF_IOM_R3_IOPORT_READ
12558 || rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
12559 Assert(!fIOWrite);
12560 else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
12561 || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
12562 || rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
12563 Assert(fIOWrite);
12564 else
12565 {
12566# if 0 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
12567 * statuses, that the VMM device and some others may return. See
12568 * IOM_SUCCESS() for guidance. */
12569 AssertMsg( RT_FAILURE(rcStrict)
12570 || rcStrict == VINF_SUCCESS
12571 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
12572 || rcStrict == VINF_EM_DBG_BREAKPOINT
12573 || rcStrict == VINF_EM_RAW_GUEST_TRAP
12574 || rcStrict == VINF_EM_RAW_TO_R3
12575 || rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12576# endif
12577 }
12578#endif
12579 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
12580 }
12581 else
12582 {
12583 /*
12584 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
12585 */
12586 int rc2 = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
12587 AssertRCReturn(rc2, rc2);
12588 STAM_COUNTER_INC(!fIOString ? fIOWrite ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
12589 : fIOWrite ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
12590 Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
12591 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12592 VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual) ? "REP " : "",
12593 fIOWrite ? "OUT" : "IN", fIOString ? "S" : "", uIOPort, uIOWidth));
12594
12595 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
12596 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
12597
12598 Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
12599 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12600 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
12601 }
12602 return rcStrict;
12603}
12604
12605
12606/**
12607 * VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
12608 * VM-exit.
12609 */
12610HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12611{
12612 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12613
12614 /* Check if this task-switch occurred while delivery an event through the guest IDT. */
12615 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12616 AssertRCReturn(rc, rc);
12617 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
12618 {
12619 rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
12620 AssertRCReturn(rc, rc);
12621 if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
12622 {
12623 uint32_t uErrCode;
12624 RTGCUINTPTR GCPtrFaultAddress;
12625 uint32_t const uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
12626 uint32_t const uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
12627 bool const fErrorCodeValid = VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo);
12628 if (fErrorCodeValid)
12629 {
12630 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
12631 AssertRCReturn(rc, rc);
12632 uErrCode = pVmxTransient->uIdtVectoringErrorCode;
12633 }
12634 else
12635 uErrCode = 0;
12636
12637 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
12638 && uVector == X86_XCPT_PF)
12639 GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
12640 else
12641 GCPtrFaultAddress = 0;
12642
12643 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
12644 0 /* cbInstr */, uErrCode, GCPtrFaultAddress);
12645
12646 Log4Func(("Pending event. uIntType=%#x uVector=%#x\n", uIntType, uVector));
12647 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12648 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12649 }
12650 }
12651
12652 /* Fall back to the interpreter to emulate the task-switch. */
12653 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12654 return VERR_EM_INTERPRETER;
12655}
12656
12657
12658/**
12659 * VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
12660 */
12661HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12662{
12663 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12664 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
12665 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
12666 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12667 AssertRCReturn(rc, rc);
12668 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
12669 return VINF_EM_DBG_STEPPED;
12670}
12671
12672
12673/**
12674 * VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
12675 */
12676HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12677{
12678 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12679
12680 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
12681
12682 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12683 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12684 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12685 {
12686 /* For some crazy guest, if an event delivery causes an APIC-access VM-exit, go to instruction emulation. */
12687 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12688 {
12689 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12690 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12691 }
12692 }
12693 else
12694 {
12695 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12696 rcStrict1 = VINF_SUCCESS;
12697 return rcStrict1;
12698 }
12699
12700 /* IOMMIOPhysHandler() below may call into IEM, save the necessary state. */
12701 int rc = hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12702 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12703 AssertRCReturn(rc, rc);
12704
12705 /* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
12706 uint32_t uAccessType = VMX_EXIT_QUAL_APIC_ACCESS_TYPE(pVmxTransient->uExitQual);
12707 VBOXSTRICTRC rcStrict2;
12708 switch (uAccessType)
12709 {
12710 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
12711 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
12712 {
12713 AssertMsg( !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
12714 || VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual) != XAPIC_OFF_TPR,
12715 ("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
12716
12717 RTGCPHYS GCPhys = pVCpu->hm.s.vmx.u64MsrApicBase; /* Always up-to-date, u64MsrApicBase is not part of the VMCS. */
12718 GCPhys &= PAGE_BASE_GC_MASK;
12719 GCPhys += VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual);
12720 PVM pVM = pVCpu->CTX_SUFF(pVM);
12721 Log4Func(("Linear access uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys,
12722 VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual)));
12723
12724 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12725 rcStrict2 = IOMMMIOPhysHandler(pVM, pVCpu,
12726 uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ ? 0 : X86_TRAP_PF_RW,
12727 CPUMCTX2CORE(pCtx), GCPhys);
12728 Log4Func(("IOMMMIOPhysHandler returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
12729 if ( rcStrict2 == VINF_SUCCESS
12730 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12731 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12732 {
12733 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
12734 | HM_CHANGED_GUEST_APIC_TPR);
12735 rcStrict2 = VINF_SUCCESS;
12736 }
12737 break;
12738 }
12739
12740 default:
12741 Log4Func(("uAccessType=%#x\n", uAccessType));
12742 rcStrict2 = VINF_EM_RAW_EMULATE_INSTR;
12743 break;
12744 }
12745
12746 if (rcStrict2 != VINF_SUCCESS)
12747 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchApicAccessToR3);
12748 return rcStrict2;
12749}
12750
12751
12752/**
12753 * VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
12754 * VM-exit.
12755 */
12756HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12757{
12758 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12759
12760 /* We should -not- get this VM-exit if the guest's debug registers were active. */
12761 if (pVmxTransient->fWasGuestDebugStateActive)
12762 {
12763 AssertMsgFailed(("Unexpected MOV DRx exit\n"));
12764 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12765 }
12766
12767 if ( !pVCpu->hm.s.fSingleInstruction
12768 && !pVmxTransient->fWasHyperDebugStateActive)
12769 {
12770 Assert(!DBGFIsStepping(pVCpu));
12771 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
12772
12773 /* Don't intercept MOV DRx any more. */
12774 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
12775 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12776 AssertRCReturn(rc, rc);
12777
12778 /* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
12779 VMMRZCallRing3Disable(pVCpu);
12780 HM_DISABLE_PREEMPT(pVCpu);
12781
12782 /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
12783 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
12784 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
12785
12786 HM_RESTORE_PREEMPT();
12787 VMMRZCallRing3Enable(pVCpu);
12788
12789#ifdef VBOX_WITH_STATISTICS
12790 rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12791 AssertRCReturn(rc, rc);
12792 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
12793 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12794 else
12795 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12796#endif
12797 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
12798 return VINF_SUCCESS;
12799 }
12800
12801 /*
12802 * EMInterpretDRx[Write|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER, CS. EFER is always up-to-date.
12803 * Update the segment registers and DR7 from the CPU.
12804 */
12805 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12806 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12807 rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_DR7);
12808 AssertRCReturn(rc, rc);
12809 Log4Func(("CS:RIP=%04x:%08RX64\n", pCtx->cs.Sel, pCtx->rip));
12810
12811 PVM pVM = pVCpu->CTX_SUFF(pVM);
12812 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
12813 {
12814 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
12815 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual),
12816 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual));
12817 if (RT_SUCCESS(rc))
12818 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
12819 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12820 }
12821 else
12822 {
12823 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
12824 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual),
12825 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual));
12826 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12827 }
12828
12829 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
12830 if (RT_SUCCESS(rc))
12831 {
12832 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
12833 AssertRCReturn(rc2, rc2);
12834 return VINF_SUCCESS;
12835 }
12836 return rc;
12837}
12838
12839
12840/**
12841 * VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
12842 * Conditional VM-exit.
12843 */
12844HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12845{
12846 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12847 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12848
12849 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12850 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12851 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12852 {
12853 /* If event delivery causes an EPT misconfig (MMIO), go back to instruction emulation as otherwise
12854 injecting the original pending event would most likely cause the same EPT misconfig VM-exit. */
12855 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12856 {
12857 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12858 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12859 }
12860 }
12861 else
12862 {
12863 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12864 rcStrict1 = VINF_SUCCESS;
12865 return rcStrict1;
12866 }
12867
12868 /*
12869 * Get sufficent state and update the exit history entry.
12870 */
12871 RTGCPHYS GCPhys;
12872 int rc = VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &GCPhys);
12873 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12874 AssertRCReturn(rc, rc);
12875
12876 VBOXSTRICTRC rcStrict;
12877 PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
12878 EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_MMIO),
12879 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
12880 if (!pExitRec)
12881 {
12882 /*
12883 * If we succeed, resume guest execution.
12884 * If we fail in interpreting the instruction because we couldn't get the guest physical address
12885 * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
12886 * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
12887 * weird case. See @bugref{6043}.
12888 */
12889 PVM pVM = pVCpu->CTX_SUFF(pVM);
12890 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12891 rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);
12892 Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pCtx->rip, VBOXSTRICTRC_VAL(rcStrict)));
12893 if ( rcStrict == VINF_SUCCESS
12894 || rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
12895 || rcStrict == VERR_PAGE_NOT_PRESENT)
12896 {
12897 /* Successfully handled MMIO operation. */
12898 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
12899 | HM_CHANGED_GUEST_APIC_TPR);
12900 rcStrict = VINF_SUCCESS;
12901 }
12902 }
12903 else
12904 {
12905 /*
12906 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
12907 */
12908 int rc2 = hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12909 AssertRCReturn(rc2, rc2);
12910
12911 Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
12912 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhys));
12913
12914 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
12915 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
12916
12917 Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
12918 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12919 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
12920 }
12921 return VBOXSTRICTRC_TODO(rcStrict);
12922}
12923
12924
12925/**
12926 * VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
12927 * VM-exit.
12928 */
12929HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12930{
12931 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12932 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12933
12934 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12935 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12936 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12937 {
12938 /* In the unlikely case that the EPT violation happened as a result of delivering an event, log it. */
12939 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12940 Log4Func(("EPT violation with an event pending u64IntInfo=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo));
12941 }
12942 else
12943 {
12944 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12945 rcStrict1 = VINF_SUCCESS;
12946 return rcStrict1;
12947 }
12948
12949 RTGCPHYS GCPhys;
12950 int rc = VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &GCPhys);
12951 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12952 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12953 AssertRCReturn(rc, rc);
12954
12955 /* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
12956 AssertMsg(((pVmxTransient->uExitQual >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQual));
12957
12958 RTGCUINT uErrorCode = 0;
12959 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_INSTR_FETCH)
12960 uErrorCode |= X86_TRAP_PF_ID;
12961 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_DATA_WRITE)
12962 uErrorCode |= X86_TRAP_PF_RW;
12963 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_ENTRY_PRESENT)
12964 uErrorCode |= X86_TRAP_PF_P;
12965
12966 TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
12967
12968
12969 /* Handle the pagefault trap for the nested shadow table. */
12970 PVM pVM = pVCpu->CTX_SUFF(pVM);
12971 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12972
12973 Log4Func(("EPT violation %#x at %#RX64 ErrorCode %#x CS:RIP=%04x:%08RX64\n", pVmxTransient->uExitQual, GCPhys, uErrorCode,
12974 pCtx->cs.Sel, pCtx->rip));
12975
12976 VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pCtx), GCPhys);
12977 TRPMResetTrap(pVCpu);
12978
12979 /* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
12980 if ( rcStrict2 == VINF_SUCCESS
12981 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12982 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12983 {
12984 /* Successfully synced our nested page tables. */
12985 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
12986 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS);
12987 return VINF_SUCCESS;
12988 }
12989
12990 Log4Func(("EPT return to ring-3 rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
12991 return rcStrict2;
12992}
12993
12994/** @} */
12995
12996/** @name VM-exit exception handlers.
12997 * @{
12998 */
12999/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13000/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= VM-exit exception handlers =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
13001/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13002
13003/**
13004 * VM-exit exception handler for \#MF (Math Fault: floating point exception).
13005 */
13006static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13007{
13008 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13009 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
13010
13011 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0);
13012 AssertRCReturn(rc, rc);
13013
13014 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE))
13015 {
13016 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
13017 rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
13018
13019 /** @todo r=ramshankar: The Intel spec. does -not- specify that this VM-exit
13020 * provides VM-exit instruction length. If this causes problem later,
13021 * disassemble the instruction like it's done on AMD-V. */
13022 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
13023 AssertRCReturn(rc2, rc2);
13024 return rc;
13025 }
13026
13027 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13028 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13029 return rc;
13030}
13031
13032
13033/**
13034 * VM-exit exception handler for \#BP (Breakpoint exception).
13035 */
13036static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13037{
13038 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13039 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
13040
13041 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13042 AssertRCReturn(rc, rc);
13043
13044 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13045 rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
13046 if (rc == VINF_EM_RAW_GUEST_TRAP)
13047 {
13048 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13049 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13050 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13051 AssertRCReturn(rc, rc);
13052
13053 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13054 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13055 }
13056
13057 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_EM_DBG_BREAKPOINT);
13058 return rc;
13059}
13060
13061
13062/**
13063 * VM-exit exception handler for \#AC (alignment check exception).
13064 */
13065static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13066{
13067 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13068
13069 /*
13070 * Re-inject it. We'll detect any nesting before getting here.
13071 */
13072 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13073 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13074 AssertRCReturn(rc, rc);
13075 Assert(ASMAtomicUoReadU32(&pVmxTransient->fVmcsFieldsRead) & HMVMX_READ_EXIT_INTERRUPTION_INFO);
13076
13077 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13078 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13079 return VINF_SUCCESS;
13080}
13081
13082
13083/**
13084 * VM-exit exception handler for \#DB (Debug exception).
13085 */
13086static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13087{
13088 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13089 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
13090
13091 /*
13092 * Get the DR6-like values from the VM-exit qualification and pass it to DBGF
13093 * for processing.
13094 */
13095 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13096
13097 /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
13098 uint64_t uDR6 = X86_DR6_INIT_VAL;
13099 uDR6 |= (pVmxTransient->uExitQual & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3 | X86_DR6_BD | X86_DR6_BS));
13100
13101 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13102 rc = DBGFRZTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
13103 Log6Func(("rc=%Rrc\n", rc));
13104 if (rc == VINF_EM_RAW_GUEST_TRAP)
13105 {
13106 /*
13107 * The exception was for the guest. Update DR6, DR7.GD and
13108 * IA32_DEBUGCTL.LBR before forwarding it.
13109 * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
13110 */
13111 VMMRZCallRing3Disable(pVCpu);
13112 HM_DISABLE_PREEMPT(pVCpu);
13113
13114 pCtx->dr[6] &= ~X86_DR6_B_MASK;
13115 pCtx->dr[6] |= uDR6;
13116 if (CPUMIsGuestDebugStateActive(pVCpu))
13117 ASMSetDR6(pCtx->dr[6]);
13118
13119 HM_RESTORE_PREEMPT();
13120 VMMRZCallRing3Enable(pVCpu);
13121
13122 rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_DR7);
13123 AssertRCReturn(rc, rc);
13124
13125 /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
13126 pCtx->dr[7] &= ~X86_DR7_GD;
13127
13128 /* Paranoia. */
13129 pCtx->dr[7] &= ~X86_DR7_RAZ_MASK;
13130 pCtx->dr[7] |= X86_DR7_RA1_MASK;
13131
13132 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pCtx->dr[7]);
13133 AssertRCReturn(rc, rc);
13134
13135 /*
13136 * Raise #DB in the guest.
13137 *
13138 * It is important to reflect exactly what the VM-exit gave us (preserving the
13139 * interruption-type) rather than use hmR0VmxSetPendingXcptDB() as the #DB could've
13140 * been raised while executing ICEBP (INT1) and not the regular #DB. Thus it may
13141 * trigger different handling in the CPU (like skipping DPL checks), see @bugref{6398}.
13142 *
13143 * Intel re-documented ICEBP/INT1 on May 2018 previously documented as part of
13144 * Intel 386, see Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
13145 */
13146 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13147 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13148 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13149 AssertRCReturn(rc, rc);
13150 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13151 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13152 return VINF_SUCCESS;
13153 }
13154
13155 /*
13156 * Not a guest trap, must be a hypervisor related debug event then.
13157 * Update DR6 in case someone is interested in it.
13158 */
13159 AssertMsg(rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
13160 AssertReturn(pVmxTransient->fWasHyperDebugStateActive, VERR_HM_IPE_5);
13161 CPUMSetHyperDR6(pVCpu, uDR6);
13162
13163 return rc;
13164}
13165
13166/**
13167 * VM-exit exception handler for \#GP (General-protection exception).
13168 *
13169 * @remarks Requires pVmxTransient->uExitIntInfo to be up-to-date.
13170 */
13171static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13172{
13173 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13174 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
13175
13176 int rc;
13177 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13178 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
13179 { /* likely */ }
13180 else
13181 {
13182#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13183 Assert(pVCpu->hm.s.fUsingDebugLoop);
13184#endif
13185 /* If the guest is not in real-mode or we have unrestricted execution support, reflect #GP to the guest. */
13186 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13187 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13188 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13189 rc |= hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13190 AssertRCReturn(rc, rc);
13191 Log4Func(("Gst: CS:RIP %04x:%08RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u TR=%#04x\n", pCtx->cs.Sel, pCtx->rip,
13192 pVmxTransient->uExitIntErrorCode, pCtx->cr0, CPUMGetGuestCPL(pVCpu), pCtx->tr.Sel));
13193 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13194 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13195 return rc;
13196 }
13197
13198 Assert(CPUMIsGuestInRealModeEx(pCtx));
13199 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest);
13200
13201 /* EMInterpretDisasCurrent() requires a lot of the state, save the entire state. */
13202 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13203 AssertRCReturn(rc, rc);
13204
13205 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
13206 uint32_t cbOp = 0;
13207 PVM pVM = pVCpu->CTX_SUFF(pVM);
13208 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
13209 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
13210 if (RT_SUCCESS(rc))
13211 {
13212 rc = VINF_SUCCESS;
13213 Assert(cbOp == pDis->cbInstr);
13214 Log4Func(("Disas OpCode=%u CS:EIP %04x:%04RX64\n", pDis->pCurInstr->uOpcode, pCtx->cs.Sel, pCtx->rip));
13215 switch (pDis->pCurInstr->uOpcode)
13216 {
13217 case OP_CLI:
13218 {
13219 pCtx->eflags.Bits.u1IF = 0;
13220 pCtx->eflags.Bits.u1RF = 0;
13221 pCtx->rip += pDis->cbInstr;
13222 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13223 if ( !fDbgStepping
13224 && pCtx->eflags.Bits.u1TF)
13225 {
13226 rc = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13227 AssertRCReturn(rc, rc);
13228 }
13229 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
13230 break;
13231 }
13232
13233 case OP_STI:
13234 {
13235 bool fOldIF = pCtx->eflags.Bits.u1IF;
13236 pCtx->eflags.Bits.u1IF = 1;
13237 pCtx->eflags.Bits.u1RF = 0;
13238 pCtx->rip += pDis->cbInstr;
13239 if (!fOldIF)
13240 {
13241 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
13242 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
13243 }
13244 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13245 if ( !fDbgStepping
13246 && pCtx->eflags.Bits.u1TF)
13247 {
13248 rc = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13249 AssertRCReturn(rc, rc);
13250 }
13251 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
13252 break;
13253 }
13254
13255 case OP_HLT:
13256 {
13257 rc = VINF_EM_HALT;
13258 pCtx->rip += pDis->cbInstr;
13259 pCtx->eflags.Bits.u1RF = 0;
13260 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
13261 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
13262 break;
13263 }
13264
13265 case OP_POPF:
13266 {
13267 Log4Func(("POPF CS:EIP %04x:%04RX64\n", pCtx->cs.Sel, pCtx->rip));
13268 uint32_t cbParm;
13269 uint32_t uMask;
13270 bool fGstStepping = RT_BOOL(pCtx->eflags.Bits.u1TF);
13271 if (pDis->fPrefix & DISPREFIX_OPSIZE)
13272 {
13273 cbParm = 4;
13274 uMask = 0xffffffff;
13275 }
13276 else
13277 {
13278 cbParm = 2;
13279 uMask = 0xffff;
13280 }
13281
13282 /* Get the stack pointer & pop the contents of the stack onto Eflags. */
13283 RTGCPTR GCPtrStack = 0;
13284 X86EFLAGS Eflags;
13285 Eflags.u32 = 0;
13286 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13287 &GCPtrStack);
13288 if (RT_SUCCESS(rc))
13289 {
13290 Assert(sizeof(Eflags.u32) >= cbParm);
13291 rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u32, cbParm, PGMACCESSORIGIN_HM));
13292 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13293 }
13294 if (RT_FAILURE(rc))
13295 {
13296 rc = VERR_EM_INTERPRETER;
13297 break;
13298 }
13299 Log4Func(("POPF %#x -> %#RX64 mask=%#x RIP=%#RX64\n", Eflags.u, pCtx->rsp, uMask, pCtx->rip));
13300 pCtx->eflags.u32 = (pCtx->eflags.u32 & ~((X86_EFL_POPF_BITS & uMask) | X86_EFL_RF))
13301 | (Eflags.u32 & X86_EFL_POPF_BITS & uMask);
13302 pCtx->esp += cbParm;
13303 pCtx->esp &= uMask;
13304 pCtx->rip += pDis->cbInstr;
13305 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS);
13306 /* Generate a pending-debug exception when the guest stepping over POPF regardless of how
13307 POPF restores EFLAGS.TF. */
13308 if ( !fDbgStepping
13309 && fGstStepping)
13310 {
13311 rc = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13312 AssertRCReturn(rc, rc);
13313 }
13314 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPopf);
13315 break;
13316 }
13317
13318 case OP_PUSHF:
13319 {
13320 uint32_t cbParm;
13321 uint32_t uMask;
13322 if (pDis->fPrefix & DISPREFIX_OPSIZE)
13323 {
13324 cbParm = 4;
13325 uMask = 0xffffffff;
13326 }
13327 else
13328 {
13329 cbParm = 2;
13330 uMask = 0xffff;
13331 }
13332
13333 /* Get the stack pointer & push the contents of eflags onto the stack. */
13334 RTGCPTR GCPtrStack = 0;
13335 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask,
13336 SELMTOFLAT_FLAGS_CPL0, &GCPtrStack);
13337 if (RT_FAILURE(rc))
13338 {
13339 rc = VERR_EM_INTERPRETER;
13340 break;
13341 }
13342 X86EFLAGS Eflags = pCtx->eflags;
13343 /* The RF & VM bits are cleared on image stored on stack; see Intel Instruction reference for PUSHF. */
13344 Eflags.Bits.u1RF = 0;
13345 Eflags.Bits.u1VM = 0;
13346
13347 rc = VBOXSTRICTRC_TODO(PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u, cbParm, PGMACCESSORIGIN_HM));
13348 if (RT_UNLIKELY(rc != VINF_SUCCESS))
13349 {
13350 AssertMsgFailed(("%Rrc\n", rc)); /** @todo allow strict return codes here */
13351 rc = VERR_EM_INTERPRETER;
13352 break;
13353 }
13354 Log4Func(("PUSHF %#x -> %#RGv\n", Eflags.u, GCPtrStack));
13355 pCtx->esp -= cbParm;
13356 pCtx->esp &= uMask;
13357 pCtx->rip += pDis->cbInstr;
13358 pCtx->eflags.Bits.u1RF = 0;
13359 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS);
13360 if ( !fDbgStepping
13361 && pCtx->eflags.Bits.u1TF)
13362 {
13363 rc = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13364 AssertRCReturn(rc, rc);
13365 }
13366 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPushf);
13367 break;
13368 }
13369
13370 case OP_IRET:
13371 {
13372 /** @todo Handle 32-bit operand sizes and check stack limits. See Intel
13373 * instruction reference. */
13374 RTGCPTR GCPtrStack = 0;
13375 uint32_t uMask = 0xffff;
13376 bool fGstStepping = RT_BOOL(pCtx->eflags.Bits.u1TF);
13377 uint16_t aIretFrame[3];
13378 if (pDis->fPrefix & (DISPREFIX_OPSIZE | DISPREFIX_ADDRSIZE))
13379 {
13380 rc = VERR_EM_INTERPRETER;
13381 break;
13382 }
13383 rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13384 &GCPtrStack);
13385 if (RT_SUCCESS(rc))
13386 {
13387 rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame),
13388 PGMACCESSORIGIN_HM));
13389 AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13390 }
13391 if (RT_FAILURE(rc))
13392 {
13393 rc = VERR_EM_INTERPRETER;
13394 break;
13395 }
13396 pCtx->eip = 0;
13397 pCtx->ip = aIretFrame[0];
13398 pCtx->cs.Sel = aIretFrame[1];
13399 pCtx->cs.ValidSel = aIretFrame[1];
13400 pCtx->cs.u64Base = (uint64_t)pCtx->cs.Sel << 4;
13401 pCtx->eflags.u32 = (pCtx->eflags.u32 & ((UINT32_C(0xffff0000) | X86_EFL_1) & ~X86_EFL_RF))
13402 | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
13403 pCtx->sp += sizeof(aIretFrame);
13404 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
13405 | HM_CHANGED_GUEST_CS);
13406 /* Generate a pending-debug exception when stepping over IRET regardless of how IRET modifies EFLAGS.TF. */
13407 if ( !fDbgStepping
13408 && fGstStepping)
13409 {
13410 rc = hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13411 AssertRCReturn(rc, rc);
13412 }
13413 Log4Func(("IRET %#RX32 to %04x:%04x\n", GCPtrStack, pCtx->cs.Sel, pCtx->ip));
13414 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIret);
13415 break;
13416 }
13417
13418 case OP_INT:
13419 {
13420 uint16_t uVector = pDis->Param1.uValue & 0xff;
13421 hmR0VmxSetPendingIntN(pVCpu, uVector, pDis->cbInstr);
13422 /* INT clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13423 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13424 break;
13425 }
13426
13427 case OP_INTO:
13428 {
13429 if (pCtx->eflags.Bits.u1OF)
13430 {
13431 hmR0VmxSetPendingXcptOF(pVCpu, pDis->cbInstr);
13432 /* INTO clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13433 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13434 }
13435 else
13436 {
13437 pCtx->eflags.Bits.u1RF = 0;
13438 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RFLAGS);
13439 }
13440 break;
13441 }
13442
13443 default:
13444 {
13445 pCtx->eflags.Bits.u1RF = 0; /* This is correct most of the time... */
13446 VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pCtx), 0 /* pvFault */,
13447 EMCODETYPE_SUPERVISOR);
13448 rc = VBOXSTRICTRC_VAL(rc2);
13449 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13450 /** @todo We have to set pending-debug exceptions here when the guest is
13451 * single-stepping depending on the instruction that was interpreted. */
13452
13453 /*
13454 * HACK ALERT! Detect mode change and go to ring-3 to properly exit this
13455 * real mode emulation stuff.
13456 */
13457 if ( rc == VINF_SUCCESS
13458 && (pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
13459 {
13460 Log4Func(("Mode changed -> VINF_EM_RESCHEDULE\n"));
13461 /** @todo Exit fRealOnV86Active here w/o dropping back to ring-3. */
13462 rc = VINF_EM_RESCHEDULE;
13463 }
13464
13465 Log4Func(("#GP rc=%Rrc\n", rc));
13466 break;
13467 }
13468 }
13469 }
13470 else
13471 rc = VERR_EM_INTERPRETER;
13472
13473 AssertMsg( rc == VINF_SUCCESS
13474 || rc == VERR_EM_INTERPRETER
13475 || rc == VINF_EM_HALT
13476 || rc == VINF_EM_RESCHEDULE
13477 , ("#GP Unexpected rc=%Rrc\n", rc));
13478 return rc;
13479}
13480
13481
13482/**
13483 * VM-exit exception handler wrapper for generic exceptions. Simply re-injects
13484 * the exception reported in the VMX transient structure back into the VM.
13485 *
13486 * @remarks Requires uExitIntInfo in the VMX transient structure to be
13487 * up-to-date.
13488 */
13489static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13490{
13491 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13492#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13493 AssertMsg(pVCpu->hm.s.fUsingDebugLoop || pVCpu->hm.s.vmx.RealMode.fRealOnV86Active,
13494 ("uVector=%#x u32XcptBitmap=%#X32\n",
13495 VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo), pVCpu->hm.s.vmx.u32XcptBitmap));
13496#endif
13497
13498 /* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in
13499 hmR0VmxCheckExitDueToEventDelivery(). */
13500 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13501 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13502 AssertRCReturn(rc, rc);
13503 Assert(ASMAtomicUoReadU32(&pVmxTransient->fVmcsFieldsRead) & HMVMX_READ_EXIT_INTERRUPTION_INFO);
13504
13505#ifdef DEBUG_ramshankar
13506 rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
13507 uint8_t uVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
13508 Log(("hmR0VmxExitXcptGeneric: Reinjecting Xcpt. uVector=%#x cs:rip=%#04x:%#RX64\n", uVector, pCtx->cs.Sel, pCtx->rip));
13509#endif
13510
13511 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13512 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13513 return VINF_SUCCESS;
13514}
13515
13516
13517/**
13518 * VM-exit exception handler for \#PF (Page-fault exception).
13519 */
13520static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13521{
13522 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13523 PVM pVM = pVCpu->CTX_SUFF(pVM);
13524 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13525 rc |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13526 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13527 AssertRCReturn(rc, rc);
13528
13529 if (!pVM->hm.s.fNestedPaging)
13530 { /* likely */ }
13531 else
13532 {
13533#if !defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) && !defined(HMVMX_ALWAYS_TRAP_PF)
13534 Assert(pVCpu->hm.s.fUsingDebugLoop);
13535#endif
13536 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
13537 if (RT_LIKELY(!pVmxTransient->fVectoringDoublePF))
13538 {
13539 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
13540 pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual);
13541 }
13542 else
13543 {
13544 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13545 hmR0VmxSetPendingXcptDF(pVCpu);
13546 Log4Func(("Pending #DF due to vectoring #PF w/ NestedPaging\n"));
13547 }
13548 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13549 return rc;
13550 }
13551
13552 /* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
13553 of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
13554 if (pVmxTransient->fVectoringPF)
13555 {
13556 Assert(pVCpu->hm.s.Event.fPending);
13557 return VINF_EM_RAW_INJECT_TRPM_EVENT;
13558 }
13559
13560 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13561 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13562 AssertRCReturn(rc, rc);
13563
13564 Log4Func(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQual, pCtx->cs.Sel,
13565 pCtx->rip, pVmxTransient->uExitIntErrorCode, pCtx->cr3));
13566
13567 TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQual, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
13568 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pCtx), (RTGCPTR)pVmxTransient->uExitQual);
13569
13570 Log4Func(("#PF: rc=%Rrc\n", rc));
13571 if (rc == VINF_SUCCESS)
13572 {
13573 /*
13574 * This is typically a shadow page table sync or a MMIO instruction. But we may have
13575 * emulated something like LTR or a far jump. Any part of the CPU context may have changed.
13576 */
13577 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13578 TRPMResetTrap(pVCpu);
13579 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
13580 return rc;
13581 }
13582
13583 if (rc == VINF_EM_RAW_GUEST_TRAP)
13584 {
13585 if (!pVmxTransient->fVectoringDoublePF)
13586 {
13587 /* It's a guest page fault and needs to be reflected to the guest. */
13588 uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);
13589 TRPMResetTrap(pVCpu);
13590 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
13591 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
13592 uGstErrorCode, pVmxTransient->uExitQual);
13593 }
13594 else
13595 {
13596 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13597 TRPMResetTrap(pVCpu);
13598 pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
13599 hmR0VmxSetPendingXcptDF(pVCpu);
13600 Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
13601 }
13602
13603 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13604 return VINF_SUCCESS;
13605 }
13606
13607 TRPMResetTrap(pVCpu);
13608 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
13609 return rc;
13610}
13611
13612/** @} */
13613
13614#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
13615
13616/** @name Nested-guest VM-exit handlers.
13617 * @{
13618 */
13619/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13620/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Nested-guest VM-exit handlers =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13621/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13622
13623/**
13624 * VM-exit handler for VMCLEAR (VMX_EXIT_VMCLEAR). Unconditional VM-exit.
13625 */
13626HMVMX_EXIT_DECL hmR0VmxExitVmclear(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13627{
13628 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13629
13630 /** @todo NSTVMX: Vmclear. */
13631 hmR0VmxSetPendingXcptUD(pVCpu);
13632 return VINF_SUCCESS;
13633}
13634
13635
13636/**
13637 * VM-exit handler for VMLAUNCH (VMX_EXIT_VMLAUNCH). Unconditional VM-exit.
13638 */
13639HMVMX_EXIT_DECL hmR0VmxExitVmlaunch(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13640{
13641 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13642
13643 /** @todo NSTVMX: Vmlaunch. */
13644 hmR0VmxSetPendingXcptUD(pVCpu);
13645 return VINF_SUCCESS;
13646}
13647
13648
13649/**
13650 * VM-exit handler for VMPTRLD (VMX_EXIT_VMPTRLD). Unconditional VM-exit.
13651 */
13652HMVMX_EXIT_DECL hmR0VmxExitVmptrld(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13653{
13654 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13655
13656 /** @todo NSTVMX: Vmptrld. */
13657 hmR0VmxSetPendingXcptUD(pVCpu);
13658 return VINF_SUCCESS;
13659}
13660
13661
13662/**
13663 * VM-exit handler for VMPTRST (VMX_EXIT_VMPTRST). Unconditional VM-exit.
13664 */
13665HMVMX_EXIT_DECL hmR0VmxExitVmptrst(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13666{
13667 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13668
13669 /** @todo NSTVMX: Vmptrst. */
13670 hmR0VmxSetPendingXcptUD(pVCpu);
13671 return VINF_SUCCESS;
13672}
13673
13674
13675/**
13676 * VM-exit handler for VMREAD (VMX_EXIT_VMREAD). Unconditional VM-exit.
13677 */
13678HMVMX_EXIT_DECL hmR0VmxExitVmread(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13679{
13680 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13681
13682 /** @todo NSTVMX: Vmread. */
13683 hmR0VmxSetPendingXcptUD(pVCpu);
13684 return VINF_SUCCESS;
13685}
13686
13687
13688/**
13689 * VM-exit handler for VMRESUME (VMX_EXIT_VMRESUME). Unconditional VM-exit.
13690 */
13691HMVMX_EXIT_DECL hmR0VmxExitVmresume(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13692{
13693 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13694
13695 /** @todo NSTVMX: Vmresume. */
13696 hmR0VmxSetPendingXcptUD(pVCpu);
13697 return VINF_SUCCESS;
13698}
13699
13700
13701/**
13702 * VM-exit handler for VMWRITE (VMX_EXIT_VMWRITE). Unconditional VM-exit.
13703 */
13704HMVMX_EXIT_DECL hmR0VmxExitVmwrite(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13705{
13706 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13707
13708 /** @todo NSTVMX: Vmwrite. */
13709 hmR0VmxSetPendingXcptUD(pVCpu);
13710 return VINF_SUCCESS;
13711}
13712
13713
13714/**
13715 * VM-exit handler for VMXOFF (VMX_EXIT_VMXOFF). Unconditional VM-exit.
13716 */
13717HMVMX_EXIT_DECL hmR0VmxExitVmxoff(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13718{
13719 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13720
13721 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13722 rc |= hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13723 AssertRCReturn(rc, rc);
13724
13725 VBOXSTRICTRC rcStrict = IEMExecDecodedVmxoff(pVCpu, pVmxTransient->cbInstr);
13726 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13727 {
13728 /* VMXOFF on success changes the internal hwvirt state but not anything that's visible to the guest. */
13729 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
13730 }
13731 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13732 {
13733 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13734 rcStrict = VINF_SUCCESS;
13735 }
13736 return rcStrict;
13737}
13738
13739
13740/**
13741 * VM-exit handler for VMXON (VMX_EXIT_VMXON). Unconditional VM-exit.
13742 */
13743HMVMX_EXIT_DECL hmR0VmxExitVmxon(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13744{
13745 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13746
13747 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13748 rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_SREG_MASK | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13749 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13750 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13751 AssertRCReturn(rc, rc);
13752
13753 VBOXSTRICTRC rcStrict = hmR0VmxCheckExitDueToVmxInstr(pVCpu, pVmxTransient);
13754 if (rcStrict == VINF_SUCCESS)
13755 { /* likely */ }
13756 else if (rcStrict == VINF_HM_PENDING_XCPT)
13757 {
13758 Log4Func(("Privilege checks failed, raising xcpt %#x!\n", VMX_ENTRY_INT_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo)));
13759 return VINF_SUCCESS;
13760 }
13761 else
13762 {
13763 Log4Func(("hmR0VmxCheckExitDueToVmxInstr failed. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13764 return rcStrict;
13765 }
13766
13767 RTGCPTR GCPtrVmxon;
13768 PCVMXEXITINSTRINFO pExitInstrInfo = &pVmxTransient->ExitInstrInfo;
13769 RTGCPTR const GCPtrDisp = pVmxTransient->uExitQual;
13770 rcStrict = hmR0VmxDecodeMemOperand(pVCpu, pExitInstrInfo, GCPtrDisp, false /*fIsWrite*/, &GCPtrVmxon);
13771 if (rcStrict == VINF_SUCCESS)
13772 { /* likely */ }
13773 else if (rcStrict == VINF_HM_PENDING_XCPT)
13774 {
13775 Log4Func(("Memory operand decoding failed, raising xcpt %#x\n", VMX_ENTRY_INT_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo)));
13776 return VINF_SUCCESS;
13777 }
13778 else
13779 {
13780 Log4Func(("hmR0VmxCheckExitDueToVmxInstr failed. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13781 return rcStrict;
13782 }
13783
13784 rcStrict = IEMExecDecodedVmxon(pVCpu, pVmxTransient->cbInstr, GCPtrVmxon, pExitInstrInfo->u, GCPtrDisp);
13785 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13786 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13787 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13788 {
13789 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13790 rcStrict = VINF_SUCCESS;
13791 }
13792 return rcStrict;
13793}
13794
13795/** @} */
13796#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
13797
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