VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 77571

Last change on this file since 77571 was 77571, checked in by vboxsync, 6 years ago

VMM/HMVMXR0: Try to not mention function names in comments if it not really critical.
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1/* $Id: HMVMXR0.cpp 77571 2019-03-06 08:55:00Z vboxsync $ */
2/** @file
3 * HM VMX (Intel VT-x) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2012-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <iprt/x86.h>
25#include <iprt/asm-amd64-x86.h>
26#include <iprt/thread.h>
27
28#include <VBox/vmm/pdmapi.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iem.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/selm.h>
33#include <VBox/vmm/tm.h>
34#include <VBox/vmm/em.h>
35#include <VBox/vmm/gim.h>
36#include <VBox/vmm/apic.h>
37#ifdef VBOX_WITH_REM
38# include <VBox/vmm/rem.h>
39#endif
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/hmvmxinline.h>
43#include "HMVMXR0.h"
44#include "dtrace/VBoxVMM.h"
45
46#ifdef DEBUG_ramshankar
47# define HMVMX_ALWAYS_SAVE_GUEST_RFLAGS
48# define HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE
49# define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
50# define HMVMX_ALWAYS_CHECK_GUEST_STATE
51# define HMVMX_ALWAYS_TRAP_ALL_XCPTS
52# define HMVMX_ALWAYS_TRAP_PF
53# define HMVMX_ALWAYS_FLUSH_TLB
54# define HMVMX_ALWAYS_SWAP_EFER
55#endif
56
57
58/*********************************************************************************************************************************
59* Defined Constants And Macros *
60*********************************************************************************************************************************/
61/** Use the function table. */
62#define HMVMX_USE_FUNCTION_TABLE
63
64/** Determine which tagged-TLB flush handler to use. */
65#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
66#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
67#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
68#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
69
70/** @name HMVMX_READ_XXX
71 * Flags to skip redundant reads of some common VMCS fields that are not part of
72 * the guest-CPU or VCPU state but are needed while handling VM-exits.
73 */
74#define HMVMX_READ_IDT_VECTORING_INFO RT_BIT_32(0)
75#define HMVMX_READ_IDT_VECTORING_ERROR_CODE RT_BIT_32(1)
76#define HMVMX_READ_EXIT_QUALIFICATION RT_BIT_32(2)
77#define HMVMX_READ_EXIT_INSTR_LEN RT_BIT_32(3)
78#define HMVMX_READ_EXIT_INTERRUPTION_INFO RT_BIT_32(4)
79#define HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE RT_BIT_32(5)
80#define HMVMX_READ_EXIT_INSTR_INFO RT_BIT_32(6)
81#define HMVMX_READ_GUEST_LINEAR_ADDR RT_BIT_32(7)
82/** @} */
83
84/**
85 * States of the VMCS.
86 *
87 * This does not reflect all possible VMCS states but currently only those
88 * needed for maintaining the VMCS consistently even when thread-context hooks
89 * are used. Maybe later this can be extended (i.e. Nested Virtualization).
90 */
91#define HMVMX_VMCS_STATE_CLEAR RT_BIT(0)
92#define HMVMX_VMCS_STATE_ACTIVE RT_BIT(1)
93#define HMVMX_VMCS_STATE_LAUNCHED RT_BIT(2)
94
95/**
96 * Subset of the guest-CPU state that is kept by VMX R0 code while executing the
97 * guest using hardware-assisted VMX.
98 *
99 * This excludes state like GPRs (other than RSP) which are always are
100 * swapped and restored across the world-switch and also registers like EFER,
101 * MSR which cannot be modified by the guest without causing a VM-exit.
102 */
103#define HMVMX_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
104 | CPUMCTX_EXTRN_RFLAGS \
105 | CPUMCTX_EXTRN_RSP \
106 | CPUMCTX_EXTRN_SREG_MASK \
107 | CPUMCTX_EXTRN_TABLE_MASK \
108 | CPUMCTX_EXTRN_KERNEL_GS_BASE \
109 | CPUMCTX_EXTRN_SYSCALL_MSRS \
110 | CPUMCTX_EXTRN_SYSENTER_MSRS \
111 | CPUMCTX_EXTRN_TSC_AUX \
112 | CPUMCTX_EXTRN_OTHER_MSRS \
113 | CPUMCTX_EXTRN_CR0 \
114 | CPUMCTX_EXTRN_CR3 \
115 | CPUMCTX_EXTRN_CR4 \
116 | CPUMCTX_EXTRN_DR7 \
117 | CPUMCTX_EXTRN_HM_VMX_MASK)
118
119/**
120 * Exception bitmap mask for real-mode guests (real-on-v86).
121 *
122 * We need to intercept all exceptions manually except:
123 * - \#AC and \#DB are always intercepted to prevent the CPU from deadlocking
124 * due to bugs in Intel CPUs.
125 * - \#PF need not be intercepted even in real-mode if we have Nested Paging
126 * support.
127 */
128#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) /* always: | RT_BIT(X86_XCPT_DB) */ | RT_BIT(X86_XCPT_NMI) \
129 | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) \
130 | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_DF) \
131 | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) \
132 | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
133 | RT_BIT(X86_XCPT_MF) /* always: | RT_BIT(X86_XCPT_AC) */ | RT_BIT(X86_XCPT_MC) \
134 | RT_BIT(X86_XCPT_XF))
135
136/** Maximum VM-instruction error number. */
137#define HMVMX_INSTR_ERROR_MAX 28
138
139/** Profiling macro. */
140#ifdef HM_PROFILE_EXIT_DISPATCH
141# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
142# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
143#else
144# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
145# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
146#endif
147
148/** Assert that preemption is disabled or covered by thread-context hooks. */
149#define HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
150 || !RTThreadPreemptIsEnabled(NIL_RTTHREAD))
151
152/** Assert that we haven't migrated CPUs when thread-context hooks are not
153 * used. */
154#define HMVMX_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
155 || (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
156 ("Illegal migration! Entered on CPU %u Current %u\n", \
157 (a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()))
158
159/** Asserts that the given CPUMCTX_EXTRN_XXX bits are present in the guest-CPU
160 * context. */
161#define HMVMX_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
162 ("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
163 (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
164
165/** Macro for importing guest state from the VMCS back into CPUMCTX (intended to be
166 * used only from VM-exit handlers). */
167#define HMVMX_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) (hmR0VmxImportGuestState((a_pVCpu), (a_fWhat)))
168
169/** Helper macro for VM-exit handlers called unexpectedly. */
170#define HMVMX_UNEXPECTED_EXIT_RET(a_pVCpu, a_pVmxTransient) \
171 do { \
172 (a_pVCpu)->hm.s.u32HMError = (a_pVmxTransient)->uExitReason; \
173 return VERR_VMX_UNEXPECTED_EXIT; \
174 } while (0)
175
176/** Macro for importing segment registers to the VMCS from the guest-CPU context. */
177#ifdef VMX_USE_CACHED_VMCS_ACCESSES
178# define HMVMX_IMPORT_SREG(Sel, a_pCtxSelReg) \
179 hmR0VmxImportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
180 VMX_VMCS_GUEST_##Sel##_BASE_CACHE_IDX, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
181#else
182# define HMVMX_IMPORT_SREG(Sel, a_pCtxSelReg) \
183 hmR0VmxImportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
184 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
185#endif
186
187/** Macro for exporting segment registers to the VMCS from the guest-CPU context. */
188#define HMVMX_EXPORT_SREG(Sel, a_pCtxSelReg) \
189 hmR0VmxExportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
190 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
191
192#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
193/** Macro that does the necessary privilege checks and intercepted VM-exits for
194 * guests that attempted to execute a VMX instruction. */
195# define HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(a_pVCpu, a_uExitReason) \
196 do \
197 { \
198 VBOXSTRICTRC rcStrictTmp = hmR0VmxCheckExitDueToVmxInstr((a_pVCpu), (a_uExitReason)); \
199 if (rcStrictTmp == VINF_SUCCESS) \
200 { /* likely */ } \
201 else if (rcStrictTmp == VINF_HM_PENDING_XCPT) \
202 { \
203 Assert((a_pVCpu)->hm.s.Event.fPending); \
204 Log4Func(("Privilege checks failed -> %#x\n", VMX_ENTRY_INT_INFO_VECTOR((a_pVCpu)->hm.s.Event.u64IntInfo))); \
205 return VINF_SUCCESS; \
206 } \
207 else \
208 { \
209 int rcTmp = VBOXSTRICTRC_VAL(rcStrictTmp); \
210 AssertMsgFailedReturn(("Unexpected failure. rc=%Rrc", rcTmp), rcTmp); \
211 } \
212 } while (0)
213
214/** Macro that decodes a memory operand for an instruction VM-exit. */
215# define HMVMX_DECODE_MEM_OPERAND(a_pVCpu, a_uExitInstrInfo, a_uExitQual, a_enmMemAccess, a_pGCPtrEffAddr) \
216 do \
217 { \
218 VBOXSTRICTRC rcStrictTmp = hmR0VmxDecodeMemOperand((a_pVCpu), (a_uExitInstrInfo), (a_uExitQual), (a_enmMemAccess), \
219 (a_pGCPtrEffAddr)); \
220 if (rcStrictTmp == VINF_SUCCESS) \
221 { /* likely */ } \
222 else if (rcStrictTmp == VINF_HM_PENDING_XCPT) \
223 { \
224 uint8_t const uXcptTmp = VMX_ENTRY_INT_INFO_VECTOR((a_pVCpu)->hm.s.Event.u64IntInfo); \
225 Log4Func(("Memory operand decoding failed, raising xcpt %#x\n", uXcptTmp)); \
226 NOREF(uXcptTmp); \
227 return VINF_SUCCESS; \
228 } \
229 else \
230 { \
231 Log4Func(("hmR0VmxDecodeMemOperand failed. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrictTmp))); \
232 return rcStrictTmp; \
233 } \
234 } while (0)
235
236#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
237
238
239/*********************************************************************************************************************************
240* Structures and Typedefs *
241*********************************************************************************************************************************/
242/**
243 * VMX transient state.
244 *
245 * A state structure for holding miscellaneous information across
246 * VMX non-root operation and restored after the transition.
247 */
248typedef struct VMXTRANSIENT
249{
250 /** The host's rflags/eflags. */
251 RTCCUINTREG fEFlags;
252#if HC_ARCH_BITS == 32
253 uint32_t u32Alignment0;
254#endif
255 /** The guest's TPR value used for TPR shadowing. */
256 uint8_t u8GuestTpr;
257 /** Alignment. */
258 uint8_t abAlignment0[7];
259
260 /** The basic VM-exit reason. */
261 uint16_t uExitReason;
262 /** Alignment. */
263 uint16_t u16Alignment0;
264 /** The VM-exit interruption error code. */
265 uint32_t uExitIntErrorCode;
266 /** The VM-exit exit code qualification. */
267 uint64_t uExitQual;
268 /** The Guest-linear address. */
269 uint64_t uGuestLinearAddr;
270
271 /** The VM-exit interruption-information field. */
272 uint32_t uExitIntInfo;
273 /** The VM-exit instruction-length field. */
274 uint32_t cbInstr;
275 /** The VM-exit instruction-information field. */
276 VMXEXITINSTRINFO ExitInstrInfo;
277 /** Whether the VM-entry failed or not. */
278 bool fVMEntryFailed;
279 /** Alignment. */
280 uint8_t abAlignment1[3];
281
282 /** The VM-entry interruption-information field. */
283 uint32_t uEntryIntInfo;
284 /** The VM-entry exception error code field. */
285 uint32_t uEntryXcptErrorCode;
286 /** The VM-entry instruction length field. */
287 uint32_t cbEntryInstr;
288
289 /** IDT-vectoring information field. */
290 uint32_t uIdtVectoringInfo;
291 /** IDT-vectoring error code. */
292 uint32_t uIdtVectoringErrorCode;
293
294 /** Mask of currently read VMCS fields; HMVMX_READ_XXX. */
295 uint32_t fVmcsFieldsRead;
296
297 /** Whether the guest debug state was active at the time of VM-exit. */
298 bool fWasGuestDebugStateActive;
299 /** Whether the hyper debug state was active at the time of VM-exit. */
300 bool fWasHyperDebugStateActive;
301 /** Whether TSC-offsetting should be setup before VM-entry. */
302 bool fUpdateTscOffsettingAndPreemptTimer;
303 /** Whether the VM-exit was caused by a page-fault during delivery of a
304 * contributory exception or a page-fault. */
305 bool fVectoringDoublePF;
306 /** Whether the VM-exit was caused by a page-fault during delivery of an
307 * external interrupt or NMI. */
308 bool fVectoringPF;
309} VMXTRANSIENT;
310AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, sizeof(uint64_t));
311AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntInfo, sizeof(uint64_t));
312AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntInfo, sizeof(uint64_t));
313AssertCompileMemberAlignment(VMXTRANSIENT, fWasGuestDebugStateActive, sizeof(uint64_t));
314AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
315/** Pointer to VMX transient state. */
316typedef VMXTRANSIENT *PVMXTRANSIENT;
317
318/**
319 * Memory operand read or write access.
320 */
321typedef enum VMXMEMACCESS
322{
323 VMXMEMACCESS_READ = 0,
324 VMXMEMACCESS_WRITE = 1
325} VMXMEMACCESS;
326
327/**
328 * VMX VM-exit handler.
329 *
330 * @returns Strict VBox status code (i.e. informational status codes too).
331 * @param pVCpu The cross context virtual CPU structure.
332 * @param pVmxTransient Pointer to the VMX-transient structure.
333 */
334#ifndef HMVMX_USE_FUNCTION_TABLE
335typedef VBOXSTRICTRC FNVMXEXITHANDLER(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
336#else
337typedef DECLCALLBACK(VBOXSTRICTRC) FNVMXEXITHANDLER(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
338/** Pointer to VM-exit handler. */
339typedef FNVMXEXITHANDLER *PFNVMXEXITHANDLER;
340#endif
341
342/**
343 * VMX VM-exit handler, non-strict status code.
344 *
345 * This is generally the same as FNVMXEXITHANDLER, the NSRC bit is just FYI.
346 *
347 * @returns VBox status code, no informational status code returned.
348 * @param pVCpu The cross context virtual CPU structure.
349 * @param pVmxTransient Pointer to the VMX-transient structure.
350 *
351 * @remarks This is not used on anything returning VERR_EM_INTERPRETER as the
352 * use of that status code will be replaced with VINF_EM_SOMETHING
353 * later when switching over to IEM.
354 */
355#ifndef HMVMX_USE_FUNCTION_TABLE
356typedef int FNVMXEXITHANDLERNSRC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
357#else
358typedef FNVMXEXITHANDLER FNVMXEXITHANDLERNSRC;
359#endif
360
361
362/*********************************************************************************************************************************
363* Internal Functions *
364*********************************************************************************************************************************/
365static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXTLBFLUSHEPT enmTlbFlush);
366static void hmR0VmxFlushVpid(PVMCPU pVCpu, VMXTLBFLUSHVPID enmTlbFlush, RTGCPTR GCPtr);
367static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu);
368static int hmR0VmxImportGuestState(PVMCPU pVCpu, uint64_t fWhat);
369static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
370 RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *pfIntrState);
371#if HC_ARCH_BITS == 32
372static int hmR0VmxInitVmcsReadCache(PVMCPU pVCpu);
373#endif
374#ifndef HMVMX_USE_FUNCTION_TABLE
375DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t rcReason);
376# define HMVMX_EXIT_DECL DECLINLINE(VBOXSTRICTRC)
377# define HMVMX_EXIT_NSRC_DECL DECLINLINE(int)
378#else
379# define HMVMX_EXIT_DECL static DECLCALLBACK(VBOXSTRICTRC)
380# define HMVMX_EXIT_NSRC_DECL HMVMX_EXIT_DECL
381#endif
382
383/** @name VM-exit handlers.
384 * @{
385 */
386static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmi;
387static FNVMXEXITHANDLER hmR0VmxExitExtInt;
388static FNVMXEXITHANDLER hmR0VmxExitTripleFault;
389static FNVMXEXITHANDLERNSRC hmR0VmxExitInitSignal;
390static FNVMXEXITHANDLERNSRC hmR0VmxExitSipi;
391static FNVMXEXITHANDLERNSRC hmR0VmxExitIoSmi;
392static FNVMXEXITHANDLERNSRC hmR0VmxExitSmi;
393static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindow;
394static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindow;
395static FNVMXEXITHANDLER hmR0VmxExitTaskSwitch;
396static FNVMXEXITHANDLER hmR0VmxExitCpuid;
397static FNVMXEXITHANDLER hmR0VmxExitGetsec;
398static FNVMXEXITHANDLER hmR0VmxExitHlt;
399static FNVMXEXITHANDLERNSRC hmR0VmxExitInvd;
400static FNVMXEXITHANDLER hmR0VmxExitInvlpg;
401static FNVMXEXITHANDLER hmR0VmxExitRdpmc;
402static FNVMXEXITHANDLER hmR0VmxExitVmcall;
403#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
404static FNVMXEXITHANDLER hmR0VmxExitVmclear;
405static FNVMXEXITHANDLER hmR0VmxExitVmlaunch;
406static FNVMXEXITHANDLER hmR0VmxExitVmptrld;
407static FNVMXEXITHANDLER hmR0VmxExitVmptrst;
408static FNVMXEXITHANDLER hmR0VmxExitVmread;
409static FNVMXEXITHANDLER hmR0VmxExitVmresume;
410static FNVMXEXITHANDLER hmR0VmxExitVmwrite;
411static FNVMXEXITHANDLER hmR0VmxExitVmxoff;
412static FNVMXEXITHANDLER hmR0VmxExitVmxon;
413#endif
414static FNVMXEXITHANDLER hmR0VmxExitRdtsc;
415static FNVMXEXITHANDLERNSRC hmR0VmxExitRsm;
416static FNVMXEXITHANDLERNSRC hmR0VmxExitSetPendingXcptUD;
417static FNVMXEXITHANDLER hmR0VmxExitMovCRx;
418static FNVMXEXITHANDLER hmR0VmxExitMovDRx;
419static FNVMXEXITHANDLER hmR0VmxExitIoInstr;
420static FNVMXEXITHANDLER hmR0VmxExitRdmsr;
421static FNVMXEXITHANDLER hmR0VmxExitWrmsr;
422static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestState;
423static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMsrLoad;
424static FNVMXEXITHANDLERNSRC hmR0VmxExitErrUndefined;
425static FNVMXEXITHANDLER hmR0VmxExitMwait;
426static FNVMXEXITHANDLER hmR0VmxExitMtf;
427static FNVMXEXITHANDLER hmR0VmxExitMonitor;
428static FNVMXEXITHANDLER hmR0VmxExitPause;
429static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMachineCheck;
430static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThreshold;
431static FNVMXEXITHANDLER hmR0VmxExitApicAccess;
432static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
433static FNVMXEXITHANDLER hmR0VmxExitEptViolation;
434static FNVMXEXITHANDLER hmR0VmxExitEptMisconfig;
435static FNVMXEXITHANDLER hmR0VmxExitRdtscp;
436static FNVMXEXITHANDLER hmR0VmxExitPreemptTimer;
437static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvd;
438static FNVMXEXITHANDLER hmR0VmxExitXsetbv;
439static FNVMXEXITHANDLER hmR0VmxExitRdrand;
440static FNVMXEXITHANDLER hmR0VmxExitInvpcid;
441/** @} */
442
443static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
444static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
445static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
446static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
447static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
448static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
449static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
450static uint32_t hmR0VmxCheckGuestState(PVMCPU pVCpu);
451
452
453/*********************************************************************************************************************************
454* Global Variables *
455*********************************************************************************************************************************/
456#ifdef HMVMX_USE_FUNCTION_TABLE
457
458/**
459 * VMX_EXIT dispatch table.
460 */
461static const PFNVMXEXITHANDLER g_apfnVMExitHandlers[VMX_EXIT_MAX + 1] =
462{
463 /* 00 VMX_EXIT_XCPT_OR_NMI */ hmR0VmxExitXcptOrNmi,
464 /* 01 VMX_EXIT_EXT_INT */ hmR0VmxExitExtInt,
465 /* 02 VMX_EXIT_TRIPLE_FAULT */ hmR0VmxExitTripleFault,
466 /* 03 VMX_EXIT_INIT_SIGNAL */ hmR0VmxExitInitSignal,
467 /* 04 VMX_EXIT_SIPI */ hmR0VmxExitSipi,
468 /* 05 VMX_EXIT_IO_SMI */ hmR0VmxExitIoSmi,
469 /* 06 VMX_EXIT_SMI */ hmR0VmxExitSmi,
470 /* 07 VMX_EXIT_INT_WINDOW */ hmR0VmxExitIntWindow,
471 /* 08 VMX_EXIT_NMI_WINDOW */ hmR0VmxExitNmiWindow,
472 /* 09 VMX_EXIT_TASK_SWITCH */ hmR0VmxExitTaskSwitch,
473 /* 10 VMX_EXIT_CPUID */ hmR0VmxExitCpuid,
474 /* 11 VMX_EXIT_GETSEC */ hmR0VmxExitGetsec,
475 /* 12 VMX_EXIT_HLT */ hmR0VmxExitHlt,
476 /* 13 VMX_EXIT_INVD */ hmR0VmxExitInvd,
477 /* 14 VMX_EXIT_INVLPG */ hmR0VmxExitInvlpg,
478 /* 15 VMX_EXIT_RDPMC */ hmR0VmxExitRdpmc,
479 /* 16 VMX_EXIT_RDTSC */ hmR0VmxExitRdtsc,
480 /* 17 VMX_EXIT_RSM */ hmR0VmxExitRsm,
481 /* 18 VMX_EXIT_VMCALL */ hmR0VmxExitVmcall,
482#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
483 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitVmclear,
484 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitVmlaunch,
485 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitVmptrld,
486 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitVmptrst,
487 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitVmread,
488 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitVmresume,
489 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitVmwrite,
490 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitVmxoff,
491 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitVmxon,
492#else
493 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitSetPendingXcptUD,
494 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitSetPendingXcptUD,
495 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitSetPendingXcptUD,
496 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitSetPendingXcptUD,
497 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitSetPendingXcptUD,
498 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitSetPendingXcptUD,
499 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitSetPendingXcptUD,
500 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitSetPendingXcptUD,
501 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitSetPendingXcptUD,
502#endif
503 /* 28 VMX_EXIT_MOV_CRX */ hmR0VmxExitMovCRx,
504 /* 29 VMX_EXIT_MOV_DRX */ hmR0VmxExitMovDRx,
505 /* 30 VMX_EXIT_IO_INSTR */ hmR0VmxExitIoInstr,
506 /* 31 VMX_EXIT_RDMSR */ hmR0VmxExitRdmsr,
507 /* 32 VMX_EXIT_WRMSR */ hmR0VmxExitWrmsr,
508 /* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ hmR0VmxExitErrInvalidGuestState,
509 /* 34 VMX_EXIT_ERR_MSR_LOAD */ hmR0VmxExitErrMsrLoad,
510 /* 35 UNDEFINED */ hmR0VmxExitErrUndefined,
511 /* 36 VMX_EXIT_MWAIT */ hmR0VmxExitMwait,
512 /* 37 VMX_EXIT_MTF */ hmR0VmxExitMtf,
513 /* 38 UNDEFINED */ hmR0VmxExitErrUndefined,
514 /* 39 VMX_EXIT_MONITOR */ hmR0VmxExitMonitor,
515 /* 40 UNDEFINED */ hmR0VmxExitPause,
516 /* 41 VMX_EXIT_PAUSE */ hmR0VmxExitErrMachineCheck,
517 /* 42 VMX_EXIT_ERR_MACHINE_CHECK */ hmR0VmxExitErrUndefined,
518 /* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ hmR0VmxExitTprBelowThreshold,
519 /* 44 VMX_EXIT_APIC_ACCESS */ hmR0VmxExitApicAccess,
520 /* 45 UNDEFINED */ hmR0VmxExitErrUndefined,
521 /* 46 VMX_EXIT_GDTR_IDTR_ACCESS */ hmR0VmxExitXdtrAccess,
522 /* 47 VMX_EXIT_LDTR_TR_ACCESS */ hmR0VmxExitXdtrAccess,
523 /* 48 VMX_EXIT_EPT_VIOLATION */ hmR0VmxExitEptViolation,
524 /* 49 VMX_EXIT_EPT_MISCONFIG */ hmR0VmxExitEptMisconfig,
525 /* 50 VMX_EXIT_INVEPT */ hmR0VmxExitSetPendingXcptUD,
526 /* 51 VMX_EXIT_RDTSCP */ hmR0VmxExitRdtscp,
527 /* 52 VMX_EXIT_PREEMPT_TIMER */ hmR0VmxExitPreemptTimer,
528 /* 53 VMX_EXIT_INVVPID */ hmR0VmxExitSetPendingXcptUD,
529 /* 54 VMX_EXIT_WBINVD */ hmR0VmxExitWbinvd,
530 /* 55 VMX_EXIT_XSETBV */ hmR0VmxExitXsetbv,
531 /* 56 VMX_EXIT_APIC_WRITE */ hmR0VmxExitErrUndefined,
532 /* 57 VMX_EXIT_RDRAND */ hmR0VmxExitRdrand,
533 /* 58 VMX_EXIT_INVPCID */ hmR0VmxExitInvpcid,
534 /* 59 VMX_EXIT_VMFUNC */ hmR0VmxExitSetPendingXcptUD,
535 /* 60 VMX_EXIT_ENCLS */ hmR0VmxExitErrUndefined,
536 /* 61 VMX_EXIT_RDSEED */ hmR0VmxExitErrUndefined, /* only spurious exits, so undefined */
537 /* 62 VMX_EXIT_PML_FULL */ hmR0VmxExitErrUndefined,
538 /* 63 VMX_EXIT_XSAVES */ hmR0VmxExitSetPendingXcptUD,
539 /* 64 VMX_EXIT_XRSTORS */ hmR0VmxExitSetPendingXcptUD,
540};
541#endif /* HMVMX_USE_FUNCTION_TABLE */
542
543#if defined(VBOX_STRICT) && defined(LOG_ENABLED)
544static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
545{
546 /* 0 */ "(Not Used)",
547 /* 1 */ "VMCALL executed in VMX root operation.",
548 /* 2 */ "VMCLEAR with invalid physical address.",
549 /* 3 */ "VMCLEAR with VMXON pointer.",
550 /* 4 */ "VMLAUNCH with non-clear VMCS.",
551 /* 5 */ "VMRESUME with non-launched VMCS.",
552 /* 6 */ "VMRESUME after VMXOFF",
553 /* 7 */ "VM-entry with invalid control fields.",
554 /* 8 */ "VM-entry with invalid host state fields.",
555 /* 9 */ "VMPTRLD with invalid physical address.",
556 /* 10 */ "VMPTRLD with VMXON pointer.",
557 /* 11 */ "VMPTRLD with incorrect revision identifier.",
558 /* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
559 /* 13 */ "VMWRITE to read-only VMCS component.",
560 /* 14 */ "(Not Used)",
561 /* 15 */ "VMXON executed in VMX root operation.",
562 /* 16 */ "VM-entry with invalid executive-VMCS pointer.",
563 /* 17 */ "VM-entry with non-launched executing VMCS.",
564 /* 18 */ "VM-entry with executive-VMCS pointer not VMXON pointer.",
565 /* 19 */ "VMCALL with non-clear VMCS.",
566 /* 20 */ "VMCALL with invalid VM-exit control fields.",
567 /* 21 */ "(Not Used)",
568 /* 22 */ "VMCALL with incorrect MSEG revision identifier.",
569 /* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
570 /* 24 */ "VMCALL with invalid SMM-monitor features.",
571 /* 25 */ "VM-entry with invalid VM-execution control fields in executive VMCS.",
572 /* 26 */ "VM-entry with events blocked by MOV SS.",
573 /* 27 */ "(Not Used)",
574 /* 28 */ "Invalid operand to INVEPT/INVVPID."
575};
576#endif /* VBOX_STRICT */
577
578
579/**
580 * Updates the VM's last error record.
581 *
582 * If there was a VMX instruction error, reads the error data from the VMCS and
583 * updates VCPU's last error record as well.
584 *
585 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
586 * Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
587 * VERR_VMX_INVALID_VMCS_FIELD.
588 * @param rc The error code.
589 */
590static void hmR0VmxUpdateErrorRecord(PVMCPU pVCpu, int rc)
591{
592 if ( rc == VERR_VMX_INVALID_VMCS_FIELD
593 || rc == VERR_VMX_UNABLE_TO_START_VM)
594 {
595 AssertPtrReturnVoid(pVCpu);
596 VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
597 }
598 pVCpu->CTX_SUFF(pVM)->hm.s.rcInit = rc;
599}
600
601
602/**
603 * Reads the VM-entry interruption-information field from the VMCS into the VMX
604 * transient structure.
605 *
606 * @returns VBox status code.
607 * @param pVmxTransient Pointer to the VMX transient structure.
608 *
609 * @remarks No-long-jump zone!!!
610 */
611DECLINLINE(int) hmR0VmxReadEntryIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
612{
613 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);
614 AssertRCReturn(rc, rc);
615 return VINF_SUCCESS;
616}
617
618#ifdef VBOX_STRICT
619/**
620 * Reads the VM-entry exception error code field from the VMCS into
621 * the VMX transient structure.
622 *
623 * @returns VBox status code.
624 * @param pVmxTransient Pointer to the VMX transient structure.
625 *
626 * @remarks No-long-jump zone!!!
627 */
628DECLINLINE(int) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
629{
630 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
631 AssertRCReturn(rc, rc);
632 return VINF_SUCCESS;
633}
634
635
636/**
637 * Reads the VM-entry exception error code field from the VMCS into
638 * the VMX transient structure.
639 *
640 * @returns VBox status code.
641 * @param pVmxTransient Pointer to the VMX transient structure.
642 *
643 * @remarks No-long-jump zone!!!
644 */
645DECLINLINE(int) hmR0VmxReadEntryInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
646{
647 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
648 AssertRCReturn(rc, rc);
649 return VINF_SUCCESS;
650}
651#endif /* VBOX_STRICT */
652
653
654/**
655 * Reads the VM-exit interruption-information field from the VMCS into the VMX
656 * transient structure.
657 *
658 * @returns VBox status code.
659 * @param pVmxTransient Pointer to the VMX transient structure.
660 */
661DECLINLINE(int) hmR0VmxReadExitIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
662{
663 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_INFO))
664 {
665 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
666 AssertRCReturn(rc,rc);
667 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_INFO;
668 }
669 return VINF_SUCCESS;
670}
671
672
673/**
674 * Reads the VM-exit interruption error code from the VMCS into the VMX
675 * transient structure.
676 *
677 * @returns VBox status code.
678 * @param pVmxTransient Pointer to the VMX transient structure.
679 */
680DECLINLINE(int) hmR0VmxReadExitIntErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
681{
682 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE))
683 {
684 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
685 AssertRCReturn(rc, rc);
686 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE;
687 }
688 return VINF_SUCCESS;
689}
690
691
692/**
693 * Reads the VM-exit instruction length field from the VMCS into the VMX
694 * transient structure.
695 *
696 * @returns VBox status code.
697 * @param pVmxTransient Pointer to the VMX transient structure.
698 */
699DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
700{
701 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_LEN))
702 {
703 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
704 AssertRCReturn(rc, rc);
705 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_LEN;
706 }
707 return VINF_SUCCESS;
708}
709
710
711/**
712 * Reads the VM-exit instruction-information field from the VMCS into
713 * the VMX transient structure.
714 *
715 * @returns VBox status code.
716 * @param pVmxTransient Pointer to the VMX transient structure.
717 */
718DECLINLINE(int) hmR0VmxReadExitInstrInfoVmcs(PVMXTRANSIENT pVmxTransient)
719{
720 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_INFO))
721 {
722 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
723 AssertRCReturn(rc, rc);
724 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_INFO;
725 }
726 return VINF_SUCCESS;
727}
728
729
730/**
731 * Reads the VM-exit Qualification from the VMCS into the VMX transient structure.
732 *
733 * @returns VBox status code.
734 * @param pVCpu The cross context virtual CPU structure of the
735 * calling EMT. (Required for the VMCS cache case.)
736 * @param pVmxTransient Pointer to the VMX transient structure.
737 */
738DECLINLINE(int) hmR0VmxReadExitQualVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
739{
740 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_QUALIFICATION))
741 {
742 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual); NOREF(pVCpu);
743 AssertRCReturn(rc, rc);
744 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_QUALIFICATION;
745 }
746 return VINF_SUCCESS;
747}
748
749
750/**
751 * Reads the Guest-linear address from the VMCS into the VMX transient structure.
752 *
753 * @returns VBox status code.
754 * @param pVCpu The cross context virtual CPU structure of the
755 * calling EMT. (Required for the VMCS cache case.)
756 * @param pVmxTransient Pointer to the VMX transient structure.
757 */
758DECLINLINE(int) hmR0VmxReadGuestLinearAddrVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
759{
760 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_LINEAR_ADDR))
761 {
762 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr); NOREF(pVCpu);
763 AssertRCReturn(rc, rc);
764 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_GUEST_LINEAR_ADDR;
765 }
766 return VINF_SUCCESS;
767}
768
769
770/**
771 * Reads the IDT-vectoring information field from the VMCS into the VMX
772 * transient structure.
773 *
774 * @returns VBox status code.
775 * @param pVmxTransient Pointer to the VMX transient structure.
776 *
777 * @remarks No-long-jump zone!!!
778 */
779DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
780{
781 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_INFO))
782 {
783 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo);
784 AssertRCReturn(rc, rc);
785 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_INFO;
786 }
787 return VINF_SUCCESS;
788}
789
790
791/**
792 * Reads the IDT-vectoring error code from the VMCS into the VMX
793 * transient structure.
794 *
795 * @returns VBox status code.
796 * @param pVmxTransient Pointer to the VMX transient structure.
797 */
798DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
799{
800 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_ERROR_CODE))
801 {
802 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
803 AssertRCReturn(rc, rc);
804 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_ERROR_CODE;
805 }
806 return VINF_SUCCESS;
807}
808
809
810/**
811 * Enters VMX root mode operation on the current CPU.
812 *
813 * @returns VBox status code.
814 * @param pVM The cross context VM structure. Can be
815 * NULL, after a resume.
816 * @param HCPhysCpuPage Physical address of the VMXON region.
817 * @param pvCpuPage Pointer to the VMXON region.
818 */
819static int hmR0VmxEnterRootMode(PVM pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
820{
821 Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
822 Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
823 Assert(pvCpuPage);
824 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
825
826 if (pVM)
827 {
828 /* Write the VMCS revision dword to the VMXON region. */
829 *(uint32_t *)pvCpuPage = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
830 }
831
832 /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
833 RTCCUINTREG fEFlags = ASMIntDisableFlags();
834
835 /* Enable the VMX bit in CR4 if necessary. */
836 RTCCUINTREG uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
837
838 /* Enter VMX root mode. */
839 int rc = VMXEnable(HCPhysCpuPage);
840 if (RT_FAILURE(rc))
841 {
842 if (!(uOldCr4 & X86_CR4_VMXE))
843 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
844
845 if (pVM)
846 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
847 }
848
849 /* Restore interrupts. */
850 ASMSetFlags(fEFlags);
851 return rc;
852}
853
854
855/**
856 * Exits VMX root mode operation on the current CPU.
857 *
858 * @returns VBox status code.
859 */
860static int hmR0VmxLeaveRootMode(void)
861{
862 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
863
864 /* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
865 RTCCUINTREG fEFlags = ASMIntDisableFlags();
866
867 /* If we're for some reason not in VMX root mode, then don't leave it. */
868 RTCCUINTREG uHostCR4 = ASMGetCR4();
869
870 int rc;
871 if (uHostCR4 & X86_CR4_VMXE)
872 {
873 /* Exit VMX root mode and clear the VMX bit in CR4. */
874 VMXDisable();
875 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
876 rc = VINF_SUCCESS;
877 }
878 else
879 rc = VERR_VMX_NOT_IN_VMX_ROOT_MODE;
880
881 /* Restore interrupts. */
882 ASMSetFlags(fEFlags);
883 return rc;
884}
885
886
887/**
888 * Allocates and maps one physically contiguous page. The allocated page is
889 * zero'd out. (Used by various VT-x structures).
890 *
891 * @returns IPRT status code.
892 * @param pMemObj Pointer to the ring-0 memory object.
893 * @param ppVirt Where to store the virtual address of the
894 * allocation.
895 * @param pHCPhys Where to store the physical address of the
896 * allocation.
897 */
898static int hmR0VmxPageAllocZ(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
899{
900 AssertPtrReturn(pMemObj, VERR_INVALID_PARAMETER);
901 AssertPtrReturn(ppVirt, VERR_INVALID_PARAMETER);
902 AssertPtrReturn(pHCPhys, VERR_INVALID_PARAMETER);
903
904 int rc = RTR0MemObjAllocCont(pMemObj, PAGE_SIZE, false /* fExecutable */);
905 if (RT_FAILURE(rc))
906 return rc;
907 *ppVirt = RTR0MemObjAddress(*pMemObj);
908 *pHCPhys = RTR0MemObjGetPagePhysAddr(*pMemObj, 0 /* iPage */);
909 ASMMemZero32(*ppVirt, PAGE_SIZE);
910 return VINF_SUCCESS;
911}
912
913
914/**
915 * Frees and unmaps an allocated physical page.
916 *
917 * @param pMemObj Pointer to the ring-0 memory object.
918 * @param ppVirt Where to re-initialize the virtual address of
919 * allocation as 0.
920 * @param pHCPhys Where to re-initialize the physical address of the
921 * allocation as 0.
922 */
923static void hmR0VmxPageFree(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
924{
925 AssertPtr(pMemObj);
926 AssertPtr(ppVirt);
927 AssertPtr(pHCPhys);
928 if (*pMemObj != NIL_RTR0MEMOBJ)
929 {
930 int rc = RTR0MemObjFree(*pMemObj, true /* fFreeMappings */);
931 AssertRC(rc);
932 *pMemObj = NIL_RTR0MEMOBJ;
933 *ppVirt = 0;
934 *pHCPhys = 0;
935 }
936}
937
938
939/**
940 * Worker function to free VT-x related structures.
941 *
942 * @returns IPRT status code.
943 * @param pVM The cross context VM structure.
944 */
945static void hmR0VmxStructsFree(PVM pVM)
946{
947 for (VMCPUID i = 0; i < pVM->cCpus; i++)
948 {
949 PVMCPU pVCpu = &pVM->aCpus[i];
950 AssertPtr(pVCpu);
951
952 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
953 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
954
955 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
956 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
957
958 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
959 }
960
961 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, &pVM->hm.s.vmx.HCPhysApicAccess);
962#ifdef VBOX_WITH_CRASHDUMP_MAGIC
963 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
964#endif
965}
966
967
968/**
969 * Worker function to allocate VT-x related VM structures.
970 *
971 * @returns IPRT status code.
972 * @param pVM The cross context VM structure.
973 */
974static int hmR0VmxStructsAlloc(PVM pVM)
975{
976 /*
977 * Initialize members up-front so we can cleanup properly on allocation failure.
978 */
979#define VMXLOCAL_INIT_VM_MEMOBJ(a_Name, a_VirtPrefix) \
980 pVM->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
981 pVM->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
982 pVM->hm.s.vmx.HCPhys##a_Name = 0;
983
984#define VMXLOCAL_INIT_VMCPU_MEMOBJ(a_Name, a_VirtPrefix) \
985 pVCpu->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
986 pVCpu->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
987 pVCpu->hm.s.vmx.HCPhys##a_Name = 0;
988
989#ifdef VBOX_WITH_CRASHDUMP_MAGIC
990 VMXLOCAL_INIT_VM_MEMOBJ(Scratch, pv);
991#endif
992 VMXLOCAL_INIT_VM_MEMOBJ(ApicAccess, pb);
993
994 AssertCompile(sizeof(VMCPUID) == sizeof(pVM->cCpus));
995 for (VMCPUID i = 0; i < pVM->cCpus; i++)
996 {
997 PVMCPU pVCpu = &pVM->aCpus[i];
998 VMXLOCAL_INIT_VMCPU_MEMOBJ(Vmcs, pv);
999 VMXLOCAL_INIT_VMCPU_MEMOBJ(MsrBitmap, pv);
1000 VMXLOCAL_INIT_VMCPU_MEMOBJ(GuestMsr, pv);
1001 VMXLOCAL_INIT_VMCPU_MEMOBJ(HostMsr, pv);
1002 }
1003#undef VMXLOCAL_INIT_VMCPU_MEMOBJ
1004#undef VMXLOCAL_INIT_VM_MEMOBJ
1005
1006 /* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
1007 AssertReturnStmt(RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_SIZE) <= PAGE_SIZE,
1008 (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
1009 VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
1010
1011 /*
1012 * Allocate all the VT-x structures.
1013 */
1014 int rc = VINF_SUCCESS;
1015#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1016 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
1017 if (RT_FAILURE(rc))
1018 goto cleanup;
1019 strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
1020 *(uint64_t *)(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
1021#endif
1022
1023 /* Allocate the APIC-access page for trapping APIC accesses from the guest. */
1024 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
1025 {
1026 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
1027 &pVM->hm.s.vmx.HCPhysApicAccess);
1028 if (RT_FAILURE(rc))
1029 goto cleanup;
1030 }
1031
1032 /*
1033 * Initialize per-VCPU VT-x structures.
1034 */
1035 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1036 {
1037 PVMCPU pVCpu = &pVM->aCpus[i];
1038 AssertPtr(pVCpu);
1039
1040 /* Allocate the VM control structure (VMCS). */
1041 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
1042 if (RT_FAILURE(rc))
1043 goto cleanup;
1044
1045 /* Get the allocated virtual-APIC page from the APIC device for transparent TPR accesses. */
1046 if ( PDMHasApic(pVM)
1047 && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
1048 {
1049 rc = APICGetApicPageForCpu(pVCpu, &pVCpu->hm.s.vmx.HCPhysVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
1050 NULL /* pR3Ptr */, NULL /* pRCPtr */);
1051 if (RT_FAILURE(rc))
1052 goto cleanup;
1053 }
1054
1055 /*
1056 * Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for
1057 * transparent accesses of specific MSRs.
1058 *
1059 * If the condition for enabling MSR bitmaps changes here, don't forget to
1060 * update HMAreMsrBitmapsAvailable().
1061 */
1062 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1063 {
1064 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
1065 &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1066 if (RT_FAILURE(rc))
1067 goto cleanup;
1068 ASMMemFill32(pVCpu->hm.s.vmx.pvMsrBitmap, PAGE_SIZE, UINT32_C(0xffffffff));
1069 }
1070
1071 /* Allocate the VM-entry MSR-load and VM-exit MSR-store page for the guest MSRs. */
1072 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
1073 if (RT_FAILURE(rc))
1074 goto cleanup;
1075
1076 /* Allocate the VM-exit MSR-load page for the host MSRs. */
1077 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
1078 if (RT_FAILURE(rc))
1079 goto cleanup;
1080 }
1081
1082 return VINF_SUCCESS;
1083
1084cleanup:
1085 hmR0VmxStructsFree(pVM);
1086 return rc;
1087}
1088
1089
1090/**
1091 * Does global VT-x initialization (called during module initialization).
1092 *
1093 * @returns VBox status code.
1094 */
1095VMMR0DECL(int) VMXR0GlobalInit(void)
1096{
1097#ifdef HMVMX_USE_FUNCTION_TABLE
1098 AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_apfnVMExitHandlers));
1099# ifdef VBOX_STRICT
1100 for (unsigned i = 0; i < RT_ELEMENTS(g_apfnVMExitHandlers); i++)
1101 Assert(g_apfnVMExitHandlers[i]);
1102# endif
1103#endif
1104 return VINF_SUCCESS;
1105}
1106
1107
1108/**
1109 * Does global VT-x termination (called during module termination).
1110 */
1111VMMR0DECL(void) VMXR0GlobalTerm()
1112{
1113 /* Nothing to do currently. */
1114}
1115
1116
1117/**
1118 * Sets up and activates VT-x on the current CPU.
1119 *
1120 * @returns VBox status code.
1121 * @param pHostCpu The HM physical-CPU structure.
1122 * @param pVM The cross context VM structure. Can be
1123 * NULL after a host resume operation.
1124 * @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
1125 * fEnabledByHost is @c true).
1126 * @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
1127 * @a fEnabledByHost is @c true).
1128 * @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
1129 * enable VT-x on the host.
1130 * @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs.
1131 */
1132VMMR0DECL(int) VMXR0EnableCpu(PHMPHYSCPU pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
1133 PCSUPHWVIRTMSRS pHwvirtMsrs)
1134{
1135 Assert(pHostCpu);
1136 Assert(pHwvirtMsrs);
1137 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1138
1139 /* Enable VT-x if it's not already enabled by the host. */
1140 if (!fEnabledByHost)
1141 {
1142 int rc = hmR0VmxEnterRootMode(pVM, HCPhysCpuPage, pvCpuPage);
1143 if (RT_FAILURE(rc))
1144 return rc;
1145 }
1146
1147 /*
1148 * Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been
1149 * using EPTPs) so we don't retain any stale guest-physical mappings which won't get
1150 * invalidated when flushing by VPID.
1151 */
1152 if (pHwvirtMsrs->u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1153 {
1154 hmR0VmxFlushEpt(NULL /* pVCpu */, VMXTLBFLUSHEPT_ALL_CONTEXTS);
1155 pHostCpu->fFlushAsidBeforeUse = false;
1156 }
1157 else
1158 pHostCpu->fFlushAsidBeforeUse = true;
1159
1160 /* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
1161 ++pHostCpu->cTlbFlushes;
1162
1163 return VINF_SUCCESS;
1164}
1165
1166
1167/**
1168 * Deactivates VT-x on the current CPU.
1169 *
1170 * @returns VBox status code.
1171 * @param pvCpuPage Pointer to the VMXON region.
1172 * @param HCPhysCpuPage Physical address of the VMXON region.
1173 *
1174 * @remarks This function should never be called when SUPR0EnableVTx() or
1175 * similar was used to enable VT-x on the host.
1176 */
1177VMMR0DECL(int) VMXR0DisableCpu(void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
1178{
1179 RT_NOREF2(pvCpuPage, HCPhysCpuPage);
1180
1181 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1182 return hmR0VmxLeaveRootMode();
1183}
1184
1185
1186/**
1187 * Sets the permission bits for the specified MSR in the MSR bitmap.
1188 *
1189 * @param pVCpu The cross context virtual CPU structure.
1190 * @param uMsr The MSR value.
1191 * @param enmRead Whether reading this MSR causes a VM-exit.
1192 * @param enmWrite Whether writing this MSR causes a VM-exit.
1193 */
1194static void hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite)
1195{
1196 int32_t iBit;
1197 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1198
1199 /*
1200 * MSR Layout:
1201 * Byte index MSR range Interpreted as
1202 * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
1203 * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
1204 * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
1205 * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
1206 *
1207 * A bit corresponding to an MSR within the above range causes a VM-exit
1208 * if the bit is 1 on executions of RDMSR/WRMSR.
1209 *
1210 * If an MSR falls out of the MSR range, it always cause a VM-exit.
1211 *
1212 * See Intel spec. 24.6.9 "MSR-Bitmap Address".
1213 */
1214 if (uMsr <= 0x00001fff)
1215 iBit = uMsr;
1216 else if (uMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
1217 {
1218 iBit = uMsr - UINT32_C(0xc0000000);
1219 pbMsrBitmap += 0x400;
1220 }
1221 else
1222 AssertMsgFailedReturnVoid(("hmR0VmxSetMsrPermission: Invalid MSR %#RX32\n", uMsr));
1223
1224 Assert(iBit <= 0x1fff);
1225 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
1226 ASMBitSet(pbMsrBitmap, iBit);
1227 else
1228 ASMBitClear(pbMsrBitmap, iBit);
1229
1230 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
1231 ASMBitSet(pbMsrBitmap + 0x800, iBit);
1232 else
1233 ASMBitClear(pbMsrBitmap + 0x800, iBit);
1234}
1235
1236
1237/**
1238 * Updates the VMCS with the number of effective MSRs in the auto-load/store MSR
1239 * area.
1240 *
1241 * @returns VBox status code.
1242 * @param pVCpu The cross context virtual CPU structure.
1243 * @param cMsrs The number of MSRs.
1244 */
1245static int hmR0VmxSetAutoLoadStoreMsrCount(PVMCPU pVCpu, uint32_t cMsrs)
1246{
1247 /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
1248 uint64_t const uVmxMiscMsr = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc;
1249 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(uVmxMiscMsr);
1250 if (RT_UNLIKELY(cMsrs > cMaxSupportedMsrs))
1251 {
1252 LogRel(("CPU auto-load/store MSR count in VMCS exceeded cMsrs=%u Supported=%u.\n", cMsrs, cMaxSupportedMsrs));
1253 pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
1254 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1255 }
1256
1257 /* Update number of guest MSRs to load/store across the world-switch. */
1258 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs);
1259 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs);
1260
1261 /* Update number of host MSRs to load after the world-switch. Identical to guest-MSR count as it's always paired. */
1262 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs);
1263 AssertRCReturn(rc, rc);
1264
1265 /* Update the VCPU's copy of the MSR count. */
1266 pVCpu->hm.s.vmx.cMsrs = cMsrs;
1267
1268 return VINF_SUCCESS;
1269}
1270
1271
1272/**
1273 * Adds a new (or updates the value of an existing) guest/host MSR
1274 * pair to be swapped during the world-switch as part of the
1275 * auto-load/store MSR area in the VMCS.
1276 *
1277 * @returns VBox status code.
1278 * @param pVCpu The cross context virtual CPU structure.
1279 * @param uMsr The MSR.
1280 * @param uGuestMsrValue Value of the guest MSR.
1281 * @param fUpdateHostMsr Whether to update the value of the host MSR if
1282 * necessary.
1283 * @param pfAddedAndUpdated Where to store whether the MSR was added -and-
1284 * its value was updated. Optional, can be NULL.
1285 */
1286static int hmR0VmxAddAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr, uint64_t uGuestMsrValue, bool fUpdateHostMsr,
1287 bool *pfAddedAndUpdated)
1288{
1289 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1290 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1291 uint32_t i;
1292 for (i = 0; i < cMsrs; i++)
1293 {
1294 if (pGuestMsr->u32Msr == uMsr)
1295 break;
1296 pGuestMsr++;
1297 }
1298
1299 bool fAdded = false;
1300 if (i == cMsrs)
1301 {
1302 ++cMsrs;
1303 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1304 AssertMsgRCReturn(rc, ("hmR0VmxAddAutoLoadStoreMsr: Insufficient space to add MSR %u\n", uMsr), rc);
1305
1306 /* Now that we're swapping MSRs during the world-switch, allow the guest to read/write them without causing VM-exits. */
1307 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1308 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1309
1310 fAdded = true;
1311 }
1312
1313 /* Update the MSR values in the auto-load/store MSR area. */
1314 pGuestMsr->u32Msr = uMsr;
1315 pGuestMsr->u64Value = uGuestMsrValue;
1316
1317 /* Create/update the MSR slot in the host MSR area. */
1318 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1319 pHostMsr += i;
1320 pHostMsr->u32Msr = uMsr;
1321
1322 /*
1323 * Update the host MSR only when requested by the caller AND when we're
1324 * adding it to the auto-load/store area. Otherwise, it would have been
1325 * updated by hmR0VmxExportHostMsrs(). We do this for performance reasons.
1326 */
1327 bool fUpdatedMsrValue = false;
1328 if ( fAdded
1329 && fUpdateHostMsr)
1330 {
1331 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1332 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1333 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1334 fUpdatedMsrValue = true;
1335 }
1336
1337 if (pfAddedAndUpdated)
1338 *pfAddedAndUpdated = fUpdatedMsrValue;
1339 return VINF_SUCCESS;
1340}
1341
1342
1343/**
1344 * Removes a guest/host MSR pair to be swapped during the world-switch from the
1345 * auto-load/store MSR area in the VMCS.
1346 *
1347 * @returns VBox status code.
1348 * @param pVCpu The cross context virtual CPU structure.
1349 * @param uMsr The MSR.
1350 */
1351static int hmR0VmxRemoveAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr)
1352{
1353 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1354 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1355 for (uint32_t i = 0; i < cMsrs; i++)
1356 {
1357 /* Find the MSR. */
1358 if (pGuestMsr->u32Msr == uMsr)
1359 {
1360 /* If it's the last MSR, simply reduce the count. */
1361 if (i == cMsrs - 1)
1362 {
1363 --cMsrs;
1364 break;
1365 }
1366
1367 /* Remove it by swapping the last MSR in place of it, and reducing the count. */
1368 PVMXAUTOMSR pLastGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1369 pLastGuestMsr += cMsrs - 1;
1370 pGuestMsr->u32Msr = pLastGuestMsr->u32Msr;
1371 pGuestMsr->u64Value = pLastGuestMsr->u64Value;
1372
1373 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1374 PVMXAUTOMSR pLastHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1375 pLastHostMsr += cMsrs - 1;
1376 pHostMsr->u32Msr = pLastHostMsr->u32Msr;
1377 pHostMsr->u64Value = pLastHostMsr->u64Value;
1378 --cMsrs;
1379 break;
1380 }
1381 pGuestMsr++;
1382 }
1383
1384 /* Update the VMCS if the count changed (meaning the MSR was found). */
1385 if (cMsrs != pVCpu->hm.s.vmx.cMsrs)
1386 {
1387 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1388 AssertRCReturn(rc, rc);
1389
1390 /* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
1391 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1392 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
1393
1394 Log4Func(("Removed MSR %#RX32 new cMsrs=%u\n", uMsr, pVCpu->hm.s.vmx.cMsrs));
1395 return VINF_SUCCESS;
1396 }
1397
1398 return VERR_NOT_FOUND;
1399}
1400
1401
1402/**
1403 * Checks if the specified guest MSR is part of the auto-load/store area in
1404 * the VMCS.
1405 *
1406 * @returns true if found, false otherwise.
1407 * @param pVCpu The cross context virtual CPU structure.
1408 * @param uMsr The MSR to find.
1409 */
1410static bool hmR0VmxIsAutoLoadStoreGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1411{
1412 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1413 uint32_t const cMsrs = pVCpu->hm.s.vmx.cMsrs;
1414
1415 for (uint32_t i = 0; i < cMsrs; i++, pGuestMsr++)
1416 {
1417 if (pGuestMsr->u32Msr == uMsr)
1418 return true;
1419 }
1420 return false;
1421}
1422
1423
1424/**
1425 * Updates the value of all host MSRs in the auto-load/store area in the VMCS.
1426 *
1427 * @param pVCpu The cross context virtual CPU structure.
1428 *
1429 * @remarks No-long-jump zone!!!
1430 */
1431static void hmR0VmxUpdateAutoLoadStoreHostMsrs(PVMCPU pVCpu)
1432{
1433 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1434 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1435 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1436 uint32_t const cMsrs = pVCpu->hm.s.vmx.cMsrs;
1437
1438 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1439 {
1440 AssertReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr);
1441
1442 /*
1443 * Performance hack for the host EFER MSR. We use the cached value rather than re-read it.
1444 * Strict builds will catch mismatches in hmR0VmxCheckAutoLoadStoreMsrs(). See @bugref{7368}.
1445 */
1446 if (pHostMsr->u32Msr == MSR_K6_EFER)
1447 pHostMsr->u64Value = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.u64HostEfer;
1448 else
1449 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1450 }
1451
1452 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
1453}
1454
1455
1456/**
1457 * Saves a set of host MSRs to allow read/write passthru access to the guest and
1458 * perform lazy restoration of the host MSRs while leaving VT-x.
1459 *
1460 * @param pVCpu The cross context virtual CPU structure.
1461 *
1462 * @remarks No-long-jump zone!!!
1463 */
1464static void hmR0VmxLazySaveHostMsrs(PVMCPU pVCpu)
1465{
1466 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1467
1468 /*
1469 * Note: If you're adding MSRs here, make sure to update the MSR-bitmap permissions in hmR0VmxSetupProcCtls().
1470 */
1471 if (!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST))
1472 {
1473 Assert(!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */
1474#if HC_ARCH_BITS == 64
1475 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1476 {
1477 pVCpu->hm.s.vmx.u64HostLStarMsr = ASMRdMsr(MSR_K8_LSTAR);
1478 pVCpu->hm.s.vmx.u64HostStarMsr = ASMRdMsr(MSR_K6_STAR);
1479 pVCpu->hm.s.vmx.u64HostSFMaskMsr = ASMRdMsr(MSR_K8_SF_MASK);
1480 pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1481 }
1482#endif
1483 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_SAVED_HOST;
1484 }
1485}
1486
1487
1488/**
1489 * Checks whether the MSR belongs to the set of guest MSRs that we restore
1490 * lazily while leaving VT-x.
1491 *
1492 * @returns true if it does, false otherwise.
1493 * @param pVCpu The cross context virtual CPU structure.
1494 * @param uMsr The MSR to check.
1495 */
1496static bool hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1497{
1498 NOREF(pVCpu);
1499#if HC_ARCH_BITS == 64
1500 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1501 {
1502 switch (uMsr)
1503 {
1504 case MSR_K8_LSTAR:
1505 case MSR_K6_STAR:
1506 case MSR_K8_SF_MASK:
1507 case MSR_K8_KERNEL_GS_BASE:
1508 return true;
1509 }
1510 }
1511#else
1512 RT_NOREF(pVCpu, uMsr);
1513#endif
1514 return false;
1515}
1516
1517
1518/**
1519 * Loads a set of guests MSRs to allow read/passthru to the guest.
1520 *
1521 * The name of this function is slightly confusing. This function does NOT
1522 * postpone loading, but loads the MSR right now. "hmR0VmxLazy" is simply a
1523 * common prefix for functions dealing with "lazy restoration" of the shared
1524 * MSRs.
1525 *
1526 * @param pVCpu The cross context virtual CPU structure.
1527 *
1528 * @remarks No-long-jump zone!!!
1529 */
1530static void hmR0VmxLazyLoadGuestMsrs(PVMCPU pVCpu)
1531{
1532 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1533 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1534
1535 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1536#if HC_ARCH_BITS == 64
1537 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1538 {
1539 /*
1540 * If the guest MSRs are not loaded -and- if all the guest MSRs are identical
1541 * to the MSRs on the CPU (which are the saved host MSRs, see assertion above) then
1542 * we can skip a few MSR writes.
1543 *
1544 * Otherwise, it implies either 1. they're not loaded, or 2. they're loaded but the
1545 * guest MSR values in the guest-CPU context might be different to what's currently
1546 * loaded in the CPU. In either case, we need to write the new guest MSR values to the
1547 * CPU, see @bugref{8728}.
1548 */
1549 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1550 if ( !(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1551 && pCtx->msrKERNELGSBASE == pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr
1552 && pCtx->msrLSTAR == pVCpu->hm.s.vmx.u64HostLStarMsr
1553 && pCtx->msrSTAR == pVCpu->hm.s.vmx.u64HostStarMsr
1554 && pCtx->msrSFMASK == pVCpu->hm.s.vmx.u64HostSFMaskMsr)
1555 {
1556#ifdef VBOX_STRICT
1557 Assert(ASMRdMsr(MSR_K8_KERNEL_GS_BASE) == pCtx->msrKERNELGSBASE);
1558 Assert(ASMRdMsr(MSR_K8_LSTAR) == pCtx->msrLSTAR);
1559 Assert(ASMRdMsr(MSR_K6_STAR) == pCtx->msrSTAR);
1560 Assert(ASMRdMsr(MSR_K8_SF_MASK) == pCtx->msrSFMASK);
1561#endif
1562 }
1563 else
1564 {
1565 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1566 ASMWrMsr(MSR_K8_LSTAR, pCtx->msrLSTAR);
1567 ASMWrMsr(MSR_K6_STAR, pCtx->msrSTAR);
1568 ASMWrMsr(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1569 }
1570 }
1571#endif
1572 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_LOADED_GUEST;
1573}
1574
1575
1576/**
1577 * Performs lazy restoration of the set of host MSRs if they were previously
1578 * loaded with guest MSR values.
1579 *
1580 * @param pVCpu The cross context virtual CPU structure.
1581 *
1582 * @remarks No-long-jump zone!!!
1583 * @remarks The guest MSRs should have been saved back into the guest-CPU
1584 * context by hmR0VmxImportGuestState()!!!
1585 */
1586static void hmR0VmxLazyRestoreHostMsrs(PVMCPU pVCpu)
1587{
1588 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1589 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1590
1591 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1592 {
1593 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1594#if HC_ARCH_BITS == 64
1595 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1596 {
1597 ASMWrMsr(MSR_K8_LSTAR, pVCpu->hm.s.vmx.u64HostLStarMsr);
1598 ASMWrMsr(MSR_K6_STAR, pVCpu->hm.s.vmx.u64HostStarMsr);
1599 ASMWrMsr(MSR_K8_SF_MASK, pVCpu->hm.s.vmx.u64HostSFMaskMsr);
1600 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr);
1601 }
1602#endif
1603 }
1604 pVCpu->hm.s.vmx.fLazyMsrs &= ~(VMX_LAZY_MSRS_LOADED_GUEST | VMX_LAZY_MSRS_SAVED_HOST);
1605}
1606
1607
1608/**
1609 * Verifies that our cached values of the VMCS fields are all consistent with
1610 * what's actually present in the VMCS.
1611 *
1612 * @returns VBox status code.
1613 * @retval VINF_SUCCESS if all our caches match their respective VMCS fields.
1614 * @retval VERR_VMX_VMCS_FIELD_CACHE_INVALID if a cache field doesn't match the
1615 * VMCS content. HMCPU error-field is
1616 * updated, see VMX_VCI_XXX.
1617 * @param pVCpu The cross context virtual CPU structure.
1618 */
1619static int hmR0VmxCheckVmcsCtls(PVMCPU pVCpu)
1620{
1621 uint32_t u32Val;
1622 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
1623 AssertRCReturn(rc, rc);
1624 AssertMsgReturnStmt(pVCpu->hm.s.vmx.Ctls.u32EntryCtls == u32Val,
1625 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.Ctls.u32EntryCtls, u32Val),
1626 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_ENTRY,
1627 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1628
1629 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);
1630 AssertRCReturn(rc, rc);
1631 AssertMsgReturnStmt(pVCpu->hm.s.vmx.Ctls.u32ExitCtls == u32Val,
1632 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.Ctls.u32ExitCtls, u32Val),
1633 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_EXIT,
1634 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1635
1636 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);
1637 AssertRCReturn(rc, rc);
1638 AssertMsgReturnStmt(pVCpu->hm.s.vmx.Ctls.u32PinCtls == u32Val,
1639 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.Ctls.u32PinCtls, u32Val),
1640 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PIN_EXEC,
1641 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1642
1643 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
1644 AssertRCReturn(rc, rc);
1645 AssertMsgReturnStmt(pVCpu->hm.s.vmx.Ctls.u32ProcCtls == u32Val,
1646 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.Ctls.u32ProcCtls, u32Val),
1647 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC,
1648 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1649
1650 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1651 {
1652 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
1653 AssertRCReturn(rc, rc);
1654 AssertMsgReturnStmt(pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 == u32Val,
1655 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.Ctls.u32ProcCtls2, u32Val),
1656 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC2,
1657 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1658 }
1659
1660 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val);
1661 AssertRCReturn(rc, rc);
1662 AssertMsgReturnStmt(pVCpu->hm.s.vmx.Ctls.u32XcptBitmap == u32Val,
1663 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.Ctls.u32XcptBitmap, u32Val),
1664 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_XCPT_BITMAP,
1665 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1666
1667 uint64_t u64Val;
1668 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, &u64Val);
1669 AssertRCReturn(rc, rc);
1670 AssertMsgReturnStmt(pVCpu->hm.s.vmx.Ctls.u64TscOffset == u64Val,
1671 ("Cache=%#RX64 VMCS=%#RX64\n", pVCpu->hm.s.vmx.Ctls.u64TscOffset, u64Val),
1672 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_TSC_OFFSET,
1673 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1674
1675 return VINF_SUCCESS;
1676}
1677
1678
1679#ifdef VBOX_STRICT
1680/**
1681 * Verifies that our cached host EFER value has not changed
1682 * since we cached it.
1683 *
1684 * @param pVCpu The cross context virtual CPU structure.
1685 */
1686static void hmR0VmxCheckHostEferMsr(PVMCPU pVCpu)
1687{
1688 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1689
1690 if (pVCpu->hm.s.vmx.Ctls.u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1691 {
1692 uint64_t u64Val;
1693 int rc = VMXReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &u64Val);
1694 AssertRC(rc);
1695
1696 uint64_t u64HostEferMsr = ASMRdMsr(MSR_K6_EFER);
1697 AssertMsgReturnVoid(u64HostEferMsr == u64Val, ("u64HostEferMsr=%#RX64 u64Val=%#RX64\n", u64HostEferMsr, u64Val));
1698 }
1699}
1700
1701
1702/**
1703 * Verifies whether the guest/host MSR pairs in the auto-load/store area in the
1704 * VMCS are correct.
1705 *
1706 * @param pVCpu The cross context virtual CPU structure.
1707 */
1708static void hmR0VmxCheckAutoLoadStoreMsrs(PVMCPU pVCpu)
1709{
1710 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1711
1712 /* Verify MSR counts in the VMCS are what we think it should be. */
1713 uint32_t cMsrs;
1714 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1715 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1716
1717 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cMsrs); AssertRC(rc);
1718 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1719
1720 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1721 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1722
1723 PCVMXAUTOMSR pHostMsr = (PCVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1724 PCVMXAUTOMSR pGuestMsr = (PCVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1725 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1726 {
1727 /* Verify that the MSRs are paired properly and that the host MSR has the correct value. */
1728 AssertMsgReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr, ("HostMsr=%#RX32 GuestMsr=%#RX32 cMsrs=%u\n", pHostMsr->u32Msr,
1729 pGuestMsr->u32Msr, cMsrs));
1730
1731 uint64_t u64Msr = ASMRdMsr(pHostMsr->u32Msr);
1732 AssertMsgReturnVoid(pHostMsr->u64Value == u64Msr, ("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
1733 pHostMsr->u32Msr, pHostMsr->u64Value, u64Msr, cMsrs));
1734
1735 /* Verify that the permissions are as expected in the MSR bitmap. */
1736 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1737 {
1738 VMXMSREXITREAD enmRead;
1739 VMXMSREXITWRITE enmWrite;
1740 rc = HMGetVmxMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, pGuestMsr->u32Msr, &enmRead, &enmWrite);
1741 AssertMsgReturnVoid(rc == VINF_SUCCESS, ("HMGetVmxMsrPermission! failed. rc=%Rrc\n", rc));
1742 if (pGuestMsr->u32Msr == MSR_K6_EFER)
1743 {
1744 AssertMsgReturnVoid(enmRead == VMXMSREXIT_INTERCEPT_READ, ("Passthru read for EFER!?\n"));
1745 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_INTERCEPT_WRITE, ("Passthru write for EFER!?\n"));
1746 }
1747 else
1748 {
1749 AssertMsgReturnVoid(enmRead == VMXMSREXIT_PASSTHRU_READ, ("u32Msr=%#RX32 cMsrs=%u No passthru read!\n",
1750 pGuestMsr->u32Msr, cMsrs));
1751 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_PASSTHRU_WRITE, ("u32Msr=%#RX32 cMsrs=%u No passthru write!\n",
1752 pGuestMsr->u32Msr, cMsrs));
1753 }
1754 }
1755 }
1756}
1757#endif /* VBOX_STRICT */
1758
1759
1760/**
1761 * Flushes the TLB using EPT.
1762 *
1763 * @returns VBox status code.
1764 * @param pVCpu The cross context virtual CPU structure of the calling
1765 * EMT. Can be NULL depending on @a enmTlbFlush.
1766 * @param enmTlbFlush Type of flush.
1767 *
1768 * @remarks Caller is responsible for making sure this function is called only
1769 * when NestedPaging is supported and providing @a enmTlbFlush that is
1770 * supported by the CPU.
1771 * @remarks Can be called with interrupts disabled.
1772 */
1773static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXTLBFLUSHEPT enmTlbFlush)
1774{
1775 uint64_t au64Descriptor[2];
1776 if (enmTlbFlush == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1777 au64Descriptor[0] = 0;
1778 else
1779 {
1780 Assert(pVCpu);
1781 au64Descriptor[0] = pVCpu->hm.s.vmx.HCPhysEPTP;
1782 }
1783 au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
1784
1785 int rc = VMXR0InvEPT(enmTlbFlush, &au64Descriptor[0]);
1786 AssertMsg(rc == VINF_SUCCESS,
1787 ("VMXR0InvEPT %#x %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hm.s.vmx.HCPhysEPTP : 0, rc));
1788
1789 if ( RT_SUCCESS(rc)
1790 && pVCpu)
1791 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
1792}
1793
1794
1795/**
1796 * Flushes the TLB using VPID.
1797 *
1798 * @returns VBox status code.
1799 * @param pVCpu The cross context virtual CPU structure of the calling
1800 * EMT. Can be NULL depending on @a enmTlbFlush.
1801 * @param enmTlbFlush Type of flush.
1802 * @param GCPtr Virtual address of the page to flush (can be 0 depending
1803 * on @a enmTlbFlush).
1804 *
1805 * @remarks Can be called with interrupts disabled.
1806 */
1807static void hmR0VmxFlushVpid(PVMCPU pVCpu, VMXTLBFLUSHVPID enmTlbFlush, RTGCPTR GCPtr)
1808{
1809 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid);
1810
1811 uint64_t au64Descriptor[2];
1812 if (enmTlbFlush == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1813 {
1814 au64Descriptor[0] = 0;
1815 au64Descriptor[1] = 0;
1816 }
1817 else
1818 {
1819 AssertPtr(pVCpu);
1820 AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1821 AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1822 au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
1823 au64Descriptor[1] = GCPtr;
1824 }
1825
1826 int rc = VMXR0InvVPID(enmTlbFlush, &au64Descriptor[0]);
1827 AssertMsg(rc == VINF_SUCCESS,
1828 ("VMXR0InvVPID %#x %u %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
1829
1830 if ( RT_SUCCESS(rc)
1831 && pVCpu)
1832 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1833 NOREF(rc);
1834}
1835
1836
1837/**
1838 * Invalidates a guest page by guest virtual address. Only relevant for
1839 * EPT/VPID, otherwise there is nothing really to invalidate.
1840 *
1841 * @returns VBox status code.
1842 * @param pVCpu The cross context virtual CPU structure.
1843 * @param GCVirt Guest virtual address of the page to invalidate.
1844 */
1845VMMR0DECL(int) VMXR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1846{
1847 AssertPtr(pVCpu);
1848 LogFlowFunc(("pVCpu=%p GCVirt=%RGv\n", pVCpu, GCVirt));
1849
1850 bool fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1851 if (!fFlushPending)
1852 {
1853 /*
1854 * We must invalidate the guest TLB entry in either case, we cannot ignore it even for
1855 * the EPT case. See @bugref{6043} and @bugref{6177}.
1856 *
1857 * Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*()
1858 * as this function maybe called in a loop with individual addresses.
1859 */
1860 PVM pVM = pVCpu->CTX_SUFF(pVM);
1861 if (pVM->hm.s.vmx.fVpid)
1862 {
1863 bool fVpidFlush = RT_BOOL(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1864
1865#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1866 /*
1867 * Workaround Erratum BV75, AAJ159 and others that affect several Intel CPUs
1868 * where executing INVVPID outside 64-bit mode does not flush translations of
1869 * 64-bit linear addresses, see @bugref{6208#c72}.
1870 */
1871 if (RT_HI_U32(GCVirt))
1872 fVpidFlush = false;
1873#endif
1874
1875 if (fVpidFlush)
1876 {
1877 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_INDIV_ADDR, GCVirt);
1878 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1879 }
1880 else
1881 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1882 }
1883 else if (pVM->hm.s.fNestedPaging)
1884 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1885 }
1886
1887 return VINF_SUCCESS;
1888}
1889
1890
1891/**
1892 * Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
1893 * case where neither EPT nor VPID is supported by the CPU.
1894 *
1895 * @param pHostCpu The HM physical-CPU structure.
1896 * @param pVCpu The cross context virtual CPU structure.
1897 *
1898 * @remarks Called with interrupts disabled.
1899 */
1900static void hmR0VmxFlushTaggedTlbNone(PHMPHYSCPU pHostCpu, PVMCPU pVCpu)
1901{
1902 AssertPtr(pVCpu);
1903 AssertPtr(pHostCpu);
1904
1905 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1906
1907 Assert(pHostCpu->idCpu != NIL_RTCPUID);
1908 pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1909 pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1910 pVCpu->hm.s.fForceTLBFlush = false;
1911 return;
1912}
1913
1914
1915/**
1916 * Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
1917 *
1918 * @param pHostCpu The HM physical-CPU structure.
1919 * @param pVCpu The cross context virtual CPU structure.
1920 *
1921 * @remarks All references to "ASID" in this function pertains to "VPID" in Intel's
1922 * nomenclature. The reason is, to avoid confusion in compare statements
1923 * since the host-CPU copies are named "ASID".
1924 *
1925 * @remarks Called with interrupts disabled.
1926 */
1927static void hmR0VmxFlushTaggedTlbBoth(PHMPHYSCPU pHostCpu, PVMCPU pVCpu)
1928{
1929#ifdef VBOX_WITH_STATISTICS
1930 bool fTlbFlushed = false;
1931# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
1932# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
1933 if (!fTlbFlushed) \
1934 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
1935 } while (0)
1936#else
1937# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
1938# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
1939#endif
1940
1941 AssertPtr(pVCpu);
1942 AssertPtr(pHostCpu);
1943 Assert(pHostCpu->idCpu != NIL_RTCPUID);
1944
1945 PVM pVM = pVCpu->CTX_SUFF(pVM);
1946 AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
1947 ("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
1948 "fNestedPaging=%RTbool fVpid=%RTbool", pVM->hm.s.fNestedPaging, pVM->hm.s.vmx.fVpid));
1949
1950 /*
1951 * Force a TLB flush for the first world-switch if the current CPU differs from the one we
1952 * ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
1953 * limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
1954 * cannot reuse the current ASID anymore.
1955 */
1956 if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1957 || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
1958 {
1959 ++pHostCpu->uCurrentAsid;
1960 if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1961 {
1962 pHostCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
1963 pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1964 pHostCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1965 }
1966
1967 pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1968 pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1969 pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1970
1971 /*
1972 * Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
1973 * invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
1974 */
1975 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmTlbFlushEpt);
1976 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1977 HMVMX_SET_TAGGED_TLB_FLUSHED();
1978 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1979 }
1980 else if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH)) /* Check for explicit TLB flushes. */
1981 {
1982 /*
1983 * Changes to the EPT paging structure by VMM requires flushing-by-EPT as the CPU
1984 * creates guest-physical (ie. only EPT-tagged) mappings while traversing the EPT
1985 * tables when EPT is in use. Flushing-by-VPID will only flush linear (only
1986 * VPID-tagged) and combined (EPT+VPID tagged) mappings but not guest-physical
1987 * mappings, see @bugref{6568}.
1988 *
1989 * See Intel spec. 28.3.2 "Creating and Using Cached Translation Information".
1990 */
1991 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmTlbFlushEpt);
1992 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1993 HMVMX_SET_TAGGED_TLB_FLUSHED();
1994 }
1995
1996 pVCpu->hm.s.fForceTLBFlush = false;
1997 HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
1998
1999 Assert(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu);
2000 Assert(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes);
2001 AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
2002 ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
2003 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2004 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
2005 pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2006 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2007 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2008
2009 /* Update VMCS with the VPID. */
2010 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2011 AssertRC(rc);
2012
2013#undef HMVMX_SET_TAGGED_TLB_FLUSHED
2014}
2015
2016
2017/**
2018 * Flushes the tagged-TLB entries for EPT CPUs as necessary.
2019 *
2020 * @param pHostCpu The HM physical-CPU structure.
2021 * @param pVCpu The cross context virtual CPU structure.
2022 *
2023 * @remarks Called with interrupts disabled.
2024 */
2025static void hmR0VmxFlushTaggedTlbEpt(PHMPHYSCPU pHostCpu, PVMCPU pVCpu)
2026{
2027 AssertPtr(pVCpu);
2028 AssertPtr(pHostCpu);
2029 Assert(pHostCpu->idCpu != NIL_RTCPUID);
2030 AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked without NestedPaging."));
2031 AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID."));
2032
2033 /*
2034 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
2035 * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
2036 */
2037 if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
2038 || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
2039 {
2040 pVCpu->hm.s.fForceTLBFlush = true;
2041 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2042 }
2043
2044 /* Check for explicit TLB flushes. */
2045 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2046 {
2047 pVCpu->hm.s.fForceTLBFlush = true;
2048 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2049 }
2050
2051 pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
2052 pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
2053
2054 if (pVCpu->hm.s.fForceTLBFlush)
2055 {
2056 hmR0VmxFlushEpt(pVCpu, pVCpu->CTX_SUFF(pVM)->hm.s.vmx.enmTlbFlushEpt);
2057 pVCpu->hm.s.fForceTLBFlush = false;
2058 }
2059}
2060
2061
2062/**
2063 * Flushes the tagged-TLB entries for VPID CPUs as necessary.
2064 *
2065 * @param pHostCpu The HM physical-CPU structure.
2066 * @param pVCpu The cross context virtual CPU structure.
2067 *
2068 * @remarks Called with interrupts disabled.
2069 */
2070static void hmR0VmxFlushTaggedTlbVpid(PHMPHYSCPU pHostCpu, PVMCPU pVCpu)
2071{
2072 AssertPtr(pVCpu);
2073 AssertPtr(pHostCpu);
2074 Assert(pHostCpu->idCpu != NIL_RTCPUID);
2075 AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked without VPID."));
2076 AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging"));
2077
2078 /*
2079 * Force a TLB flush for the first world switch if the current CPU differs from the one we
2080 * ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
2081 * limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
2082 * cannot reuse the current ASID anymore.
2083 */
2084 if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
2085 || pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes)
2086 {
2087 pVCpu->hm.s.fForceTLBFlush = true;
2088 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2089 }
2090
2091 /* Check for explicit TLB flushes. */
2092 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2093 {
2094 /*
2095 * If we ever support VPID flush combinations other than ALL or SINGLE-context (see
2096 * hmR0VmxSetupTaggedTlb()) we would need to explicitly flush in this case (add an
2097 * fExplicitFlush = true here and change the pHostCpu->fFlushAsidBeforeUse check below to
2098 * include fExplicitFlush's too) - an obscure corner case.
2099 */
2100 pVCpu->hm.s.fForceTLBFlush = true;
2101 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2102 }
2103
2104 PVM pVM = pVCpu->CTX_SUFF(pVM);
2105 pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
2106 if (pVCpu->hm.s.fForceTLBFlush)
2107 {
2108 ++pHostCpu->uCurrentAsid;
2109 if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
2110 {
2111 pHostCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
2112 pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
2113 pHostCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
2114 }
2115
2116 pVCpu->hm.s.fForceTLBFlush = false;
2117 pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
2118 pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
2119 if (pHostCpu->fFlushAsidBeforeUse)
2120 {
2121 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
2122 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
2123 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
2124 {
2125 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
2126 pHostCpu->fFlushAsidBeforeUse = false;
2127 }
2128 else
2129 {
2130 /* hmR0VmxSetupTaggedTlb() ensures we never get here. Paranoia. */
2131 AssertMsgFailed(("Unsupported VPID-flush context type.\n"));
2132 }
2133 }
2134 }
2135
2136 AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
2137 ("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
2138 AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2139 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
2140 pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2141 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2142 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2143
2144 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2145 AssertRC(rc);
2146}
2147
2148
2149/**
2150 * Flushes the guest TLB entry based on CPU capabilities.
2151 *
2152 * @param pHostCpu The HM physical-CPU structure.
2153 * @param pVCpu The cross context virtual CPU structure.
2154 *
2155 * @remarks Called with interrupts disabled.
2156 */
2157DECLINLINE(void) hmR0VmxFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPU pVCpu)
2158{
2159#ifdef HMVMX_ALWAYS_FLUSH_TLB
2160 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2161#endif
2162 PVM pVM = pVCpu->CTX_SUFF(pVM);
2163 switch (pVM->hm.s.vmx.enmTlbFlushType)
2164 {
2165 case VMXTLBFLUSHTYPE_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pHostCpu, pVCpu); break;
2166 case VMXTLBFLUSHTYPE_EPT: hmR0VmxFlushTaggedTlbEpt(pHostCpu, pVCpu); break;
2167 case VMXTLBFLUSHTYPE_VPID: hmR0VmxFlushTaggedTlbVpid(pHostCpu, pVCpu); break;
2168 case VMXTLBFLUSHTYPE_NONE: hmR0VmxFlushTaggedTlbNone(pHostCpu, pVCpu); break;
2169 default:
2170 AssertMsgFailed(("Invalid flush-tag function identifier\n"));
2171 break;
2172 }
2173 /* Don't assert that VMCPU_FF_TLB_FLUSH should no longer be pending. It can be set by other EMTs. */
2174}
2175
2176
2177/**
2178 * Sets up the appropriate tagged TLB-flush level and handler for flushing guest
2179 * TLB entries from the host TLB before VM-entry.
2180 *
2181 * @returns VBox status code.
2182 * @param pVM The cross context VM structure.
2183 */
2184static int hmR0VmxSetupTaggedTlb(PVM pVM)
2185{
2186 /*
2187 * Determine optimal flush type for Nested Paging.
2188 * We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup unrestricted
2189 * guest execution (see hmR3InitFinalizeR0()).
2190 */
2191 if (pVM->hm.s.fNestedPaging)
2192 {
2193 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
2194 {
2195 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
2196 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_SINGLE_CONTEXT;
2197 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
2198 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_ALL_CONTEXTS;
2199 else
2200 {
2201 /* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
2202 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2203 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED;
2204 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2205 }
2206
2207 /* Make sure the write-back cacheable memory type for EPT is supported. */
2208 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
2209 {
2210 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2211 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_MEM_TYPE_NOT_WB;
2212 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2213 }
2214
2215 /* EPT requires a page-walk length of 4. */
2216 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
2217 {
2218 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2219 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED;
2220 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2221 }
2222 }
2223 else
2224 {
2225 /* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
2226 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2227 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_INVEPT_UNAVAILABLE;
2228 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2229 }
2230 }
2231
2232 /*
2233 * Determine optimal flush type for VPID.
2234 */
2235 if (pVM->hm.s.vmx.fVpid)
2236 {
2237 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
2238 {
2239 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
2240 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_SINGLE_CONTEXT;
2241 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
2242 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_ALL_CONTEXTS;
2243 else
2244 {
2245 /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
2246 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
2247 LogRelFunc(("Only INDIV_ADDR supported. Ignoring VPID.\n"));
2248 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
2249 LogRelFunc(("Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
2250 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
2251 pVM->hm.s.vmx.fVpid = false;
2252 }
2253 }
2254 else
2255 {
2256 /* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
2257 Log4Func(("VPID supported without INVEPT support. Ignoring VPID.\n"));
2258 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
2259 pVM->hm.s.vmx.fVpid = false;
2260 }
2261 }
2262
2263 /*
2264 * Setup the handler for flushing tagged-TLBs.
2265 */
2266 if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
2267 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT_VPID;
2268 else if (pVM->hm.s.fNestedPaging)
2269 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT;
2270 else if (pVM->hm.s.vmx.fVpid)
2271 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_VPID;
2272 else
2273 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_NONE;
2274 return VINF_SUCCESS;
2275}
2276
2277
2278/**
2279 * Sets up pin-based VM-execution controls in the VMCS.
2280 *
2281 * @returns VBox status code.
2282 * @param pVCpu The cross context virtual CPU structure.
2283 *
2284 * @remarks We don't really care about optimizing vmwrites here as it's done only
2285 * once per VM and hence we don't care about VMCS-field cache comparisons.
2286 */
2287static int hmR0VmxSetupPinCtls(PVMCPU pVCpu)
2288{
2289 PVM pVM = pVCpu->CTX_SUFF(pVM);
2290 uint32_t fVal = pVM->hm.s.vmx.Msrs.PinCtls.n.allowed0; /* Bits set here must always be set. */
2291 uint32_t const fZap = pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
2292
2293 fVal |= VMX_PIN_CTLS_EXT_INT_EXIT /* External interrupts cause a VM-exit. */
2294 | VMX_PIN_CTLS_NMI_EXIT; /* Non-maskable interrupts (NMIs) cause a VM-exit. */
2295
2296 if (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
2297 fVal |= VMX_PIN_CTLS_VIRT_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
2298
2299 /* Enable the VMX preemption timer. */
2300 if (pVM->hm.s.vmx.fUsePreemptTimer)
2301 {
2302 Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
2303 fVal |= VMX_PIN_CTLS_PREEMPT_TIMER;
2304 }
2305
2306#if 0
2307 /* Enable posted-interrupt processing. */
2308 if (pVM->hm.s.fPostedIntrs)
2309 {
2310 Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT);
2311 Assert(pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
2312 fVal |= VMX_PIN_CTL_POSTED_INT;
2313 }
2314#endif
2315
2316 if ((fVal & fZap) != fVal)
2317 {
2318 LogRelFunc(("Invalid pin-based VM-execution controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
2319 pVM->hm.s.vmx.Msrs.PinCtls.n.allowed0, fVal, fZap));
2320 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
2321 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2322 }
2323
2324 /* Commit it to the VMCS and update our cache. */
2325 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, fVal);
2326 AssertRCReturn(rc, rc);
2327 pVCpu->hm.s.vmx.Ctls.u32PinCtls = fVal;
2328
2329 return VINF_SUCCESS;
2330}
2331
2332
2333/**
2334 * Sets up secondary processor-based VM-execution controls in the VMCS.
2335 *
2336 * @returns VBox status code.
2337 * @param pVCpu The cross context virtual CPU structure.
2338 *
2339 * @remarks We don't really care about optimizing vmwrites here as it's done only
2340 * once per VM and hence we don't care about VMCS-field cache comparisons.
2341 */
2342static int hmR0VmxSetupProcCtls2(PVMCPU pVCpu)
2343{
2344 PVM pVM = pVCpu->CTX_SUFF(pVM);
2345 uint32_t fVal = pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed0; /* Bits set here must be set in the VMCS. */
2346 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2347
2348 /* WBINVD causes a VM-exit. */
2349 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
2350 fVal |= VMX_PROC_CTLS2_WBINVD_EXIT;
2351
2352 /* Enable EPT (aka nested-paging). */
2353 if (pVM->hm.s.fNestedPaging)
2354 fVal |= VMX_PROC_CTLS2_EPT;
2355
2356 /*
2357 * Enable the INVPCID instruction if supported by the hardware and we expose
2358 * it to the guest. Without this, guest executing INVPCID would cause a #UD.
2359 */
2360 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID)
2361 && pVM->cpum.ro.GuestFeatures.fInvpcid)
2362 fVal |= VMX_PROC_CTLS2_INVPCID;
2363
2364 /* Enable VPID. */
2365 if (pVM->hm.s.vmx.fVpid)
2366 fVal |= VMX_PROC_CTLS2_VPID;
2367
2368 /* Enable Unrestricted guest execution. */
2369 if (pVM->hm.s.vmx.fUnrestrictedGuest)
2370 fVal |= VMX_PROC_CTLS2_UNRESTRICTED_GUEST;
2371
2372#if 0
2373 if (pVM->hm.s.fVirtApicRegs)
2374 {
2375 /* Enable APIC-register virtualization. */
2376 Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
2377 fVal |= VMX_PROC_CTLS2_APIC_REG_VIRT;
2378
2379 /* Enable virtual-interrupt delivery. */
2380 Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
2381 fVal |= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
2382 }
2383#endif
2384
2385 /* Virtualize-APIC accesses if supported by the CPU. The virtual-APIC page is where the TPR shadow resides. */
2386 /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
2387 * done dynamically. */
2388 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
2389 {
2390 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
2391 Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
2392 fVal |= VMX_PROC_CTLS2_VIRT_APIC_ACCESS; /* Virtualize APIC accesses. */
2393 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
2394 AssertRCReturn(rc, rc);
2395 }
2396
2397 /* Enable RDTSCP. */
2398 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP)
2399 fVal |= VMX_PROC_CTLS2_RDTSCP;
2400
2401 /* Enable Pause-Loop exiting. */
2402 if ( pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT
2403 && pVM->hm.s.vmx.cPleGapTicks
2404 && pVM->hm.s.vmx.cPleWindowTicks)
2405 {
2406 fVal |= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT;
2407
2408 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks);
2409 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks);
2410 AssertRCReturn(rc, rc);
2411 }
2412
2413 if ((fVal & fZap) != fVal)
2414 {
2415 LogRelFunc(("Invalid secondary processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
2416 pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed0, fVal, fZap));
2417 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
2418 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2419 }
2420
2421 /* Commit it to the VMCS and update our cache. */
2422 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, fVal);
2423 AssertRCReturn(rc, rc);
2424 pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 = fVal;
2425
2426 return VINF_SUCCESS;
2427}
2428
2429
2430/**
2431 * Sets up processor-based VM-execution controls in the VMCS.
2432 *
2433 * @returns VBox status code.
2434 * @param pVCpu The cross context virtual CPU structure.
2435 *
2436 * @remarks We don't really care about optimizing vmwrites here as it's done only
2437 * once per VM and hence we don't care about VMCS-field cache comparisons.
2438 */
2439static int hmR0VmxSetupProcCtls(PVMCPU pVCpu)
2440{
2441 PVM pVM = pVCpu->CTX_SUFF(pVM);
2442 uint32_t fVal = pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
2443 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2444
2445 fVal |= VMX_PROC_CTLS_HLT_EXIT /* HLT causes a VM-exit. */
2446 | VMX_PROC_CTLS_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2447 | VMX_PROC_CTLS_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2448 | VMX_PROC_CTLS_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2449 | VMX_PROC_CTLS_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2450 | VMX_PROC_CTLS_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2451 | VMX_PROC_CTLS_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2452
2453 /* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2454 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
2455 || (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
2456 {
2457 LogRelFunc(("Unsupported VMX_PROC_CTLS_MOV_DR_EXIT combo!"));
2458 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2459 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2460 }
2461
2462 /* Without Nested Paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
2463 if (!pVM->hm.s.fNestedPaging)
2464 {
2465 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest); /* Paranoia. */
2466 fVal |= VMX_PROC_CTLS_INVLPG_EXIT
2467 | VMX_PROC_CTLS_CR3_LOAD_EXIT
2468 | VMX_PROC_CTLS_CR3_STORE_EXIT;
2469 }
2470
2471 /* Use TPR shadowing if supported by the CPU. */
2472 if ( PDMHasApic(pVM)
2473 && pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW)
2474 {
2475 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
2476 Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
2477 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
2478 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
2479 AssertRCReturn(rc, rc);
2480
2481 fVal |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2482 /* CR8 writes cause a VM-exit based on TPR threshold. */
2483 Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
2484 Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
2485 }
2486 else
2487 {
2488 /*
2489 * Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is invalid on 32-bit Intel CPUs.
2490 * Set this control only for 64-bit guests.
2491 */
2492 if (pVM->hm.s.fAllow64BitGuests)
2493 {
2494 fVal |= VMX_PROC_CTLS_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2495 | VMX_PROC_CTLS_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2496 }
2497 }
2498
2499 /* Use MSR-bitmaps if supported by the CPU. */
2500 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
2501 {
2502 fVal |= VMX_PROC_CTLS_USE_MSR_BITMAPS;
2503
2504 Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2505 Assert(!(pVCpu->hm.s.vmx.HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
2506 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2507 AssertRCReturn(rc, rc);
2508
2509 /*
2510 * The guest can access the following MSRs (read, write) without causing VM-exits; they are loaded/stored
2511 * automatically using dedicated fields in the VMCS.
2512 */
2513 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2514 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2515 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2516 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2517 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_FS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2518#if HC_ARCH_BITS == 64
2519 /*
2520 * Set passthru permissions for the following MSRs (mandatory for VT-x) required for 64-bit guests.
2521 */
2522 if (pVM->hm.s.fAllow64BitGuests)
2523 {
2524 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_LSTAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2525 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_STAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2526 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_SF_MASK, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2527 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2528 }
2529#endif
2530 /*
2531 * The IA32_PRED_CMD and IA32_FLUSH_CMD MSRs are write-only and has no state
2532 * associated with then. We never need to intercept access (writes need to
2533 * be executed without exiting, reads will #GP-fault anyway).
2534 */
2535 if (pVM->cpum.ro.GuestFeatures.fIbpb)
2536 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_PRED_CMD, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2537 if (pVM->cpum.ro.GuestFeatures.fFlushCmd)
2538 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_FLUSH_CMD, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2539
2540 /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */
2541 }
2542
2543 /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2544 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2545 fVal |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
2546
2547 if ((fVal & fZap) != fVal)
2548 {
2549 LogRelFunc(("Invalid processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
2550 pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0, fVal, fZap));
2551 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2552 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2553 }
2554
2555 /* Commit it to the VMCS and update our cache. */
2556 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, fVal);
2557 AssertRCReturn(rc, rc);
2558 pVCpu->hm.s.vmx.Ctls.u32ProcCtls = fVal;
2559
2560 /* Set up secondary processor-based VM-execution controls if the CPU supports it. */
2561 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2562 return hmR0VmxSetupProcCtls2(pVCpu);
2563
2564 /* Sanity check, should not really happen. */
2565 if (RT_UNLIKELY(pVM->hm.s.vmx.fUnrestrictedGuest))
2566 {
2567 LogRelFunc(("Unrestricted Guest enabled when secondary processor-based VM-execution controls not available\n"));
2568 pVCpu->hm.s.u32HMError = VMX_UFC_INVALID_UX_COMBO;
2569 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2570 }
2571
2572 /* Old CPUs without secondary processor-based VM-execution controls would end up here. */
2573 return VINF_SUCCESS;
2574}
2575
2576
2577/**
2578 * Sets up miscellaneous (everything other than Pin & Processor-based
2579 * VM-execution) control fields in the VMCS.
2580 *
2581 * @returns VBox status code.
2582 * @param pVCpu The cross context virtual CPU structure.
2583 */
2584static int hmR0VmxSetupMiscCtls(PVMCPU pVCpu)
2585{
2586 AssertPtr(pVCpu);
2587
2588 int rc = VERR_GENERAL_FAILURE;
2589
2590 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2591#if 0
2592 /* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxExportGuestCR3AndCR4())*/
2593 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
2594 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
2595
2596 /*
2597 * Set MASK & MATCH to 0. VMX checks if GuestPFErrCode & MASK == MATCH. If equal (in our case it always is)
2598 * and if the X86_XCPT_PF bit in the exception bitmap is set it causes a VM-exit, if clear doesn't cause an exit.
2599 * We thus use the exception bitmap to control it rather than use both.
2600 */
2601 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
2602 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
2603
2604 /* All IO & IOIO instructions cause VM-exits. */
2605 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
2606 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
2607
2608 /* Initialize the MSR-bitmap area. */
2609 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
2610 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
2611 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
2612 AssertRCReturn(rc, rc);
2613#endif
2614
2615 /* Setup MSR auto-load/store area. */
2616 Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
2617 Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf)); /* Lower 4 bits MBZ. */
2618 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2619 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2620 AssertRCReturn(rc, rc);
2621
2622 Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
2623 Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf)); /* Lower 4 bits MBZ. */
2624 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
2625 AssertRCReturn(rc, rc);
2626
2627 /* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
2628 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
2629 AssertRCReturn(rc, rc);
2630
2631 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2632#if 0
2633 /* Setup debug controls */
2634 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0);
2635 rc |= VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0);
2636 AssertRCReturn(rc, rc);
2637#endif
2638
2639 return rc;
2640}
2641
2642
2643/**
2644 * Sets up the initial exception bitmap in the VMCS based on static conditions.
2645 *
2646 * We shall setup those exception intercepts that don't change during the
2647 * lifetime of the VM here. The rest are done dynamically while loading the
2648 * guest state.
2649 *
2650 * @returns VBox status code.
2651 * @param pVCpu The cross context virtual CPU structure.
2652 */
2653static int hmR0VmxInitXcptBitmap(PVMCPU pVCpu)
2654{
2655 AssertPtr(pVCpu);
2656
2657 uint32_t uXcptBitmap;
2658
2659 /* Must always intercept #AC to prevent the guest from hanging the CPU. */
2660 uXcptBitmap = RT_BIT_32(X86_XCPT_AC);
2661
2662 /* Because we need to maintain the DR6 state even when intercepting DRx reads
2663 and writes, and because recursive #DBs can cause the CPU hang, we must always
2664 intercept #DB. */
2665 uXcptBitmap |= RT_BIT_32(X86_XCPT_DB);
2666
2667 /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
2668 if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
2669 uXcptBitmap |= RT_BIT(X86_XCPT_PF);
2670
2671 /* Commit it to the VMCS. */
2672 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
2673 AssertRCReturn(rc, rc);
2674
2675 /* Update our cache of the exception bitmap. */
2676 pVCpu->hm.s.vmx.Ctls.u32XcptBitmap = uXcptBitmap;
2677 return VINF_SUCCESS;
2678}
2679
2680
2681/**
2682 * Does per-VM VT-x initialization.
2683 *
2684 * @returns VBox status code.
2685 * @param pVM The cross context VM structure.
2686 */
2687VMMR0DECL(int) VMXR0InitVM(PVM pVM)
2688{
2689 LogFlowFunc(("pVM=%p\n", pVM));
2690
2691 int rc = hmR0VmxStructsAlloc(pVM);
2692 if (RT_FAILURE(rc))
2693 {
2694 LogRelFunc(("hmR0VmxStructsAlloc failed! rc=%Rrc\n", rc));
2695 return rc;
2696 }
2697
2698 return VINF_SUCCESS;
2699}
2700
2701
2702/**
2703 * Does per-VM VT-x termination.
2704 *
2705 * @returns VBox status code.
2706 * @param pVM The cross context VM structure.
2707 */
2708VMMR0DECL(int) VMXR0TermVM(PVM pVM)
2709{
2710 LogFlowFunc(("pVM=%p\n", pVM));
2711
2712#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2713 if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
2714 ASMMemZero32(pVM->hm.s.vmx.pvScratch, PAGE_SIZE);
2715#endif
2716 hmR0VmxStructsFree(pVM);
2717 return VINF_SUCCESS;
2718}
2719
2720
2721/**
2722 * Sets up the VM for execution under VT-x.
2723 * This function is only called once per-VM during initialization.
2724 *
2725 * @returns VBox status code.
2726 * @param pVM The cross context VM structure.
2727 */
2728VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
2729{
2730 AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
2731 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2732
2733 LogFlowFunc(("pVM=%p\n", pVM));
2734
2735 /*
2736 * Without UnrestrictedGuest, pRealModeTSS and pNonPagingModeEPTPageTable *must* always be
2737 * allocated. We no longer support the highly unlikely case of UnrestrictedGuest without
2738 * pRealModeTSS, see hmR3InitFinalizeR0Intel().
2739 */
2740 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
2741 && ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
2742 || !pVM->hm.s.vmx.pRealModeTSS))
2743 {
2744 LogRelFunc(("Invalid real-on-v86 state.\n"));
2745 return VERR_INTERNAL_ERROR;
2746 }
2747
2748 /* Initialize these always, see hmR3InitFinalizeR0().*/
2749 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NONE;
2750 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NONE;
2751
2752 /* Setup the tagged-TLB flush handlers. */
2753 int rc = hmR0VmxSetupTaggedTlb(pVM);
2754 if (RT_FAILURE(rc))
2755 {
2756 LogRelFunc(("hmR0VmxSetupTaggedTlb failed! rc=%Rrc\n", rc));
2757 return rc;
2758 }
2759
2760 /* Check if we can use the VMCS controls for swapping the EFER MSR. */
2761 Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
2762#if HC_ARCH_BITS == 64
2763 if ( (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
2764 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2765 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
2766 {
2767 pVM->hm.s.vmx.fSupportsVmcsEfer = true;
2768 }
2769#endif
2770
2771 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
2772 RTCCUINTREG const uHostCR4 = ASMGetCR4();
2773 if (RT_UNLIKELY(!(uHostCR4 & X86_CR4_VMXE)))
2774 return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
2775
2776 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2777 {
2778 PVMCPU pVCpu = &pVM->aCpus[i];
2779 AssertPtr(pVCpu);
2780 AssertPtr(pVCpu->hm.s.vmx.pvVmcs);
2781
2782 /* Log the VCPU pointers, useful for debugging SMP VMs. */
2783 Log4Func(("pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
2784
2785 /* Set revision dword at the beginning of the VMCS structure. */
2786 *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
2787
2788 /* Set the VMCS launch state to "clear", see Intel spec. 31.6 "Preparation and launch a virtual machine". */
2789 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2790 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc\n", rc),
2791 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2792
2793 /* Load this VMCS as the current VMCS. */
2794 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2795 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc\n", rc),
2796 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2797
2798 rc = hmR0VmxSetupPinCtls(pVCpu);
2799 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc\n", rc),
2800 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2801
2802 rc = hmR0VmxSetupProcCtls(pVCpu);
2803 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc\n", rc),
2804 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2805
2806 rc = hmR0VmxSetupMiscCtls(pVCpu);
2807 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc\n", rc),
2808 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2809
2810 rc = hmR0VmxInitXcptBitmap(pVCpu);
2811 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc\n", rc),
2812 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2813
2814#if HC_ARCH_BITS == 32
2815 rc = hmR0VmxInitVmcsReadCache(pVCpu);
2816 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc\n", rc),
2817 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2818#endif
2819
2820 /* Sync any CPU internal VMCS data back into our VMCS in memory. */
2821 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2822 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc\n", rc),
2823 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2824
2825 pVCpu->hm.s.vmx.fVmcsState = HMVMX_VMCS_STATE_CLEAR;
2826
2827 hmR0VmxUpdateErrorRecord(pVCpu, rc);
2828 }
2829
2830 return VINF_SUCCESS;
2831}
2832
2833
2834/**
2835 * Saves the host control registers (CR0, CR3, CR4) into the host-state area in
2836 * the VMCS.
2837 *
2838 * @returns VBox status code.
2839 */
2840static int hmR0VmxExportHostControlRegs(void)
2841{
2842 RTCCUINTREG uReg = ASMGetCR0();
2843 int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
2844 AssertRCReturn(rc, rc);
2845
2846 uReg = ASMGetCR3();
2847 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
2848 AssertRCReturn(rc, rc);
2849
2850 uReg = ASMGetCR4();
2851 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
2852 AssertRCReturn(rc, rc);
2853 return rc;
2854}
2855
2856
2857/**
2858 * Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
2859 * the host-state area in the VMCS.
2860 *
2861 * @returns VBox status code.
2862 * @param pVCpu The cross context virtual CPU structure.
2863 */
2864static int hmR0VmxExportHostSegmentRegs(PVMCPU pVCpu)
2865{
2866#if HC_ARCH_BITS == 64
2867/**
2868 * Macro for adjusting host segment selectors to satisfy VT-x's VM-entry
2869 * requirements. See hmR0VmxExportHostSegmentRegs().
2870 */
2871# define VMXLOCAL_ADJUST_HOST_SEG(seg, selValue) \
2872 if ((selValue) & (X86_SEL_RPL | X86_SEL_LDT)) \
2873 { \
2874 bool fValidSelector = true; \
2875 if ((selValue) & X86_SEL_LDT) \
2876 { \
2877 uint32_t uAttr = ASMGetSegAttr((selValue)); \
2878 fValidSelector = RT_BOOL(uAttr != UINT32_MAX && (uAttr & X86_DESC_P)); \
2879 } \
2880 if (fValidSelector) \
2881 { \
2882 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_##seg; \
2883 pVCpu->hm.s.vmx.RestoreHost.uHostSel##seg = (selValue); \
2884 } \
2885 (selValue) = 0; \
2886 }
2887
2888 /*
2889 * If we've executed guest code using VT-x, the host-state bits will be messed up. We
2890 * should -not- save the messed up state without restoring the original host-state,
2891 * see @bugref{7240}.
2892 *
2893 * This apparently can happen (most likely the FPU changes), deal with it rather than
2894 * asserting. Was observed booting Solaris 10u10 32-bit guest.
2895 */
2896 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
2897 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
2898 {
2899 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags,
2900 pVCpu->idCpu));
2901 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
2902 }
2903 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
2904#else
2905 RT_NOREF(pVCpu);
2906#endif
2907
2908 /*
2909 * Host DS, ES, FS and GS segment registers.
2910 */
2911#if HC_ARCH_BITS == 64
2912 RTSEL uSelDS = ASMGetDS();
2913 RTSEL uSelES = ASMGetES();
2914 RTSEL uSelFS = ASMGetFS();
2915 RTSEL uSelGS = ASMGetGS();
2916#else
2917 RTSEL uSelDS = 0;
2918 RTSEL uSelES = 0;
2919 RTSEL uSelFS = 0;
2920 RTSEL uSelGS = 0;
2921#endif
2922
2923 /*
2924 * Host CS and SS segment registers.
2925 */
2926 RTSEL uSelCS = ASMGetCS();
2927 RTSEL uSelSS = ASMGetSS();
2928
2929 /*
2930 * Host TR segment register.
2931 */
2932 RTSEL uSelTR = ASMGetTR();
2933
2934#if HC_ARCH_BITS == 64
2935 /*
2936 * Determine if the host segment registers are suitable for VT-x. Otherwise use zero to
2937 * gain VM-entry and restore them before we get preempted.
2938 *
2939 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
2940 */
2941 VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
2942 VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
2943 VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
2944 VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
2945# undef VMXLOCAL_ADJUST_HOST_SEG
2946#endif
2947
2948 /* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
2949 Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
2950 Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
2951 Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
2952 Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
2953 Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
2954 Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
2955 Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
2956 Assert(uSelCS);
2957 Assert(uSelTR);
2958
2959 /* Assertion is right but we would not have updated u32ExitCtls yet. */
2960#if 0
2961 if (!(pVCpu->hm.s.vmx.Ctls.u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE))
2962 Assert(uSelSS != 0);
2963#endif
2964
2965 /* Write these host selector fields into the host-state area in the VMCS. */
2966 int rc = VMXWriteVmcs32(VMX_VMCS16_HOST_CS_SEL, uSelCS);
2967 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_SS_SEL, uSelSS);
2968#if HC_ARCH_BITS == 64
2969 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_DS_SEL, uSelDS);
2970 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_ES_SEL, uSelES);
2971 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FS_SEL, uSelFS);
2972 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_GS_SEL, uSelGS);
2973#else
2974 NOREF(uSelDS);
2975 NOREF(uSelES);
2976 NOREF(uSelFS);
2977 NOREF(uSelGS);
2978#endif
2979 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_TR_SEL, uSelTR);
2980 AssertRCReturn(rc, rc);
2981
2982 /*
2983 * Host GDTR and IDTR.
2984 */
2985 RTGDTR Gdtr;
2986 RTIDTR Idtr;
2987 RT_ZERO(Gdtr);
2988 RT_ZERO(Idtr);
2989 ASMGetGDTR(&Gdtr);
2990 ASMGetIDTR(&Idtr);
2991 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
2992 rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
2993 AssertRCReturn(rc, rc);
2994
2995#if HC_ARCH_BITS == 64
2996 /*
2997 * Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps
2998 * them to the maximum limit (0xffff) on every VM-exit.
2999 */
3000 if (Gdtr.cbGdt != 0xffff)
3001 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDTR;
3002
3003 /*
3004 * IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT" and
3005 * Intel spec. 6.2 "Exception and Interrupt Vectors".) Therefore if the host has the limit
3006 * as 0xfff, VT-x bloating the limit to 0xffff shouldn't cause any different CPU behavior.
3007 * However, several hosts either insists on 0xfff being the limit (Windows Patch Guard) or
3008 * uses the limit for other purposes (darwin puts the CPU ID in there but botches sidt
3009 * alignment in at least one consumer). So, we're only allowing the IDTR.LIMIT to be left
3010 * at 0xffff on hosts where we are sure it won't cause trouble.
3011 */
3012# if defined(RT_OS_LINUX) || defined(RT_OS_SOLARIS)
3013 if (Idtr.cbIdt < 0x0fff)
3014# else
3015 if (Idtr.cbIdt != 0xffff)
3016# endif
3017 {
3018 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_IDTR;
3019 AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
3020 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
3021 }
3022#endif
3023
3024 /*
3025 * Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI
3026 * and RPL bits is effectively what the CPU does for "scaling by 8". TI is always 0 and
3027 * RPL should be too in most cases.
3028 */
3029 AssertMsgReturn((uSelTR | X86_SEL_RPL_LDT) <= Gdtr.cbGdt,
3030 ("TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt), VERR_VMX_INVALID_HOST_STATE);
3031
3032 PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
3033#if HC_ARCH_BITS == 64
3034 uintptr_t uTRBase = X86DESC64_BASE(pDesc);
3035
3036 /*
3037 * VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on
3038 * all VM-exits. The type is the same for 64-bit busy TSS[1]. The limit needs manual
3039 * restoration if the host has something else. Task switching is not supported in 64-bit
3040 * mode[2], but the limit still matters as IOPM is supported in 64-bit mode. Restoring the
3041 * limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
3042 *
3043 * [1] See Intel spec. 3.5 "System Descriptor Types".
3044 * [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
3045 */
3046 PVM pVM = pVCpu->CTX_SUFF(pVM);
3047 Assert(pDesc->System.u4Type == 11);
3048 if ( pDesc->System.u16LimitLow != 0x67
3049 || pDesc->System.u4LimitHigh)
3050 {
3051 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_TR;
3052 /* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */
3053 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)
3054 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_READ_ONLY;
3055 pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
3056 }
3057
3058 /*
3059 * Store the GDTR as we need it when restoring the GDT and while restoring the TR.
3060 */
3061 if (pVCpu->hm.s.vmx.fRestoreHostFlags & (VMX_RESTORE_HOST_GDTR | VMX_RESTORE_HOST_SEL_TR))
3062 {
3063 AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
3064 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3065 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_NEED_WRITABLE)
3066 {
3067 /* The GDT is read-only but the writable GDT is available. */
3068 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_NEED_WRITABLE;
3069 pVCpu->hm.s.vmx.RestoreHost.HostGdtrRw.cb = Gdtr.cbGdt;
3070 rc = SUPR0GetCurrentGdtRw(&pVCpu->hm.s.vmx.RestoreHost.HostGdtrRw.uAddr);
3071 AssertRCReturn(rc, rc);
3072 }
3073 }
3074#else
3075 uintptr_t uTRBase = X86DESC_BASE(pDesc);
3076#endif
3077 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_TR_BASE, uTRBase);
3078 AssertRCReturn(rc, rc);
3079
3080 /*
3081 * Host FS base and GS base.
3082 */
3083#if HC_ARCH_BITS == 64
3084 uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
3085 uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
3086 rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
3087 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
3088 AssertRCReturn(rc, rc);
3089
3090 /* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
3091 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
3092 pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
3093 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
3094 pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
3095#endif
3096 return VINF_SUCCESS;
3097}
3098
3099
3100/**
3101 * Exports certain host MSRs in the VM-exit MSR-load area and some in the
3102 * host-state area of the VMCS.
3103 *
3104 * Theses MSRs will be automatically restored on the host after every successful
3105 * VM-exit.
3106 *
3107 * @returns VBox status code.
3108 * @param pVCpu The cross context virtual CPU structure.
3109 *
3110 * @remarks No-long-jump zone!!!
3111 */
3112static int hmR0VmxExportHostMsrs(PVMCPU pVCpu)
3113{
3114 AssertPtr(pVCpu);
3115 AssertPtr(pVCpu->hm.s.vmx.pvHostMsr);
3116
3117 /*
3118 * Save MSRs that we restore lazily (due to preemption or transition to ring-3)
3119 * rather than swapping them on every VM-entry.
3120 */
3121 hmR0VmxLazySaveHostMsrs(pVCpu);
3122
3123 /*
3124 * Host Sysenter MSRs.
3125 */
3126 int rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
3127#if HC_ARCH_BITS == 32
3128 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
3129 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
3130#else
3131 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
3132 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
3133#endif
3134 AssertRCReturn(rc, rc);
3135
3136 /*
3137 * Host EFER MSR.
3138 *
3139 * If the CPU supports the newer VMCS controls for managing EFER, use it. Otherwise it's
3140 * done as part of auto-load/store MSR area in the VMCS, see hmR0VmxExportGuestMsrs().
3141 */
3142 PVM pVM = pVCpu->CTX_SUFF(pVM);
3143 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
3144 {
3145 rc = VMXWriteVmcs64(VMX_VMCS64_HOST_EFER_FULL, pVM->hm.s.vmx.u64HostEfer);
3146 AssertRCReturn(rc, rc);
3147 }
3148
3149 /** @todo IA32_PERF_GLOBALCTRL, IA32_PAT also see hmR0VmxExportGuestExitCtls(). */
3150
3151 return VINF_SUCCESS;
3152}
3153
3154
3155/**
3156 * Figures out if we need to swap the EFER MSR which is particularly expensive.
3157 *
3158 * We check all relevant bits. For now, that's everything besides LMA/LME, as
3159 * these two bits are handled by VM-entry, see hmR0VmxExportGuestExitCtls() and
3160 * hmR0VMxExportGuestEntryCtls().
3161 *
3162 * @returns true if we need to load guest EFER, false otherwise.
3163 * @param pVCpu The cross context virtual CPU structure.
3164 *
3165 * @remarks Requires EFER, CR4.
3166 * @remarks No-long-jump zone!!!
3167 */
3168static bool hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu)
3169{
3170#ifdef HMVMX_ALWAYS_SWAP_EFER
3171 RT_NOREF(pVCpu);
3172 return true;
3173#else
3174
3175 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3176#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
3177 /* For 32-bit hosts running 64-bit guests, we always swap EFER in the world-switcher. Nothing to do here. */
3178 if (CPUMIsGuestInLongModeEx(pCtx))
3179 return false;
3180#endif
3181
3182 PVM pVM = pVCpu->CTX_SUFF(pVM);
3183 uint64_t const u64HostEfer = pVM->hm.s.vmx.u64HostEfer;
3184 uint64_t const u64GuestEfer = pCtx->msrEFER;
3185
3186 /*
3187 * For 64-bit guests, if EFER.SCE bit differs, we need to swap EFER to ensure that the
3188 * guest's SYSCALL behaviour isn't broken, see @bugref{7386}.
3189 */
3190 if ( CPUMIsGuestInLongModeEx(pCtx)
3191 && (u64GuestEfer & MSR_K6_EFER_SCE) != (u64HostEfer & MSR_K6_EFER_SCE))
3192 {
3193 return true;
3194 }
3195
3196 /*
3197 * If the guest uses PAE and EFER.NXE bit differs, we need to swap EFER as it
3198 * affects guest paging. 64-bit paging implies CR4.PAE as well.
3199 * See Intel spec. 4.5 "IA-32e Paging" and Intel spec. 4.1.1 "Three Paging Modes".
3200 */
3201 if ( (pCtx->cr4 & X86_CR4_PAE)
3202 && (pCtx->cr0 & X86_CR0_PG)
3203 && (u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE))
3204 {
3205 /* Assert that host is NX capable. */
3206 Assert(pVCpu->CTX_SUFF(pVM)->cpum.ro.HostFeatures.fNoExecute);
3207 return true;
3208 }
3209
3210 return false;
3211#endif
3212}
3213
3214
3215/**
3216 * Exports the guest state with appropriate VM-entry controls in the VMCS.
3217 *
3218 * These controls can affect things done on VM-exit; e.g. "load debug controls",
3219 * see Intel spec. 24.8.1 "VM-entry controls".
3220 *
3221 * @returns VBox status code.
3222 * @param pVCpu The cross context virtual CPU structure.
3223 *
3224 * @remarks Requires EFER.
3225 * @remarks No-long-jump zone!!!
3226 */
3227static int hmR0VmxExportGuestEntryCtls(PVMCPU pVCpu)
3228{
3229 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_ENTRY_CTLS)
3230 {
3231 PVM pVM = pVCpu->CTX_SUFF(pVM);
3232 uint32_t fVal = pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
3233 uint32_t const fZap = pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3234
3235 /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
3236 fVal |= VMX_ENTRY_CTLS_LOAD_DEBUG;
3237
3238 /* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
3239 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
3240 {
3241 fVal |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
3242 Log4Func(("VMX_ENTRY_CTLS_IA32E_MODE_GUEST\n"));
3243 }
3244 else
3245 Assert(!(fVal & VMX_ENTRY_CTLS_IA32E_MODE_GUEST));
3246
3247 /* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it. */
3248 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3249 && hmR0VmxShouldSwapEferMsr(pVCpu))
3250 {
3251 fVal |= VMX_ENTRY_CTLS_LOAD_EFER_MSR;
3252 Log4Func(("VMX_ENTRY_CTLS_LOAD_EFER_MSR\n"));
3253 }
3254
3255 /*
3256 * The following should -not- be set (since we're not in SMM mode):
3257 * - VMX_ENTRY_CTLS_ENTRY_TO_SMM
3258 * - VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON
3259 */
3260
3261 /** @todo VMX_ENTRY_CTLS_LOAD_PERF_MSR,
3262 * VMX_ENTRY_CTLS_LOAD_PAT_MSR. */
3263
3264 if ((fVal & fZap) != fVal)
3265 {
3266 Log4Func(("Invalid VM-entry controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
3267 pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0, fVal, fZap));
3268 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
3269 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3270 }
3271
3272 /* Commit it to the VMCS and update our cache. */
3273 if (pVCpu->hm.s.vmx.Ctls.u32EntryCtls != fVal)
3274 {
3275 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, fVal);
3276 AssertRCReturn(rc, rc);
3277 pVCpu->hm.s.vmx.Ctls.u32EntryCtls = fVal;
3278 }
3279
3280 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_ENTRY_CTLS);
3281 }
3282 return VINF_SUCCESS;
3283}
3284
3285
3286/**
3287 * Exports the guest state with appropriate VM-exit controls in the VMCS.
3288 *
3289 * @returns VBox status code.
3290 * @param pVCpu The cross context virtual CPU structure.
3291 *
3292 * @remarks Requires EFER.
3293 */
3294static int hmR0VmxExportGuestExitCtls(PVMCPU pVCpu)
3295{
3296 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_EXIT_CTLS)
3297 {
3298 PVM pVM = pVCpu->CTX_SUFF(pVM);
3299 uint32_t fVal = pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
3300 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3301
3302 /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
3303 fVal |= VMX_EXIT_CTLS_SAVE_DEBUG;
3304
3305 /*
3306 * Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary.
3307 * On VM-exit, VT-x sets both the host EFER.LMA and EFER.LME bit to this value. See assertion in
3308 * hmR0VmxExportHostMsrs().
3309 */
3310#if HC_ARCH_BITS == 64
3311 fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
3312 Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
3313#else
3314 Assert( pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64
3315 || pVCpu->hm.s.vmx.pfnStartVM == VMXR0StartVM32);
3316 /* Set the host address-space size based on the switcher, not guest state. See @bugref{8432}. */
3317 if (pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64)
3318 {
3319 /* The switcher returns to long mode, EFER is managed by the switcher. */
3320 fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
3321 Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
3322 }
3323 else
3324 Assert(!(fVal & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE));
3325#endif
3326
3327 /* If the newer VMCS fields for managing EFER exists, use it. */
3328 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3329 && hmR0VmxShouldSwapEferMsr(pVCpu))
3330 {
3331 fVal |= VMX_EXIT_CTLS_SAVE_EFER_MSR
3332 | VMX_EXIT_CTLS_LOAD_EFER_MSR;
3333 Log4Func(("VMX_EXIT_CTLS_SAVE_EFER_MSR and VMX_EXIT_CTLS_LOAD_EFER_MSR\n"));
3334 }
3335
3336 /* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
3337 Assert(!(fVal & VMX_EXIT_CTLS_ACK_EXT_INT));
3338
3339 /** @todo VMX_EXIT_CTLS_LOAD_PERF_MSR,
3340 * VMX_EXIT_CTLS_SAVE_PAT_MSR,
3341 * VMX_EXIT_CTLS_LOAD_PAT_MSR. */
3342
3343 /* Enable saving of the VMX preemption timer value on VM-exit. */
3344 if ( pVM->hm.s.vmx.fUsePreemptTimer
3345 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
3346 fVal |= VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER;
3347
3348 if ((fVal & fZap) != fVal)
3349 {
3350 LogRelFunc(("Invalid VM-exit controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%R#X32\n",
3351 pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed0, fVal, fZap));
3352 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
3353 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3354 }
3355
3356 /* Commit it to the VMCS and update our cache. */
3357 if (pVCpu->hm.s.vmx.Ctls.u32ExitCtls != fVal)
3358 {
3359 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, fVal);
3360 AssertRCReturn(rc, rc);
3361 pVCpu->hm.s.vmx.Ctls.u32ExitCtls = fVal;
3362 }
3363
3364 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_EXIT_CTLS);
3365 }
3366 return VINF_SUCCESS;
3367}
3368
3369
3370/**
3371 * Sets the TPR threshold in the VMCS.
3372 *
3373 * @returns VBox status code.
3374 * @param pVCpu The cross context virtual CPU structure.
3375 * @param u32TprThreshold The TPR threshold (task-priority class only).
3376 */
3377DECLINLINE(int) hmR0VmxApicSetTprThreshold(PVMCPU pVCpu, uint32_t u32TprThreshold)
3378{
3379 Assert(!(u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)); /* Bits 31:4 MBZ. */
3380 Assert(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
3381 return VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
3382}
3383
3384
3385/**
3386 * Exports the guest APIC TPR state into the VMCS.
3387 *
3388 * @returns VBox status code.
3389 * @param pVCpu The cross context virtual CPU structure.
3390 *
3391 * @remarks No-long-jump zone!!!
3392 */
3393static int hmR0VmxExportGuestApicTpr(PVMCPU pVCpu)
3394{
3395 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
3396 {
3397 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
3398
3399 if ( PDMHasApic(pVCpu->CTX_SUFF(pVM))
3400 && APICIsEnabled(pVCpu))
3401 {
3402 /*
3403 * Setup TPR shadowing.
3404 */
3405 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3406 {
3407 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
3408
3409 bool fPendingIntr = false;
3410 uint8_t u8Tpr = 0;
3411 uint8_t u8PendingIntr = 0;
3412 int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
3413 AssertRCReturn(rc, rc);
3414
3415 /*
3416 * If there are interrupts pending but masked by the TPR, instruct VT-x to
3417 * cause a TPR-below-threshold VM-exit when the guest lowers its TPR below the
3418 * priority of the pending interrupt so we can deliver the interrupt. If there
3419 * are no interrupts pending, set threshold to 0 to not cause any
3420 * TPR-below-threshold VM-exits.
3421 */
3422 pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR] = u8Tpr;
3423 uint32_t u32TprThreshold = 0;
3424 if (fPendingIntr)
3425 {
3426 /* Bits 3:0 of the TPR threshold field correspond to bits 7:4 of the TPR (which is the Task-Priority Class). */
3427 const uint8_t u8PendingPriority = u8PendingIntr >> 4;
3428 const uint8_t u8TprPriority = u8Tpr >> 4;
3429 if (u8PendingPriority <= u8TprPriority)
3430 u32TprThreshold = u8PendingPriority;
3431 }
3432
3433 rc = hmR0VmxApicSetTprThreshold(pVCpu, u32TprThreshold);
3434 AssertRCReturn(rc, rc);
3435 }
3436 }
3437 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
3438 }
3439 return VINF_SUCCESS;
3440}
3441
3442
3443/**
3444 * Gets the guest's interruptibility-state ("interrupt shadow" as AMD calls it).
3445 *
3446 * @returns Guest's interruptibility-state.
3447 * @param pVCpu The cross context virtual CPU structure.
3448 *
3449 * @remarks No-long-jump zone!!!
3450 */
3451static uint32_t hmR0VmxGetGuestIntrState(PVMCPU pVCpu)
3452{
3453 /*
3454 * Check if we should inhibit interrupt delivery due to instructions like STI and MOV SS.
3455 */
3456 uint32_t fIntrState = 0;
3457 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3458 {
3459 /* If inhibition is active, RIP & RFLAGS should've been accessed
3460 (i.e. read previously from the VMCS or from ring-3). */
3461 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3462#ifdef VBOX_STRICT
3463 uint64_t const fExtrn = ASMAtomicUoReadU64(&pCtx->fExtrn);
3464 AssertMsg(!(fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)), ("%#x\n", fExtrn));
3465#endif
3466 if (pCtx->rip == EMGetInhibitInterruptsPC(pVCpu))
3467 {
3468 if (pCtx->eflags.Bits.u1IF)
3469 fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
3470 else
3471 fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
3472 }
3473 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3474 {
3475 /*
3476 * We can clear the inhibit force flag as even if we go back to the recompiler
3477 * without executing guest code in VT-x, the flag's condition to be cleared is
3478 * met and thus the cleared state is correct.
3479 */
3480 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3481 }
3482 }
3483
3484 /*
3485 * NMIs to the guest are blocked after an NMI is injected until the guest executes an IRET. We only
3486 * bother with virtual-NMI blocking when we have support for virtual NMIs in the CPU, otherwise
3487 * setting this would block host-NMIs and IRET will not clear the blocking.
3488 *
3489 * See Intel spec. 26.6.1 "Interruptibility state". See @bugref{7445}.
3490 */
3491 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)
3492 && (pVCpu->hm.s.vmx.Ctls.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3493 {
3494 fIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
3495 }
3496
3497 return fIntrState;
3498}
3499
3500
3501/**
3502 * Exports the exception intercepts required for guest execution in the VMCS.
3503 *
3504 * @returns VBox status code.
3505 * @param pVCpu The cross context virtual CPU structure.
3506 *
3507 * @remarks No-long-jump zone!!!
3508 */
3509static int hmR0VmxExportGuestXcptIntercepts(PVMCPU pVCpu)
3510{
3511 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS)
3512 {
3513 uint32_t uXcptBitmap = pVCpu->hm.s.vmx.Ctls.u32XcptBitmap;
3514
3515 /* The remaining exception intercepts are handled elsewhere, e.g. in hmR0VmxExportGuestCR0(). */
3516 if (pVCpu->hm.s.fGIMTrapXcptUD)
3517 uXcptBitmap |= RT_BIT(X86_XCPT_UD);
3518#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3519 else
3520 uXcptBitmap &= ~RT_BIT(X86_XCPT_UD);
3521#endif
3522
3523 Assert(uXcptBitmap & RT_BIT_32(X86_XCPT_AC));
3524 Assert(uXcptBitmap & RT_BIT_32(X86_XCPT_DB));
3525
3526 if (uXcptBitmap != pVCpu->hm.s.vmx.Ctls.u32XcptBitmap)
3527 {
3528 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
3529 AssertRCReturn(rc, rc);
3530 pVCpu->hm.s.vmx.Ctls.u32XcptBitmap = uXcptBitmap;
3531 }
3532
3533 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS);
3534 Log4Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP=%#RX64\n", uXcptBitmap));
3535 }
3536 return VINF_SUCCESS;
3537}
3538
3539
3540/**
3541 * Exports the guest's RIP into the guest-state area in the VMCS.
3542 *
3543 * @returns VBox status code.
3544 * @param pVCpu The cross context virtual CPU structure.
3545 *
3546 * @remarks No-long-jump zone!!!
3547 */
3548static int hmR0VmxExportGuestRip(PVMCPU pVCpu)
3549{
3550 int rc = VINF_SUCCESS;
3551 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RIP)
3552 {
3553 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP);
3554
3555 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pVCpu->cpum.GstCtx.rip);
3556 AssertRCReturn(rc, rc);
3557
3558 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RIP);
3559 Log4Func(("RIP=%#RX64\n", pVCpu->cpum.GstCtx.rip));
3560 }
3561 return rc;
3562}
3563
3564
3565/**
3566 * Exports the guest's RSP into the guest-state area in the VMCS.
3567 *
3568 * @returns VBox status code.
3569 * @param pVCpu The cross context virtual CPU structure.
3570 *
3571 * @remarks No-long-jump zone!!!
3572 */
3573static int hmR0VmxExportGuestRsp(PVMCPU pVCpu)
3574{
3575 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RSP)
3576 {
3577 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP);
3578
3579 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pVCpu->cpum.GstCtx.rsp);
3580 AssertRCReturn(rc, rc);
3581
3582 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RSP);
3583 }
3584 return VINF_SUCCESS;
3585}
3586
3587
3588/**
3589 * Exports the guest's RFLAGS into the guest-state area in the VMCS.
3590 *
3591 * @returns VBox status code.
3592 * @param pVCpu The cross context virtual CPU structure.
3593 *
3594 * @remarks No-long-jump zone!!!
3595 */
3596static int hmR0VmxExportGuestRflags(PVMCPU pVCpu)
3597{
3598 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RFLAGS)
3599 {
3600 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RFLAGS);
3601
3602 /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
3603 Let us assert it as such and use 32-bit VMWRITE. */
3604 Assert(!RT_HI_U32(pVCpu->cpum.GstCtx.rflags.u64));
3605 X86EFLAGS fEFlags = pVCpu->cpum.GstCtx.eflags;
3606 Assert(fEFlags.u32 & X86_EFL_RA1_MASK);
3607 Assert(!(fEFlags.u32 & ~(X86_EFL_1 | X86_EFL_LIVE_MASK)));
3608
3609 /*
3610 * If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so
3611 * we can restore them on VM-exit. Modify the real-mode guest's eflags so that VT-x
3612 * can run the real-mode guest code under Virtual 8086 mode.
3613 */
3614 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3615 {
3616 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
3617 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
3618 pVCpu->hm.s.vmx.RealMode.Eflags.u32 = fEFlags.u32; /* Save the original eflags of the real-mode guest. */
3619 fEFlags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
3620 fEFlags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
3621 }
3622
3623 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_RFLAGS, fEFlags.u32);
3624 AssertRCReturn(rc, rc);
3625
3626 /*
3627 * Setup pending debug exceptions if the guest is single-stepping using EFLAGS.TF.
3628 *
3629 * We must avoid setting any automatic debug exceptions delivery when single-stepping
3630 * through the hypervisor debugger using EFLAGS.TF.
3631 */
3632 if ( !pVCpu->hm.s.fSingleInstruction
3633 && fEFlags.Bits.u1TF)
3634 {
3635 /** @todo r=ramshankar: Warning! We ASSUME EFLAGS.TF will not cleared on
3636 * premature trips to ring-3 esp since IEM does not yet handle it. */
3637 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS);
3638 AssertRCReturn(rc, rc);
3639 }
3640
3641 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RFLAGS);
3642 Log4Func(("EFlags=%#RX32\n", fEFlags.u32));
3643 }
3644 return VINF_SUCCESS;
3645}
3646
3647
3648/**
3649 * Exports the guest CR0 control register into the guest-state area in the VMCS.
3650 *
3651 * The guest FPU state is always pre-loaded hence we don't need to bother about
3652 * sharing FPU related CR0 bits between the guest and host.
3653 *
3654 * @returns VBox status code.
3655 * @param pVCpu The cross context virtual CPU structure.
3656 *
3657 * @remarks No-long-jump zone!!!
3658 */
3659static int hmR0VmxExportGuestCR0(PVMCPU pVCpu)
3660{
3661 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR0)
3662 {
3663 PVM pVM = pVCpu->CTX_SUFF(pVM);
3664 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3665 Assert(!RT_HI_U32(pVCpu->cpum.GstCtx.cr0));
3666
3667 uint32_t const u32ShadowCr0 = pVCpu->cpum.GstCtx.cr0;
3668 uint32_t u32GuestCr0 = pVCpu->cpum.GstCtx.cr0;
3669
3670 /*
3671 * Setup VT-x's view of the guest CR0.
3672 * Minimize VM-exits due to CR3 changes when we have NestedPaging.
3673 */
3674 uint32_t uProcCtls = pVCpu->hm.s.vmx.Ctls.u32ProcCtls;
3675 if (pVM->hm.s.fNestedPaging)
3676 {
3677 if (CPUMIsGuestPagingEnabled(pVCpu))
3678 {
3679 /* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
3680 uProcCtls &= ~( VMX_PROC_CTLS_CR3_LOAD_EXIT
3681 | VMX_PROC_CTLS_CR3_STORE_EXIT);
3682 }
3683 else
3684 {
3685 /* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
3686 uProcCtls |= VMX_PROC_CTLS_CR3_LOAD_EXIT
3687 | VMX_PROC_CTLS_CR3_STORE_EXIT;
3688 }
3689
3690 /* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
3691 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3692 uProcCtls &= ~VMX_PROC_CTLS_CR3_STORE_EXIT;
3693 }
3694 else
3695 {
3696 /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
3697 u32GuestCr0 |= X86_CR0_WP;
3698 }
3699
3700 /*
3701 * Guest FPU bits.
3702 *
3703 * Since we pre-load the guest FPU always before VM-entry there is no need to track lazy state
3704 * using CR0.TS.
3705 *
3706 * Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be
3707 * set on the first CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
3708 */
3709 u32GuestCr0 |= X86_CR0_NE;
3710
3711 /* If CR0.NE isn't set, we need to intercept #MF exceptions and report them to the guest differently. */
3712 bool const fInterceptMF = !(u32ShadowCr0 & X86_CR0_NE);
3713
3714 /*
3715 * Update exception intercepts.
3716 */
3717 uint32_t uXcptBitmap = pVCpu->hm.s.vmx.Ctls.u32XcptBitmap;
3718 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3719 {
3720 Assert(PDMVmmDevHeapIsEnabled(pVM));
3721 Assert(pVM->hm.s.vmx.pRealModeTSS);
3722 uXcptBitmap |= HMVMX_REAL_MODE_XCPT_MASK;
3723 }
3724 else
3725 {
3726 /* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */
3727 uXcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
3728 if (fInterceptMF)
3729 uXcptBitmap |= RT_BIT(X86_XCPT_MF);
3730 }
3731
3732 /* Additional intercepts for debugging, define these yourself explicitly. */
3733#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3734 uXcptBitmap |= 0
3735 | RT_BIT(X86_XCPT_BP)
3736 | RT_BIT(X86_XCPT_DE)
3737 | RT_BIT(X86_XCPT_NM)
3738 | RT_BIT(X86_XCPT_TS)
3739 | RT_BIT(X86_XCPT_UD)
3740 | RT_BIT(X86_XCPT_NP)
3741 | RT_BIT(X86_XCPT_SS)
3742 | RT_BIT(X86_XCPT_GP)
3743 | RT_BIT(X86_XCPT_PF)
3744 | RT_BIT(X86_XCPT_MF)
3745 ;
3746#elif defined(HMVMX_ALWAYS_TRAP_PF)
3747 uXcptBitmap |= RT_BIT(X86_XCPT_PF);
3748#endif
3749 if (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv)
3750 uXcptBitmap |= RT_BIT(X86_XCPT_GP);
3751 Assert(pVM->hm.s.fNestedPaging || (uXcptBitmap & RT_BIT(X86_XCPT_PF)));
3752
3753 /*
3754 * Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW).
3755 */
3756 uint32_t fSetCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3757 uint32_t fZapCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3758 if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */
3759 fSetCr0 &= ~(X86_CR0_PE | X86_CR0_PG);
3760 else
3761 Assert((fSetCr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG));
3762
3763 u32GuestCr0 |= fSetCr0;
3764 u32GuestCr0 &= fZapCr0;
3765 u32GuestCr0 &= ~(X86_CR0_CD | X86_CR0_NW); /* Always enable caching. */
3766
3767 /*
3768 * CR0 is shared between host and guest along with a CR0 read shadow. Therefore, certain bits must not be changed
3769 * by the guest because VT-x ignores saving/restoring them (namely CD, ET, NW) and for certain other bits
3770 * we want to be notified immediately of guest CR0 changes (e.g. PG to update our shadow page tables).
3771 */
3772 uint32_t u32Cr0Mask = X86_CR0_PE
3773 | X86_CR0_NE
3774 | (pVM->hm.s.fNestedPaging ? 0 : X86_CR0_WP)
3775 | X86_CR0_PG
3776 | X86_CR0_ET /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
3777 | X86_CR0_CD /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
3778 | X86_CR0_NW; /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.NW */
3779
3780 /** @todo Avoid intercepting CR0.PE with unrestricted guests. Fix PGM
3781 * enmGuestMode to be in-sync with the current mode. See @bugref{6398}
3782 * and @bugref{6944}. */
3783#if 0
3784 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3785 u32Cr0Mask &= ~X86_CR0_PE;
3786#endif
3787 /*
3788 * Finally, update VMCS fields with the CR0 values and the exception bitmap.
3789 */
3790 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCr0);
3791 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, u32ShadowCr0);
3792 if (u32Cr0Mask != pVCpu->hm.s.vmx.Ctls.u32Cr0Mask)
3793 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32Cr0Mask);
3794 if (uProcCtls != pVCpu->hm.s.vmx.Ctls.u32ProcCtls)
3795 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
3796 if (uXcptBitmap != pVCpu->hm.s.vmx.Ctls.u32XcptBitmap)
3797 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
3798 AssertRCReturn(rc, rc);
3799
3800 /* Update our caches. */
3801 pVCpu->hm.s.vmx.Ctls.u32Cr0Mask = u32Cr0Mask;
3802 pVCpu->hm.s.vmx.Ctls.u32ProcCtls = uProcCtls;
3803 pVCpu->hm.s.vmx.Ctls.u32XcptBitmap = uXcptBitmap;
3804
3805 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR0);
3806
3807 Log4Func(("u32Cr0Mask=%#RX32 u32ShadowCr0=%#RX32 u32GuestCr0=%#RX32 (fSetCr0=%#RX32 fZapCr0=%#RX32\n", u32Cr0Mask,
3808 u32ShadowCr0, u32GuestCr0, fSetCr0, fZapCr0));
3809 }
3810
3811 return VINF_SUCCESS;
3812}
3813
3814
3815/**
3816 * Exports the guest control registers (CR3, CR4) into the guest-state area
3817 * in the VMCS.
3818 *
3819 * @returns VBox strict status code.
3820 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
3821 * without unrestricted guest access and the VMMDev is not presently
3822 * mapped (e.g. EFI32).
3823 *
3824 * @param pVCpu The cross context virtual CPU structure.
3825 *
3826 * @remarks No-long-jump zone!!!
3827 */
3828static VBOXSTRICTRC hmR0VmxExportGuestCR3AndCR4(PVMCPU pVCpu)
3829{
3830 int rc = VINF_SUCCESS;
3831 PVM pVM = pVCpu->CTX_SUFF(pVM);
3832
3833 /*
3834 * Guest CR2.
3835 * It's always loaded in the assembler code. Nothing to do here.
3836 */
3837
3838 /*
3839 * Guest CR3.
3840 */
3841 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR3)
3842 {
3843 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3844
3845 RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
3846 if (pVM->hm.s.fNestedPaging)
3847 {
3848 pVCpu->hm.s.vmx.HCPhysEPTP = PGMGetHyperCR3(pVCpu);
3849
3850 /* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
3851 Assert(pVCpu->hm.s.vmx.HCPhysEPTP);
3852 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & UINT64_C(0xfff0000000000000)));
3853 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & 0xfff));
3854
3855 /* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
3856 pVCpu->hm.s.vmx.HCPhysEPTP |= VMX_EPT_MEMTYPE_WB
3857 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
3858
3859 /* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
3860 AssertMsg( ((pVCpu->hm.s.vmx.HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
3861 && ((pVCpu->hm.s.vmx.HCPhysEPTP >> 7) & 0x1f) == 0, /* Bits 7:11 MBZ. */
3862 ("EPTP %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3863 AssertMsg( !((pVCpu->hm.s.vmx.HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */
3864 || (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
3865 ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3866
3867 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.HCPhysEPTP);
3868 AssertRCReturn(rc, rc);
3869
3870 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3871 if ( pVM->hm.s.vmx.fUnrestrictedGuest
3872 || CPUMIsGuestPagingEnabledEx(pCtx))
3873 {
3874 /* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
3875 if (CPUMIsGuestInPAEModeEx(pCtx))
3876 {
3877 rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
3878 AssertRCReturn(rc, rc);
3879 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);
3880 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);
3881 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);
3882 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);
3883 AssertRCReturn(rc, rc);
3884 }
3885
3886 /*
3887 * The guest's view of its CR3 is unblemished with Nested Paging when the
3888 * guest is using paging or we have unrestricted guest execution to handle
3889 * the guest when it's not using paging.
3890 */
3891 GCPhysGuestCR3 = pCtx->cr3;
3892 }
3893 else
3894 {
3895 /*
3896 * The guest is not using paging, but the CPU (VT-x) has to. While the guest
3897 * thinks it accesses physical memory directly, we use our identity-mapped
3898 * page table to map guest-linear to guest-physical addresses. EPT takes care
3899 * of translating it to host-physical addresses.
3900 */
3901 RTGCPHYS GCPhys;
3902 Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
3903
3904 /* We obtain it here every time as the guest could have relocated this PCI region. */
3905 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
3906 if (RT_SUCCESS(rc))
3907 { /* likely */ }
3908 else if (rc == VERR_PDM_DEV_HEAP_R3_TO_GCPHYS)
3909 {
3910 Log4Func(("VERR_PDM_DEV_HEAP_R3_TO_GCPHYS -> VINF_EM_RESCHEDULE_REM\n"));
3911 return VINF_EM_RESCHEDULE_REM; /* We cannot execute now, switch to REM/IEM till the guest maps in VMMDev. */
3912 }
3913 else
3914 AssertMsgFailedReturn(("%Rrc\n", rc), rc);
3915
3916 GCPhysGuestCR3 = GCPhys;
3917 }
3918
3919 Log4Func(("u32GuestCr3=%#RGp (GstN)\n", GCPhysGuestCR3));
3920 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR3, GCPhysGuestCR3);
3921 AssertRCReturn(rc, rc);
3922 }
3923 else
3924 {
3925 /* Non-nested paging case, just use the hypervisor's CR3. */
3926 RTHCPHYS HCPhysGuestCR3 = PGMGetHyperCR3(pVCpu);
3927
3928 Log4Func(("u32GuestCr3=%#RHv (HstN)\n", HCPhysGuestCR3));
3929 rc = VMXWriteVmcsHstN(VMX_VMCS_GUEST_CR3, HCPhysGuestCR3);
3930 AssertRCReturn(rc, rc);
3931 }
3932
3933 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR3);
3934 }
3935
3936 /*
3937 * Guest CR4.
3938 * ASSUMES this is done everytime we get in from ring-3! (XCR0)
3939 */
3940 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR4)
3941 {
3942 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3943 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3944 Assert(!RT_HI_U32(pCtx->cr4));
3945
3946 uint32_t u32GuestCr4 = pCtx->cr4;
3947 uint32_t const u32ShadowCr4 = pCtx->cr4;
3948
3949 /*
3950 * Setup VT-x's view of the guest CR4.
3951 *
3952 * If we're emulating real-mode using virtual-8086 mode, we want to redirect software
3953 * interrupts to the 8086 program interrupt handler. Clear the VME bit (the interrupt
3954 * redirection bitmap is already all 0, see hmR3InitFinalizeR0())
3955 *
3956 * See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
3957 */
3958 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3959 {
3960 Assert(pVM->hm.s.vmx.pRealModeTSS);
3961 Assert(PDMVmmDevHeapIsEnabled(pVM));
3962 u32GuestCr4 &= ~X86_CR4_VME;
3963 }
3964
3965 if (pVM->hm.s.fNestedPaging)
3966 {
3967 if ( !CPUMIsGuestPagingEnabledEx(pCtx)
3968 && !pVM->hm.s.vmx.fUnrestrictedGuest)
3969 {
3970 /* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
3971 u32GuestCr4 |= X86_CR4_PSE;
3972 /* Our identity mapping is a 32-bit page directory. */
3973 u32GuestCr4 &= ~X86_CR4_PAE;
3974 }
3975 /* else use guest CR4.*/
3976 }
3977 else
3978 {
3979 /*
3980 * The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
3981 * paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
3982 */
3983 switch (pVCpu->hm.s.enmShadowMode)
3984 {
3985 case PGMMODE_REAL: /* Real-mode. */
3986 case PGMMODE_PROTECTED: /* Protected mode without paging. */
3987 case PGMMODE_32_BIT: /* 32-bit paging. */
3988 {
3989 u32GuestCr4 &= ~X86_CR4_PAE;
3990 break;
3991 }
3992
3993 case PGMMODE_PAE: /* PAE paging. */
3994 case PGMMODE_PAE_NX: /* PAE paging with NX. */
3995 {
3996 u32GuestCr4 |= X86_CR4_PAE;
3997 break;
3998 }
3999
4000 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
4001 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
4002#ifdef VBOX_ENABLE_64_BITS_GUESTS
4003 break;
4004#endif
4005 default:
4006 AssertFailed();
4007 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4008 }
4009 }
4010
4011 /* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */
4012 uint64_t const fSetCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4013 uint64_t const fZapCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4014 u32GuestCr4 |= fSetCr4;
4015 u32GuestCr4 &= fZapCr4;
4016
4017 /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them,
4018 that would cause a VM-exit. */
4019 uint32_t u32Cr4Mask = X86_CR4_VME
4020 | X86_CR4_PAE
4021 | X86_CR4_PGE
4022 | X86_CR4_PSE
4023 | X86_CR4_VMXE;
4024 if (pVM->cpum.ro.HostFeatures.fXSaveRstor)
4025 u32Cr4Mask |= X86_CR4_OSXSAVE;
4026 if (pVM->cpum.ro.GuestFeatures.fPcid)
4027 u32Cr4Mask |= X86_CR4_PCIDE;
4028
4029 /* Write VT-x's view of the guest CR4, the CR4 modify mask and the read-only CR4 shadow
4030 into the VMCS and update our cache. */
4031 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCr4);
4032 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32ShadowCr4);
4033 if (pVCpu->hm.s.vmx.Ctls.u32Cr4Mask != u32Cr4Mask)
4034 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32Cr4Mask);
4035 AssertRCReturn(rc, rc);
4036 pVCpu->hm.s.vmx.Ctls.u32Cr4Mask = u32Cr4Mask;
4037
4038 /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
4039 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4040
4041 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR4);
4042
4043 Log4Func(("u32GuestCr4=%#RX32 u32ShadowCr4=%#RX32 (fSetCr4=%#RX32 fZapCr4=%#RX32)\n", u32GuestCr4, u32ShadowCr4, fSetCr4,
4044 fZapCr4));
4045 }
4046 return rc;
4047}
4048
4049
4050/**
4051 * Exports the guest debug registers into the guest-state area in the VMCS.
4052 * The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
4053 *
4054 * This also sets up whether \#DB and MOV DRx accesses cause VM-exits.
4055 *
4056 * @returns VBox status code.
4057 * @param pVCpu The cross context virtual CPU structure.
4058 *
4059 * @remarks No-long-jump zone!!!
4060 */
4061static int hmR0VmxExportSharedDebugState(PVMCPU pVCpu)
4062{
4063 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4064
4065#ifdef VBOX_STRICT
4066 /* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
4067 if (pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4068 {
4069 /* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
4070 Assert((pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_MBZ_MASK | X86_DR7_RAZ_MASK)) == 0);
4071 Assert((pVCpu->cpum.GstCtx.dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK);
4072 }
4073#endif
4074
4075 bool fSteppingDB = false;
4076 bool fInterceptMovDRx = false;
4077 uint32_t uProcCtls = pVCpu->hm.s.vmx.Ctls.u32ProcCtls;
4078 if (pVCpu->hm.s.fSingleInstruction)
4079 {
4080 /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
4081 PVM pVM = pVCpu->CTX_SUFF(pVM);
4082 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
4083 {
4084 uProcCtls |= VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
4085 Assert(fSteppingDB == false);
4086 }
4087 else
4088 {
4089 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_TF;
4090 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_GUEST_RFLAGS;
4091 pVCpu->hm.s.fClearTrapFlag = true;
4092 fSteppingDB = true;
4093 }
4094 }
4095
4096 uint32_t u32GuestDr7;
4097 if ( fSteppingDB
4098 || (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
4099 {
4100 /*
4101 * Use the combined guest and host DRx values found in the hypervisor register set
4102 * because the debugger has breakpoints active or someone is single stepping on the
4103 * host side without a monitor trap flag.
4104 *
4105 * Note! DBGF expects a clean DR6 state before executing guest code.
4106 */
4107#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4108 if ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
4109 && !CPUMIsHyperDebugStateActivePending(pVCpu))
4110 {
4111 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4112 Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
4113 Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
4114 }
4115 else
4116#endif
4117 if (!CPUMIsHyperDebugStateActive(pVCpu))
4118 {
4119 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4120 Assert(CPUMIsHyperDebugStateActive(pVCpu));
4121 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
4122 }
4123
4124 /* Update DR7 with the hypervisor value (other DRx registers are handled by CPUM one way or another). */
4125 u32GuestDr7 = (uint32_t)CPUMGetHyperDR7(pVCpu);
4126 pVCpu->hm.s.fUsingHyperDR7 = true;
4127 fInterceptMovDRx = true;
4128 }
4129 else
4130 {
4131 /*
4132 * If the guest has enabled debug registers, we need to load them prior to
4133 * executing guest code so they'll trigger at the right time.
4134 */
4135 if (pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_ENABLED_MASK | X86_DR7_GD))
4136 {
4137#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4138 if ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
4139 && !CPUMIsGuestDebugStateActivePending(pVCpu))
4140 {
4141 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4142 Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
4143 Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
4144 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4145 }
4146 else
4147#endif
4148 if (!CPUMIsGuestDebugStateActive(pVCpu))
4149 {
4150 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4151 Assert(CPUMIsGuestDebugStateActive(pVCpu));
4152 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
4153 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4154 }
4155 Assert(!fInterceptMovDRx);
4156 }
4157 /*
4158 * If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
4159 * must intercept #DB in order to maintain a correct DR6 guest value, and
4160 * because we need to intercept it to prevent nested #DBs from hanging the
4161 * CPU, we end up always having to intercept it. See hmR0VmxInitXcptBitmap.
4162 */
4163#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4164 else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
4165 && !CPUMIsGuestDebugStateActive(pVCpu))
4166#else
4167 else if (!CPUMIsGuestDebugStateActive(pVCpu))
4168#endif
4169 {
4170 fInterceptMovDRx = true;
4171 }
4172
4173 /* Update DR7 with the actual guest value. */
4174 u32GuestDr7 = pVCpu->cpum.GstCtx.dr[7];
4175 pVCpu->hm.s.fUsingHyperDR7 = false;
4176 }
4177
4178 if (fInterceptMovDRx)
4179 uProcCtls |= VMX_PROC_CTLS_MOV_DR_EXIT;
4180 else
4181 uProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
4182
4183 /*
4184 * Update the processor-based VM-execution controls with the MOV-DRx intercepts and the
4185 * monitor-trap flag and update our cache.
4186 */
4187 if (uProcCtls != pVCpu->hm.s.vmx.Ctls.u32ProcCtls)
4188 {
4189 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
4190 AssertRCReturn(rc2, rc2);
4191 pVCpu->hm.s.vmx.Ctls.u32ProcCtls = uProcCtls;
4192 }
4193
4194 /*
4195 * Update guest DR7.
4196 */
4197 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, u32GuestDr7);
4198 AssertRCReturn(rc, rc);
4199
4200 /*
4201 * If we have forced EFLAGS.TF to be set because we're single-stepping in the hypervisor debugger,
4202 * we need to clear interrupt inhibition if any as otherwise it causes a VM-entry failure.
4203 *
4204 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
4205 */
4206 if (fSteppingDB)
4207 {
4208 Assert(pVCpu->hm.s.fSingleInstruction);
4209 Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1TF);
4210
4211 uint32_t fIntrState = 0;
4212 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
4213 AssertRCReturn(rc, rc);
4214
4215 if (fIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
4216 {
4217 fIntrState &= ~(VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
4218 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
4219 AssertRCReturn(rc, rc);
4220 }
4221 }
4222
4223 return VINF_SUCCESS;
4224}
4225
4226
4227#ifdef VBOX_STRICT
4228/**
4229 * Strict function to validate segment registers.
4230 *
4231 * @param pVCpu The cross context virtual CPU structure.
4232 *
4233 * @remarks Will import guest CR0 on strict builds during validation of
4234 * segments.
4235 */
4236static void hmR0VmxValidateSegmentRegs(PVMCPU pVCpu)
4237{
4238 /*
4239 * Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4240 *
4241 * The reason we check for attribute value 0 in this function and not just the unusable bit is
4242 * because hmR0VmxExportGuestSegmentReg() only updates the VMCS' copy of the value with the unusable bit
4243 * and doesn't change the guest-context value.
4244 */
4245 PVM pVM = pVCpu->CTX_SUFF(pVM);
4246 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4247 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0);
4248 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
4249 && ( !CPUMIsGuestInRealModeEx(pCtx)
4250 && !CPUMIsGuestInV86ModeEx(pCtx)))
4251 {
4252 /* Protected mode checks */
4253 /* CS */
4254 Assert(pCtx->cs.Attr.n.u1Present);
4255 Assert(!(pCtx->cs.Attr.u & 0xf00));
4256 Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
4257 Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
4258 || !(pCtx->cs.Attr.n.u1Granularity));
4259 Assert( !(pCtx->cs.u32Limit & 0xfff00000)
4260 || (pCtx->cs.Attr.n.u1Granularity));
4261 /* CS cannot be loaded with NULL in protected mode. */
4262 Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS? */
4263 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
4264 Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
4265 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
4266 Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
4267 else
4268 AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
4269 /* SS */
4270 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4271 Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
4272 if ( !(pCtx->cr0 & X86_CR0_PE)
4273 || pCtx->cs.Attr.n.u4Type == 3)
4274 {
4275 Assert(!pCtx->ss.Attr.n.u2Dpl);
4276 }
4277 if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
4278 {
4279 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4280 Assert(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7);
4281 Assert(pCtx->ss.Attr.n.u1Present);
4282 Assert(!(pCtx->ss.Attr.u & 0xf00));
4283 Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
4284 Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
4285 || !(pCtx->ss.Attr.n.u1Granularity));
4286 Assert( !(pCtx->ss.u32Limit & 0xfff00000)
4287 || (pCtx->ss.Attr.n.u1Granularity));
4288 }
4289 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSegmentReg(). */
4290 if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
4291 {
4292 Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4293 Assert(pCtx->ds.Attr.n.u1Present);
4294 Assert(pCtx->ds.Attr.n.u4Type > 11 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
4295 Assert(!(pCtx->ds.Attr.u & 0xf00));
4296 Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
4297 Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
4298 || !(pCtx->ds.Attr.n.u1Granularity));
4299 Assert( !(pCtx->ds.u32Limit & 0xfff00000)
4300 || (pCtx->ds.Attr.n.u1Granularity));
4301 Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4302 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
4303 }
4304 if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
4305 {
4306 Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4307 Assert(pCtx->es.Attr.n.u1Present);
4308 Assert(pCtx->es.Attr.n.u4Type > 11 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
4309 Assert(!(pCtx->es.Attr.u & 0xf00));
4310 Assert(!(pCtx->es.Attr.u & 0xfffe0000));
4311 Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
4312 || !(pCtx->es.Attr.n.u1Granularity));
4313 Assert( !(pCtx->es.u32Limit & 0xfff00000)
4314 || (pCtx->es.Attr.n.u1Granularity));
4315 Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4316 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
4317 }
4318 if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
4319 {
4320 Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4321 Assert(pCtx->fs.Attr.n.u1Present);
4322 Assert(pCtx->fs.Attr.n.u4Type > 11 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
4323 Assert(!(pCtx->fs.Attr.u & 0xf00));
4324 Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
4325 Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
4326 || !(pCtx->fs.Attr.n.u1Granularity));
4327 Assert( !(pCtx->fs.u32Limit & 0xfff00000)
4328 || (pCtx->fs.Attr.n.u1Granularity));
4329 Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4330 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4331 }
4332 if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
4333 {
4334 Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4335 Assert(pCtx->gs.Attr.n.u1Present);
4336 Assert(pCtx->gs.Attr.n.u4Type > 11 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
4337 Assert(!(pCtx->gs.Attr.u & 0xf00));
4338 Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
4339 Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
4340 || !(pCtx->gs.Attr.n.u1Granularity));
4341 Assert( !(pCtx->gs.u32Limit & 0xfff00000)
4342 || (pCtx->gs.Attr.n.u1Granularity));
4343 Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4344 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4345 }
4346 /* 64-bit capable CPUs. */
4347# if HC_ARCH_BITS == 64
4348 Assert(!RT_HI_U32(pCtx->cs.u64Base));
4349 Assert(!pCtx->ss.Attr.u || !RT_HI_U32(pCtx->ss.u64Base));
4350 Assert(!pCtx->ds.Attr.u || !RT_HI_U32(pCtx->ds.u64Base));
4351 Assert(!pCtx->es.Attr.u || !RT_HI_U32(pCtx->es.u64Base));
4352# endif
4353 }
4354 else if ( CPUMIsGuestInV86ModeEx(pCtx)
4355 || ( CPUMIsGuestInRealModeEx(pCtx)
4356 && !pVM->hm.s.vmx.fUnrestrictedGuest))
4357 {
4358 /* Real and v86 mode checks. */
4359 /* hmR0VmxExportGuestSegmentReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
4360 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
4361 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4362 {
4363 u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3; u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
4364 }
4365 else
4366 {
4367 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
4368 u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
4369 }
4370
4371 /* CS */
4372 AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
4373 Assert(pCtx->cs.u32Limit == 0xffff);
4374 Assert(u32CSAttr == 0xf3);
4375 /* SS */
4376 Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
4377 Assert(pCtx->ss.u32Limit == 0xffff);
4378 Assert(u32SSAttr == 0xf3);
4379 /* DS */
4380 Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
4381 Assert(pCtx->ds.u32Limit == 0xffff);
4382 Assert(u32DSAttr == 0xf3);
4383 /* ES */
4384 Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
4385 Assert(pCtx->es.u32Limit == 0xffff);
4386 Assert(u32ESAttr == 0xf3);
4387 /* FS */
4388 Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
4389 Assert(pCtx->fs.u32Limit == 0xffff);
4390 Assert(u32FSAttr == 0xf3);
4391 /* GS */
4392 Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
4393 Assert(pCtx->gs.u32Limit == 0xffff);
4394 Assert(u32GSAttr == 0xf3);
4395 /* 64-bit capable CPUs. */
4396# if HC_ARCH_BITS == 64
4397 Assert(!RT_HI_U32(pCtx->cs.u64Base));
4398 Assert(!u32SSAttr || !RT_HI_U32(pCtx->ss.u64Base));
4399 Assert(!u32DSAttr || !RT_HI_U32(pCtx->ds.u64Base));
4400 Assert(!u32ESAttr || !RT_HI_U32(pCtx->es.u64Base));
4401# endif
4402 }
4403}
4404#endif /* VBOX_STRICT */
4405
4406
4407/**
4408 * Exports a guest segment register into the guest-state area in the VMCS.
4409 *
4410 * @returns VBox status code.
4411 * @param pVCpu The cross context virtual CPU structure.
4412 * @param idxSel Index of the selector in the VMCS.
4413 * @param idxLimit Index of the segment limit in the VMCS.
4414 * @param idxBase Index of the segment base in the VMCS.
4415 * @param idxAccess Index of the access rights of the segment in the VMCS.
4416 * @param pSelReg Pointer to the segment selector.
4417 *
4418 * @remarks No-long-jump zone!!!
4419 */
4420static int hmR0VmxExportGuestSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
4421 PCCPUMSELREG pSelReg)
4422{
4423 int rc = VMXWriteVmcs32(idxSel, pSelReg->Sel); /* 16-bit guest selector field. */
4424 rc |= VMXWriteVmcs32(idxLimit, pSelReg->u32Limit); /* 32-bit guest segment limit field. */
4425 rc |= VMXWriteVmcsGstN(idxBase, pSelReg->u64Base); /* Natural width guest segment base field.*/
4426 AssertRCReturn(rc, rc);
4427
4428 uint32_t u32Access = pSelReg->Attr.u;
4429 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4430 {
4431 /* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
4432 u32Access = 0xf3;
4433 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
4434 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
4435 }
4436 else
4437 {
4438 /*
4439 * The way to differentiate between whether this is really a null selector or was just
4440 * a selector loaded with 0 in real-mode is using the segment attributes. A selector
4441 * loaded in real-mode with the value 0 is valid and usable in protected-mode and we
4442 * should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures
4443 * NULL selectors loaded in protected-mode have their attribute as 0.
4444 */
4445 if (!u32Access)
4446 u32Access = X86DESCATTR_UNUSABLE;
4447 }
4448
4449 /* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
4450 AssertMsg((u32Access & X86DESCATTR_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
4451 ("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
4452
4453 rc = VMXWriteVmcs32(idxAccess, u32Access); /* 32-bit guest segment access-rights field. */
4454 AssertRCReturn(rc, rc);
4455 return rc;
4456}
4457
4458
4459/**
4460 * Exports the guest segment registers, GDTR, IDTR, LDTR, (TR, FS and GS bases)
4461 * into the guest-state area in the VMCS.
4462 *
4463 * @returns VBox status code.
4464 * @param pVCpu The cross context virtual CPU structure.
4465 *
4466 * @remarks Will import guest CR0 on strict builds during validation of
4467 * segments.
4468 * @remarks No-long-jump zone!!!
4469 */
4470static int hmR0VmxExportGuestSegmentRegs(PVMCPU pVCpu)
4471{
4472 int rc = VERR_INTERNAL_ERROR_5;
4473 PVM pVM = pVCpu->CTX_SUFF(pVM);
4474 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4475
4476 /*
4477 * Guest Segment registers: CS, SS, DS, ES, FS, GS.
4478 */
4479 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SREG_MASK)
4480 {
4481#ifdef VBOX_WITH_REM
4482 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
4483 {
4484 Assert(pVM->hm.s.vmx.pRealModeTSS);
4485 AssertCompile(PGMMODE_REAL < PGMMODE_PROTECTED);
4486 if ( pVCpu->hm.s.vmx.fWasInRealMode
4487 && PGMGetGuestMode(pVCpu) >= PGMMODE_PROTECTED)
4488 {
4489 /* Signal that the recompiler must flush its code-cache as the guest -may- rewrite code it will later execute
4490 in real-mode (e.g. OpenBSD 4.0) */
4491 REMFlushTBs(pVM);
4492 Log4Func(("Switch to protected mode detected!\n"));
4493 pVCpu->hm.s.vmx.fWasInRealMode = false;
4494 }
4495 }
4496#endif
4497 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CS)
4498 {
4499 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
4500 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4501 pVCpu->hm.s.vmx.RealMode.AttrCS.u = pCtx->cs.Attr.u;
4502 rc = HMVMX_EXPORT_SREG(CS, &pCtx->cs);
4503 AssertRCReturn(rc, rc);
4504 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CS);
4505 }
4506
4507 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SS)
4508 {
4509 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
4510 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4511 pVCpu->hm.s.vmx.RealMode.AttrSS.u = pCtx->ss.Attr.u;
4512 rc = HMVMX_EXPORT_SREG(SS, &pCtx->ss);
4513 AssertRCReturn(rc, rc);
4514 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SS);
4515 }
4516
4517 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_DS)
4518 {
4519 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DS);
4520 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4521 pVCpu->hm.s.vmx.RealMode.AttrDS.u = pCtx->ds.Attr.u;
4522 rc = HMVMX_EXPORT_SREG(DS, &pCtx->ds);
4523 AssertRCReturn(rc, rc);
4524 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_DS);
4525 }
4526
4527 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_ES)
4528 {
4529 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_ES);
4530 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4531 pVCpu->hm.s.vmx.RealMode.AttrES.u = pCtx->es.Attr.u;
4532 rc = HMVMX_EXPORT_SREG(ES, &pCtx->es);
4533 AssertRCReturn(rc, rc);
4534 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_ES);
4535 }
4536
4537 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_FS)
4538 {
4539 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
4540 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4541 pVCpu->hm.s.vmx.RealMode.AttrFS.u = pCtx->fs.Attr.u;
4542 rc = HMVMX_EXPORT_SREG(FS, &pCtx->fs);
4543 AssertRCReturn(rc, rc);
4544 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_FS);
4545 }
4546
4547 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GS)
4548 {
4549 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
4550 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4551 pVCpu->hm.s.vmx.RealMode.AttrGS.u = pCtx->gs.Attr.u;
4552 rc = HMVMX_EXPORT_SREG(GS, &pCtx->gs);
4553 AssertRCReturn(rc, rc);
4554 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GS);
4555 }
4556
4557#ifdef VBOX_STRICT
4558 hmR0VmxValidateSegmentRegs(pVCpu);
4559#endif
4560
4561 Log4Func(("CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pCtx->cs.Sel, pCtx->cs.u64Base,
4562 pCtx->cs.u32Limit, pCtx->cs.Attr.u));
4563 }
4564
4565 /*
4566 * Guest TR.
4567 */
4568 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_TR)
4569 {
4570 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_TR);
4571
4572 /*
4573 * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is
4574 * achieved using the interrupt redirection bitmap (all bits cleared to let the guest
4575 * handle INT-n's) in the TSS. See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
4576 */
4577 uint16_t u16Sel = 0;
4578 uint32_t u32Limit = 0;
4579 uint64_t u64Base = 0;
4580 uint32_t u32AccessRights = 0;
4581
4582 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4583 {
4584 u16Sel = pCtx->tr.Sel;
4585 u32Limit = pCtx->tr.u32Limit;
4586 u64Base = pCtx->tr.u64Base;
4587 u32AccessRights = pCtx->tr.Attr.u;
4588 }
4589 else
4590 {
4591 Assert(pVM->hm.s.vmx.pRealModeTSS);
4592 Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMCanExecuteGuest() -XXX- what about inner loop changes? */
4593
4594 /* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
4595 RTGCPHYS GCPhys;
4596 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
4597 AssertRCReturn(rc, rc);
4598
4599 X86DESCATTR DescAttr;
4600 DescAttr.u = 0;
4601 DescAttr.n.u1Present = 1;
4602 DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
4603
4604 u16Sel = 0;
4605 u32Limit = HM_VTX_TSS_SIZE;
4606 u64Base = GCPhys; /* in real-mode phys = virt. */
4607 u32AccessRights = DescAttr.u;
4608 }
4609
4610 /* Validate. */
4611 Assert(!(u16Sel & RT_BIT(2)));
4612 AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
4613 || (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
4614 AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
4615 Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
4616 Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
4617 Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
4618 Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
4619 Assert( (u32Limit & 0xfff) == 0xfff
4620 || !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
4621 Assert( !(pCtx->tr.u32Limit & 0xfff00000)
4622 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
4623
4624 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_TR_SEL, u16Sel);
4625 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit);
4626 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);
4627 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE, u64Base);
4628 AssertRCReturn(rc, rc);
4629
4630 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_TR);
4631 Log4Func(("TR base=%#RX64\n", pCtx->tr.u64Base));
4632 }
4633
4634 /*
4635 * Guest GDTR.
4636 */
4637 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GDTR)
4638 {
4639 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GDTR);
4640
4641 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
4642 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
4643 AssertRCReturn(rc, rc);
4644
4645 /* Validate. */
4646 Assert(!(pCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4647
4648 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GDTR);
4649 Log4Func(("GDTR base=%#RX64\n", pCtx->gdtr.pGdt));
4650 }
4651
4652 /*
4653 * Guest LDTR.
4654 */
4655 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_LDTR)
4656 {
4657 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_LDTR);
4658
4659 /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
4660 uint32_t u32Access = 0;
4661 if (!pCtx->ldtr.Attr.u)
4662 u32Access = X86DESCATTR_UNUSABLE;
4663 else
4664 u32Access = pCtx->ldtr.Attr.u;
4665
4666 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel);
4667 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit);
4668 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);
4669 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base);
4670 AssertRCReturn(rc, rc);
4671
4672 /* Validate. */
4673 if (!(u32Access & X86DESCATTR_UNUSABLE))
4674 {
4675 Assert(!(pCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
4676 Assert(pCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
4677 Assert(!pCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
4678 Assert(pCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
4679 Assert(!pCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
4680 Assert(!(pCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
4681 Assert( (pCtx->ldtr.u32Limit & 0xfff) == 0xfff
4682 || !pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
4683 Assert( !(pCtx->ldtr.u32Limit & 0xfff00000)
4684 || pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
4685 }
4686
4687 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_LDTR);
4688 Log4Func(("LDTR base=%#RX64\n", pCtx->ldtr.u64Base));
4689 }
4690
4691 /*
4692 * Guest IDTR.
4693 */
4694 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_IDTR)
4695 {
4696 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_IDTR);
4697
4698 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
4699 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
4700 AssertRCReturn(rc, rc);
4701
4702 /* Validate. */
4703 Assert(!(pCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4704
4705 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_IDTR);
4706 Log4Func(("IDTR base=%#RX64\n", pCtx->idtr.pIdt));
4707 }
4708
4709 return VINF_SUCCESS;
4710}
4711
4712
4713/**
4714 * Exports certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
4715 * areas.
4716 *
4717 * These MSRs will automatically be loaded to the host CPU on every successful
4718 * VM-entry and stored from the host CPU on every successful VM-exit. This also
4719 * creates/updates MSR slots for the host MSRs. The actual host MSR values are
4720 * -not- updated here for performance reasons. See hmR0VmxExportHostMsrs().
4721 *
4722 * Also exports the guest sysenter MSRs into the guest-state area in the VMCS.
4723 *
4724 * @returns VBox status code.
4725 * @param pVCpu The cross context virtual CPU structure.
4726 *
4727 * @remarks No-long-jump zone!!!
4728 */
4729static int hmR0VmxExportGuestMsrs(PVMCPU pVCpu)
4730{
4731 AssertPtr(pVCpu);
4732 AssertPtr(pVCpu->hm.s.vmx.pvGuestMsr);
4733
4734 /*
4735 * MSRs that we use the auto-load/store MSR area in the VMCS.
4736 * For 64-bit hosts, we load/restore them lazily, see hmR0VmxLazyLoadGuestMsrs().
4737 */
4738 PVM pVM = pVCpu->CTX_SUFF(pVM);
4739 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4740 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_GUEST_AUTO_MSRS)
4741 {
4742 if (pVM->hm.s.fAllow64BitGuests)
4743 {
4744#if HC_ARCH_BITS == 32
4745 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS | CPUMCTX_EXTRN_KERNEL_GS_BASE);
4746
4747 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_LSTAR, pCtx->msrLSTAR, false, NULL);
4748 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_STAR, pCtx->msrSTAR, false, NULL);
4749 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_SF_MASK, pCtx->msrSFMASK, false, NULL);
4750 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE, false, NULL);
4751 AssertRCReturn(rc, rc);
4752# ifdef LOG_ENABLED
4753 PCVMXAUTOMSR pMsr = (PCVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
4754 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cMsrs; i++, pMsr++)
4755 Log4Func(("MSR[%RU32]: u32Msr=%#RX32 u64Value=%#RX64\n", i, pMsr->u32Msr, pMsr->u64Value));
4756# endif
4757#endif
4758 }
4759 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_GUEST_AUTO_MSRS);
4760 }
4761
4762 /*
4763 * Guest Sysenter MSRs.
4764 * These flags are only set when MSR-bitmaps are not supported by the CPU and we cause
4765 * VM-exits on WRMSRs for these MSRs.
4766 */
4767 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
4768 {
4769 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4770
4771 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
4772 {
4773 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
4774 AssertRCReturn(rc, rc);
4775 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_CS_MSR);
4776 }
4777
4778 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
4779 {
4780 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
4781 AssertRCReturn(rc, rc);
4782 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
4783 }
4784
4785 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
4786 {
4787 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
4788 AssertRCReturn(rc, rc);
4789 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
4790 }
4791 }
4792
4793 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_EFER_MSR)
4794 {
4795 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
4796
4797 if (hmR0VmxShouldSwapEferMsr(pVCpu))
4798 {
4799 /*
4800 * If the CPU supports VMCS controls for swapping EFER, use it. Otherwise, we have no option
4801 * but to use the auto-load store MSR area in the VMCS for swapping EFER. See @bugref{7368}.
4802 */
4803 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
4804 {
4805 int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, pCtx->msrEFER);
4806 AssertRCReturn(rc,rc);
4807 Log4Func(("EFER=%#RX64\n", pCtx->msrEFER));
4808 }
4809 else
4810 {
4811 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_EFER, pCtx->msrEFER, false /* fUpdateHostMsr */,
4812 NULL /* pfAddedAndUpdated */);
4813 AssertRCReturn(rc, rc);
4814
4815 /* We need to intercept reads too, see @bugref{7386#c16}. */
4816 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
4817 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
4818 Log4Func(("MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", MSR_K6_EFER, pCtx->msrEFER,
4819 pVCpu->hm.s.vmx.cMsrs));
4820 }
4821 }
4822 else if (!pVM->hm.s.vmx.fSupportsVmcsEfer)
4823 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K6_EFER);
4824 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_EFER_MSR);
4825 }
4826
4827 return VINF_SUCCESS;
4828}
4829
4830
4831#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
4832/**
4833 * Check if guest state allows safe use of 32-bit switcher again.
4834 *
4835 * Segment bases and protected mode structures must be 32-bit addressable
4836 * because the 32-bit switcher will ignore high dword when writing these VMCS
4837 * fields. See @bugref{8432} for details.
4838 *
4839 * @returns true if safe, false if must continue to use the 64-bit switcher.
4840 * @param pCtx Pointer to the guest-CPU context.
4841 *
4842 * @remarks No-long-jump zone!!!
4843 */
4844static bool hmR0VmxIs32BitSwitcherSafe(PCCPUMCTX pCtx)
4845{
4846 if (pCtx->gdtr.pGdt & UINT64_C(0xffffffff00000000)) return false;
4847 if (pCtx->idtr.pIdt & UINT64_C(0xffffffff00000000)) return false;
4848 if (pCtx->ldtr.u64Base & UINT64_C(0xffffffff00000000)) return false;
4849 if (pCtx->tr.u64Base & UINT64_C(0xffffffff00000000)) return false;
4850 if (pCtx->es.u64Base & UINT64_C(0xffffffff00000000)) return false;
4851 if (pCtx->cs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4852 if (pCtx->ss.u64Base & UINT64_C(0xffffffff00000000)) return false;
4853 if (pCtx->ds.u64Base & UINT64_C(0xffffffff00000000)) return false;
4854 if (pCtx->fs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4855 if (pCtx->gs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4856
4857 /* All good, bases are 32-bit. */
4858 return true;
4859}
4860#endif
4861
4862
4863/**
4864 * Selects up the appropriate function to run guest code.
4865 *
4866 * @returns VBox status code.
4867 * @param pVCpu The cross context virtual CPU structure.
4868 *
4869 * @remarks No-long-jump zone!!!
4870 */
4871static int hmR0VmxSelectVMRunHandler(PVMCPU pVCpu)
4872{
4873 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4874 if (CPUMIsGuestInLongModeEx(pCtx))
4875 {
4876#ifndef VBOX_ENABLE_64_BITS_GUESTS
4877 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4878#endif
4879 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
4880#if HC_ARCH_BITS == 32
4881 /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
4882 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
4883 {
4884#ifdef VBOX_STRICT
4885 if (pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4886 {
4887 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4888 uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
4889 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4890 AssertMsg(fCtxChanged & ( HM_CHANGED_VMX_EXIT_CTLS
4891 | HM_CHANGED_VMX_ENTRY_CTLS
4892 | HM_CHANGED_GUEST_EFER_MSR), ("fCtxChanged=%#RX64\n", fCtxChanged));
4893 }
4894#endif
4895 pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
4896
4897 /* Mark that we've switched to 64-bit handler, we can't safely switch back to 32-bit for
4898 the rest of the VM run (until VM reset). See @bugref{8432#c7}. */
4899 pVCpu->hm.s.vmx.fSwitchedTo64on32 = true;
4900 Log4Func(("Selected 64-bit switcher\n"));
4901 }
4902#else
4903 /* 64-bit host. */
4904 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM64;
4905#endif
4906 }
4907 else
4908 {
4909 /* Guest is not in long mode, use the 32-bit handler. */
4910#if HC_ARCH_BITS == 32
4911 if ( pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32
4912 && !pVCpu->hm.s.vmx.fSwitchedTo64on32 /* If set, guest mode change does not imply switcher change. */
4913 && pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4914 {
4915# ifdef VBOX_STRICT
4916 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4917 uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
4918 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4919 AssertMsg(fCtxChanged & ( HM_CHANGED_VMX_EXIT_CTLS
4920 | HM_CHANGED_VMX_ENTRY_CTLS
4921 | HM_CHANGED_GUEST_EFER_MSR), ("fCtxChanged=%#RX64\n", fCtxChanged));
4922# endif
4923 }
4924# ifdef VBOX_ENABLE_64_BITS_GUESTS
4925 /*
4926 * Keep using the 64-bit switcher even though we're in 32-bit because of bad Intel
4927 * design, see @bugref{8432#c7}. If real-on-v86 mode is active, clear the 64-bit
4928 * switcher flag because now we know the guest is in a sane state where it's safe
4929 * to use the 32-bit switcher. Otherwise check the guest state if it's safe to use
4930 * the much faster 32-bit switcher again.
4931 */
4932 if (!pVCpu->hm.s.vmx.fSwitchedTo64on32)
4933 {
4934 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32)
4935 Log4Func(("Selected 32-bit switcher\n"));
4936 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4937 }
4938 else
4939 {
4940 Assert(pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64);
4941 if ( pVCpu->hm.s.vmx.RealMode.fRealOnV86Active
4942 || hmR0VmxIs32BitSwitcherSafe(pCtx))
4943 {
4944 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
4945 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4946 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR
4947 | HM_CHANGED_VMX_ENTRY_CTLS
4948 | HM_CHANGED_VMX_EXIT_CTLS
4949 | HM_CHANGED_HOST_CONTEXT);
4950 Log4Func(("Selected 32-bit switcher (safe)\n"));
4951 }
4952 }
4953# else
4954 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4955# endif
4956#else
4957 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4958#endif
4959 }
4960 Assert(pVCpu->hm.s.vmx.pfnStartVM);
4961 return VINF_SUCCESS;
4962}
4963
4964
4965/**
4966 * Wrapper for running the guest code in VT-x.
4967 *
4968 * @returns VBox status code, no informational status codes.
4969 * @param pVCpu The cross context virtual CPU structure.
4970 *
4971 * @remarks No-long-jump zone!!!
4972 */
4973DECLINLINE(int) hmR0VmxRunGuest(PVMCPU pVCpu)
4974{
4975 /* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4976 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4977 pCtx->fExtrn |= HMVMX_CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_HM;
4978
4979 /*
4980 * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4981 * floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4982 * callee-saved and thus the need for this XMM wrapper.
4983 *
4984 * See MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4985 */
4986 bool const fResumeVM = RT_BOOL(pVCpu->hm.s.vmx.fVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
4987 /** @todo Add stats for resume vs launch. */
4988 PVM pVM = pVCpu->CTX_SUFF(pVM);
4989#ifdef VBOX_WITH_KERNEL_USING_XMM
4990 int rc = hmR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VmcsBatchCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
4991#else
4992 int rc = pVCpu->hm.s.vmx.pfnStartVM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VmcsBatchCache, pVM, pVCpu);
4993#endif
4994 AssertMsg(rc <= VINF_SUCCESS, ("%Rrc\n", rc));
4995 return rc;
4996}
4997
4998
4999/**
5000 * Reports world-switch error and dumps some useful debug info.
5001 *
5002 * @param pVCpu The cross context virtual CPU structure.
5003 * @param rcVMRun The return code from VMLAUNCH/VMRESUME.
5004 * @param pVmxTransient Pointer to the VMX transient structure (only
5005 * exitReason updated).
5006 */
5007static void hmR0VmxReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun, PVMXTRANSIENT pVmxTransient)
5008{
5009 Assert(pVCpu);
5010 Assert(pVmxTransient);
5011 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
5012
5013 Log4Func(("VM-entry failure: %Rrc\n", rcVMRun));
5014 switch (rcVMRun)
5015 {
5016 case VERR_VMX_INVALID_VMXON_PTR:
5017 AssertFailed();
5018 break;
5019 case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
5020 case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
5021 {
5022 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
5023 rc |= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
5024 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
5025 AssertRC(rc);
5026
5027 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
5028 /* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
5029 Cannot do it here as we may have been long preempted. */
5030
5031#ifdef VBOX_STRICT
5032 Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
5033 pVmxTransient->uExitReason));
5034 Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQual));
5035 Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
5036 if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
5037 Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
5038 else
5039 Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
5040 Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
5041 Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
5042
5043 /* VMX control bits. */
5044 uint32_t u32Val;
5045 uint64_t u64Val;
5046 RTHCUINTREG uHCReg;
5047 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc);
5048 Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val));
5049 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc);
5050 Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val));
5051 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5052 {
5053 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);
5054 Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val));
5055 }
5056 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);
5057 Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val));
5058 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);
5059 Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val));
5060 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc);
5061 Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val));
5062 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc);
5063 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val));
5064 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc);
5065 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val));
5066 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc);
5067 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val));
5068 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc);
5069 Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val));
5070 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc);
5071 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val));
5072 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5073 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val));
5074 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5075 Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val));
5076 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc);
5077 Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val));
5078 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc);
5079 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val));
5080 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc);
5081 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val));
5082 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
5083 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
5084 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
5085 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5086 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
5087 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
5088 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
5089 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5090 if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
5091 {
5092 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
5093 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
5094 }
5095
5096 /* Guest bits. */
5097 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);
5098 Log4(("Old Guest Rip %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rip, u64Val));
5099 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);
5100 Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rsp, u64Val));
5101 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);
5102 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pVCpu->cpum.GstCtx.eflags.u32, u32Val));
5103 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid)
5104 {
5105 rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val); AssertRC(rc);
5106 Log4(("VMX_VMCS16_VPID %u\n", u32Val));
5107 }
5108
5109 /* Host bits. */
5110 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);
5111 Log4(("Host CR0 %#RHr\n", uHCReg));
5112 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);
5113 Log4(("Host CR3 %#RHr\n", uHCReg));
5114 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);
5115 Log4(("Host CR4 %#RHr\n", uHCReg));
5116
5117 RTGDTR HostGdtr;
5118 PCX86DESCHC pDesc;
5119 ASMGetGDTR(&HostGdtr);
5120 rc = VMXReadVmcs32(VMX_VMCS16_HOST_CS_SEL, &u32Val); AssertRC(rc);
5121 Log4(("Host CS %#08x\n", u32Val));
5122 if (u32Val < HostGdtr.cbGdt)
5123 {
5124 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5125 hmR0DumpDescriptor(pDesc, u32Val, "CS: ");
5126 }
5127
5128 rc = VMXReadVmcs32(VMX_VMCS16_HOST_DS_SEL, &u32Val); AssertRC(rc);
5129 Log4(("Host DS %#08x\n", u32Val));
5130 if (u32Val < HostGdtr.cbGdt)
5131 {
5132 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5133 hmR0DumpDescriptor(pDesc, u32Val, "DS: ");
5134 }
5135
5136 rc = VMXReadVmcs32(VMX_VMCS16_HOST_ES_SEL, &u32Val); AssertRC(rc);
5137 Log4(("Host ES %#08x\n", u32Val));
5138 if (u32Val < HostGdtr.cbGdt)
5139 {
5140 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5141 hmR0DumpDescriptor(pDesc, u32Val, "ES: ");
5142 }
5143
5144 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FS_SEL, &u32Val); AssertRC(rc);
5145 Log4(("Host FS %#08x\n", u32Val));
5146 if (u32Val < HostGdtr.cbGdt)
5147 {
5148 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5149 hmR0DumpDescriptor(pDesc, u32Val, "FS: ");
5150 }
5151
5152 rc = VMXReadVmcs32(VMX_VMCS16_HOST_GS_SEL, &u32Val); AssertRC(rc);
5153 Log4(("Host GS %#08x\n", u32Val));
5154 if (u32Val < HostGdtr.cbGdt)
5155 {
5156 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5157 hmR0DumpDescriptor(pDesc, u32Val, "GS: ");
5158 }
5159
5160 rc = VMXReadVmcs32(VMX_VMCS16_HOST_SS_SEL, &u32Val); AssertRC(rc);
5161 Log4(("Host SS %#08x\n", u32Val));
5162 if (u32Val < HostGdtr.cbGdt)
5163 {
5164 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5165 hmR0DumpDescriptor(pDesc, u32Val, "SS: ");
5166 }
5167
5168 rc = VMXReadVmcs32(VMX_VMCS16_HOST_TR_SEL, &u32Val); AssertRC(rc);
5169 Log4(("Host TR %#08x\n", u32Val));
5170 if (u32Val < HostGdtr.cbGdt)
5171 {
5172 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5173 hmR0DumpDescriptor(pDesc, u32Val, "TR: ");
5174 }
5175
5176 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);
5177 Log4(("Host TR Base %#RHv\n", uHCReg));
5178 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);
5179 Log4(("Host GDTR Base %#RHv\n", uHCReg));
5180 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);
5181 Log4(("Host IDTR Base %#RHv\n", uHCReg));
5182 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);
5183 Log4(("Host SYSENTER CS %#08x\n", u32Val));
5184 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);
5185 Log4(("Host SYSENTER EIP %#RHv\n", uHCReg));
5186 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);
5187 Log4(("Host SYSENTER ESP %#RHv\n", uHCReg));
5188 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);
5189 Log4(("Host RSP %#RHv\n", uHCReg));
5190 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);
5191 Log4(("Host RIP %#RHv\n", uHCReg));
5192# if HC_ARCH_BITS == 64
5193 Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
5194 Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
5195 Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
5196 Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
5197 Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
5198 Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
5199# endif
5200#endif /* VBOX_STRICT */
5201 break;
5202 }
5203
5204 default:
5205 /* Impossible */
5206 AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
5207 break;
5208 }
5209}
5210
5211
5212#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
5213#ifndef VMX_USE_CACHED_VMCS_ACCESSES
5214# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
5215#endif
5216#ifdef VBOX_STRICT
5217static bool hmR0VmxIsValidWriteField(uint32_t idxField)
5218{
5219 switch (idxField)
5220 {
5221 case VMX_VMCS_GUEST_RIP:
5222 case VMX_VMCS_GUEST_RSP:
5223 case VMX_VMCS_GUEST_SYSENTER_EIP:
5224 case VMX_VMCS_GUEST_SYSENTER_ESP:
5225 case VMX_VMCS_GUEST_GDTR_BASE:
5226 case VMX_VMCS_GUEST_IDTR_BASE:
5227 case VMX_VMCS_GUEST_CS_BASE:
5228 case VMX_VMCS_GUEST_DS_BASE:
5229 case VMX_VMCS_GUEST_ES_BASE:
5230 case VMX_VMCS_GUEST_FS_BASE:
5231 case VMX_VMCS_GUEST_GS_BASE:
5232 case VMX_VMCS_GUEST_SS_BASE:
5233 case VMX_VMCS_GUEST_LDTR_BASE:
5234 case VMX_VMCS_GUEST_TR_BASE:
5235 case VMX_VMCS_GUEST_CR3:
5236 return true;
5237 }
5238 return false;
5239}
5240
5241static bool hmR0VmxIsValidReadField(uint32_t idxField)
5242{
5243 switch (idxField)
5244 {
5245 /* Read-only fields. */
5246 case VMX_VMCS_RO_EXIT_QUALIFICATION:
5247 return true;
5248 }
5249 /* Remaining readable fields should also be writable. */
5250 return hmR0VmxIsValidWriteField(idxField);
5251}
5252#endif /* VBOX_STRICT */
5253
5254
5255/**
5256 * Executes the specified handler in 64-bit mode.
5257 *
5258 * @returns VBox status code (no informational status codes).
5259 * @param pVCpu The cross context virtual CPU structure.
5260 * @param enmOp The operation to perform.
5261 * @param cParams Number of parameters.
5262 * @param paParam Array of 32-bit parameters.
5263 */
5264VMMR0DECL(int) VMXR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
5265{
5266 PVM pVM = pVCpu->CTX_SUFF(pVM);
5267 AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
5268 Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
5269 Assert(pVCpu->hm.s.vmx.VmcsBatchCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VmcsBatchCache.Write.aField));
5270 Assert(pVCpu->hm.s.vmx.VmcsBatchCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VmcsBatchCache.Read.aField));
5271
5272#ifdef VBOX_STRICT
5273 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VmcsBatchCache.Write.cValidEntries; i++)
5274 Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VmcsBatchCache.Write.aField[i]));
5275
5276 for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VmcsBatchCache.Read.cValidEntries; i++)
5277 Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VmcsBatchCache.Read.aField[i]));
5278#endif
5279
5280 /* Disable interrupts. */
5281 RTCCUINTREG fOldEFlags = ASMIntDisableFlags();
5282
5283#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
5284 RTCPUID idHostCpu = RTMpCpuId();
5285 CPUMR0SetLApic(pVCpu, idHostCpu);
5286#endif
5287
5288 PCHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
5289 RTHCPHYS HCPhysCpuPage = pHostCpu->HCPhysMemObj;
5290
5291 /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
5292 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5293 pVCpu->hm.s.vmx.fVmcsState = HMVMX_VMCS_STATE_CLEAR;
5294
5295 /* Leave VMX Root Mode. */
5296 VMXDisable();
5297
5298 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5299
5300 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
5301 CPUMSetHyperEIP(pVCpu, enmOp);
5302 for (int i = (int)cParams - 1; i >= 0; i--)
5303 CPUMPushHyper(pVCpu, paParam[i]);
5304
5305 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
5306
5307 /* Call the switcher. */
5308 int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
5309 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
5310
5311 /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
5312 /* Make sure the VMX instructions don't cause #UD faults. */
5313 SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
5314
5315 /* Re-enter VMX Root Mode */
5316 int rc2 = VMXEnable(HCPhysCpuPage);
5317 if (RT_FAILURE(rc2))
5318 {
5319 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5320 ASMSetFlags(fOldEFlags);
5321 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
5322 return rc2;
5323 }
5324
5325 rc2 = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5326 AssertRC(rc2);
5327 pVCpu->hm.s.vmx.fVmcsState = HMVMX_VMCS_STATE_ACTIVE;
5328 Assert(!(ASMGetFlags() & X86_EFL_IF));
5329 ASMSetFlags(fOldEFlags);
5330 return rc;
5331}
5332
5333
5334/**
5335 * Prepares for and executes VMLAUNCH (64-bit guests) for 32-bit hosts
5336 * supporting 64-bit guests.
5337 *
5338 * @returns VBox status code.
5339 * @param fResume Whether to VMLAUNCH or VMRESUME.
5340 * @param pCtx Pointer to the guest-CPU context.
5341 * @param pCache Pointer to the VMCS cache.
5342 * @param pVM The cross context VM structure.
5343 * @param pVCpu The cross context virtual CPU structure.
5344 */
5345DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSBATCHCACHE pCache, PVM pVM, PVMCPU pVCpu)
5346{
5347 NOREF(fResume);
5348
5349 PCHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
5350 RTHCPHYS const HCPhysCpuPage = pHostCpu->HCPhysMemObj;
5351
5352#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5353 pCache->uPos = 1;
5354 pCache->interPD = PGMGetInterPaeCR3(pVM);
5355 pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
5356#endif
5357
5358#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5359 pCache->TestIn.HCPhysCpuPage = 0;
5360 pCache->TestIn.HCPhysVmcs = 0;
5361 pCache->TestIn.pCache = 0;
5362 pCache->TestOut.HCPhysVmcs = 0;
5363 pCache->TestOut.pCache = 0;
5364 pCache->TestOut.pCtx = 0;
5365 pCache->TestOut.eflags = 0;
5366#else
5367 NOREF(pCache);
5368#endif
5369
5370 uint32_t aParam[10];
5371 aParam[0] = RT_LO_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
5372 aParam[1] = RT_HI_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Hi. */
5373 aParam[2] = RT_LO_U32(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
5374 aParam[3] = RT_HI_U32(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Hi. */
5375 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VmcsBatchCache);
5376 aParam[5] = 0;
5377 aParam[6] = VM_RC_ADDR(pVM, pVM);
5378 aParam[7] = 0;
5379 aParam[8] = VM_RC_ADDR(pVM, pVCpu);
5380 aParam[9] = 0;
5381
5382#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5383 pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
5384 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
5385#endif
5386 int rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_VMXRCStartVM64, RT_ELEMENTS(aParam), &aParam[0]);
5387
5388#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5389 Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
5390 Assert(pCtx->dr[4] == 10);
5391 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
5392#endif
5393
5394#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5395 AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
5396 AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5397 pVCpu->hm.s.vmx.HCPhysVmcs));
5398 AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5399 pCache->TestOut.HCPhysVmcs));
5400 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
5401 pCache->TestOut.pCache));
5402 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VmcsBatchCache),
5403 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VmcsBatchCache)));
5404 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
5405 pCache->TestOut.pCtx));
5406 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
5407#endif
5408 NOREF(pCtx);
5409 return rc;
5410}
5411
5412
5413/**
5414 * Initialize the VMCS-Read cache.
5415 *
5416 * The VMCS cache is used for 32-bit hosts running 64-bit guests (except 32-bit
5417 * Darwin which runs with 64-bit paging in 32-bit mode) for 64-bit fields that
5418 * cannot be accessed in 32-bit mode. Some 64-bit fields -can- be accessed
5419 * (those that have a 32-bit FULL & HIGH part).
5420 *
5421 * @returns VBox status code.
5422 * @param pVCpu The cross context virtual CPU structure.
5423 */
5424static int hmR0VmxInitVmcsReadCache(PVMCPU pVCpu)
5425{
5426#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \
5427 do { \
5428 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
5429 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
5430 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
5431 ++cReadFields; \
5432 } while (0)
5433
5434 PVMXVMCSBATCHCACHE pCache = &pVCpu->hm.s.vmx.VmcsBatchCache;
5435 uint32_t cReadFields = 0;
5436
5437 /*
5438 * Don't remove the #if 0'd fields in this code. They're listed here for consistency
5439 * and serve to indicate exceptions to the rules.
5440 */
5441
5442 /* Guest-natural selector base fields. */
5443#if 0
5444 /* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */
5445 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR0);
5446 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR4);
5447#endif
5448 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_ES_BASE);
5449 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CS_BASE);
5450 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SS_BASE);
5451 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DS_BASE);
5452 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_FS_BASE);
5453 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GS_BASE);
5454 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_LDTR_BASE);
5455 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_TR_BASE);
5456 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
5457 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
5458 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
5459 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
5460#if 0
5461 /* Unused natural width guest-state fields. */
5462 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS);
5463 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3); /* Handled in Nested Paging case */
5464#endif
5465 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
5466 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
5467
5468 /* 64-bit guest-state fields; unused as we use two 32-bit VMREADs for
5469 these 64-bit fields (using "FULL" and "HIGH" fields). */
5470#if 0
5471 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL);
5472 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_DEBUGCTL_FULL);
5473 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PAT_FULL);
5474 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_EFER_FULL);
5475 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL);
5476 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE0_FULL);
5477 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE1_FULL);
5478 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE2_FULL);
5479 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE3_FULL);
5480#endif
5481
5482 /* Natural width guest-state fields. */
5483 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
5484 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_GUEST_LINEAR_ADDR);
5485
5486 if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
5487 {
5488 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
5489 AssertMsg(cReadFields == VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields,
5490 VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX));
5491 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
5492 }
5493 else
5494 {
5495 AssertMsg(cReadFields == VMX_VMCS_MAX_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields, VMX_VMCS_MAX_CACHE_IDX));
5496 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
5497 }
5498
5499#undef VMXLOCAL_INIT_READ_CACHE_FIELD
5500 return VINF_SUCCESS;
5501}
5502
5503
5504/**
5505 * Writes a field into the VMCS. This can either directly invoke a VMWRITE or
5506 * queue up the VMWRITE by using the VMCS write cache (on 32-bit hosts, except
5507 * darwin, running 64-bit guests).
5508 *
5509 * @returns VBox status code.
5510 * @param pVCpu The cross context virtual CPU structure.
5511 * @param idxField The VMCS field encoding.
5512 * @param u64Val 16, 32 or 64-bit value.
5513 */
5514VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5515{
5516 int rc;
5517 switch (idxField)
5518 {
5519 /*
5520 * These fields consists of a "FULL" and a "HIGH" part which can be written to individually.
5521 */
5522 /* 64-bit Control fields. */
5523 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
5524 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
5525 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
5526 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
5527 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
5528 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
5529 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
5530 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
5531 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
5532 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
5533 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
5534 case VMX_VMCS64_CTRL_EPTP_FULL:
5535 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
5536 /* 64-bit Guest-state fields. */
5537 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
5538 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
5539 case VMX_VMCS64_GUEST_PAT_FULL:
5540 case VMX_VMCS64_GUEST_EFER_FULL:
5541 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
5542 case VMX_VMCS64_GUEST_PDPTE0_FULL:
5543 case VMX_VMCS64_GUEST_PDPTE1_FULL:
5544 case VMX_VMCS64_GUEST_PDPTE2_FULL:
5545 case VMX_VMCS64_GUEST_PDPTE3_FULL:
5546 /* 64-bit Host-state fields. */
5547 case VMX_VMCS64_HOST_PAT_FULL:
5548 case VMX_VMCS64_HOST_EFER_FULL:
5549 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
5550 {
5551 rc = VMXWriteVmcs32(idxField, RT_LO_U32(u64Val));
5552 rc |= VMXWriteVmcs32(idxField + 1, RT_HI_U32(u64Val));
5553 break;
5554 }
5555
5556 /*
5557 * These fields do not have high and low parts. Queue up the VMWRITE by using the VMCS write-cache (for 64-bit
5558 * values). When we switch the host to 64-bit mode for running 64-bit guests, these VMWRITEs get executed then.
5559 */
5560 /* Natural-width Guest-state fields. */
5561 case VMX_VMCS_GUEST_CR3:
5562 case VMX_VMCS_GUEST_ES_BASE:
5563 case VMX_VMCS_GUEST_CS_BASE:
5564 case VMX_VMCS_GUEST_SS_BASE:
5565 case VMX_VMCS_GUEST_DS_BASE:
5566 case VMX_VMCS_GUEST_FS_BASE:
5567 case VMX_VMCS_GUEST_GS_BASE:
5568 case VMX_VMCS_GUEST_LDTR_BASE:
5569 case VMX_VMCS_GUEST_TR_BASE:
5570 case VMX_VMCS_GUEST_GDTR_BASE:
5571 case VMX_VMCS_GUEST_IDTR_BASE:
5572 case VMX_VMCS_GUEST_RSP:
5573 case VMX_VMCS_GUEST_RIP:
5574 case VMX_VMCS_GUEST_SYSENTER_ESP:
5575 case VMX_VMCS_GUEST_SYSENTER_EIP:
5576 {
5577 if (!(RT_HI_U32(u64Val)))
5578 {
5579 /* If this field is 64-bit, VT-x will zero out the top bits. */
5580 rc = VMXWriteVmcs32(idxField, RT_LO_U32(u64Val));
5581 }
5582 else
5583 {
5584 /* Assert that only the 32->64 switcher case should ever come here. */
5585 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests);
5586 rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
5587 }
5588 break;
5589 }
5590
5591 default:
5592 {
5593 AssertMsgFailed(("VMXWriteVmcs64Ex: Invalid field %#RX32 (pVCpu=%p u64Val=%#RX64)\n", idxField, pVCpu, u64Val));
5594 rc = VERR_INVALID_PARAMETER;
5595 break;
5596 }
5597 }
5598 AssertRCReturn(rc, rc);
5599 return rc;
5600}
5601
5602
5603/**
5604 * Queue up a VMWRITE by using the VMCS write cache.
5605 * This is only used on 32-bit hosts (except darwin) for 64-bit guests.
5606 *
5607 * @param pVCpu The cross context virtual CPU structure.
5608 * @param idxField The VMCS field encoding.
5609 * @param u64Val 16, 32 or 64-bit value.
5610 */
5611VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5612{
5613 AssertPtr(pVCpu);
5614 PVMXVMCSBATCHCACHE pCache = &pVCpu->hm.s.vmx.VmcsBatchCache;
5615
5616 AssertMsgReturn(pCache->Write.cValidEntries < VMX_VMCS_BATCH_CACHE_MAX_ENTRY - 1,
5617 ("entries=%u\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
5618
5619 /* Make sure there are no duplicates. */
5620 for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
5621 {
5622 if (pCache->Write.aField[i] == idxField)
5623 {
5624 pCache->Write.aFieldVal[i] = u64Val;
5625 return VINF_SUCCESS;
5626 }
5627 }
5628
5629 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
5630 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
5631 pCache->Write.cValidEntries++;
5632 return VINF_SUCCESS;
5633}
5634#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
5635
5636
5637/**
5638 * Sets up the usage of TSC-offsetting and updates the VMCS.
5639 *
5640 * If offsetting is not possible, cause VM-exits on RDTSC(P)s. Also sets up the
5641 * VMX preemption timer.
5642 *
5643 * @returns VBox status code.
5644 * @param pVCpu The cross context virtual CPU structure.
5645 *
5646 * @remarks No-long-jump zone!!!
5647 */
5648static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVMCPU pVCpu)
5649{
5650 bool fOffsettedTsc;
5651 bool fParavirtTsc;
5652 PVM pVM = pVCpu->CTX_SUFF(pVM);
5653 uint64_t uTscOffset;
5654 if (pVM->hm.s.vmx.fUsePreemptTimer)
5655 {
5656 uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &uTscOffset, &fOffsettedTsc, &fParavirtTsc);
5657
5658 /* Make sure the returned values have sane upper and lower boundaries. */
5659 uint64_t u64CpuHz = SUPGetCpuHzFromGipBySetIndex(g_pSUPGlobalInfoPage, pVCpu->iHostCpuSet);
5660 cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second */
5661 cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
5662 cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
5663
5664 uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
5665 int rc = VMXWriteVmcs32(VMX_VMCS32_PREEMPT_TIMER_VALUE, cPreemptionTickCount);
5666 AssertRC(rc);
5667 }
5668 else
5669 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
5670
5671 if (fParavirtTsc)
5672 {
5673 /* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
5674 information before every VM-entry, hence disable it for performance sake. */
5675#if 0
5676 int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
5677 AssertRC(rc);
5678#endif
5679 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
5680 }
5681
5682 uint32_t uProcCtls = pVCpu->hm.s.vmx.Ctls.u32ProcCtls;
5683 if ( fOffsettedTsc
5684 && RT_LIKELY(!pVCpu->hm.s.fDebugWantRdTscExit))
5685 {
5686 if (pVCpu->hm.s.vmx.Ctls.u64TscOffset != uTscOffset)
5687 {
5688 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, uTscOffset);
5689 AssertRC(rc);
5690 pVCpu->hm.s.vmx.Ctls.u64TscOffset = uTscOffset;
5691 }
5692
5693 if (uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT)
5694 {
5695 uProcCtls &= ~VMX_PROC_CTLS_RDTSC_EXIT;
5696 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
5697 AssertRC(rc);
5698 pVCpu->hm.s.vmx.Ctls.u32ProcCtls = uProcCtls;
5699 }
5700 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
5701 }
5702 else
5703 {
5704 /* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
5705 if (!(uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
5706 {
5707 uProcCtls |= VMX_PROC_CTLS_RDTSC_EXIT;
5708 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
5709 AssertRC(rc);
5710 pVCpu->hm.s.vmx.Ctls.u32ProcCtls = uProcCtls;
5711 }
5712 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
5713 }
5714}
5715
5716
5717/**
5718 * Gets the IEM exception flags for the specified vector and IDT vectoring /
5719 * VM-exit interruption info type.
5720 *
5721 * @returns The IEM exception flags.
5722 * @param uVector The event vector.
5723 * @param uVmxVectorType The VMX event type.
5724 *
5725 * @remarks This function currently only constructs flags required for
5726 * IEMEvaluateRecursiveXcpt and not the complete flags (e.g, error-code
5727 * and CR2 aspects of an exception are not included).
5728 */
5729static uint32_t hmR0VmxGetIemXcptFlags(uint8_t uVector, uint32_t uVmxVectorType)
5730{
5731 uint32_t fIemXcptFlags;
5732 switch (uVmxVectorType)
5733 {
5734 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
5735 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
5736 fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5737 break;
5738
5739 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
5740 fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5741 break;
5742
5743 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
5744 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT | IEM_XCPT_FLAGS_ICEBP_INSTR;
5745 break;
5746
5747 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT:
5748 {
5749 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5750 if (uVector == X86_XCPT_BP)
5751 fIemXcptFlags |= IEM_XCPT_FLAGS_BP_INSTR;
5752 else if (uVector == X86_XCPT_OF)
5753 fIemXcptFlags |= IEM_XCPT_FLAGS_OF_INSTR;
5754 else
5755 {
5756 fIemXcptFlags = 0;
5757 AssertMsgFailed(("Unexpected vector for software int. uVector=%#x", uVector));
5758 }
5759 break;
5760 }
5761
5762 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
5763 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5764 break;
5765
5766 default:
5767 fIemXcptFlags = 0;
5768 AssertMsgFailed(("Unexpected vector type! uVmxVectorType=%#x uVector=%#x", uVmxVectorType, uVector));
5769 break;
5770 }
5771 return fIemXcptFlags;
5772}
5773
5774
5775/**
5776 * Sets an event as a pending event to be injected into the guest.
5777 *
5778 * @param pVCpu The cross context virtual CPU structure.
5779 * @param u32IntInfo The VM-entry interruption-information field.
5780 * @param cbInstr The VM-entry instruction length in bytes (for software
5781 * interrupts, exceptions and privileged software
5782 * exceptions).
5783 * @param u32ErrCode The VM-entry exception error code.
5784 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a
5785 * page-fault.
5786 *
5787 * @remarks Statistics counter assumes this is a guest event being injected or
5788 * re-injected into the guest, i.e. 'StatInjectPendingReflect' is
5789 * always incremented.
5790 */
5791DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
5792 RTGCUINTPTR GCPtrFaultAddress)
5793{
5794 Assert(!pVCpu->hm.s.Event.fPending);
5795 pVCpu->hm.s.Event.fPending = true;
5796 pVCpu->hm.s.Event.u64IntInfo = u32IntInfo;
5797 pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
5798 pVCpu->hm.s.Event.cbInstr = cbInstr;
5799 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
5800}
5801
5802
5803/**
5804 * Sets a double-fault (\#DF) exception as pending-for-injection into the VM.
5805 *
5806 * @param pVCpu The cross context virtual CPU structure.
5807 */
5808DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPU pVCpu)
5809{
5810 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DF)
5811 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5812 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5813 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5814 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5815}
5816
5817
5818/**
5819 * Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
5820 *
5821 * @param pVCpu The cross context virtual CPU structure.
5822 */
5823DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPU pVCpu)
5824{
5825 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_UD)
5826 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5827 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
5828 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5829 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5830}
5831
5832
5833/**
5834 * Sets a debug (\#DB) exception as pending-for-injection into the VM.
5835 *
5836 * @param pVCpu The cross context virtual CPU structure.
5837 */
5838DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPU pVCpu)
5839{
5840 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
5841 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5842 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
5843 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5844 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5845}
5846
5847
5848#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5849/**
5850 * Sets a general-protection (\#GP) exception as pending-for-injection into the VM.
5851 *
5852 * @param pVCpu The cross context virtual CPU structure.
5853 * @param u32ErrCode The error code for the general-protection exception.
5854 */
5855DECLINLINE(void) hmR0VmxSetPendingXcptGP(PVMCPU pVCpu, uint32_t u32ErrCode)
5856{
5857 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_GP)
5858 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5859 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5860 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5861 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrCode, 0 /* GCPtrFaultAddress */);
5862}
5863
5864
5865/**
5866 * Sets a stack (\#SS) exception as pending-for-injection into the VM.
5867 *
5868 * @param pVCpu The cross context virtual CPU structure.
5869 * @param u32ErrCode The error code for the stack exception.
5870 */
5871DECLINLINE(void) hmR0VmxSetPendingXcptSS(PVMCPU pVCpu, uint32_t u32ErrCode)
5872{
5873 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_SS)
5874 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5875 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5876 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5877 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrCode, 0 /* GCPtrFaultAddress */);
5878}
5879
5880
5881/**
5882 * Decodes the memory operand of an instruction that caused a VM-exit.
5883 *
5884 * The VM-exit qualification field provides the displacement field for memory
5885 * operand instructions, if any.
5886 *
5887 * @returns Strict VBox status code (i.e. informational status codes too).
5888 * @retval VINF_SUCCESS if the operand was successfully decoded.
5889 * @retval VINF_HM_PENDING_XCPT if an exception was raised while decoding the
5890 * operand.
5891 * @param pVCpu The cross context virtual CPU structure.
5892 * @param uExitInstrInfo The VM-exit instruction information field.
5893 * @param enmMemAccess The memory operand's access type (read or write).
5894 * @param GCPtrDisp The instruction displacement field, if any. For
5895 * RIP-relative addressing pass RIP + displacement here.
5896 * @param pGCPtrMem Where to store the effective destination memory address.
5897 */
5898static VBOXSTRICTRC hmR0VmxDecodeMemOperand(PVMCPU pVCpu, uint32_t uExitInstrInfo, RTGCPTR GCPtrDisp, VMXMEMACCESS enmMemAccess,
5899 PRTGCPTR pGCPtrMem)
5900{
5901 Assert(pGCPtrMem);
5902 Assert(!CPUMIsGuestInRealOrV86Mode(pVCpu));
5903 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_EFER
5904 | CPUMCTX_EXTRN_CR0);
5905
5906 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
5907 static uint64_t const s_auAccessSizeMasks[] = { sizeof(uint16_t), sizeof(uint32_t), sizeof(uint64_t) };
5908 AssertCompile(RT_ELEMENTS(s_auAccessSizeMasks) == RT_ELEMENTS(s_auAddrSizeMasks));
5909
5910 VMXEXITINSTRINFO ExitInstrInfo;
5911 ExitInstrInfo.u = uExitInstrInfo;
5912 uint8_t const uAddrSize = ExitInstrInfo.All.u3AddrSize;
5913 uint8_t const iSegReg = ExitInstrInfo.All.iSegReg;
5914 bool const fIdxRegValid = !ExitInstrInfo.All.fIdxRegInvalid;
5915 uint8_t const iIdxReg = ExitInstrInfo.All.iIdxReg;
5916 uint8_t const uScale = ExitInstrInfo.All.u2Scaling;
5917 bool const fBaseRegValid = !ExitInstrInfo.All.fBaseRegInvalid;
5918 uint8_t const iBaseReg = ExitInstrInfo.All.iBaseReg;
5919 bool const fIsMemOperand = !ExitInstrInfo.All.fIsRegOperand;
5920 bool const fIsLongMode = CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx);
5921
5922 /*
5923 * Validate instruction information.
5924 * This shouldn't happen on real hardware but useful while testing our nested hardware-virtualization code.
5925 */
5926 AssertLogRelMsgReturn(uAddrSize < RT_ELEMENTS(s_auAddrSizeMasks),
5927 ("Invalid address size. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_1);
5928 AssertLogRelMsgReturn(iSegReg < X86_SREG_COUNT,
5929 ("Invalid segment register. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_2);
5930 AssertLogRelMsgReturn(fIsMemOperand,
5931 ("Expected memory operand. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_3);
5932
5933 /*
5934 * Compute the complete effective address.
5935 *
5936 * See AMD instruction spec. 1.4.2 "SIB Byte Format"
5937 * See AMD spec. 4.5.2 "Segment Registers".
5938 */
5939 RTGCPTR GCPtrMem = GCPtrDisp;
5940 if (fBaseRegValid)
5941 GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iBaseReg].u64;
5942 if (fIdxRegValid)
5943 GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iIdxReg].u64 << uScale;
5944
5945 RTGCPTR const GCPtrOff = GCPtrMem;
5946 if ( !fIsLongMode
5947 || iSegReg >= X86_SREG_FS)
5948 GCPtrMem += pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
5949 GCPtrMem &= s_auAddrSizeMasks[uAddrSize];
5950
5951 /*
5952 * Validate effective address.
5953 * See AMD spec. 4.5.3 "Segment Registers in 64-Bit Mode".
5954 */
5955 uint8_t const cbAccess = s_auAccessSizeMasks[uAddrSize];
5956 Assert(cbAccess > 0);
5957 if (fIsLongMode)
5958 {
5959 if (X86_IS_CANONICAL(GCPtrMem))
5960 {
5961 *pGCPtrMem = GCPtrMem;
5962 return VINF_SUCCESS;
5963 }
5964
5965 /** @todo r=ramshankar: We should probably raise \#SS or \#GP. See AMD spec. 4.12.2
5966 * "Data Limit Checks in 64-bit Mode". */
5967 Log4Func(("Long mode effective address is not canonical GCPtrMem=%#RX64\n", GCPtrMem));
5968 hmR0VmxSetPendingXcptGP(pVCpu, 0);
5969 return VINF_HM_PENDING_XCPT;
5970 }
5971
5972 /*
5973 * This is a watered down version of iemMemApplySegment().
5974 * Parts that are not applicable for VMX instructions like real-or-v8086 mode
5975 * and segment CPL/DPL checks are skipped.
5976 */
5977 RTGCPTR32 const GCPtrFirst32 = (RTGCPTR32)GCPtrOff;
5978 RTGCPTR32 const GCPtrLast32 = GCPtrFirst32 + cbAccess - 1;
5979 PCCPUMSELREG pSel = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
5980
5981 /* Check if the segment is present and usable. */
5982 if ( pSel->Attr.n.u1Present
5983 && !pSel->Attr.n.u1Unusable)
5984 {
5985 Assert(pSel->Attr.n.u1DescType);
5986 if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_CODE))
5987 {
5988 /* Check permissions for the data segment. */
5989 if ( enmMemAccess == VMXMEMACCESS_WRITE
5990 && !(pSel->Attr.n.u4Type & X86_SEL_TYPE_WRITE))
5991 {
5992 Log4Func(("Data segment access invalid. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
5993 hmR0VmxSetPendingXcptGP(pVCpu, iSegReg);
5994 return VINF_HM_PENDING_XCPT;
5995 }
5996
5997 /* Check limits if it's a normal data segment. */
5998 if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_DOWN))
5999 {
6000 if ( GCPtrFirst32 > pSel->u32Limit
6001 || GCPtrLast32 > pSel->u32Limit)
6002 {
6003 Log4Func(("Data segment limit exceeded."
6004 "iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
6005 GCPtrLast32, pSel->u32Limit));
6006 if (iSegReg == X86_SREG_SS)
6007 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6008 else
6009 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6010 return VINF_HM_PENDING_XCPT;
6011 }
6012 }
6013 else
6014 {
6015 /* Check limits if it's an expand-down data segment.
6016 Note! The upper boundary is defined by the B bit, not the G bit! */
6017 if ( GCPtrFirst32 < pSel->u32Limit + UINT32_C(1)
6018 || GCPtrLast32 > (pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT32_C(0xffff)))
6019 {
6020 Log4Func(("Expand-down data segment limit exceeded."
6021 "iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
6022 GCPtrLast32, pSel->u32Limit));
6023 if (iSegReg == X86_SREG_SS)
6024 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6025 else
6026 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6027 return VINF_HM_PENDING_XCPT;
6028 }
6029 }
6030 }
6031 else
6032 {
6033 /* Check permissions for the code segment. */
6034 if ( enmMemAccess == VMXMEMACCESS_WRITE
6035 || ( enmMemAccess == VMXMEMACCESS_READ
6036 && !(pSel->Attr.n.u4Type & X86_SEL_TYPE_READ)))
6037 {
6038 Log4Func(("Code segment access invalid. Attr=%#RX32\n", pSel->Attr.u));
6039 Assert(!CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx));
6040 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6041 return VINF_HM_PENDING_XCPT;
6042 }
6043
6044 /* Check limits for the code segment (normal/expand-down not applicable for code segments). */
6045 if ( GCPtrFirst32 > pSel->u32Limit
6046 || GCPtrLast32 > pSel->u32Limit)
6047 {
6048 Log4Func(("Code segment limit exceeded. GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n",
6049 GCPtrFirst32, GCPtrLast32, pSel->u32Limit));
6050 if (iSegReg == X86_SREG_SS)
6051 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6052 else
6053 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6054 return VINF_HM_PENDING_XCPT;
6055 }
6056 }
6057 }
6058 else
6059 {
6060 Log4Func(("Not present or unusable segment. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
6061 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6062 return VINF_HM_PENDING_XCPT;
6063 }
6064
6065 *pGCPtrMem = GCPtrMem;
6066 return VINF_SUCCESS;
6067}
6068
6069
6070/**
6071 * Perform the relevant VMX instruction checks for VM-exits that occurred due to the
6072 * guest attempting to execute a VMX instruction.
6073 *
6074 * @returns Strict VBox status code (i.e. informational status codes too).
6075 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
6076 * @retval VINF_HM_PENDING_XCPT if an exception was raised.
6077 *
6078 * @param pVCpu The cross context virtual CPU structure.
6079 * @param uExitReason The VM-exit reason.
6080 *
6081 * @todo NstVmx: Document other error codes when VM-exit is implemented.
6082 * @remarks No-long-jump zone!!!
6083 */
6084static VBOXSTRICTRC hmR0VmxCheckExitDueToVmxInstr(PVMCPU pVCpu, uint32_t uExitReason)
6085{
6086 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS
6087 | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
6088
6089 if ( CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx)
6090 || ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
6091 && !CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx)))
6092 {
6093 Log4Func(("In real/v86-mode or long-mode outside 64-bit code segment -> #UD\n"));
6094 hmR0VmxSetPendingXcptUD(pVCpu);
6095 return VINF_HM_PENDING_XCPT;
6096 }
6097
6098 if (uExitReason == VMX_EXIT_VMXON)
6099 {
6100 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
6101
6102 /*
6103 * We check CR4.VMXE because it is required to be always set while in VMX operation
6104 * by physical CPUs and our CR4 read shadow is only consulted when executing specific
6105 * instructions (CLTS, LMSW, MOV CR, and SMSW) and thus doesn't affect CPU operation
6106 * otherwise (i.e. physical CPU won't automatically #UD if Cr4Shadow.VMXE is 0).
6107 */
6108 if (!CPUMIsGuestVmxEnabled(&pVCpu->cpum.GstCtx))
6109 {
6110 Log4Func(("CR4.VMXE is not set -> #UD\n"));
6111 hmR0VmxSetPendingXcptUD(pVCpu);
6112 return VINF_HM_PENDING_XCPT;
6113 }
6114 }
6115 else if (!CPUMIsGuestInVmxRootMode(&pVCpu->cpum.GstCtx))
6116 {
6117 /*
6118 * The guest has not entered VMX operation but attempted to execute a VMX instruction
6119 * (other than VMXON), we need to raise a #UD.
6120 */
6121 Log4Func(("Not in VMX root mode -> #UD\n"));
6122 hmR0VmxSetPendingXcptUD(pVCpu);
6123 return VINF_HM_PENDING_XCPT;
6124 }
6125
6126 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
6127 {
6128 /*
6129 * The nested-guest attempted to execute a VMX instruction, cause a VM-exit and let
6130 * the guest hypervisor deal with it.
6131 */
6132 /** @todo NSTVMX: Trigger a VM-exit */
6133 }
6134
6135 /*
6136 * VMX instructions require CPL 0 except in VMX non-root mode where the VM-exit intercept
6137 * (above) takes preceedence over the CPL check.
6138 */
6139 if (CPUMGetGuestCPL(pVCpu) > 0)
6140 {
6141 Log4Func(("CPL > 0 -> #GP(0)\n"));
6142 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6143 return VINF_HM_PENDING_XCPT;
6144 }
6145
6146 return VINF_SUCCESS;
6147}
6148#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
6149
6150
6151/**
6152 * Handle a condition that occurred while delivering an event through the guest
6153 * IDT.
6154 *
6155 * @returns Strict VBox status code (i.e. informational status codes too).
6156 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
6157 * @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought
6158 * to continue execution of the guest which will delivery the \#DF.
6159 * @retval VINF_EM_RESET if we detected a triple-fault condition.
6160 * @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
6161 *
6162 * @param pVCpu The cross context virtual CPU structure.
6163 * @param pVmxTransient Pointer to the VMX transient structure.
6164 *
6165 * @remarks No-long-jump zone!!!
6166 */
6167static VBOXSTRICTRC hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
6168{
6169 uint32_t const uExitVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
6170
6171 int rc2 = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
6172 rc2 |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
6173 AssertRCReturn(rc2, rc2);
6174
6175 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
6176 if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
6177 {
6178 uint32_t const uIdtVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
6179 uint32_t const uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
6180
6181 /*
6182 * If the event was a software interrupt (generated with INT n) or a software exception
6183 * (generated by INT3/INTO) or a privileged software exception (generated by INT1), we
6184 * can handle the VM-exit and continue guest execution which will re-execute the
6185 * instruction rather than re-injecting the exception, as that can cause premature
6186 * trips to ring-3 before injection and involve TRPM which currently has no way of
6187 * storing that these exceptions were caused by these instructions (ICEBP's #DB poses
6188 * the problem).
6189 */
6190 IEMXCPTRAISE enmRaise;
6191 IEMXCPTRAISEINFO fRaiseInfo;
6192 if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
6193 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
6194 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
6195 {
6196 enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
6197 fRaiseInfo = IEMXCPTRAISEINFO_NONE;
6198 }
6199 else if (VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo))
6200 {
6201 uint32_t const uExitVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uExitIntInfo);
6202 uint32_t const fIdtVectorFlags = hmR0VmxGetIemXcptFlags(uIdtVector, uIdtVectorType);
6203 uint32_t const fExitVectorFlags = hmR0VmxGetIemXcptFlags(uExitVector, uExitVectorType);
6204 /** @todo Make AssertMsgReturn as just AssertMsg later. */
6205 AssertMsgReturn(uExitVectorType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT,
6206 ("hmR0VmxCheckExitDueToEventDelivery: Unexpected VM-exit interruption info. %#x!\n",
6207 uExitVectorType), VERR_VMX_IPE_5);
6208
6209 enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
6210
6211 /* Determine a vectoring #PF condition, see comment in hmR0VmxExitXcptPF(). */
6212 if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF | IEMXCPTRAISEINFO_NMI_PF))
6213 {
6214 pVmxTransient->fVectoringPF = true;
6215 enmRaise = IEMXCPTRAISE_PREV_EVENT;
6216 }
6217 }
6218 else
6219 {
6220 /*
6221 * If an exception or hardware interrupt delivery caused an EPT violation/misconfig or APIC access
6222 * VM-exit, then the VM-exit interruption-information will not be valid and we end up here.
6223 * It is sufficient to reflect the original event to the guest after handling the VM-exit.
6224 */
6225 Assert( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
6226 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
6227 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
6228 enmRaise = IEMXCPTRAISE_PREV_EVENT;
6229 fRaiseInfo = IEMXCPTRAISEINFO_NONE;
6230 }
6231
6232 /*
6233 * On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig
6234 * etc.) occurred while delivering the NMI, we need to clear the block-by-NMI field in the guest
6235 * interruptibility-state before re-delivering the NMI after handling the VM-exit. Otherwise the
6236 * subsequent VM-entry would fail.
6237 *
6238 * See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
6239 */
6240 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)
6241 && uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
6242 && ( enmRaise == IEMXCPTRAISE_PREV_EVENT
6243 || (fRaiseInfo & IEMXCPTRAISEINFO_NMI_PF))
6244 && (pVCpu->hm.s.vmx.Ctls.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6245 {
6246 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6247 }
6248
6249 switch (enmRaise)
6250 {
6251 case IEMXCPTRAISE_CURRENT_XCPT:
6252 {
6253 Log4Func(("IDT: Pending secondary Xcpt: uIdtVectoringInfo=%#RX64 uExitIntInfo=%#RX64\n",
6254 pVmxTransient->uIdtVectoringInfo, pVmxTransient->uExitIntInfo));
6255 Assert(rcStrict == VINF_SUCCESS);
6256 break;
6257 }
6258
6259 case IEMXCPTRAISE_PREV_EVENT:
6260 {
6261 uint32_t u32ErrCode;
6262 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo))
6263 {
6264 rc2 = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
6265 AssertRCReturn(rc2, rc2);
6266 u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
6267 }
6268 else
6269 u32ErrCode = 0;
6270
6271 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF, see hmR0VmxExitXcptPF(). */
6272 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6273 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
6274 0 /* cbInstr */, u32ErrCode, pVCpu->cpum.GstCtx.cr2);
6275
6276 Log4Func(("IDT: Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->hm.s.Event.u64IntInfo,
6277 pVCpu->hm.s.Event.u32ErrCode));
6278 Assert(rcStrict == VINF_SUCCESS);
6279 break;
6280 }
6281
6282 case IEMXCPTRAISE_REEXEC_INSTR:
6283 Assert(rcStrict == VINF_SUCCESS);
6284 break;
6285
6286 case IEMXCPTRAISE_DOUBLE_FAULT:
6287 {
6288 /*
6289 * Determing a vectoring double #PF condition. Used later, when PGM evaluates the
6290 * second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
6291 */
6292 if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
6293 {
6294 pVmxTransient->fVectoringDoublePF = true;
6295 Log4Func(("IDT: Vectoring double #PF %#RX64 cr2=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo,
6296 pVCpu->cpum.GstCtx.cr2));
6297 rcStrict = VINF_SUCCESS;
6298 }
6299 else
6300 {
6301 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6302 hmR0VmxSetPendingXcptDF(pVCpu);
6303 Log4Func(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
6304 uIdtVector, uExitVector));
6305 rcStrict = VINF_HM_DOUBLE_FAULT;
6306 }
6307 break;
6308 }
6309
6310 case IEMXCPTRAISE_TRIPLE_FAULT:
6311 {
6312 Log4Func(("IDT: Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", uIdtVector, uExitVector));
6313 rcStrict = VINF_EM_RESET;
6314 break;
6315 }
6316
6317 case IEMXCPTRAISE_CPU_HANG:
6318 {
6319 Log4Func(("IDT: Bad guest! Entering CPU hang. fRaiseInfo=%#x\n", fRaiseInfo));
6320 rcStrict = VERR_EM_GUEST_CPU_HANG;
6321 break;
6322 }
6323
6324 default:
6325 {
6326 AssertMsgFailed(("IDT: vcpu[%RU32] Unexpected/invalid value! enmRaise=%#x\n", pVCpu->idCpu, enmRaise));
6327 rcStrict = VERR_VMX_IPE_2;
6328 break;
6329 }
6330 }
6331 }
6332 else if ( VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo)
6333 && VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(pVmxTransient->uExitIntInfo)
6334 && uExitVector != X86_XCPT_DF
6335 && (pVCpu->hm.s.vmx.Ctls.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6336 {
6337 /*
6338 * Execution of IRET caused this fault when NMI blocking was in effect (i.e we're in the guest NMI handler).
6339 * We need to set the block-by-NMI field so that NMIs remain blocked until the IRET execution is restarted.
6340 * See Intel spec. 30.7.1.2 "Resuming guest software after handling an exception".
6341 */
6342 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6343 {
6344 Log4Func(("Setting VMCPU_FF_BLOCK_NMIS. fValid=%RTbool uExitReason=%u\n",
6345 VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo), pVmxTransient->uExitReason));
6346 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6347 }
6348 }
6349
6350 Assert( rcStrict == VINF_SUCCESS || rcStrict == VINF_HM_DOUBLE_FAULT
6351 || rcStrict == VINF_EM_RESET || rcStrict == VERR_EM_GUEST_CPU_HANG);
6352 return rcStrict;
6353}
6354
6355
6356/**
6357 * Imports a guest segment register from the current VMCS into
6358 * the guest-CPU context.
6359 *
6360 * @returns VBox status code.
6361 * @param pVCpu The cross context virtual CPU structure.
6362 * @param idxSel Index of the selector in the VMCS.
6363 * @param idxLimit Index of the segment limit in the VMCS.
6364 * @param idxBase Index of the segment base in the VMCS.
6365 * @param idxAccess Index of the access rights of the segment in the VMCS.
6366 * @param pSelReg Pointer to the segment selector.
6367 *
6368 * @remarks Called with interrupts and/or preemption disabled, try not to assert and
6369 * do not log!
6370 *
6371 * @remarks Never call this function directly!!! Use the
6372 * HMVMX_IMPORT_SREG() macro as that takes care
6373 * of whether to read from the VMCS cache or not.
6374 */
6375static int hmR0VmxImportGuestSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
6376 PCPUMSELREG pSelReg)
6377{
6378 NOREF(pVCpu);
6379
6380 uint32_t u32Sel;
6381 uint32_t u32Limit;
6382 uint32_t u32Attr;
6383 uint64_t u64Base;
6384 int rc = VMXReadVmcs32(idxSel, &u32Sel);
6385 rc |= VMXReadVmcs32(idxLimit, &u32Limit);
6386 rc |= VMXReadVmcs32(idxAccess, &u32Attr);
6387 rc |= VMXReadVmcsGstNByIdxVal(idxBase, &u64Base);
6388 AssertRCReturn(rc, rc);
6389
6390 pSelReg->Sel = (uint16_t)u32Sel;
6391 pSelReg->ValidSel = (uint16_t)u32Sel;
6392 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6393 pSelReg->u32Limit = u32Limit;
6394 pSelReg->u64Base = u64Base;
6395 pSelReg->Attr.u = u32Attr;
6396
6397 /*
6398 * If VT-x marks the segment as unusable, most other bits remain undefined:
6399 * - For CS the L, D and G bits have meaning.
6400 * - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
6401 * - For the remaining data segments no bits are defined.
6402 *
6403 * The present bit and the unusable bit has been observed to be set at the
6404 * same time (the selector was supposed to be invalid as we started executing
6405 * a V8086 interrupt in ring-0).
6406 *
6407 * What should be important for the rest of the VBox code, is that the P bit is
6408 * cleared. Some of the other VBox code recognizes the unusable bit, but
6409 * AMD-V certainly don't, and REM doesn't really either. So, to be on the
6410 * safe side here, we'll strip off P and other bits we don't care about. If
6411 * any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
6412 *
6413 * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
6414 */
6415 if (pSelReg->Attr.u & X86DESCATTR_UNUSABLE)
6416 {
6417 Assert(idxSel != VMX_VMCS16_GUEST_TR_SEL); /* TR is the only selector that can never be unusable. */
6418
6419 /* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
6420 pSelReg->Attr.u &= X86DESCATTR_UNUSABLE | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
6421 | X86DESCATTR_DPL | X86DESCATTR_TYPE | X86DESCATTR_DT;
6422#ifdef VBOX_STRICT
6423 VMMRZCallRing3Disable(pVCpu);
6424 Log4Func(("Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Sel, pSelReg->Attr.u));
6425# ifdef DEBUG_bird
6426 AssertMsg((u32Attr & ~X86DESCATTR_P) == pSelReg->Attr.u,
6427 ("%#x: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
6428 idxSel, u32Sel, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
6429# endif
6430 VMMRZCallRing3Enable(pVCpu);
6431#endif
6432 }
6433 return VINF_SUCCESS;
6434}
6435
6436
6437/**
6438 * Imports the guest RIP from the VMCS back into the guest-CPU context.
6439 *
6440 * @returns VBox status code.
6441 * @param pVCpu The cross context virtual CPU structure.
6442 *
6443 * @remarks Called with interrupts and/or preemption disabled, should not assert!
6444 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6445 * instead!!!
6446 */
6447DECLINLINE(int) hmR0VmxImportGuestRip(PVMCPU pVCpu)
6448{
6449 uint64_t u64Val;
6450 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6451 if (pCtx->fExtrn & CPUMCTX_EXTRN_RIP)
6452 {
6453 int rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);
6454 if (RT_SUCCESS(rc))
6455 {
6456 pCtx->rip = u64Val;
6457 EMR0HistoryUpdatePC(pVCpu, pCtx->rip, false);
6458 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RIP;
6459 }
6460 return rc;
6461 }
6462 return VINF_SUCCESS;
6463}
6464
6465
6466/**
6467 * Imports the guest RFLAGS from the VMCS back into the guest-CPU context.
6468 *
6469 * @returns VBox status code.
6470 * @param pVCpu The cross context virtual CPU structure.
6471 *
6472 * @remarks Called with interrupts and/or preemption disabled, should not assert!
6473 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6474 * instead!!!
6475 */
6476DECLINLINE(int) hmR0VmxImportGuestRFlags(PVMCPU pVCpu)
6477{
6478 uint32_t u32Val;
6479 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6480 if (pCtx->fExtrn & CPUMCTX_EXTRN_RFLAGS)
6481 {
6482 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val);
6483 if (RT_SUCCESS(rc))
6484 {
6485 pCtx->eflags.u32 = u32Val;
6486
6487 /* Restore eflags for real-on-v86-mode hack. */
6488 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6489 {
6490 pCtx->eflags.Bits.u1VM = 0;
6491 pCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.Eflags.Bits.u2IOPL;
6492 }
6493 }
6494 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
6495 return rc;
6496 }
6497 return VINF_SUCCESS;
6498}
6499
6500
6501/**
6502 * Imports the guest interruptibility-state from the VMCS back into the guest-CPU
6503 * context.
6504 *
6505 * @returns VBox status code.
6506 * @param pVCpu The cross context virtual CPU structure.
6507 *
6508 * @remarks Called with interrupts and/or preemption disabled, try not to assert and
6509 * do not log!
6510 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6511 * instead!!!
6512 */
6513DECLINLINE(int) hmR0VmxImportGuestIntrState(PVMCPU pVCpu)
6514{
6515 uint32_t u32Val;
6516 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6517 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32Val);
6518 AssertRCReturn(rc, rc);
6519
6520 /*
6521 * We additionally have a requirement to import RIP, RFLAGS depending on whether we
6522 * might need them in while evaluating pending events before VM-entry.
6523 */
6524 if (!u32Val)
6525 {
6526 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6527 {
6528 rc = hmR0VmxImportGuestRip(pVCpu);
6529 rc |= hmR0VmxImportGuestRFlags(pVCpu);
6530 AssertRCReturn(rc, rc);
6531 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6532 }
6533
6534 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6535 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6536 }
6537 else
6538 {
6539 rc = hmR0VmxImportGuestRip(pVCpu);
6540 rc |= hmR0VmxImportGuestRFlags(pVCpu);
6541 AssertRCReturn(rc, rc);
6542
6543 if (u32Val & ( VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
6544 | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
6545 {
6546 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
6547 }
6548 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6549 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6550
6551 if (u32Val & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6552 {
6553 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6554 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6555 }
6556 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6557 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6558 }
6559
6560 return VINF_SUCCESS;
6561}
6562
6563
6564/**
6565 * Worker for VMXR0ImportStateOnDemand.
6566 *
6567 * @returns VBox status code.
6568 * @param pVCpu The cross context virtual CPU structure.
6569 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
6570 */
6571static int hmR0VmxImportGuestState(PVMCPU pVCpu, uint64_t fWhat)
6572{
6573#define VMXLOCAL_BREAK_RC(a_rc) \
6574 if (RT_FAILURE(a_rc)) \
6575 break
6576
6577 int rc = VINF_SUCCESS;
6578 PVM pVM = pVCpu->CTX_SUFF(pVM);
6579 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6580 uint64_t u64Val;
6581 uint32_t u32Val;
6582
6583 Log4Func(("fExtrn=%#RX64 fWhat=%#RX64\n", pCtx->fExtrn, fWhat));
6584 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
6585
6586 /*
6587 * We disable interrupts to make the updating of the state and in particular
6588 * the fExtrn modification atomic wrt to preemption hooks.
6589 */
6590 RTCCUINTREG const fEFlags = ASMIntDisableFlags();
6591
6592 fWhat &= pCtx->fExtrn;
6593 if (fWhat)
6594 {
6595 do
6596 {
6597 if (fWhat & CPUMCTX_EXTRN_RIP)
6598 {
6599 rc = hmR0VmxImportGuestRip(pVCpu);
6600 VMXLOCAL_BREAK_RC(rc);
6601 }
6602
6603 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
6604 {
6605 rc = hmR0VmxImportGuestRFlags(pVCpu);
6606 VMXLOCAL_BREAK_RC(rc);
6607 }
6608
6609 if (fWhat & CPUMCTX_EXTRN_HM_VMX_INT_STATE)
6610 {
6611 rc = hmR0VmxImportGuestIntrState(pVCpu);
6612 VMXLOCAL_BREAK_RC(rc);
6613 }
6614
6615 if (fWhat & CPUMCTX_EXTRN_RSP)
6616 {
6617 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);
6618 VMXLOCAL_BREAK_RC(rc);
6619 pCtx->rsp = u64Val;
6620 }
6621
6622 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
6623 {
6624 if (fWhat & CPUMCTX_EXTRN_CS)
6625 {
6626 rc = HMVMX_IMPORT_SREG(CS, &pCtx->cs);
6627 rc |= hmR0VmxImportGuestRip(pVCpu);
6628 VMXLOCAL_BREAK_RC(rc);
6629 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6630 pCtx->cs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrCS.u;
6631 EMR0HistoryUpdatePC(pVCpu, pCtx->cs.u64Base + pCtx->rip, true);
6632 }
6633 if (fWhat & CPUMCTX_EXTRN_SS)
6634 {
6635 rc = HMVMX_IMPORT_SREG(SS, &pCtx->ss);
6636 VMXLOCAL_BREAK_RC(rc);
6637 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6638 pCtx->ss.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrSS.u;
6639 }
6640 if (fWhat & CPUMCTX_EXTRN_DS)
6641 {
6642 rc = HMVMX_IMPORT_SREG(DS, &pCtx->ds);
6643 VMXLOCAL_BREAK_RC(rc);
6644 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6645 pCtx->ds.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrDS.u;
6646 }
6647 if (fWhat & CPUMCTX_EXTRN_ES)
6648 {
6649 rc = HMVMX_IMPORT_SREG(ES, &pCtx->es);
6650 VMXLOCAL_BREAK_RC(rc);
6651 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6652 pCtx->es.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrES.u;
6653 }
6654 if (fWhat & CPUMCTX_EXTRN_FS)
6655 {
6656 rc = HMVMX_IMPORT_SREG(FS, &pCtx->fs);
6657 VMXLOCAL_BREAK_RC(rc);
6658 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6659 pCtx->fs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrFS.u;
6660 }
6661 if (fWhat & CPUMCTX_EXTRN_GS)
6662 {
6663 rc = HMVMX_IMPORT_SREG(GS, &pCtx->gs);
6664 VMXLOCAL_BREAK_RC(rc);
6665 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6666 pCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrGS.u;
6667 }
6668 }
6669
6670 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
6671 {
6672 if (fWhat & CPUMCTX_EXTRN_LDTR)
6673 {
6674 rc = HMVMX_IMPORT_SREG(LDTR, &pCtx->ldtr);
6675 VMXLOCAL_BREAK_RC(rc);
6676 }
6677
6678 if (fWhat & CPUMCTX_EXTRN_GDTR)
6679 {
6680 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
6681 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
6682 VMXLOCAL_BREAK_RC(rc);
6683 pCtx->gdtr.pGdt = u64Val;
6684 pCtx->gdtr.cbGdt = u32Val;
6685 }
6686
6687 /* Guest IDTR. */
6688 if (fWhat & CPUMCTX_EXTRN_IDTR)
6689 {
6690 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
6691 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
6692 VMXLOCAL_BREAK_RC(rc);
6693 pCtx->idtr.pIdt = u64Val;
6694 pCtx->idtr.cbIdt = u32Val;
6695 }
6696
6697 /* Guest TR. */
6698 if (fWhat & CPUMCTX_EXTRN_TR)
6699 {
6700 /* Real-mode emulation using virtual-8086 mode has the fake TSS (pRealModeTSS) in TR, don't save that one. */
6701 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6702 {
6703 rc = HMVMX_IMPORT_SREG(TR, &pCtx->tr);
6704 VMXLOCAL_BREAK_RC(rc);
6705 }
6706 }
6707 }
6708
6709 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
6710 {
6711 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &pCtx->SysEnter.eip);
6712 rc |= VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &pCtx->SysEnter.esp);
6713 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val);
6714 pCtx->SysEnter.cs = u32Val;
6715 VMXLOCAL_BREAK_RC(rc);
6716 }
6717
6718#if HC_ARCH_BITS == 64
6719 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
6720 {
6721 if ( pVM->hm.s.fAllow64BitGuests
6722 && (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
6723 pCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
6724 }
6725
6726 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
6727 {
6728 if ( pVM->hm.s.fAllow64BitGuests
6729 && (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
6730 {
6731 pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
6732 pCtx->msrSTAR = ASMRdMsr(MSR_K6_STAR);
6733 pCtx->msrSFMASK = ASMRdMsr(MSR_K8_SF_MASK);
6734 }
6735 }
6736#endif
6737
6738 if ( (fWhat & (CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))
6739#if HC_ARCH_BITS == 32
6740 || (fWhat & (CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS))
6741#endif
6742 )
6743 {
6744 PCVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
6745 uint32_t const cMsrs = pVCpu->hm.s.vmx.cMsrs;
6746 for (uint32_t i = 0; i < cMsrs; i++, pMsr++)
6747 {
6748 switch (pMsr->u32Msr)
6749 {
6750#if HC_ARCH_BITS == 32
6751 case MSR_K8_LSTAR: pCtx->msrLSTAR = pMsr->u64Value; break;
6752 case MSR_K6_STAR: pCtx->msrSTAR = pMsr->u64Value; break;
6753 case MSR_K8_SF_MASK: pCtx->msrSFMASK = pMsr->u64Value; break;
6754 case MSR_K8_KERNEL_GS_BASE: pCtx->msrKERNELGSBASE = pMsr->u64Value; break;
6755#endif
6756 case MSR_IA32_SPEC_CTRL: CPUMSetGuestSpecCtrl(pVCpu, pMsr->u64Value); break;
6757 case MSR_K8_TSC_AUX: CPUMSetGuestTscAux(pVCpu, pMsr->u64Value); break;
6758 case MSR_K6_EFER: /* EFER can't be changed without causing a VM-exit */ break;
6759 default:
6760 {
6761 pVCpu->hm.s.u32HMError = pMsr->u32Msr;
6762 ASMSetFlags(fEFlags);
6763 AssertMsgFailed(("Unexpected MSR in auto-load/store area. uMsr=%#RX32 cMsrs=%u\n", pMsr->u32Msr,
6764 cMsrs));
6765 return VERR_HM_UNEXPECTED_LD_ST_MSR;
6766 }
6767 }
6768 }
6769 }
6770
6771 if (fWhat & CPUMCTX_EXTRN_DR7)
6772 {
6773 if (!pVCpu->hm.s.fUsingHyperDR7)
6774 {
6775 /* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
6776 rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val);
6777 VMXLOCAL_BREAK_RC(rc);
6778 pCtx->dr[7] = u32Val;
6779 }
6780 }
6781
6782 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
6783 {
6784 uint32_t u32Shadow;
6785 if (fWhat & CPUMCTX_EXTRN_CR0)
6786 {
6787 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val);
6788 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, &u32Shadow);
6789 VMXLOCAL_BREAK_RC(rc);
6790 u32Val = (u32Val & ~pVCpu->hm.s.vmx.Ctls.u32Cr0Mask)
6791 | (u32Shadow & pVCpu->hm.s.vmx.Ctls.u32Cr0Mask);
6792 VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
6793 CPUMSetGuestCR0(pVCpu, u32Val);
6794 VMMRZCallRing3Enable(pVCpu);
6795 }
6796
6797 if (fWhat & CPUMCTX_EXTRN_CR4)
6798 {
6799 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32Val);
6800 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &u32Shadow);
6801 VMXLOCAL_BREAK_RC(rc);
6802 u32Val = (u32Val & ~pVCpu->hm.s.vmx.Ctls.u32Cr4Mask)
6803 | (u32Shadow & pVCpu->hm.s.vmx.Ctls.u32Cr4Mask);
6804 CPUMSetGuestCR4(pVCpu, u32Val);
6805 }
6806
6807 if (fWhat & CPUMCTX_EXTRN_CR3)
6808 {
6809 /* CR0.PG bit changes are always intercepted, so it's up to date. */
6810 if ( pVM->hm.s.vmx.fUnrestrictedGuest
6811 || ( pVM->hm.s.fNestedPaging
6812 && CPUMIsGuestPagingEnabledEx(pCtx)))
6813 {
6814 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
6815 if (pCtx->cr3 != u64Val)
6816 {
6817 CPUMSetGuestCR3(pVCpu, u64Val);
6818 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
6819 }
6820
6821 /* If the guest is in PAE mode, sync back the PDPE's into the guest state.
6822 Note: CR4.PAE, CR0.PG, EFER bit changes are always intercepted, so they're up to date. */
6823 if (CPUMIsGuestInPAEModeEx(pCtx))
6824 {
6825 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
6826 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
6827 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
6828 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
6829 VMXLOCAL_BREAK_RC(rc);
6830 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
6831 }
6832 }
6833 }
6834 }
6835 } while (0);
6836
6837 if (RT_SUCCESS(rc))
6838 {
6839 /* Update fExtrn. */
6840 pCtx->fExtrn &= ~fWhat;
6841
6842 /* If everything has been imported, clear the HM keeper bit. */
6843 if (!(pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL))
6844 {
6845 pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
6846 Assert(!pCtx->fExtrn);
6847 }
6848 }
6849 }
6850 else
6851 AssertMsg(!pCtx->fExtrn || (pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL), ("%#RX64\n", pCtx->fExtrn));
6852
6853 ASMSetFlags(fEFlags);
6854
6855 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
6856
6857 /*
6858 * Honor any pending CR3 updates.
6859 *
6860 * Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> hmR0VmxCallRing3Callback()
6861 * -> VMMRZCallRing3Disable() -> hmR0VmxImportGuestState() -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
6862 * -> continue with VM-exit handling -> hmR0VmxImportGuestState() and here we are.
6863 *
6864 * The reason for such complicated handling is because VM-exits that call into PGM expect CR3 to be up-to-date and thus
6865 * if any CR3-saves -before- the VM-exit (longjmp) postponed the CR3 update via the force-flag, any VM-exit handler that
6866 * calls into PGM when it re-saves CR3 will end up here and we call PGMUpdateCR3(). This is why the code below should
6867 * -NOT- check if CPUMCTX_EXTRN_CR3 is set!
6868 *
6869 * The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
6870 */
6871 if (VMMRZCallRing3IsEnabled(pVCpu))
6872 {
6873 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6874 {
6875 Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_CR3));
6876 PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
6877 }
6878
6879 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6880 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6881
6882 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6883 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6884 }
6885
6886 return VINF_SUCCESS;
6887#undef VMXLOCAL_BREAK_RC
6888}
6889
6890
6891/**
6892 * Saves the guest state from the VMCS into the guest-CPU context.
6893 *
6894 * @returns VBox status code.
6895 * @param pVCpu The cross context virtual CPU structure.
6896 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
6897 */
6898VMMR0DECL(int) VMXR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
6899{
6900 return hmR0VmxImportGuestState(pVCpu, fWhat);
6901}
6902
6903
6904/**
6905 * Check per-VM and per-VCPU force flag actions that require us to go back to
6906 * ring-3 for one reason or another.
6907 *
6908 * @returns Strict VBox status code (i.e. informational status codes too)
6909 * @retval VINF_SUCCESS if we don't have any actions that require going back to
6910 * ring-3.
6911 * @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
6912 * @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
6913 * interrupts)
6914 * @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
6915 * all EMTs to be in ring-3.
6916 * @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
6917 * @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
6918 * to the EM loop.
6919 *
6920 * @param pVCpu The cross context virtual CPU structure.
6921 * @param fStepping Running in hmR0VmxRunGuestCodeStep().
6922 */
6923static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVMCPU pVCpu, bool fStepping)
6924{
6925 Assert(VMMRZCallRing3IsEnabled(pVCpu));
6926
6927 /*
6928 * Anything pending? Should be more likely than not if we're doing a good job.
6929 */
6930 PVM pVM = pVCpu->CTX_SUFF(pVM);
6931 if ( !fStepping
6932 ? !VM_FF_IS_ANY_SET(pVM, VM_FF_HP_R0_PRE_HM_MASK)
6933 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)
6934 : !VM_FF_IS_ANY_SET(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK)
6935 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
6936 return VINF_SUCCESS;
6937
6938 /* Pending PGM C3 sync. */
6939 if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
6940 {
6941 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6942 Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4)));
6943 VBOXSTRICTRC rcStrict2 = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4,
6944 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
6945 if (rcStrict2 != VINF_SUCCESS)
6946 {
6947 AssertRC(VBOXSTRICTRC_VAL(rcStrict2));
6948 Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
6949 return rcStrict2;
6950 }
6951 }
6952
6953 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
6954 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
6955 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
6956 {
6957 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
6958 int rc2 = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
6959 Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc2));
6960 return rc2;
6961 }
6962
6963 /* Pending VM request packets, such as hardware interrupts. */
6964 if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
6965 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
6966 {
6967 Log4Func(("Pending VM request forcing us back to ring-3\n"));
6968 return VINF_EM_PENDING_REQUEST;
6969 }
6970
6971 /* Pending PGM pool flushes. */
6972 if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
6973 {
6974 Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
6975 return VINF_PGM_POOL_FLUSH_PENDING;
6976 }
6977
6978 /* Pending DMA requests. */
6979 if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
6980 {
6981 Log4Func(("Pending DMA request forcing us back to ring-3\n"));
6982 return VINF_EM_RAW_TO_R3;
6983 }
6984
6985 return VINF_SUCCESS;
6986}
6987
6988
6989/**
6990 * Converts any TRPM trap into a pending HM event. This is typically used when
6991 * entering from ring-3 (not longjmp returns).
6992 *
6993 * @param pVCpu The cross context virtual CPU structure.
6994 */
6995static void hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu)
6996{
6997 Assert(TRPMHasTrap(pVCpu));
6998 Assert(!pVCpu->hm.s.Event.fPending);
6999
7000 uint8_t uVector;
7001 TRPMEVENT enmTrpmEvent;
7002 RTGCUINT uErrCode;
7003 RTGCUINTPTR GCPtrFaultAddress;
7004 uint8_t cbInstr;
7005
7006 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
7007 AssertRC(rc);
7008
7009 /* Refer Intel spec. 24.8.3 "VM-entry Controls for Event Injection" for the format of u32IntInfo. */
7010 uint32_t u32IntInfo = uVector | VMX_EXIT_INT_INFO_VALID;
7011 if (enmTrpmEvent == TRPM_TRAP)
7012 {
7013 switch (uVector)
7014 {
7015 case X86_XCPT_NMI:
7016 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_NMI << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7017 break;
7018
7019 case X86_XCPT_BP:
7020 case X86_XCPT_OF:
7021 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_SW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7022 break;
7023
7024 case X86_XCPT_PF:
7025 case X86_XCPT_DF:
7026 case X86_XCPT_TS:
7027 case X86_XCPT_NP:
7028 case X86_XCPT_SS:
7029 case X86_XCPT_GP:
7030 case X86_XCPT_AC:
7031 u32IntInfo |= VMX_EXIT_INT_INFO_ERROR_CODE_VALID;
7032 RT_FALL_THRU();
7033 default:
7034 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7035 break;
7036 }
7037 }
7038 else if (enmTrpmEvent == TRPM_HARDWARE_INT)
7039 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_EXT_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7040 else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
7041 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_SW_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7042 else
7043 AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
7044
7045 rc = TRPMResetTrap(pVCpu);
7046 AssertRC(rc);
7047 Log4(("TRPM->HM event: u32IntInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
7048 u32IntInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
7049
7050 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, uErrCode, GCPtrFaultAddress);
7051}
7052
7053
7054/**
7055 * Converts the pending HM event into a TRPM trap.
7056 *
7057 * @param pVCpu The cross context virtual CPU structure.
7058 */
7059static void hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu)
7060{
7061 Assert(pVCpu->hm.s.Event.fPending);
7062
7063 uint32_t uVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7064 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo);
7065 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVCpu->hm.s.Event.u64IntInfo);
7066 uint32_t uErrorCode = pVCpu->hm.s.Event.u32ErrCode;
7067
7068 /* If a trap was already pending, we did something wrong! */
7069 Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
7070
7071 TRPMEVENT enmTrapType;
7072 switch (uVectorType)
7073 {
7074 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
7075 enmTrapType = TRPM_HARDWARE_INT;
7076 break;
7077
7078 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
7079 enmTrapType = TRPM_SOFTWARE_INT;
7080 break;
7081
7082 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
7083 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
7084 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7085 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
7086 enmTrapType = TRPM_TRAP;
7087 break;
7088
7089 default:
7090 AssertMsgFailed(("Invalid trap type %#x\n", uVectorType));
7091 enmTrapType = TRPM_32BIT_HACK;
7092 break;
7093 }
7094
7095 Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
7096
7097 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7098 AssertRC(rc);
7099
7100 if (fErrorCodeValid)
7101 TRPMSetErrorCode(pVCpu, uErrorCode);
7102
7103 if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
7104 && uVector == X86_XCPT_PF)
7105 {
7106 TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
7107 }
7108 else if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7109 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
7110 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
7111 {
7112 AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7113 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7114 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
7115 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
7116 }
7117
7118 /* Clear the events from the VMCS. */
7119 VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0);
7120
7121 /* We're now done converting the pending event. */
7122 pVCpu->hm.s.Event.fPending = false;
7123}
7124
7125
7126/**
7127 * Does the necessary state syncing before returning to ring-3 for any reason
7128 * (longjmp, preemption, voluntary exits to ring-3) from VT-x.
7129 *
7130 * @returns VBox status code.
7131 * @param pVCpu The cross context virtual CPU structure.
7132 * @param fImportState Whether to import the guest state from the VMCS back
7133 * to the guest-CPU context.
7134 *
7135 * @remarks No-long-jmp zone!!!
7136 */
7137static int hmR0VmxLeave(PVMCPU pVCpu, bool fImportState)
7138{
7139 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7140 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7141
7142 RTCPUID idCpu = RTMpCpuId();
7143 Log4Func(("HostCpuId=%u\n", idCpu));
7144
7145 /*
7146 * !!! IMPORTANT !!!
7147 * If you modify code here, check whether hmR0VmxCallRing3Callback() needs to be updated too.
7148 */
7149
7150 /* Save the guest state if necessary. */
7151 if (fImportState)
7152 {
7153 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
7154 AssertRCReturn(rc, rc);
7155 }
7156
7157 /* Restore host FPU state if necessary. We will resync on next R0 reentry. */
7158 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7159 Assert(!CPUMIsGuestFPUStateActive(pVCpu));
7160
7161 /* Restore host debug registers if necessary. We will resync on next R0 reentry. */
7162#ifdef VBOX_STRICT
7163 if (CPUMIsHyperDebugStateActive(pVCpu))
7164 Assert(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
7165#endif
7166 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7167 Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
7168 Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
7169
7170#if HC_ARCH_BITS == 64
7171 /* Restore host-state bits that VT-x only restores partially. */
7172 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7173 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7174 {
7175 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags, idCpu));
7176 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7177 }
7178 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7179#endif
7180
7181 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7182 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
7183 {
7184 /* We shouldn't restore the host MSRs without saving the guest MSRs first. */
7185 if (!fImportState)
7186 {
7187 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS);
7188 AssertRCReturn(rc, rc);
7189 }
7190 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7191 Assert(!pVCpu->hm.s.vmx.fLazyMsrs);
7192 }
7193 else
7194 pVCpu->hm.s.vmx.fLazyMsrs = 0;
7195
7196 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7197 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7198
7199 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
7200 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
7201 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
7202 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
7203 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
7204 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
7205 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
7206 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
7207 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7208
7209 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7210
7211 /** @todo This partially defeats the purpose of having preemption hooks.
7212 * The problem is, deregistering the hooks should be moved to a place that
7213 * lasts until the EMT is about to be destroyed not everytime while leaving HM
7214 * context.
7215 */
7216 if (pVCpu->hm.s.vmx.fVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7217 {
7218 int rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7219 AssertRCReturn(rc, rc);
7220
7221 pVCpu->hm.s.vmx.fVmcsState = HMVMX_VMCS_STATE_CLEAR;
7222 Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
7223 }
7224 Assert(!(pVCpu->hm.s.vmx.fVmcsState & HMVMX_VMCS_STATE_LAUNCHED));
7225 NOREF(idCpu);
7226
7227 return VINF_SUCCESS;
7228}
7229
7230
7231/**
7232 * Leaves the VT-x session.
7233 *
7234 * @returns VBox status code.
7235 * @param pVCpu The cross context virtual CPU structure.
7236 *
7237 * @remarks No-long-jmp zone!!!
7238 */
7239static int hmR0VmxLeaveSession(PVMCPU pVCpu)
7240{
7241 HM_DISABLE_PREEMPT(pVCpu);
7242 HMVMX_ASSERT_CPU_SAFE(pVCpu);
7243 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7244 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7245
7246 /* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
7247 and done this from the VMXR0ThreadCtxCallback(). */
7248 if (!pVCpu->hm.s.fLeaveDone)
7249 {
7250 int rc2 = hmR0VmxLeave(pVCpu, true /* fImportState */);
7251 AssertRCReturnStmt(rc2, HM_RESTORE_PREEMPT(), rc2);
7252 pVCpu->hm.s.fLeaveDone = true;
7253 }
7254 Assert(!pVCpu->cpum.GstCtx.fExtrn);
7255
7256 /*
7257 * !!! IMPORTANT !!!
7258 * If you modify code here, make sure to check whether hmR0VmxCallRing3Callback() needs to be updated too.
7259 */
7260
7261 /* Deregister hook now that we've left HM context before re-enabling preemption. */
7262 /** @todo Deregistering here means we need to VMCLEAR always
7263 * (longjmp/exit-to-r3) in VT-x which is not efficient, eliminate need
7264 * for calling VMMR0ThreadCtxHookDisable here! */
7265 VMMR0ThreadCtxHookDisable(pVCpu);
7266
7267 /* Leave HM context. This takes care of local init (term). */
7268 int rc = HMR0LeaveCpu(pVCpu);
7269
7270 HM_RESTORE_PREEMPT();
7271 return rc;
7272}
7273
7274
7275/**
7276 * Does the necessary state syncing before doing a longjmp to ring-3.
7277 *
7278 * @returns VBox status code.
7279 * @param pVCpu The cross context virtual CPU structure.
7280 *
7281 * @remarks No-long-jmp zone!!!
7282 */
7283DECLINLINE(int) hmR0VmxLongJmpToRing3(PVMCPU pVCpu)
7284{
7285 return hmR0VmxLeaveSession(pVCpu);
7286}
7287
7288
7289/**
7290 * Take necessary actions before going back to ring-3.
7291 *
7292 * An action requires us to go back to ring-3. This function does the necessary
7293 * steps before we can safely return to ring-3. This is not the same as longjmps
7294 * to ring-3, this is voluntary and prepares the guest so it may continue
7295 * executing outside HM (recompiler/IEM).
7296 *
7297 * @returns VBox status code.
7298 * @param pVCpu The cross context virtual CPU structure.
7299 * @param rcExit The reason for exiting to ring-3. Can be
7300 * VINF_VMM_UNKNOWN_RING3_CALL.
7301 */
7302static int hmR0VmxExitToRing3(PVMCPU pVCpu, VBOXSTRICTRC rcExit)
7303{
7304 Assert(pVCpu);
7305 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7306
7307 if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
7308 {
7309 VMXGetActivatedVmcs(&pVCpu->hm.s.vmx.LastError.u64VmcsPhys);
7310 pVCpu->hm.s.vmx.LastError.u32VmcsRev = *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs;
7311 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
7312 /* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
7313 }
7314
7315 /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
7316 VMMRZCallRing3Disable(pVCpu);
7317 Log4Func(("rcExit=%d\n", VBOXSTRICTRC_VAL(rcExit)));
7318
7319 /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
7320 if (pVCpu->hm.s.Event.fPending)
7321 {
7322 hmR0VmxPendingEventToTrpmTrap(pVCpu);
7323 Assert(!pVCpu->hm.s.Event.fPending);
7324 }
7325
7326 /* Clear interrupt-window and NMI-window controls as we re-evaluate it when we return from ring-3. */
7327 hmR0VmxClearIntNmiWindowsVmcs(pVCpu);
7328
7329 /* If we're emulating an instruction, we shouldn't have any TRPM traps pending
7330 and if we're injecting an event we should have a TRPM trap pending. */
7331 AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT || TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7332#ifndef DEBUG_bird /* Triggered after firing an NMI against NT4SP1, possibly a triple fault in progress. */
7333 AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR || !TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7334#endif
7335
7336 /* Save guest state and restore host state bits. */
7337 int rc = hmR0VmxLeaveSession(pVCpu);
7338 AssertRCReturn(rc, rc);
7339 STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7340 /* Thread-context hooks are unregistered at this point!!! */
7341
7342 /* Sync recompiler state. */
7343 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
7344 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
7345 | CPUM_CHANGED_LDTR
7346 | CPUM_CHANGED_GDTR
7347 | CPUM_CHANGED_IDTR
7348 | CPUM_CHANGED_TR
7349 | CPUM_CHANGED_HIDDEN_SEL_REGS);
7350 if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
7351 && CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
7352 {
7353 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
7354 }
7355
7356 Assert(!pVCpu->hm.s.fClearTrapFlag);
7357
7358 /* Update the exit-to-ring 3 reason. */
7359 pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
7360
7361 /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
7362 if (rcExit != VINF_EM_RAW_INTERRUPT)
7363 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7364
7365 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
7366
7367 /* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
7368 VMMRZCallRing3RemoveNotification(pVCpu);
7369 VMMRZCallRing3Enable(pVCpu);
7370
7371 return rc;
7372}
7373
7374
7375/**
7376 * VMMRZCallRing3() callback wrapper which saves the guest state before we
7377 * longjump to ring-3 and possibly get preempted.
7378 *
7379 * @returns VBox status code.
7380 * @param pVCpu The cross context virtual CPU structure.
7381 * @param enmOperation The operation causing the ring-3 longjump.
7382 * @param pvUser User argument, currently unused, NULL.
7383 */
7384static DECLCALLBACK(int) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
7385{
7386 RT_NOREF(pvUser);
7387 if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
7388 {
7389 /*
7390 * !!! IMPORTANT !!!
7391 * If you modify code here, check whether hmR0VmxLeave() and hmR0VmxLeaveSession() needs to be updated too.
7392 * This is a stripped down version which gets out ASAP, trying to not trigger any further assertions.
7393 */
7394 VMMRZCallRing3RemoveNotification(pVCpu);
7395 VMMRZCallRing3Disable(pVCpu);
7396 RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
7397 RTThreadPreemptDisable(&PreemptState);
7398
7399 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
7400 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7401 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7402
7403#if HC_ARCH_BITS == 64
7404 /* Restore host-state bits that VT-x only restores partially. */
7405 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7406 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7407 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7408 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7409#endif
7410
7411 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7412 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
7413 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7414
7415 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7416 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7417 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7418 if (pVCpu->hm.s.vmx.fVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7419 {
7420 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7421 pVCpu->hm.s.vmx.fVmcsState = HMVMX_VMCS_STATE_CLEAR;
7422 }
7423
7424 /** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7425 VMMR0ThreadCtxHookDisable(pVCpu);
7426 HMR0LeaveCpu(pVCpu);
7427 RTThreadPreemptRestore(&PreemptState);
7428 return VINF_SUCCESS;
7429 }
7430
7431 Assert(pVCpu);
7432 Assert(pvUser);
7433 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7434 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7435
7436 VMMRZCallRing3Disable(pVCpu);
7437 Assert(VMMR0IsLogFlushDisabled(pVCpu));
7438
7439 Log4Func((" -> hmR0VmxLongJmpToRing3 enmOperation=%d\n", enmOperation));
7440
7441 int rc = hmR0VmxLongJmpToRing3(pVCpu);
7442 AssertRCReturn(rc, rc);
7443
7444 VMMRZCallRing3Enable(pVCpu);
7445 return VINF_SUCCESS;
7446}
7447
7448
7449/**
7450 * Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
7451 * cause a VM-exit as soon as the guest is in a state to receive interrupts.
7452 *
7453 * @param pVCpu The cross context virtual CPU structure.
7454 */
7455DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
7456{
7457 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_INT_WINDOW_EXIT))
7458 {
7459 if (!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
7460 {
7461 pVCpu->hm.s.vmx.Ctls.u32ProcCtls |= VMX_PROC_CTLS_INT_WINDOW_EXIT;
7462 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.Ctls.u32ProcCtls);
7463 AssertRC(rc);
7464 Log4Func(("Setup interrupt-window exiting\n"));
7465 }
7466 } /* else we will deliver interrupts whenever the guest exits next and is in a state to receive events. */
7467}
7468
7469
7470/**
7471 * Clears the interrupt-window exiting control in the VMCS.
7472 *
7473 * @param pVCpu The cross context virtual CPU structure.
7474 */
7475DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu)
7476{
7477 Assert(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
7478 pVCpu->hm.s.vmx.Ctls.u32ProcCtls &= ~VMX_PROC_CTLS_INT_WINDOW_EXIT;
7479 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.Ctls.u32ProcCtls);
7480 AssertRC(rc);
7481 Log4Func(("Cleared interrupt-window exiting\n"));
7482}
7483
7484
7485/**
7486 * Sets the NMI-window exiting control in the VMCS which instructs VT-x to
7487 * cause a VM-exit as soon as the guest is in a state to receive NMIs.
7488 *
7489 * @param pVCpu The cross context virtual CPU structure.
7490 */
7491DECLINLINE(void) hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu)
7492{
7493 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
7494 {
7495 if (!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
7496 {
7497 pVCpu->hm.s.vmx.Ctls.u32ProcCtls |= VMX_PROC_CTLS_NMI_WINDOW_EXIT;
7498 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.Ctls.u32ProcCtls);
7499 AssertRC(rc);
7500 Log4Func(("Setup NMI-window exiting\n"));
7501 }
7502 } /* else we will deliver NMIs whenever we VM-exit next, even possibly nesting NMIs. Can't be helped on ancient CPUs. */
7503}
7504
7505
7506/**
7507 * Clears the NMI-window exiting control in the VMCS.
7508 *
7509 * @param pVCpu The cross context virtual CPU structure.
7510 */
7511DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu)
7512{
7513 Assert(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
7514 pVCpu->hm.s.vmx.Ctls.u32ProcCtls &= ~VMX_PROC_CTLS_NMI_WINDOW_EXIT;
7515 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.Ctls.u32ProcCtls);
7516 AssertRC(rc);
7517 Log4Func(("Cleared NMI-window exiting\n"));
7518}
7519
7520
7521/**
7522 * Evaluates the event to be delivered to the guest and sets it as the pending
7523 * event.
7524 *
7525 * @returns The VT-x guest-interruptibility state.
7526 * @param pVCpu The cross context virtual CPU structure.
7527 */
7528static uint32_t hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu)
7529{
7530 /* Get the current interruptibility-state of the guest and then figure out what can be injected. */
7531 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7532 uint32_t const fIntrState = hmR0VmxGetGuestIntrState(pVCpu);
7533 bool const fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
7534 bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
7535 bool const fBlockNmi = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI);
7536
7537 Assert(!fBlockSti || !(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_RFLAGS));
7538 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7539 Assert(!fBlockSti || pCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7540 Assert(!TRPMHasTrap(pVCpu));
7541
7542 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
7543 APICUpdatePendingInterrupts(pVCpu);
7544
7545 /*
7546 * Toggling of interrupt force-flags here is safe since we update TRPM on premature exits
7547 * to ring-3 before executing guest code, see hmR0VmxExitToRing3(). We must NOT restore these force-flags.
7548 */
7549 /** @todo SMI. SMIs take priority over NMIs. */
7550 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
7551 {
7552 /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
7553 if ( !pVCpu->hm.s.Event.fPending
7554 && !fBlockNmi
7555 && !fBlockSti
7556 && !fBlockMovSS)
7557 {
7558 Log4Func(("Pending NMI\n"));
7559 uint32_t u32IntInfo = X86_XCPT_NMI | VMX_EXIT_INT_INFO_VALID;
7560 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_NMI << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7561
7562 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7563 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
7564 }
7565 else
7566 hmR0VmxSetNmiWindowExitVmcs(pVCpu);
7567 }
7568 /*
7569 * Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
7570 * a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
7571 */
7572 else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
7573 && !pVCpu->hm.s.fSingleInstruction)
7574 {
7575 Assert(!DBGFIsStepping(pVCpu));
7576 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
7577 AssertRCReturn(rc, 0);
7578 bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
7579 if ( !pVCpu->hm.s.Event.fPending
7580 && !fBlockInt
7581 && !fBlockSti
7582 && !fBlockMovSS)
7583 {
7584 uint8_t u8Interrupt;
7585 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
7586 if (RT_SUCCESS(rc))
7587 {
7588 Log4Func(("Pending external interrupt u8Interrupt=%#x\n", u8Interrupt));
7589 uint32_t u32IntInfo = u8Interrupt
7590 | VMX_EXIT_INT_INFO_VALID
7591 | (VMX_EXIT_INT_INFO_TYPE_EXT_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7592
7593 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrfaultAddress */);
7594 }
7595 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
7596 {
7597 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7598 hmR0VmxApicSetTprThreshold(pVCpu, u8Interrupt >> 4);
7599 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
7600
7601 /*
7602 * If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
7603 * APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
7604 * need to re-set this force-flag here.
7605 */
7606 }
7607 else
7608 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
7609 }
7610 else
7611 hmR0VmxSetIntWindowExitVmcs(pVCpu);
7612 }
7613
7614 return fIntrState;
7615}
7616
7617
7618/**
7619 * Injects any pending events into the guest if the guest is in a state to
7620 * receive them.
7621 *
7622 * @returns Strict VBox status code (i.e. informational status codes too).
7623 * @param pVCpu The cross context virtual CPU structure.
7624 * @param fIntrState The VT-x guest-interruptibility state.
7625 * @param fStepping Running in hmR0VmxRunGuestCodeStep() and we should
7626 * return VINF_EM_DBG_STEPPED if the event was
7627 * dispatched directly.
7628 */
7629static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPU pVCpu, uint32_t fIntrState, bool fStepping)
7630{
7631 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7632 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7633
7634 bool const fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
7635 bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
7636
7637 Assert(!fBlockSti || !(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_RFLAGS));
7638 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7639 Assert(!fBlockSti || pVCpu->cpum.GstCtx.eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7640 Assert(!TRPMHasTrap(pVCpu));
7641
7642 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
7643 if (pVCpu->hm.s.Event.fPending)
7644 {
7645 /*
7646 * Do -not- clear any interrupt-window exiting control here. We might have an interrupt
7647 * pending even while injecting an event and in this case, we want a VM-exit as soon as
7648 * the guest is ready for the next interrupt, see @bugref{6208#c45}.
7649 *
7650 * See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
7651 */
7652 uint32_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7653#ifdef VBOX_STRICT
7654 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
7655 {
7656 bool const fBlockInt = !(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_IF);
7657 Assert(!fBlockInt);
7658 Assert(!fBlockSti);
7659 Assert(!fBlockMovSS);
7660 }
7661 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
7662 {
7663 bool const fBlockNmi = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI);
7664 Assert(!fBlockSti);
7665 Assert(!fBlockMovSS);
7666 Assert(!fBlockNmi);
7667 }
7668#endif
7669 Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#RX32\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
7670 uIntType));
7671
7672 /*
7673 * Inject the event and get any changes to the guest-interruptibility state.
7674 *
7675 * The guest-interruptibility state may need to be updated if we inject the event
7676 * into the guest IDT ourselves (for real-on-v86 guest injecting software interrupts).
7677 */
7678 rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.cbInstr,
7679 pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress, fStepping,
7680 &fIntrState);
7681 AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7682
7683 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
7684 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
7685 else
7686 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
7687 }
7688
7689 /*
7690 * Update the guest-interruptibility state.
7691 *
7692 * This is required for the real-on-v86 software interrupt injection case above, as well as
7693 * updates to the guest state from ring-3 or IEM/REM.
7694 */
7695 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
7696 AssertRCReturn(rc, rc);
7697
7698 /*
7699 * There's no need to clear the VM-entry interruption-information field here if we're not
7700 * injecting anything. VT-x clears the valid bit on every VM-exit.
7701 *
7702 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7703 */
7704
7705 Assert(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping));
7706 NOREF(fBlockMovSS); NOREF(fBlockSti);
7707 return rcStrict;
7708}
7709
7710
7711/**
7712 * Injects a double-fault (\#DF) exception into the VM.
7713 *
7714 * @returns Strict VBox status code (i.e. informational status codes too).
7715 * @param pVCpu The cross context virtual CPU structure.
7716 * @param fStepping Whether we're running in hmR0VmxRunGuestCodeStep()
7717 * and should return VINF_EM_DBG_STEPPED if the event
7718 * is injected directly (register modified by us, not
7719 * by hardware on VM-entry).
7720 * @param pfIntrState Pointer to the current guest interruptibility-state.
7721 * This interruptibility-state will be updated if
7722 * necessary. This cannot not be NULL.
7723 */
7724DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptDF(PVMCPU pVCpu, bool fStepping, uint32_t *pfIntrState)
7725{
7726 uint32_t const u32IntInfo = X86_XCPT_DF | VMX_EXIT_INT_INFO_VALID
7727 | (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT)
7728 | VMX_EXIT_INT_INFO_ERROR_CODE_VALID;
7729 return hmR0VmxInjectEventVmcs(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */, fStepping,
7730 pfIntrState);
7731}
7732
7733
7734/**
7735 * Injects a general-protection (\#GP) fault into the VM.
7736 *
7737 * @returns Strict VBox status code (i.e. informational status codes too).
7738 * @param pVCpu The cross context virtual CPU structure.
7739 * @param fErrorCodeValid Whether the error code is valid (depends on the CPU
7740 * mode, i.e. in real-mode it's not valid).
7741 * @param u32ErrorCode The error code associated with the \#GP.
7742 * @param fStepping Whether we're running in
7743 * hmR0VmxRunGuestCodeStep() and should return
7744 * VINF_EM_DBG_STEPPED if the event is injected
7745 * directly (register modified by us, not by
7746 * hardware on VM-entry).
7747 * @param pfIntrState Pointer to the current guest interruptibility-state.
7748 * This interruptibility-state will be updated if
7749 * necessary. This cannot not be NULL.
7750 */
7751DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptGP(PVMCPU pVCpu, bool fErrorCodeValid, uint32_t u32ErrorCode, bool fStepping,
7752 uint32_t *pfIntrState)
7753{
7754 uint32_t const u32IntInfo = X86_XCPT_GP | VMX_EXIT_INT_INFO_VALID
7755 | (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT)
7756 | (fErrorCodeValid ? VMX_EXIT_INT_INFO_ERROR_CODE_VALID : 0);
7757 return hmR0VmxInjectEventVmcs(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */, fStepping,
7758 pfIntrState);
7759}
7760
7761
7762/**
7763 * Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
7764 * stack.
7765 *
7766 * @returns Strict VBox status code (i.e. informational status codes too).
7767 * @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
7768 * @param pVCpu The cross context virtual CPU structure.
7769 * @param uValue The value to push to the guest stack.
7770 */
7771static VBOXSTRICTRC hmR0VmxRealModeGuestStackPush(PVMCPU pVCpu, uint16_t uValue)
7772{
7773 /*
7774 * The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
7775 * virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
7776 * See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
7777 */
7778 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7779 if (pCtx->sp == 1)
7780 return VINF_EM_RESET;
7781 pCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
7782 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->ss.u64Base + pCtx->sp, &uValue, sizeof(uint16_t));
7783 AssertRC(rc);
7784 return rc;
7785}
7786
7787
7788/**
7789 * Injects an event into the guest upon VM-entry by updating the relevant fields
7790 * in the VM-entry area in the VMCS.
7791 *
7792 * @returns Strict VBox status code (i.e. informational status codes too).
7793 * @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
7794 * @retval VINF_EM_RESET if event injection resulted in a triple-fault.
7795 *
7796 * @param pVCpu The cross context virtual CPU structure.
7797 * @param u64IntInfo The VM-entry interruption-information field.
7798 * @param cbInstr The VM-entry instruction length in bytes (for
7799 * software interrupts, exceptions and privileged
7800 * software exceptions).
7801 * @param u32ErrCode The VM-entry exception error code.
7802 * @param GCPtrFaultAddress The page-fault address for \#PF exceptions.
7803 * @param pfIntrState Pointer to the current guest interruptibility-state.
7804 * This interruptibility-state will be updated if
7805 * necessary. This cannot not be NULL.
7806 * @param fStepping Whether we're running in
7807 * hmR0VmxRunGuestCodeStep() and should return
7808 * VINF_EM_DBG_STEPPED if the event is injected
7809 * directly (register modified by us, not by
7810 * hardware on VM-entry).
7811 */
7812static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
7813 RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *pfIntrState)
7814{
7815 /* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
7816 AssertMsg(!RT_HI_U32(u64IntInfo), ("%#RX64\n", u64IntInfo));
7817 Assert(pfIntrState);
7818
7819 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7820 uint32_t u32IntInfo = (uint32_t)u64IntInfo;
7821 uint32_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(u32IntInfo);
7822 uint32_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(u32IntInfo);
7823
7824#ifdef VBOX_STRICT
7825 /*
7826 * Validate the error-code-valid bit for hardware exceptions.
7827 * No error codes for exceptions in real-mode.
7828 *
7829 * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
7830 */
7831 if ( uIntType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
7832 && !CPUMIsGuestInRealModeEx(pCtx))
7833 {
7834 switch (uVector)
7835 {
7836 case X86_XCPT_PF:
7837 case X86_XCPT_DF:
7838 case X86_XCPT_TS:
7839 case X86_XCPT_NP:
7840 case X86_XCPT_SS:
7841 case X86_XCPT_GP:
7842 case X86_XCPT_AC:
7843 AssertMsg(VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo),
7844 ("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
7845 RT_FALL_THRU();
7846 default:
7847 break;
7848 }
7849 }
7850#endif
7851
7852 /* Cannot inject an NMI when block-by-MOV SS is in effect. */
7853 Assert( uIntType != VMX_EXIT_INT_INFO_TYPE_NMI
7854 || !(*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
7855
7856 STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
7857
7858 /*
7859 * Hardware interrupts & exceptions cannot be delivered through the software interrupt
7860 * redirection bitmap to the real mode task in virtual-8086 mode. We must jump to the
7861 * interrupt handler in the (real-mode) guest.
7862 *
7863 * See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode".
7864 * See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
7865 */
7866 if (CPUMIsGuestInRealModeEx(pCtx)) /* CR0.PE bit changes are always intercepted, so it's up to date. */
7867 {
7868 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest)
7869 {
7870 /*
7871 * For unrestricted execution enabled CPUs running real-mode guests, we must not
7872 * set the deliver-error-code bit.
7873 *
7874 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
7875 */
7876 u32IntInfo &= ~VMX_ENTRY_INT_INFO_ERROR_CODE_VALID;
7877 }
7878 else
7879 {
7880 PVM pVM = pVCpu->CTX_SUFF(pVM);
7881 Assert(PDMVmmDevHeapIsEnabled(pVM));
7882 Assert(pVM->hm.s.vmx.pRealModeTSS);
7883
7884 /* We require RIP, RSP, RFLAGS, CS, IDTR, import them. */
7885 int rc2 = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_RIP
7886 | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS);
7887 AssertRCReturn(rc2, rc2);
7888
7889 /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
7890 size_t const cbIdtEntry = sizeof(X86IDTR16);
7891 if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pCtx->idtr.cbIdt)
7892 {
7893 /* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
7894 if (uVector == X86_XCPT_DF)
7895 return VINF_EM_RESET;
7896
7897 /* If we're injecting a #GP with no valid IDT entry, inject a double-fault. */
7898 if (uVector == X86_XCPT_GP)
7899 return hmR0VmxInjectXcptDF(pVCpu, fStepping, pfIntrState);
7900
7901 /*
7902 * If we're injecting an event with no valid IDT entry, inject a #GP.
7903 * No error codes for exceptions in real-mode.
7904 *
7905 * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
7906 */
7907 return hmR0VmxInjectXcptGP(pVCpu, false /* fErrCodeValid */, 0 /* u32ErrCode */, fStepping, pfIntrState);
7908 }
7909
7910 /* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
7911 uint16_t uGuestIp = pCtx->ip;
7912 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT)
7913 {
7914 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7915 /* #BP and #OF are both benign traps, we need to resume the next instruction. */
7916 uGuestIp = pCtx->ip + (uint16_t)cbInstr;
7917 }
7918 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_SW_INT)
7919 uGuestIp = pCtx->ip + (uint16_t)cbInstr;
7920
7921 /* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
7922 X86IDTR16 IdtEntry;
7923 RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pCtx->idtr.pIdt + uVector * cbIdtEntry;
7924 rc2 = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
7925 AssertRCReturn(rc2, rc2);
7926
7927 /* Construct the stack frame for the interrupt/exception handler. */
7928 VBOXSTRICTRC rcStrict;
7929 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->eflags.u32);
7930 if (rcStrict == VINF_SUCCESS)
7931 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->cs.Sel);
7932 if (rcStrict == VINF_SUCCESS)
7933 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, uGuestIp);
7934
7935 /* Clear the required eflag bits and jump to the interrupt/exception handler. */
7936 if (rcStrict == VINF_SUCCESS)
7937 {
7938 pCtx->eflags.u32 &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
7939 pCtx->rip = IdtEntry.offSel;
7940 pCtx->cs.Sel = IdtEntry.uSel;
7941 pCtx->cs.ValidSel = IdtEntry.uSel;
7942 pCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
7943 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
7944 && uVector == X86_XCPT_PF)
7945 pCtx->cr2 = GCPtrFaultAddress;
7946
7947 /* If any other guest-state bits are changed here, make sure to update
7948 hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
7949 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CS | HM_CHANGED_GUEST_CR2
7950 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
7951 | HM_CHANGED_GUEST_RSP);
7952
7953 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
7954 if (*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
7955 {
7956 Assert( uIntType != VMX_ENTRY_INT_INFO_TYPE_NMI
7957 && uIntType != VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
7958 Log4Func(("Clearing inhibition due to STI\n"));
7959 *pfIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
7960 }
7961 Log4(("Injecting real-mode: u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x Eflags=%#x CS:EIP=%04x:%04x\n",
7962 u32IntInfo, u32ErrCode, cbInstr, pCtx->eflags.u, pCtx->cs.Sel, pCtx->eip));
7963
7964 /* The event has been truly dispatched. Mark it as no longer pending so we don't attempt to 'undo'
7965 it, if we are returning to ring-3 before executing guest code. */
7966 pVCpu->hm.s.Event.fPending = false;
7967
7968 /* Make hmR0VmxPreRunGuest() return if we're stepping since we've changed cs:rip. */
7969 if (fStepping)
7970 rcStrict = VINF_EM_DBG_STEPPED;
7971 }
7972 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
7973 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7974 return rcStrict;
7975 }
7976 }
7977
7978 /* Validate. */
7979 Assert(VMX_ENTRY_INT_INFO_IS_VALID(u32IntInfo)); /* Bit 31 (Valid bit) must be set by caller. */
7980 Assert(!(u32IntInfo & VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK)); /* Bits 30:12 MBZ. */
7981
7982 /* Inject. */
7983 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
7984 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo))
7985 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
7986 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
7987 AssertRCReturn(rc, rc);
7988
7989 /* Update CR2. */
7990 if ( VMX_ENTRY_INT_INFO_TYPE(u32IntInfo) == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
7991 && uVector == X86_XCPT_PF)
7992 pCtx->cr2 = GCPtrFaultAddress;
7993
7994 Log4(("Injecting u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x CR2=%#RX64\n", u32IntInfo, u32ErrCode, cbInstr, pCtx->cr2));
7995
7996 return VINF_SUCCESS;
7997}
7998
7999
8000/**
8001 * Clears the interrupt-window exiting control in the VMCS and if necessary
8002 * clears the current event in the VMCS as well.
8003 *
8004 * @returns VBox status code.
8005 * @param pVCpu The cross context virtual CPU structure.
8006 *
8007 * @remarks Use this function only to clear events that have not yet been
8008 * delivered to the guest but are injected in the VMCS!
8009 * @remarks No-long-jump zone!!!
8010 */
8011static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu)
8012{
8013 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
8014 {
8015 hmR0VmxClearIntWindowExitVmcs(pVCpu);
8016 Log4Func(("Cleared interrupt window\n"));
8017 }
8018
8019 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
8020 {
8021 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
8022 Log4Func(("Cleared NMI window\n"));
8023 }
8024}
8025
8026
8027/**
8028 * Enters the VT-x session.
8029 *
8030 * @returns VBox status code.
8031 * @param pVCpu The cross context virtual CPU structure.
8032 */
8033VMMR0DECL(int) VMXR0Enter(PVMCPU pVCpu)
8034{
8035 AssertPtr(pVCpu);
8036 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported);
8037 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8038
8039 LogFlowFunc(("pVCpu=%p\n", pVCpu));
8040 Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8041 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
8042
8043#ifdef VBOX_STRICT
8044 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
8045 RTCCUINTREG uHostCR4 = ASMGetCR4();
8046 if (!(uHostCR4 & X86_CR4_VMXE))
8047 {
8048 LogRelFunc(("X86_CR4_VMXE bit in CR4 is not set!\n"));
8049 return VERR_VMX_X86_CR4_VMXE_CLEARED;
8050 }
8051#endif
8052
8053 /*
8054 * Load the VCPU's VMCS as the current (and active) one.
8055 */
8056 Assert(pVCpu->hm.s.vmx.fVmcsState & HMVMX_VMCS_STATE_CLEAR);
8057 int rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8058 if (RT_SUCCESS(rc))
8059 {
8060 pVCpu->hm.s.vmx.fVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8061 pVCpu->hm.s.fLeaveDone = false;
8062 Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8063
8064 /*
8065 * Do the EMT scheduled L1D flush here if needed.
8066 */
8067 if (pVCpu->CTX_SUFF(pVM)->hm.s.fL1dFlushOnSched)
8068 ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D);
8069 }
8070 return rc;
8071}
8072
8073
8074/**
8075 * The thread-context callback (only on platforms which support it).
8076 *
8077 * @param enmEvent The thread-context event.
8078 * @param pVCpu The cross context virtual CPU structure.
8079 * @param fGlobalInit Whether global VT-x/AMD-V init. was used.
8080 * @thread EMT(pVCpu)
8081 */
8082VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
8083{
8084 NOREF(fGlobalInit);
8085
8086 switch (enmEvent)
8087 {
8088 case RTTHREADCTXEVENT_OUT:
8089 {
8090 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8091 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8092 VMCPU_ASSERT_EMT(pVCpu);
8093
8094 /* No longjmps (logger flushes, locks) in this fragile context. */
8095 VMMRZCallRing3Disable(pVCpu);
8096 Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
8097
8098 /*
8099 * Restore host-state (FPU, debug etc.)
8100 */
8101 if (!pVCpu->hm.s.fLeaveDone)
8102 {
8103 /*
8104 * Do -not- import the guest-state here as we might already be in the middle of importing
8105 * it, esp. bad if we're holding the PGM lock, see comment in hmR0VmxImportGuestState().
8106 */
8107 hmR0VmxLeave(pVCpu, false /* fImportState */);
8108 pVCpu->hm.s.fLeaveDone = true;
8109 }
8110
8111 /* Leave HM context, takes care of local init (term). */
8112 int rc = HMR0LeaveCpu(pVCpu);
8113 AssertRC(rc); NOREF(rc);
8114
8115 /* Restore longjmp state. */
8116 VMMRZCallRing3Enable(pVCpu);
8117 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
8118 break;
8119 }
8120
8121 case RTTHREADCTXEVENT_IN:
8122 {
8123 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8124 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8125 VMCPU_ASSERT_EMT(pVCpu);
8126
8127 /* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
8128 VMMRZCallRing3Disable(pVCpu);
8129 Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
8130
8131 /* Initialize the bare minimum state required for HM. This takes care of
8132 initializing VT-x if necessary (onlined CPUs, local init etc.) */
8133 int rc = hmR0EnterCpu(pVCpu);
8134 AssertRC(rc);
8135 Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8136 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
8137
8138 /* Load the active VMCS as the current one. */
8139 if (pVCpu->hm.s.vmx.fVmcsState & HMVMX_VMCS_STATE_CLEAR)
8140 {
8141 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8142 AssertRC(rc); NOREF(rc);
8143 pVCpu->hm.s.vmx.fVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8144 Log4Func(("Resumed: Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8145 }
8146 pVCpu->hm.s.fLeaveDone = false;
8147
8148 /* Do the EMT scheduled L1D flush if needed. */
8149 if (pVCpu->CTX_SUFF(pVM)->hm.s.fL1dFlushOnSched)
8150 ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D);
8151
8152 /* Restore longjmp state. */
8153 VMMRZCallRing3Enable(pVCpu);
8154 break;
8155 }
8156
8157 default:
8158 break;
8159 }
8160}
8161
8162
8163/**
8164 * Exports the host state into the VMCS host-state area.
8165 * Sets up the VM-exit MSR-load area.
8166 *
8167 * The CPU state will be loaded from these fields on every successful VM-exit.
8168 *
8169 * @returns VBox status code.
8170 * @param pVCpu The cross context virtual CPU structure.
8171 *
8172 * @remarks No-long-jump zone!!!
8173 */
8174static int hmR0VmxExportHostState(PVMCPU pVCpu)
8175{
8176 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8177
8178 int rc = VINF_SUCCESS;
8179 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
8180 {
8181 rc = hmR0VmxExportHostControlRegs();
8182 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8183
8184 rc = hmR0VmxExportHostSegmentRegs(pVCpu);
8185 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8186
8187 rc = hmR0VmxExportHostMsrs(pVCpu);
8188 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8189
8190 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT;
8191 }
8192 return rc;
8193}
8194
8195
8196/**
8197 * Saves the host state in the VMCS host-state.
8198 *
8199 * @returns VBox status code.
8200 * @param pVCpu The cross context virtual CPU structure.
8201 *
8202 * @remarks No-long-jump zone!!!
8203 */
8204VMMR0DECL(int) VMXR0ExportHostState(PVMCPU pVCpu)
8205{
8206 AssertPtr(pVCpu);
8207 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8208
8209 /*
8210 * Export the host state here while entering HM context.
8211 * When thread-context hooks are used, we might get preempted and have to re-save the host
8212 * state but most of the time we won't be, so do it here before we disable interrupts.
8213 */
8214 return hmR0VmxExportHostState(pVCpu);
8215}
8216
8217
8218/**
8219 * Exports the guest state into the VMCS guest-state area.
8220 *
8221 * The will typically be done before VM-entry when the guest-CPU state and the
8222 * VMCS state may potentially be out of sync.
8223 *
8224 * Sets up the VM-entry MSR-load and VM-exit MSR-store areas. Sets up the
8225 * VM-entry controls.
8226 * Sets up the appropriate VMX non-root function to execute guest code based on
8227 * the guest CPU mode.
8228 *
8229 * @returns VBox strict status code.
8230 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8231 * without unrestricted guest access and the VMMDev is not presently
8232 * mapped (e.g. EFI32).
8233 *
8234 * @param pVCpu The cross context virtual CPU structure.
8235 *
8236 * @remarks No-long-jump zone!!!
8237 */
8238static VBOXSTRICTRC hmR0VmxExportGuestState(PVMCPU pVCpu)
8239{
8240 AssertPtr(pVCpu);
8241 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8242
8243 LogFlowFunc(("pVCpu=%p\n", pVCpu));
8244
8245 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
8246
8247 /* Determine real-on-v86 mode. */
8248 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
8249 if ( !pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest
8250 && CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx))
8251 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
8252
8253 /*
8254 * Any ordering dependency among the sub-functions below must be explicitly stated using comments.
8255 * Ideally, assert that the cross-dependent bits are up-to-date at the point of using it.
8256 */
8257 int rc = hmR0VmxSelectVMRunHandler(pVCpu);
8258 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8259
8260 /* This needs to be done after hmR0VmxSelectVMRunHandler() as changing pfnStartVM may require VM-entry control updates. */
8261 rc = hmR0VmxExportGuestEntryCtls(pVCpu);
8262 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8263
8264 /* This needs to be done after hmR0VmxSelectVMRunHandler() as changing pfnStartVM may require VM-exit control updates. */
8265 rc = hmR0VmxExportGuestExitCtls(pVCpu);
8266 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8267
8268 rc = hmR0VmxExportGuestCR0(pVCpu);
8269 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8270
8271 VBOXSTRICTRC rcStrict = hmR0VmxExportGuestCR3AndCR4(pVCpu);
8272 if (rcStrict == VINF_SUCCESS)
8273 { /* likely */ }
8274 else
8275 {
8276 Assert(rcStrict == VINF_EM_RESCHEDULE_REM || RT_FAILURE_NP(rcStrict));
8277 return rcStrict;
8278 }
8279
8280 rc = hmR0VmxExportGuestSegmentRegs(pVCpu);
8281 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8282
8283 /* This needs to be done after hmR0VmxExportGuestEntryCtls() and hmR0VmxExportGuestExitCtls() as it
8284 may alter controls if we determine we don't have to swap EFER after all. */
8285 rc = hmR0VmxExportGuestMsrs(pVCpu);
8286 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8287
8288 rc = hmR0VmxExportGuestApicTpr(pVCpu);
8289 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8290
8291 rc = hmR0VmxExportGuestXcptIntercepts(pVCpu);
8292 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8293
8294 rc = hmR0VmxExportGuestRip(pVCpu);
8295 rc |= hmR0VmxExportGuestRsp(pVCpu);
8296 rc |= hmR0VmxExportGuestRflags(pVCpu);
8297 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8298
8299 /* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
8300 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( (HM_CHANGED_GUEST_GPRS_MASK & ~HM_CHANGED_GUEST_RSP)
8301 | HM_CHANGED_GUEST_CR2
8302 | (HM_CHANGED_GUEST_DR_MASK & ~HM_CHANGED_GUEST_DR7)
8303 | HM_CHANGED_GUEST_X87
8304 | HM_CHANGED_GUEST_SSE_AVX
8305 | HM_CHANGED_GUEST_OTHER_XSAVE
8306 | HM_CHANGED_GUEST_XCRx
8307 | HM_CHANGED_GUEST_KERNEL_GS_BASE /* Part of lazy or auto load-store MSRs. */
8308 | HM_CHANGED_GUEST_SYSCALL_MSRS /* Part of lazy or auto load-store MSRs. */
8309 | HM_CHANGED_GUEST_TSC_AUX
8310 | HM_CHANGED_GUEST_OTHER_MSRS
8311 | HM_CHANGED_GUEST_HWVIRT
8312 | (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_VMX_MASK)));
8313
8314 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
8315 return rc;
8316}
8317
8318
8319/**
8320 * Exports the state shared between the host and guest into the VMCS.
8321 *
8322 * @param pVCpu The cross context virtual CPU structure.
8323 *
8324 * @remarks No-long-jump zone!!!
8325 */
8326static void hmR0VmxExportSharedState(PVMCPU pVCpu)
8327{
8328 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8329 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8330
8331 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
8332 {
8333 int rc = hmR0VmxExportSharedDebugState(pVCpu);
8334 AssertRC(rc);
8335 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
8336
8337 /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
8338 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_RFLAGS)
8339 {
8340 rc = hmR0VmxExportGuestRflags(pVCpu);
8341 AssertRC(rc);
8342 }
8343 }
8344
8345 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_GUEST_LAZY_MSRS)
8346 {
8347 hmR0VmxLazyLoadGuestMsrs(pVCpu);
8348 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_VMX_GUEST_LAZY_MSRS;
8349 }
8350
8351 AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE),
8352 ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
8353}
8354
8355
8356/**
8357 * Worker for loading the guest-state bits in the inner VT-x execution loop.
8358 *
8359 * @returns Strict VBox status code (i.e. informational status codes too).
8360 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8361 * without unrestricted guest access and the VMMDev is not presently
8362 * mapped (e.g. EFI32).
8363 *
8364 * @param pVCpu The cross context virtual CPU structure.
8365 *
8366 * @remarks No-long-jump zone!!!
8367 */
8368static VBOXSTRICTRC hmR0VmxExportGuestStateOptimal(PVMCPU pVCpu)
8369{
8370 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8371 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8372 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8373
8374#ifdef HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
8375 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
8376#endif
8377
8378 /*
8379 * For many exits it's only RIP that changes and hence try to export it first
8380 * without going through a lot of change flag checks.
8381 */
8382 VBOXSTRICTRC rcStrict;
8383 uint64_t fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
8384 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
8385 if ((fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)) == HM_CHANGED_GUEST_RIP)
8386 {
8387 rcStrict = hmR0VmxExportGuestRip(pVCpu);
8388 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8389 { /* likely */}
8390 else
8391 AssertMsgFailedReturn(("hmR0VmxExportGuestRip failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
8392 STAM_COUNTER_INC(&pVCpu->hm.s.StatExportMinimal);
8393 }
8394 else if (fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8395 {
8396 rcStrict = hmR0VmxExportGuestState(pVCpu);
8397 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8398 { /* likely */}
8399 else
8400 {
8401 AssertMsg(rcStrict == VINF_EM_RESCHEDULE_REM, ("hmR0VmxExportGuestState failed! rc=%Rrc\n",
8402 VBOXSTRICTRC_VAL(rcStrict)));
8403 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8404 return rcStrict;
8405 }
8406 STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
8407 }
8408 else
8409 rcStrict = VINF_SUCCESS;
8410
8411#ifdef VBOX_STRICT
8412 /* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
8413 fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
8414 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
8415 AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)),
8416 ("fCtxChanged=%#RX64\n", fCtxChanged));
8417#endif
8418 return rcStrict;
8419}
8420
8421
8422/**
8423 * Does the preparations before executing guest code in VT-x.
8424 *
8425 * This may cause longjmps to ring-3 and may even result in rescheduling to the
8426 * recompiler/IEM. We must be cautious what we do here regarding committing
8427 * guest-state information into the VMCS assuming we assuredly execute the
8428 * guest in VT-x mode.
8429 *
8430 * If we fall back to the recompiler/IEM after updating the VMCS and clearing
8431 * the common-state (TRPM/forceflags), we must undo those changes so that the
8432 * recompiler/IEM can (and should) use them when it resumes guest execution.
8433 * Otherwise such operations must be done when we can no longer exit to ring-3.
8434 *
8435 * @returns Strict VBox status code (i.e. informational status codes too).
8436 * @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
8437 * have been disabled.
8438 * @retval VINF_EM_RESET if a triple-fault occurs while injecting a
8439 * double-fault into the guest.
8440 * @retval VINF_EM_DBG_STEPPED if @a fStepping is true and an event was
8441 * dispatched directly.
8442 * @retval VINF_* scheduling changes, we have to go back to ring-3.
8443 *
8444 * @param pVCpu The cross context virtual CPU structure.
8445 * @param pVmxTransient Pointer to the VMX transient structure.
8446 * @param fStepping Set if called from hmR0VmxRunGuestCodeStep(). Makes
8447 * us ignore some of the reasons for returning to
8448 * ring-3, and return VINF_EM_DBG_STEPPED if event
8449 * dispatching took place.
8450 */
8451static VBOXSTRICTRC hmR0VmxPreRunGuest(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, bool fStepping)
8452{
8453 Assert(VMMRZCallRing3IsEnabled(pVCpu));
8454
8455#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
8456 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
8457 {
8458 Log2(("hmR0VmxPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
8459 RT_NOREF3(pVCpu, pVmxTransient, fStepping);
8460 return VINF_EM_RESCHEDULE_REM;
8461 }
8462#endif
8463
8464#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
8465 PGMRZDynMapFlushAutoSet(pVCpu);
8466#endif
8467
8468 /* Check force flag actions that might require us to go back to ring-3. */
8469 VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVCpu, fStepping);
8470 if (rcStrict == VINF_SUCCESS)
8471 { /* FFs doesn't get set all the time. */ }
8472 else
8473 return rcStrict;
8474
8475 /*
8476 * Setup the virtualized-APIC accesses.
8477 *
8478 * Note! This can cause a longjumps to R3 due to the acquisition of the PGM lock
8479 * in both PGMHandlerPhysicalReset() and IOMMMIOMapMMIOHCPage(), see @bugref{8721}.
8480 *
8481 * This is the reason we do it here and not in hmR0VmxExportGuestState().
8482 */
8483 PVM pVM = pVCpu->CTX_SUFF(pVM);
8484 if ( !pVCpu->hm.s.vmx.u64MsrApicBase
8485 && (pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
8486 && PDMHasApic(pVM))
8487 {
8488 uint64_t const u64MsrApicBase = APICGetBaseMsrNoCheck(pVCpu);
8489 Assert(u64MsrApicBase);
8490 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
8491
8492 RTGCPHYS const GCPhysApicBase = u64MsrApicBase & PAGE_BASE_GC_MASK;
8493
8494 /* Unalias any existing mapping. */
8495 int rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
8496 AssertRCReturn(rc, rc);
8497
8498 /* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */
8499 Log4Func(("Mapped HC APIC-access page at %#RGp\n", GCPhysApicBase));
8500 rc = IOMMMIOMapMMIOHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
8501 AssertRCReturn(rc, rc);
8502
8503 /* Update the per-VCPU cache of the APIC base MSR. */
8504 pVCpu->hm.s.vmx.u64MsrApicBase = u64MsrApicBase;
8505 }
8506
8507 if (TRPMHasTrap(pVCpu))
8508 hmR0VmxTrpmTrapToPendingEvent(pVCpu);
8509 uint32_t fIntrState = hmR0VmxEvaluatePendingEvent(pVCpu);
8510
8511 /*
8512 * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus
8513 * needs to be done with longjmps or interrupts + preemption enabled. Event injection might
8514 * also result in triple-faulting the VM.
8515 */
8516 rcStrict = hmR0VmxInjectPendingEvent(pVCpu, fIntrState, fStepping);
8517 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8518 { /* likely */ }
8519 else
8520 {
8521 AssertMsg(rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8522 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8523 return rcStrict;
8524 }
8525
8526 /*
8527 * A longjump might result in importing CR3 even for VM-exits that don't necessarily
8528 * import CR3 themselves. We will need to update them here, as even as late as the above
8529 * hmR0VmxInjectPendingEvent() call may lazily import guest-CPU state on demand causing
8530 * the below force flags to be set.
8531 */
8532 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
8533 {
8534 Assert(!(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_CR3));
8535 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
8536 AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
8537 ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
8538 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
8539 }
8540 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
8541 {
8542 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
8543 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
8544 }
8545
8546 /*
8547 * No longjmps to ring-3 from this point on!!!
8548 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
8549 * This also disables flushing of the R0-logger instance (if any).
8550 */
8551 VMMRZCallRing3Disable(pVCpu);
8552
8553 /*
8554 * Export the guest state bits.
8555 *
8556 * We cannot perform longjmps while loading the guest state because we do not preserve the
8557 * host/guest state (although the VMCS will be preserved) across longjmps which can cause
8558 * CPU migration.
8559 *
8560 * If we are injecting events to a real-on-v86 mode guest, we will have to update
8561 * RIP and some segment registers, i.e. hmR0VmxInjectPendingEvent()->hmR0VmxInjectEventVmcs().
8562 * Hence, loading of the guest state needs to be done -after- injection of events.
8563 */
8564 rcStrict = hmR0VmxExportGuestStateOptimal(pVCpu);
8565 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8566 { /* likely */ }
8567 else
8568 {
8569 VMMRZCallRing3Enable(pVCpu);
8570 return rcStrict;
8571 }
8572
8573 /*
8574 * We disable interrupts so that we don't miss any interrupts that would flag preemption
8575 * (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
8576 * preemption disabled for a while. Since this is purly to aid the
8577 * RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
8578 * disable interrupt on NT.
8579 *
8580 * We need to check for force-flags that could've possible been altered since we last
8581 * checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
8582 * see @bugref{6398}).
8583 *
8584 * We also check a couple of other force-flags as a last opportunity to get the EMT back
8585 * to ring-3 before executing guest code.
8586 */
8587 pVmxTransient->fEFlags = ASMIntDisableFlags();
8588
8589 if ( ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
8590 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
8591 || ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */
8592 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT))) )
8593 {
8594 if (!RTThreadPreemptIsPending(NIL_RTTHREAD))
8595 {
8596 pVCpu->hm.s.Event.fPending = false;
8597
8598 /*
8599 * We've injected any pending events. This is really the point of no return (to ring-3).
8600 *
8601 * Note! The caller expects to continue with interrupts & longjmps disabled on successful
8602 * returns from this function, so don't enable them here.
8603 */
8604 return VINF_SUCCESS;
8605 }
8606
8607 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
8608 rcStrict = VINF_EM_RAW_INTERRUPT;
8609 }
8610 else
8611 {
8612 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
8613 rcStrict = VINF_EM_RAW_TO_R3;
8614 }
8615
8616 ASMSetFlags(pVmxTransient->fEFlags);
8617 VMMRZCallRing3Enable(pVCpu);
8618
8619 return rcStrict;
8620}
8621
8622
8623/**
8624 * Prepares to run guest code in VT-x and we've committed to doing so. This
8625 * means there is no backing out to ring-3 or anywhere else at this
8626 * point.
8627 *
8628 * @param pVCpu The cross context virtual CPU structure.
8629 * @param pVmxTransient Pointer to the VMX transient structure.
8630 *
8631 * @remarks Called with preemption disabled.
8632 * @remarks No-long-jump zone!!!
8633 */
8634static void hmR0VmxPreRunGuestCommitted(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
8635{
8636 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8637 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8638 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8639
8640 /*
8641 * Indicate start of guest execution and where poking EMT out of guest-context is recognized.
8642 */
8643 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8644 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
8645
8646 PVM pVM = pVCpu->CTX_SUFF(pVM);
8647 if (!CPUMIsGuestFPUStateActive(pVCpu))
8648 {
8649 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
8650 if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
8651 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT;
8652 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
8653 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
8654 }
8655
8656 /*
8657 * Lazy-update of the host MSRs values in the auto-load/store MSR area.
8658 */
8659 if ( !pVCpu->hm.s.vmx.fUpdatedHostMsrs
8660 && pVCpu->hm.s.vmx.cMsrs > 0)
8661 hmR0VmxUpdateAutoLoadStoreHostMsrs(pVCpu);
8662
8663 /*
8664 * Re-save the host state bits as we may've been preempted (only happens when
8665 * thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
8666 * Note that the 64-on-32 switcher saves the (64-bit) host state into the VMCS and
8667 * if we change the switcher back to 32-bit, we *must* save the 32-bit host state here.
8668 * See @bugref{8432}.
8669 */
8670 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
8671 {
8672 int rc = hmR0VmxExportHostState(pVCpu);
8673 AssertRC(rc);
8674 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreemptExportHostState);
8675 }
8676 Assert(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT));
8677
8678 /*
8679 * Export the state shared between host and guest (FPU, debug, lazy MSRs).
8680 */
8681 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)
8682 hmR0VmxExportSharedState(pVCpu);
8683 AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
8684
8685 /* Store status of the shared guest-host state at the time of VM-entry. */
8686#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
8687 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
8688 {
8689 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
8690 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
8691 }
8692 else
8693#endif
8694 {
8695 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
8696 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
8697 }
8698
8699 /*
8700 * Cache the TPR-shadow for checking on every VM-exit if it might have changed.
8701 */
8702 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
8703 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR];
8704
8705 PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
8706 RTCPUID idCurrentCpu = pHostCpu->idCpu;
8707 if ( pVmxTransient->fUpdateTscOffsettingAndPreemptTimer
8708 || idCurrentCpu != pVCpu->hm.s.idLastCpu)
8709 {
8710 hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVCpu);
8711 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
8712 }
8713
8714 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
8715 hmR0VmxFlushTaggedTlb(pHostCpu, pVCpu); /* Invalidate the appropriate guest entries from the TLB. */
8716 Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
8717 pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Update the error reporting info. with the current host CPU. */
8718
8719 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
8720
8721 TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
8722 to start executing. */
8723
8724 /*
8725 * Load the TSC_AUX MSR when we are not intercepting RDTSCP.
8726 */
8727 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 & VMX_PROC_CTLS2_RDTSCP)
8728 {
8729 if (!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
8730 {
8731 bool fMsrUpdated;
8732 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
8733 int rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, CPUMGetGuestTscAux(pVCpu), true /* fUpdateHostMsr */,
8734 &fMsrUpdated);
8735 AssertRC(rc2);
8736 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8737 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8738 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8739 }
8740 else
8741 {
8742 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX);
8743 Assert(!pVCpu->hm.s.vmx.cMsrs || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8744 }
8745 }
8746
8747 if (pVM->cpum.ro.GuestFeatures.fIbrs)
8748 {
8749 bool fMsrUpdated;
8750 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_OTHER_MSRS);
8751 int rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_IA32_SPEC_CTRL, CPUMGetGuestSpecCtrl(pVCpu), true /* fUpdateHostMsr */,
8752 &fMsrUpdated);
8753 AssertRC(rc2);
8754 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8755 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8756 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8757 }
8758
8759#ifdef VBOX_STRICT
8760 hmR0VmxCheckAutoLoadStoreMsrs(pVCpu);
8761 hmR0VmxCheckHostEferMsr(pVCpu);
8762 AssertRC(hmR0VmxCheckVmcsCtls(pVCpu));
8763#endif
8764#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
8765 if (!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
8766 {
8767 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu);
8768 if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
8769 Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
8770 }
8771#endif
8772}
8773
8774
8775/**
8776 * Performs some essential restoration of state after running guest code in
8777 * VT-x.
8778 *
8779 * @param pVCpu The cross context virtual CPU structure.
8780 * @param pVmxTransient Pointer to the VMX transient structure.
8781 * @param rcVMRun Return code of VMLAUNCH/VMRESUME.
8782 *
8783 * @remarks Called with interrupts disabled, and returns with interrupts enabled!
8784 *
8785 * @remarks No-long-jump zone!!! This function will however re-enable longjmps
8786 * unconditionally when it is safe to do so.
8787 */
8788static void hmR0VmxPostRunGuest(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, int rcVMRun)
8789{
8790 uint64_t const uHostTsc = ASMReadTSC();
8791 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8792
8793 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
8794 ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
8795 pVCpu->hm.s.fCtxChanged = 0; /* Exits/longjmps to ring-3 requires saving the guest state. */
8796 pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
8797 pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
8798 pVmxTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
8799
8800 if (!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
8801 TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVCpu->hm.s.vmx.Ctls.u64TscOffset);
8802
8803 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
8804 TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
8805 Assert(!ASMIntAreEnabled());
8806 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8807
8808#if HC_ARCH_BITS == 64
8809 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_REQUIRED; /* Host state messed up by VT-x, we must restore. */
8810#endif
8811#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
8812 /* The 64-on-32 switcher maintains fVmcsState on its own and we need to leave it alone here. */
8813 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
8814 pVCpu->hm.s.vmx.fVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8815#else
8816 pVCpu->hm.s.vmx.fVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8817#endif
8818#ifdef VBOX_STRICT
8819 hmR0VmxCheckHostEferMsr(pVCpu); /* Verify that VMRUN/VMLAUNCH didn't modify host EFER. */
8820#endif
8821 ASMSetFlags(pVmxTransient->fEFlags); /* Enable interrupts. */
8822
8823 /* Save the basic VM-exit reason. Refer Intel spec. 24.9.1 "Basic VM-exit Information". */
8824 uint32_t uExitReason;
8825 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
8826 rc |= hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
8827 AssertRC(rc);
8828 pVmxTransient->uExitReason = VMX_EXIT_REASON_BASIC(uExitReason);
8829 pVmxTransient->fVMEntryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
8830
8831 if (rcVMRun == VINF_SUCCESS)
8832 {
8833 /*
8834 * Update the VM-exit history array here even if the VM-entry failed due to:
8835 * - Invalid guest state.
8836 * - MSR loading.
8837 * - Machine-check event.
8838 *
8839 * In any of the above cases we will still have a "valid" VM-exit reason
8840 * despite @a fVMEntryFailed being false.
8841 *
8842 * See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
8843 *
8844 * Note! We don't have CS or RIP at this point. Will probably address that later
8845 * by amending the history entry added here.
8846 */
8847 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_VMX, pVmxTransient->uExitReason & EMEXIT_F_TYPE_MASK),
8848 UINT64_MAX, uHostTsc);
8849
8850 if (!pVmxTransient->fVMEntryFailed)
8851 {
8852 VMMRZCallRing3Enable(pVCpu);
8853
8854 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
8855 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
8856
8857#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) || defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
8858 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
8859 AssertRC(rc);
8860#elif defined(HMVMX_ALWAYS_SAVE_GUEST_RFLAGS)
8861 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_RFLAGS);
8862 AssertRC(rc);
8863#else
8864 /*
8865 * Import the guest-interruptibility state always as we need it while evaluating
8866 * injecting events on re-entry.
8867 *
8868 * We don't import CR0 (when Unrestricted guest execution is unavailable) despite
8869 * checking for real-mode while exporting the state because all bits that cause
8870 * mode changes wrt CR0 are intercepted.
8871 */
8872 rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_HM_VMX_INT_STATE);
8873 AssertRC(rc);
8874#endif
8875
8876 /*
8877 * Sync the TPR shadow with our APIC state.
8878 */
8879 if ( (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
8880 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR])
8881 {
8882 rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]);
8883 AssertRC(rc);
8884 ASMAtomicOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
8885 }
8886
8887 Assert(VMMRZCallRing3IsEnabled(pVCpu));
8888 return;
8889 }
8890 }
8891 else
8892 Log4Func(("VM-entry failure: rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", rcVMRun, pVmxTransient->fVMEntryFailed));
8893
8894 VMMRZCallRing3Enable(pVCpu);
8895}
8896
8897
8898/**
8899 * Runs the guest code using VT-x the normal way.
8900 *
8901 * @returns VBox status code.
8902 * @param pVCpu The cross context virtual CPU structure.
8903 *
8904 * @note Mostly the same as hmR0VmxRunGuestCodeStep().
8905 */
8906static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVMCPU pVCpu)
8907{
8908 VMXTRANSIENT VmxTransient;
8909 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
8910 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
8911 uint32_t cLoops = 0;
8912
8913 for (;; cLoops++)
8914 {
8915 Assert(!HMR0SuspendPending());
8916 HMVMX_ASSERT_CPU_SAFE(pVCpu);
8917
8918 /* Preparatory work for running guest code, this may force us to return
8919 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
8920 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
8921 rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, false /* fStepping */);
8922 if (rcStrict != VINF_SUCCESS)
8923 break;
8924
8925 hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
8926 int rcRun = hmR0VmxRunGuest(pVCpu);
8927
8928 /* Restore any residual host-state and save any bits shared between host
8929 and guest into the guest-CPU state. Re-enables interrupts! */
8930 hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
8931
8932 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
8933 if (RT_SUCCESS(rcRun))
8934 { /* very likely */ }
8935 else
8936 {
8937 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
8938 hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
8939 return rcRun;
8940 }
8941
8942 /* Profile the VM-exit. */
8943 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
8944 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
8945 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
8946 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
8947 HMVMX_START_EXIT_DISPATCH_PROF();
8948
8949 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
8950
8951 /* Handle the VM-exit. */
8952#ifdef HMVMX_USE_FUNCTION_TABLE
8953 rcStrict = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, &VmxTransient);
8954#else
8955 rcStrict = hmR0VmxHandleExit(pVCpu, &VmxTransient, VmxTransient.uExitReason);
8956#endif
8957 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
8958 if (rcStrict == VINF_SUCCESS)
8959 {
8960 if (cLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
8961 continue; /* likely */
8962 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
8963 rcStrict = VINF_EM_RAW_INTERRUPT;
8964 }
8965 break;
8966 }
8967
8968 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
8969 return rcStrict;
8970}
8971
8972
8973
8974/** @name Execution loop for single stepping, DBGF events and expensive Dtrace
8975 * probes.
8976 *
8977 * The following few functions and associated structure contains the bloat
8978 * necessary for providing detailed debug events and dtrace probes as well as
8979 * reliable host side single stepping. This works on the principle of
8980 * "subclassing" the normal execution loop and workers. We replace the loop
8981 * method completely and override selected helpers to add necessary adjustments
8982 * to their core operation.
8983 *
8984 * The goal is to keep the "parent" code lean and mean, so as not to sacrifice
8985 * any performance for debug and analysis features.
8986 *
8987 * @{
8988 */
8989
8990/**
8991 * Transient per-VCPU debug state of VMCS and related info. we save/restore in
8992 * the debug run loop.
8993 */
8994typedef struct VMXRUNDBGSTATE
8995{
8996 /** The RIP we started executing at. This is for detecting that we stepped. */
8997 uint64_t uRipStart;
8998 /** The CS we started executing with. */
8999 uint16_t uCsStart;
9000
9001 /** Whether we've actually modified the 1st execution control field. */
9002 bool fModifiedProcCtls : 1;
9003 /** Whether we've actually modified the 2nd execution control field. */
9004 bool fModifiedProcCtls2 : 1;
9005 /** Whether we've actually modified the exception bitmap. */
9006 bool fModifiedXcptBitmap : 1;
9007
9008 /** We desire the modified the CR0 mask to be cleared. */
9009 bool fClearCr0Mask : 1;
9010 /** We desire the modified the CR4 mask to be cleared. */
9011 bool fClearCr4Mask : 1;
9012 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC. */
9013 uint32_t fCpe1Extra;
9014 /** Stuff we do not want in VMX_VMCS32_CTRL_PROC_EXEC. */
9015 uint32_t fCpe1Unwanted;
9016 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC2. */
9017 uint32_t fCpe2Extra;
9018 /** Extra stuff we need in VMX_VMCS32_CTRL_EXCEPTION_BITMAP. */
9019 uint32_t bmXcptExtra;
9020 /** The sequence number of the Dtrace provider settings the state was
9021 * configured against. */
9022 uint32_t uDtraceSettingsSeqNo;
9023 /** VM-exits to check (one bit per VM-exit). */
9024 uint32_t bmExitsToCheck[3];
9025
9026 /** The initial VMX_VMCS32_CTRL_PROC_EXEC value (helps with restore). */
9027 uint32_t fProcCtlsInitial;
9028 /** The initial VMX_VMCS32_CTRL_PROC_EXEC2 value (helps with restore). */
9029 uint32_t fProcCtls2Initial;
9030 /** The initial VMX_VMCS32_CTRL_EXCEPTION_BITMAP value (helps with restore). */
9031 uint32_t bmXcptInitial;
9032} VMXRUNDBGSTATE;
9033AssertCompileMemberSize(VMXRUNDBGSTATE, bmExitsToCheck, (VMX_EXIT_MAX + 1 + 31) / 32 * 4);
9034typedef VMXRUNDBGSTATE *PVMXRUNDBGSTATE;
9035
9036
9037/**
9038 * Initializes the VMXRUNDBGSTATE structure.
9039 *
9040 * @param pVCpu The cross context virtual CPU structure of the
9041 * calling EMT.
9042 * @param pDbgState The structure to initialize.
9043 */
9044static void hmR0VmxRunDebugStateInit(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9045{
9046 pDbgState->uRipStart = pVCpu->cpum.GstCtx.rip;
9047 pDbgState->uCsStart = pVCpu->cpum.GstCtx.cs.Sel;
9048
9049 pDbgState->fModifiedProcCtls = false;
9050 pDbgState->fModifiedProcCtls2 = false;
9051 pDbgState->fModifiedXcptBitmap = false;
9052 pDbgState->fClearCr0Mask = false;
9053 pDbgState->fClearCr4Mask = false;
9054 pDbgState->fCpe1Extra = 0;
9055 pDbgState->fCpe1Unwanted = 0;
9056 pDbgState->fCpe2Extra = 0;
9057 pDbgState->bmXcptExtra = 0;
9058 pDbgState->fProcCtlsInitial = pVCpu->hm.s.vmx.Ctls.u32ProcCtls;
9059 pDbgState->fProcCtls2Initial = pVCpu->hm.s.vmx.Ctls.u32ProcCtls2;
9060 pDbgState->bmXcptInitial = pVCpu->hm.s.vmx.Ctls.u32XcptBitmap;
9061}
9062
9063
9064/**
9065 * Updates the VMSC fields with changes requested by @a pDbgState.
9066 *
9067 * This is performed after hmR0VmxPreRunGuestDebugStateUpdate as well
9068 * immediately before executing guest code, i.e. when interrupts are disabled.
9069 * We don't check status codes here as we cannot easily assert or return in the
9070 * latter case.
9071 *
9072 * @param pVCpu The cross context virtual CPU structure.
9073 * @param pDbgState The debug state.
9074 */
9075static void hmR0VmxPreRunGuestDebugStateApply(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9076{
9077 /*
9078 * Ensure desired flags in VMCS control fields are set.
9079 * (Ignoring write failure here, as we're committed and it's just debug extras.)
9080 *
9081 * Note! We load the shadow CR0 & CR4 bits when we flag the clearing, so
9082 * there should be no stale data in pCtx at this point.
9083 */
9084 if ( (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & pDbgState->fCpe1Extra) != pDbgState->fCpe1Extra
9085 || (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & pDbgState->fCpe1Unwanted))
9086 {
9087 pVCpu->hm.s.vmx.Ctls.u32ProcCtls |= pDbgState->fCpe1Extra;
9088 pVCpu->hm.s.vmx.Ctls.u32ProcCtls &= ~pDbgState->fCpe1Unwanted;
9089 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.Ctls.u32ProcCtls);
9090 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVCpu->hm.s.vmx.Ctls.u32ProcCtls));
9091 pDbgState->fModifiedProcCtls = true;
9092 }
9093
9094 if ((pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 & pDbgState->fCpe2Extra) != pDbgState->fCpe2Extra)
9095 {
9096 pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 |= pDbgState->fCpe2Extra;
9097 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVCpu->hm.s.vmx.Ctls.u32ProcCtls2);
9098 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVCpu->hm.s.vmx.Ctls.u32ProcCtls2));
9099 pDbgState->fModifiedProcCtls2 = true;
9100 }
9101
9102 if ((pVCpu->hm.s.vmx.Ctls.u32XcptBitmap & pDbgState->bmXcptExtra) != pDbgState->bmXcptExtra)
9103 {
9104 pVCpu->hm.s.vmx.Ctls.u32XcptBitmap |= pDbgState->bmXcptExtra;
9105 VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.Ctls.u32XcptBitmap);
9106 Log6Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVCpu->hm.s.vmx.Ctls.u32XcptBitmap));
9107 pDbgState->fModifiedXcptBitmap = true;
9108 }
9109
9110 if (pDbgState->fClearCr0Mask && pVCpu->hm.s.vmx.Ctls.u32Cr0Mask != 0)
9111 {
9112 pVCpu->hm.s.vmx.Ctls.u32Cr0Mask = 0;
9113 VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, 0);
9114 Log6Func(("VMX_VMCS_CTRL_CR0_MASK: 0\n"));
9115 }
9116
9117 if (pDbgState->fClearCr4Mask && pVCpu->hm.s.vmx.Ctls.u32Cr4Mask != 0)
9118 {
9119 pVCpu->hm.s.vmx.Ctls.u32Cr4Mask = 0;
9120 VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, 0);
9121 Log6Func(("VMX_VMCS_CTRL_CR4_MASK: 0\n"));
9122 }
9123}
9124
9125
9126/**
9127 * Restores VMCS fields that were changed by hmR0VmxPreRunGuestDebugStateApply for
9128 * re-entry next time around.
9129 *
9130 * @returns Strict VBox status code (i.e. informational status codes too).
9131 * @param pVCpu The cross context virtual CPU structure.
9132 * @param pDbgState The debug state.
9133 * @param rcStrict The return code from executing the guest using single
9134 * stepping.
9135 */
9136static VBOXSTRICTRC hmR0VmxRunDebugStateRevert(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, VBOXSTRICTRC rcStrict)
9137{
9138 /*
9139 * Restore VM-exit control settings as we may not reenter this function the
9140 * next time around.
9141 */
9142 /* We reload the initial value, trigger what we can of recalculations the
9143 next time around. From the looks of things, that's all that's required atm. */
9144 if (pDbgState->fModifiedProcCtls)
9145 {
9146 if (!(pDbgState->fProcCtlsInitial & VMX_PROC_CTLS_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
9147 pDbgState->fProcCtlsInitial |= VMX_PROC_CTLS_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
9148 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
9149 AssertRCReturn(rc2, rc2);
9150 pVCpu->hm.s.vmx.Ctls.u32ProcCtls = pDbgState->fProcCtlsInitial;
9151 }
9152
9153 /* We're currently the only ones messing with this one, so just restore the
9154 cached value and reload the field. */
9155 if ( pDbgState->fModifiedProcCtls2
9156 && pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 != pDbgState->fProcCtls2Initial)
9157 {
9158 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);
9159 AssertRCReturn(rc2, rc2);
9160 pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 = pDbgState->fProcCtls2Initial;
9161 }
9162
9163 /* If we've modified the exception bitmap, we restore it and trigger
9164 reloading and partial recalculation the next time around. */
9165 if (pDbgState->fModifiedXcptBitmap)
9166 pVCpu->hm.s.vmx.Ctls.u32XcptBitmap = pDbgState->bmXcptInitial;
9167
9168 return rcStrict;
9169}
9170
9171
9172/**
9173 * Configures VM-exit controls for current DBGF and DTrace settings.
9174 *
9175 * This updates @a pDbgState and the VMCS execution control fields to reflect
9176 * the necessary VM-exits demanded by DBGF and DTrace.
9177 *
9178 * @param pVCpu The cross context virtual CPU structure.
9179 * @param pDbgState The debug state.
9180 * @param pVmxTransient Pointer to the VMX transient structure. May update
9181 * fUpdateTscOffsettingAndPreemptTimer.
9182 */
9183static void hmR0VmxPreRunGuestDebugStateUpdate(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, PVMXTRANSIENT pVmxTransient)
9184{
9185 /*
9186 * Take down the dtrace serial number so we can spot changes.
9187 */
9188 pDbgState->uDtraceSettingsSeqNo = VBOXVMM_GET_SETTINGS_SEQ_NO();
9189 ASMCompilerBarrier();
9190
9191 /*
9192 * We'll rebuild most of the middle block of data members (holding the
9193 * current settings) as we go along here, so start by clearing it all.
9194 */
9195 pDbgState->bmXcptExtra = 0;
9196 pDbgState->fCpe1Extra = 0;
9197 pDbgState->fCpe1Unwanted = 0;
9198 pDbgState->fCpe2Extra = 0;
9199 for (unsigned i = 0; i < RT_ELEMENTS(pDbgState->bmExitsToCheck); i++)
9200 pDbgState->bmExitsToCheck[i] = 0;
9201
9202 /*
9203 * Software interrupts (INT XXh) - no idea how to trigger these...
9204 */
9205 PVM pVM = pVCpu->CTX_SUFF(pVM);
9206 if ( DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_INTERRUPT_SOFTWARE)
9207 || VBOXVMM_INT_SOFTWARE_ENABLED())
9208 {
9209 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9210 }
9211
9212 /*
9213 * INT3 breakpoints - triggered by #BP exceptions.
9214 */
9215 if (pVM->dbgf.ro.cEnabledInt3Breakpoints > 0)
9216 pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9217
9218 /*
9219 * Exception bitmap and XCPT events+probes.
9220 */
9221 for (int iXcpt = 0; iXcpt < (DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST + 1); iXcpt++)
9222 if (DBGF_IS_EVENT_ENABLED(pVM, (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + iXcpt)))
9223 pDbgState->bmXcptExtra |= RT_BIT_32(iXcpt);
9224
9225 if (VBOXVMM_XCPT_DE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DE);
9226 if (VBOXVMM_XCPT_DB_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DB);
9227 if (VBOXVMM_XCPT_BP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9228 if (VBOXVMM_XCPT_OF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_OF);
9229 if (VBOXVMM_XCPT_BR_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BR);
9230 if (VBOXVMM_XCPT_UD_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_UD);
9231 if (VBOXVMM_XCPT_NM_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NM);
9232 if (VBOXVMM_XCPT_DF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DF);
9233 if (VBOXVMM_XCPT_TS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_TS);
9234 if (VBOXVMM_XCPT_NP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NP);
9235 if (VBOXVMM_XCPT_SS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SS);
9236 if (VBOXVMM_XCPT_GP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_GP);
9237 if (VBOXVMM_XCPT_PF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_PF);
9238 if (VBOXVMM_XCPT_MF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_MF);
9239 if (VBOXVMM_XCPT_AC_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_AC);
9240 if (VBOXVMM_XCPT_XF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_XF);
9241 if (VBOXVMM_XCPT_VE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_VE);
9242 if (VBOXVMM_XCPT_SX_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SX);
9243
9244 if (pDbgState->bmXcptExtra)
9245 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9246
9247 /*
9248 * Process events and probes for VM-exits, making sure we get the wanted VM-exits.
9249 *
9250 * Note! This is the reverse of what hmR0VmxHandleExitDtraceEvents does.
9251 * So, when adding/changing/removing please don't forget to update it.
9252 *
9253 * Some of the macros are picking up local variables to save horizontal space,
9254 * (being able to see it in a table is the lesser evil here).
9255 */
9256#define IS_EITHER_ENABLED(a_pVM, a_EventSubName) \
9257 ( DBGF_IS_EVENT_ENABLED(a_pVM, RT_CONCAT(DBGFEVENT_, a_EventSubName)) \
9258 || RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)() )
9259#define SET_ONLY_XBM_IF_EITHER_EN(a_EventSubName, a_uExit) \
9260 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9261 { AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9262 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9263 } else do { } while (0)
9264#define SET_CPE1_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec) \
9265 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9266 { \
9267 (pDbgState)->fCpe1Extra |= (a_fCtrlProcExec); \
9268 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9269 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9270 } else do { } while (0)
9271#define SET_CPEU_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fUnwantedCtrlProcExec) \
9272 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9273 { \
9274 (pDbgState)->fCpe1Unwanted |= (a_fUnwantedCtrlProcExec); \
9275 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9276 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9277 } else do { } while (0)
9278#define SET_CPE2_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec2) \
9279 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9280 { \
9281 (pDbgState)->fCpe2Extra |= (a_fCtrlProcExec2); \
9282 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9283 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9284 } else do { } while (0)
9285
9286 SET_ONLY_XBM_IF_EITHER_EN(EXIT_TASK_SWITCH, VMX_EXIT_TASK_SWITCH); /* unconditional */
9287 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_VIOLATION, VMX_EXIT_EPT_VIOLATION); /* unconditional */
9288 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_MISCONFIG, VMX_EXIT_EPT_MISCONFIG); /* unconditional (unless #VE) */
9289 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_ACCESS, VMX_EXIT_APIC_ACCESS); /* feature dependent, nothing to enable here */
9290 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */
9291
9292 SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */
9293 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID);
9294 SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */
9295 SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC);
9296 SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_PROC_CTLS_HLT_EXIT); /* paranoia */
9297 SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT);
9298 SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */
9299 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD);
9300 SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_PROC_CTLS_INVLPG_EXIT);
9301 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG);
9302 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_PROC_CTLS_RDPMC_EXIT);
9303 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC);
9304 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_PROC_CTLS_RDTSC_EXIT);
9305 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC);
9306 SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */
9307 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM);
9308 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */
9309 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL);
9310 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */
9311 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR);
9312 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */
9313 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH);
9314 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */
9315 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD);
9316 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */
9317 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST);
9318 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */
9319 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD);
9320 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */
9321 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME);
9322 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */
9323 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE);
9324 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */
9325 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF);
9326 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */
9327 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON);
9328
9329 if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)
9330 || IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9331 {
9332 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_APIC_TPR);
9333 AssertRC(rc);
9334
9335#if 0 /** @todo fix me */
9336 pDbgState->fClearCr0Mask = true;
9337 pDbgState->fClearCr4Mask = true;
9338#endif
9339 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
9340 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_STORE_EXIT | VMX_PROC_CTLS_CR8_STORE_EXIT;
9341 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9342 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_LOAD_EXIT | VMX_PROC_CTLS_CR8_LOAD_EXIT;
9343 pDbgState->fCpe1Unwanted |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* risky? */
9344 /* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT. It would
9345 require clearing here and in the loop if we start using it. */
9346 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_CRX);
9347 }
9348 else
9349 {
9350 if (pDbgState->fClearCr0Mask)
9351 {
9352 pDbgState->fClearCr0Mask = false;
9353 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
9354 }
9355 if (pDbgState->fClearCr4Mask)
9356 {
9357 pDbgState->fClearCr4Mask = false;
9358 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
9359 }
9360 }
9361 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX);
9362 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX);
9363
9364 if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ)
9365 || IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE))
9366 {
9367 /** @todo later, need to fix handler as it assumes this won't usually happen. */
9368 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX);
9369 }
9370 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX);
9371 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX);
9372
9373 SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS); /* risky clearing this? */
9374 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR);
9375 SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS);
9376 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR);
9377 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_PROC_CTLS_MWAIT_EXIT); /* paranoia */
9378 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT);
9379 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_PROC_CTLS_MONITOR_EXIT); /* paranoia */
9380 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR);
9381#if 0 /** @todo too slow, fix handler. */
9382 SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_PROC_CTLS_PAUSE_EXIT);
9383#endif
9384 SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE);
9385
9386 if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT)
9387 || IS_EITHER_ENABLED(pVM, INSTR_SIDT)
9388 || IS_EITHER_ENABLED(pVM, INSTR_LGDT)
9389 || IS_EITHER_ENABLED(pVM, INSTR_LIDT))
9390 {
9391 pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
9392 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_GDTR_IDTR_ACCESS);
9393 }
9394 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9395 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9396 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9397 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9398
9399 if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT)
9400 || IS_EITHER_ENABLED(pVM, INSTR_STR)
9401 || IS_EITHER_ENABLED(pVM, INSTR_LLDT)
9402 || IS_EITHER_ENABLED(pVM, INSTR_LTR))
9403 {
9404 pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
9405 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_LDTR_TR_ACCESS);
9406 }
9407 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_LDTR_TR_ACCESS);
9408 SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_LDTR_TR_ACCESS);
9409 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_LDTR_TR_ACCESS);
9410 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_LDTR_TR_ACCESS);
9411
9412 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */
9413 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT);
9414 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_PROC_CTLS_RDTSC_EXIT);
9415 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP);
9416 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */
9417 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID);
9418 SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_PROC_CTLS2_WBINVD_EXIT);
9419 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD);
9420 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */
9421 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV);
9422 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_PROC_CTLS2_RDRAND_EXIT);
9423 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND);
9424 SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_PROC_CTLS_INVLPG_EXIT);
9425 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID);
9426 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */
9427 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC);
9428 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_PROC_CTLS2_RDSEED_EXIT);
9429 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED);
9430 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */
9431 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES);
9432 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */
9433 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS);
9434
9435#undef IS_EITHER_ENABLED
9436#undef SET_ONLY_XBM_IF_EITHER_EN
9437#undef SET_CPE1_XBM_IF_EITHER_EN
9438#undef SET_CPEU_XBM_IF_EITHER_EN
9439#undef SET_CPE2_XBM_IF_EITHER_EN
9440
9441 /*
9442 * Sanitize the control stuff.
9443 */
9444 pDbgState->fCpe2Extra &= pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1;
9445 if (pDbgState->fCpe2Extra)
9446 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
9447 pDbgState->fCpe1Extra &= pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1;
9448 pDbgState->fCpe1Unwanted &= ~pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed0;
9449 if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_PROC_CTLS_RDTSC_EXIT))
9450 {
9451 pVCpu->hm.s.fDebugWantRdTscExit ^= true;
9452 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9453 }
9454
9455 Log6(("HM: debug state: cpe1=%#RX32 cpeu=%#RX32 cpe2=%#RX32%s%s\n",
9456 pDbgState->fCpe1Extra, pDbgState->fCpe1Unwanted, pDbgState->fCpe2Extra,
9457 pDbgState->fClearCr0Mask ? " clr-cr0" : "",
9458 pDbgState->fClearCr4Mask ? " clr-cr4" : ""));
9459}
9460
9461
9462/**
9463 * Fires off DBGF events and dtrace probes for a VM-exit, when it's
9464 * appropriate.
9465 *
9466 * The caller has checked the VM-exit against the
9467 * VMXRUNDBGSTATE::bmExitsToCheck bitmap. The caller has checked for NMIs
9468 * already, so we don't have to do that either.
9469 *
9470 * @returns Strict VBox status code (i.e. informational status codes too).
9471 * @param pVCpu The cross context virtual CPU structure.
9472 * @param pVmxTransient Pointer to the VMX-transient structure.
9473 * @param uExitReason The VM-exit reason.
9474 *
9475 * @remarks The name of this function is displayed by dtrace, so keep it short
9476 * and to the point. No longer than 33 chars long, please.
9477 */
9478static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
9479{
9480 /*
9481 * Translate the event into a DBGF event (enmEvent + uEventArg) and at the
9482 * same time check whether any corresponding Dtrace event is enabled (fDtrace).
9483 *
9484 * Note! This is the reverse operation of what hmR0VmxPreRunGuestDebugStateUpdate
9485 * does. Must add/change/remove both places. Same ordering, please.
9486 *
9487 * Added/removed events must also be reflected in the next section
9488 * where we dispatch dtrace events.
9489 */
9490 bool fDtrace1 = false;
9491 bool fDtrace2 = false;
9492 DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END;
9493 DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END;
9494 uint32_t uEventArg = 0;
9495#define SET_EXIT(a_EventSubName) \
9496 do { \
9497 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9498 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9499 } while (0)
9500#define SET_BOTH(a_EventSubName) \
9501 do { \
9502 enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \
9503 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9504 fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \
9505 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9506 } while (0)
9507 switch (uExitReason)
9508 {
9509 case VMX_EXIT_MTF:
9510 return hmR0VmxExitMtf(pVCpu, pVmxTransient);
9511
9512 case VMX_EXIT_XCPT_OR_NMI:
9513 {
9514 uint8_t const idxVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
9515 switch (VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo))
9516 {
9517 case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
9518 case VMX_EXIT_INT_INFO_TYPE_SW_XCPT:
9519 case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT:
9520 if (idxVector <= (unsigned)(DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST))
9521 {
9522 if (VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uExitIntInfo))
9523 {
9524 hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
9525 uEventArg = pVmxTransient->uExitIntErrorCode;
9526 }
9527 enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);
9528 switch (enmEvent1)
9529 {
9530 case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break;
9531 case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break;
9532 case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break;
9533 case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break;
9534 case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break;
9535 case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break;
9536 case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break;
9537 case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break;
9538 case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break;
9539 case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break;
9540 case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break;
9541 case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break;
9542 case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break;
9543 case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break;
9544 case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break;
9545 case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break;
9546 case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break;
9547 case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break;
9548 default: break;
9549 }
9550 }
9551 else
9552 AssertFailed();
9553 break;
9554
9555 case VMX_EXIT_INT_INFO_TYPE_SW_INT:
9556 uEventArg = idxVector;
9557 enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE;
9558 fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED();
9559 break;
9560 }
9561 break;
9562 }
9563
9564 case VMX_EXIT_TRIPLE_FAULT:
9565 enmEvent1 = DBGFEVENT_TRIPLE_FAULT;
9566 //fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();
9567 break;
9568 case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break;
9569 case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break;
9570 case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break;
9571 case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break;
9572 case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break;
9573
9574 /* Instruction specific VM-exits: */
9575 case VMX_EXIT_CPUID: SET_BOTH(CPUID); break;
9576 case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break;
9577 case VMX_EXIT_HLT: SET_BOTH(HALT); break;
9578 case VMX_EXIT_INVD: SET_BOTH(INVD); break;
9579 case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break;
9580 case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break;
9581 case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break;
9582 case VMX_EXIT_RSM: SET_BOTH(RSM); break;
9583 case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break;
9584 case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break;
9585 case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break;
9586 case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break;
9587 case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break;
9588 case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break;
9589 case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break;
9590 case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break;
9591 case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break;
9592 case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break;
9593 case VMX_EXIT_MOV_CRX:
9594 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9595 if (VMX_EXIT_QUAL_CRX_ACCESS(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_CRX_ACCESS_READ)
9596 SET_BOTH(CRX_READ);
9597 else
9598 SET_BOTH(CRX_WRITE);
9599 uEventArg = VMX_EXIT_QUAL_CRX_REGISTER(pVmxTransient->uExitQual);
9600 break;
9601 case VMX_EXIT_MOV_DRX:
9602 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9603 if ( VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual)
9604 == VMX_EXIT_QUAL_DRX_DIRECTION_READ)
9605 SET_BOTH(DRX_READ);
9606 else
9607 SET_BOTH(DRX_WRITE);
9608 uEventArg = VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual);
9609 break;
9610 case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break;
9611 case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break;
9612 case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break;
9613 case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break;
9614 case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break;
9615 case VMX_EXIT_GDTR_IDTR_ACCESS:
9616 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9617 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_XDTR_INSINFO_INSTR_ID))
9618 {
9619 case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break;
9620 case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break;
9621 case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break;
9622 case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break;
9623 }
9624 break;
9625
9626 case VMX_EXIT_LDTR_TR_ACCESS:
9627 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9628 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_YYTR_INSINFO_INSTR_ID))
9629 {
9630 case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break;
9631 case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break;
9632 case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break;
9633 case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break;
9634 }
9635 break;
9636
9637 case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break;
9638 case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break;
9639 case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break;
9640 case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break;
9641 case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break;
9642 case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break;
9643 case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break;
9644 case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break;
9645 case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break;
9646 case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break;
9647 case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break;
9648
9649 /* Events that aren't relevant at this point. */
9650 case VMX_EXIT_EXT_INT:
9651 case VMX_EXIT_INT_WINDOW:
9652 case VMX_EXIT_NMI_WINDOW:
9653 case VMX_EXIT_TPR_BELOW_THRESHOLD:
9654 case VMX_EXIT_PREEMPT_TIMER:
9655 case VMX_EXIT_IO_INSTR:
9656 break;
9657
9658 /* Errors and unexpected events. */
9659 case VMX_EXIT_INIT_SIGNAL:
9660 case VMX_EXIT_SIPI:
9661 case VMX_EXIT_IO_SMI:
9662 case VMX_EXIT_SMI:
9663 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9664 case VMX_EXIT_ERR_MSR_LOAD:
9665 case VMX_EXIT_ERR_MACHINE_CHECK:
9666 break;
9667
9668 default:
9669 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9670 break;
9671 }
9672#undef SET_BOTH
9673#undef SET_EXIT
9674
9675 /*
9676 * Dtrace tracepoints go first. We do them here at once so we don't
9677 * have to copy the guest state saving and stuff a few dozen times.
9678 * Down side is that we've got to repeat the switch, though this time
9679 * we use enmEvent since the probes are a subset of what DBGF does.
9680 */
9681 if (fDtrace1 || fDtrace2)
9682 {
9683 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9684 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
9685 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
9686 switch (enmEvent1)
9687 {
9688 /** @todo consider which extra parameters would be helpful for each probe. */
9689 case DBGFEVENT_END: break;
9690 case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pCtx); break;
9691 case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pCtx, pCtx->dr[6]); break;
9692 case DBGFEVENT_XCPT_BP: VBOXVMM_XCPT_BP(pVCpu, pCtx); break;
9693 case DBGFEVENT_XCPT_OF: VBOXVMM_XCPT_OF(pVCpu, pCtx); break;
9694 case DBGFEVENT_XCPT_BR: VBOXVMM_XCPT_BR(pVCpu, pCtx); break;
9695 case DBGFEVENT_XCPT_UD: VBOXVMM_XCPT_UD(pVCpu, pCtx); break;
9696 case DBGFEVENT_XCPT_NM: VBOXVMM_XCPT_NM(pVCpu, pCtx); break;
9697 case DBGFEVENT_XCPT_DF: VBOXVMM_XCPT_DF(pVCpu, pCtx); break;
9698 case DBGFEVENT_XCPT_TS: VBOXVMM_XCPT_TS(pVCpu, pCtx, uEventArg); break;
9699 case DBGFEVENT_XCPT_NP: VBOXVMM_XCPT_NP(pVCpu, pCtx, uEventArg); break;
9700 case DBGFEVENT_XCPT_SS: VBOXVMM_XCPT_SS(pVCpu, pCtx, uEventArg); break;
9701 case DBGFEVENT_XCPT_GP: VBOXVMM_XCPT_GP(pVCpu, pCtx, uEventArg); break;
9702 case DBGFEVENT_XCPT_PF: VBOXVMM_XCPT_PF(pVCpu, pCtx, uEventArg, pCtx->cr2); break;
9703 case DBGFEVENT_XCPT_MF: VBOXVMM_XCPT_MF(pVCpu, pCtx); break;
9704 case DBGFEVENT_XCPT_AC: VBOXVMM_XCPT_AC(pVCpu, pCtx); break;
9705 case DBGFEVENT_XCPT_XF: VBOXVMM_XCPT_XF(pVCpu, pCtx); break;
9706 case DBGFEVENT_XCPT_VE: VBOXVMM_XCPT_VE(pVCpu, pCtx); break;
9707 case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pCtx, uEventArg); break;
9708 case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9709 case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
9710 case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pCtx); break;
9711 case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pCtx); break;
9712 case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pCtx); break;
9713 case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pCtx); break;
9714 case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pCtx); break;
9715 case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pCtx); break;
9716 case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pCtx); break;
9717 case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9718 case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9719 case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9720 case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9721 case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
9722 case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pCtx, pCtx->ecx,
9723 RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
9724 case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pCtx); break;
9725 case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pCtx); break;
9726 case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pCtx); break;
9727 case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pCtx); break;
9728 case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pCtx); break;
9729 case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pCtx); break;
9730 case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pCtx); break;
9731 case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pCtx); break;
9732 case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pCtx); break;
9733 case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pCtx); break;
9734 case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pCtx); break;
9735 case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pCtx); break;
9736 case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pCtx); break;
9737 case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pCtx); break;
9738 case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pCtx); break;
9739 case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pCtx); break;
9740 case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pCtx); break;
9741 case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pCtx); break;
9742 case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pCtx); break;
9743 case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pCtx); break;
9744 case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pCtx); break;
9745 case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pCtx); break;
9746 case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pCtx); break;
9747 case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pCtx); break;
9748 case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pCtx); break;
9749 case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pCtx); break;
9750 case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pCtx); break;
9751 case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pCtx); break;
9752 case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pCtx); break;
9753 case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pCtx); break;
9754 case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pCtx); break;
9755 case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pCtx); break;
9756 default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break;
9757 }
9758 switch (enmEvent2)
9759 {
9760 /** @todo consider which extra parameters would be helpful for each probe. */
9761 case DBGFEVENT_END: break;
9762 case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pCtx); break;
9763 case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
9764 case DBGFEVENT_EXIT_GETSEC: VBOXVMM_EXIT_GETSEC(pVCpu, pCtx); break;
9765 case DBGFEVENT_EXIT_HALT: VBOXVMM_EXIT_HALT(pVCpu, pCtx); break;
9766 case DBGFEVENT_EXIT_INVD: VBOXVMM_EXIT_INVD(pVCpu, pCtx); break;
9767 case DBGFEVENT_EXIT_INVLPG: VBOXVMM_EXIT_INVLPG(pVCpu, pCtx); break;
9768 case DBGFEVENT_EXIT_RDPMC: VBOXVMM_EXIT_RDPMC(pVCpu, pCtx); break;
9769 case DBGFEVENT_EXIT_RDTSC: VBOXVMM_EXIT_RDTSC(pVCpu, pCtx); break;
9770 case DBGFEVENT_EXIT_RSM: VBOXVMM_EXIT_RSM(pVCpu, pCtx); break;
9771 case DBGFEVENT_EXIT_CRX_READ: VBOXVMM_EXIT_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9772 case DBGFEVENT_EXIT_CRX_WRITE: VBOXVMM_EXIT_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9773 case DBGFEVENT_EXIT_DRX_READ: VBOXVMM_EXIT_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9774 case DBGFEVENT_EXIT_DRX_WRITE: VBOXVMM_EXIT_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9775 case DBGFEVENT_EXIT_RDMSR: VBOXVMM_EXIT_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
9776 case DBGFEVENT_EXIT_WRMSR: VBOXVMM_EXIT_WRMSR(pVCpu, pCtx, pCtx->ecx,
9777 RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
9778 case DBGFEVENT_EXIT_MWAIT: VBOXVMM_EXIT_MWAIT(pVCpu, pCtx); break;
9779 case DBGFEVENT_EXIT_MONITOR: VBOXVMM_EXIT_MONITOR(pVCpu, pCtx); break;
9780 case DBGFEVENT_EXIT_PAUSE: VBOXVMM_EXIT_PAUSE(pVCpu, pCtx); break;
9781 case DBGFEVENT_EXIT_SGDT: VBOXVMM_EXIT_SGDT(pVCpu, pCtx); break;
9782 case DBGFEVENT_EXIT_SIDT: VBOXVMM_EXIT_SIDT(pVCpu, pCtx); break;
9783 case DBGFEVENT_EXIT_LGDT: VBOXVMM_EXIT_LGDT(pVCpu, pCtx); break;
9784 case DBGFEVENT_EXIT_LIDT: VBOXVMM_EXIT_LIDT(pVCpu, pCtx); break;
9785 case DBGFEVENT_EXIT_SLDT: VBOXVMM_EXIT_SLDT(pVCpu, pCtx); break;
9786 case DBGFEVENT_EXIT_STR: VBOXVMM_EXIT_STR(pVCpu, pCtx); break;
9787 case DBGFEVENT_EXIT_LLDT: VBOXVMM_EXIT_LLDT(pVCpu, pCtx); break;
9788 case DBGFEVENT_EXIT_LTR: VBOXVMM_EXIT_LTR(pVCpu, pCtx); break;
9789 case DBGFEVENT_EXIT_RDTSCP: VBOXVMM_EXIT_RDTSCP(pVCpu, pCtx); break;
9790 case DBGFEVENT_EXIT_WBINVD: VBOXVMM_EXIT_WBINVD(pVCpu, pCtx); break;
9791 case DBGFEVENT_EXIT_XSETBV: VBOXVMM_EXIT_XSETBV(pVCpu, pCtx); break;
9792 case DBGFEVENT_EXIT_RDRAND: VBOXVMM_EXIT_RDRAND(pVCpu, pCtx); break;
9793 case DBGFEVENT_EXIT_RDSEED: VBOXVMM_EXIT_RDSEED(pVCpu, pCtx); break;
9794 case DBGFEVENT_EXIT_XSAVES: VBOXVMM_EXIT_XSAVES(pVCpu, pCtx); break;
9795 case DBGFEVENT_EXIT_XRSTORS: VBOXVMM_EXIT_XRSTORS(pVCpu, pCtx); break;
9796 case DBGFEVENT_EXIT_VMM_CALL: VBOXVMM_EXIT_VMM_CALL(pVCpu, pCtx); break;
9797 case DBGFEVENT_EXIT_VMX_VMCLEAR: VBOXVMM_EXIT_VMX_VMCLEAR(pVCpu, pCtx); break;
9798 case DBGFEVENT_EXIT_VMX_VMLAUNCH: VBOXVMM_EXIT_VMX_VMLAUNCH(pVCpu, pCtx); break;
9799 case DBGFEVENT_EXIT_VMX_VMPTRLD: VBOXVMM_EXIT_VMX_VMPTRLD(pVCpu, pCtx); break;
9800 case DBGFEVENT_EXIT_VMX_VMPTRST: VBOXVMM_EXIT_VMX_VMPTRST(pVCpu, pCtx); break;
9801 case DBGFEVENT_EXIT_VMX_VMREAD: VBOXVMM_EXIT_VMX_VMREAD(pVCpu, pCtx); break;
9802 case DBGFEVENT_EXIT_VMX_VMRESUME: VBOXVMM_EXIT_VMX_VMRESUME(pVCpu, pCtx); break;
9803 case DBGFEVENT_EXIT_VMX_VMWRITE: VBOXVMM_EXIT_VMX_VMWRITE(pVCpu, pCtx); break;
9804 case DBGFEVENT_EXIT_VMX_VMXOFF: VBOXVMM_EXIT_VMX_VMXOFF(pVCpu, pCtx); break;
9805 case DBGFEVENT_EXIT_VMX_VMXON: VBOXVMM_EXIT_VMX_VMXON(pVCpu, pCtx); break;
9806 case DBGFEVENT_EXIT_VMX_INVEPT: VBOXVMM_EXIT_VMX_INVEPT(pVCpu, pCtx); break;
9807 case DBGFEVENT_EXIT_VMX_INVVPID: VBOXVMM_EXIT_VMX_INVVPID(pVCpu, pCtx); break;
9808 case DBGFEVENT_EXIT_VMX_INVPCID: VBOXVMM_EXIT_VMX_INVPCID(pVCpu, pCtx); break;
9809 case DBGFEVENT_EXIT_VMX_VMFUNC: VBOXVMM_EXIT_VMX_VMFUNC(pVCpu, pCtx); break;
9810 case DBGFEVENT_EXIT_VMX_EPT_MISCONFIG: VBOXVMM_EXIT_VMX_EPT_MISCONFIG(pVCpu, pCtx); break;
9811 case DBGFEVENT_EXIT_VMX_EPT_VIOLATION: VBOXVMM_EXIT_VMX_EPT_VIOLATION(pVCpu, pCtx); break;
9812 case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pCtx); break;
9813 case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pCtx); break;
9814 default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break;
9815 }
9816 }
9817
9818 /*
9819 * Fire of the DBGF event, if enabled (our check here is just a quick one,
9820 * the DBGF call will do a full check).
9821 *
9822 * Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap.
9823 * Note! If we have to events, we prioritize the first, i.e. the instruction
9824 * one, in order to avoid event nesting.
9825 */
9826 PVM pVM = pVCpu->CTX_SUFF(pVM);
9827 if ( enmEvent1 != DBGFEVENT_END
9828 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
9829 {
9830 HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
9831 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent1, DBGFEVENTCTX_HM, 1, uEventArg);
9832 if (rcStrict != VINF_SUCCESS)
9833 return rcStrict;
9834 }
9835 else if ( enmEvent2 != DBGFEVENT_END
9836 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent2))
9837 {
9838 HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
9839 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent2, DBGFEVENTCTX_HM, 1, uEventArg);
9840 if (rcStrict != VINF_SUCCESS)
9841 return rcStrict;
9842 }
9843
9844 return VINF_SUCCESS;
9845}
9846
9847
9848/**
9849 * Single-stepping VM-exit filtering.
9850 *
9851 * This is preprocessing the VM-exits and deciding whether we've gotten far
9852 * enough to return VINF_EM_DBG_STEPPED already. If not, normal VM-exit
9853 * handling is performed.
9854 *
9855 * @returns Strict VBox status code (i.e. informational status codes too).
9856 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9857 * @param pVmxTransient Pointer to the VMX-transient structure.
9858 * @param pDbgState The debug state.
9859 */
9860DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState)
9861{
9862 /*
9863 * Expensive (saves context) generic dtrace VM-exit probe.
9864 */
9865 uint32_t const uExitReason = pVmxTransient->uExitReason;
9866 if (!VBOXVMM_R0_HMVMX_VMEXIT_ENABLED())
9867 { /* more likely */ }
9868 else
9869 {
9870 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9871 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
9872 AssertRC(rc);
9873 VBOXVMM_R0_HMVMX_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, pVmxTransient->uExitReason, pVmxTransient->uExitQual);
9874 }
9875
9876 /*
9877 * Check for host NMI, just to get that out of the way.
9878 */
9879 if (uExitReason != VMX_EXIT_XCPT_OR_NMI)
9880 { /* normally likely */ }
9881 else
9882 {
9883 int rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
9884 AssertRCReturn(rc2, rc2);
9885 uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
9886 if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
9887 return hmR0VmxExitXcptOrNmi(pVCpu, pVmxTransient);
9888 }
9889
9890 /*
9891 * Check for single stepping event if we're stepping.
9892 */
9893 if (pVCpu->hm.s.fSingleInstruction)
9894 {
9895 switch (uExitReason)
9896 {
9897 case VMX_EXIT_MTF:
9898 return hmR0VmxExitMtf(pVCpu, pVmxTransient);
9899
9900 /* Various events: */
9901 case VMX_EXIT_XCPT_OR_NMI:
9902 case VMX_EXIT_EXT_INT:
9903 case VMX_EXIT_TRIPLE_FAULT:
9904 case VMX_EXIT_INT_WINDOW:
9905 case VMX_EXIT_NMI_WINDOW:
9906 case VMX_EXIT_TASK_SWITCH:
9907 case VMX_EXIT_TPR_BELOW_THRESHOLD:
9908 case VMX_EXIT_APIC_ACCESS:
9909 case VMX_EXIT_EPT_VIOLATION:
9910 case VMX_EXIT_EPT_MISCONFIG:
9911 case VMX_EXIT_PREEMPT_TIMER:
9912
9913 /* Instruction specific VM-exits: */
9914 case VMX_EXIT_CPUID:
9915 case VMX_EXIT_GETSEC:
9916 case VMX_EXIT_HLT:
9917 case VMX_EXIT_INVD:
9918 case VMX_EXIT_INVLPG:
9919 case VMX_EXIT_RDPMC:
9920 case VMX_EXIT_RDTSC:
9921 case VMX_EXIT_RSM:
9922 case VMX_EXIT_VMCALL:
9923 case VMX_EXIT_VMCLEAR:
9924 case VMX_EXIT_VMLAUNCH:
9925 case VMX_EXIT_VMPTRLD:
9926 case VMX_EXIT_VMPTRST:
9927 case VMX_EXIT_VMREAD:
9928 case VMX_EXIT_VMRESUME:
9929 case VMX_EXIT_VMWRITE:
9930 case VMX_EXIT_VMXOFF:
9931 case VMX_EXIT_VMXON:
9932 case VMX_EXIT_MOV_CRX:
9933 case VMX_EXIT_MOV_DRX:
9934 case VMX_EXIT_IO_INSTR:
9935 case VMX_EXIT_RDMSR:
9936 case VMX_EXIT_WRMSR:
9937 case VMX_EXIT_MWAIT:
9938 case VMX_EXIT_MONITOR:
9939 case VMX_EXIT_PAUSE:
9940 case VMX_EXIT_GDTR_IDTR_ACCESS:
9941 case VMX_EXIT_LDTR_TR_ACCESS:
9942 case VMX_EXIT_INVEPT:
9943 case VMX_EXIT_RDTSCP:
9944 case VMX_EXIT_INVVPID:
9945 case VMX_EXIT_WBINVD:
9946 case VMX_EXIT_XSETBV:
9947 case VMX_EXIT_RDRAND:
9948 case VMX_EXIT_INVPCID:
9949 case VMX_EXIT_VMFUNC:
9950 case VMX_EXIT_RDSEED:
9951 case VMX_EXIT_XSAVES:
9952 case VMX_EXIT_XRSTORS:
9953 {
9954 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
9955 AssertRCReturn(rc, rc);
9956 if ( pVCpu->cpum.GstCtx.rip != pDbgState->uRipStart
9957 || pVCpu->cpum.GstCtx.cs.Sel != pDbgState->uCsStart)
9958 return VINF_EM_DBG_STEPPED;
9959 break;
9960 }
9961
9962 /* Errors and unexpected events: */
9963 case VMX_EXIT_INIT_SIGNAL:
9964 case VMX_EXIT_SIPI:
9965 case VMX_EXIT_IO_SMI:
9966 case VMX_EXIT_SMI:
9967 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9968 case VMX_EXIT_ERR_MSR_LOAD:
9969 case VMX_EXIT_ERR_MACHINE_CHECK:
9970 case VMX_EXIT_APIC_WRITE: /* Some talk about this being fault like, so I guess we must process it? */
9971 break;
9972
9973 default:
9974 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9975 break;
9976 }
9977 }
9978
9979 /*
9980 * Check for debugger event breakpoints and dtrace probes.
9981 */
9982 if ( uExitReason < RT_ELEMENTS(pDbgState->bmExitsToCheck) * 32U
9983 && ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
9984 {
9985 VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVCpu, pVmxTransient, uExitReason);
9986 if (rcStrict != VINF_SUCCESS)
9987 return rcStrict;
9988 }
9989
9990 /*
9991 * Normal processing.
9992 */
9993#ifdef HMVMX_USE_FUNCTION_TABLE
9994 return g_apfnVMExitHandlers[uExitReason](pVCpu, pVmxTransient);
9995#else
9996 return hmR0VmxHandleExit(pVCpu, pVmxTransient, uExitReason);
9997#endif
9998}
9999
10000
10001/**
10002 * Single steps guest code using VT-x.
10003 *
10004 * @returns Strict VBox status code (i.e. informational status codes too).
10005 * @param pVCpu The cross context virtual CPU structure.
10006 *
10007 * @note Mostly the same as hmR0VmxRunGuestCodeNormal().
10008 */
10009static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVMCPU pVCpu)
10010{
10011 VMXTRANSIENT VmxTransient;
10012 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
10013
10014 /* Set HMCPU indicators. */
10015 bool const fSavedSingleInstruction = pVCpu->hm.s.fSingleInstruction;
10016 pVCpu->hm.s.fSingleInstruction = pVCpu->hm.s.fSingleInstruction || DBGFIsStepping(pVCpu);
10017 pVCpu->hm.s.fDebugWantRdTscExit = false;
10018 pVCpu->hm.s.fUsingDebugLoop = true;
10019
10020 /* State we keep to help modify and later restore the VMCS fields we alter, and for detecting steps. */
10021 VMXRUNDBGSTATE DbgState;
10022 hmR0VmxRunDebugStateInit(pVCpu, &DbgState);
10023 hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &DbgState, &VmxTransient);
10024
10025 /*
10026 * The loop.
10027 */
10028 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
10029 for (uint32_t cLoops = 0; ; cLoops++)
10030 {
10031 Assert(!HMR0SuspendPending());
10032 HMVMX_ASSERT_CPU_SAFE(pVCpu);
10033 bool fStepping = pVCpu->hm.s.fSingleInstruction;
10034
10035 /*
10036 * Preparatory work for running guest code, this may force us to return
10037 * to ring-3. This bugger disables interrupts on VINF_SUCCESS!
10038 */
10039 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
10040 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Set up execute controls the next to can respond to. */
10041 rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, fStepping);
10042 if (rcStrict != VINF_SUCCESS)
10043 break;
10044
10045 hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
10046 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Override any obnoxious code in the above two calls. */
10047
10048 /*
10049 * Now we can run the guest code.
10050 */
10051 int rcRun = hmR0VmxRunGuest(pVCpu);
10052
10053 /*
10054 * Restore any residual host-state and save any bits shared between host
10055 * and guest into the guest-CPU state. Re-enables interrupts!
10056 */
10057 hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
10058
10059 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
10060 if (RT_SUCCESS(rcRun))
10061 { /* very likely */ }
10062 else
10063 {
10064 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
10065 hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
10066 return rcRun;
10067 }
10068
10069 /* Profile the VM-exit. */
10070 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
10071 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
10072 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
10073 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
10074 HMVMX_START_EXIT_DISPATCH_PROF();
10075
10076 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
10077
10078 /*
10079 * Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
10080 */
10081 rcStrict = hmR0VmxRunDebugHandleExit(pVCpu, &VmxTransient, &DbgState);
10082 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
10083 if (rcStrict != VINF_SUCCESS)
10084 break;
10085 if (cLoops > pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
10086 {
10087 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
10088 rcStrict = VINF_EM_RAW_INTERRUPT;
10089 break;
10090 }
10091
10092 /*
10093 * Stepping: Did the RIP change, if so, consider it a single step.
10094 * Otherwise, make sure one of the TFs gets set.
10095 */
10096 if (fStepping)
10097 {
10098 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
10099 AssertRC(rc);
10100 if ( pVCpu->cpum.GstCtx.rip != DbgState.uRipStart
10101 || pVCpu->cpum.GstCtx.cs.Sel != DbgState.uCsStart)
10102 {
10103 rcStrict = VINF_EM_DBG_STEPPED;
10104 break;
10105 }
10106 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
10107 }
10108
10109 /*
10110 * Update when dtrace settings changes (DBGF kicks us, so no need to check).
10111 */
10112 if (VBOXVMM_GET_SETTINGS_SEQ_NO() != DbgState.uDtraceSettingsSeqNo)
10113 hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &DbgState, &VmxTransient);
10114 }
10115
10116 /*
10117 * Clear the X86_EFL_TF if necessary.
10118 */
10119 if (pVCpu->hm.s.fClearTrapFlag)
10120 {
10121 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
10122 AssertRC(rc);
10123 pVCpu->hm.s.fClearTrapFlag = false;
10124 pVCpu->cpum.GstCtx.eflags.Bits.u1TF = 0;
10125 }
10126 /** @todo there seems to be issues with the resume flag when the monitor trap
10127 * flag is pending without being used. Seen early in bios init when
10128 * accessing APIC page in protected mode. */
10129
10130 /*
10131 * Restore VM-exit control settings as we may not reenter this function the
10132 * next time around.
10133 */
10134 rcStrict = hmR0VmxRunDebugStateRevert(pVCpu, &DbgState, rcStrict);
10135
10136 /* Restore HMCPU indicators. */
10137 pVCpu->hm.s.fUsingDebugLoop = false;
10138 pVCpu->hm.s.fDebugWantRdTscExit = false;
10139 pVCpu->hm.s.fSingleInstruction = fSavedSingleInstruction;
10140
10141 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
10142 return rcStrict;
10143}
10144
10145
10146/** @} */
10147
10148
10149/**
10150 * Checks if any expensive dtrace probes are enabled and we should go to the
10151 * debug loop.
10152 *
10153 * @returns true if we should use debug loop, false if not.
10154 */
10155static bool hmR0VmxAnyExpensiveProbesEnabled(void)
10156{
10157 /* It's probably faster to OR the raw 32-bit counter variables together.
10158 Since the variables are in an array and the probes are next to one
10159 another (more or less), we have good locality. So, better read
10160 eight-nine cache lines ever time and only have one conditional, than
10161 128+ conditionals, right? */
10162 return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */
10163 | VBOXVMM_XCPT_DE_ENABLED_RAW()
10164 | VBOXVMM_XCPT_DB_ENABLED_RAW()
10165 | VBOXVMM_XCPT_BP_ENABLED_RAW()
10166 | VBOXVMM_XCPT_OF_ENABLED_RAW()
10167 | VBOXVMM_XCPT_BR_ENABLED_RAW()
10168 | VBOXVMM_XCPT_UD_ENABLED_RAW()
10169 | VBOXVMM_XCPT_NM_ENABLED_RAW()
10170 | VBOXVMM_XCPT_DF_ENABLED_RAW()
10171 | VBOXVMM_XCPT_TS_ENABLED_RAW()
10172 | VBOXVMM_XCPT_NP_ENABLED_RAW()
10173 | VBOXVMM_XCPT_SS_ENABLED_RAW()
10174 | VBOXVMM_XCPT_GP_ENABLED_RAW()
10175 | VBOXVMM_XCPT_PF_ENABLED_RAW()
10176 | VBOXVMM_XCPT_MF_ENABLED_RAW()
10177 | VBOXVMM_XCPT_AC_ENABLED_RAW()
10178 | VBOXVMM_XCPT_XF_ENABLED_RAW()
10179 | VBOXVMM_XCPT_VE_ENABLED_RAW()
10180 | VBOXVMM_XCPT_SX_ENABLED_RAW()
10181 | VBOXVMM_INT_SOFTWARE_ENABLED_RAW()
10182 | VBOXVMM_INT_HARDWARE_ENABLED_RAW()
10183 ) != 0
10184 || ( VBOXVMM_INSTR_HALT_ENABLED_RAW()
10185 | VBOXVMM_INSTR_MWAIT_ENABLED_RAW()
10186 | VBOXVMM_INSTR_MONITOR_ENABLED_RAW()
10187 | VBOXVMM_INSTR_CPUID_ENABLED_RAW()
10188 | VBOXVMM_INSTR_INVD_ENABLED_RAW()
10189 | VBOXVMM_INSTR_WBINVD_ENABLED_RAW()
10190 | VBOXVMM_INSTR_INVLPG_ENABLED_RAW()
10191 | VBOXVMM_INSTR_RDTSC_ENABLED_RAW()
10192 | VBOXVMM_INSTR_RDTSCP_ENABLED_RAW()
10193 | VBOXVMM_INSTR_RDPMC_ENABLED_RAW()
10194 | VBOXVMM_INSTR_RDMSR_ENABLED_RAW()
10195 | VBOXVMM_INSTR_WRMSR_ENABLED_RAW()
10196 | VBOXVMM_INSTR_CRX_READ_ENABLED_RAW()
10197 | VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW()
10198 | VBOXVMM_INSTR_DRX_READ_ENABLED_RAW()
10199 | VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW()
10200 | VBOXVMM_INSTR_PAUSE_ENABLED_RAW()
10201 | VBOXVMM_INSTR_XSETBV_ENABLED_RAW()
10202 | VBOXVMM_INSTR_SIDT_ENABLED_RAW()
10203 | VBOXVMM_INSTR_LIDT_ENABLED_RAW()
10204 | VBOXVMM_INSTR_SGDT_ENABLED_RAW()
10205 | VBOXVMM_INSTR_LGDT_ENABLED_RAW()
10206 | VBOXVMM_INSTR_SLDT_ENABLED_RAW()
10207 | VBOXVMM_INSTR_LLDT_ENABLED_RAW()
10208 | VBOXVMM_INSTR_STR_ENABLED_RAW()
10209 | VBOXVMM_INSTR_LTR_ENABLED_RAW()
10210 | VBOXVMM_INSTR_GETSEC_ENABLED_RAW()
10211 | VBOXVMM_INSTR_RSM_ENABLED_RAW()
10212 | VBOXVMM_INSTR_RDRAND_ENABLED_RAW()
10213 | VBOXVMM_INSTR_RDSEED_ENABLED_RAW()
10214 | VBOXVMM_INSTR_XSAVES_ENABLED_RAW()
10215 | VBOXVMM_INSTR_XRSTORS_ENABLED_RAW()
10216 | VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW()
10217 | VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW()
10218 | VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW()
10219 | VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW()
10220 | VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW()
10221 | VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW()
10222 | VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW()
10223 | VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW()
10224 | VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW()
10225 | VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW()
10226 | VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW()
10227 | VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW()
10228 | VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW()
10229 | VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW()
10230 ) != 0
10231 || ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW()
10232 | VBOXVMM_EXIT_HALT_ENABLED_RAW()
10233 | VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
10234 | VBOXVMM_EXIT_MONITOR_ENABLED_RAW()
10235 | VBOXVMM_EXIT_CPUID_ENABLED_RAW()
10236 | VBOXVMM_EXIT_INVD_ENABLED_RAW()
10237 | VBOXVMM_EXIT_WBINVD_ENABLED_RAW()
10238 | VBOXVMM_EXIT_INVLPG_ENABLED_RAW()
10239 | VBOXVMM_EXIT_RDTSC_ENABLED_RAW()
10240 | VBOXVMM_EXIT_RDTSCP_ENABLED_RAW()
10241 | VBOXVMM_EXIT_RDPMC_ENABLED_RAW()
10242 | VBOXVMM_EXIT_RDMSR_ENABLED_RAW()
10243 | VBOXVMM_EXIT_WRMSR_ENABLED_RAW()
10244 | VBOXVMM_EXIT_CRX_READ_ENABLED_RAW()
10245 | VBOXVMM_EXIT_CRX_WRITE_ENABLED_RAW()
10246 | VBOXVMM_EXIT_DRX_READ_ENABLED_RAW()
10247 | VBOXVMM_EXIT_DRX_WRITE_ENABLED_RAW()
10248 | VBOXVMM_EXIT_PAUSE_ENABLED_RAW()
10249 | VBOXVMM_EXIT_XSETBV_ENABLED_RAW()
10250 | VBOXVMM_EXIT_SIDT_ENABLED_RAW()
10251 | VBOXVMM_EXIT_LIDT_ENABLED_RAW()
10252 | VBOXVMM_EXIT_SGDT_ENABLED_RAW()
10253 | VBOXVMM_EXIT_LGDT_ENABLED_RAW()
10254 | VBOXVMM_EXIT_SLDT_ENABLED_RAW()
10255 | VBOXVMM_EXIT_LLDT_ENABLED_RAW()
10256 | VBOXVMM_EXIT_STR_ENABLED_RAW()
10257 | VBOXVMM_EXIT_LTR_ENABLED_RAW()
10258 | VBOXVMM_EXIT_GETSEC_ENABLED_RAW()
10259 | VBOXVMM_EXIT_RSM_ENABLED_RAW()
10260 | VBOXVMM_EXIT_RDRAND_ENABLED_RAW()
10261 | VBOXVMM_EXIT_RDSEED_ENABLED_RAW()
10262 | VBOXVMM_EXIT_XSAVES_ENABLED_RAW()
10263 | VBOXVMM_EXIT_XRSTORS_ENABLED_RAW()
10264 | VBOXVMM_EXIT_VMM_CALL_ENABLED_RAW()
10265 | VBOXVMM_EXIT_VMX_VMCLEAR_ENABLED_RAW()
10266 | VBOXVMM_EXIT_VMX_VMLAUNCH_ENABLED_RAW()
10267 | VBOXVMM_EXIT_VMX_VMPTRLD_ENABLED_RAW()
10268 | VBOXVMM_EXIT_VMX_VMPTRST_ENABLED_RAW()
10269 | VBOXVMM_EXIT_VMX_VMREAD_ENABLED_RAW()
10270 | VBOXVMM_EXIT_VMX_VMRESUME_ENABLED_RAW()
10271 | VBOXVMM_EXIT_VMX_VMWRITE_ENABLED_RAW()
10272 | VBOXVMM_EXIT_VMX_VMXOFF_ENABLED_RAW()
10273 | VBOXVMM_EXIT_VMX_VMXON_ENABLED_RAW()
10274 | VBOXVMM_EXIT_VMX_VMFUNC_ENABLED_RAW()
10275 | VBOXVMM_EXIT_VMX_INVEPT_ENABLED_RAW()
10276 | VBOXVMM_EXIT_VMX_INVVPID_ENABLED_RAW()
10277 | VBOXVMM_EXIT_VMX_INVPCID_ENABLED_RAW()
10278 | VBOXVMM_EXIT_VMX_EPT_VIOLATION_ENABLED_RAW()
10279 | VBOXVMM_EXIT_VMX_EPT_MISCONFIG_ENABLED_RAW()
10280 | VBOXVMM_EXIT_VMX_VAPIC_ACCESS_ENABLED_RAW()
10281 | VBOXVMM_EXIT_VMX_VAPIC_WRITE_ENABLED_RAW()
10282 ) != 0;
10283}
10284
10285
10286/**
10287 * Runs the guest code using VT-x.
10288 *
10289 * @returns Strict VBox status code (i.e. informational status codes too).
10290 * @param pVCpu The cross context virtual CPU structure.
10291 */
10292VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPU pVCpu)
10293{
10294 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
10295 Assert(VMMRZCallRing3IsEnabled(pVCpu));
10296 Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
10297 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
10298
10299 VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
10300
10301 VBOXSTRICTRC rcStrict;
10302 if ( !pVCpu->hm.s.fUseDebugLoop
10303 && (!VBOXVMM_ANY_PROBES_ENABLED() || !hmR0VmxAnyExpensiveProbesEnabled())
10304 && !DBGFIsStepping(pVCpu)
10305 && !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
10306 rcStrict = hmR0VmxRunGuestCodeNormal(pVCpu);
10307 else
10308 rcStrict = hmR0VmxRunGuestCodeDebug(pVCpu);
10309
10310 if (rcStrict == VERR_EM_INTERPRETER)
10311 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
10312 else if (rcStrict == VINF_EM_RESET)
10313 rcStrict = VINF_EM_TRIPLE_FAULT;
10314
10315 int rc2 = hmR0VmxExitToRing3(pVCpu, rcStrict);
10316 if (RT_FAILURE(rc2))
10317 {
10318 pVCpu->hm.s.u32HMError = (uint32_t)VBOXSTRICTRC_VAL(rcStrict);
10319 rcStrict = rc2;
10320 }
10321 Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
10322 Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
10323 return rcStrict;
10324}
10325
10326
10327#ifndef HMVMX_USE_FUNCTION_TABLE
10328DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t rcReason)
10329{
10330#ifdef DEBUG_ramshankar
10331#define VMEXIT_CALL_RET(a_fSave, a_CallExpr) \
10332 do { \
10333 if (a_fSave != 0) \
10334 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL); \
10335 VBOXSTRICTRC rcStrict = a_CallExpr; \
10336 if (a_fSave != 0) \
10337 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
10338 return rcStrict; \
10339 } while (0)
10340#else
10341# define VMEXIT_CALL_RET(a_fSave, a_CallExpr) return a_CallExpr
10342#endif
10343 switch (rcReason)
10344 {
10345 case VMX_EXIT_EPT_MISCONFIG: VMEXIT_CALL_RET(0, hmR0VmxExitEptMisconfig(pVCpu, pVmxTransient));
10346 case VMX_EXIT_EPT_VIOLATION: VMEXIT_CALL_RET(0, hmR0VmxExitEptViolation(pVCpu, pVmxTransient));
10347 case VMX_EXIT_IO_INSTR: VMEXIT_CALL_RET(0, hmR0VmxExitIoInstr(pVCpu, pVmxTransient));
10348 case VMX_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0VmxExitCpuid(pVCpu, pVmxTransient));
10349 case VMX_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0VmxExitRdtsc(pVCpu, pVmxTransient));
10350 case VMX_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0VmxExitRdtscp(pVCpu, pVmxTransient));
10351 case VMX_EXIT_APIC_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitApicAccess(pVCpu, pVmxTransient));
10352 case VMX_EXIT_XCPT_OR_NMI: VMEXIT_CALL_RET(0, hmR0VmxExitXcptOrNmi(pVCpu, pVmxTransient));
10353 case VMX_EXIT_MOV_CRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovCRx(pVCpu, pVmxTransient));
10354 case VMX_EXIT_EXT_INT: VMEXIT_CALL_RET(0, hmR0VmxExitExtInt(pVCpu, pVmxTransient));
10355 case VMX_EXIT_INT_WINDOW: VMEXIT_CALL_RET(0, hmR0VmxExitIntWindow(pVCpu, pVmxTransient));
10356 case VMX_EXIT_TPR_BELOW_THRESHOLD: VMEXIT_CALL_RET(0, hmR0VmxExitTprBelowThreshold(pVCpu, pVmxTransient));
10357 case VMX_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0VmxExitMwait(pVCpu, pVmxTransient));
10358 case VMX_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0VmxExitMonitor(pVCpu, pVmxTransient));
10359 case VMX_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0VmxExitTaskSwitch(pVCpu, pVmxTransient));
10360 case VMX_EXIT_PREEMPT_TIMER: VMEXIT_CALL_RET(0, hmR0VmxExitPreemptTimer(pVCpu, pVmxTransient));
10361 case VMX_EXIT_RDMSR: VMEXIT_CALL_RET(0, hmR0VmxExitRdmsr(pVCpu, pVmxTransient));
10362 case VMX_EXIT_WRMSR: VMEXIT_CALL_RET(0, hmR0VmxExitWrmsr(pVCpu, pVmxTransient));
10363 case VMX_EXIT_VMCALL: VMEXIT_CALL_RET(0, hmR0VmxExitVmcall(pVCpu, pVmxTransient));
10364 case VMX_EXIT_MOV_DRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovDRx(pVCpu, pVmxTransient));
10365 case VMX_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0VmxExitHlt(pVCpu, pVmxTransient));
10366 case VMX_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0VmxExitInvd(pVCpu, pVmxTransient));
10367 case VMX_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0VmxExitInvlpg(pVCpu, pVmxTransient));
10368 case VMX_EXIT_RSM: VMEXIT_CALL_RET(0, hmR0VmxExitRsm(pVCpu, pVmxTransient));
10369 case VMX_EXIT_MTF: VMEXIT_CALL_RET(0, hmR0VmxExitMtf(pVCpu, pVmxTransient));
10370 case VMX_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0VmxExitPause(pVCpu, pVmxTransient));
10371 case VMX_EXIT_GDTR_IDTR_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitXdtrAccess(pVCpu, pVmxTransient));
10372 case VMX_EXIT_LDTR_TR_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitXdtrAccess(pVCpu, pVmxTransient));
10373 case VMX_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0VmxExitWbinvd(pVCpu, pVmxTransient));
10374 case VMX_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0VmxExitXsetbv(pVCpu, pVmxTransient));
10375 case VMX_EXIT_RDRAND: VMEXIT_CALL_RET(0, hmR0VmxExitRdrand(pVCpu, pVmxTransient));
10376 case VMX_EXIT_INVPCID: VMEXIT_CALL_RET(0, hmR0VmxExitInvpcid(pVCpu, pVmxTransient));
10377 case VMX_EXIT_GETSEC: VMEXIT_CALL_RET(0, hmR0VmxExitGetsec(pVCpu, pVmxTransient));
10378 case VMX_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0VmxExitRdpmc(pVCpu, pVmxTransient));
10379#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
10380 case VMX_EXIT_VMCLEAR: VMEXIT_CALL_RET(0, hmR0VmxExitVmclear(pVCpu, pVmxTransient));
10381 case VMX_EXIT_VMLAUNCH: VMEXIT_CALL_RET(0, hmR0VmxExitVmlaunch(pVCpu, pVmxTransient));
10382 case VMX_EXIT_VMPTRLD: VMEXIT_CALL_RET(0, hmR0VmxExitVmptrld(pVCpu, pVmxTransient));
10383 case VMX_EXIT_VMPTRST: VMEXIT_CALL_RET(0, hmR0VmxExitVmptrst(pVCpu, pVmxTransient));
10384 case VMX_EXIT_VMREAD: VMEXIT_CALL_RET(0, hmR0VmxExitVmread(pVCpu, pVmxTransient));
10385 case VMX_EXIT_VMRESUME: VMEXIT_CALL_RET(0, hmR0VmxExitVmwrite(pVCpu, pVmxTransient));
10386 case VMX_EXIT_VMWRITE: VMEXIT_CALL_RET(0, hmR0VmxExitVmresume(pVCpu, pVmxTransient));
10387 case VMX_EXIT_VMXOFF: VMEXIT_CALL_RET(0, hmR0VmxExitVmxoff(pVCpu, pVmxTransient));
10388 case VMX_EXIT_VMXON: VMEXIT_CALL_RET(0, hmR0VmxExitVmxon(pVCpu, pVmxTransient));
10389#else
10390 case VMX_EXIT_VMCLEAR:
10391 case VMX_EXIT_VMLAUNCH:
10392 case VMX_EXIT_VMPTRLD:
10393 case VMX_EXIT_VMPTRST:
10394 case VMX_EXIT_VMREAD:
10395 case VMX_EXIT_VMRESUME:
10396 case VMX_EXIT_VMWRITE:
10397 case VMX_EXIT_VMXOFF:
10398 case VMX_EXIT_VMXON:
10399 return hmR0VmxExitSetPendingXcptUD(pVCpu, pVmxTransient);
10400#endif
10401
10402 case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFault(pVCpu, pVmxTransient);
10403 case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindow(pVCpu, pVmxTransient);
10404 case VMX_EXIT_INIT_SIGNAL: return hmR0VmxExitInitSignal(pVCpu, pVmxTransient);
10405 case VMX_EXIT_SIPI: return hmR0VmxExitSipi(pVCpu, pVmxTransient);
10406 case VMX_EXIT_IO_SMI: return hmR0VmxExitIoSmi(pVCpu, pVmxTransient);
10407 case VMX_EXIT_SMI: return hmR0VmxExitSmi(pVCpu, pVmxTransient);
10408 case VMX_EXIT_ERR_MSR_LOAD: return hmR0VmxExitErrMsrLoad(pVCpu, pVmxTransient);
10409 case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestState(pVCpu, pVmxTransient);
10410 case VMX_EXIT_ERR_MACHINE_CHECK: return hmR0VmxExitErrMachineCheck(pVCpu, pVmxTransient);
10411
10412 case VMX_EXIT_INVEPT:
10413 case VMX_EXIT_INVVPID:
10414 case VMX_EXIT_VMFUNC:
10415 case VMX_EXIT_XSAVES:
10416 case VMX_EXIT_XRSTORS:
10417 return hmR0VmxExitSetPendingXcptUD(pVCpu, pVmxTransient);
10418
10419 case VMX_EXIT_ENCLS:
10420 case VMX_EXIT_RDSEED: /* only spurious VM-exits, so undefined */
10421 case VMX_EXIT_PML_FULL:
10422 default:
10423 return hmR0VmxExitErrUndefined(pVCpu, pVmxTransient);
10424 }
10425#undef VMEXIT_CALL_RET
10426}
10427#endif /* !HMVMX_USE_FUNCTION_TABLE */
10428
10429
10430#ifdef VBOX_STRICT
10431/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
10432# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
10433 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
10434
10435# define HMVMX_ASSERT_PREEMPT_CPUID() \
10436 do { \
10437 RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
10438 AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
10439 } while (0)
10440
10441# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10442 do { \
10443 AssertPtr((a_pVCpu)); \
10444 AssertPtr((a_pVmxTransient)); \
10445 Assert((a_pVmxTransient)->fVMEntryFailed == false); \
10446 Assert(ASMIntAreEnabled()); \
10447 HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
10448 HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
10449 Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", (a_pVCpu)->idCpu)); \
10450 HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
10451 if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
10452 HMVMX_ASSERT_PREEMPT_CPUID(); \
10453 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10454 } while (0)
10455
10456# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10457 do { \
10458 Log4Func(("\n")); \
10459 } while (0)
10460#else
10461# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10462 do { \
10463 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10464 NOREF((a_pVCpu)); NOREF((a_pVmxTransient)); \
10465 } while (0)
10466# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) do { } while (0)
10467#endif
10468
10469
10470/**
10471 * Advances the guest RIP by the specified number of bytes.
10472 *
10473 * @param pVCpu The cross context virtual CPU structure.
10474 * @param cbInstr Number of bytes to advance the RIP by.
10475 *
10476 * @remarks No-long-jump zone!!!
10477 */
10478DECLINLINE(void) hmR0VmxAdvanceGuestRipBy(PVMCPU pVCpu, uint32_t cbInstr)
10479{
10480 /* Advance the RIP. */
10481 pVCpu->cpum.GstCtx.rip += cbInstr;
10482 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
10483
10484 /* Update interrupt inhibition. */
10485 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10486 && pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
10487 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
10488}
10489
10490
10491/**
10492 * Advances the guest RIP after reading it from the VMCS.
10493 *
10494 * @returns VBox status code, no informational status codes.
10495 * @param pVCpu The cross context virtual CPU structure.
10496 * @param pVmxTransient Pointer to the VMX transient structure.
10497 *
10498 * @remarks No-long-jump zone!!!
10499 */
10500static int hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
10501{
10502 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
10503 rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS);
10504 AssertRCReturn(rc, rc);
10505
10506 hmR0VmxAdvanceGuestRipBy(pVCpu, pVmxTransient->cbInstr);
10507 return VINF_SUCCESS;
10508}
10509
10510
10511/**
10512 * Tries to determine what part of the guest-state VT-x has deemed as invalid
10513 * and update error record fields accordingly.
10514 *
10515 * @return VMX_IGS_* return codes.
10516 * @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
10517 * wrong with the guest state.
10518 *
10519 * @param pVCpu The cross context virtual CPU structure.
10520 *
10521 * @remarks This function assumes our cache of the VMCS controls
10522 * are valid, i.e. hmR0VmxCheckVmcsCtls() succeeded.
10523 */
10524static uint32_t hmR0VmxCheckGuestState(PVMCPU pVCpu)
10525{
10526#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
10527#define HMVMX_CHECK_BREAK(expr, err) if (!(expr)) { \
10528 uError = (err); \
10529 break; \
10530 } else do { } while (0)
10531
10532 int rc;
10533 PVM pVM = pVCpu->CTX_SUFF(pVM);
10534 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
10535 uint32_t uError = VMX_IGS_ERROR;
10536 uint32_t u32Val;
10537 bool const fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
10538
10539 do
10540 {
10541 /*
10542 * CR0.
10543 */
10544 uint32_t fSetCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10545 uint32_t const fZapCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10546 /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG).
10547 See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
10548 if (fUnrestrictedGuest)
10549 fSetCr0 &= ~(X86_CR0_PE | X86_CR0_PG);
10550
10551 uint32_t u32GuestCr0;
10552 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32GuestCr0);
10553 AssertRCBreak(rc);
10554 HMVMX_CHECK_BREAK((u32GuestCr0 & fSetCr0) == fSetCr0, VMX_IGS_CR0_FIXED1);
10555 HMVMX_CHECK_BREAK(!(u32GuestCr0 & ~fZapCr0), VMX_IGS_CR0_FIXED0);
10556 if ( !fUnrestrictedGuest
10557 && (u32GuestCr0 & X86_CR0_PG)
10558 && !(u32GuestCr0 & X86_CR0_PE))
10559 {
10560 HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
10561 }
10562
10563 /*
10564 * CR4.
10565 */
10566 uint64_t const fSetCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10567 uint64_t const fZapCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10568
10569 uint32_t u32GuestCr4;
10570 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCr4);
10571 AssertRCBreak(rc);
10572 HMVMX_CHECK_BREAK((u32GuestCr4 & fSetCr4) == fSetCr4, VMX_IGS_CR4_FIXED1);
10573 HMVMX_CHECK_BREAK(!(u32GuestCr4 & ~fZapCr4), VMX_IGS_CR4_FIXED0);
10574
10575 /*
10576 * IA32_DEBUGCTL MSR.
10577 */
10578 uint64_t u64Val;
10579 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
10580 AssertRCBreak(rc);
10581 if ( (pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
10582 && (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
10583 {
10584 HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
10585 }
10586 uint64_t u64DebugCtlMsr = u64Val;
10587
10588#ifdef VBOX_STRICT
10589 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
10590 AssertRCBreak(rc);
10591 Assert(u32Val == pVCpu->hm.s.vmx.Ctls.u32EntryCtls);
10592#endif
10593 bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
10594
10595 /*
10596 * RIP and RFLAGS.
10597 */
10598 uint32_t u32Eflags;
10599#if HC_ARCH_BITS == 64
10600 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RIP, &u64Val);
10601 AssertRCBreak(rc);
10602 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
10603 if ( !fLongModeGuest
10604 || !pCtx->cs.Attr.n.u1Long)
10605 {
10606 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
10607 }
10608 /** @todo If the processor supports N < 64 linear-address bits, bits 63:N
10609 * must be identical if the "IA-32e mode guest" VM-entry
10610 * control is 1 and CS.L is 1. No check applies if the
10611 * CPU supports 64 linear-address bits. */
10612
10613 /* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
10614 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RFLAGS, &u64Val);
10615 AssertRCBreak(rc);
10616 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
10617 VMX_IGS_RFLAGS_RESERVED);
10618 HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10619 u32Eflags = u64Val;
10620#else
10621 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Eflags);
10622 AssertRCBreak(rc);
10623 HMVMX_CHECK_BREAK(!(u32Eflags & 0xffc08028), VMX_IGS_RFLAGS_RESERVED); /* Bit 31:22, Bit 15, 5, 3 MBZ. */
10624 HMVMX_CHECK_BREAK((u32Eflags & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10625#endif
10626
10627 if ( fLongModeGuest
10628 || ( fUnrestrictedGuest
10629 && !(u32GuestCr0 & X86_CR0_PE)))
10630 {
10631 HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
10632 }
10633
10634 uint32_t u32EntryInfo;
10635 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
10636 AssertRCBreak(rc);
10637 if ( VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo)
10638 && VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
10639 {
10640 HMVMX_CHECK_BREAK(u32Eflags & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
10641 }
10642
10643 /*
10644 * 64-bit checks.
10645 */
10646#if HC_ARCH_BITS == 64
10647 if (fLongModeGuest)
10648 {
10649 HMVMX_CHECK_BREAK(u32GuestCr0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE);
10650 HMVMX_CHECK_BREAK(u32GuestCr4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
10651 }
10652
10653 if ( !fLongModeGuest
10654 && (u32GuestCr4 & X86_CR4_PCIDE))
10655 {
10656 HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
10657 }
10658
10659 /** @todo CR3 field must be such that bits 63:52 and bits in the range
10660 * 51:32 beyond the processor's physical-address width are 0. */
10661
10662 if ( (pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
10663 && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
10664 {
10665 HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
10666 }
10667
10668 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
10669 AssertRCBreak(rc);
10670 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
10671
10672 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
10673 AssertRCBreak(rc);
10674 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
10675#endif
10676
10677 /*
10678 * PERF_GLOBAL MSR.
10679 */
10680 if (pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR)
10681 {
10682 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
10683 AssertRCBreak(rc);
10684 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
10685 VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
10686 }
10687
10688 /*
10689 * PAT MSR.
10690 */
10691 if (pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
10692 {
10693 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
10694 AssertRCBreak(rc);
10695 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
10696 for (unsigned i = 0; i < 8; i++)
10697 {
10698 uint8_t u8Val = (u64Val & 0xff);
10699 if ( u8Val != 0 /* UC */
10700 && u8Val != 1 /* WC */
10701 && u8Val != 4 /* WT */
10702 && u8Val != 5 /* WP */
10703 && u8Val != 6 /* WB */
10704 && u8Val != 7 /* UC- */)
10705 {
10706 HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
10707 }
10708 u64Val >>= 8;
10709 }
10710 }
10711
10712 /*
10713 * EFER MSR.
10714 */
10715 if (pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
10716 {
10717 Assert(pVM->hm.s.vmx.fSupportsVmcsEfer);
10718 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
10719 AssertRCBreak(rc);
10720 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
10721 VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
10722 HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL( pVCpu->hm.s.vmx.Ctls.u32EntryCtls
10723 & VMX_ENTRY_CTLS_IA32E_MODE_GUEST),
10724 VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
10725 /** @todo r=ramshankar: Unrestricted check here is probably wrong, see
10726 * iemVmxVmentryCheckGuestState(). */
10727 HMVMX_CHECK_BREAK( fUnrestrictedGuest
10728 || !(u32GuestCr0 & X86_CR0_PG)
10729 || RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(u64Val & MSR_K6_EFER_LME),
10730 VMX_IGS_EFER_LMA_LME_MISMATCH);
10731 }
10732
10733 /*
10734 * Segment registers.
10735 */
10736 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10737 || !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
10738 if (!(u32Eflags & X86_EFL_VM))
10739 {
10740 /* CS */
10741 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
10742 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
10743 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
10744 HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
10745 || !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10746 HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
10747 || (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10748 /* CS cannot be loaded with NULL in protected mode. */
10749 HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
10750 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
10751 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
10752 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
10753 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
10754 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
10755 else if (pVM->hm.s.vmx.fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
10756 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
10757 else
10758 HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
10759
10760 /* SS */
10761 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10762 || (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
10763 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
10764 if ( !(pCtx->cr0 & X86_CR0_PE)
10765 || pCtx->cs.Attr.n.u4Type == 3)
10766 {
10767 HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
10768 }
10769 if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
10770 {
10771 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
10772 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
10773 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
10774 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
10775 HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
10776 || !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10777 HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
10778 || (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10779 }
10780
10781 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSegmenReg(). */
10782 if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
10783 {
10784 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
10785 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
10786 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10787 || pCtx->ds.Attr.n.u4Type > 11
10788 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10789 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
10790 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
10791 HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
10792 || !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10793 HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
10794 || (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10795 HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10796 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
10797 }
10798 if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
10799 {
10800 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
10801 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
10802 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10803 || pCtx->es.Attr.n.u4Type > 11
10804 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10805 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
10806 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
10807 HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
10808 || !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10809 HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
10810 || (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10811 HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10812 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
10813 }
10814 if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
10815 {
10816 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
10817 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
10818 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10819 || pCtx->fs.Attr.n.u4Type > 11
10820 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
10821 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
10822 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
10823 HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
10824 || !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10825 HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
10826 || (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10827 HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10828 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
10829 }
10830 if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
10831 {
10832 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
10833 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
10834 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10835 || pCtx->gs.Attr.n.u4Type > 11
10836 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
10837 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
10838 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
10839 HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
10840 || !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10841 HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
10842 || (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10843 HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10844 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
10845 }
10846 /* 64-bit capable CPUs. */
10847#if HC_ARCH_BITS == 64
10848 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10849 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10850 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10851 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10852 HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10853 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
10854 VMX_IGS_LONGMODE_SS_BASE_INVALID);
10855 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
10856 VMX_IGS_LONGMODE_DS_BASE_INVALID);
10857 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
10858 VMX_IGS_LONGMODE_ES_BASE_INVALID);
10859#endif
10860 }
10861 else
10862 {
10863 /* V86 mode checks. */
10864 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
10865 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
10866 {
10867 u32CSAttr = 0xf3; u32SSAttr = 0xf3;
10868 u32DSAttr = 0xf3; u32ESAttr = 0xf3;
10869 u32FSAttr = 0xf3; u32GSAttr = 0xf3;
10870 }
10871 else
10872 {
10873 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
10874 u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
10875 u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
10876 }
10877
10878 /* CS */
10879 HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
10880 HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
10881 HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
10882 /* SS */
10883 HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
10884 HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
10885 HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
10886 /* DS */
10887 HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
10888 HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
10889 HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
10890 /* ES */
10891 HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
10892 HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
10893 HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
10894 /* FS */
10895 HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
10896 HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
10897 HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
10898 /* GS */
10899 HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
10900 HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
10901 HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
10902 /* 64-bit capable CPUs. */
10903#if HC_ARCH_BITS == 64
10904 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10905 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10906 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10907 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10908 HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10909 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
10910 VMX_IGS_LONGMODE_SS_BASE_INVALID);
10911 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
10912 VMX_IGS_LONGMODE_DS_BASE_INVALID);
10913 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
10914 VMX_IGS_LONGMODE_ES_BASE_INVALID);
10915#endif
10916 }
10917
10918 /*
10919 * TR.
10920 */
10921 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
10922 /* 64-bit capable CPUs. */
10923#if HC_ARCH_BITS == 64
10924 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
10925#endif
10926 if (fLongModeGuest)
10927 {
10928 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
10929 VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
10930 }
10931 else
10932 {
10933 HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
10934 || pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
10935 VMX_IGS_TR_ATTR_TYPE_INVALID);
10936 }
10937 HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
10938 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
10939 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
10940 HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
10941 || !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10942 HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
10943 || (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10944 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
10945
10946 /*
10947 * GDTR and IDTR.
10948 */
10949#if HC_ARCH_BITS == 64
10950 rc = VMXReadVmcs64(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
10951 AssertRCBreak(rc);
10952 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
10953
10954 rc = VMXReadVmcs64(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
10955 AssertRCBreak(rc);
10956 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
10957#endif
10958
10959 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
10960 AssertRCBreak(rc);
10961 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10962
10963 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
10964 AssertRCBreak(rc);
10965 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10966
10967 /*
10968 * Guest Non-Register State.
10969 */
10970 /* Activity State. */
10971 uint32_t u32ActivityState;
10972 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
10973 AssertRCBreak(rc);
10974 HMVMX_CHECK_BREAK( !u32ActivityState
10975 || (u32ActivityState & RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Misc, VMX_BF_MISC_ACTIVITY_STATES)),
10976 VMX_IGS_ACTIVITY_STATE_INVALID);
10977 HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
10978 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
10979 uint32_t u32IntrState;
10980 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32IntrState);
10981 AssertRCBreak(rc);
10982 if ( u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
10983 || u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
10984 {
10985 HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
10986 }
10987
10988 /** @todo Activity state and injecting interrupts. Left as a todo since we
10989 * currently don't use activity states but ACTIVE. */
10990
10991 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
10992 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
10993
10994 /* Guest interruptibility-state. */
10995 HMVMX_CHECK_BREAK(!(u32IntrState & 0xffffffe0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
10996 HMVMX_CHECK_BREAK((u32IntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
10997 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
10998 VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
10999 HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
11000 || !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
11001 VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
11002 if (VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo))
11003 {
11004 if (VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
11005 {
11006 HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11007 && !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
11008 VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
11009 }
11010 else if (VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_NMI)
11011 {
11012 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
11013 VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
11014 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
11015 VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
11016 }
11017 }
11018 /** @todo Assumes the processor is not in SMM. */
11019 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
11020 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
11021 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.Ctls.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
11022 || (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
11023 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
11024 if ( (pVCpu->hm.s.vmx.Ctls.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
11025 && VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo)
11026 && VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_NMI)
11027 {
11028 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI),
11029 VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
11030 }
11031
11032 /* Pending debug exceptions. */
11033#if HC_ARCH_BITS == 64
11034 rc = VMXReadVmcs64(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u64Val);
11035 AssertRCBreak(rc);
11036 /* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
11037 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
11038 u32Val = u64Val; /* For pending debug exceptions checks below. */
11039#else
11040 rc = VMXReadVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u32Val);
11041 AssertRCBreak(rc);
11042 /* Bits 31:15, Bit 13, Bits 11:4 MBZ. */
11043 HMVMX_CHECK_BREAK(!(u32Val & 0xffffaff0), VMX_IGS_PENDING_DEBUG_RESERVED);
11044#endif
11045
11046 if ( (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11047 || (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
11048 || u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
11049 {
11050 if ( (u32Eflags & X86_EFL_TF)
11051 && !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11052 {
11053 /* Bit 14 is PendingDebug.BS. */
11054 HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
11055 }
11056 if ( !(u32Eflags & X86_EFL_TF)
11057 || (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11058 {
11059 /* Bit 14 is PendingDebug.BS. */
11060 HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
11061 }
11062 }
11063
11064 /* VMCS link pointer. */
11065 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
11066 AssertRCBreak(rc);
11067 if (u64Val != UINT64_C(0xffffffffffffffff))
11068 {
11069 HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
11070 /** @todo Bits beyond the processor's physical-address width MBZ. */
11071 /** @todo 32-bit located in memory referenced by value of this field (as a
11072 * physical address) must contain the processor's VMCS revision ID. */
11073 /** @todo SMM checks. */
11074 }
11075
11076 /** @todo Checks on Guest Page-Directory-Pointer-Table Entries when guest is
11077 * not using Nested Paging? */
11078 if ( pVM->hm.s.fNestedPaging
11079 && !fLongModeGuest
11080 && CPUMIsGuestInPAEModeEx(pCtx))
11081 {
11082 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);
11083 AssertRCBreak(rc);
11084 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11085
11086 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);
11087 AssertRCBreak(rc);
11088 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11089
11090 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);
11091 AssertRCBreak(rc);
11092 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11093
11094 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);
11095 AssertRCBreak(rc);
11096 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11097 }
11098
11099 /* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
11100 if (uError == VMX_IGS_ERROR)
11101 uError = VMX_IGS_REASON_NOT_FOUND;
11102 } while (0);
11103
11104 pVCpu->hm.s.u32HMError = uError;
11105 return uError;
11106
11107#undef HMVMX_ERROR_BREAK
11108#undef HMVMX_CHECK_BREAK
11109}
11110
11111
11112/** @name VM-exit handlers.
11113 * @{
11114 */
11115/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11116/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
11117/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11118
11119/**
11120 * VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
11121 */
11122HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11123{
11124 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11125 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
11126 /* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
11127 if (VMMR0ThreadCtxHookIsEnabled(pVCpu))
11128 return VINF_SUCCESS;
11129 return VINF_EM_RAW_INTERRUPT;
11130}
11131
11132
11133/**
11134 * VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
11135 */
11136HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11137{
11138 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11139 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
11140
11141 int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
11142 AssertRCReturn(rc, rc);
11143
11144 uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
11145 Assert( !(pVCpu->hm.s.vmx.Ctls.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
11146 && uIntType != VMX_EXIT_INT_INFO_TYPE_EXT_INT);
11147 Assert(VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
11148
11149 if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
11150 {
11151 /*
11152 * This cannot be a guest NMI as the only way for the guest to receive an NMI is if we
11153 * injected it ourselves and anything we inject is not going to cause a VM-exit directly
11154 * for the event being injected[1]. Go ahead and dispatch the NMI to the host[2].
11155 *
11156 * [1] -- See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
11157 * [2] -- See Intel spec. 27.5.5 "Updating Non-Register State".
11158 */
11159 VMXDispatchHostNmi();
11160 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
11161 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11162 return VINF_SUCCESS;
11163 }
11164
11165 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
11166 VBOXSTRICTRC rcStrictRc1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
11167 if (RT_UNLIKELY(rcStrictRc1 == VINF_SUCCESS))
11168 { /* likely */ }
11169 else
11170 {
11171 if (rcStrictRc1 == VINF_HM_DOUBLE_FAULT)
11172 rcStrictRc1 = VINF_SUCCESS;
11173 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11174 return rcStrictRc1;
11175 }
11176
11177 uint32_t uExitIntInfo = pVmxTransient->uExitIntInfo;
11178 uint32_t uVector = VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo);
11179 switch (uIntType)
11180 {
11181 case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT: /* Privileged software exception. (#DB from ICEBP) */
11182 Assert(uVector == X86_XCPT_DB);
11183 RT_FALL_THRU();
11184 case VMX_EXIT_INT_INFO_TYPE_SW_XCPT: /* Software exception. (#BP or #OF) */
11185 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF || uIntType == VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT);
11186 RT_FALL_THRU();
11187 case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
11188 {
11189 /*
11190 * If there's any exception caused as a result of event injection, the resulting
11191 * secondary/final execption will be pending, we shall continue guest execution
11192 * after injecting the event. The page-fault case is complicated and we manually
11193 * handle any currently pending event in hmR0VmxExitXcptPF.
11194 */
11195 if (!pVCpu->hm.s.Event.fPending)
11196 { /* likely */ }
11197 else if (uVector != X86_XCPT_PF)
11198 {
11199 rc = VINF_SUCCESS;
11200 break;
11201 }
11202
11203 switch (uVector)
11204 {
11205 case X86_XCPT_PF: rc = hmR0VmxExitXcptPF(pVCpu, pVmxTransient); break;
11206 case X86_XCPT_GP: rc = hmR0VmxExitXcptGP(pVCpu, pVmxTransient); break;
11207 case X86_XCPT_MF: rc = hmR0VmxExitXcptMF(pVCpu, pVmxTransient); break;
11208 case X86_XCPT_DB: rc = hmR0VmxExitXcptDB(pVCpu, pVmxTransient); break;
11209 case X86_XCPT_BP: rc = hmR0VmxExitXcptBP(pVCpu, pVmxTransient); break;
11210 case X86_XCPT_AC: rc = hmR0VmxExitXcptAC(pVCpu, pVmxTransient); break;
11211
11212 case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
11213 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11214 case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF);
11215 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11216 case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
11217 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11218 case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
11219 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11220 case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
11221 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11222 case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
11223 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11224 case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS);
11225 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11226 default:
11227 {
11228 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
11229 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11230 {
11231 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
11232 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
11233 Assert(CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx));
11234
11235 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
11236 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11237 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
11238 AssertRCReturn(rc, rc);
11239 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(uExitIntInfo),
11240 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode,
11241 0 /* GCPtrFaultAddress */);
11242 }
11243 else
11244 {
11245 AssertMsgFailed(("Unexpected VM-exit caused by exception %#x\n", uVector));
11246 pVCpu->hm.s.u32HMError = uVector;
11247 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
11248 }
11249 break;
11250 }
11251 }
11252 break;
11253 }
11254
11255 default:
11256 {
11257 pVCpu->hm.s.u32HMError = uExitIntInfo;
11258 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
11259 AssertMsgFailed(("Unexpected interruption info %#x\n", VMX_EXIT_INT_INFO_TYPE(uExitIntInfo)));
11260 break;
11261 }
11262 }
11263 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11264 return rc;
11265}
11266
11267
11268/**
11269 * VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
11270 */
11271HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11272{
11273 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11274
11275 /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
11276 hmR0VmxClearIntWindowExitVmcs(pVCpu);
11277
11278 /* Evaluate and deliver pending events and resume guest execution. */
11279 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
11280 return VINF_SUCCESS;
11281}
11282
11283
11284/**
11285 * VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
11286 */
11287HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11288{
11289 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11290 if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)))
11291 {
11292 AssertMsgFailed(("Unexpected NMI-window exit.\n"));
11293 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11294 }
11295
11296 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS));
11297
11298 /*
11299 * If block-by-STI is set when we get this VM-exit, it means the CPU doesn't block NMIs following STI.
11300 * It is therefore safe to unblock STI and deliver the NMI ourselves. See @bugref{7445}.
11301 */
11302 uint32_t fIntrState = 0;
11303 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
11304 AssertRCReturn(rc, rc);
11305 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
11306 if (fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11307 {
11308 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
11309 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
11310
11311 fIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
11312 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
11313 AssertRCReturn(rc, rc);
11314 }
11315
11316 /* Indicate that we no longer need to VM-exit when the guest is ready to receive NMIs, it is now ready */
11317 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
11318
11319 /* Evaluate and deliver pending events and resume guest execution. */
11320 return VINF_SUCCESS;
11321}
11322
11323
11324/**
11325 * VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
11326 */
11327HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11328{
11329 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11330 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11331}
11332
11333
11334/**
11335 * VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
11336 */
11337HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11338{
11339 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11340 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11341}
11342
11343
11344/**
11345 * VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
11346 */
11347HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11348{
11349 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11350
11351 /*
11352 * Get the state we need and update the exit history entry.
11353 */
11354 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11355 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
11356 AssertRCReturn(rc, rc);
11357
11358 VBOXSTRICTRC rcStrict;
11359 PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
11360 EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_CPUID),
11361 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
11362 if (!pExitRec)
11363 {
11364 /*
11365 * Regular CPUID instruction execution.
11366 */
11367 rcStrict = IEMExecDecodedCpuid(pVCpu, pVmxTransient->cbInstr);
11368 if (rcStrict == VINF_SUCCESS)
11369 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11370 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11371 {
11372 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11373 rcStrict = VINF_SUCCESS;
11374 }
11375 }
11376 else
11377 {
11378 /*
11379 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
11380 */
11381 int rc2 = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
11382 AssertRCReturn(rc2, rc2);
11383
11384 Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
11385 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
11386
11387 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
11388 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
11389
11390 Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
11391 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
11392 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
11393 }
11394 return rcStrict;
11395}
11396
11397
11398/**
11399 * VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
11400 */
11401HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11402{
11403 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11404 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR4);
11405 AssertRCReturn(rc, rc);
11406
11407 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_SMXE)
11408 return VINF_EM_RAW_EMULATE_INSTR;
11409
11410 AssertMsgFailed(("hmR0VmxExitGetsec: unexpected VM-exit when CR4.SMXE is 0.\n"));
11411 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11412}
11413
11414
11415/**
11416 * VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
11417 */
11418HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11419{
11420 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11421 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
11422 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11423 AssertRCReturn(rc, rc);
11424
11425 VBOXSTRICTRC rcStrict = IEMExecDecodedRdtsc(pVCpu, pVmxTransient->cbInstr);
11426 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11427 {
11428 /* If we get a spurious VM-exit when offsetting is enabled,
11429 we must reset offsetting on VM-reentry. See @bugref{6634}. */
11430 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
11431 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11432 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11433 }
11434 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11435 {
11436 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11437 rcStrict = VINF_SUCCESS;
11438 }
11439 return rcStrict;
11440}
11441
11442
11443/**
11444 * VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
11445 */
11446HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11447{
11448 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11449 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_TSC_AUX);
11450 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11451 AssertRCReturn(rc, rc);
11452
11453 VBOXSTRICTRC rcStrict = IEMExecDecodedRdtscp(pVCpu, pVmxTransient->cbInstr);
11454 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11455 {
11456 /* If we get a spurious VM-exit when offsetting is enabled,
11457 we must reset offsetting on VM-reentry. See @bugref{6634}. */
11458 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
11459 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11460 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11461 }
11462 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11463 {
11464 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11465 rcStrict = VINF_SUCCESS;
11466 }
11467 return rcStrict;
11468}
11469
11470
11471/**
11472 * VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
11473 */
11474HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11475{
11476 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11477 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11478 AssertRCReturn(rc, rc);
11479
11480 PVM pVM = pVCpu->CTX_SUFF(pVM);
11481 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11482 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11483 if (RT_LIKELY(rc == VINF_SUCCESS))
11484 {
11485 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11486 Assert(pVmxTransient->cbInstr == 2);
11487 }
11488 else
11489 {
11490 AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
11491 rc = VERR_EM_INTERPRETER;
11492 }
11493 return rc;
11494}
11495
11496
11497/**
11498 * VM-exit handler for VMCALL (VMX_EXIT_VMCALL). Unconditional VM-exit.
11499 */
11500HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11501{
11502 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11503
11504 VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
11505 if (EMAreHypercallInstructionsEnabled(pVCpu))
11506 {
11507 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CR0
11508 | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
11509 AssertRCReturn(rc, rc);
11510
11511 /* Perform the hypercall. */
11512 rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
11513 if (rcStrict == VINF_SUCCESS)
11514 {
11515 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11516 AssertRCReturn(rc, rc);
11517 }
11518 else
11519 Assert( rcStrict == VINF_GIM_R3_HYPERCALL
11520 || rcStrict == VINF_GIM_HYPERCALL_CONTINUING
11521 || RT_FAILURE(rcStrict));
11522
11523 /* If the hypercall changes anything other than guest's general-purpose registers,
11524 we would need to reload the guest changed bits here before VM-entry. */
11525 }
11526 else
11527 Log4Func(("Hypercalls not enabled\n"));
11528
11529 /* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
11530 if (RT_FAILURE(rcStrict))
11531 {
11532 hmR0VmxSetPendingXcptUD(pVCpu);
11533 rcStrict = VINF_SUCCESS;
11534 }
11535
11536 return rcStrict;
11537}
11538
11539
11540/**
11541 * VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
11542 */
11543HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11544{
11545 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11546 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging || pVCpu->hm.s.fUsingDebugLoop);
11547
11548 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
11549 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11550 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
11551 AssertRCReturn(rc, rc);
11552
11553 VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, pVmxTransient->cbInstr, pVmxTransient->uExitQual);
11554
11555 if (rcStrict == VINF_SUCCESS || rcStrict == VINF_PGM_SYNC_CR3)
11556 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11557 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11558 {
11559 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11560 rcStrict = VINF_SUCCESS;
11561 }
11562 else
11563 AssertMsgFailed(("Unexpected IEMExecDecodedInvlpg(%#RX64) sttus: %Rrc\n", pVmxTransient->uExitQual,
11564 VBOXSTRICTRC_VAL(rcStrict)));
11565 return rcStrict;
11566}
11567
11568
11569/**
11570 * VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
11571 */
11572HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11573{
11574 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11575 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11576 AssertRCReturn(rc, rc);
11577
11578 PVM pVM = pVCpu->CTX_SUFF(pVM);
11579 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11580 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11581 if (RT_LIKELY(rc == VINF_SUCCESS))
11582 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11583 else
11584 {
11585 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
11586 rc = VERR_EM_INTERPRETER;
11587 }
11588 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
11589 return rc;
11590}
11591
11592
11593/**
11594 * VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
11595 */
11596HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11597{
11598 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11599 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11600 AssertRCReturn(rc, rc);
11601
11602 PVM pVM = pVCpu->CTX_SUFF(pVM);
11603 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11604 VBOXSTRICTRC rc2 = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11605 rc = VBOXSTRICTRC_VAL(rc2);
11606 if (RT_LIKELY( rc == VINF_SUCCESS
11607 || rc == VINF_EM_HALT))
11608 {
11609 int rc3 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11610 AssertRCReturn(rc3, rc3);
11611
11612 if ( rc == VINF_EM_HALT
11613 && EMMonitorWaitShouldContinue(pVCpu, pCtx))
11614 rc = VINF_SUCCESS;
11615 }
11616 else
11617 {
11618 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
11619 rc = VERR_EM_INTERPRETER;
11620 }
11621 AssertMsg(rc == VINF_SUCCESS || rc == VINF_EM_HALT || rc == VERR_EM_INTERPRETER,
11622 ("hmR0VmxExitMwait: failed, invalid error code %Rrc\n", rc));
11623 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
11624 return rc;
11625}
11626
11627
11628/**
11629 * VM-exit handler for RSM (VMX_EXIT_RSM). Unconditional VM-exit.
11630 */
11631HMVMX_EXIT_NSRC_DECL hmR0VmxExitRsm(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11632{
11633 /*
11634 * Execution of RSM outside of SMM mode causes #UD regardless of VMX root or VMX non-root
11635 * mode. In theory, we should never get this VM-exit. This can happen only if dual-monitor
11636 * treatment of SMI and VMX is enabled, which can (only?) be done by executing VMCALL in
11637 * VMX root operation. If we get here, something funny is going on.
11638 *
11639 * See Intel spec. 33.15.5 "Enabling the Dual-Monitor Treatment".
11640 */
11641 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11642 AssertMsgFailed(("Unexpected RSM VM-exit\n"));
11643 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11644}
11645
11646
11647/**
11648 * VM-exit handler for SMI (VMX_EXIT_SMI). Unconditional VM-exit.
11649 */
11650HMVMX_EXIT_NSRC_DECL hmR0VmxExitSmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11651{
11652 /*
11653 * This can only happen if we support dual-monitor treatment of SMI, which can be activated
11654 * by executing VMCALL in VMX root operation. Only an STM (SMM transfer monitor) would get
11655 * this VM-exit when we (the executive monitor) execute a VMCALL in VMX root mode or receive
11656 * an SMI. If we get here, something funny is going on.
11657 *
11658 * See Intel spec. 33.15.6 "Activating the Dual-Monitor Treatment"
11659 * See Intel spec. 25.3 "Other Causes of VM-Exits"
11660 */
11661 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11662 AssertMsgFailed(("Unexpected SMI VM-exit\n"));
11663 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11664}
11665
11666
11667/**
11668 * VM-exit handler for IO SMI (VMX_EXIT_IO_SMI). Unconditional VM-exit.
11669 */
11670HMVMX_EXIT_NSRC_DECL hmR0VmxExitIoSmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11671{
11672 /* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
11673 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11674 AssertMsgFailed(("Unexpected IO SMI VM-exit\n"));
11675 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11676}
11677
11678
11679/**
11680 * VM-exit handler for SIPI (VMX_EXIT_SIPI). Conditional VM-exit.
11681 */
11682HMVMX_EXIT_NSRC_DECL hmR0VmxExitSipi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11683{
11684 /*
11685 * SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest activity state is used.
11686 * We don't make use of it as our guests don't have direct access to the host LAPIC.
11687 * See Intel spec. 25.3 "Other Causes of VM-exits".
11688 */
11689 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11690 AssertMsgFailed(("Unexpected SIPI VM-exit\n"));
11691 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11692}
11693
11694
11695/**
11696 * VM-exit handler for INIT signal (VMX_EXIT_INIT_SIGNAL). Unconditional
11697 * VM-exit.
11698 */
11699HMVMX_EXIT_NSRC_DECL hmR0VmxExitInitSignal(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11700{
11701 /*
11702 * INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
11703 * See Intel spec. 33.14.1 Default Treatment of SMI Delivery" and Intel spec. 29.3 "VMX Instructions" for "VMXON".
11704 *
11705 * It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these VM-exits.
11706 * See Intel spec. "23.8 Restrictions on VMX operation".
11707 */
11708 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11709 return VINF_SUCCESS;
11710}
11711
11712
11713/**
11714 * VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
11715 * VM-exit.
11716 */
11717HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11718{
11719 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11720 return VINF_EM_RESET;
11721}
11722
11723
11724/**
11725 * VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
11726 */
11727HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11728{
11729 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11730 Assert(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_HLT_EXIT);
11731
11732 int rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11733 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RFLAGS);
11734 AssertRCReturn(rc, rc);
11735
11736 if (EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx)) /* Requires eflags. */
11737 rc = VINF_SUCCESS;
11738 else
11739 rc = VINF_EM_HALT;
11740
11741 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
11742 if (rc != VINF_SUCCESS)
11743 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
11744 return rc;
11745}
11746
11747
11748/**
11749 * VM-exit handler for instructions that result in a \#UD exception delivered to
11750 * the guest.
11751 */
11752HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11753{
11754 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11755 hmR0VmxSetPendingXcptUD(pVCpu);
11756 return VINF_SUCCESS;
11757}
11758
11759
11760/**
11761 * VM-exit handler for expiry of the VMX preemption timer.
11762 */
11763HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11764{
11765 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11766
11767 /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
11768 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11769
11770 /* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
11771 PVM pVM = pVCpu->CTX_SUFF(pVM);
11772 bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
11773 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
11774 return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
11775}
11776
11777
11778/**
11779 * VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
11780 */
11781HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11782{
11783 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11784
11785 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11786 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_CR4);
11787 AssertRCReturn(rc, rc);
11788
11789 VBOXSTRICTRC rcStrict = IEMExecDecodedXsetbv(pVCpu, pVmxTransient->cbInstr);
11790 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
11791 : HM_CHANGED_RAISED_XCPT_MASK);
11792
11793 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11794 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
11795
11796 return rcStrict;
11797}
11798
11799
11800/**
11801 * VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
11802 */
11803HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11804{
11805 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11806 /** @todo Use VM-exit instruction information. */
11807 return VERR_EM_INTERPRETER;
11808}
11809
11810
11811/**
11812 * VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE).
11813 * Error VM-exit.
11814 */
11815HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11816{
11817 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
11818 AssertRCReturn(rc, rc);
11819 rc = hmR0VmxCheckVmcsCtls(pVCpu);
11820 if (RT_FAILURE(rc))
11821 return rc;
11822
11823 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu);
11824 NOREF(uInvalidReason);
11825
11826#ifdef VBOX_STRICT
11827 uint32_t fIntrState;
11828 RTHCUINTREG uHCReg;
11829 uint64_t u64Val;
11830 uint32_t u32Val;
11831
11832 rc = hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
11833 rc |= hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
11834 rc |= hmR0VmxReadEntryInstrLenVmcs(pVmxTransient);
11835 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
11836 AssertRCReturn(rc, rc);
11837
11838 Log4(("uInvalidReason %u\n", uInvalidReason));
11839 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntInfo));
11840 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
11841 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
11842 Log4(("VMX_VMCS32_GUEST_INT_STATE %#RX32\n", fIntrState));
11843
11844 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val); AssertRC(rc);
11845 Log4(("VMX_VMCS_GUEST_CR0 %#RX32\n", u32Val));
11846 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
11847 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
11848 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
11849 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11850 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
11851 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
11852 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
11853 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11854 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
11855 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
11856
11857 hmR0DumpRegs(pVCpu);
11858#else
11859 NOREF(pVmxTransient);
11860#endif
11861
11862 return VERR_VMX_INVALID_GUEST_STATE;
11863}
11864
11865
11866/**
11867 * VM-exit handler for VM-entry failure due to an MSR-load
11868 * (VMX_EXIT_ERR_MSR_LOAD). Error VM-exit.
11869 */
11870HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11871{
11872 AssertMsgFailed(("Unexpected MSR-load exit\n"));
11873 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11874}
11875
11876
11877/**
11878 * VM-exit handler for VM-entry failure due to a machine-check event
11879 * (VMX_EXIT_ERR_MACHINE_CHECK). Error VM-exit.
11880 */
11881HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11882{
11883 AssertMsgFailed(("Unexpected machine-check event exit\n"));
11884 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11885}
11886
11887
11888/**
11889 * VM-exit handler for all undefined reasons. Should never ever happen.. in
11890 * theory.
11891 */
11892HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrUndefined(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11893{
11894 RT_NOREF2(pVCpu, pVmxTransient);
11895 AssertMsgFailed(("Huh!? Undefined VM-exit reason %d\n", pVmxTransient->uExitReason));
11896 return VERR_VMX_UNDEFINED_EXIT_CODE;
11897}
11898
11899
11900/**
11901 * VM-exit handler for XDTR (LGDT, SGDT, LIDT, SIDT) accesses
11902 * (VMX_EXIT_GDTR_IDTR_ACCESS) and LDT and TR access (LLDT, LTR, SLDT, STR).
11903 * Conditional VM-exit.
11904 */
11905HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11906{
11907 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11908
11909 /* By default, we don't enable VMX_PROC_CTLS2_DESCRIPTOR_TABLE_EXIT. */
11910 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
11911 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT)
11912 return VERR_EM_INTERPRETER;
11913 AssertMsgFailed(("Unexpected XDTR access\n"));
11914 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11915}
11916
11917
11918/**
11919 * VM-exit handler for RDRAND (VMX_EXIT_RDRAND). Conditional VM-exit.
11920 */
11921HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11922{
11923 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11924
11925 /* By default, we don't enable VMX_PROC_CTLS2_RDRAND_EXIT. */
11926 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT)
11927 return VERR_EM_INTERPRETER;
11928 AssertMsgFailed(("Unexpected RDRAND exit\n"));
11929 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11930}
11931
11932
11933/**
11934 * VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
11935 */
11936HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11937{
11938 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11939
11940 /** @todo Optimize this: We currently drag in in the whole MSR state
11941 * (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
11942 * MSRs required. That would require changes to IEM and possibly CPUM too.
11943 * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
11944 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
11945 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11946 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
11947 switch (idMsr)
11948 {
11949 /* The FS and GS base MSRs are not part of the above all-MSRs mask. */
11950 case MSR_K8_FS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_FS); break;
11951 case MSR_K8_GS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_GS); break;
11952 }
11953 AssertRCReturn(rc, rc);
11954
11955 Log4Func(("ecx=%#RX32\n", idMsr));
11956
11957#ifdef VBOX_STRICT
11958 if (pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
11959 {
11960 if ( hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr)
11961 && idMsr != MSR_K6_EFER)
11962 {
11963 AssertMsgFailed(("Unexpected RDMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n", idMsr));
11964 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11965 }
11966 if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
11967 {
11968 VMXMSREXITREAD enmRead;
11969 VMXMSREXITWRITE enmWrite;
11970 int rc2 = HMGetVmxMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
11971 AssertRCReturn(rc2, rc2);
11972 if (enmRead == VMXMSREXIT_PASSTHRU_READ)
11973 {
11974 AssertMsgFailed(("Unexpected RDMSR for a passthru lazy-restore MSR. ecx=%#RX32\n", idMsr));
11975 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11976 }
11977 }
11978 }
11979#endif
11980
11981 VBOXSTRICTRC rcStrict = IEMExecDecodedRdmsr(pVCpu, pVmxTransient->cbInstr);
11982 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
11983 if (rcStrict == VINF_SUCCESS)
11984 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
11985 | HM_CHANGED_GUEST_RAX | HM_CHANGED_GUEST_RDX);
11986 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11987 {
11988 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11989 rcStrict = VINF_SUCCESS;
11990 }
11991 else
11992 AssertMsg(rcStrict == VINF_CPUM_R3_MSR_READ, ("Unexpected IEMExecDecodedRdmsr rc (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
11993
11994 return rcStrict;
11995}
11996
11997
11998/**
11999 * VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
12000 */
12001HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12002{
12003 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12004
12005 /** @todo Optimize this: We currently drag in in the whole MSR state
12006 * (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
12007 * MSRs required. That would require changes to IEM and possibly CPUM too.
12008 * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
12009 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
12010 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12011 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK
12012 | CPUMCTX_EXTRN_ALL_MSRS);
12013 switch (idMsr)
12014 {
12015 /*
12016 * The FS and GS base MSRs are not part of the above all-MSRs mask.
12017 *
12018 * Although we don't need to fetch the base as it will be overwritten shortly, while
12019 * loading guest-state we would also load the entire segment register including limit
12020 * and attributes and thus we need to load them here.
12021 */
12022 case MSR_K8_FS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_FS); break;
12023 case MSR_K8_GS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_GS); break;
12024 }
12025 AssertRCReturn(rc, rc);
12026
12027 Log4Func(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", idMsr, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.eax));
12028
12029 VBOXSTRICTRC rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmxTransient->cbInstr);
12030 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
12031
12032 if (rcStrict == VINF_SUCCESS)
12033 {
12034 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
12035
12036 /* If this is an X2APIC WRMSR access, update the APIC state as well. */
12037 if ( idMsr == MSR_IA32_APICBASE
12038 || ( idMsr >= MSR_IA32_X2APIC_START
12039 && idMsr <= MSR_IA32_X2APIC_END))
12040 {
12041 /*
12042 * We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
12043 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before IEM changes it.
12044 */
12045 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
12046 }
12047 else if (idMsr == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
12048 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
12049 else if (idMsr == MSR_K6_EFER)
12050 {
12051 /*
12052 * If the guest touches EFER we need to update the VM-Entry and VM-Exit controls as well,
12053 * even if it is -not- touching bits that cause paging mode changes (LMA/LME). We care about
12054 * the other bits as well, SCE and NXE. See @bugref{7368}.
12055 */
12056 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR | HM_CHANGED_VMX_ENTRY_CTLS
12057 | HM_CHANGED_VMX_EXIT_CTLS);
12058 }
12059
12060 /* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not supported. */
12061 if (!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
12062 {
12063 switch (idMsr)
12064 {
12065 case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
12066 case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
12067 case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
12068 case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
12069 case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
12070 case MSR_K6_EFER: /* Nothing to do, already handled above. */ break;
12071 default:
12072 {
12073 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
12074 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
12075 else if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
12076 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_LAZY_MSRS);
12077 break;
12078 }
12079 }
12080 }
12081#ifdef VBOX_STRICT
12082 else
12083 {
12084 /* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
12085 switch (idMsr)
12086 {
12087 case MSR_IA32_SYSENTER_CS:
12088 case MSR_IA32_SYSENTER_EIP:
12089 case MSR_IA32_SYSENTER_ESP:
12090 case MSR_K8_FS_BASE:
12091 case MSR_K8_GS_BASE:
12092 {
12093 AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", idMsr));
12094 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12095 }
12096
12097 /* Writes to MSRs in auto-load/store area/swapped MSRs, shouldn't cause VM-exits with MSR-bitmaps. */
12098 default:
12099 {
12100 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
12101 {
12102 /* EFER writes are always intercepted, see hmR0VmxExportGuestMsrs(). */
12103 if (idMsr != MSR_K6_EFER)
12104 {
12105 AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12106 idMsr));
12107 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12108 }
12109 }
12110
12111 if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
12112 {
12113 VMXMSREXITREAD enmRead;
12114 VMXMSREXITWRITE enmWrite;
12115 int rc2 = HMGetVmxMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
12116 AssertRCReturn(rc2, rc2);
12117 if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)
12118 {
12119 AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", idMsr));
12120 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12121 }
12122 }
12123 break;
12124 }
12125 }
12126 }
12127#endif /* VBOX_STRICT */
12128 }
12129 else if (rcStrict == VINF_IEM_RAISED_XCPT)
12130 {
12131 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
12132 rcStrict = VINF_SUCCESS;
12133 }
12134 else
12135 AssertMsg(rcStrict == VINF_CPUM_R3_MSR_WRITE, ("Unexpected IEMExecDecodedWrmsr rc (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
12136
12137 return rcStrict;
12138}
12139
12140
12141/**
12142 * VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
12143 */
12144HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12145{
12146 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12147 /** @todo The guest has likely hit a contended spinlock. We might want to
12148 * poke a schedule different guest VCPU. */
12149 return VINF_EM_RAW_INTERRUPT;
12150}
12151
12152
12153/**
12154 * VM-exit handler for when the TPR value is lowered below the specified
12155 * threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
12156 */
12157HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12158{
12159 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12160 Assert(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
12161
12162 /*
12163 * The TPR shadow would've been synced with the APIC TPR in hmR0VmxPostRunGuest(). We'll re-evaluate
12164 * pending interrupts and inject them before the next VM-entry so we can just continue execution here.
12165 */
12166 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
12167 return VINF_SUCCESS;
12168}
12169
12170
12171/**
12172 * VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
12173 * VM-exit.
12174 *
12175 * @retval VINF_SUCCESS when guest execution can continue.
12176 * @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
12177 * @retval VERR_EM_INTERPRETER when something unexpected happened, fallback to
12178 * interpreter.
12179 */
12180HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12181{
12182 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12183 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
12184
12185 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12186 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12187 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12188 AssertRCReturn(rc, rc);
12189
12190 VBOXSTRICTRC rcStrict;
12191 PVM pVM = pVCpu->CTX_SUFF(pVM);
12192 RTGCUINTPTR const uExitQual = pVmxTransient->uExitQual;
12193 uint32_t const uAccessType = VMX_EXIT_QUAL_CRX_ACCESS(uExitQual);
12194 switch (uAccessType)
12195 {
12196 case VMX_EXIT_QUAL_CRX_ACCESS_WRITE: /* MOV to CRx */
12197 {
12198 uint32_t const uOldCr0 = pVCpu->cpum.GstCtx.cr0;
12199 rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_REGISTER(uExitQual),
12200 VMX_EXIT_QUAL_CRX_GENREG(uExitQual));
12201 AssertMsg( rcStrict == VINF_SUCCESS
12202 || rcStrict == VINF_IEM_RAISED_XCPT
12203 || rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12204
12205 switch (VMX_EXIT_QUAL_CRX_REGISTER(uExitQual))
12206 {
12207 case 0:
12208 {
12209 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12210 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12211 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
12212 Log4Func(("CR0 write rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr0));
12213
12214 /*
12215 * This is a kludge for handling switches back to real mode when we try to use
12216 * V86 mode to run real mode code directly. Problem is that V86 mode cannot
12217 * deal with special selector values, so we have to return to ring-3 and run
12218 * there till the selector values are V86 mode compatible.
12219 *
12220 * Note! Using VINF_EM_RESCHEDULE_REM here rather than VINF_EM_RESCHEDULE since the
12221 * latter is an alias for VINF_IEM_RAISED_XCPT which is converted to VINF_SUCCESs
12222 * at the end of this function.
12223 */
12224 if ( rc == VINF_SUCCESS
12225 && !pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest
12226 && CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx)
12227 && (uOldCr0 & X86_CR0_PE)
12228 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
12229 {
12230 /** @todo check selectors rather than returning all the time. */
12231 Log4Func(("CR0 write, back to real mode -> VINF_EM_RESCHEDULE_REM\n"));
12232 rcStrict = VINF_EM_RESCHEDULE_REM;
12233 }
12234 break;
12235 }
12236
12237 case 2:
12238 {
12239 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
12240 /* Nothing to do here, CR2 it's not part of the VMCS. */
12241 break;
12242 }
12243
12244 case 3:
12245 {
12246 Assert( !pVM->hm.s.fNestedPaging
12247 || !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
12248 || pVCpu->hm.s.fUsingDebugLoop);
12249 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
12250 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12251 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR3);
12252 Log4Func(("CR3 write rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr3));
12253 break;
12254 }
12255
12256 case 4:
12257 {
12258 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
12259 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12260 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR4);
12261 Log4Func(("CR4 write rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n", VBOXSTRICTRC_VAL(rcStrict),
12262 pVCpu->cpum.GstCtx.cr4, pVCpu->hm.s.fLoadSaveGuestXcr0));
12263 break;
12264 }
12265
12266 case 8:
12267 {
12268 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
12269 Assert(!(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
12270 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12271 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_APIC_TPR);
12272 break;
12273 }
12274 default:
12275 AssertMsgFailed(("Invalid CRx register %#x\n", VMX_EXIT_QUAL_CRX_REGISTER(uExitQual)));
12276 break;
12277 }
12278 break;
12279 }
12280
12281 case VMX_EXIT_QUAL_CRX_ACCESS_READ: /* MOV from CRx */
12282 {
12283 Assert( !pVM->hm.s.fNestedPaging
12284 || !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
12285 || pVCpu->hm.s.fUsingDebugLoop
12286 || VMX_EXIT_QUAL_CRX_REGISTER(uExitQual) != 3);
12287 /* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
12288 Assert( VMX_EXIT_QUAL_CRX_REGISTER(uExitQual) != 8
12289 || !(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
12290
12291 rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_GENREG(uExitQual),
12292 VMX_EXIT_QUAL_CRX_REGISTER(uExitQual));
12293 AssertMsg( rcStrict == VINF_SUCCESS
12294 || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12295#ifdef VBOX_WITH_STATISTICS
12296 switch (VMX_EXIT_QUAL_CRX_REGISTER(uExitQual))
12297 {
12298 case 0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
12299 case 2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
12300 case 3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
12301 case 4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
12302 case 8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
12303 }
12304#endif
12305 Log4Func(("CR%d Read access rcStrict=%Rrc\n", VMX_EXIT_QUAL_CRX_REGISTER(uExitQual),
12306 VBOXSTRICTRC_VAL(rcStrict)));
12307 if (VMX_EXIT_QUAL_CRX_GENREG(uExitQual) == X86_GREG_xSP)
12308 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_RSP);
12309 else
12310 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
12311 break;
12312 }
12313
12314 case VMX_EXIT_QUAL_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */
12315 {
12316 rcStrict = IEMExecDecodedClts(pVCpu, pVmxTransient->cbInstr);
12317 AssertMsg( rcStrict == VINF_SUCCESS
12318 || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12319
12320 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12321 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
12322 Log4Func(("CLTS rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12323 break;
12324 }
12325
12326 case VMX_EXIT_QUAL_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
12327 {
12328 /* Note! LMSW cannot clear CR0.PE, so no fRealOnV86Active kludge needed here. */
12329 rc = hmR0VmxReadGuestLinearAddrVmcs(pVCpu, pVmxTransient);
12330 AssertRCReturn(rc, rc);
12331 rcStrict = IEMExecDecodedLmsw(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_LMSW_DATA(uExitQual),
12332 pVmxTransient->uGuestLinearAddr);
12333 AssertMsg( rcStrict == VINF_SUCCESS
12334 || rcStrict == VINF_IEM_RAISED_XCPT
12335 , ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12336
12337 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12338 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
12339 Log4Func(("LMSW rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12340 break;
12341 }
12342
12343 default:
12344 AssertMsgFailedReturn(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType),
12345 VERR_VMX_UNEXPECTED_EXCEPTION);
12346 }
12347
12348 Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS))
12349 == (HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS));
12350 if (rcStrict == VINF_IEM_RAISED_XCPT)
12351 {
12352 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
12353 rcStrict = VINF_SUCCESS;
12354 }
12355
12356 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
12357 NOREF(pVM);
12358 return rcStrict;
12359}
12360
12361
12362/**
12363 * VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
12364 * VM-exit.
12365 */
12366HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12367{
12368 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12369 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
12370
12371 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12372 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12373 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12374 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_EFER);
12375 /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
12376 AssertRCReturn(rc, rc);
12377
12378 /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
12379 uint32_t uIOPort = VMX_EXIT_QUAL_IO_PORT(pVmxTransient->uExitQual);
12380 uint8_t uIOWidth = VMX_EXIT_QUAL_IO_WIDTH(pVmxTransient->uExitQual);
12381 bool fIOWrite = (VMX_EXIT_QUAL_IO_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_IO_DIRECTION_OUT);
12382 bool fIOString = VMX_EXIT_QUAL_IO_IS_STRING(pVmxTransient->uExitQual);
12383 bool fGstStepping = RT_BOOL(pCtx->eflags.Bits.u1TF);
12384 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
12385 AssertReturn(uIOWidth <= 3 && uIOWidth != 2, VERR_VMX_IPE_1);
12386
12387 /*
12388 * Update exit history to see if this exit can be optimized.
12389 */
12390 VBOXSTRICTRC rcStrict;
12391 PCEMEXITREC pExitRec = NULL;
12392 if ( !fGstStepping
12393 && !fDbgStepping)
12394 pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
12395 !fIOString
12396 ? !fIOWrite
12397 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
12398 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
12399 : !fIOWrite
12400 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
12401 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
12402 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
12403 if (!pExitRec)
12404 {
12405 /* I/O operation lookup arrays. */
12406 static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses. */
12407 static uint32_t const s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving result in AL/AX/EAX. */
12408 uint32_t const cbValue = s_aIOSizes[uIOWidth];
12409 uint32_t const cbInstr = pVmxTransient->cbInstr;
12410 bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
12411 PVM pVM = pVCpu->CTX_SUFF(pVM);
12412 if (fIOString)
12413 {
12414 /*
12415 * INS/OUTS - I/O String instruction.
12416 *
12417 * Use instruction-information if available, otherwise fall back on
12418 * interpreting the instruction.
12419 */
12420 Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12421 AssertReturn(pCtx->dx == uIOPort, VERR_VMX_IPE_2);
12422 bool const fInsOutsInfo = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
12423 if (fInsOutsInfo)
12424 {
12425 int rc2 = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12426 AssertRCReturn(rc2, rc2);
12427 AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3);
12428 AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
12429 IEMMODE const enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
12430 bool const fRep = VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual);
12431 if (fIOWrite)
12432 rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
12433 pVmxTransient->ExitInstrInfo.StrIo.iSegReg, true /*fIoChecked*/);
12434 else
12435 {
12436 /*
12437 * The segment prefix for INS cannot be overridden and is always ES. We can safely assume X86_SREG_ES.
12438 * Hence "iSegReg" field is undefined in the instruction-information field in VT-x for INS.
12439 * See Intel Instruction spec. for "INS".
12440 * See Intel spec. Table 27-8 "Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS".
12441 */
12442 rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr, true /*fIoChecked*/);
12443 }
12444 }
12445 else
12446 rcStrict = IEMExecOne(pVCpu);
12447
12448 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
12449 fUpdateRipAlready = true;
12450 }
12451 else
12452 {
12453 /*
12454 * IN/OUT - I/O instruction.
12455 */
12456 Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12457 uint32_t const uAndVal = s_aIOOpAnd[uIOWidth];
12458 Assert(!VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual));
12459 if (fIOWrite)
12460 {
12461 rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pCtx->eax & uAndVal, cbValue);
12462 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
12463 if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
12464 && !pCtx->eflags.Bits.u1TF)
12465 rcStrict = EMRZSetPendingIoPortWrite(pVCpu, uIOPort, cbInstr, cbValue, pCtx->eax & uAndVal);
12466 }
12467 else
12468 {
12469 uint32_t u32Result = 0;
12470 rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
12471 if (IOM_SUCCESS(rcStrict))
12472 {
12473 /* Save result of I/O IN instr. in AL/AX/EAX. */
12474 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Result & uAndVal);
12475 }
12476 if ( rcStrict == VINF_IOM_R3_IOPORT_READ
12477 && !pCtx->eflags.Bits.u1TF)
12478 rcStrict = EMRZSetPendingIoPortRead(pVCpu, uIOPort, cbInstr, cbValue);
12479 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
12480 }
12481 }
12482
12483 if (IOM_SUCCESS(rcStrict))
12484 {
12485 if (!fUpdateRipAlready)
12486 {
12487 hmR0VmxAdvanceGuestRipBy(pVCpu, cbInstr);
12488 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
12489 }
12490
12491 /*
12492 * INS/OUTS with REP prefix updates RFLAGS, can be observed with triple-fault guru
12493 * while booting Fedora 17 64-bit guest.
12494 *
12495 * See Intel Instruction reference for REP/REPE/REPZ/REPNE/REPNZ.
12496 */
12497 if (fIOString)
12498 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RFLAGS);
12499
12500 /*
12501 * If any I/O breakpoints are armed, we need to check if one triggered
12502 * and take appropriate action.
12503 * Note that the I/O breakpoint type is undefined if CR4.DE is 0.
12504 */
12505 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
12506 AssertRCReturn(rc, rc);
12507
12508 /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
12509 * execution engines about whether hyper BPs and such are pending. */
12510 uint32_t const uDr7 = pCtx->dr[7];
12511 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
12512 && X86_DR7_ANY_RW_IO(uDr7)
12513 && (pCtx->cr4 & X86_CR4_DE))
12514 || DBGFBpIsHwIoArmed(pVM)))
12515 {
12516 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
12517
12518 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
12519 VMMRZCallRing3Disable(pVCpu);
12520 HM_DISABLE_PREEMPT(pVCpu);
12521
12522 bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
12523
12524 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, uIOPort, cbValue);
12525 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
12526 {
12527 /* Raise #DB. */
12528 if (fIsGuestDbgActive)
12529 ASMSetDR6(pCtx->dr[6]);
12530 if (pCtx->dr[7] != uDr7)
12531 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_GUEST_DR7;
12532
12533 hmR0VmxSetPendingXcptDB(pVCpu);
12534 }
12535 /* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
12536 however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
12537 else if ( rcStrict2 != VINF_SUCCESS
12538 && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
12539 rcStrict = rcStrict2;
12540 AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
12541
12542 HM_RESTORE_PREEMPT();
12543 VMMRZCallRing3Enable(pVCpu);
12544 }
12545 }
12546
12547#ifdef VBOX_STRICT
12548 if ( rcStrict == VINF_IOM_R3_IOPORT_READ
12549 || rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
12550 Assert(!fIOWrite);
12551 else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
12552 || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
12553 || rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
12554 Assert(fIOWrite);
12555 else
12556 {
12557# if 0 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
12558 * statuses, that the VMM device and some others may return. See
12559 * IOM_SUCCESS() for guidance. */
12560 AssertMsg( RT_FAILURE(rcStrict)
12561 || rcStrict == VINF_SUCCESS
12562 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
12563 || rcStrict == VINF_EM_DBG_BREAKPOINT
12564 || rcStrict == VINF_EM_RAW_GUEST_TRAP
12565 || rcStrict == VINF_EM_RAW_TO_R3
12566 || rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12567# endif
12568 }
12569#endif
12570 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
12571 }
12572 else
12573 {
12574 /*
12575 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
12576 */
12577 int rc2 = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
12578 AssertRCReturn(rc2, rc2);
12579 STAM_COUNTER_INC(!fIOString ? fIOWrite ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
12580 : fIOWrite ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
12581 Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
12582 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12583 VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual) ? "REP " : "",
12584 fIOWrite ? "OUT" : "IN", fIOString ? "S" : "", uIOPort, uIOWidth));
12585
12586 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
12587 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
12588
12589 Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
12590 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12591 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
12592 }
12593 return rcStrict;
12594}
12595
12596
12597/**
12598 * VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
12599 * VM-exit.
12600 */
12601HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12602{
12603 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12604
12605 /* Check if this task-switch occurred while delivery an event through the guest IDT. */
12606 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12607 AssertRCReturn(rc, rc);
12608 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
12609 {
12610 rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
12611 AssertRCReturn(rc, rc);
12612 if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
12613 {
12614 uint32_t uErrCode;
12615 RTGCUINTPTR GCPtrFaultAddress;
12616 uint32_t const uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
12617 uint32_t const uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
12618 bool const fErrorCodeValid = VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo);
12619 if (fErrorCodeValid)
12620 {
12621 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
12622 AssertRCReturn(rc, rc);
12623 uErrCode = pVmxTransient->uIdtVectoringErrorCode;
12624 }
12625 else
12626 uErrCode = 0;
12627
12628 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
12629 && uVector == X86_XCPT_PF)
12630 GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
12631 else
12632 GCPtrFaultAddress = 0;
12633
12634 rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12635 AssertRCReturn(rc, rc);
12636
12637 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
12638 pVmxTransient->cbInstr, uErrCode, GCPtrFaultAddress);
12639
12640 Log4Func(("Pending event. uIntType=%#x uVector=%#x\n", uIntType, uVector));
12641 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12642 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12643 }
12644 }
12645
12646 /* Fall back to the interpreter to emulate the task-switch. */
12647 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12648 return VERR_EM_INTERPRETER;
12649}
12650
12651
12652/**
12653 * VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
12654 */
12655HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12656{
12657 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12658 Assert(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
12659 pVCpu->hm.s.vmx.Ctls.u32ProcCtls &= ~VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
12660 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.Ctls.u32ProcCtls);
12661 AssertRCReturn(rc, rc);
12662 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
12663 return VINF_EM_DBG_STEPPED;
12664}
12665
12666
12667/**
12668 * VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
12669 */
12670HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12671{
12672 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12673
12674 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
12675
12676 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12677 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12678 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12679 {
12680 /* For some crazy guest, if an event delivery causes an APIC-access VM-exit, go to instruction emulation. */
12681 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12682 {
12683 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12684 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12685 }
12686 }
12687 else
12688 {
12689 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12690 rcStrict1 = VINF_SUCCESS;
12691 return rcStrict1;
12692 }
12693
12694 /* IOMMIOPhysHandler() below may call into IEM, save the necessary state. */
12695 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12696 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12697 AssertRCReturn(rc, rc);
12698
12699 /* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
12700 uint32_t uAccessType = VMX_EXIT_QUAL_APIC_ACCESS_TYPE(pVmxTransient->uExitQual);
12701 VBOXSTRICTRC rcStrict2;
12702 switch (uAccessType)
12703 {
12704 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
12705 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
12706 {
12707 AssertMsg( !(pVCpu->hm.s.vmx.Ctls.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
12708 || VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual) != XAPIC_OFF_TPR,
12709 ("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
12710
12711 RTGCPHYS GCPhys = pVCpu->hm.s.vmx.u64MsrApicBase; /* Always up-to-date, u64MsrApicBase is not part of the VMCS. */
12712 GCPhys &= PAGE_BASE_GC_MASK;
12713 GCPhys += VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual);
12714 PVM pVM = pVCpu->CTX_SUFF(pVM);
12715 Log4Func(("Linear access uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys,
12716 VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual)));
12717
12718 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12719 rcStrict2 = IOMMMIOPhysHandler(pVM, pVCpu,
12720 uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ ? 0 : X86_TRAP_PF_RW,
12721 CPUMCTX2CORE(pCtx), GCPhys);
12722 Log4Func(("IOMMMIOPhysHandler returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
12723 if ( rcStrict2 == VINF_SUCCESS
12724 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12725 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12726 {
12727 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
12728 | HM_CHANGED_GUEST_APIC_TPR);
12729 rcStrict2 = VINF_SUCCESS;
12730 }
12731 break;
12732 }
12733
12734 default:
12735 Log4Func(("uAccessType=%#x\n", uAccessType));
12736 rcStrict2 = VINF_EM_RAW_EMULATE_INSTR;
12737 break;
12738 }
12739
12740 if (rcStrict2 != VINF_SUCCESS)
12741 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchApicAccessToR3);
12742 return rcStrict2;
12743}
12744
12745
12746/**
12747 * VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
12748 * VM-exit.
12749 */
12750HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12751{
12752 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12753
12754 /* We should -not- get this VM-exit if the guest's debug registers were active. */
12755 if (pVmxTransient->fWasGuestDebugStateActive)
12756 {
12757 AssertMsgFailed(("Unexpected MOV DRx exit\n"));
12758 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12759 }
12760
12761 if ( !pVCpu->hm.s.fSingleInstruction
12762 && !pVmxTransient->fWasHyperDebugStateActive)
12763 {
12764 Assert(!DBGFIsStepping(pVCpu));
12765 Assert(pVCpu->hm.s.vmx.Ctls.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
12766
12767 /* Don't intercept MOV DRx any more. */
12768 pVCpu->hm.s.vmx.Ctls.u32ProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
12769 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.Ctls.u32ProcCtls);
12770 AssertRCReturn(rc, rc);
12771
12772 /* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
12773 VMMRZCallRing3Disable(pVCpu);
12774 HM_DISABLE_PREEMPT(pVCpu);
12775
12776 /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
12777 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
12778 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
12779
12780 HM_RESTORE_PREEMPT();
12781 VMMRZCallRing3Enable(pVCpu);
12782
12783#ifdef VBOX_WITH_STATISTICS
12784 rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12785 AssertRCReturn(rc, rc);
12786 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
12787 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12788 else
12789 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12790#endif
12791 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
12792 return VINF_SUCCESS;
12793 }
12794
12795 /*
12796 * EMInterpretDRx[Write|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER, CS. EFER is always up-to-date.
12797 * Update the segment registers and DR7 from the CPU.
12798 */
12799 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12800 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12801 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_DR7);
12802 AssertRCReturn(rc, rc);
12803 Log4Func(("CS:RIP=%04x:%08RX64\n", pCtx->cs.Sel, pCtx->rip));
12804
12805 PVM pVM = pVCpu->CTX_SUFF(pVM);
12806 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
12807 {
12808 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
12809 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual),
12810 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual));
12811 if (RT_SUCCESS(rc))
12812 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
12813 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12814 }
12815 else
12816 {
12817 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
12818 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual),
12819 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual));
12820 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12821 }
12822
12823 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
12824 if (RT_SUCCESS(rc))
12825 {
12826 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
12827 AssertRCReturn(rc2, rc2);
12828 return VINF_SUCCESS;
12829 }
12830 return rc;
12831}
12832
12833
12834/**
12835 * VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
12836 * Conditional VM-exit.
12837 */
12838HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12839{
12840 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12841 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12842
12843 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12844 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12845 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12846 {
12847 /* If event delivery causes an EPT misconfig (MMIO), go back to instruction emulation as otherwise
12848 injecting the original pending event would most likely cause the same EPT misconfig VM-exit. */
12849 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12850 {
12851 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12852 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12853 }
12854 }
12855 else
12856 {
12857 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12858 rcStrict1 = VINF_SUCCESS;
12859 return rcStrict1;
12860 }
12861
12862 /*
12863 * Get sufficent state and update the exit history entry.
12864 */
12865 RTGCPHYS GCPhys;
12866 int rc = VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &GCPhys);
12867 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12868 AssertRCReturn(rc, rc);
12869
12870 VBOXSTRICTRC rcStrict;
12871 PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
12872 EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_MMIO),
12873 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
12874 if (!pExitRec)
12875 {
12876 /*
12877 * If we succeed, resume guest execution.
12878 * If we fail in interpreting the instruction because we couldn't get the guest physical address
12879 * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
12880 * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
12881 * weird case. See @bugref{6043}.
12882 */
12883 PVM pVM = pVCpu->CTX_SUFF(pVM);
12884 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12885 rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);
12886 Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pCtx->rip, VBOXSTRICTRC_VAL(rcStrict)));
12887 if ( rcStrict == VINF_SUCCESS
12888 || rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
12889 || rcStrict == VERR_PAGE_NOT_PRESENT)
12890 {
12891 /* Successfully handled MMIO operation. */
12892 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
12893 | HM_CHANGED_GUEST_APIC_TPR);
12894 rcStrict = VINF_SUCCESS;
12895 }
12896 }
12897 else
12898 {
12899 /*
12900 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
12901 */
12902 int rc2 = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12903 AssertRCReturn(rc2, rc2);
12904
12905 Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
12906 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhys));
12907
12908 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
12909 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
12910
12911 Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
12912 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12913 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
12914 }
12915 return VBOXSTRICTRC_TODO(rcStrict);
12916}
12917
12918
12919/**
12920 * VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
12921 * VM-exit.
12922 */
12923HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12924{
12925 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12926 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12927
12928 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12929 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12930 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12931 {
12932 /* In the unlikely case that the EPT violation happened as a result of delivering an event, log it. */
12933 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12934 Log4Func(("EPT violation with an event pending u64IntInfo=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo));
12935 }
12936 else
12937 {
12938 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12939 rcStrict1 = VINF_SUCCESS;
12940 return rcStrict1;
12941 }
12942
12943 RTGCPHYS GCPhys;
12944 int rc = VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &GCPhys);
12945 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12946 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12947 AssertRCReturn(rc, rc);
12948
12949 /* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
12950 AssertMsg(((pVmxTransient->uExitQual >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQual));
12951
12952 RTGCUINT uErrorCode = 0;
12953 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_INSTR_FETCH)
12954 uErrorCode |= X86_TRAP_PF_ID;
12955 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_DATA_WRITE)
12956 uErrorCode |= X86_TRAP_PF_RW;
12957 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_ENTRY_PRESENT)
12958 uErrorCode |= X86_TRAP_PF_P;
12959
12960 TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
12961
12962
12963 /* Handle the pagefault trap for the nested shadow table. */
12964 PVM pVM = pVCpu->CTX_SUFF(pVM);
12965 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12966
12967 Log4Func(("EPT violation %#x at %#RX64 ErrorCode %#x CS:RIP=%04x:%08RX64\n", pVmxTransient->uExitQual, GCPhys, uErrorCode,
12968 pCtx->cs.Sel, pCtx->rip));
12969
12970 VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pCtx), GCPhys);
12971 TRPMResetTrap(pVCpu);
12972
12973 /* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
12974 if ( rcStrict2 == VINF_SUCCESS
12975 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12976 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12977 {
12978 /* Successfully synced our nested page tables. */
12979 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
12980 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS);
12981 return VINF_SUCCESS;
12982 }
12983
12984 Log4Func(("EPT return to ring-3 rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
12985 return rcStrict2;
12986}
12987
12988/** @} */
12989
12990/** @name VM-exit exception handlers.
12991 * @{
12992 */
12993/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
12994/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= VM-exit exception handlers =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
12995/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
12996
12997/**
12998 * VM-exit exception handler for \#MF (Math Fault: floating point exception).
12999 */
13000static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13001{
13002 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13003 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
13004
13005 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
13006 AssertRCReturn(rc, rc);
13007
13008 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE))
13009 {
13010 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
13011 rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
13012
13013 /** @todo r=ramshankar: The Intel spec. does -not- specify that this VM-exit
13014 * provides VM-exit instruction length. If this causes problem later,
13015 * disassemble the instruction like it's done on AMD-V. */
13016 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
13017 AssertRCReturn(rc2, rc2);
13018 return rc;
13019 }
13020
13021 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13022 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13023 return rc;
13024}
13025
13026
13027/**
13028 * VM-exit exception handler for \#BP (Breakpoint exception).
13029 */
13030static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13031{
13032 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13033 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
13034
13035 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13036 AssertRCReturn(rc, rc);
13037
13038 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13039 rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
13040 if (rc == VINF_EM_RAW_GUEST_TRAP)
13041 {
13042 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13043 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13044 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13045 AssertRCReturn(rc, rc);
13046
13047 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13048 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13049 }
13050
13051 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_EM_DBG_BREAKPOINT);
13052 return rc;
13053}
13054
13055
13056/**
13057 * VM-exit exception handler for \#AC (alignment check exception).
13058 */
13059static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13060{
13061 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13062
13063 /*
13064 * Re-inject it. We'll detect any nesting before getting here.
13065 */
13066 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13067 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13068 AssertRCReturn(rc, rc);
13069 Assert(ASMAtomicUoReadU32(&pVmxTransient->fVmcsFieldsRead) & HMVMX_READ_EXIT_INTERRUPTION_INFO);
13070
13071 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13072 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13073 return VINF_SUCCESS;
13074}
13075
13076
13077/**
13078 * VM-exit exception handler for \#DB (Debug exception).
13079 */
13080static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13081{
13082 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13083 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
13084
13085 /*
13086 * Get the DR6-like values from the VM-exit qualification and pass it to DBGF
13087 * for processing.
13088 */
13089 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13090
13091 /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
13092 uint64_t uDR6 = X86_DR6_INIT_VAL;
13093 uDR6 |= (pVmxTransient->uExitQual & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3 | X86_DR6_BD | X86_DR6_BS));
13094
13095 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13096 rc = DBGFRZTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
13097 Log6Func(("rc=%Rrc\n", rc));
13098 if (rc == VINF_EM_RAW_GUEST_TRAP)
13099 {
13100 /*
13101 * The exception was for the guest. Update DR6, DR7.GD and
13102 * IA32_DEBUGCTL.LBR before forwarding it.
13103 * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
13104 */
13105 VMMRZCallRing3Disable(pVCpu);
13106 HM_DISABLE_PREEMPT(pVCpu);
13107
13108 pCtx->dr[6] &= ~X86_DR6_B_MASK;
13109 pCtx->dr[6] |= uDR6;
13110 if (CPUMIsGuestDebugStateActive(pVCpu))
13111 ASMSetDR6(pCtx->dr[6]);
13112
13113 HM_RESTORE_PREEMPT();
13114 VMMRZCallRing3Enable(pVCpu);
13115
13116 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
13117 AssertRCReturn(rc, rc);
13118
13119 /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
13120 pCtx->dr[7] &= ~X86_DR7_GD;
13121
13122 /* Paranoia. */
13123 pCtx->dr[7] &= ~X86_DR7_RAZ_MASK;
13124 pCtx->dr[7] |= X86_DR7_RA1_MASK;
13125
13126 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pCtx->dr[7]);
13127 AssertRCReturn(rc, rc);
13128
13129 /*
13130 * Raise #DB in the guest.
13131 *
13132 * It is important to reflect exactly what the VM-exit gave us (preserving the
13133 * interruption-type) rather than use hmR0VmxSetPendingXcptDB() as the #DB could've
13134 * been raised while executing ICEBP (INT1) and not the regular #DB. Thus it may
13135 * trigger different handling in the CPU (like skipping DPL checks), see @bugref{6398}.
13136 *
13137 * Intel re-documented ICEBP/INT1 on May 2018 previously documented as part of
13138 * Intel 386, see Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
13139 */
13140 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13141 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13142 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13143 AssertRCReturn(rc, rc);
13144 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13145 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13146 return VINF_SUCCESS;
13147 }
13148
13149 /*
13150 * Not a guest trap, must be a hypervisor related debug event then.
13151 * Update DR6 in case someone is interested in it.
13152 */
13153 AssertMsg(rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
13154 AssertReturn(pVmxTransient->fWasHyperDebugStateActive, VERR_HM_IPE_5);
13155 CPUMSetHyperDR6(pVCpu, uDR6);
13156
13157 return rc;
13158}
13159
13160
13161/**
13162 * Hacks its way around the lovely mesa driver's backdoor accesses.
13163 *
13164 * @sa hmR0SvmHandleMesaDrvGp
13165 */
13166static int hmR0VmxHandleMesaDrvGp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, PCPUMCTX pCtx)
13167{
13168 Log(("hmR0VmxHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->rcx, pCtx->rbx));
13169 RT_NOREF(pCtx);
13170
13171 /* For now we'll just skip the instruction. */
13172 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
13173}
13174
13175
13176/**
13177 * Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
13178 * backdoor logging w/o checking what it is running inside.
13179 *
13180 * This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
13181 * backdoor port and magic numbers loaded in registers.
13182 *
13183 * @returns true if it is, false if it isn't.
13184 * @sa hmR0SvmIsMesaDrvGp
13185 */
13186DECLINLINE(bool) hmR0VmxIsMesaDrvGp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, PCPUMCTX pCtx)
13187{
13188 /* 0xed: IN eAX,dx */
13189 uint8_t abInstr[1];
13190 if (pVmxTransient->cbInstr != sizeof(abInstr))
13191 return false;
13192
13193 /* Check that it is #GP(0). */
13194 if (pVmxTransient->uExitIntErrorCode != 0)
13195 return false;
13196
13197 /* Check magic and port. */
13198 Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX)));
13199 /*Log(("hmR0VmxIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->rax, pCtx->rdx));*/
13200 if (pCtx->rax != UINT32_C(0x564d5868))
13201 return false;
13202 if (pCtx->dx != UINT32_C(0x5658))
13203 return false;
13204
13205 /* Flat ring-3 CS. */
13206 AssertCompile(HMVMX_CPUMCTX_EXTRN_ALL & CPUMCTX_EXTRN_CS);
13207 Assert(!(pCtx->fExtrn & CPUMCTX_EXTRN_CS));
13208 /*Log(("hmR0VmxIsMesaDrvGp: cs.Attr.n.u2Dpl=%d base=%Rx64\n", pCtx->cs.Attr.n.u2Dpl, pCtx->cs.u64Base));*/
13209 if (pCtx->cs.Attr.n.u2Dpl != 3)
13210 return false;
13211 if (pCtx->cs.u64Base != 0)
13212 return false;
13213
13214 /* Check opcode. */
13215 AssertCompile(HMVMX_CPUMCTX_EXTRN_ALL & CPUMCTX_EXTRN_RIP);
13216 Assert(!(pCtx->fExtrn & CPUMCTX_EXTRN_RIP));
13217 int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
13218 /*Log(("hmR0VmxIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0]));*/
13219 if (RT_FAILURE(rc))
13220 return false;
13221 if (abInstr[0] != 0xed)
13222 return false;
13223
13224 return true;
13225}
13226
13227
13228/**
13229 * VM-exit exception handler for \#GP (General-protection exception).
13230 *
13231 * @remarks Requires pVmxTransient->uExitIntInfo to be up-to-date.
13232 */
13233static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13234{
13235 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13236 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
13237
13238 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13239 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
13240 { /* likely */ }
13241 else
13242 {
13243#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13244 Assert(pVCpu->hm.s.fUsingDebugLoop || pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv);
13245#endif
13246 /* If the guest is not in real-mode or we have unrestricted execution support, reflect #GP to the guest. */
13247 int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13248 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13249 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13250 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13251 AssertRCReturn(rc, rc);
13252 Log4Func(("Gst: CS:RIP %04x:%08RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u TR=%#04x\n", pCtx->cs.Sel, pCtx->rip,
13253 pVmxTransient->uExitIntErrorCode, pCtx->cr0, CPUMGetGuestCPL(pVCpu), pCtx->tr.Sel));
13254
13255 if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
13256 || !hmR0VmxIsMesaDrvGp(pVCpu, pVmxTransient, pCtx))
13257 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13258 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13259 else
13260 rc = hmR0VmxHandleMesaDrvGp(pVCpu, pVmxTransient, pCtx);
13261 return rc;
13262 }
13263
13264 Assert(CPUMIsGuestInRealModeEx(pCtx));
13265 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest);
13266
13267 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13268 AssertRCReturn(rc, rc);
13269
13270 VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
13271 if (rcStrict == VINF_SUCCESS)
13272 {
13273 if (!CPUMIsGuestInRealModeEx(pCtx))
13274 {
13275 /*
13276 * The guest is no longer in real-mode, check if we can continue executing the
13277 * guest using hardware-assisted VMX. Otherwise, fall back to emulation.
13278 */
13279 if (HMCanExecuteVmxGuest(pVCpu, pCtx))
13280 {
13281 Log4Func(("Mode changed but guest still suitable for executing using VT-x\n"));
13282 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
13283 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13284 }
13285 else
13286 {
13287 Log4Func(("Mode changed -> VINF_EM_RESCHEDULE\n"));
13288 rcStrict = VINF_EM_RESCHEDULE;
13289 }
13290 }
13291 else
13292 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13293 }
13294 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13295 {
13296 rcStrict = VINF_SUCCESS;
13297 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13298 }
13299 return VBOXSTRICTRC_VAL(rcStrict);
13300}
13301
13302
13303/**
13304 * VM-exit exception handler wrapper for generic exceptions. Simply re-injects
13305 * the exception reported in the VMX transient structure back into the VM.
13306 *
13307 * @remarks Requires uExitIntInfo in the VMX transient structure to be
13308 * up-to-date.
13309 */
13310static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13311{
13312 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13313#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13314 AssertMsg(pVCpu->hm.s.fUsingDebugLoop || pVCpu->hm.s.vmx.RealMode.fRealOnV86Active,
13315 ("uVector=%#x u32XcptBitmap=%#X32\n",
13316 VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo), pVCpu->hm.s.vmx.Ctls.u32XcptBitmap));
13317#endif
13318
13319 /* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in
13320 hmR0VmxCheckExitDueToEventDelivery(). */
13321 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13322 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13323 AssertRCReturn(rc, rc);
13324 Assert(ASMAtomicUoReadU32(&pVmxTransient->fVmcsFieldsRead) & HMVMX_READ_EXIT_INTERRUPTION_INFO);
13325
13326#ifdef DEBUG_ramshankar
13327 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
13328 uint8_t uVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
13329 Log(("hmR0VmxExitXcptGeneric: Reinjecting Xcpt. uVector=%#x cs:rip=%#04x:%#RX64\n", uVector, pCtx->cs.Sel, pCtx->rip));
13330#endif
13331
13332 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13333 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13334 return VINF_SUCCESS;
13335}
13336
13337
13338/**
13339 * VM-exit exception handler for \#PF (Page-fault exception).
13340 */
13341static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13342{
13343 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13344 PVM pVM = pVCpu->CTX_SUFF(pVM);
13345 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13346 rc |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13347 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13348 AssertRCReturn(rc, rc);
13349
13350 if (!pVM->hm.s.fNestedPaging)
13351 { /* likely */ }
13352 else
13353 {
13354#if !defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) && !defined(HMVMX_ALWAYS_TRAP_PF)
13355 Assert(pVCpu->hm.s.fUsingDebugLoop);
13356#endif
13357 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
13358 if (RT_LIKELY(!pVmxTransient->fVectoringDoublePF))
13359 {
13360 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
13361 pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual);
13362 }
13363 else
13364 {
13365 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13366 hmR0VmxSetPendingXcptDF(pVCpu);
13367 Log4Func(("Pending #DF due to vectoring #PF w/ NestedPaging\n"));
13368 }
13369 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13370 return rc;
13371 }
13372
13373 /* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
13374 of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
13375 if (pVmxTransient->fVectoringPF)
13376 {
13377 Assert(pVCpu->hm.s.Event.fPending);
13378 return VINF_EM_RAW_INJECT_TRPM_EVENT;
13379 }
13380
13381 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13382 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13383 AssertRCReturn(rc, rc);
13384
13385 Log4Func(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQual, pCtx->cs.Sel,
13386 pCtx->rip, pVmxTransient->uExitIntErrorCode, pCtx->cr3));
13387
13388 TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQual, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
13389 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pCtx), (RTGCPTR)pVmxTransient->uExitQual);
13390
13391 Log4Func(("#PF: rc=%Rrc\n", rc));
13392 if (rc == VINF_SUCCESS)
13393 {
13394 /*
13395 * This is typically a shadow page table sync or a MMIO instruction. But we may have
13396 * emulated something like LTR or a far jump. Any part of the CPU context may have changed.
13397 */
13398 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13399 TRPMResetTrap(pVCpu);
13400 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
13401 return rc;
13402 }
13403
13404 if (rc == VINF_EM_RAW_GUEST_TRAP)
13405 {
13406 if (!pVmxTransient->fVectoringDoublePF)
13407 {
13408 /* It's a guest page fault and needs to be reflected to the guest. */
13409 uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);
13410 TRPMResetTrap(pVCpu);
13411 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
13412 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
13413 uGstErrorCode, pVmxTransient->uExitQual);
13414 }
13415 else
13416 {
13417 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13418 TRPMResetTrap(pVCpu);
13419 pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
13420 hmR0VmxSetPendingXcptDF(pVCpu);
13421 Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
13422 }
13423
13424 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13425 return VINF_SUCCESS;
13426 }
13427
13428 TRPMResetTrap(pVCpu);
13429 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
13430 return rc;
13431}
13432
13433/** @} */
13434
13435#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
13436/** @name Nested-guest VM-exit handlers.
13437 * @{
13438 */
13439/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13440/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Nested-guest VM-exit handlers =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13441/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13442
13443/**
13444 * VM-exit handler for VMCLEAR (VMX_EXIT_VMCLEAR). Unconditional VM-exit.
13445 */
13446HMVMX_EXIT_DECL hmR0VmxExitVmclear(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13447{
13448 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13449
13450 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13451 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13452 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13453 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13454 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13455 AssertRCReturn(rc, rc);
13456
13457 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13458
13459 VMXVEXITINFO ExitInfo;
13460 RT_ZERO(ExitInfo);
13461 ExitInfo.uReason = pVmxTransient->uExitReason;
13462 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13463 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13464 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13465 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13466
13467 VBOXSTRICTRC rcStrict = IEMExecDecodedVmclear(pVCpu, &ExitInfo);
13468 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13469 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13470 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13471 {
13472 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13473 rcStrict = VINF_SUCCESS;
13474 }
13475 return rcStrict;
13476}
13477
13478
13479/**
13480 * VM-exit handler for VMLAUNCH (VMX_EXIT_VMLAUNCH). Unconditional VM-exit.
13481 */
13482HMVMX_EXIT_DECL hmR0VmxExitVmlaunch(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13483{
13484 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13485
13486 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13487 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
13488 AssertRCReturn(rc, rc);
13489
13490 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13491
13492 VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbInstr, VMXINSTRID_VMLAUNCH);
13493 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13494 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13495 Assert(rcStrict != VINF_IEM_RAISED_XCPT);
13496 return rcStrict;
13497}
13498
13499
13500/**
13501 * VM-exit handler for VMPTRLD (VMX_EXIT_VMPTRLD). Unconditional VM-exit.
13502 */
13503HMVMX_EXIT_DECL hmR0VmxExitVmptrld(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13504{
13505 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13506
13507 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13508 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13509 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13510 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13511 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13512 AssertRCReturn(rc, rc);
13513
13514 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13515
13516 VMXVEXITINFO ExitInfo;
13517 RT_ZERO(ExitInfo);
13518 ExitInfo.uReason = pVmxTransient->uExitReason;
13519 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13520 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13521 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13522 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13523
13524 VBOXSTRICTRC rcStrict = IEMExecDecodedVmptrld(pVCpu, &ExitInfo);
13525 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13526 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13527 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13528 {
13529 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13530 rcStrict = VINF_SUCCESS;
13531 }
13532 return rcStrict;
13533}
13534
13535
13536/**
13537 * VM-exit handler for VMPTRST (VMX_EXIT_VMPTRST). Unconditional VM-exit.
13538 */
13539HMVMX_EXIT_DECL hmR0VmxExitVmptrst(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13540{
13541 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13542
13543 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13544 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13545 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13546 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13547 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13548 AssertRCReturn(rc, rc);
13549
13550 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13551
13552 VMXVEXITINFO ExitInfo;
13553 RT_ZERO(ExitInfo);
13554 ExitInfo.uReason = pVmxTransient->uExitReason;
13555 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13556 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13557 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13558 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_WRITE, &ExitInfo.GCPtrEffAddr);
13559
13560 VBOXSTRICTRC rcStrict = IEMExecDecodedVmptrst(pVCpu, &ExitInfo);
13561 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13562 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13563 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13564 {
13565 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13566 rcStrict = VINF_SUCCESS;
13567 }
13568 return rcStrict;
13569}
13570
13571
13572/**
13573 * VM-exit handler for VMREAD (VMX_EXIT_VMREAD). Unconditional VM-exit.
13574 */
13575HMVMX_EXIT_DECL hmR0VmxExitVmread(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13576{
13577 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13578
13579 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13580 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13581 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13582 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13583 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13584 AssertRCReturn(rc, rc);
13585
13586 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13587
13588 VMXVEXITINFO ExitInfo;
13589 RT_ZERO(ExitInfo);
13590 ExitInfo.uReason = pVmxTransient->uExitReason;
13591 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13592 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13593 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13594 if (!ExitInfo.InstrInfo.VmreadVmwrite.fIsRegOperand)
13595 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_WRITE, &ExitInfo.GCPtrEffAddr);
13596
13597 VBOXSTRICTRC rcStrict = IEMExecDecodedVmread(pVCpu, &ExitInfo);
13598 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13599 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13600 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13601 {
13602 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13603 rcStrict = VINF_SUCCESS;
13604 }
13605 return rcStrict;
13606}
13607
13608
13609/**
13610 * VM-exit handler for VMRESUME (VMX_EXIT_VMRESUME). Unconditional VM-exit.
13611 */
13612HMVMX_EXIT_DECL hmR0VmxExitVmresume(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13613{
13614 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13615
13616 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13617 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
13618 AssertRCReturn(rc, rc);
13619
13620 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13621
13622 VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbInstr, VMXINSTRID_VMRESUME);
13623 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13624 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13625 Assert(rcStrict != VINF_IEM_RAISED_XCPT);
13626 return rcStrict;
13627}
13628
13629
13630/**
13631 * VM-exit handler for VMWRITE (VMX_EXIT_VMWRITE). Unconditional VM-exit.
13632 */
13633HMVMX_EXIT_DECL hmR0VmxExitVmwrite(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13634{
13635 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13636
13637 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13638 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13639 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13640 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13641 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13642 AssertRCReturn(rc, rc);
13643
13644 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13645
13646 VMXVEXITINFO ExitInfo;
13647 RT_ZERO(ExitInfo);
13648 ExitInfo.uReason = pVmxTransient->uExitReason;
13649 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13650 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13651 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13652 if (!ExitInfo.InstrInfo.VmreadVmwrite.fIsRegOperand)
13653 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13654
13655 VBOXSTRICTRC rcStrict = IEMExecDecodedVmwrite(pVCpu, &ExitInfo);
13656 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13657 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13658 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13659 {
13660 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13661 rcStrict = VINF_SUCCESS;
13662 }
13663 return rcStrict;
13664}
13665
13666
13667/**
13668 * VM-exit handler for VMXOFF (VMX_EXIT_VMXOFF). Unconditional VM-exit.
13669 */
13670HMVMX_EXIT_DECL hmR0VmxExitVmxoff(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13671{
13672 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13673
13674 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13675 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR4 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
13676 AssertRCReturn(rc, rc);
13677
13678 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13679
13680 VBOXSTRICTRC rcStrict = IEMExecDecodedVmxoff(pVCpu, pVmxTransient->cbInstr);
13681 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13682 {
13683 /* VMXOFF changes the internal hwvirt. state but not anything that's visible to the guest other than RIP. */
13684 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_HWVIRT);
13685 }
13686 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13687 {
13688 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13689 rcStrict = VINF_SUCCESS;
13690 }
13691 return rcStrict;
13692}
13693
13694
13695/**
13696 * VM-exit handler for VMXON (VMX_EXIT_VMXON). Unconditional VM-exit.
13697 */
13698HMVMX_EXIT_DECL hmR0VmxExitVmxon(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13699{
13700 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13701
13702 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13703 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13704 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13705 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13706 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13707 AssertRCReturn(rc, rc);
13708
13709 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13710
13711 VMXVEXITINFO ExitInfo;
13712 RT_ZERO(ExitInfo);
13713 ExitInfo.uReason = pVmxTransient->uExitReason;
13714 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13715 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13716 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13717 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13718
13719 VBOXSTRICTRC rcStrict = IEMExecDecodedVmxon(pVCpu, &ExitInfo);
13720 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13721 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13722 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13723 {
13724 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13725 rcStrict = VINF_SUCCESS;
13726 }
13727 return rcStrict;
13728}
13729
13730/** @} */
13731#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
13732
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