HMVMXR0.cpp@ 90440

Last change on this file since 90440 was 90379, checked in by vboxsync, 4 years ago
VMM: Implementing blocking on critical sections in ring-0 HM context (actual code is disabled). bugref:6695
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1	/* $Id: HMVMXR0.cpp 90379 2021-07-28 20:00:43Z vboxsync $ */
2	/** @file
3	* HM VMX (Intel VT-x) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2012-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/x86.h>
25	#include <iprt/asm-amd64-x86.h>
26	#include <iprt/thread.h>
27	#include <iprt/mem.h>
28	#include <iprt/mp.h>
29
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/iem.h>
33	#include <VBox/vmm/iom.h>
34	#include <VBox/vmm/tm.h>
35	#include <VBox/vmm/em.h>
36	#include <VBox/vmm/gim.h>
37	#include <VBox/vmm/apic.h>
38	#include "HMInternal.h"
39	#include <VBox/vmm/vmcc.h>
40	#include <VBox/vmm/hmvmxinline.h>
41	#include "HMVMXR0.h"
42	#include "dtrace/VBoxVMM.h"
43
44	#ifdef DEBUG_ramshankar
45	# define HMVMX_ALWAYS_SAVE_GUEST_RFLAGS
46	# define HMVMX_ALWAYS_SAVE_RO_GUEST_STATE
47	# define HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE
48	# define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
49	# define HMVMX_ALWAYS_CLEAN_TRANSIENT
50	# define HMVMX_ALWAYS_CHECK_GUEST_STATE
51	# define HMVMX_ALWAYS_TRAP_ALL_XCPTS
52	# define HMVMX_ALWAYS_TRAP_PF
53	# define HMVMX_ALWAYS_FLUSH_TLB
54	# define HMVMX_ALWAYS_SWAP_EFER
55	#endif
56
57
58	/*********************************************************************************************************************************
59	* Defined Constants And Macros *
60	*********************************************************************************************************************************/
61	/** Use the function table. */
62	#define HMVMX_USE_FUNCTION_TABLE
63
64	/** Determine which tagged-TLB flush handler to use. */
65	#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
66	#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
67	#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
68	#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
69
70	/**
71	* Flags to skip redundant reads of some common VMCS fields that are not part of
72	* the guest-CPU or VCPU state but are needed while handling VM-exits.
73	*/
74	#define HMVMX_READ_IDT_VECTORING_INFO RT_BIT_32(0)
75	#define HMVMX_READ_IDT_VECTORING_ERROR_CODE RT_BIT_32(1)
76	#define HMVMX_READ_EXIT_QUALIFICATION RT_BIT_32(2)
77	#define HMVMX_READ_EXIT_INSTR_LEN RT_BIT_32(3)
78	#define HMVMX_READ_EXIT_INTERRUPTION_INFO RT_BIT_32(4)
79	#define HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE RT_BIT_32(5)
80	#define HMVMX_READ_EXIT_INSTR_INFO RT_BIT_32(6)
81	#define HMVMX_READ_GUEST_LINEAR_ADDR RT_BIT_32(7)
82	#define HMVMX_READ_GUEST_PHYSICAL_ADDR RT_BIT_32(8)
83	#define HMVMX_READ_GUEST_PENDING_DBG_XCPTS RT_BIT_32(9)
84
85	/** All the VMCS fields required for processing of exception/NMI VM-exits. */
86	#define HMVMX_READ_XCPT_INFO ( HMVMX_READ_EXIT_INTERRUPTION_INFO \
87	\| HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE \
88	\| HMVMX_READ_EXIT_INSTR_LEN \
89	\| HMVMX_READ_IDT_VECTORING_INFO \
90	\| HMVMX_READ_IDT_VECTORING_ERROR_CODE)
91
92	/** Assert that all the given fields have been read from the VMCS. */
93	#ifdef VBOX_STRICT
94	# define HMVMX_ASSERT_READ(a_pVmxTransient, a_fReadFields) \
95	do { \
96	uint32_t const fVmcsFieldRead = ASMAtomicUoReadU32(&pVmxTransient->fVmcsFieldsRead); \
97	Assert((fVmcsFieldRead & (a_fReadFields)) == (a_fReadFields)); \
98	} while (0)
99	#else
100	# define HMVMX_ASSERT_READ(a_pVmxTransient, a_fReadFields) do { } while (0)
101	#endif
102
103	/**
104	* Subset of the guest-CPU state that is kept by VMX R0 code while executing the
105	* guest using hardware-assisted VMX.
106	*
107	* This excludes state like GPRs (other than RSP) which are always are
108	* swapped and restored across the world-switch and also registers like EFER,
109	* MSR which cannot be modified by the guest without causing a VM-exit.
110	*/
111	#define HMVMX_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
112	\| CPUMCTX_EXTRN_RFLAGS \
113	\| CPUMCTX_EXTRN_RSP \
114	\| CPUMCTX_EXTRN_SREG_MASK \
115	\| CPUMCTX_EXTRN_TABLE_MASK \
116	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
117	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
118	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
119	\| CPUMCTX_EXTRN_TSC_AUX \
120	\| CPUMCTX_EXTRN_OTHER_MSRS \
121	\| CPUMCTX_EXTRN_CR0 \
122	\| CPUMCTX_EXTRN_CR3 \
123	\| CPUMCTX_EXTRN_CR4 \
124	\| CPUMCTX_EXTRN_DR7 \
125	\| CPUMCTX_EXTRN_HWVIRT \
126	\| CPUMCTX_EXTRN_HM_VMX_MASK)
127
128	/**
129	* Exception bitmap mask for real-mode guests (real-on-v86).
130	*
131	* We need to intercept all exceptions manually except:
132	* - \#AC and \#DB are always intercepted to prevent the CPU from deadlocking
133	* due to bugs in Intel CPUs.
134	* - \#PF need not be intercepted even in real-mode if we have nested paging
135	* support.
136	*/
137	#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) /* always: \| RT_BIT(X86_XCPT_DB) */ \| RT_BIT(X86_XCPT_NMI) \
138	\| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \
139	\| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_DF) \
140	\| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \
141	\| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
142	\| RT_BIT(X86_XCPT_MF) /* always: \| RT_BIT(X86_XCPT_AC) */ \| RT_BIT(X86_XCPT_MC) \
143	\| RT_BIT(X86_XCPT_XF))
144
145	/** Maximum VM-instruction error number. */
146	#define HMVMX_INSTR_ERROR_MAX 28
147
148	/** Profiling macro. */
149	#ifdef HM_PROFILE_EXIT_DISPATCH
150	# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
151	# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
152	#else
153	# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
154	# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
155	#endif
156
157	/** Assert that preemption is disabled or covered by thread-context hooks. */
158	#define HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
159	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD))
160
161	/** Assert that we haven't migrated CPUs when thread-context hooks are not
162	* used. */
163	#define HMVMX_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
164	\|\| (a_pVCpu)->hmr0.s.idEnteredCpu == RTMpCpuId(), \
165	("Illegal migration! Entered on CPU %u Current %u\n", \
166	(a_pVCpu)->hmr0.s.idEnteredCpu, RTMpCpuId()))
167
168	/** Asserts that the given CPUMCTX_EXTRN_XXX bits are present in the guest-CPU
169	* context. */
170	#define HMVMX_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
171	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
172	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
173
174	/** Log the VM-exit reason with an easily visible marker to identify it in a
175	* potential sea of logging data. */
176	#define HMVMX_LOG_EXIT(a_pVCpu, a_uExitReason) \
177	do { \
178	Log4(("VM-exit: vcpu[%RU32] %85s -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu, \
179	HMGetVmxExitName(a_uExitReason))); \
180	} while (0) \
181
182
183	/*********************************************************************************************************************************
184	* Structures and Typedefs *
185	*********************************************************************************************************************************/
186	/**
187	* VMX per-VCPU transient state.
188	*
189	* A state structure for holding miscellaneous information across
190	* VMX non-root operation and restored after the transition.
191	*
192	* Note: The members are ordered and aligned such that the most
193	* frequently used ones (in the guest execution loop) fall within
194	* the first cache line.
195	*/
196	typedef struct VMXTRANSIENT
197	{
198	/** Mask of currently read VMCS fields; HMVMX_READ_XXX. */
199	uint32_t fVmcsFieldsRead;
200	/** The guest's TPR value used for TPR shadowing. */
201	uint8_t u8GuestTpr;
202	uint8_t abAlignment0[3];
203
204	/** Whether the VM-exit was caused by a page-fault during delivery of an
205	* external interrupt or NMI. */
206	bool fVectoringPF;
207	/** Whether the VM-exit was caused by a page-fault during delivery of a
208	* contributory exception or a page-fault. */
209	bool fVectoringDoublePF;
210	/** Whether the VM-entry failed or not. */
211	bool fVMEntryFailed;
212	/** Whether the TSC_AUX MSR needs to be removed from the auto-load/store MSR
213	* area after VM-exit. */
214	bool fRemoveTscAuxMsr;
215	/** Whether TSC-offsetting and VMX-preemption timer was updated before VM-entry. */
216	bool fUpdatedTscOffsettingAndPreemptTimer;
217	/** Whether we are currently executing a nested-guest. */
218	bool fIsNestedGuest;
219	/** Whether the guest debug state was active at the time of VM-exit. */
220	bool fWasGuestDebugStateActive;
221	/** Whether the hyper debug state was active at the time of VM-exit. */
222	bool fWasHyperDebugStateActive;
223
224	/** The basic VM-exit reason. */
225	uint32_t uExitReason;
226	/** The VM-exit interruption error code. */
227	uint32_t uExitIntErrorCode;
228
229	/** The host's rflags/eflags. */
230	RTCCUINTREG fEFlags;
231
232	/** The VM-exit exit code qualification. */
233	uint64_t uExitQual;
234
235	/** The VMCS info. object. */
236	PVMXVMCSINFO pVmcsInfo;
237
238	/** The VM-exit interruption-information field. */
239	uint32_t uExitIntInfo;
240	/** The VM-exit instruction-length field. */
241	uint32_t cbExitInstr;
242
243	/** The VM-exit instruction-information field. */
244	VMXEXITINSTRINFO ExitInstrInfo;
245	/** IDT-vectoring information field. */
246	uint32_t uIdtVectoringInfo;
247
248	/** IDT-vectoring error code. */
249	uint32_t uIdtVectoringErrorCode;
250	uint32_t u32Alignment0;
251
252	/** The Guest-linear address. */
253	uint64_t uGuestLinearAddr;
254
255	/** The Guest-physical address. */
256	uint64_t uGuestPhysicalAddr;
257
258	/** The Guest pending-debug exceptions. */
259	uint64_t uGuestPendingDbgXcpts;
260
261	/** The VM-entry interruption-information field. */
262	uint32_t uEntryIntInfo;
263	/** The VM-entry exception error code field. */
264	uint32_t uEntryXcptErrorCode;
265
266	/** The VM-entry instruction length field. */
267	uint32_t cbEntryInstr;
268	} VMXTRANSIENT;
269	AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
270	AssertCompileMemberAlignment(VMXTRANSIENT, fVmcsFieldsRead, 8);
271	AssertCompileMemberAlignment(VMXTRANSIENT, fVectoringPF, 8);
272	AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, 8);
273	AssertCompileMemberAlignment(VMXTRANSIENT, fEFlags, 8);
274	AssertCompileMemberAlignment(VMXTRANSIENT, uExitQual, 8);
275	AssertCompileMemberAlignment(VMXTRANSIENT, pVmcsInfo, 8);
276	AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntInfo, 8);
277	AssertCompileMemberAlignment(VMXTRANSIENT, ExitInstrInfo, 8);
278	AssertCompileMemberAlignment(VMXTRANSIENT, uIdtVectoringErrorCode, 8);
279	AssertCompileMemberAlignment(VMXTRANSIENT, uGuestLinearAddr, 8);
280	AssertCompileMemberAlignment(VMXTRANSIENT, uGuestPhysicalAddr, 8);
281	AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntInfo, 8);
282	AssertCompileMemberAlignment(VMXTRANSIENT, cbEntryInstr, 8);
283	/** Pointer to VMX transient state. */
284	typedef VMXTRANSIENT *PVMXTRANSIENT;
285	/** Pointer to a const VMX transient state. */
286	typedef const VMXTRANSIENT *PCVMXTRANSIENT;
287
288	/**
289	* VMX page allocation information.
290	*/
291	typedef struct
292	{
293	uint32_t fValid; /*< Whether to allocate this page (e.g, based on a CPU feature). /
294	uint32_t uPadding0; /*< Padding to ensure array of these structs are aligned to a multiple of 8. /
295	PRTHCPHYS pHCPhys; /*< Where to store the host-physical address of the allocation. /
296	PRTR0PTR ppVirt; /*< Where to store the host-virtual address of the allocation. /
297	} VMXPAGEALLOCINFO;
298	/** Pointer to VMX page-allocation info. */
299	typedef VMXPAGEALLOCINFO *PVMXPAGEALLOCINFO;
300	/** Pointer to a const VMX page-allocation info. */
301	typedef const VMXPAGEALLOCINFO *PCVMXPAGEALLOCINFO;
302	AssertCompileSizeAlignment(VMXPAGEALLOCINFO, 8);
303
304	/**
305	* Memory operand read or write access.
306	*/
307	typedef enum VMXMEMACCESS
308	{
309	VMXMEMACCESS_READ = 0,
310	VMXMEMACCESS_WRITE = 1
311	} VMXMEMACCESS;
312
313	/**
314	* VMX VM-exit handler.
315	*
316	* @returns Strict VBox status code (i.e. informational status codes too).
317	* @param pVCpu The cross context virtual CPU structure.
318	* @param pVmxTransient The VMX-transient structure.
319	*/
320	#ifndef HMVMX_USE_FUNCTION_TABLE
321	typedef VBOXSTRICTRC FNVMXEXITHANDLER(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient);
322	#else
323	typedef DECLCALLBACKTYPE(VBOXSTRICTRC, FNVMXEXITHANDLER,(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient));
324	/** Pointer to VM-exit handler. */
325	typedef FNVMXEXITHANDLER *PFNVMXEXITHANDLER;
326	#endif
327
328	/**
329	* VMX VM-exit handler, non-strict status code.
330	*
331	* This is generally the same as FNVMXEXITHANDLER, the NSRC bit is just FYI.
332	*
333	* @returns VBox status code, no informational status code returned.
334	* @param pVCpu The cross context virtual CPU structure.
335	* @param pVmxTransient The VMX-transient structure.
336	*
337	* @remarks This is not used on anything returning VERR_EM_INTERPRETER as the
338	* use of that status code will be replaced with VINF_EM_SOMETHING
339	* later when switching over to IEM.
340	*/
341	#ifndef HMVMX_USE_FUNCTION_TABLE
342	typedef int FNVMXEXITHANDLERNSRC(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient);
343	#else
344	typedef FNVMXEXITHANDLER FNVMXEXITHANDLERNSRC;
345	#endif
346
347
348	/*********************************************************************************************************************************
349	* Internal Functions *
350	*********************************************************************************************************************************/
351	#ifndef HMVMX_USE_FUNCTION_TABLE
352	DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient);
353	# define HMVMX_EXIT_DECL DECLINLINE(VBOXSTRICTRC)
354	# define HMVMX_EXIT_NSRC_DECL DECLINLINE(int)
355	#else
356	# define HMVMX_EXIT_DECL static DECLCALLBACK(VBOXSTRICTRC)
357	# define HMVMX_EXIT_NSRC_DECL HMVMX_EXIT_DECL
358	#endif
359	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
360	DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExitNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient);
361	#endif
362
363	static int hmR0VmxImportGuestState(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint64_t fWhat);
364
365	/** @name VM-exit handler prototypes.
366	* @{
367	*/
368	static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmi;
369	static FNVMXEXITHANDLER hmR0VmxExitExtInt;
370	static FNVMXEXITHANDLER hmR0VmxExitTripleFault;
371	static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindow;
372	static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindow;
373	static FNVMXEXITHANDLER hmR0VmxExitTaskSwitch;
374	static FNVMXEXITHANDLER hmR0VmxExitCpuid;
375	static FNVMXEXITHANDLER hmR0VmxExitGetsec;
376	static FNVMXEXITHANDLER hmR0VmxExitHlt;
377	static FNVMXEXITHANDLERNSRC hmR0VmxExitInvd;
378	static FNVMXEXITHANDLER hmR0VmxExitInvlpg;
379	static FNVMXEXITHANDLER hmR0VmxExitRdpmc;
380	static FNVMXEXITHANDLER hmR0VmxExitVmcall;
381	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
382	static FNVMXEXITHANDLER hmR0VmxExitVmclear;
383	static FNVMXEXITHANDLER hmR0VmxExitVmlaunch;
384	static FNVMXEXITHANDLER hmR0VmxExitVmptrld;
385	static FNVMXEXITHANDLER hmR0VmxExitVmptrst;
386	static FNVMXEXITHANDLER hmR0VmxExitVmread;
387	static FNVMXEXITHANDLER hmR0VmxExitVmresume;
388	static FNVMXEXITHANDLER hmR0VmxExitVmwrite;
389	static FNVMXEXITHANDLER hmR0VmxExitVmxoff;
390	static FNVMXEXITHANDLER hmR0VmxExitVmxon;
391	static FNVMXEXITHANDLER hmR0VmxExitInvvpid;
392	#endif
393	static FNVMXEXITHANDLER hmR0VmxExitRdtsc;
394	static FNVMXEXITHANDLER hmR0VmxExitMovCRx;
395	static FNVMXEXITHANDLER hmR0VmxExitMovDRx;
396	static FNVMXEXITHANDLER hmR0VmxExitIoInstr;
397	static FNVMXEXITHANDLER hmR0VmxExitRdmsr;
398	static FNVMXEXITHANDLER hmR0VmxExitWrmsr;
399	static FNVMXEXITHANDLER hmR0VmxExitMwait;
400	static FNVMXEXITHANDLER hmR0VmxExitMtf;
401	static FNVMXEXITHANDLER hmR0VmxExitMonitor;
402	static FNVMXEXITHANDLER hmR0VmxExitPause;
403	static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThreshold;
404	static FNVMXEXITHANDLER hmR0VmxExitApicAccess;
405	static FNVMXEXITHANDLER hmR0VmxExitEptViolation;
406	static FNVMXEXITHANDLER hmR0VmxExitEptMisconfig;
407	static FNVMXEXITHANDLER hmR0VmxExitRdtscp;
408	static FNVMXEXITHANDLER hmR0VmxExitPreemptTimer;
409	static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvd;
410	static FNVMXEXITHANDLER hmR0VmxExitXsetbv;
411	static FNVMXEXITHANDLER hmR0VmxExitInvpcid;
412	static FNVMXEXITHANDLERNSRC hmR0VmxExitSetPendingXcptUD;
413	static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestState;
414	static FNVMXEXITHANDLERNSRC hmR0VmxExitErrUnexpected;
415	/** @} */
416
417	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
418	/** @name Nested-guest VM-exit handler prototypes.
419	* @{
420	*/
421	static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmiNested;
422	static FNVMXEXITHANDLER hmR0VmxExitTripleFaultNested;
423	static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindowNested;
424	static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindowNested;
425	static FNVMXEXITHANDLER hmR0VmxExitTaskSwitchNested;
426	static FNVMXEXITHANDLER hmR0VmxExitHltNested;
427	static FNVMXEXITHANDLER hmR0VmxExitInvlpgNested;
428	static FNVMXEXITHANDLER hmR0VmxExitRdpmcNested;
429	static FNVMXEXITHANDLER hmR0VmxExitVmreadVmwriteNested;
430	static FNVMXEXITHANDLER hmR0VmxExitRdtscNested;
431	static FNVMXEXITHANDLER hmR0VmxExitMovCRxNested;
432	static FNVMXEXITHANDLER hmR0VmxExitMovDRxNested;
433	static FNVMXEXITHANDLER hmR0VmxExitIoInstrNested;
434	static FNVMXEXITHANDLER hmR0VmxExitRdmsrNested;
435	static FNVMXEXITHANDLER hmR0VmxExitWrmsrNested;
436	static FNVMXEXITHANDLER hmR0VmxExitMwaitNested;
437	static FNVMXEXITHANDLER hmR0VmxExitMtfNested;
438	static FNVMXEXITHANDLER hmR0VmxExitMonitorNested;
439	static FNVMXEXITHANDLER hmR0VmxExitPauseNested;
440	static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThresholdNested;
441	static FNVMXEXITHANDLER hmR0VmxExitApicAccessNested;
442	static FNVMXEXITHANDLER hmR0VmxExitApicWriteNested;
443	static FNVMXEXITHANDLER hmR0VmxExitVirtEoiNested;
444	static FNVMXEXITHANDLER hmR0VmxExitRdtscpNested;
445	static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvdNested;
446	static FNVMXEXITHANDLER hmR0VmxExitInvpcidNested;
447	static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestStateNested;
448	static FNVMXEXITHANDLER hmR0VmxExitInstrNested;
449	static FNVMXEXITHANDLER hmR0VmxExitInstrWithInfoNested;
450	/** @} */
451	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
452
453
454	/*********************************************************************************************************************************
455	* Global Variables *
456	*********************************************************************************************************************************/
457	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
458	/**
459	* Array of all VMCS fields.
460	* Any fields added to the VT-x spec. should be added here.
461	*
462	* Currently only used to derive shadow VMCS fields for hardware-assisted execution
463	* of nested-guests.
464	*/
465	static const uint32_t g_aVmcsFields[] =
466	{
467	/* 16-bit control fields. */
468	VMX_VMCS16_VPID,
469	VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR,
470	VMX_VMCS16_EPTP_INDEX,
471
472	/* 16-bit guest-state fields. */
473	VMX_VMCS16_GUEST_ES_SEL,
474	VMX_VMCS16_GUEST_CS_SEL,
475	VMX_VMCS16_GUEST_SS_SEL,
476	VMX_VMCS16_GUEST_DS_SEL,
477	VMX_VMCS16_GUEST_FS_SEL,
478	VMX_VMCS16_GUEST_GS_SEL,
479	VMX_VMCS16_GUEST_LDTR_SEL,
480	VMX_VMCS16_GUEST_TR_SEL,
481	VMX_VMCS16_GUEST_INTR_STATUS,
482	VMX_VMCS16_GUEST_PML_INDEX,
483
484	/* 16-bits host-state fields. */
485	VMX_VMCS16_HOST_ES_SEL,
486	VMX_VMCS16_HOST_CS_SEL,
487	VMX_VMCS16_HOST_SS_SEL,
488	VMX_VMCS16_HOST_DS_SEL,
489	VMX_VMCS16_HOST_FS_SEL,
490	VMX_VMCS16_HOST_GS_SEL,
491	VMX_VMCS16_HOST_TR_SEL,
492
493	/* 64-bit control fields. */
494	VMX_VMCS64_CTRL_IO_BITMAP_A_FULL,
495	VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH,
496	VMX_VMCS64_CTRL_IO_BITMAP_B_FULL,
497	VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH,
498	VMX_VMCS64_CTRL_MSR_BITMAP_FULL,
499	VMX_VMCS64_CTRL_MSR_BITMAP_HIGH,
500	VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL,
501	VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH,
502	VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL,
503	VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH,
504	VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL,
505	VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH,
506	VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL,
507	VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH,
508	VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL,
509	VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH,
510	VMX_VMCS64_CTRL_TSC_OFFSET_FULL,
511	VMX_VMCS64_CTRL_TSC_OFFSET_HIGH,
512	VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL,
513	VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH,
514	VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL,
515	VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH,
516	VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL,
517	VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH,
518	VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL,
519	VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH,
520	VMX_VMCS64_CTRL_EPTP_FULL,
521	VMX_VMCS64_CTRL_EPTP_HIGH,
522	VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL,
523	VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH,
524	VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL,
525	VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH,
526	VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL,
527	VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH,
528	VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL,
529	VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH,
530	VMX_VMCS64_CTRL_EPTP_LIST_FULL,
531	VMX_VMCS64_CTRL_EPTP_LIST_HIGH,
532	VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL,
533	VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH,
534	VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL,
535	VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH,
536	VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL,
537	VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH,
538	VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL,
539	VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH,
540	VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL,
541	VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH,
542	VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL,
543	VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH,
544
545	/* 64-bit read-only data fields. */
546	VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL,
547	VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH,
548
549	/* 64-bit guest-state fields. */
550	VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL,
551	VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH,
552	VMX_VMCS64_GUEST_DEBUGCTL_FULL,
553	VMX_VMCS64_GUEST_DEBUGCTL_HIGH,
554	VMX_VMCS64_GUEST_PAT_FULL,
555	VMX_VMCS64_GUEST_PAT_HIGH,
556	VMX_VMCS64_GUEST_EFER_FULL,
557	VMX_VMCS64_GUEST_EFER_HIGH,
558	VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL,
559	VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH,
560	VMX_VMCS64_GUEST_PDPTE0_FULL,
561	VMX_VMCS64_GUEST_PDPTE0_HIGH,
562	VMX_VMCS64_GUEST_PDPTE1_FULL,
563	VMX_VMCS64_GUEST_PDPTE1_HIGH,
564	VMX_VMCS64_GUEST_PDPTE2_FULL,
565	VMX_VMCS64_GUEST_PDPTE2_HIGH,
566	VMX_VMCS64_GUEST_PDPTE3_FULL,
567	VMX_VMCS64_GUEST_PDPTE3_HIGH,
568	VMX_VMCS64_GUEST_BNDCFGS_FULL,
569	VMX_VMCS64_GUEST_BNDCFGS_HIGH,
570
571	/* 64-bit host-state fields. */
572	VMX_VMCS64_HOST_PAT_FULL,
573	VMX_VMCS64_HOST_PAT_HIGH,
574	VMX_VMCS64_HOST_EFER_FULL,
575	VMX_VMCS64_HOST_EFER_HIGH,
576	VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL,
577	VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH,
578
579	/* 32-bit control fields. */
580	VMX_VMCS32_CTRL_PIN_EXEC,
581	VMX_VMCS32_CTRL_PROC_EXEC,
582	VMX_VMCS32_CTRL_EXCEPTION_BITMAP,
583	VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK,
584	VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH,
585	VMX_VMCS32_CTRL_CR3_TARGET_COUNT,
586	VMX_VMCS32_CTRL_EXIT,
587	VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT,
588	VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT,
589	VMX_VMCS32_CTRL_ENTRY,
590	VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT,
591	VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO,
592	VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE,
593	VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH,
594	VMX_VMCS32_CTRL_TPR_THRESHOLD,
595	VMX_VMCS32_CTRL_PROC_EXEC2,
596	VMX_VMCS32_CTRL_PLE_GAP,
597	VMX_VMCS32_CTRL_PLE_WINDOW,
598
599	/* 32-bits read-only fields. */
600	VMX_VMCS32_RO_VM_INSTR_ERROR,
601	VMX_VMCS32_RO_EXIT_REASON,
602	VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO,
603	VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE,
604	VMX_VMCS32_RO_IDT_VECTORING_INFO,
605	VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE,
606	VMX_VMCS32_RO_EXIT_INSTR_LENGTH,
607	VMX_VMCS32_RO_EXIT_INSTR_INFO,
608
609	/* 32-bit guest-state fields. */
610	VMX_VMCS32_GUEST_ES_LIMIT,
611	VMX_VMCS32_GUEST_CS_LIMIT,
612	VMX_VMCS32_GUEST_SS_LIMIT,
613	VMX_VMCS32_GUEST_DS_LIMIT,
614	VMX_VMCS32_GUEST_FS_LIMIT,
615	VMX_VMCS32_GUEST_GS_LIMIT,
616	VMX_VMCS32_GUEST_LDTR_LIMIT,
617	VMX_VMCS32_GUEST_TR_LIMIT,
618	VMX_VMCS32_GUEST_GDTR_LIMIT,
619	VMX_VMCS32_GUEST_IDTR_LIMIT,
620	VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS,
621	VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS,
622	VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS,
623	VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS,
624	VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS,
625	VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS,
626	VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS,
627	VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS,
628	VMX_VMCS32_GUEST_INT_STATE,
629	VMX_VMCS32_GUEST_ACTIVITY_STATE,
630	VMX_VMCS32_GUEST_SMBASE,
631	VMX_VMCS32_GUEST_SYSENTER_CS,
632	VMX_VMCS32_PREEMPT_TIMER_VALUE,
633
634	/* 32-bit host-state fields. */
635	VMX_VMCS32_HOST_SYSENTER_CS,
636
637	/* Natural-width control fields. */
638	VMX_VMCS_CTRL_CR0_MASK,
639	VMX_VMCS_CTRL_CR4_MASK,
640	VMX_VMCS_CTRL_CR0_READ_SHADOW,
641	VMX_VMCS_CTRL_CR4_READ_SHADOW,
642	VMX_VMCS_CTRL_CR3_TARGET_VAL0,
643	VMX_VMCS_CTRL_CR3_TARGET_VAL1,
644	VMX_VMCS_CTRL_CR3_TARGET_VAL2,
645	VMX_VMCS_CTRL_CR3_TARGET_VAL3,
646
647	/* Natural-width read-only data fields. */
648	VMX_VMCS_RO_EXIT_QUALIFICATION,
649	VMX_VMCS_RO_IO_RCX,
650	VMX_VMCS_RO_IO_RSI,
651	VMX_VMCS_RO_IO_RDI,
652	VMX_VMCS_RO_IO_RIP,
653	VMX_VMCS_RO_GUEST_LINEAR_ADDR,
654
655	/* Natural-width guest-state field */
656	VMX_VMCS_GUEST_CR0,
657	VMX_VMCS_GUEST_CR3,
658	VMX_VMCS_GUEST_CR4,
659	VMX_VMCS_GUEST_ES_BASE,
660	VMX_VMCS_GUEST_CS_BASE,
661	VMX_VMCS_GUEST_SS_BASE,
662	VMX_VMCS_GUEST_DS_BASE,
663	VMX_VMCS_GUEST_FS_BASE,
664	VMX_VMCS_GUEST_GS_BASE,
665	VMX_VMCS_GUEST_LDTR_BASE,
666	VMX_VMCS_GUEST_TR_BASE,
667	VMX_VMCS_GUEST_GDTR_BASE,
668	VMX_VMCS_GUEST_IDTR_BASE,
669	VMX_VMCS_GUEST_DR7,
670	VMX_VMCS_GUEST_RSP,
671	VMX_VMCS_GUEST_RIP,
672	VMX_VMCS_GUEST_RFLAGS,
673	VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS,
674	VMX_VMCS_GUEST_SYSENTER_ESP,
675	VMX_VMCS_GUEST_SYSENTER_EIP,
676
677	/* Natural-width host-state fields */
678	VMX_VMCS_HOST_CR0,
679	VMX_VMCS_HOST_CR3,
680	VMX_VMCS_HOST_CR4,
681	VMX_VMCS_HOST_FS_BASE,
682	VMX_VMCS_HOST_GS_BASE,
683	VMX_VMCS_HOST_TR_BASE,
684	VMX_VMCS_HOST_GDTR_BASE,
685	VMX_VMCS_HOST_IDTR_BASE,
686	VMX_VMCS_HOST_SYSENTER_ESP,
687	VMX_VMCS_HOST_SYSENTER_EIP,
688	VMX_VMCS_HOST_RSP,
689	VMX_VMCS_HOST_RIP
690	};
691	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
692
693	#ifdef VBOX_STRICT
694	static const uint32_t g_aVmcsSegBase[] =
695	{
696	VMX_VMCS_GUEST_ES_BASE,
697	VMX_VMCS_GUEST_CS_BASE,
698	VMX_VMCS_GUEST_SS_BASE,
699	VMX_VMCS_GUEST_DS_BASE,
700	VMX_VMCS_GUEST_FS_BASE,
701	VMX_VMCS_GUEST_GS_BASE
702	};
703	static const uint32_t g_aVmcsSegSel[] =
704	{
705	VMX_VMCS16_GUEST_ES_SEL,
706	VMX_VMCS16_GUEST_CS_SEL,
707	VMX_VMCS16_GUEST_SS_SEL,
708	VMX_VMCS16_GUEST_DS_SEL,
709	VMX_VMCS16_GUEST_FS_SEL,
710	VMX_VMCS16_GUEST_GS_SEL
711	};
712	static const uint32_t g_aVmcsSegLimit[] =
713	{
714	VMX_VMCS32_GUEST_ES_LIMIT,
715	VMX_VMCS32_GUEST_CS_LIMIT,
716	VMX_VMCS32_GUEST_SS_LIMIT,
717	VMX_VMCS32_GUEST_DS_LIMIT,
718	VMX_VMCS32_GUEST_FS_LIMIT,
719	VMX_VMCS32_GUEST_GS_LIMIT
720	};
721	static const uint32_t g_aVmcsSegAttr[] =
722	{
723	VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS,
724	VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS,
725	VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS,
726	VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS,
727	VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS,
728	VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS
729	};
730	AssertCompile(RT_ELEMENTS(g_aVmcsSegSel) == X86_SREG_COUNT);
731	AssertCompile(RT_ELEMENTS(g_aVmcsSegLimit) == X86_SREG_COUNT);
732	AssertCompile(RT_ELEMENTS(g_aVmcsSegBase) == X86_SREG_COUNT);
733	AssertCompile(RT_ELEMENTS(g_aVmcsSegAttr) == X86_SREG_COUNT);
734	#endif /* VBOX_STRICT */
735
736	#ifdef HMVMX_USE_FUNCTION_TABLE
737	/**
738	* VMX_EXIT dispatch table.
739	*/
740	static const struct CLANG11NOTHROWWEIRDNESS { PFNVMXEXITHANDLER pfn; } g_aVMExitHandlers[VMX_EXIT_MAX + 1] =
741	{
742	/* 0 VMX_EXIT_XCPT_OR_NMI */ { hmR0VmxExitXcptOrNmi },
743	/* 1 VMX_EXIT_EXT_INT */ { hmR0VmxExitExtInt },
744	/* 2 VMX_EXIT_TRIPLE_FAULT */ { hmR0VmxExitTripleFault },
745	/* 3 VMX_EXIT_INIT_SIGNAL */ { hmR0VmxExitErrUnexpected },
746	/* 4 VMX_EXIT_SIPI */ { hmR0VmxExitErrUnexpected },
747	/* 5 VMX_EXIT_IO_SMI */ { hmR0VmxExitErrUnexpected },
748	/* 6 VMX_EXIT_SMI */ { hmR0VmxExitErrUnexpected },
749	/* 7 VMX_EXIT_INT_WINDOW */ { hmR0VmxExitIntWindow },
750	/* 8 VMX_EXIT_NMI_WINDOW */ { hmR0VmxExitNmiWindow },
751	/* 9 VMX_EXIT_TASK_SWITCH */ { hmR0VmxExitTaskSwitch },
752	/* 10 VMX_EXIT_CPUID */ { hmR0VmxExitCpuid },
753	/* 11 VMX_EXIT_GETSEC */ { hmR0VmxExitGetsec },
754	/* 12 VMX_EXIT_HLT */ { hmR0VmxExitHlt },
755	/* 13 VMX_EXIT_INVD */ { hmR0VmxExitInvd },
756	/* 14 VMX_EXIT_INVLPG */ { hmR0VmxExitInvlpg },
757	/* 15 VMX_EXIT_RDPMC */ { hmR0VmxExitRdpmc },
758	/* 16 VMX_EXIT_RDTSC */ { hmR0VmxExitRdtsc },
759	/* 17 VMX_EXIT_RSM */ { hmR0VmxExitErrUnexpected },
760	/* 18 VMX_EXIT_VMCALL */ { hmR0VmxExitVmcall },
761	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
762	/* 19 VMX_EXIT_VMCLEAR */ { hmR0VmxExitVmclear },
763	/* 20 VMX_EXIT_VMLAUNCH */ { hmR0VmxExitVmlaunch },
764	/* 21 VMX_EXIT_VMPTRLD */ { hmR0VmxExitVmptrld },
765	/* 22 VMX_EXIT_VMPTRST */ { hmR0VmxExitVmptrst },
766	/* 23 VMX_EXIT_VMREAD */ { hmR0VmxExitVmread },
767	/* 24 VMX_EXIT_VMRESUME */ { hmR0VmxExitVmresume },
768	/* 25 VMX_EXIT_VMWRITE */ { hmR0VmxExitVmwrite },
769	/* 26 VMX_EXIT_VMXOFF */ { hmR0VmxExitVmxoff },
770	/* 27 VMX_EXIT_VMXON */ { hmR0VmxExitVmxon },
771	#else
772	/* 19 VMX_EXIT_VMCLEAR */ { hmR0VmxExitSetPendingXcptUD },
773	/* 20 VMX_EXIT_VMLAUNCH */ { hmR0VmxExitSetPendingXcptUD },
774	/* 21 VMX_EXIT_VMPTRLD */ { hmR0VmxExitSetPendingXcptUD },
775	/* 22 VMX_EXIT_VMPTRST */ { hmR0VmxExitSetPendingXcptUD },
776	/* 23 VMX_EXIT_VMREAD */ { hmR0VmxExitSetPendingXcptUD },
777	/* 24 VMX_EXIT_VMRESUME */ { hmR0VmxExitSetPendingXcptUD },
778	/* 25 VMX_EXIT_VMWRITE */ { hmR0VmxExitSetPendingXcptUD },
779	/* 26 VMX_EXIT_VMXOFF */ { hmR0VmxExitSetPendingXcptUD },
780	/* 27 VMX_EXIT_VMXON */ { hmR0VmxExitSetPendingXcptUD },
781	#endif
782	/* 28 VMX_EXIT_MOV_CRX */ { hmR0VmxExitMovCRx },
783	/* 29 VMX_EXIT_MOV_DRX */ { hmR0VmxExitMovDRx },
784	/* 30 VMX_EXIT_IO_INSTR */ { hmR0VmxExitIoInstr },
785	/* 31 VMX_EXIT_RDMSR */ { hmR0VmxExitRdmsr },
786	/* 32 VMX_EXIT_WRMSR */ { hmR0VmxExitWrmsr },
787	/* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ { hmR0VmxExitErrInvalidGuestState },
788	/* 34 VMX_EXIT_ERR_MSR_LOAD */ { hmR0VmxExitErrUnexpected },
789	/* 35 UNDEFINED */ { hmR0VmxExitErrUnexpected },
790	/* 36 VMX_EXIT_MWAIT */ { hmR0VmxExitMwait },
791	/* 37 VMX_EXIT_MTF */ { hmR0VmxExitMtf },
792	/* 38 UNDEFINED */ { hmR0VmxExitErrUnexpected },
793	/* 39 VMX_EXIT_MONITOR */ { hmR0VmxExitMonitor },
794	/* 40 VMX_EXIT_PAUSE */ { hmR0VmxExitPause },
795	/* 41 VMX_EXIT_ERR_MACHINE_CHECK */ { hmR0VmxExitErrUnexpected },
796	/* 42 UNDEFINED */ { hmR0VmxExitErrUnexpected },
797	/* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ { hmR0VmxExitTprBelowThreshold },
798	/* 44 VMX_EXIT_APIC_ACCESS */ { hmR0VmxExitApicAccess },
799	/* 45 VMX_EXIT_VIRTUALIZED_EOI */ { hmR0VmxExitErrUnexpected },
800	/* 46 VMX_EXIT_GDTR_IDTR_ACCESS */ { hmR0VmxExitErrUnexpected },
801	/* 47 VMX_EXIT_LDTR_TR_ACCESS */ { hmR0VmxExitErrUnexpected },
802	/* 48 VMX_EXIT_EPT_VIOLATION */ { hmR0VmxExitEptViolation },
803	/* 49 VMX_EXIT_EPT_MISCONFIG */ { hmR0VmxExitEptMisconfig },
804	/* 50 VMX_EXIT_INVEPT */ { hmR0VmxExitSetPendingXcptUD },
805	/* 51 VMX_EXIT_RDTSCP */ { hmR0VmxExitRdtscp },
806	/* 52 VMX_EXIT_PREEMPT_TIMER */ { hmR0VmxExitPreemptTimer },
807	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
808	/* 53 VMX_EXIT_INVVPID */ { hmR0VmxExitInvvpid },
809	#else
810	/* 53 VMX_EXIT_INVVPID */ { hmR0VmxExitSetPendingXcptUD },
811	#endif
812	/* 54 VMX_EXIT_WBINVD */ { hmR0VmxExitWbinvd },
813	/* 55 VMX_EXIT_XSETBV */ { hmR0VmxExitXsetbv },
814	/* 56 VMX_EXIT_APIC_WRITE */ { hmR0VmxExitErrUnexpected },
815	/* 57 VMX_EXIT_RDRAND */ { hmR0VmxExitErrUnexpected },
816	/* 58 VMX_EXIT_INVPCID */ { hmR0VmxExitInvpcid },
817	/* 59 VMX_EXIT_VMFUNC */ { hmR0VmxExitErrUnexpected },
818	/* 60 VMX_EXIT_ENCLS */ { hmR0VmxExitErrUnexpected },
819	/* 61 VMX_EXIT_RDSEED */ { hmR0VmxExitErrUnexpected },
820	/* 62 VMX_EXIT_PML_FULL */ { hmR0VmxExitErrUnexpected },
821	/* 63 VMX_EXIT_XSAVES */ { hmR0VmxExitErrUnexpected },
822	/* 64 VMX_EXIT_XRSTORS */ { hmR0VmxExitErrUnexpected },
823	/* 65 UNDEFINED */ { hmR0VmxExitErrUnexpected },
824	/* 66 VMX_EXIT_SPP_EVENT */ { hmR0VmxExitErrUnexpected },
825	/* 67 VMX_EXIT_UMWAIT */ { hmR0VmxExitErrUnexpected },
826	/* 68 VMX_EXIT_TPAUSE */ { hmR0VmxExitErrUnexpected },
827	};
828	#endif /* HMVMX_USE_FUNCTION_TABLE */
829
830	#if defined(VBOX_STRICT) && defined(LOG_ENABLED)
831	static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
832	{
833	/* 0 */ "(Not Used)",
834	/* 1 */ "VMCALL executed in VMX root operation.",
835	/* 2 */ "VMCLEAR with invalid physical address.",
836	/* 3 */ "VMCLEAR with VMXON pointer.",
837	/* 4 */ "VMLAUNCH with non-clear VMCS.",
838	/* 5 */ "VMRESUME with non-launched VMCS.",
839	/* 6 */ "VMRESUME after VMXOFF",
840	/* 7 */ "VM-entry with invalid control fields.",
841	/* 8 */ "VM-entry with invalid host state fields.",
842	/* 9 */ "VMPTRLD with invalid physical address.",
843	/* 10 */ "VMPTRLD with VMXON pointer.",
844	/* 11 */ "VMPTRLD with incorrect revision identifier.",
845	/* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
846	/* 13 */ "VMWRITE to read-only VMCS component.",
847	/* 14 */ "(Not Used)",
848	/* 15 */ "VMXON executed in VMX root operation.",
849	/* 16 */ "VM-entry with invalid executive-VMCS pointer.",
850	/* 17 */ "VM-entry with non-launched executing VMCS.",
851	/* 18 */ "VM-entry with executive-VMCS pointer not VMXON pointer.",
852	/* 19 */ "VMCALL with non-clear VMCS.",
853	/* 20 */ "VMCALL with invalid VM-exit control fields.",
854	/* 21 */ "(Not Used)",
855	/* 22 */ "VMCALL with incorrect MSEG revision identifier.",
856	/* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
857	/* 24 */ "VMCALL with invalid SMM-monitor features.",
858	/* 25 */ "VM-entry with invalid VM-execution control fields in executive VMCS.",
859	/* 26 */ "VM-entry with events blocked by MOV SS.",
860	/* 27 */ "(Not Used)",
861	/* 28 */ "Invalid operand to INVEPT/INVVPID."
862	};
863	#endif /* VBOX_STRICT && LOG_ENABLED */
864
865
866	/**
867	* Checks if the given MSR is part of the lastbranch-from-IP MSR stack.
868	* @returns @c true if it's part of LBR stack, @c false otherwise.
869	*
870	* @param pVM The cross context VM structure.
871	* @param idMsr The MSR.
872	* @param pidxMsr Where to store the index of the MSR in the LBR MSR array.
873	* Optional, can be NULL.
874	*
875	* @remarks Must only be called when LBR is enabled.
876	*/
877	DECL_FORCE_INLINE(bool) hmR0VmxIsLbrBranchFromMsr(PCVMCC pVM, uint32_t idMsr, uint32_t *pidxMsr)
878	{
879	Assert(pVM->hmr0.s.vmx.fLbr);
880	Assert(pVM->hmr0.s.vmx.idLbrFromIpMsrFirst);
881	uint32_t const cLbrStack = pVM->hmr0.s.vmx.idLbrFromIpMsrLast - pVM->hmr0.s.vmx.idLbrFromIpMsrFirst + 1;
882	uint32_t const idxMsr = idMsr - pVM->hmr0.s.vmx.idLbrFromIpMsrFirst;
883	if (idxMsr < cLbrStack)
884	{
885	if (pidxMsr)
886	*pidxMsr = idxMsr;
887	return true;
888	}
889	return false;
890	}
891
892
893	/**
894	* Checks if the given MSR is part of the lastbranch-to-IP MSR stack.
895	* @returns @c true if it's part of LBR stack, @c false otherwise.
896	*
897	* @param pVM The cross context VM structure.
898	* @param idMsr The MSR.
899	* @param pidxMsr Where to store the index of the MSR in the LBR MSR array.
900	* Optional, can be NULL.
901	*
902	* @remarks Must only be called when LBR is enabled and when lastbranch-to-IP MSRs
903	* are supported by the CPU (see hmR0VmxSetupLbrMsrRange).
904	*/
905	DECL_FORCE_INLINE(bool) hmR0VmxIsLbrBranchToMsr(PCVMCC pVM, uint32_t idMsr, uint32_t *pidxMsr)
906	{
907	Assert(pVM->hmr0.s.vmx.fLbr);
908	if (pVM->hmr0.s.vmx.idLbrToIpMsrFirst)
909	{
910	uint32_t const cLbrStack = pVM->hmr0.s.vmx.idLbrToIpMsrLast - pVM->hmr0.s.vmx.idLbrToIpMsrFirst + 1;
911	uint32_t const idxMsr = idMsr - pVM->hmr0.s.vmx.idLbrToIpMsrFirst;
912	if (idxMsr < cLbrStack)
913	{
914	if (pidxMsr)
915	*pidxMsr = idxMsr;
916	return true;
917	}
918	}
919	return false;
920	}
921
922
923	/**
924	* Gets the CR0 guest/host mask.
925	*
926	* These bits typically does not change through the lifetime of a VM. Any bit set in
927	* this mask is owned by the host/hypervisor and would cause a VM-exit when modified
928	* by the guest.
929	*
930	* @returns The CR0 guest/host mask.
931	* @param pVCpu The cross context virtual CPU structure.
932	*/
933	static uint64_t hmR0VmxGetFixedCr0Mask(PCVMCPUCC pVCpu)
934	{
935	/*
936	* Modifications to CR0 bits that VT-x ignores saving/restoring (CD, ET, NW) and
937	* to CR0 bits that we require for shadow paging (PG) by the guest must cause VM-exits.
938	*
939	* Furthermore, modifications to any bits that are reserved/unspecified currently
940	* by the Intel spec. must also cause a VM-exit. This prevents unpredictable behavior
941	* when future CPUs specify and use currently reserved/unspecified bits.
942	*/
943	/** @todo Avoid intercepting CR0.PE with unrestricted guest execution. Fix PGM
944	* enmGuestMode to be in-sync with the current mode. See @bugref{6398}
945	* and @bugref{6944}. */
946	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
947	return ( X86_CR0_PE
948	\| X86_CR0_NE
949	\| (pVM->hmr0.s.fNestedPaging ? 0 : X86_CR0_WP)
950	\| X86_CR0_PG
951	\| VMX_EXIT_HOST_CR0_IGNORE_MASK);
952	}
953
954
955	/**
956	* Gets the CR4 guest/host mask.
957	*
958	* These bits typically does not change through the lifetime of a VM. Any bit set in
959	* this mask is owned by the host/hypervisor and would cause a VM-exit when modified
960	* by the guest.
961	*
962	* @returns The CR4 guest/host mask.
963	* @param pVCpu The cross context virtual CPU structure.
964	*/
965	static uint64_t hmR0VmxGetFixedCr4Mask(PCVMCPUCC pVCpu)
966	{
967	/*
968	* We construct a mask of all CR4 bits that the guest can modify without causing
969	* a VM-exit. Then invert this mask to obtain all CR4 bits that should cause
970	* a VM-exit when the guest attempts to modify them when executing using
971	* hardware-assisted VMX.
972	*
973	* When a feature is not exposed to the guest (and may be present on the host),
974	* we want to intercept guest modifications to the bit so we can emulate proper
975	* behavior (e.g., #GP).
976	*
977	* Furthermore, only modifications to those bits that don't require immediate
978	* emulation is allowed. For e.g., PCIDE is excluded because the behavior
979	* depends on CR3 which might not always be the guest value while executing
980	* using hardware-assisted VMX.
981	*/
982	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
983	bool const fFsGsBase = pVM->cpum.ro.GuestFeatures.fFsGsBase;
984	bool const fXSaveRstor = pVM->cpum.ro.GuestFeatures.fXSaveRstor;
985	bool const fFxSaveRstor = pVM->cpum.ro.GuestFeatures.fFxSaveRstor;
986
987	/*
988	* Paranoia.
989	* Ensure features exposed to the guest are present on the host.
990	*/
991	Assert(!fFsGsBase \|\| pVM->cpum.ro.HostFeatures.fFsGsBase);
992	Assert(!fXSaveRstor \|\| pVM->cpum.ro.HostFeatures.fXSaveRstor);
993	Assert(!fFxSaveRstor \|\| pVM->cpum.ro.HostFeatures.fFxSaveRstor);
994
995	uint64_t const fGstMask = ( X86_CR4_PVI
996	\| X86_CR4_TSD
997	\| X86_CR4_DE
998	\| X86_CR4_MCE
999	\| X86_CR4_PCE
1000	\| X86_CR4_OSXMMEEXCPT
1001	\| (fFsGsBase ? X86_CR4_FSGSBASE : 0)
1002	\| (fXSaveRstor ? X86_CR4_OSXSAVE : 0)
1003	\| (fFxSaveRstor ? X86_CR4_OSFXSR : 0));
1004	return ~fGstMask;
1005	}
1006
1007
1008	/**
1009	* Gets the active (in use) VMCS info. object for the specified VCPU.
1010	*
1011	* This is either the guest or nested-guest VMCS info. and need not necessarily
1012	* pertain to the "current" VMCS (in the VMX definition of the term). For instance,
1013	* if the VM-entry failed due to an invalid-guest state, we may have "cleared" the
1014	* current VMCS while returning to ring-3. However, the VMCS info. object for that
1015	* VMCS would still be active and returned here so that we could dump the VMCS
1016	* fields to ring-3 for diagnostics. This function is thus only used to
1017	* distinguish between the nested-guest or guest VMCS.
1018	*
1019	* @returns The active VMCS information.
1020	* @param pVCpu The cross context virtual CPU structure.
1021	*
1022	* @thread EMT.
1023	* @remarks This function may be called with preemption or interrupts disabled!
1024	*/
1025	DECLINLINE(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPUCC pVCpu)
1026	{
1027	if (!pVCpu->hmr0.s.vmx.fSwitchedToNstGstVmcs)
1028	return &pVCpu->hmr0.s.vmx.VmcsInfo;
1029	return &pVCpu->hmr0.s.vmx.VmcsInfoNstGst;
1030	}
1031
1032
1033	/**
1034	* Returns whether the VM-exit MSR-store area differs from the VM-exit MSR-load
1035	* area.
1036	*
1037	* @returns @c true if it's different, @c false otherwise.
1038	* @param pVmcsInfo The VMCS info. object.
1039	*/
1040	DECL_FORCE_INLINE(bool) hmR0VmxIsSeparateExitMsrStoreAreaVmcs(PCVMXVMCSINFO pVmcsInfo)
1041	{
1042	return RT_BOOL( pVmcsInfo->pvGuestMsrStore != pVmcsInfo->pvGuestMsrLoad
1043	&& pVmcsInfo->pvGuestMsrStore);
1044	}
1045
1046
1047	/**
1048	* Sets the given Processor-based VM-execution controls.
1049	*
1050	* @param pVmxTransient The VMX-transient structure.
1051	* @param uProcCtls The Processor-based VM-execution controls to set.
1052	*/
1053	static void hmR0VmxSetProcCtlsVmcs(PVMXTRANSIENT pVmxTransient, uint32_t uProcCtls)
1054	{
1055	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
1056	if ((pVmcsInfo->u32ProcCtls & uProcCtls) != uProcCtls)
1057	{
1058	pVmcsInfo->u32ProcCtls \|= uProcCtls;
1059	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
1060	AssertRC(rc);
1061	}
1062	}
1063
1064
1065	/**
1066	* Removes the given Processor-based VM-execution controls.
1067	*
1068	* @param pVCpu The cross context virtual CPU structure.
1069	* @param pVmxTransient The VMX-transient structure.
1070	* @param uProcCtls The Processor-based VM-execution controls to remove.
1071	*
1072	* @remarks When executing a nested-guest, this will not remove any of the specified
1073	* controls if the nested hypervisor has set any one of them.
1074	*/
1075	static void hmR0VmxRemoveProcCtlsVmcs(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t uProcCtls)
1076	{
1077	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
1078	if (pVmcsInfo->u32ProcCtls & uProcCtls)
1079	{
1080	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1081	if ( !pVmxTransient->fIsNestedGuest
1082	\|\| !CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, uProcCtls))
1083	#else
1084	NOREF(pVCpu);
1085	if (!pVmxTransient->fIsNestedGuest)
1086	#endif
1087	{
1088	pVmcsInfo->u32ProcCtls &= ~uProcCtls;
1089	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
1090	AssertRC(rc);
1091	}
1092	}
1093	}
1094
1095
1096	/**
1097	* Sets the TSC offset for the current VMCS.
1098	*
1099	* @param uTscOffset The TSC offset to set.
1100	* @param pVmcsInfo The VMCS info. object.
1101	*/
1102	static void hmR0VmxSetTscOffsetVmcs(PVMXVMCSINFO pVmcsInfo, uint64_t uTscOffset)
1103	{
1104	if (pVmcsInfo->u64TscOffset != uTscOffset)
1105	{
1106	int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, uTscOffset);
1107	AssertRC(rc);
1108	pVmcsInfo->u64TscOffset = uTscOffset;
1109	}
1110	}
1111
1112
1113	/**
1114	* Adds one or more exceptions to the exception bitmap and commits it to the current
1115	* VMCS.
1116	*
1117	* @param pVmxTransient The VMX-transient structure.
1118	* @param uXcptMask The exception(s) to add.
1119	*/
1120	static void hmR0VmxAddXcptInterceptMask(PCVMXTRANSIENT pVmxTransient, uint32_t uXcptMask)
1121	{
1122	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
1123	uint32_t uXcptBitmap = pVmcsInfo->u32XcptBitmap;
1124	if ((uXcptBitmap & uXcptMask) != uXcptMask)
1125	{
1126	uXcptBitmap \|= uXcptMask;
1127	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
1128	AssertRC(rc);
1129	pVmcsInfo->u32XcptBitmap = uXcptBitmap;
1130	}
1131	}
1132
1133
1134	/**
1135	* Adds an exception to the exception bitmap and commits it to the current VMCS.
1136	*
1137	* @param pVmxTransient The VMX-transient structure.
1138	* @param uXcpt The exception to add.
1139	*/
1140	static void hmR0VmxAddXcptIntercept(PCVMXTRANSIENT pVmxTransient, uint8_t uXcpt)
1141	{
1142	Assert(uXcpt <= X86_XCPT_LAST);
1143	hmR0VmxAddXcptInterceptMask(pVmxTransient, RT_BIT_32(uXcpt));
1144	}
1145
1146
1147	/**
1148	* Remove one or more exceptions from the exception bitmap and commits it to the
1149	* current VMCS.
1150	*
1151	* This takes care of not removing the exception intercept if a nested-guest
1152	* requires the exception to be intercepted.
1153	*
1154	* @returns VBox status code.
1155	* @param pVCpu The cross context virtual CPU structure.
1156	* @param pVmxTransient The VMX-transient structure.
1157	* @param uXcptMask The exception(s) to remove.
1158	*/
1159	static int hmR0VmxRemoveXcptInterceptMask(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint32_t uXcptMask)
1160	{
1161	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
1162	uint32_t u32XcptBitmap = pVmcsInfo->u32XcptBitmap;
1163	if (u32XcptBitmap & uXcptMask)
1164	{
1165	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1166	if (!pVmxTransient->fIsNestedGuest)
1167	{ /* likely */ }
1168	else
1169	{
1170	PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
1171	uXcptMask &= ~pVmcsNstGst->u32XcptBitmap;
1172	}
1173	#endif
1174	#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
1175	uXcptMask &= ~( RT_BIT(X86_XCPT_BP)
1176	\| RT_BIT(X86_XCPT_DE)
1177	\| RT_BIT(X86_XCPT_NM)
1178	\| RT_BIT(X86_XCPT_TS)
1179	\| RT_BIT(X86_XCPT_UD)
1180	\| RT_BIT(X86_XCPT_NP)
1181	\| RT_BIT(X86_XCPT_SS)
1182	\| RT_BIT(X86_XCPT_GP)
1183	\| RT_BIT(X86_XCPT_PF)
1184	\| RT_BIT(X86_XCPT_MF));
1185	#elif defined(HMVMX_ALWAYS_TRAP_PF)
1186	uXcptMask &= ~RT_BIT(X86_XCPT_PF);
1187	#endif
1188	if (uXcptMask)
1189	{
1190	/* Validate we are not removing any essential exception intercepts. */
1191	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging \|\| !(uXcptMask & RT_BIT(X86_XCPT_PF)));
1192	NOREF(pVCpu);
1193	Assert(!(uXcptMask & RT_BIT(X86_XCPT_DB)));
1194	Assert(!(uXcptMask & RT_BIT(X86_XCPT_AC)));
1195
1196	/* Remove it from the exception bitmap. */
1197	u32XcptBitmap &= ~uXcptMask;
1198
1199	/* Commit and update the cache if necessary. */
1200	if (pVmcsInfo->u32XcptBitmap != u32XcptBitmap)
1201	{
1202	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);
1203	AssertRC(rc);
1204	pVmcsInfo->u32XcptBitmap = u32XcptBitmap;
1205	}
1206	}
1207	}
1208	return VINF_SUCCESS;
1209	}
1210
1211
1212	/**
1213	* Remove an exceptions from the exception bitmap and commits it to the current
1214	* VMCS.
1215	*
1216	* @returns VBox status code.
1217	* @param pVCpu The cross context virtual CPU structure.
1218	* @param pVmxTransient The VMX-transient structure.
1219	* @param uXcpt The exception to remove.
1220	*/
1221	static int hmR0VmxRemoveXcptIntercept(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint8_t uXcpt)
1222	{
1223	return hmR0VmxRemoveXcptInterceptMask(pVCpu, pVmxTransient, RT_BIT(uXcpt));
1224	}
1225
1226
1227	/**
1228	* Loads the VMCS specified by the VMCS info. object.
1229	*
1230	* @returns VBox status code.
1231	* @param pVmcsInfo The VMCS info. object.
1232	*
1233	* @remarks Can be called with interrupts disabled.
1234	*/
1235	static int hmR0VmxLoadVmcs(PVMXVMCSINFO pVmcsInfo)
1236	{
1237	Assert(pVmcsInfo->HCPhysVmcs != 0 && pVmcsInfo->HCPhysVmcs != NIL_RTHCPHYS);
1238	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1239
1240	int rc = VMXLoadVmcs(pVmcsInfo->HCPhysVmcs);
1241	if (RT_SUCCESS(rc))
1242	pVmcsInfo->fVmcsState \|= VMX_V_VMCS_LAUNCH_STATE_CURRENT;
1243	return rc;
1244	}
1245
1246
1247	/**
1248	* Clears the VMCS specified by the VMCS info. object.
1249	*
1250	* @returns VBox status code.
1251	* @param pVmcsInfo The VMCS info. object.
1252	*
1253	* @remarks Can be called with interrupts disabled.
1254	*/
1255	static int hmR0VmxClearVmcs(PVMXVMCSINFO pVmcsInfo)
1256	{
1257	Assert(pVmcsInfo->HCPhysVmcs != 0 && pVmcsInfo->HCPhysVmcs != NIL_RTHCPHYS);
1258	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1259
1260	int rc = VMXClearVmcs(pVmcsInfo->HCPhysVmcs);
1261	if (RT_SUCCESS(rc))
1262	pVmcsInfo->fVmcsState = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
1263	return rc;
1264	}
1265
1266
1267	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1268	/**
1269	* Loads the shadow VMCS specified by the VMCS info. object.
1270	*
1271	* @returns VBox status code.
1272	* @param pVmcsInfo The VMCS info. object.
1273	*
1274	* @remarks Can be called with interrupts disabled.
1275	*/
1276	static int hmR0VmxLoadShadowVmcs(PVMXVMCSINFO pVmcsInfo)
1277	{
1278	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1279	Assert(pVmcsInfo->HCPhysShadowVmcs != 0 && pVmcsInfo->HCPhysShadowVmcs != NIL_RTHCPHYS);
1280
1281	int rc = VMXLoadVmcs(pVmcsInfo->HCPhysShadowVmcs);
1282	if (RT_SUCCESS(rc))
1283	pVmcsInfo->fShadowVmcsState \|= VMX_V_VMCS_LAUNCH_STATE_CURRENT;
1284	return rc;
1285	}
1286
1287
1288	/**
1289	* Clears the shadow VMCS specified by the VMCS info. object.
1290	*
1291	* @returns VBox status code.
1292	* @param pVmcsInfo The VMCS info. object.
1293	*
1294	* @remarks Can be called with interrupts disabled.
1295	*/
1296	static int hmR0VmxClearShadowVmcs(PVMXVMCSINFO pVmcsInfo)
1297	{
1298	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1299	Assert(pVmcsInfo->HCPhysShadowVmcs != 0 && pVmcsInfo->HCPhysShadowVmcs != NIL_RTHCPHYS);
1300
1301	int rc = VMXClearVmcs(pVmcsInfo->HCPhysShadowVmcs);
1302	if (RT_SUCCESS(rc))
1303	pVmcsInfo->fShadowVmcsState = VMX_V_VMCS_LAUNCH_STATE_CLEAR;
1304	return rc;
1305	}
1306
1307
1308	/**
1309	* Switches from and to the specified VMCSes.
1310	*
1311	* @returns VBox status code.
1312	* @param pVmcsInfoFrom The VMCS info. object we are switching from.
1313	* @param pVmcsInfoTo The VMCS info. object we are switching to.
1314	*
1315	* @remarks Called with interrupts disabled.
1316	*/
1317	static int hmR0VmxSwitchVmcs(PVMXVMCSINFO pVmcsInfoFrom, PVMXVMCSINFO pVmcsInfoTo)
1318	{
1319	/*
1320	* Clear the VMCS we are switching out if it has not already been cleared.
1321	* This will sync any CPU internal data back to the VMCS.
1322	*/
1323	if (pVmcsInfoFrom->fVmcsState != VMX_V_VMCS_LAUNCH_STATE_CLEAR)
1324	{
1325	int rc = hmR0VmxClearVmcs(pVmcsInfoFrom);
1326	if (RT_SUCCESS(rc))
1327	{
1328	/*
1329	* The shadow VMCS, if any, would not be active at this point since we
1330	* would have cleared it while importing the virtual hardware-virtualization
1331	* state as part the VMLAUNCH/VMRESUME VM-exit. Hence, there's no need to
1332	* clear the shadow VMCS here, just assert for safety.
1333	*/
1334	Assert(!pVmcsInfoFrom->pvShadowVmcs \|\| pVmcsInfoFrom->fShadowVmcsState == VMX_V_VMCS_LAUNCH_STATE_CLEAR);
1335	}
1336	else
1337	return rc;
1338	}
1339
1340	/*
1341	* Clear the VMCS we are switching to if it has not already been cleared.
1342	* This will initialize the VMCS launch state to "clear" required for loading it.
1343	*
1344	* See Intel spec. 31.6 "Preparation And Launching A Virtual Machine".
1345	*/
1346	if (pVmcsInfoTo->fVmcsState != VMX_V_VMCS_LAUNCH_STATE_CLEAR)
1347	{
1348	int rc = hmR0VmxClearVmcs(pVmcsInfoTo);
1349	if (RT_SUCCESS(rc))
1350	{ /* likely */ }
1351	else
1352	return rc;
1353	}
1354
1355	/*
1356	* Finally, load the VMCS we are switching to.
1357	*/
1358	return hmR0VmxLoadVmcs(pVmcsInfoTo);
1359	}
1360
1361
1362	/**
1363	* Switches between the guest VMCS and the nested-guest VMCS as specified by the
1364	* caller.
1365	*
1366	* @returns VBox status code.
1367	* @param pVCpu The cross context virtual CPU structure.
1368	* @param fSwitchToNstGstVmcs Whether to switch to the nested-guest VMCS (pass
1369	* true) or guest VMCS (pass false).
1370	*/
1371	static int hmR0VmxSwitchToGstOrNstGstVmcs(PVMCPUCC pVCpu, bool fSwitchToNstGstVmcs)
1372	{
1373	/* Ensure we have synced everything from the guest-CPU context to the VMCS before switching. */
1374	HMVMX_CPUMCTX_ASSERT(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
1375
1376	PVMXVMCSINFO pVmcsInfoFrom;
1377	PVMXVMCSINFO pVmcsInfoTo;
1378	if (fSwitchToNstGstVmcs)
1379	{
1380	pVmcsInfoFrom = &pVCpu->hmr0.s.vmx.VmcsInfo;
1381	pVmcsInfoTo = &pVCpu->hmr0.s.vmx.VmcsInfoNstGst;
1382	}
1383	else
1384	{
1385	pVmcsInfoFrom = &pVCpu->hmr0.s.vmx.VmcsInfoNstGst;
1386	pVmcsInfoTo = &pVCpu->hmr0.s.vmx.VmcsInfo;
1387	}
1388
1389	/*
1390	* Disable interrupts to prevent being preempted while we switch the current VMCS as the
1391	* preemption hook code path acquires the current VMCS.
1392	*/
1393	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
1394
1395	int rc = hmR0VmxSwitchVmcs(pVmcsInfoFrom, pVmcsInfoTo);
1396	if (RT_SUCCESS(rc))
1397	{
1398	pVCpu->hmr0.s.vmx.fSwitchedToNstGstVmcs = fSwitchToNstGstVmcs;
1399	pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3 = fSwitchToNstGstVmcs;
1400
1401	/*
1402	* If we are switching to a VMCS that was executed on a different host CPU or was
1403	* never executed before, flag that we need to export the host state before executing
1404	* guest/nested-guest code using hardware-assisted VMX.
1405	*
1406	* This could probably be done in a preemptible context since the preemption hook
1407	* will flag the necessary change in host context. However, since preemption is
1408	* already disabled and to avoid making assumptions about host specific code in
1409	* RTMpCpuId when called with preemption enabled, we'll do this while preemption is
1410	* disabled.
1411	*/
1412	if (pVmcsInfoTo->idHostCpuState == RTMpCpuId())
1413	{ /* likely */ }
1414	else
1415	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE);
1416
1417	ASMSetFlags(fEFlags);
1418
1419	/*
1420	* We use a different VM-exit MSR-store areas for the guest and nested-guest. Hence,
1421	* flag that we need to update the host MSR values there. Even if we decide in the
1422	* future to share the VM-exit MSR-store area page between the guest and nested-guest,
1423	* if its content differs, we would have to update the host MSRs anyway.
1424	*/
1425	pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs = false;
1426	}
1427	else
1428	ASMSetFlags(fEFlags);
1429	return rc;
1430	}
1431	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
1432
1433
1434	/**
1435	* Updates the VM's last error record.
1436	*
1437	* If there was a VMX instruction error, reads the error data from the VMCS and
1438	* updates VCPU's last error record as well.
1439	*
1440	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1441	* Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
1442	* VERR_VMX_INVALID_VMCS_FIELD.
1443	* @param rc The error code.
1444	*/
1445	static void hmR0VmxUpdateErrorRecord(PVMCPUCC pVCpu, int rc)
1446	{
1447	if ( rc == VERR_VMX_INVALID_VMCS_FIELD
1448	\|\| rc == VERR_VMX_UNABLE_TO_START_VM)
1449	{
1450	AssertPtrReturnVoid(pVCpu);
1451	VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
1452	}
1453	pVCpu->CTX_SUFF(pVM)->hm.s.ForR3.rcInit = rc;
1454	}
1455
1456
1457	#ifdef VBOX_STRICT
1458	/**
1459	* Reads the VM-entry interruption-information field from the VMCS into the VMX
1460	* transient structure.
1461	*
1462	* @param pVmxTransient The VMX-transient structure.
1463	*/
1464	DECLINLINE(void) hmR0VmxReadEntryIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
1465	{
1466	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);
1467	AssertRC(rc);
1468	}
1469
1470
1471	/**
1472	* Reads the VM-entry exception error code field from the VMCS into
1473	* the VMX transient structure.
1474	*
1475	* @param pVmxTransient The VMX-transient structure.
1476	*/
1477	DECLINLINE(void) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
1478	{
1479	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
1480	AssertRC(rc);
1481	}
1482
1483
1484	/**
1485	* Reads the VM-entry exception error code field from the VMCS into
1486	* the VMX transient structure.
1487	*
1488	* @param pVmxTransient The VMX-transient structure.
1489	*/
1490	DECLINLINE(void) hmR0VmxReadEntryInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
1491	{
1492	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
1493	AssertRC(rc);
1494	}
1495	#endif /* VBOX_STRICT */
1496
1497
1498	/**
1499	* Reads the VM-exit interruption-information field from the VMCS into the VMX
1500	* transient structure.
1501	*
1502	* @param pVmxTransient The VMX-transient structure.
1503	*/
1504	DECLINLINE(void) hmR0VmxReadExitIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
1505	{
1506	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_INFO))
1507	{
1508	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
1509	AssertRC(rc);
1510	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_EXIT_INTERRUPTION_INFO;
1511	}
1512	}
1513
1514
1515	/**
1516	* Reads the VM-exit interruption error code from the VMCS into the VMX
1517	* transient structure.
1518	*
1519	* @param pVmxTransient The VMX-transient structure.
1520	*/
1521	DECLINLINE(void) hmR0VmxReadExitIntErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
1522	{
1523	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE))
1524	{
1525	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
1526	AssertRC(rc);
1527	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE;
1528	}
1529	}
1530
1531
1532	/**
1533	* Reads the VM-exit instruction length field from the VMCS into the VMX
1534	* transient structure.
1535	*
1536	* @param pVmxTransient The VMX-transient structure.
1537	*/
1538	DECLINLINE(void) hmR0VmxReadExitInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
1539	{
1540	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_LEN))
1541	{
1542	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbExitInstr);
1543	AssertRC(rc);
1544	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_EXIT_INSTR_LEN;
1545	}
1546	}
1547
1548
1549	/**
1550	* Reads the VM-exit instruction-information field from the VMCS into
1551	* the VMX transient structure.
1552	*
1553	* @param pVmxTransient The VMX-transient structure.
1554	*/
1555	DECLINLINE(void) hmR0VmxReadExitInstrInfoVmcs(PVMXTRANSIENT pVmxTransient)
1556	{
1557	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_INFO))
1558	{
1559	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
1560	AssertRC(rc);
1561	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_EXIT_INSTR_INFO;
1562	}
1563	}
1564
1565
1566	/**
1567	* Reads the Exit Qualification from the VMCS into the VMX transient structure.
1568	*
1569	* @param pVmxTransient The VMX-transient structure.
1570	*/
1571	DECLINLINE(void) hmR0VmxReadExitQualVmcs(PVMXTRANSIENT pVmxTransient)
1572	{
1573	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_QUALIFICATION))
1574	{
1575	int rc = VMXReadVmcsNw(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual);
1576	AssertRC(rc);
1577	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_EXIT_QUALIFICATION;
1578	}
1579	}
1580
1581
1582	/**
1583	* Reads the Guest-linear address from the VMCS into the VMX transient structure.
1584	*
1585	* @param pVmxTransient The VMX-transient structure.
1586	*/
1587	DECLINLINE(void) hmR0VmxReadGuestLinearAddrVmcs(PVMXTRANSIENT pVmxTransient)
1588	{
1589	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_LINEAR_ADDR))
1590	{
1591	int rc = VMXReadVmcsNw(VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr);
1592	AssertRC(rc);
1593	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_GUEST_LINEAR_ADDR;
1594	}
1595	}
1596
1597
1598	/**
1599	* Reads the Guest-physical address from the VMCS into the VMX transient structure.
1600	*
1601	* @param pVmxTransient The VMX-transient structure.
1602	*/
1603	DECLINLINE(void) hmR0VmxReadGuestPhysicalAddrVmcs(PVMXTRANSIENT pVmxTransient)
1604	{
1605	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_PHYSICAL_ADDR))
1606	{
1607	int rc = VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &pVmxTransient->uGuestPhysicalAddr);
1608	AssertRC(rc);
1609	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_GUEST_PHYSICAL_ADDR;
1610	}
1611	}
1612
1613	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1614	/**
1615	* Reads the Guest pending-debug exceptions from the VMCS into the VMX transient
1616	* structure.
1617	*
1618	* @param pVmxTransient The VMX-transient structure.
1619	*/
1620	DECLINLINE(void) hmR0VmxReadGuestPendingDbgXctps(PVMXTRANSIENT pVmxTransient)
1621	{
1622	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_PENDING_DBG_XCPTS))
1623	{
1624	int rc = VMXReadVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &pVmxTransient->uGuestPendingDbgXcpts);
1625	AssertRC(rc);
1626	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_GUEST_PENDING_DBG_XCPTS;
1627	}
1628	}
1629	#endif
1630
1631	/**
1632	* Reads the IDT-vectoring information field from the VMCS into the VMX
1633	* transient structure.
1634	*
1635	* @param pVmxTransient The VMX-transient structure.
1636	*
1637	* @remarks No-long-jump zone!!!
1638	*/
1639	DECLINLINE(void) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
1640	{
1641	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_INFO))
1642	{
1643	int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo);
1644	AssertRC(rc);
1645	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_IDT_VECTORING_INFO;
1646	}
1647	}
1648
1649
1650	/**
1651	* Reads the IDT-vectoring error code from the VMCS into the VMX
1652	* transient structure.
1653	*
1654	* @param pVmxTransient The VMX-transient structure.
1655	*/
1656	DECLINLINE(void) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
1657	{
1658	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_ERROR_CODE))
1659	{
1660	int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
1661	AssertRC(rc);
1662	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_IDT_VECTORING_ERROR_CODE;
1663	}
1664	}
1665
1666	#ifdef HMVMX_ALWAYS_SAVE_RO_GUEST_STATE
1667	/**
1668	* Reads all relevant read-only VMCS fields into the VMX transient structure.
1669	*
1670	* @param pVmxTransient The VMX-transient structure.
1671	*/
1672	static void hmR0VmxReadAllRoFieldsVmcs(PVMXTRANSIENT pVmxTransient)
1673	{
1674	int rc = VMXReadVmcsNw(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual);
1675	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbExitInstr);
1676	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
1677	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo);
1678	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
1679	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
1680	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
1681	rc \|= VMXReadVmcsNw(VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr);
1682	rc \|= VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &pVmxTransient->uGuestPhysicalAddr);
1683	AssertRC(rc);
1684	pVmxTransient->fVmcsFieldsRead \|= HMVMX_READ_EXIT_QUALIFICATION
1685	\| HMVMX_READ_EXIT_INSTR_LEN
1686	\| HMVMX_READ_EXIT_INSTR_INFO
1687	\| HMVMX_READ_IDT_VECTORING_INFO
1688	\| HMVMX_READ_IDT_VECTORING_ERROR_CODE
1689	\| HMVMX_READ_EXIT_INTERRUPTION_INFO
1690	\| HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE
1691	\| HMVMX_READ_GUEST_LINEAR_ADDR
1692	\| HMVMX_READ_GUEST_PHYSICAL_ADDR;
1693	}
1694	#endif
1695
1696	/**
1697	* Enters VMX root mode operation on the current CPU.
1698	*
1699	* @returns VBox status code.
1700	* @param pHostCpu The HM physical-CPU structure.
1701	* @param pVM The cross context VM structure. Can be
1702	* NULL, after a resume.
1703	* @param HCPhysCpuPage Physical address of the VMXON region.
1704	* @param pvCpuPage Pointer to the VMXON region.
1705	*/
1706	static int hmR0VmxEnterRootMode(PHMPHYSCPU pHostCpu, PVMCC pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
1707	{
1708	Assert(pHostCpu);
1709	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
1710	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
1711	Assert(pvCpuPage);
1712	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1713
1714	if (pVM)
1715	{
1716	/* Write the VMCS revision identifier to the VMXON region. */
1717	(uint32_t )pvCpuPage = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID);
1718	}
1719
1720	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
1721	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
1722
1723	/* Enable the VMX bit in CR4 if necessary. */
1724	RTCCUINTREG const uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
1725
1726	/* Record whether VMXE was already prior to us enabling it above. */
1727	pHostCpu->fVmxeAlreadyEnabled = RT_BOOL(uOldCr4 & X86_CR4_VMXE);
1728
1729	/* Enter VMX root mode. */
1730	int rc = VMXEnable(HCPhysCpuPage);
1731	if (RT_FAILURE(rc))
1732	{
1733	/* Restore CR4.VMXE if it was not set prior to our attempt to set it above. */
1734	if (!pHostCpu->fVmxeAlreadyEnabled)
1735	SUPR0ChangeCR4(0 /* fOrMask */, ~(uint64_t)X86_CR4_VMXE);
1736
1737	if (pVM)
1738	pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
1739	}
1740
1741	/* Restore interrupts. */
1742	ASMSetFlags(fEFlags);
1743	return rc;
1744	}
1745
1746
1747	/**
1748	* Exits VMX root mode operation on the current CPU.
1749	*
1750	* @returns VBox status code.
1751	* @param pHostCpu The HM physical-CPU structure.
1752	*/
1753	static int hmR0VmxLeaveRootMode(PHMPHYSCPU pHostCpu)
1754	{
1755	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1756
1757	/* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
1758	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
1759
1760	/* If we're for some reason not in VMX root mode, then don't leave it. */
1761	RTCCUINTREG const uHostCr4 = ASMGetCR4();
1762
1763	int rc;
1764	if (uHostCr4 & X86_CR4_VMXE)
1765	{
1766	/* Exit VMX root mode and clear the VMX bit in CR4. */
1767	VMXDisable();
1768
1769	/* Clear CR4.VMXE only if it was clear prior to use setting it. */
1770	if (!pHostCpu->fVmxeAlreadyEnabled)
1771	SUPR0ChangeCR4(0 /* fOrMask */, ~(uint64_t)X86_CR4_VMXE);
1772
1773	rc = VINF_SUCCESS;
1774	}
1775	else
1776	rc = VERR_VMX_NOT_IN_VMX_ROOT_MODE;
1777
1778	/* Restore interrupts. */
1779	ASMSetFlags(fEFlags);
1780	return rc;
1781	}
1782
1783
1784	/**
1785	* Allocates pages specified as specified by an array of VMX page allocation info
1786	* objects.
1787	*
1788	* The pages contents are zero'd after allocation.
1789	*
1790	* @returns VBox status code.
1791	* @param phMemObj Where to return the handle to the allocation.
1792	* @param paAllocInfo The pointer to the first element of the VMX
1793	* page-allocation info object array.
1794	* @param cEntries The number of elements in the @a paAllocInfo array.
1795	*/
1796	static int hmR0VmxPagesAllocZ(PRTR0MEMOBJ phMemObj, PVMXPAGEALLOCINFO paAllocInfo, uint32_t cEntries)
1797	{
1798	*phMemObj = NIL_RTR0MEMOBJ;
1799
1800	/* Figure out how many pages to allocate. */
1801	uint32_t cPages = 0;
1802	for (uint32_t iPage = 0; iPage < cEntries; iPage++)
1803	cPages += !!paAllocInfo[iPage].fValid;
1804
1805	/* Allocate the pages. */
1806	if (cPages)
1807	{
1808	size_t const cbPages = cPages << PAGE_SHIFT;
1809	int rc = RTR0MemObjAllocPage(phMemObj, cbPages, false /* fExecutable */);
1810	if (RT_FAILURE(rc))
1811	return rc;
1812
1813	/* Zero the contents and assign each page to the corresponding VMX page-allocation entry. */
1814	void pvFirstPage = RTR0MemObjAddress(phMemObj);
1815	RT_BZERO(pvFirstPage, cbPages);
1816
1817	uint32_t iPage = 0;
1818	for (uint32_t i = 0; i < cEntries; i++)
1819	if (paAllocInfo[i].fValid)
1820	{
1821	RTHCPHYS const HCPhysPage = RTR0MemObjGetPagePhysAddr(*phMemObj, iPage);
1822	void pvPage = (void )((uintptr_t)pvFirstPage + (iPage << X86_PAGE_4K_SHIFT));
1823	Assert(HCPhysPage && HCPhysPage != NIL_RTHCPHYS);
1824	AssertPtr(pvPage);
1825
1826	Assert(paAllocInfo[iPage].pHCPhys);
1827	Assert(paAllocInfo[iPage].ppVirt);
1828	*paAllocInfo[iPage].pHCPhys = HCPhysPage;
1829	*paAllocInfo[iPage].ppVirt = pvPage;
1830
1831	/* Move to next page. */
1832	++iPage;
1833	}
1834
1835	/* Make sure all valid (requested) pages have been assigned. */
1836	Assert(iPage == cPages);
1837	}
1838	return VINF_SUCCESS;
1839	}
1840
1841
1842	/**
1843	* Frees pages allocated using hmR0VmxPagesAllocZ.
1844	*
1845	* @param phMemObj Pointer to the memory object handle. Will be set to
1846	* NIL.
1847	*/
1848	DECL_FORCE_INLINE(void) hmR0VmxPagesFree(PRTR0MEMOBJ phMemObj)
1849	{
1850	/* We can cleanup wholesale since it's all one allocation. */
1851	if (*phMemObj != NIL_RTR0MEMOBJ)
1852	{
1853	RTR0MemObjFree(phMemObj, true / fFreeMappings */);
1854	*phMemObj = NIL_RTR0MEMOBJ;
1855	}
1856	}
1857
1858
1859	/**
1860	* Initializes a VMCS info. object.
1861	*
1862	* @param pVmcsInfo The VMCS info. object.
1863	* @param pVmcsInfoShared The VMCS info. object shared with ring-3.
1864	*/
1865	static void hmR0VmxVmcsInfoInit(PVMXVMCSINFO pVmcsInfo, PVMXVMCSINFOSHARED pVmcsInfoShared)
1866	{
1867	RT_ZERO(*pVmcsInfo);
1868	RT_ZERO(*pVmcsInfoShared);
1869
1870	pVmcsInfo->pShared = pVmcsInfoShared;
1871	Assert(pVmcsInfo->hMemObj == NIL_RTR0MEMOBJ);
1872	pVmcsInfo->HCPhysVmcs = NIL_RTHCPHYS;
1873	pVmcsInfo->HCPhysShadowVmcs = NIL_RTHCPHYS;
1874	pVmcsInfo->HCPhysMsrBitmap = NIL_RTHCPHYS;
1875	pVmcsInfo->HCPhysGuestMsrLoad = NIL_RTHCPHYS;
1876	pVmcsInfo->HCPhysGuestMsrStore = NIL_RTHCPHYS;
1877	pVmcsInfo->HCPhysHostMsrLoad = NIL_RTHCPHYS;
1878	pVmcsInfo->HCPhysVirtApic = NIL_RTHCPHYS;
1879	pVmcsInfo->HCPhysEPTP = NIL_RTHCPHYS;
1880	pVmcsInfo->u64VmcsLinkPtr = NIL_RTHCPHYS;
1881	pVmcsInfo->idHostCpuState = NIL_RTCPUID;
1882	pVmcsInfo->idHostCpuExec = NIL_RTCPUID;
1883	}
1884
1885
1886	/**
1887	* Frees the VT-x structures for a VMCS info. object.
1888	*
1889	* @param pVmcsInfo The VMCS info. object.
1890	* @param pVmcsInfoShared The VMCS info. object shared with ring-3.
1891	*/
1892	static void hmR0VmxVmcsInfoFree(PVMXVMCSINFO pVmcsInfo, PVMXVMCSINFOSHARED pVmcsInfoShared)
1893	{
1894	hmR0VmxPagesFree(&pVmcsInfo->hMemObj);
1895	hmR0VmxVmcsInfoInit(pVmcsInfo, pVmcsInfoShared);
1896	}
1897
1898
1899	/**
1900	* Allocates the VT-x structures for a VMCS info. object.
1901	*
1902	* @returns VBox status code.
1903	* @param pVCpu The cross context virtual CPU structure.
1904	* @param pVmcsInfo The VMCS info. object.
1905	* @param fIsNstGstVmcs Whether this is a nested-guest VMCS.
1906	*
1907	* @remarks The caller is expected to take care of any and all allocation failures.
1908	* This function will not perform any cleanup for failures half-way
1909	* through.
1910	*/
1911	static int hmR0VmxAllocVmcsInfo(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, bool fIsNstGstVmcs)
1912	{
1913	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1914
1915	bool const fMsrBitmaps = RT_BOOL(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1916	bool const fShadowVmcs = !fIsNstGstVmcs ? pVM->hmr0.s.vmx.fUseVmcsShadowing : pVM->cpum.ro.GuestFeatures.fVmxVmcsShadowing;
1917	Assert(!pVM->cpum.ro.GuestFeatures.fVmxVmcsShadowing); /* VMCS shadowing is not yet exposed to the guest. */
1918	VMXPAGEALLOCINFO aAllocInfo[] =
1919	{
1920	{ true, 0 /* Unused */, &pVmcsInfo->HCPhysVmcs, &pVmcsInfo->pvVmcs },
1921	{ true, 0 /* Unused */, &pVmcsInfo->HCPhysGuestMsrLoad, &pVmcsInfo->pvGuestMsrLoad },
1922	{ true, 0 /* Unused */, &pVmcsInfo->HCPhysHostMsrLoad, &pVmcsInfo->pvHostMsrLoad },
1923	{ fMsrBitmaps, 0 /* Unused */, &pVmcsInfo->HCPhysMsrBitmap, &pVmcsInfo->pvMsrBitmap },
1924	{ fShadowVmcs, 0 /* Unused */, &pVmcsInfo->HCPhysShadowVmcs, &pVmcsInfo->pvShadowVmcs },
1925	};
1926
1927	int rc = hmR0VmxPagesAllocZ(&pVmcsInfo->hMemObj, &aAllocInfo[0], RT_ELEMENTS(aAllocInfo));
1928	if (RT_FAILURE(rc))
1929	return rc;
1930
1931	/*
1932	* We use the same page for VM-entry MSR-load and VM-exit MSR store areas.
1933	* Because they contain a symmetric list of guest MSRs to load on VM-entry and store on VM-exit.
1934	*/
1935	AssertCompile(RT_ELEMENTS(aAllocInfo) > 0);
1936	Assert(pVmcsInfo->HCPhysGuestMsrLoad != NIL_RTHCPHYS);
1937	pVmcsInfo->pvGuestMsrStore = pVmcsInfo->pvGuestMsrLoad;
1938	pVmcsInfo->HCPhysGuestMsrStore = pVmcsInfo->HCPhysGuestMsrLoad;
1939
1940	/*
1941	* Get the virtual-APIC page rather than allocating them again.
1942	*/
1943	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW)
1944	{
1945	if (!fIsNstGstVmcs)
1946	{
1947	if (PDMHasApic(pVM))
1948	{
1949	rc = APICGetApicPageForCpu(pVCpu, &pVmcsInfo->HCPhysVirtApic, (PRTR0PTR)&pVmcsInfo->pbVirtApic, NULL /pR3Ptr/);
1950	if (RT_FAILURE(rc))
1951	return rc;
1952	Assert(pVmcsInfo->pbVirtApic);
1953	Assert(pVmcsInfo->HCPhysVirtApic && pVmcsInfo->HCPhysVirtApic != NIL_RTHCPHYS);
1954	}
1955	}
1956	else
1957	{
1958	pVmcsInfo->pbVirtApic = (uint8_t *)CPUMGetGuestVmxVirtApicPage(&pVCpu->cpum.GstCtx, &pVmcsInfo->HCPhysVirtApic);
1959	Assert(pVmcsInfo->pbVirtApic);
1960	Assert(pVmcsInfo->HCPhysVirtApic && pVmcsInfo->HCPhysVirtApic != NIL_RTHCPHYS);
1961	}
1962	}
1963
1964	return VINF_SUCCESS;
1965	}
1966
1967
1968	/**
1969	* Free all VT-x structures for the VM.
1970	*
1971	* @returns IPRT status code.
1972	* @param pVM The cross context VM structure.
1973	*/
1974	static void hmR0VmxStructsFree(PVMCC pVM)
1975	{
1976	hmR0VmxPagesFree(&pVM->hmr0.s.vmx.hMemObj);
1977	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1978	if (pVM->hmr0.s.vmx.fUseVmcsShadowing)
1979	{
1980	RTMemFree(pVM->hmr0.s.vmx.paShadowVmcsFields);
1981	pVM->hmr0.s.vmx.paShadowVmcsFields = NULL;
1982	RTMemFree(pVM->hmr0.s.vmx.paShadowVmcsRoFields);
1983	pVM->hmr0.s.vmx.paShadowVmcsRoFields = NULL;
1984	}
1985	#endif
1986
1987	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1988	{
1989	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1990	hmR0VmxVmcsInfoFree(&pVCpu->hmr0.s.vmx.VmcsInfo, &pVCpu->hm.s.vmx.VmcsInfo);
1991	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1992	if (pVM->cpum.ro.GuestFeatures.fVmx)
1993	hmR0VmxVmcsInfoFree(&pVCpu->hmr0.s.vmx.VmcsInfoNstGst, &pVCpu->hm.s.vmx.VmcsInfoNstGst);
1994	#endif
1995	}
1996	}
1997
1998
1999	/**
2000	* Allocate all VT-x structures for the VM.
2001	*
2002	* @returns IPRT status code.
2003	* @param pVM The cross context VM structure.
2004	*
2005	* @remarks This functions will cleanup on memory allocation failures.
2006	*/
2007	static int hmR0VmxStructsAlloc(PVMCC pVM)
2008	{
2009	/*
2010	* Sanity check the VMCS size reported by the CPU as we assume 4KB allocations.
2011	* The VMCS size cannot be more than 4096 bytes.
2012	*
2013	* See Intel spec. Appendix A.1 "Basic VMX Information".
2014	*/
2015	uint32_t const cbVmcs = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_SIZE);
2016	if (cbVmcs <= X86_PAGE_4K_SIZE)
2017	{ /* likely */ }
2018	else
2019	{
2020	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE;
2021	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2022	}
2023
2024	/*
2025	* Allocate per-VM VT-x structures.
2026	*/
2027	bool const fVirtApicAccess = RT_BOOL(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
2028	bool const fUseVmcsShadowing = pVM->hmr0.s.vmx.fUseVmcsShadowing;
2029	VMXPAGEALLOCINFO aAllocInfo[] =
2030	{
2031	{ fVirtApicAccess, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysApicAccess, (PRTR0PTR)&pVM->hmr0.s.vmx.pbApicAccess },
2032	{ fUseVmcsShadowing, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysVmreadBitmap, &pVM->hmr0.s.vmx.pvVmreadBitmap },
2033	{ fUseVmcsShadowing, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysVmwriteBitmap, &pVM->hmr0.s.vmx.pvVmwriteBitmap },
2034	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2035	{ true, 0 /* Unused */, &pVM->hmr0.s.vmx.HCPhysScratch, (PRTR0PTR)&pVM->hmr0.s.vmx.pbScratch },
2036	#endif
2037	};
2038
2039	int rc = hmR0VmxPagesAllocZ(&pVM->hmr0.s.vmx.hMemObj, &aAllocInfo[0], RT_ELEMENTS(aAllocInfo));
2040	if (RT_SUCCESS(rc))
2041	{
2042	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2043	/* Allocate the shadow VMCS-fields array. */
2044	if (fUseVmcsShadowing)
2045	{
2046	Assert(!pVM->hmr0.s.vmx.cShadowVmcsFields);
2047	Assert(!pVM->hmr0.s.vmx.cShadowVmcsRoFields);
2048	pVM->hmr0.s.vmx.paShadowVmcsFields = (uint32_t *)RTMemAllocZ(sizeof(g_aVmcsFields));
2049	pVM->hmr0.s.vmx.paShadowVmcsRoFields = (uint32_t *)RTMemAllocZ(sizeof(g_aVmcsFields));
2050	if (!pVM->hmr0.s.vmx.paShadowVmcsFields \|\| !pVM->hmr0.s.vmx.paShadowVmcsRoFields)
2051	rc = VERR_NO_MEMORY;
2052	}
2053	#endif
2054
2055	/*
2056	* Allocate per-VCPU VT-x structures.
2057	*/
2058	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus && RT_SUCCESS(rc); idCpu++)
2059	{
2060	/* Allocate the guest VMCS structures. */
2061	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
2062	rc = hmR0VmxAllocVmcsInfo(pVCpu, &pVCpu->hmr0.s.vmx.VmcsInfo, false /* fIsNstGstVmcs */);
2063
2064	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2065	/* Allocate the nested-guest VMCS structures, when the VMX feature is exposed to the guest. */
2066	if (pVM->cpum.ro.GuestFeatures.fVmx && RT_SUCCESS(rc))
2067	rc = hmR0VmxAllocVmcsInfo(pVCpu, &pVCpu->hmr0.s.vmx.VmcsInfoNstGst, true /* fIsNstGstVmcs */);
2068	#endif
2069	}
2070	if (RT_SUCCESS(rc))
2071	return VINF_SUCCESS;
2072	}
2073	hmR0VmxStructsFree(pVM);
2074	return rc;
2075	}
2076
2077
2078	/**
2079	* Pre-initializes non-zero fields in VMX structures that will be allocated.
2080	*
2081	* @param pVM The cross context VM structure.
2082	*/
2083	static void hmR0VmxStructsInit(PVMCC pVM)
2084	{
2085	/* Paranoia. */
2086	Assert(pVM->hmr0.s.vmx.pbApicAccess == NULL);
2087	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2088	Assert(pVM->hmr0.s.vmx.pbScratch == NULL);
2089	#endif
2090
2091	/*
2092	* Initialize members up-front so we can cleanup en masse on allocation failures.
2093	*/
2094	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2095	pVM->hmr0.s.vmx.HCPhysScratch = NIL_RTHCPHYS;
2096	#endif
2097	pVM->hmr0.s.vmx.HCPhysApicAccess = NIL_RTHCPHYS;
2098	pVM->hmr0.s.vmx.HCPhysVmreadBitmap = NIL_RTHCPHYS;
2099	pVM->hmr0.s.vmx.HCPhysVmwriteBitmap = NIL_RTHCPHYS;
2100	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2101	{
2102	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
2103	hmR0VmxVmcsInfoInit(&pVCpu->hmr0.s.vmx.VmcsInfo, &pVCpu->hm.s.vmx.VmcsInfo);
2104	hmR0VmxVmcsInfoInit(&pVCpu->hmr0.s.vmx.VmcsInfoNstGst, &pVCpu->hm.s.vmx.VmcsInfoNstGst);
2105	}
2106	}
2107
2108	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2109	/**
2110	* Returns whether an MSR at the given MSR-bitmap offset is intercepted or not.
2111	*
2112	* @returns @c true if the MSR is intercepted, @c false otherwise.
2113	* @param pvMsrBitmap The MSR bitmap.
2114	* @param offMsr The MSR byte offset.
2115	* @param iBit The bit offset from the byte offset.
2116	*/
2117	DECLINLINE(bool) hmR0VmxIsMsrBitSet(const void *pvMsrBitmap, uint16_t offMsr, int32_t iBit)
2118	{
2119	uint8_t const * const pbMsrBitmap = (uint8_t const * const)pvMsrBitmap;
2120	Assert(pbMsrBitmap);
2121	Assert(offMsr + (iBit >> 3) <= X86_PAGE_4K_SIZE);
2122	return ASMBitTest(pbMsrBitmap + offMsr, iBit);
2123	}
2124	#endif
2125
2126	/**
2127	* Sets the permission bits for the specified MSR in the given MSR bitmap.
2128	*
2129	* If the passed VMCS is a nested-guest VMCS, this function ensures that the
2130	* read/write intercept is cleared from the MSR bitmap used for hardware-assisted
2131	* VMX execution of the nested-guest, only if nested-guest is also not intercepting
2132	* the read/write access of this MSR.
2133	*
2134	* @param pVCpu The cross context virtual CPU structure.
2135	* @param pVmcsInfo The VMCS info. object.
2136	* @param fIsNstGstVmcs Whether this is a nested-guest VMCS.
2137	* @param idMsr The MSR value.
2138	* @param fMsrpm The MSR permissions (see VMXMSRPM_XXX). This must
2139	* include both a read -and- a write permission!
2140	*
2141	* @sa CPUMGetVmxMsrPermission.
2142	* @remarks Can be called with interrupts disabled.
2143	*/
2144	static void hmR0VmxSetMsrPermission(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, bool fIsNstGstVmcs, uint32_t idMsr, uint32_t fMsrpm)
2145	{
2146	uint8_t pbMsrBitmap = (uint8_t )pVmcsInfo->pvMsrBitmap;
2147	Assert(pbMsrBitmap);
2148	Assert(VMXMSRPM_IS_FLAG_VALID(fMsrpm));
2149
2150	/*
2151	* MSR-bitmap Layout:
2152	* Byte index MSR range Interpreted as
2153	* 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
2154	* 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
2155	* 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
2156	* 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
2157	*
2158	* A bit corresponding to an MSR within the above range causes a VM-exit
2159	* if the bit is 1 on executions of RDMSR/WRMSR. If an MSR falls out of
2160	* the MSR range, it always cause a VM-exit.
2161	*
2162	* See Intel spec. 24.6.9 "MSR-Bitmap Address".
2163	*/
2164	uint16_t const offBitmapRead = 0;
2165	uint16_t const offBitmapWrite = 0x800;
2166	uint16_t offMsr;
2167	int32_t iBit;
2168	if (idMsr <= UINT32_C(0x00001fff))
2169	{
2170	offMsr = 0;
2171	iBit = idMsr;
2172	}
2173	else if (idMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
2174	{
2175	offMsr = 0x400;
2176	iBit = idMsr - UINT32_C(0xc0000000);
2177	}
2178	else
2179	AssertMsgFailedReturnVoid(("Invalid MSR %#RX32\n", idMsr));
2180
2181	/*
2182	* Set the MSR read permission.
2183	*/
2184	uint16_t const offMsrRead = offBitmapRead + offMsr;
2185	Assert(offMsrRead + (iBit >> 3) < offBitmapWrite);
2186	if (fMsrpm & VMXMSRPM_ALLOW_RD)
2187	{
2188	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2189	bool const fClear = !fIsNstGstVmcs ? true
2190	: !hmR0VmxIsMsrBitSet(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), offMsrRead, iBit);
2191	#else
2192	RT_NOREF2(pVCpu, fIsNstGstVmcs);
2193	bool const fClear = true;
2194	#endif
2195	if (fClear)
2196	ASMBitClear(pbMsrBitmap + offMsrRead, iBit);
2197	}
2198	else
2199	ASMBitSet(pbMsrBitmap + offMsrRead, iBit);
2200
2201	/*
2202	* Set the MSR write permission.
2203	*/
2204	uint16_t const offMsrWrite = offBitmapWrite + offMsr;
2205	Assert(offMsrWrite + (iBit >> 3) < X86_PAGE_4K_SIZE);
2206	if (fMsrpm & VMXMSRPM_ALLOW_WR)
2207	{
2208	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2209	bool const fClear = !fIsNstGstVmcs ? true
2210	: !hmR0VmxIsMsrBitSet(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), offMsrWrite, iBit);
2211	#else
2212	RT_NOREF2(pVCpu, fIsNstGstVmcs);
2213	bool const fClear = true;
2214	#endif
2215	if (fClear)
2216	ASMBitClear(pbMsrBitmap + offMsrWrite, iBit);
2217	}
2218	else
2219	ASMBitSet(pbMsrBitmap + offMsrWrite, iBit);
2220	}
2221
2222
2223	/**
2224	* Updates the VMCS with the number of effective MSRs in the auto-load/store MSR
2225	* area.
2226	*
2227	* @returns VBox status code.
2228	* @param pVCpu The cross context virtual CPU structure.
2229	* @param pVmcsInfo The VMCS info. object.
2230	* @param cMsrs The number of MSRs.
2231	*/
2232	static int hmR0VmxSetAutoLoadStoreMsrCount(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint32_t cMsrs)
2233	{
2234	/* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
2235	uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(g_HmMsrs.u.vmx.u64Misc);
2236	if (RT_LIKELY(cMsrs < cMaxSupportedMsrs))
2237	{
2238	/* Commit the MSR counts to the VMCS and update the cache. */
2239	if (pVmcsInfo->cEntryMsrLoad != cMsrs)
2240	{
2241	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs); AssertRC(rc);
2242	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs); AssertRC(rc);
2243	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs); AssertRC(rc);
2244	pVmcsInfo->cEntryMsrLoad = cMsrs;
2245	pVmcsInfo->cExitMsrStore = cMsrs;
2246	pVmcsInfo->cExitMsrLoad = cMsrs;
2247	}
2248	return VINF_SUCCESS;
2249	}
2250
2251	LogRel(("Auto-load/store MSR count exceeded! cMsrs=%u MaxSupported=%u\n", cMsrs, cMaxSupportedMsrs));
2252	pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
2253	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2254	}
2255
2256
2257	/**
2258	* Adds a new (or updates the value of an existing) guest/host MSR
2259	* pair to be swapped during the world-switch as part of the
2260	* auto-load/store MSR area in the VMCS.
2261	*
2262	* @returns VBox status code.
2263	* @param pVCpu The cross context virtual CPU structure.
2264	* @param pVmxTransient The VMX-transient structure.
2265	* @param idMsr The MSR.
2266	* @param uGuestMsrValue Value of the guest MSR.
2267	* @param fSetReadWrite Whether to set the guest read/write access of this
2268	* MSR (thus not causing a VM-exit).
2269	* @param fUpdateHostMsr Whether to update the value of the host MSR if
2270	* necessary.
2271	*/
2272	static int hmR0VmxAddAutoLoadStoreMsr(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint32_t idMsr, uint64_t uGuestMsrValue,
2273	bool fSetReadWrite, bool fUpdateHostMsr)
2274	{
2275	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
2276	bool const fIsNstGstVmcs = pVmxTransient->fIsNestedGuest;
2277	PVMXAUTOMSR pGuestMsrLoad = (PVMXAUTOMSR)pVmcsInfo->pvGuestMsrLoad;
2278	uint32_t cMsrs = pVmcsInfo->cEntryMsrLoad;
2279	uint32_t i;
2280
2281	/* Paranoia. */
2282	Assert(pGuestMsrLoad);
2283
2284	#ifndef DEBUG_bird
2285	LogFlowFunc(("pVCpu=%p idMsr=%#RX32 uGuestMsrValue=%#RX64\n", pVCpu, idMsr, uGuestMsrValue));
2286	#endif
2287
2288	/* Check if the MSR already exists in the VM-entry MSR-load area. */
2289	for (i = 0; i < cMsrs; i++)
2290	{
2291	if (pGuestMsrLoad[i].u32Msr == idMsr)
2292	break;
2293	}
2294
2295	bool fAdded = false;
2296	if (i == cMsrs)
2297	{
2298	/* The MSR does not exist, bump the MSR count to make room for the new MSR. */
2299	++cMsrs;
2300	int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, pVmcsInfo, cMsrs);
2301	AssertMsgRCReturn(rc, ("Insufficient space to add MSR to VM-entry MSR-load/store area %u\n", idMsr), rc);
2302
2303	/* Set the guest to read/write this MSR without causing VM-exits. */
2304	if ( fSetReadWrite
2305	&& (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
2306	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, fIsNstGstVmcs, idMsr, VMXMSRPM_ALLOW_RD_WR);
2307
2308	Log4Func(("Added MSR %#RX32, cMsrs=%u\n", idMsr, cMsrs));
2309	fAdded = true;
2310	}
2311
2312	/* Update the MSR value for the newly added or already existing MSR. */
2313	pGuestMsrLoad[i].u32Msr = idMsr;
2314	pGuestMsrLoad[i].u64Value = uGuestMsrValue;
2315
2316	/* Create the corresponding slot in the VM-exit MSR-store area if we use a different page. */
2317	if (hmR0VmxIsSeparateExitMsrStoreAreaVmcs(pVmcsInfo))
2318	{
2319	PVMXAUTOMSR pGuestMsrStore = (PVMXAUTOMSR)pVmcsInfo->pvGuestMsrStore;
2320	pGuestMsrStore[i].u32Msr = idMsr;
2321	pGuestMsrStore[i].u64Value = uGuestMsrValue;
2322	}
2323
2324	/* Update the corresponding slot in the host MSR area. */
2325	PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVmcsInfo->pvHostMsrLoad;
2326	Assert(pHostMsr != pVmcsInfo->pvGuestMsrLoad);
2327	Assert(pHostMsr != pVmcsInfo->pvGuestMsrStore);
2328	pHostMsr[i].u32Msr = idMsr;
2329
2330	/*
2331	* Only if the caller requests to update the host MSR value AND we've newly added the
2332	* MSR to the host MSR area do we actually update the value. Otherwise, it will be
2333	* updated by hmR0VmxUpdateAutoLoadHostMsrs().
2334	*
2335	* We do this for performance reasons since reading MSRs may be quite expensive.
2336	*/
2337	if (fAdded)
2338	{
2339	if (fUpdateHostMsr)
2340	{
2341	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2342	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2343	pHostMsr[i].u64Value = ASMRdMsr(idMsr);
2344	}
2345	else
2346	{
2347	/* Someone else can do the work. */
2348	pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs = false;
2349	}
2350	}
2351	return VINF_SUCCESS;
2352	}
2353
2354
2355	/**
2356	* Removes a guest/host MSR pair to be swapped during the world-switch from the
2357	* auto-load/store MSR area in the VMCS.
2358	*
2359	* @returns VBox status code.
2360	* @param pVCpu The cross context virtual CPU structure.
2361	* @param pVmxTransient The VMX-transient structure.
2362	* @param idMsr The MSR.
2363	*/
2364	static int hmR0VmxRemoveAutoLoadStoreMsr(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint32_t idMsr)
2365	{
2366	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
2367	bool const fIsNstGstVmcs = pVmxTransient->fIsNestedGuest;
2368	PVMXAUTOMSR pGuestMsrLoad = (PVMXAUTOMSR)pVmcsInfo->pvGuestMsrLoad;
2369	uint32_t cMsrs = pVmcsInfo->cEntryMsrLoad;
2370
2371	#ifndef DEBUG_bird
2372	LogFlowFunc(("pVCpu=%p idMsr=%#RX32\n", pVCpu, idMsr));
2373	#endif
2374
2375	for (uint32_t i = 0; i < cMsrs; i++)
2376	{
2377	/* Find the MSR. */
2378	if (pGuestMsrLoad[i].u32Msr == idMsr)
2379	{
2380	/*
2381	* If it's the last MSR, we only need to reduce the MSR count.
2382	* If it's -not- the last MSR, copy the last MSR in place of it and reduce the MSR count.
2383	*/
2384	if (i < cMsrs - 1)
2385	{
2386	/* Remove it from the VM-entry MSR-load area. */
2387	pGuestMsrLoad[i].u32Msr = pGuestMsrLoad[cMsrs - 1].u32Msr;
2388	pGuestMsrLoad[i].u64Value = pGuestMsrLoad[cMsrs - 1].u64Value;
2389
2390	/* Remove it from the VM-exit MSR-store area if it's in a different page. */
2391	if (hmR0VmxIsSeparateExitMsrStoreAreaVmcs(pVmcsInfo))
2392	{
2393	PVMXAUTOMSR pGuestMsrStore = (PVMXAUTOMSR)pVmcsInfo->pvGuestMsrStore;
2394	Assert(pGuestMsrStore[i].u32Msr == idMsr);
2395	pGuestMsrStore[i].u32Msr = pGuestMsrStore[cMsrs - 1].u32Msr;
2396	pGuestMsrStore[i].u64Value = pGuestMsrStore[cMsrs - 1].u64Value;
2397	}
2398
2399	/* Remove it from the VM-exit MSR-load area. */
2400	PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVmcsInfo->pvHostMsrLoad;
2401	Assert(pHostMsr[i].u32Msr == idMsr);
2402	pHostMsr[i].u32Msr = pHostMsr[cMsrs - 1].u32Msr;
2403	pHostMsr[i].u64Value = pHostMsr[cMsrs - 1].u64Value;
2404	}
2405
2406	/* Reduce the count to reflect the removed MSR and bail. */
2407	--cMsrs;
2408	break;
2409	}
2410	}
2411
2412	/* Update the VMCS if the count changed (meaning the MSR was found and removed). */
2413	if (cMsrs != pVmcsInfo->cEntryMsrLoad)
2414	{
2415	int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, pVmcsInfo, cMsrs);
2416	AssertRCReturn(rc, rc);
2417
2418	/* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
2419	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
2420	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, fIsNstGstVmcs, idMsr, VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR);
2421
2422	Log4Func(("Removed MSR %#RX32, cMsrs=%u\n", idMsr, cMsrs));
2423	return VINF_SUCCESS;
2424	}
2425
2426	return VERR_NOT_FOUND;
2427	}
2428
2429
2430	/**
2431	* Checks if the specified guest MSR is part of the VM-entry MSR-load area.
2432	*
2433	* @returns @c true if found, @c false otherwise.
2434	* @param pVmcsInfo The VMCS info. object.
2435	* @param idMsr The MSR to find.
2436	*/
2437	static bool hmR0VmxIsAutoLoadGuestMsr(PCVMXVMCSINFO pVmcsInfo, uint32_t idMsr)
2438	{
2439	PCVMXAUTOMSR pMsrs = (PCVMXAUTOMSR)pVmcsInfo->pvGuestMsrLoad;
2440	uint32_t const cMsrs = pVmcsInfo->cEntryMsrLoad;
2441	Assert(pMsrs);
2442	Assert(sizeof(pMsrs) cMsrs <= X86_PAGE_4K_SIZE);
2443	for (uint32_t i = 0; i < cMsrs; i++)
2444	{
2445	if (pMsrs[i].u32Msr == idMsr)
2446	return true;
2447	}
2448	return false;
2449	}
2450
2451
2452	/**
2453	* Updates the value of all host MSRs in the VM-exit MSR-load area.
2454	*
2455	* @param pVCpu The cross context virtual CPU structure.
2456	* @param pVmcsInfo The VMCS info. object.
2457	*
2458	* @remarks No-long-jump zone!!!
2459	*/
2460	static void hmR0VmxUpdateAutoLoadHostMsrs(PCVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo)
2461	{
2462	RT_NOREF(pVCpu);
2463	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2464
2465	PVMXAUTOMSR pHostMsrLoad = (PVMXAUTOMSR)pVmcsInfo->pvHostMsrLoad;
2466	uint32_t const cMsrs = pVmcsInfo->cExitMsrLoad;
2467	Assert(pHostMsrLoad);
2468	Assert(sizeof(pHostMsrLoad) cMsrs <= X86_PAGE_4K_SIZE);
2469	LogFlowFunc(("pVCpu=%p cMsrs=%u\n", pVCpu, cMsrs));
2470	for (uint32_t i = 0; i < cMsrs; i++)
2471	{
2472	/*
2473	* Performance hack for the host EFER MSR. We use the cached value rather than re-read it.
2474	* Strict builds will catch mismatches in hmR0VmxCheckAutoLoadStoreMsrs(). See @bugref{7368}.
2475	*/
2476	if (pHostMsrLoad[i].u32Msr == MSR_K6_EFER)
2477	pHostMsrLoad[i].u64Value = g_uHmVmxHostMsrEfer;
2478	else
2479	pHostMsrLoad[i].u64Value = ASMRdMsr(pHostMsrLoad[i].u32Msr);
2480	}
2481	}
2482
2483
2484	/**
2485	* Saves a set of host MSRs to allow read/write passthru access to the guest and
2486	* perform lazy restoration of the host MSRs while leaving VT-x.
2487	*
2488	* @param pVCpu The cross context virtual CPU structure.
2489	*
2490	* @remarks No-long-jump zone!!!
2491	*/
2492	static void hmR0VmxLazySaveHostMsrs(PVMCPUCC pVCpu)
2493	{
2494	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2495
2496	/*
2497	* Note: If you're adding MSRs here, make sure to update the MSR-bitmap accesses in hmR0VmxSetupVmcsProcCtls().
2498	*/
2499	if (!(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST))
2500	{
2501	Assert(!(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */
2502	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests)
2503	{
2504	pVCpu->hmr0.s.vmx.u64HostMsrLStar = ASMRdMsr(MSR_K8_LSTAR);
2505	pVCpu->hmr0.s.vmx.u64HostMsrStar = ASMRdMsr(MSR_K6_STAR);
2506	pVCpu->hmr0.s.vmx.u64HostMsrSfMask = ASMRdMsr(MSR_K8_SF_MASK);
2507	pVCpu->hmr0.s.vmx.u64HostMsrKernelGsBase = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
2508	}
2509	pVCpu->hmr0.s.vmx.fLazyMsrs \|= VMX_LAZY_MSRS_SAVED_HOST;
2510	}
2511	}
2512
2513
2514	/**
2515	* Checks whether the MSR belongs to the set of guest MSRs that we restore
2516	* lazily while leaving VT-x.
2517	*
2518	* @returns true if it does, false otherwise.
2519	* @param pVCpu The cross context virtual CPU structure.
2520	* @param idMsr The MSR to check.
2521	*/
2522	static bool hmR0VmxIsLazyGuestMsr(PCVMCPUCC pVCpu, uint32_t idMsr)
2523	{
2524	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests)
2525	{
2526	switch (idMsr)
2527	{
2528	case MSR_K8_LSTAR:
2529	case MSR_K6_STAR:
2530	case MSR_K8_SF_MASK:
2531	case MSR_K8_KERNEL_GS_BASE:
2532	return true;
2533	}
2534	}
2535	return false;
2536	}
2537
2538
2539	/**
2540	* Loads a set of guests MSRs to allow read/passthru to the guest.
2541	*
2542	* The name of this function is slightly confusing. This function does NOT
2543	* postpone loading, but loads the MSR right now. "hmR0VmxLazy" is simply a
2544	* common prefix for functions dealing with "lazy restoration" of the shared
2545	* MSRs.
2546	*
2547	* @param pVCpu The cross context virtual CPU structure.
2548	*
2549	* @remarks No-long-jump zone!!!
2550	*/
2551	static void hmR0VmxLazyLoadGuestMsrs(PVMCPUCC pVCpu)
2552	{
2553	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2554	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2555
2556	Assert(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
2557	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests)
2558	{
2559	/*
2560	* If the guest MSRs are not loaded -and- if all the guest MSRs are identical
2561	* to the MSRs on the CPU (which are the saved host MSRs, see assertion above) then
2562	* we can skip a few MSR writes.
2563	*
2564	* Otherwise, it implies either 1. they're not loaded, or 2. they're loaded but the
2565	* guest MSR values in the guest-CPU context might be different to what's currently
2566	* loaded in the CPU. In either case, we need to write the new guest MSR values to the
2567	* CPU, see @bugref{8728}.
2568	*/
2569	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2570	if ( !(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
2571	&& pCtx->msrKERNELGSBASE == pVCpu->hmr0.s.vmx.u64HostMsrKernelGsBase
2572	&& pCtx->msrLSTAR == pVCpu->hmr0.s.vmx.u64HostMsrLStar
2573	&& pCtx->msrSTAR == pVCpu->hmr0.s.vmx.u64HostMsrStar
2574	&& pCtx->msrSFMASK == pVCpu->hmr0.s.vmx.u64HostMsrSfMask)
2575	{
2576	#ifdef VBOX_STRICT
2577	Assert(ASMRdMsr(MSR_K8_KERNEL_GS_BASE) == pCtx->msrKERNELGSBASE);
2578	Assert(ASMRdMsr(MSR_K8_LSTAR) == pCtx->msrLSTAR);
2579	Assert(ASMRdMsr(MSR_K6_STAR) == pCtx->msrSTAR);
2580	Assert(ASMRdMsr(MSR_K8_SF_MASK) == pCtx->msrSFMASK);
2581	#endif
2582	}
2583	else
2584	{
2585	ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
2586	ASMWrMsr(MSR_K8_LSTAR, pCtx->msrLSTAR);
2587	ASMWrMsr(MSR_K6_STAR, pCtx->msrSTAR);
2588	/* The system call flag mask register isn't as benign and accepting of all
2589	values as the above, so mask it to avoid #GP'ing on corrupted input. */
2590	Assert(!(pCtx->msrSFMASK & ~(uint64_t)UINT32_MAX));
2591	ASMWrMsr(MSR_K8_SF_MASK, pCtx->msrSFMASK & UINT32_MAX);
2592	}
2593	}
2594	pVCpu->hmr0.s.vmx.fLazyMsrs \|= VMX_LAZY_MSRS_LOADED_GUEST;
2595	}
2596
2597
2598	/**
2599	* Performs lazy restoration of the set of host MSRs if they were previously
2600	* loaded with guest MSR values.
2601	*
2602	* @param pVCpu The cross context virtual CPU structure.
2603	*
2604	* @remarks No-long-jump zone!!!
2605	* @remarks The guest MSRs should have been saved back into the guest-CPU
2606	* context by hmR0VmxImportGuestState()!!!
2607	*/
2608	static void hmR0VmxLazyRestoreHostMsrs(PVMCPUCC pVCpu)
2609	{
2610	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2611	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2612
2613	if (pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
2614	{
2615	Assert(pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
2616	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fAllow64BitGuests)
2617	{
2618	ASMWrMsr(MSR_K8_LSTAR, pVCpu->hmr0.s.vmx.u64HostMsrLStar);
2619	ASMWrMsr(MSR_K6_STAR, pVCpu->hmr0.s.vmx.u64HostMsrStar);
2620	ASMWrMsr(MSR_K8_SF_MASK, pVCpu->hmr0.s.vmx.u64HostMsrSfMask);
2621	ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pVCpu->hmr0.s.vmx.u64HostMsrKernelGsBase);
2622	}
2623	}
2624	pVCpu->hmr0.s.vmx.fLazyMsrs &= ~(VMX_LAZY_MSRS_LOADED_GUEST \| VMX_LAZY_MSRS_SAVED_HOST);
2625	}
2626
2627
2628	/**
2629	* Verifies that our cached values of the VMCS fields are all consistent with
2630	* what's actually present in the VMCS.
2631	*
2632	* @returns VBox status code.
2633	* @retval VINF_SUCCESS if all our caches match their respective VMCS fields.
2634	* @retval VERR_VMX_VMCS_FIELD_CACHE_INVALID if a cache field doesn't match the
2635	* VMCS content. HMCPU error-field is
2636	* updated, see VMX_VCI_XXX.
2637	* @param pVCpu The cross context virtual CPU structure.
2638	* @param pVmcsInfo The VMCS info. object.
2639	* @param fIsNstGstVmcs Whether this is a nested-guest VMCS.
2640	*/
2641	static int hmR0VmxCheckCachedVmcsCtls(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo, bool fIsNstGstVmcs)
2642	{
2643	const char * const pcszVmcs = fIsNstGstVmcs ? "Nested-guest VMCS" : "VMCS";
2644
2645	uint32_t u32Val;
2646	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
2647	AssertRC(rc);
2648	AssertMsgReturnStmt(pVmcsInfo->u32EntryCtls == u32Val,
2649	("%s controls mismatch: Cache=%#RX32 VMCS=%#RX32\n", pcszVmcs, pVmcsInfo->u32EntryCtls, u32Val),
2650	pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_ENTRY,
2651	VERR_VMX_VMCS_FIELD_CACHE_INVALID);
2652
2653	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);
2654	AssertRC(rc);
2655	AssertMsgReturnStmt(pVmcsInfo->u32ExitCtls == u32Val,
2656	("%s controls mismatch: Cache=%#RX32 VMCS=%#RX32\n", pcszVmcs, pVmcsInfo->u32ExitCtls, u32Val),
2657	pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_EXIT,
2658	VERR_VMX_VMCS_FIELD_CACHE_INVALID);
2659
2660	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);
2661	AssertRC(rc);
2662	AssertMsgReturnStmt(pVmcsInfo->u32PinCtls == u32Val,
2663	("%s controls mismatch: Cache=%#RX32 VMCS=%#RX32\n", pcszVmcs, pVmcsInfo->u32PinCtls, u32Val),
2664	pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PIN_EXEC,
2665	VERR_VMX_VMCS_FIELD_CACHE_INVALID);
2666
2667	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
2668	AssertRC(rc);
2669	AssertMsgReturnStmt(pVmcsInfo->u32ProcCtls == u32Val,
2670	("%s controls mismatch: Cache=%#RX32 VMCS=%#RX32\n", pcszVmcs, pVmcsInfo->u32ProcCtls, u32Val),
2671	pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC,
2672	VERR_VMX_VMCS_FIELD_CACHE_INVALID);
2673
2674	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2675	{
2676	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
2677	AssertRC(rc);
2678	AssertMsgReturnStmt(pVmcsInfo->u32ProcCtls2 == u32Val,
2679	("%s controls mismatch: Cache=%#RX32 VMCS=%#RX32\n", pcszVmcs, pVmcsInfo->u32ProcCtls2, u32Val),
2680	pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC2,
2681	VERR_VMX_VMCS_FIELD_CACHE_INVALID);
2682	}
2683
2684	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val);
2685	AssertRC(rc);
2686	AssertMsgReturnStmt(pVmcsInfo->u32XcptBitmap == u32Val,
2687	("%s exception bitmap mismatch: Cache=%#RX32 VMCS=%#RX32\n", pcszVmcs, pVmcsInfo->u32XcptBitmap, u32Val),
2688	pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_XCPT_BITMAP,
2689	VERR_VMX_VMCS_FIELD_CACHE_INVALID);
2690
2691	uint64_t u64Val;
2692	rc = VMXReadVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, &u64Val);
2693	AssertRC(rc);
2694	AssertMsgReturnStmt(pVmcsInfo->u64TscOffset == u64Val,
2695	("%s TSC offset mismatch: Cache=%#RX64 VMCS=%#RX64\n", pcszVmcs, pVmcsInfo->u64TscOffset, u64Val),
2696	pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_TSC_OFFSET,
2697	VERR_VMX_VMCS_FIELD_CACHE_INVALID);
2698
2699	NOREF(pcszVmcs);
2700	return VINF_SUCCESS;
2701	}
2702
2703	#ifdef VBOX_STRICT
2704
2705	/**
2706	* Verifies that our cached host EFER MSR value has not changed since we cached it.
2707	*
2708	* @param pVmcsInfo The VMCS info. object.
2709	*/
2710	static void hmR0VmxCheckHostEferMsr(PCVMXVMCSINFO pVmcsInfo)
2711	{
2712	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2713
2714	if (pVmcsInfo->u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2715	{
2716	uint64_t const uHostEferMsr = ASMRdMsr(MSR_K6_EFER);
2717	uint64_t const uHostEferMsrCache = g_uHmVmxHostMsrEfer;
2718	uint64_t uVmcsEferMsrVmcs;
2719	int rc = VMXReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &uVmcsEferMsrVmcs);
2720	AssertRC(rc);
2721
2722	AssertMsgReturnVoid(uHostEferMsr == uVmcsEferMsrVmcs,
2723	("EFER Host/VMCS mismatch! host=%#RX64 vmcs=%#RX64\n", uHostEferMsr, uVmcsEferMsrVmcs));
2724	AssertMsgReturnVoid(uHostEferMsr == uHostEferMsrCache,
2725	("EFER Host/Cache mismatch! host=%#RX64 cache=%#RX64\n", uHostEferMsr, uHostEferMsrCache));
2726	}
2727	}
2728
2729
2730	/**
2731	* Verifies whether the guest/host MSR pairs in the auto-load/store area in the
2732	* VMCS are correct.
2733	*
2734	* @param pVCpu The cross context virtual CPU structure.
2735	* @param pVmcsInfo The VMCS info. object.
2736	* @param fIsNstGstVmcs Whether this is a nested-guest VMCS.
2737	*/
2738	static void hmR0VmxCheckAutoLoadStoreMsrs(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo, bool fIsNstGstVmcs)
2739	{
2740	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2741
2742	/* Read the various MSR-area counts from the VMCS. */
2743	uint32_t cEntryLoadMsrs;
2744	uint32_t cExitStoreMsrs;
2745	uint32_t cExitLoadMsrs;
2746	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cEntryLoadMsrs); AssertRC(rc);
2747	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cExitStoreMsrs); AssertRC(rc);
2748	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cExitLoadMsrs); AssertRC(rc);
2749
2750	/* Verify all the MSR counts are the same. */
2751	Assert(cEntryLoadMsrs == cExitStoreMsrs);
2752	Assert(cExitStoreMsrs == cExitLoadMsrs);
2753	uint32_t const cMsrs = cExitLoadMsrs;
2754
2755	/* Verify the MSR counts do not exceed the maximum count supported by the hardware. */
2756	Assert(cMsrs < VMX_MISC_MAX_MSRS(g_HmMsrs.u.vmx.u64Misc));
2757
2758	/* Verify the MSR counts are within the allocated page size. */
2759	Assert(sizeof(VMXAUTOMSR) * cMsrs <= X86_PAGE_4K_SIZE);
2760
2761	/* Verify the relevant contents of the MSR areas match. */
2762	PCVMXAUTOMSR pGuestMsrLoad = (PCVMXAUTOMSR)pVmcsInfo->pvGuestMsrLoad;
2763	PCVMXAUTOMSR pGuestMsrStore = (PCVMXAUTOMSR)pVmcsInfo->pvGuestMsrStore;
2764	PCVMXAUTOMSR pHostMsrLoad = (PCVMXAUTOMSR)pVmcsInfo->pvHostMsrLoad;
2765	bool const fSeparateExitMsrStorePage = hmR0VmxIsSeparateExitMsrStoreAreaVmcs(pVmcsInfo);
2766	for (uint32_t i = 0; i < cMsrs; i++)
2767	{
2768	/* Verify that the MSRs are paired properly and that the host MSR has the correct value. */
2769	if (fSeparateExitMsrStorePage)
2770	{
2771	AssertMsgReturnVoid(pGuestMsrLoad->u32Msr == pGuestMsrStore->u32Msr,
2772	("GuestMsrLoad=%#RX32 GuestMsrStore=%#RX32 cMsrs=%u\n",
2773	pGuestMsrLoad->u32Msr, pGuestMsrStore->u32Msr, cMsrs));
2774	}
2775
2776	AssertMsgReturnVoid(pHostMsrLoad->u32Msr == pGuestMsrLoad->u32Msr,
2777	("HostMsrLoad=%#RX32 GuestMsrLoad=%#RX32 cMsrs=%u\n",
2778	pHostMsrLoad->u32Msr, pGuestMsrLoad->u32Msr, cMsrs));
2779
2780	uint64_t const u64HostMsr = ASMRdMsr(pHostMsrLoad->u32Msr);
2781	AssertMsgReturnVoid(pHostMsrLoad->u64Value == u64HostMsr,
2782	("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
2783	pHostMsrLoad->u32Msr, pHostMsrLoad->u64Value, u64HostMsr, cMsrs));
2784
2785	/* Verify that cached host EFER MSR matches what's loaded on the CPU. */
2786	bool const fIsEferMsr = RT_BOOL(pHostMsrLoad->u32Msr == MSR_K6_EFER);
2787	AssertMsgReturnVoid(!fIsEferMsr \|\| u64HostMsr == g_uHmVmxHostMsrEfer,
2788	("Cached=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n", g_uHmVmxHostMsrEfer, u64HostMsr, cMsrs));
2789
2790	/* Verify that the accesses are as expected in the MSR bitmap for auto-load/store MSRs. */
2791	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
2792	{
2793	uint32_t const fMsrpm = CPUMGetVmxMsrPermission(pVmcsInfo->pvMsrBitmap, pGuestMsrLoad->u32Msr);
2794	if (fIsEferMsr)
2795	{
2796	AssertMsgReturnVoid((fMsrpm & VMXMSRPM_EXIT_RD), ("Passthru read for EFER MSR!?\n"));
2797	AssertMsgReturnVoid((fMsrpm & VMXMSRPM_EXIT_WR), ("Passthru write for EFER MSR!?\n"));
2798	}
2799	else
2800	{
2801	/* Verify LBR MSRs (used only for debugging) are intercepted. We don't passthru these MSRs to the guest yet. */
2802	PCVMCC pVM = pVCpu->CTX_SUFF(pVM);
2803	if ( pVM->hmr0.s.vmx.fLbr
2804	&& ( hmR0VmxIsLbrBranchFromMsr(pVM, pGuestMsrLoad->u32Msr, NULL /* pidxMsr */)
2805	\|\| hmR0VmxIsLbrBranchToMsr(pVM, pGuestMsrLoad->u32Msr, NULL /* pidxMsr */)
2806	\|\| pGuestMsrLoad->u32Msr == pVM->hmr0.s.vmx.idLbrTosMsr))
2807	{
2808	AssertMsgReturnVoid((fMsrpm & VMXMSRPM_MASK) == VMXMSRPM_EXIT_RD_WR,
2809	("u32Msr=%#RX32 cMsrs=%u Passthru read/write for LBR MSRs!\n",
2810	pGuestMsrLoad->u32Msr, cMsrs));
2811	}
2812	else if (!fIsNstGstVmcs)
2813	{
2814	AssertMsgReturnVoid((fMsrpm & VMXMSRPM_MASK) == VMXMSRPM_ALLOW_RD_WR,
2815	("u32Msr=%#RX32 cMsrs=%u No passthru read/write!\n", pGuestMsrLoad->u32Msr, cMsrs));
2816	}
2817	else
2818	{
2819	/*
2820	* A nested-guest VMCS must -also- allow read/write passthrough for the MSR for us to
2821	* execute a nested-guest with MSR passthrough.
2822	*
2823	* Check if the nested-guest MSR bitmap allows passthrough, and if so, assert that we
2824	* allow passthrough too.
2825	*/
2826	void const *pvMsrBitmapNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap);
2827	Assert(pvMsrBitmapNstGst);
2828	uint32_t const fMsrpmNstGst = CPUMGetVmxMsrPermission(pvMsrBitmapNstGst, pGuestMsrLoad->u32Msr);
2829	AssertMsgReturnVoid(fMsrpm == fMsrpmNstGst,
2830	("u32Msr=%#RX32 cMsrs=%u Permission mismatch fMsrpm=%#x fMsrpmNstGst=%#x!\n",
2831	pGuestMsrLoad->u32Msr, cMsrs, fMsrpm, fMsrpmNstGst));
2832	}
2833	}
2834	}
2835
2836	/* Move to the next MSR. */
2837	pHostMsrLoad++;
2838	pGuestMsrLoad++;
2839	pGuestMsrStore++;
2840	}
2841	}
2842
2843	#endif /* VBOX_STRICT */
2844
2845	/**
2846	* Flushes the TLB using EPT.
2847	*
2848	* @returns VBox status code.
2849	* @param pVCpu The cross context virtual CPU structure of the calling
2850	* EMT. Can be NULL depending on @a enmTlbFlush.
2851	* @param pVmcsInfo The VMCS info. object. Can be NULL depending on @a
2852	* enmTlbFlush.
2853	* @param enmTlbFlush Type of flush.
2854	*
2855	* @remarks Caller is responsible for making sure this function is called only
2856	* when NestedPaging is supported and providing @a enmTlbFlush that is
2857	* supported by the CPU.
2858	* @remarks Can be called with interrupts disabled.
2859	*/
2860	static void hmR0VmxFlushEpt(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo, VMXTLBFLUSHEPT enmTlbFlush)
2861	{
2862	uint64_t au64Descriptor[2];
2863	if (enmTlbFlush == VMXTLBFLUSHEPT_ALL_CONTEXTS)
2864	au64Descriptor[0] = 0;
2865	else
2866	{
2867	Assert(pVCpu);
2868	Assert(pVmcsInfo);
2869	au64Descriptor[0] = pVmcsInfo->HCPhysEPTP;
2870	}
2871	au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
2872
2873	int rc = VMXR0InvEPT(enmTlbFlush, &au64Descriptor[0]);
2874	AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvEPT %#x %#RHp failed. rc=%Rrc\n", enmTlbFlush, au64Descriptor[0], rc));
2875
2876	if ( RT_SUCCESS(rc)
2877	&& pVCpu)
2878	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
2879	}
2880
2881
2882	/**
2883	* Flushes the TLB using VPID.
2884	*
2885	* @returns VBox status code.
2886	* @param pVCpu The cross context virtual CPU structure of the calling
2887	* EMT. Can be NULL depending on @a enmTlbFlush.
2888	* @param enmTlbFlush Type of flush.
2889	* @param GCPtr Virtual address of the page to flush (can be 0 depending
2890	* on @a enmTlbFlush).
2891	*
2892	* @remarks Can be called with interrupts disabled.
2893	*/
2894	static void hmR0VmxFlushVpid(PVMCPUCC pVCpu, VMXTLBFLUSHVPID enmTlbFlush, RTGCPTR GCPtr)
2895	{
2896	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fVpid);
2897
2898	uint64_t au64Descriptor[2];
2899	if (enmTlbFlush == VMXTLBFLUSHVPID_ALL_CONTEXTS)
2900	{
2901	au64Descriptor[0] = 0;
2902	au64Descriptor[1] = 0;
2903	}
2904	else
2905	{
2906	AssertPtr(pVCpu);
2907	AssertMsg(pVCpu->hmr0.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hmr0.s.uCurrentAsid));
2908	AssertMsg(pVCpu->hmr0.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hmr0.s.uCurrentAsid));
2909	au64Descriptor[0] = pVCpu->hmr0.s.uCurrentAsid;
2910	au64Descriptor[1] = GCPtr;
2911	}
2912
2913	int rc = VMXR0InvVPID(enmTlbFlush, &au64Descriptor[0]);
2914	AssertMsg(rc == VINF_SUCCESS,
2915	("VMXR0InvVPID %#x %u %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hmr0.s.uCurrentAsid : 0, GCPtr, rc));
2916
2917	if ( RT_SUCCESS(rc)
2918	&& pVCpu)
2919	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
2920	NOREF(rc);
2921	}
2922
2923
2924	/**
2925	* Invalidates a guest page by guest virtual address. Only relevant for EPT/VPID,
2926	* otherwise there is nothing really to invalidate.
2927	*
2928	* @returns VBox status code.
2929	* @param pVCpu The cross context virtual CPU structure.
2930	* @param GCVirt Guest virtual address of the page to invalidate.
2931	*/
2932	VMMR0DECL(int) VMXR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
2933	{
2934	AssertPtr(pVCpu);
2935	LogFlowFunc(("pVCpu=%p GCVirt=%RGv\n", pVCpu, GCVirt));
2936
2937	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
2938	{
2939	/*
2940	* We must invalidate the guest TLB entry in either case, we cannot ignore it even for
2941	* the EPT case. See @bugref{6043} and @bugref{6177}.
2942	*
2943	* Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*()
2944	* as this function maybe called in a loop with individual addresses.
2945	*/
2946	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2947	if (pVM->hmr0.s.vmx.fVpid)
2948	{
2949	if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
2950	{
2951	hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_INDIV_ADDR, GCVirt);
2952	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
2953	}
2954	else
2955	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2956	}
2957	else if (pVM->hmr0.s.fNestedPaging)
2958	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2959	}
2960
2961	return VINF_SUCCESS;
2962	}
2963
2964
2965	/**
2966	* Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
2967	* case where neither EPT nor VPID is supported by the CPU.
2968	*
2969	* @param pHostCpu The HM physical-CPU structure.
2970	* @param pVCpu The cross context virtual CPU structure.
2971	*
2972	* @remarks Called with interrupts disabled.
2973	*/
2974	static void hmR0VmxFlushTaggedTlbNone(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
2975	{
2976	AssertPtr(pVCpu);
2977	AssertPtr(pHostCpu);
2978
2979	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
2980
2981	Assert(pHostCpu->idCpu != NIL_RTCPUID);
2982	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
2983	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
2984	pVCpu->hmr0.s.fForceTLBFlush = false;
2985	return;
2986	}
2987
2988
2989	/**
2990	* Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
2991	*
2992	* @param pHostCpu The HM physical-CPU structure.
2993	* @param pVCpu The cross context virtual CPU structure.
2994	* @param pVmcsInfo The VMCS info. object.
2995	*
2996	* @remarks All references to "ASID" in this function pertains to "VPID" in Intel's
2997	* nomenclature. The reason is, to avoid confusion in compare statements
2998	* since the host-CPU copies are named "ASID".
2999	*
3000	* @remarks Called with interrupts disabled.
3001	*/
3002	static void hmR0VmxFlushTaggedTlbBoth(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo)
3003	{
3004	#ifdef VBOX_WITH_STATISTICS
3005	bool fTlbFlushed = false;
3006	# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
3007	# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
3008	if (!fTlbFlushed) \
3009	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
3010	} while (0)
3011	#else
3012	# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
3013	# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
3014	#endif
3015
3016	AssertPtr(pVCpu);
3017	AssertPtr(pHostCpu);
3018	Assert(pHostCpu->idCpu != NIL_RTCPUID);
3019
3020	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3021	AssertMsg(pVM->hmr0.s.fNestedPaging && pVM->hmr0.s.vmx.fVpid,
3022	("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
3023	"fNestedPaging=%RTbool fVpid=%RTbool", pVM->hmr0.s.fNestedPaging, pVM->hmr0.s.vmx.fVpid));
3024
3025	/*
3026	* Force a TLB flush for the first world-switch if the current CPU differs from the one we
3027	* ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
3028	* limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
3029	* cannot reuse the current ASID anymore.
3030	*/
3031	if ( pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
3032	\|\| pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes)
3033	{
3034	++pHostCpu->uCurrentAsid;
3035	if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid)
3036	{
3037	pHostCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
3038	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
3039	pHostCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
3040	}
3041
3042	pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
3043	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
3044	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
3045
3046	/*
3047	* Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
3048	* invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
3049	*/
3050	hmR0VmxFlushEpt(pVCpu, pVmcsInfo, pVM->hmr0.s.vmx.enmTlbFlushEpt);
3051	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
3052	HMVMX_SET_TAGGED_TLB_FLUSHED();
3053	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
3054	}
3055	else if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH)) /* Check for explicit TLB flushes. */
3056	{
3057	/*
3058	* Changes to the EPT paging structure by VMM requires flushing-by-EPT as the CPU
3059	* creates guest-physical (ie. only EPT-tagged) mappings while traversing the EPT
3060	* tables when EPT is in use. Flushing-by-VPID will only flush linear (only
3061	* VPID-tagged) and combined (EPT+VPID tagged) mappings but not guest-physical
3062	* mappings, see @bugref{6568}.
3063	*
3064	* See Intel spec. 28.3.2 "Creating and Using Cached Translation Information".
3065	*/
3066	hmR0VmxFlushEpt(pVCpu, pVmcsInfo, pVM->hmr0.s.vmx.enmTlbFlushEpt);
3067	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
3068	HMVMX_SET_TAGGED_TLB_FLUSHED();
3069	}
3070	else if (pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb)
3071	{
3072	/*
3073	* The nested-guest specifies its own guest-physical address to use as the APIC-access
3074	* address which requires flushing the TLB of EPT cached structures.
3075	*
3076	* See Intel spec. 28.3.3.4 "Guidelines for Use of the INVEPT Instruction".
3077	*/
3078	hmR0VmxFlushEpt(pVCpu, pVmcsInfo, pVM->hmr0.s.vmx.enmTlbFlushEpt);
3079	pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb = false;
3080	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbNstGst);
3081	HMVMX_SET_TAGGED_TLB_FLUSHED();
3082	}
3083
3084
3085	pVCpu->hmr0.s.fForceTLBFlush = false;
3086	HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
3087
3088	Assert(pVCpu->hmr0.s.idLastCpu == pHostCpu->idCpu);
3089	Assert(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes);
3090	AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
3091	("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
3092	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid,
3093	("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
3094	pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hmr0.s.cTlbFlushes));
3095	AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid,
3096	("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
3097
3098	/* Update VMCS with the VPID. */
3099	int rc = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid);
3100	AssertRC(rc);
3101
3102	#undef HMVMX_SET_TAGGED_TLB_FLUSHED
3103	}
3104
3105
3106	/**
3107	* Flushes the tagged-TLB entries for EPT CPUs as necessary.
3108	*
3109	* @param pHostCpu The HM physical-CPU structure.
3110	* @param pVCpu The cross context virtual CPU structure.
3111	* @param pVmcsInfo The VMCS info. object.
3112	*
3113	* @remarks Called with interrupts disabled.
3114	*/
3115	static void hmR0VmxFlushTaggedTlbEpt(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo)
3116	{
3117	AssertPtr(pVCpu);
3118	AssertPtr(pHostCpu);
3119	Assert(pHostCpu->idCpu != NIL_RTCPUID);
3120	AssertMsg(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked without NestedPaging."));
3121	AssertMsg(!pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID."));
3122
3123	/*
3124	* Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
3125	* A change in the TLB flush count implies the host CPU is online after a suspend/resume.
3126	*/
3127	if ( pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
3128	\|\| pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes)
3129	{
3130	pVCpu->hmr0.s.fForceTLBFlush = true;
3131	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
3132	}
3133
3134	/* Check for explicit TLB flushes. */
3135	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
3136	{
3137	pVCpu->hmr0.s.fForceTLBFlush = true;
3138	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
3139	}
3140
3141	/* Check for TLB flushes while switching to/from a nested-guest. */
3142	if (pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb)
3143	{
3144	pVCpu->hmr0.s.fForceTLBFlush = true;
3145	pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb = false;
3146	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbNstGst);
3147	}
3148
3149	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
3150	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
3151
3152	if (pVCpu->hmr0.s.fForceTLBFlush)
3153	{
3154	hmR0VmxFlushEpt(pVCpu, pVmcsInfo, pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.enmTlbFlushEpt);
3155	pVCpu->hmr0.s.fForceTLBFlush = false;
3156	}
3157	}
3158
3159
3160	/**
3161	* Flushes the tagged-TLB entries for VPID CPUs as necessary.
3162	*
3163	* @param pHostCpu The HM physical-CPU structure.
3164	* @param pVCpu The cross context virtual CPU structure.
3165	*
3166	* @remarks Called with interrupts disabled.
3167	*/
3168	static void hmR0VmxFlushTaggedTlbVpid(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu)
3169	{
3170	AssertPtr(pVCpu);
3171	AssertPtr(pHostCpu);
3172	Assert(pHostCpu->idCpu != NIL_RTCPUID);
3173	AssertMsg(pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked without VPID."));
3174	AssertMsg(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging"));
3175
3176	/*
3177	* Force a TLB flush for the first world switch if the current CPU differs from the one we
3178	* ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
3179	* limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
3180	* cannot reuse the current ASID anymore.
3181	*/
3182	if ( pVCpu->hmr0.s.idLastCpu != pHostCpu->idCpu
3183	\|\| pVCpu->hmr0.s.cTlbFlushes != pHostCpu->cTlbFlushes)
3184	{
3185	pVCpu->hmr0.s.fForceTLBFlush = true;
3186	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
3187	}
3188
3189	/* Check for explicit TLB flushes. */
3190	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
3191	{
3192	/*
3193	* If we ever support VPID flush combinations other than ALL or SINGLE-context (see
3194	* hmR0VmxSetupTaggedTlb()) we would need to explicitly flush in this case (add an
3195	* fExplicitFlush = true here and change the pHostCpu->fFlushAsidBeforeUse check below to
3196	* include fExplicitFlush's too) - an obscure corner case.
3197	*/
3198	pVCpu->hmr0.s.fForceTLBFlush = true;
3199	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
3200	}
3201
3202	/* Check for TLB flushes while switching to/from a nested-guest. */
3203	if (pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb)
3204	{
3205	pVCpu->hmr0.s.fForceTLBFlush = true;
3206	pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb = false;
3207	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbNstGst);
3208	}
3209
3210	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3211	pVCpu->hmr0.s.idLastCpu = pHostCpu->idCpu;
3212	if (pVCpu->hmr0.s.fForceTLBFlush)
3213	{
3214	++pHostCpu->uCurrentAsid;
3215	if (pHostCpu->uCurrentAsid >= g_uHmMaxAsid)
3216	{
3217	pHostCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
3218	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
3219	pHostCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
3220	}
3221
3222	pVCpu->hmr0.s.fForceTLBFlush = false;
3223	pVCpu->hmr0.s.cTlbFlushes = pHostCpu->cTlbFlushes;
3224	pVCpu->hmr0.s.uCurrentAsid = pHostCpu->uCurrentAsid;
3225	if (pHostCpu->fFlushAsidBeforeUse)
3226	{
3227	if (pVM->hmr0.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
3228	hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
3229	else if (pVM->hmr0.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
3230	{
3231	hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
3232	pHostCpu->fFlushAsidBeforeUse = false;
3233	}
3234	else
3235	{
3236	/* hmR0VmxSetupTaggedTlb() ensures we never get here. Paranoia. */
3237	AssertMsgFailed(("Unsupported VPID-flush context type.\n"));
3238	}
3239	}
3240	}
3241
3242	AssertMsg(pVCpu->hmr0.s.cTlbFlushes == pHostCpu->cTlbFlushes,
3243	("Flush count mismatch for cpu %d (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hmr0.s.cTlbFlushes, pHostCpu->cTlbFlushes));
3244	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < g_uHmMaxAsid,
3245	("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pHostCpu->idCpu,
3246	pHostCpu->uCurrentAsid, pHostCpu->cTlbFlushes, pVCpu->hmr0.s.idLastCpu, pVCpu->hmr0.s.cTlbFlushes));
3247	AssertMsg(pVCpu->hmr0.s.uCurrentAsid >= 1 && pVCpu->hmr0.s.uCurrentAsid < g_uHmMaxAsid,
3248	("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pHostCpu->idCpu, pVCpu->hmr0.s.uCurrentAsid));
3249
3250	int rc = VMXWriteVmcs16(VMX_VMCS16_VPID, pVCpu->hmr0.s.uCurrentAsid);
3251	AssertRC(rc);
3252	}
3253
3254
3255	/**
3256	* Flushes the guest TLB entry based on CPU capabilities.
3257	*
3258	* @param pHostCpu The HM physical-CPU structure.
3259	* @param pVCpu The cross context virtual CPU structure.
3260	* @param pVmcsInfo The VMCS info. object.
3261	*
3262	* @remarks Called with interrupts disabled.
3263	*/
3264	static void hmR0VmxFlushTaggedTlb(PHMPHYSCPU pHostCpu, PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
3265	{
3266	#ifdef HMVMX_ALWAYS_FLUSH_TLB
3267	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
3268	#endif
3269	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3270	switch (pVM->hmr0.s.vmx.enmTlbFlushType)
3271	{
3272	case VMXTLBFLUSHTYPE_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pHostCpu, pVCpu, pVmcsInfo); break;
3273	case VMXTLBFLUSHTYPE_EPT: hmR0VmxFlushTaggedTlbEpt(pHostCpu, pVCpu, pVmcsInfo); break;
3274	case VMXTLBFLUSHTYPE_VPID: hmR0VmxFlushTaggedTlbVpid(pHostCpu, pVCpu); break;
3275	case VMXTLBFLUSHTYPE_NONE: hmR0VmxFlushTaggedTlbNone(pHostCpu, pVCpu); break;
3276	default:
3277	AssertMsgFailed(("Invalid flush-tag function identifier\n"));
3278	break;
3279	}
3280	/* Don't assert that VMCPU_FF_TLB_FLUSH should no longer be pending. It can be set by other EMTs. */
3281	}
3282
3283
3284	/**
3285	* Sets up the appropriate tagged TLB-flush level and handler for flushing guest
3286	* TLB entries from the host TLB before VM-entry.
3287	*
3288	* @returns VBox status code.
3289	* @param pVM The cross context VM structure.
3290	*/
3291	static int hmR0VmxSetupTaggedTlb(PVMCC pVM)
3292	{
3293	/*
3294	* Determine optimal flush type for nested paging.
3295	* We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup
3296	* unrestricted guest execution (see hmR3InitFinalizeR0()).
3297	*/
3298	if (pVM->hmr0.s.fNestedPaging)
3299	{
3300	if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
3301	{
3302	if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
3303	pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_SINGLE_CONTEXT;
3304	else if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
3305	pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_ALL_CONTEXTS;
3306	else
3307	{
3308	/* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
3309	pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
3310	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED;
3311	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3312	}
3313
3314	/* Make sure the write-back cacheable memory type for EPT is supported. */
3315	if (RT_UNLIKELY(!(g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
3316	{
3317	pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
3318	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_EPT_MEM_TYPE_NOT_WB;
3319	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3320	}
3321
3322	/* EPT requires a page-walk length of 4. */
3323	if (RT_UNLIKELY(!(g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
3324	{
3325	pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
3326	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED;
3327	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3328	}
3329	}
3330	else
3331	{
3332	/* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
3333	pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
3334	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_EPT_INVEPT_UNAVAILABLE;
3335	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3336	}
3337	}
3338
3339	/*
3340	* Determine optimal flush type for VPID.
3341	*/
3342	if (pVM->hmr0.s.vmx.fVpid)
3343	{
3344	if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
3345	{
3346	if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
3347	pVM->hmr0.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_SINGLE_CONTEXT;
3348	else if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
3349	pVM->hmr0.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_ALL_CONTEXTS;
3350	else
3351	{
3352	/* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
3353	if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
3354	LogRelFunc(("Only INDIV_ADDR supported. Ignoring VPID.\n"));
3355	if (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
3356	LogRelFunc(("Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
3357	pVM->hmr0.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
3358	pVM->hmr0.s.vmx.fVpid = false;
3359	}
3360	}
3361	else
3362	{
3363	/* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
3364	Log4Func(("VPID supported without INVEPT support. Ignoring VPID.\n"));
3365	pVM->hmr0.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
3366	pVM->hmr0.s.vmx.fVpid = false;
3367	}
3368	}
3369
3370	/*
3371	* Setup the handler for flushing tagged-TLBs.
3372	*/
3373	if (pVM->hmr0.s.fNestedPaging && pVM->hmr0.s.vmx.fVpid)
3374	pVM->hmr0.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT_VPID;
3375	else if (pVM->hmr0.s.fNestedPaging)
3376	pVM->hmr0.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT;
3377	else if (pVM->hmr0.s.vmx.fVpid)
3378	pVM->hmr0.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_VPID;
3379	else
3380	pVM->hmr0.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_NONE;
3381
3382
3383	/*
3384	* Copy out the result to ring-3.
3385	*/
3386	pVM->hm.s.ForR3.vmx.fVpid = pVM->hmr0.s.vmx.fVpid;
3387	pVM->hm.s.ForR3.vmx.enmTlbFlushType = pVM->hmr0.s.vmx.enmTlbFlushType;
3388	pVM->hm.s.ForR3.vmx.enmTlbFlushEpt = pVM->hmr0.s.vmx.enmTlbFlushEpt;
3389	pVM->hm.s.ForR3.vmx.enmTlbFlushVpid = pVM->hmr0.s.vmx.enmTlbFlushVpid;
3390	return VINF_SUCCESS;
3391	}
3392
3393
3394	/**
3395	* Sets up the LBR MSR ranges based on the host CPU.
3396	*
3397	* @returns VBox status code.
3398	* @param pVM The cross context VM structure.
3399	*/
3400	static int hmR0VmxSetupLbrMsrRange(PVMCC pVM)
3401	{
3402	Assert(pVM->hmr0.s.vmx.fLbr);
3403	uint32_t idLbrFromIpMsrFirst;
3404	uint32_t idLbrFromIpMsrLast;
3405	uint32_t idLbrToIpMsrFirst;
3406	uint32_t idLbrToIpMsrLast;
3407	uint32_t idLbrTosMsr;
3408
3409	/*
3410	* Determine the LBR MSRs supported for this host CPU family and model.
3411	*
3412	* See Intel spec. 17.4.8 "LBR Stack".
3413	* See Intel "Model-Specific Registers" spec.
3414	*/
3415	uint32_t const uFamilyModel = (pVM->cpum.ro.HostFeatures.uFamily << 8)
3416	\| pVM->cpum.ro.HostFeatures.uModel;
3417	switch (uFamilyModel)
3418	{
3419	case 0x0f01: case 0x0f02:
3420	idLbrFromIpMsrFirst = MSR_P4_LASTBRANCH_0;
3421	idLbrFromIpMsrLast = MSR_P4_LASTBRANCH_3;
3422	idLbrToIpMsrFirst = 0x0;
3423	idLbrToIpMsrLast = 0x0;
3424	idLbrTosMsr = MSR_P4_LASTBRANCH_TOS;
3425	break;
3426
3427	case 0x065c: case 0x065f: case 0x064e: case 0x065e: case 0x068e:
3428	case 0x069e: case 0x0655: case 0x0666: case 0x067a: case 0x0667:
3429	case 0x066a: case 0x066c: case 0x067d: case 0x067e:
3430	idLbrFromIpMsrFirst = MSR_LASTBRANCH_0_FROM_IP;
3431	idLbrFromIpMsrLast = MSR_LASTBRANCH_31_FROM_IP;
3432	idLbrToIpMsrFirst = MSR_LASTBRANCH_0_TO_IP;
3433	idLbrToIpMsrLast = MSR_LASTBRANCH_31_TO_IP;
3434	idLbrTosMsr = MSR_LASTBRANCH_TOS;
3435	break;
3436
3437	case 0x063d: case 0x0647: case 0x064f: case 0x0656: case 0x063c:
3438	case 0x0645: case 0x0646: case 0x063f: case 0x062a: case 0x062d:
3439	case 0x063a: case 0x063e: case 0x061a: case 0x061e: case 0x061f:
3440	case 0x062e: case 0x0625: case 0x062c: case 0x062f:
3441	idLbrFromIpMsrFirst = MSR_LASTBRANCH_0_FROM_IP;
3442	idLbrFromIpMsrLast = MSR_LASTBRANCH_15_FROM_IP;
3443	idLbrToIpMsrFirst = MSR_LASTBRANCH_0_TO_IP;
3444	idLbrToIpMsrLast = MSR_LASTBRANCH_15_TO_IP;
3445	idLbrTosMsr = MSR_LASTBRANCH_TOS;
3446	break;
3447
3448	case 0x0617: case 0x061d: case 0x060f:
3449	idLbrFromIpMsrFirst = MSR_CORE2_LASTBRANCH_0_FROM_IP;
3450	idLbrFromIpMsrLast = MSR_CORE2_LASTBRANCH_3_FROM_IP;
3451	idLbrToIpMsrFirst = MSR_CORE2_LASTBRANCH_0_TO_IP;
3452	idLbrToIpMsrLast = MSR_CORE2_LASTBRANCH_3_TO_IP;
3453	idLbrTosMsr = MSR_CORE2_LASTBRANCH_TOS;
3454	break;
3455
3456	/* Atom and related microarchitectures we don't care about:
3457	case 0x0637: case 0x064a: case 0x064c: case 0x064d: case 0x065a:
3458	case 0x065d: case 0x061c: case 0x0626: case 0x0627: case 0x0635:
3459	case 0x0636: */
3460	/* All other CPUs: */
3461	default:
3462	{
3463	LogRelFunc(("Could not determine LBR stack size for the CPU model %#x\n", uFamilyModel));
3464	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_LBR_STACK_SIZE_UNKNOWN;
3465	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3466	}
3467	}
3468
3469	/*
3470	* Validate.
3471	*/
3472	uint32_t const cLbrStack = idLbrFromIpMsrLast - idLbrFromIpMsrFirst + 1;
3473	PCVMCPU pVCpu0 = VMCC_GET_CPU_0(pVM);
3474	AssertCompile( RT_ELEMENTS(pVCpu0->hm.s.vmx.VmcsInfo.au64LbrFromIpMsr)
3475	== RT_ELEMENTS(pVCpu0->hm.s.vmx.VmcsInfo.au64LbrToIpMsr));
3476	if (cLbrStack > RT_ELEMENTS(pVCpu0->hm.s.vmx.VmcsInfo.au64LbrFromIpMsr))
3477	{
3478	LogRelFunc(("LBR stack size of the CPU (%u) exceeds our buffer size\n", cLbrStack));
3479	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_LBR_STACK_SIZE_OVERFLOW;
3480	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3481	}
3482	NOREF(pVCpu0);
3483
3484	/*
3485	* Update the LBR info. to the VM struct. for use later.
3486	*/
3487	pVM->hmr0.s.vmx.idLbrTosMsr = idLbrTosMsr;
3488
3489	pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst = pVM->hmr0.s.vmx.idLbrFromIpMsrFirst = idLbrFromIpMsrFirst;
3490	pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast = pVM->hmr0.s.vmx.idLbrFromIpMsrLast = idLbrFromIpMsrLast;
3491
3492	pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst = pVM->hmr0.s.vmx.idLbrToIpMsrFirst = idLbrToIpMsrFirst;
3493	pVM->hm.s.ForR3.vmx.idLbrToIpMsrLast = pVM->hmr0.s.vmx.idLbrToIpMsrLast = idLbrToIpMsrLast;
3494	return VINF_SUCCESS;
3495	}
3496
3497
3498	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3499	/**
3500	* Sets up the shadow VMCS fields arrays.
3501	*
3502	* This function builds arrays of VMCS fields to sync the shadow VMCS later while
3503	* executing the guest.
3504	*
3505	* @returns VBox status code.
3506	* @param pVM The cross context VM structure.
3507	*/
3508	static int hmR0VmxSetupShadowVmcsFieldsArrays(PVMCC pVM)
3509	{
3510	/*
3511	* Paranoia. Ensure we haven't exposed the VMWRITE-All VMX feature to the guest
3512	* when the host does not support it.
3513	*/
3514	bool const fGstVmwriteAll = pVM->cpum.ro.GuestFeatures.fVmxVmwriteAll;
3515	if ( !fGstVmwriteAll
3516	\|\| (g_HmMsrs.u.vmx.u64Misc & VMX_MISC_VMWRITE_ALL))
3517	{ /* likely. */ }
3518	else
3519	{
3520	LogRelFunc(("VMX VMWRITE-All feature exposed to the guest but host CPU does not support it!\n"));
3521	VMCC_GET_CPU_0(pVM)->hm.s.u32HMError = VMX_UFC_GST_HOST_VMWRITE_ALL;
3522	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3523	}
3524
3525	uint32_t const cVmcsFields = RT_ELEMENTS(g_aVmcsFields);
3526	uint32_t cRwFields = 0;
3527	uint32_t cRoFields = 0;
3528	for (uint32_t i = 0; i < cVmcsFields; i++)
3529	{
3530	VMXVMCSFIELD VmcsField;
3531	VmcsField.u = g_aVmcsFields[i];
3532
3533	/*
3534	* We will be writing "FULL" (64-bit) fields while syncing the shadow VMCS.
3535	* Therefore, "HIGH" (32-bit portion of 64-bit) fields must not be included
3536	* in the shadow VMCS fields array as they would be redundant.
3537	*
3538	* If the VMCS field depends on a CPU feature that is not exposed to the guest,
3539	* we must not include it in the shadow VMCS fields array. Guests attempting to
3540	* VMREAD/VMWRITE such VMCS fields would cause a VM-exit and we shall emulate
3541	* the required behavior.
3542	*/
3543	if ( VmcsField.n.fAccessType == VMX_VMCSFIELD_ACCESS_FULL
3544	&& CPUMIsGuestVmxVmcsFieldValid(pVM, VmcsField.u))
3545	{
3546	/*
3547	* Read-only fields are placed in a separate array so that while syncing shadow
3548	* VMCS fields later (which is more performance critical) we can avoid branches.
3549	*
3550	* However, if the guest can write to all fields (including read-only fields),
3551	* we treat it a as read/write field. Otherwise, writing to these fields would
3552	* cause a VMWRITE instruction error while syncing the shadow VMCS.
3553	*/
3554	if ( fGstVmwriteAll
3555	\|\| !VMXIsVmcsFieldReadOnly(VmcsField.u))
3556	pVM->hmr0.s.vmx.paShadowVmcsFields[cRwFields++] = VmcsField.u;
3557	else
3558	pVM->hmr0.s.vmx.paShadowVmcsRoFields[cRoFields++] = VmcsField.u;
3559	}
3560	}
3561
3562	/* Update the counts. */
3563	pVM->hmr0.s.vmx.cShadowVmcsFields = cRwFields;
3564	pVM->hmr0.s.vmx.cShadowVmcsRoFields = cRoFields;
3565	return VINF_SUCCESS;
3566	}
3567
3568
3569	/**
3570	* Sets up the VMREAD and VMWRITE bitmaps.
3571	*
3572	* @param pVM The cross context VM structure.
3573	*/
3574	static void hmR0VmxSetupVmreadVmwriteBitmaps(PVMCC pVM)
3575	{
3576	/*
3577	* By default, ensure guest attempts to access any VMCS fields cause VM-exits.
3578	*/
3579	uint32_t const cbBitmap = X86_PAGE_4K_SIZE;
3580	uint8_t pbVmreadBitmap = (uint8_t )pVM->hmr0.s.vmx.pvVmreadBitmap;
3581	uint8_t pbVmwriteBitmap = (uint8_t )pVM->hmr0.s.vmx.pvVmwriteBitmap;
3582	ASMMemFill32(pbVmreadBitmap, cbBitmap, UINT32_C(0xffffffff));
3583	ASMMemFill32(pbVmwriteBitmap, cbBitmap, UINT32_C(0xffffffff));
3584
3585	/*
3586	* Skip intercepting VMREAD/VMWRITE to guest read/write fields in the
3587	* VMREAD and VMWRITE bitmaps.
3588	*/
3589	{
3590	uint32_t const *paShadowVmcsFields = pVM->hmr0.s.vmx.paShadowVmcsFields;
3591	uint32_t const cShadowVmcsFields = pVM->hmr0.s.vmx.cShadowVmcsFields;
3592	for (uint32_t i = 0; i < cShadowVmcsFields; i++)
3593	{
3594	uint32_t const uVmcsField = paShadowVmcsFields[i];
3595	Assert(!(uVmcsField & VMX_VMCSFIELD_RSVD_MASK));
3596	Assert(uVmcsField >> 3 < cbBitmap);
3597	ASMBitClear(pbVmreadBitmap + (uVmcsField >> 3), uVmcsField & 7);
3598	ASMBitClear(pbVmwriteBitmap + (uVmcsField >> 3), uVmcsField & 7);
3599	}
3600	}
3601
3602	/*
3603	* Skip intercepting VMREAD for guest read-only fields in the VMREAD bitmap
3604	* if the host supports VMWRITE to all supported VMCS fields.
3605	*/
3606	if (g_HmMsrs.u.vmx.u64Misc & VMX_MISC_VMWRITE_ALL)
3607	{
3608	uint32_t const *paShadowVmcsRoFields = pVM->hmr0.s.vmx.paShadowVmcsRoFields;
3609	uint32_t const cShadowVmcsRoFields = pVM->hmr0.s.vmx.cShadowVmcsRoFields;
3610	for (uint32_t i = 0; i < cShadowVmcsRoFields; i++)
3611	{
3612	uint32_t const uVmcsField = paShadowVmcsRoFields[i];
3613	Assert(!(uVmcsField & VMX_VMCSFIELD_RSVD_MASK));
3614	Assert(uVmcsField >> 3 < cbBitmap);
3615	ASMBitClear(pbVmreadBitmap + (uVmcsField >> 3), uVmcsField & 7);
3616	}
3617	}
3618	}
3619	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
3620
3621
3622	/**
3623	* Sets up the virtual-APIC page address for the VMCS.
3624	*
3625	* @param pVmcsInfo The VMCS info. object.
3626	*/
3627	DECLINLINE(void) hmR0VmxSetupVmcsVirtApicAddr(PCVMXVMCSINFO pVmcsInfo)
3628	{
3629	RTHCPHYS const HCPhysVirtApic = pVmcsInfo->HCPhysVirtApic;
3630	Assert(HCPhysVirtApic != NIL_RTHCPHYS);
3631	Assert(!(HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
3632	int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, HCPhysVirtApic);
3633	AssertRC(rc);
3634	}
3635
3636
3637	/**
3638	* Sets up the MSR-bitmap address for the VMCS.
3639	*
3640	* @param pVmcsInfo The VMCS info. object.
3641	*/
3642	DECLINLINE(void) hmR0VmxSetupVmcsMsrBitmapAddr(PCVMXVMCSINFO pVmcsInfo)
3643	{
3644	RTHCPHYS const HCPhysMsrBitmap = pVmcsInfo->HCPhysMsrBitmap;
3645	Assert(HCPhysMsrBitmap != NIL_RTHCPHYS);
3646	Assert(!(HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
3647	int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, HCPhysMsrBitmap);
3648	AssertRC(rc);
3649	}
3650
3651
3652	/**
3653	* Sets up the APIC-access page address for the VMCS.
3654	*
3655	* @param pVCpu The cross context virtual CPU structure.
3656	*/
3657	DECLINLINE(void) hmR0VmxSetupVmcsApicAccessAddr(PVMCPUCC pVCpu)
3658	{
3659	RTHCPHYS const HCPhysApicAccess = pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.HCPhysApicAccess;
3660	Assert(HCPhysApicAccess != NIL_RTHCPHYS);
3661	Assert(!(HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
3662	int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, HCPhysApicAccess);
3663	AssertRC(rc);
3664	}
3665
3666	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3667
3668	/**
3669	* Sets up the VMREAD bitmap address for the VMCS.
3670	*
3671	* @param pVCpu The cross context virtual CPU structure.
3672	*/
3673	DECLINLINE(void) hmR0VmxSetupVmcsVmreadBitmapAddr(PVMCPUCC pVCpu)
3674	{
3675	RTHCPHYS const HCPhysVmreadBitmap = pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.HCPhysVmreadBitmap;
3676	Assert(HCPhysVmreadBitmap != NIL_RTHCPHYS);
3677	Assert(!(HCPhysVmreadBitmap & 0xfff)); /* Bits 11:0 MBZ. */
3678	int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL, HCPhysVmreadBitmap);
3679	AssertRC(rc);
3680	}
3681
3682
3683	/**
3684	* Sets up the VMWRITE bitmap address for the VMCS.
3685	*
3686	* @param pVCpu The cross context virtual CPU structure.
3687	*/
3688	DECLINLINE(void) hmR0VmxSetupVmcsVmwriteBitmapAddr(PVMCPUCC pVCpu)
3689	{
3690	RTHCPHYS const HCPhysVmwriteBitmap = pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.HCPhysVmwriteBitmap;
3691	Assert(HCPhysVmwriteBitmap != NIL_RTHCPHYS);
3692	Assert(!(HCPhysVmwriteBitmap & 0xfff)); /* Bits 11:0 MBZ. */
3693	int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL, HCPhysVmwriteBitmap);
3694	AssertRC(rc);
3695	}
3696
3697	#endif
3698
3699	/**
3700	* Sets up the VM-entry MSR load, VM-exit MSR-store and VM-exit MSR-load addresses
3701	* in the VMCS.
3702	*
3703	* @returns VBox status code.
3704	* @param pVmcsInfo The VMCS info. object.
3705	*/
3706	DECLINLINE(int) hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(PVMXVMCSINFO pVmcsInfo)
3707	{
3708	RTHCPHYS const HCPhysGuestMsrLoad = pVmcsInfo->HCPhysGuestMsrLoad;
3709	Assert(HCPhysGuestMsrLoad != NIL_RTHCPHYS);
3710	Assert(!(HCPhysGuestMsrLoad & 0xf)); /* Bits 3:0 MBZ. */
3711
3712	RTHCPHYS const HCPhysGuestMsrStore = pVmcsInfo->HCPhysGuestMsrStore;
3713	Assert(HCPhysGuestMsrStore != NIL_RTHCPHYS);
3714	Assert(!(HCPhysGuestMsrStore & 0xf)); /* Bits 3:0 MBZ. */
3715
3716	RTHCPHYS const HCPhysHostMsrLoad = pVmcsInfo->HCPhysHostMsrLoad;
3717	Assert(HCPhysHostMsrLoad != NIL_RTHCPHYS);
3718	Assert(!(HCPhysHostMsrLoad & 0xf)); /* Bits 3:0 MBZ. */
3719
3720	int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, HCPhysGuestMsrLoad); AssertRC(rc);
3721	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, HCPhysGuestMsrStore); AssertRC(rc);
3722	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, HCPhysHostMsrLoad); AssertRC(rc);
3723	return VINF_SUCCESS;
3724	}
3725
3726
3727	/**
3728	* Sets up MSR permissions in the MSR bitmap of a VMCS info. object.
3729	*
3730	* @param pVCpu The cross context virtual CPU structure.
3731	* @param pVmcsInfo The VMCS info. object.
3732	*/
3733	static void hmR0VmxSetupVmcsMsrPermissions(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
3734	{
3735	Assert(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
3736
3737	/*
3738	* By default, ensure guest attempts to access any MSR cause VM-exits.
3739	* This shall later be relaxed for specific MSRs as necessary.
3740	*
3741	* Note: For nested-guests, the entire bitmap will be merged prior to
3742	* executing the nested-guest using hardware-assisted VMX and hence there
3743	* is no need to perform this operation. See hmR0VmxMergeMsrBitmapNested.
3744	*/
3745	Assert(pVmcsInfo->pvMsrBitmap);
3746	ASMMemFill32(pVmcsInfo->pvMsrBitmap, X86_PAGE_4K_SIZE, UINT32_C(0xffffffff));
3747
3748	/*
3749	* The guest can access the following MSRs (read, write) without causing
3750	* VM-exits; they are loaded/stored automatically using fields in the VMCS.
3751	*/
3752	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3753	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_IA32_SYSENTER_CS, VMXMSRPM_ALLOW_RD_WR);
3754	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_IA32_SYSENTER_ESP, VMXMSRPM_ALLOW_RD_WR);
3755	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_IA32_SYSENTER_EIP, VMXMSRPM_ALLOW_RD_WR);
3756	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_K8_GS_BASE, VMXMSRPM_ALLOW_RD_WR);
3757	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_K8_FS_BASE, VMXMSRPM_ALLOW_RD_WR);
3758
3759	/*
3760	* The IA32_PRED_CMD and IA32_FLUSH_CMD MSRs are write-only and has no state
3761	* associated with then. We never need to intercept access (writes need to be
3762	* executed without causing a VM-exit, reads will #GP fault anyway).
3763	*
3764	* The IA32_SPEC_CTRL MSR is read/write and has state. We allow the guest to
3765	* read/write them. We swap the guest/host MSR value using the
3766	* auto-load/store MSR area.
3767	*/
3768	if (pVM->cpum.ro.GuestFeatures.fIbpb)
3769	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_IA32_PRED_CMD, VMXMSRPM_ALLOW_RD_WR);
3770	if (pVM->cpum.ro.GuestFeatures.fFlushCmd)
3771	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_IA32_FLUSH_CMD, VMXMSRPM_ALLOW_RD_WR);
3772	if (pVM->cpum.ro.GuestFeatures.fIbrs)
3773	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_IA32_SPEC_CTRL, VMXMSRPM_ALLOW_RD_WR);
3774
3775	/*
3776	* Allow full read/write access for the following MSRs (mandatory for VT-x)
3777	* required for 64-bit guests.
3778	*/
3779	if (pVM->hmr0.s.fAllow64BitGuests)
3780	{
3781	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_K8_LSTAR, VMXMSRPM_ALLOW_RD_WR);
3782	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_K6_STAR, VMXMSRPM_ALLOW_RD_WR);
3783	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_K8_SF_MASK, VMXMSRPM_ALLOW_RD_WR);
3784	hmR0VmxSetMsrPermission(pVCpu, pVmcsInfo, false, MSR_K8_KERNEL_GS_BASE, VMXMSRPM_ALLOW_RD_WR);
3785	}
3786
3787	/*
3788	* IA32_EFER MSR is always intercepted, see @bugref{9180#c37}.
3789	*/
3790	#ifdef VBOX_STRICT
3791	Assert(pVmcsInfo->pvMsrBitmap);
3792	uint32_t const fMsrpmEfer = CPUMGetVmxMsrPermission(pVmcsInfo->pvMsrBitmap, MSR_K6_EFER);
3793	Assert(fMsrpmEfer == VMXMSRPM_EXIT_RD_WR);
3794	#endif
3795	}
3796
3797
3798	/**
3799	* Sets up pin-based VM-execution controls in the VMCS.
3800	*
3801	* @returns VBox status code.
3802	* @param pVCpu The cross context virtual CPU structure.
3803	* @param pVmcsInfo The VMCS info. object.
3804	*/
3805	static int hmR0VmxSetupVmcsPinCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
3806	{
3807	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3808	uint32_t fVal = g_HmMsrs.u.vmx.PinCtls.n.allowed0; /* Bits set here must always be set. */
3809	uint32_t const fZap = g_HmMsrs.u.vmx.PinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
3810
3811	fVal \|= VMX_PIN_CTLS_EXT_INT_EXIT /* External interrupts cause a VM-exit. */
3812	\| VMX_PIN_CTLS_NMI_EXIT; /* Non-maskable interrupts (NMIs) cause a VM-exit. */
3813
3814	if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
3815	fVal \|= VMX_PIN_CTLS_VIRT_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
3816
3817	/* Enable the VMX-preemption timer. */
3818	if (pVM->hmr0.s.vmx.fUsePreemptTimer)
3819	{
3820	Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
3821	fVal \|= VMX_PIN_CTLS_PREEMPT_TIMER;
3822	}
3823
3824	#if 0
3825	/* Enable posted-interrupt processing. */
3826	if (pVM->hm.s.fPostedIntrs)
3827	{
3828	Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT);
3829	Assert(g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
3830	fVal \|= VMX_PIN_CTLS_POSTED_INT;
3831	}
3832	#endif
3833
3834	if ((fVal & fZap) != fVal)
3835	{
3836	LogRelFunc(("Invalid pin-based VM-execution controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
3837	g_HmMsrs.u.vmx.PinCtls.n.allowed0, fVal, fZap));
3838	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
3839	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3840	}
3841
3842	/* Commit it to the VMCS and update our cache. */
3843	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, fVal);
3844	AssertRC(rc);
3845	pVmcsInfo->u32PinCtls = fVal;
3846
3847	return VINF_SUCCESS;
3848	}
3849
3850
3851	/**
3852	* Sets up secondary processor-based VM-execution controls in the VMCS.
3853	*
3854	* @returns VBox status code.
3855	* @param pVCpu The cross context virtual CPU structure.
3856	* @param pVmcsInfo The VMCS info. object.
3857	*/
3858	static int hmR0VmxSetupVmcsProcCtls2(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
3859	{
3860	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3861	uint32_t fVal = g_HmMsrs.u.vmx.ProcCtls2.n.allowed0; /* Bits set here must be set in the VMCS. */
3862	uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3863
3864	/* WBINVD causes a VM-exit. */
3865	if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
3866	fVal \|= VMX_PROC_CTLS2_WBINVD_EXIT;
3867
3868	/* Enable EPT (aka nested-paging). */
3869	if (pVM->hmr0.s.fNestedPaging)
3870	fVal \|= VMX_PROC_CTLS2_EPT;
3871
3872	/* Enable the INVPCID instruction if we expose it to the guest and is supported
3873	by the hardware. Without this, guest executing INVPCID would cause a #UD. */
3874	if ( pVM->cpum.ro.GuestFeatures.fInvpcid
3875	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID))
3876	fVal \|= VMX_PROC_CTLS2_INVPCID;
3877
3878	/* Enable VPID. */
3879	if (pVM->hmr0.s.vmx.fVpid)
3880	fVal \|= VMX_PROC_CTLS2_VPID;
3881
3882	/* Enable unrestricted guest execution. */
3883	if (pVM->hmr0.s.vmx.fUnrestrictedGuest)
3884	fVal \|= VMX_PROC_CTLS2_UNRESTRICTED_GUEST;
3885
3886	#if 0
3887	if (pVM->hm.s.fVirtApicRegs)
3888	{
3889	/* Enable APIC-register virtualization. */
3890	Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
3891	fVal \|= VMX_PROC_CTLS2_APIC_REG_VIRT;
3892
3893	/* Enable virtual-interrupt delivery. */
3894	Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
3895	fVal \|= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
3896	}
3897	#endif
3898
3899	/* Virtualize-APIC accesses if supported by the CPU. The virtual-APIC page is
3900	where the TPR shadow resides. */
3901	/** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
3902	* done dynamically. */
3903	if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
3904	{
3905	fVal \|= VMX_PROC_CTLS2_VIRT_APIC_ACCESS;
3906	hmR0VmxSetupVmcsApicAccessAddr(pVCpu);
3907	}
3908
3909	/* Enable the RDTSCP instruction if we expose it to the guest and is supported
3910	by the hardware. Without this, guest executing RDTSCP would cause a #UD. */
3911	if ( pVM->cpum.ro.GuestFeatures.fRdTscP
3912	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP))
3913	fVal \|= VMX_PROC_CTLS2_RDTSCP;
3914
3915	/* Enable Pause-Loop exiting. */
3916	if ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
3917	&& pVM->hm.s.vmx.cPleGapTicks
3918	&& pVM->hm.s.vmx.cPleWindowTicks)
3919	{
3920	fVal \|= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT;
3921
3922	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks); AssertRC(rc);
3923	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks); AssertRC(rc);
3924	}
3925
3926	if ((fVal & fZap) != fVal)
3927	{
3928	LogRelFunc(("Invalid secondary processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
3929	g_HmMsrs.u.vmx.ProcCtls2.n.allowed0, fVal, fZap));
3930	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
3931	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3932	}
3933
3934	/* Commit it to the VMCS and update our cache. */
3935	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, fVal);
3936	AssertRC(rc);
3937	pVmcsInfo->u32ProcCtls2 = fVal;
3938
3939	return VINF_SUCCESS;
3940	}
3941
3942
3943	/**
3944	* Sets up processor-based VM-execution controls in the VMCS.
3945	*
3946	* @returns VBox status code.
3947	* @param pVCpu The cross context virtual CPU structure.
3948	* @param pVmcsInfo The VMCS info. object.
3949	*/
3950	static int hmR0VmxSetupVmcsProcCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
3951	{
3952	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3953	uint32_t fVal = g_HmMsrs.u.vmx.ProcCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
3954	uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3955
3956	fVal \|= VMX_PROC_CTLS_HLT_EXIT /* HLT causes a VM-exit. */
3957	\| VMX_PROC_CTLS_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
3958	\| VMX_PROC_CTLS_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
3959	\| VMX_PROC_CTLS_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
3960	\| VMX_PROC_CTLS_RDPMC_EXIT /* RDPMC causes a VM-exit. */
3961	\| VMX_PROC_CTLS_MONITOR_EXIT /* MONITOR causes a VM-exit. */
3962	\| VMX_PROC_CTLS_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
3963
3964	/* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
3965	if ( !(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
3966	\|\| (g_HmMsrs.u.vmx.ProcCtls.n.allowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
3967	{
3968	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
3969	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3970	}
3971
3972	/* Without nested paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
3973	if (!pVM->hmr0.s.fNestedPaging)
3974	{
3975	Assert(!pVM->hmr0.s.vmx.fUnrestrictedGuest);
3976	fVal \|= VMX_PROC_CTLS_INVLPG_EXIT
3977	\| VMX_PROC_CTLS_CR3_LOAD_EXIT
3978	\| VMX_PROC_CTLS_CR3_STORE_EXIT;
3979	}
3980
3981	/* Use TPR shadowing if supported by the CPU. */
3982	if ( PDMHasApic(pVM)
3983	&& (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
3984	{
3985	fVal \|= VMX_PROC_CTLS_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
3986	/* CR8 writes cause a VM-exit based on TPR threshold. */
3987	Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
3988	Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
3989	hmR0VmxSetupVmcsVirtApicAddr(pVmcsInfo);
3990	}
3991	else
3992	{
3993	/* Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is
3994	invalid on 32-bit Intel CPUs. Set this control only for 64-bit guests. */
3995	if (pVM->hmr0.s.fAllow64BitGuests)
3996	fVal \|= VMX_PROC_CTLS_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
3997	\| VMX_PROC_CTLS_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
3998	}
3999
4000	/* Use MSR-bitmaps if supported by the CPU. */
4001	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
4002	{
4003	fVal \|= VMX_PROC_CTLS_USE_MSR_BITMAPS;
4004	hmR0VmxSetupVmcsMsrBitmapAddr(pVmcsInfo);
4005	}
4006
4007	/* Use the secondary processor-based VM-execution controls if supported by the CPU. */
4008	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
4009	fVal \|= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
4010
4011	if ((fVal & fZap) != fVal)
4012	{
4013	LogRelFunc(("Invalid processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
4014	g_HmMsrs.u.vmx.ProcCtls.n.allowed0, fVal, fZap));
4015	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
4016	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
4017	}
4018
4019	/* Commit it to the VMCS and update our cache. */
4020	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, fVal);
4021	AssertRC(rc);
4022	pVmcsInfo->u32ProcCtls = fVal;
4023
4024	/* Set up MSR permissions that don't change through the lifetime of the VM. */
4025	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
4026	hmR0VmxSetupVmcsMsrPermissions(pVCpu, pVmcsInfo);
4027
4028	/* Set up secondary processor-based VM-execution controls if the CPU supports it. */
4029	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
4030	return hmR0VmxSetupVmcsProcCtls2(pVCpu, pVmcsInfo);
4031
4032	/* Sanity check, should not really happen. */
4033	if (RT_LIKELY(!pVM->hmr0.s.vmx.fUnrestrictedGuest))
4034	{ /* likely */ }
4035	else
4036	{
4037	pVCpu->hm.s.u32HMError = VMX_UFC_INVALID_UX_COMBO;
4038	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
4039	}
4040
4041	/* Old CPUs without secondary processor-based VM-execution controls would end up here. */
4042	return VINF_SUCCESS;
4043	}
4044
4045
4046	/**
4047	* Sets up miscellaneous (everything other than Pin, Processor and secondary
4048	* Processor-based VM-execution) control fields in the VMCS.
4049	*
4050	* @returns VBox status code.
4051	* @param pVCpu The cross context virtual CPU structure.
4052	* @param pVmcsInfo The VMCS info. object.
4053	*/
4054	static int hmR0VmxSetupVmcsMiscCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
4055	{
4056	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4057	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fUseVmcsShadowing)
4058	{
4059	hmR0VmxSetupVmcsVmreadBitmapAddr(pVCpu);
4060	hmR0VmxSetupVmcsVmwriteBitmapAddr(pVCpu);
4061	}
4062	#endif
4063
4064	Assert(pVmcsInfo->u64VmcsLinkPtr == NIL_RTHCPHYS);
4065	int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS);
4066	AssertRC(rc);
4067
4068	rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pVmcsInfo);
4069	if (RT_SUCCESS(rc))
4070	{
4071	uint64_t const u64Cr0Mask = hmR0VmxGetFixedCr0Mask(pVCpu);
4072	uint64_t const u64Cr4Mask = hmR0VmxGetFixedCr4Mask(pVCpu);
4073
4074	rc = VMXWriteVmcsNw(VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask); AssertRC(rc);
4075	rc = VMXWriteVmcsNw(VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask); AssertRC(rc);
4076
4077	pVmcsInfo->u64Cr0Mask = u64Cr0Mask;
4078	pVmcsInfo->u64Cr4Mask = u64Cr4Mask;
4079
4080	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fLbr)
4081	{
4082	rc = VMXWriteVmcsNw(VMX_VMCS64_GUEST_DEBUGCTL_FULL, MSR_IA32_DEBUGCTL_LBR);
4083	AssertRC(rc);
4084	}
4085	return VINF_SUCCESS;
4086	}
4087	else
4088	LogRelFunc(("Failed to initialize VMCS auto-load/store MSR addresses. rc=%Rrc\n", rc));
4089	return rc;
4090	}
4091
4092
4093	/**
4094	* Sets up the initial exception bitmap in the VMCS based on static conditions.
4095	*
4096	* We shall setup those exception intercepts that don't change during the
4097	* lifetime of the VM here. The rest are done dynamically while loading the
4098	* guest state.
4099	*
4100	* @param pVCpu The cross context virtual CPU structure.
4101	* @param pVmcsInfo The VMCS info. object.
4102	*/
4103	static void hmR0VmxSetupVmcsXcptBitmap(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
4104	{
4105	/*
4106	* The following exceptions are always intercepted:
4107	*
4108	* #AC - To prevent the guest from hanging the CPU and for dealing with
4109	* split-lock detecting host configs.
4110	* #DB - To maintain the DR6 state even when intercepting DRx reads/writes and
4111	* recursive #DBs can cause a CPU hang.
4112	* #PF - To sync our shadow page tables when nested-paging is not used.
4113	*/
4114	bool const fNestedPaging = pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging;
4115	uint32_t const uXcptBitmap = RT_BIT(X86_XCPT_AC)
4116	\| RT_BIT(X86_XCPT_DB)
4117	\| (fNestedPaging ? 0 : RT_BIT(X86_XCPT_PF));
4118
4119	/* Commit it to the VMCS. */
4120	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
4121	AssertRC(rc);
4122
4123	/* Update our cache of the exception bitmap. */
4124	pVmcsInfo->u32XcptBitmap = uXcptBitmap;
4125	}
4126
4127
4128	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4129	/**
4130	* Sets up the VMCS for executing a nested-guest using hardware-assisted VMX.
4131	*
4132	* @returns VBox status code.
4133	* @param pVmcsInfo The VMCS info. object.
4134	*/
4135	static int hmR0VmxSetupVmcsCtlsNested(PVMXVMCSINFO pVmcsInfo)
4136	{
4137	Assert(pVmcsInfo->u64VmcsLinkPtr == NIL_RTHCPHYS);
4138	int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS);
4139	AssertRC(rc);
4140
4141	rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pVmcsInfo);
4142	if (RT_SUCCESS(rc))
4143	{
4144	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
4145	hmR0VmxSetupVmcsMsrBitmapAddr(pVmcsInfo);
4146
4147	/* Paranoia - We've not yet initialized these, they shall be done while merging the VMCS. */
4148	Assert(!pVmcsInfo->u64Cr0Mask);
4149	Assert(!pVmcsInfo->u64Cr4Mask);
4150	return VINF_SUCCESS;
4151	}
4152	LogRelFunc(("Failed to set up the VMCS link pointer in the nested-guest VMCS. rc=%Rrc\n", rc));
4153	return rc;
4154	}
4155	#endif
4156
4157
4158	/**
4159	* Sets pfnStartVm to the best suited variant.
4160	*
4161	* This must be called whenever anything changes relative to the hmR0VmXStartVm
4162	* variant selection:
4163	* - pVCpu->hm.s.fLoadSaveGuestXcr0
4164	* - HM_WSF_IBPB_ENTRY in pVCpu->hmr0.s.fWorldSwitcher
4165	* - HM_WSF_IBPB_EXIT in pVCpu->hmr0.s.fWorldSwitcher
4166	* - Perhaps: CPUMIsGuestFPUStateActive() (windows only)
4167	* - Perhaps: CPUMCTX.fXStateMask (windows only)
4168	*
4169	* We currently ASSUME that neither HM_WSF_IBPB_ENTRY nor HM_WSF_IBPB_EXIT
4170	* cannot be changed at runtime.
4171	*/
4172	static void hmR0VmxUpdateStartVmFunction(PVMCPUCC pVCpu)
4173	{
4174	static const struct CLANGWORKAROUND { PFNHMVMXSTARTVM pfn; } s_aHmR0VmxStartVmFunctions[] =
4175	{
4176	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit },
4177	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit },
4178	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit },
4179	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit },
4180	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit },
4181	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit },
4182	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit },
4183	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit },
4184	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit },
4185	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit },
4186	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit },
4187	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit },
4188	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit },
4189	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit },
4190	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit },
4191	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit },
4192	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit },
4193	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit },
4194	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit },
4195	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit },
4196	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit },
4197	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit },
4198	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit },
4199	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit },
4200	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit },
4201	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit },
4202	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit },
4203	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit },
4204	{ hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit },
4205	{ hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit },
4206	{ hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit },
4207	{ hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit },
4208	};
4209	uintptr_t const idx = (pVCpu->hmr0.s.fLoadSaveGuestXcr0 ? 1 : 0)
4210	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_ENTRY ? 2 : 0)
4211	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_L1D_ENTRY ? 4 : 0)
4212	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_MDS_ENTRY ? 8 : 0)
4213	\| (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_IBPB_EXIT ? 16 : 0);
4214	PFNHMVMXSTARTVM const pfnStartVm = s_aHmR0VmxStartVmFunctions[idx].pfn;
4215	if (pVCpu->hmr0.s.vmx.pfnStartVm != pfnStartVm)
4216	pVCpu->hmr0.s.vmx.pfnStartVm = pfnStartVm;
4217	}
4218
4219
4220	/**
4221	* Selector FNHMSVMVMRUN implementation.
4222	*/
4223	static DECLCALLBACK(int) hmR0VmxStartVmSelector(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume)
4224	{
4225	hmR0VmxUpdateStartVmFunction(pVCpu);
4226	return pVCpu->hmr0.s.vmx.pfnStartVm(pVmcsInfo, pVCpu, fResume);
4227	}
4228
4229
4230	/**
4231	* Sets up the VMCS for executing a guest (or nested-guest) using hardware-assisted
4232	* VMX.
4233	*
4234	* @returns VBox status code.
4235	* @param pVCpu The cross context virtual CPU structure.
4236	* @param pVmcsInfo The VMCS info. object.
4237	* @param fIsNstGstVmcs Whether this is a nested-guest VMCS.
4238	*/
4239	static int hmR0VmxSetupVmcs(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, bool fIsNstGstVmcs)
4240	{
4241	Assert(pVmcsInfo->pvVmcs);
4242	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4243
4244	/* Set the CPU specified revision identifier at the beginning of the VMCS structure. */
4245	(uint32_t )pVmcsInfo->pvVmcs = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID);
4246	const char * const pszVmcs = fIsNstGstVmcs ? "nested-guest VMCS" : "guest VMCS";
4247
4248	LogFlowFunc(("\n"));
4249
4250	/*
4251	* Initialize the VMCS using VMCLEAR before loading the VMCS.
4252	* See Intel spec. 31.6 "Preparation And Launching A Virtual Machine".
4253	*/
4254	int rc = hmR0VmxClearVmcs(pVmcsInfo);
4255	if (RT_SUCCESS(rc))
4256	{
4257	rc = hmR0VmxLoadVmcs(pVmcsInfo);
4258	if (RT_SUCCESS(rc))
4259	{
4260	/*
4261	* Initialize the hardware-assisted VMX execution handler for guest and nested-guest VMCS.
4262	* The host is always 64-bit since we no longer support 32-bit hosts.
4263	* Currently we have just a single handler for all guest modes as well, see @bugref{6208#c73}.
4264	*/
4265	if (!fIsNstGstVmcs)
4266	{
4267	rc = hmR0VmxSetupVmcsPinCtls(pVCpu, pVmcsInfo);
4268	if (RT_SUCCESS(rc))
4269	{
4270	rc = hmR0VmxSetupVmcsProcCtls(pVCpu, pVmcsInfo);
4271	if (RT_SUCCESS(rc))
4272	{
4273	rc = hmR0VmxSetupVmcsMiscCtls(pVCpu, pVmcsInfo);
4274	if (RT_SUCCESS(rc))
4275	{
4276	hmR0VmxSetupVmcsXcptBitmap(pVCpu, pVmcsInfo);
4277	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4278	/*
4279	* If a shadow VMCS is allocated for the VMCS info. object, initialize the
4280	* VMCS revision ID and shadow VMCS indicator bit. Also, clear the VMCS
4281	* making it fit for use when VMCS shadowing is later enabled.
4282	*/
4283	if (pVmcsInfo->pvShadowVmcs)
4284	{
4285	VMXVMCSREVID VmcsRevId;
4286	VmcsRevId.u = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID);
4287	VmcsRevId.n.fIsShadowVmcs = 1;
4288	(uint32_t )pVmcsInfo->pvShadowVmcs = VmcsRevId.u;
4289	rc = hmR0VmxClearShadowVmcs(pVmcsInfo);
4290	if (RT_SUCCESS(rc))
4291	{ /* likely */ }
4292	else
4293	LogRelFunc(("Failed to initialize shadow VMCS. rc=%Rrc\n", rc));
4294	}
4295	#endif
4296	}
4297	else
4298	LogRelFunc(("Failed to setup miscellaneous controls. rc=%Rrc\n", rc));
4299	}
4300	else
4301	LogRelFunc(("Failed to setup processor-based VM-execution controls. rc=%Rrc\n", rc));
4302	}
4303	else
4304	LogRelFunc(("Failed to setup pin-based controls. rc=%Rrc\n", rc));
4305	}
4306	else
4307	{
4308	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4309	rc = hmR0VmxSetupVmcsCtlsNested(pVmcsInfo);
4310	if (RT_SUCCESS(rc))
4311	{ /* likely */ }
4312	else
4313	LogRelFunc(("Failed to initialize nested-guest VMCS. rc=%Rrc\n", rc));
4314	#else
4315	AssertFailed();
4316	#endif
4317	}
4318	}
4319	else
4320	LogRelFunc(("Failed to load the %s. rc=%Rrc\n", rc, pszVmcs));
4321	}
4322	else
4323	LogRelFunc(("Failed to clear the %s. rc=%Rrc\n", rc, pszVmcs));
4324
4325	/* Sync any CPU internal VMCS data back into our VMCS in memory. */
4326	if (RT_SUCCESS(rc))
4327	{
4328	rc = hmR0VmxClearVmcs(pVmcsInfo);
4329	if (RT_SUCCESS(rc))
4330	{ /* likely */ }
4331	else
4332	LogRelFunc(("Failed to clear the %s post setup. rc=%Rrc\n", rc, pszVmcs));
4333	}
4334
4335	/*
4336	* Update the last-error record both for failures and success, so we
4337	* can propagate the status code back to ring-3 for diagnostics.
4338	*/
4339	hmR0VmxUpdateErrorRecord(pVCpu, rc);
4340	NOREF(pszVmcs);
4341	return rc;
4342	}
4343
4344
4345	/**
4346	* Does global VT-x initialization (called during module initialization).
4347	*
4348	* @returns VBox status code.
4349	*/
4350	VMMR0DECL(int) VMXR0GlobalInit(void)
4351	{
4352	#ifdef HMVMX_USE_FUNCTION_TABLE
4353	AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_aVMExitHandlers));
4354	# ifdef VBOX_STRICT
4355	for (unsigned i = 0; i < RT_ELEMENTS(g_aVMExitHandlers); i++)
4356	Assert(g_aVMExitHandlers[i].pfn);
4357	# endif
4358	#endif
4359	return VINF_SUCCESS;
4360	}
4361
4362
4363	/**
4364	* Does global VT-x termination (called during module termination).
4365	*/
4366	VMMR0DECL(void) VMXR0GlobalTerm()
4367	{
4368	/* Nothing to do currently. */
4369	}
4370
4371
4372	/**
4373	* Sets up and activates VT-x on the current CPU.
4374	*
4375	* @returns VBox status code.
4376	* @param pHostCpu The HM physical-CPU structure.
4377	* @param pVM The cross context VM structure. Can be
4378	* NULL after a host resume operation.
4379	* @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
4380	* fEnabledByHost is @c true).
4381	* @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
4382	* @a fEnabledByHost is @c true).
4383	* @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
4384	* enable VT-x on the host.
4385	* @param pHwvirtMsrs Pointer to the hardware-virtualization MSRs.
4386	*/
4387	VMMR0DECL(int) VMXR0EnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
4388	PCSUPHWVIRTMSRS pHwvirtMsrs)
4389	{
4390	AssertPtr(pHostCpu);
4391	AssertPtr(pHwvirtMsrs);
4392	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4393
4394	/* Enable VT-x if it's not already enabled by the host. */
4395	if (!fEnabledByHost)
4396	{
4397	int rc = hmR0VmxEnterRootMode(pHostCpu, pVM, HCPhysCpuPage, pvCpuPage);
4398	if (RT_FAILURE(rc))
4399	return rc;
4400	}
4401
4402	/*
4403	* Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been
4404	* using EPTPs) so we don't retain any stale guest-physical mappings which won't get
4405	* invalidated when flushing by VPID.
4406	*/
4407	if (pHwvirtMsrs->u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
4408	{
4409	hmR0VmxFlushEpt(NULL /* pVCpu /, NULL / pVmcsInfo */, VMXTLBFLUSHEPT_ALL_CONTEXTS);
4410	pHostCpu->fFlushAsidBeforeUse = false;
4411	}
4412	else
4413	pHostCpu->fFlushAsidBeforeUse = true;
4414
4415	/* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
4416	++pHostCpu->cTlbFlushes;
4417
4418	return VINF_SUCCESS;
4419	}
4420
4421
4422	/**
4423	* Deactivates VT-x on the current CPU.
4424	*
4425	* @returns VBox status code.
4426	* @param pHostCpu The HM physical-CPU structure.
4427	* @param pvCpuPage Pointer to the VMXON region.
4428	* @param HCPhysCpuPage Physical address of the VMXON region.
4429	*
4430	* @remarks This function should never be called when SUPR0EnableVTx() or
4431	* similar was used to enable VT-x on the host.
4432	*/
4433	VMMR0DECL(int) VMXR0DisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
4434	{
4435	RT_NOREF2(pvCpuPage, HCPhysCpuPage);
4436
4437	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4438	return hmR0VmxLeaveRootMode(pHostCpu);
4439	}
4440
4441
4442	/**
4443	* Does per-VM VT-x initialization.
4444	*
4445	* @returns VBox status code.
4446	* @param pVM The cross context VM structure.
4447	*/
4448	VMMR0DECL(int) VMXR0InitVM(PVMCC pVM)
4449	{
4450	AssertPtr(pVM);
4451	LogFlowFunc(("pVM=%p\n", pVM));
4452
4453	hmR0VmxStructsInit(pVM);
4454	int rc = hmR0VmxStructsAlloc(pVM);
4455	if (RT_FAILURE(rc))
4456	{
4457	LogRelFunc(("Failed to allocated VMX structures. rc=%Rrc\n", rc));
4458	return rc;
4459	}
4460
4461	/* Setup the crash dump page. */
4462	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4463	strcpy((char *)pVM->hmr0.s.vmx.pbScratch, "SCRATCH Magic");
4464	(uint64_t )(pVM->hmr0.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
4465	#endif
4466	return VINF_SUCCESS;
4467	}
4468
4469
4470	/**
4471	* Does per-VM VT-x termination.
4472	*
4473	* @returns VBox status code.
4474	* @param pVM The cross context VM structure.
4475	*/
4476	VMMR0DECL(int) VMXR0TermVM(PVMCC pVM)
4477	{
4478	AssertPtr(pVM);
4479	LogFlowFunc(("pVM=%p\n", pVM));
4480
4481	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4482	if (pVM->hmr0.s.vmx.pbScratch)
4483	RT_BZERO(pVM->hmr0.s.vmx.pbScratch, X86_PAGE_4K_SIZE);
4484	#endif
4485	hmR0VmxStructsFree(pVM);
4486	return VINF_SUCCESS;
4487	}
4488
4489
4490	/**
4491	* Sets up the VM for execution using hardware-assisted VMX.
4492	* This function is only called once per-VM during initialization.
4493	*
4494	* @returns VBox status code.
4495	* @param pVM The cross context VM structure.
4496	*/
4497	VMMR0DECL(int) VMXR0SetupVM(PVMCC pVM)
4498	{
4499	AssertPtr(pVM);
4500	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4501
4502	LogFlowFunc(("pVM=%p\n", pVM));
4503
4504	/*
4505	* At least verify if VMX is enabled, since we can't check if we're in VMX root mode or not
4506	* without causing a #GP.
4507	*/
4508	RTCCUINTREG const uHostCr4 = ASMGetCR4();
4509	if (RT_LIKELY(uHostCr4 & X86_CR4_VMXE))
4510	{ /* likely */ }
4511	else
4512	return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
4513
4514	/*
4515	* Check that nested paging is supported if enabled and copy over the flag to the
4516	* ring-0 only structure.
4517	*/
4518	bool const fNestedPaging = pVM->hm.s.fNestedPagingCfg;
4519	AssertReturn( !fNestedPaging
4520	\|\| (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT), /** @todo use a ring-0 copy of ProcCtls2.n.allowed1 */
4521	VERR_INCOMPATIBLE_CONFIG);
4522	pVM->hmr0.s.fNestedPaging = fNestedPaging;
4523	pVM->hmr0.s.fAllow64BitGuests = pVM->hm.s.fAllow64BitGuestsCfg;
4524
4525	/*
4526	* Without unrestricted guest execution, pRealModeTSS and pNonPagingModeEPTPageTable must
4527	* always be allocated. We no longer support the highly unlikely case of unrestricted guest
4528	* without pRealModeTSS, see hmR3InitFinalizeR0Intel().
4529	*/
4530	bool const fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuestCfg;
4531	AssertReturn( !fUnrestrictedGuest
4532	\|\| ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
4533	&& fNestedPaging),
4534	VERR_INCOMPATIBLE_CONFIG);
4535	if ( !fUnrestrictedGuest
4536	&& ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
4537	\|\| !pVM->hm.s.vmx.pRealModeTSS))
4538	{
4539	LogRelFunc(("Invalid real-on-v86 state.\n"));
4540	return VERR_INTERNAL_ERROR;
4541	}
4542	pVM->hmr0.s.vmx.fUnrestrictedGuest = fUnrestrictedGuest;
4543
4544	/* Initialize these always, see hmR3InitFinalizeR0().*/
4545	pVM->hm.s.ForR3.vmx.enmTlbFlushEpt = pVM->hmr0.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NONE;
4546	pVM->hm.s.ForR3.vmx.enmTlbFlushVpid = pVM->hmr0.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NONE;
4547
4548	/* Setup the tagged-TLB flush handlers. */
4549	int rc = hmR0VmxSetupTaggedTlb(pVM);
4550	if (RT_FAILURE(rc))
4551	{
4552	LogRelFunc(("Failed to setup tagged TLB. rc=%Rrc\n", rc));
4553	return rc;
4554	}
4555
4556	/* Determine LBR capabilities. */
4557	pVM->hmr0.s.vmx.fLbr = pVM->hm.s.vmx.fLbrCfg;
4558	if (pVM->hmr0.s.vmx.fLbr)
4559	{
4560	rc = hmR0VmxSetupLbrMsrRange(pVM);
4561	if (RT_FAILURE(rc))
4562	{
4563	LogRelFunc(("Failed to setup LBR MSR range. rc=%Rrc\n", rc));
4564	return rc;
4565	}
4566	}
4567
4568	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4569	/* Setup the shadow VMCS fields array and VMREAD/VMWRITE bitmaps. */
4570	if (pVM->hmr0.s.vmx.fUseVmcsShadowing)
4571	{
4572	rc = hmR0VmxSetupShadowVmcsFieldsArrays(pVM);
4573	if (RT_SUCCESS(rc))
4574	hmR0VmxSetupVmreadVmwriteBitmaps(pVM);
4575	else
4576	{
4577	LogRelFunc(("Failed to setup shadow VMCS fields arrays. rc=%Rrc\n", rc));
4578	return rc;
4579	}
4580	}
4581	#endif
4582
4583	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4584	{
4585	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
4586	Log4Func(("pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
4587
4588	pVCpu->hmr0.s.vmx.pfnStartVm = hmR0VmxStartVmSelector;
4589
4590	rc = hmR0VmxSetupVmcs(pVCpu, &pVCpu->hmr0.s.vmx.VmcsInfo, false /* fIsNstGstVmcs */);
4591	if (RT_SUCCESS(rc))
4592	{
4593	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4594	if (pVM->cpum.ro.GuestFeatures.fVmx)
4595	{
4596	rc = hmR0VmxSetupVmcs(pVCpu, &pVCpu->hmr0.s.vmx.VmcsInfoNstGst, true /* fIsNstGstVmcs */);
4597	if (RT_SUCCESS(rc))
4598	{ /* likely */ }
4599	else
4600	{
4601	LogRelFunc(("Nested-guest VMCS setup failed. rc=%Rrc\n", rc));
4602	return rc;
4603	}
4604	}
4605	#endif
4606	}
4607	else
4608	{
4609	LogRelFunc(("VMCS setup failed. rc=%Rrc\n", rc));
4610	return rc;
4611	}
4612	}
4613
4614	return VINF_SUCCESS;
4615	}
4616
4617
4618	/**
4619	* Saves the host control registers (CR0, CR3, CR4) into the host-state area in
4620	* the VMCS.
4621	* @returns CR4 for passing along to hmR0VmxExportHostSegmentRegs.
4622	*/
4623	static uint64_t hmR0VmxExportHostControlRegs(void)
4624	{
4625	int rc = VMXWriteVmcsNw(VMX_VMCS_HOST_CR0, ASMGetCR0()); AssertRC(rc);
4626	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_CR3, ASMGetCR3()); AssertRC(rc);
4627	uint64_t uHostCr4 = ASMGetCR4();
4628	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_CR4, uHostCr4); AssertRC(rc);
4629	return uHostCr4;
4630	}
4631
4632
4633	/**
4634	* Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
4635	* the host-state area in the VMCS.
4636	*
4637	* @returns VBox status code.
4638	* @param pVCpu The cross context virtual CPU structure.
4639	* @param uHostCr4 The host CR4 value.
4640	*/
4641	static int hmR0VmxExportHostSegmentRegs(PVMCPUCC pVCpu, uint64_t uHostCr4)
4642	{
4643	/*
4644	* If we've executed guest code using hardware-assisted VMX, the host-state bits
4645	* will be messed up. We should -not- save the messed up state without restoring
4646	* the original host-state, see @bugref{7240}.
4647	*
4648	* This apparently can happen (most likely the FPU changes), deal with it rather than
4649	* asserting. Was observed booting Solaris 10u10 32-bit guest.
4650	*/
4651	if (pVCpu->hmr0.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
4652	{
4653	Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hmr0.s.vmx.fRestoreHostFlags,
4654	pVCpu->idCpu));
4655	VMXRestoreHostState(pVCpu->hmr0.s.vmx.fRestoreHostFlags, &pVCpu->hmr0.s.vmx.RestoreHost);
4656	pVCpu->hmr0.s.vmx.fRestoreHostFlags = 0;
4657	}
4658
4659	/*
4660	* Get all the host info.
4661	* ASSUME it is safe to use rdfsbase and friends if the CR4.FSGSBASE bit is set
4662	* without also checking the cpuid bit.
4663	*/
4664	uint32_t fRestoreHostFlags;
4665	#if RT_INLINE_ASM_EXTERNAL
4666	if (uHostCr4 & X86_CR4_FSGSBASE)
4667	{
4668	hmR0VmxExportHostSegmentRegsAsmHlp(&pVCpu->hmr0.s.vmx.RestoreHost, true /fHaveFsGsBase/);
4669	fRestoreHostFlags = VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE;
4670	}
4671	else
4672	{
4673	hmR0VmxExportHostSegmentRegsAsmHlp(&pVCpu->hmr0.s.vmx.RestoreHost, false /fHaveFsGsBase/);
4674	fRestoreHostFlags = 0;
4675	}
4676	RTSEL uSelES = pVCpu->hmr0.s.vmx.RestoreHost.uHostSelES;
4677	RTSEL uSelDS = pVCpu->hmr0.s.vmx.RestoreHost.uHostSelDS;
4678	RTSEL uSelFS = pVCpu->hmr0.s.vmx.RestoreHost.uHostSelFS;
4679	RTSEL uSelGS = pVCpu->hmr0.s.vmx.RestoreHost.uHostSelGS;
4680	#else
4681	pVCpu->hmr0.s.vmx.RestoreHost.uHostSelTR = ASMGetTR();
4682	pVCpu->hmr0.s.vmx.RestoreHost.uHostSelSS = ASMGetSS();
4683	pVCpu->hmr0.s.vmx.RestoreHost.uHostSelCS = ASMGetCS();
4684	ASMGetGDTR((PRTGDTR)&pVCpu->hmr0.s.vmx.RestoreHost.HostGdtr);
4685	ASMGetIDTR((PRTIDTR)&pVCpu->hmr0.s.vmx.RestoreHost.HostIdtr);
4686	if (uHostCr4 & X86_CR4_FSGSBASE)
4687	{
4688	pVCpu->hmr0.s.vmx.RestoreHost.uHostFSBase = ASMGetFSBase();
4689	pVCpu->hmr0.s.vmx.RestoreHost.uHostGSBase = ASMGetGSBase();
4690	fRestoreHostFlags = VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE;
4691	}
4692	else
4693	{
4694	pVCpu->hmr0.s.vmx.RestoreHost.uHostFSBase = ASMRdMsr(MSR_K8_FS_BASE);
4695	pVCpu->hmr0.s.vmx.RestoreHost.uHostGSBase = ASMRdMsr(MSR_K8_GS_BASE);
4696	fRestoreHostFlags = 0;
4697	}
4698	RTSEL uSelES, uSelDS, uSelFS, uSelGS;
4699	pVCpu->hmr0.s.vmx.RestoreHost.uHostSelDS = uSelDS = ASMGetDS();
4700	pVCpu->hmr0.s.vmx.RestoreHost.uHostSelES = uSelES = ASMGetES();
4701	pVCpu->hmr0.s.vmx.RestoreHost.uHostSelFS = uSelFS = ASMGetFS();
4702	pVCpu->hmr0.s.vmx.RestoreHost.uHostSelGS = uSelGS = ASMGetGS();
4703	#endif
4704
4705	/*
4706	* Determine if the host segment registers are suitable for VT-x. Otherwise use zero to
4707	* gain VM-entry and restore them before we get preempted.
4708	*
4709	* See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
4710	*/
4711	RTSEL const uSelAll = uSelFS \| uSelGS \| uSelES \| uSelDS;
4712	if (uSelAll & (X86_SEL_RPL \| X86_SEL_LDT))
4713	{
4714	if (!(uSelAll & X86_SEL_LDT))
4715	{
4716	#define VMXLOCAL_ADJUST_HOST_SEG(a_Seg, a_uVmcsVar) \
4717	do { \
4718	(a_uVmcsVar) = pVCpu->hmr0.s.vmx.RestoreHost.uHostSel##a_Seg; \
4719	if ((a_uVmcsVar) & X86_SEL_RPL) \
4720	{ \
4721	fRestoreHostFlags \|= VMX_RESTORE_HOST_SEL_##a_Seg; \
4722	(a_uVmcsVar) = 0; \
4723	} \
4724	} while (0)
4725	VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
4726	VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
4727	VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
4728	VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
4729	#undef VMXLOCAL_ADJUST_HOST_SEG
4730	}
4731	else
4732	{
4733	#define VMXLOCAL_ADJUST_HOST_SEG(a_Seg, a_uVmcsVar) \
4734	do { \
4735	(a_uVmcsVar) = pVCpu->hmr0.s.vmx.RestoreHost.uHostSel##a_Seg; \
4736	if ((a_uVmcsVar) & (X86_SEL_RPL \| X86_SEL_LDT)) \
4737	{ \
4738	if (!((a_uVmcsVar) & X86_SEL_LDT)) \
4739	fRestoreHostFlags \|= VMX_RESTORE_HOST_SEL_##a_Seg; \
4740	else \
4741	{ \
4742	uint32_t const fAttr = ASMGetSegAttr(a_uVmcsVar); \
4743	if ((fAttr & X86_DESC_P) && fAttr != UINT32_MAX) \
4744	fRestoreHostFlags \|= VMX_RESTORE_HOST_SEL_##a_Seg; \
4745	} \
4746	(a_uVmcsVar) = 0; \
4747	} \
4748	} while (0)
4749	VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
4750	VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
4751	VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
4752	VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
4753	#undef VMXLOCAL_ADJUST_HOST_SEG
4754	}
4755	}
4756
4757	/* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
4758	Assert(!(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelTR & X86_SEL_RPL)); Assert(!(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelTR & X86_SEL_LDT)); Assert(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelTR);
4759	Assert(!(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelCS & X86_SEL_RPL)); Assert(!(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelCS & X86_SEL_LDT)); Assert(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelCS);
4760	Assert(!(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelSS & X86_SEL_RPL)); Assert(!(pVCpu->hmr0.s.vmx.RestoreHost.uHostSelSS & X86_SEL_LDT));
4761	Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
4762	Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
4763	Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
4764	Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
4765
4766	/*
4767	* Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps
4768	* them to the maximum limit (0xffff) on every VM-exit.
4769	*/
4770	if (pVCpu->hmr0.s.vmx.RestoreHost.HostGdtr.cb != 0xffff)
4771	fRestoreHostFlags \|= VMX_RESTORE_HOST_GDTR;
4772
4773	/*
4774	* IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT" and
4775	* Intel spec. 6.2 "Exception and Interrupt Vectors".) Therefore if the host has the limit
4776	* as 0xfff, VT-x bloating the limit to 0xffff shouldn't cause any different CPU behavior.
4777	* However, several hosts either insists on 0xfff being the limit (Windows Patch Guard) or
4778	* uses the limit for other purposes (darwin puts the CPU ID in there but botches sidt
4779	* alignment in at least one consumer). So, we're only allowing the IDTR.LIMIT to be left
4780	* at 0xffff on hosts where we are sure it won't cause trouble.
4781	*/
4782	#if defined(RT_OS_LINUX) \|\| defined(RT_OS_SOLARIS)
4783	if (pVCpu->hmr0.s.vmx.RestoreHost.HostIdtr.cb < 0x0fff)
4784	#else
4785	if (pVCpu->hmr0.s.vmx.RestoreHost.HostIdtr.cb != 0xffff)
4786	#endif
4787	fRestoreHostFlags \|= VMX_RESTORE_HOST_IDTR;
4788
4789	/*
4790	* Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI
4791	* and RPL bits is effectively what the CPU does for "scaling by 8". TI is always 0 and
4792	* RPL should be too in most cases.
4793	*/
4794	RTSEL const uSelTR = pVCpu->hmr0.s.vmx.RestoreHost.uHostSelTR;
4795	AssertMsgReturn((uSelTR \| X86_SEL_RPL_LDT) <= pVCpu->hmr0.s.vmx.RestoreHost.HostGdtr.cb,
4796	("TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, pVCpu->hmr0.s.vmx.RestoreHost.HostGdtr.cb),
4797	VERR_VMX_INVALID_HOST_STATE);
4798
4799	PCX86DESCHC pDesc = (PCX86DESCHC)(pVCpu->hmr0.s.vmx.RestoreHost.HostGdtr.uAddr + (uSelTR & X86_SEL_MASK));
4800	uintptr_t const uTRBase = X86DESC64_BASE(pDesc);
4801
4802	/*
4803	* VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on
4804	* all VM-exits. The type is the same for 64-bit busy TSS[1]. The limit needs manual
4805	* restoration if the host has something else. Task switching is not supported in 64-bit
4806	* mode[2], but the limit still matters as IOPM is supported in 64-bit mode. Restoring the
4807	* limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
4808	*
4809	* [1] See Intel spec. 3.5 "System Descriptor Types".
4810	* [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
4811	*/
4812	Assert(pDesc->System.u4Type == 11);
4813	if ( pDesc->System.u16LimitLow != 0x67
4814	\|\| pDesc->System.u4LimitHigh)
4815	{
4816	fRestoreHostFlags \|= VMX_RESTORE_HOST_SEL_TR;
4817
4818	/* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */
4819	if (g_fHmHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)
4820	fRestoreHostFlags \|= VMX_RESTORE_HOST_GDT_READ_ONLY;
4821	if (g_fHmHostKernelFeatures & SUPKERNELFEATURES_GDT_NEED_WRITABLE)
4822	{
4823	/* The GDT is read-only but the writable GDT is available. */
4824	fRestoreHostFlags \|= VMX_RESTORE_HOST_GDT_NEED_WRITABLE;
4825	pVCpu->hmr0.s.vmx.RestoreHost.HostGdtrRw.cb = pVCpu->hmr0.s.vmx.RestoreHost.HostGdtr.cb;
4826	int rc = SUPR0GetCurrentGdtRw(&pVCpu->hmr0.s.vmx.RestoreHost.HostGdtrRw.uAddr);
4827	AssertRCReturn(rc, rc);
4828	}
4829	}
4830
4831	pVCpu->hmr0.s.vmx.fRestoreHostFlags = fRestoreHostFlags;
4832
4833	/*
4834	* Do all the VMCS updates in one block to assist nested virtualization.
4835	*/
4836	int rc;
4837	rc = VMXWriteVmcs16(VMX_VMCS16_HOST_CS_SEL, pVCpu->hmr0.s.vmx.RestoreHost.uHostSelCS); AssertRC(rc);
4838	rc = VMXWriteVmcs16(VMX_VMCS16_HOST_SS_SEL, pVCpu->hmr0.s.vmx.RestoreHost.uHostSelSS); AssertRC(rc);
4839	rc = VMXWriteVmcs16(VMX_VMCS16_HOST_DS_SEL, uSelDS); AssertRC(rc);
4840	rc = VMXWriteVmcs16(VMX_VMCS16_HOST_ES_SEL, uSelES); AssertRC(rc);
4841	rc = VMXWriteVmcs16(VMX_VMCS16_HOST_FS_SEL, uSelFS); AssertRC(rc);
4842	rc = VMXWriteVmcs16(VMX_VMCS16_HOST_GS_SEL, uSelGS); AssertRC(rc);
4843	rc = VMXWriteVmcs16(VMX_VMCS16_HOST_TR_SEL, pVCpu->hmr0.s.vmx.RestoreHost.uHostSelTR); AssertRC(rc);
4844	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_GDTR_BASE, pVCpu->hmr0.s.vmx.RestoreHost.HostGdtr.uAddr); AssertRC(rc);
4845	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_IDTR_BASE, pVCpu->hmr0.s.vmx.RestoreHost.HostIdtr.uAddr); AssertRC(rc);
4846	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_TR_BASE, uTRBase); AssertRC(rc);
4847	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_FS_BASE, pVCpu->hmr0.s.vmx.RestoreHost.uHostFSBase); AssertRC(rc);
4848	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_GS_BASE, pVCpu->hmr0.s.vmx.RestoreHost.uHostGSBase); AssertRC(rc);
4849
4850	return VINF_SUCCESS;
4851	}
4852
4853
4854	/**
4855	* Exports certain host MSRs in the VM-exit MSR-load area and some in the
4856	* host-state area of the VMCS.
4857	*
4858	* These MSRs will be automatically restored on the host after every successful
4859	* VM-exit.
4860	*
4861	* @param pVCpu The cross context virtual CPU structure.
4862	*
4863	* @remarks No-long-jump zone!!!
4864	*/
4865	static void hmR0VmxExportHostMsrs(PVMCPUCC pVCpu)
4866	{
4867	AssertPtr(pVCpu);
4868
4869	/*
4870	* Save MSRs that we restore lazily (due to preemption or transition to ring-3)
4871	* rather than swapping them on every VM-entry.
4872	*/
4873	hmR0VmxLazySaveHostMsrs(pVCpu);
4874
4875	/*
4876	* Host Sysenter MSRs.
4877	*/
4878	int rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)); AssertRC(rc);
4879	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP)); AssertRC(rc);
4880	rc = VMXWriteVmcsNw(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP)); AssertRC(rc);
4881
4882	/*
4883	* Host EFER MSR.
4884	*
4885	* If the CPU supports the newer VMCS controls for managing EFER, use it. Otherwise it's
4886	* done as part of auto-load/store MSR area in the VMCS, see hmR0VmxExportGuestMsrs().
4887	*/
4888	if (g_fHmVmxSupportsVmcsEfer)
4889	{
4890	rc = VMXWriteVmcs64(VMX_VMCS64_HOST_EFER_FULL, g_uHmVmxHostMsrEfer);
4891	AssertRC(rc);
4892	}
4893
4894	/** @todo IA32_PERF_GLOBALCTRL, IA32_PAT also see
4895	* hmR0VmxExportGuestEntryExitCtls(). */
4896	}
4897
4898
4899	/**
4900	* Figures out if we need to swap the EFER MSR which is particularly expensive.
4901	*
4902	* We check all relevant bits. For now, that's everything besides LMA/LME, as
4903	* these two bits are handled by VM-entry, see hmR0VMxExportGuestEntryExitCtls().
4904	*
4905	* @returns true if we need to load guest EFER, false otherwise.
4906	* @param pVCpu The cross context virtual CPU structure.
4907	* @param pVmxTransient The VMX-transient structure.
4908	*
4909	* @remarks Requires EFER, CR4.
4910	* @remarks No-long-jump zone!!!
4911	*/
4912	static bool hmR0VmxShouldSwapEferMsr(PCVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
4913	{
4914	#ifdef HMVMX_ALWAYS_SWAP_EFER
4915	RT_NOREF2(pVCpu, pVmxTransient);
4916	return true;
4917	#else
4918	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4919	uint64_t const u64HostEfer = g_uHmVmxHostMsrEfer;
4920	uint64_t const u64GuestEfer = pCtx->msrEFER;
4921
4922	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4923	/*
4924	* For nested-guests, we shall honor swapping the EFER MSR when requested by
4925	* the nested-guest.
4926	*/
4927	if ( pVmxTransient->fIsNestedGuest
4928	&& ( CPUMIsGuestVmxEntryCtlsSet(pCtx, VMX_ENTRY_CTLS_LOAD_EFER_MSR)
4929	\|\| CPUMIsGuestVmxExitCtlsSet(pCtx, VMX_EXIT_CTLS_SAVE_EFER_MSR)
4930	\|\| CPUMIsGuestVmxExitCtlsSet(pCtx, VMX_EXIT_CTLS_LOAD_EFER_MSR)))
4931	return true;
4932	# else
4933	RT_NOREF(pVmxTransient);
4934	#endif
4935
4936	/*
4937	* For 64-bit guests, if EFER.SCE bit differs, we need to swap the EFER MSR
4938	* to ensure that the guest's SYSCALL behaviour isn't broken, see @bugref{7386}.
4939	*/
4940	if ( CPUMIsGuestInLongModeEx(pCtx)
4941	&& (u64GuestEfer & MSR_K6_EFER_SCE) != (u64HostEfer & MSR_K6_EFER_SCE))
4942	return true;
4943
4944	/*
4945	* If the guest uses PAE and EFER.NXE bit differs, we need to swap the EFER MSR
4946	* as it affects guest paging. 64-bit paging implies CR4.PAE as well.
4947	*
4948	* See Intel spec. 4.5 "IA-32e Paging".
4949	* See Intel spec. 4.1.1 "Three Paging Modes".
4950	*
4951	* Verify that we always intercept CR4.PAE and CR0.PG bits, so we don't need to
4952	* import CR4 and CR0 from the VMCS here as those bits are always up to date.
4953	*/
4954	Assert(hmR0VmxGetFixedCr4Mask(pVCpu) & X86_CR4_PAE);
4955	Assert(hmR0VmxGetFixedCr0Mask(pVCpu) & X86_CR0_PG);
4956	if ( (pCtx->cr4 & X86_CR4_PAE)
4957	&& (pCtx->cr0 & X86_CR0_PG))
4958	{
4959	/*
4960	* If nested paging is not used, verify that the guest paging mode matches the
4961	* shadow paging mode which is/will be placed in the VMCS (which is what will
4962	* actually be used while executing the guest and not the CR4 shadow value).
4963	*/
4964	AssertMsg( pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging
4965	\|\| pVCpu->hm.s.enmShadowMode == PGMMODE_PAE
4966	\|\| pVCpu->hm.s.enmShadowMode == PGMMODE_PAE_NX
4967	\|\| pVCpu->hm.s.enmShadowMode == PGMMODE_AMD64
4968	\|\| pVCpu->hm.s.enmShadowMode == PGMMODE_AMD64_NX,
4969	("enmShadowMode=%u\n", pVCpu->hm.s.enmShadowMode));
4970	if ((u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE))
4971	{
4972	/* Verify that the host is NX capable. */
4973	Assert(pVCpu->CTX_SUFF(pVM)->cpum.ro.HostFeatures.fNoExecute);
4974	return true;
4975	}
4976	}
4977
4978	return false;
4979	#endif
4980	}
4981
4982
4983	/**
4984	* Exports the guest state with appropriate VM-entry and VM-exit controls in the
4985	* VMCS.
4986	*
4987	* This is typically required when the guest changes paging mode.
4988	*
4989	* @returns VBox status code.
4990	* @param pVCpu The cross context virtual CPU structure.
4991	* @param pVmxTransient The VMX-transient structure.
4992	*
4993	* @remarks Requires EFER.
4994	* @remarks No-long-jump zone!!!
4995	*/
4996	static int hmR0VmxExportGuestEntryExitCtls(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
4997	{
4998	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_ENTRY_EXIT_CTLS)
4999	{
5000	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
5001	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
5002
5003	/*
5004	* VM-entry controls.
5005	*/
5006	{
5007	uint32_t fVal = g_HmMsrs.u.vmx.EntryCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
5008	uint32_t const fZap = g_HmMsrs.u.vmx.EntryCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
5009
5010	/*
5011	* Load the guest debug controls (DR7 and IA32_DEBUGCTL MSR) on VM-entry.
5012	* The first VT-x capable CPUs only supported the 1-setting of this bit.
5013	*
5014	* For nested-guests, this is a mandatory VM-entry control. It's also
5015	* required because we do not want to leak host bits to the nested-guest.
5016	*/
5017	fVal \|= VMX_ENTRY_CTLS_LOAD_DEBUG;
5018
5019	/*
5020	* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry.
5021	*
5022	* For nested-guests, the "IA-32e mode guest" control we initialize with what is
5023	* required to get the nested-guest working with hardware-assisted VMX execution.
5024	* It depends on the nested-guest's IA32_EFER.LMA bit. Remember, a nested hypervisor
5025	* can skip intercepting changes to the EFER MSR. This is why it needs to be done
5026	* here rather than while merging the guest VMCS controls.
5027	*/
5028	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
5029	{
5030	Assert(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_LME);
5031	fVal \|= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
5032	}
5033	else
5034	Assert(!(fVal & VMX_ENTRY_CTLS_IA32E_MODE_GUEST));
5035
5036	/*
5037	* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it.
5038	*
5039	* For nested-guests, we use the "load IA32_EFER" if the hardware supports it,
5040	* regardless of whether the nested-guest VMCS specifies it because we are free to
5041	* load whatever MSRs we require and we do not need to modify the guest visible copy
5042	* of the VM-entry MSR load area.
5043	*/
5044	if ( g_fHmVmxSupportsVmcsEfer
5045	&& hmR0VmxShouldSwapEferMsr(pVCpu, pVmxTransient))
5046	fVal \|= VMX_ENTRY_CTLS_LOAD_EFER_MSR;
5047	else
5048	Assert(!(fVal & VMX_ENTRY_CTLS_LOAD_EFER_MSR));
5049
5050	/*
5051	* The following should -not- be set (since we're not in SMM mode):
5052	* - VMX_ENTRY_CTLS_ENTRY_TO_SMM
5053	* - VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON
5054	*/
5055
5056	/** @todo VMX_ENTRY_CTLS_LOAD_PERF_MSR,
5057	* VMX_ENTRY_CTLS_LOAD_PAT_MSR. */
5058
5059	if ((fVal & fZap) == fVal)
5060	{ /* likely */ }
5061	else
5062	{
5063	Log4Func(("Invalid VM-entry controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
5064	g_HmMsrs.u.vmx.EntryCtls.n.allowed0, fVal, fZap));
5065	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
5066	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
5067	}
5068
5069	/* Commit it to the VMCS. */
5070	if (pVmcsInfo->u32EntryCtls != fVal)
5071	{
5072	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, fVal);
5073	AssertRC(rc);
5074	pVmcsInfo->u32EntryCtls = fVal;
5075	}
5076	}
5077
5078	/*
5079	* VM-exit controls.
5080	*/
5081	{
5082	uint32_t fVal = g_HmMsrs.u.vmx.ExitCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
5083	uint32_t const fZap = g_HmMsrs.u.vmx.ExitCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
5084
5085	/*
5086	* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only
5087	* supported the 1-setting of this bit.
5088	*
5089	* For nested-guests, we set the "save debug controls" as the converse
5090	* "load debug controls" is mandatory for nested-guests anyway.
5091	*/
5092	fVal \|= VMX_EXIT_CTLS_SAVE_DEBUG;
5093
5094	/*
5095	* Set the host long mode active (EFER.LMA) bit (which Intel calls
5096	* "Host address-space size") if necessary. On VM-exit, VT-x sets both the
5097	* host EFER.LMA and EFER.LME bit to this value. See assertion in
5098	* hmR0VmxExportHostMsrs().
5099	*
5100	* For nested-guests, we always set this bit as we do not support 32-bit
5101	* hosts.
5102	*/
5103	fVal \|= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
5104
5105	/*
5106	* If the VMCS EFER MSR fields are supported by the hardware, we use it.
5107	*
5108	* For nested-guests, we should use the "save IA32_EFER" control if we also
5109	* used the "load IA32_EFER" control while exporting VM-entry controls.
5110	*/
5111	if ( g_fHmVmxSupportsVmcsEfer
5112	&& hmR0VmxShouldSwapEferMsr(pVCpu, pVmxTransient))
5113	{
5114	fVal \|= VMX_EXIT_CTLS_SAVE_EFER_MSR
5115	\| VMX_EXIT_CTLS_LOAD_EFER_MSR;
5116	}
5117
5118	/*
5119	* Enable saving of the VMX-preemption timer value on VM-exit.
5120	* For nested-guests, currently not exposed/used.
5121	*/
5122	/** @todo r=bird: Measure performance hit because of this vs. always rewriting
5123	* the timer value. */
5124	if (pVM->hmr0.s.vmx.fUsePreemptTimer)
5125	{
5126	Assert(g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
5127	fVal \|= VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER;
5128	}
5129
5130	/* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
5131	Assert(!(fVal & VMX_EXIT_CTLS_ACK_EXT_INT));
5132
5133	/** @todo VMX_EXIT_CTLS_LOAD_PERF_MSR,
5134	* VMX_EXIT_CTLS_SAVE_PAT_MSR,
5135	* VMX_EXIT_CTLS_LOAD_PAT_MSR. */
5136
5137	if ((fVal & fZap) == fVal)
5138	{ /* likely */ }
5139	else
5140	{
5141	Log4Func(("Invalid VM-exit controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%R#X32\n",
5142	g_HmMsrs.u.vmx.ExitCtls.n.allowed0, fVal, fZap));
5143	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
5144	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
5145	}
5146
5147	/* Commit it to the VMCS. */
5148	if (pVmcsInfo->u32ExitCtls != fVal)
5149	{
5150	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, fVal);
5151	AssertRC(rc);
5152	pVmcsInfo->u32ExitCtls = fVal;
5153	}
5154	}
5155
5156	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_ENTRY_EXIT_CTLS);
5157	}
5158	return VINF_SUCCESS;
5159	}
5160
5161
5162	/**
5163	* Sets the TPR threshold in the VMCS.
5164	*
5165	* @param pVmcsInfo The VMCS info. object.
5166	* @param u32TprThreshold The TPR threshold (task-priority class only).
5167	*/
5168	DECLINLINE(void) hmR0VmxApicSetTprThreshold(PVMXVMCSINFO pVmcsInfo, uint32_t u32TprThreshold)
5169	{
5170	Assert(!(u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)); /* Bits 31:4 MBZ. */
5171	Assert(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
5172	RT_NOREF(pVmcsInfo);
5173	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
5174	AssertRC(rc);
5175	}
5176
5177
5178	/**
5179	* Exports the guest APIC TPR state into the VMCS.
5180	*
5181	* @param pVCpu The cross context virtual CPU structure.
5182	* @param pVmxTransient The VMX-transient structure.
5183	*
5184	* @remarks No-long-jump zone!!!
5185	*/
5186	static void hmR0VmxExportGuestApicTpr(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
5187	{
5188	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
5189	{
5190	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
5191
5192	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
5193	if (!pVmxTransient->fIsNestedGuest)
5194	{
5195	if ( PDMHasApic(pVCpu->CTX_SUFF(pVM))
5196	&& APICIsEnabled(pVCpu))
5197	{
5198	/*
5199	* Setup TPR shadowing.
5200	*/
5201	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
5202	{
5203	bool fPendingIntr = false;
5204	uint8_t u8Tpr = 0;
5205	uint8_t u8PendingIntr = 0;
5206	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
5207	AssertRC(rc);
5208
5209	/*
5210	* If there are interrupts pending but masked by the TPR, instruct VT-x to
5211	* cause a TPR-below-threshold VM-exit when the guest lowers its TPR below the
5212	* priority of the pending interrupt so we can deliver the interrupt. If there
5213	* are no interrupts pending, set threshold to 0 to not cause any
5214	* TPR-below-threshold VM-exits.
5215	*/
5216	uint32_t u32TprThreshold = 0;
5217	if (fPendingIntr)
5218	{
5219	/* Bits 3:0 of the TPR threshold field correspond to bits 7:4 of the TPR
5220	(which is the Task-Priority Class). */
5221	const uint8_t u8PendingPriority = u8PendingIntr >> 4;
5222	const uint8_t u8TprPriority = u8Tpr >> 4;
5223	if (u8PendingPriority <= u8TprPriority)
5224	u32TprThreshold = u8PendingPriority;
5225	}
5226
5227	hmR0VmxApicSetTprThreshold(pVmcsInfo, u32TprThreshold);
5228	}
5229	}
5230	}
5231	/* else: the TPR threshold has already been updated while merging the nested-guest VMCS. */
5232	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
5233	}
5234	}
5235
5236
5237	/**
5238	* Gets the guest interruptibility-state and updates related force-flags.
5239	*
5240	* @returns Guest's interruptibility-state.
5241	* @param pVCpu The cross context virtual CPU structure.
5242	*
5243	* @remarks No-long-jump zone!!!
5244	*/
5245	static uint32_t hmR0VmxGetGuestIntrStateAndUpdateFFs(PVMCPUCC pVCpu)
5246	{
5247	/*
5248	* Check if we should inhibit interrupt delivery due to instructions like STI and MOV SS.
5249	*/
5250	uint32_t fIntrState = 0;
5251	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
5252	{
5253	/* If inhibition is active, RIP and RFLAGS should've been imported from the VMCS already. */
5254	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
5255
5256	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5257	if (pCtx->rip == EMGetInhibitInterruptsPC(pVCpu))
5258	{
5259	if (pCtx->eflags.Bits.u1IF)
5260	fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
5261	else
5262	fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
5263	}
5264	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
5265	{
5266	/*
5267	* We can clear the inhibit force flag as even if we go back to the recompiler
5268	* without executing guest code in VT-x, the flag's condition to be cleared is
5269	* met and thus the cleared state is correct.
5270	*/
5271	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
5272	}
5273	}
5274
5275	/*
5276	* Check if we should inhibit NMI delivery.
5277	*/
5278	if (CPUMIsGuestNmiBlocking(pVCpu))
5279	fIntrState \|= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
5280
5281	/*
5282	* Validate.
5283	*/
5284	#ifdef VBOX_STRICT
5285	/* We don't support block-by-SMI yet.*/
5286	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI));
5287
5288	/* Block-by-STI must not be set when interrupts are disabled. */
5289	if (fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
5290	{
5291	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RFLAGS);
5292	Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_IF);
5293	}
5294	#endif
5295
5296	return fIntrState;
5297	}
5298
5299
5300	/**
5301	* Exports the exception intercepts required for guest execution in the VMCS.
5302	*
5303	* @param pVCpu The cross context virtual CPU structure.
5304	* @param pVmxTransient The VMX-transient structure.
5305	*
5306	* @remarks No-long-jump zone!!!
5307	*/
5308	static void hmR0VmxExportGuestXcptIntercepts(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
5309	{
5310	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_XCPT_INTERCEPTS)
5311	{
5312	/* When executing a nested-guest, we do not need to trap GIM hypercalls by intercepting #UD. */
5313	if ( !pVmxTransient->fIsNestedGuest
5314	&& pVCpu->hm.s.fGIMTrapXcptUD)
5315	hmR0VmxAddXcptIntercept(pVmxTransient, X86_XCPT_UD);
5316	else
5317	hmR0VmxRemoveXcptIntercept(pVCpu, pVmxTransient, X86_XCPT_UD);
5318
5319	/* Other exception intercepts are handled elsewhere, e.g. while exporting guest CR0. */
5320	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_XCPT_INTERCEPTS);
5321	}
5322	}
5323
5324
5325	/**
5326	* Exports the guest's RIP into the guest-state area in the VMCS.
5327	*
5328	* @param pVCpu The cross context virtual CPU structure.
5329	*
5330	* @remarks No-long-jump zone!!!
5331	*/
5332	static void hmR0VmxExportGuestRip(PVMCPUCC pVCpu)
5333	{
5334	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RIP)
5335	{
5336	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP);
5337
5338	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_RIP, pVCpu->cpum.GstCtx.rip);
5339	AssertRC(rc);
5340
5341	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RIP);
5342	Log4Func(("rip=%#RX64\n", pVCpu->cpum.GstCtx.rip));
5343	}
5344	}
5345
5346
5347	/**
5348	* Exports the guest's RSP into the guest-state area in the VMCS.
5349	*
5350	* @param pVCpu The cross context virtual CPU structure.
5351	*
5352	* @remarks No-long-jump zone!!!
5353	*/
5354	static void hmR0VmxExportGuestRsp(PVMCPUCC pVCpu)
5355	{
5356	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RSP)
5357	{
5358	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP);
5359
5360	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_RSP, pVCpu->cpum.GstCtx.rsp);
5361	AssertRC(rc);
5362
5363	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RSP);
5364	Log4Func(("rsp=%#RX64\n", pVCpu->cpum.GstCtx.rsp));
5365	}
5366	}
5367
5368
5369	/**
5370	* Exports the guest's RFLAGS into the guest-state area in the VMCS.
5371	*
5372	* @param pVCpu The cross context virtual CPU structure.
5373	* @param pVmxTransient The VMX-transient structure.
5374	*
5375	* @remarks No-long-jump zone!!!
5376	*/
5377	static void hmR0VmxExportGuestRflags(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
5378	{
5379	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RFLAGS)
5380	{
5381	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RFLAGS);
5382
5383	/* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
5384	Let us assert it as such and use 32-bit VMWRITE. */
5385	Assert(!RT_HI_U32(pVCpu->cpum.GstCtx.rflags.u64));
5386	X86EFLAGS fEFlags = pVCpu->cpum.GstCtx.eflags;
5387	Assert(fEFlags.u32 & X86_EFL_RA1_MASK);
5388	Assert(!(fEFlags.u32 & ~(X86_EFL_1 \| X86_EFL_LIVE_MASK)));
5389
5390	/*
5391	* If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so
5392	* we can restore them on VM-exit. Modify the real-mode guest's eflags so that VT-x
5393	* can run the real-mode guest code under Virtual 8086 mode.
5394	*/
5395	PVMXVMCSINFOSHARED pVmcsInfo = pVmxTransient->pVmcsInfo->pShared;
5396	if (pVmcsInfo->RealMode.fRealOnV86Active)
5397	{
5398	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
5399	Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
5400	Assert(!pVmxTransient->fIsNestedGuest);
5401	pVmcsInfo->RealMode.Eflags.u32 = fEFlags.u32; /* Save the original eflags of the real-mode guest. */
5402	fEFlags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
5403	fEFlags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
5404	}
5405
5406	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_RFLAGS, fEFlags.u32);
5407	AssertRC(rc);
5408
5409	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RFLAGS);
5410	Log4Func(("eflags=%#RX32\n", fEFlags.u32));
5411	}
5412	}
5413
5414
5415	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5416	/**
5417	* Copies the nested-guest VMCS to the shadow VMCS.
5418	*
5419	* @returns VBox status code.
5420	* @param pVCpu The cross context virtual CPU structure.
5421	* @param pVmcsInfo The VMCS info. object.
5422	*
5423	* @remarks No-long-jump zone!!!
5424	*/
5425	static int hmR0VmxCopyNstGstToShadowVmcs(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
5426	{
5427	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
5428	PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5429
5430	/*
5431	* Disable interrupts so we don't get preempted while the shadow VMCS is the
5432	* current VMCS, as we may try saving guest lazy MSRs.
5433	*
5434	* Strictly speaking the lazy MSRs are not in the VMCS, but I'd rather not risk
5435	* calling the import VMCS code which is currently performing the guest MSR reads
5436	* (on 64-bit hosts) and accessing the auto-load/store MSR area on 32-bit hosts
5437	* and the rest of the VMX leave session machinery.
5438	*/
5439	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
5440
5441	int rc = hmR0VmxLoadShadowVmcs(pVmcsInfo);
5442	if (RT_SUCCESS(rc))
5443	{
5444	/*
5445	* Copy all guest read/write VMCS fields.
5446	*
5447	* We don't check for VMWRITE failures here for performance reasons and
5448	* because they are not expected to fail, barring irrecoverable conditions
5449	* like hardware errors.
5450	*/
5451	uint32_t const cShadowVmcsFields = pVM->hmr0.s.vmx.cShadowVmcsFields;
5452	for (uint32_t i = 0; i < cShadowVmcsFields; i++)
5453	{
5454	uint64_t u64Val;
5455	uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsFields[i];
5456	IEMReadVmxVmcsField(pVmcsNstGst, uVmcsField, &u64Val);
5457	VMXWriteVmcs64(uVmcsField, u64Val);
5458	}
5459
5460	/*
5461	* If the host CPU supports writing all VMCS fields, copy the guest read-only
5462	* VMCS fields, so the guest can VMREAD them without causing a VM-exit.
5463	*/
5464	if (g_HmMsrs.u.vmx.u64Misc & VMX_MISC_VMWRITE_ALL)
5465	{
5466	uint32_t const cShadowVmcsRoFields = pVM->hmr0.s.vmx.cShadowVmcsRoFields;
5467	for (uint32_t i = 0; i < cShadowVmcsRoFields; i++)
5468	{
5469	uint64_t u64Val;
5470	uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsRoFields[i];
5471	IEMReadVmxVmcsField(pVmcsNstGst, uVmcsField, &u64Val);
5472	VMXWriteVmcs64(uVmcsField, u64Val);
5473	}
5474	}
5475
5476	rc = hmR0VmxClearShadowVmcs(pVmcsInfo);
5477	rc \|= hmR0VmxLoadVmcs(pVmcsInfo);
5478	}
5479
5480	ASMSetFlags(fEFlags);
5481	return rc;
5482	}
5483
5484
5485	/**
5486	* Copies the shadow VMCS to the nested-guest VMCS.
5487	*
5488	* @returns VBox status code.
5489	* @param pVCpu The cross context virtual CPU structure.
5490	* @param pVmcsInfo The VMCS info. object.
5491	*
5492	* @remarks Called with interrupts disabled.
5493	*/
5494	static int hmR0VmxCopyShadowToNstGstVmcs(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
5495	{
5496	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
5497	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
5498	PVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
5499
5500	int rc = hmR0VmxLoadShadowVmcs(pVmcsInfo);
5501	if (RT_SUCCESS(rc))
5502	{
5503	/*
5504	* Copy guest read/write fields from the shadow VMCS.
5505	* Guest read-only fields cannot be modified, so no need to copy them.
5506	*
5507	* We don't check for VMREAD failures here for performance reasons and
5508	* because they are not expected to fail, barring irrecoverable conditions
5509	* like hardware errors.
5510	*/
5511	uint32_t const cShadowVmcsFields = pVM->hmr0.s.vmx.cShadowVmcsFields;
5512	for (uint32_t i = 0; i < cShadowVmcsFields; i++)
5513	{
5514	uint64_t u64Val;
5515	uint32_t const uVmcsField = pVM->hmr0.s.vmx.paShadowVmcsFields[i];
5516	VMXReadVmcs64(uVmcsField, &u64Val);
5517	IEMWriteVmxVmcsField(pVmcsNstGst, uVmcsField, u64Val);
5518	}
5519
5520	rc = hmR0VmxClearShadowVmcs(pVmcsInfo);
5521	rc \|= hmR0VmxLoadVmcs(pVmcsInfo);
5522	}
5523	return rc;
5524	}
5525
5526
5527	/**
5528	* Enables VMCS shadowing for the given VMCS info. object.
5529	*
5530	* @param pVmcsInfo The VMCS info. object.
5531	*
5532	* @remarks No-long-jump zone!!!
5533	*/
5534	static void hmR0VmxEnableVmcsShadowing(PVMXVMCSINFO pVmcsInfo)
5535	{
5536	uint32_t uProcCtls2 = pVmcsInfo->u32ProcCtls2;
5537	if (!(uProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING))
5538	{
5539	Assert(pVmcsInfo->HCPhysShadowVmcs != 0 && pVmcsInfo->HCPhysShadowVmcs != NIL_RTHCPHYS);
5540	uProcCtls2 \|= VMX_PROC_CTLS2_VMCS_SHADOWING;
5541	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, uProcCtls2); AssertRC(rc);
5542	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, pVmcsInfo->HCPhysShadowVmcs); AssertRC(rc);
5543	pVmcsInfo->u32ProcCtls2 = uProcCtls2;
5544	pVmcsInfo->u64VmcsLinkPtr = pVmcsInfo->HCPhysShadowVmcs;
5545	Log4Func(("Enabled\n"));
5546	}
5547	}
5548
5549
5550	/**
5551	* Disables VMCS shadowing for the given VMCS info. object.
5552	*
5553	* @param pVmcsInfo The VMCS info. object.
5554	*
5555	* @remarks No-long-jump zone!!!
5556	*/
5557	static void hmR0VmxDisableVmcsShadowing(PVMXVMCSINFO pVmcsInfo)
5558	{
5559	/*
5560	* We want all VMREAD and VMWRITE instructions to cause VM-exits, so we clear the
5561	* VMCS shadowing control. However, VM-entry requires the shadow VMCS indicator bit
5562	* to match the VMCS shadowing control if the VMCS link pointer is not NIL_RTHCPHYS.
5563	* Hence, we must also reset the VMCS link pointer to ensure VM-entry does not fail.
5564	*
5565	* See Intel spec. 26.2.1.1 "VM-Execution Control Fields".
5566	* See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
5567	*/
5568	uint32_t uProcCtls2 = pVmcsInfo->u32ProcCtls2;
5569	if (uProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
5570	{
5571	uProcCtls2 &= ~VMX_PROC_CTLS2_VMCS_SHADOWING;
5572	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, uProcCtls2); AssertRC(rc);
5573	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, NIL_RTHCPHYS); AssertRC(rc);
5574	pVmcsInfo->u32ProcCtls2 = uProcCtls2;
5575	pVmcsInfo->u64VmcsLinkPtr = NIL_RTHCPHYS;
5576	Log4Func(("Disabled\n"));
5577	}
5578	}
5579	#endif
5580
5581
5582	/**
5583	* Exports the guest hardware-virtualization state.
5584	*
5585	* @returns VBox status code.
5586	* @param pVCpu The cross context virtual CPU structure.
5587	* @param pVmxTransient The VMX-transient structure.
5588	*
5589	* @remarks No-long-jump zone!!!
5590	*/
5591	static int hmR0VmxExportGuestHwvirtState(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
5592	{
5593	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_HWVIRT)
5594	{
5595	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5596	/*
5597	* Check if the VMX feature is exposed to the guest and if the host CPU supports
5598	* VMCS shadowing.
5599	*/
5600	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fUseVmcsShadowing)
5601	{
5602	/*
5603	* If the nested hypervisor has loaded a current VMCS and is in VMX root mode,
5604	* copy the nested hypervisor's current VMCS into the shadow VMCS and enable
5605	* VMCS shadowing to skip intercepting some or all VMREAD/VMWRITE VM-exits.
5606	*
5607	* We check for VMX root mode here in case the guest executes VMXOFF without
5608	* clearing the current VMCS pointer and our VMXOFF instruction emulation does
5609	* not clear the current VMCS pointer.
5610	*/
5611	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
5612	if ( CPUMIsGuestInVmxRootMode(&pVCpu->cpum.GstCtx)
5613	&& !CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx)
5614	&& CPUMIsGuestVmxCurrentVmcsValid(&pVCpu->cpum.GstCtx))
5615	{
5616	/* Paranoia. */
5617	Assert(!pVmxTransient->fIsNestedGuest);
5618
5619	/*
5620	* For performance reasons, also check if the nested hypervisor's current VMCS
5621	* was newly loaded or modified before copying it to the shadow VMCS.
5622	*/
5623	if (!pVCpu->hm.s.vmx.fCopiedNstGstToShadowVmcs)
5624	{
5625	int rc = hmR0VmxCopyNstGstToShadowVmcs(pVCpu, pVmcsInfo);
5626	AssertRCReturn(rc, rc);
5627	pVCpu->hm.s.vmx.fCopiedNstGstToShadowVmcs = true;
5628	}
5629	hmR0VmxEnableVmcsShadowing(pVmcsInfo);
5630	}
5631	else
5632	hmR0VmxDisableVmcsShadowing(pVmcsInfo);
5633	}
5634	#else
5635	NOREF(pVmxTransient);
5636	#endif
5637	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_HWVIRT);
5638	}
5639	return VINF_SUCCESS;
5640	}
5641
5642
5643	/**
5644	* Exports the guest CR0 control register into the guest-state area in the VMCS.
5645	*
5646	* The guest FPU state is always pre-loaded hence we don't need to bother about
5647	* sharing FPU related CR0 bits between the guest and host.
5648	*
5649	* @returns VBox status code.
5650	* @param pVCpu The cross context virtual CPU structure.
5651	* @param pVmxTransient The VMX-transient structure.
5652	*
5653	* @remarks No-long-jump zone!!!
5654	*/
5655	static int hmR0VmxExportGuestCR0(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
5656	{
5657	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR0)
5658	{
5659	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
5660	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
5661
5662	uint64_t fSetCr0 = g_HmMsrs.u.vmx.u64Cr0Fixed0;
5663	uint64_t const fZapCr0 = g_HmMsrs.u.vmx.u64Cr0Fixed1;
5664	if (pVM->hmr0.s.vmx.fUnrestrictedGuest)
5665	fSetCr0 &= ~(uint64_t)(X86_CR0_PE \| X86_CR0_PG);
5666	else
5667	Assert((fSetCr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG));
5668
5669	if (!pVmxTransient->fIsNestedGuest)
5670	{
5671	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5672	uint64_t u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5673	uint64_t const u64ShadowCr0 = u64GuestCr0;
5674	Assert(!RT_HI_U32(u64GuestCr0));
5675
5676	/*
5677	* Setup VT-x's view of the guest CR0.
5678	*/
5679	uint32_t uProcCtls = pVmcsInfo->u32ProcCtls;
5680	if (pVM->hmr0.s.fNestedPaging)
5681	{
5682	if (CPUMIsGuestPagingEnabled(pVCpu))
5683	{
5684	/* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
5685	uProcCtls &= ~( VMX_PROC_CTLS_CR3_LOAD_EXIT
5686	\| VMX_PROC_CTLS_CR3_STORE_EXIT);
5687	}
5688	else
5689	{
5690	/* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
5691	uProcCtls \|= VMX_PROC_CTLS_CR3_LOAD_EXIT
5692	\| VMX_PROC_CTLS_CR3_STORE_EXIT;
5693	}
5694
5695	/* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
5696	if (pVM->hmr0.s.vmx.fUnrestrictedGuest)
5697	uProcCtls &= ~VMX_PROC_CTLS_CR3_STORE_EXIT;
5698	}
5699	else
5700	{
5701	/* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
5702	u64GuestCr0 \|= X86_CR0_WP;
5703	}
5704
5705	/*
5706	* Guest FPU bits.
5707	*
5708	* Since we pre-load the guest FPU always before VM-entry there is no need to track lazy state
5709	* using CR0.TS.
5710	*
5711	* Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be
5712	* set on the first CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
5713	*/
5714	u64GuestCr0 \|= X86_CR0_NE;
5715
5716	/* If CR0.NE isn't set, we need to intercept #MF exceptions and report them to the guest differently. */
5717	bool const fInterceptMF = !(u64ShadowCr0 & X86_CR0_NE);
5718
5719	/*
5720	* Update exception intercepts.
5721	*/
5722	uint32_t uXcptBitmap = pVmcsInfo->u32XcptBitmap;
5723	if (pVmcsInfo->pShared->RealMode.fRealOnV86Active)
5724	{
5725	Assert(PDMVmmDevHeapIsEnabled(pVM));
5726	Assert(pVM->hm.s.vmx.pRealModeTSS);
5727	uXcptBitmap \|= HMVMX_REAL_MODE_XCPT_MASK;
5728	}
5729	else
5730	{
5731	/* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */
5732	uXcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
5733	if (fInterceptMF)
5734	uXcptBitmap \|= RT_BIT(X86_XCPT_MF);
5735	}
5736
5737	/* Additional intercepts for debugging, define these yourself explicitly. */
5738	#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
5739	uXcptBitmap \|= 0
5740	\| RT_BIT(X86_XCPT_BP)
5741	\| RT_BIT(X86_XCPT_DE)
5742	\| RT_BIT(X86_XCPT_NM)
5743	\| RT_BIT(X86_XCPT_TS)
5744	\| RT_BIT(X86_XCPT_UD)
5745	\| RT_BIT(X86_XCPT_NP)
5746	\| RT_BIT(X86_XCPT_SS)
5747	\| RT_BIT(X86_XCPT_GP)
5748	\| RT_BIT(X86_XCPT_PF)
5749	\| RT_BIT(X86_XCPT_MF)
5750	;
5751	#elif defined(HMVMX_ALWAYS_TRAP_PF)
5752	uXcptBitmap \|= RT_BIT(X86_XCPT_PF);
5753	#endif
5754	if (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv)
5755	uXcptBitmap \|= RT_BIT(X86_XCPT_GP);
5756	Assert(pVM->hmr0.s.fNestedPaging \|\| (uXcptBitmap & RT_BIT(X86_XCPT_PF)));
5757
5758	/* Apply the hardware specified CR0 fixed bits and enable caching. */
5759	u64GuestCr0 \|= fSetCr0;
5760	u64GuestCr0 &= fZapCr0;
5761	u64GuestCr0 &= ~(uint64_t)(X86_CR0_CD \| X86_CR0_NW);
5762
5763	/* Commit the CR0 and related fields to the guest VMCS. */
5764	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_CR0, u64GuestCr0); AssertRC(rc);
5765	rc = VMXWriteVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, u64ShadowCr0); AssertRC(rc);
5766	if (uProcCtls != pVmcsInfo->u32ProcCtls)
5767	{
5768	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
5769	AssertRC(rc);
5770	}
5771	if (uXcptBitmap != pVmcsInfo->u32XcptBitmap)
5772	{
5773	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
5774	AssertRC(rc);
5775	}
5776
5777	/* Update our caches. */
5778	pVmcsInfo->u32ProcCtls = uProcCtls;
5779	pVmcsInfo->u32XcptBitmap = uXcptBitmap;
5780
5781	Log4Func(("cr0=%#RX64 shadow=%#RX64 set=%#RX64 zap=%#RX64\n", u64GuestCr0, u64ShadowCr0, fSetCr0, fZapCr0));
5782	}
5783	else
5784	{
5785	/*
5786	* With nested-guests, we may have extended the guest/host mask here since we
5787	* merged in the outer guest's mask. Thus, the merged mask can include more bits
5788	* (to read from the nested-guest CR0 read-shadow) than the nested hypervisor
5789	* originally supplied. We must copy those bits from the nested-guest CR0 into
5790	* the nested-guest CR0 read-shadow.
5791	*/
5792	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
5793	uint64_t u64GuestCr0 = pVCpu->cpum.GstCtx.cr0;
5794	uint64_t const u64ShadowCr0 = CPUMGetGuestVmxMaskedCr0(&pVCpu->cpum.GstCtx, pVmcsInfo->u64Cr0Mask);
5795	Assert(!RT_HI_U32(u64GuestCr0));
5796	Assert(u64GuestCr0 & X86_CR0_NE);
5797
5798	/* Apply the hardware specified CR0 fixed bits and enable caching. */
5799	u64GuestCr0 \|= fSetCr0;
5800	u64GuestCr0 &= fZapCr0;
5801	u64GuestCr0 &= ~(uint64_t)(X86_CR0_CD \| X86_CR0_NW);
5802
5803	/* Commit the CR0 and CR0 read-shadow to the nested-guest VMCS. */
5804	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_CR0, u64GuestCr0); AssertRC(rc);
5805	rc = VMXWriteVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, u64ShadowCr0); AssertRC(rc);
5806
5807	Log4Func(("cr0=%#RX64 shadow=%#RX64 (set=%#RX64 zap=%#RX64)\n", u64GuestCr0, u64ShadowCr0, fSetCr0, fZapCr0));
5808	}
5809
5810	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR0);
5811	}
5812
5813	return VINF_SUCCESS;
5814	}
5815
5816
5817	/**
5818	* Exports the guest control registers (CR3, CR4) into the guest-state area
5819	* in the VMCS.
5820	*
5821	* @returns VBox strict status code.
5822	* @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
5823	* without unrestricted guest access and the VMMDev is not presently
5824	* mapped (e.g. EFI32).
5825	*
5826	* @param pVCpu The cross context virtual CPU structure.
5827	* @param pVmxTransient The VMX-transient structure.
5828	*
5829	* @remarks No-long-jump zone!!!
5830	*/
5831	static VBOXSTRICTRC hmR0VmxExportGuestCR3AndCR4(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
5832	{
5833	int rc = VINF_SUCCESS;
5834	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
5835
5836	/*
5837	* Guest CR2.
5838	* It's always loaded in the assembler code. Nothing to do here.
5839	*/
5840
5841	/*
5842	* Guest CR3.
5843	*/
5844	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR3)
5845	{
5846	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
5847
5848	if (pVM->hmr0.s.fNestedPaging)
5849	{
5850	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
5851	pVmcsInfo->HCPhysEPTP = PGMGetHyperCR3(pVCpu);
5852
5853	/* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
5854	Assert(pVmcsInfo->HCPhysEPTP != NIL_RTHCPHYS);
5855	Assert(!(pVmcsInfo->HCPhysEPTP & UINT64_C(0xfff0000000000000)));
5856	Assert(!(pVmcsInfo->HCPhysEPTP & 0xfff));
5857
5858	/* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
5859	pVmcsInfo->HCPhysEPTP \|= VMX_EPT_MEMTYPE_WB
5860	\| (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
5861
5862	/* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
5863	AssertMsg( ((pVmcsInfo->HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
5864	&& ((pVmcsInfo->HCPhysEPTP >> 7) & 0x1f) == 0, /* Bits 7:11 MBZ. */
5865	("EPTP %#RX64\n", pVmcsInfo->HCPhysEPTP));
5866	AssertMsg( !((pVmcsInfo->HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */
5867	\|\| (g_HmMsrs.u.vmx.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
5868	("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVmcsInfo->HCPhysEPTP));
5869
5870	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVmcsInfo->HCPhysEPTP);
5871	AssertRC(rc);
5872
5873	uint64_t u64GuestCr3;
5874	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5875	if ( pVM->hmr0.s.vmx.fUnrestrictedGuest
5876	\|\| CPUMIsGuestPagingEnabledEx(pCtx))
5877	{
5878	/* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
5879	if (CPUMIsGuestInPAEModeEx(pCtx))
5880	{
5881	rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
5882	AssertRC(rc);
5883	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u); AssertRC(rc);
5884	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u); AssertRC(rc);
5885	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u); AssertRC(rc);
5886	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u); AssertRC(rc);
5887	}
5888
5889	/*
5890	* The guest's view of its CR3 is unblemished with nested paging when the
5891	* guest is using paging or we have unrestricted guest execution to handle
5892	* the guest when it's not using paging.
5893	*/
5894	u64GuestCr3 = pCtx->cr3;
5895	}
5896	else
5897	{
5898	/*
5899	* The guest is not using paging, but the CPU (VT-x) has to. While the guest
5900	* thinks it accesses physical memory directly, we use our identity-mapped
5901	* page table to map guest-linear to guest-physical addresses. EPT takes care
5902	* of translating it to host-physical addresses.
5903	*/
5904	RTGCPHYS GCPhys;
5905	Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
5906
5907	/* We obtain it here every time as the guest could have relocated this PCI region. */
5908	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
5909	if (RT_SUCCESS(rc))
5910	{ /* likely */ }
5911	else if (rc == VERR_PDM_DEV_HEAP_R3_TO_GCPHYS)
5912	{
5913	Log4Func(("VERR_PDM_DEV_HEAP_R3_TO_GCPHYS -> VINF_EM_RESCHEDULE_REM\n"));
5914	return VINF_EM_RESCHEDULE_REM; /* We cannot execute now, switch to REM/IEM till the guest maps in VMMDev. */
5915	}
5916	else
5917	AssertMsgFailedReturn(("%Rrc\n", rc), rc);
5918
5919	u64GuestCr3 = GCPhys;
5920	}
5921
5922	Log4Func(("guest_cr3=%#RX64 (GstN)\n", u64GuestCr3));
5923	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_CR3, u64GuestCr3);
5924	AssertRC(rc);
5925	}
5926	else
5927	{
5928	Assert(!pVmxTransient->fIsNestedGuest);
5929	/* Non-nested paging case, just use the hypervisor's CR3. */
5930	RTHCPHYS const HCPhysGuestCr3 = PGMGetHyperCR3(pVCpu);
5931
5932	Log4Func(("guest_cr3=%#RX64 (HstN)\n", HCPhysGuestCr3));
5933	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_CR3, HCPhysGuestCr3);
5934	AssertRC(rc);
5935	}
5936
5937	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR3);
5938	}
5939
5940	/*
5941	* Guest CR4.
5942	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
5943	*/
5944	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR4)
5945	{
5946	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5947	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
5948
5949	uint64_t const fSetCr4 = g_HmMsrs.u.vmx.u64Cr4Fixed0;
5950	uint64_t const fZapCr4 = g_HmMsrs.u.vmx.u64Cr4Fixed1;
5951
5952	/*
5953	* With nested-guests, we may have extended the guest/host mask here (since we
5954	* merged in the outer guest's mask, see hmR0VmxMergeVmcsNested). This means, the
5955	* mask can include more bits (to read from the nested-guest CR4 read-shadow) than
5956	* the nested hypervisor originally supplied. Thus, we should, in essence, copy
5957	* those bits from the nested-guest CR4 into the nested-guest CR4 read-shadow.
5958	*/
5959	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
5960	uint64_t u64GuestCr4 = pCtx->cr4;
5961	uint64_t const u64ShadowCr4 = !pVmxTransient->fIsNestedGuest
5962	? pCtx->cr4
5963	: CPUMGetGuestVmxMaskedCr4(pCtx, pVmcsInfo->u64Cr4Mask);
5964	Assert(!RT_HI_U32(u64GuestCr4));
5965
5966	/*
5967	* Setup VT-x's view of the guest CR4.
5968	*
5969	* If we're emulating real-mode using virtual-8086 mode, we want to redirect software
5970	* interrupts to the 8086 program interrupt handler. Clear the VME bit (the interrupt
5971	* redirection bitmap is already all 0, see hmR3InitFinalizeR0())
5972	*
5973	* See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
5974	*/
5975	if (pVmcsInfo->pShared->RealMode.fRealOnV86Active)
5976	{
5977	Assert(pVM->hm.s.vmx.pRealModeTSS);
5978	Assert(PDMVmmDevHeapIsEnabled(pVM));
5979	u64GuestCr4 &= ~(uint64_t)X86_CR4_VME;
5980	}
5981
5982	if (pVM->hmr0.s.fNestedPaging)
5983	{
5984	if ( !CPUMIsGuestPagingEnabledEx(pCtx)
5985	&& !pVM->hmr0.s.vmx.fUnrestrictedGuest)
5986	{
5987	/* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
5988	u64GuestCr4 \|= X86_CR4_PSE;
5989	/* Our identity mapping is a 32-bit page directory. */
5990	u64GuestCr4 &= ~(uint64_t)X86_CR4_PAE;
5991	}
5992	/* else use guest CR4.*/
5993	}
5994	else
5995	{
5996	Assert(!pVmxTransient->fIsNestedGuest);
5997
5998	/*
5999	* The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
6000	* paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
6001	*/
6002	switch (pVCpu->hm.s.enmShadowMode)
6003	{
6004	case PGMMODE_REAL: /* Real-mode. */
6005	case PGMMODE_PROTECTED: /* Protected mode without paging. */
6006	case PGMMODE_32_BIT: /* 32-bit paging. */
6007	{
6008	u64GuestCr4 &= ~(uint64_t)X86_CR4_PAE;
6009	break;
6010	}
6011
6012	case PGMMODE_PAE: /* PAE paging. */
6013	case PGMMODE_PAE_NX: /* PAE paging with NX. */
6014	{
6015	u64GuestCr4 \|= X86_CR4_PAE;
6016	break;
6017	}
6018
6019	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
6020	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
6021	{
6022	#ifdef VBOX_WITH_64_BITS_GUESTS
6023	/* For our assumption in hmR0VmxShouldSwapEferMsr. */
6024	Assert(u64GuestCr4 & X86_CR4_PAE);
6025	break;
6026	#endif
6027	}
6028	default:
6029	AssertFailed();
6030	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
6031	}
6032	}
6033
6034	/* Apply the hardware specified CR4 fixed bits (mainly CR4.VMXE). */
6035	u64GuestCr4 \|= fSetCr4;
6036	u64GuestCr4 &= fZapCr4;
6037
6038	/* Commit the CR4 and CR4 read-shadow to the guest VMCS. */
6039	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_CR4, u64GuestCr4); AssertRC(rc);
6040	rc = VMXWriteVmcsNw(VMX_VMCS_CTRL_CR4_READ_SHADOW, u64ShadowCr4); AssertRC(rc);
6041
6042	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
6043	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6044	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
6045	{
6046	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
6047	hmR0VmxUpdateStartVmFunction(pVCpu);
6048	}
6049
6050	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR4);
6051
6052	Log4Func(("cr4=%#RX64 shadow=%#RX64 (set=%#RX64 zap=%#RX64)\n", u64GuestCr4, u64ShadowCr4, fSetCr4, fZapCr4));
6053	}
6054	return rc;
6055	}
6056
6057
6058	/**
6059	* Exports the guest debug registers into the guest-state area in the VMCS.
6060	* The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
6061	*
6062	* This also sets up whether \#DB and MOV DRx accesses cause VM-exits.
6063	*
6064	* @returns VBox status code.
6065	* @param pVCpu The cross context virtual CPU structure.
6066	* @param pVmxTransient The VMX-transient structure.
6067	*
6068	* @remarks No-long-jump zone!!!
6069	*/
6070	static int hmR0VmxExportSharedDebugState(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
6071	{
6072	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
6073
6074	/** @todo NSTVMX: Figure out what we want to do with nested-guest instruction
6075	* stepping. */
6076	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
6077	if (pVmxTransient->fIsNestedGuest)
6078	{
6079	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_DR7, CPUMGetGuestDR7(pVCpu));
6080	AssertRC(rc);
6081
6082	/* Always intercept Mov DRx accesses for the nested-guest for now. */
6083	pVmcsInfo->u32ProcCtls \|= VMX_PROC_CTLS_MOV_DR_EXIT;
6084	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
6085	AssertRC(rc);
6086	return VINF_SUCCESS;
6087	}
6088
6089	#ifdef VBOX_STRICT
6090	/* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
6091	if (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
6092	{
6093	/* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
6094	Assert((pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_MBZ_MASK \| X86_DR7_RAZ_MASK)) == 0);
6095	Assert((pVCpu->cpum.GstCtx.dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK);
6096	}
6097	#endif
6098
6099	bool fSteppingDB = false;
6100	bool fInterceptMovDRx = false;
6101	uint32_t uProcCtls = pVmcsInfo->u32ProcCtls;
6102	if (pVCpu->hm.s.fSingleInstruction)
6103	{
6104	/* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
6105	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
6106	{
6107	uProcCtls \|= VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
6108	Assert(fSteppingDB == false);
6109	}
6110	else
6111	{
6112	pVCpu->cpum.GstCtx.eflags.u32 \|= X86_EFL_TF;
6113	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_RFLAGS;
6114	pVCpu->hmr0.s.fClearTrapFlag = true;
6115	fSteppingDB = true;
6116	}
6117	}
6118
6119	uint64_t u64GuestDr7;
6120	if ( fSteppingDB
6121	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
6122	{
6123	/*
6124	* Use the combined guest and host DRx values found in the hypervisor register set
6125	* because the hypervisor debugger has breakpoints active or someone is single stepping
6126	* on the host side without a monitor trap flag.
6127	*
6128	* Note! DBGF expects a clean DR6 state before executing guest code.
6129	*/
6130	if (!CPUMIsHyperDebugStateActive(pVCpu))
6131	{
6132	CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
6133	Assert(CPUMIsHyperDebugStateActive(pVCpu));
6134	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
6135	}
6136
6137	/* Update DR7 with the hypervisor value (other DRx registers are handled by CPUM one way or another). */
6138	u64GuestDr7 = CPUMGetHyperDR7(pVCpu);
6139	pVCpu->hmr0.s.fUsingHyperDR7 = true;
6140	fInterceptMovDRx = true;
6141	}
6142	else
6143	{
6144	/*
6145	* If the guest has enabled debug registers, we need to load them prior to
6146	* executing guest code so they'll trigger at the right time.
6147	*/
6148	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
6149	if (pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD))
6150	{
6151	if (!CPUMIsGuestDebugStateActive(pVCpu))
6152	{
6153	CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
6154	Assert(CPUMIsGuestDebugStateActive(pVCpu));
6155	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
6156	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
6157	}
6158	Assert(!fInterceptMovDRx);
6159	}
6160	else if (!CPUMIsGuestDebugStateActive(pVCpu))
6161	{
6162	/*
6163	* If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
6164	* must intercept #DB in order to maintain a correct DR6 guest value, and
6165	* because we need to intercept it to prevent nested #DBs from hanging the
6166	* CPU, we end up always having to intercept it. See hmR0VmxSetupVmcsXcptBitmap().
6167	*/
6168	fInterceptMovDRx = true;
6169	}
6170
6171	/* Update DR7 with the actual guest value. */
6172	u64GuestDr7 = pVCpu->cpum.GstCtx.dr[7];
6173	pVCpu->hmr0.s.fUsingHyperDR7 = false;
6174	}
6175
6176	if (fInterceptMovDRx)
6177	uProcCtls \|= VMX_PROC_CTLS_MOV_DR_EXIT;
6178	else
6179	uProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
6180
6181	/*
6182	* Update the processor-based VM-execution controls with the MOV-DRx intercepts and the
6183	* monitor-trap flag and update our cache.
6184	*/
6185	if (uProcCtls != pVmcsInfo->u32ProcCtls)
6186	{
6187	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
6188	AssertRC(rc);
6189	pVmcsInfo->u32ProcCtls = uProcCtls;
6190	}
6191
6192	/*
6193	* Update guest DR7.
6194	*/
6195	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_DR7, u64GuestDr7);
6196	AssertRC(rc);
6197
6198	/*
6199	* If we have forced EFLAGS.TF to be set because we're single-stepping in the hypervisor debugger,
6200	* we need to clear interrupt inhibition if any as otherwise it causes a VM-entry failure.
6201	*
6202	* See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
6203	*/
6204	if (fSteppingDB)
6205	{
6206	Assert(pVCpu->hm.s.fSingleInstruction);
6207	Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1TF);
6208
6209	uint32_t fIntrState = 0;
6210	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
6211	AssertRC(rc);
6212
6213	if (fIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI \| VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
6214	{
6215	fIntrState &= ~(VMX_VMCS_GUEST_INT_STATE_BLOCK_STI \| VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
6216	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
6217	AssertRC(rc);
6218	}
6219	}
6220
6221	return VINF_SUCCESS;
6222	}
6223
6224
6225	#ifdef VBOX_STRICT
6226	/**
6227	* Strict function to validate segment registers.
6228	*
6229	* @param pVCpu The cross context virtual CPU structure.
6230	* @param pVmcsInfo The VMCS info. object.
6231	*
6232	* @remarks Will import guest CR0 on strict builds during validation of
6233	* segments.
6234	*/
6235	static void hmR0VmxValidateSegmentRegs(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
6236	{
6237	/*
6238	* Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
6239	*
6240	* The reason we check for attribute value 0 in this function and not just the unusable bit is
6241	* because hmR0VmxExportGuestSegReg() only updates the VMCS' copy of the value with the
6242	* unusable bit and doesn't change the guest-context value.
6243	*/
6244	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6245	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6246	hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_CR0);
6247	if ( !pVM->hmr0.s.vmx.fUnrestrictedGuest
6248	&& ( !CPUMIsGuestInRealModeEx(pCtx)
6249	&& !CPUMIsGuestInV86ModeEx(pCtx)))
6250	{
6251	/* Protected mode checks */
6252	/* CS */
6253	Assert(pCtx->cs.Attr.n.u1Present);
6254	Assert(!(pCtx->cs.Attr.u & 0xf00));
6255	Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
6256	Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
6257	\|\| !(pCtx->cs.Attr.n.u1Granularity));
6258	Assert( !(pCtx->cs.u32Limit & 0xfff00000)
6259	\|\| (pCtx->cs.Attr.n.u1Granularity));
6260	/* CS cannot be loaded with NULL in protected mode. */
6261	Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS? */
6262	if (pCtx->cs.Attr.n.u4Type == 9 \|\| pCtx->cs.Attr.n.u4Type == 11)
6263	Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
6264	else if (pCtx->cs.Attr.n.u4Type == 13 \|\| pCtx->cs.Attr.n.u4Type == 15)
6265	Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
6266	else
6267	AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
6268	/* SS */
6269	Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
6270	Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
6271	if ( !(pCtx->cr0 & X86_CR0_PE)
6272	\|\| pCtx->cs.Attr.n.u4Type == 3)
6273	{
6274	Assert(!pCtx->ss.Attr.n.u2Dpl);
6275	}
6276	if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
6277	{
6278	Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
6279	Assert(pCtx->ss.Attr.n.u4Type == 3 \|\| pCtx->ss.Attr.n.u4Type == 7);
6280	Assert(pCtx->ss.Attr.n.u1Present);
6281	Assert(!(pCtx->ss.Attr.u & 0xf00));
6282	Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
6283	Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
6284	\|\| !(pCtx->ss.Attr.n.u1Granularity));
6285	Assert( !(pCtx->ss.u32Limit & 0xfff00000)
6286	\|\| (pCtx->ss.Attr.n.u1Granularity));
6287	}
6288	/* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSegReg(). */
6289	if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
6290	{
6291	Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
6292	Assert(pCtx->ds.Attr.n.u1Present);
6293	Assert(pCtx->ds.Attr.n.u4Type > 11 \|\| pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
6294	Assert(!(pCtx->ds.Attr.u & 0xf00));
6295	Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
6296	Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
6297	\|\| !(pCtx->ds.Attr.n.u1Granularity));
6298	Assert( !(pCtx->ds.u32Limit & 0xfff00000)
6299	\|\| (pCtx->ds.Attr.n.u1Granularity));
6300	Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
6301	\|\| (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
6302	}
6303	if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
6304	{
6305	Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
6306	Assert(pCtx->es.Attr.n.u1Present);
6307	Assert(pCtx->es.Attr.n.u4Type > 11 \|\| pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
6308	Assert(!(pCtx->es.Attr.u & 0xf00));
6309	Assert(!(pCtx->es.Attr.u & 0xfffe0000));
6310	Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
6311	\|\| !(pCtx->es.Attr.n.u1Granularity));
6312	Assert( !(pCtx->es.u32Limit & 0xfff00000)
6313	\|\| (pCtx->es.Attr.n.u1Granularity));
6314	Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
6315	\|\| (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
6316	}
6317	if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
6318	{
6319	Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
6320	Assert(pCtx->fs.Attr.n.u1Present);
6321	Assert(pCtx->fs.Attr.n.u4Type > 11 \|\| pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
6322	Assert(!(pCtx->fs.Attr.u & 0xf00));
6323	Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
6324	Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
6325	\|\| !(pCtx->fs.Attr.n.u1Granularity));
6326	Assert( !(pCtx->fs.u32Limit & 0xfff00000)
6327	\|\| (pCtx->fs.Attr.n.u1Granularity));
6328	Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
6329	\|\| (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
6330	}
6331	if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
6332	{
6333	Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
6334	Assert(pCtx->gs.Attr.n.u1Present);
6335	Assert(pCtx->gs.Attr.n.u4Type > 11 \|\| pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
6336	Assert(!(pCtx->gs.Attr.u & 0xf00));
6337	Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
6338	Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
6339	\|\| !(pCtx->gs.Attr.n.u1Granularity));
6340	Assert( !(pCtx->gs.u32Limit & 0xfff00000)
6341	\|\| (pCtx->gs.Attr.n.u1Granularity));
6342	Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
6343	\|\| (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
6344	}
6345	/* 64-bit capable CPUs. */
6346	Assert(!RT_HI_U32(pCtx->cs.u64Base));
6347	Assert(!pCtx->ss.Attr.u \|\| !RT_HI_U32(pCtx->ss.u64Base));
6348	Assert(!pCtx->ds.Attr.u \|\| !RT_HI_U32(pCtx->ds.u64Base));
6349	Assert(!pCtx->es.Attr.u \|\| !RT_HI_U32(pCtx->es.u64Base));
6350	}
6351	else if ( CPUMIsGuestInV86ModeEx(pCtx)
6352	\|\| ( CPUMIsGuestInRealModeEx(pCtx)
6353	&& !pVM->hmr0.s.vmx.fUnrestrictedGuest))
6354	{
6355	/* Real and v86 mode checks. */
6356	/* hmR0VmxExportGuestSegReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
6357	uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
6358	if (pVmcsInfo->pShared->RealMode.fRealOnV86Active)
6359	{
6360	u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3;
6361	u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
6362	}
6363	else
6364	{
6365	u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
6366	u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
6367	}
6368
6369	/* CS */
6370	AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
6371	Assert(pCtx->cs.u32Limit == 0xffff);
6372	Assert(u32CSAttr == 0xf3);
6373	/* SS */
6374	Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
6375	Assert(pCtx->ss.u32Limit == 0xffff);
6376	Assert(u32SSAttr == 0xf3);
6377	/* DS */
6378	Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
6379	Assert(pCtx->ds.u32Limit == 0xffff);
6380	Assert(u32DSAttr == 0xf3);
6381	/* ES */
6382	Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
6383	Assert(pCtx->es.u32Limit == 0xffff);
6384	Assert(u32ESAttr == 0xf3);
6385	/* FS */
6386	Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
6387	Assert(pCtx->fs.u32Limit == 0xffff);
6388	Assert(u32FSAttr == 0xf3);
6389	/* GS */
6390	Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
6391	Assert(pCtx->gs.u32Limit == 0xffff);
6392	Assert(u32GSAttr == 0xf3);
6393	/* 64-bit capable CPUs. */
6394	Assert(!RT_HI_U32(pCtx->cs.u64Base));
6395	Assert(!u32SSAttr \|\| !RT_HI_U32(pCtx->ss.u64Base));
6396	Assert(!u32DSAttr \|\| !RT_HI_U32(pCtx->ds.u64Base));
6397	Assert(!u32ESAttr \|\| !RT_HI_U32(pCtx->es.u64Base));
6398	}
6399	}
6400	#endif /* VBOX_STRICT */
6401
6402
6403	/**
6404	* Exports a guest segment register into the guest-state area in the VMCS.
6405	*
6406	* @returns VBox status code.
6407	* @param pVCpu The cross context virtual CPU structure.
6408	* @param pVmcsInfo The VMCS info. object.
6409	* @param iSegReg The segment register number (X86_SREG_XXX).
6410	* @param pSelReg Pointer to the segment selector.
6411	*
6412	* @remarks No-long-jump zone!!!
6413	*/
6414	static int hmR0VmxExportGuestSegReg(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo, uint32_t iSegReg, PCCPUMSELREG pSelReg)
6415	{
6416	Assert(iSegReg < X86_SREG_COUNT);
6417
6418	uint32_t u32Access = pSelReg->Attr.u;
6419	if (!pVmcsInfo->pShared->RealMode.fRealOnV86Active)
6420	{
6421	/*
6422	* The way to differentiate between whether this is really a null selector or was just
6423	* a selector loaded with 0 in real-mode is using the segment attributes. A selector
6424	* loaded in real-mode with the value 0 is valid and usable in protected-mode and we
6425	* should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures
6426	* NULL selectors loaded in protected-mode have their attribute as 0.
6427	*/
6428	if (u32Access)
6429	{ }
6430	else
6431	u32Access = X86DESCATTR_UNUSABLE;
6432	}
6433	else
6434	{
6435	/* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
6436	u32Access = 0xf3;
6437	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
6438	Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
6439	RT_NOREF_PV(pVCpu);
6440	}
6441
6442	/* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
6443	AssertMsg((u32Access & X86DESCATTR_UNUSABLE) \|\| (u32Access & X86_SEL_TYPE_ACCESSED),
6444	("Access bit not set for usable segment. %.2s sel=%#x attr %#x\n", "ESCSSSDSFSGS" + iSegReg * 2, pSelReg, pSelReg->Attr.u));
6445
6446	/*
6447	* Commit it to the VMCS.
6448	*/
6449	Assert((uint32_t)VMX_VMCS16_GUEST_SEG_SEL(iSegReg) == g_aVmcsSegSel[iSegReg]);
6450	Assert((uint32_t)VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg) == g_aVmcsSegLimit[iSegReg]);
6451	Assert((uint32_t)VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg) == g_aVmcsSegAttr[iSegReg]);
6452	Assert((uint32_t)VMX_VMCS_GUEST_SEG_BASE(iSegReg) == g_aVmcsSegBase[iSegReg]);
6453	int rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_SEG_SEL(iSegReg), pSelReg->Sel); AssertRC(rc);
6454	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg), pSelReg->u32Limit); AssertRC(rc);
6455	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_SEG_BASE(iSegReg), pSelReg->u64Base); AssertRC(rc);
6456	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg), u32Access); AssertRC(rc);
6457	return VINF_SUCCESS;
6458	}
6459
6460
6461	/**
6462	* Exports the guest segment registers, GDTR, IDTR, LDTR, TR into the guest-state
6463	* area in the VMCS.
6464	*
6465	* @returns VBox status code.
6466	* @param pVCpu The cross context virtual CPU structure.
6467	* @param pVmxTransient The VMX-transient structure.
6468	*
6469	* @remarks Will import guest CR0 on strict builds during validation of
6470	* segments.
6471	* @remarks No-long-jump zone!!!
6472	*/
6473	static int hmR0VmxExportGuestSegRegsXdtr(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
6474	{
6475	int rc = VERR_INTERNAL_ERROR_5;
6476	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6477	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6478	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
6479	PVMXVMCSINFOSHARED pVmcsInfoShared = pVmcsInfo->pShared;
6480
6481	/*
6482	* Guest Segment registers: CS, SS, DS, ES, FS, GS.
6483	*/
6484	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SREG_MASK)
6485	{
6486	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CS)
6487	{
6488	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
6489	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
6490	pVmcsInfoShared->RealMode.AttrCS.u = pCtx->cs.Attr.u;
6491	rc = hmR0VmxExportGuestSegReg(pVCpu, pVmcsInfo, X86_SREG_CS, &pCtx->cs);
6492	AssertRC(rc);
6493	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CS);
6494	}
6495
6496	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SS)
6497	{
6498	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
6499	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
6500	pVmcsInfoShared->RealMode.AttrSS.u = pCtx->ss.Attr.u;
6501	rc = hmR0VmxExportGuestSegReg(pVCpu, pVmcsInfo, X86_SREG_SS, &pCtx->ss);
6502	AssertRC(rc);
6503	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SS);
6504	}
6505
6506	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_DS)
6507	{
6508	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DS);
6509	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
6510	pVmcsInfoShared->RealMode.AttrDS.u = pCtx->ds.Attr.u;
6511	rc = hmR0VmxExportGuestSegReg(pVCpu, pVmcsInfo, X86_SREG_DS, &pCtx->ds);
6512	AssertRC(rc);
6513	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_DS);
6514	}
6515
6516	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_ES)
6517	{
6518	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_ES);
6519	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
6520	pVmcsInfoShared->RealMode.AttrES.u = pCtx->es.Attr.u;
6521	rc = hmR0VmxExportGuestSegReg(pVCpu, pVmcsInfo, X86_SREG_ES, &pCtx->es);
6522	AssertRC(rc);
6523	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_ES);
6524	}
6525
6526	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_FS)
6527	{
6528	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
6529	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
6530	pVmcsInfoShared->RealMode.AttrFS.u = pCtx->fs.Attr.u;
6531	rc = hmR0VmxExportGuestSegReg(pVCpu, pVmcsInfo, X86_SREG_FS, &pCtx->fs);
6532	AssertRC(rc);
6533	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_FS);
6534	}
6535
6536	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GS)
6537	{
6538	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
6539	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
6540	pVmcsInfoShared->RealMode.AttrGS.u = pCtx->gs.Attr.u;
6541	rc = hmR0VmxExportGuestSegReg(pVCpu, pVmcsInfo, X86_SREG_GS, &pCtx->gs);
6542	AssertRC(rc);
6543	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GS);
6544	}
6545
6546	#ifdef VBOX_STRICT
6547	hmR0VmxValidateSegmentRegs(pVCpu, pVmcsInfo);
6548	#endif
6549	Log4Func(("cs={%#04x base=%#RX64 limit=%#RX32 attr=%#RX32}\n", pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit,
6550	pCtx->cs.Attr.u));
6551	}
6552
6553	/*
6554	* Guest TR.
6555	*/
6556	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_TR)
6557	{
6558	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_TR);
6559
6560	/*
6561	* Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is
6562	* achieved using the interrupt redirection bitmap (all bits cleared to let the guest
6563	* handle INT-n's) in the TSS. See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
6564	*/
6565	uint16_t u16Sel;
6566	uint32_t u32Limit;
6567	uint64_t u64Base;
6568	uint32_t u32AccessRights;
6569	if (!pVmcsInfoShared->RealMode.fRealOnV86Active)
6570	{
6571	u16Sel = pCtx->tr.Sel;
6572	u32Limit = pCtx->tr.u32Limit;
6573	u64Base = pCtx->tr.u64Base;
6574	u32AccessRights = pCtx->tr.Attr.u;
6575	}
6576	else
6577	{
6578	Assert(!pVmxTransient->fIsNestedGuest);
6579	Assert(pVM->hm.s.vmx.pRealModeTSS);
6580	Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMCanExecuteGuest() -XXX- what about inner loop changes? */
6581
6582	/* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
6583	RTGCPHYS GCPhys;
6584	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
6585	AssertRCReturn(rc, rc);
6586
6587	X86DESCATTR DescAttr;
6588	DescAttr.u = 0;
6589	DescAttr.n.u1Present = 1;
6590	DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
6591
6592	u16Sel = 0;
6593	u32Limit = HM_VTX_TSS_SIZE;
6594	u64Base = GCPhys;
6595	u32AccessRights = DescAttr.u;
6596	}
6597
6598	/* Validate. */
6599	Assert(!(u16Sel & RT_BIT(2)));
6600	AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
6601	\|\| (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
6602	AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
6603	Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
6604	Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
6605	Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
6606	Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
6607	Assert( (u32Limit & 0xfff) == 0xfff
6608	\|\| !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
6609	Assert( !(pCtx->tr.u32Limit & 0xfff00000)
6610	\|\| (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
6611
6612	rc = VMXWriteVmcs16(VMX_VMCS16_GUEST_TR_SEL, u16Sel); AssertRC(rc);
6613	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit); AssertRC(rc);
6614	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights); AssertRC(rc);
6615	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_TR_BASE, u64Base); AssertRC(rc);
6616
6617	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_TR);
6618	Log4Func(("tr base=%#RX64 limit=%#RX32\n", pCtx->tr.u64Base, pCtx->tr.u32Limit));
6619	}
6620
6621	/*
6622	* Guest GDTR.
6623	*/
6624	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GDTR)
6625	{
6626	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GDTR);
6627
6628	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt); AssertRC(rc);
6629	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt); AssertRC(rc);
6630
6631	/* Validate. */
6632	Assert(!(pCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
6633
6634	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GDTR);
6635	Log4Func(("gdtr base=%#RX64 limit=%#RX32\n", pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt));
6636	}
6637
6638	/*
6639	* Guest LDTR.
6640	*/
6641	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_LDTR)
6642	{
6643	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_LDTR);
6644
6645	/* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
6646	uint32_t u32Access;
6647	if ( !pVmxTransient->fIsNestedGuest
6648	&& !pCtx->ldtr.Attr.u)
6649	u32Access = X86DESCATTR_UNUSABLE;
6650	else
6651	u32Access = pCtx->ldtr.Attr.u;
6652
6653	rc = VMXWriteVmcs16(VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel); AssertRC(rc);
6654	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit); AssertRC(rc);
6655	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access); AssertRC(rc);
6656	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base); AssertRC(rc);
6657
6658	/* Validate. */
6659	if (!(u32Access & X86DESCATTR_UNUSABLE))
6660	{
6661	Assert(!(pCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
6662	Assert(pCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
6663	Assert(!pCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
6664	Assert(pCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
6665	Assert(!pCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
6666	Assert(!(pCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
6667	Assert( (pCtx->ldtr.u32Limit & 0xfff) == 0xfff
6668	\|\| !pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
6669	Assert( !(pCtx->ldtr.u32Limit & 0xfff00000)
6670	\|\| pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
6671	}
6672
6673	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_LDTR);
6674	Log4Func(("ldtr base=%#RX64 limit=%#RX32\n", pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit));
6675	}
6676
6677	/*
6678	* Guest IDTR.
6679	*/
6680	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_IDTR)
6681	{
6682	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_IDTR);
6683
6684	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt); AssertRC(rc);
6685	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt); AssertRC(rc);
6686
6687	/* Validate. */
6688	Assert(!(pCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
6689
6690	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_IDTR);
6691	Log4Func(("idtr base=%#RX64 limit=%#RX32\n", pCtx->idtr.pIdt, pCtx->idtr.cbIdt));
6692	}
6693
6694	return VINF_SUCCESS;
6695	}
6696
6697
6698	/**
6699	* Exports certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
6700	* areas.
6701	*
6702	* These MSRs will automatically be loaded to the host CPU on every successful
6703	* VM-entry and stored from the host CPU on every successful VM-exit.
6704	*
6705	* We creates/updates MSR slots for the host MSRs in the VM-exit MSR-load area. The
6706	* actual host MSR values are not- updated here for performance reasons. See
6707	* hmR0VmxExportHostMsrs().
6708	*
6709	* We also exports the guest sysenter MSRs into the guest-state area in the VMCS.
6710	*
6711	* @returns VBox status code.
6712	* @param pVCpu The cross context virtual CPU structure.
6713	* @param pVmxTransient The VMX-transient structure.
6714	*
6715	* @remarks No-long-jump zone!!!
6716	*/
6717	static int hmR0VmxExportGuestMsrs(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
6718	{
6719	AssertPtr(pVCpu);
6720	AssertPtr(pVmxTransient);
6721
6722	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
6723	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6724
6725	/*
6726	* MSRs that we use the auto-load/store MSR area in the VMCS.
6727	* For 64-bit hosts, we load/restore them lazily, see hmR0VmxLazyLoadGuestMsrs(),
6728	* nothing to do here. The host MSR values are updated when it's safe in
6729	* hmR0VmxLazySaveHostMsrs().
6730	*
6731	* For nested-guests, the guests MSRs from the VM-entry MSR-load area are already
6732	* loaded (into the guest-CPU context) by the VMLAUNCH/VMRESUME instruction
6733	* emulation. The merged MSR permission bitmap will ensure that we get VM-exits
6734	* for any MSR that are not part of the lazy MSRs so we do not need to place
6735	* those MSRs into the auto-load/store MSR area. Nothing to do here.
6736	*/
6737	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_GUEST_AUTO_MSRS)
6738	{
6739	/* No auto-load/store MSRs currently. */
6740	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_GUEST_AUTO_MSRS);
6741	}
6742
6743	/*
6744	* Guest Sysenter MSRs.
6745	*/
6746	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
6747	{
6748	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
6749
6750	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
6751	{
6752	int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
6753	AssertRC(rc);
6754	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_CS_MSR);
6755	}
6756
6757	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
6758	{
6759	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
6760	AssertRC(rc);
6761	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
6762	}
6763
6764	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
6765	{
6766	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
6767	AssertRC(rc);
6768	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
6769	}
6770	}
6771
6772	/*
6773	* Guest/host EFER MSR.
6774	*/
6775	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_EFER_MSR)
6776	{
6777	/* Whether we are using the VMCS to swap the EFER MSR must have been
6778	determined earlier while exporting VM-entry/VM-exit controls. */
6779	Assert(!(ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_ENTRY_EXIT_CTLS));
6780	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
6781
6782	if (hmR0VmxShouldSwapEferMsr(pVCpu, pVmxTransient))
6783	{
6784	/*
6785	* EFER.LME is written by software, while EFER.LMA is set by the CPU to (CR0.PG & EFER.LME).
6786	* This means a guest can set EFER.LME=1 while CR0.PG=0 and EFER.LMA can remain 0.
6787	* VT-x requires that "IA-32e mode guest" VM-entry control must be identical to EFER.LMA
6788	* and to CR0.PG. Without unrestricted execution, CR0.PG (used for VT-x, not the shadow)
6789	* must always be 1. This forces us to effectively clear both EFER.LMA and EFER.LME until
6790	* the guest has also set CR0.PG=1. Otherwise, we would run into an invalid-guest state
6791	* during VM-entry.
6792	*/
6793	uint64_t uGuestEferMsr = pCtx->msrEFER;
6794	if (!pVM->hmr0.s.vmx.fUnrestrictedGuest)
6795	{
6796	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
6797	uGuestEferMsr &= ~MSR_K6_EFER_LME;
6798	else
6799	Assert((pCtx->msrEFER & (MSR_K6_EFER_LMA \| MSR_K6_EFER_LME)) == (MSR_K6_EFER_LMA \| MSR_K6_EFER_LME));
6800	}
6801
6802	/*
6803	* If the CPU supports VMCS controls for swapping EFER, use it. Otherwise, we have no option
6804	* but to use the auto-load store MSR area in the VMCS for swapping EFER. See @bugref{7368}.
6805	*/
6806	if (g_fHmVmxSupportsVmcsEfer)
6807	{
6808	int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, uGuestEferMsr);
6809	AssertRC(rc);
6810	}
6811	else
6812	{
6813	/*
6814	* We shall use the auto-load/store MSR area only for loading the EFER MSR but we must
6815	* continue to intercept guest read and write accesses to it, see @bugref{7386#c16}.
6816	*/
6817	int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, MSR_K6_EFER, uGuestEferMsr,
6818	false /* fSetReadWrite /, false / fUpdateHostMsr */);
6819	AssertRCReturn(rc, rc);
6820	}
6821
6822	Log4Func(("efer=%#RX64 shadow=%#RX64\n", uGuestEferMsr, pCtx->msrEFER));
6823	}
6824	else if (!g_fHmVmxSupportsVmcsEfer)
6825	hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, pVmxTransient, MSR_K6_EFER);
6826
6827	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_EFER_MSR);
6828	}
6829
6830	/*
6831	* Other MSRs.
6832	*/
6833	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_OTHER_MSRS)
6834	{
6835	/* Speculation Control (R/W). */
6836	HMVMX_CPUMCTX_ASSERT(pVCpu, HM_CHANGED_GUEST_OTHER_MSRS);
6837	if (pVM->cpum.ro.GuestFeatures.fIbrs)
6838	{
6839	int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, MSR_IA32_SPEC_CTRL, CPUMGetGuestSpecCtrl(pVCpu),
6840	false /* fSetReadWrite /, false / fUpdateHostMsr */);
6841	AssertRCReturn(rc, rc);
6842	}
6843
6844	/* Last Branch Record. */
6845	if (pVM->hmr0.s.vmx.fLbr)
6846	{
6847	PVMXVMCSINFOSHARED const pVmcsInfoShared = pVmxTransient->pVmcsInfo->pShared;
6848	uint32_t const idFromIpMsrStart = pVM->hmr0.s.vmx.idLbrFromIpMsrFirst;
6849	uint32_t const idToIpMsrStart = pVM->hmr0.s.vmx.idLbrToIpMsrFirst;
6850	uint32_t const cLbrStack = pVM->hmr0.s.vmx.idLbrFromIpMsrLast - pVM->hmr0.s.vmx.idLbrFromIpMsrFirst + 1;
6851	Assert(cLbrStack <= 32);
6852	for (uint32_t i = 0; i < cLbrStack; i++)
6853	{
6854	int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, idFromIpMsrStart + i,
6855	pVmcsInfoShared->au64LbrFromIpMsr[i],
6856	false /* fSetReadWrite /, false / fUpdateHostMsr */);
6857	AssertRCReturn(rc, rc);
6858
6859	/* Some CPUs don't have a Branch-To-IP MSR (P4 and related Xeons). */
6860	if (idToIpMsrStart != 0)
6861	{
6862	rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, idToIpMsrStart + i,
6863	pVmcsInfoShared->au64LbrToIpMsr[i],
6864	false /* fSetReadWrite /, false / fUpdateHostMsr */);
6865	AssertRCReturn(rc, rc);
6866	}
6867	}
6868
6869	/* Add LBR top-of-stack MSR (which contains the index to the most recent record). */
6870	int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, pVM->hmr0.s.vmx.idLbrTosMsr,
6871	pVmcsInfoShared->u64LbrTosMsr, false /* fSetReadWrite */,
6872	false /* fUpdateHostMsr */);
6873	AssertRCReturn(rc, rc);
6874	}
6875
6876	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_OTHER_MSRS);
6877	}
6878
6879	return VINF_SUCCESS;
6880	}
6881
6882
6883	/**
6884	* Wrapper for running the guest code in VT-x.
6885	*
6886	* @returns VBox status code, no informational status codes.
6887	* @param pVCpu The cross context virtual CPU structure.
6888	* @param pVmxTransient The VMX-transient structure.
6889	*
6890	* @remarks No-long-jump zone!!!
6891	*/
6892	DECLINLINE(int) hmR0VmxRunGuest(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
6893	{
6894	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
6895	pVCpu->cpum.GstCtx.fExtrn \|= HMVMX_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
6896
6897	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
6898	bool const fResumeVM = RT_BOOL(pVmcsInfo->fVmcsState & VMX_V_VMCS_LAUNCH_STATE_LAUNCHED);
6899	#ifdef VBOX_WITH_STATISTICS
6900	if (fResumeVM)
6901	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxVmResume);
6902	else
6903	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxVmLaunch);
6904	#endif
6905	int rc = pVCpu->hmr0.s.vmx.pfnStartVm(pVmcsInfo, pVCpu, fResumeVM);
6906	AssertMsg(rc <= VINF_SUCCESS, ("%Rrc\n", rc));
6907	return rc;
6908	}
6909
6910
6911	/**
6912	* Reports world-switch error and dumps some useful debug info.
6913	*
6914	* @param pVCpu The cross context virtual CPU structure.
6915	* @param rcVMRun The return code from VMLAUNCH/VMRESUME.
6916	* @param pVmxTransient The VMX-transient structure (only
6917	* exitReason updated).
6918	*/
6919	static void hmR0VmxReportWorldSwitchError(PVMCPUCC pVCpu, int rcVMRun, PVMXTRANSIENT pVmxTransient)
6920	{
6921	Assert(pVCpu);
6922	Assert(pVmxTransient);
6923	HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
6924
6925	Log4Func(("VM-entry failure: %Rrc\n", rcVMRun));
6926	switch (rcVMRun)
6927	{
6928	case VERR_VMX_INVALID_VMXON_PTR:
6929	AssertFailed();
6930	break;
6931	case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
6932	case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
6933	{
6934	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
6935	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
6936	AssertRC(rc);
6937	hmR0VmxReadExitQualVmcs(pVmxTransient);
6938
6939	pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hmr0.s.idEnteredCpu;
6940	/* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
6941	Cannot do it here as we may have been long preempted. */
6942
6943	#ifdef VBOX_STRICT
6944	PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
6945	Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
6946	pVmxTransient->uExitReason));
6947	Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQual));
6948	Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
6949	if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
6950	Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
6951	else
6952	Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
6953	Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
6954	Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
6955
6956	static struct
6957	{
6958	/** Name of the field to log. */
6959	const char *pszName;
6960	/** The VMCS field. */
6961	uint32_t uVmcsField;
6962	/** Whether host support of this field needs to be checked. */
6963	bool fCheckSupport;
6964	} const s_aVmcsFields[] =
6965	{
6966	{ "VMX_VMCS32_CTRL_PIN_EXEC", VMX_VMCS32_CTRL_PIN_EXEC, false },
6967	{ "VMX_VMCS32_CTRL_PROC_EXEC", VMX_VMCS32_CTRL_PROC_EXEC, false },
6968	{ "VMX_VMCS32_CTRL_PROC_EXEC2", VMX_VMCS32_CTRL_PROC_EXEC2, true },
6969	{ "VMX_VMCS32_CTRL_ENTRY", VMX_VMCS32_CTRL_ENTRY, false },
6970	{ "VMX_VMCS32_CTRL_EXIT", VMX_VMCS32_CTRL_EXIT, false },
6971	{ "VMX_VMCS32_CTRL_CR3_TARGET_COUNT", VMX_VMCS32_CTRL_CR3_TARGET_COUNT, false },
6972	{ "VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO", VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, false },
6973	{ "VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE", VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, false },
6974	{ "VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH", VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, false },
6975	{ "VMX_VMCS32_CTRL_TPR_THRESHOLD", VMX_VMCS32_CTRL_TPR_THRESHOLD, false },
6976	{ "VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT", VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, false },
6977	{ "VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT", VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, false },
6978	{ "VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT", VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, false },
6979	{ "VMX_VMCS32_CTRL_EXCEPTION_BITMAP", VMX_VMCS32_CTRL_EXCEPTION_BITMAP, false },
6980	{ "VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK", VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, false },
6981	{ "VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH", VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, false },
6982	{ "VMX_VMCS_CTRL_CR0_MASK", VMX_VMCS_CTRL_CR0_MASK, false },
6983	{ "VMX_VMCS_CTRL_CR0_READ_SHADOW", VMX_VMCS_CTRL_CR0_READ_SHADOW, false },
6984	{ "VMX_VMCS_CTRL_CR4_MASK", VMX_VMCS_CTRL_CR4_MASK, false },
6985	{ "VMX_VMCS_CTRL_CR4_READ_SHADOW", VMX_VMCS_CTRL_CR4_READ_SHADOW, false },
6986	{ "VMX_VMCS64_CTRL_EPTP_FULL", VMX_VMCS64_CTRL_EPTP_FULL, true },
6987	{ "VMX_VMCS_GUEST_RIP", VMX_VMCS_GUEST_RIP, false },
6988	{ "VMX_VMCS_GUEST_RSP", VMX_VMCS_GUEST_RSP, false },
6989	{ "VMX_VMCS_GUEST_RFLAGS", VMX_VMCS_GUEST_RFLAGS, false },
6990	{ "VMX_VMCS16_VPID", VMX_VMCS16_VPID, true, },
6991	{ "VMX_VMCS_HOST_CR0", VMX_VMCS_HOST_CR0, false },
6992	{ "VMX_VMCS_HOST_CR3", VMX_VMCS_HOST_CR3, false },
6993	{ "VMX_VMCS_HOST_CR4", VMX_VMCS_HOST_CR4, false },
6994	/* The order of selector fields below are fixed! */
6995	{ "VMX_VMCS16_HOST_ES_SEL", VMX_VMCS16_HOST_ES_SEL, false },
6996	{ "VMX_VMCS16_HOST_CS_SEL", VMX_VMCS16_HOST_CS_SEL, false },
6997	{ "VMX_VMCS16_HOST_SS_SEL", VMX_VMCS16_HOST_SS_SEL, false },
6998	{ "VMX_VMCS16_HOST_DS_SEL", VMX_VMCS16_HOST_DS_SEL, false },
6999	{ "VMX_VMCS16_HOST_FS_SEL", VMX_VMCS16_HOST_FS_SEL, false },
7000	{ "VMX_VMCS16_HOST_GS_SEL", VMX_VMCS16_HOST_GS_SEL, false },
7001	{ "VMX_VMCS16_HOST_TR_SEL", VMX_VMCS16_HOST_TR_SEL, false },
7002	/* End of ordered selector fields. */
7003	{ "VMX_VMCS_HOST_TR_BASE", VMX_VMCS_HOST_TR_BASE, false },
7004	{ "VMX_VMCS_HOST_GDTR_BASE", VMX_VMCS_HOST_GDTR_BASE, false },
7005	{ "VMX_VMCS_HOST_IDTR_BASE", VMX_VMCS_HOST_IDTR_BASE, false },
7006	{ "VMX_VMCS32_HOST_SYSENTER_CS", VMX_VMCS32_HOST_SYSENTER_CS, false },
7007	{ "VMX_VMCS_HOST_SYSENTER_EIP", VMX_VMCS_HOST_SYSENTER_EIP, false },
7008	{ "VMX_VMCS_HOST_SYSENTER_ESP", VMX_VMCS_HOST_SYSENTER_ESP, false },
7009	{ "VMX_VMCS_HOST_RSP", VMX_VMCS_HOST_RSP, false },
7010	{ "VMX_VMCS_HOST_RIP", VMX_VMCS_HOST_RIP, false }
7011	};
7012
7013	RTGDTR HostGdtr;
7014	ASMGetGDTR(&HostGdtr);
7015
7016	uint32_t const cVmcsFields = RT_ELEMENTS(s_aVmcsFields);
7017	for (uint32_t i = 0; i < cVmcsFields; i++)
7018	{
7019	uint32_t const uVmcsField = s_aVmcsFields[i].uVmcsField;
7020
7021	bool fSupported;
7022	if (!s_aVmcsFields[i].fCheckSupport)
7023	fSupported = true;
7024	else
7025	{
7026	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7027	switch (uVmcsField)
7028	{
7029	case VMX_VMCS64_CTRL_EPTP_FULL: fSupported = pVM->hmr0.s.fNestedPaging; break;
7030	case VMX_VMCS16_VPID: fSupported = pVM->hmr0.s.vmx.fVpid; break;
7031	case VMX_VMCS32_CTRL_PROC_EXEC2:
7032	fSupported = RT_BOOL(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
7033	break;
7034	default:
7035	AssertMsgFailedReturnVoid(("Failed to provide VMCS field support for %#RX32\n", uVmcsField));
7036	}
7037	}
7038
7039	if (fSupported)
7040	{
7041	uint8_t const uWidth = RT_BF_GET(uVmcsField, VMX_BF_VMCSFIELD_WIDTH);
7042	switch (uWidth)
7043	{
7044	case VMX_VMCSFIELD_WIDTH_16BIT:
7045	{
7046	uint16_t u16Val;
7047	rc = VMXReadVmcs16(uVmcsField, &u16Val);
7048	AssertRC(rc);
7049	Log4(("%-40s = %#RX16\n", s_aVmcsFields[i].pszName, u16Val));
7050
7051	if ( uVmcsField >= VMX_VMCS16_HOST_ES_SEL
7052	&& uVmcsField <= VMX_VMCS16_HOST_TR_SEL)
7053	{
7054	if (u16Val < HostGdtr.cbGdt)
7055	{
7056	/* Order of selectors in s_apszSel is fixed and matches the order in s_aVmcsFields. */
7057	static const char * const s_apszSel[] = { "Host ES", "Host CS", "Host SS", "Host DS",
7058	"Host FS", "Host GS", "Host TR" };
7059	uint8_t const idxSel = RT_BF_GET(uVmcsField, VMX_BF_VMCSFIELD_INDEX);
7060	Assert(idxSel < RT_ELEMENTS(s_apszSel));
7061	PCX86DESCHC pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u16Val & X86_SEL_MASK));
7062	hmR0DumpDescriptor(pDesc, u16Val, s_apszSel[idxSel]);
7063	}
7064	else
7065	Log4((" Selector value exceeds GDT limit!\n"));
7066	}
7067	break;
7068	}
7069
7070	case VMX_VMCSFIELD_WIDTH_32BIT:
7071	{
7072	uint32_t u32Val;
7073	rc = VMXReadVmcs32(uVmcsField, &u32Val);
7074	AssertRC(rc);
7075	Log4(("%-40s = %#RX32\n", s_aVmcsFields[i].pszName, u32Val));
7076	break;
7077	}
7078
7079	case VMX_VMCSFIELD_WIDTH_64BIT:
7080	case VMX_VMCSFIELD_WIDTH_NATURAL:
7081	{
7082	uint64_t u64Val;
7083	rc = VMXReadVmcs64(uVmcsField, &u64Val);
7084	AssertRC(rc);
7085	Log4(("%-40s = %#RX64\n", s_aVmcsFields[i].pszName, u64Val));
7086	break;
7087	}
7088	}
7089	}
7090	}
7091
7092	Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
7093	Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
7094	Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
7095	Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
7096	Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
7097	Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
7098	#endif /* VBOX_STRICT */
7099	break;
7100	}
7101
7102	default:
7103	/* Impossible */
7104	AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
7105	break;
7106	}
7107	}
7108
7109
7110	/**
7111	* Sets up the usage of TSC-offsetting and updates the VMCS.
7112	*
7113	* If offsetting is not possible, cause VM-exits on RDTSC(P)s. Also sets up the
7114	* VMX-preemption timer.
7115	*
7116	* @returns VBox status code.
7117	* @param pVCpu The cross context virtual CPU structure.
7118	* @param pVmxTransient The VMX-transient structure.
7119	* @param idCurrentCpu The current CPU number.
7120	*
7121	* @remarks No-long-jump zone!!!
7122	*/
7123	static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, RTCPUID idCurrentCpu)
7124	{
7125	bool fOffsettedTsc;
7126	bool fParavirtTsc;
7127	uint64_t uTscOffset;
7128	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7129	PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
7130
7131	if (pVM->hmr0.s.vmx.fUsePreemptTimer)
7132	{
7133	/* The TMCpuTickGetDeadlineAndTscOffset function is expensive (calling it on
7134	every entry slowed down the bs2-test1 CPUID testcase by ~33% (on an 10980xe). */
7135	uint64_t cTicksToDeadline;
7136	if ( idCurrentCpu == pVCpu->hmr0.s.idLastCpu
7137	&& TMVirtualSyncIsCurrentDeadlineVersion(pVM, pVCpu->hmr0.s.vmx.uTscDeadlineVersion))
7138	{
7139	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatVmxPreemptionReusingDeadline);
7140	fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
7141	cTicksToDeadline = pVCpu->hmr0.s.vmx.uTscDeadline - SUPReadTsc();
7142	if ((int64_t)cTicksToDeadline > 0)
7143	{ /* hopefully */ }
7144	else
7145	{
7146	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatVmxPreemptionReusingDeadlineExpired);
7147	cTicksToDeadline = 0;
7148	}
7149	}
7150	else
7151	{
7152	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatVmxPreemptionRecalcingDeadline);
7153	cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &uTscOffset, &fOffsettedTsc, &fParavirtTsc,
7154	&pVCpu->hmr0.s.vmx.uTscDeadline,
7155	&pVCpu->hmr0.s.vmx.uTscDeadlineVersion);
7156	pVCpu->hmr0.s.vmx.uTscDeadline += cTicksToDeadline;
7157	if (cTicksToDeadline >= 128)
7158	{ /* hopefully */ }
7159	else
7160	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatVmxPreemptionRecalcingDeadlineExpired);
7161	}
7162
7163	/* Make sure the returned values have sane upper and lower boundaries. */
7164	uint64_t const u64CpuHz = SUPGetCpuHzFromGipBySetIndex(g_pSUPGlobalInfoPage, pVCpu->iHostCpuSet);
7165	cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second, 15.625ms. / /* @todo r=bird: Once real+virtual timers move to separate thread, we can raise the upper limit (16ms isn't much). ASSUMES working poke cpu function. */
7166	cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 32678); /* 1/32768th of a second, ~30us. */
7167	cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
7168
7169	/** @todo r=ramshankar: We need to find a way to integrate nested-guest
7170	* preemption timers here. We probably need to clamp the preemption timer,
7171	* after converting the timer value to the host. */
7172	uint32_t const cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
7173	int rc = VMXWriteVmcs32(VMX_VMCS32_PREEMPT_TIMER_VALUE, cPreemptionTickCount);
7174	AssertRC(rc);
7175	}
7176	else
7177	fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
7178
7179	if (fParavirtTsc)
7180	{
7181	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
7182	information before every VM-entry, hence disable it for performance sake. */
7183	#if 0
7184	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
7185	AssertRC(rc);
7186	#endif
7187	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
7188	}
7189
7190	if ( fOffsettedTsc
7191	&& RT_LIKELY(!pVCpu->hmr0.s.fDebugWantRdTscExit))
7192	{
7193	if (pVmxTransient->fIsNestedGuest)
7194	uTscOffset = CPUMApplyNestedGuestTscOffset(pVCpu, uTscOffset);
7195	hmR0VmxSetTscOffsetVmcs(pVmcsInfo, uTscOffset);
7196	hmR0VmxRemoveProcCtlsVmcs(pVCpu, pVmxTransient, VMX_PROC_CTLS_RDTSC_EXIT);
7197	}
7198	else
7199	{
7200	/* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
7201	hmR0VmxSetProcCtlsVmcs(pVmxTransient, VMX_PROC_CTLS_RDTSC_EXIT);
7202	}
7203	}
7204
7205
7206	/**
7207	* Gets the IEM exception flags for the specified vector and IDT vectoring /
7208	* VM-exit interruption info type.
7209	*
7210	* @returns The IEM exception flags.
7211	* @param uVector The event vector.
7212	* @param uVmxEventType The VMX event type.
7213	*
7214	* @remarks This function currently only constructs flags required for
7215	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g, error-code
7216	* and CR2 aspects of an exception are not included).
7217	*/
7218	static uint32_t hmR0VmxGetIemXcptFlags(uint8_t uVector, uint32_t uVmxEventType)
7219	{
7220	uint32_t fIemXcptFlags;
7221	switch (uVmxEventType)
7222	{
7223	case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
7224	case VMX_IDT_VECTORING_INFO_TYPE_NMI:
7225	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
7226	break;
7227
7228	case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
7229	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
7230	break;
7231
7232	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
7233	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_ICEBP_INSTR;
7234	break;
7235
7236	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT:
7237	{
7238	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
7239	if (uVector == X86_XCPT_BP)
7240	fIemXcptFlags \|= IEM_XCPT_FLAGS_BP_INSTR;
7241	else if (uVector == X86_XCPT_OF)
7242	fIemXcptFlags \|= IEM_XCPT_FLAGS_OF_INSTR;
7243	else
7244	{
7245	fIemXcptFlags = 0;
7246	AssertMsgFailed(("Unexpected vector for software exception. uVector=%#x", uVector));
7247	}
7248	break;
7249	}
7250
7251	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
7252	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
7253	break;
7254
7255	default:
7256	fIemXcptFlags = 0;
7257	AssertMsgFailed(("Unexpected vector type! uVmxEventType=%#x uVector=%#x", uVmxEventType, uVector));
7258	break;
7259	}
7260	return fIemXcptFlags;
7261	}
7262
7263
7264	/**
7265	* Sets an event as a pending event to be injected into the guest.
7266	*
7267	* @param pVCpu The cross context virtual CPU structure.
7268	* @param u32IntInfo The VM-entry interruption-information field.
7269	* @param cbInstr The VM-entry instruction length in bytes (for
7270	* software interrupts, exceptions and privileged
7271	* software exceptions).
7272	* @param u32ErrCode The VM-entry exception error code.
7273	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
7274	* page-fault.
7275	*/
7276	DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPUCC pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
7277	RTGCUINTPTR GCPtrFaultAddress)
7278	{
7279	Assert(!pVCpu->hm.s.Event.fPending);
7280	pVCpu->hm.s.Event.fPending = true;
7281	pVCpu->hm.s.Event.u64IntInfo = u32IntInfo;
7282	pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
7283	pVCpu->hm.s.Event.cbInstr = cbInstr;
7284	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
7285	}
7286
7287
7288	/**
7289	* Sets an external interrupt as pending-for-injection into the VM.
7290	*
7291	* @param pVCpu The cross context virtual CPU structure.
7292	* @param u8Interrupt The external interrupt vector.
7293	*/
7294	DECLINLINE(void) hmR0VmxSetPendingExtInt(PVMCPUCC pVCpu, uint8_t u8Interrupt)
7295	{
7296	uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, u8Interrupt)
7297	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
7298	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
7299	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7300	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7301	}
7302
7303
7304	/**
7305	* Sets an NMI (\#NMI) exception as pending-for-injection into the VM.
7306	*
7307	* @param pVCpu The cross context virtual CPU structure.
7308	*/
7309	DECLINLINE(void) hmR0VmxSetPendingXcptNmi(PVMCPUCC pVCpu)
7310	{
7311	uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)
7312	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI)
7313	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
7314	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7315	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7316	}
7317
7318
7319	/**
7320	* Sets a double-fault (\#DF) exception as pending-for-injection into the VM.
7321	*
7322	* @param pVCpu The cross context virtual CPU structure.
7323	*/
7324	DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPUCC pVCpu)
7325	{
7326	uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DF)
7327	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
7328	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
7329	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7330	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7331	}
7332
7333
7334	/**
7335	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
7336	*
7337	* @param pVCpu The cross context virtual CPU structure.
7338	*/
7339	DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPUCC pVCpu)
7340	{
7341	uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_UD)
7342	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
7343	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
7344	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7345	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7346	}
7347
7348
7349	/**
7350	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
7351	*
7352	* @param pVCpu The cross context virtual CPU structure.
7353	*/
7354	DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPUCC pVCpu)
7355	{
7356	uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
7357	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
7358	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
7359	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7360	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7361	}
7362
7363
7364	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7365	/**
7366	* Sets a general-protection (\#GP) exception as pending-for-injection into the VM.
7367	*
7368	* @param pVCpu The cross context virtual CPU structure.
7369	* @param u32ErrCode The error code for the general-protection exception.
7370	*/
7371	DECLINLINE(void) hmR0VmxSetPendingXcptGP(PVMCPUCC pVCpu, uint32_t u32ErrCode)
7372	{
7373	uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_GP)
7374	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
7375	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
7376	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7377	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, u32ErrCode, 0 / GCPtrFaultAddress */);
7378	}
7379
7380
7381	/**
7382	* Sets a stack (\#SS) exception as pending-for-injection into the VM.
7383	*
7384	* @param pVCpu The cross context virtual CPU structure.
7385	* @param u32ErrCode The error code for the stack exception.
7386	*/
7387	DECLINLINE(void) hmR0VmxSetPendingXcptSS(PVMCPUCC pVCpu, uint32_t u32ErrCode)
7388	{
7389	uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_SS)
7390	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
7391	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
7392	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
7393	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, u32ErrCode, 0 / GCPtrFaultAddress */);
7394	}
7395	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
7396
7397
7398	/**
7399	* Fixes up attributes for the specified segment register.
7400	*
7401	* @param pVCpu The cross context virtual CPU structure.
7402	* @param pSelReg The segment register that needs fixing.
7403	* @param pszRegName The register name (for logging and assertions).
7404	*/
7405	static void hmR0VmxFixUnusableSegRegAttr(PVMCPUCC pVCpu, PCPUMSELREG pSelReg, const char *pszRegName)
7406	{
7407	Assert(pSelReg->Attr.u & X86DESCATTR_UNUSABLE);
7408
7409	/*
7410	* If VT-x marks the segment as unusable, most other bits remain undefined:
7411	* - For CS the L, D and G bits have meaning.
7412	* - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
7413	* - For the remaining data segments no bits are defined.
7414	*
7415	* The present bit and the unusable bit has been observed to be set at the
7416	* same time (the selector was supposed to be invalid as we started executing
7417	* a V8086 interrupt in ring-0).
7418	*
7419	* What should be important for the rest of the VBox code, is that the P bit is
7420	* cleared. Some of the other VBox code recognizes the unusable bit, but
7421	* AMD-V certainly don't, and REM doesn't really either. So, to be on the
7422	* safe side here, we'll strip off P and other bits we don't care about. If
7423	* any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
7424	*
7425	* See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
7426	*/
7427	#ifdef VBOX_STRICT
7428	uint32_t const uAttr = pSelReg->Attr.u;
7429	#endif
7430
7431	/* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
7432	pSelReg->Attr.u &= X86DESCATTR_UNUSABLE \| X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
7433	\| X86DESCATTR_DPL \| X86DESCATTR_TYPE \| X86DESCATTR_DT;
7434
7435	#ifdef VBOX_STRICT
7436	VMMRZCallRing3Disable(pVCpu);
7437	Log4Func(("Unusable %s: sel=%#x attr=%#x -> %#x\n", pszRegName, pSelReg->Sel, uAttr, pSelReg->Attr.u));
7438	# ifdef DEBUG_bird
7439	AssertMsg((uAttr & ~X86DESCATTR_P) == pSelReg->Attr.u,
7440	("%s: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
7441	pszRegName, uAttr, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
7442	# endif
7443	VMMRZCallRing3Enable(pVCpu);
7444	NOREF(uAttr);
7445	#endif
7446	RT_NOREF2(pVCpu, pszRegName);
7447	}
7448
7449
7450	/**
7451	* Imports a guest segment register from the current VMCS into the guest-CPU
7452	* context.
7453	*
7454	* @param pVCpu The cross context virtual CPU structure.
7455	* @param iSegReg The segment register number (X86_SREG_XXX).
7456	*
7457	* @remarks Called with interrupts and/or preemption disabled.
7458	*/
7459	static void hmR0VmxImportGuestSegReg(PVMCPUCC pVCpu, uint32_t iSegReg)
7460	{
7461	Assert(iSegReg < X86_SREG_COUNT);
7462	Assert((uint32_t)VMX_VMCS16_GUEST_SEG_SEL(iSegReg) == g_aVmcsSegSel[iSegReg]);
7463	Assert((uint32_t)VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg) == g_aVmcsSegLimit[iSegReg]);
7464	Assert((uint32_t)VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg) == g_aVmcsSegAttr[iSegReg]);
7465	Assert((uint32_t)VMX_VMCS_GUEST_SEG_BASE(iSegReg) == g_aVmcsSegBase[iSegReg]);
7466
7467	PCPUMSELREG pSelReg = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
7468
7469	uint16_t u16Sel;
7470	int rc = VMXReadVmcs16(VMX_VMCS16_GUEST_SEG_SEL(iSegReg), &u16Sel); AssertRC(rc);
7471	pSelReg->Sel = u16Sel;
7472	pSelReg->ValidSel = u16Sel;
7473
7474	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SEG_LIMIT(iSegReg), &pSelReg->u32Limit); AssertRC(rc);
7475	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_SEG_BASE(iSegReg), &pSelReg->u64Base); AssertRC(rc);
7476
7477	uint32_t u32Attr;
7478	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(iSegReg), &u32Attr); AssertRC(rc);
7479	pSelReg->Attr.u = u32Attr;
7480	if (u32Attr & X86DESCATTR_UNUSABLE)
7481	hmR0VmxFixUnusableSegRegAttr(pVCpu, pSelReg, "ES\0CS\0SS\0DS\0FS\0GS" + iSegReg * 3);
7482
7483	pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
7484	}
7485
7486
7487	/**
7488	* Imports the guest LDTR from the current VMCS into the guest-CPU context.
7489	*
7490	* @param pVCpu The cross context virtual CPU structure.
7491	*
7492	* @remarks Called with interrupts and/or preemption disabled.
7493	*/
7494	static void hmR0VmxImportGuestLdtr(PVMCPUCC pVCpu)
7495	{
7496	uint16_t u16Sel;
7497	uint64_t u64Base;
7498	uint32_t u32Limit, u32Attr;
7499	int rc = VMXReadVmcs16(VMX_VMCS16_GUEST_LDTR_SEL, &u16Sel); AssertRC(rc);
7500	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, &u32Limit); AssertRC(rc);
7501	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, &u32Attr); AssertRC(rc);
7502	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_LDTR_BASE, &u64Base); AssertRC(rc);
7503
7504	pVCpu->cpum.GstCtx.ldtr.Sel = u16Sel;
7505	pVCpu->cpum.GstCtx.ldtr.ValidSel = u16Sel;
7506	pVCpu->cpum.GstCtx.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
7507	pVCpu->cpum.GstCtx.ldtr.u32Limit = u32Limit;
7508	pVCpu->cpum.GstCtx.ldtr.u64Base = u64Base;
7509	pVCpu->cpum.GstCtx.ldtr.Attr.u = u32Attr;
7510	if (u32Attr & X86DESCATTR_UNUSABLE)
7511	hmR0VmxFixUnusableSegRegAttr(pVCpu, &pVCpu->cpum.GstCtx.ldtr, "LDTR");
7512	}
7513
7514
7515	/**
7516	* Imports the guest TR from the current VMCS into the guest-CPU context.
7517	*
7518	* @param pVCpu The cross context virtual CPU structure.
7519	*
7520	* @remarks Called with interrupts and/or preemption disabled.
7521	*/
7522	static void hmR0VmxImportGuestTr(PVMCPUCC pVCpu)
7523	{
7524	uint16_t u16Sel;
7525	uint64_t u64Base;
7526	uint32_t u32Limit, u32Attr;
7527	int rc = VMXReadVmcs16(VMX_VMCS16_GUEST_TR_SEL, &u16Sel); AssertRC(rc);
7528	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, &u32Limit); AssertRC(rc);
7529	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, &u32Attr); AssertRC(rc);
7530	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_TR_BASE, &u64Base); AssertRC(rc);
7531
7532	pVCpu->cpum.GstCtx.tr.Sel = u16Sel;
7533	pVCpu->cpum.GstCtx.tr.ValidSel = u16Sel;
7534	pVCpu->cpum.GstCtx.tr.fFlags = CPUMSELREG_FLAGS_VALID;
7535	pVCpu->cpum.GstCtx.tr.u32Limit = u32Limit;
7536	pVCpu->cpum.GstCtx.tr.u64Base = u64Base;
7537	pVCpu->cpum.GstCtx.tr.Attr.u = u32Attr;
7538	/* TR is the only selector that can never be unusable. */
7539	Assert(!(u32Attr & X86DESCATTR_UNUSABLE));
7540	}
7541
7542
7543	/**
7544	* Imports the guest RIP from the VMCS back into the guest-CPU context.
7545	*
7546	* @param pVCpu The cross context virtual CPU structure.
7547	*
7548	* @remarks Called with interrupts and/or preemption disabled, should not assert!
7549	* @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
7550	* instead!!!
7551	*/
7552	static void hmR0VmxImportGuestRip(PVMCPUCC pVCpu)
7553	{
7554	uint64_t u64Val;
7555	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7556	if (pCtx->fExtrn & CPUMCTX_EXTRN_RIP)
7557	{
7558	int rc = VMXReadVmcsNw(VMX_VMCS_GUEST_RIP, &u64Val);
7559	AssertRC(rc);
7560
7561	pCtx->rip = u64Val;
7562	EMR0HistoryUpdatePC(pVCpu, pCtx->rip, false);
7563	pCtx->fExtrn &= ~CPUMCTX_EXTRN_RIP;
7564	}
7565	}
7566
7567
7568	/**
7569	* Imports the guest RFLAGS from the VMCS back into the guest-CPU context.
7570	*
7571	* @param pVCpu The cross context virtual CPU structure.
7572	* @param pVmcsInfo The VMCS info. object.
7573	*
7574	* @remarks Called with interrupts and/or preemption disabled, should not assert!
7575	* @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
7576	* instead!!!
7577	*/
7578	static void hmR0VmxImportGuestRFlags(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo)
7579	{
7580	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7581	if (pCtx->fExtrn & CPUMCTX_EXTRN_RFLAGS)
7582	{
7583	uint64_t u64Val;
7584	int rc = VMXReadVmcsNw(VMX_VMCS_GUEST_RFLAGS, &u64Val);
7585	AssertRC(rc);
7586
7587	pCtx->rflags.u64 = u64Val;
7588	PCVMXVMCSINFOSHARED pVmcsInfoShared = pVmcsInfo->pShared;
7589	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
7590	{
7591	pCtx->eflags.Bits.u1VM = 0;
7592	pCtx->eflags.Bits.u2IOPL = pVmcsInfoShared->RealMode.Eflags.Bits.u2IOPL;
7593	}
7594	pCtx->fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
7595	}
7596	}
7597
7598
7599	/**
7600	* Imports the guest interruptibility-state from the VMCS back into the guest-CPU
7601	* context.
7602	*
7603	* @param pVCpu The cross context virtual CPU structure.
7604	* @param pVmcsInfo The VMCS info. object.
7605	*
7606	* @remarks Called with interrupts and/or preemption disabled, try not to assert and
7607	* do not log!
7608	* @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
7609	* instead!!!
7610	*/
7611	static void hmR0VmxImportGuestIntrState(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo)
7612	{
7613	uint32_t u32Val;
7614	int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32Val); AssertRC(rc);
7615	if (!u32Val)
7616	{
7617	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7618	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7619	CPUMSetGuestNmiBlocking(pVCpu, false);
7620	}
7621	else
7622	{
7623	/*
7624	* We must import RIP here to set our EM interrupt-inhibited state.
7625	* We also import RFLAGS as our code that evaluates pending interrupts
7626	* before VM-entry requires it.
7627	*/
7628	hmR0VmxImportGuestRip(pVCpu);
7629	hmR0VmxImportGuestRFlags(pVCpu, pVmcsInfo);
7630
7631	if (u32Val & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS \| VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
7632	EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
7633	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
7634	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
7635
7636	bool const fNmiBlocking = RT_BOOL(u32Val & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI);
7637	CPUMSetGuestNmiBlocking(pVCpu, fNmiBlocking);
7638	}
7639	}
7640
7641
7642	/**
7643	* Worker for VMXR0ImportStateOnDemand.
7644	*
7645	* @returns VBox status code.
7646	* @param pVCpu The cross context virtual CPU structure.
7647	* @param pVmcsInfo The VMCS info. object.
7648	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
7649	*/
7650	static int hmR0VmxImportGuestState(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint64_t fWhat)
7651	{
7652	int rc = VINF_SUCCESS;
7653	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
7654	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7655	uint32_t u32Val;
7656
7657	/*
7658	* Note! This is hack to workaround a mysterious BSOD observed with release builds
7659	* on Windows 10 64-bit hosts. Profile and debug builds are not affected and
7660	* neither are other host platforms.
7661	*
7662	* Committing this temporarily as it prevents BSOD.
7663	*
7664	* Update: This is very likely a compiler optimization bug, see @bugref{9180}.
7665	*/
7666	#ifdef RT_OS_WINDOWS
7667	if (pVM == 0 \|\| pVM == (void *)(uintptr_t)-1)
7668	return VERR_HM_IPE_1;
7669	#endif
7670
7671	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
7672
7673	/*
7674	* We disable interrupts to make the updating of the state and in particular
7675	* the fExtrn modification atomic wrt to preemption hooks.
7676	*/
7677	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
7678
7679	fWhat &= pCtx->fExtrn;
7680	if (fWhat)
7681	{
7682	do
7683	{
7684	if (fWhat & CPUMCTX_EXTRN_RIP)
7685	hmR0VmxImportGuestRip(pVCpu);
7686
7687	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
7688	hmR0VmxImportGuestRFlags(pVCpu, pVmcsInfo);
7689
7690	if (fWhat & CPUMCTX_EXTRN_HM_VMX_INT_STATE)
7691	hmR0VmxImportGuestIntrState(pVCpu, pVmcsInfo);
7692
7693	if (fWhat & CPUMCTX_EXTRN_RSP)
7694	{
7695	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_RSP, &pCtx->rsp);
7696	AssertRC(rc);
7697	}
7698
7699	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
7700	{
7701	PVMXVMCSINFOSHARED pVmcsInfoShared = pVmcsInfo->pShared;
7702	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
7703	if (fWhat & CPUMCTX_EXTRN_CS)
7704	{
7705	hmR0VmxImportGuestSegReg(pVCpu, X86_SREG_CS);
7706	hmR0VmxImportGuestRip(pVCpu);
7707	if (fRealOnV86Active)
7708	pCtx->cs.Attr.u = pVmcsInfoShared->RealMode.AttrCS.u;
7709	EMR0HistoryUpdatePC(pVCpu, pCtx->cs.u64Base + pCtx->rip, true /* fFlattened */);
7710	}
7711	if (fWhat & CPUMCTX_EXTRN_SS)
7712	{
7713	hmR0VmxImportGuestSegReg(pVCpu, X86_SREG_SS);
7714	if (fRealOnV86Active)
7715	pCtx->ss.Attr.u = pVmcsInfoShared->RealMode.AttrSS.u;
7716	}
7717	if (fWhat & CPUMCTX_EXTRN_DS)
7718	{
7719	hmR0VmxImportGuestSegReg(pVCpu, X86_SREG_DS);
7720	if (fRealOnV86Active)
7721	pCtx->ds.Attr.u = pVmcsInfoShared->RealMode.AttrDS.u;
7722	}
7723	if (fWhat & CPUMCTX_EXTRN_ES)
7724	{
7725	hmR0VmxImportGuestSegReg(pVCpu, X86_SREG_ES);
7726	if (fRealOnV86Active)
7727	pCtx->es.Attr.u = pVmcsInfoShared->RealMode.AttrES.u;
7728	}
7729	if (fWhat & CPUMCTX_EXTRN_FS)
7730	{
7731	hmR0VmxImportGuestSegReg(pVCpu, X86_SREG_FS);
7732	if (fRealOnV86Active)
7733	pCtx->fs.Attr.u = pVmcsInfoShared->RealMode.AttrFS.u;
7734	}
7735	if (fWhat & CPUMCTX_EXTRN_GS)
7736	{
7737	hmR0VmxImportGuestSegReg(pVCpu, X86_SREG_GS);
7738	if (fRealOnV86Active)
7739	pCtx->gs.Attr.u = pVmcsInfoShared->RealMode.AttrGS.u;
7740	}
7741	}
7742
7743	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
7744	{
7745	if (fWhat & CPUMCTX_EXTRN_LDTR)
7746	hmR0VmxImportGuestLdtr(pVCpu);
7747
7748	if (fWhat & CPUMCTX_EXTRN_GDTR)
7749	{
7750	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_GDTR_BASE, &pCtx->gdtr.pGdt); AssertRC(rc);
7751	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); AssertRC(rc);
7752	pCtx->gdtr.cbGdt = u32Val;
7753	}
7754
7755	/* Guest IDTR. */
7756	if (fWhat & CPUMCTX_EXTRN_IDTR)
7757	{
7758	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_IDTR_BASE, &pCtx->idtr.pIdt); AssertRC(rc);
7759	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); AssertRC(rc);
7760	pCtx->idtr.cbIdt = u32Val;
7761	}
7762
7763	/* Guest TR. */
7764	if (fWhat & CPUMCTX_EXTRN_TR)
7765	{
7766	/* Real-mode emulation using virtual-8086 mode has the fake TSS (pRealModeTSS) in TR,
7767	don't need to import that one. */
7768	if (!pVmcsInfo->pShared->RealMode.fRealOnV86Active)
7769	hmR0VmxImportGuestTr(pVCpu);
7770	}
7771	}
7772
7773	if (fWhat & CPUMCTX_EXTRN_DR7)
7774	{
7775	if (!pVCpu->hmr0.s.fUsingHyperDR7)
7776	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_DR7, &pCtx->dr[7]); AssertRC(rc);
7777	}
7778
7779	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
7780	{
7781	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_SYSENTER_EIP, &pCtx->SysEnter.eip); AssertRC(rc);
7782	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_SYSENTER_ESP, &pCtx->SysEnter.esp); AssertRC(rc);
7783	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val); AssertRC(rc);
7784	pCtx->SysEnter.cs = u32Val;
7785	}
7786
7787	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
7788	{
7789	if ( pVM->hmr0.s.fAllow64BitGuests
7790	&& (pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
7791	pCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
7792	}
7793
7794	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
7795	{
7796	if ( pVM->hmr0.s.fAllow64BitGuests
7797	&& (pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
7798	{
7799	pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
7800	pCtx->msrSTAR = ASMRdMsr(MSR_K6_STAR);
7801	pCtx->msrSFMASK = ASMRdMsr(MSR_K8_SF_MASK);
7802	}
7803	}
7804
7805	if (fWhat & (CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
7806	{
7807	PVMXVMCSINFOSHARED pVmcsInfoShared = pVmcsInfo->pShared;
7808	PCVMXAUTOMSR pMsrs = (PCVMXAUTOMSR)pVmcsInfo->pvGuestMsrStore;
7809	uint32_t const cMsrs = pVmcsInfo->cExitMsrStore;
7810	Assert(pMsrs);
7811	Assert(cMsrs <= VMX_MISC_MAX_MSRS(g_HmMsrs.u.vmx.u64Misc));
7812	Assert(sizeof(pMsrs) cMsrs <= X86_PAGE_4K_SIZE);
7813	for (uint32_t i = 0; i < cMsrs; i++)
7814	{
7815	uint32_t const idMsr = pMsrs[i].u32Msr;
7816	switch (idMsr)
7817	{
7818	case MSR_K8_TSC_AUX: CPUMSetGuestTscAux(pVCpu, pMsrs[i].u64Value); break;
7819	case MSR_IA32_SPEC_CTRL: CPUMSetGuestSpecCtrl(pVCpu, pMsrs[i].u64Value); break;
7820	case MSR_K6_EFER: /* Can't be changed without causing a VM-exit */ break;
7821	default:
7822	{
7823	uint32_t idxLbrMsr;
7824	if (pVM->hmr0.s.vmx.fLbr)
7825	{
7826	if (hmR0VmxIsLbrBranchFromMsr(pVM, idMsr, &idxLbrMsr))
7827	{
7828	Assert(idxLbrMsr < RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr));
7829	pVmcsInfoShared->au64LbrFromIpMsr[idxLbrMsr] = pMsrs[i].u64Value;
7830	break;
7831	}
7832	if (hmR0VmxIsLbrBranchToMsr(pVM, idMsr, &idxLbrMsr))
7833	{
7834	Assert(idxLbrMsr < RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr));
7835	pVmcsInfoShared->au64LbrToIpMsr[idxLbrMsr] = pMsrs[i].u64Value;
7836	break;
7837	}
7838	if (idMsr == pVM->hmr0.s.vmx.idLbrTosMsr)
7839	{
7840	pVmcsInfoShared->u64LbrTosMsr = pMsrs[i].u64Value;
7841	break;
7842	}
7843	/* Fallthru (no break) */
7844	}
7845	pCtx->fExtrn = 0;
7846	pVCpu->hm.s.u32HMError = pMsrs->u32Msr;
7847	ASMSetFlags(fEFlags);
7848	AssertMsgFailed(("Unexpected MSR in auto-load/store area. idMsr=%#RX32 cMsrs=%u\n", idMsr, cMsrs));
7849	return VERR_HM_UNEXPECTED_LD_ST_MSR;
7850	}
7851	}
7852	}
7853	}
7854
7855	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
7856	{
7857	if (fWhat & CPUMCTX_EXTRN_CR0)
7858	{
7859	uint64_t u64Cr0;
7860	uint64_t u64Shadow;
7861	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_CR0, &u64Cr0); AssertRC(rc);
7862	rc = VMXReadVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, &u64Shadow); AssertRC(rc);
7863	#ifndef VBOX_WITH_NESTED_HWVIRT_VMX
7864	u64Cr0 = (u64Cr0 & ~pVmcsInfo->u64Cr0Mask)
7865	\| (u64Shadow & pVmcsInfo->u64Cr0Mask);
7866	#else
7867	if (!CPUMIsGuestInVmxNonRootMode(pCtx))
7868	{
7869	u64Cr0 = (u64Cr0 & ~pVmcsInfo->u64Cr0Mask)
7870	\| (u64Shadow & pVmcsInfo->u64Cr0Mask);
7871	}
7872	else
7873	{
7874	/*
7875	* We've merged the guest and nested-guest's CR0 guest/host mask while executing
7876	* the nested-guest using hardware-assisted VMX. Accordingly we need to
7877	* re-construct CR0. See @bugref{9180#c95} for details.
7878	*/
7879	PCVMXVMCSINFO pVmcsInfoGst = &pVCpu->hmr0.s.vmx.VmcsInfo;
7880	PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7881	u64Cr0 = (u64Cr0 & ~pVmcsInfo->u64Cr0Mask)
7882	\| (pVmcsNstGst->u64GuestCr0.u & pVmcsNstGst->u64Cr0Mask.u)
7883	\| (u64Shadow & (pVmcsInfoGst->u64Cr0Mask & ~pVmcsNstGst->u64Cr0Mask.u));
7884	}
7885	#endif
7886	VMMRZCallRing3Disable(pVCpu); /* May call into PGM which has Log statements. */
7887	CPUMSetGuestCR0(pVCpu, u64Cr0);
7888	VMMRZCallRing3Enable(pVCpu);
7889	}
7890
7891	if (fWhat & CPUMCTX_EXTRN_CR4)
7892	{
7893	uint64_t u64Cr4;
7894	uint64_t u64Shadow;
7895	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_CR4, &u64Cr4); AssertRC(rc);
7896	rc \|= VMXReadVmcsNw(VMX_VMCS_CTRL_CR4_READ_SHADOW, &u64Shadow); AssertRC(rc);
7897	#ifndef VBOX_WITH_NESTED_HWVIRT_VMX
7898	u64Cr4 = (u64Cr4 & ~pVmcsInfo->u64Cr4Mask)
7899	\| (u64Shadow & pVmcsInfo->u64Cr4Mask);
7900	#else
7901	if (!CPUMIsGuestInVmxNonRootMode(pCtx))
7902	{
7903	u64Cr4 = (u64Cr4 & ~pVmcsInfo->u64Cr4Mask)
7904	\| (u64Shadow & pVmcsInfo->u64Cr4Mask);
7905	}
7906	else
7907	{
7908	/*
7909	* We've merged the guest and nested-guest's CR4 guest/host mask while executing
7910	* the nested-guest using hardware-assisted VMX. Accordingly we need to
7911	* re-construct CR4. See @bugref{9180#c95} for details.
7912	*/
7913	PCVMXVMCSINFO pVmcsInfoGst = &pVCpu->hmr0.s.vmx.VmcsInfo;
7914	PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
7915	u64Cr4 = (u64Cr4 & ~pVmcsInfo->u64Cr4Mask)
7916	\| (pVmcsNstGst->u64GuestCr4.u & pVmcsNstGst->u64Cr4Mask.u)
7917	\| (u64Shadow & (pVmcsInfoGst->u64Cr4Mask & ~pVmcsNstGst->u64Cr4Mask.u));
7918	}
7919	#endif
7920	pCtx->cr4 = u64Cr4;
7921	}
7922
7923	if (fWhat & CPUMCTX_EXTRN_CR3)
7924	{
7925	/* CR0.PG bit changes are always intercepted, so it's up to date. */
7926	if ( pVM->hmr0.s.vmx.fUnrestrictedGuest
7927	\|\| ( pVM->hmr0.s.fNestedPaging
7928	&& CPUMIsGuestPagingEnabledEx(pCtx)))
7929	{
7930	uint64_t u64Cr3;
7931	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_CR3, &u64Cr3); AssertRC(rc);
7932	if (pCtx->cr3 != u64Cr3)
7933	{
7934	pCtx->cr3 = u64Cr3;
7935	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
7936	}
7937
7938	/* If the guest is in PAE mode, sync back the PDPE's into the guest state.
7939	Note: CR4.PAE, CR0.PG, EFER MSR changes are always intercepted, so they're up to date. */
7940	if (CPUMIsGuestInPAEModeEx(pCtx))
7941	{
7942	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u); AssertRC(rc);
7943	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u); AssertRC(rc);
7944	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u); AssertRC(rc);
7945	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u); AssertRC(rc);
7946	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
7947	}
7948	}
7949	}
7950	}
7951
7952	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
7953	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
7954	{
7955	if ( (pVmcsInfo->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING)
7956	&& !CPUMIsGuestInVmxNonRootMode(pCtx))
7957	{
7958	Assert(CPUMIsGuestInVmxRootMode(pCtx));
7959	rc = hmR0VmxCopyShadowToNstGstVmcs(pVCpu, pVmcsInfo);
7960	if (RT_SUCCESS(rc))
7961	{ /* likely */ }
7962	else
7963	break;
7964	}
7965	}
7966	#endif
7967	} while (0);
7968
7969	if (RT_SUCCESS(rc))
7970	{
7971	/* Update fExtrn. */
7972	pCtx->fExtrn &= ~fWhat;
7973
7974	/* If everything has been imported, clear the HM keeper bit. */
7975	if (!(pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL))
7976	{
7977	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
7978	Assert(!pCtx->fExtrn);
7979	}
7980	}
7981	}
7982	else
7983	AssertMsg(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL), ("%#RX64\n", pCtx->fExtrn));
7984
7985	/*
7986	* Restore interrupts.
7987	*/
7988	ASMSetFlags(fEFlags);
7989
7990	STAM_PROFILE_ADV_STOP(& pVCpu->hm.s.StatImportGuestState, x);
7991
7992	if (RT_SUCCESS(rc))
7993	{ /* likely */ }
7994	else
7995	return rc;
7996
7997	/*
7998	* Honor any pending CR3 updates.
7999	*
8000	* Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> VMXR0CallRing3Callback()
8001	* -> VMMRZCallRing3Disable() -> hmR0VmxImportGuestState() -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
8002	* -> continue with VM-exit handling -> hmR0VmxImportGuestState() and here we are.
8003	*
8004	* The reason for such complicated handling is because VM-exits that call into PGM expect CR3 to be up-to-date and thus
8005	* if any CR3-saves -before- the VM-exit (longjmp) postponed the CR3 update via the force-flag, any VM-exit handler that
8006	* calls into PGM when it re-saves CR3 will end up here and we call PGMUpdateCR3(). This is why the code below should
8007	* -NOT- check if CPUMCTX_EXTRN_CR3 is set!
8008	*
8009	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
8010	*/
8011	if (VMMRZCallRing3IsEnabled(pVCpu))
8012	{
8013	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
8014	{
8015	Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_CR3));
8016	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
8017	}
8018
8019	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
8020	PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
8021
8022	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
8023	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
8024	}
8025
8026	return VINF_SUCCESS;
8027	}
8028
8029
8030	/**
8031	* Saves the guest state from the VMCS into the guest-CPU context.
8032	*
8033	* @returns VBox status code.
8034	* @param pVCpu The cross context virtual CPU structure.
8035	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
8036	*/
8037	VMMR0DECL(int) VMXR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
8038	{
8039	AssertPtr(pVCpu);
8040	PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
8041	return hmR0VmxImportGuestState(pVCpu, pVmcsInfo, fWhat);
8042	}
8043
8044
8045	/**
8046	* Check per-VM and per-VCPU force flag actions that require us to go back to
8047	* ring-3 for one reason or another.
8048	*
8049	* @returns Strict VBox status code (i.e. informational status codes too)
8050	* @retval VINF_SUCCESS if we don't have any actions that require going back to
8051	* ring-3.
8052	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
8053	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
8054	* interrupts)
8055	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
8056	* all EMTs to be in ring-3.
8057	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
8058	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
8059	* to the EM loop.
8060	*
8061	* @param pVCpu The cross context virtual CPU structure.
8062	* @param pVmxTransient The VMX-transient structure.
8063	* @param fStepping Whether we are single-stepping the guest using the
8064	* hypervisor debugger.
8065	*
8066	* @remarks This might cause nested-guest VM-exits, caller must check if the guest
8067	* is no longer in VMX non-root mode.
8068	*/
8069	static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, bool fStepping)
8070	{
8071	Assert(VMMRZCallRing3IsEnabled(pVCpu));
8072
8073	/*
8074	* Update pending interrupts into the APIC's IRR.
8075	*/
8076	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
8077	APICUpdatePendingInterrupts(pVCpu);
8078
8079	/*
8080	* Anything pending? Should be more likely than not if we're doing a good job.
8081	*/
8082	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
8083	if ( !fStepping
8084	? !VM_FF_IS_ANY_SET(pVM, VM_FF_HP_R0_PRE_HM_MASK)
8085	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)
8086	: !VM_FF_IS_ANY_SET(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK)
8087	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
8088	return VINF_SUCCESS;
8089
8090	/* Pending PGM C3 sync. */
8091	if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
8092	{
8093	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
8094	Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & (CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4)));
8095	VBOXSTRICTRC rcStrict = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4,
8096	VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
8097	if (rcStrict != VINF_SUCCESS)
8098	{
8099	AssertRC(VBOXSTRICTRC_VAL(rcStrict));
8100	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
8101	return rcStrict;
8102	}
8103	}
8104
8105	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
8106	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
8107	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
8108	{
8109	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
8110	int rc = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
8111	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
8112	return rc;
8113	}
8114
8115	/* Pending VM request packets, such as hardware interrupts. */
8116	if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
8117	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
8118	{
8119	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchVmReq);
8120	Log4Func(("Pending VM request forcing us back to ring-3\n"));
8121	return VINF_EM_PENDING_REQUEST;
8122	}
8123
8124	/* Pending PGM pool flushes. */
8125	if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
8126	{
8127	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPgmPoolFlush);
8128	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
8129	return VINF_PGM_POOL_FLUSH_PENDING;
8130	}
8131
8132	/* Pending DMA requests. */
8133	if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
8134	{
8135	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchDma);
8136	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
8137	return VINF_EM_RAW_TO_R3;
8138	}
8139
8140	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8141	/*
8142	* Pending nested-guest events.
8143	*
8144	* Please note the priority of these events are specified and important.
8145	* See Intel spec. 29.4.3.2 "APIC-Write Emulation".
8146	* See Intel spec. 6.9 "Priority Among Simultaneous Exceptions And Interrupts".
8147	*/
8148	if (pVmxTransient->fIsNestedGuest)
8149	{
8150	/* Pending nested-guest APIC-write. */
8151	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE))
8152	{
8153	Log4Func(("Pending nested-guest APIC-write\n"));
8154	VBOXSTRICTRC rcStrict = IEMExecVmxVmexitApicWrite(pVCpu);
8155	Assert(rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE);
8156	return rcStrict;
8157	}
8158
8159	/* Pending nested-guest monitor-trap flag (MTF). */
8160	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_MTF))
8161	{
8162	Log4Func(("Pending nested-guest MTF\n"));
8163	VBOXSTRICTRC rcStrict = IEMExecVmxVmexit(pVCpu, VMX_EXIT_MTF, 0 /* uExitQual */);
8164	Assert(rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE);
8165	return rcStrict;
8166	}
8167
8168	/* Pending nested-guest VMX-preemption timer expired. */
8169	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER))
8170	{
8171	Log4Func(("Pending nested-guest preempt timer\n"));
8172	VBOXSTRICTRC rcStrict = IEMExecVmxVmexitPreemptTimer(pVCpu);
8173	Assert(rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE);
8174	return rcStrict;
8175	}
8176	}
8177	#else
8178	NOREF(pVmxTransient);
8179	#endif
8180
8181	return VINF_SUCCESS;
8182	}
8183
8184
8185	/**
8186	* Converts any TRPM trap into a pending HM event. This is typically used when
8187	* entering from ring-3 (not longjmp returns).
8188	*
8189	* @param pVCpu The cross context virtual CPU structure.
8190	*/
8191	static void hmR0VmxTrpmTrapToPendingEvent(PVMCPUCC pVCpu)
8192	{
8193	Assert(TRPMHasTrap(pVCpu));
8194	Assert(!pVCpu->hm.s.Event.fPending);
8195
8196	uint8_t uVector;
8197	TRPMEVENT enmTrpmEvent;
8198	uint32_t uErrCode;
8199	RTGCUINTPTR GCPtrFaultAddress;
8200	uint8_t cbInstr;
8201	bool fIcebp;
8202
8203	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr, &fIcebp);
8204	AssertRC(rc);
8205
8206	uint32_t u32IntInfo;
8207	u32IntInfo = uVector \| VMX_IDT_VECTORING_INFO_VALID;
8208	u32IntInfo \|= HMTrpmEventTypeToVmxEventType(uVector, enmTrpmEvent, fIcebp);
8209
8210	rc = TRPMResetTrap(pVCpu);
8211	AssertRC(rc);
8212	Log4(("TRPM->HM event: u32IntInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
8213	u32IntInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
8214
8215	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, uErrCode, GCPtrFaultAddress);
8216	}
8217
8218
8219	/**
8220	* Converts the pending HM event into a TRPM trap.
8221	*
8222	* @param pVCpu The cross context virtual CPU structure.
8223	*/
8224	static void hmR0VmxPendingEventToTrpmTrap(PVMCPUCC pVCpu)
8225	{
8226	Assert(pVCpu->hm.s.Event.fPending);
8227
8228	/* If a trap was already pending, we did something wrong! */
8229	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
8230
8231	uint32_t const u32IntInfo = pVCpu->hm.s.Event.u64IntInfo;
8232	uint32_t const uVector = VMX_IDT_VECTORING_INFO_VECTOR(u32IntInfo);
8233	TRPMEVENT const enmTrapType = HMVmxEventTypeToTrpmEventType(u32IntInfo);
8234
8235	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
8236
8237	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
8238	AssertRC(rc);
8239
8240	if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(u32IntInfo))
8241	TRPMSetErrorCode(pVCpu, pVCpu->hm.s.Event.u32ErrCode);
8242
8243	if (VMX_IDT_VECTORING_INFO_IS_XCPT_PF(u32IntInfo))
8244	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
8245	else
8246	{
8247	uint8_t const uVectorType = VMX_IDT_VECTORING_INFO_TYPE(u32IntInfo);
8248	switch (uVectorType)
8249	{
8250	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
8251	TRPMSetTrapDueToIcebp(pVCpu);
8252	RT_FALL_THRU();
8253	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
8254	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT:
8255	{
8256	AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
8257	\|\| ( uVector == X86_XCPT_BP /* INT3 */
8258	\|\| uVector == X86_XCPT_OF /* INTO */
8259	\|\| uVector == X86_XCPT_DB /* INT1 (ICEBP) */),
8260	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
8261	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
8262	break;
8263	}
8264	}
8265	}
8266
8267	/* We're now done converting the pending event. */
8268	pVCpu->hm.s.Event.fPending = false;
8269	}
8270
8271
8272	/**
8273	* Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
8274	* cause a VM-exit as soon as the guest is in a state to receive interrupts.
8275	*
8276	* @param pVmcsInfo The VMCS info. object.
8277	*/
8278	static void hmR0VmxSetIntWindowExitVmcs(PVMXVMCSINFO pVmcsInfo)
8279	{
8280	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_INT_WINDOW_EXIT)
8281	{
8282	if (!(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
8283	{
8284	pVmcsInfo->u32ProcCtls \|= VMX_PROC_CTLS_INT_WINDOW_EXIT;
8285	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
8286	AssertRC(rc);
8287	}
8288	} /* else we will deliver interrupts whenever the guest Vm-exits next and is in a state to receive the interrupt. */
8289	}
8290
8291
8292	/**
8293	* Clears the interrupt-window exiting control in the VMCS.
8294	*
8295	* @param pVmcsInfo The VMCS info. object.
8296	*/
8297	DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMXVMCSINFO pVmcsInfo)
8298	{
8299	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
8300	{
8301	pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_INT_WINDOW_EXIT;
8302	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
8303	AssertRC(rc);
8304	}
8305	}
8306
8307
8308	/**
8309	* Sets the NMI-window exiting control in the VMCS which instructs VT-x to
8310	* cause a VM-exit as soon as the guest is in a state to receive NMIs.
8311	*
8312	* @param pVmcsInfo The VMCS info. object.
8313	*/
8314	static void hmR0VmxSetNmiWindowExitVmcs(PVMXVMCSINFO pVmcsInfo)
8315	{
8316	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
8317	{
8318	if (!(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
8319	{
8320	pVmcsInfo->u32ProcCtls \|= VMX_PROC_CTLS_NMI_WINDOW_EXIT;
8321	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
8322	AssertRC(rc);
8323	Log4Func(("Setup NMI-window exiting\n"));
8324	}
8325	} /* else we will deliver NMIs whenever we VM-exit next, even possibly nesting NMIs. Can't be helped on ancient CPUs. */
8326	}
8327
8328
8329	/**
8330	* Clears the NMI-window exiting control in the VMCS.
8331	*
8332	* @param pVmcsInfo The VMCS info. object.
8333	*/
8334	DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMXVMCSINFO pVmcsInfo)
8335	{
8336	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
8337	{
8338	pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_NMI_WINDOW_EXIT;
8339	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
8340	AssertRC(rc);
8341	}
8342	}
8343
8344
8345	/**
8346	* Does the necessary state syncing before returning to ring-3 for any reason
8347	* (longjmp, preemption, voluntary exits to ring-3) from VT-x.
8348	*
8349	* @returns VBox status code.
8350	* @param pVCpu The cross context virtual CPU structure.
8351	* @param fImportState Whether to import the guest state from the VMCS back
8352	* to the guest-CPU context.
8353	*
8354	* @remarks No-long-jmp zone!!!
8355	*/
8356	static int hmR0VmxLeave(PVMCPUCC pVCpu, bool fImportState)
8357	{
8358	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8359	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8360
8361	RTCPUID const idCpu = RTMpCpuId();
8362	Log4Func(("HostCpuId=%u\n", idCpu));
8363
8364	/*
8365	* !!! IMPORTANT !!!
8366	* If you modify code here, check whether VMXR0CallRing3Callback() needs to be updated too.
8367	*/
8368
8369	/* Save the guest state if necessary. */
8370	PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
8371	if (fImportState)
8372	{
8373	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
8374	AssertRCReturn(rc, rc);
8375	}
8376
8377	/* Restore host FPU state if necessary. We will resync on next R0 reentry. */
8378	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
8379	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
8380
8381	/* Restore host debug registers if necessary. We will resync on next R0 reentry. */
8382	#ifdef VBOX_STRICT
8383	if (CPUMIsHyperDebugStateActive(pVCpu))
8384	Assert(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
8385	#endif
8386	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
8387	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
8388	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
8389
8390	/* Restore host-state bits that VT-x only restores partially. */
8391	if (pVCpu->hmr0.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
8392	{
8393	Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hmr0.s.vmx.fRestoreHostFlags, idCpu));
8394	VMXRestoreHostState(pVCpu->hmr0.s.vmx.fRestoreHostFlags, &pVCpu->hmr0.s.vmx.RestoreHost);
8395	}
8396	pVCpu->hmr0.s.vmx.fRestoreHostFlags = 0;
8397
8398	/* Restore the lazy host MSRs as we're leaving VT-x context. */
8399	if (pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
8400	{
8401	/* We shouldn't restore the host MSRs without saving the guest MSRs first. */
8402	if (!fImportState)
8403	{
8404	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS);
8405	AssertRCReturn(rc, rc);
8406	}
8407	hmR0VmxLazyRestoreHostMsrs(pVCpu);
8408	Assert(!pVCpu->hmr0.s.vmx.fLazyMsrs);
8409	}
8410	else
8411	pVCpu->hmr0.s.vmx.fLazyMsrs = 0;
8412
8413	/* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
8414	pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs = false;
8415
8416	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
8417	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
8418	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
8419	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
8420	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
8421	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
8422	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
8423	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
8424	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitVmentry);
8425	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
8426
8427	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
8428
8429	/** @todo This partially defeats the purpose of having preemption hooks.
8430	* The problem is, deregistering the hooks should be moved to a place that
8431	* lasts until the EMT is about to be destroyed not everytime while leaving HM
8432	* context.
8433	*/
8434	int rc = hmR0VmxClearVmcs(pVmcsInfo);
8435	AssertRCReturn(rc, rc);
8436
8437	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
8438	/*
8439	* A valid shadow VMCS is made active as part of VM-entry. It is necessary to
8440	* clear a shadow VMCS before allowing that VMCS to become active on another
8441	* logical processor. We may or may not be importing guest state which clears
8442	* it, so cover for it here.
8443	*
8444	* See Intel spec. 24.11.1 "Software Use of Virtual-Machine Control Structures".
8445	*/
8446	if ( pVmcsInfo->pvShadowVmcs
8447	&& pVmcsInfo->fShadowVmcsState != VMX_V_VMCS_LAUNCH_STATE_CLEAR)
8448	{
8449	rc = hmR0VmxClearShadowVmcs(pVmcsInfo);
8450	AssertRCReturn(rc, rc);
8451	}
8452
8453	/*
8454	* Flag that we need to re-export the host state if we switch to this VMCS before
8455	* executing guest or nested-guest code.
8456	*/
8457	pVmcsInfo->idHostCpuState = NIL_RTCPUID;
8458	#endif
8459
8460	Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
8461	NOREF(idCpu);
8462	return VINF_SUCCESS;
8463	}
8464
8465
8466	/**
8467	* Leaves the VT-x session.
8468	*
8469	* @returns VBox status code.
8470	* @param pVCpu The cross context virtual CPU structure.
8471	*
8472	* @remarks No-long-jmp zone!!!
8473	*/
8474	static int hmR0VmxLeaveSession(PVMCPUCC pVCpu)
8475	{
8476	HM_DISABLE_PREEMPT(pVCpu);
8477	HMVMX_ASSERT_CPU_SAFE(pVCpu);
8478	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8479	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8480
8481	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
8482	and done this from the VMXR0ThreadCtxCallback(). */
8483	if (!pVCpu->hmr0.s.fLeaveDone)
8484	{
8485	int rc2 = hmR0VmxLeave(pVCpu, true /* fImportState */);
8486	AssertRCReturnStmt(rc2, HM_RESTORE_PREEMPT(), rc2);
8487	pVCpu->hmr0.s.fLeaveDone = true;
8488	}
8489	Assert(!pVCpu->cpum.GstCtx.fExtrn);
8490
8491	/*
8492	* !!! IMPORTANT !!!
8493	* If you modify code here, make sure to check whether VMXR0CallRing3Callback() needs to be updated too.
8494	*/
8495
8496	/* Deregister hook now that we've left HM context before re-enabling preemption. */
8497	/** @todo Deregistering here means we need to VMCLEAR always
8498	* (longjmp/exit-to-r3) in VT-x which is not efficient, eliminate need
8499	* for calling VMMR0ThreadCtxHookDisable here! */
8500	VMMR0ThreadCtxHookDisable(pVCpu);
8501
8502	/* Leave HM context. This takes care of local init (term) and deregistering the longjmp-to-ring-3 callback. */
8503	int rc = HMR0LeaveCpu(pVCpu);
8504	HM_RESTORE_PREEMPT();
8505	return rc;
8506	}
8507
8508
8509	/**
8510	* Does the necessary state syncing before doing a longjmp to ring-3.
8511	*
8512	* @returns VBox status code.
8513	* @param pVCpu The cross context virtual CPU structure.
8514	*
8515	* @remarks No-long-jmp zone!!!
8516	*/
8517	DECLINLINE(int) hmR0VmxLongJmpToRing3(PVMCPUCC pVCpu)
8518	{
8519	return hmR0VmxLeaveSession(pVCpu);
8520	}
8521
8522
8523	/**
8524	* Take necessary actions before going back to ring-3.
8525	*
8526	* An action requires us to go back to ring-3. This function does the necessary
8527	* steps before we can safely return to ring-3. This is not the same as longjmps
8528	* to ring-3, this is voluntary and prepares the guest so it may continue
8529	* executing outside HM (recompiler/IEM).
8530	*
8531	* @returns VBox status code.
8532	* @param pVCpu The cross context virtual CPU structure.
8533	* @param rcExit The reason for exiting to ring-3. Can be
8534	* VINF_VMM_UNKNOWN_RING3_CALL.
8535	*/
8536	static int hmR0VmxExitToRing3(PVMCPUCC pVCpu, VBOXSTRICTRC rcExit)
8537	{
8538	HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8539
8540	PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
8541	if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
8542	{
8543	VMXGetCurrentVmcs(&pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs);
8544	pVCpu->hm.s.vmx.LastError.u32VmcsRev = (uint32_t )pVmcsInfo->pvVmcs;
8545	pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hmr0.s.idEnteredCpu;
8546	/* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
8547	}
8548
8549	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
8550	VMMRZCallRing3Disable(pVCpu);
8551	Log4Func(("rcExit=%d\n", VBOXSTRICTRC_VAL(rcExit)));
8552
8553	/*
8554	* Convert any pending HM events back to TRPM due to premature exits to ring-3.
8555	* We need to do this only on returns to ring-3 and not for longjmps to ring3.
8556	*
8557	* This is because execution may continue from ring-3 and we would need to inject
8558	* the event from there (hence place it back in TRPM).
8559	*/
8560	if (pVCpu->hm.s.Event.fPending)
8561	{
8562	hmR0VmxPendingEventToTrpmTrap(pVCpu);
8563	Assert(!pVCpu->hm.s.Event.fPending);
8564
8565	/* Clear the events from the VMCS. */
8566	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc);
8567	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0); AssertRC(rc);
8568	}
8569	#ifdef VBOX_STRICT
8570	/*
8571	* We check for rcExit here since for errors like VERR_VMX_UNABLE_TO_START_VM (which are
8572	* fatal), we don't care about verifying duplicate injection of events. Errors like
8573	* VERR_EM_INTERPRET are converted to their VINF_* counterparts -prior- to calling this
8574	* function so those should and will be checked below.
8575	*/
8576	else if (RT_SUCCESS(rcExit))
8577	{
8578	/*
8579	* Ensure we don't accidentally clear a pending HM event without clearing the VMCS.
8580	* This can be pretty hard to debug otherwise, interrupts might get injected twice
8581	* occasionally, see @bugref{9180#c42}.
8582	*
8583	* However, if the VM-entry failed, any VM entry-interruption info. field would
8584	* be left unmodified as the event would not have been injected to the guest. In
8585	* such cases, don't assert, we're not going to continue guest execution anyway.
8586	*/
8587	uint32_t uExitReason;
8588	uint32_t uEntryIntInfo;
8589	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
8590	rc \|= VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &uEntryIntInfo);
8591	AssertRC(rc);
8592	AssertMsg(VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason) \|\| !VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo),
8593	("uExitReason=%#RX32 uEntryIntInfo=%#RX32 rcExit=%d\n", uExitReason, uEntryIntInfo, VBOXSTRICTRC_VAL(rcExit)));
8594	}
8595	#endif
8596
8597	/*
8598	* Clear the interrupt-window and NMI-window VMCS controls as we could have got
8599	* a VM-exit with higher priority than interrupt-window or NMI-window VM-exits
8600	* (e.g. TPR below threshold).
8601	*/
8602	if (!CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
8603	{
8604	hmR0VmxClearIntWindowExitVmcs(pVmcsInfo);
8605	hmR0VmxClearNmiWindowExitVmcs(pVmcsInfo);
8606	}
8607
8608	/* If we're emulating an instruction, we shouldn't have any TRPM traps pending
8609	and if we're injecting an event we should have a TRPM trap pending. */
8610	AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
8611	#ifndef DEBUG_bird /* Triggered after firing an NMI against NT4SP1, possibly a triple fault in progress. */
8612	AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
8613	#endif
8614
8615	/* Save guest state and restore host state bits. */
8616	int rc = hmR0VmxLeaveSession(pVCpu);
8617	AssertRCReturn(rc, rc);
8618	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
8619
8620	/* Thread-context hooks are unregistered at this point!!! */
8621	/* Ring-3 callback notifications are unregistered at this point!!! */
8622
8623	/* Sync recompiler state. */
8624	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
8625	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
8626	\| CPUM_CHANGED_LDTR
8627	\| CPUM_CHANGED_GDTR
8628	\| CPUM_CHANGED_IDTR
8629	\| CPUM_CHANGED_TR
8630	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
8631	if ( pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging
8632	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
8633	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
8634
8635	Assert(!pVCpu->hmr0.s.fClearTrapFlag);
8636
8637	/* Update the exit-to-ring 3 reason. */
8638	pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
8639
8640	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
8641	if ( rcExit != VINF_EM_RAW_INTERRUPT
8642	\|\| CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
8643	{
8644	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMVMX_CPUMCTX_EXTRN_ALL));
8645	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
8646	}
8647
8648	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
8649	VMMRZCallRing3Enable(pVCpu);
8650	return rc;
8651	}
8652
8653
8654	/**
8655	* VMMRZCallRing3() callback wrapper which saves the guest state before we
8656	* longjump to ring-3 and possibly get preempted.
8657	*
8658	* @returns VBox status code.
8659	* @param pVCpu The cross context virtual CPU structure.
8660	* @param enmOperation The operation causing the ring-3 longjump.
8661	*/
8662	VMMR0DECL(int) VMXR0CallRing3Callback(PVMCPUCC pVCpu, VMMCALLRING3 enmOperation)
8663	{
8664	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
8665	{
8666	/*
8667	* !!! IMPORTANT !!!
8668	* If you modify code here, check whether hmR0VmxLeave() and hmR0VmxLeaveSession() needs to be updated too.
8669	* This is a stripped down version which gets out ASAP, trying to not trigger any further assertions.
8670	*/
8671	VMMRZCallRing3RemoveNotification(pVCpu);
8672	VMMRZCallRing3Disable(pVCpu);
8673	HM_DISABLE_PREEMPT(pVCpu);
8674
8675	PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
8676	hmR0VmxImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
8677	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
8678	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
8679
8680	/* Restore host-state bits that VT-x only restores partially. */
8681	if (pVCpu->hmr0.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
8682	VMXRestoreHostState(pVCpu->hmr0.s.vmx.fRestoreHostFlags, &pVCpu->hmr0.s.vmx.RestoreHost);
8683	pVCpu->hmr0.s.vmx.fRestoreHostFlags = 0;
8684
8685	/* Restore the lazy host MSRs as we're leaving VT-x context. */
8686	if (pVCpu->hmr0.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
8687	hmR0VmxLazyRestoreHostMsrs(pVCpu);
8688
8689	/* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
8690	pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs = false;
8691	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
8692
8693	/* Clear the current VMCS data back to memory (shadow VMCS if any would have been
8694	cleared as part of importing the guest state above. */
8695	hmR0VmxClearVmcs(pVmcsInfo);
8696
8697	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
8698	VMMR0ThreadCtxHookDisable(pVCpu);
8699
8700	/* Leave HM context. This takes care of local init (term). */
8701	HMR0LeaveCpu(pVCpu);
8702	HM_RESTORE_PREEMPT();
8703	return VINF_SUCCESS;
8704	}
8705
8706	Assert(pVCpu);
8707	Assert(VMMRZCallRing3IsEnabled(pVCpu));
8708	HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8709
8710	VMMRZCallRing3Disable(pVCpu);
8711	Assert(VMMR0IsLogFlushDisabled(pVCpu));
8712
8713	Log4Func(("-> hmR0VmxLongJmpToRing3 enmOperation=%d\n", enmOperation));
8714
8715	int rc = hmR0VmxLongJmpToRing3(pVCpu);
8716	AssertRCReturn(rc, rc);
8717
8718	VMMRZCallRing3Enable(pVCpu);
8719	return VINF_SUCCESS;
8720	}
8721
8722
8723	/**
8724	* Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
8725	* stack.
8726	*
8727	* @returns Strict VBox status code (i.e. informational status codes too).
8728	* @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
8729	* @param pVCpu The cross context virtual CPU structure.
8730	* @param uValue The value to push to the guest stack.
8731	*/
8732	static VBOXSTRICTRC hmR0VmxRealModeGuestStackPush(PVMCPUCC pVCpu, uint16_t uValue)
8733	{
8734	/*
8735	* The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
8736	* virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
8737	* See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
8738	*/
8739	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
8740	if (pCtx->sp == 1)
8741	return VINF_EM_RESET;
8742	pCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
8743	int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->ss.u64Base + pCtx->sp, &uValue, sizeof(uint16_t));
8744	AssertRC(rc);
8745	return rc;
8746	}
8747
8748
8749	/**
8750	* Injects an event into the guest upon VM-entry by updating the relevant fields
8751	* in the VM-entry area in the VMCS.
8752	*
8753	* @returns Strict VBox status code (i.e. informational status codes too).
8754	* @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
8755	* @retval VINF_EM_RESET if event injection resulted in a triple-fault.
8756	*
8757	* @param pVCpu The cross context virtual CPU structure.
8758	* @param pVmxTransient The VMX-transient structure.
8759	* @param pEvent The event being injected.
8760	* @param pfIntrState Pointer to the VT-x guest-interruptibility-state. This
8761	* will be updated if necessary. This cannot not be NULL.
8762	* @param fStepping Whether we're single-stepping guest execution and should
8763	* return VINF_EM_DBG_STEPPED if the event is injected
8764	* directly (registers modified by us, not by hardware on
8765	* VM-entry).
8766	*/
8767	static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, PCHMEVENT pEvent, bool fStepping,
8768	uint32_t *pfIntrState)
8769	{
8770	/* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
8771	AssertMsg(!RT_HI_U32(pEvent->u64IntInfo), ("%#RX64\n", pEvent->u64IntInfo));
8772	Assert(pfIntrState);
8773
8774	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
8775	uint32_t u32IntInfo = pEvent->u64IntInfo;
8776	uint32_t const u32ErrCode = pEvent->u32ErrCode;
8777	uint32_t const cbInstr = pEvent->cbInstr;
8778	RTGCUINTPTR const GCPtrFault = pEvent->GCPtrFaultAddress;
8779	uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(u32IntInfo);
8780	uint32_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(u32IntInfo);
8781
8782	#ifdef VBOX_STRICT
8783	/*
8784	* Validate the error-code-valid bit for hardware exceptions.
8785	* No error codes for exceptions in real-mode.
8786	*
8787	* See Intel spec. 20.1.4 "Interrupt and Exception Handling"
8788	*/
8789	if ( uIntType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
8790	&& !CPUMIsGuestInRealModeEx(pCtx))
8791	{
8792	switch (uVector)
8793	{
8794	case X86_XCPT_PF:
8795	case X86_XCPT_DF:
8796	case X86_XCPT_TS:
8797	case X86_XCPT_NP:
8798	case X86_XCPT_SS:
8799	case X86_XCPT_GP:
8800	case X86_XCPT_AC:
8801	AssertMsg(VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo),
8802	("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
8803	RT_FALL_THRU();
8804	default:
8805	break;
8806	}
8807	}
8808
8809	/* Cannot inject an NMI when block-by-MOV SS is in effect. */
8810	Assert( uIntType != VMX_EXIT_INT_INFO_TYPE_NMI
8811	\|\| !(*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
8812	#endif
8813
8814	if ( uIntType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
8815	\|\| uIntType == VMX_EXIT_INT_INFO_TYPE_NMI
8816	\|\| uIntType == VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT
8817	\|\| uIntType == VMX_EXIT_INT_INFO_TYPE_SW_XCPT)
8818	{
8819	Assert(uVector <= X86_XCPT_LAST);
8820	Assert(uIntType != VMX_EXIT_INT_INFO_TYPE_NMI \|\| uVector == X86_XCPT_NMI);
8821	Assert(uIntType != VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT \|\| uVector == X86_XCPT_DB);
8822	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedXcptsR0[uVector]);
8823	}
8824	else
8825	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
8826
8827	/*
8828	* Hardware interrupts & exceptions cannot be delivered through the software interrupt
8829	* redirection bitmap to the real mode task in virtual-8086 mode. We must jump to the
8830	* interrupt handler in the (real-mode) guest.
8831	*
8832	* See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode".
8833	* See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
8834	*/
8835	if (CPUMIsGuestInRealModeEx(pCtx)) /* CR0.PE bit changes are always intercepted, so it's up to date. */
8836	{
8837	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fUnrestrictedGuest)
8838	{
8839	/*
8840	* For CPUs with unrestricted guest execution enabled and with the guest
8841	* in real-mode, we must not set the deliver-error-code bit.
8842	*
8843	* See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
8844	*/
8845	u32IntInfo &= ~VMX_ENTRY_INT_INFO_ERROR_CODE_VALID;
8846	}
8847	else
8848	{
8849	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
8850	Assert(PDMVmmDevHeapIsEnabled(pVM));
8851	Assert(pVM->hm.s.vmx.pRealModeTSS);
8852	Assert(!CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx));
8853
8854	/* We require RIP, RSP, RFLAGS, CS, IDTR, import them. */
8855	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
8856	int rc2 = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_TABLE_MASK
8857	\| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RFLAGS);
8858	AssertRCReturn(rc2, rc2);
8859
8860	/* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
8861	size_t const cbIdtEntry = sizeof(X86IDTR16);
8862	if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pCtx->idtr.cbIdt)
8863	{
8864	/* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
8865	if (uVector == X86_XCPT_DF)
8866	return VINF_EM_RESET;
8867
8868	/* If we're injecting a #GP with no valid IDT entry, inject a double-fault.
8869	No error codes for exceptions in real-mode. */
8870	if (uVector == X86_XCPT_GP)
8871	{
8872	uint32_t const uXcptDfInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DF)
8873	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
8874	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
8875	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
8876	HMEVENT EventXcptDf;
8877	RT_ZERO(EventXcptDf);
8878	EventXcptDf.u64IntInfo = uXcptDfInfo;
8879	return hmR0VmxInjectEventVmcs(pVCpu, pVmxTransient, &EventXcptDf, fStepping, pfIntrState);
8880	}
8881
8882	/*
8883	* If we're injecting an event with no valid IDT entry, inject a #GP.
8884	* No error codes for exceptions in real-mode.
8885	*
8886	* See Intel spec. 20.1.4 "Interrupt and Exception Handling"
8887	*/
8888	uint32_t const uXcptGpInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_GP)
8889	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT)
8890	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
8891	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
8892	HMEVENT EventXcptGp;
8893	RT_ZERO(EventXcptGp);
8894	EventXcptGp.u64IntInfo = uXcptGpInfo;
8895	return hmR0VmxInjectEventVmcs(pVCpu, pVmxTransient, &EventXcptGp, fStepping, pfIntrState);
8896	}
8897
8898	/* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
8899	uint16_t uGuestIp = pCtx->ip;
8900	if (uIntType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT)
8901	{
8902	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF);
8903	/* #BP and #OF are both benign traps, we need to resume the next instruction. */
8904	uGuestIp = pCtx->ip + (uint16_t)cbInstr;
8905	}
8906	else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_SW_INT)
8907	uGuestIp = pCtx->ip + (uint16_t)cbInstr;
8908
8909	/* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
8910	X86IDTR16 IdtEntry;
8911	RTGCPHYS const GCPhysIdtEntry = (RTGCPHYS)pCtx->idtr.pIdt + uVector * cbIdtEntry;
8912	rc2 = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
8913	AssertRCReturn(rc2, rc2);
8914
8915	/* Construct the stack frame for the interrupt/exception handler. */
8916	VBOXSTRICTRC rcStrict;
8917	rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->eflags.u32);
8918	if (rcStrict == VINF_SUCCESS)
8919	{
8920	rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->cs.Sel);
8921	if (rcStrict == VINF_SUCCESS)
8922	rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, uGuestIp);
8923	}
8924
8925	/* Clear the required eflag bits and jump to the interrupt/exception handler. */
8926	if (rcStrict == VINF_SUCCESS)
8927	{
8928	pCtx->eflags.u32 &= ~(X86_EFL_IF \| X86_EFL_TF \| X86_EFL_RF \| X86_EFL_AC);
8929	pCtx->rip = IdtEntry.offSel;
8930	pCtx->cs.Sel = IdtEntry.uSel;
8931	pCtx->cs.ValidSel = IdtEntry.uSel;
8932	pCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
8933	if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
8934	&& uVector == X86_XCPT_PF)
8935	pCtx->cr2 = GCPtrFault;
8936
8937	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CS \| HM_CHANGED_GUEST_CR2
8938	\| HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS
8939	\| HM_CHANGED_GUEST_RSP);
8940
8941	/*
8942	* If we delivered a hardware exception (other than an NMI) and if there was
8943	* block-by-STI in effect, we should clear it.
8944	*/
8945	if (*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
8946	{
8947	Assert( uIntType != VMX_ENTRY_INT_INFO_TYPE_NMI
8948	&& uIntType != VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
8949	Log4Func(("Clearing inhibition due to STI\n"));
8950	*pfIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
8951	}
8952
8953	Log4(("Injected real-mode: u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x Eflags=%#x CS:EIP=%04x:%04x\n",
8954	u32IntInfo, u32ErrCode, cbInstr, pCtx->eflags.u, pCtx->cs.Sel, pCtx->eip));
8955
8956	/*
8957	* The event has been truly dispatched to the guest. Mark it as no longer pending so
8958	* we don't attempt to undo it if we are returning to ring-3 before executing guest code.
8959	*/
8960	pVCpu->hm.s.Event.fPending = false;
8961
8962	/*
8963	* If we eventually support nested-guest execution without unrestricted guest execution,
8964	* we should set fInterceptEvents here.
8965	*/
8966	Assert(!pVmxTransient->fIsNestedGuest);
8967
8968	/* If we're stepping and we've changed cs:rip above, bail out of the VMX R0 execution loop. */
8969	if (fStepping)
8970	rcStrict = VINF_EM_DBG_STEPPED;
8971	}
8972	AssertMsg(rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_EM_RESET \|\| (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8973	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8974	return rcStrict;
8975	}
8976	}
8977
8978	/*
8979	* Validate.
8980	*/
8981	Assert(VMX_ENTRY_INT_INFO_IS_VALID(u32IntInfo)); /* Bit 31 (Valid bit) must be set by caller. */
8982	Assert(!(u32IntInfo & VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK)); /* Bits 30:12 MBZ. */
8983
8984	/*
8985	* Inject the event into the VMCS.
8986	*/
8987	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
8988	if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo))
8989	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
8990	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
8991	AssertRC(rc);
8992
8993	/*
8994	* Update guest CR2 if this is a page-fault.
8995	*/
8996	if (VMX_ENTRY_INT_INFO_IS_XCPT_PF(u32IntInfo))
8997	pCtx->cr2 = GCPtrFault;
8998
8999	Log4(("Injecting u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x CR2=%#RX64\n", u32IntInfo, u32ErrCode, cbInstr, pCtx->cr2));
9000	return VINF_SUCCESS;
9001	}
9002
9003
9004	/**
9005	* Evaluates the event to be delivered to the guest and sets it as the pending
9006	* event.
9007	*
9008	* Toggling of interrupt force-flags here is safe since we update TRPM on premature
9009	* exits to ring-3 before executing guest code, see hmR0VmxExitToRing3(). We must
9010	* NOT restore these force-flags.
9011	*
9012	* @returns Strict VBox status code (i.e. informational status codes too).
9013	* @param pVCpu The cross context virtual CPU structure.
9014	* @param pVmxTransient The VMX-transient structure.
9015	* @param pfIntrState Where to store the VT-x guest-interruptibility state.
9016	*/
9017	static VBOXSTRICTRC hmR0VmxEvaluatePendingEvent(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint32_t *pfIntrState)
9018	{
9019	Assert(pfIntrState);
9020	Assert(!TRPMHasTrap(pVCpu));
9021
9022	/*
9023	* Compute/update guest-interruptibility state related FFs.
9024	* The FFs will be used below while evaluating events to be injected.
9025	*/
9026	*pfIntrState = hmR0VmxGetGuestIntrStateAndUpdateFFs(pVCpu);
9027
9028	/*
9029	* Evaluate if a new event needs to be injected.
9030	* An event that's already pending has already performed all necessary checks.
9031	*/
9032	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
9033	bool const fIsNestedGuest = pVmxTransient->fIsNestedGuest;
9034	if ( !pVCpu->hm.s.Event.fPending
9035	&& !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
9036	{
9037	/** @todo SMI. SMIs take priority over NMIs. */
9038
9039	/*
9040	* NMIs.
9041	* NMIs take priority over external interrupts.
9042	*/
9043	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
9044	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))
9045	{
9046	/*
9047	* For a guest, the FF always indicates the guest's ability to receive an NMI.
9048	*
9049	* For a nested-guest, the FF always indicates the outer guest's ability to
9050	* receive an NMI while the guest-interruptibility state bit depends on whether
9051	* the nested-hypervisor is using virtual-NMIs.
9052	*/
9053	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
9054	{
9055	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9056	if ( fIsNestedGuest
9057	&& CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_NMI_EXIT))
9058	return IEMExecVmxVmexitXcptNmi(pVCpu);
9059	#endif
9060	hmR0VmxSetPendingXcptNmi(pVCpu);
9061	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
9062	Log4Func(("NMI pending injection\n"));
9063
9064	/* We've injected the NMI, bail. */
9065	return VINF_SUCCESS;
9066	}
9067	else if (!fIsNestedGuest)
9068	hmR0VmxSetNmiWindowExitVmcs(pVmcsInfo);
9069	}
9070
9071	/*
9072	* External interrupts (PIC/APIC).
9073	* Once PDMGetInterrupt() returns a valid interrupt we -must- deliver it.
9074	* We cannot re-request the interrupt from the controller again.
9075	*/
9076	if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
9077	&& !pVCpu->hm.s.fSingleInstruction)
9078	{
9079	Assert(!DBGFIsStepping(pVCpu));
9080	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_RFLAGS);
9081	AssertRC(rc);
9082
9083	/*
9084	* We must not check EFLAGS directly when executing a nested-guest, use
9085	* CPUMIsGuestPhysIntrEnabled() instead as EFLAGS.IF does not control the blocking of
9086	* external interrupts when "External interrupt exiting" is set. This fixes a nasty
9087	* SMP hang while executing nested-guest VCPUs on spinlocks which aren't rescued by
9088	* other VM-exits (like a preemption timer), see @bugref{9562#c18}.
9089	*
9090	* See Intel spec. 25.4.1 "Event Blocking".
9091	*/
9092	if (CPUMIsGuestPhysIntrEnabled(pVCpu))
9093	{
9094	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9095	if ( fIsNestedGuest
9096	&& CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
9097	{
9098	VBOXSTRICTRC rcStrict = IEMExecVmxVmexitExtInt(pVCpu, 0 /* uVector /, true / fIntPending */);
9099	if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
9100	return rcStrict;
9101	}
9102	#endif
9103	uint8_t u8Interrupt;
9104	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
9105	if (RT_SUCCESS(rc))
9106	{
9107	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
9108	if ( fIsNestedGuest
9109	&& CPUMIsGuestVmxPinCtlsSet(pCtx, VMX_PIN_CTLS_EXT_INT_EXIT))
9110	{
9111	VBOXSTRICTRC rcStrict = IEMExecVmxVmexitExtInt(pVCpu, u8Interrupt, false /* fIntPending */);
9112	Assert(rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE);
9113	return rcStrict;
9114	}
9115	#endif
9116	hmR0VmxSetPendingExtInt(pVCpu, u8Interrupt);
9117	Log4Func(("External interrupt (%#x) pending injection\n", u8Interrupt));
9118	}
9119	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
9120	{
9121	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
9122
9123	if ( !fIsNestedGuest
9124	&& (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW))
9125	hmR0VmxApicSetTprThreshold(pVmcsInfo, u8Interrupt >> 4);
9126	/* else: for nested-guests, TPR threshold is picked up while merging VMCS controls. */
9127
9128	/*
9129	* If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
9130	* APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
9131	* need to re-set this force-flag here.
9132	*/
9133	}
9134	else
9135	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
9136
9137	/* We've injected the interrupt or taken necessary action, bail. */
9138	return VINF_SUCCESS;
9139	}
9140	if (!fIsNestedGuest)
9141	hmR0VmxSetIntWindowExitVmcs(pVmcsInfo);
9142	}
9143	}
9144	else if (!fIsNestedGuest)
9145	{
9146	/*
9147	* An event is being injected or we are in an interrupt shadow. Check if another event is
9148	* pending. If so, instruct VT-x to cause a VM-exit as soon as the guest is ready to accept
9149	* the pending event.
9150	*/
9151	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))
9152	hmR0VmxSetNmiWindowExitVmcs(pVmcsInfo);
9153	else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
9154	&& !pVCpu->hm.s.fSingleInstruction)
9155	hmR0VmxSetIntWindowExitVmcs(pVmcsInfo);
9156	}
9157	/* else: for nested-guests, NMI/interrupt-window exiting will be picked up when merging VMCS controls. */
9158
9159	return VINF_SUCCESS;
9160	}
9161
9162
9163	/**
9164	* Injects any pending events into the guest if the guest is in a state to
9165	* receive them.
9166	*
9167	* @returns Strict VBox status code (i.e. informational status codes too).
9168	* @param pVCpu The cross context virtual CPU structure.
9169	* @param pVmxTransient The VMX-transient structure.
9170	* @param fIntrState The VT-x guest-interruptibility state.
9171	* @param fStepping Whether we are single-stepping the guest using the
9172	* hypervisor debugger and should return
9173	* VINF_EM_DBG_STEPPED if the event was dispatched
9174	* directly.
9175	*/
9176	static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, uint32_t fIntrState, bool fStepping)
9177	{
9178	HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
9179	Assert(VMMRZCallRing3IsEnabled(pVCpu));
9180
9181	#ifdef VBOX_STRICT
9182	/*
9183	* Verify guest-interruptibility state.
9184	*
9185	* We put this in a scoped block so we do not accidentally use fBlockSti or fBlockMovSS,
9186	* since injecting an event may modify the interruptibility state and we must thus always
9187	* use fIntrState.
9188	*/
9189	{
9190	bool const fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
9191	bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
9192	Assert(!fBlockSti \|\| !(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_RFLAGS));
9193	Assert(!fBlockSti \|\| pVCpu->cpum.GstCtx.eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
9194	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
9195	Assert(!TRPMHasTrap(pVCpu));
9196	NOREF(fBlockMovSS); NOREF(fBlockSti);
9197	}
9198	#endif
9199
9200	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
9201	if (pVCpu->hm.s.Event.fPending)
9202	{
9203	/*
9204	* Do -not- clear any interrupt-window exiting control here. We might have an interrupt
9205	* pending even while injecting an event and in this case, we want a VM-exit as soon as
9206	* the guest is ready for the next interrupt, see @bugref{6208#c45}.
9207	*
9208	* See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
9209	*/
9210	uint32_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
9211	#ifdef VBOX_STRICT
9212	if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
9213	{
9214	Assert(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_IF);
9215	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI));
9216	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
9217	}
9218	else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
9219	{
9220	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI));
9221	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI));
9222	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
9223	}
9224	#endif
9225	Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#RX32\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
9226	uIntType));
9227
9228	/*
9229	* Inject the event and get any changes to the guest-interruptibility state.
9230	*
9231	* The guest-interruptibility state may need to be updated if we inject the event
9232	* into the guest IDT ourselves (for real-on-v86 guest injecting software interrupts).
9233	*/
9234	rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pVmxTransient, &pVCpu->hm.s.Event, fStepping, &fIntrState);
9235	AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
9236
9237	if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
9238	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
9239	else
9240	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
9241	}
9242
9243	/*
9244	* Deliver any pending debug exceptions if the guest is single-stepping using EFLAGS.TF and
9245	* is an interrupt shadow (block-by-STI or block-by-MOV SS).
9246	*/
9247	if ( (fIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI \| VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
9248	&& !pVmxTransient->fIsNestedGuest)
9249	{
9250	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RFLAGS);
9251
9252	if (!pVCpu->hm.s.fSingleInstruction)
9253	{
9254	/*
9255	* Set or clear the BS bit depending on whether the trap flag is active or not. We need
9256	* to do both since we clear the BS bit from the VMCS while exiting to ring-3.
9257	*/
9258	Assert(!DBGFIsStepping(pVCpu));
9259	uint8_t const fTrapFlag = !!(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_TF);
9260	int rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, fTrapFlag << VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT);
9261	AssertRC(rc);
9262	}
9263	else
9264	{
9265	/*
9266	* We must not deliver a debug exception when single-stepping over STI/Mov-SS in the
9267	* hypervisor debugger using EFLAGS.TF but rather clear interrupt inhibition. However,
9268	* we take care of this case in hmR0VmxExportSharedDebugState and also the case if
9269	* we use MTF, so just make sure it's called before executing guest-code.
9270	*/
9271	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
9272	}
9273	}
9274	/* else: for nested-guest currently handling while merging controls. */
9275
9276	/*
9277	* Finally, update the guest-interruptibility state.
9278	*
9279	* This is required for the real-on-v86 software interrupt injection, for
9280	* pending debug exceptions as well as updates to the guest state from ring-3 (IEM).
9281	*/
9282	int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
9283	AssertRC(rc);
9284
9285	/*
9286	* There's no need to clear the VM-entry interruption-information field here if we're not
9287	* injecting anything. VT-x clears the valid bit on every VM-exit.
9288	*
9289	* See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
9290	*/
9291
9292	Assert(rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_EM_RESET \|\| (rcStrict == VINF_EM_DBG_STEPPED && fStepping));
9293	return rcStrict;
9294	}
9295
9296
9297	/**
9298	* Enters the VT-x session.
9299	*
9300	* @returns VBox status code.
9301	* @param pVCpu The cross context virtual CPU structure.
9302	*/
9303	VMMR0DECL(int) VMXR0Enter(PVMCPUCC pVCpu)
9304	{
9305	AssertPtr(pVCpu);
9306	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported);
9307	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
9308
9309	LogFlowFunc(("pVCpu=%p\n", pVCpu));
9310	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
9311	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
9312
9313	#ifdef VBOX_STRICT
9314	/* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
9315	RTCCUINTREG uHostCr4 = ASMGetCR4();
9316	if (!(uHostCr4 & X86_CR4_VMXE))
9317	{
9318	LogRelFunc(("X86_CR4_VMXE bit in CR4 is not set!\n"));
9319	return VERR_VMX_X86_CR4_VMXE_CLEARED;
9320	}
9321	#endif
9322
9323	/*
9324	* Do the EMT scheduled L1D and MDS flush here if needed.
9325	*/
9326	if (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_L1D_SCHED)
9327	ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D);
9328	else if (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_MDS_SCHED)
9329	hmR0MdsClear();
9330
9331	/*
9332	* Load the appropriate VMCS as the current and active one.
9333	*/
9334	PVMXVMCSINFO pVmcsInfo;
9335	bool const fInNestedGuestMode = CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx);
9336	if (!fInNestedGuestMode)
9337	pVmcsInfo = &pVCpu->hmr0.s.vmx.VmcsInfo;
9338	else
9339	pVmcsInfo = &pVCpu->hmr0.s.vmx.VmcsInfoNstGst;
9340	int rc = hmR0VmxLoadVmcs(pVmcsInfo);
9341	if (RT_SUCCESS(rc))
9342	{
9343	pVCpu->hmr0.s.vmx.fSwitchedToNstGstVmcs = fInNestedGuestMode;
9344	pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3 = fInNestedGuestMode;
9345	pVCpu->hmr0.s.fLeaveDone = false;
9346	Log4Func(("Loaded Vmcs. HostCpuId=%u\n", RTMpCpuId()));
9347	}
9348	return rc;
9349	}
9350
9351
9352	/**
9353	* The thread-context callback.
9354	*
9355	* This is used together with RTThreadCtxHookCreate() on platforms which
9356	* supports it, and directly from VMMR0EmtPrepareForBlocking() and
9357	* VMMR0EmtResumeAfterBlocking() on platforms which don't.
9358	*
9359	* @param enmEvent The thread-context event.
9360	* @param pVCpu The cross context virtual CPU structure.
9361	* @param fGlobalInit Whether global VT-x/AMD-V init. was used.
9362	* @thread EMT(pVCpu)
9363	*/
9364	VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
9365	{
9366	AssertPtr(pVCpu);
9367	RT_NOREF1(fGlobalInit);
9368
9369	switch (enmEvent)
9370	{
9371	case RTTHREADCTXEVENT_OUT:
9372	{
9373	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
9374	VMCPU_ASSERT_EMT(pVCpu);
9375
9376	/* No longjmps (logger flushes, locks) in this fragile context. */
9377	VMMRZCallRing3Disable(pVCpu);
9378	Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
9379
9380	/* Restore host-state (FPU, debug etc.) */
9381	if (!pVCpu->hmr0.s.fLeaveDone)
9382	{
9383	/*
9384	* Do -not- import the guest-state here as we might already be in the middle of importing
9385	* it, esp. bad if we're holding the PGM lock, see comment in hmR0VmxImportGuestState().
9386	*/
9387	hmR0VmxLeave(pVCpu, false /* fImportState */);
9388	pVCpu->hmr0.s.fLeaveDone = true;
9389	}
9390
9391	/* Leave HM context, takes care of local init (term). */
9392	int rc = HMR0LeaveCpu(pVCpu);
9393	AssertRC(rc);
9394
9395	/* Restore longjmp state. */
9396	VMMRZCallRing3Enable(pVCpu);
9397	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
9398	break;
9399	}
9400
9401	case RTTHREADCTXEVENT_IN:
9402	{
9403	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
9404	VMCPU_ASSERT_EMT(pVCpu);
9405
9406	/* Do the EMT scheduled L1D and MDS flush here if needed. */
9407	if (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_L1D_SCHED)
9408	ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D);
9409	else if (pVCpu->hmr0.s.fWorldSwitcher & HM_WSF_MDS_SCHED)
9410	hmR0MdsClear();
9411
9412	/* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
9413	VMMRZCallRing3Disable(pVCpu);
9414	Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
9415
9416	/* Initialize the bare minimum state required for HM. This takes care of
9417	initializing VT-x if necessary (onlined CPUs, local init etc.) */
9418	int rc = hmR0EnterCpu(pVCpu);
9419	AssertRC(rc);
9420	Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
9421	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
9422
9423	/* Load the active VMCS as the current one. */
9424	PVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
9425	rc = hmR0VmxLoadVmcs(pVmcsInfo);
9426	AssertRC(rc);
9427	Log4Func(("Resumed: Loaded Vmcs. HostCpuId=%u\n", RTMpCpuId()));
9428	pVCpu->hmr0.s.fLeaveDone = false;
9429
9430	/* Restore longjmp state. */
9431	VMMRZCallRing3Enable(pVCpu);
9432	break;
9433	}
9434
9435	default:
9436	break;
9437	}
9438	}
9439
9440
9441	/**
9442	* Exports the host state into the VMCS host-state area.
9443	* Sets up the VM-exit MSR-load area.
9444	*
9445	* The CPU state will be loaded from these fields on every successful VM-exit.
9446	*
9447	* @returns VBox status code.
9448	* @param pVCpu The cross context virtual CPU structure.
9449	*
9450	* @remarks No-long-jump zone!!!
9451	*/
9452	static int hmR0VmxExportHostState(PVMCPUCC pVCpu)
9453	{
9454	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
9455
9456	int rc = VINF_SUCCESS;
9457	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
9458	{
9459	uint64_t uHostCr4 = hmR0VmxExportHostControlRegs();
9460
9461	rc = hmR0VmxExportHostSegmentRegs(pVCpu, uHostCr4);
9462	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
9463
9464	hmR0VmxExportHostMsrs(pVCpu);
9465
9466	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT;
9467	}
9468	return rc;
9469	}
9470
9471
9472	/**
9473	* Saves the host state in the VMCS host-state.
9474	*
9475	* @returns VBox status code.
9476	* @param pVCpu The cross context virtual CPU structure.
9477	*
9478	* @remarks No-long-jump zone!!!
9479	*/
9480	VMMR0DECL(int) VMXR0ExportHostState(PVMCPUCC pVCpu)
9481	{
9482	AssertPtr(pVCpu);
9483	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
9484
9485	/*
9486	* Export the host state here while entering HM context.
9487	* When thread-context hooks are used, we might get preempted and have to re-save the host
9488	* state but most of the time we won't be, so do it here before we disable interrupts.
9489	*/
9490	return hmR0VmxExportHostState(pVCpu);
9491	}
9492
9493
9494	/**
9495	* Exports the guest state into the VMCS guest-state area.
9496	*
9497	* The will typically be done before VM-entry when the guest-CPU state and the
9498	* VMCS state may potentially be out of sync.
9499	*
9500	* Sets up the VM-entry MSR-load and VM-exit MSR-store areas. Sets up the
9501	* VM-entry controls.
9502	* Sets up the appropriate VMX non-root function to execute guest code based on
9503	* the guest CPU mode.
9504	*
9505	* @returns VBox strict status code.
9506	* @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
9507	* without unrestricted guest execution and the VMMDev is not presently
9508	* mapped (e.g. EFI32).
9509	*
9510	* @param pVCpu The cross context virtual CPU structure.
9511	* @param pVmxTransient The VMX-transient structure.
9512	*
9513	* @remarks No-long-jump zone!!!
9514	*/
9515	static VBOXSTRICTRC hmR0VmxExportGuestState(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
9516	{
9517	AssertPtr(pVCpu);
9518	HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
9519	LogFlowFunc(("pVCpu=%p\n", pVCpu));
9520
9521	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
9522
9523	/*
9524	* Determine real-on-v86 mode.
9525	* Used when the guest is in real-mode and unrestricted guest execution is not used.
9526	*/
9527	PVMXVMCSINFOSHARED pVmcsInfoShared = pVmxTransient->pVmcsInfo->pShared;
9528	if ( pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fUnrestrictedGuest
9529	\|\| !CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx))
9530	pVmcsInfoShared->RealMode.fRealOnV86Active = false;
9531	else
9532	{
9533	Assert(!pVmxTransient->fIsNestedGuest);
9534	pVmcsInfoShared->RealMode.fRealOnV86Active = true;
9535	}
9536
9537	/*
9538	* Any ordering dependency among the sub-functions below must be explicitly stated using comments.
9539	* Ideally, assert that the cross-dependent bits are up-to-date at the point of using it.
9540	*/
9541	int rc = hmR0VmxExportGuestEntryExitCtls(pVCpu, pVmxTransient);
9542	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
9543
9544	rc = hmR0VmxExportGuestCR0(pVCpu, pVmxTransient);
9545	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
9546
9547	VBOXSTRICTRC rcStrict = hmR0VmxExportGuestCR3AndCR4(pVCpu, pVmxTransient);
9548	if (rcStrict == VINF_SUCCESS)
9549	{ /* likely */ }
9550	else
9551	{
9552	Assert(rcStrict == VINF_EM_RESCHEDULE_REM \|\| RT_FAILURE_NP(rcStrict));
9553	return rcStrict;
9554	}
9555
9556	rc = hmR0VmxExportGuestSegRegsXdtr(pVCpu, pVmxTransient);
9557	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
9558
9559	rc = hmR0VmxExportGuestMsrs(pVCpu, pVmxTransient);
9560	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
9561
9562	hmR0VmxExportGuestApicTpr(pVCpu, pVmxTransient);
9563	hmR0VmxExportGuestXcptIntercepts(pVCpu, pVmxTransient);
9564	hmR0VmxExportGuestRip(pVCpu);
9565	hmR0VmxExportGuestRsp(pVCpu);
9566	hmR0VmxExportGuestRflags(pVCpu, pVmxTransient);
9567
9568	rc = hmR0VmxExportGuestHwvirtState(pVCpu, pVmxTransient);
9569	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
9570
9571	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
9572	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( (HM_CHANGED_GUEST_GPRS_MASK & ~HM_CHANGED_GUEST_RSP)
9573	\| HM_CHANGED_GUEST_CR2
9574	\| (HM_CHANGED_GUEST_DR_MASK & ~HM_CHANGED_GUEST_DR7)
9575	\| HM_CHANGED_GUEST_X87
9576	\| HM_CHANGED_GUEST_SSE_AVX
9577	\| HM_CHANGED_GUEST_OTHER_XSAVE
9578	\| HM_CHANGED_GUEST_XCRx
9579	\| HM_CHANGED_GUEST_KERNEL_GS_BASE /* Part of lazy or auto load-store MSRs. */
9580	\| HM_CHANGED_GUEST_SYSCALL_MSRS /* Part of lazy or auto load-store MSRs. */
9581	\| HM_CHANGED_GUEST_TSC_AUX
9582	\| HM_CHANGED_GUEST_OTHER_MSRS
9583	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_VMX_MASK)));
9584
9585	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
9586	return rc;
9587	}
9588
9589
9590	/**
9591	* Exports the state shared between the host and guest into the VMCS.
9592	*
9593	* @param pVCpu The cross context virtual CPU structure.
9594	* @param pVmxTransient The VMX-transient structure.
9595	*
9596	* @remarks No-long-jump zone!!!
9597	*/
9598	static void hmR0VmxExportSharedState(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
9599	{
9600	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
9601	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
9602
9603	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
9604	{
9605	int rc = hmR0VmxExportSharedDebugState(pVCpu, pVmxTransient);
9606	AssertRC(rc);
9607	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
9608
9609	/* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
9610	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_RFLAGS)
9611	hmR0VmxExportGuestRflags(pVCpu, pVmxTransient);
9612	}
9613
9614	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_GUEST_LAZY_MSRS)
9615	{
9616	hmR0VmxLazyLoadGuestMsrs(pVCpu);
9617	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_VMX_GUEST_LAZY_MSRS;
9618	}
9619
9620	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE),
9621	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
9622	}
9623
9624
9625	/**
9626	* Worker for loading the guest-state bits in the inner VT-x execution loop.
9627	*
9628	* @returns Strict VBox status code (i.e. informational status codes too).
9629	* @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
9630	* without unrestricted guest execution and the VMMDev is not presently
9631	* mapped (e.g. EFI32).
9632	*
9633	* @param pVCpu The cross context virtual CPU structure.
9634	* @param pVmxTransient The VMX-transient structure.
9635	*
9636	* @remarks No-long-jump zone!!!
9637	*/
9638	static VBOXSTRICTRC hmR0VmxExportGuestStateOptimal(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
9639	{
9640	HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
9641	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
9642	Assert(VMMR0IsLogFlushDisabled(pVCpu));
9643
9644	#ifdef HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
9645	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
9646	#endif
9647
9648	/*
9649	* For many VM-exits only RIP/RSP/RFLAGS (and HWVIRT state when executing a nested-guest)
9650	* changes. First try to export only these without going through all other changed-flag checks.
9651	*/
9652	VBOXSTRICTRC rcStrict;
9653	uint64_t const fCtxMask = HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
9654	uint64_t const fMinimalMask = HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RSP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_HWVIRT;
9655	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
9656
9657	/* If only RIP/RSP/RFLAGS/HWVIRT changed, export only those (quicker, happens more often).*/
9658	if ( (fCtxChanged & fMinimalMask)
9659	&& !(fCtxChanged & (fCtxMask & ~fMinimalMask)))
9660	{
9661	hmR0VmxExportGuestRip(pVCpu);
9662	hmR0VmxExportGuestRsp(pVCpu);
9663	hmR0VmxExportGuestRflags(pVCpu, pVmxTransient);
9664	rcStrict = hmR0VmxExportGuestHwvirtState(pVCpu, pVmxTransient);
9665	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportMinimal);
9666	}
9667	/* If anything else also changed, go through the full export routine and export as required. */
9668	else if (fCtxChanged & fCtxMask)
9669	{
9670	rcStrict = hmR0VmxExportGuestState(pVCpu, pVmxTransient);
9671	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
9672	{ /* likely */}
9673	else
9674	{
9675	AssertMsg(rcStrict == VINF_EM_RESCHEDULE_REM, ("Failed to export guest state! rc=%Rrc\n",
9676	VBOXSTRICTRC_VAL(rcStrict)));
9677	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
9678	return rcStrict;
9679	}
9680	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
9681	}
9682	/* Nothing changed, nothing to load here. */
9683	else
9684	rcStrict = VINF_SUCCESS;
9685
9686	#ifdef VBOX_STRICT
9687	/* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
9688	uint64_t const fCtxChangedCur = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
9689	AssertMsg(!(fCtxChangedCur & fCtxMask), ("fCtxChangedCur=%#RX64\n", fCtxChangedCur));
9690	#endif
9691	return rcStrict;
9692	}
9693
9694
9695	/**
9696	* Tries to determine what part of the guest-state VT-x has deemed as invalid
9697	* and update error record fields accordingly.
9698	*
9699	* @returns VMX_IGS_* error codes.
9700	* @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
9701	* wrong with the guest state.
9702	*
9703	* @param pVCpu The cross context virtual CPU structure.
9704	* @param pVmcsInfo The VMCS info. object.
9705	*
9706	* @remarks This function assumes our cache of the VMCS controls
9707	* are valid, i.e. hmR0VmxCheckCachedVmcsCtls() succeeded.
9708	*/
9709	static uint32_t hmR0VmxCheckGuestState(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo)
9710	{
9711	#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
9712	#define HMVMX_CHECK_BREAK(expr, err) do { \
9713	if (!(expr)) { uError = (err); break; } \
9714	} while (0)
9715
9716	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
9717	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
9718	uint32_t uError = VMX_IGS_ERROR;
9719	uint32_t u32IntrState = 0;
9720	bool const fUnrestrictedGuest = pVM->hmr0.s.vmx.fUnrestrictedGuest;
9721	do
9722	{
9723	int rc;
9724
9725	/*
9726	* Guest-interruptibility state.
9727	*
9728	* Read this first so that any check that fails prior to those that actually
9729	* require the guest-interruptibility state would still reflect the correct
9730	* VMCS value and avoids causing further confusion.
9731	*/
9732	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32IntrState);
9733	AssertRC(rc);
9734
9735	uint32_t u32Val;
9736	uint64_t u64Val;
9737
9738	/*
9739	* CR0.
9740	*/
9741	/** @todo Why do we need to OR and AND the fixed-0 and fixed-1 bits below? */
9742	uint64_t fSetCr0 = (g_HmMsrs.u.vmx.u64Cr0Fixed0 & g_HmMsrs.u.vmx.u64Cr0Fixed1);
9743	uint64_t const fZapCr0 = (g_HmMsrs.u.vmx.u64Cr0Fixed0 \| g_HmMsrs.u.vmx.u64Cr0Fixed1);
9744	/* Exceptions for unrestricted guest execution for CR0 fixed bits (PE, PG).
9745	See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
9746	if (fUnrestrictedGuest)
9747	fSetCr0 &= ~(uint64_t)(X86_CR0_PE \| X86_CR0_PG);
9748
9749	uint64_t u64GuestCr0;
9750	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_CR0, &u64GuestCr0);
9751	AssertRC(rc);
9752	HMVMX_CHECK_BREAK((u64GuestCr0 & fSetCr0) == fSetCr0, VMX_IGS_CR0_FIXED1);
9753	HMVMX_CHECK_BREAK(!(u64GuestCr0 & ~fZapCr0), VMX_IGS_CR0_FIXED0);
9754	if ( !fUnrestrictedGuest
9755	&& (u64GuestCr0 & X86_CR0_PG)
9756	&& !(u64GuestCr0 & X86_CR0_PE))
9757	HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
9758
9759	/*
9760	* CR4.
9761	*/
9762	/** @todo Why do we need to OR and AND the fixed-0 and fixed-1 bits below? */
9763	uint64_t const fSetCr4 = (g_HmMsrs.u.vmx.u64Cr4Fixed0 & g_HmMsrs.u.vmx.u64Cr4Fixed1);
9764	uint64_t const fZapCr4 = (g_HmMsrs.u.vmx.u64Cr4Fixed0 \| g_HmMsrs.u.vmx.u64Cr4Fixed1);
9765
9766	uint64_t u64GuestCr4;
9767	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_CR4, &u64GuestCr4);
9768	AssertRC(rc);
9769	HMVMX_CHECK_BREAK((u64GuestCr4 & fSetCr4) == fSetCr4, VMX_IGS_CR4_FIXED1);
9770	HMVMX_CHECK_BREAK(!(u64GuestCr4 & ~fZapCr4), VMX_IGS_CR4_FIXED0);
9771
9772	/*
9773	* IA32_DEBUGCTL MSR.
9774	*/
9775	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
9776	AssertRC(rc);
9777	if ( (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
9778	&& (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
9779	{
9780	HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
9781	}
9782	uint64_t u64DebugCtlMsr = u64Val;
9783
9784	#ifdef VBOX_STRICT
9785	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
9786	AssertRC(rc);
9787	Assert(u32Val == pVmcsInfo->u32EntryCtls);
9788	#endif
9789	bool const fLongModeGuest = RT_BOOL(pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
9790
9791	/*
9792	* RIP and RFLAGS.
9793	*/
9794	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_RIP, &u64Val);
9795	AssertRC(rc);
9796	/* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
9797	if ( !fLongModeGuest
9798	\|\| !pCtx->cs.Attr.n.u1Long)
9799	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
9800	/** @todo If the processor supports N < 64 linear-address bits, bits 63:N
9801	* must be identical if the "IA-32e mode guest" VM-entry
9802	* control is 1 and CS.L is 1. No check applies if the
9803	* CPU supports 64 linear-address bits. */
9804
9805	/* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
9806	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_RFLAGS, &u64Val);
9807	AssertRC(rc);
9808	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
9809	VMX_IGS_RFLAGS_RESERVED);
9810	HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
9811	uint32_t const u32Eflags = u64Val;
9812
9813	if ( fLongModeGuest
9814	\|\| ( fUnrestrictedGuest
9815	&& !(u64GuestCr0 & X86_CR0_PE)))
9816	{
9817	HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
9818	}
9819
9820	uint32_t u32EntryInfo;
9821	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
9822	AssertRC(rc);
9823	if (VMX_ENTRY_INT_INFO_IS_EXT_INT(u32EntryInfo))
9824	HMVMX_CHECK_BREAK(u32Eflags & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
9825
9826	/*
9827	* 64-bit checks.
9828	*/
9829	if (fLongModeGuest)
9830	{
9831	HMVMX_CHECK_BREAK(u64GuestCr0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE);
9832	HMVMX_CHECK_BREAK(u64GuestCr4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
9833	}
9834
9835	if ( !fLongModeGuest
9836	&& (u64GuestCr4 & X86_CR4_PCIDE))
9837	HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
9838
9839	/** @todo CR3 field must be such that bits 63:52 and bits in the range
9840	* 51:32 beyond the processor's physical-address width are 0. */
9841
9842	if ( (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
9843	&& (pCtx->dr[7] & X86_DR7_MBZ_MASK))
9844	HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
9845
9846	rc = VMXReadVmcsNw(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
9847	AssertRC(rc);
9848	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
9849
9850	rc = VMXReadVmcsNw(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
9851	AssertRC(rc);
9852	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
9853
9854	/*
9855	* PERF_GLOBAL MSR.
9856	*/
9857	if (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR)
9858	{
9859	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
9860	AssertRC(rc);
9861	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
9862	VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
9863	}
9864
9865	/*
9866	* PAT MSR.
9867	*/
9868	if (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
9869	{
9870	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
9871	AssertRC(rc);
9872	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
9873	for (unsigned i = 0; i < 8; i++)
9874	{
9875	uint8_t u8Val = (u64Val & 0xff);
9876	if ( u8Val != 0 /* UC */
9877	&& u8Val != 1 /* WC */
9878	&& u8Val != 4 /* WT */
9879	&& u8Val != 5 /* WP */
9880	&& u8Val != 6 /* WB */
9881	&& u8Val != 7 /* UC- */)
9882	HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
9883	u64Val >>= 8;
9884	}
9885	}
9886
9887	/*
9888	* EFER MSR.
9889	*/
9890	if (pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
9891	{
9892	Assert(g_fHmVmxSupportsVmcsEfer);
9893	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
9894	AssertRC(rc);
9895	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
9896	VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
9897	HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL( pVmcsInfo->u32EntryCtls
9898	& VMX_ENTRY_CTLS_IA32E_MODE_GUEST),
9899	VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
9900	/** @todo r=ramshankar: Unrestricted check here is probably wrong, see
9901	* iemVmxVmentryCheckGuestState(). */
9902	HMVMX_CHECK_BREAK( fUnrestrictedGuest
9903	\|\| !(u64GuestCr0 & X86_CR0_PG)
9904	\|\| RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(u64Val & MSR_K6_EFER_LME),
9905	VMX_IGS_EFER_LMA_LME_MISMATCH);
9906	}
9907
9908	/*
9909	* Segment registers.
9910	*/
9911	HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
9912	\|\| !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
9913	if (!(u32Eflags & X86_EFL_VM))
9914	{
9915	/* CS */
9916	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
9917	HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
9918	HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
9919	HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
9920	\|\| !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
9921	HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
9922	\|\| (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
9923	/* CS cannot be loaded with NULL in protected mode. */
9924	HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
9925	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
9926	if (pCtx->cs.Attr.n.u4Type == 9 \|\| pCtx->cs.Attr.n.u4Type == 11)
9927	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
9928	else if (pCtx->cs.Attr.n.u4Type == 13 \|\| pCtx->cs.Attr.n.u4Type == 15)
9929	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
9930	else if (fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
9931	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
9932	else
9933	HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
9934
9935	/* SS */
9936	HMVMX_CHECK_BREAK( fUnrestrictedGuest
9937	\|\| (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
9938	HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
9939	if ( !(pCtx->cr0 & X86_CR0_PE)
9940	\|\| pCtx->cs.Attr.n.u4Type == 3)
9941	HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
9942
9943	if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
9944	{
9945	HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 \|\| pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
9946	HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
9947	HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
9948	HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
9949	HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
9950	\|\| !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
9951	HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
9952	\|\| (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
9953	}
9954
9955	/* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSReg(). */
9956	if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
9957	{
9958	HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
9959	HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
9960	HMVMX_CHECK_BREAK( fUnrestrictedGuest
9961	\|\| pCtx->ds.Attr.n.u4Type > 11
9962	\|\| pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
9963	HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
9964	HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
9965	HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
9966	\|\| !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
9967	HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
9968	\|\| (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
9969	HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
9970	\|\| (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
9971	}
9972	if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
9973	{
9974	HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
9975	HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
9976	HMVMX_CHECK_BREAK( fUnrestrictedGuest
9977	\|\| pCtx->es.Attr.n.u4Type > 11
9978	\|\| pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
9979	HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
9980	HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
9981	HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
9982	\|\| !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
9983	HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
9984	\|\| (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
9985	HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
9986	\|\| (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
9987	}
9988	if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
9989	{
9990	HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
9991	HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
9992	HMVMX_CHECK_BREAK( fUnrestrictedGuest
9993	\|\| pCtx->fs.Attr.n.u4Type > 11
9994	\|\| pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
9995	HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
9996	HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
9997	HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
9998	\|\| !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
9999	HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
10000	\|\| (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10001	HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10002	\|\| (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
10003	}
10004	if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
10005	{
10006	HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
10007	HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
10008	HMVMX_CHECK_BREAK( fUnrestrictedGuest
10009	\|\| pCtx->gs.Attr.n.u4Type > 11
10010	\|\| pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
10011	HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
10012	HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
10013	HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
10014	\|\| !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10015	HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
10016	\|\| (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10017	HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10018	\|\| (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
10019	}
10020	/* 64-bit capable CPUs. */
10021	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10022	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10023	HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10024	\|\| X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10025	HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10026	HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) \|\| !RT_HI_U32(pCtx->ss.u64Base),
10027	VMX_IGS_LONGMODE_SS_BASE_INVALID);
10028	HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) \|\| !RT_HI_U32(pCtx->ds.u64Base),
10029	VMX_IGS_LONGMODE_DS_BASE_INVALID);
10030	HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) \|\| !RT_HI_U32(pCtx->es.u64Base),
10031	VMX_IGS_LONGMODE_ES_BASE_INVALID);
10032	}
10033	else
10034	{
10035	/* V86 mode checks. */
10036	uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
10037	if (pVmcsInfo->pShared->RealMode.fRealOnV86Active)
10038	{
10039	u32CSAttr = 0xf3; u32SSAttr = 0xf3;
10040	u32DSAttr = 0xf3; u32ESAttr = 0xf3;
10041	u32FSAttr = 0xf3; u32GSAttr = 0xf3;
10042	}
10043	else
10044	{
10045	u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
10046	u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
10047	u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
10048	}
10049
10050	/* CS */
10051	HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
10052	HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
10053	HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
10054	/* SS */
10055	HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
10056	HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
10057	HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
10058	/* DS */
10059	HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
10060	HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
10061	HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
10062	/* ES */
10063	HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
10064	HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
10065	HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
10066	/* FS */
10067	HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
10068	HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
10069	HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
10070	/* GS */
10071	HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
10072	HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
10073	HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
10074	/* 64-bit capable CPUs. */
10075	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10076	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10077	HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10078	\|\| X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10079	HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10080	HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) \|\| !RT_HI_U32(pCtx->ss.u64Base),
10081	VMX_IGS_LONGMODE_SS_BASE_INVALID);
10082	HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) \|\| !RT_HI_U32(pCtx->ds.u64Base),
10083	VMX_IGS_LONGMODE_DS_BASE_INVALID);
10084	HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) \|\| !RT_HI_U32(pCtx->es.u64Base),
10085	VMX_IGS_LONGMODE_ES_BASE_INVALID);
10086	}
10087
10088	/*
10089	* TR.
10090	*/
10091	HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
10092	/* 64-bit capable CPUs. */
10093	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
10094	if (fLongModeGuest)
10095	HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
10096	VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
10097	else
10098	HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
10099	\|\| pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
10100	VMX_IGS_TR_ATTR_TYPE_INVALID);
10101	HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
10102	HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
10103	HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
10104	HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
10105	\|\| !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10106	HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
10107	\|\| (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10108	HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
10109
10110	/*
10111	* GDTR and IDTR (64-bit capable checks).
10112	*/
10113	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
10114	AssertRC(rc);
10115	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
10116
10117	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
10118	AssertRC(rc);
10119	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
10120
10121	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
10122	AssertRC(rc);
10123	HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10124
10125	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
10126	AssertRC(rc);
10127	HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10128
10129	/*
10130	* Guest Non-Register State.
10131	*/
10132	/* Activity State. */
10133	uint32_t u32ActivityState;
10134	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
10135	AssertRC(rc);
10136	HMVMX_CHECK_BREAK( !u32ActivityState
10137	\|\| (u32ActivityState & RT_BF_GET(g_HmMsrs.u.vmx.u64Misc, VMX_BF_MISC_ACTIVITY_STATES)),
10138	VMX_IGS_ACTIVITY_STATE_INVALID);
10139	HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
10140	\|\| u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
10141
10142	if ( u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
10143	\|\| u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
10144	HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
10145
10146	/** @todo Activity state and injecting interrupts. Left as a todo since we
10147	* currently don't use activity states but ACTIVE. */
10148
10149	HMVMX_CHECK_BREAK( !(pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
10150	\|\| u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
10151
10152	/* Guest interruptibility-state. */
10153	HMVMX_CHECK_BREAK(!(u32IntrState & 0xffffffe0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
10154	HMVMX_CHECK_BREAK((u32IntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI \| VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
10155	!= (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI \| VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
10156	VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
10157	HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
10158	\|\| !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
10159	VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
10160	if (VMX_ENTRY_INT_INFO_IS_EXT_INT(u32EntryInfo))
10161	{
10162	HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
10163	&& !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
10164	VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
10165	}
10166	else if (VMX_ENTRY_INT_INFO_IS_XCPT_NMI(u32EntryInfo))
10167	{
10168	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
10169	VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
10170	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
10171	VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
10172	}
10173	/** @todo Assumes the processor is not in SMM. */
10174	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
10175	VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
10176	HMVMX_CHECK_BREAK( !(pVmcsInfo->u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
10177	\|\| (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
10178	VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
10179	if ( (pVmcsInfo->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
10180	&& VMX_ENTRY_INT_INFO_IS_XCPT_NMI(u32EntryInfo))
10181	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI), VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
10182
10183	/* Pending debug exceptions. */
10184	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u64Val);
10185	AssertRC(rc);
10186	/* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
10187	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
10188	u32Val = u64Val; /* For pending debug exceptions checks below. */
10189
10190	if ( (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
10191	\|\| (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
10192	\|\| u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
10193	{
10194	if ( (u32Eflags & X86_EFL_TF)
10195	&& !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
10196	{
10197	/* Bit 14 is PendingDebug.BS. */
10198	HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
10199	}
10200	if ( !(u32Eflags & X86_EFL_TF)
10201	\|\| (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
10202	{
10203	/* Bit 14 is PendingDebug.BS. */
10204	HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
10205	}
10206	}
10207
10208	/* VMCS link pointer. */
10209	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
10210	AssertRC(rc);
10211	if (u64Val != UINT64_C(0xffffffffffffffff))
10212	{
10213	HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
10214	/** @todo Bits beyond the processor's physical-address width MBZ. */
10215	/** @todo SMM checks. */
10216	Assert(pVmcsInfo->HCPhysShadowVmcs == u64Val);
10217	Assert(pVmcsInfo->pvShadowVmcs);
10218	VMXVMCSREVID VmcsRevId;
10219	VmcsRevId.u = (uint32_t )pVmcsInfo->pvShadowVmcs;
10220	HMVMX_CHECK_BREAK(VmcsRevId.n.u31RevisionId == RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_ID),
10221	VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID);
10222	HMVMX_CHECK_BREAK(VmcsRevId.n.fIsShadowVmcs == (uint32_t)!!(pVmcsInfo->u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING),
10223	VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW);
10224	}
10225
10226	/** @todo Checks on Guest Page-Directory-Pointer-Table Entries when guest is
10227	* not using nested paging? */
10228	if ( pVM->hmr0.s.fNestedPaging
10229	&& !fLongModeGuest
10230	&& CPUMIsGuestInPAEModeEx(pCtx))
10231	{
10232	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);
10233	AssertRC(rc);
10234	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
10235
10236	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);
10237	AssertRC(rc);
10238	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
10239
10240	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);
10241	AssertRC(rc);
10242	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
10243
10244	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);
10245	AssertRC(rc);
10246	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
10247	}
10248
10249	/* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
10250	if (uError == VMX_IGS_ERROR)
10251	uError = VMX_IGS_REASON_NOT_FOUND;
10252	} while (0);
10253
10254	pVCpu->hm.s.u32HMError = uError;
10255	pVCpu->hm.s.vmx.LastError.u32GuestIntrState = u32IntrState;
10256	return uError;
10257
10258	#undef HMVMX_ERROR_BREAK
10259	#undef HMVMX_CHECK_BREAK
10260	}
10261
10262
10263	/**
10264	* Map the APIC-access page for virtualizing APIC accesses.
10265	*
10266	* This can cause a longjumps to R3 due to the acquisition of the PGM lock. Hence,
10267	* this not done as part of exporting guest state, see @bugref{8721}.
10268	*
10269	* @returns VBox status code.
10270	* @param pVCpu The cross context virtual CPU structure.
10271	*/
10272	static int hmR0VmxMapHCApicAccessPage(PVMCPUCC pVCpu)
10273	{
10274	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
10275	uint64_t const u64MsrApicBase = APICGetBaseMsrNoCheck(pVCpu);
10276
10277	Assert(PDMHasApic(pVM));
10278	Assert(u64MsrApicBase);
10279
10280	RTGCPHYS const GCPhysApicBase = u64MsrApicBase & PAGE_BASE_GC_MASK;
10281	Log4Func(("Mappping HC APIC-access page at %#RGp\n", GCPhysApicBase));
10282
10283	/* Unalias the existing mapping. */
10284	int rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
10285	AssertRCReturn(rc, rc);
10286
10287	/* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */
10288	Assert(pVM->hmr0.s.vmx.HCPhysApicAccess != NIL_RTHCPHYS);
10289	rc = IOMR0MmioMapMmioHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hmr0.s.vmx.HCPhysApicAccess, X86_PTE_RW \| X86_PTE_P);
10290	AssertRCReturn(rc, rc);
10291
10292	/* Update the per-VCPU cache of the APIC base MSR. */
10293	pVCpu->hm.s.vmx.u64GstMsrApicBase = u64MsrApicBase;
10294	return VINF_SUCCESS;
10295	}
10296
10297
10298	/**
10299	* Worker function passed to RTMpOnSpecific() that is to be called on the target
10300	* CPU.
10301	*
10302	* @param idCpu The ID for the CPU the function is called on.
10303	* @param pvUser1 Null, not used.
10304	* @param pvUser2 Null, not used.
10305	*/
10306	static DECLCALLBACK(void) hmR0DispatchHostNmi(RTCPUID idCpu, void pvUser1, void pvUser2)
10307	{
10308	RT_NOREF3(idCpu, pvUser1, pvUser2);
10309	VMXDispatchHostNmi();
10310	}
10311
10312
10313	/**
10314	* Dispatching an NMI on the host CPU that received it.
10315	*
10316	* @returns VBox status code.
10317	* @param pVCpu The cross context virtual CPU structure.
10318	* @param pVmcsInfo The VMCS info. object corresponding to the VMCS that was
10319	* executing when receiving the host NMI in VMX non-root
10320	* operation.
10321	*/
10322	static int hmR0VmxExitHostNmi(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo)
10323	{
10324	RTCPUID const idCpu = pVmcsInfo->idHostCpuExec;
10325	Assert(idCpu != NIL_RTCPUID);
10326
10327	/*
10328	* We don't want to delay dispatching the NMI any more than we have to. However,
10329	* we have already chosen -not- to dispatch NMIs when interrupts were still disabled
10330	* after executing guest or nested-guest code for the following reasons:
10331	*
10332	* - We would need to perform VMREADs with interrupts disabled and is orders of
10333	* magnitude worse when we run as a nested hypervisor without VMCS shadowing
10334	* supported by the host hypervisor.
10335	*
10336	* - It affects the common VM-exit scenario and keeps interrupts disabled for a
10337	* longer period of time just for handling an edge case like host NMIs which do
10338	* not occur nearly as frequently as other VM-exits.
10339	*
10340	* Let's cover the most likely scenario first. Check if we are on the target CPU
10341	* and dispatch the NMI right away. This should be much faster than calling into
10342	* RTMpOnSpecific() machinery.
10343	*/
10344	bool fDispatched = false;
10345	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
10346	if (idCpu == RTMpCpuId())
10347	{
10348	VMXDispatchHostNmi();
10349	fDispatched = true;
10350	}
10351	ASMSetFlags(fEFlags);
10352	if (fDispatched)
10353	{
10354	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
10355	return VINF_SUCCESS;
10356	}
10357
10358	/*
10359	* RTMpOnSpecific() waits until the worker function has run on the target CPU. So
10360	* there should be no race or recursion even if we are unlucky enough to be preempted
10361	* (to the target CPU) without dispatching the host NMI above.
10362	*/
10363	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGCIpi);
10364	return RTMpOnSpecific(idCpu, &hmR0DispatchHostNmi, NULL /* pvUser1 /, NULL / pvUser2 */);
10365	}
10366
10367
10368	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
10369	/**
10370	* Merges the guest with the nested-guest MSR bitmap in preparation of executing the
10371	* nested-guest using hardware-assisted VMX.
10372	*
10373	* @param pVCpu The cross context virtual CPU structure.
10374	* @param pVmcsInfoNstGst The nested-guest VMCS info. object.
10375	* @param pVmcsInfoGst The guest VMCS info. object.
10376	*/
10377	static void hmR0VmxMergeMsrBitmapNested(PCVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfoNstGst, PCVMXVMCSINFO pVmcsInfoGst)
10378	{
10379	uint32_t const cbMsrBitmap = X86_PAGE_4K_SIZE;
10380	uint64_t pu64MsrBitmap = (uint64_t )pVmcsInfoNstGst->pvMsrBitmap;
10381	Assert(pu64MsrBitmap);
10382
10383	/*
10384	* We merge the guest MSR bitmap with the nested-guest MSR bitmap such that any
10385	* MSR that is intercepted by the guest is also intercepted while executing the
10386	* nested-guest using hardware-assisted VMX.
10387	*
10388	* Note! If the nested-guest is not using an MSR bitmap, every MSR must cause a
10389	* nested-guest VM-exit even if the outer guest is not intercepting some
10390	* MSRs. We cannot assume the caller has initialized the nested-guest
10391	* MSR bitmap in this case.
10392	*
10393	* The nested hypervisor may also switch whether it uses MSR bitmaps for
10394	* each of its VM-entry, hence initializing it once per-VM while setting
10395	* up the nested-guest VMCS is not sufficient.
10396	*/
10397	PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
10398	if (pVmcsNstGst->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
10399	{
10400	uint64_t const pu64MsrBitmapNstGst = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap);
10401	uint64_t const pu64MsrBitmapGst = (uint64_t const )pVmcsInfoGst->pvMsrBitmap;
10402	Assert(pu64MsrBitmapNstGst);
10403	Assert(pu64MsrBitmapGst);
10404
10405	/** @todo Detect and use EVEX.POR? */
10406	uint32_t const cFrags = cbMsrBitmap / sizeof(uint64_t);
10407	for (uint32_t i = 0; i < cFrags; i++)
10408	pu64MsrBitmap[i] = pu64MsrBitmapNstGst[i] \| pu64MsrBitmapGst[i];
10409	}
10410	else
10411	ASMMemFill32(pu64MsrBitmap, cbMsrBitmap, UINT32_C(0xffffffff));
10412	}
10413
10414
10415	/**
10416	* Merges the guest VMCS in to the nested-guest VMCS controls in preparation of
10417	* hardware-assisted VMX execution of the nested-guest.
10418	*
10419	* For a guest, we don't modify these controls once we set up the VMCS and hence
10420	* this function is never called.
10421	*
10422	* For nested-guests since the nested hypervisor provides these controls on every
10423	* nested-guest VM-entry and could potentially change them everytime we need to
10424	* merge them before every nested-guest VM-entry.
10425	*
10426	* @returns VBox status code.
10427	* @param pVCpu The cross context virtual CPU structure.
10428	*/
10429	static int hmR0VmxMergeVmcsNested(PVMCPUCC pVCpu)
10430	{
10431	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
10432	PCVMXVMCSINFO pVmcsInfoGst = &pVCpu->hmr0.s.vmx.VmcsInfo;
10433	PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
10434	Assert(pVmcsNstGst);
10435
10436	/*
10437	* Merge the controls with the requirements of the guest VMCS.
10438	*
10439	* We do not need to validate the nested-guest VMX features specified in the nested-guest
10440	* VMCS with the features supported by the physical CPU as it's already done by the
10441	* VMLAUNCH/VMRESUME instruction emulation.
10442	*
10443	* This is because the VMX features exposed by CPUM (through CPUID/MSRs) to the guest are
10444	* derived from the VMX features supported by the physical CPU.
10445	*/
10446
10447	/* Pin-based VM-execution controls. */
10448	uint32_t const u32PinCtls = pVmcsNstGst->u32PinCtls \| pVmcsInfoGst->u32PinCtls;
10449
10450	/* Processor-based VM-execution controls. */
10451	uint32_t u32ProcCtls = (pVmcsNstGst->u32ProcCtls & ~VMX_PROC_CTLS_USE_IO_BITMAPS)
10452	\| (pVmcsInfoGst->u32ProcCtls & ~( VMX_PROC_CTLS_INT_WINDOW_EXIT
10453	\| VMX_PROC_CTLS_NMI_WINDOW_EXIT
10454	\| VMX_PROC_CTLS_USE_TPR_SHADOW
10455	\| VMX_PROC_CTLS_MONITOR_TRAP_FLAG));
10456
10457	/* Secondary processor-based VM-execution controls. */
10458	uint32_t const u32ProcCtls2 = (pVmcsNstGst->u32ProcCtls2 & ~VMX_PROC_CTLS2_VPID)
10459	\| (pVmcsInfoGst->u32ProcCtls2 & ~( VMX_PROC_CTLS2_VIRT_APIC_ACCESS
10460	\| VMX_PROC_CTLS2_INVPCID
10461	\| VMX_PROC_CTLS2_VMCS_SHADOWING
10462	\| VMX_PROC_CTLS2_RDTSCP
10463	\| VMX_PROC_CTLS2_XSAVES_XRSTORS
10464	\| VMX_PROC_CTLS2_APIC_REG_VIRT
10465	\| VMX_PROC_CTLS2_VIRT_INT_DELIVERY
10466	\| VMX_PROC_CTLS2_VMFUNC));
10467
10468	/*
10469	* VM-entry controls:
10470	* These controls contains state that depends on the nested-guest state (primarily
10471	* EFER MSR) and is thus not constant between VMLAUNCH/VMRESUME and the nested-guest
10472	* VM-exit. Although the nested hypervisor cannot change it, we need to in order to
10473	* properly continue executing the nested-guest if the EFER MSR changes but does not
10474	* cause a nested-guest VM-exits.
10475	*
10476	* VM-exit controls:
10477	* These controls specify the host state on return. We cannot use the controls from
10478	* the nested hypervisor state as is as it would contain the guest state rather than
10479	* the host state. Since the host state is subject to change (e.g. preemption, trips
10480	* to ring-3, longjmp and rescheduling to a different host CPU) they are not constant
10481	* through VMLAUNCH/VMRESUME and the nested-guest VM-exit.
10482	*
10483	* VM-entry MSR-load:
10484	* The guest MSRs from the VM-entry MSR-load area are already loaded into the guest-CPU
10485	* context by the VMLAUNCH/VMRESUME instruction emulation.
10486	*
10487	* VM-exit MSR-store:
10488	* The VM-exit emulation will take care of populating the MSRs from the guest-CPU context
10489	* back into the VM-exit MSR-store area.
10490	*
10491	* VM-exit MSR-load areas:
10492	* This must contain the real host MSRs with hardware-assisted VMX execution. Hence, we
10493	* can entirely ignore what the nested hypervisor wants to load here.
10494	*/
10495
10496	/*
10497	* Exception bitmap.
10498	*
10499	* We could remove #UD from the guest bitmap and merge it with the nested-guest bitmap
10500	* here (and avoid doing anything while exporting nested-guest state), but to keep the
10501	* code more flexible if intercepting exceptions become more dynamic in the future we do
10502	* it as part of exporting the nested-guest state.
10503	*/
10504	uint32_t const u32XcptBitmap = pVmcsNstGst->u32XcptBitmap \| pVmcsInfoGst->u32XcptBitmap;
10505
10506	/*
10507	* CR0/CR4 guest/host mask.
10508	*
10509	* Modifications by the nested-guest to CR0/CR4 bits owned by the host and the guest must
10510	* cause VM-exits, so we need to merge them here.
10511	*/
10512	uint64_t const u64Cr0Mask = pVmcsNstGst->u64Cr0Mask.u \| pVmcsInfoGst->u64Cr0Mask;
10513	uint64_t const u64Cr4Mask = pVmcsNstGst->u64Cr4Mask.u \| pVmcsInfoGst->u64Cr4Mask;
10514
10515	/*
10516	* Page-fault error-code mask and match.
10517	*
10518	* Although we require unrestricted guest execution (and thereby nested-paging) for
10519	* hardware-assisted VMX execution of nested-guests and thus the outer guest doesn't
10520	* normally intercept #PFs, it might intercept them for debugging purposes.
10521	*
10522	* If the outer guest is not intercepting #PFs, we can use the nested-guest #PF filters.
10523	* If the outer guest is intercepting #PFs, we must intercept all #PFs.
10524	*/
10525	uint32_t u32XcptPFMask;
10526	uint32_t u32XcptPFMatch;
10527	if (!(pVmcsInfoGst->u32XcptBitmap & RT_BIT(X86_XCPT_PF)))
10528	{
10529	u32XcptPFMask = pVmcsNstGst->u32XcptPFMask;
10530	u32XcptPFMatch = pVmcsNstGst->u32XcptPFMatch;
10531	}
10532	else
10533	{
10534	u32XcptPFMask = 0;
10535	u32XcptPFMatch = 0;
10536	}
10537
10538	/*
10539	* Pause-Loop exiting.
10540	*/
10541	/** @todo r=bird: given that both pVM->hm.s.vmx.cPleGapTicks and
10542	* pVM->hm.s.vmx.cPleWindowTicks defaults to zero, I cannot see how
10543	* this will work... */
10544	uint32_t const cPleGapTicks = RT_MIN(pVM->hm.s.vmx.cPleGapTicks, pVmcsNstGst->u32PleGap);
10545	uint32_t const cPleWindowTicks = RT_MIN(pVM->hm.s.vmx.cPleWindowTicks, pVmcsNstGst->u32PleWindow);
10546
10547	/*
10548	* Pending debug exceptions.
10549	* Currently just copy whatever the nested-guest provides us.
10550	*/
10551	uint64_t const uPendingDbgXcpts = pVmcsNstGst->u64GuestPendingDbgXcpts.u;
10552
10553	/*
10554	* I/O Bitmap.
10555	*
10556	* We do not use the I/O bitmap that may be provided by the nested hypervisor as we always
10557	* intercept all I/O port accesses.
10558	*/
10559	Assert(u32ProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
10560	Assert(!(u32ProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS));
10561
10562	/*
10563	* VMCS shadowing.
10564	*
10565	* We do not yet expose VMCS shadowing to the guest and thus VMCS shadowing should not be
10566	* enabled while executing the nested-guest.
10567	*/
10568	Assert(!(u32ProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING));
10569
10570	/*
10571	* APIC-access page.
10572	*/
10573	RTHCPHYS HCPhysApicAccess;
10574	if (u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
10575	{
10576	Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
10577	RTGCPHYS const GCPhysApicAccess = pVmcsNstGst->u64AddrApicAccess.u;
10578
10579	/** @todo NSTVMX: This is not really correct but currently is required to make
10580	* things work. We need to re-enable the page handler when we fallback to
10581	* IEM execution of the nested-guest! */
10582	PGMHandlerPhysicalPageTempOff(pVM, GCPhysApicAccess, GCPhysApicAccess);
10583
10584	void *pvPage;
10585	PGMPAGEMAPLOCK PgLockApicAccess;
10586	int rc = PGMPhysGCPhys2CCPtr(pVM, GCPhysApicAccess, &pvPage, &PgLockApicAccess);
10587	if (RT_SUCCESS(rc))
10588	{
10589	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysApicAccess, &HCPhysApicAccess);
10590	AssertMsgRCReturn(rc, ("Failed to get host-physical address for APIC-access page at %#RGp\n", GCPhysApicAccess), rc);
10591
10592	/** @todo Handle proper releasing of page-mapping lock later. */
10593	PGMPhysReleasePageMappingLock(pVCpu->CTX_SUFF(pVM), &PgLockApicAccess);
10594	}
10595	else
10596	return rc;
10597	}
10598	else
10599	HCPhysApicAccess = 0;
10600
10601	/*
10602	* Virtual-APIC page and TPR threshold.
10603	*/
10604	RTHCPHYS HCPhysVirtApic;
10605	uint32_t u32TprThreshold;
10606	if (u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
10607	{
10608	Assert(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW);
10609	RTGCPHYS const GCPhysVirtApic = pVmcsNstGst->u64AddrVirtApic.u;
10610
10611	void *pvPage;
10612	PGMPAGEMAPLOCK PgLockVirtApic;
10613	int rc = PGMPhysGCPhys2CCPtr(pVM, GCPhysVirtApic, &pvPage, &PgLockVirtApic);
10614	if (RT_SUCCESS(rc))
10615	{
10616	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysVirtApic, &HCPhysVirtApic);
10617	AssertMsgRCReturn(rc, ("Failed to get host-physical address for virtual-APIC page at %#RGp\n", GCPhysVirtApic), rc);
10618
10619	/** @todo Handle proper releasing of page-mapping lock later. */
10620	PGMPhysReleasePageMappingLock(pVCpu->CTX_SUFF(pVM), &PgLockVirtApic);
10621	}
10622	else
10623	return rc;
10624
10625	u32TprThreshold = pVmcsNstGst->u32TprThreshold;
10626	}
10627	else
10628	{
10629	HCPhysVirtApic = 0;
10630	u32TprThreshold = 0;
10631
10632	/*
10633	* We must make sure CR8 reads/write must cause VM-exits when TPR shadowing is not
10634	* used by the nested hypervisor. Preventing MMIO accesses to the physical APIC will
10635	* be taken care of by EPT/shadow paging.
10636	*/
10637	if (pVM->hmr0.s.fAllow64BitGuests)
10638	u32ProcCtls \|= VMX_PROC_CTLS_CR8_STORE_EXIT
10639	\| VMX_PROC_CTLS_CR8_LOAD_EXIT;
10640	}
10641
10642	/*
10643	* Validate basic assumptions.
10644	*/
10645	PVMXVMCSINFO pVmcsInfoNstGst = &pVCpu->hmr0.s.vmx.VmcsInfoNstGst;
10646	Assert(pVM->hmr0.s.vmx.fUnrestrictedGuest);
10647	Assert(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
10648	Assert(hmGetVmxActiveVmcsInfo(pVCpu) == pVmcsInfoNstGst);
10649
10650	/*
10651	* Commit it to the nested-guest VMCS.
10652	*/
10653	int rc = VINF_SUCCESS;
10654	if (pVmcsInfoNstGst->u32PinCtls != u32PinCtls)
10655	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, u32PinCtls);
10656	if (pVmcsInfoNstGst->u32ProcCtls != u32ProcCtls)
10657	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, u32ProcCtls);
10658	if (pVmcsInfoNstGst->u32ProcCtls2 != u32ProcCtls2)
10659	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, u32ProcCtls2);
10660	if (pVmcsInfoNstGst->u32XcptBitmap != u32XcptBitmap)
10661	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);
10662	if (pVmcsInfoNstGst->u64Cr0Mask != u64Cr0Mask)
10663	rc \|= VMXWriteVmcsNw(VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask);
10664	if (pVmcsInfoNstGst->u64Cr4Mask != u64Cr4Mask)
10665	rc \|= VMXWriteVmcsNw(VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask);
10666	if (pVmcsInfoNstGst->u32XcptPFMask != u32XcptPFMask)
10667	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, u32XcptPFMask);
10668	if (pVmcsInfoNstGst->u32XcptPFMatch != u32XcptPFMatch)
10669	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, u32XcptPFMatch);
10670	if ( !(u32ProcCtls & VMX_PROC_CTLS_PAUSE_EXIT)
10671	&& (u32ProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT))
10672	{
10673	Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
10674	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, cPleGapTicks);
10675	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, cPleWindowTicks);
10676	}
10677	if (u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
10678	{
10679	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
10680	rc \|= VMXWriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, HCPhysVirtApic);
10681	}
10682	if (u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
10683	rc \|= VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, HCPhysApicAccess);
10684	rc \|= VMXWriteVmcsNw(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, uPendingDbgXcpts);
10685	AssertRC(rc);
10686
10687	/*
10688	* Update the nested-guest VMCS cache.
10689	*/
10690	pVmcsInfoNstGst->u32PinCtls = u32PinCtls;
10691	pVmcsInfoNstGst->u32ProcCtls = u32ProcCtls;
10692	pVmcsInfoNstGst->u32ProcCtls2 = u32ProcCtls2;
10693	pVmcsInfoNstGst->u32XcptBitmap = u32XcptBitmap;
10694	pVmcsInfoNstGst->u64Cr0Mask = u64Cr0Mask;
10695	pVmcsInfoNstGst->u64Cr4Mask = u64Cr4Mask;
10696	pVmcsInfoNstGst->u32XcptPFMask = u32XcptPFMask;
10697	pVmcsInfoNstGst->u32XcptPFMatch = u32XcptPFMatch;
10698	pVmcsInfoNstGst->HCPhysVirtApic = HCPhysVirtApic;
10699
10700	/*
10701	* We need to flush the TLB if we are switching the APIC-access page address.
10702	* See Intel spec. 28.3.3.4 "Guidelines for Use of the INVEPT Instruction".
10703	*/
10704	if (u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
10705	pVCpu->hm.s.vmx.fSwitchedNstGstFlushTlb = true;
10706
10707	/*
10708	* MSR bitmap.
10709	*
10710	* The MSR bitmap address has already been initialized while setting up the nested-guest
10711	* VMCS, here we need to merge the MSR bitmaps.
10712	*/
10713	if (u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
10714	hmR0VmxMergeMsrBitmapNested(pVCpu, pVmcsInfoNstGst, pVmcsInfoGst);
10715
10716	return VINF_SUCCESS;
10717	}
10718	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
10719
10720
10721	/**
10722	* Does the preparations before executing guest code in VT-x.
10723	*
10724	* This may cause longjmps to ring-3 and may even result in rescheduling to the
10725	* recompiler/IEM. We must be cautious what we do here regarding committing
10726	* guest-state information into the VMCS assuming we assuredly execute the
10727	* guest in VT-x mode.
10728	*
10729	* If we fall back to the recompiler/IEM after updating the VMCS and clearing
10730	* the common-state (TRPM/forceflags), we must undo those changes so that the
10731	* recompiler/IEM can (and should) use them when it resumes guest execution.
10732	* Otherwise such operations must be done when we can no longer exit to ring-3.
10733	*
10734	* @returns Strict VBox status code (i.e. informational status codes too).
10735	* @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
10736	* have been disabled.
10737	* @retval VINF_VMX_VMEXIT if a nested-guest VM-exit occurs (e.g., while evaluating
10738	* pending events).
10739	* @retval VINF_EM_RESET if a triple-fault occurs while injecting a
10740	* double-fault into the guest.
10741	* @retval VINF_EM_DBG_STEPPED if @a fStepping is true and an event was
10742	* dispatched directly.
10743	* @retval VINF_* scheduling changes, we have to go back to ring-3.
10744	*
10745	* @param pVCpu The cross context virtual CPU structure.
10746	* @param pVmxTransient The VMX-transient structure.
10747	* @param fStepping Whether we are single-stepping the guest in the
10748	* hypervisor debugger. Makes us ignore some of the reasons
10749	* for returning to ring-3, and return VINF_EM_DBG_STEPPED
10750	* if event dispatching took place.
10751	*/
10752	static VBOXSTRICTRC hmR0VmxPreRunGuest(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, bool fStepping)
10753	{
10754	Assert(VMMRZCallRing3IsEnabled(pVCpu));
10755
10756	Log4Func(("fIsNested=%RTbool fStepping=%RTbool\n", pVmxTransient->fIsNestedGuest, fStepping));
10757
10758	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
10759	if (pVmxTransient->fIsNestedGuest)
10760	{
10761	RT_NOREF2(pVCpu, fStepping);
10762	Log2Func(("Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
10763	return VINF_EM_RESCHEDULE_REM;
10764	}
10765	#endif
10766
10767	/*
10768	* Check and process force flag actions, some of which might require us to go back to ring-3.
10769	*/
10770	VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVCpu, pVmxTransient, fStepping);
10771	if (rcStrict == VINF_SUCCESS)
10772	{
10773	/* FFs don't get set all the time. */
10774	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
10775	if ( pVmxTransient->fIsNestedGuest
10776	&& !CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
10777	{
10778	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
10779	return VINF_VMX_VMEXIT;
10780	}
10781	#endif
10782	}
10783	else
10784	return rcStrict;
10785
10786	/*
10787	* Virtualize memory-mapped accesses to the physical APIC (may take locks).
10788	*/
10789	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
10790	if ( !pVCpu->hm.s.vmx.u64GstMsrApicBase
10791	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
10792	&& PDMHasApic(pVM))
10793	{
10794	int rc = hmR0VmxMapHCApicAccessPage(pVCpu);
10795	AssertRCReturn(rc, rc);
10796	}
10797
10798	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
10799	/*
10800	* Merge guest VMCS controls with the nested-guest VMCS controls.
10801	*
10802	* Even if we have not executed the guest prior to this (e.g. when resuming from a
10803	* saved state), we should be okay with merging controls as we initialize the
10804	* guest VMCS controls as part of VM setup phase.
10805	*/
10806	if ( pVmxTransient->fIsNestedGuest
10807	&& !pVCpu->hm.s.vmx.fMergedNstGstCtls)
10808	{
10809	int rc = hmR0VmxMergeVmcsNested(pVCpu);
10810	AssertRCReturn(rc, rc);
10811	pVCpu->hm.s.vmx.fMergedNstGstCtls = true;
10812	}
10813	#endif
10814
10815	/*
10816	* Evaluate events to be injected into the guest.
10817	*
10818	* Events in TRPM can be injected without inspecting the guest state.
10819	* If any new events (interrupts/NMI) are pending currently, we try to set up the
10820	* guest to cause a VM-exit the next time they are ready to receive the event.
10821	*
10822	* With nested-guests, evaluating pending events may cause VM-exits. Also, verify
10823	* that the event in TRPM that we will inject using hardware-assisted VMX is -not-
10824	* subject to interecption. Otherwise, we should have checked and injected them
10825	* manually elsewhere (IEM).
10826	*/
10827	if (TRPMHasTrap(pVCpu))
10828	{
10829	Assert(!pVmxTransient->fIsNestedGuest \|\| !CPUMIsGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx));
10830	hmR0VmxTrpmTrapToPendingEvent(pVCpu);
10831	}
10832
10833	uint32_t fIntrState;
10834	rcStrict = hmR0VmxEvaluatePendingEvent(pVCpu, pVmxTransient, &fIntrState);
10835
10836	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
10837	/*
10838	* While evaluating pending events if something failed (unlikely) or if we were
10839	* preparing to run a nested-guest but performed a nested-guest VM-exit, we should bail.
10840	*/
10841	if (rcStrict != VINF_SUCCESS)
10842	return rcStrict;
10843	if ( pVmxTransient->fIsNestedGuest
10844	&& !CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
10845	{
10846	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
10847	return VINF_VMX_VMEXIT;
10848	}
10849	#else
10850	Assert(rcStrict == VINF_SUCCESS);
10851	#endif
10852
10853	/*
10854	* Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus
10855	* needs to be done with longjmps or interrupts + preemption enabled. Event injection might
10856	* also result in triple-faulting the VM.
10857	*
10858	* With nested-guests, the above does not apply since unrestricted guest execution is a
10859	* requirement. Regardless, we do this here to avoid duplicating code elsewhere.
10860	*/
10861	rcStrict = hmR0VmxInjectPendingEvent(pVCpu, pVmxTransient, fIntrState, fStepping);
10862	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
10863	{ /* likely */ }
10864	else
10865	{
10866	AssertMsg(rcStrict == VINF_EM_RESET \|\| (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
10867	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
10868	return rcStrict;
10869	}
10870
10871	/*
10872	* A longjump might result in importing CR3 even for VM-exits that don't necessarily
10873	* import CR3 themselves. We will need to update them here, as even as late as the above
10874	* hmR0VmxInjectPendingEvent() call may lazily import guest-CPU state on demand causing
10875	* the below force flags to be set.
10876	*/
10877	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
10878	{
10879	Assert(!(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_CR3));
10880	int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
10881	AssertMsgReturn(rc2 == VINF_SUCCESS \|\| rc2 == VINF_PGM_SYNC_CR3,
10882	("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
10883	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
10884	}
10885	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
10886	{
10887	PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
10888	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
10889	}
10890
10891	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
10892	/* Paranoia. */
10893	Assert(!pVmxTransient->fIsNestedGuest \|\| CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx));
10894	#endif
10895
10896	/*
10897	* No longjmps to ring-3 from this point on!!!
10898	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
10899	* This also disables flushing of the R0-logger instance (if any).
10900	*/
10901	VMMRZCallRing3Disable(pVCpu);
10902
10903	/*
10904	* Export the guest state bits.
10905	*
10906	* We cannot perform longjmps while loading the guest state because we do not preserve the
10907	* host/guest state (although the VMCS will be preserved) across longjmps which can cause
10908	* CPU migration.
10909	*
10910	* If we are injecting events to a real-on-v86 mode guest, we would have updated RIP and some segment
10911	* registers. Hence, exporting of the guest state needs to be done -after- injection of events.
10912	*/
10913	rcStrict = hmR0VmxExportGuestStateOptimal(pVCpu, pVmxTransient);
10914	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
10915	{ /* likely */ }
10916	else
10917	{
10918	VMMRZCallRing3Enable(pVCpu);
10919	return rcStrict;
10920	}
10921
10922	/*
10923	* We disable interrupts so that we don't miss any interrupts that would flag preemption
10924	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
10925	* preemption disabled for a while. Since this is purely to aid the
10926	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
10927	* disable interrupt on NT.
10928	*
10929	* We need to check for force-flags that could've possible been altered since we last
10930	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
10931	* see @bugref{6398}).
10932	*
10933	* We also check a couple of other force-flags as a last opportunity to get the EMT back
10934	* to ring-3 before executing guest code.
10935	*/
10936	pVmxTransient->fEFlags = ASMIntDisableFlags();
10937
10938	if ( ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
10939	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
10940	\|\| ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */
10941	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT))) )
10942	{
10943	if (!RTThreadPreemptIsPending(NIL_RTTHREAD))
10944	{
10945	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
10946	/*
10947	* If we are executing a nested-guest make sure that we should intercept subsequent
10948	* events. The one we are injecting might be part of VM-entry. This is mainly to keep
10949	* the VM-exit instruction emulation happy.
10950	*/
10951	if (pVmxTransient->fIsNestedGuest)
10952	CPUMSetGuestVmxInterceptEvents(&pVCpu->cpum.GstCtx, true);
10953	#endif
10954
10955	/*
10956	* We've injected any pending events. This is really the point of no return (to ring-3).
10957	*
10958	* Note! The caller expects to continue with interrupts & longjmps disabled on successful
10959	* returns from this function, so do -not- enable them here.
10960	*/
10961	pVCpu->hm.s.Event.fPending = false;
10962	return VINF_SUCCESS;
10963	}
10964
10965	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
10966	rcStrict = VINF_EM_RAW_INTERRUPT;
10967	}
10968	else
10969	{
10970	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
10971	rcStrict = VINF_EM_RAW_TO_R3;
10972	}
10973
10974	ASMSetFlags(pVmxTransient->fEFlags);
10975	VMMRZCallRing3Enable(pVCpu);
10976
10977	return rcStrict;
10978	}
10979
10980
10981	/**
10982	* Final preparations before executing guest code using hardware-assisted VMX.
10983	*
10984	* We can no longer get preempted to a different host CPU and there are no returns
10985	* to ring-3. We ignore any errors that may happen from this point (e.g. VMWRITE
10986	* failures), this function is not intended to fail sans unrecoverable hardware
10987	* errors.
10988	*
10989	* @param pVCpu The cross context virtual CPU structure.
10990	* @param pVmxTransient The VMX-transient structure.
10991	*
10992	* @remarks Called with preemption disabled.
10993	* @remarks No-long-jump zone!!!
10994	*/
10995	static void hmR0VmxPreRunGuestCommitted(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
10996	{
10997	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
10998	Assert(VMMR0IsLogFlushDisabled(pVCpu));
10999	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
11000	Assert(!pVCpu->hm.s.Event.fPending);
11001
11002	/*
11003	* Indicate start of guest execution and where poking EMT out of guest-context is recognized.
11004	*/
11005	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
11006	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
11007
11008	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
11009	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
11010	PHMPHYSCPU pHostCpu = hmR0GetCurrentCpu();
11011	RTCPUID const idCurrentCpu = pHostCpu->idCpu;
11012
11013	if (!CPUMIsGuestFPUStateActive(pVCpu))
11014	{
11015	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
11016	if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
11017	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT;
11018	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
11019	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
11020	}
11021
11022	/*
11023	* Re-export the host state bits as we may've been preempted (only happens when
11024	* thread-context hooks are used or when the VM start function changes) or if
11025	* the host CR0 is modified while loading the guest FPU state above.
11026	*
11027	* The 64-on-32 switcher saves the (64-bit) host state into the VMCS and if we
11028	* changed the switcher back to 32-bit, we must save the 32-bit host state here,
11029	* see @bugref{8432}.
11030	*
11031	* This may also happen when switching to/from a nested-guest VMCS without leaving
11032	* ring-0.
11033	*/
11034	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
11035	{
11036	hmR0VmxExportHostState(pVCpu);
11037	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportHostState);
11038	}
11039	Assert(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT));
11040
11041	/*
11042	* Export the state shared between host and guest (FPU, debug, lazy MSRs).
11043	*/
11044	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)
11045	hmR0VmxExportSharedState(pVCpu, pVmxTransient);
11046	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
11047
11048	/*
11049	* Store status of the shared guest/host debug state at the time of VM-entry.
11050	*/
11051	pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
11052	pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
11053
11054	/*
11055	* Always cache the TPR-shadow if the virtual-APIC page exists, thereby skipping
11056	* more than one conditional check. The post-run side of our code shall determine
11057	* if it needs to sync. the virtual APIC TPR with the TPR-shadow.
11058	*/
11059	if (pVmcsInfo->pbVirtApic)
11060	pVmxTransient->u8GuestTpr = pVmcsInfo->pbVirtApic[XAPIC_OFF_TPR];
11061
11062	/*
11063	* Update the host MSRs values in the VM-exit MSR-load area.
11064	*/
11065	if (!pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs)
11066	{
11067	if (pVmcsInfo->cExitMsrLoad > 0)
11068	hmR0VmxUpdateAutoLoadHostMsrs(pVCpu, pVmcsInfo);
11069	pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs = true;
11070	}
11071
11072	/*
11073	* Evaluate if we need to intercept guest RDTSC/P accesses. Set up the
11074	* VMX-preemption timer based on the next virtual sync clock deadline.
11075	*/
11076	if ( !pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer
11077	\|\| idCurrentCpu != pVCpu->hmr0.s.idLastCpu)
11078	{
11079	hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVCpu, pVmxTransient, idCurrentCpu);
11080	pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer = true;
11081	}
11082
11083	/* Record statistics of how often we use TSC offsetting as opposed to intercepting RDTSC/P. */
11084	bool const fIsRdtscIntercepted = RT_BOOL(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
11085	if (!fIsRdtscIntercepted)
11086	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
11087	else
11088	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
11089
11090	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
11091	hmR0VmxFlushTaggedTlb(pHostCpu, pVCpu, pVmcsInfo); /* Invalidate the appropriate guest entries from the TLB. */
11092	Assert(idCurrentCpu == pVCpu->hmr0.s.idLastCpu);
11093	pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Record the error reporting info. with the current host CPU. */
11094	pVmcsInfo->idHostCpuState = idCurrentCpu; /* Record the CPU for which the host-state has been exported. */
11095	pVmcsInfo->idHostCpuExec = idCurrentCpu; /* Record the CPU on which we shall execute. */
11096
11097	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
11098
11099	TMNotifyStartOfExecution(pVM, pVCpu); /* Notify TM to resume its clocks when TSC is tied to execution,
11100	as we're about to start executing the guest. */
11101
11102	/*
11103	* Load the guest TSC_AUX MSR when we are not intercepting RDTSCP.
11104	*
11105	* This is done this late as updating the TSC offsetting/preemption timer above
11106	* figures out if we can skip intercepting RDTSCP by calculating the number of
11107	* host CPU ticks till the next virtual sync deadline (for the dynamic case).
11108	*/
11109	if ( (pVmcsInfo->u32ProcCtls2 & VMX_PROC_CTLS2_RDTSCP)
11110	&& !fIsRdtscIntercepted)
11111	{
11112	hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_TSC_AUX);
11113
11114	/* NB: Because we call hmR0VmxAddAutoLoadStoreMsr with fUpdateHostMsr=true,
11115	it's safe even after hmR0VmxUpdateAutoLoadHostMsrs has already been done. */
11116	int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, pVmxTransient, MSR_K8_TSC_AUX, CPUMGetGuestTscAux(pVCpu),
11117	true /* fSetReadWrite /, true / fUpdateHostMsr */);
11118	AssertRC(rc);
11119	Assert(!pVmxTransient->fRemoveTscAuxMsr);
11120	pVmxTransient->fRemoveTscAuxMsr = true;
11121	}
11122
11123	#ifdef VBOX_STRICT
11124	Assert(pVCpu->hmr0.s.vmx.fUpdatedHostAutoMsrs);
11125	hmR0VmxCheckAutoLoadStoreMsrs(pVCpu, pVmcsInfo, pVmxTransient->fIsNestedGuest);
11126	hmR0VmxCheckHostEferMsr(pVmcsInfo);
11127	AssertRC(hmR0VmxCheckCachedVmcsCtls(pVCpu, pVmcsInfo, pVmxTransient->fIsNestedGuest));
11128	#endif
11129
11130	#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
11131	/** @todo r=ramshankar: We can now probably use iemVmxVmentryCheckGuestState here.
11132	* Add a PVMXMSRS parameter to it, so that IEM can look at the host MSRs,
11133	* see @bugref{9180#c54}. */
11134	uint32_t const uInvalidReason = hmR0VmxCheckGuestState(pVCpu, pVmcsInfo);
11135	if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
11136	Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
11137	#endif
11138	}
11139
11140
11141	/**
11142	* First C routine invoked after running guest code using hardware-assisted VMX.
11143	*
11144	* @param pVCpu The cross context virtual CPU structure.
11145	* @param pVmxTransient The VMX-transient structure.
11146	* @param rcVMRun Return code of VMLAUNCH/VMRESUME.
11147	*
11148	* @remarks Called with interrupts disabled, and returns with interrupts enabled!
11149	*
11150	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
11151	* unconditionally when it is safe to do so.
11152	*/
11153	static void hmR0VmxPostRunGuest(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, int rcVMRun)
11154	{
11155	ASMAtomicUoWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
11156	ASMAtomicIncU32(&pVCpu->hmr0.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
11157	pVCpu->hm.s.fCtxChanged = 0; /* Exits/longjmps to ring-3 requires saving the guest state. */
11158	pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
11159	pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
11160	pVmxTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
11161
11162	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
11163	if (!(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
11164	{
11165	uint64_t uGstTsc;
11166	if (!pVmxTransient->fIsNestedGuest)
11167	uGstTsc = pVCpu->hmr0.s.uTscExit + pVmcsInfo->u64TscOffset;
11168	else
11169	{
11170	uint64_t const uNstGstTsc = pVCpu->hmr0.s.uTscExit + pVmcsInfo->u64TscOffset;
11171	uGstTsc = CPUMRemoveNestedGuestTscOffset(pVCpu, uNstGstTsc);
11172	}
11173	TMCpuTickSetLastSeen(pVCpu, uGstTsc); /* Update TM with the guest TSC. */
11174	}
11175
11176	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
11177	TMNotifyEndOfExecution(pVCpu->CTX_SUFF(pVM), pVCpu, pVCpu->hmr0.s.uTscExit); /* Notify TM that the guest is no longer running. */
11178	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
11179
11180	pVCpu->hmr0.s.vmx.fRestoreHostFlags \|= VMX_RESTORE_HOST_REQUIRED; /* Some host state messed up by VMX needs restoring. */
11181	pVmcsInfo->fVmcsState \|= VMX_V_VMCS_LAUNCH_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
11182	#ifdef VBOX_STRICT
11183	hmR0VmxCheckHostEferMsr(pVmcsInfo); /* Verify that the host EFER MSR wasn't modified. */
11184	#endif
11185	Assert(!ASMIntAreEnabled());
11186	ASMSetFlags(pVmxTransient->fEFlags); /* Enable interrupts. */
11187	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
11188
11189	#ifdef HMVMX_ALWAYS_CLEAN_TRANSIENT
11190	/*
11191	* Clean all the VMCS fields in the transient structure before reading
11192	* anything from the VMCS.
11193	*/
11194	pVmxTransient->uExitReason = 0;
11195	pVmxTransient->uExitIntErrorCode = 0;
11196	pVmxTransient->uExitQual = 0;
11197	pVmxTransient->uGuestLinearAddr = 0;
11198	pVmxTransient->uExitIntInfo = 0;
11199	pVmxTransient->cbExitInstr = 0;
11200	pVmxTransient->ExitInstrInfo.u = 0;
11201	pVmxTransient->uEntryIntInfo = 0;
11202	pVmxTransient->uEntryXcptErrorCode = 0;
11203	pVmxTransient->cbEntryInstr = 0;
11204	pVmxTransient->uIdtVectoringInfo = 0;
11205	pVmxTransient->uIdtVectoringErrorCode = 0;
11206	#endif
11207
11208	/*
11209	* Save the basic VM-exit reason and check if the VM-entry failed.
11210	* See Intel spec. 24.9.1 "Basic VM-exit Information".
11211	*/
11212	uint32_t uExitReason;
11213	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
11214	AssertRC(rc);
11215	pVmxTransient->uExitReason = VMX_EXIT_REASON_BASIC(uExitReason);
11216	pVmxTransient->fVMEntryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
11217
11218	/*
11219	* Log the VM-exit before logging anything else as otherwise it might be a
11220	* tad confusing what happens before and after the world-switch.
11221	*/
11222	HMVMX_LOG_EXIT(pVCpu, uExitReason);
11223
11224	/*
11225	* Remove the TSC_AUX MSR from the auto-load/store MSR area and reset any MSR
11226	* bitmap permissions, if it was added before VM-entry.
11227	*/
11228	if (pVmxTransient->fRemoveTscAuxMsr)
11229	{
11230	hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, pVmxTransient, MSR_K8_TSC_AUX);
11231	pVmxTransient->fRemoveTscAuxMsr = false;
11232	}
11233
11234	/*
11235	* Check if VMLAUNCH/VMRESUME succeeded.
11236	* If this failed, we cause a guru meditation and cease further execution.
11237	*
11238	* However, if we are executing a nested-guest we might fail if we use the
11239	* fast path rather than fully emulating VMLAUNCH/VMRESUME instruction in IEM.
11240	*/
11241	if (RT_LIKELY(rcVMRun == VINF_SUCCESS))
11242	{
11243	/*
11244	* Update the VM-exit history array here even if the VM-entry failed due to:
11245	* - Invalid guest state.
11246	* - MSR loading.
11247	* - Machine-check event.
11248	*
11249	* In any of the above cases we will still have a "valid" VM-exit reason
11250	* despite @a fVMEntryFailed being false.
11251	*
11252	* See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
11253	*
11254	* Note! We don't have CS or RIP at this point. Will probably address that later
11255	* by amending the history entry added here.
11256	*/
11257	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_VMX, pVmxTransient->uExitReason & EMEXIT_F_TYPE_MASK),
11258	UINT64_MAX, pVCpu->hmr0.s.uTscExit);
11259
11260	if (RT_LIKELY(!pVmxTransient->fVMEntryFailed))
11261	{
11262	VMMRZCallRing3Enable(pVCpu);
11263
11264	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
11265	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
11266
11267	#ifdef HMVMX_ALWAYS_SAVE_RO_GUEST_STATE
11268	hmR0VmxReadAllRoFieldsVmcs(pVmxTransient);
11269	#endif
11270
11271	/*
11272	* Import the guest-interruptibility state always as we need it while evaluating
11273	* injecting events on re-entry.
11274	*
11275	* We don't import CR0 (when unrestricted guest execution is unavailable) despite
11276	* checking for real-mode while exporting the state because all bits that cause
11277	* mode changes wrt CR0 are intercepted.
11278	*/
11279	uint64_t const fImportMask = CPUMCTX_EXTRN_HM_VMX_INT_STATE
11280	#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) \|\| defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
11281	\| HMVMX_CPUMCTX_EXTRN_ALL
11282	#elif defined(HMVMX_ALWAYS_SAVE_GUEST_RFLAGS)
11283	\| CPUMCTX_EXTRN_RFLAGS
11284	#endif
11285	;
11286	rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, fImportMask);
11287	AssertRC(rc);
11288
11289	/*
11290	* Sync the TPR shadow with our APIC state.
11291	*/
11292	if ( !pVmxTransient->fIsNestedGuest
11293	&& (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW))
11294	{
11295	Assert(pVmcsInfo->pbVirtApic);
11296	if (pVmxTransient->u8GuestTpr != pVmcsInfo->pbVirtApic[XAPIC_OFF_TPR])
11297	{
11298	rc = APICSetTpr(pVCpu, pVmcsInfo->pbVirtApic[XAPIC_OFF_TPR]);
11299	AssertRC(rc);
11300	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
11301	}
11302	}
11303
11304	Assert(VMMRZCallRing3IsEnabled(pVCpu));
11305	return;
11306	}
11307	}
11308	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
11309	else if (pVmxTransient->fIsNestedGuest)
11310	AssertMsgFailed(("VMLAUNCH/VMRESUME failed but shouldn't happen when VMLAUNCH/VMRESUME was emulated in IEM!\n"));
11311	#endif
11312	else
11313	Log4Func(("VM-entry failure: rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", rcVMRun, pVmxTransient->fVMEntryFailed));
11314
11315	VMMRZCallRing3Enable(pVCpu);
11316	}
11317
11318
11319	/**
11320	* Runs the guest code using hardware-assisted VMX the normal way.
11321	*
11322	* @returns VBox status code.
11323	* @param pVCpu The cross context virtual CPU structure.
11324	* @param pcLoops Pointer to the number of executed loops.
11325	*/
11326	static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVMCPUCC pVCpu, uint32_t *pcLoops)
11327	{
11328	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
11329	Assert(pcLoops);
11330	Assert(*pcLoops <= cMaxResumeLoops);
11331	Assert(!CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx));
11332
11333	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
11334	/*
11335	* Switch to the guest VMCS as we may have transitioned from executing the nested-guest
11336	* without leaving ring-0. Otherwise, if we came from ring-3 we would have loaded the
11337	* guest VMCS while entering the VMX ring-0 session.
11338	*/
11339	if (pVCpu->hmr0.s.vmx.fSwitchedToNstGstVmcs)
11340	{
11341	int rc = hmR0VmxSwitchToGstOrNstGstVmcs(pVCpu, false /* fSwitchToNstGstVmcs */);
11342	if (RT_SUCCESS(rc))
11343	{ /* likely */ }
11344	else
11345	{
11346	LogRelFunc(("Failed to switch to the guest VMCS. rc=%Rrc\n", rc));
11347	return rc;
11348	}
11349	}
11350	#endif
11351
11352	VMXTRANSIENT VmxTransient;
11353	RT_ZERO(VmxTransient);
11354	VmxTransient.pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
11355
11356	/* Paranoia. */
11357	Assert(VmxTransient.pVmcsInfo == &pVCpu->hmr0.s.vmx.VmcsInfo);
11358
11359	VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
11360	for (;;)
11361	{
11362	Assert(!HMR0SuspendPending());
11363	HMVMX_ASSERT_CPU_SAFE(pVCpu);
11364	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
11365
11366	/*
11367	* Preparatory work for running nested-guest code, this may force us to
11368	* return to ring-3.
11369	*
11370	* Warning! This bugger disables interrupts on VINF_SUCCESS!
11371	*/
11372	rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, false /* fStepping */);
11373	if (rcStrict != VINF_SUCCESS)
11374	break;
11375
11376	/* Interrupts are disabled at this point! */
11377	hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
11378	int rcRun = hmR0VmxRunGuest(pVCpu, &VmxTransient);
11379	hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
11380	/* Interrupts are re-enabled at this point! */
11381
11382	/*
11383	* Check for errors with running the VM (VMLAUNCH/VMRESUME).
11384	*/
11385	if (RT_SUCCESS(rcRun))
11386	{ /* very likely */ }
11387	else
11388	{
11389	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
11390	hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
11391	return rcRun;
11392	}
11393
11394	/*
11395	* Profile the VM-exit.
11396	*/
11397	AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
11398	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
11399	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
11400	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
11401	HMVMX_START_EXIT_DISPATCH_PROF();
11402
11403	VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
11404
11405	/*
11406	* Handle the VM-exit.
11407	*/
11408	#ifdef HMVMX_USE_FUNCTION_TABLE
11409	rcStrict = g_aVMExitHandlers[VmxTransient.uExitReason].pfn(pVCpu, &VmxTransient);
11410	#else
11411	rcStrict = hmR0VmxHandleExit(pVCpu, &VmxTransient);
11412	#endif
11413	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
11414	if (rcStrict == VINF_SUCCESS)
11415	{
11416	if (++(*pcLoops) <= cMaxResumeLoops)
11417	continue;
11418	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
11419	rcStrict = VINF_EM_RAW_INTERRUPT;
11420	}
11421	break;
11422	}
11423
11424	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
11425	return rcStrict;
11426	}
11427
11428
11429	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
11430	/**
11431	* Runs the nested-guest code using hardware-assisted VMX.
11432	*
11433	* @returns VBox status code.
11434	* @param pVCpu The cross context virtual CPU structure.
11435	* @param pcLoops Pointer to the number of executed loops.
11436	*
11437	* @sa hmR0VmxRunGuestCodeNormal.
11438	*/
11439	static VBOXSTRICTRC hmR0VmxRunGuestCodeNested(PVMCPUCC pVCpu, uint32_t *pcLoops)
11440	{
11441	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
11442	Assert(pcLoops);
11443	Assert(*pcLoops <= cMaxResumeLoops);
11444	Assert(CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx));
11445
11446	/*
11447	* Switch to the nested-guest VMCS as we may have transitioned from executing the
11448	* guest without leaving ring-0. Otherwise, if we came from ring-3 we would have
11449	* loaded the nested-guest VMCS while entering the VMX ring-0 session.
11450	*/
11451	if (!pVCpu->hmr0.s.vmx.fSwitchedToNstGstVmcs)
11452	{
11453	int rc = hmR0VmxSwitchToGstOrNstGstVmcs(pVCpu, true /* fSwitchToNstGstVmcs */);
11454	if (RT_SUCCESS(rc))
11455	{ /* likely */ }
11456	else
11457	{
11458	LogRelFunc(("Failed to switch to the nested-guest VMCS. rc=%Rrc\n", rc));
11459	return rc;
11460	}
11461	}
11462
11463	VMXTRANSIENT VmxTransient;
11464	RT_ZERO(VmxTransient);
11465	VmxTransient.pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
11466	VmxTransient.fIsNestedGuest = true;
11467
11468	/* Paranoia. */
11469	Assert(VmxTransient.pVmcsInfo == &pVCpu->hmr0.s.vmx.VmcsInfoNstGst);
11470
11471	VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
11472	for (;;)
11473	{
11474	Assert(!HMR0SuspendPending());
11475	HMVMX_ASSERT_CPU_SAFE(pVCpu);
11476	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
11477
11478	/*
11479	* Preparatory work for running guest code, this may force us to
11480	* return to ring-3.
11481	*
11482	* Warning! This bugger disables interrupts on VINF_SUCCESS!
11483	*/
11484	rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, false /* fStepping */);
11485	if (rcStrict != VINF_SUCCESS)
11486	break;
11487
11488	/* Interrupts are disabled at this point! */
11489	hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
11490	int rcRun = hmR0VmxRunGuest(pVCpu, &VmxTransient);
11491	hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
11492	/* Interrupts are re-enabled at this point! */
11493
11494	/*
11495	* Check for errors with running the VM (VMLAUNCH/VMRESUME).
11496	*/
11497	if (RT_SUCCESS(rcRun))
11498	{ /* very likely */ }
11499	else
11500	{
11501	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
11502	hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
11503	return rcRun;
11504	}
11505
11506	/*
11507	* Profile the VM-exit.
11508	*/
11509	AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
11510	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
11511	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitAll);
11512	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
11513	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
11514	HMVMX_START_EXIT_DISPATCH_PROF();
11515
11516	VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
11517
11518	/*
11519	* Handle the VM-exit.
11520	*/
11521	rcStrict = hmR0VmxHandleExitNested(pVCpu, &VmxTransient);
11522	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
11523	if (rcStrict == VINF_SUCCESS)
11524	{
11525	if (!CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
11526	{
11527	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchNstGstVmexit);
11528	rcStrict = VINF_VMX_VMEXIT;
11529	}
11530	else
11531	{
11532	if (++(*pcLoops) <= cMaxResumeLoops)
11533	continue;
11534	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
11535	rcStrict = VINF_EM_RAW_INTERRUPT;
11536	}
11537	}
11538	else
11539	Assert(rcStrict != VINF_VMX_VMEXIT);
11540	break;
11541	}
11542
11543	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
11544	return rcStrict;
11545	}
11546	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
11547
11548
11549	/** @name Execution loop for single stepping, DBGF events and expensive Dtrace
11550	* probes.
11551	*
11552	* The following few functions and associated structure contains the bloat
11553	* necessary for providing detailed debug events and dtrace probes as well as
11554	* reliable host side single stepping. This works on the principle of
11555	* "subclassing" the normal execution loop and workers. We replace the loop
11556	* method completely and override selected helpers to add necessary adjustments
11557	* to their core operation.
11558	*
11559	* The goal is to keep the "parent" code lean and mean, so as not to sacrifice
11560	* any performance for debug and analysis features.
11561	*
11562	* @{
11563	*/
11564
11565	/**
11566	* Transient per-VCPU debug state of VMCS and related info. we save/restore in
11567	* the debug run loop.
11568	*/
11569	typedef struct VMXRUNDBGSTATE
11570	{
11571	/** The RIP we started executing at. This is for detecting that we stepped. */
11572	uint64_t uRipStart;
11573	/** The CS we started executing with. */
11574	uint16_t uCsStart;
11575
11576	/** Whether we've actually modified the 1st execution control field. */
11577	bool fModifiedProcCtls : 1;
11578	/** Whether we've actually modified the 2nd execution control field. */
11579	bool fModifiedProcCtls2 : 1;
11580	/** Whether we've actually modified the exception bitmap. */
11581	bool fModifiedXcptBitmap : 1;
11582
11583	/** We desire the modified the CR0 mask to be cleared. */
11584	bool fClearCr0Mask : 1;
11585	/** We desire the modified the CR4 mask to be cleared. */
11586	bool fClearCr4Mask : 1;
11587	/** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC. */
11588	uint32_t fCpe1Extra;
11589	/** Stuff we do not want in VMX_VMCS32_CTRL_PROC_EXEC. */
11590	uint32_t fCpe1Unwanted;
11591	/** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC2. */
11592	uint32_t fCpe2Extra;
11593	/** Extra stuff we need in VMX_VMCS32_CTRL_EXCEPTION_BITMAP. */
11594	uint32_t bmXcptExtra;
11595	/** The sequence number of the Dtrace provider settings the state was
11596	* configured against. */
11597	uint32_t uDtraceSettingsSeqNo;
11598	/** VM-exits to check (one bit per VM-exit). */
11599	uint32_t bmExitsToCheck[3];
11600
11601	/** The initial VMX_VMCS32_CTRL_PROC_EXEC value (helps with restore). */
11602	uint32_t fProcCtlsInitial;
11603	/** The initial VMX_VMCS32_CTRL_PROC_EXEC2 value (helps with restore). */
11604	uint32_t fProcCtls2Initial;
11605	/** The initial VMX_VMCS32_CTRL_EXCEPTION_BITMAP value (helps with restore). */
11606	uint32_t bmXcptInitial;
11607	} VMXRUNDBGSTATE;
11608	AssertCompileMemberSize(VMXRUNDBGSTATE, bmExitsToCheck, (VMX_EXIT_MAX + 1 + 31) / 32 * 4);
11609	typedef VMXRUNDBGSTATE *PVMXRUNDBGSTATE;
11610
11611
11612	/**
11613	* Initializes the VMXRUNDBGSTATE structure.
11614	*
11615	* @param pVCpu The cross context virtual CPU structure of the
11616	* calling EMT.
11617	* @param pVmxTransient The VMX-transient structure.
11618	* @param pDbgState The debug state to initialize.
11619	*/
11620	static void hmR0VmxRunDebugStateInit(PVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState)
11621	{
11622	pDbgState->uRipStart = pVCpu->cpum.GstCtx.rip;
11623	pDbgState->uCsStart = pVCpu->cpum.GstCtx.cs.Sel;
11624
11625	pDbgState->fModifiedProcCtls = false;
11626	pDbgState->fModifiedProcCtls2 = false;
11627	pDbgState->fModifiedXcptBitmap = false;
11628	pDbgState->fClearCr0Mask = false;
11629	pDbgState->fClearCr4Mask = false;
11630	pDbgState->fCpe1Extra = 0;
11631	pDbgState->fCpe1Unwanted = 0;
11632	pDbgState->fCpe2Extra = 0;
11633	pDbgState->bmXcptExtra = 0;
11634	pDbgState->fProcCtlsInitial = pVmxTransient->pVmcsInfo->u32ProcCtls;
11635	pDbgState->fProcCtls2Initial = pVmxTransient->pVmcsInfo->u32ProcCtls2;
11636	pDbgState->bmXcptInitial = pVmxTransient->pVmcsInfo->u32XcptBitmap;
11637	}
11638
11639
11640	/**
11641	* Updates the VMSC fields with changes requested by @a pDbgState.
11642	*
11643	* This is performed after hmR0VmxPreRunGuestDebugStateUpdate as well
11644	* immediately before executing guest code, i.e. when interrupts are disabled.
11645	* We don't check status codes here as we cannot easily assert or return in the
11646	* latter case.
11647	*
11648	* @param pVCpu The cross context virtual CPU structure.
11649	* @param pVmxTransient The VMX-transient structure.
11650	* @param pDbgState The debug state.
11651	*/
11652	static void hmR0VmxPreRunGuestDebugStateApply(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState)
11653	{
11654	/*
11655	* Ensure desired flags in VMCS control fields are set.
11656	* (Ignoring write failure here, as we're committed and it's just debug extras.)
11657	*
11658	* Note! We load the shadow CR0 & CR4 bits when we flag the clearing, so
11659	* there should be no stale data in pCtx at this point.
11660	*/
11661	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
11662	if ( (pVmcsInfo->u32ProcCtls & pDbgState->fCpe1Extra) != pDbgState->fCpe1Extra
11663	\|\| (pVmcsInfo->u32ProcCtls & pDbgState->fCpe1Unwanted))
11664	{
11665	pVmcsInfo->u32ProcCtls \|= pDbgState->fCpe1Extra;
11666	pVmcsInfo->u32ProcCtls &= ~pDbgState->fCpe1Unwanted;
11667	VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
11668	Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVmcsInfo->u32ProcCtls));
11669	pDbgState->fModifiedProcCtls = true;
11670	}
11671
11672	if ((pVmcsInfo->u32ProcCtls2 & pDbgState->fCpe2Extra) != pDbgState->fCpe2Extra)
11673	{
11674	pVmcsInfo->u32ProcCtls2 \|= pDbgState->fCpe2Extra;
11675	VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVmcsInfo->u32ProcCtls2);
11676	Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVmcsInfo->u32ProcCtls2));
11677	pDbgState->fModifiedProcCtls2 = true;
11678	}
11679
11680	if ((pVmcsInfo->u32XcptBitmap & pDbgState->bmXcptExtra) != pDbgState->bmXcptExtra)
11681	{
11682	pVmcsInfo->u32XcptBitmap \|= pDbgState->bmXcptExtra;
11683	VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVmcsInfo->u32XcptBitmap);
11684	Log6Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVmcsInfo->u32XcptBitmap));
11685	pDbgState->fModifiedXcptBitmap = true;
11686	}
11687
11688	if (pDbgState->fClearCr0Mask && pVmcsInfo->u64Cr0Mask != 0)
11689	{
11690	pVmcsInfo->u64Cr0Mask = 0;
11691	VMXWriteVmcsNw(VMX_VMCS_CTRL_CR0_MASK, 0);
11692	Log6Func(("VMX_VMCS_CTRL_CR0_MASK: 0\n"));
11693	}
11694
11695	if (pDbgState->fClearCr4Mask && pVmcsInfo->u64Cr4Mask != 0)
11696	{
11697	pVmcsInfo->u64Cr4Mask = 0;
11698	VMXWriteVmcsNw(VMX_VMCS_CTRL_CR4_MASK, 0);
11699	Log6Func(("VMX_VMCS_CTRL_CR4_MASK: 0\n"));
11700	}
11701
11702	NOREF(pVCpu);
11703	}
11704
11705
11706	/**
11707	* Restores VMCS fields that were changed by hmR0VmxPreRunGuestDebugStateApply for
11708	* re-entry next time around.
11709	*
11710	* @returns Strict VBox status code (i.e. informational status codes too).
11711	* @param pVCpu The cross context virtual CPU structure.
11712	* @param pVmxTransient The VMX-transient structure.
11713	* @param pDbgState The debug state.
11714	* @param rcStrict The return code from executing the guest using single
11715	* stepping.
11716	*/
11717	static VBOXSTRICTRC hmR0VmxRunDebugStateRevert(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState,
11718	VBOXSTRICTRC rcStrict)
11719	{
11720	/*
11721	* Restore VM-exit control settings as we may not reenter this function the
11722	* next time around.
11723	*/
11724	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
11725
11726	/* We reload the initial value, trigger what we can of recalculations the
11727	next time around. From the looks of things, that's all that's required atm. */
11728	if (pDbgState->fModifiedProcCtls)
11729	{
11730	if (!(pDbgState->fProcCtlsInitial & VMX_PROC_CTLS_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
11731	pDbgState->fProcCtlsInitial \|= VMX_PROC_CTLS_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
11732	int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
11733	AssertRC(rc2);
11734	pVmcsInfo->u32ProcCtls = pDbgState->fProcCtlsInitial;
11735	}
11736
11737	/* We're currently the only ones messing with this one, so just restore the
11738	cached value and reload the field. */
11739	if ( pDbgState->fModifiedProcCtls2
11740	&& pVmcsInfo->u32ProcCtls2 != pDbgState->fProcCtls2Initial)
11741	{
11742	int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);
11743	AssertRC(rc2);
11744	pVmcsInfo->u32ProcCtls2 = pDbgState->fProcCtls2Initial;
11745	}
11746
11747	/* If we've modified the exception bitmap, we restore it and trigger
11748	reloading and partial recalculation the next time around. */
11749	if (pDbgState->fModifiedXcptBitmap)
11750	pVmcsInfo->u32XcptBitmap = pDbgState->bmXcptInitial;
11751
11752	return rcStrict;
11753	}
11754
11755
11756	/**
11757	* Configures VM-exit controls for current DBGF and DTrace settings.
11758	*
11759	* This updates @a pDbgState and the VMCS execution control fields to reflect
11760	* the necessary VM-exits demanded by DBGF and DTrace.
11761	*
11762	* @param pVCpu The cross context virtual CPU structure.
11763	* @param pVmxTransient The VMX-transient structure. May update
11764	* fUpdatedTscOffsettingAndPreemptTimer.
11765	* @param pDbgState The debug state.
11766	*/
11767	static void hmR0VmxPreRunGuestDebugStateUpdate(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState)
11768	{
11769	/*
11770	* Take down the dtrace serial number so we can spot changes.
11771	*/
11772	pDbgState->uDtraceSettingsSeqNo = VBOXVMM_GET_SETTINGS_SEQ_NO();
11773	ASMCompilerBarrier();
11774
11775	/*
11776	* We'll rebuild most of the middle block of data members (holding the
11777	* current settings) as we go along here, so start by clearing it all.
11778	*/
11779	pDbgState->bmXcptExtra = 0;
11780	pDbgState->fCpe1Extra = 0;
11781	pDbgState->fCpe1Unwanted = 0;
11782	pDbgState->fCpe2Extra = 0;
11783	for (unsigned i = 0; i < RT_ELEMENTS(pDbgState->bmExitsToCheck); i++)
11784	pDbgState->bmExitsToCheck[i] = 0;
11785
11786	/*
11787	* Software interrupts (INT XXh) - no idea how to trigger these...
11788	*/
11789	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
11790	if ( DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_INTERRUPT_SOFTWARE)
11791	\|\| VBOXVMM_INT_SOFTWARE_ENABLED())
11792	{
11793	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
11794	}
11795
11796	/*
11797	* INT3 breakpoints - triggered by #BP exceptions.
11798	*/
11799	if (pVM->dbgf.ro.cEnabledInt3Breakpoints > 0)
11800	pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_BP);
11801
11802	/*
11803	* Exception bitmap and XCPT events+probes.
11804	*/
11805	for (int iXcpt = 0; iXcpt < (DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST + 1); iXcpt++)
11806	if (DBGF_IS_EVENT_ENABLED(pVM, (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + iXcpt)))
11807	pDbgState->bmXcptExtra \|= RT_BIT_32(iXcpt);
11808
11809	if (VBOXVMM_XCPT_DE_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_DE);
11810	if (VBOXVMM_XCPT_DB_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_DB);
11811	if (VBOXVMM_XCPT_BP_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_BP);
11812	if (VBOXVMM_XCPT_OF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_OF);
11813	if (VBOXVMM_XCPT_BR_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_BR);
11814	if (VBOXVMM_XCPT_UD_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_UD);
11815	if (VBOXVMM_XCPT_NM_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_NM);
11816	if (VBOXVMM_XCPT_DF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_DF);
11817	if (VBOXVMM_XCPT_TS_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_TS);
11818	if (VBOXVMM_XCPT_NP_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_NP);
11819	if (VBOXVMM_XCPT_SS_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_SS);
11820	if (VBOXVMM_XCPT_GP_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_GP);
11821	if (VBOXVMM_XCPT_PF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_PF);
11822	if (VBOXVMM_XCPT_MF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_MF);
11823	if (VBOXVMM_XCPT_AC_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_AC);
11824	if (VBOXVMM_XCPT_XF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_XF);
11825	if (VBOXVMM_XCPT_VE_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_VE);
11826	if (VBOXVMM_XCPT_SX_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_SX);
11827
11828	if (pDbgState->bmXcptExtra)
11829	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
11830
11831	/*
11832	* Process events and probes for VM-exits, making sure we get the wanted VM-exits.
11833	*
11834	* Note! This is the reverse of what hmR0VmxHandleExitDtraceEvents does.
11835	* So, when adding/changing/removing please don't forget to update it.
11836	*
11837	* Some of the macros are picking up local variables to save horizontal space,
11838	* (being able to see it in a table is the lesser evil here).
11839	*/
11840	#define IS_EITHER_ENABLED(a_pVM, a_EventSubName) \
11841	( DBGF_IS_EVENT_ENABLED(a_pVM, RT_CONCAT(DBGFEVENT_, a_EventSubName)) \
11842	\|\| RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)() )
11843	#define SET_ONLY_XBM_IF_EITHER_EN(a_EventSubName, a_uExit) \
11844	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
11845	{ AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
11846	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
11847	} else do { } while (0)
11848	#define SET_CPE1_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec) \
11849	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
11850	{ \
11851	(pDbgState)->fCpe1Extra \|= (a_fCtrlProcExec); \
11852	AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
11853	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
11854	} else do { } while (0)
11855	#define SET_CPEU_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fUnwantedCtrlProcExec) \
11856	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
11857	{ \
11858	(pDbgState)->fCpe1Unwanted \|= (a_fUnwantedCtrlProcExec); \
11859	AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
11860	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
11861	} else do { } while (0)
11862	#define SET_CPE2_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec2) \
11863	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
11864	{ \
11865	(pDbgState)->fCpe2Extra \|= (a_fCtrlProcExec2); \
11866	AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
11867	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
11868	} else do { } while (0)
11869
11870	SET_ONLY_XBM_IF_EITHER_EN(EXIT_TASK_SWITCH, VMX_EXIT_TASK_SWITCH); /* unconditional */
11871	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_VIOLATION, VMX_EXIT_EPT_VIOLATION); /* unconditional */
11872	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_MISCONFIG, VMX_EXIT_EPT_MISCONFIG); /* unconditional (unless #VE) */
11873	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_ACCESS, VMX_EXIT_APIC_ACCESS); /* feature dependent, nothing to enable here */
11874	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */
11875
11876	SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */
11877	SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID);
11878	SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */
11879	SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC);
11880	SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_PROC_CTLS_HLT_EXIT); /* paranoia */
11881	SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT);
11882	SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */
11883	SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD);
11884	SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_PROC_CTLS_INVLPG_EXIT);
11885	SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG);
11886	SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_PROC_CTLS_RDPMC_EXIT);
11887	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC);
11888	SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_PROC_CTLS_RDTSC_EXIT);
11889	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC);
11890	SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */
11891	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM);
11892	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */
11893	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL);
11894	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */
11895	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR);
11896	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */
11897	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH);
11898	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */
11899	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD);
11900	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */
11901	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST);
11902	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */
11903	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD);
11904	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */
11905	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME);
11906	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */
11907	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE);
11908	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */
11909	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF);
11910	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */
11911	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON);
11912
11913	if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)
11914	\|\| IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
11915	{
11916	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4
11917	\| CPUMCTX_EXTRN_APIC_TPR);
11918	AssertRC(rc);
11919
11920	#if 0 /** @todo fix me */
11921	pDbgState->fClearCr0Mask = true;
11922	pDbgState->fClearCr4Mask = true;
11923	#endif
11924	if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
11925	pDbgState->fCpe1Extra \|= VMX_PROC_CTLS_CR3_STORE_EXIT \| VMX_PROC_CTLS_CR8_STORE_EXIT;
11926	if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
11927	pDbgState->fCpe1Extra \|= VMX_PROC_CTLS_CR3_LOAD_EXIT \| VMX_PROC_CTLS_CR8_LOAD_EXIT;
11928	pDbgState->fCpe1Unwanted \|= VMX_PROC_CTLS_USE_TPR_SHADOW; /* risky? */
11929	/* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT. It would
11930	require clearing here and in the loop if we start using it. */
11931	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_CRX);
11932	}
11933	else
11934	{
11935	if (pDbgState->fClearCr0Mask)
11936	{
11937	pDbgState->fClearCr0Mask = false;
11938	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
11939	}
11940	if (pDbgState->fClearCr4Mask)
11941	{
11942	pDbgState->fClearCr4Mask = false;
11943	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
11944	}
11945	}
11946	SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX);
11947	SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX);
11948
11949	if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ)
11950	\|\| IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE))
11951	{
11952	/** @todo later, need to fix handler as it assumes this won't usually happen. */
11953	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX);
11954	}
11955	SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX);
11956	SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX);
11957
11958	SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS); /* risky clearing this? */
11959	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR);
11960	SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS);
11961	SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR);
11962	SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_PROC_CTLS_MWAIT_EXIT); /* paranoia */
11963	SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT);
11964	SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_PROC_CTLS_MONITOR_EXIT); /* paranoia */
11965	SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR);
11966	#if 0 /** @todo too slow, fix handler. */
11967	SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_PROC_CTLS_PAUSE_EXIT);
11968	#endif
11969	SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE);
11970
11971	if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT)
11972	\|\| IS_EITHER_ENABLED(pVM, INSTR_SIDT)
11973	\|\| IS_EITHER_ENABLED(pVM, INSTR_LGDT)
11974	\|\| IS_EITHER_ENABLED(pVM, INSTR_LIDT))
11975	{
11976	pDbgState->fCpe2Extra \|= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
11977	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_GDTR_IDTR_ACCESS);
11978	}
11979	SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_GDTR_IDTR_ACCESS);
11980	SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_GDTR_IDTR_ACCESS);
11981	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_GDTR_IDTR_ACCESS);
11982	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_GDTR_IDTR_ACCESS);
11983
11984	if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT)
11985	\|\| IS_EITHER_ENABLED(pVM, INSTR_STR)
11986	\|\| IS_EITHER_ENABLED(pVM, INSTR_LLDT)
11987	\|\| IS_EITHER_ENABLED(pVM, INSTR_LTR))
11988	{
11989	pDbgState->fCpe2Extra \|= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
11990	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_LDTR_TR_ACCESS);
11991	}
11992	SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_LDTR_TR_ACCESS);
11993	SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_LDTR_TR_ACCESS);
11994	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_LDTR_TR_ACCESS);
11995	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_LDTR_TR_ACCESS);
11996
11997	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */
11998	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT);
11999	SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_PROC_CTLS_RDTSC_EXIT);
12000	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP);
12001	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */
12002	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID);
12003	SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_PROC_CTLS2_WBINVD_EXIT);
12004	SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD);
12005	SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */
12006	SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV);
12007	SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_PROC_CTLS2_RDRAND_EXIT);
12008	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND);
12009	SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_PROC_CTLS_INVLPG_EXIT);
12010	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID);
12011	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */
12012	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC);
12013	SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_PROC_CTLS2_RDSEED_EXIT);
12014	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED);
12015	SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */
12016	SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES);
12017	SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */
12018	SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS);
12019
12020	#undef IS_EITHER_ENABLED
12021	#undef SET_ONLY_XBM_IF_EITHER_EN
12022	#undef SET_CPE1_XBM_IF_EITHER_EN
12023	#undef SET_CPEU_XBM_IF_EITHER_EN
12024	#undef SET_CPE2_XBM_IF_EITHER_EN
12025
12026	/*
12027	* Sanitize the control stuff.
12028	*/
12029	pDbgState->fCpe2Extra &= g_HmMsrs.u.vmx.ProcCtls2.n.allowed1;
12030	if (pDbgState->fCpe2Extra)
12031	pDbgState->fCpe1Extra \|= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
12032	pDbgState->fCpe1Extra &= g_HmMsrs.u.vmx.ProcCtls.n.allowed1;
12033	pDbgState->fCpe1Unwanted &= ~g_HmMsrs.u.vmx.ProcCtls.n.allowed0;
12034	if (pVCpu->hmr0.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_PROC_CTLS_RDTSC_EXIT))
12035	{
12036	pVCpu->hmr0.s.fDebugWantRdTscExit ^= true;
12037	pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer = false;
12038	}
12039
12040	Log6(("HM: debug state: cpe1=%#RX32 cpeu=%#RX32 cpe2=%#RX32%s%s\n",
12041	pDbgState->fCpe1Extra, pDbgState->fCpe1Unwanted, pDbgState->fCpe2Extra,
12042	pDbgState->fClearCr0Mask ? " clr-cr0" : "",
12043	pDbgState->fClearCr4Mask ? " clr-cr4" : ""));
12044	}
12045
12046
12047	/**
12048	* Fires off DBGF events and dtrace probes for a VM-exit, when it's
12049	* appropriate.
12050	*
12051	* The caller has checked the VM-exit against the
12052	* VMXRUNDBGSTATE::bmExitsToCheck bitmap. The caller has checked for NMIs
12053	* already, so we don't have to do that either.
12054	*
12055	* @returns Strict VBox status code (i.e. informational status codes too).
12056	* @param pVCpu The cross context virtual CPU structure.
12057	* @param pVmxTransient The VMX-transient structure.
12058	* @param uExitReason The VM-exit reason.
12059	*
12060	* @remarks The name of this function is displayed by dtrace, so keep it short
12061	* and to the point. No longer than 33 chars long, please.
12062	*/
12063	static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
12064	{
12065	/*
12066	* Translate the event into a DBGF event (enmEvent + uEventArg) and at the
12067	* same time check whether any corresponding Dtrace event is enabled (fDtrace).
12068	*
12069	* Note! This is the reverse operation of what hmR0VmxPreRunGuestDebugStateUpdate
12070	* does. Must add/change/remove both places. Same ordering, please.
12071	*
12072	* Added/removed events must also be reflected in the next section
12073	* where we dispatch dtrace events.
12074	*/
12075	bool fDtrace1 = false;
12076	bool fDtrace2 = false;
12077	DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END;
12078	DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END;
12079	uint32_t uEventArg = 0;
12080	#define SET_EXIT(a_EventSubName) \
12081	do { \
12082	enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
12083	fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
12084	} while (0)
12085	#define SET_BOTH(a_EventSubName) \
12086	do { \
12087	enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \
12088	enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
12089	fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \
12090	fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
12091	} while (0)
12092	switch (uExitReason)
12093	{
12094	case VMX_EXIT_MTF:
12095	return hmR0VmxExitMtf(pVCpu, pVmxTransient);
12096
12097	case VMX_EXIT_XCPT_OR_NMI:
12098	{
12099	uint8_t const idxVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
12100	switch (VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo))
12101	{
12102	case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
12103	case VMX_EXIT_INT_INFO_TYPE_SW_XCPT:
12104	case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT:
12105	if (idxVector <= (unsigned)(DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST))
12106	{
12107	if (VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uExitIntInfo))
12108	{
12109	hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
12110	uEventArg = pVmxTransient->uExitIntErrorCode;
12111	}
12112	enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);
12113	switch (enmEvent1)
12114	{
12115	case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break;
12116	case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break;
12117	case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break;
12118	case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break;
12119	case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break;
12120	case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break;
12121	case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break;
12122	case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break;
12123	case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break;
12124	case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break;
12125	case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break;
12126	case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break;
12127	case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break;
12128	case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break;
12129	case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break;
12130	case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break;
12131	case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break;
12132	case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break;
12133	default: break;
12134	}
12135	}
12136	else
12137	AssertFailed();
12138	break;
12139
12140	case VMX_EXIT_INT_INFO_TYPE_SW_INT:
12141	uEventArg = idxVector;
12142	enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE;
12143	fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED();
12144	break;
12145	}
12146	break;
12147	}
12148
12149	case VMX_EXIT_TRIPLE_FAULT:
12150	enmEvent1 = DBGFEVENT_TRIPLE_FAULT;
12151	//fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();
12152	break;
12153	case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break;
12154	case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break;
12155	case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break;
12156	case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break;
12157	case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break;
12158
12159	/* Instruction specific VM-exits: */
12160	case VMX_EXIT_CPUID: SET_BOTH(CPUID); break;
12161	case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break;
12162	case VMX_EXIT_HLT: SET_BOTH(HALT); break;
12163	case VMX_EXIT_INVD: SET_BOTH(INVD); break;
12164	case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break;
12165	case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break;
12166	case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break;
12167	case VMX_EXIT_RSM: SET_BOTH(RSM); break;
12168	case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break;
12169	case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break;
12170	case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break;
12171	case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break;
12172	case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break;
12173	case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break;
12174	case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break;
12175	case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break;
12176	case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break;
12177	case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break;
12178	case VMX_EXIT_MOV_CRX:
12179	hmR0VmxReadExitQualVmcs(pVmxTransient);
12180	if (VMX_EXIT_QUAL_CRX_ACCESS(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_CRX_ACCESS_READ)
12181	SET_BOTH(CRX_READ);
12182	else
12183	SET_BOTH(CRX_WRITE);
12184	uEventArg = VMX_EXIT_QUAL_CRX_REGISTER(pVmxTransient->uExitQual);
12185	break;
12186	case VMX_EXIT_MOV_DRX:
12187	hmR0VmxReadExitQualVmcs(pVmxTransient);
12188	if ( VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual)
12189	== VMX_EXIT_QUAL_DRX_DIRECTION_READ)
12190	SET_BOTH(DRX_READ);
12191	else
12192	SET_BOTH(DRX_WRITE);
12193	uEventArg = VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual);
12194	break;
12195	case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break;
12196	case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break;
12197	case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break;
12198	case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break;
12199	case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break;
12200	case VMX_EXIT_GDTR_IDTR_ACCESS:
12201	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12202	switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_XDTR_INSINFO_INSTR_ID))
12203	{
12204	case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break;
12205	case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break;
12206	case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break;
12207	case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break;
12208	}
12209	break;
12210
12211	case VMX_EXIT_LDTR_TR_ACCESS:
12212	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12213	switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_YYTR_INSINFO_INSTR_ID))
12214	{
12215	case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break;
12216	case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break;
12217	case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break;
12218	case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break;
12219	}
12220	break;
12221
12222	case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break;
12223	case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break;
12224	case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break;
12225	case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break;
12226	case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break;
12227	case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break;
12228	case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break;
12229	case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break;
12230	case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break;
12231	case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break;
12232	case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break;
12233
12234	/* Events that aren't relevant at this point. */
12235	case VMX_EXIT_EXT_INT:
12236	case VMX_EXIT_INT_WINDOW:
12237	case VMX_EXIT_NMI_WINDOW:
12238	case VMX_EXIT_TPR_BELOW_THRESHOLD:
12239	case VMX_EXIT_PREEMPT_TIMER:
12240	case VMX_EXIT_IO_INSTR:
12241	break;
12242
12243	/* Errors and unexpected events. */
12244	case VMX_EXIT_INIT_SIGNAL:
12245	case VMX_EXIT_SIPI:
12246	case VMX_EXIT_IO_SMI:
12247	case VMX_EXIT_SMI:
12248	case VMX_EXIT_ERR_INVALID_GUEST_STATE:
12249	case VMX_EXIT_ERR_MSR_LOAD:
12250	case VMX_EXIT_ERR_MACHINE_CHECK:
12251	case VMX_EXIT_PML_FULL:
12252	case VMX_EXIT_VIRTUALIZED_EOI:
12253	break;
12254
12255	default:
12256	AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
12257	break;
12258	}
12259	#undef SET_BOTH
12260	#undef SET_EXIT
12261
12262	/*
12263	* Dtrace tracepoints go first. We do them here at once so we don't
12264	* have to copy the guest state saving and stuff a few dozen times.
12265	* Down side is that we've got to repeat the switch, though this time
12266	* we use enmEvent since the probes are a subset of what DBGF does.
12267	*/
12268	if (fDtrace1 \|\| fDtrace2)
12269	{
12270	hmR0VmxReadExitQualVmcs(pVmxTransient);
12271	hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
12272	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12273	switch (enmEvent1)
12274	{
12275	/** @todo consider which extra parameters would be helpful for each probe. */
12276	case DBGFEVENT_END: break;
12277	case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pCtx); break;
12278	case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pCtx, pCtx->dr[6]); break;
12279	case DBGFEVENT_XCPT_BP: VBOXVMM_XCPT_BP(pVCpu, pCtx); break;
12280	case DBGFEVENT_XCPT_OF: VBOXVMM_XCPT_OF(pVCpu, pCtx); break;
12281	case DBGFEVENT_XCPT_BR: VBOXVMM_XCPT_BR(pVCpu, pCtx); break;
12282	case DBGFEVENT_XCPT_UD: VBOXVMM_XCPT_UD(pVCpu, pCtx); break;
12283	case DBGFEVENT_XCPT_NM: VBOXVMM_XCPT_NM(pVCpu, pCtx); break;
12284	case DBGFEVENT_XCPT_DF: VBOXVMM_XCPT_DF(pVCpu, pCtx); break;
12285	case DBGFEVENT_XCPT_TS: VBOXVMM_XCPT_TS(pVCpu, pCtx, uEventArg); break;
12286	case DBGFEVENT_XCPT_NP: VBOXVMM_XCPT_NP(pVCpu, pCtx, uEventArg); break;
12287	case DBGFEVENT_XCPT_SS: VBOXVMM_XCPT_SS(pVCpu, pCtx, uEventArg); break;
12288	case DBGFEVENT_XCPT_GP: VBOXVMM_XCPT_GP(pVCpu, pCtx, uEventArg); break;
12289	case DBGFEVENT_XCPT_PF: VBOXVMM_XCPT_PF(pVCpu, pCtx, uEventArg, pCtx->cr2); break;
12290	case DBGFEVENT_XCPT_MF: VBOXVMM_XCPT_MF(pVCpu, pCtx); break;
12291	case DBGFEVENT_XCPT_AC: VBOXVMM_XCPT_AC(pVCpu, pCtx); break;
12292	case DBGFEVENT_XCPT_XF: VBOXVMM_XCPT_XF(pVCpu, pCtx); break;
12293	case DBGFEVENT_XCPT_VE: VBOXVMM_XCPT_VE(pVCpu, pCtx); break;
12294	case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pCtx, uEventArg); break;
12295	case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pCtx, (uint8_t)uEventArg); break;
12296	case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
12297	case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pCtx); break;
12298	case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pCtx); break;
12299	case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pCtx); break;
12300	case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pCtx); break;
12301	case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pCtx); break;
12302	case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pCtx); break;
12303	case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pCtx); break;
12304	case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
12305	case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
12306	case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
12307	case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
12308	case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
12309	case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pCtx, pCtx->ecx,
12310	RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
12311	case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pCtx); break;
12312	case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pCtx); break;
12313	case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pCtx); break;
12314	case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pCtx); break;
12315	case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pCtx); break;
12316	case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pCtx); break;
12317	case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pCtx); break;
12318	case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pCtx); break;
12319	case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pCtx); break;
12320	case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pCtx); break;
12321	case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pCtx); break;
12322	case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pCtx); break;
12323	case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pCtx); break;
12324	case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pCtx); break;
12325	case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pCtx); break;
12326	case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pCtx); break;
12327	case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pCtx); break;
12328	case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pCtx); break;
12329	case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pCtx); break;
12330	case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pCtx); break;
12331	case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pCtx); break;
12332	case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pCtx); break;
12333	case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pCtx); break;
12334	case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pCtx); break;
12335	case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pCtx); break;
12336	case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pCtx); break;
12337	case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pCtx); break;
12338	case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pCtx); break;
12339	case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pCtx); break;
12340	case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pCtx); break;
12341	case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pCtx); break;
12342	case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pCtx); break;
12343	default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break;
12344	}
12345	switch (enmEvent2)
12346	{
12347	/** @todo consider which extra parameters would be helpful for each probe. */
12348	case DBGFEVENT_END: break;
12349	case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pCtx); break;
12350	case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
12351	case DBGFEVENT_EXIT_GETSEC: VBOXVMM_EXIT_GETSEC(pVCpu, pCtx); break;
12352	case DBGFEVENT_EXIT_HALT: VBOXVMM_EXIT_HALT(pVCpu, pCtx); break;
12353	case DBGFEVENT_EXIT_INVD: VBOXVMM_EXIT_INVD(pVCpu, pCtx); break;
12354	case DBGFEVENT_EXIT_INVLPG: VBOXVMM_EXIT_INVLPG(pVCpu, pCtx); break;
12355	case DBGFEVENT_EXIT_RDPMC: VBOXVMM_EXIT_RDPMC(pVCpu, pCtx); break;
12356	case DBGFEVENT_EXIT_RDTSC: VBOXVMM_EXIT_RDTSC(pVCpu, pCtx); break;
12357	case DBGFEVENT_EXIT_RSM: VBOXVMM_EXIT_RSM(pVCpu, pCtx); break;
12358	case DBGFEVENT_EXIT_CRX_READ: VBOXVMM_EXIT_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
12359	case DBGFEVENT_EXIT_CRX_WRITE: VBOXVMM_EXIT_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
12360	case DBGFEVENT_EXIT_DRX_READ: VBOXVMM_EXIT_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
12361	case DBGFEVENT_EXIT_DRX_WRITE: VBOXVMM_EXIT_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
12362	case DBGFEVENT_EXIT_RDMSR: VBOXVMM_EXIT_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
12363	case DBGFEVENT_EXIT_WRMSR: VBOXVMM_EXIT_WRMSR(pVCpu, pCtx, pCtx->ecx,
12364	RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
12365	case DBGFEVENT_EXIT_MWAIT: VBOXVMM_EXIT_MWAIT(pVCpu, pCtx); break;
12366	case DBGFEVENT_EXIT_MONITOR: VBOXVMM_EXIT_MONITOR(pVCpu, pCtx); break;
12367	case DBGFEVENT_EXIT_PAUSE: VBOXVMM_EXIT_PAUSE(pVCpu, pCtx); break;
12368	case DBGFEVENT_EXIT_SGDT: VBOXVMM_EXIT_SGDT(pVCpu, pCtx); break;
12369	case DBGFEVENT_EXIT_SIDT: VBOXVMM_EXIT_SIDT(pVCpu, pCtx); break;
12370	case DBGFEVENT_EXIT_LGDT: VBOXVMM_EXIT_LGDT(pVCpu, pCtx); break;
12371	case DBGFEVENT_EXIT_LIDT: VBOXVMM_EXIT_LIDT(pVCpu, pCtx); break;
12372	case DBGFEVENT_EXIT_SLDT: VBOXVMM_EXIT_SLDT(pVCpu, pCtx); break;
12373	case DBGFEVENT_EXIT_STR: VBOXVMM_EXIT_STR(pVCpu, pCtx); break;
12374	case DBGFEVENT_EXIT_LLDT: VBOXVMM_EXIT_LLDT(pVCpu, pCtx); break;
12375	case DBGFEVENT_EXIT_LTR: VBOXVMM_EXIT_LTR(pVCpu, pCtx); break;
12376	case DBGFEVENT_EXIT_RDTSCP: VBOXVMM_EXIT_RDTSCP(pVCpu, pCtx); break;
12377	case DBGFEVENT_EXIT_WBINVD: VBOXVMM_EXIT_WBINVD(pVCpu, pCtx); break;
12378	case DBGFEVENT_EXIT_XSETBV: VBOXVMM_EXIT_XSETBV(pVCpu, pCtx); break;
12379	case DBGFEVENT_EXIT_RDRAND: VBOXVMM_EXIT_RDRAND(pVCpu, pCtx); break;
12380	case DBGFEVENT_EXIT_RDSEED: VBOXVMM_EXIT_RDSEED(pVCpu, pCtx); break;
12381	case DBGFEVENT_EXIT_XSAVES: VBOXVMM_EXIT_XSAVES(pVCpu, pCtx); break;
12382	case DBGFEVENT_EXIT_XRSTORS: VBOXVMM_EXIT_XRSTORS(pVCpu, pCtx); break;
12383	case DBGFEVENT_EXIT_VMM_CALL: VBOXVMM_EXIT_VMM_CALL(pVCpu, pCtx); break;
12384	case DBGFEVENT_EXIT_VMX_VMCLEAR: VBOXVMM_EXIT_VMX_VMCLEAR(pVCpu, pCtx); break;
12385	case DBGFEVENT_EXIT_VMX_VMLAUNCH: VBOXVMM_EXIT_VMX_VMLAUNCH(pVCpu, pCtx); break;
12386	case DBGFEVENT_EXIT_VMX_VMPTRLD: VBOXVMM_EXIT_VMX_VMPTRLD(pVCpu, pCtx); break;
12387	case DBGFEVENT_EXIT_VMX_VMPTRST: VBOXVMM_EXIT_VMX_VMPTRST(pVCpu, pCtx); break;
12388	case DBGFEVENT_EXIT_VMX_VMREAD: VBOXVMM_EXIT_VMX_VMREAD(pVCpu, pCtx); break;
12389	case DBGFEVENT_EXIT_VMX_VMRESUME: VBOXVMM_EXIT_VMX_VMRESUME(pVCpu, pCtx); break;
12390	case DBGFEVENT_EXIT_VMX_VMWRITE: VBOXVMM_EXIT_VMX_VMWRITE(pVCpu, pCtx); break;
12391	case DBGFEVENT_EXIT_VMX_VMXOFF: VBOXVMM_EXIT_VMX_VMXOFF(pVCpu, pCtx); break;
12392	case DBGFEVENT_EXIT_VMX_VMXON: VBOXVMM_EXIT_VMX_VMXON(pVCpu, pCtx); break;
12393	case DBGFEVENT_EXIT_VMX_INVEPT: VBOXVMM_EXIT_VMX_INVEPT(pVCpu, pCtx); break;
12394	case DBGFEVENT_EXIT_VMX_INVVPID: VBOXVMM_EXIT_VMX_INVVPID(pVCpu, pCtx); break;
12395	case DBGFEVENT_EXIT_VMX_INVPCID: VBOXVMM_EXIT_VMX_INVPCID(pVCpu, pCtx); break;
12396	case DBGFEVENT_EXIT_VMX_VMFUNC: VBOXVMM_EXIT_VMX_VMFUNC(pVCpu, pCtx); break;
12397	case DBGFEVENT_EXIT_VMX_EPT_MISCONFIG: VBOXVMM_EXIT_VMX_EPT_MISCONFIG(pVCpu, pCtx); break;
12398	case DBGFEVENT_EXIT_VMX_EPT_VIOLATION: VBOXVMM_EXIT_VMX_EPT_VIOLATION(pVCpu, pCtx); break;
12399	case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pCtx); break;
12400	case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pCtx); break;
12401	default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break;
12402	}
12403	}
12404
12405	/*
12406	* Fire of the DBGF event, if enabled (our check here is just a quick one,
12407	* the DBGF call will do a full check).
12408	*
12409	* Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap.
12410	* Note! If we have to events, we prioritize the first, i.e. the instruction
12411	* one, in order to avoid event nesting.
12412	*/
12413	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
12414	if ( enmEvent1 != DBGFEVENT_END
12415	&& DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
12416	{
12417	hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
12418	VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent1, DBGFEVENTCTX_HM, 1, uEventArg);
12419	if (rcStrict != VINF_SUCCESS)
12420	return rcStrict;
12421	}
12422	else if ( enmEvent2 != DBGFEVENT_END
12423	&& DBGF_IS_EVENT_ENABLED(pVM, enmEvent2))
12424	{
12425	hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
12426	VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent2, DBGFEVENTCTX_HM, 1, uEventArg);
12427	if (rcStrict != VINF_SUCCESS)
12428	return rcStrict;
12429	}
12430
12431	return VINF_SUCCESS;
12432	}
12433
12434
12435	/**
12436	* Single-stepping VM-exit filtering.
12437	*
12438	* This is preprocessing the VM-exits and deciding whether we've gotten far
12439	* enough to return VINF_EM_DBG_STEPPED already. If not, normal VM-exit
12440	* handling is performed.
12441	*
12442	* @returns Strict VBox status code (i.e. informational status codes too).
12443	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
12444	* @param pVmxTransient The VMX-transient structure.
12445	* @param pDbgState The debug state.
12446	*/
12447	DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState)
12448	{
12449	/*
12450	* Expensive (saves context) generic dtrace VM-exit probe.
12451	*/
12452	uint32_t const uExitReason = pVmxTransient->uExitReason;
12453	if (!VBOXVMM_R0_HMVMX_VMEXIT_ENABLED())
12454	{ /* more likely */ }
12455	else
12456	{
12457	hmR0VmxReadExitQualVmcs(pVmxTransient);
12458	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
12459	AssertRC(rc);
12460	VBOXVMM_R0_HMVMX_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, pVmxTransient->uExitReason, pVmxTransient->uExitQual);
12461	}
12462
12463	/*
12464	* Check for host NMI, just to get that out of the way.
12465	*/
12466	if (uExitReason != VMX_EXIT_XCPT_OR_NMI)
12467	{ /* normally likely */ }
12468	else
12469	{
12470	hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
12471	uint32_t const uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
12472	if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
12473	return hmR0VmxExitHostNmi(pVCpu, pVmxTransient->pVmcsInfo);
12474	}
12475
12476	/*
12477	* Check for single stepping event if we're stepping.
12478	*/
12479	if (pVCpu->hm.s.fSingleInstruction)
12480	{
12481	switch (uExitReason)
12482	{
12483	case VMX_EXIT_MTF:
12484	return hmR0VmxExitMtf(pVCpu, pVmxTransient);
12485
12486	/* Various events: */
12487	case VMX_EXIT_XCPT_OR_NMI:
12488	case VMX_EXIT_EXT_INT:
12489	case VMX_EXIT_TRIPLE_FAULT:
12490	case VMX_EXIT_INT_WINDOW:
12491	case VMX_EXIT_NMI_WINDOW:
12492	case VMX_EXIT_TASK_SWITCH:
12493	case VMX_EXIT_TPR_BELOW_THRESHOLD:
12494	case VMX_EXIT_APIC_ACCESS:
12495	case VMX_EXIT_EPT_VIOLATION:
12496	case VMX_EXIT_EPT_MISCONFIG:
12497	case VMX_EXIT_PREEMPT_TIMER:
12498
12499	/* Instruction specific VM-exits: */
12500	case VMX_EXIT_CPUID:
12501	case VMX_EXIT_GETSEC:
12502	case VMX_EXIT_HLT:
12503	case VMX_EXIT_INVD:
12504	case VMX_EXIT_INVLPG:
12505	case VMX_EXIT_RDPMC:
12506	case VMX_EXIT_RDTSC:
12507	case VMX_EXIT_RSM:
12508	case VMX_EXIT_VMCALL:
12509	case VMX_EXIT_VMCLEAR:
12510	case VMX_EXIT_VMLAUNCH:
12511	case VMX_EXIT_VMPTRLD:
12512	case VMX_EXIT_VMPTRST:
12513	case VMX_EXIT_VMREAD:
12514	case VMX_EXIT_VMRESUME:
12515	case VMX_EXIT_VMWRITE:
12516	case VMX_EXIT_VMXOFF:
12517	case VMX_EXIT_VMXON:
12518	case VMX_EXIT_MOV_CRX:
12519	case VMX_EXIT_MOV_DRX:
12520	case VMX_EXIT_IO_INSTR:
12521	case VMX_EXIT_RDMSR:
12522	case VMX_EXIT_WRMSR:
12523	case VMX_EXIT_MWAIT:
12524	case VMX_EXIT_MONITOR:
12525	case VMX_EXIT_PAUSE:
12526	case VMX_EXIT_GDTR_IDTR_ACCESS:
12527	case VMX_EXIT_LDTR_TR_ACCESS:
12528	case VMX_EXIT_INVEPT:
12529	case VMX_EXIT_RDTSCP:
12530	case VMX_EXIT_INVVPID:
12531	case VMX_EXIT_WBINVD:
12532	case VMX_EXIT_XSETBV:
12533	case VMX_EXIT_RDRAND:
12534	case VMX_EXIT_INVPCID:
12535	case VMX_EXIT_VMFUNC:
12536	case VMX_EXIT_RDSEED:
12537	case VMX_EXIT_XSAVES:
12538	case VMX_EXIT_XRSTORS:
12539	{
12540	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
12541	AssertRCReturn(rc, rc);
12542	if ( pVCpu->cpum.GstCtx.rip != pDbgState->uRipStart
12543	\|\| pVCpu->cpum.GstCtx.cs.Sel != pDbgState->uCsStart)
12544	return VINF_EM_DBG_STEPPED;
12545	break;
12546	}
12547
12548	/* Errors and unexpected events: */
12549	case VMX_EXIT_INIT_SIGNAL:
12550	case VMX_EXIT_SIPI:
12551	case VMX_EXIT_IO_SMI:
12552	case VMX_EXIT_SMI:
12553	case VMX_EXIT_ERR_INVALID_GUEST_STATE:
12554	case VMX_EXIT_ERR_MSR_LOAD:
12555	case VMX_EXIT_ERR_MACHINE_CHECK:
12556	case VMX_EXIT_PML_FULL:
12557	case VMX_EXIT_VIRTUALIZED_EOI:
12558	case VMX_EXIT_APIC_WRITE: /* Some talk about this being fault like, so I guess we must process it? */
12559	break;
12560
12561	default:
12562	AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
12563	break;
12564	}
12565	}
12566
12567	/*
12568	* Check for debugger event breakpoints and dtrace probes.
12569	*/
12570	if ( uExitReason < RT_ELEMENTS(pDbgState->bmExitsToCheck) * 32U
12571	&& ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
12572	{
12573	VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVCpu, pVmxTransient, uExitReason);
12574	if (rcStrict != VINF_SUCCESS)
12575	return rcStrict;
12576	}
12577
12578	/*
12579	* Normal processing.
12580	*/
12581	#ifdef HMVMX_USE_FUNCTION_TABLE
12582	return g_aVMExitHandlers[uExitReason].pfn(pVCpu, pVmxTransient);
12583	#else
12584	return hmR0VmxHandleExit(pVCpu, pVmxTransient, uExitReason);
12585	#endif
12586	}
12587
12588
12589	/**
12590	* Single steps guest code using hardware-assisted VMX.
12591	*
12592	* This is -not- the same as the guest single-stepping itself (say using EFLAGS.TF)
12593	* but single-stepping through the hypervisor debugger.
12594	*
12595	* @returns Strict VBox status code (i.e. informational status codes too).
12596	* @param pVCpu The cross context virtual CPU structure.
12597	* @param pcLoops Pointer to the number of executed loops.
12598	*
12599	* @note Mostly the same as hmR0VmxRunGuestCodeNormal().
12600	*/
12601	static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVMCPUCC pVCpu, uint32_t *pcLoops)
12602	{
12603	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hmr0.s.cMaxResumeLoops;
12604	Assert(pcLoops);
12605	Assert(*pcLoops <= cMaxResumeLoops);
12606
12607	VMXTRANSIENT VmxTransient;
12608	RT_ZERO(VmxTransient);
12609	VmxTransient.pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
12610
12611	/* Set HMCPU indicators. */
12612	bool const fSavedSingleInstruction = pVCpu->hm.s.fSingleInstruction;
12613	pVCpu->hm.s.fSingleInstruction = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
12614	pVCpu->hmr0.s.fDebugWantRdTscExit = false;
12615	pVCpu->hmr0.s.fUsingDebugLoop = true;
12616
12617	/* State we keep to help modify and later restore the VMCS fields we alter, and for detecting steps. */
12618	VMXRUNDBGSTATE DbgState;
12619	hmR0VmxRunDebugStateInit(pVCpu, &VmxTransient, &DbgState);
12620	hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &VmxTransient, &DbgState);
12621
12622	/*
12623	* The loop.
12624	*/
12625	VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
12626	for (;;)
12627	{
12628	Assert(!HMR0SuspendPending());
12629	HMVMX_ASSERT_CPU_SAFE(pVCpu);
12630	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
12631	bool fStepping = pVCpu->hm.s.fSingleInstruction;
12632
12633	/* Set up VM-execution controls the next two can respond to. */
12634	hmR0VmxPreRunGuestDebugStateApply(pVCpu, &VmxTransient, &DbgState);
12635
12636	/*
12637	* Preparatory work for running guest code, this may force us to
12638	* return to ring-3.
12639	*
12640	* Warning! This bugger disables interrupts on VINF_SUCCESS!
12641	*/
12642	rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, fStepping);
12643	if (rcStrict != VINF_SUCCESS)
12644	break;
12645
12646	/* Interrupts are disabled at this point! */
12647	hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
12648
12649	/* Override any obnoxious code in the above two calls. */
12650	hmR0VmxPreRunGuestDebugStateApply(pVCpu, &VmxTransient, &DbgState);
12651
12652	/*
12653	* Finally execute the guest.
12654	*/
12655	int rcRun = hmR0VmxRunGuest(pVCpu, &VmxTransient);
12656
12657	hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
12658	/* Interrupts are re-enabled at this point! */
12659
12660	/* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
12661	if (RT_SUCCESS(rcRun))
12662	{ /* very likely */ }
12663	else
12664	{
12665	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
12666	hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
12667	return rcRun;
12668	}
12669
12670	/* Profile the VM-exit. */
12671	AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
12672	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
12673	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
12674	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
12675	HMVMX_START_EXIT_DISPATCH_PROF();
12676
12677	VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
12678
12679	/*
12680	* Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
12681	*/
12682	rcStrict = hmR0VmxRunDebugHandleExit(pVCpu, &VmxTransient, &DbgState);
12683	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
12684	if (rcStrict != VINF_SUCCESS)
12685	break;
12686	if (++(*pcLoops) > cMaxResumeLoops)
12687	{
12688	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
12689	rcStrict = VINF_EM_RAW_INTERRUPT;
12690	break;
12691	}
12692
12693	/*
12694	* Stepping: Did the RIP change, if so, consider it a single step.
12695	* Otherwise, make sure one of the TFs gets set.
12696	*/
12697	if (fStepping)
12698	{
12699	int rc = hmR0VmxImportGuestState(pVCpu, VmxTransient.pVmcsInfo, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
12700	AssertRC(rc);
12701	if ( pVCpu->cpum.GstCtx.rip != DbgState.uRipStart
12702	\|\| pVCpu->cpum.GstCtx.cs.Sel != DbgState.uCsStart)
12703	{
12704	rcStrict = VINF_EM_DBG_STEPPED;
12705	break;
12706	}
12707	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
12708	}
12709
12710	/*
12711	* Update when dtrace settings changes (DBGF kicks us, so no need to check).
12712	*/
12713	if (VBOXVMM_GET_SETTINGS_SEQ_NO() != DbgState.uDtraceSettingsSeqNo)
12714	hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &VmxTransient, &DbgState);
12715
12716	/* Restore all controls applied by hmR0VmxPreRunGuestDebugStateApply above. */
12717	rcStrict = hmR0VmxRunDebugStateRevert(pVCpu, &VmxTransient, &DbgState, rcStrict);
12718	Assert(rcStrict == VINF_SUCCESS);
12719	}
12720
12721	/*
12722	* Clear the X86_EFL_TF if necessary.
12723	*/
12724	if (pVCpu->hmr0.s.fClearTrapFlag)
12725	{
12726	int rc = hmR0VmxImportGuestState(pVCpu, VmxTransient.pVmcsInfo, CPUMCTX_EXTRN_RFLAGS);
12727	AssertRC(rc);
12728	pVCpu->hmr0.s.fClearTrapFlag = false;
12729	pVCpu->cpum.GstCtx.eflags.Bits.u1TF = 0;
12730	}
12731	/** @todo there seems to be issues with the resume flag when the monitor trap
12732	* flag is pending without being used. Seen early in bios init when
12733	* accessing APIC page in protected mode. */
12734
12735	/* Restore HMCPU indicators. */
12736	pVCpu->hmr0.s.fUsingDebugLoop = false;
12737	pVCpu->hmr0.s.fDebugWantRdTscExit = false;
12738	pVCpu->hm.s.fSingleInstruction = fSavedSingleInstruction;
12739
12740	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
12741	return rcStrict;
12742	}
12743
12744
12745	/** @} */
12746
12747
12748	/**
12749	* Checks if any expensive dtrace probes are enabled and we should go to the
12750	* debug loop.
12751	*
12752	* @returns true if we should use debug loop, false if not.
12753	*/
12754	static bool hmR0VmxAnyExpensiveProbesEnabled(void)
12755	{
12756	/* It's probably faster to OR the raw 32-bit counter variables together.
12757	Since the variables are in an array and the probes are next to one
12758	another (more or less), we have good locality. So, better read
12759	eight-nine cache lines ever time and only have one conditional, than
12760	128+ conditionals, right? */
12761	return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */
12762	\| VBOXVMM_XCPT_DE_ENABLED_RAW()
12763	\| VBOXVMM_XCPT_DB_ENABLED_RAW()
12764	\| VBOXVMM_XCPT_BP_ENABLED_RAW()
12765	\| VBOXVMM_XCPT_OF_ENABLED_RAW()
12766	\| VBOXVMM_XCPT_BR_ENABLED_RAW()
12767	\| VBOXVMM_XCPT_UD_ENABLED_RAW()
12768	\| VBOXVMM_XCPT_NM_ENABLED_RAW()
12769	\| VBOXVMM_XCPT_DF_ENABLED_RAW()
12770	\| VBOXVMM_XCPT_TS_ENABLED_RAW()
12771	\| VBOXVMM_XCPT_NP_ENABLED_RAW()
12772	\| VBOXVMM_XCPT_SS_ENABLED_RAW()
12773	\| VBOXVMM_XCPT_GP_ENABLED_RAW()
12774	\| VBOXVMM_XCPT_PF_ENABLED_RAW()
12775	\| VBOXVMM_XCPT_MF_ENABLED_RAW()
12776	\| VBOXVMM_XCPT_AC_ENABLED_RAW()
12777	\| VBOXVMM_XCPT_XF_ENABLED_RAW()
12778	\| VBOXVMM_XCPT_VE_ENABLED_RAW()
12779	\| VBOXVMM_XCPT_SX_ENABLED_RAW()
12780	\| VBOXVMM_INT_SOFTWARE_ENABLED_RAW()
12781	\| VBOXVMM_INT_HARDWARE_ENABLED_RAW()
12782	) != 0
12783	\|\| ( VBOXVMM_INSTR_HALT_ENABLED_RAW()
12784	\| VBOXVMM_INSTR_MWAIT_ENABLED_RAW()
12785	\| VBOXVMM_INSTR_MONITOR_ENABLED_RAW()
12786	\| VBOXVMM_INSTR_CPUID_ENABLED_RAW()
12787	\| VBOXVMM_INSTR_INVD_ENABLED_RAW()
12788	\| VBOXVMM_INSTR_WBINVD_ENABLED_RAW()
12789	\| VBOXVMM_INSTR_INVLPG_ENABLED_RAW()
12790	\| VBOXVMM_INSTR_RDTSC_ENABLED_RAW()
12791	\| VBOXVMM_INSTR_RDTSCP_ENABLED_RAW()
12792	\| VBOXVMM_INSTR_RDPMC_ENABLED_RAW()
12793	\| VBOXVMM_INSTR_RDMSR_ENABLED_RAW()
12794	\| VBOXVMM_INSTR_WRMSR_ENABLED_RAW()
12795	\| VBOXVMM_INSTR_CRX_READ_ENABLED_RAW()
12796	\| VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW()
12797	\| VBOXVMM_INSTR_DRX_READ_ENABLED_RAW()
12798	\| VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW()
12799	\| VBOXVMM_INSTR_PAUSE_ENABLED_RAW()
12800	\| VBOXVMM_INSTR_XSETBV_ENABLED_RAW()
12801	\| VBOXVMM_INSTR_SIDT_ENABLED_RAW()
12802	\| VBOXVMM_INSTR_LIDT_ENABLED_RAW()
12803	\| VBOXVMM_INSTR_SGDT_ENABLED_RAW()
12804	\| VBOXVMM_INSTR_LGDT_ENABLED_RAW()
12805	\| VBOXVMM_INSTR_SLDT_ENABLED_RAW()
12806	\| VBOXVMM_INSTR_LLDT_ENABLED_RAW()
12807	\| VBOXVMM_INSTR_STR_ENABLED_RAW()
12808	\| VBOXVMM_INSTR_LTR_ENABLED_RAW()
12809	\| VBOXVMM_INSTR_GETSEC_ENABLED_RAW()
12810	\| VBOXVMM_INSTR_RSM_ENABLED_RAW()
12811	\| VBOXVMM_INSTR_RDRAND_ENABLED_RAW()
12812	\| VBOXVMM_INSTR_RDSEED_ENABLED_RAW()
12813	\| VBOXVMM_INSTR_XSAVES_ENABLED_RAW()
12814	\| VBOXVMM_INSTR_XRSTORS_ENABLED_RAW()
12815	\| VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW()
12816	\| VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW()
12817	\| VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW()
12818	\| VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW()
12819	\| VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW()
12820	\| VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW()
12821	\| VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW()
12822	\| VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW()
12823	\| VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW()
12824	\| VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW()
12825	\| VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW()
12826	\| VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW()
12827	\| VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW()
12828	\| VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW()
12829	) != 0
12830	\|\| ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW()
12831	\| VBOXVMM_EXIT_HALT_ENABLED_RAW()
12832	\| VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
12833	\| VBOXVMM_EXIT_MONITOR_ENABLED_RAW()
12834	\| VBOXVMM_EXIT_CPUID_ENABLED_RAW()
12835	\| VBOXVMM_EXIT_INVD_ENABLED_RAW()
12836	\| VBOXVMM_EXIT_WBINVD_ENABLED_RAW()
12837	\| VBOXVMM_EXIT_INVLPG_ENABLED_RAW()
12838	\| VBOXVMM_EXIT_RDTSC_ENABLED_RAW()
12839	\| VBOXVMM_EXIT_RDTSCP_ENABLED_RAW()
12840	\| VBOXVMM_EXIT_RDPMC_ENABLED_RAW()
12841	\| VBOXVMM_EXIT_RDMSR_ENABLED_RAW()
12842	\| VBOXVMM_EXIT_WRMSR_ENABLED_RAW()
12843	\| VBOXVMM_EXIT_CRX_READ_ENABLED_RAW()
12844	\| VBOXVMM_EXIT_CRX_WRITE_ENABLED_RAW()
12845	\| VBOXVMM_EXIT_DRX_READ_ENABLED_RAW()
12846	\| VBOXVMM_EXIT_DRX_WRITE_ENABLED_RAW()
12847	\| VBOXVMM_EXIT_PAUSE_ENABLED_RAW()
12848	\| VBOXVMM_EXIT_XSETBV_ENABLED_RAW()
12849	\| VBOXVMM_EXIT_SIDT_ENABLED_RAW()
12850	\| VBOXVMM_EXIT_LIDT_ENABLED_RAW()
12851	\| VBOXVMM_EXIT_SGDT_ENABLED_RAW()
12852	\| VBOXVMM_EXIT_LGDT_ENABLED_RAW()
12853	\| VBOXVMM_EXIT_SLDT_ENABLED_RAW()
12854	\| VBOXVMM_EXIT_LLDT_ENABLED_RAW()
12855	\| VBOXVMM_EXIT_STR_ENABLED_RAW()
12856	\| VBOXVMM_EXIT_LTR_ENABLED_RAW()
12857	\| VBOXVMM_EXIT_GETSEC_ENABLED_RAW()
12858	\| VBOXVMM_EXIT_RSM_ENABLED_RAW()
12859	\| VBOXVMM_EXIT_RDRAND_ENABLED_RAW()
12860	\| VBOXVMM_EXIT_RDSEED_ENABLED_RAW()
12861	\| VBOXVMM_EXIT_XSAVES_ENABLED_RAW()
12862	\| VBOXVMM_EXIT_XRSTORS_ENABLED_RAW()
12863	\| VBOXVMM_EXIT_VMM_CALL_ENABLED_RAW()
12864	\| VBOXVMM_EXIT_VMX_VMCLEAR_ENABLED_RAW()
12865	\| VBOXVMM_EXIT_VMX_VMLAUNCH_ENABLED_RAW()
12866	\| VBOXVMM_EXIT_VMX_VMPTRLD_ENABLED_RAW()
12867	\| VBOXVMM_EXIT_VMX_VMPTRST_ENABLED_RAW()
12868	\| VBOXVMM_EXIT_VMX_VMREAD_ENABLED_RAW()
12869	\| VBOXVMM_EXIT_VMX_VMRESUME_ENABLED_RAW()
12870	\| VBOXVMM_EXIT_VMX_VMWRITE_ENABLED_RAW()
12871	\| VBOXVMM_EXIT_VMX_VMXOFF_ENABLED_RAW()
12872	\| VBOXVMM_EXIT_VMX_VMXON_ENABLED_RAW()
12873	\| VBOXVMM_EXIT_VMX_VMFUNC_ENABLED_RAW()
12874	\| VBOXVMM_EXIT_VMX_INVEPT_ENABLED_RAW()
12875	\| VBOXVMM_EXIT_VMX_INVVPID_ENABLED_RAW()
12876	\| VBOXVMM_EXIT_VMX_INVPCID_ENABLED_RAW()
12877	\| VBOXVMM_EXIT_VMX_EPT_VIOLATION_ENABLED_RAW()
12878	\| VBOXVMM_EXIT_VMX_EPT_MISCONFIG_ENABLED_RAW()
12879	\| VBOXVMM_EXIT_VMX_VAPIC_ACCESS_ENABLED_RAW()
12880	\| VBOXVMM_EXIT_VMX_VAPIC_WRITE_ENABLED_RAW()
12881	) != 0;
12882	}
12883
12884
12885	/**
12886	* Runs the guest using hardware-assisted VMX.
12887	*
12888	* @returns Strict VBox status code (i.e. informational status codes too).
12889	* @param pVCpu The cross context virtual CPU structure.
12890	*/
12891	VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPUCC pVCpu)
12892	{
12893	AssertPtr(pVCpu);
12894	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12895	Assert(VMMRZCallRing3IsEnabled(pVCpu));
12896	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
12897	HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
12898
12899	VBOXSTRICTRC rcStrict;
12900	uint32_t cLoops = 0;
12901	for (;;)
12902	{
12903	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
12904	bool const fInNestedGuestMode = CPUMIsGuestInVmxNonRootMode(pCtx);
12905	#else
12906	NOREF(pCtx);
12907	bool const fInNestedGuestMode = false;
12908	#endif
12909	if (!fInNestedGuestMode)
12910	{
12911	if ( !pVCpu->hm.s.fUseDebugLoop
12912	&& (!VBOXVMM_ANY_PROBES_ENABLED() \|\| !hmR0VmxAnyExpensiveProbesEnabled())
12913	&& !DBGFIsStepping(pVCpu)
12914	&& !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
12915	rcStrict = hmR0VmxRunGuestCodeNormal(pVCpu, &cLoops);
12916	else
12917	rcStrict = hmR0VmxRunGuestCodeDebug(pVCpu, &cLoops);
12918	}
12919	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
12920	else
12921	rcStrict = hmR0VmxRunGuestCodeNested(pVCpu, &cLoops);
12922
12923	if (rcStrict == VINF_VMX_VMLAUNCH_VMRESUME)
12924	{
12925	Assert(CPUMIsGuestInVmxNonRootMode(pCtx));
12926	continue;
12927	}
12928	if (rcStrict == VINF_VMX_VMEXIT)
12929	{
12930	Assert(!CPUMIsGuestInVmxNonRootMode(pCtx));
12931	continue;
12932	}
12933	#endif
12934	break;
12935	}
12936
12937	int const rcLoop = VBOXSTRICTRC_VAL(rcStrict);
12938	switch (rcLoop)
12939	{
12940	case VERR_EM_INTERPRETER: rcStrict = VINF_EM_RAW_EMULATE_INSTR; break;
12941	case VINF_EM_RESET: rcStrict = VINF_EM_TRIPLE_FAULT; break;
12942	}
12943
12944	int rc2 = hmR0VmxExitToRing3(pVCpu, rcStrict);
12945	if (RT_FAILURE(rc2))
12946	{
12947	pVCpu->hm.s.u32HMError = (uint32_t)VBOXSTRICTRC_VAL(rcStrict);
12948	rcStrict = rc2;
12949	}
12950	Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
12951	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
12952	return rcStrict;
12953	}
12954
12955
12956	#ifndef HMVMX_USE_FUNCTION_TABLE
12957	/**
12958	* Handles a guest VM-exit from hardware-assisted VMX execution.
12959	*
12960	* @returns Strict VBox status code (i.e. informational status codes too).
12961	* @param pVCpu The cross context virtual CPU structure.
12962	* @param pVmxTransient The VMX-transient structure.
12963	*/
12964	DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
12965	{
12966	#ifdef DEBUG_ramshankar
12967	# define VMEXIT_CALL_RET(a_fSave, a_CallExpr) \
12968	do { \
12969	if (a_fSave != 0) \
12970	hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL); \
12971	VBOXSTRICTRC rcStrict = a_CallExpr; \
12972	if (a_fSave != 0) \
12973	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
12974	return rcStrict; \
12975	} while (0)
12976	#else
12977	# define VMEXIT_CALL_RET(a_fSave, a_CallExpr) return a_CallExpr
12978	#endif
12979	uint32_t const uExitReason = pVmxTransient->uExitReason;
12980	switch (uExitReason)
12981	{
12982	case VMX_EXIT_EPT_MISCONFIG: VMEXIT_CALL_RET(0, hmR0VmxExitEptMisconfig(pVCpu, pVmxTransient));
12983	case VMX_EXIT_EPT_VIOLATION: VMEXIT_CALL_RET(0, hmR0VmxExitEptViolation(pVCpu, pVmxTransient));
12984	case VMX_EXIT_IO_INSTR: VMEXIT_CALL_RET(0, hmR0VmxExitIoInstr(pVCpu, pVmxTransient));
12985	case VMX_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0VmxExitCpuid(pVCpu, pVmxTransient));
12986	case VMX_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0VmxExitRdtsc(pVCpu, pVmxTransient));
12987	case VMX_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0VmxExitRdtscp(pVCpu, pVmxTransient));
12988	case VMX_EXIT_APIC_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitApicAccess(pVCpu, pVmxTransient));
12989	case VMX_EXIT_XCPT_OR_NMI: VMEXIT_CALL_RET(0, hmR0VmxExitXcptOrNmi(pVCpu, pVmxTransient));
12990	case VMX_EXIT_MOV_CRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovCRx(pVCpu, pVmxTransient));
12991	case VMX_EXIT_EXT_INT: VMEXIT_CALL_RET(0, hmR0VmxExitExtInt(pVCpu, pVmxTransient));
12992	case VMX_EXIT_INT_WINDOW: VMEXIT_CALL_RET(0, hmR0VmxExitIntWindow(pVCpu, pVmxTransient));
12993	case VMX_EXIT_TPR_BELOW_THRESHOLD: VMEXIT_CALL_RET(0, hmR0VmxExitTprBelowThreshold(pVCpu, pVmxTransient));
12994	case VMX_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0VmxExitMwait(pVCpu, pVmxTransient));
12995	case VMX_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0VmxExitMonitor(pVCpu, pVmxTransient));
12996	case VMX_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0VmxExitTaskSwitch(pVCpu, pVmxTransient));
12997	case VMX_EXIT_PREEMPT_TIMER: VMEXIT_CALL_RET(0, hmR0VmxExitPreemptTimer(pVCpu, pVmxTransient));
12998	case VMX_EXIT_RDMSR: VMEXIT_CALL_RET(0, hmR0VmxExitRdmsr(pVCpu, pVmxTransient));
12999	case VMX_EXIT_WRMSR: VMEXIT_CALL_RET(0, hmR0VmxExitWrmsr(pVCpu, pVmxTransient));
13000	case VMX_EXIT_VMCALL: VMEXIT_CALL_RET(0, hmR0VmxExitVmcall(pVCpu, pVmxTransient));
13001	case VMX_EXIT_MOV_DRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovDRx(pVCpu, pVmxTransient));
13002	case VMX_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0VmxExitHlt(pVCpu, pVmxTransient));
13003	case VMX_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0VmxExitInvd(pVCpu, pVmxTransient));
13004	case VMX_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0VmxExitInvlpg(pVCpu, pVmxTransient));
13005	case VMX_EXIT_MTF: VMEXIT_CALL_RET(0, hmR0VmxExitMtf(pVCpu, pVmxTransient));
13006	case VMX_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0VmxExitPause(pVCpu, pVmxTransient));
13007	case VMX_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0VmxExitWbinvd(pVCpu, pVmxTransient));
13008	case VMX_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0VmxExitXsetbv(pVCpu, pVmxTransient));
13009	case VMX_EXIT_INVPCID: VMEXIT_CALL_RET(0, hmR0VmxExitInvpcid(pVCpu, pVmxTransient));
13010	case VMX_EXIT_GETSEC: VMEXIT_CALL_RET(0, hmR0VmxExitGetsec(pVCpu, pVmxTransient));
13011	case VMX_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0VmxExitRdpmc(pVCpu, pVmxTransient));
13012	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
13013	case VMX_EXIT_VMCLEAR: VMEXIT_CALL_RET(0, hmR0VmxExitVmclear(pVCpu, pVmxTransient));
13014	case VMX_EXIT_VMLAUNCH: VMEXIT_CALL_RET(0, hmR0VmxExitVmlaunch(pVCpu, pVmxTransient));
13015	case VMX_EXIT_VMPTRLD: VMEXIT_CALL_RET(0, hmR0VmxExitVmptrld(pVCpu, pVmxTransient));
13016	case VMX_EXIT_VMPTRST: VMEXIT_CALL_RET(0, hmR0VmxExitVmptrst(pVCpu, pVmxTransient));
13017	case VMX_EXIT_VMREAD: VMEXIT_CALL_RET(0, hmR0VmxExitVmread(pVCpu, pVmxTransient));
13018	case VMX_EXIT_VMRESUME: VMEXIT_CALL_RET(0, hmR0VmxExitVmwrite(pVCpu, pVmxTransient));
13019	case VMX_EXIT_VMWRITE: VMEXIT_CALL_RET(0, hmR0VmxExitVmresume(pVCpu, pVmxTransient));
13020	case VMX_EXIT_VMXOFF: VMEXIT_CALL_RET(0, hmR0VmxExitVmxoff(pVCpu, pVmxTransient));
13021	case VMX_EXIT_VMXON: VMEXIT_CALL_RET(0, hmR0VmxExitVmxon(pVCpu, pVmxTransient));
13022	case VMX_EXIT_INVVPID: VMEXIT_CALL_RET(0, hmR0VmxExitInvvpid(pVCpu, pVmxTransient));
13023	case VMX_EXIT_INVEPT: VMEXIT_CALL_RET(0, hmR0VmxExitSetPendingXcptUD(pVCpu, pVmxTransient));
13024	#else
13025	case VMX_EXIT_VMCLEAR:
13026	case VMX_EXIT_VMLAUNCH:
13027	case VMX_EXIT_VMPTRLD:
13028	case VMX_EXIT_VMPTRST:
13029	case VMX_EXIT_VMREAD:
13030	case VMX_EXIT_VMRESUME:
13031	case VMX_EXIT_VMWRITE:
13032	case VMX_EXIT_VMXOFF:
13033	case VMX_EXIT_VMXON:
13034	case VMX_EXIT_INVVPID:
13035	case VMX_EXIT_INVEPT:
13036	return hmR0VmxExitSetPendingXcptUD(pVCpu, pVmxTransient);
13037	#endif
13038
13039	case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFault(pVCpu, pVmxTransient);
13040	case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindow(pVCpu, pVmxTransient);
13041	case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestState(pVCpu, pVmxTransient);
13042
13043	case VMX_EXIT_INIT_SIGNAL:
13044	case VMX_EXIT_SIPI:
13045	case VMX_EXIT_IO_SMI:
13046	case VMX_EXIT_SMI:
13047	case VMX_EXIT_ERR_MSR_LOAD:
13048	case VMX_EXIT_ERR_MACHINE_CHECK:
13049	case VMX_EXIT_PML_FULL:
13050	case VMX_EXIT_VIRTUALIZED_EOI:
13051	case VMX_EXIT_GDTR_IDTR_ACCESS:
13052	case VMX_EXIT_LDTR_TR_ACCESS:
13053	case VMX_EXIT_APIC_WRITE:
13054	case VMX_EXIT_RDRAND:
13055	case VMX_EXIT_RSM:
13056	case VMX_EXIT_VMFUNC:
13057	case VMX_EXIT_ENCLS:
13058	case VMX_EXIT_RDSEED:
13059	case VMX_EXIT_XSAVES:
13060	case VMX_EXIT_XRSTORS:
13061	case VMX_EXIT_UMWAIT:
13062	case VMX_EXIT_TPAUSE:
13063	default:
13064	return hmR0VmxExitErrUnexpected(pVCpu, pVmxTransient);
13065	}
13066	#undef VMEXIT_CALL_RET
13067	}
13068	#endif /* !HMVMX_USE_FUNCTION_TABLE */
13069
13070
13071	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
13072	/**
13073	* Handles a nested-guest VM-exit from hardware-assisted VMX execution.
13074	*
13075	* @returns Strict VBox status code (i.e. informational status codes too).
13076	* @param pVCpu The cross context virtual CPU structure.
13077	* @param pVmxTransient The VMX-transient structure.
13078	*/
13079	DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExitNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
13080	{
13081	uint32_t const uExitReason = pVmxTransient->uExitReason;
13082	switch (uExitReason)
13083	{
13084	case VMX_EXIT_EPT_MISCONFIG: return hmR0VmxExitEptMisconfig(pVCpu, pVmxTransient);
13085	case VMX_EXIT_EPT_VIOLATION: return hmR0VmxExitEptViolation(pVCpu, pVmxTransient);
13086	case VMX_EXIT_XCPT_OR_NMI: return hmR0VmxExitXcptOrNmiNested(pVCpu, pVmxTransient);
13087	case VMX_EXIT_IO_INSTR: return hmR0VmxExitIoInstrNested(pVCpu, pVmxTransient);
13088	case VMX_EXIT_HLT: return hmR0VmxExitHltNested(pVCpu, pVmxTransient);
13089
13090	/*
13091	* We shouldn't direct host physical interrupts to the nested-guest.
13092	*/
13093	case VMX_EXIT_EXT_INT:
13094	return hmR0VmxExitExtInt(pVCpu, pVmxTransient);
13095
13096	/*
13097	* Instructions that cause VM-exits unconditionally or the condition is
13098	* always is taken solely from the nested hypervisor (meaning if the VM-exit
13099	* happens, it's guaranteed to be a nested-guest VM-exit).
13100	*
13101	* - Provides VM-exit instruction length ONLY.
13102	*/
13103	case VMX_EXIT_CPUID: /* Unconditional. */
13104	case VMX_EXIT_VMCALL:
13105	case VMX_EXIT_GETSEC:
13106	case VMX_EXIT_INVD:
13107	case VMX_EXIT_XSETBV:
13108	case VMX_EXIT_VMLAUNCH:
13109	case VMX_EXIT_VMRESUME:
13110	case VMX_EXIT_VMXOFF:
13111	case VMX_EXIT_ENCLS: /* Condition specified solely by nested hypervisor. */
13112	case VMX_EXIT_VMFUNC:
13113	return hmR0VmxExitInstrNested(pVCpu, pVmxTransient);
13114
13115	/*
13116	* Instructions that cause VM-exits unconditionally or the condition is
13117	* always is taken solely from the nested hypervisor (meaning if the VM-exit
13118	* happens, it's guaranteed to be a nested-guest VM-exit).
13119	*
13120	* - Provides VM-exit instruction length.
13121	* - Provides VM-exit information.
13122	* - Optionally provides Exit qualification.
13123	*
13124	* Since Exit qualification is 0 for all VM-exits where it is not
13125	* applicable, reading and passing it to the guest should produce
13126	* defined behavior.
13127	*
13128	* See Intel spec. 27.2.1 "Basic VM-Exit Information".
13129	*/
13130	case VMX_EXIT_INVEPT: /* Unconditional. */
13131	case VMX_EXIT_INVVPID:
13132	case VMX_EXIT_VMCLEAR:
13133	case VMX_EXIT_VMPTRLD:
13134	case VMX_EXIT_VMPTRST:
13135	case VMX_EXIT_VMXON:
13136	case VMX_EXIT_GDTR_IDTR_ACCESS: /* Condition specified solely by nested hypervisor. */
13137	case VMX_EXIT_LDTR_TR_ACCESS:
13138	case VMX_EXIT_RDRAND:
13139	case VMX_EXIT_RDSEED:
13140	case VMX_EXIT_XSAVES:
13141	case VMX_EXIT_XRSTORS:
13142	case VMX_EXIT_UMWAIT:
13143	case VMX_EXIT_TPAUSE:
13144	return hmR0VmxExitInstrWithInfoNested(pVCpu, pVmxTransient);
13145
13146	case VMX_EXIT_RDTSC: return hmR0VmxExitRdtscNested(pVCpu, pVmxTransient);
13147	case VMX_EXIT_RDTSCP: return hmR0VmxExitRdtscpNested(pVCpu, pVmxTransient);
13148	case VMX_EXIT_RDMSR: return hmR0VmxExitRdmsrNested(pVCpu, pVmxTransient);
13149	case VMX_EXIT_WRMSR: return hmR0VmxExitWrmsrNested(pVCpu, pVmxTransient);
13150	case VMX_EXIT_INVLPG: return hmR0VmxExitInvlpgNested(pVCpu, pVmxTransient);
13151	case VMX_EXIT_INVPCID: return hmR0VmxExitInvpcidNested(pVCpu, pVmxTransient);
13152	case VMX_EXIT_TASK_SWITCH: return hmR0VmxExitTaskSwitchNested(pVCpu, pVmxTransient);
13153	case VMX_EXIT_WBINVD: return hmR0VmxExitWbinvdNested(pVCpu, pVmxTransient);
13154	case VMX_EXIT_MTF: return hmR0VmxExitMtfNested(pVCpu, pVmxTransient);
13155	case VMX_EXIT_APIC_ACCESS: return hmR0VmxExitApicAccessNested(pVCpu, pVmxTransient);
13156	case VMX_EXIT_APIC_WRITE: return hmR0VmxExitApicWriteNested(pVCpu, pVmxTransient);
13157	case VMX_EXIT_VIRTUALIZED_EOI: return hmR0VmxExitVirtEoiNested(pVCpu, pVmxTransient);
13158	case VMX_EXIT_MOV_CRX: return hmR0VmxExitMovCRxNested(pVCpu, pVmxTransient);
13159	case VMX_EXIT_INT_WINDOW: return hmR0VmxExitIntWindowNested(pVCpu, pVmxTransient);
13160	case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindowNested(pVCpu, pVmxTransient);
13161	case VMX_EXIT_TPR_BELOW_THRESHOLD: return hmR0VmxExitTprBelowThresholdNested(pVCpu, pVmxTransient);
13162	case VMX_EXIT_MWAIT: return hmR0VmxExitMwaitNested(pVCpu, pVmxTransient);
13163	case VMX_EXIT_MONITOR: return hmR0VmxExitMonitorNested(pVCpu, pVmxTransient);
13164	case VMX_EXIT_PAUSE: return hmR0VmxExitPauseNested(pVCpu, pVmxTransient);
13165
13166	case VMX_EXIT_PREEMPT_TIMER:
13167	{
13168	/** @todo NSTVMX: Preempt timer. */
13169	return hmR0VmxExitPreemptTimer(pVCpu, pVmxTransient);
13170	}
13171
13172	case VMX_EXIT_MOV_DRX: return hmR0VmxExitMovDRxNested(pVCpu, pVmxTransient);
13173	case VMX_EXIT_RDPMC: return hmR0VmxExitRdpmcNested(pVCpu, pVmxTransient);
13174
13175	case VMX_EXIT_VMREAD:
13176	case VMX_EXIT_VMWRITE: return hmR0VmxExitVmreadVmwriteNested(pVCpu, pVmxTransient);
13177
13178	case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFaultNested(pVCpu, pVmxTransient);
13179	case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestStateNested(pVCpu, pVmxTransient);
13180
13181	case VMX_EXIT_INIT_SIGNAL:
13182	case VMX_EXIT_SIPI:
13183	case VMX_EXIT_IO_SMI:
13184	case VMX_EXIT_SMI:
13185	case VMX_EXIT_ERR_MSR_LOAD:
13186	case VMX_EXIT_ERR_MACHINE_CHECK:
13187	case VMX_EXIT_PML_FULL:
13188	case VMX_EXIT_RSM:
13189	default:
13190	return hmR0VmxExitErrUnexpected(pVCpu, pVmxTransient);
13191	}
13192	}
13193	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
13194
13195
13196	/** @name VM-exit helpers.
13197	* @{
13198	*/
13199	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13200	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= VM-exit helpers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
13201	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13202
13203	/** Macro for VM-exits called unexpectedly. */
13204	#define HMVMX_UNEXPECTED_EXIT_RET(a_pVCpu, a_HmError) \
13205	do { \
13206	(a_pVCpu)->hm.s.u32HMError = (a_HmError); \
13207	return VERR_VMX_UNEXPECTED_EXIT; \
13208	} while (0)
13209
13210	#ifdef VBOX_STRICT
13211	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
13212	# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
13213	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
13214
13215	# define HMVMX_ASSERT_PREEMPT_CPUID() \
13216	do { \
13217	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
13218	AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
13219	} while (0)
13220
13221	# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
13222	do { \
13223	AssertPtr((a_pVCpu)); \
13224	AssertPtr((a_pVmxTransient)); \
13225	Assert((a_pVmxTransient)->fVMEntryFailed == false); \
13226	Assert((a_pVmxTransient)->pVmcsInfo); \
13227	Assert(ASMIntAreEnabled()); \
13228	HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
13229	HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
13230	Log4Func(("vcpu[%RU32]\n", (a_pVCpu)->idCpu)); \
13231	HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
13232	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
13233	HMVMX_ASSERT_PREEMPT_CPUID(); \
13234	HMVMX_STOP_EXIT_DISPATCH_PROF(); \
13235	} while (0)
13236
13237	# define HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
13238	do { \
13239	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient); \
13240	Assert((a_pVmxTransient)->fIsNestedGuest); \
13241	} while (0)
13242
13243	# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
13244	do { \
13245	Log4Func(("\n")); \
13246	} while (0)
13247	#else
13248	# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
13249	do { \
13250	HMVMX_STOP_EXIT_DISPATCH_PROF(); \
13251	NOREF((a_pVCpu)); NOREF((a_pVmxTransient)); \
13252	} while (0)
13253
13254	# define HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
13255	do { HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient); } while (0)
13256
13257	# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) do { } while (0)
13258	#endif
13259
13260	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
13261	/** Macro that does the necessary privilege checks and intercepted VM-exits for
13262	* guests that attempted to execute a VMX instruction. */
13263	# define HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(a_pVCpu, a_uExitReason) \
13264	do \
13265	{ \
13266	VBOXSTRICTRC rcStrictTmp = hmR0VmxCheckExitDueToVmxInstr((a_pVCpu), (a_uExitReason)); \
13267	if (rcStrictTmp == VINF_SUCCESS) \
13268	{ /* likely */ } \
13269	else if (rcStrictTmp == VINF_HM_PENDING_XCPT) \
13270	{ \
13271	Assert((a_pVCpu)->hm.s.Event.fPending); \
13272	Log4Func(("Privilege checks failed -> %#x\n", VMX_ENTRY_INT_INFO_VECTOR((a_pVCpu)->hm.s.Event.u64IntInfo))); \
13273	return VINF_SUCCESS; \
13274	} \
13275	else \
13276	{ \
13277	int rcTmp = VBOXSTRICTRC_VAL(rcStrictTmp); \
13278	AssertMsgFailedReturn(("Unexpected failure. rc=%Rrc", rcTmp), rcTmp); \
13279	} \
13280	} while (0)
13281
13282	/** Macro that decodes a memory operand for an VM-exit caused by an instruction. */
13283	# define HMVMX_DECODE_MEM_OPERAND(a_pVCpu, a_uExitInstrInfo, a_uExitQual, a_enmMemAccess, a_pGCPtrEffAddr) \
13284	do \
13285	{ \
13286	VBOXSTRICTRC rcStrictTmp = hmR0VmxDecodeMemOperand((a_pVCpu), (a_uExitInstrInfo), (a_uExitQual), (a_enmMemAccess), \
13287	(a_pGCPtrEffAddr)); \
13288	if (rcStrictTmp == VINF_SUCCESS) \
13289	{ /* likely */ } \
13290	else if (rcStrictTmp == VINF_HM_PENDING_XCPT) \
13291	{ \
13292	uint8_t const uXcptTmp = VMX_ENTRY_INT_INFO_VECTOR((a_pVCpu)->hm.s.Event.u64IntInfo); \
13293	Log4Func(("Memory operand decoding failed, raising xcpt %#x\n", uXcptTmp)); \
13294	NOREF(uXcptTmp); \
13295	return VINF_SUCCESS; \
13296	} \
13297	else \
13298	{ \
13299	Log4Func(("hmR0VmxDecodeMemOperand failed. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrictTmp))); \
13300	return rcStrictTmp; \
13301	} \
13302	} while (0)
13303	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
13304
13305
13306	/**
13307	* Advances the guest RIP by the specified number of bytes.
13308	*
13309	* @param pVCpu The cross context virtual CPU structure.
13310	* @param cbInstr Number of bytes to advance the RIP by.
13311	*
13312	* @remarks No-long-jump zone!!!
13313	*/
13314	DECLINLINE(void) hmR0VmxAdvanceGuestRipBy(PVMCPUCC pVCpu, uint32_t cbInstr)
13315	{
13316	/* Advance the RIP. */
13317	pVCpu->cpum.GstCtx.rip += cbInstr;
13318	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
13319
13320	/* Update interrupt inhibition. */
13321	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
13322	&& pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
13323	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
13324	}
13325
13326
13327	/**
13328	* Advances the guest RIP after reading it from the VMCS.
13329	*
13330	* @returns VBox status code, no informational status codes.
13331	* @param pVCpu The cross context virtual CPU structure.
13332	* @param pVmxTransient The VMX-transient structure.
13333	*
13334	* @remarks No-long-jump zone!!!
13335	*/
13336	static int hmR0VmxAdvanceGuestRip(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
13337	{
13338	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13339	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
13340	AssertRCReturn(rc, rc);
13341
13342	hmR0VmxAdvanceGuestRipBy(pVCpu, pVmxTransient->cbExitInstr);
13343	return VINF_SUCCESS;
13344	}
13345
13346
13347	/**
13348	* Handle a condition that occurred while delivering an event through the guest or
13349	* nested-guest IDT.
13350	*
13351	* @returns Strict VBox status code (i.e. informational status codes too).
13352	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
13353	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought
13354	* to continue execution of the guest which will delivery the \#DF.
13355	* @retval VINF_EM_RESET if we detected a triple-fault condition.
13356	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
13357	*
13358	* @param pVCpu The cross context virtual CPU structure.
13359	* @param pVmxTransient The VMX-transient structure.
13360	*
13361	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
13362	* Additionally, HMVMX_READ_EXIT_QUALIFICATION is required if the VM-exit
13363	* is due to an EPT violation, PML full or SPP-related event.
13364	*
13365	* @remarks No-long-jump zone!!!
13366	*/
13367	static VBOXSTRICTRC hmR0VmxCheckExitDueToEventDelivery(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
13368	{
13369	Assert(!pVCpu->hm.s.Event.fPending);
13370	HMVMX_ASSERT_READ(pVmxTransient, HMVMX_READ_XCPT_INFO);
13371	if ( pVmxTransient->uExitReason == VMX_EXIT_EPT_VIOLATION
13372	\|\| pVmxTransient->uExitReason == VMX_EXIT_PML_FULL
13373	\|\| pVmxTransient->uExitReason == VMX_EXIT_SPP_EVENT)
13374	HMVMX_ASSERT_READ(pVmxTransient, HMVMX_READ_EXIT_QUALIFICATION);
13375
13376	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
13377	PCVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
13378	uint32_t const uIdtVectorInfo = pVmxTransient->uIdtVectoringInfo;
13379	uint32_t const uExitIntInfo = pVmxTransient->uExitIntInfo;
13380	if (VMX_IDT_VECTORING_INFO_IS_VALID(uIdtVectorInfo))
13381	{
13382	uint32_t const uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(uIdtVectorInfo);
13383	uint32_t const uIdtVectorType = VMX_IDT_VECTORING_INFO_TYPE(uIdtVectorInfo);
13384
13385	/*
13386	* If the event was a software interrupt (generated with INT n) or a software exception
13387	* (generated by INT3/INTO) or a privileged software exception (generated by INT1), we
13388	* can handle the VM-exit and continue guest execution which will re-execute the
13389	* instruction rather than re-injecting the exception, as that can cause premature
13390	* trips to ring-3 before injection and involve TRPM which currently has no way of
13391	* storing that these exceptions were caused by these instructions (ICEBP's #DB poses
13392	* the problem).
13393	*/
13394	IEMXCPTRAISE enmRaise;
13395	IEMXCPTRAISEINFO fRaiseInfo;
13396	if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
13397	\|\| uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
13398	\|\| uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
13399	{
13400	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
13401	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
13402	}
13403	else if (VMX_EXIT_INT_INFO_IS_VALID(uExitIntInfo))
13404	{
13405	uint32_t const uExitVectorType = VMX_EXIT_INT_INFO_TYPE(uExitIntInfo);
13406	uint8_t const uExitVector = VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo);
13407	Assert(uExitVectorType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT);
13408
13409	uint32_t const fIdtVectorFlags = hmR0VmxGetIemXcptFlags(uIdtVector, uIdtVectorType);
13410	uint32_t const fExitVectorFlags = hmR0VmxGetIemXcptFlags(uExitVector, uExitVectorType);
13411
13412	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
13413
13414	/* Determine a vectoring #PF condition, see comment in hmR0VmxExitXcptPF(). */
13415	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
13416	{
13417	pVmxTransient->fVectoringPF = true;
13418	enmRaise = IEMXCPTRAISE_PREV_EVENT;
13419	}
13420	}
13421	else
13422	{
13423	/*
13424	* If an exception or hardware interrupt delivery caused an EPT violation/misconfig or APIC access
13425	* VM-exit, then the VM-exit interruption-information will not be valid and we end up here.
13426	* It is sufficient to reflect the original event to the guest after handling the VM-exit.
13427	*/
13428	Assert( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
13429	\|\| uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
13430	\|\| uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
13431	enmRaise = IEMXCPTRAISE_PREV_EVENT;
13432	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
13433	}
13434
13435	/*
13436	* On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig
13437	* etc.) occurred while delivering the NMI, we need to clear the block-by-NMI field in the guest
13438	* interruptibility-state before re-delivering the NMI after handling the VM-exit. Otherwise the
13439	* subsequent VM-entry would fail, see @bugref{7445}.
13440	*
13441	* See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception".
13442	*/
13443	if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
13444	&& enmRaise == IEMXCPTRAISE_PREV_EVENT
13445	&& (pVmcsInfo->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
13446	&& CPUMIsGuestNmiBlocking(pVCpu))
13447	{
13448	CPUMSetGuestNmiBlocking(pVCpu, false);
13449	}
13450
13451	switch (enmRaise)
13452	{
13453	case IEMXCPTRAISE_CURRENT_XCPT:
13454	{
13455	Log4Func(("IDT: Pending secondary Xcpt: idtinfo=%#RX64 exitinfo=%#RX64\n", uIdtVectorInfo, uExitIntInfo));
13456	Assert(rcStrict == VINF_SUCCESS);
13457	break;
13458	}
13459
13460	case IEMXCPTRAISE_PREV_EVENT:
13461	{
13462	uint32_t u32ErrCode;
13463	if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(uIdtVectorInfo))
13464	u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
13465	else
13466	u32ErrCode = 0;
13467
13468	/* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF, see hmR0VmxExitXcptPF(). */
13469	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflect);
13470	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(uIdtVectorInfo), 0 /* cbInstr */,
13471	u32ErrCode, pVCpu->cpum.GstCtx.cr2);
13472
13473	Log4Func(("IDT: Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->hm.s.Event.u64IntInfo,
13474	pVCpu->hm.s.Event.u32ErrCode));
13475	Assert(rcStrict == VINF_SUCCESS);
13476	break;
13477	}
13478
13479	case IEMXCPTRAISE_REEXEC_INSTR:
13480	Assert(rcStrict == VINF_SUCCESS);
13481	break;
13482
13483	case IEMXCPTRAISE_DOUBLE_FAULT:
13484	{
13485	/*
13486	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
13487	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
13488	*/
13489	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
13490	{
13491	pVmxTransient->fVectoringDoublePF = true;
13492	Log4Func(("IDT: Vectoring double #PF %#RX64 cr2=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo,
13493	pVCpu->cpum.GstCtx.cr2));
13494	rcStrict = VINF_SUCCESS;
13495	}
13496	else
13497	{
13498	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectConvertDF);
13499	hmR0VmxSetPendingXcptDF(pVCpu);
13500	Log4Func(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
13501	uIdtVector, VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo)));
13502	rcStrict = VINF_HM_DOUBLE_FAULT;
13503	}
13504	break;
13505	}
13506
13507	case IEMXCPTRAISE_TRIPLE_FAULT:
13508	{
13509	Log4Func(("IDT: Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", uIdtVector,
13510	VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo)));
13511	rcStrict = VINF_EM_RESET;
13512	break;
13513	}
13514
13515	case IEMXCPTRAISE_CPU_HANG:
13516	{
13517	Log4Func(("IDT: Bad guest! Entering CPU hang. fRaiseInfo=%#x\n", fRaiseInfo));
13518	rcStrict = VERR_EM_GUEST_CPU_HANG;
13519	break;
13520	}
13521
13522	default:
13523	{
13524	AssertMsgFailed(("IDT: vcpu[%RU32] Unexpected/invalid value! enmRaise=%#x\n", pVCpu->idCpu, enmRaise));
13525	rcStrict = VERR_VMX_IPE_2;
13526	break;
13527	}
13528	}
13529	}
13530	else if ( (pVmcsInfo->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
13531	&& !CPUMIsGuestNmiBlocking(pVCpu))
13532	{
13533	if ( VMX_EXIT_INT_INFO_IS_VALID(uExitIntInfo)
13534	&& VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo) != X86_XCPT_DF
13535	&& VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(uExitIntInfo))
13536	{
13537	/*
13538	* Execution of IRET caused a fault when NMI blocking was in effect (i.e we're in
13539	* the guest or nested-guest NMI handler). We need to set the block-by-NMI field so
13540	* that virtual NMIs remain blocked until the IRET execution is completed.
13541	*
13542	* See Intel spec. 31.7.1.2 "Resuming Guest Software After Handling An Exception".
13543	*/
13544	CPUMSetGuestNmiBlocking(pVCpu, true);
13545	Log4Func(("Set NMI blocking. uExitReason=%u\n", pVmxTransient->uExitReason));
13546	}
13547	else if ( pVmxTransient->uExitReason == VMX_EXIT_EPT_VIOLATION
13548	\|\| pVmxTransient->uExitReason == VMX_EXIT_PML_FULL
13549	\|\| pVmxTransient->uExitReason == VMX_EXIT_SPP_EVENT)
13550	{
13551	/*
13552	* Execution of IRET caused an EPT violation, page-modification log-full event or
13553	* SPP-related event VM-exit when NMI blocking was in effect (i.e. we're in the
13554	* guest or nested-guest NMI handler). We need to set the block-by-NMI field so
13555	* that virtual NMIs remain blocked until the IRET execution is completed.
13556	*
13557	* See Intel spec. 27.2.3 "Information about NMI unblocking due to IRET"
13558	*/
13559	if (VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(pVmxTransient->uExitQual))
13560	{
13561	CPUMSetGuestNmiBlocking(pVCpu, true);
13562	Log4Func(("Set NMI blocking. uExitReason=%u\n", pVmxTransient->uExitReason));
13563	}
13564	}
13565	}
13566
13567	Assert( rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_HM_DOUBLE_FAULT
13568	\|\| rcStrict == VINF_EM_RESET \|\| rcStrict == VERR_EM_GUEST_CPU_HANG);
13569	return rcStrict;
13570	}
13571
13572
13573	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
13574	/**
13575	* Perform the relevant VMX instruction checks for VM-exits that occurred due to the
13576	* guest attempting to execute a VMX instruction.
13577	*
13578	* @returns Strict VBox status code (i.e. informational status codes too).
13579	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
13580	* @retval VINF_HM_PENDING_XCPT if an exception was raised.
13581	*
13582	* @param pVCpu The cross context virtual CPU structure.
13583	* @param uExitReason The VM-exit reason.
13584	*
13585	* @todo NSTVMX: Document other error codes when VM-exit is implemented.
13586	* @remarks No-long-jump zone!!!
13587	*/
13588	static VBOXSTRICTRC hmR0VmxCheckExitDueToVmxInstr(PVMCPUCC pVCpu, uint32_t uExitReason)
13589	{
13590	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_SS
13591	\| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_EFER);
13592
13593	/*
13594	* The physical CPU would have already checked the CPU mode/code segment.
13595	* We shall just assert here for paranoia.
13596	* See Intel spec. 25.1.1 "Relative Priority of Faults and VM Exits".
13597	*/
13598	Assert(!CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx));
13599	Assert( !CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
13600	\|\| CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx));
13601
13602	if (uExitReason == VMX_EXIT_VMXON)
13603	{
13604	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
13605
13606	/*
13607	* We check CR4.VMXE because it is required to be always set while in VMX operation
13608	* by physical CPUs and our CR4 read-shadow is only consulted when executing specific
13609	* instructions (CLTS, LMSW, MOV CR, and SMSW) and thus doesn't affect CPU operation
13610	* otherwise (i.e. physical CPU won't automatically #UD if Cr4Shadow.VMXE is 0).
13611	*/
13612	if (!CPUMIsGuestVmxEnabled(&pVCpu->cpum.GstCtx))
13613	{
13614	Log4Func(("CR4.VMXE is not set -> #UD\n"));
13615	hmR0VmxSetPendingXcptUD(pVCpu);
13616	return VINF_HM_PENDING_XCPT;
13617	}
13618	}
13619	else if (!CPUMIsGuestInVmxRootMode(&pVCpu->cpum.GstCtx))
13620	{
13621	/*
13622	* The guest has not entered VMX operation but attempted to execute a VMX instruction
13623	* (other than VMXON), we need to raise a #UD.
13624	*/
13625	Log4Func(("Not in VMX root mode -> #UD\n"));
13626	hmR0VmxSetPendingXcptUD(pVCpu);
13627	return VINF_HM_PENDING_XCPT;
13628	}
13629
13630	/* All other checks (including VM-exit intercepts) are handled by IEM instruction emulation. */
13631	return VINF_SUCCESS;
13632	}
13633
13634
13635	/**
13636	* Decodes the memory operand of an instruction that caused a VM-exit.
13637	*
13638	* The Exit qualification field provides the displacement field for memory
13639	* operand instructions, if any.
13640	*
13641	* @returns Strict VBox status code (i.e. informational status codes too).
13642	* @retval VINF_SUCCESS if the operand was successfully decoded.
13643	* @retval VINF_HM_PENDING_XCPT if an exception was raised while decoding the
13644	* operand.
13645	* @param pVCpu The cross context virtual CPU structure.
13646	* @param uExitInstrInfo The VM-exit instruction information field.
13647	* @param enmMemAccess The memory operand's access type (read or write).
13648	* @param GCPtrDisp The instruction displacement field, if any. For
13649	* RIP-relative addressing pass RIP + displacement here.
13650	* @param pGCPtrMem Where to store the effective destination memory address.
13651	*
13652	* @remarks Warning! This function ASSUMES the instruction cannot be used in real or
13653	* virtual-8086 mode hence skips those checks while verifying if the
13654	* segment is valid.
13655	*/
13656	static VBOXSTRICTRC hmR0VmxDecodeMemOperand(PVMCPUCC pVCpu, uint32_t uExitInstrInfo, RTGCPTR GCPtrDisp, VMXMEMACCESS enmMemAccess,
13657	PRTGCPTR pGCPtrMem)
13658	{
13659	Assert(pGCPtrMem);
13660	Assert(!CPUMIsGuestInRealOrV86Mode(pVCpu));
13661	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_EFER
13662	\| CPUMCTX_EXTRN_CR0);
13663
13664	static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
13665	static uint64_t const s_auAccessSizeMasks[] = { sizeof(uint16_t), sizeof(uint32_t), sizeof(uint64_t) };
13666	AssertCompile(RT_ELEMENTS(s_auAccessSizeMasks) == RT_ELEMENTS(s_auAddrSizeMasks));
13667
13668	VMXEXITINSTRINFO ExitInstrInfo;
13669	ExitInstrInfo.u = uExitInstrInfo;
13670	uint8_t const uAddrSize = ExitInstrInfo.All.u3AddrSize;
13671	uint8_t const iSegReg = ExitInstrInfo.All.iSegReg;
13672	bool const fIdxRegValid = !ExitInstrInfo.All.fIdxRegInvalid;
13673	uint8_t const iIdxReg = ExitInstrInfo.All.iIdxReg;
13674	uint8_t const uScale = ExitInstrInfo.All.u2Scaling;
13675	bool const fBaseRegValid = !ExitInstrInfo.All.fBaseRegInvalid;
13676	uint8_t const iBaseReg = ExitInstrInfo.All.iBaseReg;
13677	bool const fIsMemOperand = !ExitInstrInfo.All.fIsRegOperand;
13678	bool const fIsLongMode = CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx);
13679
13680	/*
13681	* Validate instruction information.
13682	* This shouldn't happen on real hardware but useful while testing our nested hardware-virtualization code.
13683	*/
13684	AssertLogRelMsgReturn(uAddrSize < RT_ELEMENTS(s_auAddrSizeMasks),
13685	("Invalid address size. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_1);
13686	AssertLogRelMsgReturn(iSegReg < X86_SREG_COUNT,
13687	("Invalid segment register. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_2);
13688	AssertLogRelMsgReturn(fIsMemOperand,
13689	("Expected memory operand. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_3);
13690
13691	/*
13692	* Compute the complete effective address.
13693	*
13694	* See AMD instruction spec. 1.4.2 "SIB Byte Format"
13695	* See AMD spec. 4.5.2 "Segment Registers".
13696	*/
13697	RTGCPTR GCPtrMem = GCPtrDisp;
13698	if (fBaseRegValid)
13699	GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iBaseReg].u64;
13700	if (fIdxRegValid)
13701	GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iIdxReg].u64 << uScale;
13702
13703	RTGCPTR const GCPtrOff = GCPtrMem;
13704	if ( !fIsLongMode
13705	\|\| iSegReg >= X86_SREG_FS)
13706	GCPtrMem += pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
13707	GCPtrMem &= s_auAddrSizeMasks[uAddrSize];
13708
13709	/*
13710	* Validate effective address.
13711	* See AMD spec. 4.5.3 "Segment Registers in 64-Bit Mode".
13712	*/
13713	uint8_t const cbAccess = s_auAccessSizeMasks[uAddrSize];
13714	Assert(cbAccess > 0);
13715	if (fIsLongMode)
13716	{
13717	if (X86_IS_CANONICAL(GCPtrMem))
13718	{
13719	*pGCPtrMem = GCPtrMem;
13720	return VINF_SUCCESS;
13721	}
13722
13723	/** @todo r=ramshankar: We should probably raise \#SS or \#GP. See AMD spec. 4.12.2
13724	* "Data Limit Checks in 64-bit Mode". */
13725	Log4Func(("Long mode effective address is not canonical GCPtrMem=%#RX64\n", GCPtrMem));
13726	hmR0VmxSetPendingXcptGP(pVCpu, 0);
13727	return VINF_HM_PENDING_XCPT;
13728	}
13729
13730	/*
13731	* This is a watered down version of iemMemApplySegment().
13732	* Parts that are not applicable for VMX instructions like real-or-v8086 mode
13733	* and segment CPL/DPL checks are skipped.
13734	*/
13735	RTGCPTR32 const GCPtrFirst32 = (RTGCPTR32)GCPtrOff;
13736	RTGCPTR32 const GCPtrLast32 = GCPtrFirst32 + cbAccess - 1;
13737	PCCPUMSELREG pSel = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
13738
13739	/* Check if the segment is present and usable. */
13740	if ( pSel->Attr.n.u1Present
13741	&& !pSel->Attr.n.u1Unusable)
13742	{
13743	Assert(pSel->Attr.n.u1DescType);
13744	if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_CODE))
13745	{
13746	/* Check permissions for the data segment. */
13747	if ( enmMemAccess == VMXMEMACCESS_WRITE
13748	&& !(pSel->Attr.n.u4Type & X86_SEL_TYPE_WRITE))
13749	{
13750	Log4Func(("Data segment access invalid. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
13751	hmR0VmxSetPendingXcptGP(pVCpu, iSegReg);
13752	return VINF_HM_PENDING_XCPT;
13753	}
13754
13755	/* Check limits if it's a normal data segment. */
13756	if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_DOWN))
13757	{
13758	if ( GCPtrFirst32 > pSel->u32Limit
13759	\|\| GCPtrLast32 > pSel->u32Limit)
13760	{
13761	Log4Func(("Data segment limit exceeded. "
13762	"iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
13763	GCPtrLast32, pSel->u32Limit));
13764	if (iSegReg == X86_SREG_SS)
13765	hmR0VmxSetPendingXcptSS(pVCpu, 0);
13766	else
13767	hmR0VmxSetPendingXcptGP(pVCpu, 0);
13768	return VINF_HM_PENDING_XCPT;
13769	}
13770	}
13771	else
13772	{
13773	/* Check limits if it's an expand-down data segment.
13774	Note! The upper boundary is defined by the B bit, not the G bit! */
13775	if ( GCPtrFirst32 < pSel->u32Limit + UINT32_C(1)
13776	\|\| GCPtrLast32 > (pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT32_C(0xffff)))
13777	{
13778	Log4Func(("Expand-down data segment limit exceeded. "
13779	"iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
13780	GCPtrLast32, pSel->u32Limit));
13781	if (iSegReg == X86_SREG_SS)
13782	hmR0VmxSetPendingXcptSS(pVCpu, 0);
13783	else
13784	hmR0VmxSetPendingXcptGP(pVCpu, 0);
13785	return VINF_HM_PENDING_XCPT;
13786	}
13787	}
13788	}
13789	else
13790	{
13791	/* Check permissions for the code segment. */
13792	if ( enmMemAccess == VMXMEMACCESS_WRITE
13793	\|\| ( enmMemAccess == VMXMEMACCESS_READ
13794	&& !(pSel->Attr.n.u4Type & X86_SEL_TYPE_READ)))
13795	{
13796	Log4Func(("Code segment access invalid. Attr=%#RX32\n", pSel->Attr.u));
13797	Assert(!CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx));
13798	hmR0VmxSetPendingXcptGP(pVCpu, 0);
13799	return VINF_HM_PENDING_XCPT;
13800	}
13801
13802	/* Check limits for the code segment (normal/expand-down not applicable for code segments). */
13803	if ( GCPtrFirst32 > pSel->u32Limit
13804	\|\| GCPtrLast32 > pSel->u32Limit)
13805	{
13806	Log4Func(("Code segment limit exceeded. GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n",
13807	GCPtrFirst32, GCPtrLast32, pSel->u32Limit));
13808	if (iSegReg == X86_SREG_SS)
13809	hmR0VmxSetPendingXcptSS(pVCpu, 0);
13810	else
13811	hmR0VmxSetPendingXcptGP(pVCpu, 0);
13812	return VINF_HM_PENDING_XCPT;
13813	}
13814	}
13815	}
13816	else
13817	{
13818	Log4Func(("Not present or unusable segment. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
13819	hmR0VmxSetPendingXcptGP(pVCpu, 0);
13820	return VINF_HM_PENDING_XCPT;
13821	}
13822
13823	*pGCPtrMem = GCPtrMem;
13824	return VINF_SUCCESS;
13825	}
13826	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
13827
13828
13829	/**
13830	* VM-exit helper for LMSW.
13831	*/
13832	static VBOXSTRICTRC hmR0VmxExitLmsw(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint8_t cbInstr, uint16_t uMsw, RTGCPTR GCPtrEffDst)
13833	{
13834	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
13835	AssertRCReturn(rc, rc);
13836
13837	VBOXSTRICTRC rcStrict = IEMExecDecodedLmsw(pVCpu, cbInstr, uMsw, GCPtrEffDst);
13838	AssertMsg( rcStrict == VINF_SUCCESS
13839	\|\| rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13840
13841	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_CR0);
13842	if (rcStrict == VINF_IEM_RAISED_XCPT)
13843	{
13844	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13845	rcStrict = VINF_SUCCESS;
13846	}
13847
13848	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
13849	Log4Func(("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13850	return rcStrict;
13851	}
13852
13853
13854	/**
13855	* VM-exit helper for CLTS.
13856	*/
13857	static VBOXSTRICTRC hmR0VmxExitClts(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint8_t cbInstr)
13858	{
13859	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
13860	AssertRCReturn(rc, rc);
13861
13862	VBOXSTRICTRC rcStrict = IEMExecDecodedClts(pVCpu, cbInstr);
13863	AssertMsg( rcStrict == VINF_SUCCESS
13864	\|\| rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13865
13866	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_CR0);
13867	if (rcStrict == VINF_IEM_RAISED_XCPT)
13868	{
13869	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13870	rcStrict = VINF_SUCCESS;
13871	}
13872
13873	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
13874	Log4Func(("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13875	return rcStrict;
13876	}
13877
13878
13879	/**
13880	* VM-exit helper for MOV from CRx (CRx read).
13881	*/
13882	static VBOXSTRICTRC hmR0VmxExitMovFromCrX(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg)
13883	{
13884	Assert(iCrReg < 16);
13885	Assert(iGReg < RT_ELEMENTS(pVCpu->cpum.GstCtx.aGRegs));
13886
13887	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
13888	AssertRCReturn(rc, rc);
13889
13890	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
13891	AssertMsg( rcStrict == VINF_SUCCESS
13892	\|\| rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13893
13894	if (iGReg == X86_GREG_xSP)
13895	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_RSP);
13896	else
13897	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
13898	#ifdef VBOX_WITH_STATISTICS
13899	switch (iCrReg)
13900	{
13901	case 0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
13902	case 2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
13903	case 3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
13904	case 4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
13905	case 8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
13906	}
13907	#endif
13908	Log4Func(("CR%d Read access rcStrict=%Rrc\n", iCrReg, VBOXSTRICTRC_VAL(rcStrict)));
13909	return rcStrict;
13910	}
13911
13912
13913	/**
13914	* VM-exit helper for MOV to CRx (CRx write).
13915	*/
13916	static VBOXSTRICTRC hmR0VmxExitMovToCrX(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg)
13917	{
13918	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
13919	AssertRCReturn(rc, rc);
13920
13921	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
13922	AssertMsg( rcStrict == VINF_SUCCESS
13923	\|\| rcStrict == VINF_IEM_RAISED_XCPT
13924	\|\| rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
13925
13926	switch (iCrReg)
13927	{
13928	case 0:
13929	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_CR0
13930	\| HM_CHANGED_GUEST_EFER_MSR \| HM_CHANGED_VMX_ENTRY_EXIT_CTLS);
13931	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
13932	Log4Func(("CR0 write. rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr0));
13933	break;
13934
13935	case 2:
13936	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
13937	/* Nothing to do here, CR2 it's not part of the VMCS. */
13938	break;
13939
13940	case 3:
13941	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_CR3);
13942	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
13943	Log4Func(("CR3 write. rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr3));
13944	break;
13945
13946	case 4:
13947	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_CR4);
13948	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
13949	Log4Func(("CR4 write. rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n", VBOXSTRICTRC_VAL(rcStrict),
13950	pVCpu->cpum.GstCtx.cr4, pVCpu->hmr0.s.fLoadSaveGuestXcr0));
13951	break;
13952
13953	case 8:
13954	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
13955	HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_APIC_TPR);
13956	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
13957	break;
13958
13959	default:
13960	AssertMsgFailed(("Invalid CRx register %#x\n", iCrReg));
13961	break;
13962	}
13963
13964	if (rcStrict == VINF_IEM_RAISED_XCPT)
13965	{
13966	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13967	rcStrict = VINF_SUCCESS;
13968	}
13969	return rcStrict;
13970	}
13971
13972
13973	/**
13974	* VM-exit exception handler for \#PF (Page-fault exception).
13975	*
13976	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
13977	*/
13978	static VBOXSTRICTRC hmR0VmxExitXcptPF(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
13979	{
13980	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13981	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
13982	hmR0VmxReadExitQualVmcs(pVmxTransient);
13983
13984	if (!pVM->hmr0.s.fNestedPaging)
13985	{ /* likely */ }
13986	else
13987	{
13988	#if !defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) && !defined(HMVMX_ALWAYS_TRAP_PF)
13989	Assert(pVmxTransient->fIsNestedGuest \|\| pVCpu->hmr0.s.fUsingDebugLoop);
13990	#endif
13991	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
13992	if (!pVmxTransient->fVectoringDoublePF)
13993	{
13994	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
13995	pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual);
13996	}
13997	else
13998	{
13999	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
14000	Assert(!pVmxTransient->fIsNestedGuest);
14001	hmR0VmxSetPendingXcptDF(pVCpu);
14002	Log4Func(("Pending #DF due to vectoring #PF w/ NestedPaging\n"));
14003	}
14004	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
14005	return VINF_SUCCESS;
14006	}
14007
14008	Assert(!pVmxTransient->fIsNestedGuest);
14009
14010	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
14011	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
14012	if (pVmxTransient->fVectoringPF)
14013	{
14014	Assert(pVCpu->hm.s.Event.fPending);
14015	return VINF_EM_RAW_INJECT_TRPM_EVENT;
14016	}
14017
14018	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
14019	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
14020	AssertRCReturn(rc, rc);
14021
14022	Log4Func(("#PF: cs:rip=%#04x:%#RX64 err_code=%#RX32 exit_qual=%#RX64 cr3=%#RX64\n", pCtx->cs.Sel, pCtx->rip,
14023	pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual, pCtx->cr3));
14024
14025	TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQual, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
14026	rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pCtx), (RTGCPTR)pVmxTransient->uExitQual);
14027
14028	Log4Func(("#PF: rc=%Rrc\n", rc));
14029	if (rc == VINF_SUCCESS)
14030	{
14031	/*
14032	* This is typically a shadow page table sync or a MMIO instruction. But we may have
14033	* emulated something like LTR or a far jump. Any part of the CPU context may have changed.
14034	*/
14035	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
14036	TRPMResetTrap(pVCpu);
14037	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
14038	return rc;
14039	}
14040
14041	if (rc == VINF_EM_RAW_GUEST_TRAP)
14042	{
14043	if (!pVmxTransient->fVectoringDoublePF)
14044	{
14045	/* It's a guest page fault and needs to be reflected to the guest. */
14046	uint32_t const uGstErrorCode = TRPMGetErrorCode(pVCpu);
14047	TRPMResetTrap(pVCpu);
14048	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
14049	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
14050	uGstErrorCode, pVmxTransient->uExitQual);
14051	}
14052	else
14053	{
14054	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
14055	TRPMResetTrap(pVCpu);
14056	pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
14057	hmR0VmxSetPendingXcptDF(pVCpu);
14058	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
14059	}
14060
14061	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
14062	return VINF_SUCCESS;
14063	}
14064
14065	TRPMResetTrap(pVCpu);
14066	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
14067	return rc;
14068	}
14069
14070
14071	/**
14072	* VM-exit exception handler for \#MF (Math Fault: floating point exception).
14073	*
14074	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
14075	*/
14076	static VBOXSTRICTRC hmR0VmxExitXcptMF(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14077	{
14078	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14079	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
14080
14081	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CR0);
14082	AssertRCReturn(rc, rc);
14083
14084	if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE))
14085	{
14086	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
14087	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
14088
14089	/** @todo r=ramshankar: The Intel spec. does -not- specify that this VM-exit
14090	* provides VM-exit instruction length. If this causes problem later,
14091	* disassemble the instruction like it's done on AMD-V. */
14092	int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
14093	AssertRCReturn(rc2, rc2);
14094	return rc;
14095	}
14096
14097	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbExitInstr,
14098	pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
14099	return VINF_SUCCESS;
14100	}
14101
14102
14103	/**
14104	* VM-exit exception handler for \#BP (Breakpoint exception).
14105	*
14106	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
14107	*/
14108	static VBOXSTRICTRC hmR0VmxExitXcptBP(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14109	{
14110	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14111	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
14112
14113	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
14114	AssertRCReturn(rc, rc);
14115
14116	if (!pVmxTransient->fIsNestedGuest)
14117	rc = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx));
14118	else
14119	rc = VINF_EM_RAW_GUEST_TRAP;
14120
14121	if (rc == VINF_EM_RAW_GUEST_TRAP)
14122	{
14123	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
14124	pVmxTransient->cbExitInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
14125	rc = VINF_SUCCESS;
14126	}
14127
14128	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_DBG_BREAKPOINT);
14129	return rc;
14130	}
14131
14132
14133	/**
14134	* VM-exit exception handler for \#AC (Alignment-check exception).
14135	*
14136	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
14137	*/
14138	static VBOXSTRICTRC hmR0VmxExitXcptAC(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14139	{
14140	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14141
14142	/*
14143	* Detect #ACs caused by host having enabled split-lock detection.
14144	* Emulate such instructions.
14145	*/
14146	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo,
14147	CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_SS \| CPUMCTX_EXTRN_CS);
14148	AssertRCReturn(rc, rc);
14149	/** @todo detect split lock in cpu feature? */
14150	if ( /* 1. If 486-style alignment checks aren't enabled, then this must be a split-lock exception */
14151	!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_AM)
14152	/* 2. #AC cannot happen in rings 0-2 except for split-lock detection. */
14153	\|\| CPUMGetGuestCPL(pVCpu) != 3
14154	/* 3. When the EFLAGS.AC != 0 this can only be a split-lock case. */
14155	\|\| !(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_AC) )
14156	{
14157	/*
14158	* Check for debug/trace events and import state accordingly.
14159	*/
14160	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitGuestACSplitLock);
14161	PVMCC pVM = pVCpu->pVMR0;
14162	if ( !DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_VMX_SPLIT_LOCK)
14163	&& !VBOXVMM_VMX_SPLIT_LOCK_ENABLED())
14164	{
14165	if (pVM->cCpus == 1)
14166	{
14167	#if 0 /** @todo r=bird: This is potentially wrong. Might have to just do a whole state sync above and mark everything changed to be safe... */
14168	rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
14169	#else
14170	rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
14171	#endif
14172	AssertRCReturn(rc, rc);
14173	}
14174	}
14175	else
14176	{
14177	rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
14178	AssertRCReturn(rc, rc);
14179
14180	VBOXVMM_XCPT_DF(pVCpu, &pVCpu->cpum.GstCtx);
14181
14182	if (DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_VMX_SPLIT_LOCK))
14183	{
14184	VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, DBGFEVENT_VMX_SPLIT_LOCK, DBGFEVENTCTX_HM, 0);
14185	if (rcStrict != VINF_SUCCESS)
14186	return rcStrict;
14187	}
14188	}
14189
14190	/*
14191	* Emulate the instruction.
14192	*
14193	* We have to ignore the LOCK prefix here as we must not retrigger the
14194	* detection on the host. This isn't all that satisfactory, though...
14195	*/
14196	if (pVM->cCpus == 1)
14197	{
14198	Log8Func(("cs:rip=%#04x:%#RX64 rflags=%#RX64 cr0=%#RX64 split-lock #AC\n", pVCpu->cpum.GstCtx.cs.Sel,
14199	pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags, pVCpu->cpum.GstCtx.cr0));
14200
14201	/** @todo For SMP configs we should do a rendezvous here. */
14202	VBOXSTRICTRC rcStrict = IEMExecOneIgnoreLock(pVCpu);
14203	if (rcStrict == VINF_SUCCESS)
14204	#if 0 /** @todo r=bird: This is potentially wrong. Might have to just do a whole state sync above and mark everything changed to be safe... */
14205	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
14206	HM_CHANGED_GUEST_RIP
14207	\| HM_CHANGED_GUEST_RFLAGS
14208	\| HM_CHANGED_GUEST_GPRS_MASK
14209	\| HM_CHANGED_GUEST_CS
14210	\| HM_CHANGED_GUEST_SS);
14211	#else
14212	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
14213	#endif
14214	else if (rcStrict == VINF_IEM_RAISED_XCPT)
14215	{
14216	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
14217	rcStrict = VINF_SUCCESS;
14218	}
14219	return rcStrict;
14220	}
14221	Log8Func(("cs:rip=%#04x:%#RX64 rflags=%#RX64 cr0=%#RX64 split-lock #AC -> VINF_EM_EMULATE_SPLIT_LOCK\n",
14222	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags, pVCpu->cpum.GstCtx.cr0));
14223	return VINF_EM_EMULATE_SPLIT_LOCK;
14224	}
14225
14226	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC);
14227	Log8Func(("cs:rip=%#04x:%#RX64 rflags=%#RX64 cr0=%#RX64 cpl=%d -> #AC\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
14228	pVCpu->cpum.GstCtx.rflags, pVCpu->cpum.GstCtx.cr0, CPUMGetGuestCPL(pVCpu) ));
14229
14230	/* Re-inject it. We'll detect any nesting before getting here. */
14231	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
14232	pVmxTransient->cbExitInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
14233	return VINF_SUCCESS;
14234	}
14235
14236
14237	/**
14238	* VM-exit exception handler for \#DB (Debug exception).
14239	*
14240	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
14241	*/
14242	static VBOXSTRICTRC hmR0VmxExitXcptDB(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14243	{
14244	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14245	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
14246
14247	/*
14248	* Get the DR6-like values from the Exit qualification and pass it to DBGF for processing.
14249	*/
14250	hmR0VmxReadExitQualVmcs(pVmxTransient);
14251
14252	/* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
14253	uint64_t const uDR6 = X86_DR6_INIT_VAL
14254	\| (pVmxTransient->uExitQual & ( X86_DR6_B0 \| X86_DR6_B1 \| X86_DR6_B2 \| X86_DR6_B3
14255	\| X86_DR6_BD \| X86_DR6_BS));
14256
14257	int rc;
14258	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
14259	if (!pVmxTransient->fIsNestedGuest)
14260	{
14261	rc = DBGFTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
14262
14263	/*
14264	* Prevents stepping twice over the same instruction when the guest is stepping using
14265	* EFLAGS.TF and the hypervisor debugger is stepping using MTF.
14266	* Testcase: DOSQEMM, break (using "ba x 1") at cs:rip 0x70:0x774 and step (using "t").
14267	*/
14268	if ( rc == VINF_EM_DBG_STEPPED
14269	&& (pVmxTransient->pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG))
14270	{
14271	Assert(pVCpu->hm.s.fSingleInstruction);
14272	rc = VINF_EM_RAW_GUEST_TRAP;
14273	}
14274	}
14275	else
14276	rc = VINF_EM_RAW_GUEST_TRAP;
14277	Log6Func(("rc=%Rrc\n", rc));
14278	if (rc == VINF_EM_RAW_GUEST_TRAP)
14279	{
14280	/*
14281	* The exception was for the guest. Update DR6, DR7.GD and
14282	* IA32_DEBUGCTL.LBR before forwarding it.
14283	* See Intel spec. 27.1 "Architectural State before a VM-Exit".
14284	*/
14285	VMMRZCallRing3Disable(pVCpu);
14286	HM_DISABLE_PREEMPT(pVCpu);
14287
14288	pCtx->dr[6] &= ~X86_DR6_B_MASK;
14289	pCtx->dr[6] \|= uDR6;
14290	if (CPUMIsGuestDebugStateActive(pVCpu))
14291	ASMSetDR6(pCtx->dr[6]);
14292
14293	HM_RESTORE_PREEMPT();
14294	VMMRZCallRing3Enable(pVCpu);
14295
14296	rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_DR7);
14297	AssertRCReturn(rc, rc);
14298
14299	/* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
14300	pCtx->dr[7] &= ~(uint64_t)X86_DR7_GD;
14301
14302	/* Paranoia. */
14303	pCtx->dr[7] &= ~(uint64_t)X86_DR7_RAZ_MASK;
14304	pCtx->dr[7] \|= X86_DR7_RA1_MASK;
14305
14306	rc = VMXWriteVmcsNw(VMX_VMCS_GUEST_DR7, pCtx->dr[7]);
14307	AssertRC(rc);
14308
14309	/*
14310	* Raise #DB in the guest.
14311	*
14312	* It is important to reflect exactly what the VM-exit gave us (preserving the
14313	* interruption-type) rather than use hmR0VmxSetPendingXcptDB() as the #DB could've
14314	* been raised while executing ICEBP (INT1) and not the regular #DB. Thus it may
14315	* trigger different handling in the CPU (like skipping DPL checks), see @bugref{6398}.
14316	*
14317	* Intel re-documented ICEBP/INT1 on May 2018 previously documented as part of
14318	* Intel 386, see Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
14319	*/
14320	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
14321	pVmxTransient->cbExitInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
14322	return VINF_SUCCESS;
14323	}
14324
14325	/*
14326	* Not a guest trap, must be a hypervisor related debug event then.
14327	* Update DR6 in case someone is interested in it.
14328	*/
14329	AssertMsg(rc == VINF_EM_DBG_STEPPED \|\| rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
14330	AssertReturn(pVmxTransient->fWasHyperDebugStateActive, VERR_HM_IPE_5);
14331	CPUMSetHyperDR6(pVCpu, uDR6);
14332
14333	return rc;
14334	}
14335
14336
14337	/**
14338	* Hacks its way around the lovely mesa driver's backdoor accesses.
14339	*
14340	* @sa hmR0SvmHandleMesaDrvGp.
14341	*/
14342	static int hmR0VmxHandleMesaDrvGp(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, PCPUMCTX pCtx)
14343	{
14344	LogFunc(("cs:rip=%#04x:%#RX64 rcx=%#RX64 rbx=%#RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->rcx, pCtx->rbx));
14345	RT_NOREF(pCtx);
14346
14347	/* For now we'll just skip the instruction. */
14348	return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
14349	}
14350
14351
14352	/**
14353	* Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
14354	* backdoor logging w/o checking what it is running inside.
14355	*
14356	* This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
14357	* backdoor port and magic numbers loaded in registers.
14358	*
14359	* @returns true if it is, false if it isn't.
14360	* @sa hmR0SvmIsMesaDrvGp.
14361	*/
14362	DECLINLINE(bool) hmR0VmxIsMesaDrvGp(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient, PCPUMCTX pCtx)
14363	{
14364	/* 0xed: IN eAX,dx */
14365	uint8_t abInstr[1];
14366	if (pVmxTransient->cbExitInstr != sizeof(abInstr))
14367	return false;
14368
14369	/* Check that it is #GP(0). */
14370	if (pVmxTransient->uExitIntErrorCode != 0)
14371	return false;
14372
14373	/* Check magic and port. */
14374	Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RDX \| CPUMCTX_EXTRN_RCX)));
14375	/Log(("hmR0VmxIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->rax, pCtx->rdx));/
14376	if (pCtx->rax != UINT32_C(0x564d5868))
14377	return false;
14378	if (pCtx->dx != UINT32_C(0x5658))
14379	return false;
14380
14381	/* Flat ring-3 CS. */
14382	AssertCompile(HMVMX_CPUMCTX_EXTRN_ALL & CPUMCTX_EXTRN_CS);
14383	Assert(!(pCtx->fExtrn & CPUMCTX_EXTRN_CS));
14384	/Log(("hmR0VmxIsMesaDrvGp: cs.Attr.n.u2Dpl=%d base=%Rx64\n", pCtx->cs.Attr.n.u2Dpl, pCtx->cs.u64Base));/
14385	if (pCtx->cs.Attr.n.u2Dpl != 3)
14386	return false;
14387	if (pCtx->cs.u64Base != 0)
14388	return false;
14389
14390	/* Check opcode. */
14391	AssertCompile(HMVMX_CPUMCTX_EXTRN_ALL & CPUMCTX_EXTRN_RIP);
14392	Assert(!(pCtx->fExtrn & CPUMCTX_EXTRN_RIP));
14393	int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
14394	/Log(("hmR0VmxIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0]));/
14395	if (RT_FAILURE(rc))
14396	return false;
14397	if (abInstr[0] != 0xed)
14398	return false;
14399
14400	return true;
14401	}
14402
14403
14404	/**
14405	* VM-exit exception handler for \#GP (General-protection exception).
14406	*
14407	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
14408	*/
14409	static VBOXSTRICTRC hmR0VmxExitXcptGP(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14410	{
14411	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14412	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
14413
14414	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
14415	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14416	PVMXVMCSINFOSHARED pVmcsInfoShared = pVmcsInfo->pShared;
14417	if (pVmcsInfoShared->RealMode.fRealOnV86Active)
14418	{ /* likely */ }
14419	else
14420	{
14421	#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
14422	Assert(pVCpu->hmr0.s.fUsingDebugLoop \|\| pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv \|\| pVmxTransient->fIsNestedGuest);
14423	#endif
14424	/*
14425	* If the guest is not in real-mode or we have unrestricted guest execution support, or if we are
14426	* executing a nested-guest, reflect #GP to the guest or nested-guest.
14427	*/
14428	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
14429	AssertRCReturn(rc, rc);
14430	Log4Func(("Gst: cs:rip=%#04x:%#RX64 ErrorCode=%#x cr0=%#RX64 cpl=%u tr=%#04x\n", pCtx->cs.Sel, pCtx->rip,
14431	pVmxTransient->uExitIntErrorCode, pCtx->cr0, CPUMGetGuestCPL(pVCpu), pCtx->tr.Sel));
14432
14433	if ( pVmxTransient->fIsNestedGuest
14434	\|\| !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
14435	\|\| !hmR0VmxIsMesaDrvGp(pVCpu, pVmxTransient, pCtx))
14436	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
14437	pVmxTransient->cbExitInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
14438	else
14439	rc = hmR0VmxHandleMesaDrvGp(pVCpu, pVmxTransient, pCtx);
14440	return rc;
14441	}
14442
14443	Assert(CPUMIsGuestInRealModeEx(pCtx));
14444	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fUnrestrictedGuest);
14445	Assert(!pVmxTransient->fIsNestedGuest);
14446
14447	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
14448	AssertRCReturn(rc, rc);
14449
14450	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
14451	if (rcStrict == VINF_SUCCESS)
14452	{
14453	if (!CPUMIsGuestInRealModeEx(pCtx))
14454	{
14455	/*
14456	* The guest is no longer in real-mode, check if we can continue executing the
14457	* guest using hardware-assisted VMX. Otherwise, fall back to emulation.
14458	*/
14459	pVmcsInfoShared->RealMode.fRealOnV86Active = false;
14460	if (HMCanExecuteVmxGuest(pVCpu->pVMR0, pVCpu, pCtx))
14461	{
14462	Log4Func(("Mode changed but guest still suitable for executing using hardware-assisted VMX\n"));
14463	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
14464	}
14465	else
14466	{
14467	Log4Func(("Mode changed -> VINF_EM_RESCHEDULE\n"));
14468	rcStrict = VINF_EM_RESCHEDULE;
14469	}
14470	}
14471	else
14472	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
14473	}
14474	else if (rcStrict == VINF_IEM_RAISED_XCPT)
14475	{
14476	rcStrict = VINF_SUCCESS;
14477	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
14478	}
14479	return VBOXSTRICTRC_VAL(rcStrict);
14480	}
14481
14482
14483	/**
14484	* VM-exit exception handler wrapper for all other exceptions that are not handled
14485	* by a specific handler.
14486	*
14487	* This simply re-injects the exception back into the VM without any special
14488	* processing.
14489	*
14490	* @remarks Requires all fields in HMVMX_READ_XCPT_INFO to be read from the VMCS.
14491	*/
14492	static VBOXSTRICTRC hmR0VmxExitXcptOthers(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14493	{
14494	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14495
14496	#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
14497	PCVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14498	AssertMsg(pVCpu->hmr0.s.fUsingDebugLoop \|\| pVmcsInfo->pShared->RealMode.fRealOnV86Active \|\| pVmxTransient->fIsNestedGuest,
14499	("uVector=%#x u32XcptBitmap=%#X32\n",
14500	VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo), pVmcsInfo->u32XcptBitmap));
14501	NOREF(pVmcsInfo);
14502	#endif
14503
14504	/*
14505	* Re-inject the exception into the guest. This cannot be a double-fault condition which
14506	* would have been handled while checking exits due to event delivery.
14507	*/
14508	uint8_t const uVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
14509
14510	#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
14511	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
14512	AssertRCReturn(rc, rc);
14513	Log4Func(("Reinjecting Xcpt. uVector=%#x cs:rip=%#04x:%#RX64\n", uVector, pCtx->cs.Sel, pCtx->rip));
14514	#endif
14515
14516	#ifdef VBOX_WITH_STATISTICS
14517	switch (uVector)
14518	{
14519	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE); break;
14520	case X86_XCPT_DB: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB); break;
14521	case X86_XCPT_BP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP); break;
14522	case X86_XCPT_OF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
14523	case X86_XCPT_BR: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBR); break;
14524	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD); break;
14525	case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestOF); break;
14526	case X86_XCPT_DF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDF); break;
14527	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS); break;
14528	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP); break;
14529	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS); break;
14530	case X86_XCPT_GP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP); break;
14531	case X86_XCPT_PF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF); break;
14532	case X86_XCPT_MF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF); break;
14533	case X86_XCPT_AC: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestAC); break;
14534	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF); break;
14535	default:
14536	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
14537	break;
14538	}
14539	#endif
14540
14541	/* We should never call this function for a page-fault, we'd need to pass on the fault address below otherwise. */
14542	Assert(!VMX_EXIT_INT_INFO_IS_XCPT_PF(pVmxTransient->uExitIntInfo));
14543	NOREF(uVector);
14544
14545	/* Re-inject the original exception into the guest. */
14546	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
14547	pVmxTransient->cbExitInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
14548	return VINF_SUCCESS;
14549	}
14550
14551
14552	/**
14553	* VM-exit exception handler for all exceptions (except NMIs!).
14554	*
14555	* @remarks This may be called for both guests and nested-guests. Take care to not
14556	* make assumptions and avoid doing anything that is not relevant when
14557	* executing a nested-guest (e.g., Mesa driver hacks).
14558	*/
14559	static VBOXSTRICTRC hmR0VmxExitXcpt(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14560	{
14561	HMVMX_ASSERT_READ(pVmxTransient, HMVMX_READ_XCPT_INFO);
14562
14563	/*
14564	* If this VM-exit occurred while delivering an event through the guest IDT, take
14565	* action based on the return code and additional hints (e.g. for page-faults)
14566	* that will be updated in the VMX transient structure.
14567	*/
14568	VBOXSTRICTRC rcStrict = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
14569	if (rcStrict == VINF_SUCCESS)
14570	{
14571	/*
14572	* If an exception caused a VM-exit due to delivery of an event, the original
14573	* event may have to be re-injected into the guest. We shall reinject it and
14574	* continue guest execution. However, page-fault is a complicated case and
14575	* needs additional processing done in hmR0VmxExitXcptPF().
14576	*/
14577	Assert(VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
14578	uint8_t const uVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
14579	if ( !pVCpu->hm.s.Event.fPending
14580	\|\| uVector == X86_XCPT_PF)
14581	{
14582	switch (uVector)
14583	{
14584	case X86_XCPT_PF: return hmR0VmxExitXcptPF(pVCpu, pVmxTransient);
14585	case X86_XCPT_GP: return hmR0VmxExitXcptGP(pVCpu, pVmxTransient);
14586	case X86_XCPT_MF: return hmR0VmxExitXcptMF(pVCpu, pVmxTransient);
14587	case X86_XCPT_DB: return hmR0VmxExitXcptDB(pVCpu, pVmxTransient);
14588	case X86_XCPT_BP: return hmR0VmxExitXcptBP(pVCpu, pVmxTransient);
14589	case X86_XCPT_AC: return hmR0VmxExitXcptAC(pVCpu, pVmxTransient);
14590	default:
14591	return hmR0VmxExitXcptOthers(pVCpu, pVmxTransient);
14592	}
14593	}
14594	/* else: inject pending event before resuming guest execution. */
14595	}
14596	else if (rcStrict == VINF_HM_DOUBLE_FAULT)
14597	{
14598	Assert(pVCpu->hm.s.Event.fPending);
14599	rcStrict = VINF_SUCCESS;
14600	}
14601
14602	return rcStrict;
14603	}
14604	/** @} */
14605
14606
14607	/** @name VM-exit handlers.
14608	* @{
14609	*/
14610	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
14611	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
14612	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
14613
14614	/**
14615	* VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
14616	*/
14617	HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14618	{
14619	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14620	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
14621	/* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
14622	if (VMMR0ThreadCtxHookIsEnabled(pVCpu))
14623	return VINF_SUCCESS;
14624	return VINF_EM_RAW_INTERRUPT;
14625	}
14626
14627
14628	/**
14629	* VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI). Conditional
14630	* VM-exit.
14631	*/
14632	HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14633	{
14634	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14635	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
14636
14637	hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
14638
14639	uint32_t const uExitIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
14640	uint8_t const uVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
14641	Assert(VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
14642
14643	PCVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14644	Assert( !(pVmcsInfo->u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
14645	&& uExitIntType != VMX_EXIT_INT_INFO_TYPE_EXT_INT);
14646	NOREF(pVmcsInfo);
14647
14648	VBOXSTRICTRC rcStrict;
14649	switch (uExitIntType)
14650	{
14651	/*
14652	* Host physical NMIs:
14653	* This cannot be a guest NMI as the only way for the guest to receive an NMI is if we
14654	* injected it ourselves and anything we inject is not going to cause a VM-exit directly
14655	* for the event being injected[1]. Go ahead and dispatch the NMI to the host[2].
14656	*
14657	* See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
14658	* See Intel spec. 27.5.5 "Updating Non-Register State".
14659	*/
14660	case VMX_EXIT_INT_INFO_TYPE_NMI:
14661	{
14662	rcStrict = hmR0VmxExitHostNmi(pVCpu, pVmcsInfo);
14663	break;
14664	}
14665
14666	/*
14667	* Privileged software exceptions (#DB from ICEBP),
14668	* Software exceptions (#BP and #OF),
14669	* Hardware exceptions:
14670	* Process the required exceptions and resume guest execution if possible.
14671	*/
14672	case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT:
14673	Assert(uVector == X86_XCPT_DB);
14674	RT_FALL_THRU();
14675	case VMX_EXIT_INT_INFO_TYPE_SW_XCPT:
14676	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF \|\| uExitIntType == VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT);
14677	RT_FALL_THRU();
14678	case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
14679	{
14680	NOREF(uVector);
14681	hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
14682	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
14683	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
14684	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
14685
14686	rcStrict = hmR0VmxExitXcpt(pVCpu, pVmxTransient);
14687	break;
14688	}
14689
14690	default:
14691	{
14692	pVCpu->hm.s.u32HMError = pVmxTransient->uExitIntInfo;
14693	rcStrict = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
14694	AssertMsgFailed(("Invalid/unexpected VM-exit interruption info %#x\n", pVmxTransient->uExitIntInfo));
14695	break;
14696	}
14697	}
14698
14699	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
14700	return rcStrict;
14701	}
14702
14703
14704	/**
14705	* VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
14706	*/
14707	HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14708	{
14709	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14710
14711	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
14712	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14713	hmR0VmxClearIntWindowExitVmcs(pVmcsInfo);
14714
14715	/* Evaluate and deliver pending events and resume guest execution. */
14716	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
14717	return VINF_SUCCESS;
14718	}
14719
14720
14721	/**
14722	* VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
14723	*/
14724	HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14725	{
14726	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14727
14728	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14729	if (RT_UNLIKELY(!(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))) /** @todo NSTVMX: Turn this into an assertion. */
14730	{
14731	AssertMsgFailed(("Unexpected NMI-window exit.\n"));
14732	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient->uExitReason);
14733	}
14734
14735	Assert(!CPUMIsGuestNmiBlocking(pVCpu));
14736
14737	/*
14738	* If block-by-STI is set when we get this VM-exit, it means the CPU doesn't block NMIs following STI.
14739	* It is therefore safe to unblock STI and deliver the NMI ourselves. See @bugref{7445}.
14740	*/
14741	uint32_t fIntrState;
14742	int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
14743	AssertRC(rc);
14744	Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
14745	if (fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
14746	{
14747	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
14748	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
14749
14750	fIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
14751	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
14752	AssertRC(rc);
14753	}
14754
14755	/* Indicate that we no longer need to VM-exit when the guest is ready to receive NMIs, it is now ready */
14756	hmR0VmxClearNmiWindowExitVmcs(pVmcsInfo);
14757
14758	/* Evaluate and deliver pending events and resume guest execution. */
14759	return VINF_SUCCESS;
14760	}
14761
14762
14763	/**
14764	* VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
14765	*/
14766	HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14767	{
14768	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14769	return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
14770	}
14771
14772
14773	/**
14774	* VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
14775	*/
14776	HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14777	{
14778	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14779	return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
14780	}
14781
14782
14783	/**
14784	* VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
14785	*/
14786	HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14787	{
14788	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14789
14790	/*
14791	* Get the state we need and update the exit history entry.
14792	*/
14793	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14794	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
14795
14796	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
14797	AssertRCReturn(rc, rc);
14798
14799	VBOXSTRICTRC rcStrict;
14800	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
14801	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
14802	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
14803	if (!pExitRec)
14804	{
14805	/*
14806	* Regular CPUID instruction execution.
14807	*/
14808	rcStrict = IEMExecDecodedCpuid(pVCpu, pVmxTransient->cbExitInstr);
14809	if (rcStrict == VINF_SUCCESS)
14810	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
14811	else if (rcStrict == VINF_IEM_RAISED_XCPT)
14812	{
14813	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
14814	rcStrict = VINF_SUCCESS;
14815	}
14816	}
14817	else
14818	{
14819	/*
14820	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
14821	*/
14822	int rc2 = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
14823	AssertRCReturn(rc2, rc2);
14824
14825	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
14826	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
14827
14828	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
14829	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
14830
14831	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
14832	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
14833	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
14834	}
14835	return rcStrict;
14836	}
14837
14838
14839	/**
14840	* VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
14841	*/
14842	HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14843	{
14844	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14845
14846	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14847	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_CR4);
14848	AssertRCReturn(rc, rc);
14849
14850	if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_SMXE)
14851	return VINF_EM_RAW_EMULATE_INSTR;
14852
14853	AssertMsgFailed(("hmR0VmxExitGetsec: Unexpected VM-exit when CR4.SMXE is 0.\n"));
14854	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient->uExitReason);
14855	}
14856
14857
14858	/**
14859	* VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
14860	*/
14861	HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14862	{
14863	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14864
14865	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14866	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
14867	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
14868	AssertRCReturn(rc, rc);
14869
14870	VBOXSTRICTRC rcStrict = IEMExecDecodedRdtsc(pVCpu, pVmxTransient->cbExitInstr);
14871	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
14872	{
14873	/* If we get a spurious VM-exit when TSC offsetting is enabled,
14874	we must reset offsetting on VM-entry. See @bugref{6634}. */
14875	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
14876	pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer = false;
14877	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
14878	}
14879	else if (rcStrict == VINF_IEM_RAISED_XCPT)
14880	{
14881	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
14882	rcStrict = VINF_SUCCESS;
14883	}
14884	return rcStrict;
14885	}
14886
14887
14888	/**
14889	* VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
14890	*/
14891	HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14892	{
14893	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14894
14895	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14896	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
14897	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_TSC_AUX);
14898	AssertRCReturn(rc, rc);
14899
14900	VBOXSTRICTRC rcStrict = IEMExecDecodedRdtscp(pVCpu, pVmxTransient->cbExitInstr);
14901	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
14902	{
14903	/* If we get a spurious VM-exit when TSC offsetting is enabled,
14904	we must reset offsetting on VM-reentry. See @bugref{6634}. */
14905	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
14906	pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer = false;
14907	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
14908	}
14909	else if (rcStrict == VINF_IEM_RAISED_XCPT)
14910	{
14911	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
14912	rcStrict = VINF_SUCCESS;
14913	}
14914	return rcStrict;
14915	}
14916
14917
14918	/**
14919	* VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
14920	*/
14921	HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14922	{
14923	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14924
14925	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14926	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR0
14927	\| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_SS);
14928	AssertRCReturn(rc, rc);
14929
14930	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
14931	rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
14932	if (RT_LIKELY(rc == VINF_SUCCESS))
14933	{
14934	rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
14935	Assert(pVmxTransient->cbExitInstr == 2);
14936	}
14937	else
14938	{
14939	AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
14940	rc = VERR_EM_INTERPRETER;
14941	}
14942	return rc;
14943	}
14944
14945
14946	/**
14947	* VM-exit handler for VMCALL (VMX_EXIT_VMCALL). Unconditional VM-exit.
14948	*/
14949	HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14950	{
14951	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14952
14953	VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
14954	if (EMAreHypercallInstructionsEnabled(pVCpu))
14955	{
14956	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14957	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_CR0
14958	\| CPUMCTX_EXTRN_SS \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_EFER);
14959	AssertRCReturn(rc, rc);
14960
14961	/* Perform the hypercall. */
14962	rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
14963	if (rcStrict == VINF_SUCCESS)
14964	{
14965	rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
14966	AssertRCReturn(rc, rc);
14967	}
14968	else
14969	Assert( rcStrict == VINF_GIM_R3_HYPERCALL
14970	\|\| rcStrict == VINF_GIM_HYPERCALL_CONTINUING
14971	\|\| RT_FAILURE(rcStrict));
14972
14973	/* If the hypercall changes anything other than guest's general-purpose registers,
14974	we would need to reload the guest changed bits here before VM-entry. */
14975	}
14976	else
14977	Log4Func(("Hypercalls not enabled\n"));
14978
14979	/* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
14980	if (RT_FAILURE(rcStrict))
14981	{
14982	hmR0VmxSetPendingXcptUD(pVCpu);
14983	rcStrict = VINF_SUCCESS;
14984	}
14985
14986	return rcStrict;
14987	}
14988
14989
14990	/**
14991	* VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
14992	*/
14993	HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
14994	{
14995	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
14996	Assert(!pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging \|\| pVCpu->hmr0.s.fUsingDebugLoop);
14997
14998	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
14999	hmR0VmxReadExitQualVmcs(pVmxTransient);
15000	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15001	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
15002	AssertRCReturn(rc, rc);
15003
15004	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, pVmxTransient->cbExitInstr, pVmxTransient->uExitQual);
15005
15006	if (rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_PGM_SYNC_CR3)
15007	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
15008	else if (rcStrict == VINF_IEM_RAISED_XCPT)
15009	{
15010	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
15011	rcStrict = VINF_SUCCESS;
15012	}
15013	else
15014	AssertMsgFailed(("Unexpected IEMExecDecodedInvlpg(%#RX64) status: %Rrc\n", pVmxTransient->uExitQual,
15015	VBOXSTRICTRC_VAL(rcStrict)));
15016	return rcStrict;
15017	}
15018
15019
15020	/**
15021	* VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
15022	*/
15023	HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15024	{
15025	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15026
15027	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15028	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15029	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
15030	AssertRCReturn(rc, rc);
15031
15032	VBOXSTRICTRC rcStrict = IEMExecDecodedMonitor(pVCpu, pVmxTransient->cbExitInstr);
15033	if (rcStrict == VINF_SUCCESS)
15034	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
15035	else if (rcStrict == VINF_IEM_RAISED_XCPT)
15036	{
15037	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
15038	rcStrict = VINF_SUCCESS;
15039	}
15040
15041	return rcStrict;
15042	}
15043
15044
15045	/**
15046	* VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
15047	*/
15048	HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15049	{
15050	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15051
15052	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15053	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15054	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
15055	AssertRCReturn(rc, rc);
15056
15057	VBOXSTRICTRC rcStrict = IEMExecDecodedMwait(pVCpu, pVmxTransient->cbExitInstr);
15058	if (RT_SUCCESS(rcStrict))
15059	{
15060	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
15061	if (EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
15062	rcStrict = VINF_SUCCESS;
15063	}
15064
15065	return rcStrict;
15066	}
15067
15068
15069	/**
15070	* VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
15071	* VM-exit.
15072	*/
15073	HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15074	{
15075	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15076	return VINF_EM_RESET;
15077	}
15078
15079
15080	/**
15081	* VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
15082	*/
15083	HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15084	{
15085	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15086
15087	int rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
15088	AssertRCReturn(rc, rc);
15089
15090	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RFLAGS); /* Advancing the RIP above should've imported eflags. */
15091	if (EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx)) /* Requires eflags. */
15092	rc = VINF_SUCCESS;
15093	else
15094	rc = VINF_EM_HALT;
15095
15096	if (rc != VINF_SUCCESS)
15097	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
15098	return rc;
15099	}
15100
15101
15102	/**
15103	* VM-exit handler for instructions that result in a \#UD exception delivered to
15104	* the guest.
15105	*/
15106	HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15107	{
15108	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15109	hmR0VmxSetPendingXcptUD(pVCpu);
15110	return VINF_SUCCESS;
15111	}
15112
15113
15114	/**
15115	* VM-exit handler for expiry of the VMX-preemption timer.
15116	*/
15117	HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15118	{
15119	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15120
15121	/* If the VMX-preemption timer has expired, reinitialize the preemption timer on next VM-entry. */
15122	pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer = false;
15123	Log12(("hmR0VmxExitPreemptTimer:\n"));
15124
15125	/* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
15126	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
15127	bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
15128	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
15129	return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
15130	}
15131
15132
15133	/**
15134	* VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
15135	*/
15136	HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15137	{
15138	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15139
15140	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15141	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15142	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_CR4);
15143	AssertRCReturn(rc, rc);
15144
15145	VBOXSTRICTRC rcStrict = IEMExecDecodedXsetbv(pVCpu, pVmxTransient->cbExitInstr);
15146	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS
15147	: HM_CHANGED_RAISED_XCPT_MASK);
15148
15149	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
15150	bool const fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
15151	if (fLoadSaveGuestXcr0 != pVCpu->hmr0.s.fLoadSaveGuestXcr0)
15152	{
15153	pVCpu->hmr0.s.fLoadSaveGuestXcr0 = fLoadSaveGuestXcr0;
15154	hmR0VmxUpdateStartVmFunction(pVCpu);
15155	}
15156
15157	return rcStrict;
15158	}
15159
15160
15161	/**
15162	* VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
15163	*/
15164	HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15165	{
15166	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15167
15168	/** @todo Enable the new code after finding a reliably guest test-case. */
15169	#if 1
15170	return VERR_EM_INTERPRETER;
15171	#else
15172	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15173	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
15174	hmR0VmxReadExitQualVmcs(pVmxTransient);
15175	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
15176	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
15177	AssertRCReturn(rc, rc);
15178
15179	/* Paranoia. Ensure this has a memory operand. */
15180	Assert(!pVmxTransient->ExitInstrInfo.Inv.u1Cleared0);
15181
15182	uint8_t const iGReg = pVmxTransient->ExitInstrInfo.VmreadVmwrite.iReg2;
15183	Assert(iGReg < RT_ELEMENTS(pVCpu->cpum.GstCtx.aGRegs));
15184	uint64_t const uType = CPUMIsGuestIn64BitCode(pVCpu) ? pVCpu->cpum.GstCtx.aGRegs[iGReg].u64
15185	: pVCpu->cpum.GstCtx.aGRegs[iGReg].u32;
15186
15187	RTGCPTR GCPtrDesc;
15188	HMVMX_DECODE_MEM_OPERAND(pVCpu, pVmxTransient->ExitInstrInfo.u, pVmxTransient->uExitQual, VMXMEMACCESS_READ, &GCPtrDesc);
15189
15190	VBOXSTRICTRC rcStrict = IEMExecDecodedInvpcid(pVCpu, pVmxTransient->cbExitInstr, pVmxTransient->ExitInstrInfo.Inv.iSegReg,
15191	GCPtrDesc, uType);
15192	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
15193	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
15194	else if (rcStrict == VINF_IEM_RAISED_XCPT)
15195	{
15196	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
15197	rcStrict = VINF_SUCCESS;
15198	}
15199	return rcStrict;
15200	#endif
15201	}
15202
15203
15204	/**
15205	* VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE). Error
15206	* VM-exit.
15207	*/
15208	HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrInvalidGuestState(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15209	{
15210	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15211	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
15212	AssertRCReturn(rc, rc);
15213
15214	rc = hmR0VmxCheckCachedVmcsCtls(pVCpu, pVmcsInfo, pVmxTransient->fIsNestedGuest);
15215	if (RT_FAILURE(rc))
15216	return rc;
15217
15218	uint32_t const uInvalidReason = hmR0VmxCheckGuestState(pVCpu, pVmcsInfo);
15219	NOREF(uInvalidReason);
15220
15221	#ifdef VBOX_STRICT
15222	uint32_t fIntrState;
15223	uint64_t u64Val;
15224	hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
15225	hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
15226	hmR0VmxReadEntryInstrLenVmcs(pVmxTransient);
15227
15228	Log4(("uInvalidReason %u\n", uInvalidReason));
15229	Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntInfo));
15230	Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
15231	Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
15232
15233	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState); AssertRC(rc);
15234	Log4(("VMX_VMCS32_GUEST_INT_STATE %#RX32\n", fIntrState));
15235	rc = VMXReadVmcsNw(VMX_VMCS_GUEST_CR0, &u64Val); AssertRC(rc);
15236	Log4(("VMX_VMCS_GUEST_CR0 %#RX64\n", u64Val));
15237	rc = VMXReadVmcsNw(VMX_VMCS_CTRL_CR0_MASK, &u64Val); AssertRC(rc);
15238	Log4(("VMX_VMCS_CTRL_CR0_MASK %#RX64\n", u64Val));
15239	rc = VMXReadVmcsNw(VMX_VMCS_CTRL_CR0_READ_SHADOW, &u64Val); AssertRC(rc);
15240	Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RX64\n", u64Val));
15241	rc = VMXReadVmcsNw(VMX_VMCS_CTRL_CR4_MASK, &u64Val); AssertRC(rc);
15242	Log4(("VMX_VMCS_CTRL_CR4_MASK %#RX64\n", u64Val));
15243	rc = VMXReadVmcsNw(VMX_VMCS_CTRL_CR4_READ_SHADOW, &u64Val); AssertRC(rc);
15244	Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RX64\n", u64Val));
15245	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging)
15246	{
15247	rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
15248	Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
15249	}
15250	hmR0DumpRegs(pVCpu, HM_DUMP_REG_FLAGS_ALL);
15251	#endif
15252
15253	return VERR_VMX_INVALID_GUEST_STATE;
15254	}
15255
15256	/**
15257	* VM-exit handler for all undefined/unexpected reasons. Should never happen.
15258	*/
15259	HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrUnexpected(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15260	{
15261	/*
15262	* Cumulative notes of all recognized but unexpected VM-exits.
15263	*
15264	* 1. This does -not- cover scenarios like a page-fault VM-exit occurring when
15265	* nested-paging is used.
15266	*
15267	* 2. Any instruction that causes a VM-exit unconditionally (for e.g. VMXON) must be
15268	* emulated or a #UD must be raised in the guest. Therefore, we should -not- be using
15269	* this function (and thereby stop VM execution) for handling such instructions.
15270	*
15271	*
15272	* VMX_EXIT_INIT_SIGNAL:
15273	* INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
15274	* It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these
15275	* VM-exits. However, we should not receive INIT signals VM-exit while executing a VM.
15276	*
15277	* See Intel spec. 33.14.1 Default Treatment of SMI Delivery"
15278	* See Intel spec. 29.3 "VMX Instructions" for "VMXON".
15279	* See Intel spec. "23.8 Restrictions on VMX operation".
15280	*
15281	* VMX_EXIT_SIPI:
15282	* SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest
15283	* activity state is used. We don't make use of it as our guests don't have direct
15284	* access to the host local APIC.
15285	*
15286	* See Intel spec. 25.3 "Other Causes of VM-exits".
15287	*
15288	* VMX_EXIT_IO_SMI:
15289	* VMX_EXIT_SMI:
15290	* This can only happen if we support dual-monitor treatment of SMI, which can be
15291	* activated by executing VMCALL in VMX root operation. Only an STM (SMM transfer
15292	* monitor) would get this VM-exit when we (the executive monitor) execute a VMCALL in
15293	* VMX root mode or receive an SMI. If we get here, something funny is going on.
15294	*
15295	* See Intel spec. 33.15.6 "Activating the Dual-Monitor Treatment"
15296	* See Intel spec. 25.3 "Other Causes of VM-Exits"
15297	*
15298	* VMX_EXIT_ERR_MSR_LOAD:
15299	* Failures while loading MSRs are part of the VM-entry MSR-load area are unexpected
15300	* and typically indicates a bug in the hypervisor code. We thus cannot not resume
15301	* execution.
15302	*
15303	* See Intel spec. 26.7 "VM-Entry Failures During Or After Loading Guest State".
15304	*
15305	* VMX_EXIT_ERR_MACHINE_CHECK:
15306	* Machine check exceptions indicates a fatal/unrecoverable hardware condition
15307	* including but not limited to system bus, ECC, parity, cache and TLB errors. A
15308	* #MC exception abort class exception is raised. We thus cannot assume a
15309	* reasonable chance of continuing any sort of execution and we bail.
15310	*
15311	* See Intel spec. 15.1 "Machine-check Architecture".
15312	* See Intel spec. 27.1 "Architectural State Before A VM Exit".
15313	*
15314	* VMX_EXIT_PML_FULL:
15315	* VMX_EXIT_VIRTUALIZED_EOI:
15316	* VMX_EXIT_APIC_WRITE:
15317	* We do not currently support any of these features and thus they are all unexpected
15318	* VM-exits.
15319	*
15320	* VMX_EXIT_GDTR_IDTR_ACCESS:
15321	* VMX_EXIT_LDTR_TR_ACCESS:
15322	* VMX_EXIT_RDRAND:
15323	* VMX_EXIT_RSM:
15324	* VMX_EXIT_VMFUNC:
15325	* VMX_EXIT_ENCLS:
15326	* VMX_EXIT_RDSEED:
15327	* VMX_EXIT_XSAVES:
15328	* VMX_EXIT_XRSTORS:
15329	* VMX_EXIT_UMWAIT:
15330	* VMX_EXIT_TPAUSE:
15331	* These VM-exits are -not- caused unconditionally by execution of the corresponding
15332	* instruction. Any VM-exit for these instructions indicate a hardware problem,
15333	* unsupported CPU modes (like SMM) or potentially corrupt VMCS controls.
15334	*
15335	* See Intel spec. 25.1.3 "Instructions That Cause VM Exits Conditionally".
15336	*/
15337	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15338	AssertMsgFailed(("Unexpected VM-exit %u\n", pVmxTransient->uExitReason));
15339	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient->uExitReason);
15340	}
15341
15342
15343	/**
15344	* VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
15345	*/
15346	HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15347	{
15348	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15349
15350	/** @todo Optimize this: We currently drag in the whole MSR state
15351	* (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
15352	* MSRs required. That would require changes to IEM and possibly CPUM too.
15353	* (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
15354	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15355	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
15356	uint64_t fImport = IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS;
15357	switch (idMsr)
15358	{
15359	case MSR_K8_FS_BASE: fImport \|= CPUMCTX_EXTRN_FS; break;
15360	case MSR_K8_GS_BASE: fImport \|= CPUMCTX_EXTRN_GS; break;
15361	}
15362
15363	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15364	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, fImport);
15365	AssertRCReturn(rc, rc);
15366
15367	Log4Func(("ecx=%#RX32\n", idMsr));
15368
15369	#ifdef VBOX_STRICT
15370	Assert(!pVmxTransient->fIsNestedGuest);
15371	if (pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
15372	{
15373	if ( hmR0VmxIsAutoLoadGuestMsr(pVmcsInfo, idMsr)
15374	&& idMsr != MSR_K6_EFER)
15375	{
15376	AssertMsgFailed(("Unexpected RDMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n", idMsr));
15377	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, idMsr);
15378	}
15379	if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
15380	{
15381	Assert(pVmcsInfo->pvMsrBitmap);
15382	uint32_t fMsrpm = CPUMGetVmxMsrPermission(pVmcsInfo->pvMsrBitmap, idMsr);
15383	if (fMsrpm & VMXMSRPM_ALLOW_RD)
15384	{
15385	AssertMsgFailed(("Unexpected RDMSR for a passthru lazy-restore MSR. ecx=%#RX32\n", idMsr));
15386	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, idMsr);
15387	}
15388	}
15389	}
15390	#endif
15391
15392	VBOXSTRICTRC rcStrict = IEMExecDecodedRdmsr(pVCpu, pVmxTransient->cbExitInstr);
15393	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
15394	if (rcStrict == VINF_SUCCESS)
15395	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
15396	else if (rcStrict == VINF_IEM_RAISED_XCPT)
15397	{
15398	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
15399	rcStrict = VINF_SUCCESS;
15400	}
15401	else
15402	AssertMsg(rcStrict == VINF_CPUM_R3_MSR_READ \|\| rcStrict == VINF_EM_TRIPLE_FAULT,
15403	("Unexpected IEMExecDecodedRdmsr rc (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
15404
15405	return rcStrict;
15406	}
15407
15408
15409	/**
15410	* VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
15411	*/
15412	HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15413	{
15414	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15415
15416	/** @todo Optimize this: We currently drag in the whole MSR state
15417	* (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
15418	* MSRs required. That would require changes to IEM and possibly CPUM too.
15419	* (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
15420	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
15421	uint64_t fImport = IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS;
15422
15423	/*
15424	* The FS and GS base MSRs are not part of the above all-MSRs mask.
15425	* Although we don't need to fetch the base as it will be overwritten shortly, while
15426	* loading guest-state we would also load the entire segment register including limit
15427	* and attributes and thus we need to load them here.
15428	*/
15429	switch (idMsr)
15430	{
15431	case MSR_K8_FS_BASE: fImport \|= CPUMCTX_EXTRN_FS; break;
15432	case MSR_K8_GS_BASE: fImport \|= CPUMCTX_EXTRN_GS; break;
15433	}
15434
15435	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15436	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15437	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, fImport);
15438	AssertRCReturn(rc, rc);
15439
15440	Log4Func(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", idMsr, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.eax));
15441
15442	VBOXSTRICTRC rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmxTransient->cbExitInstr);
15443	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
15444
15445	if (rcStrict == VINF_SUCCESS)
15446	{
15447	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
15448
15449	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
15450	if ( idMsr == MSR_IA32_APICBASE
15451	\|\| ( idMsr >= MSR_IA32_X2APIC_START
15452	&& idMsr <= MSR_IA32_X2APIC_END))
15453	{
15454	/*
15455	* We've already saved the APIC related guest-state (TPR) in post-run phase.
15456	* When full APIC register virtualization is implemented we'll have to make
15457	* sure APIC state is saved from the VMCS before IEM changes it.
15458	*/
15459	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
15460	}
15461	else if (idMsr == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
15462	pVmxTransient->fUpdatedTscOffsettingAndPreemptTimer = false;
15463	else if (idMsr == MSR_K6_EFER)
15464	{
15465	/*
15466	* If the guest touches the EFER MSR we need to update the VM-Entry and VM-Exit controls
15467	* as well, even if it is -not- touching bits that cause paging mode changes (LMA/LME).
15468	* We care about the other bits as well, SCE and NXE. See @bugref{7368}.
15469	*/
15470	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR \| HM_CHANGED_VMX_ENTRY_EXIT_CTLS);
15471	}
15472
15473	/* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not used. */
15474	if (!(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
15475	{
15476	switch (idMsr)
15477	{
15478	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
15479	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
15480	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
15481	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
15482	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
15483	case MSR_K6_EFER: /* Nothing to do, already handled above. */ break;
15484	default:
15485	{
15486	if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
15487	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_LAZY_MSRS);
15488	else if (hmR0VmxIsAutoLoadGuestMsr(pVmcsInfo, idMsr))
15489	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
15490	break;
15491	}
15492	}
15493	}
15494	#ifdef VBOX_STRICT
15495	else
15496	{
15497	/* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
15498	switch (idMsr)
15499	{
15500	case MSR_IA32_SYSENTER_CS:
15501	case MSR_IA32_SYSENTER_EIP:
15502	case MSR_IA32_SYSENTER_ESP:
15503	case MSR_K8_FS_BASE:
15504	case MSR_K8_GS_BASE:
15505	{
15506	AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", idMsr));
15507	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, idMsr);
15508	}
15509
15510	/* Writes to MSRs in auto-load/store area/swapped MSRs, shouldn't cause VM-exits with MSR-bitmaps. */
15511	default:
15512	{
15513	if (hmR0VmxIsAutoLoadGuestMsr(pVmcsInfo, idMsr))
15514	{
15515	/* EFER MSR writes are always intercepted. */
15516	if (idMsr != MSR_K6_EFER)
15517	{
15518	AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
15519	idMsr));
15520	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, idMsr);
15521	}
15522	}
15523
15524	if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
15525	{
15526	Assert(pVmcsInfo->pvMsrBitmap);
15527	uint32_t fMsrpm = CPUMGetVmxMsrPermission(pVmcsInfo->pvMsrBitmap, idMsr);
15528	if (fMsrpm & VMXMSRPM_ALLOW_WR)
15529	{
15530	AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", idMsr));
15531	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, idMsr);
15532	}
15533	}
15534	break;
15535	}
15536	}
15537	}
15538	#endif /* VBOX_STRICT */
15539	}
15540	else if (rcStrict == VINF_IEM_RAISED_XCPT)
15541	{
15542	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
15543	rcStrict = VINF_SUCCESS;
15544	}
15545	else
15546	AssertMsg(rcStrict == VINF_CPUM_R3_MSR_WRITE \|\| rcStrict == VINF_EM_TRIPLE_FAULT,
15547	("Unexpected IEMExecDecodedWrmsr rc (%Rrc)\n", VBOXSTRICTRC_VAL(rcStrict)));
15548
15549	return rcStrict;
15550	}
15551
15552
15553	/**
15554	* VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
15555	*/
15556	HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15557	{
15558	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15559
15560	/** @todo The guest has likely hit a contended spinlock. We might want to
15561	* poke a schedule different guest VCPU. */
15562	int rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
15563	if (RT_SUCCESS(rc))
15564	return VINF_EM_RAW_INTERRUPT;
15565
15566	AssertMsgFailed(("hmR0VmxExitPause: Failed to increment RIP. rc=%Rrc\n", rc));
15567	return rc;
15568	}
15569
15570
15571	/**
15572	* VM-exit handler for when the TPR value is lowered below the specified
15573	* threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
15574	*/
15575	HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15576	{
15577	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15578	Assert(pVmxTransient->pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
15579
15580	/*
15581	* The TPR shadow would've been synced with the APIC TPR in the post-run phase.
15582	* We'll re-evaluate pending interrupts and inject them before the next VM
15583	* entry so we can just continue execution here.
15584	*/
15585	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
15586	return VINF_SUCCESS;
15587	}
15588
15589
15590	/**
15591	* VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
15592	* VM-exit.
15593	*
15594	* @retval VINF_SUCCESS when guest execution can continue.
15595	* @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
15596	* @retval VERR_EM_RESCHEDULE_REM when we need to return to ring-3 due to
15597	* incompatible guest state for VMX execution (real-on-v86 case).
15598	*/
15599	HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15600	{
15601	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15602	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
15603
15604	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15605	hmR0VmxReadExitQualVmcs(pVmxTransient);
15606	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15607
15608	VBOXSTRICTRC rcStrict;
15609	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
15610	uint64_t const uExitQual = pVmxTransient->uExitQual;
15611	uint32_t const uAccessType = VMX_EXIT_QUAL_CRX_ACCESS(uExitQual);
15612	switch (uAccessType)
15613	{
15614	/*
15615	* MOV to CRx.
15616	*/
15617	case VMX_EXIT_QUAL_CRX_ACCESS_WRITE:
15618	{
15619	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
15620	AssertRCReturn(rc, rc);
15621
15622	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
15623	uint32_t const uOldCr0 = pVCpu->cpum.GstCtx.cr0;
15624	uint8_t const iGReg = VMX_EXIT_QUAL_CRX_GENREG(uExitQual);
15625	uint8_t const iCrReg = VMX_EXIT_QUAL_CRX_REGISTER(uExitQual);
15626
15627	/*
15628	* MOV to CR3 only cause a VM-exit when one or more of the following are true:
15629	* - When nested paging isn't used.
15630	* - If the guest doesn't have paging enabled (intercept CR3 to update shadow page tables).
15631	* - We are executing in the VM debug loop.
15632	*/
15633	Assert( iCrReg != 3
15634	\|\| !pVM->hmr0.s.fNestedPaging
15635	\|\| !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
15636	\|\| pVCpu->hmr0.s.fUsingDebugLoop);
15637
15638	/* MOV to CR8 writes only cause VM-exits when TPR shadow is not used. */
15639	Assert( iCrReg != 8
15640	\|\| !(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
15641
15642	rcStrict = hmR0VmxExitMovToCrX(pVCpu, pVmcsInfo, pVmxTransient->cbExitInstr, iGReg, iCrReg);
15643	AssertMsg( rcStrict == VINF_SUCCESS
15644	\|\| rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
15645
15646	/*
15647	* This is a kludge for handling switches back to real mode when we try to use
15648	* V86 mode to run real mode code directly. Problem is that V86 mode cannot
15649	* deal with special selector values, so we have to return to ring-3 and run
15650	* there till the selector values are V86 mode compatible.
15651	*
15652	* Note! Using VINF_EM_RESCHEDULE_REM here rather than VINF_EM_RESCHEDULE since the
15653	* latter is an alias for VINF_IEM_RAISED_XCPT which is asserted at the end of
15654	* this function.
15655	*/
15656	if ( iCrReg == 0
15657	&& rcStrict == VINF_SUCCESS
15658	&& !pVM->hmr0.s.vmx.fUnrestrictedGuest
15659	&& CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx)
15660	&& (uOldCr0 & X86_CR0_PE)
15661	&& !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE))
15662	{
15663	/** @todo Check selectors rather than returning all the time. */
15664	Assert(!pVmxTransient->fIsNestedGuest);
15665	Log4Func(("CR0 write, back to real mode -> VINF_EM_RESCHEDULE_REM\n"));
15666	rcStrict = VINF_EM_RESCHEDULE_REM;
15667	}
15668	break;
15669	}
15670
15671	/*
15672	* MOV from CRx.
15673	*/
15674	case VMX_EXIT_QUAL_CRX_ACCESS_READ:
15675	{
15676	uint8_t const iGReg = VMX_EXIT_QUAL_CRX_GENREG(uExitQual);
15677	uint8_t const iCrReg = VMX_EXIT_QUAL_CRX_REGISTER(uExitQual);
15678
15679	/*
15680	* MOV from CR3 only cause a VM-exit when one or more of the following are true:
15681	* - When nested paging isn't used.
15682	* - If the guest doesn't have paging enabled (pass guest's CR3 rather than our identity mapped CR3).
15683	* - We are executing in the VM debug loop.
15684	*/
15685	Assert( iCrReg != 3
15686	\|\| !pVM->hmr0.s.fNestedPaging
15687	\|\| !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
15688	\|\| pVCpu->hmr0.s.fLeaveDone);
15689
15690	/* MOV from CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
15691	Assert( iCrReg != 8
15692	\|\| !(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
15693
15694	rcStrict = hmR0VmxExitMovFromCrX(pVCpu, pVmcsInfo, pVmxTransient->cbExitInstr, iGReg, iCrReg);
15695	break;
15696	}
15697
15698	/*
15699	* CLTS (Clear Task-Switch Flag in CR0).
15700	*/
15701	case VMX_EXIT_QUAL_CRX_ACCESS_CLTS:
15702	{
15703	rcStrict = hmR0VmxExitClts(pVCpu, pVmcsInfo, pVmxTransient->cbExitInstr);
15704	break;
15705	}
15706
15707	/*
15708	* LMSW (Load Machine-Status Word into CR0).
15709	* LMSW cannot clear CR0.PE, so no fRealOnV86Active kludge needed here.
15710	*/
15711	case VMX_EXIT_QUAL_CRX_ACCESS_LMSW:
15712	{
15713	RTGCPTR GCPtrEffDst;
15714	uint8_t const cbInstr = pVmxTransient->cbExitInstr;
15715	uint16_t const uMsw = VMX_EXIT_QUAL_CRX_LMSW_DATA(uExitQual);
15716	bool const fMemOperand = VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(uExitQual);
15717	if (fMemOperand)
15718	{
15719	hmR0VmxReadGuestLinearAddrVmcs(pVmxTransient);
15720	GCPtrEffDst = pVmxTransient->uGuestLinearAddr;
15721	}
15722	else
15723	GCPtrEffDst = NIL_RTGCPTR;
15724	rcStrict = hmR0VmxExitLmsw(pVCpu, pVmcsInfo, cbInstr, uMsw, GCPtrEffDst);
15725	break;
15726	}
15727
15728	default:
15729	{
15730	AssertMsgFailed(("Unrecognized Mov CRX access type %#x\n", uAccessType));
15731	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, uAccessType);
15732	}
15733	}
15734
15735	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS))
15736	== (HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS));
15737	Assert(rcStrict != VINF_IEM_RAISED_XCPT);
15738
15739	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
15740	NOREF(pVM);
15741	return rcStrict;
15742	}
15743
15744
15745	/**
15746	* VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
15747	* VM-exit.
15748	*/
15749	HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15750	{
15751	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15752	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
15753
15754	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
15755	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
15756	hmR0VmxReadExitQualVmcs(pVmxTransient);
15757	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
15758	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK
15759	\| CPUMCTX_EXTRN_EFER);
15760	/* EFER MSR also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
15761	AssertRCReturn(rc, rc);
15762
15763	/* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
15764	uint32_t const uIOPort = VMX_EXIT_QUAL_IO_PORT(pVmxTransient->uExitQual);
15765	uint8_t const uIOSize = VMX_EXIT_QUAL_IO_SIZE(pVmxTransient->uExitQual);
15766	bool const fIOWrite = (VMX_EXIT_QUAL_IO_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_IO_DIRECTION_OUT);
15767	bool const fIOString = VMX_EXIT_QUAL_IO_IS_STRING(pVmxTransient->uExitQual);
15768	bool const fGstStepping = RT_BOOL(pCtx->eflags.Bits.u1TF);
15769	bool const fDbgStepping = pVCpu->hm.s.fSingleInstruction;
15770	AssertReturn(uIOSize <= 3 && uIOSize != 2, VERR_VMX_IPE_1);
15771
15772	/*
15773	* Update exit history to see if this exit can be optimized.
15774	*/
15775	VBOXSTRICTRC rcStrict;
15776	PCEMEXITREC pExitRec = NULL;
15777	if ( !fGstStepping
15778	&& !fDbgStepping)
15779	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
15780	!fIOString
15781	? !fIOWrite
15782	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
15783	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
15784	: !fIOWrite
15785	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
15786	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
15787	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
15788	if (!pExitRec)
15789	{
15790	static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses in bytes. */
15791	static uint32_t const s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving result in AL/AX/EAX. */
15792
15793	uint32_t const cbValue = s_aIOSizes[uIOSize];
15794	uint32_t const cbInstr = pVmxTransient->cbExitInstr;
15795	bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
15796	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
15797	if (fIOString)
15798	{
15799	/*
15800	* INS/OUTS - I/O String instruction.
15801	*
15802	* Use instruction-information if available, otherwise fall back on
15803	* interpreting the instruction.
15804	*/
15805	Log4Func(("cs:rip=%#04x:%#RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
15806	AssertReturn(pCtx->dx == uIOPort, VERR_VMX_IPE_2);
15807	bool const fInsOutsInfo = RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
15808	if (fInsOutsInfo)
15809	{
15810	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
15811	AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3);
15812	AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
15813	IEMMODE const enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
15814	bool const fRep = VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual);
15815	if (fIOWrite)
15816	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
15817	pVmxTransient->ExitInstrInfo.StrIo.iSegReg, true /fIoChecked/);
15818	else
15819	{
15820	/*
15821	* The segment prefix for INS cannot be overridden and is always ES. We can safely assume X86_SREG_ES.
15822	* Hence "iSegReg" field is undefined in the instruction-information field in VT-x for INS.
15823	* See Intel Instruction spec. for "INS".
15824	* See Intel spec. Table 27-8 "Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS".
15825	*/
15826	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr, true /fIoChecked/);
15827	}
15828	}
15829	else
15830	rcStrict = IEMExecOne(pVCpu);
15831
15832	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
15833	fUpdateRipAlready = true;
15834	}
15835	else
15836	{
15837	/*
15838	* IN/OUT - I/O instruction.
15839	*/
15840	Log4Func(("cs:rip=%04x:%08RX64 %#06x/%u %c\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
15841	uint32_t const uAndVal = s_aIOOpAnd[uIOSize];
15842	Assert(!VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual));
15843	if (fIOWrite)
15844	{
15845	rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pCtx->eax & uAndVal, cbValue);
15846	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
15847	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
15848	&& !pCtx->eflags.Bits.u1TF)
15849	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, uIOPort, cbInstr, cbValue, pCtx->eax & uAndVal);
15850	}
15851	else
15852	{
15853	uint32_t u32Result = 0;
15854	rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
15855	if (IOM_SUCCESS(rcStrict))
15856	{
15857	/* Save result of I/O IN instr. in AL/AX/EAX. */
15858	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Result & uAndVal);
15859	}
15860	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
15861	&& !pCtx->eflags.Bits.u1TF)
15862	rcStrict = EMRZSetPendingIoPortRead(pVCpu, uIOPort, cbInstr, cbValue);
15863	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
15864	}
15865	}
15866
15867	if (IOM_SUCCESS(rcStrict))
15868	{
15869	if (!fUpdateRipAlready)
15870	{
15871	hmR0VmxAdvanceGuestRipBy(pVCpu, cbInstr);
15872	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
15873	}
15874
15875	/*
15876	* INS/OUTS with REP prefix updates RFLAGS, can be observed with triple-fault guru
15877	* while booting Fedora 17 64-bit guest.
15878	*
15879	* See Intel Instruction reference for REP/REPE/REPZ/REPNE/REPNZ.
15880	*/
15881	if (fIOString)
15882	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RFLAGS);
15883
15884	/*
15885	* If any I/O breakpoints are armed, we need to check if one triggered
15886	* and take appropriate action.
15887	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
15888	*/
15889	rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_DR7);
15890	AssertRCReturn(rc, rc);
15891
15892	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
15893	* execution engines about whether hyper BPs and such are pending. */
15894	uint32_t const uDr7 = pCtx->dr[7];
15895	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
15896	&& X86_DR7_ANY_RW_IO(uDr7)
15897	&& (pCtx->cr4 & X86_CR4_DE))
15898	\|\| DBGFBpIsHwIoArmed(pVM)))
15899	{
15900	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
15901
15902	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
15903	VMMRZCallRing3Disable(pVCpu);
15904	HM_DISABLE_PREEMPT(pVCpu);
15905
15906	bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
15907
15908	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, uIOPort, cbValue);
15909	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
15910	{
15911	/* Raise #DB. */
15912	if (fIsGuestDbgActive)
15913	ASMSetDR6(pCtx->dr[6]);
15914	if (pCtx->dr[7] != uDr7)
15915	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR7;
15916
15917	hmR0VmxSetPendingXcptDB(pVCpu);
15918	}
15919	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
15920	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
15921	else if ( rcStrict2 != VINF_SUCCESS
15922	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
15923	rcStrict = rcStrict2;
15924	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
15925
15926	HM_RESTORE_PREEMPT();
15927	VMMRZCallRing3Enable(pVCpu);
15928	}
15929	}
15930
15931	#ifdef VBOX_STRICT
15932	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
15933	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
15934	Assert(!fIOWrite);
15935	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
15936	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
15937	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
15938	Assert(fIOWrite);
15939	else
15940	{
15941	# if 0 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
15942	* statuses, that the VMM device and some others may return. See
15943	* IOM_SUCCESS() for guidance. */
15944	AssertMsg( RT_FAILURE(rcStrict)
15945	\|\| rcStrict == VINF_SUCCESS
15946	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
15947	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
15948	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
15949	\|\| rcStrict == VINF_EM_RAW_TO_R3
15950	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
15951	# endif
15952	}
15953	#endif
15954	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
15955	}
15956	else
15957	{
15958	/*
15959	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
15960	*/
15961	int rc2 = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
15962	AssertRCReturn(rc2, rc2);
15963	STAM_COUNTER_INC(!fIOString ? fIOWrite ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
15964	: fIOWrite ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
15965	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
15966	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
15967	VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual) ? "REP " : "",
15968	fIOWrite ? "OUT" : "IN", fIOString ? "S" : "", uIOPort, uIOSize));
15969
15970	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
15971	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
15972
15973	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
15974	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
15975	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
15976	}
15977	return rcStrict;
15978	}
15979
15980
15981	/**
15982	* VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
15983	* VM-exit.
15984	*/
15985	HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
15986	{
15987	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
15988
15989	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
15990	hmR0VmxReadExitQualVmcs(pVmxTransient);
15991	if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
15992	{
15993	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
15994	if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
15995	{
15996	uint32_t uErrCode;
15997	if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo))
15998	{
15999	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
16000	uErrCode = pVmxTransient->uIdtVectoringErrorCode;
16001	}
16002	else
16003	uErrCode = 0;
16004
16005	RTGCUINTPTR GCPtrFaultAddress;
16006	if (VMX_IDT_VECTORING_INFO_IS_XCPT_PF(pVmxTransient->uIdtVectoringInfo))
16007	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
16008	else
16009	GCPtrFaultAddress = 0;
16010
16011	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16012
16013	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
16014	pVmxTransient->cbExitInstr, uErrCode, GCPtrFaultAddress);
16015
16016	Log4Func(("Pending event. uIntType=%#x uVector=%#x\n", VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo),
16017	VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo)));
16018	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
16019	return VINF_EM_RAW_INJECT_TRPM_EVENT;
16020	}
16021	}
16022
16023	/* Fall back to the interpreter to emulate the task-switch. */
16024	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
16025	return VERR_EM_INTERPRETER;
16026	}
16027
16028
16029	/**
16030	* VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
16031	*/
16032	HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16033	{
16034	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16035
16036	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
16037	pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
16038	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
16039	AssertRC(rc);
16040	return VINF_EM_DBG_STEPPED;
16041	}
16042
16043
16044	/**
16045	* VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
16046	*/
16047	HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16048	{
16049	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16050	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
16051
16052	hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
16053	hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
16054	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16055	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
16056	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
16057
16058	/*
16059	* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly.
16060	*/
16061	VBOXSTRICTRC rcStrict = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
16062	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16063	{
16064	/* For some crazy guest, if an event delivery causes an APIC-access VM-exit, go to instruction emulation. */
16065	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
16066	{
16067	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
16068	return VINF_EM_RAW_INJECT_TRPM_EVENT;
16069	}
16070	}
16071	else
16072	{
16073	Assert(rcStrict != VINF_HM_DOUBLE_FAULT);
16074	return rcStrict;
16075	}
16076
16077	/* IOMMIOPhysHandler() below may call into IEM, save the necessary state. */
16078	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
16079	hmR0VmxReadExitQualVmcs(pVmxTransient);
16080	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
16081	AssertRCReturn(rc, rc);
16082
16083	/* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
16084	uint32_t const uAccessType = VMX_EXIT_QUAL_APIC_ACCESS_TYPE(pVmxTransient->uExitQual);
16085	switch (uAccessType)
16086	{
16087	case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
16088	case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
16089	{
16090	AssertMsg( !(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
16091	\|\| VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual) != XAPIC_OFF_TPR,
16092	("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
16093
16094	RTGCPHYS GCPhys = pVCpu->hm.s.vmx.u64GstMsrApicBase; /* Always up-to-date, as it is not part of the VMCS. */
16095	GCPhys &= PAGE_BASE_GC_MASK;
16096	GCPhys += VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual);
16097	Log4Func(("Linear access uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys,
16098	VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual)));
16099
16100	rcStrict = IOMR0MmioPhysHandler(pVCpu->CTX_SUFF(pVM), pVCpu,
16101	uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ ? 0 : X86_TRAP_PF_RW, GCPhys);
16102	Log4Func(("IOMMMIOPhysHandler returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
16103	if ( rcStrict == VINF_SUCCESS
16104	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
16105	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
16106	{
16107	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RSP \| HM_CHANGED_GUEST_RFLAGS
16108	\| HM_CHANGED_GUEST_APIC_TPR);
16109	rcStrict = VINF_SUCCESS;
16110	}
16111	break;
16112	}
16113
16114	default:
16115	{
16116	Log4Func(("uAccessType=%#x\n", uAccessType));
16117	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
16118	break;
16119	}
16120	}
16121
16122	if (rcStrict != VINF_SUCCESS)
16123	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchApicAccessToR3);
16124	return rcStrict;
16125	}
16126
16127
16128	/**
16129	* VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
16130	* VM-exit.
16131	*/
16132	HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16133	{
16134	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16135	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
16136
16137	/* We might get this VM-exit if the nested-guest is not intercepting MOV DRx accesses. */
16138	if (!pVmxTransient->fIsNestedGuest)
16139	{
16140	/* We should -not- get this VM-exit if the guest's debug registers were active. */
16141	if (pVmxTransient->fWasGuestDebugStateActive)
16142	{
16143	AssertMsgFailed(("Unexpected MOV DRx exit\n"));
16144	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient->uExitReason);
16145	}
16146
16147	if ( !pVCpu->hm.s.fSingleInstruction
16148	&& !pVmxTransient->fWasHyperDebugStateActive)
16149	{
16150	Assert(!DBGFIsStepping(pVCpu));
16151	Assert(pVmcsInfo->u32XcptBitmap & RT_BIT(X86_XCPT_DB));
16152
16153	/* Don't intercept MOV DRx any more. */
16154	pVmcsInfo->u32ProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
16155	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVmcsInfo->u32ProcCtls);
16156	AssertRC(rc);
16157
16158	/* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
16159	VMMRZCallRing3Disable(pVCpu);
16160	HM_DISABLE_PREEMPT(pVCpu);
16161
16162	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
16163	CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
16164	Assert(CPUMIsGuestDebugStateActive(pVCpu));
16165
16166	HM_RESTORE_PREEMPT();
16167	VMMRZCallRing3Enable(pVCpu);
16168
16169	#ifdef VBOX_WITH_STATISTICS
16170	hmR0VmxReadExitQualVmcs(pVmxTransient);
16171	if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
16172	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
16173	else
16174	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
16175	#endif
16176	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
16177	return VINF_SUCCESS;
16178	}
16179	}
16180
16181	/*
16182	* EMInterpretDRx[Write\|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER MSR, CS.
16183	* The EFER MSR is always up-to-date.
16184	* Update the segment registers and DR7 from the CPU.
16185	*/
16186	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
16187	hmR0VmxReadExitQualVmcs(pVmxTransient);
16188	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_DR7);
16189	AssertRCReturn(rc, rc);
16190	Log4Func(("cs:rip=%#04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
16191
16192	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
16193	if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
16194	{
16195	rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
16196	VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual),
16197	VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual));
16198	if (RT_SUCCESS(rc))
16199	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
16200	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
16201	}
16202	else
16203	{
16204	rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
16205	VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual),
16206	VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual));
16207	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
16208	}
16209
16210	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
16211	if (RT_SUCCESS(rc))
16212	{
16213	int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
16214	AssertRCReturn(rc2, rc2);
16215	return VINF_SUCCESS;
16216	}
16217	return rc;
16218	}
16219
16220
16221	/**
16222	* VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
16223	* Conditional VM-exit.
16224	*/
16225	HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16226	{
16227	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16228	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
16229
16230	hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
16231	hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
16232	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16233	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
16234	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
16235
16236	/*
16237	* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly.
16238	*/
16239	VBOXSTRICTRC rcStrict = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
16240	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16241	{
16242	/*
16243	* In the unlikely case where delivering an event causes an EPT misconfig (MMIO), go back to
16244	* instruction emulation to inject the original event. Otherwise, injecting the original event
16245	* using hardware-assisted VMX would trigger the same EPT misconfig VM-exit again.
16246	*/
16247	if (!pVCpu->hm.s.Event.fPending)
16248	{ /* likely */ }
16249	else
16250	{
16251	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterpret);
16252	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
16253	/** @todo NSTVMX: Think about how this should be handled. */
16254	if (pVmxTransient->fIsNestedGuest)
16255	return VERR_VMX_IPE_3;
16256	#endif
16257	return VINF_EM_RAW_INJECT_TRPM_EVENT;
16258	}
16259	}
16260	else
16261	{
16262	Assert(rcStrict != VINF_HM_DOUBLE_FAULT);
16263	return rcStrict;
16264	}
16265
16266	/*
16267	* Get sufficient state and update the exit history entry.
16268	*/
16269	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
16270	hmR0VmxReadGuestPhysicalAddrVmcs(pVmxTransient);
16271	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
16272	AssertRCReturn(rc, rc);
16273
16274	RTGCPHYS const GCPhys = pVmxTransient->uGuestPhysicalAddr;
16275	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
16276	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
16277	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
16278	if (!pExitRec)
16279	{
16280	/*
16281	* If we succeed, resume guest execution.
16282	* If we fail in interpreting the instruction because we couldn't get the guest physical address
16283	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
16284	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
16285	* weird case. See @bugref{6043}.
16286	*/
16287	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
16288	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
16289	/** @todo bird: We can probably just go straight to IOM here and assume that
16290	* it's MMIO, then fall back on PGM if that hunch didn't work out so
16291	* well. However, we need to address that aliasing workarounds that
16292	* PGMR0Trap0eHandlerNPMisconfig implements. So, some care is needed.
16293	*
16294	* Might also be interesting to see if we can get this done more or
16295	* less locklessly inside IOM. Need to consider the lookup table
16296	* updating and use a bit more carefully first (or do all updates via
16297	* rendezvous) */
16298	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);
16299	Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pCtx->rip, VBOXSTRICTRC_VAL(rcStrict)));
16300	if ( rcStrict == VINF_SUCCESS
16301	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
16302	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
16303	{
16304	/* Successfully handled MMIO operation. */
16305	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RSP \| HM_CHANGED_GUEST_RFLAGS
16306	\| HM_CHANGED_GUEST_APIC_TPR);
16307	rcStrict = VINF_SUCCESS;
16308	}
16309	}
16310	else
16311	{
16312	/*
16313	* Frequent exit or something needing probing. Call EMHistoryExec.
16314	*/
16315	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
16316	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhys));
16317
16318	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
16319	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
16320
16321	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
16322	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
16323	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
16324	}
16325	return rcStrict;
16326	}
16327
16328
16329	/**
16330	* VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
16331	* VM-exit.
16332	*/
16333	HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16334	{
16335	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16336	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
16337
16338	hmR0VmxReadExitQualVmcs(pVmxTransient);
16339	hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
16340	hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
16341	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16342	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
16343	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
16344
16345	/*
16346	* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly.
16347	*/
16348	VBOXSTRICTRC rcStrict = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
16349	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16350	{
16351	/*
16352	* If delivery of an event causes an EPT violation (true nested #PF and not MMIO),
16353	* we shall resolve the nested #PF and re-inject the original event.
16354	*/
16355	if (pVCpu->hm.s.Event.fPending)
16356	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectReflectNPF);
16357	}
16358	else
16359	{
16360	Assert(rcStrict != VINF_HM_DOUBLE_FAULT);
16361	return rcStrict;
16362	}
16363
16364	PVMXVMCSINFO pVmcsInfo = pVmxTransient->pVmcsInfo;
16365	hmR0VmxReadGuestPhysicalAddrVmcs(pVmxTransient);
16366	int rc = hmR0VmxImportGuestState(pVCpu, pVmcsInfo, IEM_CPUMCTX_EXTRN_MUST_MASK);
16367	AssertRCReturn(rc, rc);
16368
16369	RTGCPHYS const GCPhys = pVmxTransient->uGuestPhysicalAddr;
16370	uint64_t const uExitQual = pVmxTransient->uExitQual;
16371	AssertMsg(((pVmxTransient->uExitQual >> 7) & 3) != 2, ("%#RX64", uExitQual));
16372
16373	RTGCUINT uErrorCode = 0;
16374	if (uExitQual & VMX_EXIT_QUAL_EPT_INSTR_FETCH)
16375	uErrorCode \|= X86_TRAP_PF_ID;
16376	if (uExitQual & VMX_EXIT_QUAL_EPT_DATA_WRITE)
16377	uErrorCode \|= X86_TRAP_PF_RW;
16378	if (uExitQual & VMX_EXIT_QUAL_EPT_ENTRY_PRESENT)
16379	uErrorCode \|= X86_TRAP_PF_P;
16380
16381	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
16382	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
16383	Log4Func(("at %#RX64 (%#RX64 errcode=%#x) cs:rip=%#04x:%#RX64\n", GCPhys, uExitQual, uErrorCode, pCtx->cs.Sel, pCtx->rip));
16384
16385	/*
16386	* Handle the pagefault trap for the nested shadow table.
16387	*/
16388	TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
16389	rcStrict = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pCtx), GCPhys);
16390	TRPMResetTrap(pVCpu);
16391
16392	/* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
16393	if ( rcStrict == VINF_SUCCESS
16394	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
16395	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
16396	{
16397	/* Successfully synced our nested page tables. */
16398	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
16399	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RSP \| HM_CHANGED_GUEST_RFLAGS);
16400	return VINF_SUCCESS;
16401	}
16402
16403	Log4Func(("EPT return to ring-3 rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
16404	return rcStrict;
16405	}
16406
16407
16408	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
16409	/**
16410	* VM-exit handler for VMCLEAR (VMX_EXIT_VMCLEAR). Unconditional VM-exit.
16411	*/
16412	HMVMX_EXIT_DECL hmR0VmxExitVmclear(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16413	{
16414	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16415
16416	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16417	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
16418	hmR0VmxReadExitQualVmcs(pVmxTransient);
16419	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
16420	\| CPUMCTX_EXTRN_HWVIRT
16421	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
16422	AssertRCReturn(rc, rc);
16423
16424	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16425
16426	VMXVEXITINFO ExitInfo;
16427	RT_ZERO(ExitInfo);
16428	ExitInfo.uReason = pVmxTransient->uExitReason;
16429	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16430	ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
16431	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16432	HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
16433
16434	VBOXSTRICTRC rcStrict = IEMExecDecodedVmclear(pVCpu, &ExitInfo);
16435	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16436	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_HWVIRT);
16437	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16438	{
16439	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16440	rcStrict = VINF_SUCCESS;
16441	}
16442	return rcStrict;
16443	}
16444
16445
16446	/**
16447	* VM-exit handler for VMLAUNCH (VMX_EXIT_VMLAUNCH). Unconditional VM-exit.
16448	*/
16449	HMVMX_EXIT_DECL hmR0VmxExitVmlaunch(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16450	{
16451	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16452
16453	/* Import the entire VMCS state for now as we would be switching VMCS on successful VMLAUNCH,
16454	otherwise we could import just IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK. */
16455	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16456	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
16457	AssertRCReturn(rc, rc);
16458
16459	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16460
16461	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
16462	VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbExitInstr, VMXINSTRID_VMLAUNCH);
16463	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
16464	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16465	{
16466	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
16467	if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
16468	rcStrict = VINF_VMX_VMLAUNCH_VMRESUME;
16469	}
16470	Assert(rcStrict != VINF_IEM_RAISED_XCPT);
16471	return rcStrict;
16472	}
16473
16474
16475	/**
16476	* VM-exit handler for VMPTRLD (VMX_EXIT_VMPTRLD). Unconditional VM-exit.
16477	*/
16478	HMVMX_EXIT_DECL hmR0VmxExitVmptrld(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16479	{
16480	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16481
16482	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16483	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
16484	hmR0VmxReadExitQualVmcs(pVmxTransient);
16485	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
16486	\| CPUMCTX_EXTRN_HWVIRT
16487	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
16488	AssertRCReturn(rc, rc);
16489
16490	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16491
16492	VMXVEXITINFO ExitInfo;
16493	RT_ZERO(ExitInfo);
16494	ExitInfo.uReason = pVmxTransient->uExitReason;
16495	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16496	ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
16497	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16498	HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
16499
16500	VBOXSTRICTRC rcStrict = IEMExecDecodedVmptrld(pVCpu, &ExitInfo);
16501	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16502	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_HWVIRT);
16503	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16504	{
16505	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16506	rcStrict = VINF_SUCCESS;
16507	}
16508	return rcStrict;
16509	}
16510
16511
16512	/**
16513	* VM-exit handler for VMPTRST (VMX_EXIT_VMPTRST). Unconditional VM-exit.
16514	*/
16515	HMVMX_EXIT_DECL hmR0VmxExitVmptrst(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16516	{
16517	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16518
16519	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16520	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
16521	hmR0VmxReadExitQualVmcs(pVmxTransient);
16522	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
16523	\| CPUMCTX_EXTRN_HWVIRT
16524	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
16525	AssertRCReturn(rc, rc);
16526
16527	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16528
16529	VMXVEXITINFO ExitInfo;
16530	RT_ZERO(ExitInfo);
16531	ExitInfo.uReason = pVmxTransient->uExitReason;
16532	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16533	ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
16534	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16535	HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_WRITE, &ExitInfo.GCPtrEffAddr);
16536
16537	VBOXSTRICTRC rcStrict = IEMExecDecodedVmptrst(pVCpu, &ExitInfo);
16538	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16539	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
16540	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16541	{
16542	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16543	rcStrict = VINF_SUCCESS;
16544	}
16545	return rcStrict;
16546	}
16547
16548
16549	/**
16550	* VM-exit handler for VMREAD (VMX_EXIT_VMREAD). Conditional VM-exit.
16551	*/
16552	HMVMX_EXIT_DECL hmR0VmxExitVmread(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16553	{
16554	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16555
16556	/*
16557	* Strictly speaking we should not get VMREAD VM-exits for shadow VMCS fields and
16558	* thus might not need to import the shadow VMCS state, it's safer just in case
16559	* code elsewhere dares look at unsynced VMCS fields.
16560	*/
16561	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16562	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
16563	hmR0VmxReadExitQualVmcs(pVmxTransient);
16564	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
16565	\| CPUMCTX_EXTRN_HWVIRT
16566	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
16567	AssertRCReturn(rc, rc);
16568
16569	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16570
16571	VMXVEXITINFO ExitInfo;
16572	RT_ZERO(ExitInfo);
16573	ExitInfo.uReason = pVmxTransient->uExitReason;
16574	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16575	ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
16576	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16577	if (!ExitInfo.InstrInfo.VmreadVmwrite.fIsRegOperand)
16578	HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_WRITE, &ExitInfo.GCPtrEffAddr);
16579
16580	VBOXSTRICTRC rcStrict = IEMExecDecodedVmread(pVCpu, &ExitInfo);
16581	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16582	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
16583	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16584	{
16585	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16586	rcStrict = VINF_SUCCESS;
16587	}
16588	return rcStrict;
16589	}
16590
16591
16592	/**
16593	* VM-exit handler for VMRESUME (VMX_EXIT_VMRESUME). Unconditional VM-exit.
16594	*/
16595	HMVMX_EXIT_DECL hmR0VmxExitVmresume(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16596	{
16597	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16598
16599	/* Import the entire VMCS state for now as we would be switching VMCS on successful VMRESUME,
16600	otherwise we could import just IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK. */
16601	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16602	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
16603	AssertRCReturn(rc, rc);
16604
16605	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16606
16607	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitVmentry, z);
16608	VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbExitInstr, VMXINSTRID_VMRESUME);
16609	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);
16610	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16611	{
16612	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
16613	if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
16614	rcStrict = VINF_VMX_VMLAUNCH_VMRESUME;
16615	}
16616	Assert(rcStrict != VINF_IEM_RAISED_XCPT);
16617	return rcStrict;
16618	}
16619
16620
16621	/**
16622	* VM-exit handler for VMWRITE (VMX_EXIT_VMWRITE). Conditional VM-exit.
16623	*/
16624	HMVMX_EXIT_DECL hmR0VmxExitVmwrite(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16625	{
16626	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16627
16628	/*
16629	* Although we should not get VMWRITE VM-exits for shadow VMCS fields, since our HM hook
16630	* gets invoked when IEM's VMWRITE instruction emulation modifies the current VMCS and it
16631	* flags re-loading the entire shadow VMCS, we should save the entire shadow VMCS here.
16632	*/
16633	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16634	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
16635	hmR0VmxReadExitQualVmcs(pVmxTransient);
16636	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
16637	\| CPUMCTX_EXTRN_HWVIRT
16638	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
16639	AssertRCReturn(rc, rc);
16640
16641	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16642
16643	VMXVEXITINFO ExitInfo;
16644	RT_ZERO(ExitInfo);
16645	ExitInfo.uReason = pVmxTransient->uExitReason;
16646	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16647	ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
16648	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16649	if (!ExitInfo.InstrInfo.VmreadVmwrite.fIsRegOperand)
16650	HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
16651
16652	VBOXSTRICTRC rcStrict = IEMExecDecodedVmwrite(pVCpu, &ExitInfo);
16653	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16654	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_HWVIRT);
16655	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16656	{
16657	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16658	rcStrict = VINF_SUCCESS;
16659	}
16660	return rcStrict;
16661	}
16662
16663
16664	/**
16665	* VM-exit handler for VMXOFF (VMX_EXIT_VMXOFF). Unconditional VM-exit.
16666	*/
16667	HMVMX_EXIT_DECL hmR0VmxExitVmxoff(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16668	{
16669	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16670
16671	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16672	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_CR4
16673	\| CPUMCTX_EXTRN_HWVIRT
16674	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
16675	AssertRCReturn(rc, rc);
16676
16677	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16678
16679	VBOXSTRICTRC rcStrict = IEMExecDecodedVmxoff(pVCpu, pVmxTransient->cbExitInstr);
16680	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16681	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_HWVIRT);
16682	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16683	{
16684	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16685	rcStrict = VINF_SUCCESS;
16686	}
16687	return rcStrict;
16688	}
16689
16690
16691	/**
16692	* VM-exit handler for VMXON (VMX_EXIT_VMXON). Unconditional VM-exit.
16693	*/
16694	HMVMX_EXIT_DECL hmR0VmxExitVmxon(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16695	{
16696	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16697
16698	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16699	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
16700	hmR0VmxReadExitQualVmcs(pVmxTransient);
16701	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
16702	\| CPUMCTX_EXTRN_HWVIRT
16703	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
16704	AssertRCReturn(rc, rc);
16705
16706	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16707
16708	VMXVEXITINFO ExitInfo;
16709	RT_ZERO(ExitInfo);
16710	ExitInfo.uReason = pVmxTransient->uExitReason;
16711	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16712	ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
16713	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16714	HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
16715
16716	VBOXSTRICTRC rcStrict = IEMExecDecodedVmxon(pVCpu, &ExitInfo);
16717	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16718	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS \| HM_CHANGED_GUEST_HWVIRT);
16719	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16720	{
16721	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16722	rcStrict = VINF_SUCCESS;
16723	}
16724	return rcStrict;
16725	}
16726
16727
16728	/**
16729	* VM-exit handler for INVVPID (VMX_EXIT_INVVPID). Unconditional VM-exit.
16730	*/
16731	HMVMX_EXIT_DECL hmR0VmxExitInvvpid(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16732	{
16733	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16734
16735	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16736	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
16737	hmR0VmxReadExitQualVmcs(pVmxTransient);
16738	int rc = hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_SREG_MASK
16739	\| IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
16740	AssertRCReturn(rc, rc);
16741
16742	HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
16743
16744	VMXVEXITINFO ExitInfo;
16745	RT_ZERO(ExitInfo);
16746	ExitInfo.uReason = pVmxTransient->uExitReason;
16747	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16748	ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
16749	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16750	HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
16751
16752	VBOXSTRICTRC rcStrict = IEMExecDecodedInvvpid(pVCpu, &ExitInfo);
16753	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
16754	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
16755	else if (rcStrict == VINF_IEM_RAISED_XCPT)
16756	{
16757	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
16758	rcStrict = VINF_SUCCESS;
16759	}
16760	return rcStrict;
16761	}
16762	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
16763	/** @} */
16764
16765
16766	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
16767	/** @name Nested-guest VM-exit handlers.
16768	* @{
16769	*/
16770	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
16771	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Nested-guest VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
16772	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
16773
16774	/**
16775	* Nested-guest VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
16776	* Conditional VM-exit.
16777	*/
16778	HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmiNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16779	{
16780	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16781
16782	hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
16783
16784	uint64_t const uExitIntInfo = pVmxTransient->uExitIntInfo;
16785	uint32_t const uExitIntType = VMX_EXIT_INT_INFO_TYPE(uExitIntInfo);
16786	Assert(VMX_EXIT_INT_INFO_IS_VALID(uExitIntInfo));
16787
16788	switch (uExitIntType)
16789	{
16790	/*
16791	* Physical NMIs:
16792	* We shouldn't direct host physical NMIs to the nested-guest. Dispatch it to the host.
16793	*/
16794	case VMX_EXIT_INT_INFO_TYPE_NMI:
16795	return hmR0VmxExitHostNmi(pVCpu, pVmxTransient->pVmcsInfo);
16796
16797	/*
16798	* Hardware exceptions,
16799	* Software exceptions,
16800	* Privileged software exceptions:
16801	* Figure out if the exception must be delivered to the guest or the nested-guest.
16802	*/
16803	case VMX_EXIT_INT_INFO_TYPE_SW_XCPT:
16804	case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT:
16805	case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
16806	{
16807	hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
16808	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16809	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
16810	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
16811
16812	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
16813	bool const fIntercept = CPUMIsGuestVmxXcptInterceptSet(pCtx, VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo),
16814	pVmxTransient->uExitIntErrorCode);
16815	if (fIntercept)
16816	{
16817	/* Exit qualification is required for debug and page-fault exceptions. */
16818	hmR0VmxReadExitQualVmcs(pVmxTransient);
16819
16820	/*
16821	* For VM-exits due to software exceptions (those generated by INT3 or INTO) and privileged
16822	* software exceptions (those generated by INT1/ICEBP) we need to supply the VM-exit instruction
16823	* length. However, if delivery of a software interrupt, software exception or privileged
16824	* software exception causes a VM-exit, that too provides the VM-exit instruction length.
16825	*/
16826	VMXVEXITINFO ExitInfo;
16827	RT_ZERO(ExitInfo);
16828	ExitInfo.uReason = pVmxTransient->uExitReason;
16829	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16830	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16831
16832	VMXVEXITEVENTINFO ExitEventInfo;
16833	RT_ZERO(ExitEventInfo);
16834	ExitEventInfo.uExitIntInfo = pVmxTransient->uExitIntInfo;
16835	ExitEventInfo.uExitIntErrCode = pVmxTransient->uExitIntErrorCode;
16836	ExitEventInfo.uIdtVectoringInfo = pVmxTransient->uIdtVectoringInfo;
16837	ExitEventInfo.uIdtVectoringErrCode = pVmxTransient->uIdtVectoringErrorCode;
16838
16839	#ifdef DEBUG_ramshankar
16840	hmR0VmxImportGuestState(pVCpu, pVmxTransient->pVmcsInfo, HMVMX_CPUMCTX_EXTRN_ALL);
16841	Log4Func(("exit_int_info=%#RX32 err_code=%#RX32 exit_qual=%#RX64\n", pVmxTransient->uExitIntInfo,
16842	pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual));
16843	if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
16844	{
16845	Log4Func(("idt_info=%#RX32 idt_errcode=%#RX32 cr2=%#RX64\n", pVmxTransient->uIdtVectoringInfo,
16846	pVmxTransient->uIdtVectoringErrorCode, pCtx->cr2));
16847	}
16848	#endif
16849	return IEMExecVmxVmexitXcpt(pVCpu, &ExitInfo, &ExitEventInfo);
16850	}
16851
16852	/* Nested paging is currently a requirement, otherwise we would need to handle shadow #PFs in hmR0VmxExitXcptPF. */
16853	Assert(pVCpu->CTX_SUFF(pVM)->hmr0.s.fNestedPaging);
16854	return hmR0VmxExitXcpt(pVCpu, pVmxTransient);
16855	}
16856
16857	/*
16858	* Software interrupts:
16859	* VM-exits cannot be caused by software interrupts.
16860	*
16861	* External interrupts:
16862	* This should only happen when "acknowledge external interrupts on VM-exit"
16863	* control is set. However, we never set this when executing a guest or
16864	* nested-guest. For nested-guests it is emulated while injecting interrupts into
16865	* the guest.
16866	*/
16867	case VMX_EXIT_INT_INFO_TYPE_SW_INT:
16868	case VMX_EXIT_INT_INFO_TYPE_EXT_INT:
16869	default:
16870	{
16871	pVCpu->hm.s.u32HMError = pVmxTransient->uExitIntInfo;
16872	return VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
16873	}
16874	}
16875	}
16876
16877
16878	/**
16879	* Nested-guest VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT).
16880	* Unconditional VM-exit.
16881	*/
16882	HMVMX_EXIT_DECL hmR0VmxExitTripleFaultNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16883	{
16884	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16885	return IEMExecVmxVmexitTripleFault(pVCpu);
16886	}
16887
16888
16889	/**
16890	* Nested-guest VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
16891	*/
16892	HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindowNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16893	{
16894	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16895
16896	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_INT_WINDOW_EXIT))
16897	return IEMExecVmxVmexit(pVCpu, pVmxTransient->uExitReason, 0 /* uExitQual */);
16898	return hmR0VmxExitIntWindow(pVCpu, pVmxTransient);
16899	}
16900
16901
16902	/**
16903	* Nested-guest VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
16904	*/
16905	HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindowNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16906	{
16907	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16908
16909	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_NMI_WINDOW_EXIT))
16910	return IEMExecVmxVmexit(pVCpu, pVmxTransient->uExitReason, 0 /* uExitQual */);
16911	return hmR0VmxExitIntWindow(pVCpu, pVmxTransient);
16912	}
16913
16914
16915	/**
16916	* Nested-guest VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH).
16917	* Unconditional VM-exit.
16918	*/
16919	HMVMX_EXIT_DECL hmR0VmxExitTaskSwitchNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16920	{
16921	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16922
16923	hmR0VmxReadExitQualVmcs(pVmxTransient);
16924	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16925	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
16926	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
16927
16928	VMXVEXITINFO ExitInfo;
16929	RT_ZERO(ExitInfo);
16930	ExitInfo.uReason = pVmxTransient->uExitReason;
16931	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16932	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16933
16934	VMXVEXITEVENTINFO ExitEventInfo;
16935	RT_ZERO(ExitEventInfo);
16936	ExitEventInfo.uIdtVectoringInfo = pVmxTransient->uIdtVectoringInfo;
16937	ExitEventInfo.uIdtVectoringErrCode = pVmxTransient->uIdtVectoringErrorCode;
16938	return IEMExecVmxVmexitTaskSwitch(pVCpu, &ExitInfo, &ExitEventInfo);
16939	}
16940
16941
16942	/**
16943	* Nested-guest VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
16944	*/
16945	HMVMX_EXIT_DECL hmR0VmxExitHltNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16946	{
16947	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16948
16949	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_HLT_EXIT))
16950	{
16951	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16952	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
16953	}
16954	return hmR0VmxExitHlt(pVCpu, pVmxTransient);
16955	}
16956
16957
16958	/**
16959	* Nested-guest VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
16960	*/
16961	HMVMX_EXIT_DECL hmR0VmxExitInvlpgNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16962	{
16963	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16964
16965	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_INVLPG_EXIT))
16966	{
16967	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16968	hmR0VmxReadExitQualVmcs(pVmxTransient);
16969
16970	VMXVEXITINFO ExitInfo;
16971	RT_ZERO(ExitInfo);
16972	ExitInfo.uReason = pVmxTransient->uExitReason;
16973	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
16974	ExitInfo.u64Qual = pVmxTransient->uExitQual;
16975	return IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
16976	}
16977	return hmR0VmxExitInvlpg(pVCpu, pVmxTransient);
16978	}
16979
16980
16981	/**
16982	* Nested-guest VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
16983	*/
16984	HMVMX_EXIT_DECL hmR0VmxExitRdpmcNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
16985	{
16986	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
16987
16988	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_RDPMC_EXIT))
16989	{
16990	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
16991	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
16992	}
16993	return hmR0VmxExitRdpmc(pVCpu, pVmxTransient);
16994	}
16995
16996
16997	/**
16998	* Nested-guest VM-exit handler for VMREAD (VMX_EXIT_VMREAD) and VMWRITE
16999	* (VMX_EXIT_VMWRITE). Conditional VM-exit.
17000	*/
17001	HMVMX_EXIT_DECL hmR0VmxExitVmreadVmwriteNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17002	{
17003	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17004
17005	Assert( pVmxTransient->uExitReason == VMX_EXIT_VMREAD
17006	\|\| pVmxTransient->uExitReason == VMX_EXIT_VMWRITE);
17007
17008	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
17009
17010	uint8_t const iGReg = pVmxTransient->ExitInstrInfo.VmreadVmwrite.iReg2;
17011	Assert(iGReg < RT_ELEMENTS(pVCpu->cpum.GstCtx.aGRegs));
17012	uint64_t u64VmcsField = pVCpu->cpum.GstCtx.aGRegs[iGReg].u64;
17013
17014	HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
17015	if (!CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
17016	u64VmcsField &= UINT64_C(0xffffffff);
17017
17018	if (CPUMIsGuestVmxVmreadVmwriteInterceptSet(pVCpu, pVmxTransient->uExitReason, u64VmcsField))
17019	{
17020	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17021	hmR0VmxReadExitQualVmcs(pVmxTransient);
17022
17023	VMXVEXITINFO ExitInfo;
17024	RT_ZERO(ExitInfo);
17025	ExitInfo.uReason = pVmxTransient->uExitReason;
17026	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17027	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17028	ExitInfo.InstrInfo = pVmxTransient->ExitInstrInfo;
17029	return IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17030	}
17031
17032	if (pVmxTransient->uExitReason == VMX_EXIT_VMREAD)
17033	return hmR0VmxExitVmread(pVCpu, pVmxTransient);
17034	return hmR0VmxExitVmwrite(pVCpu, pVmxTransient);
17035	}
17036
17037
17038	/**
17039	* Nested-guest VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
17040	*/
17041	HMVMX_EXIT_DECL hmR0VmxExitRdtscNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17042	{
17043	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17044
17045	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_RDTSC_EXIT))
17046	{
17047	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17048	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17049	}
17050
17051	return hmR0VmxExitRdtsc(pVCpu, pVmxTransient);
17052	}
17053
17054
17055	/**
17056	* Nested-guest VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX).
17057	* Conditional VM-exit.
17058	*/
17059	HMVMX_EXIT_DECL hmR0VmxExitMovCRxNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17060	{
17061	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17062
17063	hmR0VmxReadExitQualVmcs(pVmxTransient);
17064	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17065
17066	VBOXSTRICTRC rcStrict;
17067	uint32_t const uAccessType = VMX_EXIT_QUAL_CRX_ACCESS(pVmxTransient->uExitQual);
17068	switch (uAccessType)
17069	{
17070	case VMX_EXIT_QUAL_CRX_ACCESS_WRITE:
17071	{
17072	uint8_t const iCrReg = VMX_EXIT_QUAL_CRX_REGISTER(pVmxTransient->uExitQual);
17073	uint8_t const iGReg = VMX_EXIT_QUAL_CRX_GENREG(pVmxTransient->uExitQual);
17074	Assert(iGReg < RT_ELEMENTS(pVCpu->cpum.GstCtx.aGRegs));
17075	uint64_t const uNewCrX = pVCpu->cpum.GstCtx.aGRegs[iGReg].u64;
17076
17077	bool fIntercept;
17078	switch (iCrReg)
17079	{
17080	case 0:
17081	case 4:
17082	fIntercept = CPUMIsGuestVmxMovToCr0Cr4InterceptSet(&pVCpu->cpum.GstCtx, iCrReg, uNewCrX);
17083	break;
17084
17085	case 3:
17086	fIntercept = CPUMIsGuestVmxMovToCr3InterceptSet(pVCpu, uNewCrX);
17087	break;
17088
17089	case 8:
17090	fIntercept = CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_CR8_LOAD_EXIT);
17091	break;
17092
17093	default:
17094	fIntercept = false;
17095	break;
17096	}
17097	if (fIntercept)
17098	{
17099	VMXVEXITINFO ExitInfo;
17100	RT_ZERO(ExitInfo);
17101	ExitInfo.uReason = pVmxTransient->uExitReason;
17102	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17103	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17104	rcStrict = IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17105	}
17106	else
17107	rcStrict = hmR0VmxExitMovToCrX(pVCpu, pVmxTransient->pVmcsInfo, pVmxTransient->cbExitInstr, iGReg, iCrReg);
17108	break;
17109	}
17110
17111	case VMX_EXIT_QUAL_CRX_ACCESS_READ:
17112	{
17113	/*
17114	* CR0/CR4 reads do not cause VM-exits, the read-shadow is used (subject to masking).
17115	* CR2 reads do not cause a VM-exit.
17116	* CR3 reads cause a VM-exit depending on the "CR3 store exiting" control.
17117	* CR8 reads cause a VM-exit depending on the "CR8 store exiting" control.
17118	*/
17119	uint8_t const iCrReg = VMX_EXIT_QUAL_CRX_REGISTER(pVmxTransient->uExitQual);
17120	if ( iCrReg == 3
17121	\|\| iCrReg == 8)
17122	{
17123	static const uint32_t s_auCrXReadIntercepts[] = { 0, 0, 0, VMX_PROC_CTLS_CR3_STORE_EXIT, 0,
17124	0, 0, 0, VMX_PROC_CTLS_CR8_STORE_EXIT };
17125	uint32_t const uIntercept = s_auCrXReadIntercepts[iCrReg];
17126	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, uIntercept))
17127	{
17128	VMXVEXITINFO ExitInfo;
17129	RT_ZERO(ExitInfo);
17130	ExitInfo.uReason = pVmxTransient->uExitReason;
17131	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17132	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17133	rcStrict = IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17134	}
17135	else
17136	{
17137	uint8_t const iGReg = VMX_EXIT_QUAL_CRX_GENREG(pVmxTransient->uExitQual);
17138	rcStrict = hmR0VmxExitMovFromCrX(pVCpu, pVmxTransient->pVmcsInfo, pVmxTransient->cbExitInstr, iGReg, iCrReg);
17139	}
17140	}
17141	else
17142	{
17143	AssertMsgFailed(("MOV from CR%d VM-exit must not happen\n", iCrReg));
17144	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, iCrReg);
17145	}
17146	break;
17147	}
17148
17149	case VMX_EXIT_QUAL_CRX_ACCESS_CLTS:
17150	{
17151	PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
17152	Assert(pVmcsNstGst);
17153	uint64_t const uGstHostMask = pVmcsNstGst->u64Cr0Mask.u;
17154	uint64_t const uReadShadow = pVmcsNstGst->u64Cr0ReadShadow.u;
17155	if ( (uGstHostMask & X86_CR0_TS)
17156	&& (uReadShadow & X86_CR0_TS))
17157	{
17158	VMXVEXITINFO ExitInfo;
17159	RT_ZERO(ExitInfo);
17160	ExitInfo.uReason = pVmxTransient->uExitReason;
17161	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17162	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17163	rcStrict = IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17164	}
17165	else
17166	rcStrict = hmR0VmxExitClts(pVCpu, pVmxTransient->pVmcsInfo, pVmxTransient->cbExitInstr);
17167	break;
17168	}
17169
17170	case VMX_EXIT_QUAL_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
17171	{
17172	RTGCPTR GCPtrEffDst;
17173	uint16_t const uNewMsw = VMX_EXIT_QUAL_CRX_LMSW_DATA(pVmxTransient->uExitQual);
17174	bool const fMemOperand = VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(pVmxTransient->uExitQual);
17175	if (fMemOperand)
17176	{
17177	hmR0VmxReadGuestLinearAddrVmcs(pVmxTransient);
17178	GCPtrEffDst = pVmxTransient->uGuestLinearAddr;
17179	}
17180	else
17181	GCPtrEffDst = NIL_RTGCPTR;
17182
17183	if (CPUMIsGuestVmxLmswInterceptSet(&pVCpu->cpum.GstCtx, uNewMsw))
17184	{
17185	VMXVEXITINFO ExitInfo;
17186	RT_ZERO(ExitInfo);
17187	ExitInfo.uReason = pVmxTransient->uExitReason;
17188	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17189	ExitInfo.u64GuestLinearAddr = GCPtrEffDst;
17190	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17191	rcStrict = IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17192	}
17193	else
17194	rcStrict = hmR0VmxExitLmsw(pVCpu, pVmxTransient->pVmcsInfo, pVmxTransient->cbExitInstr, uNewMsw, GCPtrEffDst);
17195	break;
17196	}
17197
17198	default:
17199	{
17200	AssertMsgFailed(("Unrecognized Mov CRX access type %#x\n", uAccessType));
17201	HMVMX_UNEXPECTED_EXIT_RET(pVCpu, uAccessType);
17202	}
17203	}
17204
17205	if (rcStrict == VINF_IEM_RAISED_XCPT)
17206	{
17207	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
17208	rcStrict = VINF_SUCCESS;
17209	}
17210	return rcStrict;
17211	}
17212
17213
17214	/**
17215	* Nested-guest VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX).
17216	* Conditional VM-exit.
17217	*/
17218	HMVMX_EXIT_DECL hmR0VmxExitMovDRxNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17219	{
17220	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17221
17222	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_MOV_DR_EXIT))
17223	{
17224	hmR0VmxReadExitQualVmcs(pVmxTransient);
17225	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17226
17227	VMXVEXITINFO ExitInfo;
17228	RT_ZERO(ExitInfo);
17229	ExitInfo.uReason = pVmxTransient->uExitReason;
17230	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17231	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17232	return IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17233	}
17234	return hmR0VmxExitMovDRx(pVCpu, pVmxTransient);
17235	}
17236
17237
17238	/**
17239	* Nested-guest VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR).
17240	* Conditional VM-exit.
17241	*/
17242	HMVMX_EXIT_DECL hmR0VmxExitIoInstrNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17243	{
17244	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17245
17246	hmR0VmxReadExitQualVmcs(pVmxTransient);
17247
17248	uint32_t const uIOPort = VMX_EXIT_QUAL_IO_PORT(pVmxTransient->uExitQual);
17249	uint8_t const uIOSize = VMX_EXIT_QUAL_IO_SIZE(pVmxTransient->uExitQual);
17250	AssertReturn(uIOSize <= 3 && uIOSize != 2, VERR_VMX_IPE_1);
17251
17252	static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses in bytes. */
17253	uint8_t const cbAccess = s_aIOSizes[uIOSize];
17254	if (CPUMIsGuestVmxIoInterceptSet(pVCpu, uIOPort, cbAccess))
17255	{
17256	/*
17257	* IN/OUT instruction:
17258	* - Provides VM-exit instruction length.
17259	*
17260	* INS/OUTS instruction:
17261	* - Provides VM-exit instruction length.
17262	* - Provides Guest-linear address.
17263	* - Optionally provides VM-exit instruction info (depends on CPU feature).
17264	*/
17265	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
17266	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17267
17268	/* Make sure we don't use stale/uninitialized VMX-transient info. below. */
17269	pVmxTransient->ExitInstrInfo.u = 0;
17270	pVmxTransient->uGuestLinearAddr = 0;
17271
17272	bool const fVmxInsOutsInfo = pVM->cpum.ro.GuestFeatures.fVmxInsOutInfo;
17273	bool const fIOString = VMX_EXIT_QUAL_IO_IS_STRING(pVmxTransient->uExitQual);
17274	if (fIOString)
17275	{
17276	hmR0VmxReadGuestLinearAddrVmcs(pVmxTransient);
17277	if (fVmxInsOutsInfo)
17278	{
17279	Assert(RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS)); /* Paranoia. */
17280	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
17281	}
17282	}
17283
17284	VMXVEXITINFO ExitInfo;
17285	RT_ZERO(ExitInfo);
17286	ExitInfo.uReason = pVmxTransient->uExitReason;
17287	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17288	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17289	ExitInfo.InstrInfo = pVmxTransient->ExitInstrInfo;
17290	ExitInfo.u64GuestLinearAddr = pVmxTransient->uGuestLinearAddr;
17291	return IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17292	}
17293	return hmR0VmxExitIoInstr(pVCpu, pVmxTransient);
17294	}
17295
17296
17297	/**
17298	* Nested-guest VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
17299	*/
17300	HMVMX_EXIT_DECL hmR0VmxExitRdmsrNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17301	{
17302	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17303
17304	uint32_t fMsrpm;
17305	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_USE_MSR_BITMAPS))
17306	fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), pVCpu->cpum.GstCtx.ecx);
17307	else
17308	fMsrpm = VMXMSRPM_EXIT_RD;
17309
17310	if (fMsrpm & VMXMSRPM_EXIT_RD)
17311	{
17312	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17313	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17314	}
17315	return hmR0VmxExitRdmsr(pVCpu, pVmxTransient);
17316	}
17317
17318
17319	/**
17320	* Nested-guest VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
17321	*/
17322	HMVMX_EXIT_DECL hmR0VmxExitWrmsrNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17323	{
17324	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17325
17326	uint32_t fMsrpm;
17327	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_USE_MSR_BITMAPS))
17328	fMsrpm = CPUMGetVmxMsrPermission(pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pvMsrBitmap), pVCpu->cpum.GstCtx.ecx);
17329	else
17330	fMsrpm = VMXMSRPM_EXIT_WR;
17331
17332	if (fMsrpm & VMXMSRPM_EXIT_WR)
17333	{
17334	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17335	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17336	}
17337	return hmR0VmxExitWrmsr(pVCpu, pVmxTransient);
17338	}
17339
17340
17341	/**
17342	* Nested-guest VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
17343	*/
17344	HMVMX_EXIT_DECL hmR0VmxExitMwaitNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17345	{
17346	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17347
17348	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_MWAIT_EXIT))
17349	{
17350	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17351	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17352	}
17353	return hmR0VmxExitMwait(pVCpu, pVmxTransient);
17354	}
17355
17356
17357	/**
17358	* Nested-guest VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional
17359	* VM-exit.
17360	*/
17361	HMVMX_EXIT_DECL hmR0VmxExitMtfNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17362	{
17363	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17364
17365	/** @todo NSTVMX: Should consider debugging nested-guests using VM debugger. */
17366	hmR0VmxReadGuestPendingDbgXctps(pVmxTransient);
17367	VMXVEXITINFO ExitInfo;
17368	RT_ZERO(ExitInfo);
17369	ExitInfo.uReason = pVmxTransient->uExitReason;
17370	ExitInfo.u64GuestPendingDbgXcpts = pVmxTransient->uGuestPendingDbgXcpts;
17371	return IEMExecVmxVmexitTrapLike(pVCpu, &ExitInfo);
17372	}
17373
17374
17375	/**
17376	* Nested-guest VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
17377	*/
17378	HMVMX_EXIT_DECL hmR0VmxExitMonitorNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17379	{
17380	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17381
17382	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_MONITOR_EXIT))
17383	{
17384	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17385	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17386	}
17387	return hmR0VmxExitMonitor(pVCpu, pVmxTransient);
17388	}
17389
17390
17391	/**
17392	* Nested-guest VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
17393	*/
17394	HMVMX_EXIT_DECL hmR0VmxExitPauseNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17395	{
17396	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17397
17398	/** @todo NSTVMX: Think about this more. Does the outer guest need to intercept
17399	* PAUSE when executing a nested-guest? If it does not, we would not need
17400	* to check for the intercepts here. Just call VM-exit... */
17401
17402	/* The CPU would have already performed the necessary CPL checks for PAUSE-loop exiting. */
17403	if ( CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_PAUSE_EXIT)
17404	\|\| CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT))
17405	{
17406	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17407	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17408	}
17409	return hmR0VmxExitPause(pVCpu, pVmxTransient);
17410	}
17411
17412
17413	/**
17414	* Nested-guest VM-exit handler for when the TPR value is lowered below the
17415	* specified threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
17416	*/
17417	HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThresholdNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17418	{
17419	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17420
17421	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_USE_TPR_SHADOW))
17422	{
17423	hmR0VmxReadGuestPendingDbgXctps(pVmxTransient);
17424	VMXVEXITINFO ExitInfo;
17425	RT_ZERO(ExitInfo);
17426	ExitInfo.uReason = pVmxTransient->uExitReason;
17427	ExitInfo.u64GuestPendingDbgXcpts = pVmxTransient->uGuestPendingDbgXcpts;
17428	return IEMExecVmxVmexitTrapLike(pVCpu, &ExitInfo);
17429	}
17430	return hmR0VmxExitTprBelowThreshold(pVCpu, pVmxTransient);
17431	}
17432
17433
17434	/**
17435	* Nested-guest VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional
17436	* VM-exit.
17437	*/
17438	HMVMX_EXIT_DECL hmR0VmxExitApicAccessNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17439	{
17440	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17441
17442	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17443	hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
17444	hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
17445	hmR0VmxReadExitQualVmcs(pVmxTransient);
17446
17447	Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_VIRT_APIC_ACCESS));
17448
17449	Log4Func(("at offset %#x type=%u\n", VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual),
17450	VMX_EXIT_QUAL_APIC_ACCESS_TYPE(pVmxTransient->uExitQual)));
17451
17452	VMXVEXITINFO ExitInfo;
17453	RT_ZERO(ExitInfo);
17454	ExitInfo.uReason = pVmxTransient->uExitReason;
17455	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17456	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17457
17458	VMXVEXITEVENTINFO ExitEventInfo;
17459	RT_ZERO(ExitEventInfo);
17460	ExitEventInfo.uIdtVectoringInfo = pVmxTransient->uIdtVectoringInfo;
17461	ExitEventInfo.uIdtVectoringErrCode = pVmxTransient->uIdtVectoringErrorCode;
17462	return IEMExecVmxVmexitApicAccess(pVCpu, &ExitInfo, &ExitEventInfo);
17463	}
17464
17465
17466	/**
17467	* Nested-guest VM-exit handler for APIC write emulation (VMX_EXIT_APIC_WRITE).
17468	* Conditional VM-exit.
17469	*/
17470	HMVMX_EXIT_DECL hmR0VmxExitApicWriteNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17471	{
17472	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17473
17474	Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_APIC_REG_VIRT));
17475	hmR0VmxReadExitQualVmcs(pVmxTransient);
17476	return IEMExecVmxVmexit(pVCpu, pVmxTransient->uExitReason, pVmxTransient->uExitQual);
17477	}
17478
17479
17480	/**
17481	* Nested-guest VM-exit handler for virtualized EOI (VMX_EXIT_VIRTUALIZED_EOI).
17482	* Conditional VM-exit.
17483	*/
17484	HMVMX_EXIT_DECL hmR0VmxExitVirtEoiNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17485	{
17486	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17487
17488	Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_VIRT_INT_DELIVERY));
17489	hmR0VmxReadExitQualVmcs(pVmxTransient);
17490	return IEMExecVmxVmexit(pVCpu, pVmxTransient->uExitReason, pVmxTransient->uExitQual);
17491	}
17492
17493
17494	/**
17495	* Nested-guest VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
17496	*/
17497	HMVMX_EXIT_DECL hmR0VmxExitRdtscpNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17498	{
17499	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17500
17501	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_RDTSC_EXIT))
17502	{
17503	Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_RDTSCP));
17504	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17505	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17506	}
17507	return hmR0VmxExitRdtscp(pVCpu, pVmxTransient);
17508	}
17509
17510
17511	/**
17512	* Nested-guest VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
17513	*/
17514	HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvdNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17515	{
17516	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17517
17518	if (CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_WBINVD_EXIT))
17519	{
17520	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17521	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17522	}
17523	return hmR0VmxExitWbinvd(pVCpu, pVmxTransient);
17524	}
17525
17526
17527	/**
17528	* Nested-guest VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
17529	*/
17530	HMVMX_EXIT_DECL hmR0VmxExitInvpcidNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17531	{
17532	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17533
17534	if (CPUMIsGuestVmxProcCtlsSet(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS_INVLPG_EXIT))
17535	{
17536	Assert(CPUMIsGuestVmxProcCtls2Set(&pVCpu->cpum.GstCtx, VMX_PROC_CTLS2_INVPCID));
17537	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17538	hmR0VmxReadExitQualVmcs(pVmxTransient);
17539	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
17540
17541	VMXVEXITINFO ExitInfo;
17542	RT_ZERO(ExitInfo);
17543	ExitInfo.uReason = pVmxTransient->uExitReason;
17544	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17545	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17546	ExitInfo.InstrInfo = pVmxTransient->ExitInstrInfo;
17547	return IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17548	}
17549	return hmR0VmxExitInvpcid(pVCpu, pVmxTransient);
17550	}
17551
17552
17553	/**
17554	* Nested-guest VM-exit handler for invalid-guest state
17555	* (VMX_EXIT_ERR_INVALID_GUEST_STATE). Error VM-exit.
17556	*/
17557	HMVMX_EXIT_DECL hmR0VmxExitErrInvalidGuestStateNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17558	{
17559	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17560
17561	/*
17562	* Currently this should never happen because we fully emulate VMLAUNCH/VMRESUME in IEM.
17563	* So if it does happen, it indicates a bug possibly in the hardware-assisted VMX code.
17564	* Handle it like it's in an invalid guest state of the outer guest.
17565	*
17566	* When the fast path is implemented, this should be changed to cause the corresponding
17567	* nested-guest VM-exit.
17568	*/
17569	return hmR0VmxExitErrInvalidGuestState(pVCpu, pVmxTransient);
17570	}
17571
17572
17573	/**
17574	* Nested-guest VM-exit handler for instructions that cause VM-exits uncondtionally
17575	* and only provide the instruction length.
17576	*
17577	* Unconditional VM-exit.
17578	*/
17579	HMVMX_EXIT_DECL hmR0VmxExitInstrNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17580	{
17581	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17582
17583	#ifdef VBOX_STRICT
17584	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
17585	switch (pVmxTransient->uExitReason)
17586	{
17587	case VMX_EXIT_ENCLS:
17588	Assert(CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_ENCLS_EXIT));
17589	break;
17590
17591	case VMX_EXIT_VMFUNC:
17592	Assert(CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_VMFUNC));
17593	break;
17594	}
17595	#endif
17596
17597	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17598	return IEMExecVmxVmexitInstr(pVCpu, pVmxTransient->uExitReason, pVmxTransient->cbExitInstr);
17599	}
17600
17601
17602	/**
17603	* Nested-guest VM-exit handler for instructions that provide instruction length as
17604	* well as more information.
17605	*
17606	* Unconditional VM-exit.
17607	*/
17608	HMVMX_EXIT_DECL hmR0VmxExitInstrWithInfoNested(PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
17609	{
17610	HMVMX_VALIDATE_NESTED_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
17611
17612	#ifdef VBOX_STRICT
17613	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
17614	switch (pVmxTransient->uExitReason)
17615	{
17616	case VMX_EXIT_GDTR_IDTR_ACCESS:
17617	case VMX_EXIT_LDTR_TR_ACCESS:
17618	Assert(CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_DESC_TABLE_EXIT));
17619	break;
17620
17621	case VMX_EXIT_RDRAND:
17622	Assert(CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_RDRAND_EXIT));
17623	break;
17624
17625	case VMX_EXIT_RDSEED:
17626	Assert(CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_RDSEED_EXIT));
17627	break;
17628
17629	case VMX_EXIT_XSAVES:
17630	case VMX_EXIT_XRSTORS:
17631	/** @todo NSTVMX: Verify XSS-bitmap. */
17632	Assert(CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_XSAVES_XRSTORS));
17633	break;
17634
17635	case VMX_EXIT_UMWAIT:
17636	case VMX_EXIT_TPAUSE:
17637	Assert(CPUMIsGuestVmxProcCtlsSet(pCtx, VMX_PROC_CTLS_RDTSC_EXIT));
17638	Assert(CPUMIsGuestVmxProcCtls2Set(pCtx, VMX_PROC_CTLS2_USER_WAIT_PAUSE));
17639	break;
17640	}
17641	#endif
17642
17643	hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
17644	hmR0VmxReadExitQualVmcs(pVmxTransient);
17645	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
17646
17647	VMXVEXITINFO ExitInfo;
17648	RT_ZERO(ExitInfo);
17649	ExitInfo.uReason = pVmxTransient->uExitReason;
17650	ExitInfo.cbInstr = pVmxTransient->cbExitInstr;
17651	ExitInfo.u64Qual = pVmxTransient->uExitQual;
17652	ExitInfo.InstrInfo = pVmxTransient->ExitInstrInfo;
17653	return IEMExecVmxVmexitInstrWithInfo(pVCpu, &ExitInfo);
17654	}
17655
17656	/** @} */
17657	#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
17658

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 90440

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