| 1 | /* $Id: HMVMXR0.h 72744 2018-06-29 07:36:19Z vboxsync $ */
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| 2 | /** @file
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| 3 | * HM VMX (VT-x) - Internal header file.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2017 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 | #ifndef ___HMVMXR0_h
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| 19 | #define ___HMVMXR0_h
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| 20 |
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| 21 | RT_C_DECLS_BEGIN
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| 22 |
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| 23 | /** @defgroup grp_vmx_int Internal
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| 24 | * @ingroup grp_vmx
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| 25 | * @internal
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| 26 | * @{
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| 27 | */
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| 28 |
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| 29 | #ifdef IN_RING0
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| 30 |
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| 31 | VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
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| 32 | VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit);
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| 33 | VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys,
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| 34 | bool fEnabledBySystem, void *pvMsrs);
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| 35 | VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
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| 36 | VMMR0DECL(int) VMXR0GlobalInit(void);
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| 37 | VMMR0DECL(void) VMXR0GlobalTerm(void);
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| 38 | VMMR0DECL(int) VMXR0InitVM(PVM pVM);
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| 39 | VMMR0DECL(int) VMXR0TermVM(PVM pVM);
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| 40 | VMMR0DECL(int) VMXR0SetupVM(PVM pVM);
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| 41 | VMMR0DECL(int) VMXR0ExportHostState(PVMCPU pVCpu);
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| 42 | VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt);
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| 43 | VMMR0DECL(int) VMXR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat);
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| 44 | VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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| 45 | DECLASM(int) VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
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| 46 | DECLASM(int) VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
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| 47 |
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| 48 | # if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
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| 49 | DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
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| 50 | VMMR0DECL(int) VMXR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cbParam, uint32_t *paParam);
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| 51 | # endif
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| 52 |
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| 53 | /* Cached VMCS accesses -- defined only for 32-bit hosts (with 64-bit guest support). */
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| 54 | # ifdef VMX_USE_CACHED_VMCS_ACCESSES
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| 55 | VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
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| 56 |
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| 57 | DECLINLINE(int) VMXReadCachedVmcsEx(PVMCPU pVCpu, uint32_t idxCache, RTGCUINTREG *pVal)
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| 58 | {
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| 59 | Assert(idxCache <= VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX);
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| 60 | *pVal = pVCpu->hm.s.vmx.VMCSCache.Read.aFieldVal[idxCache];
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| 61 | return VINF_SUCCESS;
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| 62 | }
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| 63 | # endif
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| 64 |
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| 65 | # if HC_ARCH_BITS == 32
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| 66 | # define VMXReadVmcsHstN VMXReadVmcs32
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| 67 | # define VMXReadVmcsGstN(idxField, pVal) VMXReadCachedVmcsEx(pVCpu, idxField##_CACHE_IDX, pVal)
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| 68 | # define VMXReadVmcsGstNByIdxVal(idxField, pVal) VMXReadCachedVmcsEx(pVCpu, idxField, pVal)
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| 69 | # else /* HC_ARCH_BITS == 64 */
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| 70 | # define VMXReadVmcsHstN VMXReadVmcs64
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| 71 | # define VMXReadVmcsGstN VMXReadVmcs64
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| 72 | # define VMXReadVmcsGstNByIdxVal VMXReadVmcs64
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| 73 | # endif
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| 74 |
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| 75 | #endif /* IN_RING0 */
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| 76 |
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| 77 | /** @} */
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| 78 |
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| 79 | RT_C_DECLS_END
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| 80 |
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| 81 | #endif /* !___HMVMXR0_h */
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| 82 |
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